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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,
1 D& a! o2 i- |% R7 i0 ?input mcasp_ahclkx,6 z7 S. m# p' B, h) M
input mcasp_aclkx,
" G7 M6 t0 [( Z/ M# N$ Cinput axr0,- |# U& W8 b8 \- Z$ {
! |& X* s2 J {! Woutput mcasp_afsr, S# B; P2 ]9 j: K3 ~
output mcasp_ahclkr,7 X/ u- G2 S- ?$ ~7 ^2 x
output mcasp_aclkr,1 X: [8 U/ ]8 M$ T0 i% `
output axr1,1 e) T; P! P( _; w0 g+ v
assign mcasp_afsr = mcasp_afsx;
& h0 j ], t8 _8 V' fassign mcasp_aclkr = mcasp_aclkx;
# A3 `# n' N: ]" `0 ~assign mcasp_ahclkr = mcasp_ahclkx;
) B# d6 q7 f0 n: kassign axr1 = axr0;
( Z* y$ i6 g3 a; y0 X) P/ C1 G
. ~4 u; a! [' j3 s! g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
# R$ e! e2 a7 g1 }- |) Y9 T7 W2 Ystatic void McASPI2SConfigure(void)
7 Q' B: C& e% g4 s, ]; m7 b* w{
: n' W& N. B* D K j& Q& o$ |" KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 M7 d* s, N3 ^4 _8 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */
1 q0 `( w% h+ I3 pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! O3 K6 q" b+ b# E5 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */
" _3 V9 |4 H% }6 G) uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% u0 O& K. o3 V+ M7 D0 g2 t
MCASP_RX_MODE_DMA);
0 \0 e$ L1 Y. E( r, GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, R" _. w, }( }1 `* ZMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */: @: i# R2 |4 p6 J6 q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) X/ L: A; r9 q0 I/ D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); ^' V! x% W* h, V, B% U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 X/ U s8 N6 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */ E: W3 b" M7 b! b) W/ g; Y6 f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! m- o9 k" B9 ]$ o2 A! P! p; R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 z& U8 m/ `# u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! r3 k& k6 S0 `9 u( g9 y0 A
0x00, 0xFF);
/* configure the clock for transmitter */% M2 {9 \- G! q9 s4 K% a) Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) W' ?6 a) _( L% m3 ?7 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 o1 R- g" C8 N3 _0 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 q+ _# _4 V" I' l( I, [4 J" v! ~- P0x00, 0xFF);: I2 I+ r d* a z
$ y* ~# D+ ^+ e6 P6 y/* Enable synchronization of RX and TX sections */ ( x; g/ x/ j: F8 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
" d2 T8 H; l+ V u; |8 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' c3 d5 T9 C% _. M7 t$ iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*
. `: ?6 |/ x( K( C4 [5 V/ z** Set the serializers, Currently only one serializer is set as
( {: r0 M, M# J** transmitter and one serializer as receiver.
* R& b2 R# ^) [9 K" F7 e- g% N*/
! f* I7 c# a% D/ I9 y$ KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 {! ]$ F" ]/ ?5 l! P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*6 K: L+ N7 Z- t+ I/ x4 G0 x
** Configure the McASP pins 8 b/ i2 ^' P# w+ w' @3 ~- E% y
** Input - Frame Sync, Clock and Serializer Rx
' H3 }& v: U+ ^0 k7 N; n$ X** Output - Serializer Tx is connected to the input of the codec 1 Q+ \3 R4 [' ]; n/ @) R' w" p, R
*/
# _9 @! B \9 J$ v$ LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( J8 z1 x; s; Z, e" v0 H; ~+ ~" G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ ^) J, E4 ^ c/ \2 d) H- u/ q. JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ I; d- z/ K. R x( p5 E2 }
| MCASP_PIN_ACLKX
0 v: K5 O( p- V! I# \| MCASP_PIN_AHCLKX
. M4 L' y* X; [5 R2 n| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */
/ l# c8 a1 `2 A4 q' Y: l9 ? B; f6 zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& h: Q* k- e) s1 B4 {| MCASP_TX_CLKFAIL # `* D2 ^" l \+ R+ {" B( t3 ` b0 o
| MCASP_TX_SYNCERROR
* E3 V/ q( z2 N! v. w+ [| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ a% v7 d6 e$ c0 W: Q( \- ]| MCASP_RX_CLKFAIL, B8 ]) l& d! u
| MCASP_RX_SYNCERROR 1 D- M9 } @- f; m
| MCASP_RX_OVERRUN);
% o( {4 @- h# i% G% ^- I+ |}
static void I2SDataTxRxActivate(void)+ B3 X' A0 y/ G& \* n
{* E+ V0 [* \& X8 Q$ H
/* Start the clocks */
( }) ~% [2 w1 ? h" IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! I% ^/ l/ M/ ^. r7 `6 D. l) L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
$ X* X( W' F! LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; W' v" T3 e8 I# G- W c; ~
EDMA3_TRIG_MODE_EVENT);. W+ Q7 k9 W" G" M5 o) z* s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 T$ C7 h9 p! f6 [/ }: D* w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */3 A" d9 H! i" I! K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 C' w0 n# T. U( yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */
& n! p$ {/ e3 V8 Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */. D, `3 |6 T( z/ B) n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" s* c3 P0 a. U. E" u- eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. T, @! m1 ]3 O0 X4 `}
* R- \, e2 x# y2 k
请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 {) B9 a+ F* R' h6 K
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