* O' D6 h- @7 X6 X% k% Q, L- X/* OPT Field specific defines */* I2 B3 w4 O$ e& h! \8 o
#define OPT_SYNCDIM_SHIFT (0x00000002u)! Q1 U) _. @9 _ `2 e+ e, Q
#define OPT_TCC_MASK (0x0003F000u) 5 E$ E2 v* @- I5 O$ I0 b#define OPT_TCC_SHIFT (0x0000000Cu)+ e5 H% }* w4 n0 ?0 r2 S* s
#define OPT_ITCINTEN_SHIFT (0x00000015u) 3 E. C s4 K+ B9 A" P5 |) Q! E' C( I#define OPT_TCINTEN_SHIFT (0x00000014u) , Z% r. n5 F. F$ j! ~0 M# v: R [ # `' D5 P1 G# x# K' N7 x! \char ping_buffer[PING_PONG_BCNT];3 C! I$ S- ^+ s9 T; _$ z" w
char pong_buffer[PING_PONG_BCNT];$ d5 l4 f4 M0 D( x, G7 v( Y* G
2 @8 ^# {3 Z0 v
4 P R7 Z" r* m
C6 L- r! k8 D4 E+ s
: R c: w$ O; \2 r8 T, G
static void ys_edma3_init() ; o% G; e7 b4 P; X* q) }{. } K9 q# E L5 z7 ]
EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};8 J( A2 t$ n" q' `* u+ }
EDMA3_DRV_Result result = EDMA3_DRV_SOK;6 \$ F/ l2 J5 ^3 i1 X3 N
EDMA3_DRV_Handle hEdma; 7 c& i: K& V3 `- T- F uint32_t chId = 0; 0 ? w+ q! g8 J' H" m uint32_t tcc = 0; 1 y0 H) i- [2 X5 e: b# F 9 Q7 p' Z4 d! t- x* N1 D- [5 u$ _ print2arm("edma3 driver init...",0); ) ~- c ^$ C2 n A( ?' N J% C: y Y" P o hEdma = edma3init(0,&result); 7 D& a) m; Q* ^3 o% G if(hEdma)2 S' u. L5 D4 b+ V; T' M2 z
{ ) U0 N1 K7 [& l/ B' C H( o print2arm("edma3init() Passed.",0);0 o/ X f3 E% X* ]- G
} 5 O7 Y$ k) B5 y& O" f else , D: v2 ~+ n+ M, y+ v1 ~: X {9 M% S! X) M- G' Y: \
print2arm("edma3init() Failed.",0);5 `4 j f( b p1 |
} + ]( {1 b. Y$ f ( z' D$ N' C- l6 m8 X/ l0 h if (result == EDMA3_DRV_SOK)% _# w e% x2 ]8 a
{4 }- J0 T5 K% h# I; S
result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc, w X: F8 P' q' ^; S (EDMA3_RM_EventQueue)0, ; P! @. T) b. g, ?7 s! S. x1 i &edma3_isr, NULL); # \" {( }0 @+ |8 ~' N, Q- d4 W } , t! v. L' z/ r* D, ? " z) M+ ]& W- ?9 \5 j; F8 j if(result == EDMA3_DRV_SOK)! S6 o& A3 A% j1 \, _
{# k6 W1 H3 z9 s% \2 s
paramSet.srcBIdx = 0; q8 t- Q6 R* S+ d, o4 [
paramSet.destBIdx = 1;; @1 J& _2 C% f* s
paramSet.srcCIdx = 0; ; j& F$ X% A, B- W/ Y2 X paramSet.destCIdx = 0; $ t) ^* A+ A" A) B0 `# x, |& L* _ paramSet.aCnt = PING_PONG_ACNT;/ n2 h7 U* A5 g: R: a9 e& E
paramSet.bCnt = PING_PONG_BCNT; # X, r0 t8 M' J9 ` paramSet.cCnt = PING_PONG_CCNT;3 e: K0 I3 Y# n$ |+ d2 a
+ M7 Z) i: D+ O, F, ^+ c
/* For AB-synchronized transfers, BCNTRLD is not used. */2 ?( h; E' Y3 n; W- s( Q7 K6 E
paramSet.bCntReload = PING_PONG_BCNT; # }! L5 y) Z6 ^6 \8 \ # i" t4 |6 V8 r0 V /* Src in constant mode Dest in INCR modes *// X+ S9 s8 h% P: o% l( `: L* j+ g
paramSet.opt &= 0xFFFFFFFDu;% K! U* h0 A0 U* G
//paramSet.opt &= 0xFFFFFFFCu;: r1 L( J8 n+ h* o6 c
# g$ [4 ]! \! Q& E& g- B4 T /* Program the TCC */ , s9 ?3 y7 L, C/ ` paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK); 7 i& v8 u& J6 _0 l+ F g! Q9 M3 {) |+ t5 Z
/* Enable Intermediate & Final transfer completion interrupt */ 6 W9 }, Y2 F& O/ C' ~ paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT);: w3 c8 a! w, g# _5 B0 u! R) l
paramSet.opt |= (1 << OPT_TCINTEN_SHIFT);3 h& t1 O* l: C, n, ^/ ^
- }; h$ q! t) _; S& J
/* AB Sync Transfer Mode */. r2 o/ F# E; m. C% f/ F: `
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT);1 Y- b5 B9 `: Z4 R# Q# A" X' W
5 m/ E& M7 \8 \- H% c /* Program the source and dest addresses for master DMA channel */2 D. k% P) S7 c' h
paramSet.srcAddr = (uint32_t)(MCASP_BASEADDR+0X029C); ) H5 c5 D& t e; B+ Z paramSet.destAddr = (uint32_t)(ping_buffer);; L. {/ u3 c; S9 m V3 [
3 C1 J$ u0 e4 S/ B4 T7 {% _0 M /* Write to the master DMA channel first. */" H4 W: ~: v3 P( s; _( M+ c+ L
result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet); . X4 j" X$ Z# m9 n7 U5 F5 l } 9 P3 I4 I+ ~6 e. Y) e4 T ( k$ t3 n9 l* s; H% ~/ f; y+ z result = EDMA3_DRV_enableTransfer(hEdma,chId,EDMA3_DRV_TRIG_MODE_EVENT); , o7 ~5 z. p+ ]% p4 G" [ ; C; \& E) e% \, ~+ I8 d* ]( [/ J8 Z if(result == EDMA3_DRV_SOK) / S5 J( U4 d$ P4 _# a' ^ { ; e1 f4 @( B a# t print2arm("edma3 driver init success.",0);0 g n4 @+ [) u! i1 @0 {- i
} 4 B P/ c! T; [/ q9 ?
}/ Y2 @7 m$ ~$ N* q" o* c