: ^ C- c4 }; S3 g* ~( Z- L/* OPT Field specific defines */ . q1 W5 ?+ O& {+ H1 m/ d#define OPT_SYNCDIM_SHIFT (0x00000002u)9 z. B- p2 c! w5 p, @; _6 P V; l6 i
#define OPT_TCC_MASK (0x0003F000u) 9 G/ L& h5 |& A+ U5 f9 O! v' K#define OPT_TCC_SHIFT (0x0000000Cu)6 A7 ^! i5 C: z/ y1 |+ Y' w# `8 T
#define OPT_ITCINTEN_SHIFT (0x00000015u)' ~3 g+ y: o9 F7 `. E
#define OPT_TCINTEN_SHIFT (0x00000014u)" Y1 V6 L& X. T) b
7 H* Q& f& B" {, B+ Z- }. _; x
char ping_buffer[PING_PONG_BCNT];/ Z* t+ y# G9 j/ W( U; p
char pong_buffer[PING_PONG_BCNT]; " V X( f4 c$ Y: O }, T3 b% i9 i8 j0 s6 m1 {* a4 ^ B J1 C! Z
- W& O4 ^7 u5 X8 _8 C% N 8 z! q% I8 _4 y0 R6 Z 5 d G/ \9 t5 L- z' K& `. t7 nstatic void ys_edma3_init() 0 [. Y5 K# H/ r6 q' Z{ . v& p! y7 A$ n$ a. Y EDMA3_DRV_PaRAMRegs paramSet = {0,0,0,0,0,0,0,0,0,0,0,0};9 z. a; E- Q, R( p8 m7 S
EDMA3_DRV_Result result = EDMA3_DRV_SOK;/ D; t2 K* f8 n, Q
EDMA3_DRV_Handle hEdma; * [6 y/ C$ i4 I1 J' e uint32_t chId = 0;: }- N" k' x2 h7 a
uint32_t tcc = 0;$ s$ |" @* I0 i! L7 L+ u
; r/ E6 k n7 v4 u# Q4 W
print2arm("edma3 driver init...",0); & o- F4 J7 }) k/ i; z1 {+ q# g( x) E( l& ?; j b8 D7 t
hEdma = edma3init(0,&result);4 f- i' v) ?. A* M! B1 `8 R7 {+ O
if(hEdma) / j' H# f0 J( h: r! m { , S2 L3 N9 S- Y2 ]0 J print2arm("edma3init() Passed.",0); + D W8 {; T3 Y0 w }. B K6 e8 F- H x/ A
else n5 L& t9 K3 @0 ~& k {5 P: ]8 P# C! \5 f& b$ R' P
print2arm("edma3init() Failed.",0);# v! }$ b, ~4 ^ H1 U
} 3 \$ [, p, R) b# p3 l0 W 6 O- B5 ~4 g& |* f if (result == EDMA3_DRV_SOK) : z! M, |: Z8 p8 u5 C4 K { ' ?: ~4 D( O5 @! z( w result = EDMA3_DRV_requestChannel (hEdma, &chId, &tcc, % j7 U) g3 E! B" T* `8 c (EDMA3_RM_EventQueue)0, 9 P! i' t; ?" O0 i5 F* ?) U &edma3_isr, NULL); & }+ h' k9 J0 o; N } - A& [' E2 Q7 m" R9 d, J( Q' l H- |( B2 f6 W) X: V
if(result == EDMA3_DRV_SOK) ) _" S- @5 J1 j0 w: f& ^6 E2 w7 A { + b' U- H" H/ |# ~8 V! @) K+ \ paramSet.srcBIdx = 0;9 Y" E/ v4 ^% a* c" t, s# d8 d
paramSet.destBIdx = 1;5 w2 Y2 a% j7 o$ |' ~8 |- }& r
paramSet.srcCIdx = 0;% B( q* ?3 S1 T/ D- g
paramSet.destCIdx = 0; 4 h& R) b; q0 w5 o6 C# R6 n paramSet.aCnt = PING_PONG_ACNT;( t5 Y- G& \* Q. R$ \ }6 n1 a! o
paramSet.bCnt = PING_PONG_BCNT; 2 L9 {+ _& J: ~# i paramSet.cCnt = PING_PONG_CCNT;& a. l4 f" j# q0 x1 P
8 j' |( B) `' f' N$ p /* For AB-synchronized transfers, BCNTRLD is not used. */0 M* M. |$ I8 e+ z! T1 i
paramSet.bCntReload = PING_PONG_BCNT;! x3 e3 e" D( o) s( X) s
4 i3 s: m% `" e5 W6 a% T /* Src in constant mode Dest in INCR modes */- o# Q0 i2 r0 h; s
paramSet.opt &= 0xFFFFFFFDu;$ P% P/ m! R. ^: v. i2 J, Z
//paramSet.opt &= 0xFFFFFFFCu;' e/ ]! ~3 c" a9 B$ t
- C6 X/ A$ V8 G' |3 ?& T /* Program the TCC */ ) y v& l7 e G5 f- X# h9 M paramSet.opt |= ((tcc << OPT_TCC_SHIFT) & OPT_TCC_MASK);7 G& d) _) H; }6 ]' D
, O8 V9 O' c* Z4 L6 A: [, {
/* Enable Intermediate & Final transfer completion interrupt */' q3 n1 z1 ?! T# ^
paramSet.opt |= (1 << OPT_ITCINTEN_SHIFT); 6 ^% q! K: ^( J5 k! U% \ paramSet.opt |= (1 << OPT_TCINTEN_SHIFT); / K0 Y$ y& U2 U& R7 p3 M1 `9 r # h% g% c9 M4 w) z* @$ P /* AB Sync Transfer Mode */+ `) h* o5 y3 b0 d* x: c
paramSet.opt |= (1 << OPT_SYNCDIM_SHIFT); ' w6 g' _! ^& ]9 v , K! t# U0 k/ }8 }1 P7 o /* Program the source and dest addresses for master DMA channel */' U/ y7 h6 P" W% _1 R! k
paramSet.srcAddr = (uint32_t)(MCASP_BASEADDR+0X029C); % g: E2 [9 S) g paramSet.destAddr = (uint32_t)(ping_buffer); * m# C: U1 [4 _4 s2 R z $ D$ k. b# X5 g8 u) I /* Write to the master DMA channel first. */ & e% o/ g: }$ W/ U" d result = EDMA3_DRV_setPaRAM(hEdma, chId, ¶mSet); $ H# E; Z7 g9 w: v1 X" N( C } ) [' G7 ?% r: g" q! ^; Q- J- }' m: B . I4 B% d( z6 q& B0 m1 v result = EDMA3_DRV_enableTransfer(hEdma,chId,EDMA3_DRV_TRIG_MODE_EVENT);& B; w7 j, V6 R" A% E
* l, L8 x2 y X8 u
if(result == EDMA3_DRV_SOK) ( p* R' P- O3 B6 y1 E& l" e
{9 ]( L+ V1 ?8 c! q4 V5 }- f
print2arm("edma3 driver init success.",0); ' H- @2 f; W% v) Z' l( P" O } 5 |6 C! J% Y3 q9 i" [
}3 j: i) p8 z' T+ M/ z6 Q0 E4 R. K
4 S6 ~" t' o. L1 P
. V _9 q; ?7 b6 E
EDMA3的配置就这个函数，是由MCASP接收事件触发EDMA3传输的，中断函数edma3_isr只能进去一次，请大家帮忙看看哪里有问题。。。 / X6 F, p, B# Q3 d! p" S+ g4 u# l( q2 T