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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,: `* M N1 Z, p7 f7 e
input mcasp_ahclkx,- j2 R- k. u3 J# o5 n
input mcasp_aclkx,) ^. O( [3 N9 Z5 i
input axr0,
" }. O$ p, r7 G$ a3 j7 X: t% n, K$ s/ Q# E, }3 F0 p& p$ I/ q3 A
output mcasp_afsr,
, m$ B1 N/ V- M( eoutput mcasp_ahclkr,
, }+ D% E- k# eoutput mcasp_aclkr,
: d, h$ T w9 ~output axr1,
1 k+ w8 B) B3 ^
assign mcasp_afsr = mcasp_afsx;
; d- L, u( K) Z4 ?assign mcasp_aclkr = mcasp_aclkx;
~4 S4 L( W* f6 T, o. _- H& v" Z/ }assign mcasp_ahclkr = mcasp_ahclkx;! A2 A5 q; j( G/ W9 ]+ V& }
assign axr1 = axr0;
9 C# W$ z/ ~1 }' z, U1 L0 B
5 j3 j- l( i6 l3 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
8 U( c$ G+ V g- b4 b9 ], N B
static void McASPI2SConfigure(void)) ]0 M/ k6 k1 K7 Z
{5 H9 ]3 w I1 Z( }' y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 p! _2 m. S0 \3 L6 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */4 i- T2 X n6 j _' _# ]7 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- e2 y# ?$ ~1 d8 T3 ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */+ m) `5 I/ {6 M* p6 n; o+ e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
K* z( o& L' \$ [( |0 _$ rMCASP_RX_MODE_DMA);
o: ~, G: g& QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 U3 v l$ P# j; S) l( HMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */! B$ i; |, [7 C C# `5 `( `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! v* Z, Q: N2 D6 [) ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 |6 \: n; @. P9 M! ]: GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 D' l8 m1 M5 ~# j2 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */& @# o k% ^8 \& Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 k' h o2 P1 ]! n0 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( N8 k( U V* U. p. zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& I1 a" {! [$ L: r- N! r& e( d0x00, 0xFF);
/* configure the clock for transmitter */' j! W) ~5 S& ?# L- E4 Z( H; x4 u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# a" I7 H, e. q3 b# o9 O QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 Z* y @8 Z( Y9 B: YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) e7 w) u- i# l* l# B, t0x00, 0xFF);, D! E* H, G/ D, x5 D, V
6 A: {* K) Y8 a. B0 j A% q
/* Enable synchronization of RX and TX sections */ 6 u% x! B( a' P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */; H" i5 n- s0 e% P4 ?) }1 s6 D4 a2 X4 [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& U+ o e: Y" i5 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*
/ K8 N9 u, y/ a* v9 }** Set the serializers, Currently only one serializer is set as! `( [9 |; P; a
** transmitter and one serializer as receiver.3 h, E3 c' g7 {1 }0 f
*/" F$ d/ L* K; d# B" L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: R$ ~' M4 A/ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*
1 \% H0 }. a! o1 C5 e** Configure the McASP pins
( I9 `2 t" C# N& E! T% g% R$ B** Input - Frame Sync, Clock and Serializer Rx
3 ]1 t6 W) R& H** Output - Serializer Tx is connected to the input of the codec
7 K0 K* X( e" w3 {! x*/# u6 A7 x" ^5 q! B1 f' ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ U5 x) P1 d; W9 E6 ?2 i3 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- I* p- L3 l/ T2 l0 ?: z3 U& X- PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
z( n5 p$ j( ]' m2 D% a| MCASP_PIN_ACLKX1 e0 }1 ]3 T* v: H, p( ]0 O0 w' E
| MCASP_PIN_AHCLKX
2 E7 i) ^( E3 I+ q; o( i" o| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */% A, V( P3 h, }( f- [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - |! n; C1 D( f9 e: }8 F
| MCASP_TX_CLKFAIL 2 B+ r) ?% d$ C4 w
| MCASP_TX_SYNCERROR
/ W" e* ]* L" |6 u| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * I& m- H! ?) o# v' _- r
| MCASP_RX_CLKFAIL
5 V( {8 h O4 c* m2 d$ `- Q| MCASP_RX_SYNCERROR + t2 V4 v& n6 E2 O1 f b) I
| MCASP_RX_OVERRUN);7 L7 ^8 q4 s2 C* r- d! i6 f F
}
static void I2SDataTxRxActivate(void)& t* @" [: }8 X) Q# |6 p
{
! ^& \, f( x2 e) n8 T/* Start the clocks */
# k6 J# N8 r! j5 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ G* E/ N1 Z8 v2 F7 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */% q& w s( N( f: M: c" H) _. o7 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 v% I: v9 ?9 z; g( t" OEDMA3_TRIG_MODE_EVENT);
, v4 E: ~6 q9 y0 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ H6 ~; T3 i& z l" GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */& @8 L8 r- b9 e* W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% D! s! h4 f1 ^4 f. C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */0 j0 K5 J% ~$ [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */$ Q# f/ l+ h. Y: U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 H; E& y3 l6 A. E- ?2 p( I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# L9 |, B# ~- H4 {( @+ x' ~* {}
; `+ P& h- c9 k6 q: g
请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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