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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,
6 ^7 i0 Z* L5 s5 [: L* u1 x5 n: U- Tinput mcasp_ahclkx,
8 v! Z3 Y8 q: d; F+ uinput mcasp_aclkx,
- Z6 p/ M0 z4 [* z' l$ j- K* g# jinput axr0,
$ v% o& Y2 O3 i
% D3 ]. C l; A) eoutput mcasp_afsr,5 Z' [( L( h6 n2 r$ V
output mcasp_ahclkr,/ F B- T1 `2 T1 m9 @: |% {: O
output mcasp_aclkr,' _% h/ F8 i) l* e
output axr1,/ y- P( i2 U7 { @0 N& M0 k9 E
assign mcasp_afsr = mcasp_afsx;1 c8 B1 ~. u* ?
assign mcasp_aclkr = mcasp_aclkx;
5 O$ z3 K( L/ z1 g1 qassign mcasp_ahclkr = mcasp_ahclkx;
$ W; c/ ^. ^! Z; Xassign axr1 = axr0;
) Q5 T" X3 i$ b1 d
$ v# M% Z5 E8 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
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static void McASPI2SConfigure(void)
6 F$ V0 m, }( x5 O$ X{
8 s$ w! u% w g& M+ L6 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% F% p# t z, ~% ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */
0 |8 h: I* j1 W6 T; Z5 lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 l. z. I. c2 ?& m, B5 p% fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */
+ P& z$ ?3 V% t; J) A% v& |; {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, m" F3 r+ _- ?
MCASP_RX_MODE_DMA);9 p5 F4 \; ^0 {( ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: E8 ^% x$ r+ [, VMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */( Y9 \ z7 i5 v9 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 ?' f6 f5 U0 B$ J& @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ b' d& P2 T& R1 X4 E$ wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. D+ h( X- d `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
. q9 S1 F: F+ {6 B8 J5 U/ _4 xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* v H D% h2 D5 a7 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); a U% l: O) Z0 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 C. }) W+ j6 [* }0x00, 0xFF);
/* configure the clock for transmitter */( W1 O. n" i% {( W& R9 ?: U6 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ z! A- C/ z o9 w2 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ H% n& j4 I) n- ]2 Z$ c% sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' i" h# E" @( L, l7 a) ]) S: z0x00, 0xFF);- g4 q* y7 ?# \: q# D+ \
# d } Q" o* g- |$ B4 [/* Enable synchronization of RX and TX sections */
" E& h! P! G- S+ Y2 v( a6 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */, T; t) x4 p; m3 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 e# z2 X5 \4 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*1 W3 X F+ {% R! ]. x5 V
** Set the serializers, Currently only one serializer is set as# \9 m& T! k& v1 L
** transmitter and one serializer as receiver.5 W G$ m3 n. l+ |% o
*/
: {1 l3 W: j3 q8 IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& l9 ?/ D- B/ L1 c2 ]& M. lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*- }' I, C- t \, s7 J4 p5 p8 @' r. L0 e
** Configure the McASP pins * k7 |8 U. e5 G$ @5 U* v
** Input - Frame Sync, Clock and Serializer Rx- h' F( Z$ ?6 x
** Output - Serializer Tx is connected to the input of the codec
. y G/ O; t" J& _*/
& v5 A* e2 _0 M5 y' @) y; GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# a3 Z# Q9 L' o$ CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# r$ R/ |4 @2 I' I' wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" H- t5 ^; b1 R; T
| MCASP_PIN_ACLKX
: o U7 z" k: l0 M, R| MCASP_PIN_AHCLKX
- }( j* O) h2 g+ [$ K) x1 ^+ o| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */: D- n) D" z0 ^' k: }. y3 Q; G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * x( k) H1 ~5 X& o# ?5 m
| MCASP_TX_CLKFAIL * o" h r [/ P0 N, L; b
| MCASP_TX_SYNCERROR+ K x+ e* P8 v- Q! {& r( c7 J
| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; `3 V( @# U% K. \1 k/ g& ?5 k, g
| MCASP_RX_CLKFAIL7 n I/ F4 Q. m/ A3 d& O4 {$ F
| MCASP_RX_SYNCERROR
' C j3 |: T1 X. m. G& q) T9 [| MCASP_RX_OVERRUN);! z' c# L& E- |; _0 S5 \: i
}
static void I2SDataTxRxActivate(void)
7 d6 p6 w2 B$ T{
) m, k) G6 ?, r/* Start the clocks */
9 u8 F. I& e* |) @( `+ `" jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 [7 U$ Q) k. a$ }$ _. T- ^/ `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
1 N' W# B& p4 k! ^$ a! t; Y$ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! ?# b- d9 u, U, R' F
EDMA3_TRIG_MODE_EVENT);% X3 `2 j+ i! A: L: J9 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, N1 [% c0 w5 h# AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */% r# t8 s# ~$ l; Q' L) u! a( ]8 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 Y8 }& H* v! z J2 A/ xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */( ~0 K6 v) @" {9 {# _6 C% [3 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */2 F3 L5 j* L8 i$ c* A# S& h% m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; F L! m7 N& y3 L: @. z' x7 M; {% uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 }) ?. K+ J# z. _2 e}
5 d( g4 M0 T0 ~5 L
请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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