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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,
4 ~3 l- P; C. Finput mcasp_ahclkx,2 H; B2 w5 k" `" k) S: v) d
input mcasp_aclkx,
7 n* M+ y1 f) ?/ Yinput axr0,
" O4 ^( b! c+ j4 f; T/ A8 E4 E5 ^+ q
output mcasp_afsr,! m) _- x) E; _- W
output mcasp_ahclkr,- A2 A' b' I3 e6 T
output mcasp_aclkr,
) x' O/ @# e2 V7 m2 F. b" Loutput axr1,
1 `7 S6 v$ C$ E5 O6 a9 L, j! {5 a
assign mcasp_afsr = mcasp_afsx;
- M4 j1 b0 m8 f+ T. Eassign mcasp_aclkr = mcasp_aclkx;
+ Y8 n- k9 a+ s. j2 ?# Q" L3 Y$ i# hassign mcasp_ahclkr = mcasp_ahclkx;
- T1 J( k! h" f& y! z) n/ Passign axr1 = axr0;
" U7 n8 d+ V7 r; d2 s
" ^ L8 _5 q6 O6 b& o( |; Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
7 ]4 `, L' u1 c: r8 [
static void McASPI2SConfigure(void)6 a2 }! B& t! B }7 ~0 }4 T% W
{+ H7 J, X7 `0 W$ ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; h0 Q8 p$ {0 I5 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer *// h4 [$ ^2 U. R+ g5 [1 x( \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) ]9 M: P N) p6 l, UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */% n2 W# Z+ ?5 A" O" k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# P& p+ n2 W& P6 l" N! P* t. j& QMCASP_RX_MODE_DMA);
+ a9 N8 z3 h4 H% D0 b) A, E: A+ IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; C) h! D9 W% z+ L/ n& y9 E$ c
MCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( W9 f" E, U; o3 R( g/ \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " S+ S; d* d9 _* J6 ^3 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. z* L; `! t# K: c$ }. gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 l; h% o: k# P7 w5 ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */, Z& ]0 E# W. `+ o) `/ R+ t$ }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# B" r+ i. @# {3 `4 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 G c' Q+ \' M. \$ L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ L8 u: `4 F8 t! Y8 j
0x00, 0xFF);
/* configure the clock for transmitter */
7 j3 ?3 r9 j8 C hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! A* U. M% ~+ h* `# ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # ?# e5 e( B. a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% ^" u5 Y+ C/ g8 Q0x00, 0xFF);
) w7 b& w, \+ o7 K- i
( ]* ]& M, _: [& a! N3 s. W/* Enable synchronization of RX and TX sections */
8 I% n& y" T! z8 k, x. nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */. r/ N1 T4 j* L E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( z7 X, @# e- K+ W9 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*
0 w6 a l- f, c5 G- z& M** Set the serializers, Currently only one serializer is set as
+ c. [4 l$ l1 J/ w** transmitter and one serializer as receiver.3 ^$ ^7 d+ }: c4 G: G5 T8 a& \
*/
9 e' X" I6 U" EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- T% D G; L; bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*, ]2 U/ M' D- g: `# m y
** Configure the McASP pins
' Z2 p" H& I% ~8 Y+ b, G. b** Input - Frame Sync, Clock and Serializer Rx
/ m: v5 S3 X7 Z** Output - Serializer Tx is connected to the input of the codec ) B- Z( F8 z: ^& k
*/. A% r) F8 l" }* j% p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* R- S9 w1 `) _, [9 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: b% h7 ?; i; V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 e& r) f3 H I2 A+ d( u
| MCASP_PIN_ACLKX
! ]! e5 J4 Z1 F" U) @| MCASP_PIN_AHCLKX
" K, r" c1 }& R& R2 d! R6 j| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */
( S6 L5 a9 a# g e9 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 o# a6 z' H- G6 O| MCASP_TX_CLKFAIL 8 r) d+ y. \3 ?( I5 J( L g* c7 d
| MCASP_TX_SYNCERROR% W) i0 J8 L3 m
| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % t# _1 ~7 ]: m6 m7 f, X7 {
| MCASP_RX_CLKFAIL
5 h( Z" ~* U; H| MCASP_RX_SYNCERROR
. R7 r0 c( d/ q1 J1 @' q, E| MCASP_RX_OVERRUN);7 y1 a: x. N! v3 ?) m
}
static void I2SDataTxRxActivate(void)
- \- f" ?( J9 `2 M9 V4 ~2 d{
& R- d) Q/ w |' F$ e& r' P! I/* Start the clocks */
$ o+ p7 O+ q$ JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. o1 i: T8 O% `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
4 B7 {' I+ G& @7 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% |$ O8 Z" W' sEDMA3_TRIG_MODE_EVENT);$ l3 l& ~2 \: i$ G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) m4 @/ W' i& d4 n0 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */' v, i6 X; \/ T' e& a4 y: f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 z6 e- L+ @9 u+ BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */
u7 P# e4 j# @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */2 {* P1 \1 l R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% E% ~) ^' |9 K2 L8 p; b+ t+ l5 F9 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) A) A3 l! j( ~/ q; Q; i" B' V2 b s
}
, N" w: q- S2 I) D) e3 T3 [请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ z0 }0 p. F# B
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