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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,
% D3 V+ W/ N2 p% E3 Oinput mcasp_ahclkx,6 H/ B& l" F& l5 ]
input mcasp_aclkx,; e; q3 D" ?5 {, r% j
input axr0,: U& e: u& }- V7 r/ P- K
2 K+ R0 ^ ~' {: k$ W6 ]( n
output mcasp_afsr,
4 S: \! E" ~) F' e$ G5 n' M9 boutput mcasp_ahclkr,- } J0 I( o ^2 V6 Y
output mcasp_aclkr,$ @) I5 E+ n+ o$ t5 b
output axr1,7 z# d% A3 x- y: y: c' A
assign mcasp_afsr = mcasp_afsx;
* |0 Q) I: Q. ~% c. |1 eassign mcasp_aclkr = mcasp_aclkx;4 G9 T0 P" }/ y ^/ x/ c
assign mcasp_ahclkr = mcasp_ahclkx;! K0 x4 t( B5 u/ }! i, H
assign axr1 = axr0;
* ]7 R2 \$ N6 ?' w9 _8 E
6 U# w- O& S. ^5 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
; Q: }0 t+ [$ f5 g6 A- e8 Tstatic void McASPI2SConfigure(void)+ Q: B4 I$ B2 o3 ]- ?
{: o( _6 c% U: m4 }, F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 G( |) J4 c% L+ yMcASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */
/ p! }- Q7 J* G/ i8 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 m0 W) O0 P# _" BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */* d% h! w8 ? R3 X+ C, z0 Y+ O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* N* s& X2 ]1 ?. u6 H
MCASP_RX_MODE_DMA);
2 W1 Z2 l/ O9 a" j6 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ~8 D7 i& F }5 b4 A cMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */% f6 }; d8 }. g9 ]5 z7 J* g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- K" w, h4 I" w2 r5 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 h& w: e4 x2 g1 s6 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 Z5 R/ t8 Z: J4 G1 O f- N4 I3 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
4 U7 b' E$ j4 k1 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 z. `; x" ]' T: `. }! L1 s# G# sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
X T% `- n; l: C; tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 j( M! ]( x; h* C0x00, 0xFF);
/* configure the clock for transmitter */
$ w) h" o0 _% n- ?& T" A- \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) N( r% d8 ]6 ?) H1 V& lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # a7 q$ [! e. S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! E/ b7 ]9 u$ k& f* a0x00, 0xFF);
1 W( f! f5 O1 }- d6 O6 X" o2 [ ?
1 ?- q' q+ }& r6 l' F/* Enable synchronization of RX and TX sections */ + d. z' t8 g L# [% \( o, S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */3 ~; \6 |9 t. V! n- `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( |# R+ k4 N9 i" e" n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*' t/ E9 U5 H8 n) P# i
** Set the serializers, Currently only one serializer is set as
; t+ c* X: Q% k2 ~** transmitter and one serializer as receiver.
- F9 t; `' {. c7 P1 Q) E$ s8 O*/2 a- D [0 U8 Q% Q& H, R9 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) Z- _3 G8 x. _, x/ s5 C% f! jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*
( a- X/ z2 Z5 h5 c& R$ w** Configure the McASP pins
+ L! D/ Z0 h6 H- m7 Y** Input - Frame Sync, Clock and Serializer Rx t6 Z+ I/ |- q/ d$ L
** Output - Serializer Tx is connected to the input of the codec
$ s! `9 E8 V. r5 G& y*/) [$ q; @5 `9 k( {) N n* U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 M$ K5 Z5 w, l5 K% Z1 V$ s: a8 DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! y& } c& u* Q0 n( c4 p N t# {7 q& uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 J7 u- D. |; H
| MCASP_PIN_ACLKX
& ]: O0 _- ^* Q' z3 h1 f| MCASP_PIN_AHCLKX% `+ j! g7 k4 x8 N) E
| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */
# }. f' |& N) E3 p2 t" WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. {4 D9 v# W% A& I| MCASP_TX_CLKFAIL
4 W* b6 N! z( ^, ^| MCASP_TX_SYNCERROR% d6 m; j, r: W: i
| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 u: _, z. }% m& y, }- F| MCASP_RX_CLKFAIL
; b7 n" n0 `/ L. n8 n$ l| MCASP_RX_SYNCERROR % v4 n E5 k2 F
| MCASP_RX_OVERRUN);
# h `* V2 ^, J/ P}
static void I2SDataTxRxActivate(void) @7 B+ |" q% ^: X0 o" [+ M1 ~# l
{, y+ x( ~) D& ?# g: t- V+ |! h
/* Start the clocks */6 A) s4 L: j# s9 f2 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 q9 X# H: r2 p$ S1 H8 |. h, w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
1 G: v' z3 D* P" h+ J) ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ Q- ?9 x. M4 {% g5 F; G) n& ^; N
EDMA3_TRIG_MODE_EVENT);
& c9 J P" T7 l% }8 d& N$ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 k' I2 p! s) g4 M$ L0 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */
$ M& G: U: e1 G$ E# h5 z; J' yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ K5 M7 S6 P' U+ `1 Z2 V4 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */
) m p" s- B3 P0 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */
4 O C) \) K4 t" W8 w! }3 L, LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 K$ @: X. C9 T- Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& O' K# \8 V: u
}
! w2 ?; T2 i" M" y. c8 g8 z请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
3 t$ D) Z" }$ @& }
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