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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,
/ I' _2 |- v! X3 {+ q5 Xinput mcasp_ahclkx,
" B$ P1 d! a' \input mcasp_aclkx,4 }/ H; e' H# |2 A% ^& C
input axr0," g3 I/ v0 C5 f0 _4 x1 }/ L! \
0 F: M9 a8 \; c( Eoutput mcasp_afsr,& u7 C% y2 S* i! I% X3 b; x2 i8 Q
output mcasp_ahclkr,: q8 H2 p4 Y% C: ]- W
output mcasp_aclkr,
3 R0 {2 M: X3 a1 M' I6 M2 [output axr1,
8 H# Z$ M- A) }& c/ H( o4 K- Q
assign mcasp_afsr = mcasp_afsx;
( c) N/ d& Z( L, |' ^- |assign mcasp_aclkr = mcasp_aclkx;
7 E8 T' F/ z, u: j# oassign mcasp_ahclkr = mcasp_ahclkx;
- A8 M7 L+ W* u3 Tassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
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static void McASPI2SConfigure(void)
. m5 \% F9 l2 J$ {{4 f! m- X" V( Q0 P' p8 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- k$ S8 I9 R4 X; J" l$ Y# `McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */
& S I2 J3 G4 x. z. m& P" A' K3 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 _ r4 Z: N+ C+ U" v3 Q2 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */2 W2 S) v; B1 A' q( f( U: y' {7 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" c- k [. I. Y4 H( R9 KMCASP_RX_MODE_DMA);! R9 _; B9 b5 I1 v! {4 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; M% \; i6 }3 c y- {MCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 D# h8 s: m; D, S/ }8 g$ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! r! `3 {$ H r- n2 G: }1 u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 I4 e( ?9 }# R0 m4 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, J @# c8 \7 R6 G" Y. _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
5 w. l _ W/ ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' V% N: Q+ V; P* M9 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- K: I$ l8 _6 ^. }/ r5 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; z9 `& W1 F! m4 r, O0x00, 0xFF);
/* configure the clock for transmitter */
# g( o! J; y; s% O2 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 c( q5 f- C5 i% m4 f7 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' S- b3 i I& l* N* N6 B! ~+ sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- l' L* e0 G* v3 a9 ?. g# \
0x00, 0xFF);
% B" ~4 K. R- \
~* r3 @, {2 ]9 l/ J/* Enable synchronization of RX and TX sections */
% E# u. g5 Z3 F) tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */5 B3 s6 ^& [! ^% b- n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 r4 A( b! N' Y8 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*- H' ~8 R6 r% j# N* L* j/ Y* c& c8 U V
** Set the serializers, Currently only one serializer is set as
& U1 E+ g4 l& C* U" t** transmitter and one serializer as receiver.- e( k0 `% N8 q ^ K s( T& P9 R$ s
*/
0 d% l2 d& i4 ?+ i5 WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* W0 i" s) ?3 N! h0 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*. e. S* V4 u7 S! s& Q
** Configure the McASP pins
% O; Z- E- G6 p4 f" {! l; n** Input - Frame Sync, Clock and Serializer Rx) Y: N- U0 H! l0 }5 H
** Output - Serializer Tx is connected to the input of the codec / F, f. _0 J# K2 y
*/
/ t6 i4 P% o) \, k5 K' l5 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 I! |) L, u' h/ b0 y; @# o& M' S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ {; ]8 D; z8 `) P. D3 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% A$ a6 `6 t8 p$ F# u" A| MCASP_PIN_ACLKX! D6 W. L* N6 f6 D' e9 M% v
| MCASP_PIN_AHCLKX% @% r: F/ [$ k" [2 y
| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */' Q4 R' Z' D K B: @+ p3 g- ?1 P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
x$ T# [4 X! i3 t% d4 M| MCASP_TX_CLKFAIL
5 h, I0 ^( m6 V9 b" j0 M6 p| MCASP_TX_SYNCERROR+ I' q! |1 m/ B5 b4 O+ f
| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- c+ D' a! ]+ c( G| MCASP_RX_CLKFAIL
4 [ @" V4 j2 r S| MCASP_RX_SYNCERROR ) Y/ P2 ~8 z8 Y; k4 P# L+ q) l
| MCASP_RX_OVERRUN);, u+ [: d4 q! r }4 g
}
static void I2SDataTxRxActivate(void)
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/* Start the clocks */& s8 I& u3 X) `, Z. Y0 ~2 g3 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& Z; w1 {* i2 `% YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
* a: w+ F3 k/ `; W- hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; A G" U1 j; ]: d
EDMA3_TRIG_MODE_EVENT);
) [$ o, X: ^2 @& f7 p! T2 K4 L8 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( K0 } _3 w8 M. q+ q F) l0 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */. r+ ]9 n$ a) `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 S. c& r* i* Q+ |! m3 k qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */- B& N/ e. K( v4 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */
2 b- \8 Z! d1 ^6 s' x% R; tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' A, }5 i; J/ V7 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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