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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,# b3 r% E- B7 c; I! V, M
input mcasp_ahclkx,
( l6 f# d/ Y. m0 sinput mcasp_aclkx,
" n* K5 q4 j ]5 [% Oinput axr0, S) Q; k% L Y/ q- s( B
/ B5 A2 |4 V2 K# V$ Y' O* Ooutput mcasp_afsr,
" d# e0 q! D$ p5 C$ I! ~- _output mcasp_ahclkr,
# m% M% e9 m8 p8 s7 \* O0 n4 _output mcasp_aclkr,
) W% n5 i9 M' ]. foutput axr1,
7 J- L: X. d. w' k, `+ d5 m0 \
assign mcasp_afsr = mcasp_afsx;, o l( Q* w) V6 M5 w0 a
assign mcasp_aclkr = mcasp_aclkx;$ r& Q& b- F# `7 U+ z* _4 G$ o ?
assign mcasp_ahclkr = mcasp_ahclkx;* G$ S, p* x" f& q. R5 b
assign axr1 = axr0;
- h% K" M$ e% R: m5 D" ]5 W: j% x7 c; n2 k4 `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
0 M% m7 J) s3 S& Dstatic void McASPI2SConfigure(void)$ ^8 c1 B7 E% H
{
2 _9 J6 F8 r* L* w" C vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 {( f" P0 ], A' U& ^& j
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */! I( | B/ ~% u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 U k6 m4 I6 B. l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */( w5 S3 o8 V% d( Y( V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* V) x; k- g' D9 d. DMCASP_RX_MODE_DMA); P+ H* R% R' H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
f5 h6 t8 y$ D$ ~/ qMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */# y' M( ?8 I0 A5 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ U# I5 N1 V3 B$ yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, W4 N9 t$ Q6 I0 v+ t# E! N) C& K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - Y; g1 V; L8 i2 _# v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
, J8 |4 j" d9 y) LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* w) T& j% a9 s3 n0 s5 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' T0 @$ K0 B* pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ U+ ~- w: o, }9 V; w* P0x00, 0xFF);
/* configure the clock for transmitter */
& Z" g- g9 A8 x& x" y* |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" _) `+ ^9 i3 ]% H( D, g3 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 K n; \# d# u9 P' TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# I, N! } _ r7 Y8 `0x00, 0xFF);
/ H" V$ b% I* D( y8 L0 k$ E" u5 O$ ~) w# c, Q. R" }- A: f
/* Enable synchronization of RX and TX sections */ $ O+ |. O5 H/ H+ b1 {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
( k% b4 t/ r4 D0 [8 |7 w" WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ B( V O1 F R" z" E5 C+ ~5 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*
/ K( M% u' A! B4 H2 h** Set the serializers, Currently only one serializer is set as
; b8 J, a+ `8 P+ C6 h# A/ D ^" s** transmitter and one serializer as receiver.! n% X* `8 Q# p! F
*/
2 l' T9 N* k% u) @2 y; mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
A& g, H! ?9 o( g7 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*
5 m3 v& f/ d. Z% X** Configure the McASP pins ( P; _9 p d- A5 ^! r
** Input - Frame Sync, Clock and Serializer Rx
8 g" q* i, i- ~& D1 U4 B** Output - Serializer Tx is connected to the input of the codec 5 X" J" J4 d+ e% h$ m' J, x
*/0 _- y: Y& B) I- `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* g3 s9 }& e! s6 Y1 x; n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ | ]5 y- g7 `5 v0 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ ]7 B5 ]9 O% v+ n1 L1 R| MCASP_PIN_ACLKX a' h- u7 F; O& B8 U8 X
| MCASP_PIN_AHCLKX
9 \* E$ r0 o1 Z| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */
* E+ U( K5 B) l2 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, M- {/ i, x, k" k- Z. m* u0 {5 {| MCASP_TX_CLKFAIL
9 h( R) ^& {5 e/ s/ e| MCASP_TX_SYNCERROR
0 x, D% U4 K. }, H/ j4 l0 w| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 p9 T. [. n7 l* F| MCASP_RX_CLKFAIL
0 B/ r4 V5 k+ G7 q8 m. l| MCASP_RX_SYNCERROR
8 r2 L& ]% z* _3 \. d% z| MCASP_RX_OVERRUN);9 s( h* {$ X/ w C
}
static void I2SDataTxRxActivate(void); I& W/ W8 `5 Z$ o* {
{
3 G) f# A" S2 S/* Start the clocks */4 m$ P2 N9 u9 W$ o' ~8 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; _& G' ^, [! p. hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */: x1 g4 K" p; I) p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: X& N* S) C7 q" I W1 F0 q% v. |EDMA3_TRIG_MODE_EVENT);
4 b# V3 H0 f& d# `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 C& O: ^4 f( l# Y5 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */: e* F& E$ H! t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( k# M% G; K1 |# ]% h; gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */
5 F' p+ [* w9 U& }' Y: qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */7 S3 E+ E. V6 l4 L9 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& S0 H. r! R9 [" ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ l( j \% u9 _/ Z}
" K9 w+ U `. `* T, x' p
请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ |) ~9 B1 _, |) H% ^1 E
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