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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,
! g6 K E: k7 l2 zinput mcasp_ahclkx,! s, x" a/ y% D
input mcasp_aclkx,* I5 j; i& g7 y0 a9 T
input axr0,
( k, \7 O! U( s I
7 X! G2 G: r6 N$ _# K2 ]output mcasp_afsr,
+ ~5 _$ Z: q; youtput mcasp_ahclkr,6 a d7 H8 j4 W3 R v
output mcasp_aclkr,% n5 C8 R% K# u' ^6 _
output axr1,% h& E+ T' I5 T' j
assign mcasp_afsr = mcasp_afsx;
' Q6 y- r$ Q' `2 F& A3 ^assign mcasp_aclkr = mcasp_aclkx;
- \2 z& i; U. [' Z/ E7 L1 Aassign mcasp_ahclkr = mcasp_ahclkx;1 ~2 Y( P9 t+ w/ V2 b( } J1 v
assign axr1 = axr0;
8 n- Q- T/ \% N9 ^/ o
: k' m! m6 x& `# b1 c1 m6 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
, C7 T( H- d% B6 p% j8 R* U
static void McASPI2SConfigure(void)1 C z: l2 P# i9 ]3 E
{$ x" h% H& P& v9 ~5 r( C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ M6 S& ]1 N/ V, K$ B
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */1 J8 A, a" ?# k' F2 W9 o/ n/ R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ p; Q8 H: O7 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */& d3 a1 D" ?8 D( x* B' C' G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& B7 n9 x+ R6 W. N! Y- c! @
MCASP_RX_MODE_DMA);
4 u0 R+ [+ B7 p7 k7 @0 l2 Z' G; zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" k0 J/ G/ d0 tMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 o5 K L% j- d: wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 m1 e' D1 B" m2 b1 `* R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% |* @' V* }8 z' n2 m7 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ _: B* r8 Z2 M: S/ ~4 I0 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
7 F/ g+ l& v6 z- n' e6 B/ bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. |. r* K3 d' s, I D7 `7 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ Q* m/ s2 {5 p% IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 ]7 c- p& u* q0x00, 0xFF);
/* configure the clock for transmitter */
& R- o5 p' K+ @+ x9 f8 I3 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# E% V( u2 P0 e4 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . G' r* Z, \' S' h3 K( H5 I6 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 d9 v" F8 p2 P/ o! R( @
0x00, 0xFF);$ O$ F% ]" V2 [- o( j' w9 F
3 J6 J$ R+ ^- d, C/* Enable synchronization of RX and TX sections */
/ F* |8 ]$ y( Q/ ?1 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
* x8 `6 a5 a1 E2 |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ B- b+ ?2 T8 c2 Q( zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*
; b! L! t2 T9 W e+ k' _# v** Set the serializers, Currently only one serializer is set as5 I7 L2 D1 q; G* a6 x* w k9 {& t$ q
** transmitter and one serializer as receiver.
. u5 z5 I, G) X( K+ A( L*/
: `6 J, c# W3 E# UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 [1 }, p% `! R; ~6 ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*
9 z" _1 N8 F% O N# |7 P** Configure the McASP pins
! g9 {9 f3 B# [/ F3 T0 J9 I** Input - Frame Sync, Clock and Serializer Rx
; T, T _4 S8 b1 k; }** Output - Serializer Tx is connected to the input of the codec
1 x0 K8 X/ `+ S+ @$ A" h- C*/- v9 `* C7 b) Z/ A0 g- x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# e! h6 F$ [8 k/ q) ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ N& e* z4 [2 J/ {% b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 \$ Y8 h* t. u1 y3 `. T4 j! E5 \
| MCASP_PIN_ACLKX* ~; r3 u. \8 l: A' n
| MCASP_PIN_AHCLKX
* D: {! _* d4 w. Y/ g| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */
2 o. b" d/ k7 K9 H) `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& n6 e9 a/ d& j/ M# w. O| MCASP_TX_CLKFAIL
1 E( M w" v/ {4 d' ?0 [| MCASP_TX_SYNCERROR
4 p6 F' I6 R7 t| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 I) W; g- c9 K2 \1 i; x7 [- c- e
| MCASP_RX_CLKFAIL
" {0 T; V$ V4 n) o" `- t| MCASP_RX_SYNCERROR
; H$ e& u2 I: s, \3 t| MCASP_RX_OVERRUN);
; N6 ~; [! _0 v7 s. a% {' Y" v# j}
static void I2SDataTxRxActivate(void)2 L" r: W8 e/ W; F C: H4 h* F
{
, h2 v: o- ~+ w& e/* Start the clocks */! F; |1 a7 D8 J7 ?- J, Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 Q+ n9 p: K; V* D3 C% \$ rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
4 P% d1 @ M- AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 O! x( d! c0 NEDMA3_TRIG_MODE_EVENT);
7 S8 w1 k, h: D* NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - y4 r* R2 B5 }, C) o# w0 B6 _7 ~7 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */
6 y8 Q' Z' T$ N" |8 T; w) IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. q8 V. g% K6 L: f; {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */
. ? D) Q' p5 n) c7 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */) T; y' w. T3 E5 R- Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 z2 y3 X' M4 v- j$ N- t6 x7 n! N% _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% H2 i9 X, C& L6 {}
2 ~- i5 s! A2 b' O
请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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