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标题: MCASP自环配置。 [打印本页]
作者: wapdasta 时间: 2018-11-7 13:28
标题: MCASP自环配置。
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。
部分代码如下
input mcasp_afsx,# N& b# e, D7 {7 S
input mcasp_ahclkx,
# V3 I1 b L I( G( pinput mcasp_aclkx,
: C2 L9 O' @' P$ F* Y Zinput axr0,
7 l0 R, c \( m6 A: `
3 G! i+ w: {% _& G6 B8 qoutput mcasp_afsr,
2 `$ ^7 S) N5 t- S* Goutput mcasp_ahclkr,
8 S/ V2 L9 G5 coutput mcasp_aclkr,- i; g* t* Q+ ?2 p; K
output axr1,
6 ] E7 X; n* ^( u1 K
assign mcasp_afsr = mcasp_afsx;
+ q Z( l' ] m. H1 ~8 zassign mcasp_aclkr = mcasp_aclkx;5 A4 S! E+ b; }: C4 p
assign mcasp_ahclkr = mcasp_ahclkx;
" z# m9 ?- E* I* c- Aassign axr1 = axr0;
. ~# U* s% s+ j/ P- {: d& o
' t5 ^5 W+ a* l/ m* G9 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。
在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。
一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。
部分代码如下,关于edma3的部分未做变化。
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static void McASPI2SConfigure(void)
4 {( E6 A% \' l% S7 S. [{6 d' p3 X$ Y8 T+ S7 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' m9 v, Y! b# ?6 i" l; F5 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS);
/* Enable the FIFOs for DMA transfer */' M& w: }. R; b3 c+ g3 i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 [/ t% [: z% b+ W9 R9 K6 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/* Set I2S format in the transmitter/receiver format units */% I3 `" q: N+ U% T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," h; m" o! z6 M% A
MCASP_RX_MODE_DMA);: z' B+ l+ D8 B4 P7 T( w- Z. [7 c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. V7 ] R4 @: a0 iMCASP_TX_MODE_DMA);
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ I L* f6 H- c2 E8 p. o* l+ LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, |( b/ M0 C( x0 _% X; O4 k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 D% g0 m) R2 u& R1 ?8 f7 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 Q# m0 Z2 r5 l# i3 @; `- Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);
/* configure the clock for receiver */
3 o2 B0 |& z; a* G" V5 aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% L3 l2 c; p3 d& s: T* Q% c! A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! ?" N5 M* Q: D; s* H9 Y+ cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ }' J! R3 I4 z, g+ Q: K0 G9 f
0x00, 0xFF);
/* configure the clock for transmitter */1 J" t' |: V$ K0 v& U8 z% B7 U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ^, E2 ^6 a% d6 @: C' X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) \5 b% z. c* L7 X8 Y- M% eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, U% X) q# I; r* Y
0x00, 0xFF);2 \* z9 x4 U- d# o% k
# A, b: m( C) H
/* Enable synchronization of RX and TX sections */
9 Y* f K2 v4 |) vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
/* Enable the transmitter/receiver slots. I2S uses 2 slots */- G! z c4 L X. h( g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# S6 k2 B9 q7 j$ S/ X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/*+ @5 Q* r5 N/ W6 r# z
** Set the serializers, Currently only one serializer is set as9 F9 X" b5 C9 t8 ]+ m/ M. R
** transmitter and one serializer as receiver.
* L& Q) q. q: V {# ?$ H3 e D5 A*/! C- t8 N0 e2 \; T( S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 j& U5 v: k, J: {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/*2 I2 ^, v9 Z' B" I. h* Q! N7 k
** Configure the McASP pins
9 I( L3 h- `: \* I5 L+ H$ K** Input - Frame Sync, Clock and Serializer Rx) m% A4 z" _0 Z) ^
** Output - Serializer Tx is connected to the input of the codec
% m4 T" }8 @3 @*/ j/ ~- v, n1 E8 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 J- e- G6 T* Q9 F1 |; |7 w8 Z7 L1 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) C6 l% h* V; h8 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' e8 b: x, G. }% B0 u5 s| MCASP_PIN_ACLKX
5 U% Y7 \9 U* K+ N& u| MCASP_PIN_AHCLKX! M& J$ |# k3 z$ t9 J6 {
| MCASP_PIN_AXR(MCASP_XSER_RX));
/* Enable error interrupts for McASP */3 n$ C% C5 h, T& ?' s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, J2 k( l& a% c4 N9 H5 p; p| MCASP_TX_CLKFAIL * t2 x, n" S, v3 d) _& _& k7 \
| MCASP_TX_SYNCERROR0 X4 R1 \5 ? k) g
| MCASP_TX_UNDERRUN);
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 k% M9 L: G- D1 G r: o, l' [/ g2 S
| MCASP_RX_CLKFAIL/ P! r: `) S. |: |3 A
| MCASP_RX_SYNCERROR
3 p0 M7 z( j7 r k* r| MCASP_RX_OVERRUN);1 t2 d0 y: [+ p7 r5 w! P! \' ^* [8 J
}
static void I2SDataTxRxActivate(void)1 T: Z5 a8 B4 x: b* y& Y( U, ?/ X
{
l Q) }; ~, N5 i) ^. D/* Start the clocks */' \: m3 g% {# C8 `; G) |3 O% o) j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 ^" M+ Z& z M9 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);
/* Enable EDMA for the transfer */
/ z% p9 |7 R# D' a& FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% E% S- n1 m0 M/ {5 mEDMA3_TRIG_MODE_EVENT);3 w' n( F5 X0 L- k+ b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( G) c% b: e, p% T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/* Activate the serializers */
, \4 j& w- ^+ @1 [, w+ a# XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 t0 ~4 q; m( c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
/* make sure that the XDATA bit is cleared to zero */
& m: A/ U; X5 |9 M( ]/ ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/* Activate the state machines */: }( W- N; e6 v: D9 x" N3 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* X- @6 i9 V( P. i1 }$ y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: g4 i; P- w- R+ n3 ]
}
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请问:问题出在哪了,时钟按照这样配是否有错。
另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
, \$ s' \7 m5 f* _
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