JTAG无法连接

foxpro · 发表于 2017-3-29 14:31:14

本人用开发板，JTAG可以连接；使用自制底板+核心板，JTAG无法连接。。。

请创龙和大师帮忙诊断下，可能是什么问题？

1、本人按照“TL665X-ASY-B4.PDF”设计的底板，核心板使用TMS320C6655；
2、JTAG口使用每个脚单独给高和低电平的方法测试了，DSP_TCK,DSP_TDI,DSP_TDO,DSP_TMS,DSP_TRST#,DSP_EMU_0,DSP_EMU_1
都能变高或变低，说明TXS0108EPWR正常没坏，但是DSP_TRST#是1.3V不是1.8V，其它几个信号都是1.8V或0V
3、Boot Configuration :no boot,即DSP_GPIO_01、DSP_GPIO_03、DSP_GPIO_05、DSP_GPIO_012、DSP_GPIO_015都是0V
4、上电后，核心板红色LED灯长亮，红色LED灯旁的绿灯闪烁

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

C:\Users\Lh\AppData\Local\.TI\4084209646\
0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'bh560v2u.out'.
Loaded FPGA Image: D:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
The library build date was 'Aug 19 2013'.
The library build time was '22:41:20'.
The library package version is '5.1.229.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '8' (0x00000008).
The cable+pod has a capability number of '7423' (0x00001cff).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class second-generation-560 cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use falling-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '2' (0x0002).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.
Loaded FPGA Image: D:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

An error occurred while hard opening the controller.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.

[End]