我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 S: p6 k; o" w# V% }# x+ Xinput mcasp_ahclkx,$ R1 F- b7 \5 J. {3 `, D
input mcasp_aclkx,, g6 A" R6 ~) H+ h& H+ {
input axr0,
+ E" Y) S1 Y+ H! v6 `) e& f$ z2 g
output mcasp_afsr,
) `! A9 K/ r, |: |1 A6 V8 N& [; Goutput mcasp_ahclkr,/ |! l7 K1 [7 e- W# C. s7 A
output mcasp_aclkr,( f. j0 f# X5 W- X2 L
output axr1,& B$ y5 O& \& p \1 m, u
assign mcasp_afsr = mcasp_afsx;
$ Z A9 d% A+ Z# ?5 aassign mcasp_aclkr = mcasp_aclkx;- A/ S/ J) D3 a0 J: D( N
assign mcasp_ahclkr = mcasp_ahclkx;
+ V! C! y0 E- ]- Fassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " u( F- f+ x' o4 V) U
static void McASPI2SConfigure(void)* _9 s, T5 \ T! A- L
{
! U# Y. G! u) z2 T8 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 P8 N7 c6 O6 u5 R @7 w" F6 `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 s! @; y1 Z& k, {! C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& Z. |5 d* n! \% l. m- `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# V3 r9 N; U3 ~" y) E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ A( {5 ~( C7 ~ H# vMCASP_RX_MODE_DMA);% o6 o# Y, h4 w0 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 w4 P; x" C/ W0 X2 I9 Z) ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 L$ T3 [1 a2 t0 b" }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 @9 f5 {* ?6 w$ U. v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, C3 L+ k7 E; i) ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / I% [! m% d3 E& V# b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 K) u' ^1 V+ d/ f7 q$ IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ |+ ?3 y, _$ o5 t! `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / N( d$ ^# ^$ ^3 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 `$ f' W0 e" [
0x00, 0xFF); /* configure the clock for transmitter */
8 c# m2 a5 `9 b) S9 R9 b0 g1 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( j# L! b% V& w! I& T: c& d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 T( P# }# O; t1 |' _4 Y2 h' HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 Z z3 t' S, {8 d9 K& u5 c0x00, 0xFF);$ `' l5 I3 i: c& j- i
0 t" {' A8 Q$ @; n, k/* Enable synchronization of RX and TX sections */
' x7 T+ w# ~9 v L! U2 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- i( T1 f( b, s/ `+ \# [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" Z' n6 q% P( r* r4 P# u0 a2 E# uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) s0 J/ }7 ?$ k- K3 L
** Set the serializers, Currently only one serializer is set as1 W; ~' j; j4 \2 z+ y# c: @* g
** transmitter and one serializer as receiver.* c7 j l- r) w
*/: k* p3 H, N4 U( y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" F1 c- ^! d( h N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) y% R4 ]+ {" q& c1 M
** Configure the McASP pins
: }* e- J( U% [9 d- H( I, r** Input - Frame Sync, Clock and Serializer Rx
% N& f* _( e$ `) R: V4 ]** Output - Serializer Tx is connected to the input of the codec 7 K) v) b2 b' @
*/! W' ~1 u4 y! t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 ?3 W# K* ~% Q: t% WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ l0 s1 I# y, f9 C2 l$ e+ A8 |/ {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% y! V7 F8 A5 w g& }| MCASP_PIN_ACLKX/ _( D: F0 Q- O) H
| MCASP_PIN_AHCLKX
v! q" ]4 G5 u9 l1 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* e* C9 c# x& q W1 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( U" z3 ~+ E% G9 l; s$ ]
| MCASP_TX_CLKFAIL $ W" ]; B' \3 r1 ?& S" K
| MCASP_TX_SYNCERROR9 S' P0 Z2 I4 H+ [3 ]. R+ U" g% ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. }1 \: w* _( A9 o$ t# U| MCASP_RX_CLKFAIL
" }2 d- ~! L" W/ T! U$ |9 L7 A| MCASP_RX_SYNCERROR
! z% S% w4 h+ r4 V8 }5 m0 m| MCASP_RX_OVERRUN);
+ y% Z2 H# z+ x* F) _1 L} static void I2SDataTxRxActivate(void)0 Y- Y; r' s/ N! [- e$ I2 m2 k+ R
{8 P4 ^% _/ A, _- N% V
/* Start the clocks */6 y& ^, p" ^+ U/ T6 _7 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; x/ r* \- j \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 S @/ Q6 I8 Y8 M8 N# C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, {4 q$ S% S/ `1 |3 M: {4 S
EDMA3_TRIG_MODE_EVENT);7 j3 c! n. t* _" B9 P* d9 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 E) f5 ^, n/ j# a, I7 R2 f1 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* D, Y2 }3 Y. m; dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 Z! j; D8 {) U: u: E6 i U: T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 b! m3 ?, Z' ]2 N9 G( o( owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; R( W) m) f5 j* p$ Z- V$ p( `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ b* D" g: x6 l6 ^( s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 ~" G- Y0 G. o6 E! E' u! M y} $ t0 H: M& D7 B3 A; k0 j+ j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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