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C6747和C6748感觉差不多,我想实现McASP发送中断方式控制音频信号,在轮询的例程基础上改的,轮询程序可以实现,但是中断一直实现不了,也找不到错误,求大神帮忙!下边是主要程序:: @0 ^! M8 n) K
main文件:
, F* ]# R ]" s2 h( Q. O: Ninterrupt void interrupt4(void)
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Uint32 sample;
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+ u, }+ s( w+ J4 U+ R sample = input_sample(); // read L + R samples from ADC# H) g* B6 N% _0 m- u
output_sample(sample); // write L + R samples to DAC
; y; W6 d& y7 X) V4 e+ `# ^ return;
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int main( void ) ~: v4 a( y$ K6 l0 k8 y
{
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/* Initialize BSL *// U* S" b' h( B; C% _; x
EVMC6747_init( ); y6 `! q$ H4 G8 V
/* Call evmc6747_intr function */
" x' q7 t4 D1 L `: B aic3106_init( );: o( F2 w2 K# a I. D1 @
while(1);
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, U! n- G# R; d( }7 Waic3106_init文件的一部分,McASP配置部分,采用内部时钟,I2S方式,同步传输。音频芯片的配置应该没问题: ~% _2 r, U3 M4 }& z
/* Initialize MCASP1 */
2 |" H+ r. [& w, _' z1 X3 \ mcasp = &MCASP_MODULE_1;/ ]9 N/ Z3 h' |. v. m1 }# v0 E
mcasp->regs->GBLCTL = 0; // Reset4 b4 _+ N f- L; Z+ a) n$ ~( d
mcasp->regs->RGBLCTL = 0; // Reset RX1 I* ]# @2 X w; Y$ ^
mcasp->regs->XGBLCTL = 0; // Reset TX i. r8 f* j7 i4 l/ |8 x5 H+ t
mcasp->regs->PWRDEMU = 1; // Free-running6 K1 Y2 V7 u1 z/ _, E8 l
// configure McASP0 receive registers0 {, k1 P# V; {, M! z2 j
mcasp->regs->RMASK = 0xFFFFFFFF; // No padding used
?; n& O4 m4 G6 o mcasp->regs->RFMT = 0x00018078; // MSB 16bit, 0-delay, no pad, CFGBus+ ]; d& _! O7 i. V* k0 @6 U' ^! E
mcasp->regs->AFSRCTL = 0x00000112; // 2TDM, 1bit Falling, External FS, word: }& W+ \* O# C& B0 [7 E
mcasp->regs->ACLKRCTL = 0x000000AF; // Rising INTERNAL CLK,(from tx side)( |- a8 A8 U. `0 I* O
mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)
) q2 J$ s: s% `0 i mcasp->regs->RTDM = 0x00000003; // Slots 0,1
( J( m h2 O+ d3 R1 O; I9 U mcasp->regs->RINTCTL = 0x00000000; // Not used
$ Y+ X" W% o: q; v6 l( s: L mcasp->regs->RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-2564 f9 V# q6 H4 Q
" t3 `% \$ S# T9 Q( C4 @/ S" } mcasp->regs->XMASK = 0xFFFFFFFF; // No padding used6 I# N' i" a' V
mcasp->regs->XFMT = 0x00018078; // MSB 16bit, 0-delay, no pad, CFGBus( I: M- K( f; O1 P0 q; z
mcasp->regs->AFSXCTL = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
# L- D5 a4 }1 ?" j mcasp->regs->ACLKXCTL = 0x000000AF; // ASYNC, Rising INTERNAL CLK, div-by-16
; k' m& |& F5 c! m& Y mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK
# ?' W; u8 s9 B* R" L/ ]& L mcasp->regs->XTDM = 0x00000003; // Slots 0,1
' o, g- [ q9 O4 }5 M; p8 j, z mcasp->regs->XINTCTL = 0x00000020; // interrupt on transmit8 a" Z- S' m. z( q' m' @
mcasp->regs->XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
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mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN
: {0 U6 i; C5 o mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT
* j9 b# a( f8 g2 y mcasp->regs->PFUNC = 0; // All MCASPs) X. e* Z: h) M. L' }
mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1
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( o. G1 C. u4 d mcasp->regs->DITCTL = 0x00000000; // Not used
: p# p3 c6 G$ a8 n9 f mcasp->regs->DLBCTL = 0x00000000; // Not used, A3 o# W3 e3 |
mcasp->regs->AMUTE = 0x00000000; // Not used1 U a( `" d9 E3 y/ |6 ~9 d
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/* Starting sections of the McASP*/' h7 Y( a8 X2 c7 H" U$ {) O
mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON;
* S% ]1 r) l3 V1 J while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
5 s" k# J# p; R! c- s" ^ mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON;
/ U2 g3 m" v* Y9 ~. ` while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
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( N, q; D1 Z$ Z+ H1 b; y mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; 2 U5 c7 D6 p) o5 X* R: O% d1 c0 c4 _
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );% _$ Q' z. |0 _3 P: ^
mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON;
' @8 y4 O) ^/ ^1 A* ^3 U3 q+ q% } j: C while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
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9 U1 s$ `% H% `$ p mcasp->regs->XSTAT = 0x0000ffff;
1 k! J5 d/ U# G, V3 a mcasp->regs->RSTAT = 0x0000ffff;
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6 f' o8 Y5 T' j0 ?7 @- O mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON;' M; B1 O8 w: l" E9 p, T
while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );. ]# D. q# D2 w- H9 ^
mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; ; k, ^% i# A6 a' ^. ?: j
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
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/* Write a 0, so that no underrun occurs after releasing the state machine */. o; t8 Y n; F: D
mcasp->regs->XBUF5 = 0;
5 J$ g1 K6 G6 d2 S mcasp->regs->RBUF0 = 0;
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& g. p3 O4 D0 r' K! E0 y s" a mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON;
* C$ y" X, l( s while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
4 P6 k, C* R4 t$ s# [ mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; ) D- y) i' e4 w+ M% e: s
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );1 _+ l$ r3 U7 v5 r+ c1 N2 C. v. Z
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mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON;
$ S5 Q/ d" E8 k5 Q0 Y( @ while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
; b* A5 b" P V: {5 F3 t mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; / L8 i' b: ^8 G! [
while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );! Y# W3 h% K7 p7 l* Z) o
6 g! F- f5 J2 H6 ~/ P( @8 Y CSR = 0x0000;, N' j9 D' a, b% A& H% E2 D
INTC_INTMUX1 = 0x3d;
# X( L1 n( E9 O c$ r, L ISTP = (unsigned int)vectors;
" w3 \/ r, s% ~& w1 j ICR = 0xFFF0; % P8 ^2 X O! ^4 J2 ]) y8 Y
IER |= 0x12;
2 r7 a. W( s9 U6 U$ `6 S CSR |= 0x01; % n% W2 y* k% Z4 ^+ n" W5 ~& Q
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/ w; g1 G6 K, k/ L还有就是两个输入输出函数:
& q8 W: S" o; y2 j6 Fvoid output_sample(Int32 out_data); Y0 O* z6 j$ i, c2 U/ S" q
{
. @9 h3 X0 g; a/ w% C AIC31_data.uint = out_data;
7 F) r& X. S( W8 V6 M7 H0 F MCASP1_XBUF5_32BIT = AIC31_data.uint;1 q% b( H* x+ i- a
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Int32 input_sample(void) Q. x9 b( O5 w+ N* \
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AIC31_data.uint = MCASP1_RBUF0_32BIT;
0 l7 V( B9 x1 ]8 M6 } return (AIC31_data.uint);3 v5 W7 [0 d# c( R( L
}
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