我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," ^! \$ C9 ]! `, G
input mcasp_ahclkx,8 l% v: H5 w" o' w9 l6 l
input mcasp_aclkx,5 q$ F. Y- p) _. l+ V
input axr0,
' ^& m" f; ]. R2 c3 v; m
1 D; M6 y4 w: T @3 zoutput mcasp_afsr,! H8 ^: ~0 M p- t# u
output mcasp_ahclkr,
% i2 O0 j9 C3 Z r; Ioutput mcasp_aclkr,
: y$ ^: M5 v0 [% ]2 I0 Loutput axr1,
0 O' d; F" Q5 Y& y* T' q9 t assign mcasp_afsr = mcasp_afsx;/ N$ [% p9 C; W) V P6 O
assign mcasp_aclkr = mcasp_aclkx;
* h+ B% Y9 G2 I& f& [; gassign mcasp_ahclkr = mcasp_ahclkx;
9 D) ~7 U/ D% T6 T) W) A& bassign axr1 = axr0;
/ j; a+ P: ~0 [$ X0 w; y* U1 A R' v! o% o1 A% g! R/ U9 J I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - k; v4 g! M+ T2 l. j; R: f
static void McASPI2SConfigure(void)
1 r4 o, P4 s& X( c2 S) K7 v1 G{% k) z0 @- {6 J4 d- \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; k2 n* O3 k% r) @" o7 f) y- Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 l4 u. ^2 {9 G0 n5 u* z8 b/ hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 s: T- U: R+ x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 f2 P. f# y( t! F: Z6 k% ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' {; [, \% T% ?/ `. O) s
MCASP_RX_MODE_DMA);
0 k$ S3 I+ a' a, t" f' E, @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 d+ z) Q- g- B' y8 ~+ c- J3 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 T, N5 Z. \' M% {8 w1 c/ [( EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, j) c6 ^/ [) _6 m7 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 h7 h% j: u: {& E* bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& F5 N" F6 j6 A2 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 y4 [ ^6 Z I& N8 R' J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. K4 ]* l% i. l& J/ i" Z* E$ ]/ M& u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* e+ s# K0 E2 b1 P' pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. b7 I& ]7 I( Z. \, M
0x00, 0xFF); /* configure the clock for transmitter */' O: p! r, U! D+ S9 I! c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; y F" ~- r" N& e! \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) S5 p# [& h$ P& H$ U5 L' ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* t8 M* ]: v6 F8 a, f2 K
0x00, 0xFF);( p( F# l, I3 _7 |( t" m/ t
3 u. h6 b" [7 ^: }4 s6 S/* Enable synchronization of RX and TX sections */ . J- V" P. V6 t& }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( a' M1 y: S8 D, I. Q1 P7 YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 p0 n7 h+ Q2 [( M) K, c- o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 \1 ?1 O; f; M* w** Set the serializers, Currently only one serializer is set as
/ m" e6 a2 i& L: o# V** transmitter and one serializer as receiver.
$ S8 ^- o8 y4 w6 @! F! w8 |- L*/
5 F& p+ f! q3 E; cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; @$ Y# i4 _8 K6 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* R% d* O, w, i; i, z** Configure the McASP pins
" w e T) W* n** Input - Frame Sync, Clock and Serializer Rx7 T- }4 j7 O$ p! ~. ]
** Output - Serializer Tx is connected to the input of the codec H0 {6 k( R1 h! a8 u& Y! I. I( U l
*/
, F+ o+ x6 S4 |$ O7 f& m- N/ X& zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, U( U- y: K2 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 ~. L4 }: \( J, g& k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 T( D- K7 u5 X$ ^7 q
| MCASP_PIN_ACLKX
) I- d! }1 I l: ]* r| MCASP_PIN_AHCLKX3 d" l8 y, N; ?" Z/ t Y, Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* r0 y) l; g* l2 H8 e [4 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 b9 {- C- d( I& T, ~| MCASP_TX_CLKFAIL 4 ^6 L+ a0 r4 T4 G+ Y; L, }( Z
| MCASP_TX_SYNCERROR
+ w" m# S4 e( k) _4 c/ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 e/ {% S: \$ u+ _| MCASP_RX_CLKFAIL$ ^3 S0 a. V' F* {( Q2 R
| MCASP_RX_SYNCERROR
9 D" c2 j# r+ c3 D4 `: M| MCASP_RX_OVERRUN);- I+ [! I" w! V' N3 d3 w/ o
} static void I2SDataTxRxActivate(void)
9 U5 d- U% v/ }% }1 A4 M{0 T! N# p0 M/ T* @( H1 j
/* Start the clocks */
1 y/ T, v! \' {/ M7 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( L5 t5 [% {; d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 W; m, ?: W1 ~9 n m6 J2 t* DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, S7 k7 e$ U. `: ^EDMA3_TRIG_MODE_EVENT);
$ f7 E6 G3 q! Z" ]( \3 J/ g+ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ M- g n; E& g- f3 v3 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// k b) X( l; o& y7 s8 g( c3 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ d: G/ L( Z2 k8 ]9 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
x& u3 F, w4 [3 ?4 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' a" H2 T4 ^: R7 Q2 D9 G; Y# K- Y0 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* r: S* K% P$ Y2 R0 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& `2 Z; Y) u7 s: r
}
+ Y+ s: \9 `8 T" f8 A% E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. H3 e; n, p% S# F: n ]
|