我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ c9 C, U) I, Y* H J) tinput mcasp_ahclkx,2 G8 a/ L4 F1 Y* B Z
input mcasp_aclkx,
. N3 o9 x) @6 r# |input axr0,
" J# M$ s; ]" u& E2 j/ F8 J J3 u
" F7 I) ?2 t! d# T3 E6 C# m9 boutput mcasp_afsr,
3 C! O. R; N, J" |) Qoutput mcasp_ahclkr,8 W: E2 R5 {: g" L6 W+ a1 a4 Q
output mcasp_aclkr,
' k, t; n) V. u! s+ Y" _output axr1,8 E) X n; E) D% Y! M
assign mcasp_afsr = mcasp_afsx;
1 {0 M; M) X$ Z& U) P Dassign mcasp_aclkr = mcasp_aclkx;! M; q& p) r3 H* d- }) o
assign mcasp_ahclkr = mcasp_ahclkx;
1 T$ |! S$ Y8 _( O) uassign axr1 = axr0;
7 v) _% q5 s+ f: E9 O: j7 f- A. w ?/ a8 U3 W- Z7 o( Z# {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 I% A: _% P- W, B
static void McASPI2SConfigure(void)
# a( g h, d r% ~- W9 L; T- P- m{% s) V) G8 W7 [4 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 {/ n# R, m- M+ J$ t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 Z) u% T! s# k6 b* M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! @ W$ I8 P1 ^; U$ f; ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ w6 I0 z9 { \! S, z' ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 h/ {4 R) B" KMCASP_RX_MODE_DMA);& `( m2 G* ~- N1 `, y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 W+ N, m: y5 }/ g* I& D/ }( }, _! j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! R0 h+ |/ p7 Y+ S! n) SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' f( o0 ?7 x6 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
@% e. s# P: X/ q- s5 [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
d. T3 R2 U+ v/ L* A( x z' g! eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 T1 }" m2 q6 {( }+ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ ^1 A j% I2 H* Y9 l- D# V% g' f+ uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + V. \. E* ?/ [& B( b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 f% H+ r# A! P! {0 t! g8 Q, J0x00, 0xFF); /* configure the clock for transmitter */
! J' X) z. F; `7 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) v, \* A) h, K% a0 [8 j- tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 |' ]+ J+ D) V" ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 D; N4 D) K7 u4 {6 \
0x00, 0xFF);% `3 }7 c5 T. R0 R }# v
& R( ~ E3 }0 [. |! o, k- h$ q; P
/* Enable synchronization of RX and TX sections */ . G0 p0 ^3 N o7 Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) Q* F) D( A( B3 m8 z5 z+ H( c \* [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( N4 a6 [; d3 u8 o& a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ B- M1 O# F+ D** Set the serializers, Currently only one serializer is set as
4 N' g# _8 h0 d) t9 Q& ~- }7 E** transmitter and one serializer as receiver. O( [8 ?+ n; Z, V7 x
*/
0 ?% P% {7 |& n) L9 y# C/ k' |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 L2 @% r* x7 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, O' e0 i/ G1 O- C6 m- u1 V
** Configure the McASP pins % Q" x% k$ ^- w6 ~6 J
** Input - Frame Sync, Clock and Serializer Rx
- F. m# C/ d2 B" ]9 L, W** Output - Serializer Tx is connected to the input of the codec S0 J+ b5 I. y$ f7 ?7 M) }9 {
*/- t+ C& G7 a" K+ d. _5 Q; M; j4 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% A; i% a" x# E, hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 M6 ]/ ^# L" k& }$ G- R2 O( m! sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX O1 {8 h; k z) X
| MCASP_PIN_ACLKX" _% G5 @" D: T. a' ?% _
| MCASP_PIN_AHCLKX
& Q+ X& E) Q. i0 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 a' ]0 C2 n! K' D: G8 |1 g4 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* d# a+ M4 _( f: y2 w6 k| MCASP_TX_CLKFAIL , z, m% ?; t6 {: L8 u# C
| MCASP_TX_SYNCERROR
, E+ |2 J- ]0 }7 k4 Z' G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " R0 q# P5 q V* O% U$ x
| MCASP_RX_CLKFAIL
' z! s6 Y7 @! ?' o| MCASP_RX_SYNCERROR
8 y( P8 }& Z9 j% X% m| MCASP_RX_OVERRUN);
$ `" v6 q5 {% y0 A# y( U6 N} static void I2SDataTxRxActivate(void)
- v+ U1 _: W. z: w x{
' c7 _3 e, C$ E" G/* Start the clocks */
! p3 v) \. e& z2 \! @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ z: ?$ w. S/ u; a" ?/ m$ wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 P. S0 k: ?: |: U, x( U' k- VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ I6 a: C- c/ b CEDMA3_TRIG_MODE_EVENT);! _2 x& y0 [0 t5 v; b. K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 B: O9 E! Q1 x$ w- }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 T$ x5 `8 [. y/ |( A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 E( S) X/ F" t! O: X0 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) Y% N( l& b& H3 S+ ~! ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ ^ m0 T" Y, y- S0 v$ _6 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ l8 O- ?& D; |, D- q6 \2 l! z6 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& e. x9 A; x% `" T: X& ~
} " R6 V# k. { C# U M8 o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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