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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# ^: q3 f4 s9 Qinput mcasp_ahclkx,6 ~0 e3 ]5 u. L' G4 t
input mcasp_aclkx,
3 U) \$ \9 T/ B5 l2 w' z; ?input axr0,2 e# R) X$ W/ S3 P+ o
5 c; f. m+ `( V: e! F! ~output mcasp_afsr,+ j. V1 D* s% j; X
output mcasp_ahclkr,
# K6 `: z( u5 X+ {) |output mcasp_aclkr,: t/ c! \( A4 r4 y9 T8 _! Z) v
output axr1,9 D8 q9 }6 A' p6 \
assign mcasp_afsr = mcasp_afsx;
! `. `/ g3 q3 q# `% [2 ?/ F1 aassign mcasp_aclkr = mcasp_aclkx;
1 P. Q$ |4 S% T; _assign mcasp_ahclkr = mcasp_ahclkx;3 i8 Z! a! o6 n+ D- R
assign axr1 = axr0; 5 ^, Y5 B7 D* m( ~& T0 s* ~; |! S
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; o8 `* ?1 z$ q7 p! P/ z
static void McASPI2SConfigure(void)
. k9 ?" B! \: T{
- s5 \# ?" x1 ]9 L7 [7 Q) AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 k: i2 x+ ^( e% `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 n* v7 S6 z+ L# v( xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! J* s2 z) I' Q0 T1 B- v0 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 ]; b7 G. d1 S' ]$ j: b+ @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 g8 j) l- b1 v8 d8 D
MCASP_RX_MODE_DMA);+ U- r7 L$ u8 _- }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 u: k% u' f! k0 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 @* z' `! T4 @" F/ |/ n8 F ^" OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 U+ u B, U. r+ O/ Y: PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); z- L* n0 `) j6 u, `# }$ c7 @% p& U H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) v$ K* H$ l( O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 {% j( J0 w1 D, O. }6 X/ ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( ^( ^8 X! z9 Y0 P! z- zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + b- N# I: W5 D0 L* R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' w$ R8 y0 S& I: U% Q% ?& }2 V: u3 R
0x00, 0xFF); /* configure the clock for transmitter */7 \. w1 u8 G' j3 Z, o# y1 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- r* V8 ^. R$ H& R: VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* R7 j0 O O* Y' i3 u6 h2 D+ EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' S9 n) f& B( w0x00, 0xFF);
) O. B; P/ E" Q* |" i' s# Q# y' O1 E* c" Z6 S, C
/* Enable synchronization of RX and TX sections */
" z3 t& b6 t5 H! ^+ V; D' `, S3 X7 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 u0 a* R O& x7 S* B! N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! o' `- A' x( ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: J$ `& q2 M+ A8 Z
** Set the serializers, Currently only one serializer is set as
- u/ l. a* V9 ~5 s& J** transmitter and one serializer as receiver.
6 h7 `" d9 l( Y$ J8 h*/
& v8 c! u4 ^2 q' @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ E8 }% f. G/ L3 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) \6 {$ m% D8 Z" v. u** Configure the McASP pins 7 f( s/ q2 c" ^
** Input - Frame Sync, Clock and Serializer Rx, r- @. |7 Y( w4 R1 c+ R$ {2 Z& c
** Output - Serializer Tx is connected to the input of the codec # b2 Q4 L. E6 w3 c
*/8 N/ B- q3 e# O+ h* t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% v+ x% {1 Z) T* A; s; X$ R" o2 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, w' D2 Q$ ^% l* D/ r, k' F; Z# u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ D$ z- z8 R" O- q4 u {
| MCASP_PIN_ACLKX
' `( t s. l1 d3 ~' I9 ^5 J: i| MCASP_PIN_AHCLKX$ k! A+ Y4 v' g5 l- W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 [& g) U: G! D- MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 T4 {2 M" E: ]( ? l( a( [) H7 C5 V: _
| MCASP_TX_CLKFAIL
. I4 P7 r; k5 f" t0 S| MCASP_TX_SYNCERROR
6 s" H5 D% |9 K* j% H+ W3 m( l9 X M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! p( ~, T! P. P- |; D| MCASP_RX_CLKFAIL
. E& p9 f F* w$ ?8 P6 t' y| MCASP_RX_SYNCERROR
; R" a7 P; p4 o6 I8 j| MCASP_RX_OVERRUN);; ?, x6 S9 _ ?6 b
} static void I2SDataTxRxActivate(void)+ H% Z! x7 w0 g1 x" ?; n2 _* s
{3 a. x% f6 ^8 d! y9 `
/* Start the clocks */7 A7 F3 Y) [, G" R3 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 C+ ^! D4 G* }0 {, r" Q7 gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 M- t- ~' L8 _* x" r/ l! iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& Z* R4 T$ s5 K, H& m3 C
EDMA3_TRIG_MODE_EVENT);! H9 D, R9 _9 }2 W- g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 \5 ?/ t0 P8 e, ^; B% nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. l0 }' V3 C( _+ u6 a/ h4 N, a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ g- r& ~3 M2 w. q4 z5 g, o3 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 ]& Q; \; i+ H8 Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 G% ?2 V5 \4 }5 H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- c8 o+ J8 c' _4 a+ U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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