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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% z- C1 ]/ }# R q1 V$ t9 j$ K
input mcasp_ahclkx,8 G+ P/ s! o8 D4 c4 q7 h; B
input mcasp_aclkx,
+ O" e# c0 M/ ~- a: D& v* o* g# sinput axr0,
+ ^+ }( @1 b, [$ ?$ t g: s- _* V7 r
output mcasp_afsr,6 M) Y: n& ~$ |* N: F; t5 y
output mcasp_ahclkr,
3 r5 a8 k" ^3 J' Eoutput mcasp_aclkr,
6 p: C3 Z/ u# g1 J+ A0 Woutput axr1,' D9 t. R+ A8 v& c5 ]* T! j
assign mcasp_afsr = mcasp_afsx;
+ n: G' \1 i& k! P6 T! c {* G; Dassign mcasp_aclkr = mcasp_aclkx;! X9 C! g* P" a! c; ]
assign mcasp_ahclkr = mcasp_ahclkx;( O2 h, J: k* o0 B
assign axr1 = axr0; 5 z* s; f+ ]* P0 H, l4 ^) V; S4 H
! N: V1 [" g6 [; z" A! `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 @% f1 N% \8 _& R
static void McASPI2SConfigure(void)+ u, w( t' q" E
{
4 M& w: d0 n: A; R: y0 d' `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- C; R9 |3 x3 o1 |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# I* h2 r- o: q8 ~( g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 k6 W9 Q# Y+ g7 I, j; xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 j; A! X" m% f0 b v! G% h# [. ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 [+ M( T7 ~* M+ a' m
MCASP_RX_MODE_DMA);0 D1 z V* f6 q1 |1 b' B) {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! W) `& g. t0 x8 B6 C6 Y& SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! a% z5 Z4 y: `, A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* |" z1 m0 F; D0 rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 s8 l2 @; F/ Q1 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 \& l6 o: z0 t& mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 A' x2 \4 [/ F$ r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. o$ n8 b. G. YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; o8 X* U6 F7 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 S, t) U+ C- \
0x00, 0xFF); /* configure the clock for transmitter */4 U) H# M! F7 H- I5 ^0 p _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% |/ R i5 }% {; HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" B$ S1 q+ u+ B3 P- l, EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 J2 m- F7 K" F/ X
0x00, 0xFF);
5 \' c" E6 z2 @& w4 u! g! k9 v8 @& G! m/ P
/* Enable synchronization of RX and TX sections */ ( S7 Z3 l v5 j* I* u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- f( O! J- ]9 Z. h8 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ v+ i7 ^- C1 u2 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ^3 n" t/ l: u2 D9 F+ J" v
** Set the serializers, Currently only one serializer is set as
) u0 P! G+ ]6 B3 J** transmitter and one serializer as receiver.% u, m. t4 f& `* K6 a! v1 a: ?& N5 R
*/1 O: y( d6 H* A0 F( ~3 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) L2 s/ e- r$ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( {& N# I. j- Y$ C( n" N** Configure the McASP pins
% Z/ l% K# ]: R# l* p) d9 K1 M** Input - Frame Sync, Clock and Serializer Rx
Z% R1 s8 {) T" ?** Output - Serializer Tx is connected to the input of the codec
3 {- n+ f6 u% k. t0 S0 \*/, r" j! t8 z! x% e. R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# F; x) b) I) |2 r" Q# Q& YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 g3 t0 I2 `: E$ K% M7 N5 {* EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 k. P |7 K$ k. ^| MCASP_PIN_ACLKX/ ^. E; n, O- H6 ]# K& h: b5 r# V
| MCASP_PIN_AHCLKX+ o* t2 T7 W# m' L( L- k: ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// W" u2 k0 m/ h0 X4 g" A: f6 @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, @" I+ U; \* J* e8 a2 h- J* F| MCASP_TX_CLKFAIL
5 Y6 C1 X8 s( ]9 D- n, g5 Q| MCASP_TX_SYNCERROR4 M2 e" `/ t, [9 F$ E9 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ K j4 J1 n+ Q, Z: u6 d+ B| MCASP_RX_CLKFAIL9 Q! G, A. _2 d; Z; E% M- O) d
| MCASP_RX_SYNCERROR - b ]( t7 F' p2 k: q
| MCASP_RX_OVERRUN);7 F/ W3 f; e4 u( F' w3 `8 A
} static void I2SDataTxRxActivate(void): L/ O" v4 Q- G) s( n9 w! C
{( L8 D1 |. A6 P
/* Start the clocks */ u5 n |, o) Z# U% j4 ~; k2 `/ g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 k) g8 k i/ L- b2 o- u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" O+ b4 w# v# n' u8 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, U, ], `' r' J2 iEDMA3_TRIG_MODE_EVENT);
2 e' b( H+ O5 @# y' D5 {, O1 J4 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! L( m2 C! G/ {1 w" Z, w- DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! p! c- G- O, A! W7 X& hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# M! O' ?; Z, }; G6 K. r3 K8 I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 H7 b6 y2 F3 M: S) f3 M8 K8 lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' R& c! M# ~% A1 F) l6 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ L: r) }! L" W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 t- T' t8 ?; C% O% i H w
}
* f3 b6 s% U8 n! d2 Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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