我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% w5 D" M4 r4 y( y) Q6 @: ?input mcasp_ahclkx,
0 s& h& k3 X L( [0 q H4 D+ l: {input mcasp_aclkx,& t$ L7 @9 e: T
input axr0,, S' ?8 Z$ W( c: |3 m2 A
! Y2 b7 _& ]0 y1 g' } C! i* Y
output mcasp_afsr,
6 `6 h. U- S! M$ Q6 P, @output mcasp_ahclkr,) O: ?" e d3 w( \ ?/ F
output mcasp_aclkr,2 W% N0 x1 {& A p1 e9 U
output axr1,8 X& R0 `1 Y Q
assign mcasp_afsr = mcasp_afsx;
4 c, V5 R7 p/ }/ K) N2 Vassign mcasp_aclkr = mcasp_aclkx;$ N; @7 ~( m d& o& I" R9 l7 h# Q
assign mcasp_ahclkr = mcasp_ahclkx;
3 i' t2 |" q! `1 E1 Eassign axr1 = axr0; + Z( ~( h* \) h; _: X4 m
# f6 r/ k8 Z' M4 c4 @! F* _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' l3 E9 n9 r' \3 ?+ Y1 u
static void McASPI2SConfigure(void)1 [# G: T' R+ o4 z
{6 X# f% D! G1 \. P& Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. |# M% f& g/ J% l6 P+ ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 q" K) j8 X/ v1 O! r8 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( y! V$ r# {5 n' @1 z9 s3 S: ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, Q# D6 G- Y* e+ x1 a% _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- S U" ?+ O4 e5 V, q) E1 O6 P6 uMCASP_RX_MODE_DMA);
( O) ^2 ?5 p- `5 u* H" ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 P# ~0 L! b' Q% A) d& X8 S5 O' |* ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# S8 _: |: E* \7 c; o- u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * z! G- g; i2 V) R- p5 }. n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ g' G( F5 }8 D1 [1 n+ u E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 r' R3 u. p' G% ~% zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 c0 O0 G1 u4 C7 s( }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- R4 g' z; @7 x# [' _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 m, y" n1 K' i* v: B% ]0 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( J1 L. ]4 Z& ^3 b; c2 ]$ E
0x00, 0xFF); /* configure the clock for transmitter */' {/ g b; B+ n" j9 ~1 h( a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 a) t+ S& j6 ~3 L- w" a& ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % E2 V8 E* D: t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; G4 b0 x0 H# \$ ]6 \. P. E( O. V0x00, 0xFF);
6 o) V1 I6 `/ L( p" E. s8 @. B" g# |7 p
/* Enable synchronization of RX and TX sections */ + n; x/ ~5 d5 B$ }3 K2 J& x5 f# b9 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" y) u9 L- Z+ n# m( i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' H) J3 i1 W8 g# R" E8 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 B( a; U) a8 ]* P8 h1 e** Set the serializers, Currently only one serializer is set as" t8 h1 H; P; n! V% [
** transmitter and one serializer as receiver.' n+ A7 g9 ^0 g
*/" ?4 L2 g i- P; N3 R! D( D# k3 Q/ L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 h% z; A% U9 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: R( m- K. B' [. X3 O5 Z0 y' T** Configure the McASP pins
& B) W7 {5 s. @( l$ o: t** Input - Frame Sync, Clock and Serializer Rx4 k ?7 w' l: f
** Output - Serializer Tx is connected to the input of the codec
, V4 Q7 @- u# g) ~*/
" j, G' L B4 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 Y: V0 W: p' B0 h8 u3 e0 E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# B: A# h$ W3 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX h+ s# q) w% k$ b& L$ y
| MCASP_PIN_ACLKX2 h4 C7 _0 k0 \
| MCASP_PIN_AHCLKX
: h4 C; @. J& P' f& f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ y9 e# `" ~, d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 x& d6 d6 P9 P- R6 S. e% f$ \| MCASP_TX_CLKFAIL
2 D4 @! ~, I* E0 p| MCASP_TX_SYNCERROR
- E- @; l3 r% h2 ]: ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; n. V% G M0 q% j| MCASP_RX_CLKFAIL6 M# k0 i. {9 P' E5 t
| MCASP_RX_SYNCERROR
$ V& H: D: C/ m: j/ F- k1 @7 h| MCASP_RX_OVERRUN);, N- p5 s9 ~' M7 e9 Z+ F( g: U
} static void I2SDataTxRxActivate(void)
4 w3 n# R1 i0 ^1 S6 d5 _: ^( L{* v" p0 }9 j9 R1 B/ y. k! W
/* Start the clocks */
! l/ I/ k0 _; Z1 h) q& R( j) ~* dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% X: M; ~* C, O- M: qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; m( ]2 ~+ |7 j- @1 d* _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, m; V: y' O ^2 y/ _
EDMA3_TRIG_MODE_EVENT);' @ T& y- w ]) z* p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * A" a9 r1 d6 N S) m p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 W, p: Q0 w- d1 C/ \( p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 k+ d _4 ]' @: E2 J' N2 y& lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! s9 R' g( }- k- M# q) N6 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; j- u3 @1 ]9 z6 z" {) ]: t2 D! d6 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* F, ], a1 e4 U8 J* m- x! r8 ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 {# A* C" u k' M
} : D" P& ^" v7 R W$ I+ _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 V& H3 D9 g* V
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