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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 c" e L$ d; |! r& @+ s: U+ J) n
input mcasp_ahclkx,
. q- Z$ W% Z, P; f8 \. n8 qinput mcasp_aclkx,7 Z( q# [* d# `) W/ O7 H
input axr0,
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output mcasp_afsr,# G) v- X6 Y9 F
output mcasp_ahclkr,3 L5 X4 E' d+ t' E; N# I/ Z: d
output mcasp_aclkr,
, \5 m1 i" r; B# L6 C5 Poutput axr1,! T5 M# B- t6 @6 }" w" E8 u+ J n( G
assign mcasp_afsr = mcasp_afsx;% `& a) \/ k" [8 x
assign mcasp_aclkr = mcasp_aclkx;
7 Y" a& y9 L- x2 Q" _+ Hassign mcasp_ahclkr = mcasp_ahclkx;
5 d: Z: [1 S" ^7 ~4 ^! { o1 ~assign axr1 = axr0; 9 S2 Z; D! b2 R/ ]9 Z) O7 {/ x
% {7 t) v7 P* M N8 d& c& j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " p+ G1 B7 V$ r# k
static void McASPI2SConfigure(void)
. p! s; D) O/ S/ j* V{' z. w7 o4 Z/ u& m0 X3 w6 V4 o: B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- y$ X, V9 Z8 R- M Z2 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// `& H" a' y6 x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 K+ o0 V; Q7 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 T, M' \: N- k2 P$ `5 p) EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ?" K9 u6 v) x$ t' G4 I4 c3 `* k
MCASP_RX_MODE_DMA);
# t. n5 S3 P0 `6 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 y3 P. S* E0 z, X% D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 K/ s" r- }! ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % E- `5 S t8 v8 P: f/ V! _5 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& O- F) E. q# p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 u: J# u8 u: G+ l) W. t2 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" ?$ a9 T4 R! iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( y$ }# t3 [* O Y9 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ k' [8 I& J1 C+ P' fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# a, b/ ], b" a6 K* j! r& ^' i
0x00, 0xFF); /* configure the clock for transmitter */
8 w/ K: e& }, h8 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; P0 H4 @& V! I. rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 \% N" E. T( n% bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ _$ k# a3 E/ o# V, d& ]" O5 k0x00, 0xFF);
0 g( _9 _ ^; }7 p! z; k4 V- N: v0 C2 K% D5 k( ?# [& F9 l( O; {
/* Enable synchronization of RX and TX sections */
! c t8 U3 T- ~& O8 {0 `. K# ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
U% F o3 k. Q' O$ G: T- oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* I' q. x" j, g( L. t+ \4 n( D& e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 E& x6 a8 N1 _) G( |- K8 W9 B! t3 s
** Set the serializers, Currently only one serializer is set as5 m; C6 B1 h6 x. @& l2 v
** transmitter and one serializer as receiver.5 E8 Z1 f6 |1 _+ B+ p8 K5 C
*/
8 o. J7 k( C# O/ A: O3 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ Z! r9 Y7 k) EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) @+ G Y; }6 S. C6 A. a** Configure the McASP pins 9 v" T% f6 ~' \" }: I( X
** Input - Frame Sync, Clock and Serializer Rx
! r4 s1 Y& {0 d0 f# |; W! N- w7 X M4 Z** Output - Serializer Tx is connected to the input of the codec
% u; ?/ {* n' G3 y*/8 b; ]* r4 m6 w8 X! Y- N* T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; x1 H3 r m. Z( i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. O5 H$ ]) A, d& B4 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- P s3 q) s; W1 {& K| MCASP_PIN_ACLKX
$ F2 }3 B5 V5 Q. T/ ~| MCASP_PIN_AHCLKX
, k V4 }7 M/ c& s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// u7 v( A( M6 J$ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( M$ Q, r3 B' [/ }* u( a| MCASP_TX_CLKFAIL
) O; S( h! V6 }; [* @| MCASP_TX_SYNCERROR
T4 R: Y7 {7 i* L7 [* N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# O+ |- L/ r# A: X| MCASP_RX_CLKFAIL' K- p4 j, u5 h7 |% O c* t" D
| MCASP_RX_SYNCERROR
! ?# M" E/ K% H+ R1 L9 N, [7 v| MCASP_RX_OVERRUN);9 G& A5 E% z7 R, z9 K) C# G* a) w& P
} static void I2SDataTxRxActivate(void)5 n) t% V3 Y5 m1 W( b* P& l
{
6 ~) k' Y7 z6 {, l7 B6 |, ^! _4 E/* Start the clocks */
0 b+ `2 h: O9 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 F$ X1 h7 O) L( w" F# s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ H7 O; W1 q3 s5 |+ s, R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 Z( F/ [# l4 o3 X1 N2 KEDMA3_TRIG_MODE_EVENT);
2 |3 e" f; w. h) b E IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * a1 Z/ e. J; }4 @0 O4 I7 `7 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 i0 m% ]: i% K" W& Q% d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) L. {3 j2 _* {9 Y H9 A. |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# @. G0 B; |# ], I( U, L1 ?8 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& Q' N( h0 W& s' w# ?" G% WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& T! g3 Q& S+ y( R& TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 r' {6 m+ j" F4 \+ Y}
3 O9 R' P& p7 y, M/ ]6 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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