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The timers support the following features:
' }' K) C; b2 S8 \6 e2 U• Configurable as single 64-bit timer or two 32-bit timers
: b" F. X9 @4 d/ f' U• Period timeouts generate interrupts, DMA events or external pin events
& {) C5 O) W2 s& @& `* Z• 8 32-bit compare registers
/ S( u: g* V7 r H: m• Compare matches generate interrupt events9 s" j: n* z* ?, O5 p
• Capture capability
& k# n( M ?# P5 R) U9 S• 64-bit Watchdog capability (Timer64P1 only)" a) o; C& g; a1 P
! b7 V$ J4 m6 {* V
/*
& u D6 P$ N* G2 ` q * T0_BOT: Timer 0, bottom : Used for clock_event \7 T! W( ]% `4 ~ j" }
* T0_TOP: Timer 0, top : Used for clocksource4 A' G0 M; J e. ~/ X) q: y8 N0 w
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer' e& s, {, s/ i" l- S
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