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The timers support the following features:
: U: N! }# j$ m- R9 T• Configurable as single 64-bit timer or two 32-bit timers' p6 U+ Z; Q! v6 R b
• Period timeouts generate interrupts, DMA events or external pin events
o$ [8 q3 Q9 p% n, H% ?• 8 32-bit compare registers
h6 [/ R8 N3 S4 o• Compare matches generate interrupt events) s! `2 K- Q# ^/ [4 e4 M2 ]- b1 }3 r
• Capture capability1 s4 e$ ~& s) \; F
• 64-bit Watchdog capability (Timer64P1 only)
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/*
( q5 i& M. O! {, C0 z# r# ? * T0_BOT: Timer 0, bottom : Used for clock_event
) P( Q% f: |( g+ S& H2 w8 x7 { * T0_TOP: Timer 0, top : Used for clocksource6 |3 R2 \# w* N+ @* U+ ^
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer" @: a" X* O+ Y
*/ |
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