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The timers support the following features:9 ]+ u6 m+ o8 {9 b
• Configurable as single 64-bit timer or two 32-bit timers4 {( E6 h6 e( h& D- Y. e @" Q. @
• Period timeouts generate interrupts, DMA events or external pin events4 C7 z" t9 G, D+ I; w
• 8 32-bit compare registers
: l. E+ L9 b0 Y3 r• Compare matches generate interrupt events
# m8 U: W. k }( z/ G9 c• Capture capability
( y6 N& g$ `5 n• 64-bit Watchdog capability (Timer64P1 only)! |4 `, N8 n9 n8 @( m4 p" t
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/*
8 X9 a* a N6 ]) c: O * T0_BOT: Timer 0, bottom : Used for clock_event# M$ l9 O% D8 R3 w5 f- s
* T0_TOP: Timer 0, top : Used for clocksource/ y1 G% U6 H5 Z6 y! Y7 r
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
/ { r% W7 n2 Y# U0 I */ |
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