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The timers support the following features:
$ J9 k ~; Q, I2 G! q• Configurable as single 64-bit timer or two 32-bit timers# z- ^- b, {( w& x, _5 J
• Period timeouts generate interrupts, DMA events or external pin events! |0 _- d7 W( [/ W n% Q
• 8 32-bit compare registers
- x# @& \; S" C1 ?5 s& h( k• Compare matches generate interrupt events. W; G# Q4 B" h/ z
• Capture capability
$ @( N9 n# u% j1 @* ]4 W5 R+ Q, y* A1 M: a• 64-bit Watchdog capability (Timer64P1 only)4 \3 C9 ~3 p# R3 X Y7 F* M
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* T0_BOT: Timer 0, bottom : Used for clock_event3 T& E. u( t: e) y9 p5 @- l9 f3 R) f
* T0_TOP: Timer 0, top : Used for clocksource
_2 {) s' [: Y, g X- O * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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