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The timers support the following features:
6 x5 B0 L" R) W) Q• Configurable as single 64-bit timer or two 32-bit timers4 W( k) K a ~( u
• Period timeouts generate interrupts, DMA events or external pin events R5 u7 `: D: {4 c) }# u" \
• 8 32-bit compare registers' D( B& M7 }/ }+ {5 @ D) O
• Compare matches generate interrupt events) k) U2 ~) N9 c; {; p0 Y
• Capture capability
. @0 `6 q" n3 X4 ]. z$ e7 c• 64-bit Watchdog capability (Timer64P1 only)$ [; d. {7 w1 R5 @& o* \# a, ]
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* T0_BOT: Timer 0, bottom : Used for clock_event
: g: a' p% k# Y8 ~& k6 u! x * T0_TOP: Timer 0, top : Used for clocksource8 i* H) U, O# u Z6 F7 ~' I6 C
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer+ |6 w6 u8 _: o
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