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The timers support the following features:# c3 ]$ S5 V, n
• Configurable as single 64-bit timer or two 32-bit timers
6 M, `4 p6 a/ j8 D) h3 z* A• Period timeouts generate interrupts, DMA events or external pin events7 g+ u$ \/ J; H1 p) x; i/ A
• 8 32-bit compare registers! M+ a2 G, j q; i
• Compare matches generate interrupt events/ z) p' e* ~4 l5 v) S$ e5 a
• Capture capability7 M$ _' X G/ r* x, i3 |' ]. z
• 64-bit Watchdog capability (Timer64P1 only)% U5 K6 I# v3 F
+ p( A2 D% U1 {1 M8 J3 j/ V/*
! @! u o' D! U * T0_BOT: Timer 0, bottom : Used for clock_event. S: x6 k' Y0 a# _4 b: T: s' `5 R
* T0_TOP: Timer 0, top : Used for clocksource: T( B; G0 G1 k2 ]' M5 q
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer1 @. g2 ?( F- x, b3 f) O
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