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The timers support the following features:
3 L/ G* q* d/ }# u• Configurable as single 64-bit timer or two 32-bit timers1 I" O" i0 \! {+ ^# V
• Period timeouts generate interrupts, DMA events or external pin events
" {( c6 m; @2 Q; H• 8 32-bit compare registers
. E% m1 R0 h" n# y• Compare matches generate interrupt events, C- S4 N) }2 T2 {6 y- {
• Capture capability
$ |% j' D- l8 r" N+ n! |• 64-bit Watchdog capability (Timer64P1 only): a$ D5 _3 m3 g
& X5 R: Q6 I" m' o
/*( e3 \! f: J5 B' w% E: U
* T0_BOT: Timer 0, bottom : Used for clock_event
1 K# z- {- [% I; Z7 P * T0_TOP: Timer 0, top : Used for clocksource# x0 G) W4 a' M# C+ t
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer* u" j) v- r! _3 z5 |7 a# O) ~
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