|
|
The timers support the following features:
+ t; L8 b, O$ o• Configurable as single 64-bit timer or two 32-bit timers
1 x( i- N, ]) |1 e% j• Period timeouts generate interrupts, DMA events or external pin events0 {9 K! V* V' G8 y
• 8 32-bit compare registers
$ N9 e( u: D' j• Compare matches generate interrupt events
; q, @2 e1 ~$ N* C' y G• Capture capability
; P- P1 N! v1 Y2 E• 64-bit Watchdog capability (Timer64P1 only) b4 F0 p- X8 \' G: i' D
0 A0 q* p- m1 j
/* o) O0 v9 x5 Y. X7 O* \/ a
* T0_BOT: Timer 0, bottom : Used for clock_event) f7 b5 r- S0 g# _
* T0_TOP: Timer 0, top : Used for clocksource2 Y, L- I' U2 @2 Q# o
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer5 u$ W9 u& X; i% }; G4 m) W
*/ |
|