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The timers support the following features:
r) L! |( o$ k& v• Configurable as single 64-bit timer or two 32-bit timers
/ j) C- c9 |: R2 ^) X3 z9 j8 D• Period timeouts generate interrupts, DMA events or external pin events) Q* r* O, G2 k7 K& m( p D
• 8 32-bit compare registers
! b# t' h: I; t0 ^; r% k+ R• Compare matches generate interrupt events' b6 s% s8 ]- r% k" |" Y# \; U0 h
• Capture capability$ O$ B+ C3 B8 T9 q$ d
• 64-bit Watchdog capability (Timer64P1 only)
8 x! b1 `2 D Y" L: B! `
7 i, @9 }: I) ^$ v/ {6 ^7 `/*3 D: _' e7 }# ?- Z$ q
* T0_BOT: Timer 0, bottom : Used for clock_event
2 o: b" J0 R- L+ ^' j9 d- \5 I * T0_TOP: Timer 0, top : Used for clocksource
# z/ y) P4 }, J; F* I* D3 z3 P * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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