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The timers support the following features:
8 D8 `' e- }1 _- q4 P5 u• Configurable as single 64-bit timer or two 32-bit timers& [; R8 P" n5 F7 G
• Period timeouts generate interrupts, DMA events or external pin events
; n( h+ h2 d7 K, h% F/ ?7 e• 8 32-bit compare registers
! W' G D& v- S& L8 Q+ _0 q• Compare matches generate interrupt events
, ~* P" E7 f( M: J' X• Capture capability
I# v& x* b$ G6 D6 G• 64-bit Watchdog capability (Timer64P1 only)
: D( n! T3 [5 g, x6 X% _
/ X" x% [7 v3 s4 t* c/*( K" {* V7 c p |/ s& H V
* T0_BOT: Timer 0, bottom : Used for clock_event
7 o! r% B, V; o * T0_TOP: Timer 0, top : Used for clocksource9 b4 a& A2 b8 g% K4 M+ \+ O
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer/ F$ D, o9 R2 |8 z
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