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The timers support the following features:! G# V- D, J# `
• Configurable as single 64-bit timer or two 32-bit timers
+ m0 h2 j3 P$ U: c+ g: `- B; h• Period timeouts generate interrupts, DMA events or external pin events% M, e% p7 P" k5 W# l
• 8 32-bit compare registers! S9 t [1 I% P" V" ]8 C$ D7 I
• Compare matches generate interrupt events
3 Q- Z! \7 J c5 [• Capture capability
$ j7 e8 b" Y, w% A; Q! u# d• 64-bit Watchdog capability (Timer64P1 only)
& d+ a2 S+ ?9 d( \6 i5 q0 n( P6 r, @: F% l$ u
/*! p, A& J2 V" \, S
* T0_BOT: Timer 0, bottom : Used for clock_event* u( E \( e. l, M' T7 [
* T0_TOP: Timer 0, top : Used for clocksource
# i4 ]' `1 h1 d- z* W0 e * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer( m, u. C, a( @) V6 s
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