|
|
我的McASP配置分别如下:
3 L/ E4 h# f+ g& z! H管脚的复用设置是:2 o7 S$ C& _! X
void McASPPinMuxSetup(void), R$ X8 q% x" J
{. m' S' q) X( e V: z$ ^' U
unsigned int savePinMux = 0;1 f* o7 k! w1 j" K# G- ?
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \- T5 V2 { g: ~2 _6 {
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
4 z, x! H& l9 |. ^ SYSCFG_PINMUX0_PINMUX0_23_20 | \* S& E% s: M! ^9 N. k" j! V: ~
SYSCFG_PINMUX0_PINMUX0_19_16 | \) K- H b0 Q5 R/ t2 A
SYSCFG_PINMUX0_PINMUX0_15_12 | \0 G9 Q I+ [3 h3 w+ V
SYSCFG_PINMUX0_PINMUX0_11_8 | \
4 }* N. e s& C* Z SYSCFG_PINMUX0_PINMUX0_7_4 | \
. M7 E+ S! ~' p& W9 H SYSCFG_PINMUX0_PINMUX0_3_0);
" j5 @" ^' W4 @+ y HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
/ h! y. l6 Q) q m (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
* g, e7 N# @0 Q7 q: K PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \+ E- K* u# p/ [6 a
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \: C" K! c& D ]; ~0 a8 x
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);- I0 O* y( g, M3 K2 ?; d
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
' q5 p( i( i9 U( ?- Q$ ?+ H ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \* o$ z. Q4 x7 J3 d0 h
SYSCFG_PINMUX1_PINMUX1_15_12 | \' ]: O& r6 B1 P/ [3 g! y8 Q1 g* L8 h
SYSCFG_PINMUX1_PINMUX1_11_8 | \
: \7 A8 U$ x( T. }* ^ SYSCFG_PINMUX1_PINMUX1_7_4 | \
1 K$ T* h: p" e6 g" f7 ~6 l# ^! @ SYSCFG_PINMUX1_PINMUX1_23_20 | \
$ K& ]; F. f; ~& o% q% s5 [ SYSCFG_PINMUX1_PINMUX1_27_24 | \+ E) E% Q1 h/ g9 n9 a" H
SYSCFG_PINMUX1_PINMUX1_31_28
1 u# a9 Q! N3 z# \ a );4 R* h+ F# ]3 I$ }
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
# ?! i# P# c! Y& k0 Q (PINMUX1_MCASP0_AXR11_ENABLE | \# ~8 M) A Q4 v' P
PINMUX1_MCASP0_AXR12_ENABLE | \
6 Y2 P2 D7 {& U6 y N: K; g$ I PINMUX1_MCASP0_AXR13_ENABLE | \
: K6 N) @% ~0 G3 K PINMUX1_MCASP0_AXR14_ENABLE | \
5 Z8 u7 ^; c& w9 P PINMUX1_MCASP0_AXR8_ENABLE | \3 o# ]% }$ ~# H* s; {0 j
PINMUX1_MCASP0_AXR9_ENABLE | \
- @0 |: d8 J) B! @; ^ x4 e$ _ PINMUX1_MCASP0_AXR10_ENABLE | \
8 R, n: N0 _/ M0 P0 Z savePinMux);
/ }: w% |/ i, M7 I% I% n6 @}
! x6 L" x1 {6 I" W. B3 n. D1 X
% u; E* g0 \+ d4 \$ K. \4 Z U1.McASPI2SConfigure(); McASP的配置程序如下:* J0 v* Y2 N/ |( ?9 r, c2 X4 k; z1 g
static void McASPI2SConfigure(void)1 L, O! p+ Z( @/ `/ d
{2 ^! _+ b( `8 c4 }, [( K' w+ Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, B8 ]/ C% R( H1 N& _ McASPTxReset(SOC_MCASP_0_CTRL_REGS);
. d7 R' k8 s# S6 j- C! l. v) ]! P8 `& `9 p
/* Enable the FIFOs for DMA transfer */
N! k$ ~' H- E( q' k: F// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);& a1 S; }0 j, Y! v8 J
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( f& f6 ]7 I' o: \
! L" L3 v; m$ d
/* Set I2S format in the transmitter/receiver format units */
6 q- ?* [# O6 P; | McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' `" Z: h' M2 T0 H$ s0 h MCASP_RX_MODE_NON_DMA);; ~0 S6 Q, _; T0 [ |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: g1 y( C% v0 Z% T# b
MCASP_TX_MODE_NON_DMA);
0 p H! o( g5 n( W! b T" H3 I1 y' y" P$ ]; Q3 s& D; w
/* Configure the frame sync. I2S shall work in TDM format with 2 slots *// A! g% I, _3 X: I, k" e5 }$ l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 v7 V0 N( o( j2 ~ h MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; h6 ?: D! m$ g+ P' i/ R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 l& L9 t" \5 K( e
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);# r/ `' H! ]- ]1 x. n8 A3 M
! u+ p, J1 _: p8 b( h3 ?: E /* configure the clock for receiver */6 d3 q8 ~6 K6 b/ I. k% s$ y
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
w! Z, z" u- v& q+ O McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. ^3 ^3 G/ e% \+ v/ M4 U McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
n$ i+ l7 T; `& `- x McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. G0 Q+ u; g- K2 F7 m 0x00, 0xFF);
: a6 G& q7 P! G* T$ {* ~8 H9 ^& P; X1 Z7 ]" L" K3 V7 }
/* configure the clock for transmitter */6 Q" A2 D' B6 o) j5 E
// HWREG(0x01D000A0) = (0x00001F00);6 ~2 E X/ w0 ^2 g: }/ ^& v) ?
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
8 t' x/ g& r# m6 w! Z McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
/ N3 a! L, g% E7 S, R+ m McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ~7 g3 L2 n$ I' {+ o7 F& A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' n. N1 p, O+ V: m' W$ Q! s 0x00, 0xFF);
+ M( R) Z4 z" |% V ' { }; Z1 t0 r7 `4 y) ^% {9 N' M# K" K
/* Enable synchronization of RX and TX sections */ # F: ^' p& J4 R7 d; d7 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
3 q9 S/ r g0 ?6 X0 {1 |9 \" z& Q. c1 n0 ?% f$ P3 ^
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
?) W: b6 P! I* h5 }5 i$ j" I McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: |# F Y* L; p% `. G2 _ McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% |# G3 r# `8 h `$ j" t! Z; v
' b( W( K! O) y. A9 `% U+ }3 i /*' w5 V/ X9 N& y8 U
** Set the serializers, Currently only one serializer is set as
) M9 T6 ~5 d! N0 f$ k9 S$ f ** transmitter and one serializer as receiver.
2 k; o0 F& V+ z- g6 @ */
/ A; N& G2 n: L5 [ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 R! H% F8 B a+ o. t$ s) Q( c6 k- [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);$ K+ _5 r$ ^( ^ F. F7 ~0 }- k# N) z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
" h* |$ L! c. Y5 Y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);5 R0 b1 h6 o8 {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
4 x5 ^0 B0 z: l7 e$ L McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
$ x/ e% H- @* N& D
: r/ @* T+ V# P McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
% x, k# G9 b+ O2 @5 G7 i* K) n- @ N, i% r9 Y9 C5 i1 e
/*
8 [9 U. C" V& b" i ** Configure the McASP pins 3 ^# u' }. j4 K
** Input - Frame Sync, Clock and Serializer Rx7 v4 k$ Y" M- `/ l5 ` X
** Output - Serializer Tx is connected to the input of the codec - i7 s6 P" A) Q3 M( b- o
*/) `* G8 u& u; d1 E; ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) N- P) K+ l: F) g" M- G McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
8 O. ?+ w2 D" j: s. ~1 u MCASP_PIN_AXR(MCASP_XSER_TX)+ x, b t# E5 `! p* g
| MCASP_PIN_AMUTE
/ ?8 n0 [- J; B' k! Z4 ~- H+ b );
- O) T. S3 }" Z& {8 H+ C% | McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
- f$ F6 [! _8 j, M. |/ _& g MCASP_PIN_AFSX
" y$ r* N, S5 B7 R0 F | MCASP_PIN_AFSR5 ?0 f' d w* B' Z; S- o
| MCASP_PIN_AHCLKX% J, S5 P5 d, S" J; w( `1 D5 ^
| MCASP_PIN_AHCLKR
" E0 Q6 \" o- D* j4 T! e# c- Q' ] f- S | MCASP_PIN_ACLKX6 I$ Q* k6 N- c ?( p
| MCASP_PIN_ACLKR' k# t9 \2 \. ~; ?+ Y
| MCASP_PIN_AXR(MCASP_XSER_RX)$ ^ i0 z/ e: }. A1 h
| MCASP_PIN_AXR(1u<<(13u))6 V8 W. Q1 e* D% T% Y& r; v
| MCASP_PIN_AXR(1u<<(14u))' x( \% D2 d$ k/ P% W
| MCASP_PIN_AXR(1u<<(8u))
6 K+ S8 s7 v7 R* E9 ?; G | MCASP_PIN_AXR(1u<<(10u))* r9 e- N1 {2 _- V% N. b& q% t4 B
| MCASP_PIN_AXR(1u<<(11u))! m+ W' w$ K/ g% m) \
);
7 F1 O6 G B9 p
$ } H/ v K5 {7 ^ /* Enable error interrupts for McASP */
/ |- F: T+ @& Z# H; [* J McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
9 k- ?, Q1 ~2 V/ Q MCASP_TX_DATAREADY7 O' E2 P$ C5 Y4 M3 x1 T! U( c
| MCASP_TX_CLKFAIL 8 S" l3 `- u5 ?( B0 \6 E' y
| MCASP_TX_SYNCERROR8 d4 }5 Y# U5 @' M7 u
| MCASP_TX_UNDERRUN);
F0 [3 u+ I! `% l* x& ?! p# e7 x/ g1 a) C$ z% `
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
# O% X' h$ m* o" X MCASP_RX_DATAREADY" H" l3 H5 U! |, {
| MCASP_RX_CLKFAIL
Z0 w& j/ z* u6 H | MCASP_RX_SYNCERROR
- S- H, D9 E: Y$ T& z | MCASP_RX_OVERRUN);9 @1 d9 K/ R% e1 y9 t
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
" G: g$ A" M `) r9 f! @0 X9 T* J' O7 I" R/ {) z @6 U
}
( S( H. ]0 m' S, P" r' L* {( R2 e) Y' R6 ^& v4 y0 `. V
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句7 a0 Z' b! ~ d# z# D6 B" `
static void I2SDataTxRxActivate(void)
8 h" m9 k) E) F. R$ f6 d{* a- F) _6 Z% W7 C4 ?! w# ~
/* Start the clocks */: ?2 ^& s( B, J1 Z' F/ U- G: L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 I. i" H# L1 R# ^: E' p7 J) L McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);: V5 M, X( j* K; k6 l0 u7 }
8 S/ T( d8 q+ _7 t; J
/* Enable EDMA for the transfer */5 q5 j. m0 ~* y M
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 l2 X8 s: F& U( u// EDMA3_TRIG_MODE_EVENT);* [2 |$ x" i1 M- ~8 _7 h* [* N
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,- Q& z' g: Q+ {* I ]8 X+ Z& t8 U
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);8 R2 C# S! g2 I' X
/* Activate the serializers */
* [5 z8 g- }# }! k3 x McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! ?: b9 K$ R* H" n; w) f0 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 s' C+ k7 g. ^) N+ M3 n /* make sure that the XDATA bit is cleared to zero */( S+ z) G. O* D5 \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);: [/ |, `2 h+ w$ R% o
/* Activate the state machines */
! f% P+ O8 a6 R1 R McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, \3 l. g3 g$ I# D0 K+ J0 u6 ~ McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 p& ~8 I1 z1 g McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
% ]' v% v" b5 e" N3 w) Q8 e( {}
2 x4 t6 X6 I# R. s m8 S
% M9 s% B8 J6 }% M& [2 B |
|