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我的McASP配置分别如下:
1 p2 ?$ v! t4 a' v& d3 R: S管脚的复用设置是:5 a+ N6 P# D6 S3 T0 S
void McASPPinMuxSetup(void)2 U) _% x5 v( y' j( H
{8 ?* p7 m; V* V* {. S
unsigned int savePinMux = 0;8 |* O- K) q" Y _8 @: ~8 e* p
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \' K7 ]- ]8 @7 u
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \4 m* D) C1 s$ s# J9 r' F
SYSCFG_PINMUX0_PINMUX0_23_20 | \
/ I3 J7 W2 d. @2 |; _- ]9 A1 k SYSCFG_PINMUX0_PINMUX0_19_16 | \1 z' u v9 p f: Z7 h
SYSCFG_PINMUX0_PINMUX0_15_12 | \
" s! V* Z/ m. |0 p% [' w* `# a. T# r SYSCFG_PINMUX0_PINMUX0_11_8 | \/ q6 n1 \: ?5 r" M' @1 r: H
SYSCFG_PINMUX0_PINMUX0_7_4 | \
+ _# T& f5 w& T9 `9 x SYSCFG_PINMUX0_PINMUX0_3_0);
! V& y/ O( Z# `' V: n HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \$ H- E, P5 N5 F8 o
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \ F M( z8 L Q8 D
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \1 Y, `, M9 w- _: R* D7 F- m
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
7 ?) ?4 }. f1 j# u: j5 n* h PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
0 p/ ~1 l9 s, h6 V5 ^ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
. v' W, C' ]$ N n. u ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
& p4 Z4 D" ~5 F% t/ C+ V& d7 ^ SYSCFG_PINMUX1_PINMUX1_15_12 | \
& U9 V8 |$ a! O SYSCFG_PINMUX1_PINMUX1_11_8 | \. |3 U& s& b4 d
SYSCFG_PINMUX1_PINMUX1_7_4 | \
; l1 A/ c6 x- z4 W SYSCFG_PINMUX1_PINMUX1_23_20 | \4 t" { P. V0 n/ |! t. Q6 [. w
SYSCFG_PINMUX1_PINMUX1_27_24 | \
$ I3 w. j2 o4 F/ Y$ Z+ F* |' J l SYSCFG_PINMUX1_PINMUX1_31_28
: u2 v8 e6 |) [8 Y1 ` );
! i, ?1 X: ]9 ~6 v, U* J HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \" x0 y$ D C, g6 O+ P. m! W1 Q
(PINMUX1_MCASP0_AXR11_ENABLE | \' D" \5 s4 U. e1 b
PINMUX1_MCASP0_AXR12_ENABLE | \$ Q" i, |) B/ @* F% }7 W
PINMUX1_MCASP0_AXR13_ENABLE | \$ p% \: }, F& u& e/ E+ x
PINMUX1_MCASP0_AXR14_ENABLE | \" R) Z# [( ~5 G3 l* G
PINMUX1_MCASP0_AXR8_ENABLE | \
) Y& m6 D% h4 z2 e PINMUX1_MCASP0_AXR9_ENABLE | \
6 L" t) J& U1 B7 G& C PINMUX1_MCASP0_AXR10_ENABLE | \* r Q9 \+ X5 q0 x
savePinMux);, h* }1 { ~* J& |! ~ ]# G2 x
}2 e% Y/ V' m ^/ q. U3 g
$ m, g2 ^0 w6 {$ x& Y! k7 ]5 L7 g( N1.McASPI2SConfigure(); McASP的配置程序如下:& e& b) ?) G7 _
static void McASPI2SConfigure(void)6 e; B" U; x: h- _
{0 w: e) q& M2 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 t2 Q7 \; h9 J1 i5 Z; q* r/ K McASPTxReset(SOC_MCASP_0_CTRL_REGS);8 I( M) M, g9 A$ Z7 b& [8 [# p; W: I
, A6 A- d7 w" c; i /* Enable the FIFOs for DMA transfer */4 v# X2 T, n+ Y6 Y; H6 o% t
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);- X) l1 Y' P2 d, ^8 m: R
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, X& J# U2 l! E; r
) Z G+ u) J8 R4 x8 D /* Set I2S format in the transmitter/receiver format units */
' M, Q# b0 J5 [ ~1 ?! H5 z- l1 m McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 N M3 X& X3 J# w2 g
MCASP_RX_MODE_NON_DMA);, h* S' j* q! A: ~6 |6 ~7 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 Q" m* ?- x! C0 H7 L2 A
MCASP_TX_MODE_NON_DMA);
0 z, W3 c! H1 }* _
: Y; b U, d4 Y" J! O8 { /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 V2 y$ u) w# J( }8 u McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' v( b7 c# b4 |/ a/ l( f MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* Q) L# H9 V$ A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # e+ e- f' x r
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
. \4 f9 r3 a# T" H' o9 v! L9 i; T. L0 I) g# T
/* configure the clock for receiver */
6 X6 c- x& i/ O4 Z// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);5 {7 U/ F3 u6 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' B( q. r& G; u1 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);3 O7 {3 J. ?# K5 _8 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: I4 q8 J( M% B% ~
0x00, 0xFF);, _) ~1 s) P @- F: U7 k6 v
* A' N" ]7 |' e, W9 {7 Y
/* configure the clock for transmitter */0 M4 \0 ?8 }/ @5 d% i, T f
// HWREG(0x01D000A0) = (0x00001F00);
" e! a$ M8 r" ^/ ]3 Z* H// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);0 s0 o+ r. ?, F; @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
) ~0 J8 }7 U% [$ u- R2 Y/ {3 F McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, n6 e* I: M4 U- ^. a2 i1 N McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 f0 N9 Z# y- ^0 E7 C3 o; R/ ~ 0x00, 0xFF);5 U) b3 u$ b8 V+ D6 ]; C( g
( q% [. n* l9 b0 a /* Enable synchronization of RX and TX sections */
$ m; i0 f9 Z1 M( x! [6 s! S H: O McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);) j! S' b; L1 s l/ S
! v9 L" R' L" ~9 O; Z* U
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ J+ C% Y, w; p+ ?, N+ } McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 [0 C% N: j8 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 \- J9 n. b- ^# E- p4 r
6 K, W) M( a+ o
/*
! X5 R; ^5 x& K& B0 D6 ^ ** Set the serializers, Currently only one serializer is set as8 Y. j# ?3 G* x7 |( v
** transmitter and one serializer as receiver.# L: q$ \$ \/ Q
*/' g) c" Y2 I, ?# P6 W, f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! t' ]0 V& y& i' g2 P7 ] McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
% A5 J' O' u9 i/ |8 C McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
9 I7 P7 I. j, K McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
5 L0 {! m# N7 e3 Q' N$ d- j McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);# e( b+ ~, H" X0 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
& `! j5 [! J! ?+ t% m
# A. S G% ?1 a. k. q* G) |! s McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
: I$ v0 B& }& C; T( c
/ h3 a& ` {) I# \. ~4 W" Y /*; R- e3 L1 s D. A8 E
** Configure the McASP pins
3 E$ L; w- M* s6 _ ** Input - Frame Sync, Clock and Serializer Rx# ?5 i0 L7 o+ m+ d
** Output - Serializer Tx is connected to the input of the codec
% z& N/ s- t, X, R8 E; A */
; G F. s! K4 {5 g% V McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 T6 g- p; A9 K' Z% r) U McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, W D7 S2 }& ^! T5 o$ u
MCASP_PIN_AXR(MCASP_XSER_TX)
7 ]' y$ t6 c/ O2 G/ V* V$ b | MCASP_PIN_AMUTE
6 m" N: M* X( Z8 h2 a1 U );
5 b% T* w4 K3 j) {3 X2 ` McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
6 J+ r) t# X0 r, ? MCASP_PIN_AFSX8 Y! C, t1 h* \; y5 X
| MCASP_PIN_AFSR
/ J C- x1 L4 f! `8 ~ | MCASP_PIN_AHCLKX" x& Q8 B D; S' c# [5 p
| MCASP_PIN_AHCLKR+ n+ Y/ y9 k! X3 \/ u3 B
| MCASP_PIN_ACLKX
( ?- ~# `/ Z P. e. \ | MCASP_PIN_ACLKR
( d. V& C! a0 D5 {0 {9 A | MCASP_PIN_AXR(MCASP_XSER_RX)
. F* p! |1 g$ s& A0 A | MCASP_PIN_AXR(1u<<(13u))' Y, U0 W, ] D2 F% R8 w
| MCASP_PIN_AXR(1u<<(14u))
; n' x6 m% u2 l, p: l; K: v | MCASP_PIN_AXR(1u<<(8u)). A+ \/ k) D6 x6 w
| MCASP_PIN_AXR(1u<<(10u))9 A5 D+ |$ O( g" j4 i2 W
| MCASP_PIN_AXR(1u<<(11u))" z* U6 m8 @- a4 p8 @, O3 l, w
);7 f& f+ A0 p) M j; c `
4 \" ?* y2 S0 P' v
/* Enable error interrupts for McASP */
& J! V9 x R8 [; S, |1 {3 n McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,9 z9 {# R6 [2 Q/ [0 _# g2 h
MCASP_TX_DATAREADY
" s7 D; D- m, l1 M7 u | MCASP_TX_CLKFAIL
. A) E2 P7 A& c6 ?# o | MCASP_TX_SYNCERROR# u! e. p/ d$ r, j& D+ u
| MCASP_TX_UNDERRUN);7 m* u3 G/ N6 k A+ `
" g+ H4 z. L( q% C McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
% b+ N: M l4 ] MCASP_RX_DATAREADY/ Q9 n& u2 a! m* z% K q
| MCASP_RX_CLKFAIL
" V) w, V/ J7 S+ Q& h1 Q | MCASP_RX_SYNCERROR 8 Z/ {2 v; j+ s
| MCASP_RX_OVERRUN);
- T+ E, A+ V- h5 |/ \//MCASP_RX_DMAERROR MCASP_TX_DMAERROR: r% w* h5 J# } i# E |
" s" |" Z6 w5 W8 f: H}
0 S& \7 w$ U! b( w# U% H/ K' [* }. h, y' O
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句" ]6 p( {. c0 X0 v3 g1 p
static void I2SDataTxRxActivate(void)
: k M8 _+ z' W" _4 ?{5 E0 I% b) n( m: [: ~& s9 j8 I& P
/* Start the clocks */
' v; ?. [3 ]" v' c' s% ?( L3 s McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' ~. n m. A) L" p* P1 S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);, L! E6 g- t% S0 X' C6 c
! c t# U; d) k/ C; ~3 @
/* Enable EDMA for the transfer */
6 D8 ^9 n8 T+ S# L) D0 b4 _4 l& X// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- {/ O- c1 A7 h: m0 ~5 Y
// EDMA3_TRIG_MODE_EVENT);, T: X, r# @+ |; Z& l
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 \% C" P; i |0 {, ^. t" ?// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);! i) e6 O5 s* t2 a
/* Activate the serializers */
, f1 U* h6 ?! H3 ^' j/ g; b McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ T8 q$ ^1 o0 L7 [% E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 D$ d2 @6 v5 _# `: x# A /* make sure that the XDATA bit is cleared to zero */
+ Y7 `4 v8 s! z6 l! `& r while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);. g) ]( V7 J, O3 v& P0 C) r' N& ^
/* Activate the state machines */* h+ x4 m4 x9 U9 Y+ X$ \2 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" D. ?1 b0 G4 O- P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ k) _8 H Q' m n! G7 W
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);; u7 }% C* `8 N( {0 Q
}4 u, k) E; n5 Q8 A7 v. y% [( Q+ V: E
3 H5 ~2 f: n* |' a/ } |
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