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我的McASP配置分别如下:
U3 K7 {" B4 ?4 r管脚的复用设置是:
* d0 J2 f9 o# {* `( X% S$ c) @void McASPPinMuxSetup(void)" F' P& \ Q3 r
{
j4 @( f/ A1 t& S& e, f8 m unsigned int savePinMux = 0; |/ l% Q. O9 i: [
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
' f) \5 }5 r; k. ~ X. | ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \ {* j4 P# |2 E
SYSCFG_PINMUX0_PINMUX0_23_20 | \$ Z6 l- L( W0 `1 c6 Y/ E
SYSCFG_PINMUX0_PINMUX0_19_16 | \
3 X7 `, Q6 p: b% b! S& Z" H0 B SYSCFG_PINMUX0_PINMUX0_15_12 | \
+ H2 v: O. D8 o0 _ SYSCFG_PINMUX0_PINMUX0_11_8 | \, r( t% ^5 i; A0 Z- |
SYSCFG_PINMUX0_PINMUX0_7_4 | \! Y: X( j9 ^# Q" [9 {* U7 \
SYSCFG_PINMUX0_PINMUX0_3_0);+ I8 {3 d, C3 s$ i: _2 r
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \4 Y, G9 F. ^: B+ F
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
1 S5 r, V' I F: M3 @% Q" K PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \" a2 y7 m, b3 Y2 b3 `) v
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
2 L+ }7 ^& o8 U$ v; _8 ?9 O PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
5 r7 J4 v6 y$ x5 t7 y! F) X! Y savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
S0 M, J* _( e( } ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
0 l1 [+ X5 J: V% m SYSCFG_PINMUX1_PINMUX1_15_12 | \
U- o4 @% @0 t' H SYSCFG_PINMUX1_PINMUX1_11_8 | \
1 O' k' F$ G9 y4 \3 n! v/ w7 U1 U SYSCFG_PINMUX1_PINMUX1_7_4 | \
9 i1 P {9 C, g7 W/ u& K5 D9 ? SYSCFG_PINMUX1_PINMUX1_23_20 | \
' t0 ]" ^% ~& P9 H( p$ G SYSCFG_PINMUX1_PINMUX1_27_24 | \& ~7 w" o3 J9 h& {
SYSCFG_PINMUX1_PINMUX1_31_289 F2 W8 E9 P. e, Q, n) u+ m. o. K
);
e$ V$ N0 w0 C; O HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
( M4 v2 ?! N) T0 s# I1 t$ ` Y (PINMUX1_MCASP0_AXR11_ENABLE | \! n# d$ f. M, N. C5 u4 M4 u8 T9 p
PINMUX1_MCASP0_AXR12_ENABLE | \# h6 ?5 V9 }9 F3 e
PINMUX1_MCASP0_AXR13_ENABLE | \
, _' ?1 r8 I: @& q PINMUX1_MCASP0_AXR14_ENABLE | \. q. o2 e% P; i9 F, X2 _
PINMUX1_MCASP0_AXR8_ENABLE | \
9 a5 @ |, H; p2 @. y. h9 v" d PINMUX1_MCASP0_AXR9_ENABLE | \3 D! b# I: {) w, q' {: j
PINMUX1_MCASP0_AXR10_ENABLE | \
, X& O* ~% G; @; ] savePinMux);
" ]6 M# z' ^, I. p0 v0 i}
( U/ s: F* |7 t0 k7 a# `8 Z2 {7 V+ E% ^6 h! c. F# }: |7 W
1.McASPI2SConfigure(); McASP的配置程序如下:7 k$ G" a: R& f
static void McASPI2SConfigure(void). Y& n- S) _( S; j# z& ?. P; v
{
+ x9 @* h1 j/ c; A McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 `$ }/ ] |; d$ r( y% q McASPTxReset(SOC_MCASP_0_CTRL_REGS);( U( f# s- b7 r1 _7 j7 i
w5 o% @! u! K- H2 J6 }
/* Enable the FIFOs for DMA transfer */1 z! |4 L# m7 A7 ]# ?0 g& i9 F6 _
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
b V( t4 I2 ]0 f// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 o& U; c, [ D' T8 g2 R/ L/ m$ s( n" l- t* b
/* Set I2S format in the transmitter/receiver format units */
/ }# o5 v" [6 B* D3 ~' {$ |8 k McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% E b/ |6 r4 q; m# U. `- U) _! W$ h
MCASP_RX_MODE_NON_DMA);
' X! Q0 W" M$ x- ?# b7 M McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' v# S$ V7 s( d5 A' { MCASP_TX_MODE_NON_DMA);
0 C* k0 v8 d& L9 R1 n* l
2 [3 B+ M. r6 v% q6 m6 y+ Z /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 |( E% s d* R1 Z J, H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * A3 i9 `; u/ ]1 g2 p. \( Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( }& p; c( C; @- J8 b- H McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % `% [) e; Z" |
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);% e; K1 r. \4 i
3 d8 j) z/ o5 H: c, d6 y0 n6 q /* configure the clock for receiver */7 l4 ?3 R' C y* i
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
& P8 @9 d, Z+ n" s( l McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 R4 ]" z$ V2 D& { R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: E( v9 k9 \6 [8 d, { McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 S. S- W% u. {) ~( D
0x00, 0xFF);
) U2 j6 d$ s$ W' g% N; p9 H* x; u3 D8 o' H7 @# \
/* configure the clock for transmitter */
4 v8 V# {7 q, M// HWREG(0x01D000A0) = (0x00001F00);9 |0 c, } G! I$ P5 m2 u
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);. `( n a) W1 Y5 E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
; g) ]+ x) v2 p) ^1 K4 S McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" h+ a, U C' c+ z McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 e( D8 \( Y5 w* A7 {
0x00, 0xFF);, p2 X' f7 M4 m! h! S
$ A$ e/ m. O/ N! A! T, R
/* Enable synchronization of RX and TX sections */ 0 _ U1 s& y1 ^# H9 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);8 R2 H# p" ?# c2 T
7 O1 g2 X$ x7 `! b% V /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 Y# x2 f s9 d }- F, A& V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( X3 g: X- B# T4 ?. T2 f McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 c. c, U& }- @. y! w& j1 ^& K! U+ C8 Y1 D# e( H
/*6 R7 F: J0 z1 o2 n
** Set the serializers, Currently only one serializer is set as
" j$ G, g, s: D; ?) H/ F: \ ** transmitter and one serializer as receiver.
1 ^6 Y4 v0 G2 V */
) @+ c! j/ m9 s6 d" [ u McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ j# S2 c) o5 G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
% a: s% B; `5 x, [ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
/ d6 C2 Z4 T* N* X% ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);; c& |6 p! p! W: r, \! r8 G* G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
h7 b4 w0 R/ i) G8 l' V+ @7 ? McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);7 m" B- `* k' @* F
# U6 Z# C# y" V+ I% f$ e# N McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
( X, E. a( @# w, t0 H
7 H2 n# c# L+ k1 f2 I0 `) C /*
" I. p6 e$ Y8 N% z ** Configure the McASP pins 0 X' T: b# C1 X' c# O4 T/ B
** Input - Frame Sync, Clock and Serializer Rx$ ?, |9 _/ ]: \( z, x/ l- X! @
** Output - Serializer Tx is connected to the input of the codec + {6 e$ S' f% g# G+ N0 ]# d
*/4 ^: G! G- [/ ~; E, ^% \- R9 k) }0 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, C/ W, }7 l+ U [ McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,( H' ~6 k+ x0 _, n9 |
MCASP_PIN_AXR(MCASP_XSER_TX)
# U) I+ G( I/ j( D' z. S | MCASP_PIN_AMUTE
$ l4 o/ f3 \6 J7 A* _+ e, M );
2 n+ w5 C) b9 X* R1 ?8 [6 h McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
& R+ b( \1 F, o6 I. k; m MCASP_PIN_AFSX
1 ]& J/ m5 E% x7 A | MCASP_PIN_AFSR, o6 ?6 p' y4 A, m% n
| MCASP_PIN_AHCLKX/ H4 L4 O8 s# C8 ]/ o: S
| MCASP_PIN_AHCLKR
5 W$ p; t, J# l4 m: ?# w" | | MCASP_PIN_ACLKX
: t7 N5 N* @/ T2 C/ k | MCASP_PIN_ACLKR1 M& d# s) w1 O1 T4 j- m" f
| MCASP_PIN_AXR(MCASP_XSER_RX)7 z+ s$ K# t/ t/ p
| MCASP_PIN_AXR(1u<<(13u))
* {" ?9 {! T1 X+ ?0 m | MCASP_PIN_AXR(1u<<(14u))
# ]* {8 w4 n$ h' a+ X | MCASP_PIN_AXR(1u<<(8u))! a' w$ o, j8 |+ l; m* G
| MCASP_PIN_AXR(1u<<(10u))
' T7 t6 Q S, U0 H7 r | MCASP_PIN_AXR(1u<<(11u))0 u! [( e- H; S4 e6 k# i6 E, \( h
);
# e2 u2 R8 d. s3 O. L
3 ]' e6 ^7 @& T# J: { /* Enable error interrupts for McASP */1 T: ^ y6 R3 |4 b2 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,. t }. V" ?. o V& |" ^& T3 i
MCASP_TX_DATAREADY
1 I2 R& n% F0 z/ b3 Y( B1 g; R | MCASP_TX_CLKFAIL
3 h* ]& l* E4 j4 f" V( }. z' a3 P | MCASP_TX_SYNCERROR! K2 h1 x3 h; M2 H
| MCASP_TX_UNDERRUN);
8 p2 L" t& Q) t9 g9 d* b: M, N! C+ w6 t" q' r
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,9 ?4 ^7 t8 V B4 _" I' ?$ |! n
MCASP_RX_DATAREADY" D2 \/ [ r% a2 V- F! S' |
| MCASP_RX_CLKFAIL& y6 m; X9 W1 C; I- I
| MCASP_RX_SYNCERROR
$ a9 ~% n: A/ t | MCASP_RX_OVERRUN);
7 n& _/ ?0 H2 c8 G& E//MCASP_RX_DMAERROR MCASP_TX_DMAERROR! d- v+ o/ Y t" @- O
9 e% {: z& J: n9 E6 N" C( m
}3 ]2 u: I5 n+ j. j
' l) o$ z) C/ {' B k) H e) D; e" Y
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
$ O0 a' j3 j+ Zstatic void I2SDataTxRxActivate(void)/ P5 g: h4 {6 V7 J/ c) o) t8 ~
{8 Z- q* ]7 Z) Q
/* Start the clocks */0 i; G" r6 ^ O# J8 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ D' {7 H; p5 T6 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);! _$ Q1 ~3 }1 ~: N0 z. T6 k
' n, M7 ~ b6 W8 ?9 T- ^& X; ]) g /* Enable EDMA for the transfer */
( f) d! ]. e4 S/ l0 R' `' Q% X// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ E$ K$ f1 _# l( }% b) |& d// EDMA3_TRIG_MODE_EVENT);
) ~$ V1 s: B0 E; z0 E) m1 u// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' C+ s* c+ |5 W$ U0 @5 }- ^ N// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); ^0 H, k3 W) i$ i% s! U
/* Activate the serializers */
, N4 l' F% {; A+ B8 ~, @ McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 V! [9 ] t: P' F/ b! W7 }# e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
# e) m) c0 {3 _8 O /* make sure that the XDATA bit is cleared to zero */
' j& U# n0 t* |% p9 ?* S while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);+ [4 M+ a; O3 [3 p, P0 v
/* Activate the state machines */8 Z' F. H( A/ ]1 g3 ~4 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 O7 p4 A7 w4 I! x9 ^% ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 R2 X' M; U6 a0 C6 d3 n McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);: B0 _& Q' A+ E
}. J% r4 m% b) a) e3 l! W2 J# U
' x' x+ o3 L; A' [" t |
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