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我的McASP配置分别如下:1 V: k2 R" Q4 X0 G8 a
管脚的复用设置是:
9 T2 L* R2 l' D4 _' Y9 ~ e3 ]' Jvoid McASPPinMuxSetup(void)
: o/ p7 _& J+ T9 a{$ }% I* x% z& ~, z( ?
unsigned int savePinMux = 0;, A5 U4 i3 A3 f& B9 q+ C
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
) K' P l# ]$ a! l& i6 e1 L" e2 S ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
) j% s8 q: y t! B SYSCFG_PINMUX0_PINMUX0_23_20 | \
7 X) m& I2 s- J SYSCFG_PINMUX0_PINMUX0_19_16 | \
X: i Z( Q8 p$ L1 s2 y SYSCFG_PINMUX0_PINMUX0_15_12 | \
+ {' v8 u3 L, |- \( O% K2 d SYSCFG_PINMUX0_PINMUX0_11_8 | \3 t$ r( v2 z. a' S! E/ X/ Y
SYSCFG_PINMUX0_PINMUX0_7_4 | \
' s2 v; v8 `& ] SYSCFG_PINMUX0_PINMUX0_3_0);+ x% r: T# l: g% y
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \6 m5 R) \( ~; p! h) B4 W
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
- c" F" f1 _( ~" `/ P- w, M PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \" L6 [5 g# g9 @) Y3 t
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
1 l! V8 a2 @9 p) ] PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
; e& V6 s% `) \! {, j+ F savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \8 k7 ?+ T* ~: r; k$ O5 \8 s/ j
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \& n* E% ~* I) Q: w" i5 E/ b# E
SYSCFG_PINMUX1_PINMUX1_15_12 | \
4 L. T$ G2 L9 g% a/ k SYSCFG_PINMUX1_PINMUX1_11_8 | \
/ q% ^; I3 C: q; i- b5 r% m# E SYSCFG_PINMUX1_PINMUX1_7_4 | \
1 \' [4 H* C4 O% b1 E SYSCFG_PINMUX1_PINMUX1_23_20 | \
8 y( _3 M% f7 z" c! ]' i4 f SYSCFG_PINMUX1_PINMUX1_27_24 | \
+ h& D# y S0 Z SYSCFG_PINMUX1_PINMUX1_31_28
3 T: V( m8 y" u0 A& [; t );
- d! z8 d3 G5 R6 } HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \, ^2 }3 ^0 W& R& U. A, a
(PINMUX1_MCASP0_AXR11_ENABLE | \2 k: }9 n# o v, r, g
PINMUX1_MCASP0_AXR12_ENABLE | \
' u- Z% m. A# k) v; G PINMUX1_MCASP0_AXR13_ENABLE | \ c/ l) P" y6 y# L: e0 y; A% J! T" `
PINMUX1_MCASP0_AXR14_ENABLE | \
, q3 Q9 V" h% \0 r* Q8 T* w# o PINMUX1_MCASP0_AXR8_ENABLE | \
9 i+ Y' g1 J/ v5 J PINMUX1_MCASP0_AXR9_ENABLE | \
; ~' \3 n- w' G, r* p PINMUX1_MCASP0_AXR10_ENABLE | \
0 I; S0 x; r3 {8 f8 M9 p. i2 ` savePinMux);
v$ a) N7 m& @& P8 e% W}
0 c' x4 F( G5 R A; Q' ?- R
9 x' y0 x' s* h8 ~4 O; [* N. r1.McASPI2SConfigure(); McASP的配置程序如下:. i4 S" L/ t" Y6 r9 O1 L
static void McASPI2SConfigure(void)
+ q/ {- N& O4 d{
' ]( _. f: R$ P6 {" ?2 M McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, Y% @) ?8 M4 ` |$ V McASPTxReset(SOC_MCASP_0_CTRL_REGS);$ g; s% i& x! N- |
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/* Enable the FIFOs for DMA transfer */
/ n+ y8 {! h4 E( x* O6 O: ~// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);7 l; J6 O3 E) h. ~
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* V B2 r, M% _! _3 L3 X4 f
; C" b( \$ y- V" Y /* Set I2S format in the transmitter/receiver format units */
/ `. {5 K: ?* w McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 T: t3 M( u4 V
MCASP_RX_MODE_NON_DMA);7 l0 r4 U. H9 y6 `+ w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: j1 P: s1 c+ y/ p$ b. F, b( A
MCASP_TX_MODE_NON_DMA);
: U/ N- [$ h1 m) k" e
1 ]" R; E) u4 {5 f2 x. ]6 M /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% O- P; i8 y* R: N& t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: D8 A& x8 J+ \. z7 l1 H# x3 v MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; s5 K s& o" } L: J6 R. ` McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 C* u6 i# Z! I& K
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
' @5 |' Z8 U' x4 M" Y
0 z+ n$ o' N- y) w6 K /* configure the clock for receiver */2 B) c. Q+ x* c% G$ T
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);7 _. Q% b& i0 c, S2 }% M9 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' U) E& q& u/ X' n' j* ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Y* z+ U. z/ J$ n7 `! J McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( V! ^ C1 h2 G3 y; g6 S) b; q
0x00, 0xFF);# W( {. }3 N! x! ]/ |* {
, B7 X& |9 U. ]; e, `1 k7 h /* configure the clock for transmitter */
+ h0 c2 R; a5 z6 Q* t, ?/ k// HWREG(0x01D000A0) = (0x00001F00);
A |5 W2 g4 }- t* X: j7 d. y// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);! p- _$ @: \& e6 h/ ]# ^ h+ T R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
) z! r3 e6 w# q McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ u0 g) p! ]' ?* w6 z* v# t McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% [1 g2 o' W% C; V T) z$ W 0x00, 0xFF);" s0 m k5 Q% }( d
8 o' _$ M. m! Z/ W /* Enable synchronization of RX and TX sections */ 5 c0 u' p U* @5 k9 S: |/ h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); L" R. J- y. g1 K
* J/ ~1 j0 e7 J! x2 c
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 L/ B' B1 {& {( d3 F/ |( [' w McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' ]# Q4 _8 }4 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) T- E% b+ y0 {2 J& k5 G
1 |( v j$ E8 @$ U3 d
/*
; O- H' A' J, A5 w$ f ** Set the serializers, Currently only one serializer is set as
$ [) R: j( d( s% f ** transmitter and one serializer as receiver.
* l( c4 \7 R4 m" M */, ~' _7 J! B4 p" u7 `" |+ i0 B3 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 F0 n8 \+ Y9 `0 ^5 K) a9 [- P# r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);$ O) T# F7 v% b1 t& ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);% u# V7 h8 Q7 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);+ Y9 H% j/ e2 w7 [% X/ t2 U' d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
- a2 t/ M% s5 l s- t McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u); h% ^; ?& V0 r/ T& d* l8 a- u$ D* ~
4 r s7 j5 q- q, G+ Y McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);/ V# Y$ n" V" `
+ p: k, h8 r# J
/*- k$ R% X" a( l$ j) ^) v; T
** Configure the McASP pins
( t. z* d; Y9 u$ K7 N ** Input - Frame Sync, Clock and Serializer Rx
/ [5 f* K9 j2 I' V9 p: z9 y& x6 v ** Output - Serializer Tx is connected to the input of the codec
; _+ B- e! g& ?/ s */
" S7 H9 i: \5 ?) R) V- ]. { McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( A) e# f8 L( j3 A1 t4 U' M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,' Z, _. @5 }) p) u
MCASP_PIN_AXR(MCASP_XSER_TX)
9 K* p) H2 i; e% Q0 l. d& L | MCASP_PIN_AMUTE/ b, b' u8 p7 t) x0 O% L
);# @3 h- k! V. s( A7 N% F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
# x1 X w- o9 ~' ~* C3 l( Z MCASP_PIN_AFSX
: a9 m$ X1 C' l* `! v3 n | MCASP_PIN_AFSR# O* c! ^1 f+ M% U4 u
| MCASP_PIN_AHCLKX# @8 N7 R" L2 X, H6 Q
| MCASP_PIN_AHCLKR/ ^# c; F( P; r. X" K
| MCASP_PIN_ACLKX
+ h! G) e' O d8 v& F | MCASP_PIN_ACLKR) p+ _1 H1 x2 j& r1 s3 X: z( Q$ b9 m1 U
| MCASP_PIN_AXR(MCASP_XSER_RX)2 R# }( k, x- j
| MCASP_PIN_AXR(1u<<(13u))
- N, G# h: P4 N* h | MCASP_PIN_AXR(1u<<(14u))
! K/ h0 Q/ `0 v Q+ V* ] | MCASP_PIN_AXR(1u<<(8u))1 N; `5 b/ m7 c- g; A1 w8 r
| MCASP_PIN_AXR(1u<<(10u))
3 r0 B5 `7 `2 P | MCASP_PIN_AXR(1u<<(11u))) ~; z9 w+ D" {! F v% J
);# j5 C7 ^% z1 d4 K2 a
/ T7 \% v+ k% i; r
/* Enable error interrupts for McASP */
' P Y' u9 J @* }: C! @3 {6 D1 C McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,4 ~4 K% Q, N; [7 B) Q
MCASP_TX_DATAREADY
7 ?, p% L, f1 y" N | MCASP_TX_CLKFAIL
: D) o7 L: f; B: r- b' v | MCASP_TX_SYNCERROR V7 {7 j5 h) y8 K
| MCASP_TX_UNDERRUN);& r8 h: g3 @# h! S
. w4 C( S" v& V- H9 l' ^9 ^
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
# k2 ]3 b# m9 N- N6 h MCASP_RX_DATAREADY
4 U1 B. W9 e: ]! T9 I3 u | MCASP_RX_CLKFAIL
1 Q. ?0 N& h% u0 x; E7 z$ t- ~ | MCASP_RX_SYNCERROR 1 w* S/ @/ T* r6 c b$ U( k
| MCASP_RX_OVERRUN);2 S. v$ ~) C) g/ k' A, ^* V9 @& U
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
! y7 n; ^% B1 m4 i( c# z- f0 l r
4 ?& V7 I! k5 g}
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2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
}. U# U g! N' sstatic void I2SDataTxRxActivate(void)
' D4 h3 U; S _{
# ^- s& A! h4 C5 K$ a /* Start the clocks */' W2 c d6 {# q; g' W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 u8 B+ q) a; @" o McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
+ c, I; ?* z" q* m, c" j& r3 M% Z
/* Enable EDMA for the transfer */
5 l5 `$ ?3 Z; c4 F// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 c6 U" q2 @; S8 z+ g// EDMA3_TRIG_MODE_EVENT);1 r9 H* q! B0 g v9 `- ^
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,2 L8 |" G- C/ f
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);. W3 F! L1 d( D2 w B Y
/* Activate the serializers */
( `7 l b" p, ?5 {/ n7 u5 V McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 M, q" I7 A( P* Q# m McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);( @. s$ S/ ] P4 \3 f$ x
/* make sure that the XDATA bit is cleared to zero */4 g) @' P, }4 t- K# S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
e& s* }$ n9 A9 m /* Activate the state machines */
% ]4 \& R" L, ~9 V McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: E; J. Z3 {& m1 m" d8 E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* ?9 [2 z% P. {6 i$ s2 ] McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);* ~3 _# U: u. O7 W' e/ d4 R
}3 Y, M6 d- h* F& ?3 i1 Z: I3 H
9 x- \5 v) G& j% q) {& n* q8 n
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