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我的McASP配置分别如下:( g6 _$ u( B# d; K
管脚的复用设置是:
( B1 ]7 ]$ i7 e0 p/ Q+ Tvoid McASPPinMuxSetup(void)7 H/ {- f5 l# c( m* g
{
, Z3 i9 h" `0 h5 g! O% |$ T unsigned int savePinMux = 0;
8 W; F# _! w) k% s savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \$ n" L" C5 x; a/ D, N ~
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
5 D2 K( D& a& J( G' a SYSCFG_PINMUX0_PINMUX0_23_20 | \7 Q/ u, r/ t- i* E
SYSCFG_PINMUX0_PINMUX0_19_16 | \
. Y- L# q( G) ]8 k1 k* }% y0 x SYSCFG_PINMUX0_PINMUX0_15_12 | \
Y8 u2 |4 P+ z" Q# w/ b SYSCFG_PINMUX0_PINMUX0_11_8 | \( g2 y9 v1 d* Q" K- S
SYSCFG_PINMUX0_PINMUX0_7_4 | \
1 @3 V# |$ w: o: H SYSCFG_PINMUX0_PINMUX0_3_0);- q a0 k' q" s! q: V
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
) Y/ K! L& r/ W, j" p- c (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
6 L+ {8 J4 n3 d PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \8 E6 I5 H9 w) ]- X/ d' ^
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \) d2 d6 s7 e" H9 a- H; E( \
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);6 y' o# y6 v3 z: h
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \* |- A, }' C _7 M) h
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
+ I# v4 g: P+ r( |2 z2 ^ SYSCFG_PINMUX1_PINMUX1_15_12 | \
1 o! N2 g8 j- [; Y0 o SYSCFG_PINMUX1_PINMUX1_11_8 | \
/ F* X6 O6 e x# ^+ ]8 b( M SYSCFG_PINMUX1_PINMUX1_7_4 | \; I3 R& z6 r5 f3 v5 u& v
SYSCFG_PINMUX1_PINMUX1_23_20 | \+ n5 z% D6 g: A1 l
SYSCFG_PINMUX1_PINMUX1_27_24 | \
' [0 C7 P* A, f, _ SYSCFG_PINMUX1_PINMUX1_31_285 x* Z7 J" G! c5 I2 G7 g( Q
);
3 k9 {5 O8 `% N- y HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
, Z8 J) U9 C1 M8 t5 W5 H) I( R (PINMUX1_MCASP0_AXR11_ENABLE | \: O: N' C8 ~; H; Y L
PINMUX1_MCASP0_AXR12_ENABLE | \
! l( S, S8 _) ? PINMUX1_MCASP0_AXR13_ENABLE | \9 o7 `6 a" I" H
PINMUX1_MCASP0_AXR14_ENABLE | \
! i' {7 \# g6 K- _" V9 H5 @ PINMUX1_MCASP0_AXR8_ENABLE | \
# R' \- C [) ^1 Q7 Y PINMUX1_MCASP0_AXR9_ENABLE | \
! Y3 C* ]1 n4 [( O6 f* \ PINMUX1_MCASP0_AXR10_ENABLE | \
! g' P/ a# w# i$ o3 o savePinMux);# ~) _. b# ^7 i- ^4 Q! M2 s0 I; ?7 J
}3 C; U* U' l: ~5 d4 e
& @9 M- `% |' I& }# ~: u1 f1.McASPI2SConfigure(); McASP的配置程序如下:
& R6 v" d7 D! V! _! N/ s/ Ostatic void McASPI2SConfigure(void)) f9 a/ Y0 s5 B% f1 r1 R3 |
{6 i k. U3 j# h8 t8 C% U4 ?/ }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 ?6 l* ^& @/ k) g0 s/ ]6 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
0 d- h$ H5 s) ?. L3 B0 m" n
$ [, T# g( v$ X) S2 X /* Enable the FIFOs for DMA transfer */! Z4 j. P$ C' F$ l
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
( l4 F- g7 d3 d( `// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 k: |" @. M& z' L X/ z
* K: C2 \1 {6 }# }; r /* Set I2S format in the transmitter/receiver format units */
+ U2 S2 e. T5 J' M McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 C z2 ?9 S; A& I2 o0 R$ B8 | MCASP_RX_MODE_NON_DMA);+ A& Z j) y: p# f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# n7 a/ [0 [, Y- t( H" N
MCASP_TX_MODE_NON_DMA);
9 F) D2 f7 w- C$ C1 e' I+ W6 {0 \8 e5 p6 y+ Z4 {* i3 c8 n4 D$ |9 [; ~
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */" w$ P! C4 B" u0 n# ~$ h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' {" p6 o0 { j ~1 w MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 D7 v2 N( \ l' h3 E McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - r. c+ N! n( i: a% {( v) x
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
( }) `' ], f4 }- R4 u
! i' O6 ] Q% ?# \; s$ k /* configure the clock for receiver */
) e" Y* T* d0 _+ e0 H+ E// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);4 B1 T9 b% q: @' z: J3 q. T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 i2 u2 [( E/ e" t3 M6 S- G McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 l0 U- n# C0 S7 L1 w- ^& M* V8 r McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) I8 o; X* Q" |
0x00, 0xFF);
F- H3 v0 G3 a/ @% c1 E( b: k Z0 v; t
( m. H( {# z$ e: d6 x /* configure the clock for transmitter */$ p/ B. ?% K1 ^/ S/ A" ]" \
// HWREG(0x01D000A0) = (0x00001F00);
& P+ h' ~0 s; i! J/ u; z6 ~% M// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);2 k* [2 {/ ?! T& b; T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
2 k% z3 K+ j. d( N. f7 X( C McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 A- h4 I" W1 M; r! f McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, b5 Y/ R9 s4 b% y; z& g
0x00, 0xFF);
2 x6 }* }8 x( n, M- A& `
* I H7 S6 [8 M4 o" D /* Enable synchronization of RX and TX sections */
. v/ w" [ Y& W" A' f! h McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);; ~7 _/ B7 B5 t! G- h- w& L' L
8 W8 }) j* p) m) N /* Enable the transmitter/receiver slots. I2S uses 2 slots */" I' z" t1 D$ j! T: k. l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 D$ L, {/ Z0 W# t! `7 L. h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! W- x1 A- H$ F$ a/ Y
; z, c! j3 |/ J0 t /*
( t! `) h' q+ L- J5 M0 L, A$ j! g ** Set the serializers, Currently only one serializer is set as( s2 [( i- B: r' A i* l1 C
** transmitter and one serializer as receiver.6 W7 d5 v1 T/ n9 F; Q
*/
) V" G3 W, R& c! m. G9 Z5 [, K McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 l$ j; q+ f/ c+ ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);2 ~# t) E' B: C4 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
4 A5 b3 d* w. K/ r3 q' K7 C McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
3 p: ?. E8 O/ P% X5 L' K( T5 F) R McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);1 l5 @& f6 _% L0 l2 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);7 P' G) G5 U7 _5 `' A2 }- C
6 k2 Z9 P+ @ i8 [7 ^/ O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
5 l- h0 c8 L9 d
& n0 N# ?( w0 r. o5 u" P /*
8 x2 K2 N; V8 b6 j8 u( A/ A ** Configure the McASP pins
, n$ u, d& G* A ** Input - Frame Sync, Clock and Serializer Rx
: |: f: T, F5 l8 N/ o0 F% M ** Output - Serializer Tx is connected to the input of the codec
3 Z5 }' V* t. V5 m+ d# Q */4 q5 e& y) A0 z8 ]5 x( y4 b( b6 V1 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 E' [9 M* q! s$ Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,3 q1 s2 I7 Y) J0 e+ w
MCASP_PIN_AXR(MCASP_XSER_TX)
" U8 F u. ?+ o1 \! E5 Q& X | MCASP_PIN_AMUTE
3 t8 _6 ?; m! ? );, ^- v7 ]& T L+ c1 G: c7 ?1 O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
6 n$ W3 F2 j/ I- Q2 ?+ G MCASP_PIN_AFSX" j7 O7 G1 ^' w, ~% f5 i% B
| MCASP_PIN_AFSR
0 c% R7 E3 u% K1 k2 i" I | MCASP_PIN_AHCLKX" l9 h5 D+ C5 Y* K0 F
| MCASP_PIN_AHCLKR* J' P; J; y4 V0 f! E
| MCASP_PIN_ACLKX9 b& g+ U! p: [; C' h+ l: U# _
| MCASP_PIN_ACLKR
" ]% o0 i/ V8 [6 H" O' Z4 P& O4 U | MCASP_PIN_AXR(MCASP_XSER_RX); ~8 D, n" ^2 B4 e
| MCASP_PIN_AXR(1u<<(13u))0 T6 l/ l3 ]# b3 `% c* M
| MCASP_PIN_AXR(1u<<(14u))' U, `! N4 Z+ A5 H4 {# L
| MCASP_PIN_AXR(1u<<(8u))
9 S. d/ {; Z- F | MCASP_PIN_AXR(1u<<(10u))1 d4 U* |) H7 G4 S1 {& z) d9 f3 K/ B
| MCASP_PIN_AXR(1u<<(11u))
6 X; l( ]/ ~! d+ W) p7 d- f0 @ );, x& P# v7 P& | Y
6 S* F: M& Y4 J) E* t/ ] /* Enable error interrupts for McASP */
' I4 b; o* X ~0 \- l McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,. m- a' A' L5 g7 Q
MCASP_TX_DATAREADY
0 t, w/ }* t. E d) M8 e | MCASP_TX_CLKFAIL
! o; e- y8 O7 s5 o8 O | MCASP_TX_SYNCERROR
. W d6 s/ H6 _2 Q5 D | MCASP_TX_UNDERRUN);
2 A+ X0 z2 h8 A0 h3 t1 A6 A
5 ?% c% S, H6 G McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,5 w% v% a9 b u; M# x: e
MCASP_RX_DATAREADY
* Q" V8 x( h/ n5 J& a | MCASP_RX_CLKFAIL0 i) l! O; `! K2 c# P
| MCASP_RX_SYNCERROR " P6 T8 C, @6 J1 R c
| MCASP_RX_OVERRUN);
. u e. X" Y8 q" k" ?//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
O- f# P/ l5 \- s
4 f. B7 O! U. Z2 u8 B* {: S" @}& D) E1 J' d- r
( f! S! f' T% U0 Y/ V9 n+ |! v& z
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句+ p" L8 V% {+ Z( ]
static void I2SDataTxRxActivate(void)& G% |% h% s" \+ _6 z
{
( f7 P$ _% `* A* j6 y: q /* Start the clocks */
- M1 Q/ W* k- s! \ McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 ~2 W3 ^! w- d' i; X# Z" o McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
5 c8 q$ P" M# G. @5 C" t Y2 \' ~8 Y9 t9 V) X) P3 h7 z8 f9 v9 j
/* Enable EDMA for the transfer */
& U0 B; _5 l/ p( L. C Z# t$ p// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," Y2 y* m% i( H$ A- Q
// EDMA3_TRIG_MODE_EVENT);& ]- D% \' W- ]% `0 ?: Y% M, v
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. x( F5 f6 M5 J# I7 k' J# D// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);# @6 @# J) T. O/ X: q% q+ y
/* Activate the serializers */1 m8 `4 |9 }& f" j* Y K- c2 v, N! c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* c/ ]0 u) r' e4 E4 l McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
# J0 A. N# i- D( L% R /* make sure that the XDATA bit is cleared to zero */
" j- D6 ?8 L F* s while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);& E0 O1 j4 ^0 @ I+ ?
/* Activate the state machines */3 Z6 ^8 e8 k8 e3 C/ I6 _/ ], |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; n' o s3 l( V5 Q: B J+ C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 X$ i1 t2 z( f Y+ }% `1 B
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);& v: L: O- J% @6 [% H
}' U; ~1 n9 j8 }; R2 {1 H0 R
+ [8 N$ `' ~3 r- c4 D4 W |
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