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我的McASP配置分别如下:1 r; n( I' v! N3 c$ G: {
管脚的复用设置是:- L* U' X( w3 p: {2 c8 y
void McASPPinMuxSetup(void)
4 t% _2 q% m& l1 J5 }: o4 ]. s{
G& f" T8 ]0 r5 z2 G/ _9 g unsigned int savePinMux = 0;
. o0 P) f4 n0 a, J+ j savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
; D3 ]0 L9 } l# A- R ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \; T6 S& S6 ^7 X" b" M- u
SYSCFG_PINMUX0_PINMUX0_23_20 | \5 k; P$ U. V! ~) L& v6 i
SYSCFG_PINMUX0_PINMUX0_19_16 | \% H0 k6 |5 ]( c
SYSCFG_PINMUX0_PINMUX0_15_12 | \
7 ?6 y7 ~& o1 R5 |" J SYSCFG_PINMUX0_PINMUX0_11_8 | \
$ C# X4 {9 h) h5 |; ?3 u SYSCFG_PINMUX0_PINMUX0_7_4 | \
8 w9 ]# d Y i# s; }2 F- C SYSCFG_PINMUX0_PINMUX0_3_0);2 Z: T2 t# y, d, D% X
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \' D3 y2 i' v* _) w7 C
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \$ ] w6 L; o+ I# Q, l+ X
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
: f" s; {+ _; L* U PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \0 `# k8 T- n2 G$ _$ Y, ^
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);* Y9 H/ T E1 s- f7 E8 Y; s; [- q
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
; U$ Q( d* M6 o3 I) {, ~5 I ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
$ D9 }# u2 o1 l SYSCFG_PINMUX1_PINMUX1_15_12 | \
9 q$ R- M, B: s SYSCFG_PINMUX1_PINMUX1_11_8 | \
# L+ C5 E" d$ Y/ _4 r# j0 F! G# V SYSCFG_PINMUX1_PINMUX1_7_4 | \! e7 r; Q$ N% n
SYSCFG_PINMUX1_PINMUX1_23_20 | \
+ J: P5 f( U/ e' i7 L- U3 S SYSCFG_PINMUX1_PINMUX1_27_24 | \. K+ y, z. r$ `) U! M4 A
SYSCFG_PINMUX1_PINMUX1_31_28+ P5 b* N4 Z& X) F
);7 M% v. \! ~% g& i" f/ t2 y7 J+ N
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \& T S5 J' }7 X: N: ^$ L% l1 j; U
(PINMUX1_MCASP0_AXR11_ENABLE | \5 p7 `/ T9 v8 t7 `
PINMUX1_MCASP0_AXR12_ENABLE | \
" Y- l$ u! |& Z3 B PINMUX1_MCASP0_AXR13_ENABLE | \
( f) L, Q8 y# `/ `- x* e PINMUX1_MCASP0_AXR14_ENABLE | \; e( Z& \$ [6 G
PINMUX1_MCASP0_AXR8_ENABLE | \4 q3 L; |1 H" s! K" K. l
PINMUX1_MCASP0_AXR9_ENABLE | \
2 _6 \" n3 p+ `* b2 g PINMUX1_MCASP0_AXR10_ENABLE | \
/ `# }2 K( f4 i7 x. j1 A0 ?% J! J savePinMux);
; b0 A, B, t7 O& D' {! n4 v" Y}
9 a' z# }0 s$ L7 Z7 V3 x# q! [
1.McASPI2SConfigure(); McASP的配置程序如下:1 v4 y& \1 o9 X) H! k B
static void McASPI2SConfigure(void)
% ~7 ?- m r- k r& V{
/ q z! D# a1 C* ~' u McASPRxReset(SOC_MCASP_0_CTRL_REGS);( `8 f% ^3 M) J; }! L. v
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
$ I# D! q5 i$ I1 W
+ k9 f* J* p7 t+ f: v /* Enable the FIFOs for DMA transfer */
7 u) P: W$ q# `1 u4 ]// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
2 `0 e9 C4 s. c// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 S0 S( e: i) k( p
" S0 L1 f' v. O: F! |% P! E0 { /* Set I2S format in the transmitter/receiver format units */
: I- A3 B6 Q- W9 u McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) m3 q, B+ f e6 Y4 P' \( B4 o) n6 m
MCASP_RX_MODE_NON_DMA);
- H# w! Y( [' `: C McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. Q! m9 V; |1 R; p& w MCASP_TX_MODE_NON_DMA);' ^/ i# S4 N' I5 m/ h8 T7 V
: }- E! o' S3 a5 B$ b
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. L$ ^! s7 s: W% Z% H McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( U3 K, n- Q) N) h l- Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 W$ k8 b9 s" f# ]9 |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: z& o1 \+ [9 Y7 F1 a. q+ t0 e MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
4 I% m( w: \$ Q8 g) K4 w4 W6 a
& m; h! O0 V L% a0 @ /* configure the clock for receiver */4 O" v' z$ V2 ~9 ~# [7 u
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
* Z" o8 `2 x% O ^+ ]0 ]8 N McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- x, k+ |0 }/ X McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);, E1 Z6 K3 g* V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 Q' X2 I) z5 {0 S+ @/ P ~" z 0x00, 0xFF);/ E( {0 ?+ r5 n4 F% U
0 @ H! {. {& w
/* configure the clock for transmitter */6 {0 U7 u8 [+ | u+ W4 f
// HWREG(0x01D000A0) = (0x00001F00);9 u' u6 y* J, r7 s& D- P
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);- Q4 z/ A3 I# @5 ?! i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
, l9 {+ f1 n$ m9 f8 k& o McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);1 Y9 N" f7 i- s0 x- r3 {* J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& F2 j3 R) _& q2 z; P
0x00, 0xFF);
, c8 H$ M4 ]$ R' c: q
/ ?7 e2 P6 x$ ^ /* Enable synchronization of RX and TX sections */ - Y ?# B! ]$ z$ p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);- b/ k0 b3 |, p: Q, u! Z: {
7 b7 d8 k* N7 F/ E# t- O2 X6 g+ T: i /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ p) }% @* l5 n& x0 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 n; Y. d# R' @& a% C McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 T* l2 S8 O; s: v' q
* n z; S( @* L( d0 e+ r, K /*
) r- T+ p% s9 ?' w, r; |# u3 U ** Set the serializers, Currently only one serializer is set as. N+ X* X1 f& R o
** transmitter and one serializer as receiver.
' P( ^* i4 I3 W$ S */, {: |% o* `9 h' _* W: F$ q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 l1 t( m+ t9 ^8 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
- M% V: `) L3 L. k# b1 T McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);; t: q2 g" E' m% r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);+ W8 G T9 ^1 h2 h8 r L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
+ p+ ], ]. {' B McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);! Y1 v* v7 r$ A2 i9 |$ v* B
9 g9 Y9 M" A b. N( O McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
* @) q: A" E- k8 N( H7 p) S
9 O* v; W i5 q; O+ a$ ]! w! i& Y /*
7 K5 K8 y8 v6 A% H% F ^6 ~( W- `6 q ** Configure the McASP pins
' V% Q, d: N+ l: s2 h; c) r$ c6 B' @ ** Input - Frame Sync, Clock and Serializer Rx; z- B+ z ^9 d8 `+ s5 X
** Output - Serializer Tx is connected to the input of the codec
& a8 P0 o6 Y2 ?, i" f/ u" D. V8 t */7 ~/ Y1 [/ _( {- S- X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ _ {0 F& ^* N1 O5 z5 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,) [8 f2 K# X" N4 L
MCASP_PIN_AXR(MCASP_XSER_TX)
4 k# i# m9 u. V | MCASP_PIN_AMUTE
9 I0 N+ m k% \8 Q8 B, n; \ );
. B' [, b8 Z9 U$ t McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
/ L7 Y2 m6 x, T, \ MCASP_PIN_AFSX8 @0 z; Q1 ~% ~5 X2 `
| MCASP_PIN_AFSR& r/ S' K G9 W( [6 D3 X5 ~
| MCASP_PIN_AHCLKX
3 P; X* L6 a# l& j6 @3 D) P | MCASP_PIN_AHCLKR
1 L: t; F/ ~# H5 u0 [+ M7 `$ z | MCASP_PIN_ACLKX- G, Q0 s, w) v2 P$ f
| MCASP_PIN_ACLKR
: x# g; z) ~ ~0 B, f- _3 o | MCASP_PIN_AXR(MCASP_XSER_RX)
2 c8 Z5 U! [! N: `3 r. X3 n) G2 } | MCASP_PIN_AXR(1u<<(13u))
# a% ]/ g8 M5 y. F! j2 C8 Z& ^ | MCASP_PIN_AXR(1u<<(14u))
7 }; u6 t, }: C | MCASP_PIN_AXR(1u<<(8u))
7 I( A; s$ W( b$ ^3 X | MCASP_PIN_AXR(1u<<(10u)): Y+ i& o4 n0 D2 l* c2 w* J( m
| MCASP_PIN_AXR(1u<<(11u))
1 P, q, M% F `4 E7 @ );* b& w K A s2 v
8 w# } K {% s+ i$ f
/* Enable error interrupts for McASP */
8 Q9 E. M1 h$ Y5 |, R; T' Z: T McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ ]9 t3 p$ K0 ~( V MCASP_TX_DATAREADY
" H( q( {7 E4 W& Y$ L9 e | MCASP_TX_CLKFAIL 6 V! R0 E2 ^# K
| MCASP_TX_SYNCERROR6 N% i- {8 R( g- M2 z$ Z! p
| MCASP_TX_UNDERRUN);6 z) E* s8 ]% L" h4 E" C
5 @. B$ v k; I; y1 | }9 o; U McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
" ?1 `* b) h" x- X) V. v MCASP_RX_DATAREADY
: {1 Q- h4 {2 O& R$ e& v7 z | MCASP_RX_CLKFAIL6 P0 h8 Z. }5 ?" \$ |! F
| MCASP_RX_SYNCERROR 1 g# e/ h/ u( m5 Q3 T" s( Z
| MCASP_RX_OVERRUN);
7 C+ v) P, m: R- t3 F//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
3 i; f# j, B) F" L) ]; U
! V; c+ }/ Z4 S U}
( k9 ~, [0 F4 J' k$ j, b0 r$ U) N+ K, E. v
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句) J5 d5 w- {* j0 @- p x8 {
static void I2SDataTxRxActivate(void)
- W* U* O4 D U/ G4 |{
6 k E( j' S1 B /* Start the clocks */
& J [5 |7 W- _! P4 q7 f McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% P1 L" Y {% l$ @+ s McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);% v! \$ u+ n& a# }8 L6 m
* t0 ~4 x, q. S: a3 u0 J# H0 o7 x /* Enable EDMA for the transfer */
; I6 V8 q6 C* M C3 Z/ z0 p0 S+ B D3 y! n// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 j0 E |) M! N6 m$ T// EDMA3_TRIG_MODE_EVENT);
. F% l9 J1 B. w4 H+ |1 n( j* b// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 W% X, I/ M; h5 ]7 I4 E# X// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
; z H A( k4 n: x) u0 g: s9 { /* Activate the serializers */
7 f' H& U- r4 L0 S McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 |# W0 ]8 t5 f, h' P1 v' o: Q McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);/ o4 ?8 N: d' B; c9 Y) D0 y2 t
/* make sure that the XDATA bit is cleared to zero */: h4 t h7 t# Q) D! Z6 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);/ I2 a4 [9 }( F" {0 n. A
/* Activate the state machines */
4 v% ^2 g2 u; E7 T" W# v McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 {2 ?9 }3 K1 d& s& T( ? McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. }* E V$ q' x& q% g9 ~& P o. c8 C
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
( S& o0 _3 S q5 M9 g$ j: H4 N}1 J4 X0 \' o8 M* z2 @
8 g6 ?9 m' W6 } |
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