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我的McASP配置分别如下:
* @1 X6 M# x' R% }% c' N7 w管脚的复用设置是: D. `4 k9 t+ X& s; I/ \- t
void McASPPinMuxSetup(void)
3 a- @5 p5 N( J{
! q3 E; D/ C) g: k$ r unsigned int savePinMux = 0;
5 m, C3 @# a# _4 a' i4 j savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \# p' E& G( S$ f2 q
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
% r0 Y! i6 B1 y. |0 G) \3 F SYSCFG_PINMUX0_PINMUX0_23_20 | \" c' b" |; Z* x3 ]1 _
SYSCFG_PINMUX0_PINMUX0_19_16 | \9 c: f; T0 z$ D8 j
SYSCFG_PINMUX0_PINMUX0_15_12 | \
3 M+ b% ^+ M% z' W; v0 T& L$ f SYSCFG_PINMUX0_PINMUX0_11_8 | \4 l; g- ~- V1 R- B* p
SYSCFG_PINMUX0_PINMUX0_7_4 | \
, C1 B6 G) \& b9 Z9 H* c' l8 x/ Y SYSCFG_PINMUX0_PINMUX0_3_0);* n8 q5 `0 P# Q5 x& S1 |' ?6 k
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \ X; t' R% H! i4 L& _0 c
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
- p/ C5 m/ l: W+ C! ~+ M PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
7 ] Q) O8 e4 S" K7 t PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \9 v" q; O5 {" P! S2 f
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
- } ~2 V/ S# S: ~ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
( T5 v- _, W) o$ h4 o: d& z ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \5 M7 V- J9 c+ Q; q
SYSCFG_PINMUX1_PINMUX1_15_12 | \
# n, `$ @ K# d& u9 `: G2 u SYSCFG_PINMUX1_PINMUX1_11_8 | \7 R( H3 z- y$ y
SYSCFG_PINMUX1_PINMUX1_7_4 | \' X' V" I, Z9 U# p% t9 M
SYSCFG_PINMUX1_PINMUX1_23_20 | \
. u, C+ u2 w+ o SYSCFG_PINMUX1_PINMUX1_27_24 | \( c" p# h* z8 n4 J, q) B
SYSCFG_PINMUX1_PINMUX1_31_28
. @3 E8 v& y& K$ ~: L );
! u/ l9 }, o$ G I* c HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
]0 c4 W3 G& q (PINMUX1_MCASP0_AXR11_ENABLE | \; h' E4 r" h. D8 D/ i( c$ ?7 l {' p! [
PINMUX1_MCASP0_AXR12_ENABLE | \2 R0 u4 ]; {; _ `- S
PINMUX1_MCASP0_AXR13_ENABLE | \
: e2 e% O% [; @9 k/ C PINMUX1_MCASP0_AXR14_ENABLE | \- D: I, H0 i% X4 l& ]% B+ t0 T
PINMUX1_MCASP0_AXR8_ENABLE | \
3 n2 B% G2 W7 U# O0 L PINMUX1_MCASP0_AXR9_ENABLE | \
4 `& Y& R8 P+ _ C: n4 y. y8 ~ PINMUX1_MCASP0_AXR10_ENABLE | \
3 @1 e# L _, [. x savePinMux);
; G; q$ _. g" V# V}& g' s) t8 ?0 ~/ b
# f8 f' i; K0 l' n: i) V* u1.McASPI2SConfigure(); McASP的配置程序如下:% i! n: h% g, C3 H1 M( g
static void McASPI2SConfigure(void)
0 I+ x) I5 @4 Q! v' I' Z{% Y' g# Z2 |$ G! ]0 Z& F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& \6 b' U5 q+ ^$ ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS);- r7 Y) V! m% N& }% b
, x" a1 m1 d# m# ? /* Enable the FIFOs for DMA transfer */5 S% N/ v5 |# Q% n0 `
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
3 U1 y4 D: R2 h* B$ |// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ q' n6 B3 b/ Y9 I' G. O5 d' S% r" M* e% o; ~* l& N
/* Set I2S format in the transmitter/receiver format units */! m) S: M% Q p4 w, H, i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) t& w( Y. c) [8 F/ ` q9 P, ? MCASP_RX_MODE_NON_DMA);
+ N8 U& T3 D5 b9 z4 P! k2 r% d McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, p/ u* n! q7 L+ h, L
MCASP_TX_MODE_NON_DMA);
. H! {/ p2 H% j' l# N# U$ x+ f1 V: ^1 X) C
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* p6 U# j0 N% r% `. T McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , I, ^7 G# H# N+ t( @4 N6 ~7 Q, h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 K3 H/ g! h. ~3 y q% i% R McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ n" q- \: I) e( k/ |0 J MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);( n+ {! _. r5 t5 L7 U8 A% r
. Q6 r' O% A0 s7 f9 ^
/* configure the clock for receiver */% l$ {7 V G* A. j
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);- X% [ U1 U( X4 s. O' f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 i3 J" l/ D x, Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- D- B6 _8 {9 d McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) P! `- x z' o# J7 A 0x00, 0xFF);
' T' i% I6 ?) I6 Z
" \+ [ S, j# x. W; A6 E2 d /* configure the clock for transmitter */
7 Z; G! F! a4 M" M0 n0 U// HWREG(0x01D000A0) = (0x00001F00);) E' e p+ G3 Z% w1 }3 V6 g
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);3 o; ^# \, g5 B5 r& X% _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
2 g9 v2 l+ ?0 K5 o9 ]! `+ R McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);; l9 b1 Y5 {5 G/ X( C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 I8 p: {% h% O5 j, v4 J! M8 w7 J
0x00, 0xFF);( C! {. Y b/ O5 o' O
& D' L2 q8 Z q! b* \% L& {6 z- f /* Enable synchronization of RX and TX sections */
3 h. K9 C8 b. ]; J! L! k" ]' ~ McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
8 J7 G3 n* Y9 Q* B/ R
# `1 l V7 R7 n' A# y! } /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 K" ?/ [: J- t) o* W4 ?6 b' Z* c McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ m( `9 L! u- h" o# G: F; T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 {2 n( j5 N3 }$ t
$ A, V7 \) B4 G# @! w1 W% R
/* G4 g% V8 ?; [4 O, |) j
** Set the serializers, Currently only one serializer is set as
! z- s7 o1 o ?( y+ O ** transmitter and one serializer as receiver.4 Q/ U3 e! D- g" c& f/ `5 V) a
*/
/ _: `7 C& k/ ]* l$ D McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" _+ ` G8 |/ X. L, k* E/ K# c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);' L- `8 B0 H' a0 w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);; D2 O9 [ D7 `! ` S/ Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);3 C- u- Q- ], F' y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);* V6 z6 W1 [/ [# c z+ x" _% E1 r, {1 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
6 p$ j# |0 n( R1 y5 w" N3 F1 S
7 m+ C) r' N3 G- f( f; X0 r4 f6 ^ McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
" t6 h# l4 q8 P/ @7 r
0 F$ E& o @9 T, e /*+ e* |! S I0 z9 u/ ~
** Configure the McASP pins
; d* d7 l6 g- Q) i, f% ]7 d1 N9 x ** Input - Frame Sync, Clock and Serializer Rx! T! P5 i' r; H+ \
** Output - Serializer Tx is connected to the input of the codec
2 c; a( Y. [0 N. a+ u- F; f */4 x2 @4 ?7 H' A* I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 X5 I% @3 d' [% A8 M6 }3 o1 N McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,9 x' U9 @ c/ U, T9 g
MCASP_PIN_AXR(MCASP_XSER_TX)
% H i3 f9 S- x0 l | MCASP_PIN_AMUTE
/ x. X# S9 q9 V9 z+ | );
* x6 a7 s& a+ }( r/ c } McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
1 i2 D( }1 V) C MCASP_PIN_AFSX( F1 P c6 L+ }+ Z7 R4 r1 {$ L
| MCASP_PIN_AFSR4 Y$ t& g' o% e$ F H- o% v) n+ o
| MCASP_PIN_AHCLKX( _8 M2 ?! O. |6 j* c9 G: p- X
| MCASP_PIN_AHCLKR
8 h: T2 ^$ m1 B0 q3 u% ~ | MCASP_PIN_ACLKX- ]4 t* W6 U; `( p& M) f7 h
| MCASP_PIN_ACLKR
2 h& I% z* h! v+ X. {! D* b% u | MCASP_PIN_AXR(MCASP_XSER_RX)
0 M9 v# x! Z0 d+ D: x" V0 B9 u9 I | MCASP_PIN_AXR(1u<<(13u))
- p3 U( v% @8 r% v4 z | MCASP_PIN_AXR(1u<<(14u)); A( O5 b* j6 p6 }! o" h( M
| MCASP_PIN_AXR(1u<<(8u))
0 P# G6 @8 t; j/ E8 y3 M1 ^) g& Q | MCASP_PIN_AXR(1u<<(10u))
+ A6 b- u, @2 \' j | MCASP_PIN_AXR(1u<<(11u))5 i5 {9 m. ?" j0 `0 ]
);% E3 p3 a+ \) d8 s
$ r/ C4 |3 O, D) g) I9 D3 f! R$ v/ y
/* Enable error interrupts for McASP */7 T9 Y2 E( x! ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,) d" K2 z. D; V4 z. F: x) u
MCASP_TX_DATAREADY; b% `2 ]! x. P2 n
| MCASP_TX_CLKFAIL * [3 \6 Y7 k/ u1 \; v/ S
| MCASP_TX_SYNCERROR
- P! ]: R# X. W& R4 m- y4 l | MCASP_TX_UNDERRUN);
3 F- o; S, p4 Y/ u0 R/ Z# M1 w9 W, ~, _" a
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,9 O* M& I- v- H( m# R
MCASP_RX_DATAREADY
; t5 }" H" l3 ]% O; p& Y2 t" m | MCASP_RX_CLKFAIL; m4 a* t! k: P! q. W
| MCASP_RX_SYNCERROR # N/ u! r0 o: B; I
| MCASP_RX_OVERRUN);
/ N5 v) v/ ^) I) R//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
: {* f" i9 x5 q) K7 K6 D1 h7 G) U: l7 {
}0 {0 b7 E, u$ [! [. T
6 [6 q) d" A+ H
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句) q. d7 k8 ]5 ?/ c. p1 y
static void I2SDataTxRxActivate(void)0 I# I( \; L( y) M# I
{. {2 p: S: p3 b
/* Start the clocks */
- K4 H, [ N7 y McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 g2 h% `. m! X$ R" ?+ i" ~ McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);2 y6 m: C/ \9 T! T3 i8 x
7 c4 [/ z# ~: a% |! x /* Enable EDMA for the transfer */
' E; Q8 s% B d3 C. n- L// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% P7 R- w* T0 H+ P- m
// EDMA3_TRIG_MODE_EVENT);. }( v6 R5 w# u' ~$ B' Z2 N
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 U! j8 l2 \0 ?( A8 \1 c' Y// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);4 W; Z8 [8 W6 O/ K
/* Activate the serializers */0 I- _8 J2 ]- W6 Z i$ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" ~) z' | i% g; W# s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 C( ^" X1 v, u7 s8 }7 e% | /* make sure that the XDATA bit is cleared to zero */
4 \% W4 I p4 ?6 Q7 d while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
& `: p4 f! `1 p: X+ v /* Activate the state machines */$ _7 v9 r: p/ b1 h+ C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& J7 X; [* \6 ?' x* b) Y/ k McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. u2 N/ C3 W) k' t: [7 Z* B& W McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);) q% f7 q) N5 h- C' X/ C. U5 z
}1 ]: i4 }; r4 }0 ?: N- ~3 g
- Y" C: F8 R5 f0 e% R; e
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