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我的McASP配置分别如下:
$ N# V1 P6 W4 M0 o管脚的复用设置是:$ ^7 x8 R' x# a& |* @! ^4 m
void McASPPinMuxSetup(void)
4 S! m c) F( ]5 O{! E- i8 L! Q6 h, [; V# I$ i w
unsigned int savePinMux = 0;3 J8 A+ Z- t& Q7 s6 q: v& A% i
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
- i7 ], r/ }, U& ~( O ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
C# a r9 g Z SYSCFG_PINMUX0_PINMUX0_23_20 | \
9 r4 w, a) o3 n5 A& C' }0 x6 x7 s SYSCFG_PINMUX0_PINMUX0_19_16 | \
% I2 G; I- E d! b0 l SYSCFG_PINMUX0_PINMUX0_15_12 | \1 J3 z) z, X+ q- y- Q6 j; \& F# W0 K
SYSCFG_PINMUX0_PINMUX0_11_8 | \
9 f7 Y3 c1 i- W$ V; j, `6 a7 G SYSCFG_PINMUX0_PINMUX0_7_4 | \/ F3 j" w- ]$ V, C* o1 h3 a a6 _8 [
SYSCFG_PINMUX0_PINMUX0_3_0);# t$ o$ ?% c, t1 L4 ]" T) J, H- c
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
' Y2 o& Z1 x: a0 q3 \1 B2 X (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
; b. J4 ?! \: N% p* J' G. } PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \, P/ Q S, e1 r f0 ^: a7 n
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \5 }2 N) @& P% c- j7 R- W$ n2 h
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
4 O5 W. M( b7 i9 t2 C: l: @0 s/ ^ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
$ I. D; l& W. z# C% T7 p ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
n* N4 f( ^0 Y4 s6 V$ c! w \ SYSCFG_PINMUX1_PINMUX1_15_12 | \; L7 o1 v7 @. h* T
SYSCFG_PINMUX1_PINMUX1_11_8 | \/ v) B5 Y. B- f$ ^6 J) f, J8 [
SYSCFG_PINMUX1_PINMUX1_7_4 | \9 K2 p# z7 h( j
SYSCFG_PINMUX1_PINMUX1_23_20 | \
$ T4 e" v6 l4 @/ t4 B1 z+ I SYSCFG_PINMUX1_PINMUX1_27_24 | \
3 ^% X. J1 R5 E3 m SYSCFG_PINMUX1_PINMUX1_31_28. h' s4 ?/ N$ G N+ C; r
);1 U) x' A: C" @6 B! L9 H _6 O
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
" N8 s8 w3 |9 B1 M' I (PINMUX1_MCASP0_AXR11_ENABLE | \
2 v$ \ B* c/ r. `" o1 C PINMUX1_MCASP0_AXR12_ENABLE | \5 e A& z0 W' B% D
PINMUX1_MCASP0_AXR13_ENABLE | \
/ w, t, {: j' [" m$ r PINMUX1_MCASP0_AXR14_ENABLE | \- I4 b1 r, Z8 k% c
PINMUX1_MCASP0_AXR8_ENABLE | \
+ v. a& H E5 T* H; S PINMUX1_MCASP0_AXR9_ENABLE | \( _/ r/ K5 h1 b3 x5 r4 q7 d
PINMUX1_MCASP0_AXR10_ENABLE | \. w/ y1 ^1 U9 _5 G2 b
savePinMux);
5 y' ?& j2 _0 z" a3 q- P" `5 I}
3 p+ ]2 g" i8 o/ f$ ~0 p
9 {$ G8 }. l4 q$ j$ M6 O1.McASPI2SConfigure(); McASP的配置程序如下:& F% X5 V6 x8 m/ m! j# n7 G/ F6 F W, ]9 z6 [
static void McASPI2SConfigure(void)
9 K6 I8 j/ `& W{
1 r4 c' Z* r8 q; n: A) V2 L McASPRxReset(SOC_MCASP_0_CTRL_REGS);" X/ K: r% N7 Q3 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
4 `4 H6 g8 a0 ^
; t; ?! L; J4 P) P7 K /* Enable the FIFOs for DMA transfer */3 p! O) y- h" P
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
! }# F0 G; ^+ k( l3 [. {) x% v) |// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& j$ T" g( Q) Y, ?
1 c; [2 s+ _* n+ c- b /* Set I2S format in the transmitter/receiver format units *// |5 U& I; c% S7 {4 L7 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' i; W2 ]* ], j5 F9 ^0 F MCASP_RX_MODE_NON_DMA);
( ?3 M8 Z5 H. ~2 V- b8 K' r5 T McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ^ e' q% p/ Z' q+ ? MCASP_TX_MODE_NON_DMA);
" D% [ q/ T) M' O% n
W1 x% `7 Q9 V( [" ?: S /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: c& T6 q. H6 P+ e% o/ _7 a" q! `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 \! `; E7 H( H# ^3 N MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 x$ v# V# o6 j3 {* ]0 w4 E4 y6 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 T, ?2 S3 \$ U, @6 U/ Z MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);* ^# q" u% a7 D# E _, j, h; b Z
- W x9 [5 o# U5 D! U8 M4 i
/* configure the clock for receiver */. t" a# p3 Z( A
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);5 }8 r& r) j& D, U1 m7 e! Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); N3 g: |1 X2 d: E; [9 F5 B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& m5 F7 Y/ Q9 w4 r2 X McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 D: j) N' J, J/ P: }7 M' a
0x00, 0xFF);
- b9 c y8 L( k, W P( {: V5 w- T4 w U. N/ H' n& U4 {
/* configure the clock for transmitter */7 n: x9 e; y7 ^( a
// HWREG(0x01D000A0) = (0x00001F00);$ Z# Y, y7 f( u3 ?( S( P f" x
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);. p8 ^3 M+ y( T6 M6 c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);5 P5 d$ M. N& O6 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);5 h9 B* G- s, B5 J6 u' L: f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 o' `$ e5 |+ V# j) p3 f! x 0x00, 0xFF);. ?* `/ T7 C% d( O2 H$ D5 r
& r: S2 R0 q, n /* Enable synchronization of RX and TX sections */ 6 O: O# ]8 O' R3 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
0 u, r7 a2 f. l8 J$ C, u2 N5 R7 x' l) `9 N9 [) @, F9 c& R
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 q) ~! a% g2 D" i* d* K McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! W8 w* \) H7 I- v0 @6 m* d McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ^. ~ P6 G& S) `+ u. Q
4 N! o2 l7 b- b- F /*( Q+ u) O$ ^( _$ [+ _3 x
** Set the serializers, Currently only one serializer is set as9 w, x' c( q ?+ ~
** transmitter and one serializer as receiver.* B8 U3 e9 Y+ k T1 @7 e( ?
*/0 u; {3 E) c& T7 E) w, m; r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) T" t, M; X/ l3 d& P2 d; o. P! ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
! V8 n# u: K/ d7 V McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
4 u' Y1 D8 @, D% @" `: h* j& Y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
& f, r% l7 O8 I9 d' k+ u, r McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
/ U/ ?2 d6 [/ U; J( l6 a3 e$ d+ x McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
" O! y0 k h1 P6 Z1 N5 A) T: v7 ~/ W4 Y- T7 N/ \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
; t( t* a* ^' I; i1 O5 k8 B& r) L3 V. Q4 K+ U
/*/ @" C9 d; _4 D
** Configure the McASP pins , M- T* m: m. B
** Input - Frame Sync, Clock and Serializer Rx
2 t: O# ?. |2 ~% ^, R ** Output - Serializer Tx is connected to the input of the codec 2 E9 R1 ^+ [& R- m m7 _
*/
8 C6 j3 X- f3 ] McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; ~: Y4 q# e) C9 J; n3 Y R McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
6 P) y T) i: y9 m' h2 N0 k MCASP_PIN_AXR(MCASP_XSER_TX)
$ D$ p6 h; \0 }/ p2 q) U, s/ K | MCASP_PIN_AMUTE
" W. e; u" x) L" V7 q* m6 i );
6 E ^' c. V( {8 y McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
|$ i5 Y8 y/ f3 G# g5 a MCASP_PIN_AFSX; F! h( F& Q, ?, H' U
| MCASP_PIN_AFSR
) b/ @& E# Z+ V, o | MCASP_PIN_AHCLKX
* ?% o- f9 t/ d9 F* P5 l- r | MCASP_PIN_AHCLKR
0 [2 k& E0 c5 m! w+ ?. l | MCASP_PIN_ACLKX- U. K1 n# ?* D- |
| MCASP_PIN_ACLKR
9 Q1 g% w6 k; r | MCASP_PIN_AXR(MCASP_XSER_RX)- e6 C( K9 \/ u$ ^; P
| MCASP_PIN_AXR(1u<<(13u)). j0 P6 m! Y1 C5 Q. f7 a: L9 d: R
| MCASP_PIN_AXR(1u<<(14u))
% c8 U8 C1 e% z$ w/ Z- [ | MCASP_PIN_AXR(1u<<(8u)); b9 F( c! Q+ P z
| MCASP_PIN_AXR(1u<<(10u))
3 [2 |0 A9 f- Q. o! Y' c0 {2 d | MCASP_PIN_AXR(1u<<(11u))
" v. ^2 F0 b8 B );
* b, ~; o/ Y1 w# n: A: C
8 H% \$ d3 y7 } /* Enable error interrupts for McASP */$ X: f$ ^3 Q% }! n* K3 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
3 Q0 Z! R" T& {# d) H MCASP_TX_DATAREADY P1 v6 k1 a: k7 H$ f
| MCASP_TX_CLKFAIL
5 D. b( @+ _. |& J, ^7 l" I, n | MCASP_TX_SYNCERROR% ?9 ^! R; D" {4 ~6 o
| MCASP_TX_UNDERRUN);
$ H9 l; C6 d0 i' q# z8 S6 G! y( M3 X* V/ ~% W" D8 Q8 S$ ^
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,4 y! o/ ?( B L6 p) G
MCASP_RX_DATAREADY
/ z! k7 Y9 C' } | MCASP_RX_CLKFAIL
) y2 y. K4 z: E/ h2 ^: D$ |+ D | MCASP_RX_SYNCERROR
3 s$ A3 e8 x( |: F | MCASP_RX_OVERRUN);
; ~8 H( G9 f- p' M//MCASP_RX_DMAERROR MCASP_TX_DMAERROR3 W; B& ~' m- u; v
; H! v+ s# x2 S}% c+ w( Q9 P+ a% x; l! A
* `) ~% R3 x; K, P2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句( W& Y9 ~& |* q7 X9 n3 _
static void I2SDataTxRxActivate(void)" s: s4 A) d. S1 S! b( A% h
{! V, I* k0 R5 L! V3 B" w
/* Start the clocks */
7 {" X9 q( a% f McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 `0 E/ H6 O" P3 Z McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
. U3 i5 O4 j0 r4 m4 | }8 j- S4 `9 B- Q
/* Enable EDMA for the transfer */$ g% Q- M, k- P9 t
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 {7 M# V" v0 i0 H// EDMA3_TRIG_MODE_EVENT);
' `' q7 G, E" `// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 p3 ]4 g0 {' X// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
, l$ G; ?7 v0 ^ /* Activate the serializers */! O& e7 Y) v# ?/ v% |5 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 [: d' U/ O( w# d) ` l0 ` McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);1 N" v- d3 Y/ y
/* make sure that the XDATA bit is cleared to zero */$ s- Z3 j; H' ^3 U5 o3 f* P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);& J7 q8 \. Y/ F+ z
/* Activate the state machines */
0 U. r/ y4 n: F( j4 ]4 D0 X McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# j7 W6 z7 J: q8 K% M0 M McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 @! M5 | e5 r2 P( @ McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
0 }. @% h+ H' j6 \) J1 Q) A}0 T- h" z8 O6 t
8 A$ [# }% d5 k: b6 t |
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