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我的McASP配置分别如下:0 n" S9 f% b1 `; y1 L
管脚的复用设置是:7 O8 Q* W# e- c) L$ j
void McASPPinMuxSetup(void)
2 M8 p9 E- a: q/ a( p; j{) W9 d2 ~; B* A: m1 B0 M
unsigned int savePinMux = 0;
0 T' ~% C- U2 A& l8 k% Z savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \8 J ^' V8 i/ \
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
7 b$ |1 J; V: s) | k: g SYSCFG_PINMUX0_PINMUX0_23_20 | \
# W* e" q; V2 p' m SYSCFG_PINMUX0_PINMUX0_19_16 | \
& R8 F- ]: E2 @ c. ~ SYSCFG_PINMUX0_PINMUX0_15_12 | \
! U. y* B" A" g! ` SYSCFG_PINMUX0_PINMUX0_11_8 | \
2 A4 {5 L/ t# I3 g; H# p! m SYSCFG_PINMUX0_PINMUX0_7_4 | \
& a. P" z3 x! r& \ SYSCFG_PINMUX0_PINMUX0_3_0);
( {- ^* l J5 P. b$ K$ | HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \3 P& S# O' C; ?! L! |3 N. M4 s
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
: [% t/ @: t8 S. e, | PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
* L) j% o" l' G2 }+ L PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
2 i* B- P; H- ^, e PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
u" }: r, M# Q1 ~! [. [! k V% Y8 V savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \* _. k/ M# Y# B0 I0 p
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \. X' b+ ^0 q8 N: K) ?" x3 R
SYSCFG_PINMUX1_PINMUX1_15_12 | \8 P1 U; e; Q/ t5 o2 R% _ N
SYSCFG_PINMUX1_PINMUX1_11_8 | \ w, N, ?# m2 ^7 x0 y7 F) e
SYSCFG_PINMUX1_PINMUX1_7_4 | \4 \8 {0 j- @) U
SYSCFG_PINMUX1_PINMUX1_23_20 | \
; D4 \4 T/ i2 B5 w2 r; |3 m SYSCFG_PINMUX1_PINMUX1_27_24 | \
6 L% K0 I" F5 f8 B2 e0 E8 ~# V" d- W SYSCFG_PINMUX1_PINMUX1_31_28" @6 Z' i6 U7 a+ p, b/ I
);
I. B( _/ u) D( v% y. M HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
$ J6 S$ w; w4 _) Q) p (PINMUX1_MCASP0_AXR11_ENABLE | \# o- ^ M/ W8 x z: k
PINMUX1_MCASP0_AXR12_ENABLE | \
6 v0 p' R$ x5 q( T PINMUX1_MCASP0_AXR13_ENABLE | \. n* ~: G: h8 [) a
PINMUX1_MCASP0_AXR14_ENABLE | \4 p: h/ w: ?/ O) j
PINMUX1_MCASP0_AXR8_ENABLE | \( p9 Y' [/ H7 L. k# o }1 n8 ?
PINMUX1_MCASP0_AXR9_ENABLE | \& J& B- j$ |' u) r0 S+ q1 L1 x" T5 F
PINMUX1_MCASP0_AXR10_ENABLE | \+ t' \5 t( T/ y* o
savePinMux);
6 Y3 f/ E6 s- o" j6 x% q}# j, a. M3 C* J% z8 V- ^
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1.McASPI2SConfigure(); McASP的配置程序如下:& W& p( q7 F' k, ]" _1 V; I
static void McASPI2SConfigure(void): ^! x6 M2 `5 ^( l
{5 L2 e! p( L! p1 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, D& j. }4 V/ f) v/ C) ~- W
McASPTxReset(SOC_MCASP_0_CTRL_REGS);$ X* S8 f5 e9 K" r i" Z
5 E+ ]7 @; j5 |, g
/* Enable the FIFOs for DMA transfer */" o& B$ Y, ^ O6 e8 [' {( _, C
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
- d2 L9 n" A3 e5 k. r2 M// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 h+ U$ ?0 S0 n& Q# g; X; \/ h; t( h+ ~( h8 S
/* Set I2S format in the transmitter/receiver format units */: c1 O% w! t3 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, S. [5 c$ w% |
MCASP_RX_MODE_NON_DMA);2 z5 r! F1 b l. O1 m/ F9 k* e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 u+ U% w8 M/ ^1 T" n
MCASP_TX_MODE_NON_DMA);- i$ m/ F) |) V+ J I* F G
2 X2 T# V/ w: U9 Q% h
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
U8 u! \% S8 M* i, p5 l0 s4 I McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 C. g0 ~0 k0 M& ]+ O MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- _, N# M9 l, w* A0 x5 o/ _7 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! `$ { r' R/ I0 F
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
6 P4 L* i# Y& p2 I
, x' N& O2 c7 @$ s V% { /* configure the clock for receiver */) v8 A! Z `/ O- ?: i/ V
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
$ H( i7 i' |& d* I4 [) a3 v McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 ^# t' z a. B( }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ z4 C, f1 O. ^' z1 S3 T- b McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* n; x# d" X' _) @; e, s 0x00, 0xFF);
& }) x- ]: H7 ~; w" b, a3 T3 D3 f+ A- c# x1 Q+ l: l, m
/* configure the clock for transmitter */
7 h0 I' f- F' f& W4 C7 t& I// HWREG(0x01D000A0) = (0x00001F00);" A* F; r: z5 Q$ w8 X" w! H
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);8 `0 a9 ]( a1 x! p9 _, W t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
) T# S' ?# z; ^+ A McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 i7 f5 C& X0 g McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. r! q. Z( I2 ^& x 0x00, 0xFF);2 i3 h/ C# Q0 f
+ b, C) L( t( l/ f /* Enable synchronization of RX and TX sections */ 0 f, \# ~9 K7 z! Z0 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
. |! k% p4 w+ b6 d! L8 [& t Q9 p- v* G/ H4 x ~0 f8 Z; [, T
/* Enable the transmitter/receiver slots. I2S uses 2 slots */9 q/ I% G1 o6 W' z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. n+ s) V6 x; Q. B8 o: M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ K7 p0 c1 ]3 c$ c) A. _) k
( T4 E2 y, V; ?' u8 y2 a; } /*9 J. B' \9 m/ ?4 p* N W' a7 |- {5 H
** Set the serializers, Currently only one serializer is set as+ j% G( x& \+ |4 m5 [% R+ v
** transmitter and one serializer as receiver.
$ t& E5 J- S; O8 m$ T5 f7 ^ */
4 ^9 l$ t' {. N& `8 ]7 E McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% R5 A5 B& J7 {5 O% H& H McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
$ K* `7 O! D5 j/ W7 h McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);* o7 ?4 S1 ?2 R: ?& J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
' V4 c* o3 ?9 G4 g; q9 B4 c McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
/ Z4 o; w7 j+ a3 m McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
3 U: A: e3 N" k+ V
/ H6 C; P# K6 O- X: U9 U, h McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);& I9 Y. w5 M, v2 F+ P. j% ?) W
! t/ k [/ G5 c# `6 m /*
! x% [+ I6 R2 }+ s5 b1 \ ** Configure the McASP pins
8 Y$ }$ |7 Z: ?: h+ O+ ` ** Input - Frame Sync, Clock and Serializer Rx
7 C& d2 [; S0 b ** Output - Serializer Tx is connected to the input of the codec
& ~( l* [1 A8 ^6 a5 K) A */
5 |4 y2 a4 Z o9 H3 f# E McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 s! Y, S7 X) e6 ]- @- P4 F- k McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
2 V! B$ O: X% L, B+ a MCASP_PIN_AXR(MCASP_XSER_TX)
% I1 f9 S! L9 h. V. i | MCASP_PIN_AMUTE- v* _/ |3 r% F4 }$ E& U c6 z) n
);
3 b( q& X+ c- n McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,; r `$ g; _- b* v2 A( l8 J5 p
MCASP_PIN_AFSX1 `7 l C) \" J6 R
| MCASP_PIN_AFSR
+ t* `; Q/ K+ d6 s9 j# Q, _ | MCASP_PIN_AHCLKX
( {1 \) W- u) @$ O | MCASP_PIN_AHCLKR( p- L1 |5 q( k1 o) T$ V4 _. `
| MCASP_PIN_ACLKX3 ~( E' |0 s, [
| MCASP_PIN_ACLKR, Z$ q5 H# u: @! x
| MCASP_PIN_AXR(MCASP_XSER_RX)2 }: E# \( B ?' V
| MCASP_PIN_AXR(1u<<(13u))
6 K- \& q7 }: a | MCASP_PIN_AXR(1u<<(14u))
4 k3 u. U/ m/ P0 x) c4 k4 }4 f | MCASP_PIN_AXR(1u<<(8u)) O% h. g% ]7 G0 `5 L& `
| MCASP_PIN_AXR(1u<<(10u))
3 N2 p- P5 z3 ^9 G | MCASP_PIN_AXR(1u<<(11u)) S$ x6 p0 \. `8 N0 N7 V
);
4 Q% A# e- v& v, | |7 P+ M* ~
4 \2 m$ ]+ M, X- f; T6 I" K6 y; } /* Enable error interrupts for McASP */
! M; @# P5 h! y/ V0 }: B McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ w) I9 P4 O% M# X7 E MCASP_TX_DATAREADY" [ k2 Y* X* ?* p/ r
| MCASP_TX_CLKFAIL
9 }' E, F& z6 X8 h/ t; T | MCASP_TX_SYNCERROR/ w5 ^) B, c6 ?) _3 v
| MCASP_TX_UNDERRUN);4 _+ ?7 M! ~# s, B4 M! D
: L8 C, m% `- n) e$ E# _
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,$ f2 T1 q: J& i, `; t$ g
MCASP_RX_DATAREADY
' X! R5 A- i( h3 j9 @( X, x | MCASP_RX_CLKFAIL
! O: A, K5 p$ \- E8 { | MCASP_RX_SYNCERROR - I/ F$ ` W: m ]
| MCASP_RX_OVERRUN);
) P' Y+ ~ ? B1 D1 R Z+ v//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
! a- K; q3 x8 m ~* ]
0 f1 X+ \) {/ c! W. L}
- y+ n5 }+ m4 f. \) f6 P- G/ }( \' F- N
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
1 L0 ]! I X' v; ?9 n1 ]static void I2SDataTxRxActivate(void)
' t! D) C# Q' l{
5 g7 L* W9 B6 {3 q# @- P /* Start the clocks */
2 U8 \9 _$ o# n; ] McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 Y1 [* h# E p @- ]" s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);4 t+ f" M$ @4 p3 E7 j0 C) y# j- ~
: c) k7 B4 n4 O& {! @# V9 c) H /* Enable EDMA for the transfer */4 Q- t3 t2 N* {# V( t) E
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) j T0 _* w3 Q+ K5 g
// EDMA3_TRIG_MODE_EVENT);" u* f0 V h2 ?9 Q; E" i _
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,3 `% p: O' m9 c
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
' {) Q% o. Z! Z0 x$ M /* Activate the serializers */6 }& m3 b: { Y( b2 h) s) }' G" b# ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. j0 f/ I- k, E }, m! g McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);, _5 _7 X+ w1 A5 |/ p
/* make sure that the XDATA bit is cleared to zero */
8 C) d5 M8 x& l6 l/ V, V/ z+ R8 s while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);/ v: e" L5 W. P
/* Activate the state machines */3 {; g" [2 I7 X, T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# Q8 P$ w: `0 E: y$ T McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' Y4 [. T1 [( h& Y2 K3 ^9 S1 H
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
6 ?7 ]3 W& R- X: d# B/ [2 d- F0 {}& n: o8 V. j. F, A3 Y; }: |
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