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我的McASP配置分别如下:
, L& e* h- F$ `管脚的复用设置是:3 H4 x2 C' A0 u7 Z+ P
void McASPPinMuxSetup(void)
) G. I' U( g- V: P{+ s9 ^2 d& H) s' r
unsigned int savePinMux = 0;
( a2 \2 ~9 y; ?0 G8 S/ \1 L- K savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
' x# o' X4 u. z ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \' ]( S% l/ ?/ i+ `
SYSCFG_PINMUX0_PINMUX0_23_20 | \5 X* }. G( W: S1 n4 U
SYSCFG_PINMUX0_PINMUX0_19_16 | \
+ b' H$ b" I6 U SYSCFG_PINMUX0_PINMUX0_15_12 | \; ?. q# K2 ]* ^4 L; ]5 y; X
SYSCFG_PINMUX0_PINMUX0_11_8 | \
' D" D/ B2 w2 U; K SYSCFG_PINMUX0_PINMUX0_7_4 | \
! C2 z2 _7 Z% F! q2 [& R SYSCFG_PINMUX0_PINMUX0_3_0);
: Q$ Z( i& j8 r, E6 O) o! j HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \ T' l5 r3 N- A3 \. i5 K( {$ N
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \" D, k: Z/ [+ ~) B0 S! n
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \2 n! ]3 i! K! S. X5 Q, C
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \/ y3 f/ Y$ l6 V" `
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux); v3 t1 s z6 y- x3 J
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
' X; ?: u1 ~+ x; l; ~- w ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \0 Q$ g6 N: b$ Y
SYSCFG_PINMUX1_PINMUX1_15_12 | \
6 _" k8 i- O* s SYSCFG_PINMUX1_PINMUX1_11_8 | \' S6 f- K+ }' [. g) x
SYSCFG_PINMUX1_PINMUX1_7_4 | \; U9 I! |* X* W" C
SYSCFG_PINMUX1_PINMUX1_23_20 | \5 V8 q& ^* z8 V
SYSCFG_PINMUX1_PINMUX1_27_24 | \
8 Z; M. |" o3 [8 x9 n/ A. l ~ SYSCFG_PINMUX1_PINMUX1_31_28
9 g; F! { ]5 s, }4 W ); P3 x% L" _! i1 V |# i
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \. b% s8 i! |0 V2 b" y5 t4 T9 W, C
(PINMUX1_MCASP0_AXR11_ENABLE | \
* J. O6 u+ [0 \ PINMUX1_MCASP0_AXR12_ENABLE | \6 X. g# K( G2 y
PINMUX1_MCASP0_AXR13_ENABLE | \
4 h) t: c& b t/ G W. w- C6 p PINMUX1_MCASP0_AXR14_ENABLE | \ W% p5 s- l! j
PINMUX1_MCASP0_AXR8_ENABLE | \1 ]6 ^6 u3 q5 \
PINMUX1_MCASP0_AXR9_ENABLE | \
) G. Q( R8 j9 f3 d PINMUX1_MCASP0_AXR10_ENABLE | \
* n8 G% b5 |) i# z savePinMux);' j) ~* C: C: W" F* z$ r! k. Q$ j
}
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1.McASPI2SConfigure(); McASP的配置程序如下:
% H+ D) ^3 J ^static void McASPI2SConfigure(void)
" w. x5 s# r: d" T{) {. K; O' G; f6 m* c; w- I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 h: \3 R$ N$ t2 f n McASPTxReset(SOC_MCASP_0_CTRL_REGS);
9 a E! K+ c! S5 V4 v, P3 e; D# i% P) M- j3 P. O
/* Enable the FIFOs for DMA transfer */8 U- [' `$ C$ ]/ _& {0 s4 G8 \
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);+ Z! r3 B2 B; z6 f+ ]. `+ U% ^
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Q! i" j' q8 i# I) Q' g# P
7 {* ~! E o/ U /* Set I2S format in the transmitter/receiver format units */
; l* F8 |5 C* V0 Z. F5 a9 h% c3 d McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 E T5 ~! P. q- k9 @2 { MCASP_RX_MODE_NON_DMA);
* M* O, V, a! p+ h McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" T/ x$ [. @+ R/ D MCASP_TX_MODE_NON_DMA);' N$ i+ r( h/ T( Z! }9 }, r( R' B( N
1 A8 I& K$ \- P2 G8 r /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 I% ?) \. o, ]$ O McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ h% ~0 s2 r* Y7 W MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* q& z- n, l# z, u: o McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" X6 z% u- V9 g) ]. B MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
5 t* a0 U: i" [; u' a+ b `( f2 M! t9 j6 c' ]( U" U
/* configure the clock for receiver */; R) D+ Z; s; p; v
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
. F2 l8 b: u% H8 V8 c+ c: F% A McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& Z. Z6 |8 c/ G$ B McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);0 O# ] l6 o7 k! y$ i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ L1 x; k3 k. a& g* ^ 0x00, 0xFF);
& g! N) Q2 j6 Z" D8 ?( ^7 Z8 Y: B! f1 n. _' Y
/* configure the clock for transmitter */9 D6 B! }& I( r* M2 Y# `- {
// HWREG(0x01D000A0) = (0x00001F00);
( H" I8 f4 B$ q! n// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);4 ]* {$ E! a( m& {" W9 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
& p4 A5 n- q: g McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);7 U: `. J: h: m5 F0 h* n6 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; I; Z' E9 z2 W( F2 ~: g4 H
0x00, 0xFF);9 }1 A6 q, M5 `. ~- ^6 ^
k$ V$ n+ J n$ k /* Enable synchronization of RX and TX sections */ " p. g; c2 b2 q' ?( {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);8 g* {# k. Z" k: l4 J& U& I; L; I
$ U& H5 P B& ~% q, V Y5 a /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 y: v9 @) a7 A! ]' R' v4 w( Q G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Y6 d d% m$ y McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
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5 ^0 ?7 s L5 v7 w1 k /*0 h9 R0 j3 Y. U' s9 y
** Set the serializers, Currently only one serializer is set as$ h) C6 ?$ z0 ?
** transmitter and one serializer as receiver.: ~- W: v7 ~% A: z- m7 Q8 g
*/1 H3 A: W |# B/ D" g0 g4 e9 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! t( k" C; V" W9 i McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);8 C3 I# k% I, V# ?: R) H1 r/ M- z4 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);/ s7 P$ w- K4 [( b) f5 W# F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);( R! x2 m# A8 E% j4 K& g. i8 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
0 Z; a+ u# _8 L8 J McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);' o# a x$ R& h$ s& ~& Y+ N
" k0 e1 @) V* S$ _ a" [+ `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);6 x" Q7 t$ I1 ?& Q2 c! o. T
# W$ ]5 W1 X, L2 M3 X L3 O
/*. a- o4 V4 h% d4 {; c" u6 T7 H( G
** Configure the McASP pins 0 d! \, _* |. Z& g' M2 \
** Input - Frame Sync, Clock and Serializer Rx
8 h7 t, l& e- P/ T6 e9 H7 d. G; M6 R5 k ** Output - Serializer Tx is connected to the input of the codec
1 z$ S7 ]1 {+ o) e6 W% }$ q3 P */
7 `8 C/ @8 B4 b% T3 O1 j+ g/ X McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ M0 K: o7 T X8 B; l+ W5 _4 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,3 E5 H8 t1 f& X r m
MCASP_PIN_AXR(MCASP_XSER_TX)
- E' y7 b1 I5 o. T8 z2 d | MCASP_PIN_AMUTE6 n. m' n4 n6 H8 m; n' s
);* \; c) ?5 F' @. w& z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
& F* n2 q9 V* e0 l/ A1 r MCASP_PIN_AFSX" T6 x: S; g! [& F0 `
| MCASP_PIN_AFSR$ L: a& S$ _% W6 W6 h* q; U6 G" L
| MCASP_PIN_AHCLKX' W0 O( `# ?- M* ~7 p6 U
| MCASP_PIN_AHCLKR
" j5 [1 Q' q$ q* P2 `0 ] | MCASP_PIN_ACLKX+ h0 N5 ~- {8 z/ B/ b. b" \
| MCASP_PIN_ACLKR
2 I. v5 ^/ F) W9 M& w& b7 T6 s | MCASP_PIN_AXR(MCASP_XSER_RX)" f( ? o, K7 O, l6 i5 T
| MCASP_PIN_AXR(1u<<(13u))1 j+ |* M' G6 |& U' K+ z! L
| MCASP_PIN_AXR(1u<<(14u)); Q" N0 D" \' V% }# ]6 [$ D
| MCASP_PIN_AXR(1u<<(8u))
( N) B6 q3 P- B8 B& A3 p: N | MCASP_PIN_AXR(1u<<(10u))3 k9 R5 P* G* X& q
| MCASP_PIN_AXR(1u<<(11u))
. o& [( Q6 `7 e0 ~6 Z );! P% a; v* F% P
$ S- O" z* r& {5 J! S
/* Enable error interrupts for McASP */% _) t! Q H( c+ V5 h0 ^7 G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,/ J8 `* r7 I) Y S7 G$ @/ E" X3 p3 S7 g
MCASP_TX_DATAREADY
+ A, h& e" ~$ {1 Z1 `7 h8 U | MCASP_TX_CLKFAIL ' D! d2 U1 \: [
| MCASP_TX_SYNCERROR
/ u0 l5 E0 x/ _. M; ~ | MCASP_TX_UNDERRUN);: a8 y& \# u' f
6 x' F" A, a3 ~ McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
9 `( y0 Q- i) i% u' x4 q MCASP_RX_DATAREADY/ U4 b) ?" a7 S8 y7 m
| MCASP_RX_CLKFAIL
5 r1 c/ }$ J- d" e' b | MCASP_RX_SYNCERROR 8 M) s; q8 j5 Q( I/ P, m9 B4 R
| MCASP_RX_OVERRUN);
) P+ d# H& f0 k( j$ S' M//MCASP_RX_DMAERROR MCASP_TX_DMAERROR5 U# x+ F& l+ W/ r
/ ^4 Z6 e+ p- x/ R! }}4 z8 \5 p/ L% \- y5 `5 t
6 t# ~; l: O/ s: x; [2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句& m- h; L7 ?' a2 S2 Y9 [8 v
static void I2SDataTxRxActivate(void)
" c& P, a$ A6 a( o{
6 B$ k6 s+ J1 r& j% p/ B /* Start the clocks */
5 {: J3 N2 O, o McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" Z6 l0 J7 ^6 u% M z `3 I McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
* P" G! B$ P$ u) s0 X0 e' x( R2 j% H! }) y- I
/* Enable EDMA for the transfer */
' u# ]- C. z, m- _& M5 T// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 K- D5 | h6 p8 [$ {# A) ?// EDMA3_TRIG_MODE_EVENT);
6 V$ n. x3 `' H5 s) W5 B6 Y// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 e- G- S \3 U) J* o, V9 g// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);8 Y5 O& h* W3 |5 @
/* Activate the serializers */
( c2 x4 V# b- d/ M; Y% k McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( h, h2 w1 q8 c+ r+ D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
) t9 C) W4 l# _% N /* make sure that the XDATA bit is cleared to zero */
8 }8 X( G# `' u% ]# V+ Z while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);% C: u1 h# _ P4 ~- O
/* Activate the state machines */& C4 L$ i( u% N3 J' m% ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' ]' L. q. m9 Y1 \4 l, j3 }' k McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, B" U1 }" M6 S3 P) ~ McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);* X7 L+ H/ u' { a
}' z% Y3 p+ O2 P6 c8 ]8 ]
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