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我的McASP配置分别如下:! I& P2 I9 K5 V' s: F
管脚的复用设置是:% K2 Z& N, h8 g6 {& w- L" a' ^! P( L
void McASPPinMuxSetup(void)
( U+ E1 g; }5 O* K{
8 Z' t M/ w% c; S: Q4 A unsigned int savePinMux = 0;2 }) O- r. F$ Y
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
) O7 T; s7 ]$ t3 j ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
: F4 `& n |4 V2 K, ^ SYSCFG_PINMUX0_PINMUX0_23_20 | \" i* V( {, X: x. E8 r9 }# E
SYSCFG_PINMUX0_PINMUX0_19_16 | \
6 Z+ V: Z9 E$ n# Q* t, R4 Z SYSCFG_PINMUX0_PINMUX0_15_12 | \
, \3 w1 s+ D# G3 [ SYSCFG_PINMUX0_PINMUX0_11_8 | \9 {7 i! e; D5 `0 ?+ C
SYSCFG_PINMUX0_PINMUX0_7_4 | \
8 T' N: y: ?* Y- I- F1 w SYSCFG_PINMUX0_PINMUX0_3_0);
* X; r! F1 L! Q7 t& Y HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \# r% ^, D7 T1 Z: p, G
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \3 W) O( B6 B, z( Y. Y6 j
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \, g3 y; ^. c& a0 _, I; L
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
, j$ @$ i9 D# l0 Q/ p( \7 C# P PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
9 N o3 k) g3 n$ v' O) H# V J savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \8 s3 t& q$ ~2 E& P0 P6 c
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \1 U! L6 {% m2 o9 _) G6 Z# W: N) s
SYSCFG_PINMUX1_PINMUX1_15_12 | \
/ j6 \* @ ?) x% j, g7 h) K: t! x SYSCFG_PINMUX1_PINMUX1_11_8 | \
' I. c: Y$ A* q9 | SYSCFG_PINMUX1_PINMUX1_7_4 | \6 ?- i i# J' q9 l
SYSCFG_PINMUX1_PINMUX1_23_20 | \
9 R/ ]) S" i- J9 X SYSCFG_PINMUX1_PINMUX1_27_24 | \9 |0 L, a* r3 D. j
SYSCFG_PINMUX1_PINMUX1_31_28
5 F ]9 }2 }3 |1 t1 I );1 Y) S* w, [* Y( y7 h6 K. F
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
" c9 H/ [, M W9 M) g (PINMUX1_MCASP0_AXR11_ENABLE | \8 I3 k& { M8 K% ]2 R% ^
PINMUX1_MCASP0_AXR12_ENABLE | \
' w! R8 l" V" P% L, N9 q PINMUX1_MCASP0_AXR13_ENABLE | \
' r0 [( P4 ?2 R PINMUX1_MCASP0_AXR14_ENABLE | \1 b, Z9 R( d, G8 ?' R- l8 e6 H' q
PINMUX1_MCASP0_AXR8_ENABLE | \
; ?8 x1 G9 |. W5 E f$ F PINMUX1_MCASP0_AXR9_ENABLE | \) v m( a' [; R$ U8 C0 s
PINMUX1_MCASP0_AXR10_ENABLE | \
$ k s) \9 ?$ Y& f D: L+ k, U savePinMux);
# j1 m% ]4 u1 ^# Y" J# l f X/ b}2 b! ? y8 H! w, J4 V
. R, v3 b8 M- q9 c# E+ j; X
1.McASPI2SConfigure(); McASP的配置程序如下:( R4 B+ ~ {8 ^; J% e
static void McASPI2SConfigure(void)5 t2 O3 [% Y: B% K8 k( C! F
{% n" _/ F$ W: p% n; f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ?7 g( W( ]3 t- K @) N2 q y McASPTxReset(SOC_MCASP_0_CTRL_REGS);
2 S) k; }" x# M$ ^: k
9 T& g2 @9 }9 u+ g* F8 t /* Enable the FIFOs for DMA transfer */
9 [) [: n7 a4 O" l& x// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
# y& [! ~/ _' r* D' O+ ^// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) g5 v5 q5 v1 V; O
0 U; j4 u6 o6 V* O6 Q! ~ /* Set I2S format in the transmitter/receiver format units */& i" {7 l; ~4 q K; [( j- K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 S' F4 F4 y! O7 ?: `* `2 z' X
MCASP_RX_MODE_NON_DMA);
, X/ T3 A# T6 a% u' f McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) N/ g& O1 N2 z9 S, K MCASP_TX_MODE_NON_DMA);! g, ?9 x( a2 K# h3 {( y* Y. |+ k
- e! A m/ Y8 n! c5 u& K: A% R' s /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- P: N" B3 Y7 Q% W, m0 } McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( y# I1 y$ z j! j0 E+ j r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 D* n) e3 B# F" W3 a/ Z& ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" U4 y, s% P" O% d! Z MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);! Q1 X: S4 m( C6 @! b* ^, B3 C
- z4 s" o, C8 i* j5 \( @0 `- J
/* configure the clock for receiver */
/ i$ v- H1 z( t1 H// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);9 B8 o& h0 z9 a1 t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% o- v8 _6 y' O+ b+ L7 k McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. o: }4 V6 t' v5 C1 ~' B6 G8 P McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. i# w' }' E0 F) N! A7 E6 P2 Z% W% } 0x00, 0xFF);
9 D; q! R1 r6 k' }; k4 S3 k( z f% N j7 _* D' k/ a
/* configure the clock for transmitter */
- m% |: `* a. E9 b4 H+ b// HWREG(0x01D000A0) = (0x00001F00);8 X* k% j O0 u% W7 J
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
! [% s, A5 B1 {. Q8 T McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);+ t# w9 e, ^& r P$ }/ ]5 A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);1 N6 a! M9 ~* q$ K7 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ q! ?) m* \; V& x( V* Z* e
0x00, 0xFF);
6 P9 F3 t- P# `5 P% h: v" s6 z2 M * ]8 s7 i& K1 m3 _$ @1 V
/* Enable synchronization of RX and TX sections */ 8 Y5 O( x4 ^ O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);, H& P! r) }0 I* J4 F6 U
7 a6 h6 O' e3 X7 }
/* Enable the transmitter/receiver slots. I2S uses 2 slots */2 p& t. B" a2 z& {$ ]: s; R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 Z2 Z; R7 j+ r; D) n7 w McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, v0 ~7 q, S& }) K; o3 g6 R1 y$ K: S/ n0 M* X$ K
/*% {& `2 v% M, p; k
** Set the serializers, Currently only one serializer is set as
$ l7 r8 Q, ]. Q: h ** transmitter and one serializer as receiver.: A" P! c9 g2 F+ \5 ^& e5 U7 g
*/
: E3 X" Z% y' ^2 Y) J McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 I! w8 v) ~4 C: e% o5 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);0 h3 d- E% Y2 l' l4 h. }+ j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);0 v5 ` j) A7 J. F- m* k- u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
( @3 x0 Y* l) f0 x }0 \8 c9 E( S McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);: y C( h2 q* X! V% I. _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);+ v. A* v* z* i( R5 }8 P
! A2 ^) f. K7 v3 E; `' x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);, P+ f3 }. s- ~( r% a/ o& i8 u3 n
- M& R x2 p8 w8 H
/*
% o- U- p* f3 W+ q4 i9 i' i! H9 U ** Configure the McASP pins 1 `, _) D4 G0 f, y* N t
** Input - Frame Sync, Clock and Serializer Rx
9 G. N/ q3 E6 g( J( B; A0 T ** Output - Serializer Tx is connected to the input of the codec
w$ |+ H# i+ s6 H */
+ K K- u3 }1 K7 W/ h: s+ w McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* L1 t5 A# k. I9 {# M McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,% B: N1 O' `) M
MCASP_PIN_AXR(MCASP_XSER_TX)
" \7 I6 j9 I) y) A, W* L) ] | MCASP_PIN_AMUTE2 n: K$ `& i4 _# @; [: D* J+ r, c/ |7 Y% ?
);
4 T. M% Z, D& |8 |: w: w McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
3 J7 F1 x! @4 Q& y( Z, r MCASP_PIN_AFSX/ d' x: {8 `" D9 `1 Z% c
| MCASP_PIN_AFSR
4 r! W5 s3 L- c. j | MCASP_PIN_AHCLKX
# ]4 P8 C. H7 u | MCASP_PIN_AHCLKR) V9 H" f2 S# p6 l' ]
| MCASP_PIN_ACLKX8 ~2 M8 d0 \1 N- e
| MCASP_PIN_ACLKR
0 q6 A* r7 ^; C4 g( \& L& } | MCASP_PIN_AXR(MCASP_XSER_RX)
% Q. {, Y" J& F% Y7 D8 Y | MCASP_PIN_AXR(1u<<(13u))5 m! r( a/ D' w
| MCASP_PIN_AXR(1u<<(14u))
4 |1 m1 @' K5 [2 m; l | MCASP_PIN_AXR(1u<<(8u))( L& X) o; N2 R; R; n" F% h
| MCASP_PIN_AXR(1u<<(10u))
; R9 e6 P$ \- c" y. Q2 U9 R" ` | MCASP_PIN_AXR(1u<<(11u)): ~7 B& K8 P$ }6 o
);
1 z7 i4 q' B5 y+ E' I* E7 j3 Y
( d& q. g3 f: | /* Enable error interrupts for McASP */$ Z4 z5 m4 l# p; j4 P# i- v b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,4 T; A& L( l! _& w/ ?) ~2 R
MCASP_TX_DATAREADY
: n8 i Z$ J. O1 X5 } | MCASP_TX_CLKFAIL
/ i8 U9 u6 e/ d | MCASP_TX_SYNCERROR
/ c1 ^7 O, p) m4 H | MCASP_TX_UNDERRUN); }. q0 J, Z& _7 T
3 B6 n. e" H) _3 W, S
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ a6 [: R1 w2 |; V! p; d ` MCASP_RX_DATAREADY
* _* H! }# N& M1 e. o# T$ ?2 u | MCASP_RX_CLKFAIL) G% X6 c' C9 a3 @: Q% y
| MCASP_RX_SYNCERROR
) c. L4 R) A2 ] | MCASP_RX_OVERRUN);* e8 e7 E. X* B L4 f3 G
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
( |: k# r. C8 ^
" E# z1 r& d5 Y}
Q( ~& `! a7 C; _7 f9 e
2 V( K) A' I/ y, _8 r2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
+ ~3 j0 c- ~+ ?, lstatic void I2SDataTxRxActivate(void)4 U7 h+ p R+ K( `% {* c7 G& {# w1 p. E
{
; I& B- J0 g& q- s5 ~& n# P /* Start the clocks */' o1 x: \% U9 d, p8 x9 E. j- f" S$ L) M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ D& @! f6 O+ g McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);9 R, {# d9 ~, q/ V5 B
+ `$ n) ?. i! f- c T5 L
/* Enable EDMA for the transfer */8 [5 r1 i, J; `) y3 N, i$ G
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; ^' R* |* t" u: z// EDMA3_TRIG_MODE_EVENT);
% k# M' G) v8 p0 M8 N' \// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,3 J- @8 R8 m. h
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
3 W* A, c' V& B; ? /* Activate the serializers */
. k/ P. ~3 O, @ `9 j7 J McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 X. u; `+ D; F McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 d6 P6 [0 q1 J w5 @ /* make sure that the XDATA bit is cleared to zero */
' h) a4 D! |! u R. d9 G5 ] while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);6 a9 T" g7 T- V" G* ~
/* Activate the state machines */: C$ y0 v w4 _# k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! d D/ b4 B/ G6 V; Q& I/ s, A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, h9 M6 `3 w/ z& D
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
' ^: q c% _& R( }: @}
% |: t1 ?6 B/ I! D; @8 K% S6 X1 N/ t9 l: P; r
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