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我的McASP配置分别如下:8 H& o4 J4 W4 c& J
管脚的复用设置是:! H2 {- a5 }/ N$ \4 W7 j- x: a) y- ?2 G
void McASPPinMuxSetup(void)
8 M2 _ ~$ |! y/ ~7 S6 \" l& m9 q{
1 [7 Q/ D7 X0 E2 M- S unsigned int savePinMux = 0;
' J: ~# U& t) y6 @* |* R savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \4 Y$ \8 S- y6 K7 J* T
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \. O" d2 u# q- `& j
SYSCFG_PINMUX0_PINMUX0_23_20 | \
5 F& D$ \% ?5 m7 K SYSCFG_PINMUX0_PINMUX0_19_16 | \" K8 Y I( L. V2 I/ T" g* F. n6 @# e5 S u
SYSCFG_PINMUX0_PINMUX0_15_12 | \
' |" Q5 I0 v! O9 M5 l% m$ `; l SYSCFG_PINMUX0_PINMUX0_11_8 | \$ r. J1 Y# V# T$ T
SYSCFG_PINMUX0_PINMUX0_7_4 | \: w* v, i) D( Z1 C
SYSCFG_PINMUX0_PINMUX0_3_0);9 ]& @+ d2 \, g
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \3 C ^( n7 G$ }) X: q. f& X
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
3 J: \; C$ E+ Y$ o( U6 v- K( y PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
5 [. R( U/ P; d8 z1 p, Q e PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \8 [8 c' M6 r# ]/ m t
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
9 R1 Z; S6 \2 E! ~) _" S savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \4 k; A' W( ^: B' g# a4 N- k$ D
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
2 O( l k8 b8 N; z" A' o: e U SYSCFG_PINMUX1_PINMUX1_15_12 | \
- P2 W+ c3 p7 ]7 A( k$ ] SYSCFG_PINMUX1_PINMUX1_11_8 | \
% j9 A( J S/ r! G$ u! M! K/ H, ~5 o SYSCFG_PINMUX1_PINMUX1_7_4 | \
: [' o1 ~2 y& O$ ] SYSCFG_PINMUX1_PINMUX1_23_20 | \& K% d2 L C, z' e9 g# O
SYSCFG_PINMUX1_PINMUX1_27_24 | \
0 O& A7 R4 F; _6 K SYSCFG_PINMUX1_PINMUX1_31_28
( F- |$ Z' N) L; U+ c- q );* z; W& A' } s' Q
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
8 {. O* a/ Z b4 V (PINMUX1_MCASP0_AXR11_ENABLE | \4 `% i1 D2 a. V9 Q
PINMUX1_MCASP0_AXR12_ENABLE | \
o2 F b- v2 g7 k3 n PINMUX1_MCASP0_AXR13_ENABLE | \! r3 J. ^- c C6 J6 V% V1 Z
PINMUX1_MCASP0_AXR14_ENABLE | \# E& m" }# w' c% ~, Q# k' o" u
PINMUX1_MCASP0_AXR8_ENABLE | \
+ w! g7 y [$ z9 Q+ x PINMUX1_MCASP0_AXR9_ENABLE | \3 r) n, j! j' R
PINMUX1_MCASP0_AXR10_ENABLE | \
Q% q( P7 s( a. u, S" y. w savePinMux);# d/ z: j$ o$ L/ W5 k
}% u; Y5 [ V( A# ]8 b3 u
3 {# J; Q: x! j y" r! w
1.McASPI2SConfigure(); McASP的配置程序如下:8 X# V; Q3 q5 j
static void McASPI2SConfigure(void)1 A2 Q1 g: L) e3 g4 F& P
{: }3 N' A! T) p; K6 a! ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( W x; W6 q, v; N3 t McASPTxReset(SOC_MCASP_0_CTRL_REGS);
2 p8 X" j- n6 U3 N8 X+ D
! D+ s& K7 k0 @3 T! S /* Enable the FIFOs for DMA transfer */7 J# \$ c9 T1 p3 Z: g6 _& C3 V
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
) H7 _5 X' C4 K: g7 J, m// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: {/ D" i- }% @" o5 C
) |( [1 ^( w- O" _
/* Set I2S format in the transmitter/receiver format units */
. c/ I- G0 k" S# Y7 c# U" W McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: }8 B! q' h8 B* Q0 b+ q; U
MCASP_RX_MODE_NON_DMA);1 S% g6 h4 g0 r u& X3 K7 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; Z: c; `% B$ J0 Z MCASP_TX_MODE_NON_DMA);
3 X$ c( R" u% x- ^. D; H1 R5 h/ h
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 M# J' @$ m; d5 P( }2 l% M! q McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- Y f8 A# S5 V' k MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. p; ]5 ?1 n' ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, c3 H8 v9 [2 a1 [) e" i' @1 m
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
% p7 i% F/ H- k% t; F: Z( \" {9 r. e4 [0 p$ W3 H
/* configure the clock for receiver */* r" A: [# E3 t1 C" v
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);% K0 |8 H" t' r. w ]0 B! I3 B$ ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& p8 r0 k9 e* B! C3 A McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);) T; D, E7 O0 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 \1 ^9 s7 E6 R5 ? 0x00, 0xFF);3 u( \: e2 w' t
9 Z5 l7 d3 F" j7 K' f$ ?4 y /* configure the clock for transmitter */
1 B3 L, t4 a. p& r% t' V; k! f) Z// HWREG(0x01D000A0) = (0x00001F00);2 T& d3 U' @! v: U$ `
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
# e% G, l) Q1 U, ?- B8 @8 ~& f McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);/ Z) i' \* C( i3 f0 r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);6 Y4 J, U$ x: j+ n( d7 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 k, J/ C9 f3 d- I% I0 j% b# r
0x00, 0xFF);
7 a' B+ n6 K+ K4 G$ s9 \) w
8 Z4 Y2 W, _$ S& p( N1 X /* Enable synchronization of RX and TX sections */ # @, W. p/ t! N0 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);: Y7 ^5 p( A7 p( N
1 }( {8 k8 U$ E' n# n/ I6 X
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 F; X# f( g- G6 k# q. H) E McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; O4 F" J7 e! n2 t2 t* i5 ` McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& K2 ^6 Y$ t- {6 h* Y" A
- q& F# Z) D8 y% I; j /*
/ G7 U5 ~! H5 d; O7 z ** Set the serializers, Currently only one serializer is set as+ V$ S; r3 Z0 ?7 f
** transmitter and one serializer as receiver.6 q1 T: d S5 P7 G: v8 `
*/; U8 S* w U: L- \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* O( _ l+ d7 ]4 e c8 E McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
, Q0 ^$ V& t* h9 o7 _% ?+ k8 K; G! \ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);' j: j/ V* l' K: v9 Y0 `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);0 {4 l0 D/ N4 H- k& G+ o9 }6 s# \, P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);1 u$ t4 M+ k$ V, \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);- z+ w" Y1 H! A/ l: u: f
& P* h% O, [* E0 L& i1 Z McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
2 G' }' i% z; h _1 H, V7 S, I; |, m) u+ i+ `* D3 K
/*
, G0 Q& M' E9 G8 g5 T6 B% t ** Configure the McASP pins
% L! O/ D8 g {% e" q3 g5 k V) W ** Input - Frame Sync, Clock and Serializer Rx
6 M8 ?/ @* \* e8 y5 Y5 U* \7 ` ** Output - Serializer Tx is connected to the input of the codec 8 M3 c/ ~$ S1 q7 L6 z. Y3 t' M0 Z
*/
. g4 B g; H" [3 k% [$ x+ n1 W McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ K' J3 _% w4 k8 w6 a McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,9 P1 M; G* I, J0 d+ `
MCASP_PIN_AXR(MCASP_XSER_TX)8 Q3 z0 |- [$ q, m1 c
| MCASP_PIN_AMUTE
( Z5 O6 l. f- [: {+ Z6 Z$ | );0 h) H) w; U7 p& [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,8 u, w5 ?8 \8 T. }+ c
MCASP_PIN_AFSX/ s( U9 M; ~, ^ [ D7 F. i
| MCASP_PIN_AFSR
* D0 J* r n ~. H' [) S% R# ~3 A | MCASP_PIN_AHCLKX
/ B; _3 p, g8 m) i | MCASP_PIN_AHCLKR
; V9 e# B) S: L- ?9 _( X | MCASP_PIN_ACLKX
8 r1 y9 W, g& [1 c | MCASP_PIN_ACLKR+ K0 ]- K% i( c4 ]) Q
| MCASP_PIN_AXR(MCASP_XSER_RX)
! t/ p8 \% C# i1 \. v | MCASP_PIN_AXR(1u<<(13u))
2 n6 o% _, U2 w* s. c | MCASP_PIN_AXR(1u<<(14u))- u' ^! O4 C0 J
| MCASP_PIN_AXR(1u<<(8u))
2 I' ~1 O- s. @* n* T4 ?+ C | MCASP_PIN_AXR(1u<<(10u))* l! V' l& ?. U+ W* R: H
| MCASP_PIN_AXR(1u<<(11u))
1 H0 g4 e5 T9 _ D! | );6 u4 J5 r$ R* }: n
' Y1 c p8 a# t2 j2 q
/* Enable error interrupts for McASP */8 \$ D/ a& Q5 i# }, L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
( N' |4 \" v8 S r0 G* c6 K9 D MCASP_TX_DATAREADY
. J. {4 z" b# ]! a5 t7 v7 ?4 ?# d | MCASP_TX_CLKFAIL
: R/ x- H" q; m& R6 r1 H | MCASP_TX_SYNCERROR
2 t" R4 b4 I% z& u" c4 Q | MCASP_TX_UNDERRUN);! V, l7 ~: P' k2 D* |
2 ?6 s# F, C0 x
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
8 g3 X. S7 p5 }4 Z8 f( t5 k4 z" J MCASP_RX_DATAREADY
: @8 w7 t: _2 q+ k% g2 q2 j | MCASP_RX_CLKFAIL
5 ~) P* p B+ j4 ^9 W | MCASP_RX_SYNCERROR
$ [( c' _% L5 I! p& o% Z | MCASP_RX_OVERRUN);/ P* `+ L& t6 W, Q
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
: U0 o1 _/ W; U7 p
6 S2 t e2 P" h4 X8 @}
6 u3 y7 t3 d0 g- D. V K. O
, n( {# \5 Z7 j- r; Z2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句5 G$ ~8 k0 [6 G5 C/ V
static void I2SDataTxRxActivate(void); M7 {1 Y$ X4 h
{6 H% U2 r1 U! k+ I( s5 }5 x2 \
/* Start the clocks */: A8 s; [! X3 ?# }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) R' X p% G' ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);4 r7 W* y0 p: X u& t$ n3 H
9 q3 E' c6 W! S& J! B3 w /* Enable EDMA for the transfer */0 Y) e7 z9 i+ P/ V+ H; }: i/ H
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 [5 p5 V2 X' o1 q9 n// EDMA3_TRIG_MODE_EVENT);
% s0 [9 |) C5 x0 z. C0 ^// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- t$ G4 h, t- j- l* V// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
( y) W5 \1 V1 z& Y /* Activate the serializers */. g; V6 l% G/ P: {5 J; h- f1 V; `) X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 N! ?9 `& q5 j% E+ h8 h McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 k$ @+ F! H5 `3 O, T& a o0 E3 m /* make sure that the XDATA bit is cleared to zero */7 W% [! I+ K7 g5 e) Q6 A/ i# g2 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);6 _; N* L( E- b" |& ?& {) A# i
/* Activate the state machines */, w5 A" L* B! a, E0 e& r1 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& b% l. K) S m( W3 c1 ?, L% r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 Z! e- A7 {6 m0 A9 j
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);" d# S4 u5 b* {- s) ?0 ]
}8 h" [3 g9 x7 N+ J
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