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我的McASP配置分别如下:
' \5 O8 x9 E0 ]* l' m0 L P管脚的复用设置是:
- a. V; E6 z+ E2 v( Cvoid McASPPinMuxSetup(void)
# a1 t! B; D, d: }9 I; J{( G1 i3 u1 E* _; @1 t0 \
unsigned int savePinMux = 0;
9 L/ ?& ~' Y2 c# R( T% O savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
& w( ?# \0 c5 ?0 A ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \& [1 _9 H4 N5 z' n6 G6 {) L
SYSCFG_PINMUX0_PINMUX0_23_20 | \
+ f$ C5 B, K6 U" P' Y9 S0 E5 a SYSCFG_PINMUX0_PINMUX0_19_16 | \; c' s3 Y0 m8 b% k. p8 r6 ^
SYSCFG_PINMUX0_PINMUX0_15_12 | \
) ~) F5 P, s; m+ ~# I. l SYSCFG_PINMUX0_PINMUX0_11_8 | \, O+ I7 e: O8 i
SYSCFG_PINMUX0_PINMUX0_7_4 | \7 V5 d) Y3 j" n# }' P' }
SYSCFG_PINMUX0_PINMUX0_3_0);
5 w/ {9 ^* } ~2 M6 E6 Z% ` HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
# i7 S$ C5 z r0 y- k6 m, X (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
& M# D/ g) X5 k* Y5 ^( J PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \* p2 p: V, \/ f2 e
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \9 H1 S$ o& c/ ~( k7 H: I# n
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
8 Y1 K @! P, P, ?+ S$ q7 q( {6 e savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \4 U4 f$ Z4 d% u X
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \4 p# d, c O) D; ]3 v2 _5 y
SYSCFG_PINMUX1_PINMUX1_15_12 | \: r' B8 L* g7 B/ M5 q
SYSCFG_PINMUX1_PINMUX1_11_8 | \
+ } ^/ Y u. B SYSCFG_PINMUX1_PINMUX1_7_4 | \
9 {; P3 Y! e% h2 K# P SYSCFG_PINMUX1_PINMUX1_23_20 | \
. I- [( U9 \* V! J0 W; F SYSCFG_PINMUX1_PINMUX1_27_24 | \ B9 U; Z) D# v( s4 c% ]0 s
SYSCFG_PINMUX1_PINMUX1_31_28
+ J7 l! I0 x+ l C8 m9 ~/ b7 _0 ~( O );
- L. z" |! s+ W7 P! e HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
' h% C, L7 Z) n, q3 O (PINMUX1_MCASP0_AXR11_ENABLE | \2 u9 G0 {" D$ j' l: u
PINMUX1_MCASP0_AXR12_ENABLE | \# T) z1 M+ u, m) ]" y4 T
PINMUX1_MCASP0_AXR13_ENABLE | \
# Q$ u& s' ?# R! u" S" D PINMUX1_MCASP0_AXR14_ENABLE | \" E1 q; ~- S0 y+ i2 S7 F
PINMUX1_MCASP0_AXR8_ENABLE | \
! ?5 H S! a! p/ }* m PINMUX1_MCASP0_AXR9_ENABLE | \
: U6 I% X9 n& h3 ?8 r3 t9 R PINMUX1_MCASP0_AXR10_ENABLE | \: e& l% Y# Q7 O5 V* _* K/ Y- B
savePinMux);' m1 k, D: L4 t4 j4 D
}6 | D" b/ I) L, z. ]
& ~2 G+ c/ e' S! G4 A; F. p v
1.McASPI2SConfigure(); McASP的配置程序如下:
0 m/ J+ I* t. P3 C3 B' \9 c$ Lstatic void McASPI2SConfigure(void)! o* a8 {2 N7 f# O
{
6 {5 U1 a" _% c+ n3 o/ ` McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# ~; h2 H, b6 O# h5 ]3 V' U1 y4 _ McASPTxReset(SOC_MCASP_0_CTRL_REGS);& A- M, j+ Y8 |/ l# X' R
/ z! U& m2 t0 F /* Enable the FIFOs for DMA transfer */9 b2 P( [: n$ ^/ G0 r, F
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);0 ?3 W" n$ J" ~. e
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) X8 k- y e7 V" X2 h0 [! B& m& x% E. T
/* Set I2S format in the transmitter/receiver format units */6 W2 _3 _4 l5 X+ |* S5 N! P! \ d8 D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( Q. A7 Q/ e$ C) B5 x% V" k MCASP_RX_MODE_NON_DMA);
! V' v! Z7 N$ N* N% b+ ~ McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 w9 L N: K& v& I7 `" F3 B/ @
MCASP_TX_MODE_NON_DMA);. b4 {& @- s3 e( D
) }2 W- J$ |: g4 l: J /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 ^& G& |& v" d1 U* J( h# g8 g McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 j0 [, x! k: \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 z# Z5 S1 _( E f+ J1 \* g! W/ G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . R0 z) D0 r7 |, u. U6 R! R$ A6 z
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);6 ^/ c: F2 K6 n$ @0 M- o& _
5 X" o. i+ M- X; M! b0 H4 h+ y /* configure the clock for receiver */
, [# J; e) D) u/ v// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);1 ?+ C3 l, Z- n( q3 v/ I& N9 N5 W l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" o4 w* u9 x8 J1 t8 m McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);0 |$ J5 q6 s* V2 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," r4 ]4 U @+ d* D+ w% h
0x00, 0xFF); y, R9 J) Z* d- U% J+ C' t
5 C0 ^5 \2 Q7 ?! L" r+ \' X6 p /* configure the clock for transmitter */
4 @0 z, x' q! U& u Q( ]// HWREG(0x01D000A0) = (0x00001F00);
) j$ P9 B+ L. V/ u! V, m# w// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
; }" X' F- ~7 B! q% [9 t; K McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
- o+ t1 ^" N2 y McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ [/ Q+ |/ d5 H/ l McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 m1 |. N4 L l4 Y% w 0x00, 0xFF);
1 x U7 U8 y/ \/ O/ a- h/ i( Y, J
/ `" n9 V0 b {6 L( P ]; C/ |+ S- [ /* Enable synchronization of RX and TX sections */
* |) U' e/ t' v/ u8 n! X! y' c McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
0 O" w' n7 { x- t; D+ b2 F/ ^/ E( S- {
/* Enable the transmitter/receiver slots. I2S uses 2 slots */% m! n% D) X( x* {* q5 c7 n* h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 l4 s& U ] H' t( i McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 \* P n* u, M8 [
4 m2 K0 K4 s$ @4 s8 h /*
: \ S6 D; `; o3 V ** Set the serializers, Currently only one serializer is set as3 S( O& Q9 C+ E! Y V
** transmitter and one serializer as receiver.
; h+ [4 R# X3 x4 m4 Y) d, r# m9 J0 h */
5 N4 k- j2 E, R- z9 s8 Y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" M5 L1 _. d2 R4 W) o" Y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);) b: U" E3 e% M0 x g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
1 [: G" K4 d& p McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);) _( N/ {' l5 c) W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
' ~ l9 z, v+ R0 f2 z McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
: l) i& T( s& P6 b- n
: e" Q4 e$ `6 k0 U2 k7 W6 @, K McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);" x# v4 J w" s; T' b, \
! H9 i# e9 I2 u /*
. T& z6 G" ~+ H: F ** Configure the McASP pins 2 p3 v. w& H' @4 A u6 x+ j, h
** Input - Frame Sync, Clock and Serializer Rx# q5 I/ o* ?, t! G J0 s
** Output - Serializer Tx is connected to the input of the codec
7 J1 y8 O) L# h6 {/ n */' r. h5 G& j$ ^6 ~1 O9 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 S9 Y8 h1 R. O7 x0 ` McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, V) B" e; f4 h1 ]
MCASP_PIN_AXR(MCASP_XSER_TX)0 G" Q! K# c2 _" E- E) x
| MCASP_PIN_AMUTE
4 J- i* |9 P; G( G6 U- v );
* w5 j( L) r* |- v" D2 t McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,5 W/ ?# j$ x. x" v E0 p
MCASP_PIN_AFSX
, a3 K9 ^' d; u: Y0 r8 _# v | MCASP_PIN_AFSR
( K, w4 c# r8 g( x1 W5 w" O | MCASP_PIN_AHCLKX0 B* ?7 A- T: s( b5 @
| MCASP_PIN_AHCLKR
% X- r3 J( U9 Z2 ? | MCASP_PIN_ACLKX- n+ s9 i% r* C5 |2 }
| MCASP_PIN_ACLKR
3 H \5 o x8 F9 d; K& \ | MCASP_PIN_AXR(MCASP_XSER_RX)
. S1 A- ^" q- D# W7 o/ a- }5 ~ | MCASP_PIN_AXR(1u<<(13u))
0 g0 s% J/ Y8 ~& D | MCASP_PIN_AXR(1u<<(14u))
) M2 R: c& [* Z5 ?6 y! p# m3 x | MCASP_PIN_AXR(1u<<(8u))- s6 ]+ `0 j' p7 Z* ^; ~
| MCASP_PIN_AXR(1u<<(10u))# ?( S0 T. S7 T8 K; F* W
| MCASP_PIN_AXR(1u<<(11u))& M8 V3 o& Z" F0 T9 i* t$ K
);# J0 U- p2 o S* ~5 ^6 u, q
9 h, V4 o, w7 B7 X9 S& M' a /* Enable error interrupts for McASP */
+ L, L' l% e) K1 K McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
" e5 F! A, e3 v0 V6 y% T. t; v MCASP_TX_DATAREADY2 x- D) `% F. e) [
| MCASP_TX_CLKFAIL / G5 z6 A& N' p6 P1 T0 j
| MCASP_TX_SYNCERROR k) n2 s8 X( @. N3 U
| MCASP_TX_UNDERRUN);
& d5 m7 n& F2 ^# U6 E" w/ {. R4 ~3 V. S* x' u" L0 w
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,) L! s: }; m5 t1 [* w f+ R
MCASP_RX_DATAREADY; P2 X7 Z7 b; O4 P6 E# t- S
| MCASP_RX_CLKFAIL- S v7 T9 d6 t: x, ~5 C( r
| MCASP_RX_SYNCERROR
: G2 Y0 _5 |) o: y$ u" X5 o | MCASP_RX_OVERRUN);
9 Z( h+ Y/ Y& ~( D1 \//MCASP_RX_DMAERROR MCASP_TX_DMAERROR5 }; R* M* v6 W! v" C# C
4 J/ H5 T# b/ l) m
}
( S" h; g2 a' H7 p, F8 D& p, V) ?' F5 ]* w. h7 \& v
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句+ }& h D: G+ m5 ^4 X0 w# A
static void I2SDataTxRxActivate(void)
' b Z$ x% |: U$ c{
1 w. F: _$ i3 \5 A9 t* P. A /* Start the clocks */. D% ~' ^5 E/ M3 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" @5 a# D& a% g2 r3 R7 }. ?' k McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
: M! t- Z) }; l+ k! c
; |8 a; C6 H- j% G /* Enable EDMA for the transfer */
4 Z" j0 n5 b* n// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 H8 j; [- f1 J// EDMA3_TRIG_MODE_EVENT);* m. y( c$ o& S# \
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,2 }! u, T, p0 w$ y* G/ ?/ q
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);- M9 |0 r4 ~2 \
/* Activate the serializers */
+ J2 l! D, z5 C! _ McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 q! l$ X0 _# p! L% M7 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 O; H+ \. m6 h: [) J) C /* make sure that the XDATA bit is cleared to zero */
( v @* Y9 f6 x while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);( k, l J1 X% k9 ~* u
/* Activate the state machines */# N3 W$ {% e% M3 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; Q3 ~5 S$ b1 p8 C% s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% i" j& }2 D/ Z5 s( b3 n6 x McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
) x- m i; R- g1 m% a6 \}0 q4 b+ ^ G8 M( D0 k; P
% t* K# X! t- u' H5 Z
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