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我的McASP配置分别如下:
! C6 r0 |8 t8 E5 Z( J) O, d管脚的复用设置是:; T) [! `! P6 |6 [5 n, M( p+ t3 W
void McASPPinMuxSetup(void)
; e/ [# x# J" h+ X, B1 S! O# \3 C{
4 z+ C, O1 y, e2 D/ _ unsigned int savePinMux = 0;
6 x. r+ I3 _: G2 h0 [( } savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \! Z0 E+ \" B5 O' K" |/ H+ B
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \6 v, L3 X' Z) Q* t4 B& ]0 N& q7 |, w
SYSCFG_PINMUX0_PINMUX0_23_20 | \- o/ W- g( s/ N: q9 b& U& y
SYSCFG_PINMUX0_PINMUX0_19_16 | \
" L+ t' w. ~9 r SYSCFG_PINMUX0_PINMUX0_15_12 | \
$ S, V3 c' w" h/ y4 j' M5 f9 x- R4 Z SYSCFG_PINMUX0_PINMUX0_11_8 | \
. _, R8 V$ A+ q5 m, L SYSCFG_PINMUX0_PINMUX0_7_4 | \+ E# G4 P2 d1 }9 A. ]
SYSCFG_PINMUX0_PINMUX0_3_0);5 V- T0 N; k! ~+ F9 Q; ?
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
: }( }) D }, Z! P (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \5 A0 D0 l! \* Z/ s, z- s7 v3 |- ^$ ]
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \' T: G t# C- U
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \2 }, {- x% J, q& A! ^
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
: D, ? @; [" U. J/ B- q' | savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
5 Q( e$ ]) [# k7 m9 o$ G* G ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \+ t$ i: t* O7 n" S$ W- ?0 l
SYSCFG_PINMUX1_PINMUX1_15_12 | \
% |! W0 U7 A! {4 K/ M; U SYSCFG_PINMUX1_PINMUX1_11_8 | \
6 ?! I5 h, {: m: C( J1 [, O SYSCFG_PINMUX1_PINMUX1_7_4 | \! o/ s2 `6 d2 S
SYSCFG_PINMUX1_PINMUX1_23_20 | \7 Y1 }; P; @8 W ^& W3 b
SYSCFG_PINMUX1_PINMUX1_27_24 | \, s3 M- L$ K: ?5 J# E' T
SYSCFG_PINMUX1_PINMUX1_31_28
; g1 [# k) ~0 y& D0 P2 y. M );
; y* O3 f0 a1 e$ s5 J HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \. a& y! j. [: R" i
(PINMUX1_MCASP0_AXR11_ENABLE | \
2 V, L' v5 o% M$ `7 t$ d, e PINMUX1_MCASP0_AXR12_ENABLE | \, `# P7 v- s/ o d$ j5 W
PINMUX1_MCASP0_AXR13_ENABLE | \7 K+ O% j3 ]- A2 u) V- X6 \' B5 X* f
PINMUX1_MCASP0_AXR14_ENABLE | \
E# F% S: D* {& ?: ^2 I( [ PINMUX1_MCASP0_AXR8_ENABLE | \
/ _- x* f$ x* f PINMUX1_MCASP0_AXR9_ENABLE | \
, B1 p" ?' `+ G) {4 t PINMUX1_MCASP0_AXR10_ENABLE | \
/ K' F3 {) z( H* c0 l; x- q f* s$ K& g savePinMux);: ~$ d4 l7 a) d$ o2 N- }
}% h" Y! Z/ l1 o
# n" _; C. Y! b1.McASPI2SConfigure(); McASP的配置程序如下:
) s0 m; a6 X! k* bstatic void McASPI2SConfigure(void), n$ J: a2 }- M/ L; N" h) | N( g
{* K0 b8 z$ v! X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 X& `: N4 m8 E# W
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
, c. N2 s1 `, _7 u
L8 b" d( N; s+ m% V /* Enable the FIFOs for DMA transfer */$ q/ C3 T" U. P' Q! I" }
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
4 N% K' {! Y( k: g" T// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: f8 E1 O# W$ C! `
+ h, j( `; I& K) H3 X* Y& q /* Set I2S format in the transmitter/receiver format units */! x1 s- l _/ I) G( \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 K, b0 ?! `( Y! f1 ] MCASP_RX_MODE_NON_DMA);3 a' `; { x$ z0 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, g; _5 F) C o: u5 A/ |. d# |( L. J
MCASP_TX_MODE_NON_DMA);+ w" ]9 Y' a3 @8 q: O
3 ?6 h' Q1 U) A% o
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) Y& h+ L g, n/ y2 q, } T6 s, _' F McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( e# o! g+ V* q3 ]) D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
Q6 c4 W- [& F- J# `8 {( x McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 @3 r+ k+ R% h3 Y/ k* l" F2 ]# o1 Z1 H MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);5 x1 F' R7 b0 ^9 T5 s( p9 O, v
# d ]& { N2 H0 C1 }& | /* configure the clock for receiver */
. L7 O# T1 q$ R5 }9 h# d// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
4 K/ O% N9 f2 i McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: F/ `. _. X! y( o. X, \' Q$ A" y McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);; h! y! d3 X9 E y d2 h0 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 G" p4 @ F6 o, x: Q5 d3 L2 ^ 0x00, 0xFF);( A9 N j0 d8 {: S/ s" P
/ r. g; q' t, R /* configure the clock for transmitter */
$ F- [3 A5 N( a8 N, F( U// HWREG(0x01D000A0) = (0x00001F00);
8 ^: ^1 U/ U4 l0 D S5 w// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
- }/ c# _0 L( {4 m) ] McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
& j8 V* u: L4 x3 I7 H& o McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 e: Y. B& W- @- t0 A McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 } `) ^& e: A) j" ` 0x00, 0xFF);8 C+ R4 Q8 A4 |0 \% P9 g7 {
' M- E" p% ]: [
/* Enable synchronization of RX and TX sections */
% h0 y) ?# ]5 } McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);7 a3 h" E( p0 u" ]+ C
; ^- ?3 k- m& z j
/* Enable the transmitter/receiver slots. I2S uses 2 slots */" R; N5 T6 H& c5 O: F3 [, ]0 a( j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- m/ o" I' e' {% ^3 ~ McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' R2 v; k h: ^& G0 ^* U1 W1 D2 p$ Q+ p A3 B) s4 H+ J8 J
/*
8 T; l. D0 W* F6 m) u2 S! U ** Set the serializers, Currently only one serializer is set as- l% p( b) p: L+ C1 v
** transmitter and one serializer as receiver.$ a- M# w( F" R- r! O% U
*/
& f+ v7 G3 s! u6 f McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 ^* ]5 m* z+ |3 l+ p( k1 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);9 N! ~2 @0 a. a- W5 A9 F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
7 j# | c7 g* r( s* U& t% w, V McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
4 I" U M& b1 U# D" K6 X McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
D+ M+ h2 R0 O1 p3 {# t' ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);% S# `" |# m& W) G$ m, G2 r
5 f) n6 U! _& ~, {+ z. F McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
6 } C, n6 \* f' _$ Z- C0 I
! A5 X! ^5 r1 F* k /*
4 f( n* h E$ K ` E ** Configure the McASP pins 4 M3 V( Z: f# t# W4 t! P
** Input - Frame Sync, Clock and Serializer Rx% i( m' M B9 K+ T9 H' e2 x' @
** Output - Serializer Tx is connected to the input of the codec
! O* {& ^9 f q7 l */% ~: U( u2 e+ b [2 C) @% ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; \# U2 B4 I' {1 S$ P McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,3 A5 ` }5 e U7 }) o/ c9 s
MCASP_PIN_AXR(MCASP_XSER_TX)
! g. A! y; k! |* w$ a) B: X8 W; ^ | MCASP_PIN_AMUTE
; G# Y3 ]4 _0 M0 | );5 O/ n5 |3 u6 Z$ ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
7 d4 u% s) G4 S MCASP_PIN_AFSX
6 e& k8 l( O! T( Q$ b | MCASP_PIN_AFSR
$ D: j4 h6 i' a2 Z1 K | MCASP_PIN_AHCLKX+ a6 ]) n' T9 T3 ]. k
| MCASP_PIN_AHCLKR/ l2 t9 C' Q/ m! y& U% g& O+ {
| MCASP_PIN_ACLKX
3 S* z& L" ]& E | MCASP_PIN_ACLKR
3 k) \( d: V* g T | MCASP_PIN_AXR(MCASP_XSER_RX)
" h* _/ a5 [+ k1 q8 g; u/ f | MCASP_PIN_AXR(1u<<(13u))
! N+ P9 |+ n4 K" H5 P6 i | MCASP_PIN_AXR(1u<<(14u))/ `! @, M7 X0 }; u' Q
| MCASP_PIN_AXR(1u<<(8u))7 X1 f6 T' Q# k& W7 b; w
| MCASP_PIN_AXR(1u<<(10u))
% A& e y) j# }! z$ {2 H- b | MCASP_PIN_AXR(1u<<(11u))4 Y P& u* m" R! h
);
* H3 u6 f# d1 S7 r+ D D) ]' n7 x
/* Enable error interrupts for McASP */8 [. H0 f! d8 z$ H; S* |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
! P) P5 m$ |; R+ r; Q/ K MCASP_TX_DATAREADY& X1 D' s T* h! P0 y* C! S F5 A. V
| MCASP_TX_CLKFAIL
, n' x, f0 ?/ j4 A- E1 W M. S | MCASP_TX_SYNCERROR
( u+ S* z6 y1 D0 a | MCASP_TX_UNDERRUN);: b; `* }' r0 r) C) } ^
/ ^8 V7 c* X' |0 c% { McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,6 R2 G% H0 W+ C! G
MCASP_RX_DATAREADY
1 O( v, _. Y( O3 f6 l- I: F | MCASP_RX_CLKFAIL0 s- E% Z/ h) R% z7 K% w
| MCASP_RX_SYNCERROR
/ z: n( {) q Y$ P$ c* |' V) Z | MCASP_RX_OVERRUN);5 W/ j0 C" A$ D3 ~3 y) ~
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
' Z) g2 w+ ]7 L! Q2 y
* u! {5 w& N/ B0 J9 _}* B" W; h( Y3 x9 C1 ~
/ c# f& Z& p1 p9 _2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
v" S; ^' s# f' j! ~1 Ostatic void I2SDataTxRxActivate(void)
d) _2 x* A1 \2 ], O{/ S8 \9 G4 ]" s* e0 M+ \" `
/* Start the clocks */
' r: C0 b0 c. L. e# ]4 _6 H& v McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 j: ^( N" `- l) l# D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
; _/ ]3 R, J& I. {, t( y% Z8 O- o* t8 |+ b% e7 K A! q# S- ^3 F9 ^& g
/* Enable EDMA for the transfer */
, {- T& J. F1 Y" [9 Z// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 d/ N0 |3 u5 ^1 y$ b3 ^0 j
// EDMA3_TRIG_MODE_EVENT);
: j7 @% S% n+ }( @// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,, c9 A' Q3 ~$ c# s6 I
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);+ U4 H% t$ }# t1 r' |7 s
/* Activate the serializers */
$ b$ m3 v9 } X: P McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; D4 v P# S$ X+ [" }2 J3 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 B& R8 H6 x. h /* make sure that the XDATA bit is cleared to zero */ ~; [! {3 I2 P2 w [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
. j1 X6 z! s% N. R* a9 i& ?$ z /* Activate the state machines *// V5 o* j M3 w+ {% m' y1 O5 ? ]) g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 U+ F+ }% P6 Q/ {& ` McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" I; z; J! N" O, i3 c! M
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
/ c7 f# ~7 l, b' {% |}9 t" h6 \0 z# d- T2 n1 K8 g( `+ \
& B5 Q5 L. j/ {, \, M- J, v! h2 k
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