我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' [. X' h6 k9 h7 e$ j. ^7 p# ~7 _input mcasp_ahclkx,3 a- p9 ~! _9 Q/ q
input mcasp_aclkx,1 l/ R( S2 r9 f; ^/ t0 r$ x
input axr0,
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output mcasp_afsr,
( M: x) I7 k5 @output mcasp_ahclkr,
) K. r, o# u+ ?output mcasp_aclkr,
2 E3 O6 j r+ [output axr1, \. |8 l+ M) _
assign mcasp_afsr = mcasp_afsx;7 Z5 L8 M: f2 E/ @3 f( n3 ]
assign mcasp_aclkr = mcasp_aclkx;
/ y3 r7 ?1 }( b# b! }2 e8 L' p, passign mcasp_ahclkr = mcasp_ahclkx;
6 h! J8 O8 z; S4 Jassign axr1 = axr0; ' h3 ]6 ^9 J3 `6 C
. G2 j" U$ D5 {2 @' x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 h4 q& X# M) Y, P/ [* v; c. M9 ^static void McASPI2SConfigure(void)
/ J1 i* E3 K$ E{$ h) F1 \8 _1 {2 E" D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 Y, R' i" e2 m, ` E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 o9 e( A: ?/ I/ E/ ]$ A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, R2 N& p) F& m! B7 J) OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 H4 G9 [, p {: \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. v4 R# {1 y3 f. R5 E& Q
MCASP_RX_MODE_DMA);
9 U& u. Y8 d* f3 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," e! b/ N4 d% E- Y$ k# \; q3 B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// I& q" x* B \+ z: y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 T: z3 R! Q* k) ~& e. C! _4 Z4 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) [* V& z# D( ]- @$ c) R" n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 j4 O& h. }% n% a9 m- O9 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* R& G5 {9 M$ C7 J8 sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 W' k) m1 E( N: oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 [ Y, t0 r8 {+ r0 Q; z# ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 P& Y# M9 N/ A
0x00, 0xFF); /* configure the clock for transmitter */9 e* i7 }8 p! L- ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ A6 Y" X0 Y3 G7 n8 L9 qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! ?6 P2 H! k$ u2 N7 K- T% r+ j! G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: Z+ ]% S+ _; U' Z# i: E9 H0x00, 0xFF);8 I+ X6 k, H2 n8 Q l
Y' b+ y: c& @: A
/* Enable synchronization of RX and TX sections */ 2 G: T$ b$ L5 F4 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 j1 L3 w# I' {& Y) X8 b1 [+ W, R2 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); k+ H2 R5 b: c" ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# X3 ^4 f$ Y: v- K/ n6 Y
** Set the serializers, Currently only one serializer is set as1 U, k( r$ j& _
** transmitter and one serializer as receiver.4 P/ ^8 w/ F8 S) h2 i. }5 ^. ]
*/
9 }' z7 B! C; B, z; X! {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. j$ Q& S' I/ W$ l4 \) e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** _4 T2 t* c: f2 M, q p& J
** Configure the McASP pins , _" p& `: F8 L) Z0 V" W: ]$ x; h
** Input - Frame Sync, Clock and Serializer Rx# _8 F+ B; y; j! F5 B8 g3 S1 B
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# s, J: r3 z( s3 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% G0 t G$ A2 E0 ?+ I& n6 U, [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX M e v; j' D/ |% K' ^
| MCASP_PIN_ACLKX6 d1 n. ?- |5 O+ |! i/ a9 h
| MCASP_PIN_AHCLKX9 c! P" @% r2 u" m0 U' R- J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* c5 X9 H8 p: k' N$ n; g+ Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! J7 v, V1 F& x# `% c9 b7 q% `8 i" D
| MCASP_TX_CLKFAIL ; ?, @3 i/ C+ g- b1 g9 h/ d9 O+ J/ x
| MCASP_TX_SYNCERROR N% F) b' l0 p( U6 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 Z6 a- V# n# \ y0 I; _2 `
| MCASP_RX_CLKFAIL+ z( d0 n ^8 M9 n2 |+ q% O
| MCASP_RX_SYNCERROR # M ?2 D. v/ H8 s7 d
| MCASP_RX_OVERRUN);0 ~0 R2 Y0 q# y" m4 H( R! {8 y
} static void I2SDataTxRxActivate(void)6 B4 ]2 [$ N" H# S' P9 k
{; j8 `* j, b; X
/* Start the clocks */- B) V0 H8 i8 `/ `7 L. T6 m7 I4 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 c) Z8 E8 p1 X$ \; D. HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 O& Y# J5 E5 e& @! C( I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ~; c' X& _8 O% t4 Q0 H+ xEDMA3_TRIG_MODE_EVENT);
( V/ ~, k0 D# W- @6 i" O4 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( Y# e; C) ]" E6 \% P( d6 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- V$ {- N; O. ^) r( \# U. X2 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 j+ b* l) A, ]5 e, `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ H# S6 Q t' u& N+ Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ i8 r7 V9 H6 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! S0 |) M8 f/ n9 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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