我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ S2 R! f1 G4 ^5 }5 I; p* n
input mcasp_ahclkx,# v G) p- }0 e1 G
input mcasp_aclkx,9 s$ o7 Q5 S" c$ N- f1 s& }6 K
input axr0,+ v( H2 R" W! d! ^+ L
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output mcasp_afsr,1 W( G+ T2 U9 T' M4 y
output mcasp_ahclkr,
! t3 A- D! W! ]/ a/ |+ Youtput mcasp_aclkr,
. x" t8 _& v/ @7 w" p' @output axr1,2 M% u& Y0 m3 {! T7 _- [
assign mcasp_afsr = mcasp_afsx;
0 \: i0 J' X0 ~) A+ e- N+ eassign mcasp_aclkr = mcasp_aclkx;
7 K& B M) x4 Massign mcasp_ahclkr = mcasp_ahclkx;
7 P4 X4 W5 J5 J* w6 I' a* n2 A4 oassign axr1 = axr0;
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; W0 [' K0 n2 b/ E( H0 P; U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' _; j9 w! j( C& g* D
static void McASPI2SConfigure(void)+ F8 ~( h1 z5 `1 ~# ]$ N7 z" U
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 \9 {' w6 `$ c/ n" A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 Y/ Q! c S1 u) L/ dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 K- k0 H" o! m1 {; E( P( Z& G4 R' J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 _) V/ n/ [0 e7 @2 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 C% |* y U* q' _3 F# H
MCASP_RX_MODE_DMA);
5 ?1 ^$ R9 @) [3 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 [1 z- D& {5 ~) p. L7 d+ VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# N5 O- b/ W! v' |3 x3 A6 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 B7 v9 K7 x) a" S& B. x8 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" p; n/ u2 b1 F; [$ L, J2 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& z& O* s" k6 O$ Z! LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 Q9 c3 ~; n! i' x3 M! @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# G7 P! ~, x! f; \! m& WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 z. k0 K. n9 `& T1 }9 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 n$ E- N2 W2 v7 M2 b
0x00, 0xFF); /* configure the clock for transmitter */; g7 G; T7 u+ Y6 i' a* [% i) Y0 X: R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 K6 A! F( n5 F# _4 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 w6 \3 |3 R" T5 k; D9 [; H. H1 gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- {8 e" O7 O' i3 T8 ^5 F* E, `1 Y2 [0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
: o* h, w0 F# Q2 }% pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 u: h5 u6 j8 P, c% M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 t7 I, }6 h! }. g; G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 ~( g2 r9 k8 E* f. `** Set the serializers, Currently only one serializer is set as# V: S, ^' i4 J) @+ b3 p
** transmitter and one serializer as receiver.
+ t4 q9 q8 M" R5 J*/
1 k9 ~8 y8 Y# B) Z8 k: u9 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 N% s7 a& }( J. Z- F* y* OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. t/ l# ]) \6 b4 `, o$ w, {
** Configure the McASP pins ; s9 _* z9 l2 O, Q
** Input - Frame Sync, Clock and Serializer Rx$ h7 h" i) }- b* N, ?. Q
** Output - Serializer Tx is connected to the input of the codec
" B9 j8 T5 a3 C: V/ I" o$ R0 N. ~*/
2 v7 u' k( C w6 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 r; x, @/ l! }7 W' Q gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( j6 X; v6 I6 @$ R; T$ ~ }0 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ J! [% ?& N5 [% t
| MCASP_PIN_ACLKX. T; e0 B& u; e$ p& Y9 e6 d5 c
| MCASP_PIN_AHCLKX% G+ G8 l+ K( x- s: m0 g7 R3 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ~: r+ D* S/ }% x7 y% |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# B1 O0 S) A$ [0 R" ]7 d| MCASP_TX_CLKFAIL . g `, V$ j6 M7 k
| MCASP_TX_SYNCERROR5 p2 [8 ?4 R" X$ L1 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, f* H+ l. h4 _7 m! A| MCASP_RX_CLKFAIL& u% P9 E/ S- s5 k
| MCASP_RX_SYNCERROR : p. \( @+ m, q4 `4 S, V& i, }5 ?, x
| MCASP_RX_OVERRUN);
* @( S- P, F/ c# W t8 M} static void I2SDataTxRxActivate(void)0 V ^9 u1 D/ V5 ^& X( D
{
! T! V$ ]7 @6 @- m2 p/* Start the clocks */
9 T4 H6 b# T" u7 ` ?' H: p* k( lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, u$ G% D _% N: L dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- J8 U' g2 G/ \1 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 Q. V" m, N9 J# _: |( i
EDMA3_TRIG_MODE_EVENT);
$ |1 h- H7 E$ ]2 |* u( v# lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 P0 J* W# l8 _2 I% B4 GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 E& P1 K1 Z% r9 p) K* i0 _! V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# \. [) x6 N) @$ wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' ?) q0 K2 G! [6 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; d" o$ G& z) z0 Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" x/ P, ^- \, E. S1 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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