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我的McASP配置分别如下:
: O5 J6 g3 U6 Z e( b5 Z2 ~管脚的复用设置是:
% k6 f, Z' t/ C6 G4 c5 H5 i; }9 uvoid McASPPinMuxSetup(void)
" Y: O4 E3 ?0 C* S& M{
6 J2 r- ^! H- u unsigned int savePinMux = 0;
1 ~( o/ o5 J6 q+ _4 t$ @/ ` savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \8 b% y5 Z F: X( o3 e, @. p4 t
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
: k/ E/ z8 B. w! Z; [* g; y1 i SYSCFG_PINMUX0_PINMUX0_23_20 | \
4 L) o+ g6 y2 I/ | SYSCFG_PINMUX0_PINMUX0_19_16 | \
6 a# z, _9 k' |! U! D) z6 S! x b SYSCFG_PINMUX0_PINMUX0_15_12 | \4 i, _6 O t: G! X- b
SYSCFG_PINMUX0_PINMUX0_11_8 | \
8 K4 D4 Z1 ^) k' j2 Y SYSCFG_PINMUX0_PINMUX0_7_4 | \
# {4 m3 h1 U4 p2 [ SYSCFG_PINMUX0_PINMUX0_3_0);# j- }, k+ l+ G& @$ F! D, ]. I7 \, J
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
& F2 G2 g! v, p8 c) X. ]- ?6 N) K (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \9 Q/ g1 n5 `) y; U u- L
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \; f: V& {; X+ T7 n% E& b
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \* m" N# I# c3 \0 |0 {8 |
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);# @: t3 Q/ E" U! r5 I
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \9 r; m' a& S1 U' o; s' ~4 q) [! _' A" M9 J
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
# `5 C) \2 q$ ^& a+ M; i SYSCFG_PINMUX1_PINMUX1_15_12 | \
& Z8 a7 J( l% E# }0 i5 e p% c SYSCFG_PINMUX1_PINMUX1_11_8 | \2 n8 m9 S' D; M2 F* f
SYSCFG_PINMUX1_PINMUX1_7_4 | \- p7 K O/ A" c% k4 L
SYSCFG_PINMUX1_PINMUX1_23_20 | \( s, E$ |: O2 E: N, ?
SYSCFG_PINMUX1_PINMUX1_27_24 | \% b1 i4 s2 U$ D6 ]: ~5 S) n
SYSCFG_PINMUX1_PINMUX1_31_28& v$ `0 H- C8 S- p" c/ }
); l" ]" ^9 J4 r. q) H5 I }/ s
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \/ r7 {0 o; [. j0 E
(PINMUX1_MCASP0_AXR11_ENABLE | \
- L5 g' x# L6 _4 H: @4 ^ PINMUX1_MCASP0_AXR12_ENABLE | \
0 @/ B/ k9 t1 J PINMUX1_MCASP0_AXR13_ENABLE | \- w* Z1 T. |( n& p- k
PINMUX1_MCASP0_AXR14_ENABLE | \
- [" C; G S3 c8 l PINMUX1_MCASP0_AXR8_ENABLE | \
& D8 f2 e/ J( q% } PINMUX1_MCASP0_AXR9_ENABLE | \
9 Y" c6 J% Z: G PINMUX1_MCASP0_AXR10_ENABLE | \
5 m6 c3 M6 R0 _8 m( I savePinMux);
! b8 E; O5 w* B$ m/ |4 i2 e7 T}! }4 P1 q' ~* k7 _5 |- _5 h$ b
; T" m& W& B3 Y' b, i; _1.McASPI2SConfigure(); McASP的配置程序如下:
- q5 V; l1 j zstatic void McASPI2SConfigure(void)- }) n) |5 G$ C, d2 z. v. m
{
+ I7 x7 H ^8 g4 F" i' A McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 X+ u" L: H1 ^5 c5 N T McASPTxReset(SOC_MCASP_0_CTRL_REGS);/ O* Z$ {! i7 Q# o5 {" n
$ D, m0 R3 z+ h /* Enable the FIFOs for DMA transfer */5 r" |. Q" e% K6 A A
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);! s4 y7 M0 `* k( ?; z
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( S% z7 q/ {: Q; Z0 |4 \0 P& x
3 w, H. x; ^! C /* Set I2S format in the transmitter/receiver format units */5 S* e6 \7 ?2 ~7 U4 V* u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 i1 H7 y3 w$ p9 h2 } \ MCASP_RX_MODE_NON_DMA);& P) M% E4 N8 P; h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 q2 q& m9 r8 X! V' S MCASP_TX_MODE_NON_DMA);" }: Z) w( d! s. ^+ G+ D
6 A Y5 d( a a) E0 I /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 [3 V( V3 K) w1 l C; S) ^0 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, V' I; }& X7 i3 k7 X3 t; t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 P5 [' m4 F' x, ^: e8 V% L) t+ w/ V McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 T9 P; ~6 s7 x2 Z( `/ y
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
. I+ R# p( B& e7 t7 E# C$ a
1 d# d& ^, ~& U( w& r$ M /* configure the clock for receiver */
# j# ]3 C7 y* w# k* H// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);9 A- p3 M( I7 S, d/ R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 a, M8 M$ I& R4 n1 c% B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);+ N9 @8 w% ^5 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( j. Z/ t) r$ o1 e/ `( K% y4 u& _ 0x00, 0xFF);
, L# ]( ~' }" c5 F
! [) h/ z: z9 K, W/ b L* u' [ /* configure the clock for transmitter */0 g5 e4 w3 ~- L$ b, L6 n
// HWREG(0x01D000A0) = (0x00001F00);( N2 f p' o; a5 j# J" Z, R
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
& }: m- e2 G% R9 j1 |0 g McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
$ T- H+ f+ D! \/ K/ _0 f! Z8 i McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 g# z. D! r" g; F7 q McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 X2 R6 \' _# G5 L- M4 B
0x00, 0xFF);
7 J, T9 \: m% ]3 [/ A8 } . A$ w/ D0 ~4 m
/* Enable synchronization of RX and TX sections */
" _1 S0 K$ ~/ i. C8 c McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
$ _4 f! r4 F$ |6 V( E/ N* v- ]/ E4 D; E! o/ }% g
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 A' R" v! L4 }% H' Z McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ w7 r0 ^% v' T! ?% O- L+ F! Y! S; M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 b4 v& C6 o- o& }& S% z/ I- X9 D, b
/*: n7 C) a/ Q& j3 j+ U& u) h9 j
** Set the serializers, Currently only one serializer is set as
S1 G8 U4 ?3 W0 a7 P* r ** transmitter and one serializer as receiver.
7 a2 f9 m* G' I" o6 [! } */
+ z2 @1 Y+ U( ]& E, [. F/ z McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' Z) ?+ i/ c* t# h2 \% n# \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);6 M7 @: ?' L, B0 X8 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
0 x/ b; x9 v' D: E! X) j; R: Y6 p McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
) s6 J/ ^7 [% b1 d: Y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);3 n0 l L7 O+ l+ h" s$ _) U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);+ ~! C S2 G- T7 Z0 v9 K
/ I* ~: {3 B6 [2 Z McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
" W: F% c! f% }5 c1 i1 K1 i! M% h+ q: ~( @) D
/*
/ y+ O. j, ? v# M3 F/ {, G5 H ** Configure the McASP pins & f; R" B; m$ |- a& C) @
** Input - Frame Sync, Clock and Serializer Rx
9 O# j8 [! Y0 P9 T% A) r ** Output - Serializer Tx is connected to the input of the codec 1 O& x. P5 @1 t: F/ K. N
*/, K- M9 ]5 h4 L) W6 Z7 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& W' _ d+ |! k4 Y9 z2 y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,' X4 j6 U/ [9 B, B: n0 ]
MCASP_PIN_AXR(MCASP_XSER_TX), l I, A1 N# g8 |
| MCASP_PIN_AMUTE
5 W+ }, e8 M: l4 M );" y2 b. _9 F6 k6 B g7 `% n [4 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
7 ]7 e% p( O3 \* M MCASP_PIN_AFSX
2 x8 X9 O8 i4 T | MCASP_PIN_AFSR
' x( p) L ?7 O7 q H3 c | MCASP_PIN_AHCLKX# q/ @" n' j$ u" N! e! _
| MCASP_PIN_AHCLKR |! h" c& N# p6 [
| MCASP_PIN_ACLKX
1 a5 d/ [- ^' D$ w" p | MCASP_PIN_ACLKR
% l9 Q) ]7 [, U; `$ ?/ p | MCASP_PIN_AXR(MCASP_XSER_RX)
- p* r' N0 P; a7 k5 _ | MCASP_PIN_AXR(1u<<(13u)): J. c/ Y2 N! G2 [, } [
| MCASP_PIN_AXR(1u<<(14u))
2 r' P- L: Q4 I9 G( U | MCASP_PIN_AXR(1u<<(8u))
/ l! i5 f0 p0 F, c8 [$ _: w' o& a | MCASP_PIN_AXR(1u<<(10u))
# }0 ]: u$ w- r | MCASP_PIN_AXR(1u<<(11u))7 x% l1 _+ {7 j$ H5 ^" i! o
);
" D8 N1 f) f7 h8 N3 g4 |) e4 r8 H
/* Enable error interrupts for McASP */
1 k3 C% @% M. h n7 Y! a) Z' y8 p McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
; x8 o. r, U: S# ] _ MCASP_TX_DATAREADY
G/ Z4 v' L$ G: V3 ]2 m2 _; S: [, ] | MCASP_TX_CLKFAIL - i5 {8 ]: \% K1 N/ |& e
| MCASP_TX_SYNCERROR0 T6 z9 o9 k- J }. w6 V
| MCASP_TX_UNDERRUN);; Z2 g& s. w1 W2 F: C
7 G) ?4 O, T5 |. Z
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,1 u7 ]1 c# y8 ~) ~2 h8 W' n
MCASP_RX_DATAREADY
& q$ f3 _/ X( X | MCASP_RX_CLKFAIL
% V1 L! l" b/ r5 n1 A3 v | MCASP_RX_SYNCERROR : t0 ]1 W& \% B1 }
| MCASP_RX_OVERRUN);
* @1 M; W7 q: j0 O& f, y//MCASP_RX_DMAERROR MCASP_TX_DMAERROR6 S1 `' A( ?! H1 x; t4 p
* l2 N# S/ _/ V3 K
}# l! N1 t, n, z
( U3 p" g" e, ~+ ]8 ^8 V2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句. k! R3 A+ Z# l2 d9 {/ G) a+ f
static void I2SDataTxRxActivate(void)
2 |/ |, _- D3 r. S O2 H0 j) O& z{
6 C4 g0 c7 {% S3 I; h' l7 ^& [" A /* Start the clocks */ m9 ]) V4 A# X) i$ {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 s5 I6 u3 _7 `. M s McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);/ {, m. w9 g1 Y0 x% Y: w* w
) {0 x4 Z; K( R- W! X5 G /* Enable EDMA for the transfer */
; E5 I' [+ G) Y. B+ d) @// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: ^2 X9 M2 J! [. C- n8 ~- f2 M
// EDMA3_TRIG_MODE_EVENT);
3 j( z6 J/ G. F0 H; k// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,7 c* g6 J( T5 \/ g) j; b
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
. W& ~7 T$ z, {; y- b' B /* Activate the serializers */2 Q' Z) T: P$ Z5 [7 \7 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 h* y# ]! K. x0 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
: v0 I2 m0 Q5 f+ e& h /* make sure that the XDATA bit is cleared to zero */
. F' S: @+ t* a" J while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);& T- C) {% v, a* W7 p3 P" T
/* Activate the state machines */7 c- h: S& P3 F" m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ R& `. A" \. r% R; k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% j0 P( D, f! ?* Z McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
. }) e6 A# _2 ^- @4 J1 U- {}7 Z( u& f. a" ?6 J. x; c2 s
, _4 O7 o& k* } |
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