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The timers support the following features:
" A6 V0 Y, v7 t0 j• Configurable as single 64-bit timer or two 32-bit timers5 Z* h/ ]* L5 w1 I
• Period timeouts generate interrupts, DMA events or external pin events
# M7 F: o/ b7 |8 x% ]• 8 32-bit compare registers! d0 q- l6 J8 p: ~+ }
• Compare matches generate interrupt events
: r8 r. y: d& V- D• Capture capability
4 h6 q$ K" a: F6 R# m; i: \• 64-bit Watchdog capability (Timer64P1 only)
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/*! O5 ?# D3 V# s1 J+ d
* T0_BOT: Timer 0, bottom : Used for clock_event
! J- z+ C+ N; u. s- ^ * T0_TOP: Timer 0, top : Used for clocksource+ q8 q3 z( O4 ~% e. Q% D
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer; H/ i, \0 ]* [, @) S- J
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