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The timers support the following features:
/ K1 w) E% a/ L. y4 J. ~( Y* q! H• Configurable as single 64-bit timer or two 32-bit timers
$ u7 P" r7 l* _" n0 w: ]• Period timeouts generate interrupts, DMA events or external pin events
4 Z9 r2 k0 p2 q2 R+ Q* t+ N• 8 32-bit compare registers
9 N; P r) d+ o( S! m6 P# m• Compare matches generate interrupt events) e3 \3 F7 \& h' D/ ^& Q
• Capture capability# `% H2 H' s5 z: K) f1 E
• 64-bit Watchdog capability (Timer64P1 only)8 H7 ?7 D O6 |, D8 F, `9 F
/ p: B9 d' Q! W# p" I* Y0 v$ ?/*( b) _ G8 h! g+ C, V
* T0_BOT: Timer 0, bottom : Used for clock_event! ^3 w7 E5 ?( O2 S
* T0_TOP: Timer 0, top : Used for clocksource
2 p. B% q7 v. c1 [- I" T8 w1 ?, K * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer- `, k9 w5 t8 f7 p
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