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The timers support the following features:
: Z/ e% J, l6 a2 t0 l! p( \7 T0 b* [• Configurable as single 64-bit timer or two 32-bit timers
/ `7 ^& L) o4 i/ T3 ^% M• Period timeouts generate interrupts, DMA events or external pin events2 O) f" y4 ~" k T( ?2 ~- g& {/ R4 B
• 8 32-bit compare registers& U# ~9 ^; ~- b& o! B+ S1 `
• Compare matches generate interrupt events
# F# P0 C4 W' ], E8 y$ v" q• Capture capability
1 F6 G1 M; l. L• 64-bit Watchdog capability (Timer64P1 only)/ ~) H) H8 u/ r5 c* H! Z8 p5 N
: w; R, ?- l! L3 Y4 P( U
/*
, {6 a' Q( @# O" l* `* ~2 \0 E7 ] * T0_BOT: Timer 0, bottom : Used for clock_event
0 c# i- y: p- j% l * T0_TOP: Timer 0, top : Used for clocksource
7 Q, l6 X3 b% `( Y$ @) F * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
6 Q' {( j. l, I6 W6 q- q5 L( j */ |
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