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The timers support the following features:( o, S D9 h. l* Q) R* v5 B
• Configurable as single 64-bit timer or two 32-bit timers5 {$ ?9 ?# s' b# ` N) {1 _% p% H
• Period timeouts generate interrupts, DMA events or external pin events
5 J1 }. |) l! J* i" Y* e p• 8 32-bit compare registers2 J/ x( x' ~. r0 o2 R7 c
• Compare matches generate interrupt events& S( v3 K1 T o2 A7 r' ^
• Capture capability- r G o2 N& W8 d! V; @
• 64-bit Watchdog capability (Timer64P1 only). x5 _9 S2 _7 m0 a2 |, b1 R
( W( B o7 Q5 |3 } f
/*
9 F2 H! m7 X1 `5 Q+ @ * T0_BOT: Timer 0, bottom : Used for clock_event
9 n @9 k1 ]1 n3 y- z6 N * T0_TOP: Timer 0, top : Used for clocksource
; b0 B7 T \0 M* L" b1 V * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer- E# r" a- d8 J/ z# r3 ~
*/ |
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