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The timers support the following features:) h, @1 p, Z& ^$ D+ ^+ b8 E
• Configurable as single 64-bit timer or two 32-bit timers
$ s8 s: S4 \' E: t- Y0 u• Period timeouts generate interrupts, DMA events or external pin events- C5 G4 \5 M5 C( U
• 8 32-bit compare registers$ |: }2 u7 P1 T. K4 f* B8 _% u" a+ {
• Compare matches generate interrupt events+ j# K6 ^+ _" u% s, R: r
• Capture capability3 }; a! Q# A" v+ @* f1 y6 S9 f
• 64-bit Watchdog capability (Timer64P1 only)6 b9 \/ z- }& ]4 T* r
+ H: U5 ?" }: J2 R7 A
/*
( i; W: }! T7 ]3 B( y) k * T0_BOT: Timer 0, bottom : Used for clock_event
$ X6 t% A) [( W. X * T0_TOP: Timer 0, top : Used for clocksource; N" A+ Y& c) l/ H( O5 \4 I% U0 u7 V
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
. O$ B K6 I& H' v# O! r */ |
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