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The timers support the following features:
* p8 Z; V I# @& L1 v" w• Configurable as single 64-bit timer or two 32-bit timers
0 V/ j. X# u+ j6 r• Period timeouts generate interrupts, DMA events or external pin events$ W( |4 Z/ g3 @. e9 F+ y
• 8 32-bit compare registers e8 k: M O. ^
• Compare matches generate interrupt events2 j8 n' W7 l1 E( @
• Capture capability
6 ]+ t' B) K& I* X9 H+ d3 o; `• 64-bit Watchdog capability (Timer64P1 only)3 ~$ t( j5 v5 n
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* T0_BOT: Timer 0, bottom : Used for clock_event+ |* B2 U" H3 n: }
* T0_TOP: Timer 0, top : Used for clocksource! e( b5 g S( S& j+ K' D) }
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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