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The timers support the following features:
" g* v4 y+ {; R! t$ p• Configurable as single 64-bit timer or two 32-bit timers7 [% A6 N2 s4 i, I& t" Q. I
• Period timeouts generate interrupts, DMA events or external pin events
3 i) K! B% p4 `3 [• 8 32-bit compare registers
; M0 }5 ]% d6 c9 e/ d+ ]• Compare matches generate interrupt events
" x# U; C' {9 b: {• Capture capability/ T, }7 i* e% f- L, i: Q
• 64-bit Watchdog capability (Timer64P1 only)
6 J/ y4 o% Y- i, p- q! G. |, K; |/ \, h6 N# v0 t! @
/*
: ^# l1 M) A% u. A* `7 g+ } * T0_BOT: Timer 0, bottom : Used for clock_event& `& M) T; f4 O$ \5 C7 f' b
* T0_TOP: Timer 0, top : Used for clocksource
+ a, Y# L; Z6 X6 q* F& C: ^. X * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
6 U( {' `9 N, G' [6 H8 E" x: L */ |
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