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The timers support the following features:
7 Z/ F6 q- O* q% ~, U0 k% V• Configurable as single 64-bit timer or two 32-bit timers
/ h9 g6 C! C" O* H• Period timeouts generate interrupts, DMA events or external pin events7 ]1 o* v9 t# T% ~5 u; J. q+ D
• 8 32-bit compare registers
/ h/ X: \* L$ J2 q/ t: M9 z• Compare matches generate interrupt events4 k; W4 C0 E% \- V8 `- q: e9 T
• Capture capability
/ C$ U6 T+ V* z" t1 n+ ^• 64-bit Watchdog capability (Timer64P1 only)
) F9 |# {# t+ H6 i l; n, H% ~: O4 f# V7 ^
/* Z1 H1 ]7 j, n/ Q0 M
* T0_BOT: Timer 0, bottom : Used for clock_event
0 F* z( W8 k: s4 f: g * T0_TOP: Timer 0, top : Used for clocksource
2 R+ A! {. _' H: H * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
! l1 F5 M% o1 n! E8 [' T4 U* I* n+ T */ |
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