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The timers support the following features:) N- J3 I0 M% ]4 H7 {
• Configurable as single 64-bit timer or two 32-bit timers
# n+ E, a1 W4 X: e: M* P( }3 ~• Period timeouts generate interrupts, DMA events or external pin events
! b7 P# \ ~- ~& a" x2 T; C• 8 32-bit compare registers7 L X% y: ]9 j4 A: t9 q
• Compare matches generate interrupt events
g% i8 X. ~7 S/ Q6 ~2 G, T i• Capture capability
3 D1 S& S: r& R: [: u( W2 Q• 64-bit Watchdog capability (Timer64P1 only)
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* T0_BOT: Timer 0, bottom : Used for clock_event
) Y0 _( b% w0 h7 G7 `% E9 ~8 ~ * T0_TOP: Timer 0, top : Used for clocksource
( L }* z: M b- p# ` * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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