|
|
The timers support the following features:
9 _5 K5 j$ f5 U8 S0 i• Configurable as single 64-bit timer or two 32-bit timers
7 T0 t5 H2 p- q• Period timeouts generate interrupts, DMA events or external pin events2 T% e# S: G( d6 q% p v/ M
• 8 32-bit compare registers8 c5 h8 a, m6 H
• Compare matches generate interrupt events3 e; q3 c4 @/ M! m% G& h
• Capture capability, q; D$ q1 Z2 v0 ^8 Q3 u, {$ U! z
• 64-bit Watchdog capability (Timer64P1 only)
- K# w4 }0 k7 V3 X$ L J: b
$ {7 {% ^7 c4 L1 g5 Q/*: ?5 L# I+ @ X) n, X3 c9 R
* T0_BOT: Timer 0, bottom : Used for clock_event
' u3 J2 s2 u9 F+ n, H& r7 F * T0_TOP: Timer 0, top : Used for clocksource
& T- V) f g& O/ v" e6 l * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
- I' u# n9 u1 ]2 f7 B0 ^ */ |
|