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The timers support the following features:. F) o3 ~, P+ g$ v. L) U, R
• Configurable as single 64-bit timer or two 32-bit timers
. y1 }3 D7 ~' }8 f3 w; b• Period timeouts generate interrupts, DMA events or external pin events8 B0 [# m' E' T, t# S2 d4 ~
• 8 32-bit compare registers( p, A) F9 g, x+ t
• Compare matches generate interrupt events9 s+ b/ l3 n) ]$ M
• Capture capability4 X. o: \& w- L G+ ^+ ~
• 64-bit Watchdog capability (Timer64P1 only)& E3 e. f% e3 {9 E/ R% R o
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4 r+ T1 G6 W# h8 D X * T0_BOT: Timer 0, bottom : Used for clock_event/ B, H0 ~+ b# T2 X9 _6 ~
* T0_TOP: Timer 0, top : Used for clocksource
! l! }" K9 E0 s9 c * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer, K' E: d7 ^) v+ Z( _! f8 z. c
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