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The timers support the following features:/ G( r! z1 W. b8 ~- d
• Configurable as single 64-bit timer or two 32-bit timers
3 _# D3 Z; t/ X) W# Z' w. g• Period timeouts generate interrupts, DMA events or external pin events
: e5 j' p& v1 K4 ]• 8 32-bit compare registers/ V6 b) u3 J% o0 I$ V! V9 e! i( ?
• Compare matches generate interrupt events+ K) u0 e# [7 ~/ ^$ E2 Y0 c
• Capture capability
( j" ]$ ^6 K2 t/ |1 t5 U& u( |% G• 64-bit Watchdog capability (Timer64P1 only)2 c% k H& k# J) n8 `+ @* `
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/*
# [$ @1 Q' d# @7 W# [ * T0_BOT: Timer 0, bottom : Used for clock_event+ m9 ]' {+ I8 a( a2 y
* T0_TOP: Timer 0, top : Used for clocksource! r7 }' b. T; b$ c( P( ]
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer* g# r- \8 [6 X2 Z' ]
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