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The timers support the following features:
/ Z" Q4 n* a* N, U: R+ Q, W+ u• Configurable as single 64-bit timer or two 32-bit timers. V! r3 {" ^7 q7 a$ h
• Period timeouts generate interrupts, DMA events or external pin events
N6 B+ X- F2 y' S4 H• 8 32-bit compare registers
* A3 a: k( t, P$ A: a5 q• Compare matches generate interrupt events! u1 W) {" }) w0 ]
• Capture capability! E! Y$ z' H* N) ^+ ~: N1 @ ~
• 64-bit Watchdog capability (Timer64P1 only); h& i1 a8 m* K. b2 u. m2 I
$ N) R7 x5 i9 I S1 Z+ z" d a4 i
/*
2 ?1 N$ @8 b$ E# c9 ~- C * T0_BOT: Timer 0, bottom : Used for clock_event/ V% b O& {$ t5 j+ L! K$ B
* T0_TOP: Timer 0, top : Used for clocksource
& I- Z# z; u7 P * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
& p4 Z8 C* C6 u8 N$ M$ Q' A */ |
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