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The timers support the following features:9 l, v1 R1 \- O8 V# [% I$ I% \
• Configurable as single 64-bit timer or two 32-bit timers
/ M9 s. p, {: w1 L! M• Period timeouts generate interrupts, DMA events or external pin events
7 q& l9 M' k: U' J• 8 32-bit compare registers7 D9 \2 a. }: J! r
• Compare matches generate interrupt events9 _0 v$ P b& k/ n9 X9 f: L( s
• Capture capability, s( B! B4 G9 _: }9 @. f# V/ I/ ^
• 64-bit Watchdog capability (Timer64P1 only)
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/*
, X' Y. L$ ~$ h1 ~0 c! f2 x * T0_BOT: Timer 0, bottom : Used for clock_event
1 W1 r& {. Y5 ]1 p; e+ x! ]& x$ R * T0_TOP: Timer 0, top : Used for clocksource b' \5 z, v" u2 N9 d
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer* [% p, b1 T/ ?, g
*/ |
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