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The timers support the following features:0 g! ^! q* g* s }/ J
• Configurable as single 64-bit timer or two 32-bit timers9 m& P. y+ g1 ^3 Y( ~8 B# x7 r2 z
• Period timeouts generate interrupts, DMA events or external pin events: H6 k- {5 N9 V+ Q5 m8 R8 B4 M
• 8 32-bit compare registers
3 E) I. N. V8 B0 \, C% h9 f6 _• Compare matches generate interrupt events
- } S; E6 T* t4 M; c! h• Capture capability& N, ~1 f$ W, |$ ^" a: u
• 64-bit Watchdog capability (Timer64P1 only)
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/*7 R9 d2 w; P5 t! z0 B7 U. y
* T0_BOT: Timer 0, bottom : Used for clock_event
# X0 r: ?* m H1 F/ Q! { * T0_TOP: Timer 0, top : Used for clocksource. S2 x3 A. A, K4 ~ K5 n0 n
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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