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The timers support the following features:0 f7 [) K6 \4 R2 d
• Configurable as single 64-bit timer or two 32-bit timers
0 s5 n( D2 \# o4 P/ r• Period timeouts generate interrupts, DMA events or external pin events$ w0 U0 n! o7 T! _: u, J5 _( }7 D
• 8 32-bit compare registers8 {0 C6 K3 J& f) t$ b
• Compare matches generate interrupt events
7 Y: g% h( ~1 X0 e8 ]• Capture capability6 Z% ?6 K4 P6 f9 O
• 64-bit Watchdog capability (Timer64P1 only)) E F$ O0 D6 D
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/*9 M' h$ g9 m5 q+ `3 k1 t, Z
* T0_BOT: Timer 0, bottom : Used for clock_event
4 u! w! u; S) k O6 j6 e * T0_TOP: Timer 0, top : Used for clocksource2 L$ L2 U" ^/ @9 ~/ `0 e
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer# T( G# Q& |, }, _# c* i
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