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The timers support the following features:
" ?) ~% J; y' ~% @- N3 D• Configurable as single 64-bit timer or two 32-bit timers
+ q8 Z) `" s# _! T7 _- Y# {• Period timeouts generate interrupts, DMA events or external pin events9 M4 u. W( T; u6 ~+ ]
• 8 32-bit compare registers
4 \+ z6 A: N$ _3 V# A" g9 j- k• Compare matches generate interrupt events5 w0 ?( M3 m, X5 t
• Capture capability
1 A7 q) w% ^) v• 64-bit Watchdog capability (Timer64P1 only)
1 v8 v- I/ m$ i# K0 Y$ U
5 G. C! G' h/ z/ I3 u+ t# C/*
- a: c; x, O, A * T0_BOT: Timer 0, bottom : Used for clock_event( R& t; G( H8 K% S* E' e
* T0_TOP: Timer 0, top : Used for clocksource# D a' V! {$ ?2 ^3 N- x: g
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer/ O: M( {' B1 K
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