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The timers support the following features:: u) S/ {8 `1 y# y* }5 K
• Configurable as single 64-bit timer or two 32-bit timers
3 u/ b: V) Q! ~) E0 F• Period timeouts generate interrupts, DMA events or external pin events
4 \- T) k, A9 I5 S8 N$ @• 8 32-bit compare registers
4 e8 X$ j/ y! u9 t" a8 e' A2 o• Compare matches generate interrupt events
: }/ f. i6 C L& h* O$ n+ r• Capture capability
- j. q# ^' J) N9 K$ F• 64-bit Watchdog capability (Timer64P1 only)5 `# B7 L( E4 ], R# M! x
5 x% B. Z2 S4 a
/*
% h7 E9 s# O+ g( [4 @/ G( G# R! F * T0_BOT: Timer 0, bottom : Used for clock_event
! @# P [3 i8 V" `' i z e% d, @ * T0_TOP: Timer 0, top : Used for clocksource
/ Z' d8 m) V. D. e7 {$ d * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
5 o& d6 Y8 J9 j4 b) W$ \ */ |
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