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The timers support the following features:1 S( T0 u# l( q) a- }+ k3 R
• Configurable as single 64-bit timer or two 32-bit timers) x# E& y4 o9 q. w K, k
• Period timeouts generate interrupts, DMA events or external pin events
$ q" m& H5 i) r) `2 I7 n. q• 8 32-bit compare registers
: I8 |& w' D6 |$ Z• Compare matches generate interrupt events
; ~. ?7 h, N+ V j• Capture capability1 F% G: w+ l; z+ T5 r- ^) Z
• 64-bit Watchdog capability (Timer64P1 only)
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- d! w* q! [) [) @+ F6 {% f! n9 G * T0_BOT: Timer 0, bottom : Used for clock_event
0 N1 C" p1 b6 C; c1 f; p2 q * T0_TOP: Timer 0, top : Used for clocksource
5 w1 I- @2 ~( Y* F0 {6 u( W * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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