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The timers support the following features:
7 r4 v7 V8 t) {; ^• Configurable as single 64-bit timer or two 32-bit timers
7 F2 I. R. l' Q9 G• Period timeouts generate interrupts, DMA events or external pin events
. d9 W# j7 i& O' S: W# X2 E0 e- d- D: Q• 8 32-bit compare registers
, v! g. T! v5 V/ \• Compare matches generate interrupt events7 C3 ]1 M' Q5 O/ Z# b
• Capture capability
y3 ~- h: m. M1 ]• 64-bit Watchdog capability (Timer64P1 only)6 |. H# N$ j3 ~* }9 h' w# F4 d+ z
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/*
' U" s; p" ~: m R * T0_BOT: Timer 0, bottom : Used for clock_event, {. `0 Q, Q4 n, p: I9 t _7 T
* T0_TOP: Timer 0, top : Used for clocksource% K K- k$ @% a+ j
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
2 j4 c% z$ |* j */ |
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