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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" }1 I" e% a: h- A* iinput mcasp_ahclkx,- v0 O8 [: t' U& z/ ^/ I3 T
input mcasp_aclkx,6 S; P& W' c+ Y4 F+ v+ F; [
input axr0,
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5 m; m$ ?) y1 ]9 f+ s6 x/ j, M. x: F4 ^: Xoutput mcasp_afsr,/ e7 i7 R6 f7 N
output mcasp_ahclkr,1 W+ D1 B5 D. _7 l$ T" h
output mcasp_aclkr,7 x s0 o* b/ v6 i# \8 F, C' @/ \
output axr1,1 `% b3 P$ X8 x" q8 _
assign mcasp_afsr = mcasp_afsx;0 W& t' F- w3 E: s' i6 _/ a. \- z
assign mcasp_aclkr = mcasp_aclkx;
- b) P- e7 w1 N' l5 Dassign mcasp_ahclkr = mcasp_ahclkx;% Z* O7 v+ }7 ~6 d! w) k1 C. ?; Y
assign axr1 = axr0; ' |! e/ q7 n' n* M0 m
* I+ q5 j( z) V) ~4 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 J8 ]/ ?/ j# u0 [0 M
static void McASPI2SConfigure(void): h, b3 [5 f7 L6 L3 J9 k
{. ~. Z7 ]+ I3 r% D$ \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 I `1 f9 j% f6 Z x$ C7 w$ ~& ?6 M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, T) x* [( j/ k( }# s- V! uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 y8 z- ]' r' w' E& B# S- K; `3 s; B5 mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, N, A) N! P: h" N7 C+ v' dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* T/ N" X0 [* r' r7 e9 KMCASP_RX_MODE_DMA);
t: u: x; C6 W) |% ], uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# n/ H7 a5 Z7 m/ m( p- ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: u( \, M5 G. }; M0 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 `3 x! _$ J8 [8 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# f+ i% a( p( ?! w. X1 X+ i1 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + N- R' z: y& V. X9 I( b# z5 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// v8 x3 J' @0 Z( a# l' L: }" K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 ~0 }5 C2 k1 W" D* M6 R0 P) ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' y7 i+ N3 h: _. b: e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: h5 R! ?0 S9 x8 [; I! R8 X" f
0x00, 0xFF); /* configure the clock for transmitter */
/ B, [) ?. \! G+ Y+ Z7 EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- e$ \2 C) O; x! E. W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # F: Q' a6 E& T6 M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 s) W4 t5 {0 t3 ?. [: ^# B
0x00, 0xFF);6 s% e( t; Z) E( z
4 W6 m* s8 V: j+ l* [% o, a
/* Enable synchronization of RX and TX sections */ ; j7 w* x. E! J" w8 N) l- |6 @2 R/ H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% z7 c( u9 Z: g3 O6 V/ CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 y( D+ O# r0 a% w4 s! ?4 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; G: B4 P& G) `. u. l, e. s5 n U** Set the serializers, Currently only one serializer is set as; d+ |' w* w% Y9 t+ l
** transmitter and one serializer as receiver.2 B* w5 J9 O1 U. I
*/8 N* L- ~" R! g+ k: T/ ?" B9 S! r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% X" Q, D' N g8 H1 \8 GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 T7 W: q8 Y7 Q9 x4 B. a
** Configure the McASP pins 5 h- P/ y0 {2 O; z6 Q
** Input - Frame Sync, Clock and Serializer Rx2 h: b& S1 U( m2 g
** Output - Serializer Tx is connected to the input of the codec 5 S; F) E1 s8 F9 H/ l
*/
* q) ]2 I# V) d5 c- @7 i) m& m/ {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. J( ~! d7 ]1 Q; Y" I# I/ D+ v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); _' K& E7 H' C9 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; U3 V; e8 R4 e5 d {| MCASP_PIN_ACLKX
5 F" A1 U4 ?3 x+ `; c: g b| MCASP_PIN_AHCLKX+ `& f8 g1 k" C M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 W3 A. Z4 Z+ w( A6 D% WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 j F. u9 `0 z* }1 a' L. r8 V| MCASP_TX_CLKFAIL * s+ Y' z' D/ y$ y; o$ k6 x' _9 d
| MCASP_TX_SYNCERROR
* w' E. d: z" U6 {+ ~3 w& F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 d4 z; f4 j& f/ _; |" P6 s! Q
| MCASP_RX_CLKFAIL* X9 j) S) U" B& C4 J
| MCASP_RX_SYNCERROR / D, M; r. p" Z* `# d
| MCASP_RX_OVERRUN);
0 m4 z+ R# G4 [7 l8 R0 K" G8 m} static void I2SDataTxRxActivate(void)6 r( S( I1 j& `; P
{ f7 K. _0 W# X7 i* c, x
/* Start the clocks */) g- @1 }3 Y3 p( @* ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 M$ G- `8 p, ~% H' @, m2 s3 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. @3 o, E5 D! x' Y& UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& L. U1 Z. a, l- P5 F: ]
EDMA3_TRIG_MODE_EVENT);1 s! T2 [0 Q# F8 j7 U8 R/ m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# h+ K6 j7 t/ v# t- U9 h! z3 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* B4 m! g% h6 s1 ]2 G! [2 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, f2 F2 w/ Q, {. Q. p* i& j: l3 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 Y6 \( S5 D, {2 S5 L+ _* {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 c l, J9 @ t* W$ A( D- h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 H+ b- E6 m* [9 ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 h" L0 O* l' }* E& g- `; B d: g3 _. ~
}
. I/ p9 V2 _+ _; \* _+ ]3 l0 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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