|
|
我的McASP配置分别如下:
4 w6 r* R7 h7 h$ T6 b管脚的复用设置是:- j2 y3 _% T1 {4 `# N
void McASPPinMuxSetup(void)
2 e. B# G- Y) h8 h5 N6 A{
. C' B- g, l& _9 `! } unsigned int savePinMux = 0;
9 o9 X. ~0 Y1 O savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \4 }. V8 r2 |0 U3 Y6 J) W! I
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
$ O- N5 L2 A8 W7 Y* V9 i) C) F SYSCFG_PINMUX0_PINMUX0_23_20 | \
5 N8 u' A) t0 Q. m9 _ SYSCFG_PINMUX0_PINMUX0_19_16 | \
" E4 }: b x8 C8 K# k$ ?6 C- t5 A SYSCFG_PINMUX0_PINMUX0_15_12 | \
# ?1 l9 T" c* z8 e9 m SYSCFG_PINMUX0_PINMUX0_11_8 | \
; e* O! M0 a2 m/ l0 w SYSCFG_PINMUX0_PINMUX0_7_4 | \
, Y9 Q* {5 X/ x$ B2 R- v# V SYSCFG_PINMUX0_PINMUX0_3_0);7 F9 l$ H$ `' O+ G3 V3 d* L
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
1 F( G/ f0 C e* f- G (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
2 }: R# L/ D4 r- f0 b3 s- B PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \3 S) w! M# I2 n- _8 C( ]$ O
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \6 z. V# n( h$ Y* s
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
! N+ \7 v) c/ m# P! B( k savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
& ^) }/ X6 O" T. c, ] ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \+ E# r" K5 F0 l O7 |7 ~4 w
SYSCFG_PINMUX1_PINMUX1_15_12 | \. O5 l# i" N+ Z1 W& K; Z' M7 I
SYSCFG_PINMUX1_PINMUX1_11_8 | \0 e, b+ L* v; e3 D6 {
SYSCFG_PINMUX1_PINMUX1_7_4 | \
4 w7 @$ ]# L& T; q& ?1 W f' m, {; U$ U SYSCFG_PINMUX1_PINMUX1_23_20 | \
) M" }8 Q% i# o7 y* z, i5 _ SYSCFG_PINMUX1_PINMUX1_27_24 | \7 \, r' b2 O* I% a( a
SYSCFG_PINMUX1_PINMUX1_31_28! C1 Y$ z% e" u8 w+ J% f
);4 O8 g- s$ B ^9 j2 _
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \4 r$ Q( F& A* R1 o# f2 k
(PINMUX1_MCASP0_AXR11_ENABLE | \
4 }# U. s+ \" o" i" @" Y; X PINMUX1_MCASP0_AXR12_ENABLE | \
3 a, r( z) A% {$ g: |: F' s6 z PINMUX1_MCASP0_AXR13_ENABLE | \2 s4 {$ ~4 E! b B2 q* ]- p
PINMUX1_MCASP0_AXR14_ENABLE | \! s3 [+ b5 Q0 j! e7 R2 B1 D3 P( _6 n
PINMUX1_MCASP0_AXR8_ENABLE | \1 U9 Z, H9 r& n" J8 t
PINMUX1_MCASP0_AXR9_ENABLE | \
* ]4 D$ h c' e! d: m PINMUX1_MCASP0_AXR10_ENABLE | \3 h+ R% t' B2 i f8 q$ g; `
savePinMux);$ A$ S( U. I1 U8 `6 Y' A8 b+ P1 g9 l% T
}
' D- s: T- j& ?' w% [& r
- A# g9 a6 M% C# w1 b* s& j* h1.McASPI2SConfigure(); McASP的配置程序如下:$ B7 N" t( T$ F% K. L7 Y9 {
static void McASPI2SConfigure(void)9 ]6 Z8 N# {. H* p% R
{
B0 ^. m0 ^2 ^% i$ b McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 U5 k. P8 s& t3 ^6 f/ I3 O9 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS);$ B2 @3 Y! m7 a: A2 x Q* s
* [, @9 \ q! B. o) J8 N9 }
/* Enable the FIFOs for DMA transfer *// R+ d6 S% k' _. f
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);% g1 e$ F, V. O! G j1 d; n+ D! B
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 X7 \! B7 H7 n2 S% z# ?' S3 a$ @2 c1 ]+ A' H, z2 F" e
/* Set I2S format in the transmitter/receiver format units */+ k7 m1 L3 ]" [ ]/ Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* g) s- d4 D8 P3 X5 t0 `7 G G
MCASP_RX_MODE_NON_DMA);
# u _0 C" {1 B" }+ g: @ McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 I7 T- O3 U- k+ M4 i
MCASP_TX_MODE_NON_DMA);8 j+ y" k8 R9 D$ _
; p. w. Q- |5 _+ h3 \/ {0 p
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */ k9 y* n Z9 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 u) C5 o; K9 } MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; u6 q0 I6 R. s* [ McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ W, V: j5 ^4 Y# \
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
7 t" U. s( k% l. [7 G
7 |/ W" o7 p* ] q# a6 @ /* configure the clock for receiver */
9 S, l( n. [7 d, _" ~% I// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
0 Y% o% \' q' J% G/ _: R! } McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; \+ i( ^, r% \7 X6 p: W* o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# c/ v5 { B4 E/ R6 C9 y$ S& W McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! [- M6 m: C0 Z+ n) h 0x00, 0xFF);9 C% K- L+ g3 l+ [; R2 ~
- a' `; L/ a' B. V /* configure the clock for transmitter */
9 d1 z/ x& p0 _// HWREG(0x01D000A0) = (0x00001F00);% n9 r( j+ j0 V- ^. R* u
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
- F- ]3 k- G/ p4 H; y$ | McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);8 G$ U0 ^% @- D/ \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- g J3 r: r/ P4 f* |2 Q McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: n5 C4 f* O# t! ^
0x00, 0xFF);+ T/ t5 K" S$ \2 ?' C
; y1 F- X: a' f( R& U
/* Enable synchronization of RX and TX sections */
3 ]0 a7 `2 \4 W McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);) A. `: d% C( T+ U$ `9 u
8 u |/ ^3 f' P- W! d2 Z: ^ /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 D% h+ {! Z5 {6 P7 ]0 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 I* {9 y+ ~1 I McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" V# @9 S) X0 e5 f9 V& N
) d0 E& K7 V9 K, `3 m5 h /*
8 e+ A1 s6 o# Q/ i8 ?7 a ** Set the serializers, Currently only one serializer is set as
K" k: O( j# u* c8 M; C1 v" P% R ** transmitter and one serializer as receiver.* k ^( v$ N1 | D9 k* | _( Y
*/
' }4 E) F! t3 ^! ^& B McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ Q# v7 g" m' [7 M6 a McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
' F! x T3 e s! f: E& k0 l McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);9 |( U! n& H8 G, W, r1 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);" W! u. o3 E$ c9 s$ z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
6 N3 j! v* d) i q3 W. Y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
* G+ _; M4 R e
i" p3 R% k. G% \" |3 ~4 l6 i9 \ McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
6 |9 Y& {0 s, p9 m( ]# K3 w& G- U; B2 Z2 H
/*) S- R$ M9 o3 D
** Configure the McASP pins ; R3 ?: T8 z( y
** Input - Frame Sync, Clock and Serializer Rx% J I/ D1 n3 [+ @9 i% l* K4 U
** Output - Serializer Tx is connected to the input of the codec
% `0 m7 r- j1 j/ c8 O) z* F- M */! N! ]( P9 H7 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 F+ X ]3 D" V5 t3 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
8 H# C6 G/ D ?1 X# g+ f" F MCASP_PIN_AXR(MCASP_XSER_TX)' P$ E" w% B7 n3 z
| MCASP_PIN_AMUTE
: Z1 i2 w z# v* P4 \ );
. V6 {4 N c$ ]. P) z McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,6 X' [" S0 G* ]6 a# k
MCASP_PIN_AFSX5 ]" j1 S g+ s1 o6 t0 I
| MCASP_PIN_AFSR
' H3 U3 l- }, Z2 ~+ Y- E | MCASP_PIN_AHCLKX% X6 {% E0 C( ^' R5 \
| MCASP_PIN_AHCLKR4 m. L' W) g5 h9 z) M% V
| MCASP_PIN_ACLKX
9 `* W6 K. |6 s( | | MCASP_PIN_ACLKR5 H* ^+ F- U' e) P6 s4 e. f
| MCASP_PIN_AXR(MCASP_XSER_RX)6 e# O2 V4 t$ q7 e% n
| MCASP_PIN_AXR(1u<<(13u))9 S, A# c3 ~. A, b9 ~" h4 S/ A
| MCASP_PIN_AXR(1u<<(14u))
# V+ q5 k) X4 m' D( e | MCASP_PIN_AXR(1u<<(8u))
) E `4 c/ |6 Y }6 w8 k7 k | MCASP_PIN_AXR(1u<<(10u))
$ T0 N, L' a5 }6 J | MCASP_PIN_AXR(1u<<(11u))
8 A/ V2 \2 R' ^& O* Z" E( \# u );# K6 X" ~. D/ }7 ?
; d$ T. M; Q6 m- m: p: O r4 k
/* Enable error interrupts for McASP */
5 r. G$ s$ U' U3 C" d1 r McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,! W9 \3 W( t- G" }
MCASP_TX_DATAREADY; t8 \4 U; L& ^3 h* D c E
| MCASP_TX_CLKFAIL 4 l9 ?( s; S* a6 I- h+ Z
| MCASP_TX_SYNCERROR
4 `3 O, F' D: r0 L1 m+ v | MCASP_TX_UNDERRUN);5 X( Q W# I% O3 S. v* @- m
+ f- J$ K! C2 U/ R3 X" p/ w
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,% N5 Q: B' w& f2 |
MCASP_RX_DATAREADY
8 Z; r0 u. R. K2 u | MCASP_RX_CLKFAIL
( P' g) B% X: b. O; c- O$ ^# D9 u | MCASP_RX_SYNCERROR
; t/ `5 G) `4 E) R | MCASP_RX_OVERRUN);
+ n- S W/ {/ }& K3 ]//MCASP_RX_DMAERROR MCASP_TX_DMAERROR% W9 e7 s R+ _
( F# B# G1 X" u. M$ W' R
}& b0 \; D9 Q4 L" x2 s8 F( w
4 V3 {# z5 l0 C+ Q" `, B6 G2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
+ m: v, Q% H& |* X( J* g# u: g' a8 K) xstatic void I2SDataTxRxActivate(void)
- J. Y" y7 k' L9 v3 I8 I{7 P5 K, a5 b' W; j
/* Start the clocks */
! t, i, ?- v% A McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 B e% Z, v! K/ G- ] McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);1 K, o" x, R; n; m! O
, j- t! ]# |2 E8 m5 A0 a2 F0 [6 i# m /* Enable EDMA for the transfer */3 k1 G3 B- A: k
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 |: W" _! z% A' q. V0 S% A
// EDMA3_TRIG_MODE_EVENT);
" G- `. |( I- J Q# n// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) h; D% F! C5 g9 ]: W// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); G9 G* J% [* D1 G5 R9 k# R t
/* Activate the serializers */8 t' O% P; Z; {9 z7 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( z7 u7 w" B' _1 n1 M/ [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 ?) D7 [1 W' L2 f /* make sure that the XDATA bit is cleared to zero */; L5 x! x$ N( X& W6 ]. ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);6 ]4 z9 S( Y% C# m( |/ T
/* Activate the state machines */
. T& ?$ {7 ]- v McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 N s6 V @ `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" H0 v. ?0 Q, M/ m
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);4 f$ Q p6 e2 o9 u) W n. K% A* F
}
1 t8 _# p9 x" i) ^2 s$ r1 p4 ]- b
|
|