|
|
我的McASP配置分别如下:+ j, X% r3 }6 z4 m' f9 r8 v9 p7 i8 z3 G
管脚的复用设置是:
0 n! z+ e4 S. y8 G0 f5 o* P! b5 ovoid McASPPinMuxSetup(void)/ J. W7 K( _6 k1 p' R2 n
{
: J6 f& N: j/ G1 b% ?4 T0 X1 s4 C unsigned int savePinMux = 0;5 ?% W' I3 ?$ _
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \4 a$ O: e! M4 h
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
8 M" O2 Z% W+ u+ r; I SYSCFG_PINMUX0_PINMUX0_23_20 | \ }3 o. P* g3 i7 s" k+ K
SYSCFG_PINMUX0_PINMUX0_19_16 | \
5 H! e& ~0 r) Y0 d' c* ~% A8 C SYSCFG_PINMUX0_PINMUX0_15_12 | \
- H( `+ m1 |) B8 R7 I# J SYSCFG_PINMUX0_PINMUX0_11_8 | \
# q/ C1 B6 n$ V; a6 m4 q$ R3 Z SYSCFG_PINMUX0_PINMUX0_7_4 | \$ p4 K' S, Z* ~5 i! L
SYSCFG_PINMUX0_PINMUX0_3_0);; r" s. t' _. G+ _
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
6 k% a5 [$ B( k: X' Z6 D+ j6 D% w (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
0 d8 L8 h! S5 p. h: e" p1 h9 C- T PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \7 |4 y: @% \' m! B
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \1 m' `' V/ C: Z; ]
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);" d: w" t' p3 @, \ B3 ?4 D
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
8 R; z$ r1 P# I* D1 p, H ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
( S# c/ c9 N* u# d1 E8 r SYSCFG_PINMUX1_PINMUX1_15_12 | \
: Q0 ?1 b- e, c! h SYSCFG_PINMUX1_PINMUX1_11_8 | \+ ^1 G' M' G; b" o) C2 M
SYSCFG_PINMUX1_PINMUX1_7_4 | \
6 j4 i$ A: q' m SYSCFG_PINMUX1_PINMUX1_23_20 | \
# h0 a: E, Y% i3 r3 M/ `2 r' e SYSCFG_PINMUX1_PINMUX1_27_24 | \, v" V9 W3 R0 D& X
SYSCFG_PINMUX1_PINMUX1_31_28; x8 `0 w4 V, ^' D
);
% p5 {, O( C, v y) ?) e HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
; T- T9 @ L' {% N# c2 D& f- | (PINMUX1_MCASP0_AXR11_ENABLE | \
x: v0 ^7 h7 h1 r$ U* v# t PINMUX1_MCASP0_AXR12_ENABLE | \5 f2 Z) O1 ]7 i! S
PINMUX1_MCASP0_AXR13_ENABLE | \
- N4 X) D' y7 n8 Z: f# x9 b PINMUX1_MCASP0_AXR14_ENABLE | \
4 b7 ]1 P7 c/ s! J PINMUX1_MCASP0_AXR8_ENABLE | \2 \9 a C8 Q, _
PINMUX1_MCASP0_AXR9_ENABLE | \
! B c' G7 ^' ]+ ^& I PINMUX1_MCASP0_AXR10_ENABLE | \
7 `4 |" @ |+ Z8 Z1 p0 P+ a savePinMux);
/ b# j6 Q4 n" l) }3 ?# l3 h, h}
# }, X1 A" g% \7 ?/ u2 b* L9 P4 O9 s
1.McASPI2SConfigure(); McASP的配置程序如下:
, X0 c7 Q( u& ~+ L; V4 _static void McASPI2SConfigure(void)
' J4 s8 Y( J4 e+ @{
$ B- {6 p7 h8 |( m( M- K- D McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& }, j' {* p6 g3 o McASPTxReset(SOC_MCASP_0_CTRL_REGS);) @: z- r# U+ n0 u0 m7 \
0 Z. w* }* |- p" Z/ @( q/ \9 l8 M0 N /* Enable the FIFOs for DMA transfer */
6 I3 p- D, }5 x: Y# H; \, \% K// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
1 k. H) A% {" N+ d5 G// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- N: i% r4 [2 o& c
. e' t9 E$ {) v% Q: f! b /* Set I2S format in the transmitter/receiver format units */
: G. ]8 V/ z9 \: J% T7 O# X+ O McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 A8 F; q3 J6 E
MCASP_RX_MODE_NON_DMA);
1 Y; b8 E4 m7 l3 r McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 D' j% W$ e* Q4 l# c, X, g. q, S( W
MCASP_TX_MODE_NON_DMA);2 G8 L# x b0 P3 }! C
/ } D) d7 d" }3 ^$ `+ m8 ]( X* g4 G4 N /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& s4 [) g1 I1 S7 {& b2 m McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! Z1 M1 `2 l% h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 e' J' i, K% P. E; p8 O; K* | o McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 p9 z6 y2 @" v MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
1 ?* E3 P! ~1 ?( H, x+ v3 f* A* h5 r8 F, d" _
/* configure the clock for receiver */
2 n0 G+ y3 |+ B3 n [# Q) e3 e9 M0 W% e: ^// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);/ {5 |- a" [, g6 P* F9 z, l; i# C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ k0 o5 o3 `) p: V& X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);( I) X, T+ M* Y6 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 V- C' @4 b- {% z* b 0x00, 0xFF);: m7 a4 X3 n% X8 R/ T, v$ ^, y/ A8 `
3 C. E3 F$ s' [& n* q /* configure the clock for transmitter */
0 s8 J, Q: |6 b d; U; R// HWREG(0x01D000A0) = (0x00001F00);
5 ?! b- l2 t3 p% _) B( c// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);4 @8 I5 {1 \2 d! }3 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);0 X" I0 A* w' k+ W M9 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);0 z6 N5 e2 D w ~# W7 U: A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, P+ N5 f7 J2 K; S
0x00, 0xFF);- ?9 C' N7 q+ x8 b/ B* x4 w* Y# w! ^
7 I |2 U- n, i! |" r
/* Enable synchronization of RX and TX sections */ ; S5 ]* r& Q/ a% P+ x- \' x, x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);& q7 [# S* @6 f) T1 E" n1 l7 W
, j7 r* X6 F. P) ?" C0 W
/* Enable the transmitter/receiver slots. I2S uses 2 slots */& w' z* B6 o. f1 l d7 Z3 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 h$ k- r. i3 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 U# v4 _- B# b" o) O/ C4 j
6 y0 F3 C& [2 \# Y) p& A! ~! U /*3 t0 T- a' [. ]1 i c
** Set the serializers, Currently only one serializer is set as
- T' O+ g9 a4 w' X ** transmitter and one serializer as receiver.! [9 q' X! V d9 ?
*/
{" q) [) J& m8 H$ z0 L McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 C$ R a2 I1 h, O3 _* V1 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);; M' H6 h& [+ ] z% Y# E% o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
" p* T% k6 P4 {0 N/ P McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
. P& \9 [7 a4 J$ b. W9 a/ w2 E McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);- A" [5 Y" d2 t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);# d. ^1 F$ v7 M: y, N
* r: @0 o& c: S/ U \ McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);! C/ o# P& \1 y- b) D* F
* b: |& {% j/ v% V4 f1 Q
/*
1 ~; c) V3 X/ W. a ** Configure the McASP pins 2 w8 M' D7 w2 o6 X) B
** Input - Frame Sync, Clock and Serializer Rx
$ P8 G" E* C% f4 v9 v" r* u$ H ** Output - Serializer Tx is connected to the input of the codec
* H7 l# t' E: F9 @6 M */3 x+ \4 `- f2 ^4 d9 e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; [$ H. a1 S, o) ?! ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
+ R( T8 l+ `8 ~& c" X( u MCASP_PIN_AXR(MCASP_XSER_TX)" [: j, Z3 j* l9 l+ ~" Q
| MCASP_PIN_AMUTE
& p6 y: S" o( ?- p9 t1 I* g ); ~' [9 X! ?6 x( o9 i3 G: p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,, {7 f- J: e8 E% B" }, t6 @7 m
MCASP_PIN_AFSX
1 {* F+ F- D, M | MCASP_PIN_AFSR
( `2 p- P5 G3 d8 k0 Y | MCASP_PIN_AHCLKX
* J5 e0 T, u. j! c- Q" z' G | MCASP_PIN_AHCLKR+ F3 {; T% l5 V' A) k9 W( W) M
| MCASP_PIN_ACLKX
7 _) a+ t# h8 p2 O, ~ | MCASP_PIN_ACLKR j" x2 U7 d: M. b1 t5 h9 r; [
| MCASP_PIN_AXR(MCASP_XSER_RX)
* I4 N0 L: R' h1 F. z6 x6 \1 I! D | MCASP_PIN_AXR(1u<<(13u))
4 T3 j1 d$ U, X r | MCASP_PIN_AXR(1u<<(14u))
( T) B. U( G2 s' ]# e9 v4 o; ? | MCASP_PIN_AXR(1u<<(8u))
. U& H- F# N, E; ^: f | MCASP_PIN_AXR(1u<<(10u)): d8 C0 A% Y, ]5 z6 g v) y
| MCASP_PIN_AXR(1u<<(11u))
6 _1 _9 c& W5 o- t% Y );" S9 T! C: i) r6 g
5 s! m8 A, Y6 h# b* U+ p /* Enable error interrupts for McASP */
7 I) m# b+ W8 x4 S3 _) c1 n McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
9 ^6 N U: Y' [) J4 V0 q; q2 z& ~ MCASP_TX_DATAREADY
' e& c3 E, o+ m: W: J( H: W | MCASP_TX_CLKFAIL s' j1 R! ~( n0 E5 C7 Y; y* h
| MCASP_TX_SYNCERROR
8 D) }$ ~0 @. k( Z' ]; ^& ^ | MCASP_TX_UNDERRUN);3 h% {, K7 d' _; _& D b# A$ j
3 g3 e# Q- }% u2 Y5 Q
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,& ]0 D) M7 J6 g! v: d/ j
MCASP_RX_DATAREADY; s: s& _2 Q; S
| MCASP_RX_CLKFAIL
: v+ z! d; A- f | MCASP_RX_SYNCERROR
9 G" Y0 ]- C5 `+ b/ _ | MCASP_RX_OVERRUN);
5 l$ m& B; u" m5 s+ {& u//MCASP_RX_DMAERROR MCASP_TX_DMAERROR: |. G- {& L7 k
6 S9 r& m5 I5 D f8 M& }
}
8 ]/ G& W5 @+ D6 G c! T% D
+ b. o4 r' S& |3 h3 g2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句9 S% P# F) B, G7 M" \
static void I2SDataTxRxActivate(void)4 l9 m. z- d# C. e! S8 \
{5 x+ t; d* u* q$ V$ @' \3 n
/* Start the clocks */
- h) C% ~3 `" A6 E4 x McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 d7 G7 [4 u4 t# T% F+ t McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
0 C$ I8 \8 e3 }2 O; S" }- c1 h: Y3 f5 o2 r/ X% W7 u' R9 n; l
/* Enable EDMA for the transfer */
! `4 L# H8 k- L// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# o) q; e8 Z+ n9 q5 ?% \1 |// EDMA3_TRIG_MODE_EVENT);
6 H! B' H2 M8 b! E4 c// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,7 f* ^0 B! c( U: r4 v/ h' W( l
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);6 o( Y3 n% ?) s- B
/* Activate the serializers */( @ O+ g4 @/ M' Y) p- S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 A1 m0 P5 x' l! a$ o) T5 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 H6 n+ Q" F; p$ R3 w5 ^9 Y# i /* make sure that the XDATA bit is cleared to zero */' h! E; N( O0 q Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
# ]6 u2 P* i/ J) i /* Activate the state machines */
8 J/ W: _2 C! ^ McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 J- O+ i$ l+ R+ W McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 u3 O; |- d0 E* C, M1 d
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);" \! |4 k+ R) B. W6 f, p- u
}! U+ E7 x% S6 a8 ]9 C9 O
5 b9 w, O: K$ y) m& A9 k |
|