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我的McASP配置分别如下:$ k4 M3 [& Q7 Y1 u# x
管脚的复用设置是:
# E! C# P1 c4 U8 ~void McASPPinMuxSetup(void)& E) o' E, N1 k, o/ U
{( P% b4 I5 c! E& _- S0 w% m
unsigned int savePinMux = 0;
0 R3 M ?" V# Q7 C7 C9 S$ s savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
) C2 o2 j7 s; m7 M$ x! |6 J4 R ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
) O: V. J& v7 y x SYSCFG_PINMUX0_PINMUX0_23_20 | \
; O% ^0 {% ~+ F1 ]8 I SYSCFG_PINMUX0_PINMUX0_19_16 | \8 _% r0 J6 O% M+ C1 a" U! n/ n2 R
SYSCFG_PINMUX0_PINMUX0_15_12 | \# j! {3 X n7 T' [+ L* e/ ]
SYSCFG_PINMUX0_PINMUX0_11_8 | \
. \7 J* q& j/ c5 o& {, t g SYSCFG_PINMUX0_PINMUX0_7_4 | \- I/ R4 ^% D- I) Q
SYSCFG_PINMUX0_PINMUX0_3_0);
* }- h/ i; P& l' u6 S* x% g2 n# | HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \$ b7 m# w B% ~0 a6 I
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
6 |' \ ~) L, a d PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
' H& ] c/ e( x: Q4 B% f6 ~" R6 ~2 i PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
5 j* |, k7 L' [* j1 l- k3 @9 ]+ L PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
8 ~/ a% L( @8 t, I. g savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
0 k2 a% _* g+ v ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \/ o8 T: E) u% s* \ m. I
SYSCFG_PINMUX1_PINMUX1_15_12 | \
& ]- m* c9 o7 a) [* y SYSCFG_PINMUX1_PINMUX1_11_8 | \' A; k/ g; q! z) q
SYSCFG_PINMUX1_PINMUX1_7_4 | \& X' K- G+ ^+ v7 C: j3 G
SYSCFG_PINMUX1_PINMUX1_23_20 | \8 X' D- \4 k8 D4 S! v; s! u5 x
SYSCFG_PINMUX1_PINMUX1_27_24 | \
1 v5 ~3 ~+ s# y2 [1 Q SYSCFG_PINMUX1_PINMUX1_31_289 q7 \, u q, L+ I, ]
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HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
. e7 K+ V. w& I) z- [: v (PINMUX1_MCASP0_AXR11_ENABLE | \8 }; B0 T9 {# v
PINMUX1_MCASP0_AXR12_ENABLE | \
5 |! u4 Q: D0 G+ N% G2 v PINMUX1_MCASP0_AXR13_ENABLE | \
! Z/ @' G3 b, n% z" X+ M PINMUX1_MCASP0_AXR14_ENABLE | \
4 }( @* u) o: C5 @( x8 x/ v) l PINMUX1_MCASP0_AXR8_ENABLE | \' a E, B- x% \, e; Q
PINMUX1_MCASP0_AXR9_ENABLE | \
" Y4 E! a1 N2 |' v3 `2 } PINMUX1_MCASP0_AXR10_ENABLE | \1 P. t: X- J8 W
savePinMux);
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1.McASPI2SConfigure(); McASP的配置程序如下:* z. O4 b0 J: N/ B' g
static void McASPI2SConfigure(void)
+ j' ^, r: k7 @/ ^* M j{
+ M8 D. Q3 I' x9 } McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: y6 Q6 q8 w2 x! o R7 c McASPTxReset(SOC_MCASP_0_CTRL_REGS);* t8 ^$ ]0 F4 B1 ~! i) Z5 C1 Z
, m5 l: b) k3 G2 J9 P9 M( _ /* Enable the FIFOs for DMA transfer */! o( z3 ~% K% ^. \
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1); M5 n$ a; t) D
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* R( |& ^5 ?# K- |$ A k! ~% s2 s
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/* Set I2S format in the transmitter/receiver format units */
$ w& \0 }9 ?& x McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 R) Q: O* f( a& _1 N8 z5 a0 } MCASP_RX_MODE_NON_DMA);
7 F1 A# F6 U" Y McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. }; j/ `. `/ [1 H6 ~* r6 o
MCASP_TX_MODE_NON_DMA);! V# R E$ K$ J: q/ Y, h- f) g; o
' @- m5 E. Q" ^ /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 r, L0 l0 z; U' O' P9 m9 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 `4 F% z- `. C: @ i4 T# \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ S& G% Z- _! D McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# P0 s4 p% r, b MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);9 R& e+ W4 g* \" i/ F: U
6 ^1 I- b1 o6 ^: _, d /* configure the clock for receiver */
/ E' Q o/ o+ L. L2 o- [. t; |9 z0 k// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);0 J) ?. T' G% d9 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 c. {' L1 Y) i! z8 t McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" Y8 P* P$ p1 k% H# g- P1 D9 R McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% M2 [8 C& N$ ~8 \# V9 J. b 0x00, 0xFF);! g/ X, |2 Q" X: x6 j- v' y9 W
! d, o& W( o' ^ k+ ?8 T8 }' M /* configure the clock for transmitter */
# M& ^7 N6 H b' n7 p// HWREG(0x01D000A0) = (0x00001F00);. A9 h5 t3 c$ a. d
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);8 C! f3 S5 g/ p! O3 a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
- C" P6 m* | r L McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);. o3 C" @/ q5 ]* T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 M0 }1 Y( I! o8 b
0x00, 0xFF);5 R! L2 Q+ a7 J4 ?: W. w
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/* Enable synchronization of RX and TX sections */
7 H3 L$ W( s# C9 @2 N7 K McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
7 I/ B% q& e& G
; b+ e0 Z9 w+ W" ?' m# N0 O /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 [; r9 Q$ B6 I+ ]! a$ |, [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ?1 _& H O& K& H5 _" \9 u7 K McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, V9 {$ q6 P7 h5 E# E! A8 g( D- I5 Y& N8 U# t) F
/*
+ Z3 h4 H2 i' A5 {% j9 e' Q! o) j ** Set the serializers, Currently only one serializer is set as$ c1 ^0 _6 U- O' V& K
** transmitter and one serializer as receiver.5 {. Q4 v$ m% v* _* W2 o+ {& `
*/7 T8 N: {' T8 E9 S8 g9 g X" G. u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% R8 |+ i0 {7 r& x" K* a8 e McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
9 R6 D/ {1 `9 u- I$ D McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
f' H) {9 g4 Z d/ L McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
: O( B. \, |4 A" ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);3 v8 Z( F) q: b1 L, w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
/ V9 S5 B# E1 V9 ^' k7 c4 {& A, x7 @ _
$ F- k1 B3 \ {" z+ C/ N McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);5 A3 j) M* Z/ m! `# o7 z
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/*8 M" C$ C8 u% b. h# t
** Configure the McASP pins - N( s$ k6 X Y) P/ h- G* o
** Input - Frame Sync, Clock and Serializer Rx4 ?' B2 g* J+ t& F
** Output - Serializer Tx is connected to the input of the codec % i) o# R! R0 Z- Z! U) B% d8 h+ Y
*/
3 X# @2 ` s# j; C McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! z: @+ @7 a# g* A: O0 K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
4 I; |' A/ a5 U, o. S1 F& K. K MCASP_PIN_AXR(MCASP_XSER_TX)
$ w' @3 J& U. H8 N7 S | MCASP_PIN_AMUTE! H+ m0 g' a. |4 D( I. L1 y1 v+ u
);
- E' _3 t1 [' i7 j McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,8 Y3 P$ Y# f x
MCASP_PIN_AFSX
+ N3 Z$ C! o/ m4 r$ ` | MCASP_PIN_AFSR& L7 \2 g% W2 j
| MCASP_PIN_AHCLKX5 {/ J b( f; T) ], e; L
| MCASP_PIN_AHCLKR
6 r: n Z: G7 S2 [. V0 s | MCASP_PIN_ACLKX
7 ^5 ~) K& \( b& m' e$ L | MCASP_PIN_ACLKR
\* u% y2 ~) \ | MCASP_PIN_AXR(MCASP_XSER_RX)
, q9 b" v, m: a% J! |% n& [& ]# h | MCASP_PIN_AXR(1u<<(13u))
. m! L6 l' ~2 e3 a! {- C | MCASP_PIN_AXR(1u<<(14u))
" ?8 k+ {6 g4 k3 ]2 U | MCASP_PIN_AXR(1u<<(8u))
7 D! V& ?+ O" X7 J; m# k a | MCASP_PIN_AXR(1u<<(10u)), Z4 C/ E$ ?! r. U
| MCASP_PIN_AXR(1u<<(11u))2 x6 a# B) Y* J8 j9 L: F3 A1 c1 ~
);
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8 C- w& R8 U% m6 y2 I /* Enable error interrupts for McASP */
& f' H9 r/ {. T9 L! Q McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,+ P5 A1 T, M0 {$ q8 o
MCASP_TX_DATAREADY) `, u( c6 x0 E7 z; b2 d* b
| MCASP_TX_CLKFAIL F- M: u- X `) o, ]% p9 ?
| MCASP_TX_SYNCERROR
1 k' W9 [ V' A) O6 ~ | MCASP_TX_UNDERRUN);
% `$ Q' x3 k! @9 g; F
' n. [! m# [, t+ w McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ S. ~7 m' r. `7 z& q MCASP_RX_DATAREADY. D0 O% ^! o: U( Y
| MCASP_RX_CLKFAIL' P4 l% W4 A9 L2 J, p" {! ?1 G/ K
| MCASP_RX_SYNCERROR
9 {6 n% o8 @, a: n0 d1 z$ y | MCASP_RX_OVERRUN);
9 ^# ~: J4 ]9 E! K, F* u% j//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
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2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
1 E7 X1 n9 z' T3 O0 K5 P7 Mstatic void I2SDataTxRxActivate(void)
1 R0 R- X% B# g, U# V* T{
* W, `9 P; d6 d# M% D; U /* Start the clocks */2 I1 K# r$ W" }3 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 {' I. T% o; G, S, } r% I# s McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
4 O- k1 N# Y5 G7 H2 H* A$ `3 }4 V8 n4 U$ G* M" h1 n
/* Enable EDMA for the transfer */
8 ` Y& L/ q8 S3 K// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 ^0 R8 h* P# p1 ^8 u7 K
// EDMA3_TRIG_MODE_EVENT);
8 | }9 m3 Q' ]2 l8 S5 m$ e* ?// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,& s+ J( S) J- ]" q, h
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
7 F; c$ g, @3 v: p' [; v5 ~ /* Activate the serializers */
1 E3 O) [# P6 R ] B McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- T. C6 Q3 i7 {2 I* c% k/ G McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);% y% J7 p/ U- h0 j5 l4 D. C
/* make sure that the XDATA bit is cleared to zero */
3 m/ W$ \+ g/ ?, P while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);: c- C& \+ a5 n6 ~4 l
/* Activate the state machines */
; W, m6 V* @0 @/ s% f6 | McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. s" X2 u9 I$ q" n$ _: f) h$ X" m! } McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 T4 w: L! j6 ?1 B# e! d; L McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);/ N8 N) u j" B7 H* d1 _
}
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