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我的McASP配置分别如下:
; \. u" ^) p0 | p. ?管脚的复用设置是:
2 W" @6 W% c6 l5 a% q$ wvoid McASPPinMuxSetup(void)
9 g* v/ w4 h( ~, M) p{) X* E7 U' q6 d* r1 ]6 b
unsigned int savePinMux = 0;. u8 p0 r0 h. ~9 C5 D5 j, _% T, t
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \7 k- p$ ~6 `- `: ~% z* ~
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
6 ~, t5 V5 ~" n: ]3 I u4 z SYSCFG_PINMUX0_PINMUX0_23_20 | \3 T2 J; k) y/ W* v* ], J$ `5 E
SYSCFG_PINMUX0_PINMUX0_19_16 | \. S# `8 d0 }" t I
SYSCFG_PINMUX0_PINMUX0_15_12 | \
* I: E5 i2 T. X% a" ~ SYSCFG_PINMUX0_PINMUX0_11_8 | \* f {4 L1 @) W
SYSCFG_PINMUX0_PINMUX0_7_4 | \
' e2 p& K7 V6 x( R7 ` SYSCFG_PINMUX0_PINMUX0_3_0);0 T+ o/ W, ?& m+ g
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
5 b9 O. H. Z0 |' N (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
7 K8 M4 X2 j$ G. z- o/ S, h PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \, Y* L4 ~6 g' f8 }, T% X/ w
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
5 M; |) ?% G* s* C, I PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);6 Q, @# l- n8 u8 H: |2 W8 L
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
0 V, P+ T$ }! L4 n ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
2 o$ P: \; W5 ]+ G& l SYSCFG_PINMUX1_PINMUX1_15_12 | \' X) o- M5 f) F" ]
SYSCFG_PINMUX1_PINMUX1_11_8 | \
: r$ j2 P! C7 m5 |9 e- R SYSCFG_PINMUX1_PINMUX1_7_4 | \
q) [* [% b% H6 q7 `/ u SYSCFG_PINMUX1_PINMUX1_23_20 | \: f4 j7 ] s l1 _: p9 T5 R+ r1 h
SYSCFG_PINMUX1_PINMUX1_27_24 | \
2 W( `( n' S1 P, H7 t5 l2 K SYSCFG_PINMUX1_PINMUX1_31_28: Q+ ^8 v; u4 I' e
);) T" t$ R* x& ^2 z
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \1 Q2 T# |! h/ ~! l9 K
(PINMUX1_MCASP0_AXR11_ENABLE | \
n5 S$ ?! |0 o3 y+ c PINMUX1_MCASP0_AXR12_ENABLE | \
Z' x3 U3 ] ^ x5 x& k PINMUX1_MCASP0_AXR13_ENABLE | \5 H% i+ w! j& C: d2 B
PINMUX1_MCASP0_AXR14_ENABLE | \
( U+ K- {! K& i* h( J- c( @ PINMUX1_MCASP0_AXR8_ENABLE | \
' u6 x/ x; ~$ N; i# l' W PINMUX1_MCASP0_AXR9_ENABLE | \& \" h4 P0 W. l( }' S) \
PINMUX1_MCASP0_AXR10_ENABLE | \. }( o1 h) K Z I' S; j
savePinMux);
7 g) [: c T$ m, W9 A& q}7 [! ~; x: B: \7 m0 c
* s* j% e$ L7 ~" D q1 t2 j
1.McASPI2SConfigure(); McASP的配置程序如下:, Y* H" C0 G5 W$ g% |3 t) D
static void McASPI2SConfigure(void)
; B9 j' l1 ^+ E. D{
% k1 I$ u0 f6 @! s% ? McASPRxReset(SOC_MCASP_0_CTRL_REGS);* t" ^0 x; n( [8 S9 |) y
McASPTxReset(SOC_MCASP_0_CTRL_REGS);" e5 {% N* k$ Z4 Z d% v, n
' J8 G7 ~/ }+ Y) k2 U+ v
/* Enable the FIFOs for DMA transfer */
5 y& H1 j5 r: C o2 I0 w. S, f$ e5 \7 `// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
- O0 O8 F+ q; @4 h3 ]// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' Z5 I7 d* g$ y, U5 [ ]
8 R5 T9 n1 l( R, R. @0 @
/* Set I2S format in the transmitter/receiver format units */
* c, n( [+ o3 t! F, J- g6 p, s McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) e9 l8 X, Q1 n
MCASP_RX_MODE_NON_DMA);/ Z7 y# l: W$ o* w2 X/ v ?* ~' c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ z* I/ B% z- g8 P7 d MCASP_TX_MODE_NON_DMA);$ X' }# f4 i, k1 E
% m! w! j+ A% s4 }! J
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* o8 v" b2 |, { A McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & s( p# o5 N; V4 i, d# B* d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
G. t: N! _. n" S McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 S5 }/ ?& ?( \6 J8 ?7 G! e MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
) Z8 p/ F; O% ^: k5 \8 c, ]7 F4 R3 z
/* configure the clock for receiver */
# x" ?7 k; m& I E// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);: P0 W$ J; P {' A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 w' \& z1 d5 G7 U' n& Y9 L: K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; n2 N" N9 Y8 Q6 K3 H McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 [% O3 ]% i3 a4 V; ~: j 0x00, 0xFF);
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/* configure the clock for transmitter */) |/ I3 e9 b% e+ N3 p/ j8 I
// HWREG(0x01D000A0) = (0x00001F00);4 @! g, I% L7 g# ?7 P
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);: ~. H) {2 F2 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
7 z: U& P$ A& d4 Z _( i0 z, @& A McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
i5 w4 G6 s( B, a- a; z McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% Y0 x( U0 F w: W, M
0x00, 0xFF);! g9 B( e8 u) z4 k
$ g. ]5 u# O* V+ H
/* Enable synchronization of RX and TX sections */
8 \( x0 D$ J6 t" B. V4 B McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
6 n. P- R9 L0 m; c# S" ]4 A5 \+ f4 a
8 ]% z( i# E L: m$ N$ x9 Z /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 }6 Q" u8 L. L) @" o, m5 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( u9 R. F. c- M( Z McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 ~3 ~# }, `7 a$ Q& R$ ~+ X' W" ]* T- a
: P2 A C7 H, N& B( K* o
/*
k5 t6 [. q: J6 i, H. }2 D ** Set the serializers, Currently only one serializer is set as1 b% ^1 s/ J! \) n' q8 x1 M6 }2 q- L
** transmitter and one serializer as receiver.
! A, D( e4 Q5 H) Z- t2 n/ E8 w */
( Z# j: C1 b) S. ]0 _5 n McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ F' _3 y0 m2 X8 d% k# m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
. c5 I( y+ e& W9 f9 }8 c7 f/ | McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);/ H* F b6 E% g# U7 Y0 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
$ H0 s; a/ U; ~9 e" ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
1 n( C2 P: m6 A McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
. r0 D) |( |4 G1 r, u6 X$ x4 ^. c: S0 @0 ?3 T& O$ ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);4 a6 ^; ~- S) W3 w2 l
3 B8 r s2 {; I; \# @' s& X /*
! C$ v: {4 E; ~3 b+ }& } ** Configure the McASP pins
+ d; X1 a; T" S- @% ]* S1 o ** Input - Frame Sync, Clock and Serializer Rx
; [9 r+ I* ~) R$ b ** Output - Serializer Tx is connected to the input of the codec & D1 W1 k' l9 t; y* N! i+ ]
*/
- b9 K5 }& }" d McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, O" o q j& }# T/ q; H+ S McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
9 H! U1 J8 z3 l7 p6 I: X7 b MCASP_PIN_AXR(MCASP_XSER_TX)
3 H% R P6 K$ q$ r. J | MCASP_PIN_AMUTE
- g# y8 z( S1 z- ^: W* h );* q, N# N0 a. x8 E' J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,' e) e0 a! e% L. f
MCASP_PIN_AFSX8 `, {- S! r% \$ O" C
| MCASP_PIN_AFSR
2 u5 f7 _8 X1 v$ g: e | MCASP_PIN_AHCLKX" O6 a# q# `& ?% w) H
| MCASP_PIN_AHCLKR- H/ g7 N. q' m- H
| MCASP_PIN_ACLKX
2 p5 P0 W6 ]4 U( ~* N | MCASP_PIN_ACLKR
8 o* k6 v* ?0 R e3 i4 F) u m9 ` | MCASP_PIN_AXR(MCASP_XSER_RX). E- o$ ^: A5 W+ _. {% M `- n
| MCASP_PIN_AXR(1u<<(13u))! ` E8 S0 \$ R- k' [9 d7 R
| MCASP_PIN_AXR(1u<<(14u)); \! V1 j3 c0 U7 A m) ]3 x8 n/ m
| MCASP_PIN_AXR(1u<<(8u))
. y1 O: ?! v1 P4 } | MCASP_PIN_AXR(1u<<(10u))
, W2 h- _, U4 I& ~: i. n1 q | MCASP_PIN_AXR(1u<<(11u)): X) N2 y% s/ _4 X3 k- |
);$ C- w7 O: a! S h' q+ m R; }0 R! W
# z3 J/ K# B, Z+ ^5 Z
/* Enable error interrupts for McASP */# f( x/ G# I2 y" ?5 k7 A) {# O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
9 z0 B; ~! G! r0 O& s. `( I! h MCASP_TX_DATAREADY
: D, s3 L* L$ n: k | MCASP_TX_CLKFAIL
9 u+ L% X. }$ S0 y6 F4 K+ U | MCASP_TX_SYNCERROR! T. W& V( t( A( G+ d
| MCASP_TX_UNDERRUN);
+ O6 \" m6 E0 x4 r) r) G9 Q4 ]5 s) {1 I [2 r
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,$ g8 v6 |# s. X8 M& {7 ?9 X1 S: x
MCASP_RX_DATAREADY
& O {% [( \1 W7 Z/ y | MCASP_RX_CLKFAIL
2 ]& `# p: S! Z5 o: J | MCASP_RX_SYNCERROR % A: m1 J/ u! s5 c6 A4 g
| MCASP_RX_OVERRUN);
7 x3 X+ _4 y& A- V; J' j/ @//MCASP_RX_DMAERROR MCASP_TX_DMAERROR' P0 Y1 r# e9 R) e6 d; z
; y" o+ n$ V; E7 D' C ?7 b
}9 I6 \! j1 S6 [ `. D, o3 H
0 [" X- i! V) T, X [4 S7 N% |2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句1 z6 ]7 u% k: H' ` W% z2 n" U
static void I2SDataTxRxActivate(void)$ h: ]$ _ s$ u$ c' S4 p+ |4 d# B
{
1 r- P5 w! z% n$ P" k* |$ W) k" Q /* Start the clocks */
0 R+ O- O0 z6 M3 n; M6 P0 N1 D, k McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ @* j* V7 ]. P4 w! E* B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
/ l+ [# i6 k6 v' C* U1 p$ J1 z
2 k) g9 z# A- e; Y% K2 ~8 l /* Enable EDMA for the transfer */. S' Y; G7 Z7 Z$ H7 g# s* Y! `0 n
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 ~6 n' M0 ^) b) f- n// EDMA3_TRIG_MODE_EVENT);
% d3 p6 `! X; Y3 o* x// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 ?; P6 q; o; L3 I8 ^// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);2 p2 o3 F; Y/ d& B& J' p2 k
/* Activate the serializers */
! `5 H$ w; I, {4 v McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ }% g- N* B# x+ O( z% V* M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);7 t' D6 a9 i) |2 _( ^" f
/* make sure that the XDATA bit is cleared to zero */
( k: C: d4 \& h) a- [ while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);9 t9 t4 O( z0 j% n' a7 t+ W/ |
/* Activate the state machines */+ F: Y9 ]1 E* J. V+ c. p; I, \" A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! ^% q" I3 G' ^% z7 `3 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& a& o, p! g2 a, R# c+ C( }( k
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
- D$ g/ A) l g) M* u* M}
( _0 Q! g5 a2 {" X9 v# `/ n: \* L
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