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我的McASP配置分别如下:
7 d# A! n; D$ S' z管脚的复用设置是:$ f. p$ |) f' S* E% S" t" D+ \
void McASPPinMuxSetup(void)
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unsigned int savePinMux = 0;. v8 t5 U) T; l# L: R R; k
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \! Z' y9 C. e: [: ?
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
' n4 C, P* t! e; S SYSCFG_PINMUX0_PINMUX0_23_20 | \
+ y7 ?) k0 W2 O0 P- M0 c SYSCFG_PINMUX0_PINMUX0_19_16 | \
F- L7 G1 @( i1 L SYSCFG_PINMUX0_PINMUX0_15_12 | \
$ n8 {3 E5 D4 E, Z. O" Y8 H SYSCFG_PINMUX0_PINMUX0_11_8 | \
3 l; I% [) B3 I4 J7 k SYSCFG_PINMUX0_PINMUX0_7_4 | \7 y2 M9 z' c) r1 ^ O
SYSCFG_PINMUX0_PINMUX0_3_0);
( ]( G4 U, ? w# a HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \% |( q2 G: A7 ~! H j# y+ G" L
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
8 L: i* w' a- [( V- f' T' [ a PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
w3 }: e+ T4 n3 f! k* { PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
. E- T' O9 u+ \' V1 L PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
# v6 J( j0 f6 U/ f- b. l. z) F savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \0 E& b3 K* D1 Q2 j' h- \' @
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
: x5 w% `9 P. q0 V6 _$ a( I; E" d$ k SYSCFG_PINMUX1_PINMUX1_15_12 | \3 k5 k) |! W! z: F" G* ~4 q
SYSCFG_PINMUX1_PINMUX1_11_8 | \
8 H! p- r# m, T# s SYSCFG_PINMUX1_PINMUX1_7_4 | \5 P+ k8 c0 c4 w& q/ C3 v$ Q
SYSCFG_PINMUX1_PINMUX1_23_20 | \
. z3 x8 \+ Q/ a% Z: Z SYSCFG_PINMUX1_PINMUX1_27_24 | \! o- O" |, N. r
SYSCFG_PINMUX1_PINMUX1_31_28. f8 K* x. A4 k9 F& J! w
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HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
' u" v w. S' x8 b4 S1 A (PINMUX1_MCASP0_AXR11_ENABLE | \$ \& V7 F3 v7 b( J+ ]
PINMUX1_MCASP0_AXR12_ENABLE | \
) J7 z. _3 V4 t" x7 V+ l5 ? PINMUX1_MCASP0_AXR13_ENABLE | \% S# O9 J( C9 z. S; h* b9 [7 z+ I6 I
PINMUX1_MCASP0_AXR14_ENABLE | \, {5 @8 D! u, F$ q9 w0 ^
PINMUX1_MCASP0_AXR8_ENABLE | \
% A0 v: A7 J) p; D+ ^$ m PINMUX1_MCASP0_AXR9_ENABLE | \& M2 x7 e% s$ q J
PINMUX1_MCASP0_AXR10_ENABLE | \
9 c G7 ?% U; ^. z& @ savePinMux);
% X$ A% x1 v) a}* f. P2 i* c& Z+ u& A
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1.McASPI2SConfigure(); McASP的配置程序如下:! C' R1 s/ t0 \! z$ \/ {) V( R- B
static void McASPI2SConfigure(void)! E% f8 [6 f- Y
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, N) e$ {' ^& e; `) g McASPTxReset(SOC_MCASP_0_CTRL_REGS);
$ D9 C6 l, M0 e: N( A H5 o! l) r+ d6 @ R2 Z- j6 n3 a
/* Enable the FIFOs for DMA transfer */
+ o% k" A, X, h o// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
! J8 e8 H" c- m" \* d/ B// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 Y+ j. E+ p, g0 i& m
3 ?4 c$ ^5 H% a9 U
/* Set I2S format in the transmitter/receiver format units */
5 s7 y% J" H( ?# D6 f! ? McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* M* o; u [* f# ?( Y0 z8 c i
MCASP_RX_MODE_NON_DMA);
- _3 k. L8 B2 \) h# Q, ] McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% }. h: J: r$ Z: Y y/ I MCASP_TX_MODE_NON_DMA);
3 u. L% q! H2 v2 D. e* v; \4 F) k; m9 k. C5 |7 B( A+ |
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 V0 f7 q% T# [1 P) p McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ Q; g ~: R( ~) n- C8 ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ R t/ H2 J- M9 U' J% k+ C5 J McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 a: _( ^& ~4 z8 B
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
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/* configure the clock for receiver */# X y% `7 p. |7 P2 @- T5 _* F
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
, j4 A$ ? ^% N6 F- V( X2 t McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
t7 |( e" J( P; C" }% ^ McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 H# w# B. W ^, J7 D McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 }1 i' A' y& o3 J; a
0x00, 0xFF);- k7 [3 Y5 f( _1 a
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/* configure the clock for transmitter */( T; {2 [9 a$ M( l R6 m% ^2 s
// HWREG(0x01D000A0) = (0x00001F00);
. n. l% F4 ~9 G) K// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);( W6 E4 T( _' }7 a& S, y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
3 b+ K( i- [" |( V0 k" { McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);7 @8 E4 l$ U, k0 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 ?9 b5 r0 B% D3 Y1 W8 E; c4 N 0x00, 0xFF);3 O- I& l: z9 v
+ r: A6 w, `' p5 g8 q
/* Enable synchronization of RX and TX sections */ 7 K! u$ V9 C* M: U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
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/* Enable the transmitter/receiver slots. I2S uses 2 slots */; m; D1 G q9 g' s. W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 a" h& g6 \2 e6 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( g- \6 v" N7 @" g* @* M9 q V
) Y! j8 ?" x1 c. J* y /*( }8 x1 k9 p7 s
** Set the serializers, Currently only one serializer is set as
2 m3 p) y8 {, T" x ** transmitter and one serializer as receiver.
2 k; h8 ^" x6 a# R, Z0 d */
+ E Q- |0 q2 Y4 R McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) ]7 I4 R1 \" U8 W$ q" H+ E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
/ f7 v- B7 ]4 j0 c McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
! B/ _: n4 C P( { McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
2 ^$ t0 ^/ X! y3 [$ \# d McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
( J' B4 q3 \! T- f4 T McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);4 I4 y3 t4 s/ c
! Q. J' N- B* u* _ ?( b" ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);' b7 M, r" j" [: s3 L- w P
, x% Z1 [" Q% F, w f0 F2 t
/*
/ W: \( h. r/ d ** Configure the McASP pins
- B3 ]7 I/ i+ c/ T- c9 I ** Input - Frame Sync, Clock and Serializer Rx
$ o; p, e+ i. _ ** Output - Serializer Tx is connected to the input of the codec
H' d0 X6 i3 P" T$ D */
+ B/ ^9 y3 H/ B7 [% a McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 A5 k3 a$ P; T5 T: k1 D7 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
+ h x/ w: c' ^8 P$ L5 j MCASP_PIN_AXR(MCASP_XSER_TX)7 x" R: Z, z2 U
| MCASP_PIN_AMUTE$ F2 G0 o. P+ M; R" u$ m
);2 [7 K2 p8 e. P5 c; W3 n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
! V+ ~8 @- h9 ^* `3 C/ `5 G MCASP_PIN_AFSX
. |" |$ c% B/ K9 y+ ~ | MCASP_PIN_AFSR. h3 F4 n) ~' Y0 C! h6 B
| MCASP_PIN_AHCLKX- K6 {2 P1 e6 w' {' r8 F
| MCASP_PIN_AHCLKR3 _- F+ j5 x5 k* d( e4 b
| MCASP_PIN_ACLKX
7 B# M8 Z7 y% B% N | MCASP_PIN_ACLKR
- n3 I/ v) ]1 B" g% o0 P4 D5 b+ k3 } | MCASP_PIN_AXR(MCASP_XSER_RX). \6 n* _# r# l w+ g
| MCASP_PIN_AXR(1u<<(13u))
3 s' A! b: q, b' c- R | MCASP_PIN_AXR(1u<<(14u))
. X8 P. U6 I/ {0 [0 \ | MCASP_PIN_AXR(1u<<(8u))
( F6 v" H1 v, p! W$ F K | MCASP_PIN_AXR(1u<<(10u))
8 H8 M) K- j9 D9 q | MCASP_PIN_AXR(1u<<(11u))+ Y1 H+ ?5 p) T* r8 S( ]3 r# E: m
);: j' t- m' D& z
: @; K+ `* l9 \3 y
/* Enable error interrupts for McASP */
1 E- {2 K7 {6 _ McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,1 n5 m) @! a. k+ |; ^7 S Q
MCASP_TX_DATAREADY8 A8 w0 q/ f; g, e4 d S- d
| MCASP_TX_CLKFAIL ! {5 z' ^+ c* H* V* ~3 r6 `
| MCASP_TX_SYNCERROR
& W5 z, y2 O3 N | MCASP_TX_UNDERRUN);
- ]: x- x# y! D# G. ~+ Q2 ^' u4 t0 k/ a
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS," x+ D& n" Z0 e9 r3 Z" o" ^( N
MCASP_RX_DATAREADY" G: N/ ^& t. W! k0 q
| MCASP_RX_CLKFAIL
) j7 h! C) W _! i# D( Z, Y | MCASP_RX_SYNCERROR
4 P7 v- i" D3 c6 J; L q, A | MCASP_RX_OVERRUN);2 x# _) Z' U' S# x
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR; d' {6 m# ]; j! A: n! c
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+ v) ^; V* u+ ~4 e: d) V
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
$ V3 e |$ E# Q( l: ^# v0 i Estatic void I2SDataTxRxActivate(void)
' k# u ^! n& z5 s{3 M$ S) N1 u0 D
/* Start the clocks */
, O9 g+ m- S: g6 h McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. N: ]" R( V. u% n9 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
1 a) l9 O U" |4 H8 W6 [; ^% D0 l* H: b+ Y ~6 n
/* Enable EDMA for the transfer */
; @/ ^7 P4 E$ R; R) C% e1 }// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ i- X+ v& O4 I+ N5 J* Z5 W0 X
// EDMA3_TRIG_MODE_EVENT);3 V. a+ b$ E$ ~# {" W' y8 K
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ f8 ]( g3 t+ d) C- [3 }: Y// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
' U Z9 o c" `2 r7 M /* Activate the serializers */
9 P' |4 G% K6 T; O: b Y McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 @0 I0 G9 \6 ? M& {% k1 k McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);+ y' \& J8 ~3 i' Z* D3 d4 y. R- [
/* make sure that the XDATA bit is cleared to zero */
, g( T+ n4 D' m while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
: Q+ ~* n8 m" V: H x3 a /* Activate the state machines */2 w/ L0 F9 z9 \/ `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% H9 q' ^7 L6 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" o8 Z/ E+ f; ]' F8 U# f
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
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