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我的McASP配置分别如下: K$ G6 ^' a* h% X' Q# V- H+ [
管脚的复用设置是:
$ [# q" G: v9 ?4 s/ M9 Qvoid McASPPinMuxSetup(void)3 f- j: Q/ o) l/ r
{
1 c/ o6 D5 _# v! E8 ~; X unsigned int savePinMux = 0;
, b( [* { N: X- P& l savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \ r8 Y: d$ x8 x" q0 r) s" X
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \& O: k* @, w; ?' t
SYSCFG_PINMUX0_PINMUX0_23_20 | \6 I2 I. Z5 n9 D7 N. O% a5 l
SYSCFG_PINMUX0_PINMUX0_19_16 | \% Y; P) ^4 r# B
SYSCFG_PINMUX0_PINMUX0_15_12 | \+ [( O: Y# S! Z" v% j! s
SYSCFG_PINMUX0_PINMUX0_11_8 | \
2 Y7 Q2 R: L8 A- C+ Y A SYSCFG_PINMUX0_PINMUX0_7_4 | \
9 V4 D6 ]5 m" y, r+ @ SYSCFG_PINMUX0_PINMUX0_3_0);3 `+ Q1 M/ t3 r! ~! h) _: f
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
9 X' T/ G M" V3 D$ _# c G (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \/ [ h* c1 ]% t; q H2 ]5 V" K
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \0 u( R U" K' `
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \6 K: m( s( @- T& u- a5 I9 r
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
: n& P6 V; r {" ? X; X/ _0 Q savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \2 I# U3 |3 A5 t) N' j
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \# \& u# ]# C- x
SYSCFG_PINMUX1_PINMUX1_15_12 | \
4 J8 `: e' ~4 ^; c* j; H SYSCFG_PINMUX1_PINMUX1_11_8 | \2 k# w9 I( K% e) H: U( U7 O
SYSCFG_PINMUX1_PINMUX1_7_4 | \
/ A- N8 b* o7 P% h SYSCFG_PINMUX1_PINMUX1_23_20 | \
& ]3 G2 R4 I9 H5 j* q0 C, o5 S" ]0 u: j SYSCFG_PINMUX1_PINMUX1_27_24 | \0 s7 v# G, {" R7 g+ ^* v
SYSCFG_PINMUX1_PINMUX1_31_281 L/ a- E) |6 u" Q) f
);
6 u: Z: M7 h! v/ ~ HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
- P+ A- _1 x9 y# u5 {0 R9 S6 P8 L (PINMUX1_MCASP0_AXR11_ENABLE | \3 t f5 N' W9 H/ e( G9 p' P; _
PINMUX1_MCASP0_AXR12_ENABLE | \
; t! } r; j8 P; H* X; [& \, b( _- T PINMUX1_MCASP0_AXR13_ENABLE | \5 M- @8 U, A. l1 o! m
PINMUX1_MCASP0_AXR14_ENABLE | \2 G! j& |3 v1 Y Q4 m
PINMUX1_MCASP0_AXR8_ENABLE | \
; X/ \5 b( }! J PINMUX1_MCASP0_AXR9_ENABLE | \
2 d4 }6 u' j6 s8 [% Z0 e& Y& W PINMUX1_MCASP0_AXR10_ENABLE | \* ` J4 K# [1 s# L
savePinMux);
# b# P; ]% r1 B% {. }}3 H# ^) k# U5 ^0 n+ o9 \6 x5 H
5 ~$ R7 w* ^7 ?& W* x5 Q [, C1.McASPI2SConfigure(); McASP的配置程序如下:
2 I W! p. e$ \0 z' o( J. Sstatic void McASPI2SConfigure(void)9 U; |, S4 d. e% o4 L8 T8 y, }
{
" H K [! z9 ]6 L McASPRxReset(SOC_MCASP_0_CTRL_REGS);; G+ {) q* G# V! Q7 U+ _
McASPTxReset(SOC_MCASP_0_CTRL_REGS);0 N6 |# ?4 w! b& b7 Q8 x( o
9 r n* d% Y4 p D, f0 Q" _
/* Enable the FIFOs for DMA transfer */7 O. v7 a' h. v# |. b8 q
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);- k; t: T" m0 `* D, F! M# ]
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" E! f0 r. ~" l+ A7 ~6 ]
3 U+ }: J: O' h$ w0 G8 f0 A /* Set I2S format in the transmitter/receiver format units */ H$ \8 U, k% g$ w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) d2 \5 g# ]& L9 q/ r* c! } H
MCASP_RX_MODE_NON_DMA);9 w' _8 z* I0 D0 G! Q9 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 V1 D3 |$ p4 R2 P8 Z& F! } MCASP_TX_MODE_NON_DMA);
$ F& Q1 D6 ^7 C6 G7 }% \+ c
+ ~+ ]9 f: [: o /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) \2 E* ]* j0 i! M7 z, T0 i B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 X; t5 O7 v; ]; t MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( z) a2 s2 F3 G! C ^' `8 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! G8 E2 \) f. E
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
" ~1 ~" q; `6 q. H U! ^. ~+ J8 N: Z- `0 u( n! \5 r2 n+ m
/* configure the clock for receiver */
& E; k4 w8 K6 ?1 j// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
9 V3 {* N" |4 L6 ~; U1 G McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ R( e. _6 o/ q. B. t7 ]0 U# _ McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);3 ~, s- }0 O- B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 X: P2 D& |$ j8 O
0x00, 0xFF);0 K1 _+ z; S7 [% A% |
% E; `- _6 I& } T; A7 E$ u; f
/* configure the clock for transmitter */* r# q4 m! u/ y/ S* I
// HWREG(0x01D000A0) = (0x00001F00);
) Z% R. ?$ \5 h6 u// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u); b5 v$ G& U- ?+ O" |: @2 E( {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);/ l: X& l. w* o) l- k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 I: v% ?! M. j: z McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," |) A# _3 z5 }0 n
0x00, 0xFF);
* J! i' ~8 B3 U$ x8 d. k
2 o8 r: j0 b8 }# X' J, ? /* Enable synchronization of RX and TX sections */ ) ?3 c; E" ^4 q( N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);( _% Q3 }' W; O, A: w
$ ~" v* Z4 b0 h9 n8 S3 A9 B5 ]
/* Enable the transmitter/receiver slots. I2S uses 2 slots */! S6 t" X% H7 S; v6 y( p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ?: t- a' |0 ]' q% P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 `3 P( Q4 u `- Z8 C
0 x4 ~" A" i% D7 f) S& {7 g /*
5 i- i8 m) V9 j ** Set the serializers, Currently only one serializer is set as ~& S& Z( [, i& T0 j
** transmitter and one serializer as receiver.( E; v& {: k5 d5 w
*/# [) z( g/ D/ ?+ L/ P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 y c, q( r% r% e# ~8 N, D4 I McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
. @9 ^2 _: Y, z' w* l McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
) N0 w& `" Y; G: e9 b0 K McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);, u1 i5 [3 s k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);) r& ^0 M( g* ?* ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);5 A. m; f# V: q
- j/ t$ Y' i1 z+ `# j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
- C* {! F q7 c; ~: ?+ R: K: w M- e
4 k5 Q+ V3 e2 o+ O O /*
) M& Y3 I* C! u2 }# M3 V& U ** Configure the McASP pins
$ l9 p( z: H h4 h3 b0 G7 n/ q ** Input - Frame Sync, Clock and Serializer Rx8 K% l# C% X1 d0 Y/ m! V% f7 U1 \/ l# }
** Output - Serializer Tx is connected to the input of the codec , o# ]+ j% z) y& i7 F+ A5 E
*/
# L) X4 _' g6 h) {2 D) U( ?4 e McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 E2 [! o: f' W McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
3 g. C1 l" ?$ Q, S' u \! r X MCASP_PIN_AXR(MCASP_XSER_TX)* q( E, s$ n/ i: u3 W! M
| MCASP_PIN_AMUTE
3 Z1 a0 `' }' Z+ A );
$ f4 t) j2 G& v McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,% W1 g4 O) d' d# y# B0 R/ f6 g
MCASP_PIN_AFSX9 k t# ?5 `9 W- ~! A0 V! }5 f
| MCASP_PIN_AFSR
! M2 |8 `5 L0 j8 l | MCASP_PIN_AHCLKX4 c7 C2 P9 C& D2 u
| MCASP_PIN_AHCLKR1 D% j4 \2 }6 b; A2 c4 I/ N4 p6 [8 ]
| MCASP_PIN_ACLKX
$ h! Y8 n; t/ h8 d! `. e | MCASP_PIN_ACLKR2 Z- @. D- `' @0 ?5 L( L# E
| MCASP_PIN_AXR(MCASP_XSER_RX)
# C# x7 v2 Q" a$ O0 Z | MCASP_PIN_AXR(1u<<(13u))6 d @5 x+ n- x% X4 J& r
| MCASP_PIN_AXR(1u<<(14u))
6 Y- y% p. O* z | MCASP_PIN_AXR(1u<<(8u)). _1 c- q" l/ M- p$ `0 T
| MCASP_PIN_AXR(1u<<(10u))2 R) o2 Z" q7 n
| MCASP_PIN_AXR(1u<<(11u))1 D5 }6 o3 M% L: u$ F" O( }( ~
);5 O- b4 u) T0 N# j9 T- }
" _7 |! A% F6 R9 K/ M /* Enable error interrupts for McASP */6 `2 Z# H) ?2 t! {& K. c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
: _+ Q' a/ W+ f# M! @9 h/ x0 y MCASP_TX_DATAREADY( W" L1 G) S l. Z: E% {
| MCASP_TX_CLKFAIL 8 w; c8 M8 R9 I2 t9 k9 N, _
| MCASP_TX_SYNCERROR; O n4 m8 F) y; H: l
| MCASP_TX_UNDERRUN);' O- f0 g& _: G. g7 z' _3 p: t
6 a x* S9 n! ]/ L4 z& _( l1 k
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,7 I0 s4 ]' \1 `- f$ _ {
MCASP_RX_DATAREADY, E( F1 C) N$ V+ ?- V
| MCASP_RX_CLKFAIL" t' K# p+ J( ~6 q' e1 E
| MCASP_RX_SYNCERROR 9 {" h1 }2 I- Z' M, S8 s' k$ A7 L
| MCASP_RX_OVERRUN);3 q; W% J s9 t
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR+ m$ @) Y, H4 S! o/ w4 y/ M
. c: |; o) F, j1 N. h5 y
}
8 ~7 {. A: @/ A2 _# P% \; V
5 e# y$ c& p: N2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句7 X3 ]9 v' [9 N4 ^' E: |% T+ d
static void I2SDataTxRxActivate(void)
5 r* V9 v* h. b8 Q( \{3 s! ~7 c& l' C. D+ c! G
/* Start the clocks */0 X% B) K; }% U% B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. H: |% u/ v# D6 ?+ y McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);% y0 [% F5 w/ {* v" c' O3 B; @
% a3 C9 W4 F* W C
/* Enable EDMA for the transfer */
/ d' C: E2 A. M1 d2 E// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& z- l1 g; V% V8 H$ C
// EDMA3_TRIG_MODE_EVENT);
' P2 H/ ]3 Z8 p; P4 j// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,; F) Q" E1 _" e c
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);: r$ x- J b5 F
/* Activate the serializers */- A2 z K, Y! m' `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 ]; Q8 D& c2 D W/ i9 E McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
c) x* c+ F$ B6 } R6 ^) ` /* make sure that the XDATA bit is cleared to zero */) [8 a; Z: b# |& m( s3 u& }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);4 V1 `+ m* C, a0 B( m
/* Activate the state machines */
% i. ~" X/ L* y; B4 v McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 w. }+ T# r% q* e/ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; S* k1 u! Y, l/ P
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
I( E- A9 {: O7 e) i}" m4 A/ Z- f* X" B0 V% n& u/ Y
6 s1 g# Z7 ^# r. ~) ^ |
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