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我的McASP配置分别如下:3 _1 U" s5 O- r/ m
管脚的复用设置是: Z3 `4 b/ G7 z e- ^8 T
void McASPPinMuxSetup(void)) t+ X9 E! l; I4 ~7 |% Q* p" Q0 X
{
$ P+ Z( g, f! J8 \ unsigned int savePinMux = 0;" R i) @# I7 q2 @! {) {7 z
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
; w/ r. V; f% C" @4 t ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
# T4 [2 P( e* V b SYSCFG_PINMUX0_PINMUX0_23_20 | \
) R# M1 ^+ O$ e SYSCFG_PINMUX0_PINMUX0_19_16 | \! U1 j4 n- \% z) W m
SYSCFG_PINMUX0_PINMUX0_15_12 | \4 A7 f# D& f7 @" w
SYSCFG_PINMUX0_PINMUX0_11_8 | \: d& }6 m. T [, |( x9 y& G
SYSCFG_PINMUX0_PINMUX0_7_4 | \$ m% j. g5 G- X& o8 [- z
SYSCFG_PINMUX0_PINMUX0_3_0);5 c2 J* G" M0 d$ B; k1 m5 X
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \' s# }, w( Z# g, O
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
! P8 I' O. f3 M PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
# N. m' a2 x& M+ ^ PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
( _1 H- _+ p) m+ P y; o7 t PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
5 `3 Z8 |) H+ D) k1 O9 F savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \6 M) Q% f. C# Q2 Q W
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \+ P& }' O1 `; s8 _$ _
SYSCFG_PINMUX1_PINMUX1_15_12 | \
3 C$ ? W4 Y: r3 Q+ E- q SYSCFG_PINMUX1_PINMUX1_11_8 | \
" A& |- R2 f, I+ h* | SYSCFG_PINMUX1_PINMUX1_7_4 | \
- q4 [* [2 c' i1 W" J SYSCFG_PINMUX1_PINMUX1_23_20 | \
e* ~( W4 z: `5 D& p6 N2 _ SYSCFG_PINMUX1_PINMUX1_27_24 | \
2 w& K3 g e* V SYSCFG_PINMUX1_PINMUX1_31_28
" F5 P( c2 I: s9 Y& Z );
* g, p* i) t& u! G3 T. [ HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
l, w. n+ n7 q& W8 ` (PINMUX1_MCASP0_AXR11_ENABLE | \2 z% T0 k$ H; h# q& n0 O* x
PINMUX1_MCASP0_AXR12_ENABLE | \
% G) d' [9 R6 K2 Y* z PINMUX1_MCASP0_AXR13_ENABLE | \
. [8 W# `9 r3 [ PINMUX1_MCASP0_AXR14_ENABLE | \
7 T8 S( ]" H) G3 b( m; O PINMUX1_MCASP0_AXR8_ENABLE | \
. G( W/ R- u: ^4 [4 }/ v- m PINMUX1_MCASP0_AXR9_ENABLE | \$ x" e, }2 ^, Z' J
PINMUX1_MCASP0_AXR10_ENABLE | \
" F5 f; H5 T8 B/ f5 I C savePinMux);
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$ Q. m9 D$ {$ H3 e! B; ~
1.McASPI2SConfigure(); McASP的配置程序如下:4 f& B. a' |1 Z( g8 e/ w/ m
static void McASPI2SConfigure(void)
" h6 z0 v7 j) R7 z$ I3 B6 n{
3 Z& M7 c" Y4 ^. ]1 g McASPRxReset(SOC_MCASP_0_CTRL_REGS);) T. I# g' _# ] J @3 F! f
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
X, r/ X2 j, Z7 m" |6 D* Q/ U$ E8 B% z1 _) Q O, e8 r$ H
/* Enable the FIFOs for DMA transfer */
) a* ~$ t( ], P// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);1 s) ~9 r7 I, P' M; k) v
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 Z9 |2 U5 r, J, b5 I& B0 b @! o4 p. Y9 G! S7 T1 e
/* Set I2S format in the transmitter/receiver format units */8 l- F0 Z3 N! ^) v. n% r! |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 R- n+ v" k% F+ [4 r. p7 @8 \. @
MCASP_RX_MODE_NON_DMA);
( X S1 g+ J4 K; a( B! r McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% B+ Y5 F! L) `% S+ [/ E
MCASP_TX_MODE_NON_DMA);
; W+ R3 y X7 D, X" ?4 W
S- T) |, ^/ B# _$ M /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) t$ E+ J: Z& y6 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 \; G: Z! Y) ^; Y4 I8 } MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) u( h( F2 g8 f( s3 d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 X4 N' f. R7 X MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);, B9 A w1 c7 i! ]+ f' F; g
) h D" V5 o1 N% n; y" x /* configure the clock for receiver */( t9 P" {' ?1 @( h
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);5 S8 N" B' O1 v7 }! z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! B8 C# g( `) u X i& z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);# C; Z* z) i F# @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ y0 Y: d' u2 c) }+ ] 0x00, 0xFF);
0 X+ `. X2 `0 [$ G% `, U' ^8 _' R# }7 ?
/* configure the clock for transmitter */
1 L3 c$ ]3 B. H: |* P// HWREG(0x01D000A0) = (0x00001F00);; N& U0 }* M c. O5 t+ q! e
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);$ G- r2 V5 J: j2 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
. N$ C0 G+ \/ H$ _& z3 o7 a/ s McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 d# v5 |% G* m McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 S5 c2 w" L* b; }
0x00, 0xFF);7 L" j5 l3 g- }( F; d
' T: F0 F. K4 T: W, Y3 O
/* Enable synchronization of RX and TX sections */
/ Q: J0 T5 g# D. G8 s5 ` McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
+ |0 O0 l: `4 D, E2 ^' e$ }; ?2 f6 S- s0 b* @
/* Enable the transmitter/receiver slots. I2S uses 2 slots */: E( r* e& J! `# Y+ G2 W9 `+ e5 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 X) I" Y! g4 ^ McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; Y4 B$ N. x1 H% H" Q; D ^1 ?( t8 d$ N5 w9 e$ d
/*
# f' p( [; S8 `; }! n2 b ** Set the serializers, Currently only one serializer is set as
+ q ]5 R2 O+ d. H1 @' b ** transmitter and one serializer as receiver.6 y: p) _4 t! N0 q
*/. f! P8 w; D9 u4 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 C" P, v7 }' ^% O3 z: W: h McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);4 z7 s6 }& D5 u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);; m+ |$ j1 q, V2 J- J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);/ y( x q; @. y: D/ C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
) G* E5 b' N" q9 T2 M, h- a McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);7 H( O3 v4 T5 z( h% g. r% o3 N
+ o2 R2 |1 l' W+ Q8 r5 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
7 o" V: ?; e; y( i$ u4 ^
3 q- C% Z6 c- S" s6 J /*
) n+ t# I1 j: k1 o# z ** Configure the McASP pins + Z+ a1 Y/ c5 Z. e9 S
** Input - Frame Sync, Clock and Serializer Rx J; r+ ]4 }' E% ~- ~
** Output - Serializer Tx is connected to the input of the codec
$ D2 F* O3 @2 T7 U h1 G */
3 z$ t) [7 [5 O# M: @- x& S McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' _/ i5 T j7 I, ^ McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, [8 ]9 D- ]3 ~
MCASP_PIN_AXR(MCASP_XSER_TX)( W9 d# V# T$ n* A9 m( ^2 _
| MCASP_PIN_AMUTE
5 i$ ~# o3 O2 r# I$ B* z; Z- k );7 b; m1 t8 {1 f, Q0 H. K/ h% B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
6 G, O8 d4 F" f: X9 q0 Y MCASP_PIN_AFSX7 ]; _ U1 ~' ?: n, R
| MCASP_PIN_AFSR
9 ?7 n8 n1 x) p | MCASP_PIN_AHCLKX$ n2 h6 t* ?- a* n! d7 {4 c
| MCASP_PIN_AHCLKR* E. b2 O- U( Q% r) |0 w' n
| MCASP_PIN_ACLKX- S, ]9 C0 l3 R& b$ Y, x
| MCASP_PIN_ACLKR3 z% U5 Q8 }9 T$ U& `
| MCASP_PIN_AXR(MCASP_XSER_RX)
$ m# a1 K, R2 T/ F( d | MCASP_PIN_AXR(1u<<(13u))
# ?/ p% g" C2 P6 t, {; b | MCASP_PIN_AXR(1u<<(14u))
% O( ]& o( y6 N. R s4 \. q8 ?/ { | MCASP_PIN_AXR(1u<<(8u))* x. D# D+ T5 a. O$ n
| MCASP_PIN_AXR(1u<<(10u)) j. z% e$ \" r
| MCASP_PIN_AXR(1u<<(11u))
9 {/ z- k! z3 |1 [ );! A2 U% F; d/ _
7 x M, p% `) J3 H9 N3 N& g; A1 j
/* Enable error interrupts for McASP */
9 M5 z# K; [2 l2 a* S/ o+ h. a McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,* _4 c1 I0 q d7 J! _. _* ~3 o
MCASP_TX_DATAREADY7 f2 v& t4 d# f( M5 B+ _8 W
| MCASP_TX_CLKFAIL
, r# F+ _2 w; a( X& { f" e9 ] | MCASP_TX_SYNCERROR" X0 M; c" z1 f4 x7 U
| MCASP_TX_UNDERRUN);& G- `6 v1 N6 U1 ~( ]/ e6 V
& s( f- O: Q" @0 \* D McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ C3 S9 E, j5 W) g MCASP_RX_DATAREADY4 Z- O* [9 m* _1 h" l' C) j9 G; q! _2 X
| MCASP_RX_CLKFAIL
z* A; Y4 a1 d3 M9 o c% O" ` | MCASP_RX_SYNCERROR ( g5 l! S; N' P$ [& h% o& x
| MCASP_RX_OVERRUN);
: @! ^* }4 {' `7 E* b2 L1 T2 u& B//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
( V: b7 m, R: K; D* ^0 S3 q$ e) Y* T( ^8 G
}6 R: h0 u s3 z0 l$ `. x7 d" z: @
3 J) p+ J* W8 Z c2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句7 X+ F- x" @0 S" C3 f
static void I2SDataTxRxActivate(void)
$ k4 u7 j$ y( y8 l$ U' e{
& K# J2 s. r: Q s( J z /* Start the clocks */3 \' d! d- O/ H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 P/ I6 J& x. r1 @. Z1 ?& U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
8 L2 {( h: i$ r( X5 c
0 F' O! q7 n/ i3 @- I /* Enable EDMA for the transfer */
; r* _0 o+ v- D( u* T! X// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& T4 L, m9 p% s8 ?5 E7 O// EDMA3_TRIG_MODE_EVENT);" ~5 b1 t/ C ^7 \( j. T$ J
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
G T2 O0 T* P9 Q3 J- I// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);- d3 V- N" ]9 U! f% Z" T/ W: x" P0 M
/* Activate the serializers */
) G$ P# G( Q& s, ?& `3 { {# i McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( y& L- s1 N( ^) v. c& c2 Z- @ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 ?* J5 u) h2 a& h /* make sure that the XDATA bit is cleared to zero */
' v' X5 M9 A5 w' |8 j. L$ l while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);. ^5 ^4 O/ p" B5 o" Y4 F8 a/ D8 u
/* Activate the state machines */
0 K$ K- e3 X" C! ?8 z McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ @0 L% s X& g/ s0 y9 k$ ?; K1 p McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 h! n- R! K4 n9 {# y
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);/ f9 C" u: O0 b K r) p( P
}
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