|
The timers support the following features:2 Z5 \8 \# N! j: I5 Q: E
• Configurable as single 64-bit timer or two 32-bit timers
9 {' y" v2 y, O' O- M+ X; `1 J, O• Period timeouts generate interrupts, DMA events or external pin events
0 S9 N& S1 h* ^7 \( J; c• 8 32-bit compare registers
7 `% w. I- b- x" ~7 }- G0 T0 L& T• Compare matches generate interrupt events
, z1 u& H3 p+ S$ f( D- ^0 {; }0 t• Capture capability
9 e* [& I+ m) E% s0 \% l" z• 64-bit Watchdog capability (Timer64P1 only)
1 @& v3 q1 ?" V; o# {) y9 G9 j; g) ^$ c0 p, Z& ?
/*
& J3 K: b$ {+ b% n- e" _ * T0_BOT: Timer 0, bottom : Used for clock_event
9 ]5 @8 ~9 {9 T. f& k) [1 g! P * T0_TOP: Timer 0, top : Used for clocksource
; o6 ]( ?* v3 }8 v4 O1 \( ~% S * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer! l. {1 I G1 U. O6 X9 b( e- E
*/ |
|