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The timers support the following features:
' k' w- d% T' y1 v* O• Configurable as single 64-bit timer or two 32-bit timers
$ u5 k/ ]; {* D9 |• Period timeouts generate interrupts, DMA events or external pin events
( U& a H" _- I• 8 32-bit compare registers
& s$ l. Q: c( Y. W0 m) R• Compare matches generate interrupt events* W" m! a+ H3 S: g
• Capture capability
) _8 m) a: D) Q7 `. F• 64-bit Watchdog capability (Timer64P1 only)
7 w8 c) w+ G3 B; _, r% Q7 F7 G1 X5 [" y' G9 X
/*0 ]9 k$ N, H& g( o
* T0_BOT: Timer 0, bottom : Used for clock_event
6 K1 O4 U/ V; e' G * T0_TOP: Timer 0, top : Used for clocksource
: I5 ? g1 p- E8 u7 `5 P: ^ * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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