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The timers support the following features:7 N* p$ I, p' H- h. Q1 L/ K
• Configurable as single 64-bit timer or two 32-bit timers
: K: A! W2 B" I7 q- I, \• Period timeouts generate interrupts, DMA events or external pin events
2 C5 z! M; g) \6 ~• 8 32-bit compare registers2 O+ V" @: p; ^* j( d2 L
• Compare matches generate interrupt events
8 s+ p3 f0 p$ {# F0 Z& N• Capture capability6 i5 D" P; a. t# a; ]
• 64-bit Watchdog capability (Timer64P1 only)0 j7 O8 z8 ?' U* \
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/*
- D0 C2 P% V8 j% Y0 r: g * T0_BOT: Timer 0, bottom : Used for clock_event
5 ^. [! |# y$ H( F9 d# o! j1 E% p * T0_TOP: Timer 0, top : Used for clocksource; Z* j% A; u) D) d* R3 b7 d' q
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
7 l; K' t7 ^! _: v$ ^6 }/ z */ |
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