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The timers support the following features:8 \! q4 O+ L; }( Y" X+ }
• Configurable as single 64-bit timer or two 32-bit timers
; X4 ^6 ~$ S+ F- k• Period timeouts generate interrupts, DMA events or external pin events
0 k j5 [0 M+ M2 Y( P! \. ]• 8 32-bit compare registers8 W- l8 f4 V( L9 x. R) D
• Compare matches generate interrupt events: w4 I0 U5 B+ G8 [# R! J, t
• Capture capability
) H: ^: \( E+ n2 E2 }• 64-bit Watchdog capability (Timer64P1 only)
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* T0_BOT: Timer 0, bottom : Used for clock_event% A; v+ X/ y$ ^' @ B
* T0_TOP: Timer 0, top : Used for clocksource
" h/ Z: M* w h8 |2 A0 W( W: o$ K * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer+ Z) {" E1 M' O/ ? _
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