|
The timers support the following features:2 i: W8 n; r- M& i. E
• Configurable as single 64-bit timer or two 32-bit timers
9 E' H" B; |7 A* Y• Period timeouts generate interrupts, DMA events or external pin events9 M* g x( p+ T s+ A- j# l" Z
• 8 32-bit compare registers
" L9 S' f3 { x I" a: Z• Compare matches generate interrupt events& A8 H1 Y* E& J- Y
• Capture capability# ?& c5 I) u( j7 d* a( z# v# b
• 64-bit Watchdog capability (Timer64P1 only)& O5 c1 M; L4 F' n' ?; i
4 d, `1 L8 i& q9 E( Y1 x/*
7 J# [& ~' A& i& Y+ ^4 Y2 r1 L. Q * T0_BOT: Timer 0, bottom : Used for clock_event
* `4 p. r, y( G% Z) T E * T0_TOP: Timer 0, top : Used for clocksource8 n" G# l" C6 V. l
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer5 y4 R6 h2 W [" b: q: L
*/ |
|