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The timers support the following features:
4 V+ W3 i, _" u! f• Configurable as single 64-bit timer or two 32-bit timers( w( t1 k5 e9 C* ?4 @3 X. q, X$ P
• Period timeouts generate interrupts, DMA events or external pin events6 \, `/ p& A( G* Q+ |# Q
• 8 32-bit compare registers) ~% k; G. w0 h, j- C2 O: W9 q) y) ? |
• Compare matches generate interrupt events3 y8 ]9 y2 `2 j3 g; W" M
• Capture capability6 x& t/ L; C! Y: x2 F" ]' e
• 64-bit Watchdog capability (Timer64P1 only)
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* T0_BOT: Timer 0, bottom : Used for clock_event8 W; A' X V2 q; T) T8 z8 C
* T0_TOP: Timer 0, top : Used for clocksource
$ v" y2 r# k* j' J% Z: k' ] * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer1 @$ v3 ]2 V/ N6 Z: v
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