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The timers support the following features:
+ D$ R% p: { ?" z: I- I7 b/ ]• Configurable as single 64-bit timer or two 32-bit timers
! e* f/ R! P- y, N1 R S( Y• Period timeouts generate interrupts, DMA events or external pin events
) Q* Y& R1 N# Z* t" y• 8 32-bit compare registers# p) e/ d; s) M( j2 n
• Compare matches generate interrupt events
# O& p2 S2 }& y• Capture capability$ v" u1 Q1 ^: n: ]3 L9 W
• 64-bit Watchdog capability (Timer64P1 only)
: x- {4 x1 h2 l6 x. ]8 T* n* D" S- N' G J5 U8 S! Q/ @" |) P0 [
/*
. i! e! h9 L* q. M/ [$ ] * T0_BOT: Timer 0, bottom : Used for clock_event$ B- `7 G4 n( G" r7 w
* T0_TOP: Timer 0, top : Used for clocksource! }' R: @# K# w! u- v5 Q
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer8 L6 W! R! ?. C' d
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