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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! k9 C, p' g7 r5 c4 s& `
input mcasp_ahclkx,: M1 e" @6 I" X& k/ u/ A* C
input mcasp_aclkx,
9 o6 W; {( l9 d& w2 B. s- F9 \+ s p# Finput axr0,
) n6 M$ z- N8 [% {
1 P4 k: x( a, c- ?: S. Joutput mcasp_afsr,
$ e+ \- k+ D) u" G! Noutput mcasp_ahclkr,
; }+ N) S4 P, ~8 Voutput mcasp_aclkr,' i5 t8 [: Z7 [% ^# R9 Z9 c
output axr1,
) P- F) J/ A0 @7 l assign mcasp_afsr = mcasp_afsx;
. t1 \9 o' a% Vassign mcasp_aclkr = mcasp_aclkx;
i2 E' ]4 T" W/ Dassign mcasp_ahclkr = mcasp_ahclkx;, A* K$ D* v1 ?5 z0 r# v: g O
assign axr1 = axr0; 5 w+ e8 V) |" l0 |6 `
7 c L7 f7 j0 [) N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
Z; _( @5 ?7 C$ h# G* kstatic void McASPI2SConfigure(void)5 P) a6 d) W: i" [% u5 v1 D" J2 b3 L
{% Q9 a! s5 `3 X4 i& c8 ], q k, ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 X& N; x& }0 o8 eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 V# ?% V% h6 {- u+ ~- c" Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ [5 t, V+ X7 j, K# SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 t$ {) d7 ]! K% I* h% AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 M4 g) U n5 H& o/ sMCASP_RX_MODE_DMA);! o: P. g& g# X5 q$ v. d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t1 x2 }$ D3 K1 W+ _3 h2 V5 S, m- F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, _: ]- n/ S$ U7 g! u. f" rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ J0 N6 W$ k: rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( w/ z1 }& ?5 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* D) h- {8 h' w2 k) @. [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* j) g1 H/ s3 m' Z( b+ k0 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( s5 G5 ~# d! {% @- r4 a# Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Y' J# L9 d+ k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 j( n, s1 w' Y5 h1 K- @0x00, 0xFF); /* configure the clock for transmitter */
# g+ r! g3 t3 O* tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 h& Q( W1 e6 U6 a: `- T* o2 K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" d6 P: g4 X) C6 u5 _" X4 w V5 XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& R3 Y7 G# d0 N* `2 h* V$ e) w3 M0x00, 0xFF);2 e/ \. f2 f$ I6 P
4 m! \% M& E1 F- l$ T1 s
/* Enable synchronization of RX and TX sections */ 6 X4 J% Y4 j8 b7 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 n( r5 q: q* [9 v2 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; u) m L" G: l8 `( U: l6 X9 P& u+ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ N# y9 _! p5 O d4 q1 K& f
** Set the serializers, Currently only one serializer is set as
- G: @3 b4 _3 I" I! J** transmitter and one serializer as receiver.
) g* q' _* ]& m! s5 Q9 T/ Q*/4 g) K8 y. z4 f3 x9 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' c1 H2 P8 |+ o7 N8 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- b/ t5 F6 w6 n# J, T- n** Configure the McASP pins
2 M+ V8 v+ b' H% ^+ z** Input - Frame Sync, Clock and Serializer Rx+ j5 j3 q6 {- O* I4 C/ Q
** Output - Serializer Tx is connected to the input of the codec 3 n( m' i" K* w
*/
4 g$ V, P+ B! q7 Z8 q0 h# vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 i' z$ Y5 ~2 ~3 G: u8 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" S/ [5 Y: U' d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ A/ k* V0 v5 b, O" I) o
| MCASP_PIN_ACLKX# i+ ]. q c' Y. E
| MCASP_PIN_AHCLKX
+ |1 M: H9 w" L( ?' A* S% D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' {. B1 f5 ~9 e' m: q+ z9 \: ?$ rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' I0 v' c* H3 e) L- E| MCASP_TX_CLKFAIL
8 B! W! E* R6 k. A2 E! M| MCASP_TX_SYNCERROR* }5 r+ e+ c$ |! n5 S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * v4 ~/ F' \7 J: _& `
| MCASP_RX_CLKFAIL
5 Z" `& ~' d# P2 }8 H6 R| MCASP_RX_SYNCERROR
& @5 u1 `0 ~! D% \" R Q/ T* f| MCASP_RX_OVERRUN);1 n: e# c3 x6 p% H% Z
} static void I2SDataTxRxActivate(void)" I6 f( n, ]' _1 K* F g) D ~
{
- J: L$ z7 F3 Q4 y ?) t/ j! p/* Start the clocks */
$ g3 H/ Y/ ], L0 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 T7 Y7 Z% L2 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 G$ S9 l. Z5 t" [ CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 }+ ]9 i- f/ H2 ?EDMA3_TRIG_MODE_EVENT);
# h P8 K: R* A2 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % J R% _$ M/ W9 V. n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& m! L& N9 t; N5 \/ ]% D/ bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 U% U. Y+ K+ {+ U+ e O( ~& @' c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 K- M4 n+ @2 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ ]2 [4 g7 i! oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) ^; M( }4 _/ L+ M" H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* g2 F8 k# _* Q9 d, }6 f+ A
}
2 S' _- V5 n8 x. v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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