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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 f1 z+ G3 }2 z6 X B# @
input mcasp_ahclkx,
6 }0 O7 a' {+ V8 Y, T" ^+ @input mcasp_aclkx,6 l5 ]0 G. x$ S
input axr0,
* X9 c3 @' D5 \3 Y& I& u/ T' t4 W
output mcasp_afsr,
. p" V% I! |% y1 Ooutput mcasp_ahclkr,6 d: ?) r0 l$ X7 q( w( n- y
output mcasp_aclkr,* y9 a$ ~) y0 ~- M
output axr1,+ O0 d' G8 M& P+ v' O
assign mcasp_afsr = mcasp_afsx;1 B$ E3 F% n" y5 R
assign mcasp_aclkr = mcasp_aclkx;: b# U! T0 h( ^: L6 ~( {
assign mcasp_ahclkr = mcasp_ahclkx;
. K+ y h5 \) w+ [( @: \$ P1 `assign axr1 = axr0;
4 v$ i/ U5 d" G9 P# {
- h1 a- L3 u D1 \! j& Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; }1 M- }; @3 P% Cstatic void McASPI2SConfigure(void)
0 ] V. a8 y3 { W! \- }{
8 {( _8 p; h6 N0 T' @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 K- b! \1 k* R! O r: [ UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ Z7 ~: o$ n, Z5 M0 R. h, v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( \- k( l1 F6 v. k* M" H$ \4 g# q+ XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& H+ v1 M- L+ }& `: v* E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' I6 Z3 X* ? w" E% Q; x. Z
MCASP_RX_MODE_DMA); |3 _$ g( x4 y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 w1 j4 K" r8 g, h7 y/ W+ w4 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; T: _: p4 {- Z9 _% a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , e7 d% \: f# Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 W1 d' f+ a1 Q& a: z2 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' p9 I [9 E& q7 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: a- H2 g: z. J" D5 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ R9 y& p- S5 \, m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 P9 ^) \. P b' e5 g9 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," h) X! l8 {) O/ N) I
0x00, 0xFF); /* configure the clock for transmitter */
8 i6 n/ [6 L8 Q/ C/ WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. y9 u8 \: ~# @3 r) f+ d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 I( N: c- g9 F0 g. b. ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, q5 B7 L) ?, u8 |0x00, 0xFF);
; N( v, b" F/ d" f$ \1 W+ |2 w# F( x
/* Enable synchronization of RX and TX sections */
2 |1 k% H; J. G: v- QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 w/ B# |( z" y& u/ w1 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# D X) T. A& C1 B v; PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& H, n9 x4 P, z3 S& k$ {
** Set the serializers, Currently only one serializer is set as
( n/ U& |3 n$ i& ^4 _( N** transmitter and one serializer as receiver.
2 j" o* e$ `; K5 X% A*/2 w* t9 y6 G/ f) l. h8 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
S# a5 D h( Y1 i: K F& WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 m M$ Z7 Q! \/ o' l
** Configure the McASP pins
8 ~: H% B' A$ {* Q5 b+ a5 S** Input - Frame Sync, Clock and Serializer Rx, q+ O) w9 K. O; K6 W2 F
** Output - Serializer Tx is connected to the input of the codec
2 a m: K. R* r2 M. L0 Y*/
3 Y& f7 _* ^6 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! f% X( R1 U6 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) [; ^" D6 M e; [. Q* UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 }* W, z$ z# A+ ~3 s| MCASP_PIN_ACLKX; t* D$ S% E6 B! i8 l* f. p
| MCASP_PIN_AHCLKX6 u9 U6 b+ Q# Y' h6 W ~' H, s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( J! P$ ^: C# ~" d: h5 ?7 S7 {' ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: F1 w; I# x+ k- K. \; k$ z| MCASP_TX_CLKFAIL
9 U( V$ S4 L' X0 G- b9 j1 I: T( T& W| MCASP_TX_SYNCERROR
; j0 P' w0 i/ T& b m7 R4 [- g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , d- s& \* X4 k; e! g8 G
| MCASP_RX_CLKFAIL) O2 R ^3 N4 x% W: J: J3 i
| MCASP_RX_SYNCERROR 5 h2 U0 A4 L9 x
| MCASP_RX_OVERRUN);; J; E% [# P4 L+ q0 _( {
} static void I2SDataTxRxActivate(void)8 u8 I: p( F- v* T6 R
{
/ H A5 U {8 |2 h( O! O; M/* Start the clocks */ r& q# L, F9 h4 @% R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 M. ^2 t8 @+ N u: n4 j9 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! |( F* `" t5 L5 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& R2 p7 ^) h1 m2 s! ]
EDMA3_TRIG_MODE_EVENT);" J# d/ g# L6 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: o! X4 S+ S/ m6 n1 h4 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. F8 {7 I( c9 l* C, Z' b8 D( IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 G V# i* p, V' m6 T lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: ~+ ~; H" `/ X( J) fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
s4 n% w H4 ]& |" |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# {7 V: h7 t/ G* ^# C: f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 \6 e8 O+ [; N; h. d6 p
}
' _- V! e( ?8 a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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