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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# u4 X X4 x" U f3 E, }" S3 x1 I# q5 ~
input mcasp_ahclkx,' D. ~4 I1 f7 k. o8 P& f( q1 \
input mcasp_aclkx,- X" ^, B+ M, ]) F9 q2 \9 k
input axr0,( ~% a" {- @; E% X, T* ^, G
) v8 T3 c/ J# |, j+ J* c9 woutput mcasp_afsr,8 b# b/ F7 F8 D5 }
output mcasp_ahclkr,
. b9 a8 P1 }/ @8 J- t( |output mcasp_aclkr,' j" j" `( W: O7 u4 X
output axr1,) ^0 |/ O/ L1 b- b8 w- V
assign mcasp_afsr = mcasp_afsx; R# D+ ^9 u* Q4 a5 S$ J
assign mcasp_aclkr = mcasp_aclkx;2 [' ?! N. U* C% M, K2 d! k2 B9 e
assign mcasp_ahclkr = mcasp_ahclkx;
8 R h6 j% j- \0 a2 T+ jassign axr1 = axr0;
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# Z- k1 D I* w1 W) y3 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 N# u5 V) q% l3 \3 c
static void McASPI2SConfigure(void)0 B' H: y2 F' l: D; M
{. _6 D9 I+ p, A7 h6 _+ r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, Q, N, N; x' B. `. w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& R, t. j9 D9 H4 [1 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. G# J: o8 p* _4 G6 L" ~; F. lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! e4 w) T& y h, B' C& q( n& tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 d- }2 g( ^/ G0 Z; s7 Q. h( r7 a1 t
MCASP_RX_MODE_DMA);% }9 e/ U5 }$ t: D2 ]3 T) ~ B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& I, K6 [( M5 w3 q, X' B) X7 T7 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( o% ^5 S2 G# d' a& { h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 U% t$ N- P& G& H/ ^* ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# ]% Q" i" k- u5 U, rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * H! l' r+ I8 c/ I, H5 c' o4 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& {+ s8 S% d# I+ Z% z7 ?9 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* h- `0 C7 b! e+ {) h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 c. R* m4 M/ A8 ]" [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. Y6 X" r+ O# o9 j6 k0x00, 0xFF); /* configure the clock for transmitter */' r9 ^. D8 k8 ]+ e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% S, ^# a' e0 C: {' b P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ G6 Q2 [4 h A4 t( Y6 H, c& aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' W& f X- B& u9 r1 J7 a: I+ V0x00, 0xFF);5 @! L; C( e% A' ^# o9 P
$ ?$ _! l' r# k% D5 c3 X/* Enable synchronization of RX and TX sections */ 2 r. Q8 E* _8 U8 X+ C2 I, d) l% V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: f& X* @% a1 Q5 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! B; X0 J+ T* X( B7 E. v/ eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% P2 d9 b, t- [. x+ M* }4 H! e3 Y
** Set the serializers, Currently only one serializer is set as
) g& K) x. D( A t** transmitter and one serializer as receiver.
4 ^/ r9 w" |& `6 s7 H( P*/
' k, l1 s( i6 c5 uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% z- ]+ p0 S# Q1 D9 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 D9 d' W( o5 I% a. x
** Configure the McASP pins 5 u9 ~2 S9 G/ u# U: U/ I& L
** Input - Frame Sync, Clock and Serializer Rx
6 Y6 I; a1 z/ g& O9 O+ _: ~4 C** Output - Serializer Tx is connected to the input of the codec
: f; ~6 M+ f& _& |- F*/
1 O* g. ~& D( M# x! r0 _5 [* [4 ], cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ G! Y6 L* I( q. {% \3 y) B- Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 U" E. _) W l" E! m% q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' F& g7 f; p9 |7 D4 z/ b9 S( E6 H9 i
| MCASP_PIN_ACLKX$ u n! O" ^, L6 [/ b9 T" c: }
| MCASP_PIN_AHCLKX5 l# `+ ?' c8 D, b- d* _0 \7 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* u4 ~ k/ }, A9 k6 H6 ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. ^& y3 l/ J: _ R& r c9 E| MCASP_TX_CLKFAIL 6 c0 M" v& R3 p2 O
| MCASP_TX_SYNCERROR
# }; L' z2 ?5 o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % J$ O, f' |* r; q9 v+ @* f8 T
| MCASP_RX_CLKFAIL
# ]( Z W: x" y$ v9 Y6 g1 X| MCASP_RX_SYNCERROR * J- h9 q, ]8 N
| MCASP_RX_OVERRUN);/ |' S. x$ [+ E5 H
} static void I2SDataTxRxActivate(void)
$ d! u) V6 g! e4 m1 R' c! i{4 }, U% ~$ D/ x5 R1 b, M
/* Start the clocks */# u/ B% J% q o) O6 V, M# u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 D) O( O, u& t. uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( A) J e& | c0 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& `+ ~. r; h+ x& }( s1 I
EDMA3_TRIG_MODE_EVENT);
5 k" C% ?% `8 |+ MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 D- Z$ b$ v! z( k1 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; ^5 y, |2 Y* O2 X# s! U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# p6 m6 z1 B0 i" q* W# NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( [* X6 F) j" Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, v0 ^7 i0 O5 t* r/ h S( C0 X' qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& J2 j2 w7 g |) l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ [! m. y& t% _}
% h% b# N# i1 e# T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. N& P/ s4 N7 p
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