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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ t7 m+ } P0 n$ rinput mcasp_ahclkx,& o+ v; |2 g5 l: x9 F
input mcasp_aclkx,
9 K8 w' y: y( E1 }4 _9 oinput axr0,
; L$ v# z/ n- v! n" B1 r4 n" O) d4 V- T* Q* q5 U5 y. d* P t
output mcasp_afsr,
1 Z& c5 r$ O' Xoutput mcasp_ahclkr,* i" f2 n% d4 i5 o: T( y! y
output mcasp_aclkr,
9 W* i" j6 _) u) i8 eoutput axr1,0 H& V, M3 `, O0 |: o" Z# K" e7 o* \
assign mcasp_afsr = mcasp_afsx;" W- t& J, w) @; C
assign mcasp_aclkr = mcasp_aclkx;
' d5 ~9 Q' H! E) Cassign mcasp_ahclkr = mcasp_ahclkx;- s, [ q/ I3 Z
assign axr1 = axr0; " F+ ]/ c2 F: t. R
4 x) `9 s. i4 t/ {, ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 R) T7 L- T* j, n1 mstatic void McASPI2SConfigure(void)4 K+ u$ b* K- W, t; @8 W1 |% A
{ _4 r; y+ U6 l# T' H5 K! |
McASPRxReset(SOC_MCASP_0_CTRL_REGS); X6 e' e) E" ^; t# B: X o" C3 ~- U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- P5 |+ b: w3 S$ T2 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! `6 P) o; H6 c9 i+ Y+ ?( W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) f4 p+ N+ E$ Q- W; J QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% ^/ j2 Z0 y* Y/ M, J$ C) L# `
MCASP_RX_MODE_DMA);
9 S) }2 f# `7 K! KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ s" [, \- h; L. Y- mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# A- W6 R8 Y/ [; CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, f& {# n) X) QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 ?1 P. v' f1 n) Y5 Y4 M: r* `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; Y9 a* L* N* ]1 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ Q( Z3 B6 D" a: rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 K% a% B9 p4 l8 L# u( H( @0 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ W% x/ w* \9 l6 b* O# Q e8 ] c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* F0 \ `: X) ~, t8 p; L. j0x00, 0xFF); /* configure the clock for transmitter */5 W. z7 N5 S8 ^* J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( F: f: R. g" t! h3 L. _# z. {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 n. g( h) g- {$ fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' p$ Y M& ]! ^$ Q0x00, 0xFF);% V) p) v( L9 o; l- @. G0 v
/ O; o) K$ v! {7 ?2 i0 y9 J( l6 E/* Enable synchronization of RX and TX sections */
% J% E! }+ X3 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" [7 Y# C5 X1 {. f- G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& [7 y- T. M+ k) a, y" o) zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 Q3 K# z7 T6 d" r6 g
** Set the serializers, Currently only one serializer is set as
, c V H0 U" e' {# B** transmitter and one serializer as receiver.6 |( L! O# d$ E) f& O
*/
; M+ S9 J, s0 D2 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
d, C: {' m7 L1 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 g7 H; b7 @- e- R4 N** Configure the McASP pins ( Y- |3 q3 j, _7 B/ F# [
** Input - Frame Sync, Clock and Serializer Rx1 Q8 Y/ x* ~7 f1 C& K
** Output - Serializer Tx is connected to the input of the codec 3 k6 Z7 }7 M0 g9 L2 p
*/$ [: F. o; P7 I# u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
n# E) j. D: D2 [: K2 F/ z6 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' V: t% a8 Y* I3 Y! Q. s* L4 G4 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- i. a. h3 {7 ?: F% S* A| MCASP_PIN_ACLKX
2 ~, E$ M% z" J6 M7 I& U| MCASP_PIN_AHCLKX
, b1 k0 ~ p. y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 u7 ?$ X1 q9 S0 S3 Q0 \7 T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( D( C; P: t" X0 D& L| MCASP_TX_CLKFAIL , U: r3 M% s% }- {# s. R2 G3 a
| MCASP_TX_SYNCERROR
/ x6 ?) g j! _1 C3 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 `0 @* r$ J' [. Q2 |- z| MCASP_RX_CLKFAIL
. c" ^+ W V/ u7 p1 P* g| MCASP_RX_SYNCERROR ! n/ x& Z8 j8 J) h$ [
| MCASP_RX_OVERRUN);8 ]7 }5 V" X" q
} static void I2SDataTxRxActivate(void); M8 Y: ~6 k5 C0 K' C7 h$ g
{; N h2 a# L0 c
/* Start the clocks */, }8 X5 l* G4 m3 h2 _1 o7 b: d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 C: e. N w7 h9 R& Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% X3 ?3 F8 Q1 }% AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! P, t8 E. g$ a, ~4 z2 CEDMA3_TRIG_MODE_EVENT);
! @; }: W) H0 d+ G: l$ r+ qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 y$ R/ K% a- y0 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; E& O; p X% x: h8 S# h0 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* A, R8 h% y7 o# |! |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 r& @* w2 U! p- n3 [/ P2 |* A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( s/ D' w, S: S2 C: }. l8 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! |2 x5 r2 o1 S8 K" E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& p2 M( G) \4 |3 c: c* D
}
8 Z3 c9 p* m4 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; z$ t, Y5 x( z! d3 u# a
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