|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 s1 H' I ?% kinput mcasp_ahclkx,: M6 B1 c, }( G1 {1 e9 W; ?/ ~
input mcasp_aclkx,
) w, ?1 _; g7 f0 o$ g4 Y0 y4 [% pinput axr0,
+ O5 a" t; s" q9 @% E9 [9 r: `/ L( ?2 q0 L, l+ m1 s. K1 ~
output mcasp_afsr,
1 c4 s) B: u9 P* b1 ]8 voutput mcasp_ahclkr,* z# d: @3 ^8 X8 K0 G( N
output mcasp_aclkr,# ~* N) P( p2 _
output axr1, t# v2 M5 m" z/ u) u5 ?2 y
assign mcasp_afsr = mcasp_afsx;4 ~4 s% N- w# P) q7 V; i1 V
assign mcasp_aclkr = mcasp_aclkx;' Z7 y6 G5 t$ F1 a& `! O7 \; @
assign mcasp_ahclkr = mcasp_ahclkx;% W( v/ Z! E& m' q7 k2 `
assign axr1 = axr0; 2 ~5 n6 Q: V: W4 r0 `3 Y6 `
4 n$ W' a" F5 S' \' X- i4 n% F! R7 p5 T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 P2 Q. ~0 v4 W5 V! j+ ostatic void McASPI2SConfigure(void)
1 [/ W) r/ v+ R- s" _7 a( G{: U+ B6 i$ H5 I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ }% s" K5 Z% g. X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 w0 P( Y0 V, s" U( bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) R z" Y# T% ]4 v# u% ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ |3 }/ F2 n. l0 }" N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 E- ~6 @0 y: M$ _* hMCASP_RX_MODE_DMA);! Y/ G1 n0 T& Z: I" N8 q, l1 S; [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 E) Z$ g7 v) ]" C( ^9 T$ k b9 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) p; H5 w: |. z) DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 E f7 [& S/ L1 `8 l1 |! o J; A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 p [# p" t$ Y2 n) h/ f0 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* ]5 q) |, S4 [ [2 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# a/ Y+ q- n! i$ z% X" HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' r( n P( C3 c8 }' Z9 ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# @* B4 u. e0 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- k. s5 `5 v# A" C* s; g1 z' V3 E: n0x00, 0xFF); /* configure the clock for transmitter */* i* W4 U6 l9 @/ N) D( {4 K9 x: D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 ]! p+ o9 {8 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 _/ T- E! w. | S. s& M6 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 s# r. S: b* N0x00, 0xFF);
: B" V! O$ F! m4 E2 P: | k/ k9 X( V+ X% t" [! _) ~$ J
/* Enable synchronization of RX and TX sections */ t5 g6 P. E5 T' n+ e9 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 |, |/ F' v6 z5 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! F/ v7 o) q; Q3 N: c2 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 M8 F/ h/ _6 n% k
** Set the serializers, Currently only one serializer is set as
- ]8 o2 m- K& U+ `# ~# C6 @** transmitter and one serializer as receiver.
6 z6 {$ K t8 c- g5 a& {*/
6 L$ z* u8 Q- R2 Z8 ]) _5 }% rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, }8 `" v$ m. m7 c8 A) b" H9 j1 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 }+ a% f; G- g& x** Configure the McASP pins
3 \; [: ~/ B3 _** Input - Frame Sync, Clock and Serializer Rx
- H( r5 t0 m# y+ t) q+ v3 W** Output - Serializer Tx is connected to the input of the codec
+ g4 E: J6 ]6 r [$ t$ y*/
& ^* x; q" f: s: T d8 j5 a( rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! ^' b: r/ F' l' G3 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, T0 R1 N" }% A- _9 l7 t- o( hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 R- }: B! T$ k7 \: T; g| MCASP_PIN_ACLKX
+ N: o$ B% b5 K2 [. r" C# Q+ ~9 l9 z" A| MCASP_PIN_AHCLKX
% Z3 [5 J; }& E* h% d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, @) I6 O* P& D L1 u+ b/ t- m( Q LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: R/ w. _" z9 {2 T5 i| MCASP_TX_CLKFAIL " [* r+ o, r5 }/ K! X) j
| MCASP_TX_SYNCERROR
, o5 a8 W& a5 E# r: ]* x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" x4 C0 Z# g; J! ~; N- _" M| MCASP_RX_CLKFAIL; ^0 Z( m6 _; S+ S) d+ }
| MCASP_RX_SYNCERROR 5 O5 q3 P$ [2 H8 N1 v5 g K" U
| MCASP_RX_OVERRUN);! m9 |* n0 J. ]5 t$ b" {
} static void I2SDataTxRxActivate(void)4 |2 h4 y" Z. a0 G2 @# L
{$ \! ~4 I' m- ]# V
/* Start the clocks */
; R; f4 n9 e, \2 @6 r$ m( aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ \3 Q: a% o& [% V' L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 v/ f6 X8 K* S/ sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 ~/ Z& U) O3 c9 N' M- `7 ~
EDMA3_TRIG_MODE_EVENT);( |6 i' m- g8 |% F( k8 Q- [* H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ ], X/ k1 e1 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 E( t$ t2 o1 v7 \. `) R9 XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* h1 {0 D( x- N5 R! m' C7 o8 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! W0 Y" @, z/ B, v$ g7 f$ f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ F$ w( ^6 h8 _6 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 J# k: E) l1 H, ]" L& T" |% i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) B9 D" Z( i- a% ^% q
} - S' s6 S6 d# X; z8 z# V1 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / K$ c) _# z& D- b0 d
|