MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
5 J+ ]! F: Y- G5 `  M  Ainput mcasp_ahclkx,
; C9 v; z% v8 v: G5 T; Dinput mcasp_aclkx,
input axr0,
: v$ q3 P0 E& ~  z- u& p
output mcasp_afsr,
  t9 q2 t* B1 s" U, z# goutput mcasp_ahclkr,
output mcasp_aclkr,
) l$ L- r4 m' ]' routput axr1,
+ ]' D+ |( M$ g0 x

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
) c% R! |" T* L0 }assign axr1 = axr0;

  i/ T, A. x# M; j; z+ g" a. N7 \
. M* r6 n0 ?0 `6 m& x

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
) x$ b8 R- N  `& z{
5 s" K9 M. {8 W; N% nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 N5 y$ }) T7 BMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; D$ h- v5 q0 X, @" bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 P, y( x( }% o6 U# rMCASP_RX_MODE_DMA);
- k2 P9 e: l0 R  x0 c  zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' E# c# k, Q4 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, v7 T6 h1 `! m% }& OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 ]  _/ x. ~1 J2 @5 S3 e# _# fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) ~9 I. M5 i6 }1 T" g; ~) r( u0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) J, t& _- I  s% @5 j0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
# f' u. E" u' y+ p* sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
6 ]: K! @! r' E+ Q** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
- j4 P0 Q6 s+ b/ s*/
) ]. H( d! q, Y0 }1 J1 B3 F+ V5 ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
* `+ o" O4 |: q) l6 v8 g& q- p** Output - Serializer Tx is connected to the input of the codec
' _4 i( J$ f$ P! T1 V*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 K! |* [" v9 V, V$ AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 ?- m% [! K' o6 p! \* C9 d| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
: m2 \& D/ N# Z  O/ L4 v| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
$ `2 z' N2 y& D. l) U9 z  [4 tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 V" G/ R' d! E+ ^2 i! t| MCASP_TX_CLKFAIL
! k3 k0 _) @- F& b* k! h| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) B; ~9 X+ O% `9 T! C0 J| MCASP_RX_CLKFAIL
3 m, J) C' S5 e5 H# |% u| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
0 T5 T6 G6 @' m# A0 _0 H. w/* Start the clocks */
7 K4 E: z+ ^% s7 S/ D* NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ |) R! e! R8 M, P0 H. q' _EDMA3_TRIG_MODE_EVENT);
* {! x2 |% A: ~0 G5 P( ], ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* T0 q( h1 ^  H! r4 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
7 Z+ d. F2 _2 t' T4 G( K7 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 ^  T- S* D( C5 ?}

7 w; _3 o7 r9 a/ E

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.