我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 _5 S) _1 y* P/ ]: z) rinput mcasp_ahclkx,
" T$ H* Z5 V- T; rinput mcasp_aclkx,& R! G3 B4 X d) z! ]& `5 ~
input axr0,+ x' r; ^; l: x
) D6 X( S; T) c/ C7 ~7 m
output mcasp_afsr,9 H7 |% u. ?5 S+ q: B/ {2 X5 h
output mcasp_ahclkr,
0 F, C+ n/ p7 V$ B+ ooutput mcasp_aclkr,; m; d& ~9 `) P; S0 c
output axr1,' U. h( v6 ~: P
assign mcasp_afsr = mcasp_afsx;
6 V2 x- E4 t& m( n2 S r; _assign mcasp_aclkr = mcasp_aclkx;
- ~& C. v/ C4 e. }" xassign mcasp_ahclkr = mcasp_ahclkx;
+ }* ^6 _; E6 E6 e1 A& d/ S' R8 dassign axr1 = axr0;
E, b% {+ i0 x8 h$ Q9 k; C+ @9 \1 R5 [8 t- v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: d( o4 G8 j/ Q& _& Q# H! b& \static void McASPI2SConfigure(void)
+ S& h# V( x' O4 M{ S. d* ?& }' x/ c# {- A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 N4 z+ I9 c9 Y( s+ WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 }( ~1 Q3 u; p1 y- gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- V" s1 n7 m2 L: m! R" q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 ]9 y0 b$ F8 N/ f t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 i6 d8 ?7 B' oMCASP_RX_MODE_DMA);
4 K. b8 {% s0 W- g0 ^" l$ A9 bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 F: h* Q( P) v2 z/ n" g( |& B1 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 v: _* Y: U9 r; @5 ?' Q, O- V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 }. b. D6 ?. tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 Y4 a3 I/ b( `0 z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / U4 ^; J$ k m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 D$ e) B+ Q$ D+ _+ {1 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ P1 d2 h2 o7 F3 \* w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ r; b: p4 [1 |. DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' _- u% x _4 c( ]. H) R2 t0x00, 0xFF); /* configure the clock for transmitter */ a: y( A: j( y1 e* @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ p8 |; B2 u z o, N. H7 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 c- {$ \5 x/ l6 l* i7 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 u. z) R& Q2 l, V0x00, 0xFF);! j1 d+ J$ \, D( u
- s. o u, p6 l
/* Enable synchronization of RX and TX sections */
' h1 L1 X! r! B* O4 W4 M1 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 J/ ?+ A- n2 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
E, ^7 V- s! J p+ k9 S) a! mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ n; u/ ]& c1 e2 M& j8 h
** Set the serializers, Currently only one serializer is set as q( b. i. X) H1 R* L* J) V
** transmitter and one serializer as receiver.( U" B: {8 L% o8 Y: p% J9 I0 f6 P+ c
*/
# }3 F) @0 @/ v9 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: A s6 N2 y' a7 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 S% r* M5 ?$ k
** Configure the McASP pins . Q% B% Q: G: Q9 _: G
** Input - Frame Sync, Clock and Serializer Rx
& V( \1 n s. w** Output - Serializer Tx is connected to the input of the codec
; L# B. K/ A/ Y6 A0 n*/' y5 W1 W: w S5 l5 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 o0 C7 [3 m" b7 E0 V1 Q/ Z7 M5 S1 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ [" D! x' ~+ I% M; W( ?/ S& PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% B8 `# E5 a G2 a( G$ A
| MCASP_PIN_ACLKX, t! y- m1 V2 X& O( c
| MCASP_PIN_AHCLKX) `- m7 `2 ~3 [% Q) V# i$ d% D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( `* w ]7 H; M9 `" `' p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - b' N! E; h" {- e- `/ @
| MCASP_TX_CLKFAIL
. v- k% e4 i( u* p" f| MCASP_TX_SYNCERROR. l+ o- G5 b3 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . g. J$ v" L$ F2 W8 ^* j' H
| MCASP_RX_CLKFAIL
# \. U- a/ N3 l6 f8 I| MCASP_RX_SYNCERROR
4 o9 y6 R( _2 B& q) T0 Z0 a, ] Z| MCASP_RX_OVERRUN);, Q4 o$ Q/ q; p# C
} static void I2SDataTxRxActivate(void)3 n" f1 |2 I! c2 f
{& ~: D: Q1 V: K$ m0 L
/* Start the clocks */8 k. m& z+ p5 b: X3 H* i Z! a7 d% O/ n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 s" p' s% t3 {; ^0 a, JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 Q) O( x- F( ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 G8 |0 `& o) J2 XEDMA3_TRIG_MODE_EVENT);
" k# T9 N0 W; E! eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& J" G3 Q9 q; r4 }4 C+ aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 ~$ P* L6 H3 B" ~ S) h, G! |% dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 A/ k3 L5 D% ^$ p; T) [; YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 d o( P, K: X) t8 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* {$ K0 y+ i6 M+ j, Y( G) Z8 s4 B, i. B3 F0 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 l+ G0 H! O- c+ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 t- N; i5 H; h5 h
}
3 t9 e5 K2 V( W9 [* P0 B* \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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