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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
s5 [, C! U) F7 g& Ginput mcasp_ahclkx,
# B9 t4 q# K- j, y; t8 |input mcasp_aclkx,2 F: ]# t0 h1 e: q# J: h
input axr0,
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; e$ c2 @1 r; g8 r& ^% d7 Y( ooutput mcasp_afsr,9 ~7 z6 g1 I8 \8 N* ~
output mcasp_ahclkr,
: k& V4 o4 K7 T, Coutput mcasp_aclkr,( S* J. Q0 F9 h- M
output axr1,9 z( z5 I; _4 c' f- F# r
assign mcasp_afsr = mcasp_afsx;# }1 B M N8 T1 u: u) s. K
assign mcasp_aclkr = mcasp_aclkx;
! T, \9 i% ]6 P& Y9 _# U2 @assign mcasp_ahclkr = mcasp_ahclkx;. z9 L+ s, {( O1 l7 S/ z8 P' T5 R
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 {% j" [2 _3 H7 b c
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- M- ]/ `/ F `1 R, B A& A3 w6 @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) E9 I- C( G; X2 k* @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( c# ?/ y9 @& A$ ]/ g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 D$ \ r# S' f. Y4 o" K4 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 U" R m0 K% X& m/ n
MCASP_RX_MODE_DMA);9 X# n+ d) P" R6 r4 T* `9 ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- c" w3 ~; q! E0 E1 }/ ?: }5 dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
q# T, ^% {- T) aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - \# G; ]( f1 `% V8 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, _3 R2 ]# c/ z5 t, r6 ~# q$ xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 Z' d" B4 A3 W* p3 Y" k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ b( v0 w+ E6 D, ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. T0 e% r ~: Z k. RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 a+ T; I$ R/ v2 i; L+ PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 K/ I, R3 y9 X
0x00, 0xFF); /* configure the clock for transmitter */, x. \9 K3 Y2 m8 ?; G- n( O7 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ C3 X( ?5 l% W3 i( FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) V" X" z1 |$ g& d( \6 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. a, Q9 N8 _: o: A3 y
0x00, 0xFF);+ b1 n2 u1 E5 B! K: \* `
$ O8 [% [' C4 H8 P/* Enable synchronization of RX and TX sections */ ) e B& @; h6 W4 q. M9 h: Q" C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ P- O* G; x; u1 j- \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 Z5 L4 q7 {3 C5 e- \8 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: ?$ I% r, w6 b0 {5 Z+ Z x+ c
** Set the serializers, Currently only one serializer is set as9 s7 i' p. b0 s% V4 i
** transmitter and one serializer as receiver.
1 |/ Q C4 U, D5 x# K! I*/
) a. D, j' h/ U1 |3 uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ V7 s& `6 e8 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ K y; s. w4 p& g. w& }* E
** Configure the McASP pins 8 r5 b- q1 J8 s [/ `1 r- n# I
** Input - Frame Sync, Clock and Serializer Rx8 P( x( |; H0 h, s& O& q+ ]
** Output - Serializer Tx is connected to the input of the codec
( T; s% J7 j0 m- F5 M! |/ _*/
! c$ F: s6 d1 d1 m' JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& ^# z4 {& Q5 ]- PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 l2 i/ y+ h9 M3 h3 N+ \* n1 G/ G3 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( x3 }# Q: W+ t" t6 n9 J5 N$ ^| MCASP_PIN_ACLKX e: r# Q# I0 X/ C' I& o- p h
| MCASP_PIN_AHCLKX
) O5 @; A. G3 C2 m- H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; b: m8 t/ Q Q1 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + d) M* d1 t% I+ w# K# D) E
| MCASP_TX_CLKFAIL 6 V* @' a& u, p' E+ g' j0 D m
| MCASP_TX_SYNCERROR3 D, s3 [: {; y1 _! K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! a8 w3 i3 ~! g| MCASP_RX_CLKFAIL1 `' C j7 D( z5 j9 h6 K
| MCASP_RX_SYNCERROR
0 f' Y1 z3 l5 w( M. @9 ^| MCASP_RX_OVERRUN);" ~( M F1 \% b) K6 O, ^& `
} static void I2SDataTxRxActivate(void)/ D) i: Q' `1 Q0 W6 E: I
{
8 D- S5 }0 t. ?/* Start the clocks */
. e+ H* i# q8 A7 p/ D9 o: FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 H" z, J% Z* p6 w) ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" V& b+ f, j/ S% Y% ~0 Y6 E0 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 z( j, {5 }0 E; ^; F7 H
EDMA3_TRIG_MODE_EVENT);
1 v6 f7 L) O. [1 O7 F- V# qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 J* a5 G9 o. j JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! `+ Z, J6 {! j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! k( i, I) y6 K p. W$ ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) a+ n; k; Z# w1 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# C' n$ H* U6 t7 P% y* _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 i; `( ~% O. R8 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 `) ^1 {0 L) G+ s}
' c3 H$ k4 w, ^3 l- r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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