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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& C' \% H; U% u7 Q
input mcasp_ahclkx, w9 T9 y9 M( {2 v5 ?
input mcasp_aclkx," f! x. I1 p( B
input axr0,
7 O" V" e+ ]! J6 |* ]
( a) V4 K: m* y+ goutput mcasp_afsr,
/ n z& P% j; u+ N+ eoutput mcasp_ahclkr,
" o y# M$ {+ c9 f! M0 ~. z* `output mcasp_aclkr,7 t3 O0 L n6 w0 X
output axr1,6 }% P6 S( ]7 p8 S) n
assign mcasp_afsr = mcasp_afsx;
7 `% B- X$ A! }* |2 ^assign mcasp_aclkr = mcasp_aclkx;
+ i B8 L1 h8 ] I9 R; ^assign mcasp_ahclkr = mcasp_ahclkx;+ r W! S: l l7 l9 Z% }2 `
assign axr1 = axr0;
- Q& H0 p0 N2 B% `" ^: X7 M4 z
$ }' T$ ?. S, X$ g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% C0 \9 |) k& U9 W% i* O6 gstatic void McASPI2SConfigure(void)
u6 }- J) i6 R* l6 H7 i3 D{1 e$ j8 @) p6 h3 o1 {5 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ l# l! I' Y5 c c& AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 s9 S/ t: p# D. ]% L7 d5 b; IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& q# H, y4 A4 L, x$ X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, f! O1 E1 ~9 w+ _% ^# {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) z8 ^5 \8 k/ m, T7 Z z$ aMCASP_RX_MODE_DMA);: \% X- ]* V' V( x8 w) Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# p0 P \) Y1 F8 E6 U8 AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 Z4 W- S% Q' g/ ^5 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, |: Y& H- ?% d- n6 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 T g1 P' l p0 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% V M. x7 w# Y! N8 NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ x. ]2 C' O5 y1 I0 W+ YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! y9 y% P1 x3 T2 d' m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 n# L/ K8 C6 Z5 BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- p9 X. A8 W+ R2 q B! W0x00, 0xFF); /* configure the clock for transmitter */4 j+ z# ]0 G2 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 s9 w% E- S) _; U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . v. I( n: i- m! J$ |6 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! R, `( A+ R! t+ Y9 l. M0x00, 0xFF);
( L7 ]8 M1 O! l+ N' y+ \# x0 i' R5 l9 c6 a; F' p
/* Enable synchronization of RX and TX sections */
1 ]+ }% ^# u1 [% Q. K/ aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( ~1 Y" N- B& n& e8 g' A- MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 ?9 |7 X: ~6 o! g0 A% }" t" E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 i# w5 I( B2 i& r
** Set the serializers, Currently only one serializer is set as- |8 Z8 ]) u& L# M* `$ E K9 s0 O( B( d
** transmitter and one serializer as receiver.
- t1 z$ F4 ^ B w, Q ^1 v5 R: L- ~; r* a*/
3 d& _; d8 j9 ?% V+ W" e9 }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# A9 C. S9 ]( h0 C: f2 ^7 t7 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** L X2 R, o& v4 G/ G$ h% g
** Configure the McASP pins 1 T3 Q7 B h7 a. s- K; a" s4 w
** Input - Frame Sync, Clock and Serializer Rx; ]/ Y5 |$ Y) r# q8 p: o" j
** Output - Serializer Tx is connected to the input of the codec - N* n* i/ s: x% B8 t0 Z
*/+ x, p4 L% ?& G+ T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 Y; h1 z. {1 S6 {: Y' u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( F0 ^# h: n; ^* X; y7 C! }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& ]; W# Z& O3 `0 d; @| MCASP_PIN_ACLKX
) j- j; }! ~6 `| MCASP_PIN_AHCLKX# M7 Y3 Q) b9 y1 V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 {+ x+ y( P% `3 @7 {* BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. a( y! F2 M$ Z" B/ X| MCASP_TX_CLKFAIL + ]' Z) k( \7 V- p$ S/ X$ Z
| MCASP_TX_SYNCERROR0 Z& o5 b% T3 \3 m1 h; u( M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 W& @7 c5 k/ m9 ~& @
| MCASP_RX_CLKFAIL
, z4 [- b. ?& ` l9 Q7 d| MCASP_RX_SYNCERROR # u, x% a) H/ Q+ {' B- w' |2 N
| MCASP_RX_OVERRUN);
. @5 p0 a% {) h0 ~# g7 ]} static void I2SDataTxRxActivate(void)
' G5 E! k( P Z/ N$ ^{
: c8 K! r* f) u) u& F( P/* Start the clocks */6 J( D. ?! A; \5 ~1 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 P: q0 `/ m/ N: q3 _1 s P# L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* a3 m6 O, |" J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! D0 _4 f a* Q/ B1 o$ ?, ^EDMA3_TRIG_MODE_EVENT);
/ K2 n' S; ^* h& CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ B% u! F0 I: W% O/ w4 c9 h* H7 {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- M* q& L- e5 i7 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 b6 e- W- H& k9 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 j" ~% e+ K+ i9 a* o, J6 o( G( o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 C6 O% {$ t+ N8 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 B, C7 F a! b; s: ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 u, e' j& `) @. L h9 S/ _}
4 h( A/ {# F. A: X( e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % B6 M' S5 t* j9 b5 [1 p
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