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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' s3 b* b! g* r xinput mcasp_ahclkx,% S6 V7 ?1 D# Y5 r: u
input mcasp_aclkx,+ i7 Q) n' T- [
input axr0,; S; w0 _& K6 M0 c' z& I% r
: }, e; f/ o- X( routput mcasp_afsr,
' a& G9 |/ l- K( o, w8 ^output mcasp_ahclkr,
9 f, b1 w0 q' S" y( Z" I5 T+ k4 ?output mcasp_aclkr,
. z) g% S1 }- b+ m5 S4 goutput axr1,+ z0 P6 t% L2 W( t# b
assign mcasp_afsr = mcasp_afsx;* F+ V+ @5 W3 A; M8 }3 u
assign mcasp_aclkr = mcasp_aclkx;( Y V& v) t; C# j0 C, J9 F
assign mcasp_ahclkr = mcasp_ahclkx;
; }4 r: M W- Z5 _" q0 x8 U: cassign axr1 = axr0;
1 r( B, f" g9 Y D R9 m8 m/ |# W, P, P1 V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% @5 \1 z8 ^/ f/ M! C: k# vstatic void McASPI2SConfigure(void)9 O' `/ r6 }5 E7 p* b* e7 s
{- e2 a2 c* S9 t' m: G3 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- ^) [4 h8 [4 C _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
c4 n" V) j2 y( `: x kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ h: W0 {4 b8 x7 J3 N! JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 j" j" ?! W- W2 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 J& K( n. U) b& A- t& _
MCASP_RX_MODE_DMA);
0 Z. \' B) ^. }1 e& _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 E$ p7 ^ }7 s7 |" V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' Z7 m9 y8 |9 |% q: i8 b" r9 s+ A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) p4 Y, h. Q+ b* c2 c0 `& NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' o- j3 D* w+ R# a, ~: XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 l3 t) r( T% h4 [$ J- DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' d, {! `5 `5 h- r5 xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 p4 O; s" ?3 L, b; o4 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 q3 `: G3 k1 Z' g3 r# ~* dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( ]; a; V( b; M4 g" r% r
0x00, 0xFF); /* configure the clock for transmitter */ Q. J$ {; T7 _" A: N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 W$ A8 [0 n; M W1 Z6 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 K" Z5 J, g/ o. T" d2 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% G/ P, {: `3 E8 _# z
0x00, 0xFF);
5 x9 h; z/ u$ p: M( m
' l7 l) J% k5 c+ q$ L/ P3 w: ?) C/* Enable synchronization of RX and TX sections */ 1 r0 K4 e7 B, g: A$ E g* b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 d& I! `6 ~( P0 I/ h: R, B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' J. }1 ]2 c3 I4 R0 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& v/ n1 P7 S, u* Y+ \6 G' V% W X1 j** Set the serializers, Currently only one serializer is set as, S1 C: `; U1 m! R- ^, X
** transmitter and one serializer as receiver.
8 @: d" C% M& ?( m" d0 r6 L. Z2 k*/
5 ~# j9 Z: t0 v5 Q' bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: l4 j/ Q4 O# P2 P, OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: l7 [/ B2 ~. a2 o5 p( \
** Configure the McASP pins
5 K0 t, i0 M# d8 ?** Input - Frame Sync, Clock and Serializer Rx5 v9 ^6 T$ m. O9 K
** Output - Serializer Tx is connected to the input of the codec 4 J+ X8 n& _( `2 `
*/
- F( ?9 ], o7 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ T$ J0 Q" a* ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 _0 V$ F! m$ k& X' d! Q: ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' `& c+ v3 }& ~& K( p4 c3 Z| MCASP_PIN_ACLKX
1 P* p. `' U A5 @; D% J0 ^: N( y| MCASP_PIN_AHCLKX
$ Z0 }# M, v& E' |1 i8 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) f2 t3 d- ?! n7 U* B( UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 p2 F+ s" q/ a. c
| MCASP_TX_CLKFAIL
0 V* Y, i) G/ K6 M& Q t/ h6 }| MCASP_TX_SYNCERROR; E( U5 G, c& Y9 I& m2 F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, m/ o, `" p/ T) c. p/ D8 y| MCASP_RX_CLKFAIL
. K) e4 N. |1 s" E+ e, j| MCASP_RX_SYNCERROR ) a( }+ J" y4 @# w7 I5 H
| MCASP_RX_OVERRUN);
7 w4 w) V6 Q) ~! j$ I5 A# L) \' V4 B- u} static void I2SDataTxRxActivate(void)
8 ?: ?# j% N0 o! |{
$ n! h% Q; Y. L/ \- G/ X& e" g/* Start the clocks */2 N8 Q V! _7 t2 l% p0 t& I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 J( y' Y5 \1 h8 hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ o& N, x! L; Q b6 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 X" |8 z% f; n9 b
EDMA3_TRIG_MODE_EVENT);; h) c/ s% W9 B" Y6 W1 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 \+ b! t, j+ i' X/ E4 u+ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# @6 [* o# c& H8 m r6 A' T% q$ xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. Q# {' O; A0 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 P* I+ \* v; F7 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" f1 u! z- E) b6 A! s, P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# a' u1 [8 M( i/ h4 _2 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ H2 w& C% z: t4 F' j F& R
}
+ |0 R# D5 c# M$ ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : m/ M8 J- a2 z/ ]. z( O* g- H$ {
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