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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 _4 l+ t# O4 L( Minput mcasp_ahclkx,: H5 g; g8 {4 ^4 {! }" b4 a; M
input mcasp_aclkx,2 m7 W* R$ b, ?. [
input axr0,
5 e2 D8 j) ?$ j$ o/ d7 [: i1 ?. `1 ^) i5 y* q |# b; e
output mcasp_afsr,
$ Q; s; n7 N/ i) [output mcasp_ahclkr,
( ?% M6 S, \9 o# E7 L% X6 A3 Xoutput mcasp_aclkr,
7 [- m6 C7 M! l( l# d5 doutput axr1,
- o, C2 K0 ^0 s+ M2 C7 \9 M) E+ v0 q assign mcasp_afsr = mcasp_afsx;
! i' j3 Q% p# I$ V! s. u: Qassign mcasp_aclkr = mcasp_aclkx;6 P2 T; ?* H/ _3 R
assign mcasp_ahclkr = mcasp_ahclkx;' x3 B5 _( j- f& R% W, S) a
assign axr1 = axr0; 5 W4 w8 [5 O6 Z4 c, V
( r6 Y9 c9 e6 v3 ~. F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & \1 `2 C8 Y) F
static void McASPI2SConfigure(void)
; J! L+ h+ `5 O: Q' f- I. [" n7 Y{
2 }" O3 o" S) L; Q' ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% R s; y. t' R- j) A+ oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 l+ d7 _* B% n: W! IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& ~& k6 }) I% @ h$ S3 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 g# Y) i d4 w( W$ I& M6 c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 W2 t1 I5 D f& V$ J) Q
MCASP_RX_MODE_DMA);
5 H6 _( C; Z U JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! G$ \; A: O9 P$ G7 P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ G5 s" J8 \; o! Z( v! U& r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ j9 p) t0 p! V# R+ P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ W4 Y1 D# b6 D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ e, a5 \. {; v& a8 a; _0 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. c# f8 ~1 m% X8 {0 Q# eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. V! ?- }1 Q; L) u" d2 S" @) D- T" M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ S) [ T! U7 O! t4 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" {. N; R m5 ^+ l, W3 _. p0x00, 0xFF); /* configure the clock for transmitter */. s: l! Q! g, R" i! `: A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! P6 E% d- Q" b; n) n0 l. m( k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - ^' I* K' Y, E1 y+ Q; R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! a ^5 t3 i2 l/ a- d2 S% L0x00, 0xFF);; e, {2 [" ]2 L$ G. C5 s
7 f5 P$ T1 ?, A, }
/* Enable synchronization of RX and TX sections */ , l& C$ q l+ y5 \8 O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ h8 _; @1 [* z1 u/ IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' X% E# i/ ^1 H. G2 M6 ?. s# K2 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& Y$ f" z9 g# H. S) e3 R, j
** Set the serializers, Currently only one serializer is set as) Q( o6 T: w/ j) `# \7 ]
** transmitter and one serializer as receiver.* A" y9 h! C& |' ~6 a
*/" y; | D$ s6 Q( R, t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 K3 j. O- D/ A" I5 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. t0 p# T6 S7 l5 }. A% J
** Configure the McASP pins 6 J5 p' a. J8 ~* `& {. b- ]
** Input - Frame Sync, Clock and Serializer Rx
; T) @; E1 o/ i# p( B4 b8 _+ i** Output - Serializer Tx is connected to the input of the codec
' j+ e1 n) d1 V% v& F0 J7 K6 X6 l*/: d. i) w5 b: U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 N5 l8 y* n* _: H, X: t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 l, X, q5 ^/ U. {+ Z* B# K' mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ ?) C6 A( d+ U1 L& a. L; o* ]
| MCASP_PIN_ACLKX9 T% }" b4 z" i1 @( q: q* d
| MCASP_PIN_AHCLKX
2 @( y. T! Y2 l' m U% m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( l- M+ e) ~' q* a# B. l& e3 e! t- xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 p% c4 Q9 ~$ \) p9 }: ~' B| MCASP_TX_CLKFAIL
9 g9 f3 V& |# Q, c! S* s4 w* E6 {# w| MCASP_TX_SYNCERROR
/ Z' j# W1 T- |# J) t$ [ A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 d7 {, b1 n- s. M3 a| MCASP_RX_CLKFAIL
0 n+ o( g4 w+ S# k7 B! s: g| MCASP_RX_SYNCERROR
8 S1 c8 i) W7 e| MCASP_RX_OVERRUN);
! y6 w: r: K1 ~1 R6 r# l6 }} static void I2SDataTxRxActivate(void)
2 o" M: n! w5 I' M7 ]{5 J" S: e* S% G% V" H2 {" e4 C
/* Start the clocks */
8 J; O: Q1 a. y3 p( L1 z% FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 V- X4 u2 w2 d1 @; r) ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" e/ v. P2 @4 K* ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- ^3 F7 {0 f& p$ k7 \# `5 P- @
EDMA3_TRIG_MODE_EVENT);
9 }* a' D3 ]2 ?( D3 P+ nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 x9 {) v# q" P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
i1 M. r% j( [2 M* kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% K+ v% p4 F! x; n% _. f2 W# e0 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' |( g0 ~+ f& A, `/ T7 q* B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 ?4 y# Y# [6 Q# MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. o3 B) T2 _5 o4 O/ S% n" R. A- [9 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 m) p z% }1 s O/ z% b}
3 k# c2 k, q; ?2 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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