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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 C7 p7 Q l6 y( U+ O
input mcasp_ahclkx," v N/ v" W% P2 M! D
input mcasp_aclkx,) t, f2 v; ^" l- L7 F: B" F
input axr0,: |3 ~0 e5 ~- \
. ]4 n7 j, g6 d" {: c4 n
output mcasp_afsr, Y6 s) o( G: l$ b, E
output mcasp_ahclkr,
* h/ [! t7 d% C. ^ w8 voutput mcasp_aclkr,/ W, j+ x2 B% ?8 g# L1 v
output axr1,
8 t! m C( X8 L" ` assign mcasp_afsr = mcasp_afsx;8 {9 H( t- o) ]& W
assign mcasp_aclkr = mcasp_aclkx;
- [5 E0 M2 l1 M/ Wassign mcasp_ahclkr = mcasp_ahclkx;
" r4 S* d# W: @( F" q+ D' r" tassign axr1 = axr0;
% ?: T& J# x2 ^7 M' i9 U7 K
9 S$ u: v1 k( l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , l7 O: a/ L/ E8 A. J
static void McASPI2SConfigure(void)" h7 \; d5 ]# O5 e8 f! h4 o
{9 z: ?; i$ m- c- G, t3 [. ]' X# i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) p( B7 ~" Z" t. J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" X, x' N# i( [/ f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' a. {2 G" H4 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 l) U) W# g8 D8 l: Q! S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 w# o$ X. d% ?3 E+ F
MCASP_RX_MODE_DMA);
2 V3 x6 J; E! GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ v5 j/ B) k* u$ S: I% z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) E9 u* c8 M3 b9 G4 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! g3 m& ~( R' y3 @+ D* U( y' O# Y0 _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- z; @) r2 r- p4 u$ F$ j, XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, b' g3 M. M5 p/ @2 j0 J U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 j) N4 e7 P; AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 W5 W1 C% U2 q' p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! G+ B" Z: n- HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! q8 ?7 f0 X) I7 C# ?0 m. X% K
0x00, 0xFF); /* configure the clock for transmitter */
. [/ {9 C0 N% rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! g7 s3 r* B: t0 ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# E2 E( p! S' v2 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 k- g6 K, N6 D% j( I7 W
0x00, 0xFF);6 H* B, Q6 }! t& F' t8 Z8 W4 P
2 O$ s, [! s/ \; [# L
/* Enable synchronization of RX and TX sections */ 4 y5 a; `% q9 i6 g0 Z) V& l( |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! i4 q. F: o6 q O/ @0 a- BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& h0 k# x8 ]1 f7 I" FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; s G! v6 o- e" f* Z
** Set the serializers, Currently only one serializer is set as k0 m( a- i7 r& i' a2 l
** transmitter and one serializer as receiver.
0 S9 L+ W. O# u7 f& g {& r2 N*/( |6 M* Y& K) U0 T1 w* t9 _/ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( X+ Y h; e( M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 w- D- p- H9 h* U8 U4 q4 x0 w
** Configure the McASP pins
5 D" G+ Y2 i. S! V8 Z6 `3 e** Input - Frame Sync, Clock and Serializer Rx
3 L6 h. a2 c9 D) h** Output - Serializer Tx is connected to the input of the codec 8 z! p9 n' o) C; `
*/
7 F. U1 l* K8 n' g8 l7 W" iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 Z$ R; O2 q5 w5 w5 U8 v6 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ i+ P/ x1 P* N; p, F& z+ t( R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX k% {6 ~ n8 ]+ L
| MCASP_PIN_ACLKX
/ ~. i- N6 H1 v+ Z| MCASP_PIN_AHCLKX+ i8 l+ q$ F$ K' M+ Z. m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 I2 o0 N3 |) D0 z5 k5 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( \& q* p4 Y: _1 X) V+ L
| MCASP_TX_CLKFAIL ) Q" E; b" B5 e( F l
| MCASP_TX_SYNCERROR" l& g! t" p' n/ p$ g* G* x* S4 o+ e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - r# v$ v$ n8 o& t. Z' e/ ?( E
| MCASP_RX_CLKFAIL
6 I1 \, E, w$ U| MCASP_RX_SYNCERROR 3 W! a6 l, z4 q5 h/ g. ^
| MCASP_RX_OVERRUN);( m4 a9 S% v n( J8 b! m
} static void I2SDataTxRxActivate(void)
/ {% a' [$ ^. c, J! y( m5 p{: h2 z+ m. z3 [9 z
/* Start the clocks */
8 U* H( I9 ?; t" H1 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ ]* [/ U/ {3 Z0 D/ F7 l$ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ M. N; n, x) |; d. W) z% G& z% B4 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' e1 a8 F' ?: ~9 h4 d4 Z, e
EDMA3_TRIG_MODE_EVENT);* g3 E+ R- o3 G$ ~: E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - H' } v+ F( F! F \1 E7 F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 L, w- g# [: o) o/ OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# z; K& H0 F! R1 q1 _7 `9 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 E/ ?. ]9 h# jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 C) H4 u! j+ j B) y* uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: X( t; ^/ V) S9 W. e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 T( S* q. c! l/ ]- C! h} 1 \" V( H' N, U5 h. I" N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 i8 U K J( r! S
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