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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 L6 j9 S; w, l( }; p( Q0 C
input mcasp_ahclkx,
: _/ a ^; H* `* |2 uinput mcasp_aclkx,
2 x+ `8 M" t4 Rinput axr0,( F$ y: w5 _ M1 ?
; T( z# _% t6 e L7 youtput mcasp_afsr,
* m9 O5 l0 h9 Y/ z& ?" |output mcasp_ahclkr, A2 Z- ^0 y& A: W7 s
output mcasp_aclkr,
; _! ~2 b/ A, ^( p$ ]* \2 |4 Houtput axr1,
* I3 @1 ?% y* U assign mcasp_afsr = mcasp_afsx;
4 \8 b% e! t( ~- v5 U9 j' ]assign mcasp_aclkr = mcasp_aclkx;
, G; Q$ e& ^1 L2 j# iassign mcasp_ahclkr = mcasp_ahclkx;
7 R& `9 I: z" `) t( Z& f. passign axr1 = axr0;
8 F5 L" H% V# \" d
! p& R8 v4 d- Z ~5 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( |" f. o- J$ Y4 V4 Vstatic void McASPI2SConfigure(void)
, k* }4 g1 Z7 [6 E6 V: H1 d{) }, K1 i* ?8 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 g: Z& R( Q* Y+ G: pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 ^8 F+ G; u7 I0 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- r" `# S# ^5 V! V/ s7 s1 k2 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) x% a, W+ B. A; @. g9 M: ^$ `/ w! g: `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 P, M y& \( r- [/ i; z' qMCASP_RX_MODE_DMA);+ A4 h! ^- y0 v' C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 z" w4 I- F% S8 z2 N6 E* UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ^5 P, F8 d' m& ^' Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) N" p1 \1 z0 C4 ~+ v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 ~) s( I$ m% a7 K) F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 H& f2 G4 |: I$ @5 A5 v% H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) w# y% S% K% _" GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. p4 }% A2 _7 Y. F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! J7 I& g+ N; s; eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 k6 F4 f) B0 A! S R0x00, 0xFF); /* configure the clock for transmitter */
9 _& L' j3 W, @4 y/ q% P* l1 @! JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- k" o, |+ `4 Z1 X2 M. s0 h: o* GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 y6 s/ a: u8 k* U [$ }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; M; _& F* S" M& }7 {0x00, 0xFF);
% E' Q2 `% B2 {9 x/ h% n9 v( F! `) s. Z& o4 \# r' L9 v& r/ _
/* Enable synchronization of RX and TX sections */
# u8 {+ X8 F% x1 H' JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& ^2 s9 T: A5 J8 ~1 } T: KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 c# G# N6 d5 J- G0 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ ?( G8 d4 k) O) Z4 N
** Set the serializers, Currently only one serializer is set as1 j7 ~0 T x2 g4 i# k& h! H6 x
** transmitter and one serializer as receiver.# o& Q9 r' V6 Z' G: k
*/
+ `4 X* g) V+ S; \) j- s* B2 _# M3 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ R$ |) k8 |5 O) o" R* L7 I* p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 W: N4 F' T# b* O** Configure the McASP pins - _( _( ?" t m8 S1 n, ^
** Input - Frame Sync, Clock and Serializer Rx
# d. S0 x% t" ?$ @2 j; N7 w** Output - Serializer Tx is connected to the input of the codec 0 X+ t4 ^; U; x- ~
*/
" e, o. h6 ]7 A% q* {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 f# \+ h6 R; y( _* x2 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; O( x. X6 p( BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. R; s9 ?: t/ e8 t6 f2 U
| MCASP_PIN_ACLKX
- S8 e+ t. d/ |# E& ?- R| MCASP_PIN_AHCLKX$ y$ O2 c* }4 \# D' p" ? e% L9 z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' H* T5 _# r/ ~% B& y6 H H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR X& @! U" _0 Q
| MCASP_TX_CLKFAIL
4 Y9 F! _+ e3 W| MCASP_TX_SYNCERROR
; T8 X7 }* H7 f9 V; o3 F9 e. @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: ]1 S- g: k& c# J1 f| MCASP_RX_CLKFAIL
% u6 y: q5 w9 O| MCASP_RX_SYNCERROR
# E" I) f S0 c. w4 i| MCASP_RX_OVERRUN);
$ @. a6 d( a5 h9 w7 h" e4 Y} static void I2SDataTxRxActivate(void). V3 Q9 S2 H# T0 `. i2 j
{' s) K8 W% \# E, i2 u
/* Start the clocks */
1 p4 I1 ^9 `/ ^, o& h0 c& iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 k% F1 j/ B& w: H7 x& D0 H- IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ z: O5 j; m7 e8 O- d$ ^8 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 F, J' t1 c' g+ e! r$ v+ uEDMA3_TRIG_MODE_EVENT);
+ i# A# [* z4 c7 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ^: M B0 [5 W1 U yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) f2 e0 T: u5 R1 b ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ e q" L& G& pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 C6 O0 d& I4 O( mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: h* ?1 u; v9 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, H. I2 W3 T# b4 S' r0 ]0 o, t1 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# a X* G. r; N3 [% X} ( S+ F/ u6 {7 y0 E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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