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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* A, {' k" Y( k( X minput mcasp_ahclkx,
" c& M$ e% T6 {8 r2 Y* n9 }9 yinput mcasp_aclkx,9 v; g, f; g% Z& W" E" r0 D1 u3 w
input axr0,
% q: i" p$ [ m/ X4 M1 d
' L# q5 [$ z# H/ |# k/ poutput mcasp_afsr,
" X- K4 W6 X* o% woutput mcasp_ahclkr,
+ }. z. W6 t5 v8 H( q& |$ S6 ]) v- ^$ Poutput mcasp_aclkr,& p9 q7 z7 ~( `+ e+ u
output axr1,
# d9 o( O4 R+ G assign mcasp_afsr = mcasp_afsx;! T' h1 e* g, W+ E+ h' o
assign mcasp_aclkr = mcasp_aclkx;1 h; U4 h9 k1 l8 `+ D7 q, o
assign mcasp_ahclkr = mcasp_ahclkx;
5 z; H+ P3 C* h N" O/ r: \. lassign axr1 = axr0; ) G D$ d+ _$ S* d# x ?+ _
0 O! l/ I/ x1 T& I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' t7 k% x; O# z3 E% u# Tstatic void McASPI2SConfigure(void)
9 @1 h! ^8 y, x8 P/ B, |* A% ^{
: e; z! x( `. Y& t O* h9 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 h5 a: y2 g. J& v+ p; JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: f# N2 u1 f3 l. Y; J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; h' S+ m- Q+ C; @# I- S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# I4 ?9 G( A4 P: ^# v& k9 oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! C! Y0 w+ `4 N, n7 _MCASP_RX_MODE_DMA);9 o# K' o0 r3 V p% w/ o ^' @) r8 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) Y y' t8 Y/ f/ C- _. |8 i) ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 N6 ^$ l9 P, LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 M, t: J0 T j4 U0 b9 DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, j& w" O5 }) G+ F- K* |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: I. N! b3 ?$ R. gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# V3 W8 q4 a- s2 ] |; C; P! o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! z0 R7 S. ?8 a6 M/ Z3 V8 _2 X2 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 L1 r/ e- E& K2 P/ G z6 \" m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( h# ~9 _% W: R: N
0x00, 0xFF); /* configure the clock for transmitter */! b5 u5 _; |: _& A1 B; w( F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) T! S& U7 w C( UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 N, c4 G) l; ~0 c" i6 \% T. O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& m- ^) @% X: w: _: k& n* n
0x00, 0xFF);. D/ M1 e3 Y4 G1 ~; \: i1 E" n' Y
% s, v: `' N; N2 A2 \4 [/* Enable synchronization of RX and TX sections */
# T3 g6 I$ X& n; j: \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( j6 N8 _& S8 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 T* w5 P" n+ `- {3 i+ qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 {& }) M- [ D) P4 |( D2 q' _$ G- U9 M
** Set the serializers, Currently only one serializer is set as7 ^7 y# u6 \# l% ~/ G! q* C. C- ]5 e
** transmitter and one serializer as receiver.1 g# X) D7 g2 u0 C6 `( p
*/, z' z& A/ X$ l0 G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 K* G8 r4 u! ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ?; B; I. w* @; l( d" |; o$ _
** Configure the McASP pins
; P: j# w- [2 s$ m$ B** Input - Frame Sync, Clock and Serializer Rx
9 f5 L0 j& _. T" t, s7 e** Output - Serializer Tx is connected to the input of the codec
: _9 C0 U b" d2 T*/" S- [9 R2 v g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 x5 V+ W" L# @8 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) m4 Q1 ]6 x& x! |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; h- U# y4 e% P7 Z; P5 I0 p
| MCASP_PIN_ACLKX# \" C9 b9 J) F% n" V
| MCASP_PIN_AHCLKX
1 \& f2 s9 w# T% x. W' y% A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ n# u& s" H* zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 X( q+ D8 m6 f: ?$ H7 [| MCASP_TX_CLKFAIL
' m% P# M# j8 z2 \| MCASP_TX_SYNCERROR
0 e5 ]% l( V( ]5 G5 D. e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( q2 v8 [' b. w! ^& ~" w
| MCASP_RX_CLKFAIL4 N6 C0 ~9 {* c
| MCASP_RX_SYNCERROR $ |5 M6 O. J6 B
| MCASP_RX_OVERRUN);
1 R6 @# Y- T' S4 b" t} static void I2SDataTxRxActivate(void), E4 v) F! E+ D
{) ?* H5 W! \! v3 ~; h. T
/* Start the clocks */
+ o8 n% t+ f2 q# T; I( RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ |& F2 F/ c: g9 i4 y" v, V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; g$ Z% B* l% z4 H* [; ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 J* c% K) V2 XEDMA3_TRIG_MODE_EVENT);* p ?' y% p9 U; T% \# L O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * \4 v0 L- m0 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 a$ I( R! _9 k3 ]& U8 k4 Y* Z8 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); i P+ r; ]5 f8 c W% v) h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' q! }& K" X$ W) g1 }2 b) F: E" q* X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! q, M+ k6 O* ~; h$ J' ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ @2 r/ O8 \, R! F mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) ~4 X! k1 X) @* u}
7 f8 G) U$ b3 A5 J: \ n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; |$ P5 r. |$ D+ J+ ~( n* C+ q |