MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
) T$ u# K/ Y# ^, }3 |2 V" _input axr0,
2 U; C# q/ [9 c
output mcasp_afsr,
$ d6 a! q  u7 w( Goutput mcasp_ahclkr,
# L: S; X# q' `- i5 Goutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
3 I; O2 H/ J3 a% v) c* B; A( oassign mcasp_aclkr = mcasp_aclkx;
6 F2 C, i$ `$ N  d$ j' Oassign mcasp_ahclkr = mcasp_ahclkx;
+ F# z. h0 p! U* `" @. K0 Fassign axr1 = axr0;

, s/ D* [( F/ J, L8 l( b0 S6 a
: w% U. j4 \5 \+ c. }( f

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

: I3 ^. D9 H; V- |/ P2 \3 S& X* l7 \

static void McASPI2SConfigure(void)
{
4 S2 s: E( {& h, ]& MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- y+ z5 N7 M5 vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 C$ ~# b+ j" O" EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) _1 P9 g1 Z0 x1 F1 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% K9 h. Y( Z' ~. d) D9 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 z! [+ k( T6 P* ]0 V! y% N% U: JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* A/ t% u* |- N0x00, 0xFF);

/* configure the clock for transmitter */
6 \% I8 {, B% Z1 Y( ]2 r. pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
  N0 u7 K5 l+ G! W6 ^
* \' R( h& ^3 z& V5 A/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
# H, Q4 \1 Q, R0 d/ s- I3 J* x* oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
% f9 b/ t2 q; V& A*/
, R! c/ d  X' p/ w) g2 s/ O" q( b  M% dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 N' o. m) F, i9 A; w# m. CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
$ z6 v+ E- j. j! g** Input - Frame Sync, Clock and Serializer Rx
$ H) b3 S1 ~/ K, J( O** Output - Serializer Tx is connected to the input of the codec
: B% y# C, n9 ~- _, j5 S*/
+ A+ C. ?! a# @9 I8 \+ `  E4 \4 a2 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ z. Q' w/ c; |' wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. H; J) ]9 R% B$ Y& N| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
) x/ _5 [$ _) q2 i& M: f! X; || MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& g1 M6 R5 k' T/ }+ V1 a| MCASP_TX_CLKFAIL
$ N1 u% J2 r8 R# k2 z5 Y| MCASP_TX_SYNCERROR
% g: U1 P  c0 e' x. J/ a| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
# a  l" {6 }$ a5 n. u. d7 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& E+ Y) o: F. t) Q, z3 C  w2 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: ]$ Z0 r- o% h. U/ Q; u* ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) M. Q! k) g; S1 _0 S( H. B: AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
- M3 L) ?7 D5 w, s$ {0 f* O' Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
$ r3 t! \; m/ ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.