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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 I, p( m" H9 F' f# Z: {input mcasp_ahclkx,
. b2 z$ k- S0 \" g2 Yinput mcasp_aclkx,
- Y# A* j7 A9 U9 n2 q( D# {input axr0,' h) @8 ]% ~* W h8 x
6 ~0 U( p$ ~5 T" b6 _5 Poutput mcasp_afsr,
6 X# ?) b8 ]# `; `output mcasp_ahclkr,
% p7 e$ p, l% W6 houtput mcasp_aclkr,- e/ T; C1 r7 [2 H! e+ h/ Z3 j: l
output axr1,# r- h F6 }1 [$ D+ g* _
assign mcasp_afsr = mcasp_afsx;. [+ C0 O7 }/ {1 t' \
assign mcasp_aclkr = mcasp_aclkx;3 f: N/ ?. g6 W% O; Z T+ {
assign mcasp_ahclkr = mcasp_ahclkx;$ P6 n* @, R% Z: P
assign axr1 = axr0;
% N. Y' {8 G; N; ]; s7 M4 `7 y1 a' q D @8 [. o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 x( s$ r- H2 _: d+ i1 \6 @static void McASPI2SConfigure(void): H. b3 x# b/ e& {3 J6 R+ I" o3 G
{
8 b3 b. u3 \# `; V4 b: g2 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# B) i1 Y! [! ^1 H. o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* }3 G! L# K# N! R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! l3 W* M6 P5 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 w5 E6 [$ m) t. L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Z# @; U2 E q3 |* ^4 ?MCASP_RX_MODE_DMA);
+ ?( F1 B1 e& kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 `) C4 ]# [6 ~+ h' N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 C7 W/ w& d& J# ]0 J7 ^0 v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 k9 I8 X% T1 h/ \: X% Y: b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 Q7 T* c: q$ a- X0 o6 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 h9 E; u- V) U; x% \2 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 k6 ]: z4 E2 k% hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 q" {# I) B* [, g5 O) H1 C3 ?5 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 G9 M( n* W7 b# E2 U2 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, I" O- G- j& o3 ^$ H
0x00, 0xFF); /* configure the clock for transmitter */+ o. j4 U3 C% X$ ~4 [/ k# K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 i) r; M0 J* y6 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, z+ Z2 Z$ T- h. n qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# J8 w6 L6 f+ F/ r+ s' g0x00, 0xFF);
/ O+ G N) T' J" G. N& @
2 S+ P Q* o# J3 ^/* Enable synchronization of RX and TX sections */ : y& r6 l6 }) m5 a. B; g: R2 e) D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% n3 S7 J0 |# @9 n9 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ r; ^0 F( Y" p) i" U) fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; V$ S$ ~; |+ u: G5 I, ?
** Set the serializers, Currently only one serializer is set as
6 K4 z- H; I1 c0 p+ ~' _" s% U* c; e** transmitter and one serializer as receiver.- @ L2 i e& [+ B% C' x; T$ a- K2 Q, p
*/
& k% i, Y7 k CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& M* g ?# Y7 G9 k% E$ e @9 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 Z+ p' U% }0 ?0 K+ g( ^** Configure the McASP pins & z7 N V' g3 _; ~+ P0 k
** Input - Frame Sync, Clock and Serializer Rx
" H0 \4 k/ W& V& s X** Output - Serializer Tx is connected to the input of the codec I' `& P- q% Q& s: C
*/1 d2 w5 P, g$ X5 \/ [% g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 }7 Q, P N/ K# s. q4 M" |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" k% l% O& [9 S1 ? _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( z" ]0 E+ @. s3 x: {6 P| MCASP_PIN_ACLKX; G; w: O& ~6 R4 f1 ]
| MCASP_PIN_AHCLKX
8 D2 o2 b2 w7 M/ {$ E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) @: l+ N4 Z5 g1 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 K- ` b- _$ k. j+ Q# v- ?
| MCASP_TX_CLKFAIL 3 C) X* L# Y5 ]2 l- s/ L4 `
| MCASP_TX_SYNCERROR. \4 \5 k8 C$ e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. P# p6 r6 E" B3 {6 f( y! B| MCASP_RX_CLKFAIL
8 H- F$ ^6 O7 C| MCASP_RX_SYNCERROR
+ G8 A+ ~/ y1 M& [, u# o| MCASP_RX_OVERRUN);) Q+ j7 G9 |% b. A8 B: i* t
} static void I2SDataTxRxActivate(void)1 G, [2 P) V1 E* u
{
, @- \, ~% i: Q1 e5 d/* Start the clocks */
1 [- c: z4 H- P: D; q5 ?: JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' q( p6 Y5 r9 E( ^$ F% E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, M& Y. e8 V+ u. ^+ G$ P/ M4 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 J0 B9 v/ g5 Y! h7 t2 [, m& k
EDMA3_TRIG_MODE_EVENT);& k% M w! E9 q& B* ?& D' x1 s" W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ |2 }. U' w' E) E* s& ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 n- c# S& c6 I5 F% ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# {8 d5 e- L7 I" C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; n5 R9 M+ F0 Z+ h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ T: e/ e; }1 F0 s# G% zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; N6 h2 [) z8 |/ F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ Q8 N/ ~6 l' O0 Q/ O, z
} % j: V' l5 ^. c: A+ s7 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) R9 X7 {( O& u# |* x- \$ r
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