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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ^% N1 ]: T! ~. n4 C; I8 ^input mcasp_ahclkx,- U) }5 i% ]4 A
input mcasp_aclkx,8 T1 g% t' d: x) g7 k
input axr0,
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! f& Z6 e; ~& d" |/ f- H9 Noutput mcasp_afsr,- n, p' M/ r* f- D# X) |
output mcasp_ahclkr,
$ |9 l# s/ P: g$ A; t( soutput mcasp_aclkr,+ V: {, d7 [5 [3 o& z x" R: B
output axr1,7 [8 ?6 |7 F" P) n
assign mcasp_afsr = mcasp_afsx; ?& ~& }1 Y7 T$ }
assign mcasp_aclkr = mcasp_aclkx;
4 M# f* Q/ `: i s1 Sassign mcasp_ahclkr = mcasp_ahclkx;
% h, C- s; J$ F2 r/ Aassign axr1 = axr0; * y# P) g. d+ X7 F; J# u
8 I. Y$ S( n, @! K' }' v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / g; B; ]1 m* E4 p3 }
static void McASPI2SConfigure(void)
& X2 `! G9 P9 I" H0 G4 H{
5 N) r6 [9 C9 F" v4 ^2 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( X T3 {, K% t4 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 A; a9 K' k2 H6 c/ _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 M# W; d2 f1 k( U$ {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* T) B8 E5 Z- G1 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' F" X7 z' X; a7 G0 Q
MCASP_RX_MODE_DMA);
+ N) ~5 p7 C! }/ ~% rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' g+ X1 y2 J; |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 X& o- \! C O9 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 e) E# ]- Y3 L# f' L+ T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% y9 h* a( G& Z* G4 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& h* R4 \: Q0 y+ ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# |; `+ k, J+ P) b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 D6 e. L; w, [9 m% e( yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 J1 e8 ~ z! @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% N7 [* w; n2 g+ d) q0x00, 0xFF); /* configure the clock for transmitter */1 I1 {, o' M, y, ]: \% I+ r. {3 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 E# t$ G4 X1 {4 a( M9 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : b& E5 D- S+ D# `; p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ E1 Z( k; O) f7 N7 S/ l
0x00, 0xFF);
7 W9 t2 a5 Y6 \/ w$ V7 Q
1 D5 N: W# h5 u" z/* Enable synchronization of RX and TX sections */ ( b$ Q4 x4 S3 _3 N9 Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ |1 ?+ L9 z3 H! X- ?" R( ?+ y- DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); P. G+ j7 t! E( l( S7 z: n2 d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' |8 o/ C2 w5 Q/ S U2 W** Set the serializers, Currently only one serializer is set as
1 [% Z% x3 p5 R% Q. Q** transmitter and one serializer as receiver.
4 [$ W' o* J- _* }2 z; s. z0 \3 F, f*/3 m7 Z3 s8 B$ q5 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- A0 Q' Z% E+ q$ D, d7 i0 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" z% f! p" U8 {4 c% U** Configure the McASP pins
# {1 k- i6 C# o; `- a/ x** Input - Frame Sync, Clock and Serializer Rx
( y1 I' [! Y+ b+ a% R; c9 u7 S** Output - Serializer Tx is connected to the input of the codec
4 `" j$ Y8 X0 W' X' R) o*/
. k/ @2 D" r9 d' d' _% _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 _& i! P& b7 ?) x, d0 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' |2 M% @. ?4 x5 V: H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! y8 `$ @1 @. r, {8 R; d
| MCASP_PIN_ACLKX' n8 a( Y( K7 W3 g1 p/ m& O
| MCASP_PIN_AHCLKX" T! d( r( {* E7 N. E# K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; N7 G0 B. s# n6 s; e/ _. h. @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 V/ y4 c' j2 o# x6 Q9 t| MCASP_TX_CLKFAIL ' x" ~2 r5 _' K- p6 f. y
| MCASP_TX_SYNCERROR
9 s: q7 S, [$ B7 C/ A0 |) T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! v, q$ Q- i4 I: c8 l- k* D| MCASP_RX_CLKFAIL/ v2 Y5 ]% d' ~6 o
| MCASP_RX_SYNCERROR 1 N8 z: o; I8 c Z0 X
| MCASP_RX_OVERRUN);. W) w0 Q5 b n- Q, ~0 N+ m
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */4 q6 y. M# J! e' f1 r) `+ A6 j/ J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 X$ @- @9 R7 v2 p8 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 @- D, M5 }% l9 L8 v% B yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 ^0 K* E) D% K2 P! C! D: X; ?& u
EDMA3_TRIG_MODE_EVENT);
- a6 y( B" [+ @, ]( R- OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( N) d1 l+ X e( Y1 y) m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& G0 `+ n( |$ \/ x6 ^9 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) O4 w8 Q3 G4 k6 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 V, S; d7 x: w+ ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
W6 u/ w& _7 g) }8 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 Q6 u" Q) Z, ] D& H. R/ l5 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* d/ E# {3 u5 e
}
5 `1 {* B& O7 l& c+ u, s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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