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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ I; h" O1 `7 r2 O. N
input mcasp_ahclkx,$ P" O, o S3 @) ]; V
input mcasp_aclkx,) _/ f4 `: r% r6 `. m' X3 v
input axr0,
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output mcasp_afsr,' t+ D/ b3 d$ Z" k" w
output mcasp_ahclkr,5 D; M; C6 T9 _' P5 k, N
output mcasp_aclkr,7 U: ^% v6 j0 C9 q6 J
output axr1,' c$ s2 i0 x1 Z% i/ e( d" q3 a
assign mcasp_afsr = mcasp_afsx;
% }2 b O& Y6 P3 [6 W+ Massign mcasp_aclkr = mcasp_aclkx;
$ t( v$ a3 @6 x3 J1 F" Rassign mcasp_ahclkr = mcasp_ahclkx;
* z: R7 i# o& v0 massign axr1 = axr0; * l% o) L" ^% w
: r: u# ~! m1 D: f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# S+ F4 s+ j3 U5 w+ h0 x8 qstatic void McASPI2SConfigure(void)
2 v8 X9 P. A# C6 H9 V! n; _{
5 v$ X. G# E) g9 r6 |9 w- ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);) d5 N) q0 o0 D6 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 c. e; J/ D# [( Q2 \, m% X% YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' }% r( N( f( c" i6 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; x6 E; p# v9 l% BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( d0 j+ O; E+ d( u8 v
MCASP_RX_MODE_DMA);
- W9 ^ |0 r7 W5 L! LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ c& ^2 u1 p5 x8 X3 n% W; q$ i! s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ N' c( r7 h. V M! j7 V$ V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 R& r9 L# p7 V: g* @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% k; d- y# c+ J3 \$ @ X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! x9 x. u7 C5 N. d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 _$ D; ~0 j; M% o. I" mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 b2 f: s" T8 G( @4 E; {, v# \) pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 M0 ~4 X" C- \ _& L( e) U0 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% \5 @6 U8 n+ f) b5 G0x00, 0xFF); /* configure the clock for transmitter */( p1 `6 N0 S& ^4 z" E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 ]4 \4 _' }, H5 ` C. u$ ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! h7 [2 ^& X7 o% K! J2 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 u B3 B1 p6 R# I4 ?; M
0x00, 0xFF);
7 E* o+ ^, g+ B- W, Y0 O. Y3 T! t- }! L, o7 x2 ]0 l; Q! y6 T5 w
/* Enable synchronization of RX and TX sections */
! W/ d1 p% u3 h/ w8 x- k3 j, T9 S: wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" f! ]+ b7 I& Y3 j1 D( M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) o2 G# m/ X# ]' j' ]) R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) p1 I6 T" C. Y6 [% j2 Z
** Set the serializers, Currently only one serializer is set as2 w) @& N3 @& m) o
** transmitter and one serializer as receiver.8 p! s: u" V4 b9 x, I" s
*/
! @: }! {/ n) E) k& oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" R5 |' A9 U& B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ I+ b5 I" q R
** Configure the McASP pins ' w1 a4 [0 ]( _# }; [1 O
** Input - Frame Sync, Clock and Serializer Rx
8 ~, ~- U- ?$ Z/ E% X** Output - Serializer Tx is connected to the input of the codec 7 [. {3 S; s4 l2 j7 l! s; F' P' z' ~8 v
*/
1 m2 s0 X$ K6 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 y' W9 H4 R3 D1 z$ X+ tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); r. `6 D6 }4 f Y% m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' X2 \8 r, G7 u* R3 J' u/ W1 _| MCASP_PIN_ACLKX
4 G. t: K2 _ E| MCASP_PIN_AHCLKX
U, d$ ]" t" \# s* Y6 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' N4 \, a* c6 t9 ~+ a4 d9 ^) ^6 W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 r/ Y3 p9 u% O, p9 k! q' x
| MCASP_TX_CLKFAIL $ @+ X* c1 X+ A0 g8 |
| MCASP_TX_SYNCERROR
( f3 I- L+ [7 q/ z, {% d/ r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' }& P1 ~; Z3 x3 V, f9 {| MCASP_RX_CLKFAIL
' f# o _1 Z, y5 i| MCASP_RX_SYNCERROR * P0 C. b7 j; D7 `" W2 C" Y( Q, M
| MCASP_RX_OVERRUN);
* _( @+ C6 C; p3 |9 x} static void I2SDataTxRxActivate(void)8 h4 c& ?' W% }
{
8 \( e5 L: Y( G' o" u! k/* Start the clocks */
/ u9 y( m7 ?( N$ |- RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ Q6 P6 }, }2 Z7 Y: [7 K5 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) |$ f' b' F+ _; C% _. YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' o( @1 ?8 ]* GEDMA3_TRIG_MODE_EVENT);
8 [( v4 [& V z% @8 ?3 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 @- _7 G0 M) G% n U% m) e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' ~- x/ t0 l. TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; O7 F, P, j2 P ~& o2 C4 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ x z# w) Y- ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 q0 @4 N5 r6 K- b! O) \9 y# W& Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ h H% b+ h! |2 K( P- F2 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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