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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) g4 {3 @5 [ e- W
input mcasp_ahclkx,
( J% J: x* j1 y R; O' A% ainput mcasp_aclkx,
. N2 d( n8 |/ [! ainput axr0,! Q' m3 ~3 s) ^# Y
9 A4 G( @" ~/ b! @
output mcasp_afsr,6 ?; j% h( e1 z& g9 M/ A
output mcasp_ahclkr,
w s* q9 [ N; H3 }output mcasp_aclkr,* r" o' `( ]: a, e
output axr1,3 F/ \4 ^" } G3 P1 I/ m6 n8 K, Q
assign mcasp_afsr = mcasp_afsx;
* ]9 M3 @2 I$ s) @) Aassign mcasp_aclkr = mcasp_aclkx;2 C" J8 E$ ^: L7 Z* e) |+ x! |$ Q
assign mcasp_ahclkr = mcasp_ahclkx;
- |, g8 {' \1 s- F! eassign axr1 = axr0; " N' M6 b: s* R' h2 H
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 q# Z0 o9 X2 e) p/ E8 Jstatic void McASPI2SConfigure(void)
7 t7 m5 Z1 p6 e( }7 F{
2 z( W# ?4 a: G8 H, q' kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" O# k( t6 }' ^; w2 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 l& U3 O% P g0 q* x8 c8 c$ X3 U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) [9 }( E* Z% o( k8 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" ^4 X7 P: ]' d0 Y, f( W3 N; X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; Q0 v$ N9 M- R5 O0 T2 A QMCASP_RX_MODE_DMA);, Q$ B1 c: j7 q, g H j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 J3 J$ T$ _0 O: `4 hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 [" W8 T; w9 y0 h3 _+ S7 Q- H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 u! G$ \* q+ R1 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; p0 w g; u8 e; WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' g$ [3 N& c+ R( f0 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; @! G- I0 h+ h" y( v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 ~# o) Q! ]: m; W0 H! JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * d9 B( q# N4 S+ s2 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 f6 [7 M* p9 e' ]( D7 O
0x00, 0xFF); /* configure the clock for transmitter */
4 ~: G$ s: V# X( M% p" _- IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. `/ Q7 x0 r2 e b8 p1 _9 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * u( \8 }2 n: U' x% ?9 |$ V2 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 M7 U; h7 o2 a' v0x00, 0xFF);' w i5 |) i* M* c: U9 v% ^
( P* R$ k; U! t y/* Enable synchronization of RX and TX sections */
' ?7 ~( a2 h- D: K: RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
x& N( J" p: n: Q5 f7 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 s- D' F6 z# n/ Z0 M3 L0 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 L- ^6 O* c# V$ y$ K" m
** Set the serializers, Currently only one serializer is set as |- K' s1 f. A3 A4 A% @
** transmitter and one serializer as receiver.
9 B( A' b' z' s# i2 z9 N" s# I*/
( D8 U5 H2 o+ a8 q, X, H9 h6 \2 R* G, }& cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, M1 q; O$ ?, |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* ?8 d! `& D- v% q- |6 c** Configure the McASP pins
1 n( b8 G3 w0 }/ C** Input - Frame Sync, Clock and Serializer Rx* p& V7 M/ x3 f
** Output - Serializer Tx is connected to the input of the codec 3 x( Q' N) i9 Z6 _% Y. E
*/3 ^' ?: z& N0 \8 k1 N+ n( N8 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' ]* [ A$ U1 B- _* O- d9 {/ |9 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; t4 K: d$ E& ] U. A0 f2 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) ]5 ~! {. T, b| MCASP_PIN_ACLKX
% p9 U5 z, q+ Q0 F| MCASP_PIN_AHCLKX$ p9 |$ B1 T4 V/ I+ h/ o8 B% p. K! U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 h7 T( D" N& u* U$ E9 g1 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 r% j5 }" j0 V; P3 v7 q/ {4 I
| MCASP_TX_CLKFAIL - F" R* b! ~! c' h
| MCASP_TX_SYNCERROR# K( T* s0 u- N5 \ e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 `! g0 W. X; |" `$ E1 _. h$ s
| MCASP_RX_CLKFAIL' X5 C: e/ [# K( ], m- q V, o+ F
| MCASP_RX_SYNCERROR
1 k: g! K! {" r$ e| MCASP_RX_OVERRUN);' ?! g ?5 B7 ~; ^
} static void I2SDataTxRxActivate(void)
! r w( X9 q- C{
' p8 ~# B; ~( }" y* m# \$ q/* Start the clocks */
* M4 P5 o+ f2 K' J# T, mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- P, \, `% }4 z) K7 TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 A5 O. k& J% C p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' U. u: C- b" ?" G
EDMA3_TRIG_MODE_EVENT);
1 L1 N5 V: l. B( J, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) T* t7 K7 ?& b, W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% ~; w7 @/ I' ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ z2 R7 r( M8 V; c* Y2 r/ \$ t* E4 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 F2 D6 x3 s" ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 @- N' Q# m) V, O% w9 T2 `8 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# }8 C) \8 k* q+ l' @. v4 c7 P" dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" H0 ]+ W4 Q% v6 b: M# }/ I
}
4 z# E1 v( @! Q, j2 Q1 j" {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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