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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( X1 ^8 k( R5 S f! ^' S! ^
input mcasp_ahclkx,2 \ M. O2 K' U3 @
input mcasp_aclkx,
* u, k& ?: a& n; ginput axr0,. B6 n7 r$ h" [
1 p8 P& F/ l& b; X! l. a
output mcasp_afsr,' {2 D: E1 g# M6 g% e8 v) [
output mcasp_ahclkr,0 `% b! V- t3 w* V( e$ R
output mcasp_aclkr,4 t; o" @' E* a
output axr1,
+ c! r" K5 q R' O( e assign mcasp_afsr = mcasp_afsx;
' ^% [* r8 p7 _) e2 N# K& T* zassign mcasp_aclkr = mcasp_aclkx;8 l) p. [: D7 C% f, w5 K
assign mcasp_ahclkr = mcasp_ahclkx;
: C9 [( ]* ~. V/ Qassign axr1 = axr0; % S" A+ b. r2 a& C) p" ^1 B4 w* i0 c
! l0 [( j* f: Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 Z E7 Q# i" \9 c1 M# o, ]4 m
static void McASPI2SConfigure(void)8 H z) N/ }+ ^+ {' C
{
8 E$ ?6 g' p& I& p- K, n2 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 W6 B% ]+ M$ y' A* d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// }! u2 ]* X5 g$ q( C* F6 r" b9 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) h" b! ^$ m6 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( L. Y4 A: a0 a1 s+ w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," Z; a4 j6 f0 w
MCASP_RX_MODE_DMA);" w( k& R) T& o8 K3 l a) @% t* \5 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( V6 A# _# k. B3 j5 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ Q% u. K6 n4 L" |5 W n8 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! G7 o" r# m8 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 _/ N) @, `9 q3 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * t& z! j8 w% z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 y1 X: r; w" i6 Z: `; Q3 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, b7 v: t5 |1 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) o8 d4 e, C) {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 {- K7 q- u8 n7 h0 \+ j
0x00, 0xFF); /* configure the clock for transmitter */$ r" q) {6 V; `" b' s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 o8 ]5 A8 w* B" V0 A. G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Q! U) k8 |2 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 n! e8 Z( M6 D) |1 Q0x00, 0xFF);1 X0 Z+ ]& K F. h8 |& S) t
! Y S: R4 Y. J
/* Enable synchronization of RX and TX sections */ 5 G& m; N& V3 l [. K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 M) f8 |% _1 l }6 q3 y4 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ i9 c% m% g- _* ]+ }' Y n& Q" L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! F4 {- E% `7 H3 C: o C" k. w
** Set the serializers, Currently only one serializer is set as+ h% z( v+ I* s$ @1 F" o2 k' i* U
** transmitter and one serializer as receiver.8 J1 |) T" k! W
*/3 Q4 s* `. a) H w( V+ A1 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 D( c' H {" K* m/ v8 bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: ~: Q4 C7 r" w; u- s0 y0 x/ J** Configure the McASP pins
4 T4 z/ Q3 b+ R: F U. Z. [: ~** Input - Frame Sync, Clock and Serializer Rx
; y7 m& l; v# [9 z0 v U" n** Output - Serializer Tx is connected to the input of the codec
% \5 W) h {: @2 K*/
I. R* X$ Q0 [) o5 {' \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) [5 y ]. r; i9 k$ J& R& e" n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* C' L: b9 c. f9 W8 q' f+ XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 x" v- y/ Z% }3 j3 m0 D' \0 N! G
| MCASP_PIN_ACLKX9 Z! M+ ^% V4 y& g0 }% e
| MCASP_PIN_AHCLKX
( F( h+ ?% G; z. a3 x) G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ A9 K8 S7 w7 C' I) [$ i& u4 P; R; q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 {/ T; u$ _2 h2 B* V) t8 E
| MCASP_TX_CLKFAIL 5 ]+ G2 C. G6 n( [
| MCASP_TX_SYNCERROR
% j1 l' D2 E' ?. e5 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 c8 A6 R8 l% Y* ~- F' O
| MCASP_RX_CLKFAIL, [. N1 z ^4 S5 ]$ h6 O
| MCASP_RX_SYNCERROR
- R2 [3 u2 ?" g" F' u| MCASP_RX_OVERRUN);* G$ W6 h/ {- p8 i0 r& l
} static void I2SDataTxRxActivate(void)
& O( ]8 q: p P; a' ^% H3 E{
7 Z' i* ~# `# k: M+ {& f/* Start the clocks */
7 N3 t9 L- @4 W, E) l& {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 {9 m+ l' a/ w0 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- u, P) Y. |* {9 L4 \1 v! H8 m. lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( }$ p) F. p7 c& yEDMA3_TRIG_MODE_EVENT);
4 ^* e& g4 F$ Y5 p5 u6 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # v2 U/ E1 q8 V3 H. C/ C* l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ S2 _4 c8 Y% m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 O; J% @; Q0 R% u1 s9 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. F: W( Z# y& ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
], j, n6 s" q* P$ BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' J0 C) u0 K$ M) G4 e' F: c0 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 u: V6 y% C" j} : {* v1 @" }( B' F7 ]4 ~, ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # g E+ R3 n, J7 o; f0 V" J) M
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