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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, E2 Q' A; P, I! |input mcasp_ahclkx,
X* |3 t8 k# J: F1 H6 ]input mcasp_aclkx,
( M R1 z' w/ W6 m& [, |input axr0,3 I7 ~7 C Y2 E+ r$ I8 b
; c0 I! @6 _, c* }" poutput mcasp_afsr,0 B/ D! t5 h+ g3 ] Q3 z
output mcasp_ahclkr,: [. }, w! X' |# x* n% ]4 g3 l
output mcasp_aclkr,
6 }4 V# W; y/ L4 Routput axr1,8 {+ |2 e9 ]4 B6 q2 r& @5 t
assign mcasp_afsr = mcasp_afsx;
0 d! |/ E ~' G* x4 vassign mcasp_aclkr = mcasp_aclkx;
) o- @, C$ l# A' U0 s( I! [assign mcasp_ahclkr = mcasp_ahclkx;
, ~7 G0 Y1 B& s0 ^' ~$ q! Y+ |7 yassign axr1 = axr0;
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& k7 H- j& @, |* m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * T/ Y7 b( V! g& m: F4 g7 @% {( ]/ w
static void McASPI2SConfigure(void)
! s2 k0 q7 e' b{" F& b- m1 z6 ?. y# c* q5 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 B' I4 |1 B" e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 ?0 ~& y0 K- J) f8 x" xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 u9 B) o4 T0 T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, k) h* A8 V2 P! l0 Y9 K; a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; m# N O: Q3 p% o
MCASP_RX_MODE_DMA);
* M; z. Y2 a' w2 q; ^0 [- c8 O2 k" bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; r; O, S& }4 F/ O, cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" q9 o3 a& g/ n& j& E* ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 L4 }% H3 h/ J, V. ]8 A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); W% {; \. I! D$ M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & ]9 V; v+ \$ {$ Z* s# l! l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: W5 m5 K0 ]( M! xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: H* O% [1 s4 ]# F2 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' V, I; d! E; d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ F3 V+ a" t1 Y& ?9 ]0x00, 0xFF); /* configure the clock for transmitter */
! D) H8 M0 M {( S" n/ ~& EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 h$ l& i4 Z8 d4 P6 ]" l" d. O5 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); v! V, P9 ~1 f3 r8 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' L( x& N7 f3 f5 Q. K; h
0x00, 0xFF);
, ~" f" o1 r9 n8 J! V: B3 s
- x" a/ O0 p' u6 {* H5 w I/* Enable synchronization of RX and TX sections */
l8 i# Q8 N6 U. z& T1 c [) UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- H8 P/ e* p: F" O9 AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" P* H1 w9 t I. i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 |2 O5 B( M Z
** Set the serializers, Currently only one serializer is set as5 X* i; p! [/ G( S4 _% ^6 n
** transmitter and one serializer as receiver.$ H* w% m# A$ I0 @3 U; j
*/+ Z4 z% H# S# U" y o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 l3 c0 l7 q I( u/ t. v$ V# \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ D9 V& n* z1 G$ q7 k
** Configure the McASP pins
t$ L# L A# L% M! y: ^ k& c** Input - Frame Sync, Clock and Serializer Rx
0 t/ Y1 z8 K; D, P4 r** Output - Serializer Tx is connected to the input of the codec
6 c7 v' t4 z! Z*/
3 Q/ r5 e7 [4 | R' U+ yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 {" K* ~. v4 ` l7 \1 g# M) {: {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 D* C) D; M: y& y" `' K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" O* Q- C1 k4 P7 t1 x
| MCASP_PIN_ACLKX' J3 D/ I& _5 m* h3 O. r0 _6 _1 d
| MCASP_PIN_AHCLKX
8 e# t% Z* c% H; [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 k, z# b; K+ J0 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 ~7 p8 L( ]" e$ f( s| MCASP_TX_CLKFAIL
1 n& m* S @8 }" _| MCASP_TX_SYNCERROR
/ o2 y3 F) ?7 O) d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - D' o6 p7 Y5 M
| MCASP_RX_CLKFAIL
' B1 L' e: J: g& |( H| MCASP_RX_SYNCERROR 2 D. x: P0 }& x7 @/ F
| MCASP_RX_OVERRUN);
% r& G0 a" C$ g% P. X. Z} static void I2SDataTxRxActivate(void)
4 u, J1 c" K( g r6 u$ q{; i0 T/ l" M6 R1 t
/* Start the clocks */" x) [3 X4 X4 Z+ |# T) A) I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; m- n- ~ ]: Y7 r% W5 D1 \: HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& i8 B* e; _" L) X( z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 e2 t3 i# M& R9 d& H, o9 G) A
EDMA3_TRIG_MODE_EVENT);6 F2 p5 S, u4 [5 k8 ^* E' S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! d7 f f2 X9 ~5 S* l' d$ Z5 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# q3 R- E+ U' k8 m. D/ O2 _3 Y% S" p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! S: ?; T# z M+ f$ {$ r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- J4 y6 m7 T5 F1 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 W1 e0 _7 S' N; cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 T0 @) r: M( f7 AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 M9 j2 S d$ b7 X( }* W8 {} $ }! n: ?1 t1 \# V. F/ c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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