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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& m, T9 x% B4 N) B5 {3 ~+ w) {
input mcasp_ahclkx,+ }- w# f) [/ X) ?" N
input mcasp_aclkx,
/ _4 K d- O/ a: m; f9 Vinput axr0,
/ t7 Q: p5 Y( M2 T4 z9 X( g( A1 {4 P. g- z7 b
output mcasp_afsr,
/ f" m: F! H o- x7 routput mcasp_ahclkr,8 k7 E* @7 v+ N/ m, O2 B
output mcasp_aclkr,' D, N$ l; O7 z
output axr1,
) z$ J- i. o$ {0 s assign mcasp_afsr = mcasp_afsx;
* N7 ]- b3 x6 j0 f/ g0 p( G' @assign mcasp_aclkr = mcasp_aclkx;
n* T$ P$ U( Y0 Aassign mcasp_ahclkr = mcasp_ahclkx;
3 t: Q2 Y/ }" Uassign axr1 = axr0; ( M- x6 J1 |. W6 ~0 b5 X
* a( I% @; j# e9 P# a) Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, l/ R$ h. h$ M# dstatic void McASPI2SConfigure(void)7 w3 o) P4 B! o+ _+ a V6 d
{; K! n. W2 Q& K/ \ t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 m, Q" X/ K2 `" y( d! oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, V1 p3 @* H" w0 q& p3 ^/ I" v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 C/ J- C7 m) m/ Y# O. I: d# q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 M: w0 j5 h! L& l& ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- y r, s* t( e& FMCASP_RX_MODE_DMA);
9 ~3 e( N9 D* ]9 `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! r" {# z6 z2 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- v1 g* O" u7 v3 x/ _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 V% U3 y R$ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 i. N; {* T' p2 o: F& rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 G5 H ~0 S: h+ P9 M, u/ ?: T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# J+ ?7 V! C. |: w( Q6 V [. eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 d9 e! e0 m. y% U& a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 R: {" b/ _+ y) U4 UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 F! U! y) n/ c. n. E& P0x00, 0xFF); /* configure the clock for transmitter */
- T# C" x; r" w C$ F3 |8 ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) C, y5 b6 s- h" [& c' Z# k* s8 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " e7 o2 L, @8 Z: {1 S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( C0 I% R, p0 j3 h- T3 E, P; j# v- k
0x00, 0xFF);
. P9 z# M; r6 t- F# x. y, N& T7 r& ?% g$ ~/ U, z& s- r7 B
/* Enable synchronization of RX and TX sections */ ) `+ g# A- ]3 f6 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& `, g2 Q2 P/ Z n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 D( t% m% z& j+ }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; Y( J, w- [. @0 {) n# D6 p6 l
** Set the serializers, Currently only one serializer is set as6 v# ]' C" |7 a i
** transmitter and one serializer as receiver.. ?! Q: o! f/ |! K+ H3 N$ O: Z
*/- o6 }; K, e" N$ F9 D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 S) B5 g* {; v. k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 [" O+ \: U' H; u) m7 U8 R
** Configure the McASP pins
' H, V* t4 O N9 |$ o0 G** Input - Frame Sync, Clock and Serializer Rx% k; ^, ]! H9 p+ A& p+ Y% t* I
** Output - Serializer Tx is connected to the input of the codec
* M& b& ~1 t3 V! k*/& F* X- i0 t6 q# S- ~% C- f7 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' ?4 r# q+ v' D* x" N" c" }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* F$ T! R- X9 g, QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 i C7 S! Q- f1 p
| MCASP_PIN_ACLKX1 m) B+ T6 j1 T) w& W
| MCASP_PIN_AHCLKX
% f. }2 e& I d* r% T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 N2 w6 _- n$ T% {! mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # O' u4 F' P. E
| MCASP_TX_CLKFAIL : |, m0 ]) c$ O" x* f
| MCASP_TX_SYNCERROR
2 P; T# W; o5 W* ~ b( ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 H* k/ U$ ^/ X$ w9 v2 E
| MCASP_RX_CLKFAIL
7 N' {+ V) o; N0 ~$ ~1 u& |/ T| MCASP_RX_SYNCERROR
0 T* c: h8 t; U0 a$ i3 k8 W" w| MCASP_RX_OVERRUN);) Y2 k! d9 v4 m, G# d% J
} static void I2SDataTxRxActivate(void)
6 F9 D( X6 O6 b. }, Y: g{: U. `% o7 X0 C" \( F; |
/* Start the clocks */
. v3 {; K+ @8 g4 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, @2 h) o) B, c6 gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// z* t" W; t; J" b. X. o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 i1 x+ @. E6 ?' C3 B' R5 T
EDMA3_TRIG_MODE_EVENT);5 C; @' \( O5 u- R$ x h- J1 W! b/ B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
h% o' l/ n# f% hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 q9 P. T' b& w$ U# n eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 l7 D0 {! F# c# D0 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
G, a* J# j" C5 L' `6 r1 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) a7 Q4 d! m4 k6 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: p+ J: t' m8 B4 T' V. kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& S5 b& e0 y4 S; x}
) F2 V$ _5 W$ i" Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' ?( I _$ H* g7 N# w
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