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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 G/ |: o! y# K1 G$ {
input mcasp_ahclkx,% S1 X2 U/ o" |: y1 k7 N, C" b9 ^2 K
input mcasp_aclkx,
/ ?5 ]& d5 d8 X0 zinput axr0,& o. Z% ^7 e+ l& x* e
( ]) R, J0 w" w/ K7 z" j; W$ I( Youtput mcasp_afsr,
5 y* c7 d' F" ~ Noutput mcasp_ahclkr,% o2 l" u" t6 Q. {! Y# a
output mcasp_aclkr,
- y7 b. ]0 C$ Q" P9 i$ youtput axr1,% j, y1 s2 ~0 a8 q9 q" d) r
assign mcasp_afsr = mcasp_afsx;
/ g4 ~: [7 S, ]- {1 Massign mcasp_aclkr = mcasp_aclkx;
! l0 h. q" h0 Yassign mcasp_ahclkr = mcasp_ahclkx;
; A( L7 v' d6 g0 Wassign axr1 = axr0; 3 T% v1 Q9 H6 d" P3 W
0 ]( E3 C- ~3 x H& ^" A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! w; K0 M# J: d8 y3 y- \9 ostatic void McASPI2SConfigure(void)- R7 C, c: Q) w( @1 `
{
5 R( j! C1 D. S3 S2 E, RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& u) w. ?4 j8 H4 K% E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. H; d$ n) t! R/ n: H3 I& `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# k* u; k6 Q0 j' ?% l: J9 YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) d+ L8 u. v9 Q. ^6 K- x+ _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 T1 B/ S" i; XMCASP_RX_MODE_DMA);
6 R7 U2 k: M$ v2 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; k- G+ x# `& kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. B' s) [# z5 v3 b: ~" H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' z2 b- E u3 v. p4 a( OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" _" O7 ]* w' ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 f, W9 M% \& x: C# xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 x7 q2 D3 j! Q2 kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' X5 p! d/ J0 t3 q" ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 p3 Z. P' P5 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# e7 d. c- ^6 U6 L; ?2 @0x00, 0xFF); /* configure the clock for transmitter */) ?( x3 h7 B# N3 X4 h# G& ^4 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ d8 Y# \' e) \- t5 u. h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 Q# |' {" Z9 ~* P3 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. a( N2 ~* x7 Q5 R
0x00, 0xFF);( K: V. [1 e8 B* \
^3 n" h* W8 W' Y/* Enable synchronization of RX and TX sections */ 1 i: ~0 l# f9 I. k7 p* F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# V$ Q- X/ g- q- G3 a, v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; A1 z# m0 Q9 m/ Z# C8 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 u1 v" C' q7 b; v9 B
** Set the serializers, Currently only one serializer is set as
: i! X3 c7 F* v; L( ~4 b$ _** transmitter and one serializer as receiver.
: O& ~4 r& A% d/ s- `*/; J/ F9 U* ?; ?' U0 R( K, `/ K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 F6 c9 w9 h, B6 L; X- M. lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 S6 e& b+ ? L. N** Configure the McASP pins
2 D9 Q8 A( B" d2 U7 ^3 `- E) ]** Input - Frame Sync, Clock and Serializer Rx
4 | f5 S. @7 Q0 Z, s** Output - Serializer Tx is connected to the input of the codec
) n( Q3 H6 l9 P# t- e6 _: J*/
5 G8 w3 f: a" yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. L+ [6 X, i Y! W4 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. e, V( e- s6 e8 T# |2 k6 _1 Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ `$ f, m1 |, h7 I3 y3 [| MCASP_PIN_ACLKX% u6 p( j" ?6 P, m% Z) }
| MCASP_PIN_AHCLKX2 l6 V, q% R8 F, j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! r5 ?$ g2 \/ d& ]0 A% I" g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; i" q, \. z& J ?3 L( W| MCASP_TX_CLKFAIL / o2 A$ ~* L) l" l N4 }' r
| MCASP_TX_SYNCERROR
" f: m: t$ R+ ^5 l) X! C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& V: @9 F# C5 _1 T: B| MCASP_RX_CLKFAIL
" |# ~6 c4 w t4 ?. H$ e| MCASP_RX_SYNCERROR h s9 P" E& k! s
| MCASP_RX_OVERRUN);9 d+ m* @3 a6 g# O7 O
} static void I2SDataTxRxActivate(void)( B) w4 ^) E1 i0 F% C
{1 U, Z w; \+ p# F6 I6 A% s
/* Start the clocks */# M/ p* O+ {- o% f; z9 q! w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 f* C% O4 l1 J R P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ j+ v% {6 d5 T7 o# o: vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* K+ @& Z' `5 nEDMA3_TRIG_MODE_EVENT);0 Z7 F1 W! h; A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: C+ W" r( R4 D, R+ GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 j1 \$ `) L; J' U$ @/ AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 k% s2 {$ o6 K8 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 V/ j2 B+ R& Z. |# M+ Y8 m* Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 i8 ^7 a! W, m6 \; b& X# gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 F& Y+ N& B# x. k% \1 @/ Y8 u5 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! w" u# d" Z7 m0 U. a
} 9 O0 y: O( y8 U& q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # P2 @4 m* p& u: w) E: O
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