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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- h% F( f4 i( @& s! c4 h$ B
input mcasp_ahclkx,
8 U1 G3 U! z$ ^; H4 A5 s; Xinput mcasp_aclkx,2 q8 a9 L4 \ q, |3 l5 a& j- V9 p
input axr0,# H3 r+ O, P" L/ _4 j5 w5 B! Z
! e; C" g3 G' X' g' B3 [output mcasp_afsr,
* ~7 s, O: r# D1 U, X5 J& s7 r }output mcasp_ahclkr,
- s$ B3 U) U. Soutput mcasp_aclkr,# I+ i9 @0 R& X, J
output axr1,
9 |* I" }- i( U$ Z assign mcasp_afsr = mcasp_afsx;
' |6 X' A' ~8 E2 Wassign mcasp_aclkr = mcasp_aclkx; A- R& j" ?+ j( s
assign mcasp_ahclkr = mcasp_ahclkx;( |# y( h3 M7 W1 S \' b
assign axr1 = axr0; 9 O) W" O$ M: B0 k% c) A
; H3 { T; i1 P3 W9 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( r, m& p8 f# U ~9 bstatic void McASPI2SConfigure(void)
, y5 o, o$ ]! J" }6 }{
7 C% A3 G8 N( {McASPRxReset(SOC_MCASP_0_CTRL_REGS);, i+ `5 _) e7 @% k2 \" ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 T' O1 {4 Z$ ^! ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% C- y' T1 u' I K/ q; bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) G1 n* Z, N, g; I$ T6 G' X& Q! B" \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, m0 I/ [4 ?3 D0 |8 F9 k9 WMCASP_RX_MODE_DMA); t& O8 W, F0 X. a) Z+ H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. f% d& I: H1 x0 M( RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 `, R% s+ a3 }8 a$ xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( h& P# b6 u! q% d+ ?$ q. fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& D4 g# s& Y; \, p1 w+ @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 t6 W% c% a, K' h' dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, N$ p- ?/ a( u3 ?; y" |7 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
h6 D+ p- e" b5 ^5 ]# V) G' jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 y2 t3 C ~) L9 m" @+ u% DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 V& u9 X4 ]- z! {* O# ]% C0x00, 0xFF); /* configure the clock for transmitter */, M* O" w5 `* X. L9 k3 C7 ]4 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- T- y9 U+ e2 M% |5 I" x9 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 Y6 L' k7 M9 R: B1 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ F' E% l3 l2 J0x00, 0xFF);
- d! y! K' {& M! }# O- K
( ~3 t3 F% F0 b; W( q/* Enable synchronization of RX and TX sections */ 5 ?3 i5 o/ g0 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 _5 A( q" g5 G- W, K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 f; S4 X& _; U1 O- m9 T* m" p6 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& f+ Q/ k/ ~' v9 _' l7 k% d# l! X
** Set the serializers, Currently only one serializer is set as
1 ~7 G% h0 H2 q, r** transmitter and one serializer as receiver., o2 N) }* Q5 B5 m
*/
# ]/ o: x ?( EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 C2 e1 l+ F2 A/ S/ x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) J/ M/ z0 U S# \) D, l9 l** Configure the McASP pins 6 f. [5 e- }4 v2 H
** Input - Frame Sync, Clock and Serializer Rx' b$ ^) T1 b7 X, i7 C8 J
** Output - Serializer Tx is connected to the input of the codec
4 ~. o' _# Z9 T*/
. w# m$ e; s$ e1 c% r0 [# \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% S x9 B: x) Q; J& h! |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 B8 }. a; R. k0 _$ v( B" dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! }: _5 K O8 O! U4 O" u: Q| MCASP_PIN_ACLKX
. M, o5 g2 f& f1 m" n| MCASP_PIN_AHCLKX# P% D+ m) s- n1 ^6 D+ ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 B s, }) g$ v- V8 f. {5 } ^) r! D' `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 M9 E- Y- Z) m! m0 O
| MCASP_TX_CLKFAIL 9 o1 }% E( g9 j& _3 c$ R: Q
| MCASP_TX_SYNCERROR
( k6 c$ E+ i" Z7 [0 Y9 E" G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 x2 a( z! @/ \% J/ ]% m: K| MCASP_RX_CLKFAIL3 j' d9 a7 G% p5 J, H
| MCASP_RX_SYNCERROR " t: ?: @$ T+ r' _
| MCASP_RX_OVERRUN);0 ^& R5 X& j3 b
} static void I2SDataTxRxActivate(void)
- V3 a6 j/ x- |' n5 |) b( K$ j{
# N1 q% m4 j& a3 K8 O/ X/* Start the clocks */
: h6 n6 A9 F3 p; ]2 @0 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; a! S |% y% F4 B' PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// i6 i7 {1 U) H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
R- G, b4 [9 j6 xEDMA3_TRIG_MODE_EVENT);
$ k+ w1 c: z" ]& h, a0 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & a9 F$ s" r5 S# s" P% p/ Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ U' g5 `1 V' `: K& x6 k7 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# y5 N; r. T7 a5 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* T K" ?0 c; Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 E* X1 ]9 k y0 \: q) h$ d2 S& o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ L% q' b$ e' U0 q, {& j# C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" c* l: B2 N% Z7 P} / g5 ]0 q# d2 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ p( s& K6 L6 v4 u1 x
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