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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 b" l4 Q5 U/ q( Z4 {, cinput mcasp_ahclkx,+ a% \. H! |* P. R
input mcasp_aclkx,% K7 c9 |7 ?) U) W M
input axr0,$ R6 S4 L# ^0 q; U. }6 `% {
; T. C9 a v Z* J1 q/ Z( o) uoutput mcasp_afsr,) Q0 M4 a9 r3 M% M* I @$ R x5 A
output mcasp_ahclkr,5 `+ }+ e* _1 T; E4 c Y% d: f
output mcasp_aclkr,! w' L: }+ ]4 s j: }) ^
output axr1,/ Z3 Y; K; t% K* C b8 N5 B$ \/ e
assign mcasp_afsr = mcasp_afsx;) E5 s% r$ a [$ h
assign mcasp_aclkr = mcasp_aclkx;
% q$ r2 e: O( W2 Sassign mcasp_ahclkr = mcasp_ahclkx;
/ B# z) h; l, {7 V0 r( j0 P) M% X/ hassign axr1 = axr0; ; S, \! Y% p/ M1 ?5 i. k
H' {/ c+ ~3 v& h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 O2 U) A# Z8 [# {6 F* C
static void McASPI2SConfigure(void)/ h+ K9 Q& b, f4 q1 {4 B/ i8 s# A
{
% x2 l T1 w# [/ S zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( L% H8 m+ b q2 ^7 O( {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: j7 B- G0 |/ T r7 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ @# W% u- B# e1 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 |; B: L5 D5 q- \: cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 B/ @' z' [ R' M# { p/ _MCASP_RX_MODE_DMA);
4 @, k$ y) q: m* W1 x% [( XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t# k* F, F P$ N& ~) t1 |' Y0 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 i4 \: t1 H4 t" A4 F# y7 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" n' V5 M" n% n) w. LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; ] M$ O3 C2 C: t% |8 e( U/ F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: m! E# O/ K8 `; ~$ ` ]$ EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) D) j0 \* z; E. {5 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. Z7 r' Z: L4 B0 B e; \' B7 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! Y8 [ ^) V$ t: ?* |+ j; q! O4 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# P; s, D( c# W* c% _# G
0x00, 0xFF); /* configure the clock for transmitter */5 D, ^5 u3 X) z2 c' ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& ]/ t- w' J% o6 @* z0 F& D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
E0 V/ w# R$ ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 f; C, P h! l$ \
0x00, 0xFF);
! V' f$ y7 N8 S9 }6 V- C
$ P/ N4 P& {: U$ ~- A& z z/* Enable synchronization of RX and TX sections */ * F2 Y5 z8 ^7 l% C* K% c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 v+ U; ^8 \1 ]* H: c* F$ y# ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ a/ i" ] ^6 w6 N( E+ tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! N- L( J7 ~) B1 |** Set the serializers, Currently only one serializer is set as1 |7 y+ W0 q6 j2 |. D( F
** transmitter and one serializer as receiver.
9 k5 B4 M9 V3 h1 S T r5 x*/8 t8 J0 Z! e5 ^! F) h7 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! _' g- N- ]8 Y5 @3 T/ ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% \, a5 A, }6 r' V9 |* [$ T8 e1 u
** Configure the McASP pins ) f k" D3 X% v3 G9 q
** Input - Frame Sync, Clock and Serializer Rx
4 N& F9 ]0 e/ @1 z** Output - Serializer Tx is connected to the input of the codec
. P4 b+ E4 ?# V/ b*/
* O" c! g7 a5 L2 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* T/ [2 x% N0 o, {3 b- T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' J% p; a5 K7 v# y0 `4 D! S$ t& N; dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: y- _ V. a& G$ B7 S
| MCASP_PIN_ACLKX9 d1 }1 e9 L x
| MCASP_PIN_AHCLKX
) Q. S& O$ N- i* O7 A+ @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: q8 z# K/ y) n, c- d3 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 A8 O: S0 }" B' a. D( k
| MCASP_TX_CLKFAIL ) g3 @8 m# f2 y B: s7 L% B L
| MCASP_TX_SYNCERROR
" s4 |3 p: \, @2 q1 |# H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ j5 K5 b: E: z$ s6 y8 O; u| MCASP_RX_CLKFAIL
7 i0 @ K. R3 h| MCASP_RX_SYNCERROR
' n2 y4 j1 p' D+ o$ I& b0 ?9 Y0 M' j| MCASP_RX_OVERRUN);
/ f+ y' Y1 j" _: u" j} static void I2SDataTxRxActivate(void)
- p' G& K" a- m- \) r{
0 K/ e( c$ R5 a/ W, D$ }/* Start the clocks */
6 i4 Z& X5 R$ I: xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- L- u; j5 C* Y$ a; I. qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! w( V2 \. }5 p* g7 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! F9 s9 V) \8 {6 i& E; }& e' G% wEDMA3_TRIG_MODE_EVENT);: W" W2 ~% X# a& d# z T- ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 P5 m1 M, W2 e7 r- Q2 ]6 ^8 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, d' p$ ^* V: |" r+ Z( x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ U" B5 W& m+ ~$ C- M9 _5 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 ?5 O2 ^. Q2 g' C' o; r/ a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 T: N7 e) y) W3 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) ]" F6 \# Y3 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( a% z! d$ R1 p! F1 T
}
$ Y# t6 D$ I0 r! `7 S: d3 y3 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 t- S8 r/ ]7 J) N
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