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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 _+ ]( m' _7 a' g% W
input mcasp_ahclkx,, [( n; S& F' i" _* E
input mcasp_aclkx,7 l- K# m. ^; B) C! o/ R
input axr0,
& [+ t3 |0 }" x
2 x' W7 \: h8 Moutput mcasp_afsr,- x3 D' j+ R. Z0 L) `
output mcasp_ahclkr,; Y! ]6 |! E, I: q' ~
output mcasp_aclkr,
& N; E2 }7 P3 z, P, a2 eoutput axr1,
- j5 D4 Q& y; U7 }! ~ assign mcasp_afsr = mcasp_afsx;
]& W1 m; `, R- _- u, \! Zassign mcasp_aclkr = mcasp_aclkx;9 @# T* Y5 A! ]# K# J6 q
assign mcasp_ahclkr = mcasp_ahclkx;. z$ A) f+ d$ ?' y
assign axr1 = axr0; ' D. u& w7 L" K% m
$ E2 Y& }$ g- l+ E$ x2 `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # T5 ?& m+ _- s
static void McASPI2SConfigure(void)
# a+ ~" T: F! v# D/ D{
: t( r- M9 F! C# k$ X* oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. s* A& O$ E* BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ x, Y$ p F/ p. \: H0 z4 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: p% ~/ G" S- o6 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: Q0 Z3 [* p6 w1 X0 @% W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 a* N$ S1 K! a3 _
MCASP_RX_MODE_DMA);7 S8 w+ O3 K& \0 Y3 p% a% R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( n* L* G7 q0 l2 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- v0 B3 t! l* C$ ~. lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 V8 Y9 I: {" b( F4 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 y+ ]. ?' K3 n0 H) Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 d# ?3 `7 v9 Q8 j8 Q" GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& h7 P5 y7 @- }7 \5 |- tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ h0 g1 k2 M' x; X' i# ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " t6 T8 _6 T) H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% F4 X/ z. T& b5 ~* s/ |0x00, 0xFF); /* configure the clock for transmitter */
V: ?, J# \/ t& Y6 nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% y% @1 X' g o; LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # u, z$ C/ k9 r% Q6 i6 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 o2 b+ a7 f5 K9 s' E9 n* \$ Q0x00, 0xFF);5 L) \! }& n' o4 j
& t; w1 e" f/ _" M/* Enable synchronization of RX and TX sections */ 2 H0 u7 l% y5 \( @' ]( x$ R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 ~4 i$ C. A$ y' n8 x k( O- YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% q% ]% f$ N' w- u3 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' c& `! Y. D; {- O( C% {. o' g8 a
** Set the serializers, Currently only one serializer is set as
4 e5 \( I0 {* U& ?; f3 E" S** transmitter and one serializer as receiver.1 X$ a5 Q5 i' _# B/ _
*/! I `; w/ D- t7 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, A1 q8 D* P4 g, D6 O! M* c/ ?7 bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" c2 O8 B8 C5 c% H7 Q# }1 U5 G** Configure the McASP pins
- c4 _1 P7 P$ S4 Q" N# V: E** Input - Frame Sync, Clock and Serializer Rx
1 K; L6 N* m. l2 Y' Q** Output - Serializer Tx is connected to the input of the codec
: j3 Y4 s( q& I! K U*/
7 s9 y9 @/ U2 t) b2 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* v; v% _7 f( e6 M, o7 z6 u& \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 S9 y s- z+ E W# m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& h* h2 R- h5 A1 C* Q, b| MCASP_PIN_ACLKX
/ p9 B! A! S; l4 ? Y7 L| MCASP_PIN_AHCLKX# L4 N) \; @" d" T2 l, V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 h' E+ u% j6 }! N" EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ a! V S( ]: z/ U$ F% w2 ? M| MCASP_TX_CLKFAIL ( t. y+ [: {1 E9 B5 K
| MCASP_TX_SYNCERROR
, n1 `# ?6 M y! P. ?. d t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) j& s% |" ^1 [2 w8 F| MCASP_RX_CLKFAIL9 d7 d; o: J( ]& ]4 z4 |6 h/ n+ [
| MCASP_RX_SYNCERROR 3 d7 Q% ^' o2 O7 e6 u( _
| MCASP_RX_OVERRUN);- ], R, m6 Y7 \$ z R, [3 ^
} static void I2SDataTxRxActivate(void)" A9 M& u, U. M' E" f* P1 J
{; ?8 \6 W4 T$ M. C* C% j
/* Start the clocks *// L$ y! a' A$ j! O& a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" m: O4 M3 K. L1 n; w; G# KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ X8 j- r0 ?2 x/ m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% S! G- l3 I0 l( H! A, n9 u8 SEDMA3_TRIG_MODE_EVENT);2 ?$ {) g( `4 @8 b* o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % ?3 ^; M: k0 _8 L6 ?: h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% M/ O2 R2 g: e% S/ d$ x- v' vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 s- I, O& m4 K' o! X$ V1 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 _6 h- y; v" s7 U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 z2 l; B+ P2 x. o1 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 N1 ]! N# A8 A: K8 a) U/ Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 K7 |1 ?( ]: y0 n, z0 y- n} ! W: n2 p3 \+ d" s* \: B8 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - d8 i' M: M1 s
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