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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 p) t* n! P( a* J, p
input mcasp_ahclkx,9 d* N/ R4 k9 c7 s
input mcasp_aclkx,' I# A) _2 _+ `8 s
input axr0,
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7 t5 ^7 Q* V1 G# ?6 V5 Y1 \' goutput mcasp_afsr,9 }) \9 j+ g. f3 }1 o" _* S& P
output mcasp_ahclkr,
7 l; U1 s# G* `1 C" a5 M' P) E" ]3 w n5 houtput mcasp_aclkr,; y/ I! q9 ?8 ]3 _
output axr1,7 W$ f$ t, ]! c
assign mcasp_afsr = mcasp_afsx;6 Y' x, n' U8 B; d
assign mcasp_aclkr = mcasp_aclkx;' ~0 Z0 l; c( i% l% @- J' o
assign mcasp_ahclkr = mcasp_ahclkx;
$ a' m# v8 L9 }' l- N; [$ ^assign axr1 = axr0;
5 d( A5 p9 Z4 t" H$ ^( |9 Q6 \. M( i/ J' T5 ^0 W, @2 b0 G# C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 a1 z4 U0 ^( R3 ^
static void McASPI2SConfigure(void)5 G. w% S6 C! E; _8 O7 R% |
{, z8 L3 b" `# |' ] d
McASPRxReset(SOC_MCASP_0_CTRL_REGS); f8 P: T6 U1 }3 |! m& m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; N" ?4 Y, w C/ |0 p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. K2 _5 l+ B1 @9 y6 M( u8 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
e0 D# @- G# R0 A' Z( i, ]) ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 |8 o& z& Y9 Q. b- G) j0 Q
MCASP_RX_MODE_DMA);
) J$ h c- M) R9 T3 ?8 u8 w/ _" J, aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) p" {; {* s0 U6 @. l. s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 `0 M1 w$ Z" uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' X" X2 D/ q! t% z' S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ m, h1 o7 k8 I9 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( c$ l% j# y* M3 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
\. _7 v; I: j' l5 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( k7 U9 v$ z2 T1 X* v d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
e5 u- Y' l6 Y9 t% P% SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, o0 \. L3 a/ c1 d5 G* ^) i
0x00, 0xFF); /* configure the clock for transmitter */( }( R6 ]+ R& q% ^8 Y( M; V, u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 G% O' D& g! Z( g* [4 d" d4 l8 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 G$ O6 a$ F, h7 J1 O; r5 d9 SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& D X& N! F% |" |, G
0x00, 0xFF);
0 c7 y( N' h( w# m
+ u2 v4 u7 F5 E j/* Enable synchronization of RX and TX sections */ ( \8 ~: I- d0 ~8 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 Z4 @. e }0 k0 T8 s) ~: k) f. Y# Z) kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 a5 I! f( q: w1 q6 K" D1 B& YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 l& m9 [1 R c% d d# ?** Set the serializers, Currently only one serializer is set as
7 @9 f2 s, D/ x: K8 z** transmitter and one serializer as receiver., G& L) Q) h) M( ~% i8 ?- Z
*/0 K3 P# l: h! t& P7 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; B! @' I1 x4 v4 o, K! t" OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 Y1 X! A: H+ C, B Z" D3 F9 l** Configure the McASP pins |8 g9 S4 x5 P& r; [
** Input - Frame Sync, Clock and Serializer Rx
% L* X3 [& `% G# a0 T5 c** Output - Serializer Tx is connected to the input of the codec 8 Z& f, G0 {0 w, v: [
*/
* w6 I, ^2 U" IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 ^/ |! z6 S; a9 O$ z W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* Y0 G: M' D& Z% t$ {3 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
v G9 J% f1 @+ U( L% P# r| MCASP_PIN_ACLKX" f% d" W& m# I3 e
| MCASP_PIN_AHCLKX9 k/ U) Q$ V0 J4 ]( E# J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; s3 S2 {/ n9 A- yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( P8 a8 x# K0 g| MCASP_TX_CLKFAIL ) z2 w8 a& {: b- H& q
| MCASP_TX_SYNCERROR
; C( t2 ~) F9 W7 z" z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 U5 C' }; @) X; N: D, W' A
| MCASP_RX_CLKFAIL
$ Y; `. {3 V9 e| MCASP_RX_SYNCERROR
/ I1 z5 l0 R4 O4 |( P& F: {) L| MCASP_RX_OVERRUN);* @) n$ o' U" g; `$ ]4 r
} static void I2SDataTxRxActivate(void)& ~# h l$ o( |0 F+ @
{8 f( d- M ^: f% \7 v
/* Start the clocks */
7 M Z& d' ~" q' L5 `% u, g' f7 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 M* ^* K6 K" Q$ u ?3 `% @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. [+ A; {* f4 [6 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ k( z3 k7 G' s
EDMA3_TRIG_MODE_EVENT);: @7 V4 n N1 }2 h5 l" K. N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' }! k* `3 D" l3 j$ ?7 L7 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: m3 j% q3 c6 k/ ]( T" O }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# _# _/ T' R1 d8 O( C; g% H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 }5 M! Z' T9 q7 |, C" M. q5 o r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 n$ e* j' W4 Z/ Y& F: w- p! D2 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- x: O& t. ^, u- H' h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 l' @2 b% Q: X \4 i% y! d/ s
} 2 j4 [! L7 z/ R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 t7 Z+ ?9 g( E
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