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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 \4 J$ W/ Z" Y3 u# H( y ainput mcasp_ahclkx,
! { | ]* p( `# O3 \$ D$ ^& binput mcasp_aclkx,. g9 C/ i9 G, H) N# K
input axr0,5 z( F5 {; ?: q
' k8 S y/ {; L5 k4 i6 s7 Z) w" ^output mcasp_afsr,- T; ] g7 C0 |4 }
output mcasp_ahclkr,
" S. I; u3 p y) }output mcasp_aclkr,% |% \6 N. ~% {2 G
output axr1,* n+ Q. l4 x$ Z! P2 R: i
assign mcasp_afsr = mcasp_afsx;2 J, ]; {$ I+ C7 c# V: i
assign mcasp_aclkr = mcasp_aclkx;
9 l& K9 O4 p& _" k( Wassign mcasp_ahclkr = mcasp_ahclkx;8 q' O% e% A' m' ? G
assign axr1 = axr0; 4 a5 a! ~& { X6 A
+ X" N$ o2 f/ z8 u: A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' l+ w7 A% Q1 u; ?+ t4 F: ~, c' e" r7 }
static void McASPI2SConfigure(void)6 v A: H5 z# P; K$ ~/ k
{
5 x8 }% B* B; G: E3 {: A kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 x o! n4 S" S B O h. G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* M m# d3 l; @1 }3 ~1 y- {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 L1 P+ O* L0 e" s# Y Q4 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 z- s) u/ P+ u% `+ k$ O5 A& a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( U# I7 ?# k' r7 N5 H; I ]- d
MCASP_RX_MODE_DMA);% c4 R7 o* J( j3 ?! p2 S7 }6 C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ^1 {3 m2 Z% f" d4 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# A# E" m# S& `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , p6 K9 }8 ?" B: ?! ^/ ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 Q! _% S$ A9 K8 F/ s( K2 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 D2 V: ^8 p" H8 v( s2 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 |* I/ j6 f, MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ [. N" k1 m0 [8 j) zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : x. _% |4 z/ O8 M" H k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) f) ?3 F0 L% U- t8 L0x00, 0xFF); /* configure the clock for transmitter */
H/ p4 v7 t7 G1 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: `6 r* q" ~, I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % P) ?8 e4 y0 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 j$ g, `" O; Q5 }4 F( ]! h0x00, 0xFF);
. d C; v' J$ i# g* e3 y9 Y" p: P& r/ q9 w& {/ j# F
/* Enable synchronization of RX and TX sections */
6 {3 f) e6 ~/ |- KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 L! Q* s; M! j$ R: gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 u) i% w5 d4 X( ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( s1 h: r( D. l% n** Set the serializers, Currently only one serializer is set as
( a7 \2 \) Z" q5 N) }( T** transmitter and one serializer as receiver.& k* ^7 @. Y: z, O& m `0 }1 P1 V
*/
' I3 A" l( i' D% E$ t/ o; U+ [3 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 \' H/ }" ]6 a( q+ Z) p- p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: k5 B$ k* W0 } Y** Configure the McASP pins
8 [8 S6 }) _ ]& ^. d2 M+ o** Input - Frame Sync, Clock and Serializer Rx
; U1 n; T3 a# Y* k1 k) } k** Output - Serializer Tx is connected to the input of the codec
1 q# K" O9 y- l- d3 R*/+ Y0 J6 J3 X6 p& C3 Y; s- i! |) P( w* ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" q' L* R2 e4 H& m2 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" }, c1 {5 P, k8 B* r2 VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" Y5 `3 o# o! p5 d| MCASP_PIN_ACLKX
8 Y5 x( S: Y$ v| MCASP_PIN_AHCLKX" \& U+ @9 b- i. Y: R* W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 K* _8 ~' m- _$ e- K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% M3 K8 o3 C# \7 [* Z# D" ^| MCASP_TX_CLKFAIL % ^; _. j* B8 h. k. W' R' w* Y6 s
| MCASP_TX_SYNCERROR q% v m5 r" s) |" e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 h0 d0 Z; }. V: P3 Q
| MCASP_RX_CLKFAIL% F' e$ |+ {# T1 N+ K
| MCASP_RX_SYNCERROR
" i& K; S1 o8 b, b" m" g| MCASP_RX_OVERRUN);
5 R% ]/ P/ o7 ], c/ \} static void I2SDataTxRxActivate(void)
5 x' ~5 ]( {5 J7 n; E- }{# }$ ?5 e u: Z$ {) \( B: V
/* Start the clocks */
! y7 Q! @1 p* f& x3 @) Y+ tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" x! n+ u$ t" V" o- p0 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& n# D1 y) f& u( N AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 E8 P$ ^8 L+ E$ eEDMA3_TRIG_MODE_EVENT);4 q2 b/ V! F9 J( s/ N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 K( f+ N$ Y; P" f) B# p; A$ wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* y4 `5 K8 k- ?. o# O6 Y0 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! b& e! b$ S& U2 _/ p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' c' x o- M/ b) C6 ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ U# j* S4 [( c i9 Q7 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. Z3 A# `8 M; L2 l! S$ D' R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! w8 ?' E$ G n! f1 p+ N- @" K
}
" j, T! a- S) ^7 Q$ d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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