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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 v5 q6 f* O7 O5 Z
input mcasp_ahclkx,2 k" c$ }6 {4 N, ~
input mcasp_aclkx,
9 Y5 s" L9 X D, I6 j5 s; u4 q" }5 ~input axr0,
7 D; \% N# ?1 _; a Q; m! j/ j0 I. @* _
output mcasp_afsr,( ?1 J* w4 t- s8 c1 M. y! m: A4 L
output mcasp_ahclkr, U, Q5 v1 s( w8 S7 E8 R/ U
output mcasp_aclkr,
8 c1 K- |9 t+ Z& D r/ _- N3 koutput axr1,7 {3 p H. v7 q6 d! k2 O2 ^
assign mcasp_afsr = mcasp_afsx;5 G. H- r) g2 h- B2 q
assign mcasp_aclkr = mcasp_aclkx;' k6 Q: S6 z4 k6 ~" q
assign mcasp_ahclkr = mcasp_ahclkx;/ |- O5 \% x7 B8 J5 S
assign axr1 = axr0; ~- [7 G* [+ n$ h( Y$ |- U
9 J' b5 F1 |8 R: j; `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% S7 V2 K) c% R* o. q: z' jstatic void McASPI2SConfigure(void)
) r7 H& F" }. H. G1 O{' N% a' }" V* \+ ^$ R5 x( \' |0 p. q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Q! Q0 V2 y1 T6 \! t+ i+ Q' sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! y `5 p0 V* E% XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ `2 V+ U+ d; \3 [5 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ z3 U. r* E& y5 e/ } N/ T& N, R3 N' sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
N7 K& z3 X: k. IMCASP_RX_MODE_DMA);
+ t/ u5 Z- _) J* S- J1 S4 mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. B* |1 r8 K0 K2 oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( y) n- Z! \9 N' o* r: b% v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( R1 w9 d: V% F. }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ c* u- `: y# g! g# w1 j6 t9 T( ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 p( C7 I" K6 l' nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 z: o6 l8 T/ C& S; U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# [+ @) {" t h) r& [, |$ A0 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: |1 z; N$ t. ^9 {/ j# p1 I5 BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 ?1 h4 m# A# P* L3 g! ^0x00, 0xFF); /* configure the clock for transmitter */" p! Z# B: }) l! v8 v3 O& D% V+ q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 ]7 L6 F! {$ U; s$ t; ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) x' W2 C2 N$ u+ ^* D4 l( G C" ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; Y( e: x" P( \7 b$ T2 r4 c; |0x00, 0xFF);7 K9 d7 v5 K' D& `& u, }
' V8 [$ q% A5 {/ p8 K1 ~! l/* Enable synchronization of RX and TX sections */ / Q* J7 l/ A6 {- H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; Z0 u5 @8 |, S9 z' h! ^0 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# P* n& H% W# J! P7 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ u# ~/ u1 e$ v" K2 _7 f8 {4 H1 ~** Set the serializers, Currently only one serializer is set as
; i+ A5 k" r1 Z S0 g b** transmitter and one serializer as receiver.4 h8 `; j! S' b$ e4 E
*/7 s9 P# @- G! l" l3 e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 m; U$ @4 n" ?( ~, Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 n: S& l( v9 M! s** Configure the McASP pins
% g( [. q9 u. }** Input - Frame Sync, Clock and Serializer Rx4 W/ O( v9 k' A
** Output - Serializer Tx is connected to the input of the codec
7 a- F9 y* T, Y7 }; n*/3 Z# K3 R3 x3 M' o( @2 I2 p/ V! [. D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: O( ~ ^ p! l* V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ M8 w" \, t8 K% K* h" T6 ?3 N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ u+ |: B& z0 B, c# n
| MCASP_PIN_ACLKX D) i. g* a% J
| MCASP_PIN_AHCLKX
0 W8 n) I; a, G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( X8 |3 @% H3 e/ t; w9 M; h, X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 T3 e& z' D$ _: l' c| MCASP_TX_CLKFAIL
8 F( ~; k" V7 J5 j$ M| MCASP_TX_SYNCERROR
" O# D' N$ O Q, E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / d7 S% b% C% j
| MCASP_RX_CLKFAIL
& R: y9 c- }, o$ {9 ~& B% R5 e| MCASP_RX_SYNCERROR
3 p' g4 N+ Y$ F| MCASP_RX_OVERRUN);/ `5 c- o, h O9 ~
} static void I2SDataTxRxActivate(void)( D0 m; W4 w. Z
{
* v, ?8 t- y$ {; g! v( e/* Start the clocks */. C# r- ]& I. j2 S# o' B9 Q! h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, Z* M, r3 \/ @! CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, c5 ~1 A- Z; `: V& `& OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. z1 @( M" V7 Q9 Y8 D8 H+ l
EDMA3_TRIG_MODE_EVENT);
) N& g) F' ~7 R! `/ b B! _' p+ [: fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 I& x6 R! @% E* C' AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 x/ E) t8 D$ T3 L) S3 `: kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* J; o% ?2 W9 y$ I8 I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// B# V6 i7 E9 S- K( V! M) C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! | o9 i* K3 Y- q nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( C1 G$ h9 l+ Q4 u, `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( [( a6 Y; ~7 f1 ~4 o" c6 K$ L4 Z}
9 u9 \5 K' M- _- y+ j$ t1 M, m5 O7 |; V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ?3 P8 A% V- L9 M
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