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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( t8 F4 g! [0 Z# X7 [: P' Q. s
input mcasp_ahclkx,
0 P; w, W/ J8 Z) i# `: Dinput mcasp_aclkx,8 {, _9 z1 N* E' W R+ V8 d9 i
input axr0,0 u3 w/ ^2 J3 N s: _
& Y6 D7 L, W6 k* R- G/ noutput mcasp_afsr,1 |( v# l* R5 i' T
output mcasp_ahclkr,7 @: J7 m8 s6 S1 i- |6 M/ B
output mcasp_aclkr,
7 `; |6 N. k6 B( W7 Noutput axr1,
% i9 i1 [, e- h( e assign mcasp_afsr = mcasp_afsx;
2 g, u5 O. u% N9 N( Y Wassign mcasp_aclkr = mcasp_aclkx;
+ l+ I6 {& m. D6 D( p& Passign mcasp_ahclkr = mcasp_ahclkx;
1 I. W$ z- H3 X# Aassign axr1 = axr0;
U. d7 x( V+ y1 p! }
2 G; B) O8 M5 g$ F- J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 T3 H, }2 j4 W3 {7 \1 z+ Ustatic void McASPI2SConfigure(void)3 U L* n* |+ v) S q! }. H" A
{# F) j x( @$ }$ y* H4 \
McASPRxReset(SOC_MCASP_0_CTRL_REGS); A! h8 d+ q* M& B( S! t# F* j' I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ m* h. ?+ U: e7 Q" ?4 k, w0 ]6 A' n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 a% C; V$ ]: _7 l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* b2 j- L- L+ g2 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 Y+ U1 @. Y7 k& n7 d* B
MCASP_RX_MODE_DMA);
8 S, ~( v! B" z7 U# V* F& oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, I1 W4 y. y# v4 f) a5 D& F8 `- V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 s( H- v+ V `% k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: G5 O( z: X5 N7 u* [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 G! X% ~% d n `" E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . J" c9 S) Y) q/ _+ O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* |4 D; r- A# x r/ I' GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 k" D n& {8 x( s0 u6 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 i! I$ r: r$ H) g& R+ f8 v/ L9 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" N" G& r* X) `0 {! S; Y5 g& U: h9 [0x00, 0xFF); /* configure the clock for transmitter */0 H3 x' j1 \" Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 U, T6 a( n. `4 `! vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 E6 n3 _7 t: `* Z) a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& A5 U1 V7 }( F6 J% ~* B
0x00, 0xFF);
4 d1 G! S: P. _* ]- N/ s1 a0 \3 T' a2 g
/* Enable synchronization of RX and TX sections */ 6 p$ W, W- N. b; w' F8 l, _+ _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ y" z( n- X; KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 F, Z" f3 D6 t: h* ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ q# z, E* `# ] W* k6 x% ^$ l** Set the serializers, Currently only one serializer is set as- ~' L- Y+ v, `( p& ?* _5 r
** transmitter and one serializer as receiver.7 E3 i! c' u2 J& o7 |4 o
*/
3 V1 p0 O( j/ V/ H) iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# i8 R; w$ Y) L6 p/ _" @* M6 |! vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 }- ^' R* p- V9 M _; o v** Configure the McASP pins . W8 {, j7 b0 [! ?$ ^. V
** Input - Frame Sync, Clock and Serializer Rx
l% q7 K, e5 S5 g/ @ e U6 v, r** Output - Serializer Tx is connected to the input of the codec
: W# c U6 U8 Y& ~1 Y/ s*/
6 X$ |9 [+ n8 V. V3 D' WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; g! Q5 g' y+ VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& S1 p: n1 l9 t! U, _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 L" f& o/ R! l P; d8 b5 t& _| MCASP_PIN_ACLKX) C( L; @ P( U9 r* l
| MCASP_PIN_AHCLKX1 I: i) v$ I$ h0 k; C# [; ]' |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 c* w1 p6 {( |# o" @5 @' B" P1 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 g! g6 D% {- q9 m' h7 s
| MCASP_TX_CLKFAIL
+ A: H8 g; W" e+ o% H" ?& J| MCASP_TX_SYNCERROR
' Z& M0 h6 p9 B2 k+ t6 e7 i' x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( f5 N; J9 w) D| MCASP_RX_CLKFAIL& V! D9 ^6 t$ N; o& n/ E
| MCASP_RX_SYNCERROR " X9 a1 E9 |4 `2 ^6 C2 G! w
| MCASP_RX_OVERRUN);% v+ g) E8 h. ?1 k7 D7 k' ~- v
} static void I2SDataTxRxActivate(void)
% f0 s$ N# e8 b{5 K$ x5 E, m: J( ^
/* Start the clocks */4 O2 G9 Z& k$ `* S0 h- a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. N/ u9 L, C% c! l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) ] l! ^9 V! u: D- u8 C7 s) P/ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 Q! h* H( y1 ?; LEDMA3_TRIG_MODE_EVENT);, n! _ G: i5 E% n; s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 R; P4 ~. p$ t( t; N4 [6 z3 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ r" n. f8 ]% r( J d: p( P1 g2 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( \! L7 f/ y4 V$ H0 n0 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, x. Z+ p) z1 V7 x) D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 W* {" ]! K# R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 U0 c9 v0 |* c) z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 g% F" W0 ~3 P3 X; l
}
7 _9 X* T: I6 R7 G o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; M! M3 B" T/ b3 ]* a! U- x. Z1 i
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