|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 z* N. ^8 \/ X' x& I. e
input mcasp_ahclkx,
, C$ t+ I7 y# F* a |input mcasp_aclkx,
F a/ D4 m5 r: [2 V4 e& ]input axr0,& K* m' ^) O2 e, Q2 h' y
% C2 U0 `# S1 [4 a) ?$ J
output mcasp_afsr,
/ d6 a4 T3 {! c* t7 f" [: |output mcasp_ahclkr,
) f: X. L" S+ S) Q2 Q- Eoutput mcasp_aclkr,
3 G1 B$ O+ J/ K5 z0 |output axr1,& }2 u6 L9 l8 b, y" d/ a
assign mcasp_afsr = mcasp_afsx;
2 R! F! J8 r# ~. Q. U& @& L, \assign mcasp_aclkr = mcasp_aclkx;6 w0 E7 B% }. ]+ g* ?5 F( L4 Q
assign mcasp_ahclkr = mcasp_ahclkx;3 C7 g; k8 {; Y& S# ?
assign axr1 = axr0; 7 S" Z$ _& C9 Z5 Y% V
& R7 T$ r+ _- N! H* T0 U, ]5 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 `) ?0 K- G1 T
static void McASPI2SConfigure(void)- ~: F/ B8 P2 h' b2 y2 K+ }
{- c+ @5 v! z$ z; |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 W6 ~$ `3 b" y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% ^' O$ E) S+ n I2 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; n+ P- l1 ^. I0 e. ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ p% ?: T( j1 g1 W2 L. X i- OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, i- [' E) H% v: ]9 K% P* b
MCASP_RX_MODE_DMA);1 Q+ a* d4 ?! H2 b! w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, C& g3 l) a3 w% |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, w D0 ^& g3 d8 Z) {) G4 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ _) \2 H9 O6 H4 |& p: jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ y1 d' K% x, Y5 c$ B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 s s; g2 M5 m& F3 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 \1 S: V6 f# S; Z& n$ I( F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& C* |3 f/ @9 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 b# Y- M3 [3 o& y* U' sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. u0 u7 j5 D8 R4 O; T: r1 O9 r% _
0x00, 0xFF); /* configure the clock for transmitter */
W6 e( s X5 Z: Y' h$ O2 j9 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); y# G& \ b8 l" U. B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 o" @& i) L+ n g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 e: d" T! c8 [: h) y
0x00, 0xFF);4 G% W4 j. {% t# {
& ?1 e# \. r/ V: Y4 O4 F" f; \/* Enable synchronization of RX and TX sections */ : L v$ w% V7 v2 P5 p q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ T# U# {3 [4 i- L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 `! E, L! v$ w4 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- F4 Y6 n3 p, D0 u5 q; b** Set the serializers, Currently only one serializer is set as
4 J( g+ V, h# C8 @6 a+ u$ e+ w; Z% s. T' N** transmitter and one serializer as receiver.
7 q) k& v+ G4 i% a0 }6 J3 I*/5 S1 w8 c" d5 A5 G2 } C' a% ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% y( a6 N0 a; `/ r' ?# l) W4 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' B0 W. s4 V3 J! N r1 K
** Configure the McASP pins
9 n/ u4 c$ b- ~ f$ a( }** Input - Frame Sync, Clock and Serializer Rx
9 F; G+ \6 t* g% S** Output - Serializer Tx is connected to the input of the codec
# c7 t7 a7 o$ j. O*/
7 ^& w; q6 O. wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: H& e7 g& h) \4 a* r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; t' M7 {2 h- ]9 E0 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; n# }: c7 G q! S2 h3 b
| MCASP_PIN_ACLKX
9 y4 F) t# D* D# G" x/ o0 z| MCASP_PIN_AHCLKX, I, v/ \* ~6 g5 |" k4 a7 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 E6 {3 a' b8 ]# Q3 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 v# a" T3 n5 ^5 w1 i' F% T+ g
| MCASP_TX_CLKFAIL . o8 H# m0 a4 S+ N% I
| MCASP_TX_SYNCERROR
) ~8 M4 E6 C M& x3 n& _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# f2 h0 J; f j* r( q- B| MCASP_RX_CLKFAIL& Y3 @, r+ D& a+ N% g$ C
| MCASP_RX_SYNCERROR 7 M9 p' k" V$ o1 a8 L5 \) u
| MCASP_RX_OVERRUN);
. b! _6 ^8 O3 c( w1 Z} static void I2SDataTxRxActivate(void)! q5 U& E5 E7 W _
{$ A9 g. U9 C) \6 ]; G3 a: Q& `
/* Start the clocks */
8 ~3 c3 j* _# e! _9 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 Q+ Q3 A2 Z3 p" C2 O g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 ~- Y. S4 r2 S8 b& AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- A" d) O2 i( q6 X' c0 H
EDMA3_TRIG_MODE_EVENT);5 F- |# W8 M; ]# I( L$ h# p1 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
r$ g3 G O+ h8 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 g$ Y5 r8 ]0 v& r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: v7 O) n7 {: j# Z4 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 d( Z' j% c0 _" X. o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 I @3 ]# W! W- y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ y* g% ~4 e4 c5 E* P$ r$ m, p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ E- H9 e/ n2 L# _}
; K$ G% @$ D8 f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! @& S7 Q& E- _) s |