MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

( u; I- \, n& X) X* }1 Koutput mcasp_afsr,
2 B- d$ g" l& \* G% C4 y9 soutput mcasp_ahclkr,
output mcasp_aclkr,
# t% R$ A3 T* b% Eoutput axr1,
. E" u' d! H1 h

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
6 j# }+ c' x" p. j- Xassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

2 k4 g' Z) O! w3 _2 V
$ a3 T, J8 o. k- x

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

, I& i2 E$ W+ Y3 J

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' V/ m1 K* Y5 |0 Y% z* M% BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
) h# b- \2 r1 M; w! ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) L& F5 a/ d4 I, k4 H! G; BMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: F' o1 |, v' t5 C( @; sMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# z) U$ t2 o# U) uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# v  W- r- P5 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( Q+ W8 d5 Q% L5 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 X. e1 Y1 K/ A' f! tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: a( \4 \. ]3 L; @, [; t. k5 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
! S9 B) e' W- q- N8 {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# C) b4 O1 i9 \+ K/ nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 a" e5 u* w6 C/ n7 _: t1 `  w9 Q+ [0x00, 0xFF);

& L% ?: q9 M+ C# S/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 I0 ^( J# h& ~3 Y0 s7 D% jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
; T+ S! Q2 s0 v/ }*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
; k6 h! L( b1 V; K** Configure the McASP pins
/ |4 w3 k0 q; B) j" A! Z" q** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
8 _' a+ L  _2 `& f# ?" J*/
( R5 o9 e6 J% j, g4 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ a( m9 p8 K' S7 O# u( I2 l. z) sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
3 p, `+ c- }, ]" I, l| MCASP_PIN_AHCLKX
6 v! q: h. p7 ^  f/ W/ J) e) O| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
" I. `" l' g- T! U! ]8 O* x' iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
  Q; \! y& @# r6 X| MCASP_TX_CLKFAIL
2 D+ t  u  Y" K, t$ f3 x% t| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 @2 e9 O/ l0 I) S| MCASP_RX_CLKFAIL
! `0 a5 Q* `; t0 E1 J& E| MCASP_RX_SYNCERROR
, D3 I$ q; x5 R& I# T# c0 ?| MCASP_RX_OVERRUN);
2 _# d: @% x" v% D1 O}

static void I2SDataTxRxActivate(void)
9 m" q# ~, Q( i) r" F) g{
$ ]' K; \. g3 |3 ]% {6 o/* Start the clocks */
9 |5 K% J& E/ K* @- L+ oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
  @6 b2 Q% D% ~: X  v5 M3 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 D8 E9 ^% m- Y, K0 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
/ j. N! J+ y! p+ Z) C4 R* g: lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' C( K; b  _1 U/ T}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

' v+ f0 T  H) B$ d6 j' ?# \/ {