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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) r0 |: i& f/ G% H$ uinput mcasp_ahclkx,# O- Y- Q b4 e
input mcasp_aclkx,
6 e# v6 A- V% P- X, ginput axr0,3 T8 d9 O1 B4 c$ q1 B+ E
6 _0 K# g5 X! D' s7 N9 M M
output mcasp_afsr,
5 a9 s8 ?' y* S+ Koutput mcasp_ahclkr,/ d( L! \; b* X
output mcasp_aclkr,
: I5 r* M/ S% q8 q# H+ i, Koutput axr1,
8 J- s% p8 H7 m' Q8 j, w assign mcasp_afsr = mcasp_afsx;
7 P4 I" X) K: T8 Nassign mcasp_aclkr = mcasp_aclkx;
. }; ]/ z& q: ^, Iassign mcasp_ahclkr = mcasp_ahclkx;4 Q3 Y- r, \, l7 U: O2 \2 F/ D' V
assign axr1 = axr0;
3 a1 U- F) G7 W, Z/ J
& E" N' {' c; n- q3 G( X: e1 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ B) Y3 E1 q8 f% E+ fstatic void McASPI2SConfigure(void)
$ R9 n- x9 g( z# _& l6 a{
$ ?9 E# I: J6 l+ \6 k2 D2 G eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 c# W. ~1 z$ ?* a/ f. v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 _! K7 s1 a \% {* P$ J4 a3 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 I9 X0 v* }. d4 H- X; BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
y+ W A; M2 W0 I' t" J7 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) g. J0 V6 e" | U* c
MCASP_RX_MODE_DMA);7 Z, S/ x* d! n0 M s5 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& J- K$ g, x/ s8 W6 Q% Q4 _' A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ i) Y. j7 k' @: H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( s9 a- W: a5 v" G' {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 \- E2 M9 e5 C# ~ Z) \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; Z- b/ s) k8 q: WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 B1 ] T# \2 O% K% C) B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* Z$ K4 h8 {* S6 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) Y5 N2 D4 _$ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' E$ w$ D' P( d# ^) y' B0x00, 0xFF); /* configure the clock for transmitter */
- G" x% O" J2 \$ p; z0 W. sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 {- y Y" j' r" u' ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" K% \- v7 N5 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) f. A3 h1 D- m9 T
0x00, 0xFF);
& m" ?, @' Q& {7 `2 R; u4 l1 U6 F" o! N" K# Y2 p/ E
/* Enable synchronization of RX and TX sections */ $ R9 [. |; g0 j0 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 f( |4 g8 [- N8 N `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" e, L4 u# M+ I! K( E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, n4 b- N7 c/ R0 h7 _ l! e
** Set the serializers, Currently only one serializer is set as( l% u9 F ?: W W
** transmitter and one serializer as receiver.
: v# C$ a! Y# {9 V0 j" m0 N7 B*/; e6 B8 r% X6 H2 m' i6 ?7 {7 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) o( q4 p% n( V2 SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% O3 j" D/ R( F3 X7 h: P
** Configure the McASP pins , o2 o, [6 O/ c- _+ I# G8 d
** Input - Frame Sync, Clock and Serializer Rx
1 t' n6 ~& d0 k, A** Output - Serializer Tx is connected to the input of the codec
g' Q# D) X# b: e*/) o- q1 T7 P3 s/ @3 x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 I# C1 q, ~ h2 W G, S' \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" X% F4 W5 b. g2 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ n2 V' {. Q; S| MCASP_PIN_ACLKX
# H+ e6 Q% _6 `7 L7 P| MCASP_PIN_AHCLKX
% L7 z7 G( o! |7 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* n, M L. o7 I4 q4 |1 _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , U. Z: ^; L! T7 w. U- c1 J2 Z
| MCASP_TX_CLKFAIL
; {/ E K& O1 O| MCASP_TX_SYNCERROR- L! ^# N, T3 M4 D/ F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& a" [2 ^( l7 c _/ B& _8 i| MCASP_RX_CLKFAIL
: c3 }) Z6 W7 m| MCASP_RX_SYNCERROR
' p( B1 r( w0 Y5 T9 _9 b `| MCASP_RX_OVERRUN);# r% S- J3 A3 @) V
} static void I2SDataTxRxActivate(void)
* h) r1 W, G8 O- e( K{
J5 }1 q' ~% u) } k8 w+ [/* Start the clocks */
* g/ i) ?2 }7 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& h2 D" b* S9 B3 C V o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" G1 R/ _ n3 l2 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, `7 B. n% J5 B% d0 ]5 Q7 x4 i- SEDMA3_TRIG_MODE_EVENT);
& {# r4 r9 X- W' U, P* g- E8 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, F* B/ L! ]. f5 I' F9 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ T8 i! a r' M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 N8 i4 C+ Z+ U0 n. n6 ~+ G' e0 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* K4 j" h9 Z7 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) d* _( F* B2 `8 q' j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 ?9 d+ g" r2 Z- @, V. s7 k$ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; l6 V0 R6 k! \1 G C: J
} 0 K K1 }( _/ o/ ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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