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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: U( |4 N7 F( k( `9 m5 `- G( s8 q/ I
input mcasp_ahclkx,
0 `6 j8 `) ?( \1 yinput mcasp_aclkx,
0 q M6 } s% sinput axr0,
; x: u& u+ ~3 A0 c$ r' s1 i
1 g; J5 I1 P( Y$ K. l" poutput mcasp_afsr,
! u w6 u, H: ?output mcasp_ahclkr,
) ]8 `4 Q* x1 L+ K9 O) ^2 {output mcasp_aclkr,: l) R+ ]) A& C- w' B9 K5 m
output axr1,( P6 D1 t0 q9 w0 @
assign mcasp_afsr = mcasp_afsx;
0 P; E W0 ? Q+ a: }" B8 g% O. tassign mcasp_aclkr = mcasp_aclkx;
I( i& J9 d) o* H aassign mcasp_ahclkr = mcasp_ahclkx;
8 q. L a7 i! P. t ]assign axr1 = axr0;
' v+ O7 S5 v. [' R4 ~7 C5 ~; y) T
- P8 `) @7 M) x" A% b/ L. g" I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% W2 M: K. V9 u0 qstatic void McASPI2SConfigure(void)) r7 u$ [. t3 Z* |5 ?
{
7 m3 }, Z, |0 i$ VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 ]0 K: c @" ?1 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& x$ T& l6 \3 \ k- A6 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' L* U6 E3 X/ z0 ]) U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 E4 v* o) w8 I+ I% h. m% M$ jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 z9 _ n9 S/ s. ?& @5 `3 a) O! u! G
MCASP_RX_MODE_DMA);4 L7 r" r4 A/ h& m3 ?6 }/ M: h/ ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ {0 F- E( f( z1 v& Z( A+ AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 _. q# Z7 I# q6 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , L' k7 A1 B( J$ Z/ k! s, C0 l/ E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 u: M' p+ y' b1 }1 L; C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, q1 \" v$ @6 }0 p* s' zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 t* [" o: z7 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' A9 E8 g+ u: {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) k1 i0 d2 b+ ^3 N- `( K* P! K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, _& l$ r4 F; p" U% t- h5 ]
0x00, 0xFF); /* configure the clock for transmitter */
( u, S# p; O( H2 j7 y& T8 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( f# x; v9 A2 I- N% L+ C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : w: I* g; u6 \' u6 M7 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 t0 h1 w4 s5 b
0x00, 0xFF);
5 a5 [. Y& F! X% T+ q& `8 t" Q3 S# n6 o8 V+ `2 a
/* Enable synchronization of RX and TX sections */ . E: c" f2 W9 [' i5 k1 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 w9 u6 e+ l, u E& H. ?4 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( i2 z, O& |1 l) I& v( \6 t# ~/ u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 c. k: h, c6 b: @* }. ?
** Set the serializers, Currently only one serializer is set as
" r: E1 |9 y( P: V; e5 p** transmitter and one serializer as receiver.- i- j V9 D# B" V- U k" {( w+ ^
*/4 [3 ` s* T. H. b' Z- M" J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! D* G2 K9 [7 k# R1 m+ {5 W8 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! `) v( c8 R, O- ~1 P ^. @& L. O6 E
** Configure the McASP pins
" V* q2 j! r) n- ~' J** Input - Frame Sync, Clock and Serializer Rx
* Y$ r; N4 J9 C- l# ^! ?7 T$ I** Output - Serializer Tx is connected to the input of the codec
. ~! U, @1 m6 u*/: E6 i9 N6 m. c' _9 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: C1 |. ~8 j% y& N0 c2 L4 T/ U d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; S) ?2 Y* |9 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' O9 }9 }" P; b7 n* O/ V: B+ ?2 A
| MCASP_PIN_ACLKX
9 e4 ~) k% H: I& s+ i; D1 E| MCASP_PIN_AHCLKX
+ @: L( l+ p' A0 Z v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
a9 H. @4 r1 U: H2 ^' t# x$ uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 W) b! k# x( d' C" r* A- u| MCASP_TX_CLKFAIL
% k+ ?2 L* `: x, _" [| MCASP_TX_SYNCERROR
1 {2 o8 S0 P1 A+ k5 U( [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 c, l9 {) B6 o6 [6 @" h' f
| MCASP_RX_CLKFAIL
6 X, j/ b0 n/ u5 w| MCASP_RX_SYNCERROR ' ^; j6 v' @) a2 K0 |
| MCASP_RX_OVERRUN);
5 [/ p. e% F$ Z6 N% S8 u$ M+ @} static void I2SDataTxRxActivate(void)' b9 L/ E/ ~9 }
{
- C3 Y0 ~. o/ O0 B/ i$ [/* Start the clocks */+ Z1 l& e9 ?( |0 Q0 O# l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ k; j. o' T, }7 f2 [$ Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. A$ _1 o3 a, S( |1 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( Y; N' F, T# e5 W2 b% w
EDMA3_TRIG_MODE_EVENT);- `9 r, Z5 J( Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 Q) `$ S: S9 l2 Z5 ?1 A: P* N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- {) z' [, q5 jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) Y4 M8 @, n- U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 ?9 N3 P2 y) F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% ^$ e- @ x: r! {( g' U9 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
t& z- z+ @& k, EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" c4 {5 O& L X; C8 }+ I2 {
} & X3 [5 U |! Y) }+ a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) r. J% m. M; }' p! f. U
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