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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( N' v6 } w1 uinput mcasp_ahclkx,
) u$ W- L, J/ g" _9 |/ cinput mcasp_aclkx,
6 ~2 N: e$ U7 o7 J) _- ?/ O+ t( linput axr0,7 L4 _/ m5 U- [; r2 a* L; [
h+ ~1 L; a4 ~- X& _- g5 Soutput mcasp_afsr,
5 F9 ] J5 u, _9 N2 m( qoutput mcasp_ahclkr,
2 p# R( q: x6 j8 ~( H R$ Poutput mcasp_aclkr,. K) t2 k8 ]% b# |. G
output axr1,
3 V- M0 F: V7 ?1 y$ I. e7 I- ^ assign mcasp_afsr = mcasp_afsx;
, \. j2 r& s5 [ l- [, lassign mcasp_aclkr = mcasp_aclkx;
5 x2 V6 }# x8 Q) A0 S0 L2 lassign mcasp_ahclkr = mcasp_ahclkx;, j, K3 r$ u4 Z% d0 [$ Z
assign axr1 = axr0; 1 ]- e/ J/ y7 d" C
) ~$ ^+ j$ q1 _6 ]- w! F' N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- x4 i- r: c' r" F4 [* e; Wstatic void McASPI2SConfigure(void)! g; m$ W; j, U; d" ^) W4 J
{
B$ Z* I. T! |McASPRxReset(SOC_MCASP_0_CTRL_REGS);) p& i( L5 `- m; M, {- V# x1 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# ?4 T5 A7 {7 X9 l7 x8 q+ V; [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 p% o2 s1 R' QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; T8 I& c h" _7 R2 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) Q1 }% m8 Z8 B% _) v. V$ GMCASP_RX_MODE_DMA);
* m& [; V! e* \; @# ?0 K- aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 @+ h& m: K2 ^$ Y7 {8 {' n3 p4 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 i; ?0 p$ N; n; ~" @, G5 Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' o8 y4 O- F% @$ \* f/ h6 i) VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 w q \, _5 [* u* }! G( \* v5 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 W9 F5 S/ L2 p$ y+ S2 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" Z6 p |8 H+ t( ]- W- r Z/ zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 }& f |5 D$ _, i- X5 lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / N2 X1 i5 W# T% {! e; g# L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& A) I `5 }* p- u) X4 `
0x00, 0xFF); /* configure the clock for transmitter */
( E0 _& I4 ^: WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ K5 a/ Y5 Q2 ]4 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ F; K6 M# e X9 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 ^# m4 A8 B! D& v( g( [ J l) i# `7 A0x00, 0xFF);( H& }$ R! |8 d) W: I, a) _- R
$ d4 O' I S5 y' ^5 k5 b. u4 g2 a6 n$ i/* Enable synchronization of RX and TX sections */
! S1 p; u ]4 ]7 [& e3 H: ~* tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) R) i- t" S6 D* N. q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 [) S( t+ o6 ]) B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, X: _' W h, D1 o1 O }
** Set the serializers, Currently only one serializer is set as
9 p& u3 x8 f% A/ l- C( v+ G** transmitter and one serializer as receiver.
: \4 @( R8 V! R% A*/
7 c/ f0 j. \ P# J. P2 L* s& dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; J" F3 i7 }, P! GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 S$ E+ F `+ |( V** Configure the McASP pins 7 w- v/ Z! Y0 M
** Input - Frame Sync, Clock and Serializer Rx
8 y. m; U9 m5 |. T: ?** Output - Serializer Tx is connected to the input of the codec & j. l; V% ?. g3 D/ W! {
*/! R5 v1 R- q% U% m. e' T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: y# x/ S2 T: c, X8 }8 Z) lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 m% N$ _. r; i8 K& N5 [( ~! j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ p* u4 P' R, v/ P! y
| MCASP_PIN_ACLKX
& n4 I+ v, {6 v H+ N7 x| MCASP_PIN_AHCLKX
% V, f3 f7 X( c$ d) b T4 G- v+ I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 V( H, l* X0 `& A) }0 t3 B* `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% D: Z& s+ P9 o* Q) y" Z. w" v0 A; X7 Z# X| MCASP_TX_CLKFAIL
. g' h' l6 g3 @/ T. a| MCASP_TX_SYNCERROR
- J* p4 G, o8 G: z8 o1 }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . ?, ~) c+ Q7 p3 G
| MCASP_RX_CLKFAIL* D1 q. \4 n1 F ?
| MCASP_RX_SYNCERROR
- H7 o, q. F( e& O2 }* x| MCASP_RX_OVERRUN);
+ I6 r( ~$ {! F- E} static void I2SDataTxRxActivate(void)8 p1 I4 ~& Z: L5 K
{0 _+ G! h8 d/ |. }1 O! K
/* Start the clocks */7 {$ b J- w! c$ A5 }2 H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. A% _1 y) O1 }& [) {) l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- b4 c/ y3 X( VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# B9 r2 D1 u1 dEDMA3_TRIG_MODE_EVENT);
{8 _7 C8 W# z6 l3 v9 |+ gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ d! U, |+ S2 REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ u1 Q& {: B/ Z( w0 A1 | C. nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 T5 I# U: J/ @/ S8 G+ k7 p/ @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 i0 `6 l6 Q. ]6 N1 H7 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- V( f# @1 U6 Y1 w" j0 gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ R4 b( @. l3 t7 m( f" @, M- m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- w( C' q: M9 B$ k& X
}
' d8 c3 h& ^& y9 l2 n; a+ I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & @1 @# N3 w X* i8 z
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