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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 c( g/ ^- s! @' B6 G
input mcasp_ahclkx,
0 N, n. n1 t7 W4 R$ [8 L& Hinput mcasp_aclkx,, Y: @4 P; z4 W
input axr0,
- M! G A9 z. i: D6 g: ^2 S1 O; {: f
9 O, a% b/ U2 ^9 Q0 U+ f; \output mcasp_afsr,
]3 s" `+ q8 S6 f3 w Joutput mcasp_ahclkr,+ {: }. Q5 P2 W
output mcasp_aclkr,
: M! t2 S4 f6 r7 Routput axr1,
( m$ A0 B$ _- Z. J* |6 z- |( X( y assign mcasp_afsr = mcasp_afsx;
9 f$ k3 @! ^; U) u0 `9 ~, Kassign mcasp_aclkr = mcasp_aclkx;
' I+ K0 ]8 }/ ^3 I: z' O) F. @assign mcasp_ahclkr = mcasp_ahclkx;
: M$ g- f3 Q( T/ g0 M3 u- T& `$ T5 Tassign axr1 = axr0; ' V# ]& O4 M' P( s
& }9 `3 l |9 r! j( j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! @; W: H/ Y# Astatic void McASPI2SConfigure(void)! n3 T9 J! k# v: m, s( P
{) F, o1 H) `; { p. `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 B1 W7 _" x1 S" E* @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 I2 |9 Y+ L- R# u1 d7 D0 K+ EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 \1 B/ }" l% }) g4 g+ ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" y; W8 t+ p- E# m" kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 G1 d# W7 u& _; I7 K
MCASP_RX_MODE_DMA);
7 V3 a5 Z% W$ D, r/ KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 l: p$ {8 K4 ~3 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, |$ H9 S4 D( d, PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 C' {* G) w0 Q* }) k% Q, a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) y4 B8 L! p+ ^$ u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) @( M* |0 M; k# A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* W1 x) _$ m8 {' l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 z- m$ v. L- r( N- g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 b/ q, v6 t$ S, A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, p7 K& ]; [& M8 Q. U. H+ v
0x00, 0xFF); /* configure the clock for transmitter */
' n2 L& O2 a/ B' z! d) M: pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. o2 k( |7 W- w, KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
j# T! |' c9 B) I6 GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# h( _1 }. c# a3 r9 v6 L8 w
0x00, 0xFF);
% x! ?+ T, k) [- @ W! u0 A
/ ], U3 b* a j' k, l5 d/* Enable synchronization of RX and TX sections */
; r3 Y8 e2 A" x5 P% nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. W) p5 }0 ^8 f# lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 \- |1 @" s- w) W7 w& w1 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ k$ q& e$ I) T% L/ O$ Y: O
** Set the serializers, Currently only one serializer is set as$ I2 q- M! h! _ v6 @4 \# `
** transmitter and one serializer as receiver.% V) v/ u6 x h/ m
*/
' u% Z: r" W+ IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 [$ \5 Z4 Z+ @- C" P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, ]3 y) J! L3 S! |" k; {/ V" k/ a: ~
** Configure the McASP pins
/ S8 }" H$ F; \1 \: ~** Input - Frame Sync, Clock and Serializer Rx: b7 H+ q( V0 \# R" }1 `5 Z
** Output - Serializer Tx is connected to the input of the codec . u! f+ r/ I1 [ u0 I7 ?% a1 ]$ H. T$ V
*/
. A# N% ~' W i4 X) N+ D: R/ C9 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 P+ `% c7 ]+ O3 s2 K1 y1 m1 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 w; _ [3 g& k/ {# s! kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: c& c& A0 E$ M& i- R( Q& ]| MCASP_PIN_ACLKX
& G6 w, i4 j3 X| MCASP_PIN_AHCLKX
, B1 D. |6 J) C6 ?2 q2 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 P x2 W" o$ Y! w% D. c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* `- `6 P2 G2 K8 E$ C1 m| MCASP_TX_CLKFAIL / p$ y1 a8 i6 o% c% O5 E( S1 T
| MCASP_TX_SYNCERROR
7 J! [% y. }0 x/ l# d C0 H1 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 U x" R1 |: D; v, l0 _( h
| MCASP_RX_CLKFAIL# }) S" k. Y3 L' O* r
| MCASP_RX_SYNCERROR ( U% {0 k% x l
| MCASP_RX_OVERRUN);
) \& F9 N6 p! ^} static void I2SDataTxRxActivate(void)1 E# G1 C# y( M# X/ d7 \; M0 R/ \! i
{5 C: T- {" F4 E4 B( L0 Q
/* Start the clocks */
4 f+ T7 c1 N3 N4 m) tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% U" ^* `% ]( n4 M5 n- p2 E0 c2 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. j- L/ n+ l! g! A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 _1 J1 Z" k$ ^, @5 Z0 }EDMA3_TRIG_MODE_EVENT);, x. O- a+ E. M+ m0 H5 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " X5 }8 k$ e; S! S. m( q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ ^2 n) O' R/ y; K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ [: n9 a1 C6 E+ r# y3 ?7 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, `! Q- B8 y% l% n$ Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ E0 Z6 w3 R1 Q. a# A# | bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 N, r, D; f5 E7 v$ V* }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
i w- G J4 ^. Q} " R$ g/ p; K2 E5 {7 `+ z3 N3 [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + \$ ?# `$ B$ k: Q) [- u
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