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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: _7 Z8 o3 r. a1 b/ R
input mcasp_ahclkx,
, o; j. Z. ^8 \: o; Q+ h7 sinput mcasp_aclkx,
$ r0 E; d0 q" B3 M6 m7 cinput axr0,
' R# j( m, g3 u3 c1 r1 X. [ |0 D
9 Z- B5 ~5 z% [' l) h; U% Moutput mcasp_afsr,
4 e/ X$ x+ K( t# |output mcasp_ahclkr,- d1 |- q7 Y* D5 S: Z
output mcasp_aclkr,
0 i, N/ c+ Z- A) Houtput axr1,4 I* q A% l( ^7 W! A1 E( {
assign mcasp_afsr = mcasp_afsx;
5 d+ f9 g) D0 H* U) Sassign mcasp_aclkr = mcasp_aclkx;- |7 V; E% B+ s+ M( b. ~
assign mcasp_ahclkr = mcasp_ahclkx;' }& C' f. z) a$ `# S+ x) v, v& [
assign axr1 = axr0;
. Q5 p8 h9 O6 J1 V: D& ~
' K& e$ R) j- g. w, P! ?; K2 M Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) U( O7 A; m5 f( qstatic void McASPI2SConfigure(void)
* e( G* l" V, n7 o, F# `{
5 B9 [+ `2 H1 J0 s8 W. Z( j+ U+ KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* ^: S/ U8 z2 C: N5 {# l* [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) j% U. E2 \& Z( x; x* z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, I1 j( z4 w6 F' xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ]/ |5 D: |4 x8 a; [* O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," f! p4 v, W- \2 g
MCASP_RX_MODE_DMA);
4 {8 m3 q7 k4 d1 V& Z8 a+ p( k% fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 p, h+ G/ _- ~ z& _3 d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ^* g4 ?9 I A) a0 Y. A( H5 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 _: n2 ^/ v' ?1 z' c' }6 O7 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& ] k- p+ T) q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . b: B' c( W- e9 {" n5 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 b: E m5 A' f' i3 M* X1 W9 g+ {2 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 @1 e( i; g/ f p- PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # o) M3 w( W9 n" h' y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ F' W6 ^: g! ^) e9 O( p& {0x00, 0xFF); /* configure the clock for transmitter */' a6 w; H) ^0 T- ]9 y4 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( }$ O3 M* ^, C0 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % L% s: b; o1 g+ Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% H& v6 Q8 \( L6 b9 {6 V' e) b4 p
0x00, 0xFF);
5 d1 q* A2 C1 I, N% ^* D! R' ~4 L5 h1 S7 F8 N* X
/* Enable synchronization of RX and TX sections */ 7 y' C! t0 t {, Y3 R: V$ a, Q. {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 d' v+ y1 ^7 j7 S5 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 f1 C* g' ^, V5 H- t& qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 d! {' u$ T* u! T
** Set the serializers, Currently only one serializer is set as
3 j; I% [$ e5 X b* O6 C! |** transmitter and one serializer as receiver.' o6 v0 Q0 u* v) ~
*/
# U* ]7 v( C: { W6 W- wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 S, m: s; x7 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* x5 }1 r2 i9 n+ t6 {& B0 W- z! O** Configure the McASP pins 2 a/ k" _4 d% x7 g, Q* d" d
** Input - Frame Sync, Clock and Serializer Rx* W. e' L4 C8 y" q
** Output - Serializer Tx is connected to the input of the codec
: R- P) h% @8 U; }*/
x; u; x3 p3 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; Z. M2 y6 M. J. y' M Z2 |# T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( @* m% Y. `0 }/ J0 j$ WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( M F8 t. Y2 ?9 y ^) \# f
| MCASP_PIN_ACLKX9 c4 h- R- T! s& T/ i% \ @+ l" u1 s* B
| MCASP_PIN_AHCLKX2 F) \7 ~+ H, r# E* v) S5 p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" o/ n7 v7 ]% F) c2 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " W2 p; I& V% O T7 H( S- |
| MCASP_TX_CLKFAIL
; j2 P& J9 C; x9 h& Z| MCASP_TX_SYNCERROR
* b1 G+ X9 L9 j9 j" R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; {' ?8 |8 ]. j8 w# L| MCASP_RX_CLKFAIL& _" G' c8 g. Z. K" i
| MCASP_RX_SYNCERROR
0 v2 z0 t1 Y! ~" o2 Z8 V# @) w| MCASP_RX_OVERRUN);
( Y( D* l3 |4 B/ t6 ]& k} static void I2SDataTxRxActivate(void)2 J: b. S; Q3 W; [! J3 v! _$ _
{
3 g0 w# w: u( q3 h/* Start the clocks */
! B {. a+ q! {& j& D- B& GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- q8 z2 e7 G0 Q' G1 c' {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, Q0 ~0 g4 U3 c/ \5 j& yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 K$ E& ]" ]+ A& UEDMA3_TRIG_MODE_EVENT);$ n. D6 @3 O# M$ T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ v: d A9 [4 S/ P& P3 b4 B [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ M" O8 F6 t. g8 k R% l0 C/ o) mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& w3 V( C; r+ Y' ?. Z3 _/ [* P5 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, g! ~, x1 k6 f2 c" x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! x. R4 m+ C; U0 K) h9 l2 g# m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 }! f$ Q$ C) D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- r8 Q" B: |8 e$ ~
}
( N# a' R- Q; u6 ]6 g f# R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # |! ]0 `3 K; r
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