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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 p/ K4 T O' A1 Winput mcasp_ahclkx,) V' L) p) M8 R( |- J. h0 d
input mcasp_aclkx," u1 p5 p5 `) L" n/ Y
input axr0,
0 k. Z- n' u1 i5 r: m1 I3 T4 M
Y+ M( ?7 K& a Foutput mcasp_afsr,- }: p. E# v5 f1 w7 s+ ?' d
output mcasp_ahclkr,+ Y1 f( R9 A9 k9 T# L
output mcasp_aclkr,
5 f0 j9 R% E4 Y; p2 b; B0 Uoutput axr1,
3 f# {2 v' v( H& z% c: z assign mcasp_afsr = mcasp_afsx;
: x5 F) G1 w% yassign mcasp_aclkr = mcasp_aclkx;
7 ^# o6 W, a2 |0 O$ y$ ]2 a# xassign mcasp_ahclkr = mcasp_ahclkx;
4 y6 q/ a4 N. E/ C; |3 l0 Y& U1 iassign axr1 = axr0; P" ^' ?: E3 q7 f
& c' [* o- t7 d' x2 C, C2 V$ ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 X" j$ {( q; L8 N) t( Ustatic void McASPI2SConfigure(void)% ?# Y6 @% y- z( D4 k
{2 P& r3 ?! D/ \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 d% ^8 F( W& }/ A# y9 V) k0 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( a; {# H" z' u8 L, Q; p. i# cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: D' Z0 L% v3 F* j3 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 P, s1 ?4 X6 C* V* w2 w( J& aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* K0 c: ~* V8 l' VMCASP_RX_MODE_DMA);
# V& M8 Y3 w7 r( \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
\! R6 u6 W& y+ Z) R& W4 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 Y0 ]1 d6 `9 x# }7 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* D3 N Q6 c7 i% BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 [. F4 z6 O# f7 l& Q4 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 k" T6 ?% @& t4 v A+ hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, n% G; Y* ]. i$ ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, @) ]& @* F* R; c' ?8 ?* _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! e: g3 g* E- O1 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* ^6 h# A3 i5 w4 a5 y9 S
0x00, 0xFF); /* configure the clock for transmitter */
4 d* S, k& M) |- B: m5 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ E2 E) B" T. N" TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 r' w7 l- \- Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 k7 x) Q7 m% V3 r* v: [# e" B0x00, 0xFF);
" ^+ d1 V+ G, z) J% o# y2 L6 c, d6 U: `6 y6 e5 J7 x7 z
/* Enable synchronization of RX and TX sections */ 6 J# K0 O; R2 |5 r+ K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 N R+ }) k( k1 I: n5 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" ?8 u3 W2 G/ H0 | T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) J# M; m% A+ G9 k9 T7 T* V
** Set the serializers, Currently only one serializer is set as$ {9 F: ?. f- d+ u. w3 o; l; _
** transmitter and one serializer as receiver.
) R4 v5 E3 q* S7 Z*// Y. _. Q# P1 { t& r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 l+ Q- P5 }. a+ G$ x3 [1 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) T* o, _5 O9 v2 \: N* Y** Configure the McASP pins / w, e" M+ _2 C @
** Input - Frame Sync, Clock and Serializer Rx
; w' |; u+ ]/ @6 P( W** Output - Serializer Tx is connected to the input of the codec
2 x) q5 i* @5 d; @' h- p*/! f. A3 O6 k" _' O* O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 j% Y+ P8 v P, O* h, \( O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 [$ W$ @2 S, x$ B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* T J' T. X; a" X8 D
| MCASP_PIN_ACLKX7 F# C; @2 \# f5 l$ X
| MCASP_PIN_AHCLKX
+ b' l; S; N2 B$ Q4 N: E3 S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ i) u* t3 ^/ `. ^5 p9 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
M, T7 y, r) C& k6 v" r7 Y) O" y| MCASP_TX_CLKFAIL
3 p& D7 f0 u0 f| MCASP_TX_SYNCERROR! J! j) {. |: g/ J) g( F0 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 Y0 m( q2 c6 J: K/ u
| MCASP_RX_CLKFAIL1 ^7 h/ j& F- {9 @
| MCASP_RX_SYNCERROR ' i- i: g; s' g/ X! Y
| MCASP_RX_OVERRUN);
, Z, j& y; R0 b c} static void I2SDataTxRxActivate(void)
# f1 j) r+ B/ u' n{
- N. V) K1 T6 x' ^' r/* Start the clocks */
- }1 Y5 v; T) b2 ?) |- i+ tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 e* Q' J8 H; j6 E7 D. cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) e$ H; V( y& j& v& D7 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* y. C6 d3 V! N3 e- ]- h5 Z# `! {
EDMA3_TRIG_MODE_EVENT);
: _# b5 M0 O8 v+ ?& xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 U H8 {' y; I) C7 t3 A8 mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
\. H5 V, y' }- Q2 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; w% C ]* g1 b$ s" VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' K9 U0 T7 u4 ?2 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: u( @0 r" u. @* N2 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: c; @2 T" M8 j0 F1 P! a& QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 `6 v1 {, W+ |4 b; ~}
2 E9 c0 I% Z3 O A% q0 z8 a- d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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