MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
4 g/ a6 Q% k4 p5 W& ?9 ]' V
2 u1 `9 ]: t+ ~) B* k3 Qoutput mcasp_afsr,
( ^) S) N8 g( N; A9 J7 aoutput mcasp_ahclkr,
, V! U: I, @3 k) d$ T$ Houtput mcasp_aclkr,
: S' p& B7 _3 Boutput axr1,
5 M  E5 E8 c) @. l* N

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
. v7 y  G* a/ p& e' massign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. S2 D& ?2 H$ F8 ], x' f, c* ~6 q

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
; d2 e' R8 _8 F+ G; N) D{
! d0 k) H8 m4 h- r9 _  e! M$ VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 R3 o% w/ J2 K& fMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
/ r( V& {; w4 g* p! cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# k/ B3 A- P8 Y+ DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ j! F3 A! B- G6 @" b4 q; p; w6 yMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ X# W6 y5 Q9 x" cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 f4 l4 A6 Z. B; s1 J9 FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% f' y, Z- V: p7 {6 C2 W' H; v" a, GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& G$ h: \5 ?1 o; I! u7 @$ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. L' @% O# c2 ~9 W( p0x00, 0xFF);

/* configure the clock for transmitter */
' l9 n& y5 g2 l% X3 \. f' UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" i/ L! R9 X& QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% n5 f' T) O6 r: }" F0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ |$ Q' o* D) ]. I8 [' PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
3 a0 s) G+ K5 S+ p" D' L4 c3 B** transmitter and one serializer as receiver.
9 @2 O1 z2 ?: ~( A$ x. E*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# C1 I3 ^5 x* w; CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
& M+ `/ f! v! E% T8 W. D** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 @* F% I: Z: x% wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 u0 w# A0 o3 e* `/ y/ {5 S| MCASP_PIN_ACLKX
. |; i/ q  _6 Q2 O' i| MCASP_PIN_AHCLKX
9 g- x5 Q1 R+ ^1 Q) J| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 t& w, e: d% N: M| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
: `! k' L+ j1 c) P# I| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
6 L; c( g" X1 Z{
/* Start the clocks */
% W/ {! v. u5 V+ I, z! d6 D& }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) t* ~2 b! X! K8 W5 @" WEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
; g( ?( r$ z; p7 f( J1 r; w$ SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
1 M7 ^. b% @, |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& ~3 M, g9 h1 V* J}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.