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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' f0 }# ^5 h$ P
input mcasp_ahclkx,
& `" e0 g3 J1 P$ L+ M3 m# Ginput mcasp_aclkx,5 F+ L2 Z- J( p6 {# o6 X/ q0 E
input axr0,
0 L4 S4 u# u0 A; w0 N4 i0 f$ V% w8 s; y
output mcasp_afsr,4 v5 v- z F; f8 R8 Q% l9 H
output mcasp_ahclkr,
8 |6 X' C9 o+ s& youtput mcasp_aclkr,: d6 }: _0 f8 y
output axr1,
! E! w* t% C6 C0 r1 W/ v" k0 u/ \ assign mcasp_afsr = mcasp_afsx;1 _$ ~$ X* }! s& }. y
assign mcasp_aclkr = mcasp_aclkx;
4 l0 G# L" ?8 {0 b% iassign mcasp_ahclkr = mcasp_ahclkx;
- ]3 m: o, s7 r& K* z' bassign axr1 = axr0;
& p+ x, R* j( x5 a& W7 X. {( ]
~2 S( l- ^+ d4 a; e* ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! y- D* g$ S/ vstatic void McASPI2SConfigure(void)
0 [( x6 K8 p; a9 K+ Y{
: I5 R) ? [- J) Y5 A) n* L+ |McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 e) g% L& _& e P6 o, d4 U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 }; t0 X% B$ ~/ v! ~, I$ RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& \3 s) ?: N% r) }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 e6 [. c3 j* r7 o( n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ~1 f) h$ t, Z( z6 T& |
MCASP_RX_MODE_DMA);
9 X, x& n8 e! E7 B. \, X+ XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 P- B3 g. \. G- b0 P( M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ P) D& {) _5 b* Y- @ W YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' q% s) F" P1 s! q1 {+ fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* G% z, Y, x; `. N+ L; a) s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 A& b8 b7 ~! v `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% o6 r ^6 t9 g! j* NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& [' L; `! |$ H4 r& F, uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 r# I* l! m5 J3 U* L2 z: z! J' h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 o( E8 N& S- ^. ]/ n. K
0x00, 0xFF); /* configure the clock for transmitter */
( E- Q( j+ i8 K2 d; `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( l2 d# h( Z: g' K* K P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ ^9 ~- x+ T+ R4 V* P1 C( ^( NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, N# L% N# `& v$ ~" E# Z+ u& @! l2 S
0x00, 0xFF);+ v5 T% g+ F0 x0 W
6 T0 U* ~% O6 Q$ h( p
/* Enable synchronization of RX and TX sections */ / o5 U' C( j5 j1 I/ G, B6 h* L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 k; e8 X5 X) c6 _) y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 q8 R. D" k) i) Q7 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; |: T/ n+ l* _7 i8 b6 }! h; J
** Set the serializers, Currently only one serializer is set as- k/ j! T' \- ^$ n5 ~
** transmitter and one serializer as receiver.) g3 j7 n; U8 ^2 p0 F
*/! i) J v9 }9 J, b; J. l+ T) {& Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* P; F' v, L" G: w$ J3 m# v0 y+ B+ l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, _0 z$ W# B+ e, Y( N" U, H/ U** Configure the McASP pins
# l4 K- i: \ A( Z** Input - Frame Sync, Clock and Serializer Rx
' Y; f, ]4 A5 d# W" e+ m0 A; n** Output - Serializer Tx is connected to the input of the codec ! n2 |4 f/ |/ b6 k. P
*/
/ E, R1 E T/ ~! y/ c5 o( N* ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 M# J2 y# O% u M6 y: DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 f7 o' P e. I6 b+ BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ r. y1 f* E6 U3 w% N7 ?| MCASP_PIN_ACLKX
3 _1 [& x+ `- b: g0 @# e) [% C& A0 ~| MCASP_PIN_AHCLKX* p5 M* [7 S. A) D7 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 B' q3 w" X6 u* _4 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 H" G8 {* c" o) |1 t, b9 i* H) o
| MCASP_TX_CLKFAIL
; J8 k. f9 ?( x, Y7 w| MCASP_TX_SYNCERROR
1 v( _6 X9 G. k% r" U5 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 A, `4 G1 y/ ^% r| MCASP_RX_CLKFAIL
& V' `% R7 s' R| MCASP_RX_SYNCERROR 9 K9 ? }+ |5 g5 _; K
| MCASP_RX_OVERRUN);
C5 Q0 Z3 Z& E- O7 t, p} static void I2SDataTxRxActivate(void)! e3 C, ^9 a$ D" N# H! V$ \2 _7 y
{
3 Y! A& A+ Z y1 S% k V/* Start the clocks */
% }4 C. a( X0 X5 W1 h4 J7 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) ?; {. n6 f" l- E% `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% S/ o8 h, F4 g) n# I1 m! r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& s' j. Y `+ c; J
EDMA3_TRIG_MODE_EVENT);
8 R, I" T4 p: N: Y# `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 R% Z+ I% b q: m+ c) G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: v9 x+ h% f$ TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 n& u1 J. U, }; }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! Z7 c3 H& W. P# q; `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! I" x; z$ f- z2 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, y! Z9 |5 G/ F) z& o, D( aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! I4 a0 @7 U7 [0 \" Q3 Y* p
} 9 |8 H7 X1 j; o _$ d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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