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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& O$ J7 d" G; Y8 [0 \
input mcasp_ahclkx,
# J& J* f& |3 u7 {input mcasp_aclkx,
+ V1 m5 `4 l7 x, I3 P+ d" H# ^input axr0,) U5 Y; f1 z1 a2 F, ~. |: L* _
( I# K$ z |7 e. b# v% H2 j; [output mcasp_afsr,3 |! ~9 F; _# b
output mcasp_ahclkr,3 F0 U5 m$ B6 p4 T
output mcasp_aclkr,
1 H$ L& O6 X8 a$ Doutput axr1,- I/ e0 t" d8 C
assign mcasp_afsr = mcasp_afsx;$ a8 K. s( Z6 _% Q( r' |/ D
assign mcasp_aclkr = mcasp_aclkx;
# Y3 C4 U* f2 rassign mcasp_ahclkr = mcasp_ahclkx;
& T) |$ Q7 K, A# Nassign axr1 = axr0; : A8 S! o2 E$ q6 s8 ~, f
. s n1 m, d3 b$ c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 o- Z# c4 t; s- t+ _7 J8 e
static void McASPI2SConfigure(void)$ t: A! Z) h6 j0 j; q; }$ D+ ?
{7 U/ I N$ U) C0 l6 K0 X2 S/ J4 G+ C/ E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! e; p4 M% N. U4 i0 J5 K# e8 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! Y; y) E2 |. \/ W5 A+ k4 k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) n8 ]. x3 [9 x/ R3 Q* {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 q" X) w/ t# {. JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( Y1 S" R+ n9 W
MCASP_RX_MODE_DMA);
. [ H8 [* ~- z! yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
N: J! B' V0 }$ i+ P+ I# DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, y3 _- K) a5 Q4 Q* W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! `2 R3 D9 E7 a8 M i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: F, B+ ?2 O$ q4 s$ n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. M) w: t1 I# I7 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 N* ]5 ]6 w/ h! F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' K$ L1 |9 p8 L0 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , y& @8 j2 l2 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ U( e& x/ X- ]
0x00, 0xFF); /* configure the clock for transmitter */' a% V( ]8 c; y, G( {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ q8 `) ~4 d6 X8 |$ F% W6 e) z$ { W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 K7 G, S. Q2 ~# I+ z/ L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ d4 z$ P+ g- [0x00, 0xFF);3 [) E' y: x3 L
* q3 e. Y% H6 B O- C; k/* Enable synchronization of RX and TX sections */ , |; o) O* a3 ]7 p- I# A' {8 J1 `) M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 n& O- z, _. L- ]+ Q4 W, K5 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 l" C! u1 r+ v, p8 \" bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) x' u- f$ V. @) O# l `4 o
** Set the serializers, Currently only one serializer is set as& Y9 Z; e# K: k# P
** transmitter and one serializer as receiver.# K6 m- [: F* Y4 r. ?! j. X% z X
*/! {% w1 G b, ^3 m+ Z/ [8 {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 Q" d# X7 [# Z5 a, P+ M& B6 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 F) P4 A5 |! T
** Configure the McASP pins 6 ]& B q* W( d8 L
** Input - Frame Sync, Clock and Serializer Rx# a0 j5 L; D, q# S; I& S
** Output - Serializer Tx is connected to the input of the codec 0 G, i+ ]/ \, P. }
*/
0 c: F e+ O9 H- f2 e: q- oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- |/ t! u/ |: w7 o/ R& W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ k8 l3 G) F2 N. x/ B! ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 H6 \( d% ?, i g- S| MCASP_PIN_ACLKX; s, R I4 H& d1 ~
| MCASP_PIN_AHCLKX
r. g: ^$ b4 ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 V+ M1 y, k; Q+ \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . z, }8 B f, h4 z- J' }* M2 h
| MCASP_TX_CLKFAIL
# k' L# \% A. Z$ D3 _; f9 t2 ?2 }7 x| MCASP_TX_SYNCERROR3 w r E5 H0 N1 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 }3 r9 ~- x- e4 C
| MCASP_RX_CLKFAIL
) o: @8 @9 N/ _ e% `( v0 M| MCASP_RX_SYNCERROR
+ [( _+ K$ @- }' E( e, b| MCASP_RX_OVERRUN);
3 D& F. j) F) G* Q, ^; E} static void I2SDataTxRxActivate(void)
9 Y; z2 @# v7 p2 K, A{3 R/ n5 S- K& v' ?( ^" @; m! m; l r, E
/* Start the clocks */
; D" M7 _; r+ Q$ t& SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 A6 ^7 d0 B+ x/ V7 _2 T2 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 H4 }0 G7 E# I8 g- i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" x Q3 _; E- y, o: a4 AEDMA3_TRIG_MODE_EVENT);. P1 K8 z4 m4 x" d( U" [6 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 T3 ~, H2 I& r `+ ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 ^' C$ B3 n; t/ m$ j+ [8 ^( I6 l) qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ~+ x+ }; `# j* o" g; ~% jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: q& |4 R& m: \ p; V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- I$ G0 P$ K8 c$ B2 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 G$ C& E# W: eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' V$ ^+ P. j4 q
} ) m5 d2 u& X+ D; e6 s6 ]) p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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