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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: |( @8 p3 K. F* {# V
input mcasp_ahclkx,7 j( |0 \2 G/ w0 ^7 Z- y! ?2 |
input mcasp_aclkx,
0 L6 e* p, k: Qinput axr0,
, c# l6 F! e, Q! w' o) j$ k1 L! X2 ?/ \5 O* \
output mcasp_afsr,! q$ g0 u* x8 J, J$ s
output mcasp_ahclkr,
6 ^/ Y+ c& K. zoutput mcasp_aclkr,2 K6 }( b: J" b
output axr1,
+ n& R( l2 q* v1 E: G Z assign mcasp_afsr = mcasp_afsx;
( D" D( S! o3 z( D' Sassign mcasp_aclkr = mcasp_aclkx;
- B9 p3 b" j3 q U; \# ]3 A- Wassign mcasp_ahclkr = mcasp_ahclkx;
. n9 A. j& F/ u1 E& bassign axr1 = axr0; - }+ n3 S5 d$ g
9 p' a9 C- e% M4 X2 ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 `" l! ^0 T4 U E, x: ~ ]
static void McASPI2SConfigure(void)# m$ ~& E5 \, m' ]
{
9 E N* Q) ^- [; l, HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ f/ r" t4 m( w5 N# z6 G8 S& bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% b: @, W- V0 j0 |+ a" H. Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# F% F, M+ c' D1 j, k/ W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 s4 M- c8 @# J: p7 G+ z! NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* i) A& c) c& {+ K* _6 EMCASP_RX_MODE_DMA);
F7 k' C5 n" \8 ~ o; ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 F7 s* U* d2 {. t2 X* k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 p4 r* F7 k# p" N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) R5 t0 a# U- R- F" w# [' sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) F; S" v3 Z+ `5 R2 v5 O4 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ p, M% w+ r# B3 H0 |, {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' |8 `& G% s ~5 D" H8 B( n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' ]# g! X" V( s4 D1 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( r( o3 P p9 p: B9 |% x" ?" e3 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: K1 q: K8 a) c* O2 B9 a4 K
0x00, 0xFF); /* configure the clock for transmitter */
2 S, p+ G% y( h8 P" VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. w& e5 d6 p2 Z! R- G$ u1 z U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 b/ d4 ?$ @3 S' V! G3 E; \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( M4 H9 T- w( q* l5 F: O0x00, 0xFF);0 E! I Y& C, P1 c: w e& G4 m* B
; F. u3 o% m/ \, x0 ^2 a: G% ~( i; w/* Enable synchronization of RX and TX sections */ + k- M. W! j( K, G4 L% E5 B) r; k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ W) S* V8 u1 I3 G8 l+ @+ E; D2 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 x! O, v: N0 ?4 ]- VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 P% X5 m. {4 L** Set the serializers, Currently only one serializer is set as
3 ~2 F5 J6 s. w+ K1 ?! k; e** transmitter and one serializer as receiver.
L; R8 A9 u$ M, B J8 u! B*/0 g0 S: u5 Q# l$ c9 V* `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, G1 F4 x: e: A' F; ~4 F0 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ W; u4 n) O, |$ [9 t% o1 J: A5 O
** Configure the McASP pins
! y5 o" ~# q( K7 ^** Input - Frame Sync, Clock and Serializer Rx. L; T, v S) G7 n
** Output - Serializer Tx is connected to the input of the codec 9 G4 Y5 ^2 S( `6 E% \ q
*/
( ?; f! `: o8 O1 y2 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- O6 Q1 j$ d/ M, HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ M1 C/ G+ K' N5 ^( q+ e6 H5 u; W) j+ hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 Y5 T( M2 P1 m7 L- C8 X, || MCASP_PIN_ACLKX: {8 ^: f% l7 Y0 o" D$ O3 u {- p
| MCASP_PIN_AHCLKX4 L: j5 J0 @, J* w9 T7 Z9 K L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) I* F2 T+ ^8 X. a8 p* p* K( } XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 g* l) t* v! I, B3 ~8 y/ S| MCASP_TX_CLKFAIL ; q& q; G" h; b# F
| MCASP_TX_SYNCERROR
# o2 j2 A0 P$ J# W/ e. d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; |; Z4 i9 N" l0 k p5 G
| MCASP_RX_CLKFAIL
5 Y' P, L# q4 H4 m. g8 I+ I8 i| MCASP_RX_SYNCERROR
+ |8 r' N1 q$ s, D3 I* v' n| MCASP_RX_OVERRUN);
8 T' R( Y0 ]+ w7 {; ?0 P$ t} static void I2SDataTxRxActivate(void)
; |6 f9 T4 q7 F{
6 h: J& w1 y' _/* Start the clocks */$ \" B9 K) p- Y4 n6 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" D6 l1 `5 {) F" p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
L1 r* ?* Z. W: `* o$ Z# WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: m2 v, y+ _4 J: k1 l& M1 {8 G
EDMA3_TRIG_MODE_EVENT);
5 l' s- s5 ~0 |; hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* r2 N. b1 \* e* b% REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// Q: I5 A3 o5 h. r9 u$ E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ s$ r; q5 \4 B6 }, e8 z( u3 oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. I% T' K/ q9 J& hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# R" x* b) F( V j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' a% E" f* B I" H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: |% D' v4 ~4 u& _% k3 H
} : g: X; P# b4 A9 X4 |# F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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