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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ y' ^! d9 Z: Y8 U+ g6 e3 ~input mcasp_ahclkx,
3 \% e, ?) F; A: O1 c( pinput mcasp_aclkx,
& V, K% B' n' [* T' w( X, Tinput axr0,5 L& a. v, i5 ?, c0 s5 [
! C) ~ \5 \8 P" \4 |output mcasp_afsr,/ y, {' P W5 C8 Y
output mcasp_ahclkr,
% e$ h) h* k `' z" M; F! o# Woutput mcasp_aclkr,
, y9 M' o. F! |) ^: z: A9 e, O! A7 ioutput axr1,
8 y: |0 d4 J9 B( f assign mcasp_afsr = mcasp_afsx;
3 [( [3 I# g5 D0 |: |assign mcasp_aclkr = mcasp_aclkx;9 t6 b) M- i ~
assign mcasp_ahclkr = mcasp_ahclkx;# Q& u2 L: x! b0 n/ D- E& ~
assign axr1 = axr0; + ~- p- l4 U% r- M# | O" Q) h
. o# r9 i, K- v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, l# X6 h' x/ P- a2 ustatic void McASPI2SConfigure(void)
5 w) L9 O% \9 R) Z2 f{: L, e s, C* ~" q3 y
McASPRxReset(SOC_MCASP_0_CTRL_REGS); @# j9 S5 K5 h, x" t2 f* g* `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! H8 ^( I: o/ c z F1 Z2 Z, E- x {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); X& X; o2 ^. V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- ?+ L+ v1 S( H% ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- W2 R7 j/ c- t4 E& j" } x- LMCASP_RX_MODE_DMA);
7 h1 e! l+ E) j0 q# h0 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 W% y) A7 Q) V' rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. F! `4 D8 d DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; H& L( R9 c) F3 K. lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 d- ^0 f/ T& o. h1 m- F4 a, _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 D. _. F! \9 K s: H2 s( m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- S& ]9 @ U5 ?9 n+ K8 O( Q w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 @% `$ Y) @! g6 r2 Z L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 Y8 R, {6 Z7 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# b) [$ J% r5 k3 U0x00, 0xFF); /* configure the clock for transmitter */
9 B$ _" H0 R9 u% {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& b4 [) ^3 j- E6 K/ w- Z+ n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) A& `6 Q( f5 |* y' mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# W0 O1 }/ u5 O0x00, 0xFF);
7 w* C* w: K+ q6 R! z$ S. z: I4 t& h# r* O) f) B2 L1 j/ I
/* Enable synchronization of RX and TX sections */ $ T8 K# L( }' [' S& `7 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" n) j2 M/ T" j0 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" @: b; Y' p" c' N" n3 Z. iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 D ^ ]8 v& G* k** Set the serializers, Currently only one serializer is set as- f' ~7 K( D; M* @# O* y
** transmitter and one serializer as receiver.
. ]% `9 V) Z2 d; I*/9 l! j7 F! z* P9 |3 D2 e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 }7 A$ E( v( t" o+ i# X7 S" i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% p- }- y1 w( C4 C/ q1 n- s: S/ z
** Configure the McASP pins 7 U0 h& m% B3 l S7 ~/ [
** Input - Frame Sync, Clock and Serializer Rx- K( X2 L% P" R/ f1 q* Y% l2 G: a
** Output - Serializer Tx is connected to the input of the codec
; P1 } M' g L- e*/* Q' C- ]- I" L0 w' E& N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# |1 L8 g1 T; H- }* oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 B" ?8 r8 O- G+ V0 D8 B( N' v# hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ D E: A# M3 L| MCASP_PIN_ACLKX& e) G- a4 ~3 r
| MCASP_PIN_AHCLKX
' I8 k, I2 l! ^; }5 t5 Y; W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; O6 `1 G4 |! W2 E% g7 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) k( D4 @3 ]7 L; G4 F/ i: H4 r
| MCASP_TX_CLKFAIL
/ M: r8 a- j! |% N| MCASP_TX_SYNCERROR
- v/ w5 J6 d4 C& U4 I" e( S5 y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% ]# G- s2 ? [8 V7 E| MCASP_RX_CLKFAIL: I- l. |( f5 k/ n7 C# D e
| MCASP_RX_SYNCERROR , N0 x7 s, v& ^, c. _
| MCASP_RX_OVERRUN);
6 @) t: b3 I1 w# O% ` i/ o! i& t} static void I2SDataTxRxActivate(void). y) C0 X" [) d2 }" x- p
{
" \4 X+ u0 r) M3 u% h# e) Q5 T( L/* Start the clocks */; I9 }; S- @5 x. y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 M7 r1 G& z- X) D9 r6 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 I4 {' e! h1 G2 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," Y1 p0 i* J2 ], ~# B
EDMA3_TRIG_MODE_EVENT);
$ w, e# q4 m2 P9 d) XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 N, K* h: D5 Q/ z8 _; A2 J( oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: m: g9 ^& d- |# z- r; d0 I" C6 u' oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' c) l4 x N% X. }/ t8 K6 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ Y: {0 Y8 a1 N& x2 c0 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. G& Z g0 t, g" o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# d! E- R3 G$ e1 f1 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. G5 ?% w' N) W0 {" N6 q
}
' N# J# C% Z# E! b% X2 Q" y0 }. a D( [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 v% T, x$ e: C
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