|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: b/ C- F" Y6 k
input mcasp_ahclkx,
& b! j% x0 ^& ?. X7 S/ @4 Einput mcasp_aclkx,
3 \3 H" g* T) i' ? d) Ninput axr0,/ M- a; w" Q+ H& |( _2 K' p
1 k3 R: x% N8 N0 v0 B
output mcasp_afsr,
+ f ~/ }" K* E5 s7 m7 ~5 zoutput mcasp_ahclkr,7 z( B8 H- q" q6 a7 O; z
output mcasp_aclkr,; O# N2 l; ^* z3 s
output axr1,+ ~) z) Y% M( p8 @
assign mcasp_afsr = mcasp_afsx;7 i' z l! I8 O! i6 j3 b4 I+ E
assign mcasp_aclkr = mcasp_aclkx;
1 w/ k+ q% I+ t. V. ~1 [assign mcasp_ahclkr = mcasp_ahclkx;
0 l2 c4 Q7 c; y) N- `/ Q e. Rassign axr1 = axr0;
0 }: K9 X8 f( p1 w) `: Z# ^- M# b; |$ L0 @8 [5 _8 Q m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + J4 E5 v# H6 s9 ?8 s8 |( S
static void McASPI2SConfigure(void)
1 E, {/ V9 M) d" h3 V# o2 A. v{
+ e* ~& @ ~9 G# j3 |4 L) A2 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# K/ V, E6 ~ _3 i- tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 T/ S/ i/ P; r3 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 O7 |6 [ S+ h5 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! N4 ?4 _1 ^/ n) ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( f0 v3 F8 T f! q+ k9 W" A
MCASP_RX_MODE_DMA);
. W6 }9 U; d* r3 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' \8 E- ^6 P7 \: jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( d' u: _2 x! o# n: @" D P9 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 a) ^. o) q! A- U' pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; V4 [0 u, K1 W) o7 [: h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 g$ ]) v# J3 I4 q3 W, P" k7 Y, \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' {5 \# g% p9 Q A5 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' C! n# r; ~3 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 O* t Z" I D- a; ^- ^; vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ x* V! P: g6 Y) b
0x00, 0xFF); /* configure the clock for transmitter */
5 Y0 |# W" \4 f: e, H4 L$ wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 M# e c- S4 _4 L. F2 [/ zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . A8 ^7 Q: a2 m( {5 ~, z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, a1 k- |; e( M3 e q' [* [& u
0x00, 0xFF);0 [1 f4 n6 x+ p1 B" }/ P
1 F- r1 J" Q, _0 \9 T
/* Enable synchronization of RX and TX sections */
6 ^3 ]! R7 v! m8 V6 d1 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) F% _' \& e7 p2 _ Q6 t4 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- J. d: l8 I* Y3 X# s4 d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 u' l& K0 r% c( Q% x$ y
** Set the serializers, Currently only one serializer is set as! H$ }* A+ E% D( s; u4 H9 {# v
** transmitter and one serializer as receiver.3 ^! {9 r/ ]" D2 R5 @& ]/ V
*/
/ {) y" B1 W1 U: kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( x2 d/ b3 p# o6 e1 W4 s0 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 H; [# _! q+ d, D8 k8 l** Configure the McASP pins
2 ]% T3 e2 ]. X/ w& m** Input - Frame Sync, Clock and Serializer Rx% I# Y c( L( }% }
** Output - Serializer Tx is connected to the input of the codec
4 [. q# Q4 T) n*/5 U, s- l; Z0 `# F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" R1 l0 f* G& ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 h: m* G9 U: m$ U7 |) e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; E# H& j) V3 b2 V* ~9 S6 Y; A| MCASP_PIN_ACLKX/ e/ Q/ V3 C! }7 n7 v! K
| MCASP_PIN_AHCLKX$ H" s8 P8 Z4 U m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( {3 p/ C, G' w; }7 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! }6 \# T8 r9 P| MCASP_TX_CLKFAIL
* E$ W2 Y) G. U5 ~) a2 Q" i1 x4 p; H. [| MCASP_TX_SYNCERROR( c: T+ Q1 z5 O+ E3 E6 p; s9 \3 U3 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: D w6 H7 }3 _# z8 S3 B1 z9 G| MCASP_RX_CLKFAIL
! |- U: _1 A6 T' W9 ^6 W/ H| MCASP_RX_SYNCERROR 9 f' |) B2 l w( M1 f$ Q
| MCASP_RX_OVERRUN);
/ S8 }; {3 a" ?0 u) z} static void I2SDataTxRxActivate(void); Q7 z. h- L0 |) I* r
{0 r3 s0 p' Z) ~; K
/* Start the clocks */
; l% s, }) \; {& b8 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; ~5 [5 m q& G/ t$ ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 }5 i% Q* P2 P) k \6 N7 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; L2 D, P, p! p* M$ {5 b2 gEDMA3_TRIG_MODE_EVENT);
& y; O% w+ \1 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; {7 i2 `6 `, _0 U# x FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% N/ q, Y$ \1 }7 T5 d& j+ q" I/ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 |+ K6 E! l9 T- tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ ~: J, F* s5 O# {) t0 K5 G5 \3 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" p! s6 U' J7 S+ {# H' \) DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( P- L2 ?! y/ o6 ?6 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 E% H9 r' s2 g. t}
6 _: i+ Z F! K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
' O# _, M# G; E8 y7 J |