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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# R, E* [0 N) H7 ~! P! |( Y& linput mcasp_ahclkx,
+ `. }& \. X- v+ m( E1 iinput mcasp_aclkx,. e1 {2 W- v1 ~) X/ \! s) G
input axr0,
7 @+ J9 p, M$ k/ { I# E: |; M4 w# r8 X' s( B- S' y, n z2 l# h
output mcasp_afsr,; U& v; v' [- v- _3 f! k( }5 D
output mcasp_ahclkr,) ?/ {" ~$ Z: d, w- r
output mcasp_aclkr,
; H" o Q6 x1 f% v, koutput axr1,7 ^; v4 l7 a4 {1 Y1 x, C7 |6 \1 [$ Y
assign mcasp_afsr = mcasp_afsx;/ O) Q& \. v+ Y0 v6 K% a8 D; Q( d
assign mcasp_aclkr = mcasp_aclkx;9 s- W5 Y- a' m) S. r
assign mcasp_ahclkr = mcasp_ahclkx;
2 m' l( W' `& R9 r* d z3 }assign axr1 = axr0;
( n! {& t( V- ^5 \, Z/ i/ G3 L7 {" w) U+ x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 |5 j; S- C, B0 W e# l" O! bstatic void McASPI2SConfigure(void)
- A- m1 B( K& s, P' i8 u8 Z{- L# Z( u. f8 v1 _$ K& V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* b& b7 j: h+ C6 P. U0 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 c8 ^5 N# {* p- q# h) G6 ?* UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) {! { T4 x: J. {0 ]" rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. t$ [$ |% g7 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! G5 X! B" L: AMCASP_RX_MODE_DMA);
# \: t% Y' Q q$ f, E" J; C( z4 h9 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ _/ _6 H4 ^$ t5 \: YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ i; R/ d) {6 a- k* XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ k1 p Y2 U+ r: d lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 Q+ k M8 d; W C; d# PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* j2 f) \/ I5 ~( K2 P" VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
K$ L2 b( g& ]# Q" m+ vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ G& J* G/ v& k* SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) E4 |4 l9 W+ D4 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ I5 T2 W* B5 H2 w; c q; O0x00, 0xFF); /* configure the clock for transmitter */3 z) L/ x* K) O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ x8 s, b5 z; B/ Y& O& g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 Q" l9 t7 y% w: \$ v$ wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," H# d# o3 P* A; r$ G, _
0x00, 0xFF);
2 c9 e* Q7 y2 }. D$ D; @' L
2 x' n8 K5 d" Z/* Enable synchronization of RX and TX sections */ 9 g6 X; q2 a) y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 w3 Z* |, m# z, H) k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% H) s# O3 i8 R. f$ V3 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 a% o. q. N' @5 Q' ?3 l! s2 |
** Set the serializers, Currently only one serializer is set as
; C. v; {$ n* M1 a. K1 r. p* Y** transmitter and one serializer as receiver.) S1 K+ j, {; X
*/
/ Q9 m0 W. x& ^$ P" QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 Y* j% w) W5 x# F( u+ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! V( S2 E1 ]# p- u) }, e: }2 g
** Configure the McASP pins
, i4 b0 ]! o; i. g** Input - Frame Sync, Clock and Serializer Rx+ w. @' F) h1 f( w
** Output - Serializer Tx is connected to the input of the codec , D2 V/ f2 v, W; ^% |
*/" V! Q% L! E) X3 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 X2 A$ W9 J# k* I" R; `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 ]; O1 C4 _) j7 E" W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 z, B% q, }, i! d* J+ [| MCASP_PIN_ACLKX
2 U0 r* _' ^) ~; D0 b| MCASP_PIN_AHCLKX( q% v9 v. b% h# m; L6 |0 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. f5 y& N/ R& P) lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 t3 }8 w# y, |4 l& i+ Q; p
| MCASP_TX_CLKFAIL
% q- N6 e- W9 R| MCASP_TX_SYNCERROR
) G: c2 `: w& P- q( a0 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ ?/ B: A) i4 l7 |8 s| MCASP_RX_CLKFAIL
) R" N- m5 D! ~2 J5 F9 ?| MCASP_RX_SYNCERROR
) c) x$ `# \) G+ L+ r| MCASP_RX_OVERRUN);
3 U$ z( K4 h1 [# F& _5 W7 |} static void I2SDataTxRxActivate(void), ?3 ?9 k' H F X' `
{4 w; B" P" s' z* A4 p' G9 u1 }, y
/* Start the clocks */- ]5 y3 c" {# s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( A+ f) E$ a7 o, x" _( x+ j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% V- `( _6 P7 f9 c% n3 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% @5 w8 ?7 c9 o( J/ h3 ?
EDMA3_TRIG_MODE_EVENT);
, K2 b6 g2 Q KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. E8 E, D9 Z8 u, i4 O- `$ b t9 H# G$ WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) P9 ^4 ?1 L: e; `7 F2 i% t+ r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: W0 c7 @9 N% f8 N6 q8 K7 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( R, F: r6 y% J( [ P) @6 p7 T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( s" n% Z, H6 f0 T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& n4 V/ l% ]0 I7 b* |: F1 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! u6 x+ H) c! V* F4 A; C( R0 v) F
}
+ }" Q- A. |/ k4 m! X, M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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