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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% h5 z5 L' h/ D' `, O9 [+ j
input mcasp_ahclkx,
* j0 z0 {: {! einput mcasp_aclkx,
, T* \7 H3 O: y* o$ Rinput axr0,
, U" ~0 Y. m% S. f3 L6 a- F
" F- i7 y. d i( Ooutput mcasp_afsr,
* q0 E; a. _' E& y* soutput mcasp_ahclkr,
; U/ r: q; ~- U# a, ~# Y; t$ \output mcasp_aclkr,
5 ?6 w: B5 K' H' M0 h" z- m( `% x5 zoutput axr1,$ U7 W q$ X- @. W8 R y: r
assign mcasp_afsr = mcasp_afsx;
6 S& T+ `. j6 }) v- v ~0 G$ P. hassign mcasp_aclkr = mcasp_aclkx;
7 s/ T& I$ I3 q: K( b. Dassign mcasp_ahclkr = mcasp_ahclkx;
/ r$ N* \: c+ Q6 X( B& k3 }& zassign axr1 = axr0; : `+ O$ y, C d+ v2 J
* \1 t0 L* q$ \% Z& ^9 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 k2 L. ]+ }6 _: P2 v2 {7 lstatic void McASPI2SConfigure(void)
1 q) L- N' x5 ~4 E# A3 A{, F h" Q# q' i6 j" [" J5 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; o0 ]9 a$ O: b8 m1 }8 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ |% \ ?8 l4 d: g9 ]3 h8 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 V8 E/ H% x* ~, j; DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& Z' o9 \! F. u E1 u1 L/ m& mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- ~: \. B$ t0 m& ]9 y0 t" J* ]MCASP_RX_MODE_DMA);" b. e- A& ^8 M/ H7 _' N6 o/ T' s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. @' o' P; b6 N# E0 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ t7 o' ~ o! ]. `1 |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ y" c @! D! t2 A! bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, t" b0 n3 E" a$ ], r9 f tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) U6 i' W3 B5 w0 ^4 A9 x, F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* x- q! _2 D0 l1 @0 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 e9 e4 ], P# B0 X" d4 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 H; A1 X% E4 \4 `$ t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( ^8 {+ Z7 f+ W3 D" y; T0x00, 0xFF); /* configure the clock for transmitter */, C& Q. Y7 H h( L. z- m% U7 s4 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* b% r+ p9 r( C6 D, k' bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 a4 v' g) v- G% p% GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- w1 c0 i* D5 e8 n7 c9 c6 e0x00, 0xFF);6 V0 \4 U% P. O3 L0 a) Y5 c
& Q8 ]* S5 u/ h$ C! _5 h
/* Enable synchronization of RX and TX sections */ * z$ x( _1 w9 @% f e# g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! S; r x/ D: x' Q* q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Q$ T7 J7 r* C, F8 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* Y; l' w: u8 P9 d** Set the serializers, Currently only one serializer is set as
* v8 [ a6 l. U3 a% V** transmitter and one serializer as receiver.6 ~; _' B h+ |: _
*/! Y& q4 R' k" \; }* Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 C7 |6 S7 ~. b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ _% F) V6 L# ?2 k3 \. |* K% x** Configure the McASP pins
; p2 v, I: u/ f7 k/ J** Input - Frame Sync, Clock and Serializer Rx; X8 a9 [' s% q7 V: U
** Output - Serializer Tx is connected to the input of the codec
9 J8 k a+ }5 o3 \*/
! f0 u K, G$ t- d6 H6 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: z/ {3 a4 z w+ q5 c. g q# D0 L6 q' }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% L% t; z; G% V0 N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. }( w6 ] a1 h& a6 X5 R8 v9 O
| MCASP_PIN_ACLKX, E* A0 M/ K; k2 Z/ H; M$ I
| MCASP_PIN_AHCLKX5 x2 o( W0 e% c/ k& [; Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# z+ K! M# Z. r. F% _$ Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ D" t1 ~- u0 V! g, M| MCASP_TX_CLKFAIL F% G4 E+ U3 v, p
| MCASP_TX_SYNCERROR
+ R; M- ^ X: i& N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 M. U- }7 {+ E| MCASP_RX_CLKFAIL, M- D! a! t0 r+ R) m
| MCASP_RX_SYNCERROR : W P7 w$ S" V% D) O
| MCASP_RX_OVERRUN);
; ?2 r- }' n4 Z! O6 s" B6 V} static void I2SDataTxRxActivate(void)* z. D% C( l+ o8 A! F
{
: Z2 w' ]( r/ O/* Start the clocks */; i" y7 {0 L& C5 P3 I! F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: m& b) t" w. \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 P- K+ y. |& h- S/ j9 C# r/ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ X( E o% [2 N8 Q2 a) E3 S3 n5 |: OEDMA3_TRIG_MODE_EVENT);2 _! t" ] P9 d- g' ?% S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( b- l* p, ^( d! q% s6 L8 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ B/ U6 L" H4 q- @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 ^+ z$ ?, K$ h, i) F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ k. B3 N& |+ Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& ], ~3 I; I3 Z1 H# j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% _1 J2 z* G- E0 f% m" |1 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# L& Q% s2 j7 U" U: i+ n5 T}
3 z) |! Z" J" d8 |0 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 o/ `+ @( r7 ^5 X
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