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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ U e/ v/ h/ I5 S+ q- m2 [3 q
input mcasp_ahclkx,8 W% F3 ~+ h' n) Z* x; p# Z
input mcasp_aclkx,+ S) q" @+ P' X3 _) b
input axr0,
9 D1 s! ?/ d& e8 `6 J" E* |' V" A. l3 V
output mcasp_afsr,8 I* G. M- o7 O) ]* R% S
output mcasp_ahclkr,
/ x) p. Q6 h- f0 [7 F% w7 S- loutput mcasp_aclkr,6 Z% G& V7 G/ J4 k6 Q/ [
output axr1,
9 e# D# w; n0 w- m( v assign mcasp_afsr = mcasp_afsx;4 ]+ j1 N0 u4 N8 F. W$ h
assign mcasp_aclkr = mcasp_aclkx;; e/ `2 S- v& y1 k3 ?9 y4 X- j) k
assign mcasp_ahclkr = mcasp_ahclkx;
- Q G" s: z0 b$ Iassign axr1 = axr0; , z- G; e. F0 [
1 g9 V5 Y, Z) A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 U% v* }; @1 o/ O6 Y4 ]# C6 ostatic void McASPI2SConfigure(void)/ |- k' j S/ B4 I j7 b
{# V9 d5 M& ?& Z" I3 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 n) B; p" I! C! a( k# L+ K M+ v+ S% JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% |& n" H; g0 J! t6 ^ @. {- KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& Y9 J$ B% |- d$ d# F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 n. U; f: \) m: ?7 H3 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 n* e- h5 ^. Y9 `) P; D# |MCASP_RX_MODE_DMA);
" G+ X( c; I6 a1 E6 |& L$ N7 X% xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 r) ]6 p6 l( a% D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 V4 M4 m4 S! C4 z X& V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ [! B! F7 N) W( V h) l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ {6 A V+ Q* Q9 f: zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / `8 w: `( i0 T1 Q/ S7 M$ l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& [0 Z( a' O$ W! m3 W _. h, ~9 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 j5 L o! s- {# j" z9 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' [, O% q( w/ K" M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- Y1 q/ P1 m& G( z; p" x" u5 Y' w
0x00, 0xFF); /* configure the clock for transmitter */
' d# T9 S T- G1 w* t/ }" gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 G6 a! ], [0 ^/ M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! Y1 |$ u4 l3 ]* P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 L# X& ~ Z/ x% \% m. Z0x00, 0xFF);
; w6 [* Q% l# l- F$ E
Z& @5 o1 \. J2 t/* Enable synchronization of RX and TX sections */ 2 E# G/ I# w7 |5 _" H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- C3 b; ?0 h+ a- J* g* P6 Q, I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% v; e* j/ ~/ c( c! Z# f$ aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& \: X0 y0 e1 [8 K% ?$ e
** Set the serializers, Currently only one serializer is set as
9 O! J- l( d! E** transmitter and one serializer as receiver.2 M- H- D- y( N! ^
*/
- H% r1 ^ k! O% M; f" ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 B9 `. t- R6 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 t3 E2 E, \; o7 K6 j3 y5 ~** Configure the McASP pins
, C/ q/ k" [! ]( A2 t** Input - Frame Sync, Clock and Serializer Rx8 n. O- H' k# e4 Y: S
** Output - Serializer Tx is connected to the input of the codec
7 d6 Y' c, m- U' x% e7 p; K*/
$ Y; e" z) G: x5 {6 ]0 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 Z; f7 p/ k( Z7 j1 Z7 D$ JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 I6 c% z" x8 _8 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( N" v& y6 J! A# W
| MCASP_PIN_ACLKX$ l. o# [9 z% S
| MCASP_PIN_AHCLKX
( N1 I" z+ K" W4 v: F x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" [$ w1 X& |8 p; o2 I5 T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 o L3 O! [6 R6 s0 r| MCASP_TX_CLKFAIL & d' a; f- [, U' e$ Z
| MCASP_TX_SYNCERROR7 H6 @8 Y8 H0 B2 e2 R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ i/ a, O& v/ j9 O# o) @$ ]' D
| MCASP_RX_CLKFAIL
% ~2 j# \, u. U) l2 q| MCASP_RX_SYNCERROR & A* W& K- _+ J& \
| MCASP_RX_OVERRUN);0 x x# N0 [5 y7 u
} static void I2SDataTxRxActivate(void)
8 y, C" E8 [5 c{
# g T, }( I& d! h/* Start the clocks */# C* R+ B: I* \/ T5 p0 ^' a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* }; W6 w& G9 p3 u" M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! Q* g- u) W) U, r3 Y1 R+ ] z2 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* ?! d$ R3 O- } U
EDMA3_TRIG_MODE_EVENT);6 C2 i; R; c* R8 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% _" Y1 f2 \: Y3 ^4 A/ X$ dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! I3 y3 g1 \$ O \; ^: `" K! G Z! h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ P5 L/ r. x+ V' R1 A% L, ~, BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ p A0 Y* {- ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- n' T+ V r/ [: |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( l# j7 ^) \2 H* h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); J$ F7 w+ d1 V m3 F; M- N
}
8 c9 O4 Q! Z8 q5 u3 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 D$ f H( `7 M" p! e. q$ a
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