我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; @& d q& p& m! @( w0 |8 J' yinput mcasp_ahclkx,
P- N) }. C4 L0 I- u' D# E5 q+ Vinput mcasp_aclkx,
; @8 ?; m' n% P( O5 j+ z3 q' cinput axr0,
9 B, t% H) t2 H; k$ v* {/ {
/ y9 i- Q8 T# S1 C1 E' A0 q) e, Joutput mcasp_afsr,
( C' @7 \, t4 o% ]. L) z( M7 N$ ioutput mcasp_ahclkr,
7 w8 d$ I8 t3 |8 n6 x# Routput mcasp_aclkr,
! K; G2 s: ^0 }output axr1,* T3 w+ I$ p# e$ E0 t# Q$ u
assign mcasp_afsr = mcasp_afsx;3 s+ J: M" d7 L4 P. D9 L& ?% I
assign mcasp_aclkr = mcasp_aclkx;
- s( ^1 |% S( iassign mcasp_ahclkr = mcasp_ahclkx;
" R% r- C- E/ @1 {7 ?) R# Hassign axr1 = axr0; ! x: h3 {7 S2 E
8 S# p7 W/ \. [+ M. ^+ C3 o. }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- j, S3 H" s) i; M* ~2 _; |static void McASPI2SConfigure(void)) y4 ~# ^9 U0 ~6 C6 U' i
{! f" x5 J1 P* D; t* |+ |2 g# J1 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 m: Q4 Y3 n6 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 E) t8 y9 F* w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 ~: y) j! b1 k3 `4 b; r5 l$ p: P' ]( y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- {. h) Y7 A4 g' K$ UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 t% A9 g3 G) o: I) T! Q, aMCASP_RX_MODE_DMA);
& V' n$ R A3 u; {/ QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, z- k: T" ^$ y" J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- H1 `# {* F' M* s' M, Q) q3 l( q3 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 F7 k3 q, Z+ e( NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# T) P+ L: A7 b R1 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 ~( J) E0 M6 x0 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; I& {( ]8 z" @' N- C/ \7 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 P2 x3 U% l, Q% u- I, m6 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # I" p" @& B- a" w3 l2 Z2 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* i0 V6 I8 X7 j) _; P7 y0x00, 0xFF); /* configure the clock for transmitter */
2 i0 B$ d8 M0 v4 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 q. s$ |$ V( O. b8 D9 F- t& D2 ~/ V( A* |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * M5 i v- O$ E" m, \% b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ Q- c/ X& b4 r+ C: h3 H% o0x00, 0xFF);* R1 n* g7 f* x3 e4 {8 K+ s0 {
0 p- t; s' F7 _( p3 Y! M
/* Enable synchronization of RX and TX sections */
# v. V# J% r; L& C# {) tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" |/ K0 D" v9 K& f: aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" e2 |0 L! }$ u0 i5 \* p, pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! ?+ w0 x4 d+ W+ D9 P5 b** Set the serializers, Currently only one serializer is set as
9 }* }( P' {( o, a+ g$ E** transmitter and one serializer as receiver.
2 u: o2 x$ E0 A x7 N*/
1 O0 ^0 R, ~2 I) uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); t! {. \$ c+ }9 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ @5 {! F& |$ U$ `2 }0 p** Configure the McASP pins
' C5 V# O; y6 y/ W% P8 b& N- f- u* B** Input - Frame Sync, Clock and Serializer Rx9 @# r6 ~3 ?3 [% r3 Q
** Output - Serializer Tx is connected to the input of the codec
9 M+ b, ~# f) E0 @, {6 c# ?/ p+ f2 E*/) _, I6 ]5 _; c; t- c ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, H6 [3 ?- R0 y8 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# I4 G/ V) l) G# S. K! l+ s2 vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 o) @& j; v7 x; i+ \| MCASP_PIN_ACLKX
/ X5 N2 [# X" v+ R% C3 ]1 _| MCASP_PIN_AHCLKX
* v5 e, E& A3 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ [8 W0 V$ |( L" q/ \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) A* n5 @, Q8 \# G. H
| MCASP_TX_CLKFAIL I9 U; D" `( a3 X
| MCASP_TX_SYNCERROR5 ?2 S% I) h% F0 b4 I1 l6 U7 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 q- ~9 v! ?: k k6 R1 w| MCASP_RX_CLKFAIL3 `3 `: ~5 ] ]% K
| MCASP_RX_SYNCERROR
+ D4 @8 ]% P7 z0 W| MCASP_RX_OVERRUN);5 z1 c. @( ~/ J6 R! x+ J D: ^
} static void I2SDataTxRxActivate(void); L" u4 K& ~) ^4 g2 V
{
: L9 F' X5 h8 D( W: x! ^/* Start the clocks */" U1 z' ^! s+ Y6 H- v+ p6 b6 h; ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 F, D) p" { U* U |1 t- G2 {; iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 `# ~: o: Y% D$ }! G0 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 q# a/ G! ?5 c+ D; g8 Z5 _EDMA3_TRIG_MODE_EVENT);
* S4 S7 g' A$ D; o# D6 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + c5 t8 }8 A3 {3 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 K) s9 U# D+ G2 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 G( S" M& e: P; t0 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// y3 N2 @9 G4 G+ X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ d: ^9 Y" W# _* g/ K3 f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) u1 i' v2 M% p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# k- v# g2 y0 r% m
}
( m1 I: u, v- P; F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) n( H+ G. o: R a U- q5 Y- q3 y |