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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% V; W+ R. w r% M a4 ginput mcasp_ahclkx,# `) \9 s2 \7 X, q0 U
input mcasp_aclkx,+ o3 J& F& {6 k$ Q! X4 B9 {5 x: w1 f
input axr0,
& k7 _# |0 ^$ Q* t
) M0 K, l% T1 ]output mcasp_afsr,
6 S% m, g, R* _* B: Doutput mcasp_ahclkr,
( G S# H5 _. E- @! s8 N' @$ G3 p+ toutput mcasp_aclkr,
- R! T' Q1 W0 d5 Poutput axr1,
# {2 @+ D* }# c assign mcasp_afsr = mcasp_afsx;
' I1 b; J+ K; s( v" Cassign mcasp_aclkr = mcasp_aclkx;
- ^1 m" |1 S# t0 y5 \' n. `assign mcasp_ahclkr = mcasp_ahclkx;
2 z1 {- o2 n- p. z4 P# @ J' D* Rassign axr1 = axr0;
% F9 }2 x- d8 }7 @5 e5 v" ?
/ j6 p9 H S- G W/ R: t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , a* u" a! q, O/ `& \9 E4 T
static void McASPI2SConfigure(void)
) a( R' `8 h+ Y$ t, Y" J& Y* ?0 @{
! o, V. c E$ h% u0 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ d& ` o% b% t& C$ e0 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 A# z5 ^8 y2 ]* W5 j, k# z, eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 l$ T2 k4 k6 w; \. e/ H5 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 e& m+ J( E4 C K. RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 E d( w2 P; DMCASP_RX_MODE_DMA);% ?1 l6 c0 J* q+ N& C! @* y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. a R" A+ m1 M# r. o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 q8 ?* ^" k/ w" d. ?* l) Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! k* F X+ j. n: dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* P) Y3 o8 g# r& F/ ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 ] a* }/ e9 N/ h; \$ [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% Z0 ^" I/ a3 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 d" Q7 s* p5 d& D7 T9 _' B3 B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 a; ?/ r0 o* N0 W* ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 _& U, ^% A4 D5 a) R0x00, 0xFF); /* configure the clock for transmitter */$ O8 f% x! A- K+ x% _8 J- E" L! ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* K. @+ J4 S- d! P& ~8 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ h6 {3 T% y3 rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 D4 \: C2 K$ `2 P7 B0 }& A0x00, 0xFF);. u9 M4 ^( s Z9 N
. i$ K4 K! Z/ a3 V8 G/ C& u/* Enable synchronization of RX and TX sections */
3 Q# V& h( a" z/ J5 w5 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- |0 `: }3 k4 g4 n: D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 N( @) Y+ W' ]6 s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: S5 T% j& p3 `5 D- I' c- Z9 {5 c
** Set the serializers, Currently only one serializer is set as
7 v; [/ {- d0 G4 p** transmitter and one serializer as receiver.
" E) }' f5 n. Y* M0 [*/
0 t/ }% ~ L" OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 X2 w* g# t! J8 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) z) A0 C. h1 X+ c; Z7 `
** Configure the McASP pins
* [6 Y/ \/ Y" [9 `' G5 [** Input - Frame Sync, Clock and Serializer Rx0 D9 O$ p, i Q7 J9 x' e
** Output - Serializer Tx is connected to the input of the codec
3 a/ v( t3 }" O/ _+ y1 {- J4 J1 S*/. Q& V* J! v9 @0 x# R$ e1 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& T" q# l, [) x& aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 O5 S! N: R3 g I1 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 Z: Z9 n: A+ ~, C! s% Y- d| MCASP_PIN_ACLKX
; J, |: Z5 [+ e8 M. R) k| MCASP_PIN_AHCLKX
. D: Z$ D' h# |8 s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. q4 C5 g! l: @1 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, ~% p. J& y1 I4 B+ W5 H" t& S| MCASP_TX_CLKFAIL
8 R$ G5 ]$ E1 Y/ i| MCASP_TX_SYNCERROR3 s, G% P _+ R% J4 [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! x( T n- t9 k3 ~4 E @: ~; q. z| MCASP_RX_CLKFAIL5 V% ^, K8 Z, @
| MCASP_RX_SYNCERROR 6 N) E( K! ^1 b5 A" A9 B w
| MCASP_RX_OVERRUN);
/ \# W( m+ P4 ]7 j} static void I2SDataTxRxActivate(void)9 v9 \5 `$ N5 z8 L! ?
{6 w3 J) [+ [$ d5 L
/* Start the clocks */$ b- `/ S; _& R3 l+ k" z& ?6 E5 @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 N; ]; O3 h( i/ O6 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# f$ u6 C W) U% z: S& Z8 |6 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. r& F7 I& ]% y/ ~, D9 D
EDMA3_TRIG_MODE_EVENT);: f9 f4 U4 Z1 @( T. w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; w+ h* M5 N0 }1 R5 E# {. |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 T0 [) @! f+ ?, F3 E: ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# M, ]- k1 Y' R) zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ ?9 z* [: c$ I0 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, {( q( Z+ Y2 F7 z: L: y2 k5 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% h+ k( @% ? X" B$ Y$ ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 \& B" v9 d3 n+ y# j8 k}
$ k/ j2 t: Z# e2 _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & l$ l: a, e1 G" Q
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