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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) Q# {) p! ~0 W: _5 Kinput mcasp_ahclkx,
& W8 D& A# V5 ]% u$ s) winput mcasp_aclkx,
; n! {7 d, I2 I1 tinput axr0,
s+ x/ z0 L0 [
( D b# h1 [; e2 m; ooutput mcasp_afsr,
4 j' q1 w3 k2 s2 B7 a$ e$ l$ Noutput mcasp_ahclkr,
% K G) z |: M. I7 {% houtput mcasp_aclkr,4 s; ~9 `8 q& y- y2 ]7 o+ L
output axr1,
" v( |9 J5 {( { i. b assign mcasp_afsr = mcasp_afsx;
7 i. D6 u+ W: b& p* \( Qassign mcasp_aclkr = mcasp_aclkx;6 ~) }! Q) T8 h$ m( |
assign mcasp_ahclkr = mcasp_ahclkx;8 t0 I6 S$ `/ P! N) k
assign axr1 = axr0; : X2 x3 _+ ~$ d7 G
( R& F7 {! f( a' v( P* J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + ~" a; z, i% F# |0 R
static void McASPI2SConfigure(void)1 O5 h$ ?8 B, Z. S* J) y1 l
{2 E/ ^' c/ a5 a+ }$ f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, B) A. Y' U( Y, h; W$ [. h( g# SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 K* N& @; A' L0 R& z, v6 [2 x3 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 M; A8 e) `5 x+ ^) r ^& u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) G* S8 p' C, N( f& S* s$ Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# K7 \" J6 [6 N4 Y5 oMCASP_RX_MODE_DMA);
2 D, _5 S) z7 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& l0 j9 s% p* s) W0 V6 c$ e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. s8 Q* J% Z- W' j: a! ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% C% }9 q' W* h' _. QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ }3 {6 }) l- _0 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 ?' M9 V( D5 v4 X1 f4 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 }7 z4 H4 p' V& T/ G. x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" g6 }" K Z& @" S& G3 f+ ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- |' X2 c" l8 [7 l2 K+ d3 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 a( D( D0 X& J- U
0x00, 0xFF); /* configure the clock for transmitter */
5 l* d7 J5 b" p' _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 } b8 A" J0 _4 }: YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 j( O& O& l; [0 K2 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& n* M$ Q; ]9 v$ m
0x00, 0xFF);* U4 k. |4 G5 V/ o. U5 D
2 [% F; i( A/ X1 Y* X+ t" y T, m/* Enable synchronization of RX and TX sections */ 2 g1 ^# C, \3 G0 u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: E; y# D1 K) u Z/ o. O4 Z, S3 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ V5 @( N% |: v7 J) A( _ E1 |( {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% A8 R2 m) @& @) y8 T
** Set the serializers, Currently only one serializer is set as
0 V, W) K* N* t0 R$ u1 m0 N** transmitter and one serializer as receiver.2 E1 m; r' _, |3 H3 J! Q
*/( K" J. F: A& M5 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ L& h4 f5 r( D3 q+ R( Y( d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ^( l2 L! v8 m3 P, |( F3 Z
** Configure the McASP pins & N5 g8 S8 [# w0 H) v, K
** Input - Frame Sync, Clock and Serializer Rx6 M2 m7 q: ~9 y( e/ X3 @/ c/ O/ {0 T
** Output - Serializer Tx is connected to the input of the codec + B0 L: l! }. i" e0 K/ i* E" a% l3 [
*/
* A- i; X Q8 `0 n4 l3 W! P+ m0 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: n- U' D3 q+ O5 u* _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; n) p, N/ N5 S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 |6 S2 k" N& E" H* T
| MCASP_PIN_ACLKX b$ L$ Z# V+ S- H, R
| MCASP_PIN_AHCLKX1 m& u: a) J; @1 h0 V" e$ e7 K3 t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% o1 s) T6 z3 D. L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( c% R2 h I' R% t F3 }| MCASP_TX_CLKFAIL 8 X' h( n p* I3 c
| MCASP_TX_SYNCERROR
c; E# k, Z: R/ q1 ]6 \' F+ F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 t. x( u0 I7 q0 y3 }# t: q| MCASP_RX_CLKFAIL; f# G a5 z: m! L$ w2 d1 O) ?2 V& P
| MCASP_RX_SYNCERROR
# U* O) I! j: ?; M R( A% t| MCASP_RX_OVERRUN);+ o$ b5 k% B N" k, Y0 N
} static void I2SDataTxRxActivate(void)" \8 m5 N' ^( @! X- |8 Y- V' l1 n
{
5 D7 A, K) {" k: K/* Start the clocks */
- D* f# V& `+ m- x% M& e+ l0 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( F! `! J' H2 l) v1 B- D6 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// X; r+ y. u- A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 T' o; R- P. b! v* eEDMA3_TRIG_MODE_EVENT);
- q) s' Z8 n$ t, `" ?, wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' f8 E8 ~* v0 w* sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
?) o3 M9 O. `; z+ JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 v2 l6 i6 x% H4 D$ tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, ]* h2 X8 f% I/ w, o' T3 W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 F5 D4 f/ B4 d% ^# S# u0 y$ `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 i0 P. b a8 j b1 W- |; p8 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! z8 X( a N6 @ N" W5 P& Z5 h}
: E5 B7 Z4 r r# H% r" ~% G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / N2 @1 @( J4 v
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