|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' z: v. o" x3 M$ o2 m% tinput mcasp_ahclkx,
$ Y" g$ h( S2 u% B; Kinput mcasp_aclkx,
4 s8 @, K$ B/ \2 e# @9 |' G: ?input axr0,& y8 A/ U) v5 k
1 Y C& ^: ^4 t9 H' koutput mcasp_afsr,
. L) A0 [% @- }- [! d& D9 m# A* Toutput mcasp_ahclkr,
# [2 w( s; l Loutput mcasp_aclkr,
8 o4 {4 W7 I. u, E* M( g" aoutput axr1,
6 @ q: P9 C! E' V \4 O% J0 e: x% i assign mcasp_afsr = mcasp_afsx;0 x& h2 F% f+ t |" T- n& t
assign mcasp_aclkr = mcasp_aclkx;
3 e5 k7 ~& A& G' v# s8 Fassign mcasp_ahclkr = mcasp_ahclkx;% Y0 p% E+ g/ h7 j0 ?! [8 r
assign axr1 = axr0; 4 P. [! b X2 E
5 E: ^+ k/ l5 w1 L+ Y1 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' L& Q" ] ?) m; f1 G, Astatic void McASPI2SConfigure(void)) K, R K% @: n9 L( v7 [5 L
{
! |( g8 j- f6 T0 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! c9 J$ P/ ]# ^8 e9 T( w `7 Y$ M& `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) w- E7 s- c7 G4 B# x, u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) }" q) p" ^" Z! D! Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ G9 H9 i) {% m8 b K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. d# [0 S$ i' qMCASP_RX_MODE_DMA);- d! d! O0 E0 ?/ _$ i9 N, ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; F# m8 v4 ^8 H* h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 G" l7 n7 h2 f7 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! o- {% q! @- h$ ~4 B& VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# H4 k; M9 ]4 L, z; s& \6 MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 S" o" U0 _: j4 [. K3 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( M9 P0 E( S& d sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 E" d1 c4 [! Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % y/ V+ H! h' W9 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 k U- L4 V2 M# g2 T R' K0x00, 0xFF); /* configure the clock for transmitter */
3 H; F) E$ t+ @8 f, R. Z6 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 S: i$ [; I! s5 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 k: z) r- l: t8 y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ Q" J0 @5 n: b# S
0x00, 0xFF);
2 h/ C' k3 i1 W; H* L" W% A6 q! _% ]! j9 V
/* Enable synchronization of RX and TX sections */
1 L; y! O0 l" kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 {1 v7 T$ ^& X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. v* N3 d5 y% G' H) ^9 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# T# ~) t/ q' A
** Set the serializers, Currently only one serializer is set as! Y% j& J5 B! d
** transmitter and one serializer as receiver.' g0 \6 k9 S8 o5 a
*/
& c! {6 C" v$ y; g" lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: E& g! `& l: p0 p) S. k' Q# X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 s; v# O) L! v2 z$ d8 K
** Configure the McASP pins 9 M6 P3 ]) F# C" z6 j# w4 t
** Input - Frame Sync, Clock and Serializer Rx
0 |( B6 J# h: l3 ~" L$ w** Output - Serializer Tx is connected to the input of the codec
- p' x) g1 s, `4 O. K* ]2 S5 Y*/
7 n" g8 Z" p" B' p N/ uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ V |( X; k0 Y1 Q1 } `* \) f+ oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' h: G3 J Z7 {! O5 c5 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' c& X9 i% x2 u# d' J. O" W ]/ k# ~
| MCASP_PIN_ACLKX: T2 A) c$ Y! j' _ r: ~$ m: _
| MCASP_PIN_AHCLKX
/ D j8 `) f: Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( K# S8 u% j% u4 J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ @/ X u2 m& ~| MCASP_TX_CLKFAIL
7 Z1 _, G3 I- Y& n| MCASP_TX_SYNCERROR$ g9 l) s: G" U7 s& q$ l, r: I; `5 Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! h, Y$ i: g0 }/ A2 _, \
| MCASP_RX_CLKFAIL
3 |. M8 i- U! a ^( R| MCASP_RX_SYNCERROR
+ J9 |" }( C% M| MCASP_RX_OVERRUN);! H& U" m; F, A/ f# Z3 b4 k
} static void I2SDataTxRxActivate(void)" e8 d/ _) }# ]* l K1 n* w) L1 K
{( w/ E$ f+ T) M8 U7 j
/* Start the clocks */ {* b, |6 N9 t. q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; O6 A$ M4 z) m9 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 r/ f- w% z& y# @+ I, xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
Y# U! {+ ^. ~7 o* \0 [EDMA3_TRIG_MODE_EVENT);
; \) n! u8 C' [3 O# f J: W; V6 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 N7 v# ?# u. XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: ?2 s0 i6 V1 j" T4 s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); u% [- T8 G' j" e" E5 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 I4 a2 U# { j0 f" D/ wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 p: K# E& S4 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 q! J1 |) Z: F7 X, R6 R$ `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) j" a2 f# i7 T+ k
} o7 i' {" c0 B1 U/ ^# v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
( K/ }. L I9 O7 n5 B7 x" ]' q |