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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
[3 n$ q. B& J0 [input mcasp_ahclkx,3 |: W( o0 S$ T* r, M+ j7 ?
input mcasp_aclkx,
1 }2 S1 `! {0 ?4 Linput axr0,
# N% D: g5 b8 i# V8 S$ L. A6 X
+ r1 z. Q0 U. Poutput mcasp_afsr,
+ c1 @4 o( V* U6 x/ soutput mcasp_ahclkr,: o- a0 v) g5 j: a1 }6 j8 I
output mcasp_aclkr,. `9 I' c) e0 ~$ W' C, b, z( ?
output axr1,
* m$ E2 \0 G; Q# _2 N2 D# T K assign mcasp_afsr = mcasp_afsx;
5 J Y- h1 c4 h; F( Sassign mcasp_aclkr = mcasp_aclkx;) C" ]# S" a0 }- l$ R
assign mcasp_ahclkr = mcasp_ahclkx;& p7 q% ~! f: u6 P
assign axr1 = axr0; 8 P4 }' m- k7 _" p" C; a
0 |$ W. O: \8 P8 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 ^* s$ V3 _4 d) B+ `1 C+ f8 i' Mstatic void McASPI2SConfigure(void)! N! X! N4 V/ y1 `
{
* L8 I9 ? [0 l! G( rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# X% m+ ~% k$ J0 |1 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 F3 ?3 O: |( Q7 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* T6 \6 ^0 b6 D% {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, B$ b' a4 e, W7 tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: x9 H7 q2 |1 `8 p( xMCASP_RX_MODE_DMA);- [( J2 q) c; I7 U2 k" G6 j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! {6 d4 E+ G9 {1 W4 n- S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 j* r' e$ x2 |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % v( Q" T& N: b" R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! T/ l @, H7 e& l" p3 o% p0 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) R4 \# j& w+ B# I$ d0 I, J2 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' D, F1 H7 O. L- M6 p$ H: } a) ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 g7 C! M# r- AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# u' { ~% o! o) K' _' B$ mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' s7 s% r' W. ]* n" a0x00, 0xFF); /* configure the clock for transmitter */; @) o+ P4 O/ x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 e; Q% P- H5 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 U+ ?! r1 Q: Z4 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. m, B6 x/ v$ {3 I
0x00, 0xFF);
2 H ?6 i9 b' k" R' ^: K: v
& [* R+ i0 V6 x7 U- G$ h/* Enable synchronization of RX and TX sections */ 5 m6 p. \4 }& f' J) ~. M( o7 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! H: H5 T8 f2 @# h& q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 n4 v7 I% s D. d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# W1 u# n& l1 z6 N
** Set the serializers, Currently only one serializer is set as
% U6 X* |# S) T% ?/ w! j. O5 `: d** transmitter and one serializer as receiver.% A# U' S# q5 G' ^8 V( O) e
*/0 C0 j- ]6 a1 ?9 k; E' T6 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# e+ O: P- ^ t0 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. O. b% n0 a9 v: M% ]1 X9 U* x** Configure the McASP pins * U) e* G0 i: p3 T8 v* v) U5 L
** Input - Frame Sync, Clock and Serializer Rx3 F9 n% [* l6 t2 g( \; |8 r1 o) k
** Output - Serializer Tx is connected to the input of the codec ( V) f# t2 C; u0 s3 C0 @7 f J
*/
! h/ ^. D$ N. z5 p% B0 g/ s2 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! [$ J( s% C2 Z8 r" T& _' C9 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% ?2 P7 ^2 [4 N) R& j) NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: r$ z8 A A @$ v0 s- Z
| MCASP_PIN_ACLKX
" K# K- _/ y+ \8 X- \| MCASP_PIN_AHCLKX) S5 _5 h- w* r( l. X( D1 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; ?8 x8 `+ O Z7 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) I% y+ G2 P5 k5 c t5 P% D7 {! \9 d
| MCASP_TX_CLKFAIL ( g: f* N1 v' R3 W R, l
| MCASP_TX_SYNCERROR5 w" ], V9 ?8 x% H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% |7 ^/ q9 R4 ]+ z| MCASP_RX_CLKFAIL
& z& d5 k7 U" ^" |; C| MCASP_RX_SYNCERROR
& k# G; V5 R1 W7 A! }| MCASP_RX_OVERRUN);
0 i* g* J7 {* D' m} static void I2SDataTxRxActivate(void)
. g% R6 a1 {' p2 d! a. r3 Z{6 c/ P1 z) E2 L9 j/ F
/* Start the clocks */
& C+ j# I9 x7 ]) o. ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 t4 C6 F% I' e* ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 f& y& _% {" I9 \! Z4 ?( V4 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, y1 m. R/ ^/ J. x
EDMA3_TRIG_MODE_EVENT);
: e& r4 m: S9 Z( `# wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % K) o1 c' Q0 l8 g! I0 f, O3 ^( o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 M+ u8 S) O. x" F7 z4 R' J* GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& n2 j4 G& Y+ f: G; z& N9 H: EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 ]1 R% ?- k9 {+ p# Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! u+ a; x1 x8 p, |$ Z" Z# B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: Z2 H3 n8 |. i; ~& P. `+ PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 F. D0 I/ D1 h y$ s} * A( s4 a4 |! d, ~; F2 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 @8 r7 V( a( _5 Y8 V6 c
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