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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 b* E$ `- ~( k7 z* [) `
input mcasp_ahclkx,
0 P- [: C5 F9 p0 `input mcasp_aclkx,7 a3 e7 r7 n$ _5 |. h0 T7 ]
input axr0,9 Q0 V1 P9 Z# K% @* B' m
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output mcasp_afsr,
4 C/ S- S. M% g: c# Uoutput mcasp_ahclkr,! @* P! n$ j* X( [+ _
output mcasp_aclkr,
' N5 p/ P# c* e+ X$ t% c, routput axr1,
- c& C& O+ u" c: p3 O" r! `4 V: Z1 j assign mcasp_afsr = mcasp_afsx;
1 ?1 U% ?* F! ~assign mcasp_aclkr = mcasp_aclkx;) Z; t( R; @, F) Z: H
assign mcasp_ahclkr = mcasp_ahclkx;9 u2 |* [* ]: n, ^; b! E6 d
assign axr1 = axr0;
. ?/ B9 o/ l" A# E3 H7 j0 ~/ ]+ U r6 X G- T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 o9 U, }% k q5 \0 n* C" N! d7 X
static void McASPI2SConfigure(void)& |" r' R: ?1 S
{# Z- n% p" }1 {" t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ \7 G9 T2 ` F" B+ N; S% YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" X/ Y. c% z7 D8 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ a" g& L: F0 q* YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, y% r D1 E( ^& S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% z6 n7 `" Q c h& oMCASP_RX_MODE_DMA);! L% {! n/ S7 c% b7 G* R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ j% O+ q2 ?. S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
i; R7 K/ s8 K9 n: UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . ~7 \3 ^/ G3 ]4 ^1 A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( e+ d* G4 C+ G9 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, o) ~. M2 Y# K' W3 @2 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( h" l$ u* X6 g' @" _8 y% jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 U' ~# v3 ^% u; G& }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ \* I$ E+ Y# l$ T: [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 M& ]' V6 P& C) ?
0x00, 0xFF); /* configure the clock for transmitter */
/ g' Y+ [& R2 b: dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% t+ g* A1 y4 W- J% z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 W* V( O7 T" N" Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( f+ b1 R2 _9 v. p, ~0x00, 0xFF);
5 n, r! s0 [( L, _% \' e4 S' h$ u4 c
/* Enable synchronization of RX and TX sections */ 2 ]- k! l& B" l3 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 T' u" H2 U7 P: G$ }* r2 W) `' ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. G$ |/ B/ p5 M- ]1 F9 ^9 X" z: x& wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) d6 O2 L7 j) s {/ E** Set the serializers, Currently only one serializer is set as
- ]* D( j4 F5 a1 ^** transmitter and one serializer as receiver.
1 H& Q3 N4 A2 ?/ d( U* }*/% y& U. G/ t+ L1 Q1 @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 T: t" k/ o) x+ R; c0 r k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. D0 n+ M% @" K
** Configure the McASP pins
5 n, C1 r0 t u5 t7 w' Y** Input - Frame Sync, Clock and Serializer Rx
! `' I2 L4 w* F5 k8 i# i8 H% c+ L** Output - Serializer Tx is connected to the input of the codec
) Z" Z! {4 M8 O9 T*/4 [5 J/ ]1 Z7 A+ K, _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ D7 v- m. o& D1 @ x, v5 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# j- }0 N c3 x* F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 C- W9 s. F* C) W \9 A| MCASP_PIN_ACLKX
8 [( {6 f4 t# \6 w8 `| MCASP_PIN_AHCLKX
7 u# X4 g9 r% r) K3 B* B$ P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 D2 ^$ j8 h d2 r p6 o) WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # t3 J' Y. a' m7 o/ S
| MCASP_TX_CLKFAIL 0 }3 d6 C& S1 f% c5 M+ v
| MCASP_TX_SYNCERROR
, o1 g8 u- G, }1 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* E$ \ w4 A$ [+ ^| MCASP_RX_CLKFAIL
/ Q9 U5 J6 p- G* N& V8 A- n- a| MCASP_RX_SYNCERROR 1 [# V- f+ d3 u& k$ W
| MCASP_RX_OVERRUN);
: W% n& _" [8 F" A3 M4 w0 |' ^5 P; I} static void I2SDataTxRxActivate(void), t" Z0 i( k+ `5 |8 M
{, @5 D* ?" R+ A. F! C" C" s1 H
/* Start the clocks */
( V. M- x' ]% ` p7 p9 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* O1 a+ _% h- nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& Q. D/ D* a% X E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* M% W( z% T. X6 pEDMA3_TRIG_MODE_EVENT);
; v* p4 O# A! Z GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, j5 @+ E/ m" f; \9 n; H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 f7 v% X6 ?; |4 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* [: f5 W6 I0 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ H/ \: l/ N0 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# |0 @4 @" `$ Q' I# @' B* sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) I% b5 N* {. t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ v' |% d$ f' f" t3 u/ Q, D
} 5 j8 F& Q# E' t+ a5 @ O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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