MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
6 a3 T7 D+ ]% v3 U- Vinput mcasp_ahclkx,
input mcasp_aclkx,
3 |; i8 f& \# S0 \input axr0,
( \" m( [$ b& B1 V
9 m2 V: t: H: doutput mcasp_afsr,
, L) b& V( ^4 n; A; J! u9 youtput mcasp_ahclkr,
* y/ Q- ?% u1 p/ j3 k7 boutput mcasp_aclkr,
output axr1,
0 n* j2 E' B! a% f

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

; g0 ~5 ^. H- r) h" Y* {6 c  K5 x

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

$ }' d2 J! b5 _/ Z* i+ ]

static void McASPI2SConfigure(void)
{
" m8 E8 S2 R+ I- g; Z! p; E! ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 H; s; P8 p: z, b. YMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, u* V" I  F7 U9 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
) o& l/ q" F! Y8 ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
& V, l  s- Y1 H2 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& ?- _, u( M/ |7 a  P& T) JMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) u! |# [: w  f6 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 ]2 |* h7 I9 M) P5 }3 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 u4 o& Q( `" m, G7 a# {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 \. G1 v1 E* J" ]: c2 k& IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
" K1 t+ n* }: k6 l5 j7 N  nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 |0 P% ^9 y1 L) c5 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) D8 {, j& Q1 V& M+ z; [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' s: H& a/ n' j/ I- o, KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* u' G$ ~7 o6 D: w" W% {0x00, 0xFF);

3 V9 o  u% F) b+ O2 J9 X/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
3 i" w/ c9 L  p1 r- I: s5 f** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
9 {/ \( L7 s; F** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
7 S  _# S& r! F: _** Output - Serializer Tx is connected to the input of the codec
*/
# r' V& W2 Y( k  P/ d# EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& `  s- c/ B4 f2 I1 M* R( qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
4 q& Q4 x! N6 M9 d( b| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
6 L+ g3 I* ^4 W" k4 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
  {4 _0 h$ J+ |  D  K- G| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ l* W  s7 s+ K+ }9 Q| MCASP_RX_CLKFAIL
& }1 z5 M& f! c9 P3 F$ d| MCASP_RX_SYNCERROR
, f9 M8 J5 C& i- C9 S2 v3 {8 D# d| MCASP_RX_OVERRUN);
( q3 I# O0 T6 P. B4 |. J+ q& {- Y% T}

static void I2SDataTxRxActivate(void)
{
3 q' K0 s% p# T! @) X- p+ J% k5 x/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 L) [+ w; ^  d* s$ W' y8 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
2 I$ d# p/ B: t9 P( E0 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ]! i) k5 X6 `! q# L: lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
9 \% \  N& `* z8 g1 ?1 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# E; f; c2 S& v9 p. ?) FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
. l0 h3 i5 g2 C3 ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
; S1 o0 \% G6 ?: A5 l0 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 l) d) P6 V' q, C" K}

% W) Q6 J6 s& ~& l

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

- k! v- n; M6 r# f