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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 F, G, x" _( _, Q& k( u
input mcasp_ahclkx,
* V1 W- U+ l" d( \6 x; i; h; xinput mcasp_aclkx,5 g0 \+ r: ^3 P5 X2 J$ k- }7 i4 _
input axr0,
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output mcasp_afsr,
/ K7 g+ y1 e/ ioutput mcasp_ahclkr,
6 ]+ G! j8 }1 Y! l' ]: [7 H8 Aoutput mcasp_aclkr, ^ U( g; b3 M# n
output axr1,
+ _# L2 {* z: g assign mcasp_afsr = mcasp_afsx;
- J2 m! u) U/ t1 K3 Zassign mcasp_aclkr = mcasp_aclkx;
* q! C; n2 D7 a' i/ o$ dassign mcasp_ahclkr = mcasp_ahclkx;
, u1 H0 B+ k6 t0 D6 w5 P$ u' N- iassign axr1 = axr0; ; x/ d5 n% B) K6 v3 C i/ g
. y1 d8 h# g8 N5 V5 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " e& `0 V( B1 r: }+ f! f
static void McASPI2SConfigure(void)
. J7 |( a( H+ o+ s1 u$ ]; P{
1 d! v- j9 Z! o+ @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 B* A+ }/ w) A% ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( I& B: J$ [' a! cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ w) e' n4 p& {5 t4 s+ sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 ~" e$ j) |+ V+ Z, t% c6 e# aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& j# ^' M! K1 B# v5 f
MCASP_RX_MODE_DMA);
6 }7 w+ {9 ?& eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& g. l7 G5 x5 f$ w9 a& j( W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 n) {, b: Z% m) c5 q0 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # H7 P9 Y& j2 Y, R( g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ I% v- r0 ]4 H* x. y! NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( @1 x. `% b; V% X% bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, F# O1 h5 v2 n' ~* i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 K3 f+ b% Q- e+ t/ |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! @& |6 `# [* {8 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! Y' p P6 S0 O4 F
0x00, 0xFF); /* configure the clock for transmitter */. N, x7 o/ f( E1 u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 ^9 b$ V: P( f) `( o( p( h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# j3 Z% y" o5 ~9 l6 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 q- U2 r1 I3 }0x00, 0xFF);+ w$ X( l* O) H/ Z5 ^; F% b9 z& `0 E) G
" m2 {7 k$ g7 C" v! {% e1 B
/* Enable synchronization of RX and TX sections */
: z ^# ]- l6 `9 W6 _9 g! LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 }8 \0 T m9 ]) l2 e( j4 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! q# w! w: K+ s& r9 U6 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% h5 s5 x, z7 k
** Set the serializers, Currently only one serializer is set as- A7 q* [$ G: a y1 h& y% z/ S7 R' s
** transmitter and one serializer as receiver.
5 r9 R% G- |' D" m5 E*/& P' ^7 m9 M( G2 |; l) }: a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 e3 B2 Z! r+ p1 _: ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; S( ?2 R, F1 R Y1 |/ M** Configure the McASP pins ~9 d$ B, y+ b! G5 ^5 o
** Input - Frame Sync, Clock and Serializer Rx/ C0 H3 A, N, ^# O) i! K; Z& s
** Output - Serializer Tx is connected to the input of the codec " P' `& k7 G* y7 b) _$ x1 c: }
*/
3 J* L9 ~0 r5 U) b2 F: r7 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 M; Z$ i0 u/ @- L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& e0 J4 V9 m: f, N. M9 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! R/ t {- t1 e3 W3 I3 X" V| MCASP_PIN_ACLKX
4 g. D$ Q5 s _* A( V0 i! p| MCASP_PIN_AHCLKX; s% i( `6 B z) F/ F" b& D# g$ t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
k9 S" t/ O A& W" R6 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
A# a3 J1 W( T( E) Q/ R| MCASP_TX_CLKFAIL
; F% s3 T& [$ p| MCASP_TX_SYNCERROR
8 S& \+ S1 o7 H/ a& || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 D M2 T1 u9 B) L$ q/ D
| MCASP_RX_CLKFAIL
2 S2 }0 l. u* Q- i# y# || MCASP_RX_SYNCERROR
, U; A7 ^+ b+ S, @- L" ?0 j| MCASP_RX_OVERRUN);! B/ N v( ]. f4 i: r6 D8 ^6 z( b2 r
} static void I2SDataTxRxActivate(void)2 |7 E i* j0 e+ ~
{. t5 F" {; {4 G2 Z2 |. }
/* Start the clocks */1 F7 ]% H/ z# W& U8 V( H# v& a* u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 g2 V# ~2 ?! B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* @* J+ r) L" C( H5 m; U$ G. J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- z- @1 s, s* }3 EEDMA3_TRIG_MODE_EVENT);* E1 x; C$ A! E1 m* ?1 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 S3 j8 {4 N O/ b/ E9 y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 t( {# {6 x/ [5 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, ^( f* s2 w& ?/ m" v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 w7 D5 C2 I9 k6 G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: E: ? } z0 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* B u' S. e; W# U- m4 kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, E" g6 P; e3 @1 Y+ P" s2 \; k}
" m7 Q% u* f: N/ |2 z# n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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