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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. G/ N4 |" J p6 tinput mcasp_ahclkx," Q' g& f y2 J) P. ]- _! r+ `( Z' ~
input mcasp_aclkx,1 ], n2 z3 r- x' L" E$ \ J$ ^5 t; u8 t
input axr0,2 w6 `+ t P9 S+ Z; r9 ?
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output mcasp_afsr, c/ `% v0 {1 _0 G9 h
output mcasp_ahclkr,
& k6 X6 E L; V( h* Aoutput mcasp_aclkr,) ?! W' V1 j/ c8 ~- M! ]
output axr1,
* e9 o8 _# j3 D5 X" n" b: L assign mcasp_afsr = mcasp_afsx;
9 {5 i1 @2 L; F2 Z& \; [assign mcasp_aclkr = mcasp_aclkx;, T; X. F. i- Z, I9 j7 Y. W
assign mcasp_ahclkr = mcasp_ahclkx;
! ` S7 C* Q" k- n& q8 q4 i- \assign axr1 = axr0;
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; f8 N3 J& p2 v7 y& W. h. A" l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( o2 M" K' ?7 t* u0 Z1 J2 r
static void McASPI2SConfigure(void)
0 y9 B/ E. z X% v{" k! \: b; X4 }/ M! M; ~% |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 {3 N# g" l, C& ?6 b. F J9 C7 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% \* v. \+ G7 t; F5 w6 q& Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 `! Z; b& v! }8 l5 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& m, }* r \3 {9 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& V5 g, C) f9 _; M- t3 j
MCASP_RX_MODE_DMA);
, A# J7 ]: J5 B- [( @. j0 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 f* |: q% q% k m- KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 F2 g1 O# p& y1 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " [# I0 B0 n4 J+ V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' ?3 s3 r5 i" ]) i7 x! W4 K. ^; Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / k: K" B, ~. P! R+ x: W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 h0 F5 ?9 D2 q& BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! B' r. _- \& z5 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. H' x- Z6 \! Z [6 c/ V% wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 Q' Y7 l ~# [( n9 M$ Z4 u E2 c- Y0x00, 0xFF); /* configure the clock for transmitter */
' q i; y) F9 u: Y; ]1 vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; b' r+ D: K3 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ |, i7 r4 s. NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) O9 Q* ~- c( _+ I
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ u: G8 k: Q8 ?* L v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 O* |' [3 O8 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 M t% ?- P Z7 j( t& u7 S! x. P. tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 K( m& f# L" s q, E** Set the serializers, Currently only one serializer is set as
% K; W% X; |* B4 A** transmitter and one serializer as receiver.
9 J. d. F4 k0 q4 H' `0 O1 d*/
" F6 ]0 |3 `$ @# Q. u! o: U2 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 [3 ?* p" X( M3 h3 u2 S4 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; {0 S. g/ m* D8 J, ?
** Configure the McASP pins
2 x* z/ }2 N5 @, ^; e$ a7 h** Input - Frame Sync, Clock and Serializer Rx
2 ?8 k" d& |: F8 N** Output - Serializer Tx is connected to the input of the codec
$ z' H" V- }& E0 l7 X9 Q*/
- \# b- X9 @- S! a0 y1 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 c$ i$ A# p+ F. `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& W8 \3 D4 w3 N: C W/ [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 E C0 P. l% s| MCASP_PIN_ACLKX. v6 R% Q8 m4 [4 v' t7 Y
| MCASP_PIN_AHCLKX5 t- }& L4 U7 ~& a- Q) K/ [1 Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 _6 ]- {) Q, H" o* y# m# [' ^$ E, G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 X3 y6 X: Z o. T7 Z3 E" f
| MCASP_TX_CLKFAIL 9 X" }% c1 o+ f1 d& A6 k
| MCASP_TX_SYNCERROR; L+ V) d$ ^% b$ }6 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. m/ C/ e1 [5 \/ g s. f8 e/ B| MCASP_RX_CLKFAIL" v% I$ i8 h( o
| MCASP_RX_SYNCERROR " k3 b7 C# {+ W" ^
| MCASP_RX_OVERRUN);
; B* O5 M3 G. N, Z% H( p} static void I2SDataTxRxActivate(void)! F* _- ^9 i% }( N/ R
{
- a( y' N, t: a# K! p. E/* Start the clocks */
M, Q# [" W& r6 u* s* KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ I5 U D( i( j* @/ P8 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! f/ x. K9 F9 K* s5 M7 i% `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ Q; a/ E2 \+ ]8 EEDMA3_TRIG_MODE_EVENT);! N8 M1 b$ \: D# ?6 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( u1 x0 l& `* o' h' N1 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 G; h; N' D& ~! DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); C% o6 P- L, [4 p# s" F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. D/ ^6 s2 N' W$ Z% Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 b+ a6 M: L2 F R, K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. o# K+ X$ X) t$ l; }: Z2 G+ YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: X7 x2 i$ e& U" U# Y
} 2 i! j( y2 b2 R! G8 t% E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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