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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; A% e, r+ Q$ x5 ^
input mcasp_ahclkx,: m+ c! R5 t8 Z# ?8 ?" y1 b. `
input mcasp_aclkx,
; y( F$ r* S* f7 q+ y8 J1 Q. O$ |" Ginput axr0,
, x" n% f+ B! t4 w! o! T# f
* c* F/ Z, i2 doutput mcasp_afsr,
- l" [0 `% B/ t. y6 e* Q/ W( ^output mcasp_ahclkr, w( I- W! G1 Y+ Q8 f
output mcasp_aclkr,) O- B+ q; k' h( x
output axr1,
' y* E# ]5 l& Z: c assign mcasp_afsr = mcasp_afsx;
8 L" _& B7 l% h% _/ Gassign mcasp_aclkr = mcasp_aclkx;7 [" ?: f( W6 v
assign mcasp_ahclkr = mcasp_ahclkx;
& `5 y' f' Y$ E" z% v9 x' Q& zassign axr1 = axr0; 0 E5 H0 ?. f" m, N7 T; N- n1 }5 w
$ D& {$ q- m/ x/ E; D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 l! f# f* k$ A- o+ R
static void McASPI2SConfigure(void)4 V% F' M. p! ^) A3 v' f8 s; n
{/ F: g; g; D0 C- j7 T% D% t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 ~8 j, ~% m' N [2 g) o% MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' V* [* ~, i0 e- X9 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 n$ J- ^7 }. E# T, RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 i8 w% w/ G+ j0 F8 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% e, ^0 S" \, w5 v( a$ n3 ~8 ?
MCASP_RX_MODE_DMA);7 t1 L; p$ Q: F: H9 t! k) m8 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* t5 C7 l! p9 A& Y" A3 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// }/ Y8 t& n+ \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : K) N& P1 x/ U2 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) R' O5 X, m0 F( ?) o9 N. U7 o% Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; k- I6 \0 Y( S' M$ }4 m. ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 y. O3 p0 B. e$ d& b0 z& ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ m3 i0 j2 Q* N& ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 E3 Y6 C% y, \! B3 D7 i" D0 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; Z. `7 d% k; {7 l: f6 m9 S) ~
0x00, 0xFF); /* configure the clock for transmitter */
) K' F2 X" P8 G5 m( G4 v3 L3 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
E3 r; C; [9 b( o' a cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& z; ~9 @- u5 u2 x4 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% w! \ j: c E3 }: u& T
0x00, 0xFF);( F2 }( t8 L* ]6 k
7 s$ A' p9 @* `# a6 z
/* Enable synchronization of RX and TX sections */
5 q5 l) p/ W6 E5 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! I$ w) ?" o) J; ?1 i+ W% i' E( J* o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! ~( c$ @1 s& u7 j1 S1 P5 ]7 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 W3 u3 k) [9 `. p2 g** Set the serializers, Currently only one serializer is set as$ g! G9 [) X0 M- i3 s
** transmitter and one serializer as receiver.+ [- i0 r8 C- X% c2 h( |; I
*/
, \* I& ?* n. m% B ^& HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 C" o4 d6 H' _! r. P& O8 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** n" U5 e+ u1 p5 m9 h+ b) |
** Configure the McASP pins
! V2 w) z4 |6 O; ?3 x( ~** Input - Frame Sync, Clock and Serializer Rx% T% F$ F$ B S. b. ?2 J* P
** Output - Serializer Tx is connected to the input of the codec % F1 k0 P0 A$ K) d) s% O
*/! d/ K! m6 w t: d0 y" i& {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ B2 I2 p: A- L U, T- F; sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 j+ H7 K5 R# Y" YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 K* Y( e- N/ g2 r9 {1 H
| MCASP_PIN_ACLKX/ E0 y) `& j0 N0 R d6 Q
| MCASP_PIN_AHCLKX
4 y$ a+ T+ i( \# A, \) [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 G0 S* I, r9 N( r1 k/ f; TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( f: o# V X2 `: v' L' F( |; Q
| MCASP_TX_CLKFAIL , b0 h( I: d; Q: m7 c# y
| MCASP_TX_SYNCERROR4 j( b( V7 p, z1 H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. G- H) z# a# B" R$ N2 k2 g0 Z3 m+ R| MCASP_RX_CLKFAIL
9 f% c8 l. F& v$ Z) b| MCASP_RX_SYNCERROR
/ ]7 J5 {3 K2 ~' o3 Z3 z: }| MCASP_RX_OVERRUN);& G. ^0 E( _4 ~( ~% Q
} static void I2SDataTxRxActivate(void)
. K8 p: O% Z1 a( O$ E# t& n. `{
) g" }; D' D: U% |; X1 F/* Start the clocks */, H9 G5 N6 H: {. m2 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! }/ q5 Z, G8 w0 v) K1 l- G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* x1 Q8 M- c0 w7 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, m3 S2 e& Z- M2 k; B8 _EDMA3_TRIG_MODE_EVENT);1 ?. R. b0 z: |8 r- x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 s E9 W9 ~' ^, ]% YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ K$ {. F% I/ r/ d1 a: p. j- V+ MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ p4 \, q# K$ g$ d, D7 b9 ^) L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ a! ~3 L" @/ M" V) p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 I" F( a6 X) d o, C. Z- |8 a* Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( }( B( x5 Q$ i$ n5 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 U8 N- Z+ A0 l7 _" k) V" Q! G} 3 M" a. J; D. ]. W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . r- h& E0 x2 Q" D- F$ E: r
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