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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 B% h% Z! m; u0 p Tinput mcasp_ahclkx,
( H8 p3 n* E) }7 R1 zinput mcasp_aclkx,# _* U2 c' \* T3 z
input axr0,9 [; t0 `, t* |; E/ p9 o9 O
2 M* e# J b, q+ X% y* P1 C/ ^+ o
output mcasp_afsr,) h' C( V( `- F$ w) k
output mcasp_ahclkr,& @/ @; T2 ]9 e( F) j+ p
output mcasp_aclkr,
! E& B5 N) s$ |' \5 \& ^# poutput axr1,
' _: y4 f1 n& p& ~' P# O" { assign mcasp_afsr = mcasp_afsx;2 ?3 u8 f. M! W! E
assign mcasp_aclkr = mcasp_aclkx;3 f- `+ X3 L) r4 T( ?% I" I0 @
assign mcasp_ahclkr = mcasp_ahclkx;
4 K6 {0 U* j& `3 Z8 Tassign axr1 = axr0;
5 ?9 Z4 Y: V0 z" h- }4 a. d2 d2 h/ K
$ K {5 y( h( V5 L q9 ]0 }4 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' \' Z' V2 x0 }9 H! |static void McASPI2SConfigure(void); O1 v0 _+ \1 \% [6 _* q
{( L/ r; W8 \4 D# g/ ?6 M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 T' m- z2 ^: k% ^. e- [3 x/ r3 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# V A9 o" c0 g" R% w/ x4 u& }5 f! rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: C& a5 r5 V8 Z$ v! K3 {2 l6 G# \, cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* \/ H, w! T+ k W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 K. C* P' o- e, xMCASP_RX_MODE_DMA);
/ Y9 o8 j7 X$ \* P xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 b, G7 _/ x3 O. z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, K8 o2 B4 J' h9 n2 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 z1 y+ Z( e8 _6 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! P$ b0 |1 [5 K1 A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : F7 d! B* J9 k. t7 A7 p9 f7 w, ~( ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! T6 H9 e3 X& P6 ]* ~' @" h. x; B8 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 P# S P6 |% u+ D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( }) y* Q' l$ B# T0 [* H- V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 w0 c( h9 R+ Z) W
0x00, 0xFF); /* configure the clock for transmitter */
( `5 e3 a% K' vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 j- r4 Q2 B* p* X, g. EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 [7 e& d/ v- ^, ?" ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" E! x) W6 m2 T) A; P) |2 \4 o0x00, 0xFF);
; m+ V$ _, R5 Y* f$ e4 s: j: S3 ?! W1 r e9 h' `
/* Enable synchronization of RX and TX sections */ ' ]. v9 z `/ z: p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' ?4 ]* d$ R2 A; ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. X9 [3 `, `8 l+ y; k7 {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& z" X: [$ U# N+ O) H, _0 n** Set the serializers, Currently only one serializer is set as6 I) Z2 _0 Y4 ?$ z3 }- y2 {. W
** transmitter and one serializer as receiver.
0 j; K! `7 K# b0 h8 r*/( W: J( z* y4 X. q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- v; V7 |" T& WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% F# n7 m/ z* k3 S3 j" _3 v
** Configure the McASP pins
( m' f/ I m" o% x; R- A: E X** Input - Frame Sync, Clock and Serializer Rx6 G' a) b7 B4 Y% _
** Output - Serializer Tx is connected to the input of the codec ; h) u: Y; N) A- ~! |4 f5 Z
*/" ~1 `) H, W2 p O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' l! m& U5 D' \, h5 A$ m0 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, v4 D+ d- D- _1 ?/ G6 U1 n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* [4 x8 d: K( f| MCASP_PIN_ACLKX
) [3 o' o+ Y% \5 E) o| MCASP_PIN_AHCLKX! I! ^# o9 l& P7 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" Z5 w, r. H. R. U8 R; NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. p4 C1 k( Q# w+ v+ Z| MCASP_TX_CLKFAIL
4 F# H \( o1 R' j6 V| MCASP_TX_SYNCERROR- R3 K" g1 X1 Z7 U, o( n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * g1 Y" ]* L; X$ ]; L
| MCASP_RX_CLKFAIL
# {3 D! n* y# f| MCASP_RX_SYNCERROR
% w3 H! q, G/ U7 u) ?| MCASP_RX_OVERRUN);
" ?+ Y+ p" @9 ^3 T. d} static void I2SDataTxRxActivate(void)% z% w$ J8 t( c+ s: f& ~( {* Y
{
" _! X4 v% c% w& g/* Start the clocks */
7 p# Z- b. Q* H$ n& J+ cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 [) N2 y$ T: R8 |- J( i1 J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 `: {* M& ^9 c: v3 n& R4 h0 q; K" N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# _. e9 R" P$ p) `" U% l1 w" r! P9 J/ E
EDMA3_TRIG_MODE_EVENT);) O8 O( A( Q0 k7 d; `% s8 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) N3 h H; S8 |( ?$ ?0 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 O( X" \0 H$ X6 f* A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! F& A! G/ A5 k1 q# v6 ^3 B4 s1 WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* {8 Q% F7 ^( Y% u7 u* d/ K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 ^7 s9 a- Q0 x- }7 W' g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& J$ V. b3 t( }1 n. a( {* cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! _+ C$ H. |# S m) b. T3 E} / x2 d7 b9 j6 \9 ?" a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & ]2 [6 F' e- k# @) \" z
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