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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 W/ x0 F! J0 o) F3 q& V
input mcasp_ahclkx,
* E" k, x9 ?; T# ^2 M+ ninput mcasp_aclkx,
4 B6 O3 f% `2 M: b8 z& l# Minput axr0,
( o. x; b$ c* l3 e, \; ~! h3 `$ n. H; b. d3 N* t' _
output mcasp_afsr,
1 e/ L: S5 T3 ^output mcasp_ahclkr,
1 u$ V9 B$ c. ^' G; routput mcasp_aclkr,
5 S5 h8 F) i Z6 \) I& Ooutput axr1,
; K8 |+ j6 B- D' o0 L. K7 X1 m assign mcasp_afsr = mcasp_afsx;" Q5 \& s( ]: `! e' |/ F8 J
assign mcasp_aclkr = mcasp_aclkx;0 q# k! X) g. L; \* b; Y% P: \, L
assign mcasp_ahclkr = mcasp_ahclkx;
7 b) b* D, J' [' K0 b* r2 O+ B- massign axr1 = axr0; + x O9 R# O# o8 i+ b: k% V
) l) Z* S* q/ {% x8 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 M6 Z9 M: W' D. W" P) {static void McASPI2SConfigure(void)
5 ?. Q# Y/ [' X* l/ z{
9 r' d! D- K7 x. t8 `4 ?: yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
h& g- y. c$ H; MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ X: [5 `/ J$ K( \" c) n7 @2 k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" e0 K5 u& \ g, _. u: \. K; WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 {7 g. F$ @! R6 u9 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
d: G g U6 |1 bMCASP_RX_MODE_DMA);
3 b5 {$ w% c! E; o, O2 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ n, K% R! e! |: P! x8 U! I9 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% w, Z. r% p8 r+ q; K6 `0 K" rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; Z$ C( M# l. E0 S# J6 \. gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% h! a- C' A0 s+ i- B7 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ G. m# p- S. v. t- JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. B) P4 I! D) I5 y3 M$ u' l4 HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 J) Y& ]8 l8 p: _4 ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 k7 K ^5 \' j, V9 y' k: W+ x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 _9 e& E6 n3 {! [0 _# |' E$ `2 P k0 d
0x00, 0xFF); /* configure the clock for transmitter */4 U+ I* h/ H% G2 q% s0 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ s+ F% m1 ~+ n! U$ K9 O) IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . x f' q, \" a3 ?8 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' ?. f6 Z6 O* `4 a k+ N9 k! f( L0x00, 0xFF);0 m. e7 g5 X0 t. g
: W$ e E) K8 q! q! W! Q9 z9 v
/* Enable synchronization of RX and TX sections */ + ^% s3 Q4 s, } F" `/ _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' `+ d) q$ Q8 B4 H0 _$ H5 V kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ z8 }# ~: {5 Y' o: y2 b" }9 h3 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 ]( L& r& z$ F8 e6 g6 s** Set the serializers, Currently only one serializer is set as
% l- v1 M# y0 E) d. [** transmitter and one serializer as receiver.) U# S) o2 J: d- g6 g
*/
, {7 h4 e7 u5 P' W( LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" d, C) J8 G' E' {$ t8 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- X2 T# C9 M7 k& F9 ]+ j** Configure the McASP pins 3 t0 Q1 K! t# r! Y8 Y) ]' [
** Input - Frame Sync, Clock and Serializer Rx
( A. e, U5 P/ Z+ x. |: i4 w; U** Output - Serializer Tx is connected to the input of the codec
& `6 ~; j* I; y4 n; g0 g4 F*/# o" A9 A: t. J- d, ]1 T! r8 i8 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( a# V1 O+ @) ]9 X. c) KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' }* A' g* M$ ?% e! h5 \: e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 u0 H5 c2 |6 a1 e2 f9 L| MCASP_PIN_ACLKX$ ?8 _% D4 K/ P/ i# Q& y$ h
| MCASP_PIN_AHCLKX' C# ?5 o# ?3 s" X9 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 I. z; S. O2 U+ {7 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* Y6 ]- ]! p+ T| MCASP_TX_CLKFAIL
6 K5 k* g1 D, W; m7 H# e4 c. s" f| MCASP_TX_SYNCERROR* l9 S; H! Y! q4 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 y R) h& }0 W, Y) s( G) {7 B
| MCASP_RX_CLKFAIL& E. o$ b( L' m0 P' h
| MCASP_RX_SYNCERROR
3 }5 U8 t9 U5 `0 U: J! F j$ n" W| MCASP_RX_OVERRUN);" b3 R% M2 z s" S% G6 N2 l
} static void I2SDataTxRxActivate(void), f5 S5 D5 b9 G! m3 B. o4 A
{
H; \+ S% @) h- Z, v$ y/* Start the clocks */
) I6 u+ O A O" U: UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- C( U! r% s0 q4 U$ h- T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// C2 r5 N8 x8 |! T0 S9 h7 _4 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* d, Q1 T* u2 @7 tEDMA3_TRIG_MODE_EVENT);. X) Q& p6 F- x5 `, H+ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 M& k5 J0 u0 v* {5 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. b* E" y0 z5 n$ T& ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; j/ w X; K5 r' F) }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ z. A2 `# G* r# g2 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- b3 g* f, j& m7 y) q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( G3 R8 f, g9 O0 G9 }5 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 Z( H( O1 ~5 V: Q/ a+ q} 7 n% N! A3 X% u* o; P: c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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