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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- v* ^3 Q) n) h* {! C* Q2 }0 h( cinput mcasp_ahclkx,$ M" ~( e# o5 ]. Y
input mcasp_aclkx,
; y+ y2 p8 p0 U. iinput axr0,
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output mcasp_afsr,, ~4 k) U" U5 g4 `3 s/ n) K
output mcasp_ahclkr,
. p) M" Y& Z5 p I( i) `% Doutput mcasp_aclkr,% t% G2 R/ L% `, _
output axr1,
5 O0 G- V5 j6 ? A$ z" K: g1 l assign mcasp_afsr = mcasp_afsx;2 X* p" U: U' K8 ?3 g* Z/ v. ?
assign mcasp_aclkr = mcasp_aclkx;
6 d: Y. z A8 f# l% p9 {0 Yassign mcasp_ahclkr = mcasp_ahclkx;. B: F# c% w9 `- a+ }. {
assign axr1 = axr0; # W6 {4 q: o* k; P6 `
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! L' l9 _- H1 I; o# L2 s+ V) B Tstatic void McASPI2SConfigure(void)
7 A, E6 B% a( b. s1 f{5 y2 _; a2 K' f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, G& J0 Y) m, h# D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 S' o' O: Q1 I2 FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( o% L8 [& W. W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; x m+ k3 X! x. @/ i ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& c$ d* T* s+ Q% C, l4 T+ I
MCASP_RX_MODE_DMA);6 b; d1 Q3 l7 w. R6 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& ]# h# C1 _$ a' E1 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& C* _( p: X4 f4 WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 \' r m! |. w; d$ k; NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 I8 Z2 \; @! L. aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 r* w3 n8 P$ E/ ^! T6 p5 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ G, }. b) y1 M! ~! \" Z' j+ jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, V5 o+ I! d0 E fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " \' S/ L7 J( [' m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 [8 ?8 y3 @3 [5 G
0x00, 0xFF); /* configure the clock for transmitter */# e4 f( R; P5 F5 @7 n7 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 L7 I" H) a: P/ R) _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 k; u/ y- K! R" c7 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 `2 O0 H6 p) l6 S: j
0x00, 0xFF);
: q# M$ Y! g5 \- |5 J/ `' G6 E6 d" M
/* Enable synchronization of RX and TX sections */
# i6 t+ Q5 _2 j; r1 z9 c7 F( LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! A/ L j; U6 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( C/ }, u5 [" H9 D/ W8 G$ dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 ?/ [' P$ _2 h7 y- P
** Set the serializers, Currently only one serializer is set as( D: o6 B) Y9 h( B4 m; F1 e
** transmitter and one serializer as receiver.8 p. h# o# g3 k9 w( Z
*/
: j7 `: E+ v# y+ c; A6 F/ ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: M8 M7 V3 V. `& J4 U1 ^! Y# Z( z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% U2 d7 I$ j* U( ?& q4 N4 {1 Z5 T
** Configure the McASP pins
. M2 `. [# x. D** Input - Frame Sync, Clock and Serializer Rx
1 |+ a% E8 ~& C8 c" |7 S7 H+ r** Output - Serializer Tx is connected to the input of the codec
9 U- Z w1 L1 g, u9 r$ U*/; F/ ]+ h2 k, P9 ~7 \. W+ v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# t f0 \) @8 \; d+ m4 d: _. X$ @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 n3 t, B2 \1 p" }6 g4 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& U9 c0 r! ]6 e3 u# z! d; T| MCASP_PIN_ACLKX& M( n& {5 B. F' V; g0 {" A+ c
| MCASP_PIN_AHCLKX
) y1 i6 E6 D' Q% ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 a+ ]- ]! \9 ?; @) E/ z9 qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 B; A2 M4 v0 l" j: z+ V; k| MCASP_TX_CLKFAIL
1 q' \/ @, _* g0 z2 Y: g* {| MCASP_TX_SYNCERROR" x# y/ p5 Q. ]) F& w2 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - J" ~/ G+ V5 z9 k
| MCASP_RX_CLKFAIL
! y/ N [9 ^8 C| MCASP_RX_SYNCERROR
0 [; |: d [& p& v0 || MCASP_RX_OVERRUN);' v, g* V6 ]- _
} static void I2SDataTxRxActivate(void)
% _6 g: t7 l/ Z% o{! g* v3 [4 P! Q; B
/* Start the clocks */
! H- U- F( n. }. ~0 l: A, PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, m4 Z/ Q5 X. Y2 d* i7 z L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; B4 e$ I; D: u* L: ]4 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 R" Q1 Q1 p2 w4 k! pEDMA3_TRIG_MODE_EVENT);
* t4 r# E4 X3 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . ^' v# [5 I; }' r% j. {$ Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 L4 D- M$ q6 U" a8 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 g! n/ I0 O% X! u( J$ i/ xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 _2 d' d+ r" z+ Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( C/ l" j) S/ ?5 }5 a. x% gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. ~# t$ |1 m9 {% kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 u1 o( Q* [7 O8 k}
9 i& j2 o" \, Q8 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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