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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
J! e3 q8 p- r6 {( minput mcasp_ahclkx,' B2 F1 L6 v b* O9 \7 p! C8 v; O
input mcasp_aclkx,
- D6 c/ t3 N0 ^input axr0,
. r s2 Z. I9 Q/ \0 |5 L. `$ b* }" C: c
output mcasp_afsr,
$ c5 a8 Y3 [: L2 V6 E/ Toutput mcasp_ahclkr,
2 @; Q0 U9 ~6 N' Soutput mcasp_aclkr,
- v0 N4 z' V, r7 x+ x7 R/ U( ]. Woutput axr1,
! y. h6 P6 o$ U; G assign mcasp_afsr = mcasp_afsx;
! [/ ]0 [, u, U7 ~4 u f2 Gassign mcasp_aclkr = mcasp_aclkx;2 a$ Z5 T! _) R. C0 O) A6 W+ B; L5 ]+ ]
assign mcasp_ahclkr = mcasp_ahclkx;. K0 D8 w/ G4 x7 Y9 J9 A
assign axr1 = axr0;
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" o' ]0 B4 Y; l* L3 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ q$ \" B( l# J" a/ x: K' jstatic void McASPI2SConfigure(void)& V- m& X$ k( |
{
! p2 v, f6 o3 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 y7 U4 d2 b/ y' b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ \* E2 P/ f% V0 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% s" Y5 o) F( D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 U, X' Y! X% T! x: [! x* {: q4 kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" ^- ?7 f) R- p. `MCASP_RX_MODE_DMA);4 v6 M, g0 \5 N- t- F) G& U. d* P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 K8 l+ K: z* N8 o% u# lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! T: z5 `) K& c4 K5 _, a4 |* `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 R1 e) O: u8 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 [: r% }: v7 s% }4 ~2 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 _, E; I' y' f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& p0 W1 H; \. g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); x# X8 D$ U, ?: L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# Y+ \" j* o+ s9 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; v5 F5 b+ g' x; X0x00, 0xFF); /* configure the clock for transmitter */
" k# I8 o( i+ ^8 W! R$ q+ ~9 D IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 V1 a- s2 `% v$ ~7 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 O- a6 u, V1 F! b! X" c9 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 b: o! q* ?8 D! t8 I0x00, 0xFF);
. e9 ?7 v, b+ p2 _- N# s, Z% j i; _1 y9 U' o9 I
/* Enable synchronization of RX and TX sections */
3 U: m0 C$ i& q. m: ` {7 X3 iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- k# y- c' J0 W1 \6 i$ t4 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Q6 i9 L3 |( ]) `+ s/ m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 q% h. A7 {4 v1 Y) e** Set the serializers, Currently only one serializer is set as) b9 j, @: W' S8 b9 V
** transmitter and one serializer as receiver.
( I0 k/ A# V) A6 l*/! y7 n( b) e4 R( ?4 P* q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 K+ n2 X- g6 {8 e' w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 J5 q8 [+ L# [2 F9 X# r! t, E** Configure the McASP pins
Z" V {& r; I( v2 V** Input - Frame Sync, Clock and Serializer Rx
2 k; x1 V; G0 b" Q% l7 M** Output - Serializer Tx is connected to the input of the codec
( P% h6 x/ I5 f- i*/6 a& Z$ }) v- U+ z1 _7 t* `2 D: B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# o' p4 m6 {/ t6 A& iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: P) ^, L- |7 M. t1 ~+ x fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: ^1 r: F! I+ ^, V7 C; }3 _
| MCASP_PIN_ACLKX7 t: B4 f+ x0 p! k& F2 c
| MCASP_PIN_AHCLKX( S: i8 c, g f; \ g0 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. w* d4 F& i, v& z! p; x2 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; Q$ M% Z) v W& Z0 R
| MCASP_TX_CLKFAIL ) V) k. N1 {& d/ X, C
| MCASP_TX_SYNCERROR8 S! V# @# R# b' y# J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" f+ q5 ~' j, w" h8 P| MCASP_RX_CLKFAIL% S; w) B* N0 l5 R
| MCASP_RX_SYNCERROR 3 h D U1 b- w2 C/ I) m
| MCASP_RX_OVERRUN);0 j9 w0 ]; }3 ]1 z
} static void I2SDataTxRxActivate(void)
3 d6 G3 k5 P7 ?/ Q- ^6 T+ P$ W- B{
2 {. r# _8 V: f7 t9 T/* Start the clocks */) \8 G b! R z# f: h9 I3 ~8 g% ]1 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 [, X% `" e+ r7 L. Y( `+ b. Y g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 R) X. n5 x b8 g2 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" A. v7 p5 j8 F3 ?) ^& I8 hEDMA3_TRIG_MODE_EVENT);& i6 A" h! h( \$ ~1 _2 l$ r! [& r: _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 p* E0 _$ y! x+ D5 P2 ~/ NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 o* ^6 L+ B' r1 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% |8 W) h% W4 T/ Q4 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. I; J; I: A2 T8 S; D$ U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; Z1 Q# o( L+ ?0 m5 }( s( h. k* GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: V* B" T, \% [. M' p9 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- Q4 l: s, u; h7 G4 r. Z} 8 a% ?# ^2 W1 @6 ]/ ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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