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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! P* e2 w* t' N% s- `3 X
input mcasp_ahclkx,
% N0 v$ _; m l1 B: A; f2 c, {input mcasp_aclkx,8 c4 a# T* J! O
input axr0,
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output mcasp_afsr,' E9 }7 W( `* y! f% [1 r7 K+ |
output mcasp_ahclkr,1 ^! m/ G c* u# d p+ n6 |* w
output mcasp_aclkr,9 Y- G0 E& k8 X: L6 ?' {; k3 E: d
output axr1,0 d' |* E$ n4 Z; H5 K
assign mcasp_afsr = mcasp_afsx;8 \1 l: Y! p+ e' Q0 |# U
assign mcasp_aclkr = mcasp_aclkx;& t8 V4 ~$ R4 G3 Z9 u. |! L4 @6 N
assign mcasp_ahclkr = mcasp_ahclkx;
* x8 X! ^6 B) Eassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( i& j8 h) U, g
static void McASPI2SConfigure(void)# e0 m' h/ f! G$ t1 [
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 g+ B3 q0 x) B1 q D: k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// z' m, i" L% O' L& r; n$ Y. w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ r( }6 v( h* _- k. IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( X3 ?" g4 c6 y$ q& e" j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 v# |( g& c6 G* [8 [
MCASP_RX_MODE_DMA);
5 {) J4 ^; R1 l4 W" ~; {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ G+ ^% q* L5 b, L3 b: tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 g, T' Y9 B9 k% F& M: `5 N: O, U9 j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 T6 ]+ Z0 v3 P7 V. |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. N9 j' E2 g5 K+ G* \! Q6 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ H j# S& ^& |; x k0 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 |6 ~8 _7 g5 _* N8 _' _3 hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 A( J4 N6 z7 f9 ?: j; A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! {' q; B0 K. [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! Y0 X: @8 M+ d. `
0x00, 0xFF); /* configure the clock for transmitter */
' V; J' U7 {' o* s+ HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& \: Y2 k; u; l5 q7 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ }% x. H$ R' g6 Z J& ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ a$ N1 W7 @/ a$ y0x00, 0xFF);" G1 I, r; S) H. ?' q' i5 y
/ Q9 u+ v( |- g/* Enable synchronization of RX and TX sections */
/ r- c F; J% z+ e' B2 UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) u0 X" ]! f( J8 N; bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' X' Z6 R! `. F) W! P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 b- o* Q. B3 K4 p x `# k Z5 \* b
** Set the serializers, Currently only one serializer is set as
- w* H5 A2 \; l7 T' A, l4 U/ N** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ X7 [( ?) ~$ A9 l! _' }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! G4 i0 a+ {/ F5 E: @3 }9 L** Configure the McASP pins ) M+ b" K# ]; a% M' G. p
** Input - Frame Sync, Clock and Serializer Rx
& x& u; I" T( G3 W9 {/ G: E** Output - Serializer Tx is connected to the input of the codec
5 v: `, ~, L. M*/
) p0 C" \0 X$ N) ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. n1 z) k% v* D5 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% @8 m. n( @/ J+ l1 ^4 }3 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: R5 G5 v1 P, P$ _1 {| MCASP_PIN_ACLKX! t3 f/ ?% Y* B0 C. L7 E
| MCASP_PIN_AHCLKX" m8 n: Y; e& ^5 r, m, U$ i7 R5 H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 Q9 d/ R# S) [0 `8 K+ O% ?5 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, R8 r% T7 o2 L8 w0 Q. [: a, N| MCASP_TX_CLKFAIL 6 w0 X4 {& P% _$ s
| MCASP_TX_SYNCERROR
$ N+ k6 V5 u( X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ ~$ k% t' a. f+ F, M* W
| MCASP_RX_CLKFAIL- Q+ [) M! p/ C. o$ Z' B, w, a8 }
| MCASP_RX_SYNCERROR
" c/ s2 a# G( ]& P; N: T* v2 O| MCASP_RX_OVERRUN);
3 K& s. ^9 a' s} static void I2SDataTxRxActivate(void)+ V7 U8 E1 E, l2 w6 z) r
{; v1 v s; w2 z+ V' b/ {. k9 n) O
/* Start the clocks */* t& n t" W) _' I" k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 i6 ?8 Q) o2 s; n* q- dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 ^+ b- w c \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. y& h6 w& B; x0 G) Z1 I
EDMA3_TRIG_MODE_EVENT);# s+ H# i7 x& P: i% k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 V" C5 q3 h$ {# UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' y; T% L# n2 C+ L9 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 N1 x+ A! _; c/ B R' \) f3 [+ ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# F/ s+ c6 Q" G! G! o: M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& P7 S: }: d/ Q/ t8 x \4 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: s! B$ d7 S& J0 I9 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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