|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 u$ M% U% b8 j. minput mcasp_ahclkx,% c" q9 [5 _3 s* w4 D
input mcasp_aclkx,
& v1 `( v- \% \* O1 l- O+ Oinput axr0,
/ M/ w3 g: ?+ ]( H0 \/ r+ n I) D0 M% ]% @1 D; k- H1 m
output mcasp_afsr,' y8 D J" n- ]2 H* K7 r% Z
output mcasp_ahclkr,
: y% q" A4 M2 A" _ ]' Voutput mcasp_aclkr,
. T( i& X0 b; A* k- a6 ?output axr1,
3 g2 Q# w& T3 X assign mcasp_afsr = mcasp_afsx;
1 p% c2 ]; l. j7 p/ a& Lassign mcasp_aclkr = mcasp_aclkx;
7 _3 w9 J- U- z; P$ a: C7 kassign mcasp_ahclkr = mcasp_ahclkx;
k4 d% Q \* {1 T7 k% ?1 I, Jassign axr1 = axr0;
1 z/ T" \5 `0 u" D) k. V* ^6 z! W: ^. E. W8 x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 [8 ^- m( N& {" j/ Dstatic void McASPI2SConfigure(void)9 [ S, W8 [1 R8 ?8 Q5 y
{
" Q# }- s' J% G6 V* Z9 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: E5 T$ K% I1 a' y6 T) N7 a9 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: @' n) F- q+ Y1 x' [! xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; V0 b, A# P, x: _& _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- @, j f4 l; n/ [, K0 Q9 [4 PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; o1 b. i" w7 H; R5 h
MCASP_RX_MODE_DMA); a: r! z. C' V+ |: c, i7 E2 \5 ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" V- b7 _2 e; P) FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' f, Q! Z, L C: B9 j1 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, z. S/ K r) c G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) _6 M# P& s$ b# ^% @8 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 Z1 g# I" S8 K6 W" P) [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 n T/ ^' f. A# |, [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* m `. i" b( V# o5 A+ q/ Y O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 G2 U; o$ i# T, W2 Q" \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 l* B& y: l, j8 V0x00, 0xFF); /* configure the clock for transmitter */( [, m# `+ s# m, j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, U4 X; D3 O6 |' M7 F9 }7 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 a- ]2 P" c2 d! e" VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& d4 q* c: A# P" ~0x00, 0xFF);# N+ [% }" J( y6 o" \" a
% o s6 X* l# E: d
/* Enable synchronization of RX and TX sections */
8 r+ q5 Y& N( c: H# KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 ^' E2 D& E8 H" b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 f( h; K6 a. C) EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( k& d2 p, h$ T- Z" a, A
** Set the serializers, Currently only one serializer is set as$ V3 |9 v$ F+ A9 J
** transmitter and one serializer as receiver.) d) } A# w, ? I3 Z& Y
*/. R" L% Z: g* C4 ]) ]3 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 k' n0 G+ e! ~7 E9 i/ H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; u v, x. \& r( _, _2 m ]
** Configure the McASP pins
( i) f7 B) ]* [** Input - Frame Sync, Clock and Serializer Rx+ b& N5 N: D8 C$ C# z) S
** Output - Serializer Tx is connected to the input of the codec 8 ?: q$ ]8 V' `/ u( s2 Z9 F
*/: B% m3 K5 ^: f- J; i; \5 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 Z4 U6 C+ x. Q) o2 _. |9 {! k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' s$ Y1 Q: i! O7 q2 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 F# Q7 ~5 K/ Y& _) J+ ^5 \
| MCASP_PIN_ACLKX/ X! a# |' w) m3 @* {* a5 J
| MCASP_PIN_AHCLKX! m) M( H! l* f3 E7 l. A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; {& l# q- h, k" ]/ @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 O; p2 s+ K! P9 V! D% O/ Q4 \$ R| MCASP_TX_CLKFAIL
9 B( Q3 i6 X) F x| MCASP_TX_SYNCERROR
3 \( J! h) Z8 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' C3 H& x) l- x8 m0 Y7 \, @8 h| MCASP_RX_CLKFAIL$ i- w3 q; @8 n7 G e }
| MCASP_RX_SYNCERROR
V- f2 D1 U, T1 [| MCASP_RX_OVERRUN);
S: O6 i( e; ~* e! j* x/ F} static void I2SDataTxRxActivate(void)' A8 R4 ^# c# T- p( _& H
{# @. {- y3 H6 |
/* Start the clocks */
( Y5 X3 Q- g* E) xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) s4 W" g+ w) O4 Z( Z( cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# I+ i# I$ f# B6 Q# GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ z U4 I, w! k9 F/ f' tEDMA3_TRIG_MODE_EVENT);' V1 v5 C! b& t/ A! i2 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . b/ C4 B7 a9 |$ Y( H; {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* A1 K& J0 F- I$ P0 Z* [: K. iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: O+ N+ P/ f9 V X& M7 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; b% ~9 ^0 l+ T8 q3 Y' C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 m" F( U8 F+ E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 C1 O7 w) X# }1 MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- v7 b! _; j$ q5 q; G2 s4 C8 c}
' m( R) v& X+ S+ i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
' j, M1 b* v: `2 t |