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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# g& \3 ~# f$ y% q9 A" K% o" i7 kinput mcasp_ahclkx, `: h- {+ c* b' j# C" A. o; X9 H
input mcasp_aclkx,
% w( M+ V! [( x+ S; q! u6 ginput axr0,
9 H# x! B4 E% c/ u3 n6 E5 U v
; h$ ^( d% q% o( Routput mcasp_afsr,3 B" U" k/ r1 V$ J
output mcasp_ahclkr,
8 i& H& N! Z' U+ foutput mcasp_aclkr,* k6 w/ V4 O( o0 f0 p* w; I
output axr1,
0 V3 i" Z& l; {8 m+ D. Y v4 T2 x# h assign mcasp_afsr = mcasp_afsx;
% U$ r8 z: I: C; N0 h! ~* ]assign mcasp_aclkr = mcasp_aclkx;
' E$ O+ `! b" D' u1 h) f% Vassign mcasp_ahclkr = mcasp_ahclkx;
% P, F- @- n( M2 N! o0 G- y! H; eassign axr1 = axr0;
7 U" U9 [% ~/ A, o/ z/ G( l: e6 B$ O9 m1 ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( {) k' d4 m. M2 f4 @
static void McASPI2SConfigure(void)
{$ z; F, {" w- ^{
# j- t& \1 y. g+ UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; ^" W, w% ~" KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' I% r! R5 E/ y! L4 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ l6 ~' m) }( ]' }: h; L' r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ @5 ^% O: G* W* b) d6 F- pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# j$ ? E2 U- e5 n5 H( fMCASP_RX_MODE_DMA);
- Z/ A* B# h" TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( @; k! F) b7 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 P; j7 W5 i" _3 n5 F* s; H6 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 _! v) [7 m0 H2 d1 I4 j/ d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ i2 e. _& k/ } J( `4 n( i0 |/ x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) R# M- J/ i" Y7 S. X kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ J( K/ ?9 y3 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 L, i, a6 v7 b; l- L5 }$ q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " X0 c) n1 z1 A! J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( g1 f9 o- b- E
0x00, 0xFF); /* configure the clock for transmitter */ U3 I7 U& i4 L' ~- S# [. M5 {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% _+ H' w3 g) `# i. [' v6 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% [/ J8 L2 ~) g( c! DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& O! D! T. n/ g/ q; G& k" n
0x00, 0xFF); H6 F4 `) Z2 L4 t
9 h2 ? o1 g& Q, R% ?9 ]2 s
/* Enable synchronization of RX and TX sections */ 3 B' n) x% \% `; k/ w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 _% Q; v" _5 m6 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% H% M: |1 G( J$ B' [1 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ z0 T, F8 t4 U! M, ~! Q) P
** Set the serializers, Currently only one serializer is set as& D& O. v2 G$ t
** transmitter and one serializer as receiver.
0 ]% r" y* H2 Y1 G: Y*/2 V( U/ Y8 X; l* t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, C2 O- u4 e3 n, N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% b( e4 H- E0 j1 `** Configure the McASP pins & b3 Z9 d8 A2 _) H% ?8 w
** Input - Frame Sync, Clock and Serializer Rx0 R: I U& y0 b7 G
** Output - Serializer Tx is connected to the input of the codec , m7 P) ]5 Z, h) H& h9 l: g
*/
- `2 f/ d* D: O' o% H* j; z) gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ w& y8 q6 Q( S' H$ b5 E4 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# _. p; D' {7 N9 u1 v8 |; k# p aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 I; u* W6 M$ K+ |% y$ b| MCASP_PIN_ACLKX# m1 Y( r& {; S/ D, F
| MCASP_PIN_AHCLKX
x& N+ e, s3 [# C6 f' ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ @% p, A! ], X7 e# B* i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 Q' w) T* T3 Q0 ^! p, F| MCASP_TX_CLKFAIL $ b0 y* {0 z/ ]
| MCASP_TX_SYNCERROR
# L) a$ v* [2 C+ p8 Z/ g: q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 g2 h( C: R5 {, f" o' W Z| MCASP_RX_CLKFAIL( V4 a, p. O; @" ^( m% g0 P+ g
| MCASP_RX_SYNCERROR - D( N5 j' j! `* p
| MCASP_RX_OVERRUN);
" d2 U4 z8 k( R: v$ }} static void I2SDataTxRxActivate(void)2 O8 c |& K6 ]$ Q- O. C
{3 u5 S& `0 r- b
/* Start the clocks */2 h% `; N" J) \! r, d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( n6 N+ w: M* LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 @& y1 w* J4 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ F: \& c9 W6 Q* i/ N
EDMA3_TRIG_MODE_EVENT);
% D% G( A0 Q1 J" o4 |( xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / N/ [$ |4 x1 ]$ K6 L- O7 h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 Y! ~+ x6 B3 n1 w- }- f9 d" Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* z% I0 W; I' V- {4 S- M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 G8 _9 C0 c( B' j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# [8 R5 |8 t$ ^ F% e3 |: i6 o! s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 v6 `- |4 v+ P1 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( U. e: _) ^/ w- L( ~, P9 g
}
1 J- ^& Y' o% y+ O N% e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ f/ f( p5 `/ J. T
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