MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
7 s1 H' I  ?% kinput mcasp_ahclkx,
input mcasp_aclkx,
) w, ?1 _; g7 f0 o$ g4 Y0 y4 [% pinput axr0,
+ O5 a" t; s" q9 @% E9 [
output mcasp_afsr,
1 c4 s) B: u9 P* b1 ]8 voutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

3 P2 Q. ~0 v4 W5 V! j+ o

static void McASPI2SConfigure(void)
1 [/ W) r/ v+ R- s" _7 a( G{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
3 w0 P( Y0 V, s" U( bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) R  z" Y# T% ]4 v# u% ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 E- ~6 @0 y: M$ _* hMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 E) Z$ g7 v) ]" C( ^9 T$ k  b9 EMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) p; H5 w: |. z) DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 p  [# p" t$ Y2 n) h/ f0 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* ]5 q) |, S4 [  [2 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
# a/ Y+ q- n! i$ z% X" HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# @* B4 u. e0 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- k. s5 `5 v# A" C* s; g1 z' V3 E: n0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 ]! p+ o9 {8 hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 _/ T- E! w. |  S. s& M6 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 s# r. S: b* N0x00, 0xFF);
: B" V! O$ F! m4 E2 P: |  k/ k
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! F/ v7 o) q; Q3 N: c2 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
- ]8 o2 m- K& U+ `# ~# C6 @** transmitter and one serializer as receiver.
6 z6 {$ K  t8 c- g5 a& {*/
6 L$ z* u8 Q- R2 Z8 ]) _5 }% rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 }+ a% f; G- g& x** Configure the McASP pins
3 \; [: ~/ B3 _** Input - Frame Sync, Clock and Serializer Rx
- H( r5 t0 m# y+ t) q+ v3 W** Output - Serializer Tx is connected to the input of the codec
+ g4 E: J6 ]6 r  [$ t$ y*/
& ^* x; q" f: s: T  d8 j5 a( rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, T0 R1 N" }% A- _9 l7 t- o( hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 R- }: B! T$ k7 \: T; g| MCASP_PIN_ACLKX
+ N: o$ B% b5 K2 [. r" C# Q+ ~9 l9 z" A| MCASP_PIN_AHCLKX
% Z3 [5 J; }& E* h% d| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
, @) I6 O* P& D  L1 u+ b/ t- m( Q  LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: R/ w. _" z9 {2 T5 i| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
, o5 a8 W& a5 E# r: ]* x| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" x4 C0 Z# g; J! ~; N- _" M| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
; R; f4 n9 e, \2 @6 r$ m( aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
5 v/ f6 X8 K* S/ sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ ], X/ k1 e1 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 E( t$ t2 o1 v7 \. `) R9 XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.