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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# _% a. f) h6 Y6 t( f. v8 a- k
input mcasp_ahclkx,
' b1 Z" [* Q, R% Sinput mcasp_aclkx,5 Y, P1 u8 y8 N9 A( ~, h6 ?
input axr0,
1 w# }7 g5 V& l8 t" U" V# l0 |
6 r+ t7 N& z+ r; e& joutput mcasp_afsr,! P) R8 E! S, ^- ^" D6 |
output mcasp_ahclkr,
5 S' b8 s6 q! Y* ?( l) woutput mcasp_aclkr,3 t6 E* h; a3 d+ N. V1 v- y
output axr1,
! W W, X9 P1 b6 W assign mcasp_afsr = mcasp_afsx;
! Q6 O( P: Z; W9 i+ m k6 |) massign mcasp_aclkr = mcasp_aclkx;1 e0 Y J Q! y; M. R
assign mcasp_ahclkr = mcasp_ahclkx;7 j0 ?' ~; \. y, K: [
assign axr1 = axr0; 4 k0 R' A! m9 v* J
5 d2 t7 J7 C8 v- ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* o* W; A! U* D/ | @static void McASPI2SConfigure(void)/ ^( |% S. S6 V5 C# P9 D/ ~
{
; z# s% @6 N" b: \6 y6 K8 N, j% N0 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' l) ?" N% y% K' WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ v& f& l* w7 l8 y* W5 n) S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; \1 L; z3 { x; A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% F% ~6 i+ E" [3 Z7 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ^# ]- `. @ w: q n) o; ^6 qMCASP_RX_MODE_DMA);
4 K7 F$ D1 C3 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& f; }- i" e% q- }! z8 P: M) }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 q0 F" n1 \0 V- MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 N; o( \6 P. N2 C7 \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' `2 N) t' d$ q) t I7 w0 M2 l" ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( z" B3 p G) ^! K) A; L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* d; H+ G- L9 `3 r0 U2 g9 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. d; S6 F# r( `( _( m3 z$ r# GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ V! w ?; ~" O; m. v9 w9 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. M2 V$ @: e/ m& l7 K. W B
0x00, 0xFF); /* configure the clock for transmitter */
8 k# h% @+ s# E( Y0 x0 I+ aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 N1 J% A5 y M% _/ Z. w& A2 q) J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) r d1 g5 {9 b& e& H cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! g& ^, i& k% E0x00, 0xFF);
# q8 }' P; T X7 i2 p6 [( B2 Z7 ~% o. X9 ?( o& V
/* Enable synchronization of RX and TX sections */ 6 f% w7 Y6 D/ q- N U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ A5 T4 q2 ^& k; e; \$ A& `4 R+ \6 T, h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- A$ M7 p. r1 {9 c- z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* b; P) }4 ^/ g" q
** Set the serializers, Currently only one serializer is set as- P$ G1 `2 `7 p( a* \
** transmitter and one serializer as receiver.
2 a; Y: A- m( L. x*/. L2 }' z+ f3 w4 o* v! x9 b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ s4 Q1 v/ U! n: X. d. _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ h* w2 E8 F( ~: M4 p& L6 J** Configure the McASP pins
# M n6 R$ U9 j. h# P/ S** Input - Frame Sync, Clock and Serializer Rx7 i' }; M0 h% ]- T/ k: d
** Output - Serializer Tx is connected to the input of the codec
6 S" m3 G- R& _+ Q* M$ t4 L*/
1 C5 @9 h9 \1 V6 n' M+ [( IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" n2 H" Z' j/ N" f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! e* a5 _; e' C/ i# }" K6 S* w* L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 v0 ~/ @* ]2 ^; _, G3 [. K
| MCASP_PIN_ACLKX) }( N# n8 Z- W4 M" B
| MCASP_PIN_AHCLKX% f: w( H! [8 A4 ^/ Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" O5 D$ @# g) F0 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! A4 y: l8 W( {- }3 H, B
| MCASP_TX_CLKFAIL 8 o8 R) n; x. u# o* @
| MCASP_TX_SYNCERROR4 S) ?! S% Y ]! Z8 T- Z# c( A# U, L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# y' m0 n; z U: N; z| MCASP_RX_CLKFAIL
& k6 i/ E- i' d0 K8 _| MCASP_RX_SYNCERROR 9 a. h# N9 `' Q# v
| MCASP_RX_OVERRUN);9 h: y0 z0 x' ~
} static void I2SDataTxRxActivate(void)
- ~- b* [: _; M5 V, v2 B{
" Y: {" p/ d- V$ \9 _- Y* i2 G/* Start the clocks */
) g- O8 j& k# M( PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. O1 ]' c9 K; _7 p5 [9 l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( B% K5 c4 b: D* Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, a7 T+ H0 L2 _9 j8 G8 @2 H- U ~
EDMA3_TRIG_MODE_EVENT);8 {9 z/ X. G1 A% y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, [, ]/ ]; o e. j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; H+ [) O- m& _; q- iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ x( o2 @* [7 [0 S n" N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 T; W) [$ M0 {9 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 a' U8 g+ @3 |3 s o, BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. U& ^: z3 }4 k0 _ K% {& ?: f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; q3 J" ^9 }$ T( T# o4 h* y3 U
}
" u5 A) W/ q* _2 I0 E. l8 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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