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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 \$ c4 {: u3 i- u# X. A
input mcasp_ahclkx,
5 J8 P/ n3 { E' q0 qinput mcasp_aclkx,2 r6 n% s* b9 H5 s# L3 e( I% d5 C
input axr0,
, e( Y5 v( z; s' b! @- _# ?% K8 v
8 ]- e* G% h- _1 q/ ]output mcasp_afsr,
' w5 i$ n5 [0 X2 foutput mcasp_ahclkr,
8 b* m8 D) E" r7 G3 s5 c; n3 Noutput mcasp_aclkr,
' s& w# s) r$ s6 B% d$ }. Qoutput axr1,. B1 u9 b/ t4 Z( c- f! m7 Y& E) ?1 @
assign mcasp_afsr = mcasp_afsx;
- \/ ]9 |! g: e- }& P: u8 g) U- @assign mcasp_aclkr = mcasp_aclkx;0 e9 x5 ^6 I0 t" d" s) x/ Y6 i
assign mcasp_ahclkr = mcasp_ahclkx;* E2 u# n, |' B% |8 Y$ X
assign axr1 = axr0; 2 j: o( W$ u' R# [5 \$ p& @# y
* v% g5 ~7 ?# l. m, \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& n: g: {/ \! J9 vstatic void McASPI2SConfigure(void)( e* m" M+ Z2 ^$ D6 u' {
{( {/ ^. K' o$ n* X' b# q1 y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 `6 X/ \/ k5 h3 e- aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 C. H ^" r4 I2 Z. U2 h9 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' g3 O6 N7 ~ HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 e: I+ A( v$ WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ }3 ~+ U5 N* S* O3 S$ w
MCASP_RX_MODE_DMA);
1 Y; |) }+ r/ fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, Y# P: R. x7 W2 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 l3 V- [, J& ]% Y: K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , o0 M* E3 Z l G' E! ^5 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; Y ~1 H2 v/ \5 D8 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 @0 y0 C2 ~; u+ Z. v3 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; t- z# @8 [% [1 i7 q& C: Q, h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. a% k1 X1 {4 R& m5 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% c/ {% o! r8 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& `6 d |: W3 A, J; p) w6 [. D8 t, p0x00, 0xFF); /* configure the clock for transmitter */. }( m! I0 R/ N3 T7 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# Q4 P) d5 n8 t+ K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 m8 A5 }- A! @- Y9 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" w) i" k1 C6 A& R* a( s9 B2 w" l) U0x00, 0xFF);2 z# f |# J7 X
* {7 [. u/ @" b7 F, q
/* Enable synchronization of RX and TX sections */ 1 v% A p( J- ?& S& I3 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 Y4 f5 f u% Q1 j% d8 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ^) y. L) ~5 A$ f& z0 t$ b+ Y3 E" i; pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' f8 d7 W; u5 t$ w v$ O J** Set the serializers, Currently only one serializer is set as0 Q( `! t& ~* l3 ]; z6 M- v
** transmitter and one serializer as receiver.9 q5 K9 D2 {4 \
*/; X ]& f( ]7 Y! N' o! U7 ^0 h5 `$ x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 L" C+ o, X4 d5 X1 ~8 H. A0 Y* f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" o& x$ P% u0 ~5 z
** Configure the McASP pins 0 Q- K3 h! W; ^4 x
** Input - Frame Sync, Clock and Serializer Rx9 k& Q7 F' \3 E
** Output - Serializer Tx is connected to the input of the codec
" H P' B. @8 f- r*/2 r( M" \& z+ f6 T; R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' W8 A/ C' N: N- u6 d3 P) \0 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# h- Z( X+ R; LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 j |& s* m$ y# A. b' l1 i| MCASP_PIN_ACLKX
7 B& N8 ?- R' z5 h* E, h: F| MCASP_PIN_AHCLKX
; x5 G; B( d* N; t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) J u, |9 ?& Z# Y# g1 b. WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, M/ Z! u* ]3 X( p% k( w| MCASP_TX_CLKFAIL
' A2 I1 Y2 e( l' N& [3 b# q| MCASP_TX_SYNCERROR9 J- h5 x3 K9 M% p: o9 Y0 @; b) S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# ~" [- S5 a2 W- \$ `# m( c9 |0 M* Z| MCASP_RX_CLKFAIL/ k0 h+ `' E( J
| MCASP_RX_SYNCERROR
) G+ w ~2 c) s5 P8 D2 {| MCASP_RX_OVERRUN);
2 ]2 A+ j: _, z f1 W: _} static void I2SDataTxRxActivate(void)8 F9 c v/ s' v9 V$ I
{
3 w0 ]; g( f. I/* Start the clocks */9 r i# J0 u" t) i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* d Y3 R7 k: EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ x9 f4 t1 W) I+ ?, M& L# Y" K2 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 ]& m$ t- A, N: m
EDMA3_TRIG_MODE_EVENT);7 G+ w( N B" g$ g6 q2 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: J0 [3 D" I, C+ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& Z" e+ R" T4 Y; SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 e' x1 C# j. R: a [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 t& ^! H' c- b A2 Y2 Z6 t9 t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' N1 p6 B, x1 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 ~) V. i. z, ^/ I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 N" e) Z! `" O- z5 _}
" S7 p/ ?# b# Z5 S% Q- i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . n! Y. ~! @% c+ O! x; q# C
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