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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- z7 i- v) h8 `5 f% c/ v: binput mcasp_ahclkx,* s e: L9 D, I5 k( E$ Y; m9 G3 G
input mcasp_aclkx,6 w/ [: _6 k. g0 y
input axr0,
0 ^: i4 o1 q: c9 w6 |! Q
j& p- q* E8 q! loutput mcasp_afsr,0 m5 N% ]/ r I+ G+ F; Z' [1 Y
output mcasp_ahclkr,
6 I8 D; X1 x h2 x+ C1 moutput mcasp_aclkr,
$ l- ?2 v% J% x `output axr1,. O. N' f# v4 U
assign mcasp_afsr = mcasp_afsx;, a$ l5 {% x5 M6 y, X
assign mcasp_aclkr = mcasp_aclkx;
& N8 ~ E9 ~7 K0 M/ lassign mcasp_ahclkr = mcasp_ahclkx;
( x; i% Y: ^& ^2 ]8 X1 g0 t* lassign axr1 = axr0; 1 Z7 G( c( E) c
3 q4 Y, g- R3 ?5 d6 C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( H4 M* B9 u2 d) c- ?! V* x" lstatic void McASPI2SConfigure(void)
% w" C A. T* Y! Y" k3 E! m4 r{
0 h1 v m, @7 p, a4 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ B% d, e2 g% ]% f) R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 S& Z g: r$ u9 @ O; r- X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 A' f) ^! N: a: A# q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 a1 V, j5 y; L2 N( AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% R' F. h8 }; Y1 F4 S4 i3 qMCASP_RX_MODE_DMA);: l8 `2 v2 ^, b8 G9 m7 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( b. f9 p8 }/ ^( F2 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, D! ~6 `; m, o0 WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, g ` K4 e w: |( J7 s* s: _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ e; b1 G/ P; Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( V1 }/ n: t. C5 \ D, M2 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 I- D/ E2 m a ~& AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 R* y" z* r( B: O* O s$ Z" q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) M2 O* K: j* H9 w! Y4 @5 FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) |5 [; N3 T9 _! |+ } Q. E9 g4 v0 o
0x00, 0xFF); /* configure the clock for transmitter */
9 ?, z) p) i+ ?9 UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ N1 A- r `# w. a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! [. D( ^# J; E! [5 F3 H4 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 h5 s6 Z5 e# `
0x00, 0xFF);! V0 h# n- [8 N5 n
/ ~' p$ g+ b% J! {
/* Enable synchronization of RX and TX sections */ 6 P) d+ \$ ]' ]- D) L# |0 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, m# r {* j% D V: r& Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 ] e" p" B/ h3 q# e" B! O- ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 h5 o, G1 r+ U+ Q** Set the serializers, Currently only one serializer is set as) s: h( L4 k+ Y5 s3 P; o8 j
** transmitter and one serializer as receiver.7 K a- w# ^: b; \% b2 } o4 u
*/# M" `1 Q, f$ k; @( P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 l! I' N6 t0 g, h6 q5 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; }1 K! j9 a1 p3 ^; d7 p9 B8 Y** Configure the McASP pins
: Y* \! t( d- b q1 Z** Input - Frame Sync, Clock and Serializer Rx
- R0 ?7 H2 z& I4 G** Output - Serializer Tx is connected to the input of the codec
5 Z' ~7 T4 U: n- B6 y*/6 \ W% l x, e1 t/ @" L6 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 b' h' ?: k: \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& X. q% |7 T% a& X6 R; f9 d9 P) V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 T* S8 \1 Q" w A
| MCASP_PIN_ACLKX
5 F- B7 M4 y3 b0 } D| MCASP_PIN_AHCLKX
* z% w9 h# t- l' k7 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# x; d, i2 \7 P$ cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 d$ n7 W3 F3 P: h3 Y3 o2 h8 O
| MCASP_TX_CLKFAIL
2 w( h7 o( i- f8 D0 _: @! v| MCASP_TX_SYNCERROR
1 ~5 {8 p! F9 A- h/ G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . ^& }+ s! e- m9 T* q% v8 R8 |0 K+ f
| MCASP_RX_CLKFAIL
% N+ w& e0 Y( K| MCASP_RX_SYNCERROR
3 }" m* G O N3 ]9 X Q| MCASP_RX_OVERRUN);
; u& ~. c! K( n6 r} static void I2SDataTxRxActivate(void)
x1 e, Y/ T; `1 i{: b: r# J' Z& R: L. {& b
/* Start the clocks */
9 Q3 G1 e$ M6 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 l2 m4 b: M# }3 i& WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 G& t M6 E g. v7 x! dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, a/ K8 P0 N, ?! {4 wEDMA3_TRIG_MODE_EVENT);
* i ?" x1 a3 h% N/ a: uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 Y4 O+ F, N5 L. P W; FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 ?: b0 x9 ?' G8 [( F: N2 RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 g/ v8 t0 V- E# z( b) q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 v' w' `) Z4 ~1 z# {5 {/ @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 `* q; c; L8 K( M: g( ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( l2 Z) y- g4 H0 R- N1 Y* J, mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% Q& [8 p( p1 ^2 t' L( |* b3 q}
" d. O1 L4 ~$ Z7 f6 B. I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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