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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, M8 Z: O" T( q, y" G
input mcasp_ahclkx,) l- S( Y) A' I
input mcasp_aclkx,
) o; L$ b6 t. }0 t6 b3 {input axr0,
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output mcasp_afsr," S+ k& e# H z
output mcasp_ahclkr,: ~0 Q# {; q8 P, O
output mcasp_aclkr, a/ m5 s8 f" R
output axr1,. m" `9 `# e3 o
assign mcasp_afsr = mcasp_afsx;0 M. V* Z4 y- E d. |1 @
assign mcasp_aclkr = mcasp_aclkx;5 E2 F! f3 ]5 I! ?6 i# r! ^! L
assign mcasp_ahclkr = mcasp_ahclkx;
- e: A k9 j3 e% B3 tassign axr1 = axr0; . s$ r/ g N: [2 v" j0 r
" e3 _& [" |1 y; o& O+ E# {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 p* J( J7 ]+ r4 z; z/ q3 O
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% V. P" E- g8 T; wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 A2 @6 l4 i5 h. R5 o* n* v# t/ ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- M& q: Y+ S( w7 Y& b. XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! @) a1 @+ r8 r EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ X" V5 B) G" _ F RMCASP_RX_MODE_DMA);
- @. _ {4 n2 \* s3 hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 f [) I$ @" ]. d: w+ C& o' b% e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' l: e$ Y- k1 |4 tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 B& l4 ^- M' X l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 A" }2 r: T5 p. o9 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 f: R: x0 e! C7 n: {+ qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- X* q T$ K4 n1 `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ {+ a+ b9 R" S5 r$ z6 P! w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Q& h, h& B; K4 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% P; j" X2 x- \3 ~/ b
0x00, 0xFF); /* configure the clock for transmitter */
" F- v9 }* Q, GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); A& K5 z6 v* \8 H' A5 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & W9 Q2 r! {1 m# J1 c, c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 x0 l6 l2 Z- z1 ^" @$ s$ a
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
- D1 v+ {5 {8 i0 N( [; |6 j$ FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& G; Z3 d, l' ]* u/ u1 n) W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 \8 Q4 ?, s: m# T( C7 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 e; `' h6 u% U$ Q: A" g** Set the serializers, Currently only one serializer is set as
2 L. X: G/ w+ V** transmitter and one serializer as receiver.
) s8 A1 @' d. j+ y! @*/
! C# B5 d* g$ y J# IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 Z/ }: m# C: S$ |6 o8 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 ?1 O0 {* l0 L4 G3 }1 k1 h' V z** Configure the McASP pins
1 N: t) g9 v0 k0 f# n% N; o! ], }** Input - Frame Sync, Clock and Serializer Rx2 c) D8 P1 i0 k0 G4 @
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ ?0 r4 t* f# p; d* |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" s) F& \; `! N# x* T+ {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' V7 G0 S, j( p ]' V! ?/ q| MCASP_PIN_ACLKX& o6 U; n2 I2 Q
| MCASP_PIN_AHCLKX
2 o' }5 X# e, n/ t+ @( ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 @% v2 |7 d# U' Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ?! b- x( h' r$ k K# V+ ~7 [: h
| MCASP_TX_CLKFAIL : F" Z) k9 o9 _! ^3 B
| MCASP_TX_SYNCERROR
H$ A; p' V! e6 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& _3 S! V* i8 ~3 o8 c% F3 A| MCASP_RX_CLKFAIL
7 p' V9 f. F3 n$ C) l7 u# A7 d3 m; P| MCASP_RX_SYNCERROR . W" j* p6 V e: b; G
| MCASP_RX_OVERRUN);; N% n; T/ n5 r6 @8 S
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */! A" ?- J7 q* Z7 ?# }* Z2 p! Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 v% E/ T& @. p. ?6 k' \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- i1 Z- }* [3 c9 R0 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 Z7 y% o. |/ x l& \ q0 f
EDMA3_TRIG_MODE_EVENT);8 e$ L7 G7 d/ U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* |7 k% Q* P8 g- I" q# lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ q: {6 {* o/ f3 ?4 t# [) e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 ]; x( i" j2 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
l2 N% k; s2 ~8 p+ O2 J: Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 D6 _ G: z1 r2 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, S% z( d7 g: C: s# Y7 C! X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' `2 e4 v! X) {& @; F
}
$ R! h$ |3 o J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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