|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; X9 z2 o4 j" k; j: p* H7 Iinput mcasp_ahclkx,
# `! G* {, c: o2 Uinput mcasp_aclkx,
, W0 a! x) h, r7 w' f% \input axr0,
/ ~! P' m9 I. b: z" Q/ I6 W/ ~) z1 K
output mcasp_afsr,
7 n' a3 {& ?: d! \& Loutput mcasp_ahclkr,. @4 \2 F5 ]4 \* t
output mcasp_aclkr,- |5 r) q5 J5 h* [7 k, }3 V
output axr1,
& R/ p( u6 s7 q8 L6 c assign mcasp_afsr = mcasp_afsx;) P+ ?0 o( G3 u: h* g0 Z% y
assign mcasp_aclkr = mcasp_aclkx;% w0 E# w3 `& w5 q
assign mcasp_ahclkr = mcasp_ahclkx;
2 \* g2 s3 L+ K5 ~assign axr1 = axr0; 1 ^" A3 D# V5 N$ k1 e) ?
4 D4 \% {7 W2 a. n1 k" ~6 I3 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 e b, {5 @# |3 i2 Estatic void McASPI2SConfigure(void)
4 `, C& w; E! x! V{
2 C- _; s$ V! h' n# y0 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 r+ j( u; F+ Y& {8 nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' }% b! V. _6 s, A E: f# jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" _* g5 B8 D. s2 P1 s# ?8 @, T& a; P# I- a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: z! x7 E% s) \ pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& m- |9 K8 k+ e7 P1 |( DMCASP_RX_MODE_DMA);; E# c$ O1 k. _9 _$ A( b9 }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: X1 q# |, o+ }% L: ?* J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; H2 Y0 o* }& o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( x0 t8 }) _8 r6 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& @- }" a5 @, `( H1 l% D. eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ k9 J( \ p, ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 B2 A5 t+ B& s. a2 w5 u# cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( S1 g1 q. {* O8 I+ Q+ @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! l* S2 F. l, T$ e0 H: m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& i3 C! I, D$ ]- p' R5 K5 ?0x00, 0xFF); /* configure the clock for transmitter */
+ j: ~' V, F; Z' {" r9 p* A; sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ j$ v; T( B; pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
@" o& p; N9 k1 yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* ]5 y4 q$ U/ N+ ^4 Y$ M
0x00, 0xFF);
# A! T" C2 f' Z& y4 D+ L* {+ v6 ~, Y9 }
/* Enable synchronization of RX and TX sections */
" D2 R9 H7 z R8 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& i1 N& [1 [$ t* Y) D4 K$ y6 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; i, p+ C- Z8 g2 \: v j3 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, j4 ?2 Q$ i% F) m1 ~) M+ b
** Set the serializers, Currently only one serializer is set as
; n$ g$ s {0 @/ y% g0 S# h7 M" [/ z** transmitter and one serializer as receiver.. ?' ^0 U' w" h. G: z
*/. e& e, `7 ?& t5 ~/ I- j0 C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ X( }# y5 A7 Z/ {; w, D0 M" d8 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 H$ ]" r) J* U! o! C) g
** Configure the McASP pins 5 c% q L+ Z! h7 B% S* M) Z
** Input - Frame Sync, Clock and Serializer Rx9 d9 `( ~: ^7 u0 [+ B: j
** Output - Serializer Tx is connected to the input of the codec
7 _ a/ P- { X4 ~8 j [. g/ e*/2 ~7 a6 g t) a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 y- `3 {3 b5 i, W; JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% }# ?6 b5 f- T1 S @$ A+ }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# U) T; v0 K$ F( E o6 l# y| MCASP_PIN_ACLKX5 Y# s1 J/ q" w, O- b( X0 y
| MCASP_PIN_AHCLKX7 S( x* P) u8 j% X- e, A% g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% x1 q- p) b9 H2 N& n0 v' j! r2 ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 }/ ~! N$ O/ d' S0 X0 d: z
| MCASP_TX_CLKFAIL
( ?5 X. K) b$ I2 _| MCASP_TX_SYNCERROR
4 }6 |7 X# N/ O/ s- \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 o# E& w+ [, y- b! [( B+ f0 O- m, O
| MCASP_RX_CLKFAIL
9 x& Z: a( I" w1 ~# F. s. F| MCASP_RX_SYNCERROR
2 w4 v: z8 L: S5 c4 _| MCASP_RX_OVERRUN);
8 u1 r5 b4 S5 n1 z* x P} static void I2SDataTxRxActivate(void)
" b( d( g6 z% Q9 b! b, O+ q5 S{5 F) q) s- L! R- |0 G/ U
/* Start the clocks */, \0 v" N1 j W5 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( V* W+ f3 L& Y5 G( X3 @8 \- N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. \. K { r3 n# B+ Q: G9 R! F* n' A, |. I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ p5 F; } d" l2 f7 c+ j* l( GEDMA3_TRIG_MODE_EVENT);0 T; ]" l& p) Q8 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 c) F# N4 F2 q5 B; K7 \% f u$ EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. _, W0 E' @$ r- j8 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* \6 x8 T$ C- w) uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. Y- W/ \/ J# U8 z, f! M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; G/ @" u T: b; A( o. n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ t8 l9 e+ k7 U& V6 f& {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; l( v* \0 g3 @6 I% R9 D}
6 S/ r; g) \, G7 ]( K/ `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 f8 h2 O% V8 R. n1 o d |