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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! g: c; \6 F. i! H! G5 Tinput mcasp_ahclkx,
Y3 `0 l9 U' b+ Yinput mcasp_aclkx,! {: C; _. z; H: C2 k8 Q
input axr0,# q$ \4 n! V2 n- Z# t# m }
; C; P# p9 E7 ^
output mcasp_afsr,/ S+ _6 h, d$ Q& O9 C) a
output mcasp_ahclkr,
$ v: Z% m; O% X3 _$ a( Eoutput mcasp_aclkr,3 j. N- D3 C' S& N$ Y4 Q
output axr1,: x6 E, w1 i& s" R
assign mcasp_afsr = mcasp_afsx;
U% F9 g* |1 Q, R0 Tassign mcasp_aclkr = mcasp_aclkx;
0 x3 A& i+ S$ T5 ~1 ~+ ^assign mcasp_ahclkr = mcasp_ahclkx;$ D" ^# C. Z' s" j
assign axr1 = axr0;
) o( @. Q, _+ S! |% s9 z/ g8 D. i: e& x9 [$ _1 `; |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
[9 o8 A3 J8 o5 Wstatic void McASPI2SConfigure(void)
) z0 o; P4 x! S8 W; J; ~) H( x5 A{
. H$ p$ b5 x( |0 w% z: wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) F& G# }/ ^. X; x! R* lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 L3 L5 ?% e$ m" h) Q6 P* Q' n& r% d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( E' y3 p' y X9 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 K7 M4 F/ O' y9 a ]% Y3 E- uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 P. J% U' m' e( A+ RMCASP_RX_MODE_DMA);
* x+ k0 m) z; ` ^0 G# h3 V7 RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* [3 T. O" v: k6 h8 p8 I# _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 d. s& Z3 \7 g- }6 m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: W1 N* B3 j# I' ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 S8 | v8 n( y# O1 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 n7 q0 G8 @. p* ?3 b; m( `" Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
u: g$ S2 `/ ^6 i. F( F/ YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( L' J8 d! |! Z* T [0 }" g$ L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " M2 p. D/ h5 O) V8 E8 f! p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! d& Y( x% Q6 W, N/ [0 O6 \- S0x00, 0xFF); /* configure the clock for transmitter */; L: W. t* d: i' N8 d. A0 w/ V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 W+ ~( x3 t: g! L/ k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 c9 ]0 Y; _0 ]( e/ {& TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 Z3 B; j+ y/ t) v% U
0x00, 0xFF);
) J' M( e2 H$ X- z9 u; K
. }# _# u8 o0 u8 v. u6 t4 o/* Enable synchronization of RX and TX sections */
. D5 [2 m0 h$ f$ B- s9 d/ }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 v* Q1 ]1 d" n- ]' \) cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- q' O, V6 A. e: T7 O6 B) v( |% t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 k: G8 G7 Q$ B% C5 c** Set the serializers, Currently only one serializer is set as4 ^- o! _0 r0 }2 f6 t* D. h8 q
** transmitter and one serializer as receiver.
! L1 ]+ h$ d& f- p7 c7 T( R5 @*/4 k! Q9 H1 [- o) A( U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 ` l( |% d! e' e; P- o4 v' F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 `% m, b* C% \** Configure the McASP pins
8 Q# y+ v3 A+ A# E' |** Input - Frame Sync, Clock and Serializer Rx
+ p: ~% j+ d" n2 }. P6 C** Output - Serializer Tx is connected to the input of the codec
* O) @6 _0 g' g7 f( {2 ?. m2 q/ M*/
; a- S8 M- {3 t" D" C; GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 k' ~1 R" X" e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# I- t/ B$ s! m# ?/ XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& T5 K- q& ? Y$ B, c0 W" L8 h# ?& D| MCASP_PIN_ACLKX1 {# L& h9 j2 F/ ?& `
| MCASP_PIN_AHCLKX
# X5 K. p2 ^& l9 n6 N" L) Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 |4 P1 R& h4 u i2 I9 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / F/ m* b/ k6 L' T4 y9 Y& H6 @0 H
| MCASP_TX_CLKFAIL
' n8 [6 |8 f* f2 i4 T, H" P) [- T| MCASP_TX_SYNCERROR
* P* J9 |9 r( \% |4 R- w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 y& @3 F3 ]6 n/ g, V| MCASP_RX_CLKFAIL
; D2 I( H! [* N% S% } Z| MCASP_RX_SYNCERROR
v7 e! p- }( p9 Z. h: [| MCASP_RX_OVERRUN);
7 m1 Q! |* [/ t} static void I2SDataTxRxActivate(void)3 `: w) |; J4 c
{) J- B, X) b* M, P: E% N8 U2 ?
/* Start the clocks */
. v% P/ \# e U7 _' ~! [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" k& \9 r4 q; w$ q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 t. T! |8 t$ Z, v5 b$ P' n# a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: h8 S& \7 y4 E: j! p9 k" X
EDMA3_TRIG_MODE_EVENT);
9 `: _: b# g+ T! n& SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 O( }5 Y2 c. ^, |. t' ^- s$ m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ L( F. R6 m0 R4 sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ A: T5 U2 H, t' F) o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ K0 `7 I2 d+ u$ Q. cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; P, d7 A# s$ N/ J3 P/ IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- J2 P1 d1 M* H5 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& r7 B; ]' N: z0 }" O- }
}
* L% I/ r2 _% B! R+ I. Z, e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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