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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 K1 p, b* a) r, D" r2 \/ d
input mcasp_ahclkx,. R- [7 v! x" |# w* b
input mcasp_aclkx,
6 Z8 I5 ?7 [% s& X0 xinput axr0,8 P+ ?5 X; l+ Z, F/ g9 o3 y. C( ]
0 w5 ]% J; p3 g0 V1 Koutput mcasp_afsr,
" k4 B' P( d4 F# }+ b }, u3 coutput mcasp_ahclkr,' l- A: Q# o9 h5 O$ l
output mcasp_aclkr,4 b9 T9 O/ D+ H0 h* Y! W5 `( L
output axr1,
* F1 r, z7 ]1 f7 n1 z3 r7 y assign mcasp_afsr = mcasp_afsx;
6 i" G0 e8 U$ dassign mcasp_aclkr = mcasp_aclkx;$ y4 X3 r2 p( E3 `. z! C+ j5 o2 `
assign mcasp_ahclkr = mcasp_ahclkx;
# r* L) ?% q2 n9 f$ `5 [assign axr1 = axr0; ' `; M, k5 H' q" w% k; y8 e
6 I! O! l0 ]5 r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 P* B9 a$ w! p8 d; Q! g; W* _
static void McASPI2SConfigure(void)1 v7 }; t, e, M: Y
{
. z I, B! r" ]5 U3 V3 o* A$ ?$ CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" [ B9 ^9 R/ l/ r7 m% n A! ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, H2 m, T6 h" Y8 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 `% g+ F% M4 v* {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 U4 Y7 W# V0 M/ R A4 y: `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ R, C- q* _- q0 Y" {
MCASP_RX_MODE_DMA);/ D5 o, d, ~0 Q7 I' |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ i7 g# q _" j: ~3 o; `7 OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& ` w, ^& T i1 g9 a, E$ g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; R' f$ q: ?1 K! z8 g0 [* {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ |3 J) U' q+ A2 D0 X2 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
D5 {8 h( f& L4 ], l1 X" zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 b8 H1 j8 O: `; VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 ^6 |5 w- {6 u% k: T- ]% y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 V( z+ K+ B: e% {& a' J% Z" F& }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& e5 }# O% V C. k6 ^% b$ i2 l. M0x00, 0xFF); /* configure the clock for transmitter */) @; a+ y: F7 G, A2 h* o m( D3 M, F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. [, S: o$ s4 d. J2 Y+ [8 w8 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' m$ e* O% A% dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' O2 ]9 g, @- J6 v8 V3 J% W' B8 i
0x00, 0xFF);7 A, R8 G8 W! o) s
% l9 p( X6 b7 k' E E
/* Enable synchronization of RX and TX sections */
g; a* C2 f7 e/ G, CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ V! Y$ a1 Z! {5 R2 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' v1 a% Z! e- ?( I* ?4 ]& tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 Z( P8 p# ^4 u, d' x+ G( u** Set the serializers, Currently only one serializer is set as$ u, H, s; _8 p2 j+ G
** transmitter and one serializer as receiver.
g5 Z( n. k4 S. A*/
. r0 ?( T4 x! v1 _# YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 u, ]$ F. |# ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ k7 w1 p4 a- f2 L6 L0 w0 `0 Y
** Configure the McASP pins
; a/ P+ s5 p( i- e" g- T) B/ n# L** Input - Frame Sync, Clock and Serializer Rx5 x O# J- E3 |8 ^ {
** Output - Serializer Tx is connected to the input of the codec
( b0 }, l3 @: x3 f8 i' N*/, R: }: }! ~3 p* u( E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 q* q1 F2 k! XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 v3 j% M; _9 ?% J* x0 cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ _/ t& l5 h* v# |0 A
| MCASP_PIN_ACLKX
2 r. i: `8 j" {- \| MCASP_PIN_AHCLKX, r5 I# J ]$ w8 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! f: v4 V8 ~8 ~1 H' I* c* J: H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 p, o1 w6 M1 {- ^# u8 b| MCASP_TX_CLKFAIL ' Q" O/ ^1 K+ S' W; [8 |2 k
| MCASP_TX_SYNCERROR
& c( E2 R$ ^6 K& \) @& x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) d5 P- R4 M' j; X| MCASP_RX_CLKFAIL" |( T) R. n% C; R( W+ ]. R
| MCASP_RX_SYNCERROR
, G+ h* x! d% M8 C5 D; Y+ l. D6 x0 `! e| MCASP_RX_OVERRUN);
; S- X9 ?, | a} static void I2SDataTxRxActivate(void)! n1 Y; S7 j2 P0 C' C
{+ k" o9 f. H9 A" f+ B0 J; b
/* Start the clocks */- P. ~; h1 V/ l( g) s+ p: A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! N' M8 y1 |5 l8 g; m2 u! oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ t; Z% L6 @7 g1 S% [% T' e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; r* N* {. p) M3 |EDMA3_TRIG_MODE_EVENT);
7 y& t4 Y- D, c1 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# W6 `: k; U; X' REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* I( W9 Z1 a0 @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- K( W7 w) d+ z3 Y3 J) a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* ^8 U) n* v8 \5 U* Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
c( H. F# B% w: i% F4 M& N" WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( L! T, a. | ~) Z: T2 l, d a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% N" x4 U2 M6 |6 v}
- A+ d8 p1 p9 G0 D& ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 W% R; i8 r( x7 s$ ~
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