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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ \+ ]5 r7 F0 ~9 Zinput mcasp_ahclkx,
7 L( h( P N# e/ S5 y \$ y! Sinput mcasp_aclkx,
1 t6 x$ v+ r' r. @0 d3 u$ |! ^! \input axr0,
2 @' [$ e8 k' y1 z8 `& t; P2 R) M; R
output mcasp_afsr,: t, _" P3 r {. @/ I1 t
output mcasp_ahclkr,% E. v+ r* E, l$ D
output mcasp_aclkr,
: c8 ~0 h% _ a* z5 F; P" r; `4 zoutput axr1,
& Y7 ]2 r; W S8 ?- P/ v0 |. G9 z4 n assign mcasp_afsr = mcasp_afsx;
: @3 |$ N& G6 a4 uassign mcasp_aclkr = mcasp_aclkx;
+ U# G' B9 G# g* ?8 `- ?1 L* Qassign mcasp_ahclkr = mcasp_ahclkx;
' S3 X3 g+ j4 n9 v+ @1 ]assign axr1 = axr0; 6 n }2 V/ ~1 @2 G7 m* ]7 `( E. R
1 n% n. G9 W: x( m! Q6 _( X' @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " F' Z2 g |9 y: n
static void McASPI2SConfigure(void)
. L1 _1 m& |4 @. p+ r{
H8 y6 Y7 i9 F. k1 }: ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 M: P/ V- K$ [- h0 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' ^) e& _# R7 q* Q" }; z! `9 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# `% E8 v, T$ n0 D. C& h+ z8 QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 h+ @, i$ z+ y. |3 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ q/ u! v. O2 L0 B% H( jMCASP_RX_MODE_DMA);& F8 X1 A! P- V n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, j$ B2 k( _" |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 V+ h' l2 ^0 D$ W8 ?, B! ` SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 j. q7 d0 y* M* _4 {& jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( _9 N- C+ ]7 c8 l% Y+ t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 K) {* l B6 z- T7 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ D4 p$ ?& y- }( L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 M" H/ Q: P2 Y7 T- \ {7 m. KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) k" ^0 T9 N) D2 N7 L$ B* y( Z- H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 Z- l8 S1 {9 F9 t7 ^8 P) p, ^1 g0x00, 0xFF); /* configure the clock for transmitter */
# c& p# q! y6 X$ l; ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); {4 P0 S. I! ]" ~0 z+ W& l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 J$ W1 n/ ?: e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ b6 t7 ]/ C1 \$ K5 W3 g" n j& y% Q
0x00, 0xFF);
8 e$ b' h* w' A' m! G
7 K! O9 K7 D: Q; b$ @/* Enable synchronization of RX and TX sections */ ' X3 t% j6 P+ L4 i( s0 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ D% N6 A& p' C4 w9 l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 O/ w: K& s; S8 \4 _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ~, a' \6 v7 k# p+ w; u
** Set the serializers, Currently only one serializer is set as
& Y q8 [) X) N, m0 M** transmitter and one serializer as receiver.& i6 S3 j1 ~" m
*/* ]# j6 o) Q: p6 w! S6 B' j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& T) x. y# a! a# R5 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. H8 [" F; T9 G. h$ T* {) e6 V) {
** Configure the McASP pins
7 d( M x( |3 T4 W0 x2 ?** Input - Frame Sync, Clock and Serializer Rx* h6 Y- g' ~. N G: c
** Output - Serializer Tx is connected to the input of the codec
5 y" u- x! v! N2 T6 K*/
- _2 G F! d4 f* C1 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% G) F# q; o- q8 f" \5 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" S m* W( t% z& q+ T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" m( o6 r; B: V) Y2 ~1 G/ Y* k! r' s| MCASP_PIN_ACLKX
4 m- c0 V h' u' R- F3 q| MCASP_PIN_AHCLKX- X3 d* Z1 S% u5 b! E; Z1 k, W0 j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ W3 j7 [# ^# ?5 A6 Y: J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' a2 w3 m. T9 w4 s| MCASP_TX_CLKFAIL
4 L, H: F/ D4 v% B8 H+ P| MCASP_TX_SYNCERROR! Q, u1 u7 U9 {/ G L0 V6 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : m! N' ^8 e7 p7 M: L# S+ W
| MCASP_RX_CLKFAIL- i% q3 s9 C @4 Z) P0 i
| MCASP_RX_SYNCERROR
0 v, G' @. N- \: C9 G| MCASP_RX_OVERRUN);8 Q% F6 H" T+ _. z k4 |) o
} static void I2SDataTxRxActivate(void)7 Q# Y. j+ `( K* c7 y' O) E) h
{+ c3 ?3 Q/ w" o t4 H7 z
/* Start the clocks */, C$ i7 i& o4 k' ?; f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 Q$ r+ Z/ {2 R6 N* g' b; R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 l9 t; ?" M% a9 k7 [/ F# \9 c2 Z4 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 I# @- I8 v. E$ k; F
EDMA3_TRIG_MODE_EVENT);
7 w' V6 p( x$ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ V) }( T5 Q# y# j! B+ T* \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// _% I j6 K0 I+ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, q2 r1 W6 H7 U& `6 J# |; {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* j8 z' k% ^ R" j2 P! E) @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 h# T8 [$ A( `3 F: F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 R1 o2 J j- V4 x/ F7 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; D- f, }" T1 s. A}
9 ], _) Q6 Y6 O- J# n, w, G) M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 [! m. W s4 h ?* B. S# W |