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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* Q7 ?9 x. ]/ _. Q0 y, S) |. v
input mcasp_ahclkx,+ v* Y. g# V9 }# ]; s
input mcasp_aclkx,4 b* v) H& m6 l5 U/ ^" h, i& ^
input axr0,
# n1 b3 S7 W2 m) B
8 ?/ X9 ~' |& i( Joutput mcasp_afsr,8 W1 t3 ?# G& R
output mcasp_ahclkr,. b. B% u* I& Y9 x2 g+ H' ]) |
output mcasp_aclkr,
- K2 ?. w0 V# a% s0 foutput axr1,
7 _; [: f" S% P% v, ` assign mcasp_afsr = mcasp_afsx;
+ ?- U$ x1 y9 ]" d/ z4 o$ kassign mcasp_aclkr = mcasp_aclkx;/ U! H Y+ t0 U) C4 E9 c) s- F* X3 y& V( p# l
assign mcasp_ahclkr = mcasp_ahclkx;( t3 c( l( n+ ^" @* q: r9 Q
assign axr1 = axr0; # _( ]" X. k0 `
5 E* J4 ~* I2 r6 L8 z5 h3 \1 ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 b6 q6 p* r" f8 O. L8 ?static void McASPI2SConfigure(void)
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3 G$ q S- {, A. j& |% @- x3 t' |McASPRxReset(SOC_MCASP_0_CTRL_REGS);! Y- q, K2 |. f2 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( e& }: G- o; |" G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ L. w0 }$ Y, l% S. D' T) GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. V G# @9 z* B$ v) R# n5 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! _+ @' {# Z3 `8 b: XMCASP_RX_MODE_DMA);7 X$ q$ \: x7 I, V# _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," R7 Q8 w5 V$ c2 r; J) ]% F; R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// E. _+ B" v; M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 i9 _ A) x3 s- p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# k$ v0 m3 i4 Z7 L! p1 k7 G/ n$ D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 K" X5 i( u/ s' l3 q. E- t7 `: J5 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ P! h' o* _7 G6 n8 l. A" a8 H3 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 Z% ~3 t3 c# ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ O/ D% o! r; ~, H! T, dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ L4 ^' D+ ~3 c) |- X0 h7 X
0x00, 0xFF); /* configure the clock for transmitter */7 a7 w3 l. W& K& H' \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! P! N% U& P; V, A7 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & l9 |# e. p7 f( X; W% `1 m# c2 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" ?! q( p7 |. g9 t0x00, 0xFF);. h9 O, I+ ?: b
, v1 r1 y& j, i, k/* Enable synchronization of RX and TX sections */
3 k) d; P% l" d6 m# p% `4 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 V! C1 |# ]$ L" L: A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) ]$ d) k: w8 Z, Z. H) d0 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ t( x: w# J- r! [+ Q2 H8 K
** Set the serializers, Currently only one serializer is set as
8 I- ~# {, i+ r** transmitter and one serializer as receiver.
1 t/ s4 r7 W1 `/ B$ H7 T5 e*/, |4 s! v& g; s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, U" C& Y! c! e! W) e8 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# s$ }/ Q6 x! [+ X3 b
** Configure the McASP pins * X3 P; p0 x% e
** Input - Frame Sync, Clock and Serializer Rx
8 g y$ _7 M/ d' B# |** Output - Serializer Tx is connected to the input of the codec , |9 Z+ d/ A* D; V9 C1 C
*/9 L8 b* r) G& K! z2 U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: y& U/ @3 A4 Y: zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 [5 z7 c9 y: o5 s5 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% D- v; ^4 A' r5 v u- d| MCASP_PIN_ACLKX- W9 j S( J6 I2 a' @: i0 O- g
| MCASP_PIN_AHCLKX
. W- Z, Y3 F7 P) o3 u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ z% c" ^) C: Z! w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 H- I% r" R/ q# M! T
| MCASP_TX_CLKFAIL
( i! D* O8 R* m, B7 S! O7 @| MCASP_TX_SYNCERROR
# g k) z% W" d5 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
}# k! F+ |$ V- q/ N9 p| MCASP_RX_CLKFAIL
. f, |& X+ d9 l& m9 M| MCASP_RX_SYNCERROR
% y( b0 x: Z2 M0 [) c; R| MCASP_RX_OVERRUN);# Y( h: V; o4 S/ Q( x# t' `# Q' }3 A N
} static void I2SDataTxRxActivate(void)
8 u1 g- b0 z$ x; [: e- \{) X3 A' w$ v9 E; {3 v8 }% x
/* Start the clocks */
+ e1 k A9 D8 ?/ s3 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. ^; K& {* P7 W# Y3 e+ P% R8 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 _' p3 t- j# y9 l) oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ s# m" b0 e! }: f9 EEDMA3_TRIG_MODE_EVENT);+ v, K/ x7 u! v% ?/ H5 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 \5 C- O5 \* n8 n* [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 W2 g" b% f- R9 `* C$ v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ w- {; j' v+ w6 @" Y2 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 j+ g. R: G1 Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ J3 D, A; _2 P# ?( T9 g' D% v+ {* SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( F h3 _. }8 g: g: p6 P6 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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9 z9 J* q5 b4 [) I- p* X7 o/ |6 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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