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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 M' M7 A9 Z) ~ g4 F) K- pinput mcasp_ahclkx,3 m! Y9 l1 c- z: `- I
input mcasp_aclkx,6 S* o5 g0 W0 ~# Y1 M
input axr0,
. y' G1 z+ D: ^- w' a8 V+ N- O& X' A
7 ?. H3 E# {" ioutput mcasp_afsr,* G8 x) n O" {! U4 I
output mcasp_ahclkr,
& M6 |$ Q) O! n* Q; Boutput mcasp_aclkr,
; W* z1 s" [* P4 ^output axr1,
/ a; \& {7 T0 L4 y7 H8 z assign mcasp_afsr = mcasp_afsx;
/ s* |' k2 F* e# j) passign mcasp_aclkr = mcasp_aclkx;& Y& w$ \: j+ I/ O* E
assign mcasp_ahclkr = mcasp_ahclkx;4 G% F6 {% X0 k4 ?' |
assign axr1 = axr0; 6 T5 @# o4 F/ E6 q
6 ]6 z$ I8 i$ u" f! e# |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& S) a5 x; O& {8 e5 [static void McASPI2SConfigure(void)) K7 V- O O* ]$ K5 X5 H
{ p0 h6 N; O1 d, ~& p; b2 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: Q1 `! [4 \3 t7 r) W6 ^, j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. L2 l* z2 c+ rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& D# k- m( y8 K6 E8 l; c: C1 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 [, T, r0 T- z5 V3 e3 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- d4 Q0 H* l1 qMCASP_RX_MODE_DMA);
( w, O; |% O5 F8 @& [) z5 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 P+ n0 A/ F7 k7 a1 a+ [2 z; U' |3 ? _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 F. B3 t6 Q3 D& J0 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 K; O9 v- ^( @$ |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: Z+ A' X1 G/ D3 WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & |$ i! T2 l/ Y- ~$ n; Y5 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 u1 Z7 `+ Q( t0 K" b( f6 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, {8 v: l+ `5 H1 ?+ Y8 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ K, ^/ Z) ~. \3 X8 P$ j: SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 d- {2 P" j) m6 G4 F
0x00, 0xFF); /* configure the clock for transmitter */5 x% K( E9 j, ?/ n! I3 r! H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! `. |) O& d: ?3 c; x. O$ ^4 C% OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 i& O# ^7 G, H, ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* u! l- O) X, f2 G6 Z, ~
0x00, 0xFF);8 S. M3 T- X4 b" v: v3 }
7 u; F Z s7 B1 K; X/* Enable synchronization of RX and TX sections */ & k- N- p9 v: T, E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, c/ m& n* T( O$ }$ ?7 l2 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- z; e' E3 F5 r e# r t0 \9 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' |' E4 K1 p! h4 E6 i* _- J4 O
** Set the serializers, Currently only one serializer is set as
6 N6 q* X6 i/ ^; a** transmitter and one serializer as receiver.
/ B% w; \' Y d3 D% N/ {7 x*/
8 l* a/ P F& O8 K) pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' X) y) q2 \) t$ z& L5 a7 ?+ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 b% K& `( `* R* q$ E' t** Configure the McASP pins ! s7 V9 d. O. U; s% R6 B+ ^7 X
** Input - Frame Sync, Clock and Serializer Rx
. d/ z5 p/ |. w5 d C" [** Output - Serializer Tx is connected to the input of the codec # y, \, V! W2 O' M& X, ~
*/
6 W; N. f4 T. }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: |7 c+ N g) E4 U% L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 r" f2 @( a$ D. A( D. ^0 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- m# s9 k, H$ L! ^
| MCASP_PIN_ACLKX
+ e$ I+ _) P4 D6 N' g; x| MCASP_PIN_AHCLKX" o( M3 i% G1 O* m# P& D/ ]& d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 Z8 ^5 C! J- Q& FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - _1 n; d& K' |, i
| MCASP_TX_CLKFAIL
$ @ J8 d9 y# A! J: f| MCASP_TX_SYNCERROR
+ X9 {# @$ O9 [; g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& U0 F; a- f V0 T/ @| MCASP_RX_CLKFAIL- t; O; `0 L2 M
| MCASP_RX_SYNCERROR
3 c1 Z. e& m; i3 {$ m/ V' K- G| MCASP_RX_OVERRUN);
1 z8 X4 }/ m" R O9 ]( _} static void I2SDataTxRxActivate(void)1 @! I) c0 N, ~6 r- f
{
! T% e$ |2 E. G/* Start the clocks */' {, J* y( O' n$ v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( X( v' i( g. i! ~+ UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 H/ [. S5 p( k9 e" |, ]- tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 u N3 C7 s. ?- L
EDMA3_TRIG_MODE_EVENT);
9 v: c* E7 A: \. dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ F7 f5 d) G- B% c Z. h6 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& a' A! K2 O# ^8 t1 Q/ b# w/ GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% M- b8 w' v+ x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" h6 S; C8 l% z3 `1 l. C/ d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 K& o; S! ~$ LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; H8 X5 V; T, G" gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 d4 x' j: r" V8 L9 i& v}
; a/ L7 u2 W! L8 a5 ~ \) {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 L: g; @) u* Q9 f, T9 J! _- |
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