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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 U& x5 e( k1 `3 ]2 o! m t: z
input mcasp_ahclkx,# u# y& b+ p: d7 J4 I1 q4 \) V3 M- I
input mcasp_aclkx,) P6 s6 `. w3 e6 D( Y
input axr0,
4 e$ @* q+ ~$ B4 d: \, Y
q( H) f( h' Y4 R, w2 n3 C* Joutput mcasp_afsr,- ^+ I$ G7 U# J& z) i5 _
output mcasp_ahclkr,
$ R6 x' L( y0 Uoutput mcasp_aclkr, ~% U( k6 J! q) }7 z
output axr1,) M' z5 Y1 y2 T4 S
assign mcasp_afsr = mcasp_afsx;
( m* V" I6 K# \* massign mcasp_aclkr = mcasp_aclkx;
0 {8 H; _5 A0 [% t! G8 L6 _assign mcasp_ahclkr = mcasp_ahclkx;+ { P, T. T) A& h
assign axr1 = axr0; ' c1 s7 R% D& v
& q6 a4 _7 {0 Z- P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " i* I6 Q7 u* x
static void McASPI2SConfigure(void)1 J4 Y3 S* v) L6 S
{0 U5 f9 p/ ]; q( O: U9 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( @3 e$ F) N1 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. e1 B4 c0 d7 D2 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 E* i: t7 ~% `. e" K, o( B k4 F3 U, B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* g; v* I# Z# QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! M) [1 ^4 k. _$ RMCASP_RX_MODE_DMA);
0 {* u# b6 z- V& {; ]' SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% W3 f3 L2 { M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* G+ b" E. K8 B" RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( s1 c/ A) l4 k E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 P$ B$ q! e; d9 b! N4 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; d+ H) |* c3 B9 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* V S u- Q& I: K2 V# o. BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 a- ]# y' w+ u' y# d0 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " _9 ~+ P6 K) M+ m4 m, g6 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* p! y( x( }5 I/ Q8 g6 m
0x00, 0xFF); /* configure the clock for transmitter */
3 N) d9 p, F5 O6 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. a1 e7 ?* {, cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * d. S* P' t0 s# [) i; a4 ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ R& P! e2 u& f( F+ J
0x00, 0xFF);
! q( u$ d) d9 p t3 d( ?5 P P5 ^: h2 s+ y M) j
/* Enable synchronization of RX and TX sections */ ) \; i/ ^6 c/ I4 A6 O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 _3 f& a: o6 w( z! B4 B QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- m8 E0 g' [9 y0 a$ S1 ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ Y7 M2 ^$ `5 U; H j9 y( L
** Set the serializers, Currently only one serializer is set as
) m7 L1 O9 g1 I8 H' r# W5 U** transmitter and one serializer as receiver.
A$ k$ P2 n0 Z; T0 h*/. k! v; r( t, ?8 B, X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, A& _: y3 d- f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% |/ [3 ?! n$ Y6 o3 U( ` r: J8 e
** Configure the McASP pins
! |; p ~4 I: y7 _ { c6 A** Input - Frame Sync, Clock and Serializer Rx
# I+ |* v4 k7 b. ^3 R5 Z2 _: H: S** Output - Serializer Tx is connected to the input of the codec 4 A5 `# M& U& j5 A3 G5 v; I- c9 z
*/
# O$ ^2 k& o: sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) Z/ s5 _' ^, ~1 ?1 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, M5 `5 y' K0 w& y5 R" L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' w5 @+ i' V2 {% u6 A" y| MCASP_PIN_ACLKX
, p$ {- b$ v% p) K- f. t5 K- G| MCASP_PIN_AHCLKX
9 w5 M6 M5 A; k6 s! x4 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( s) m7 p6 d7 d, m7 V# RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& j+ Q- z/ e, I% G| MCASP_TX_CLKFAIL
( j8 M( R3 T) Z0 N1 F" {2 G; H: B| MCASP_TX_SYNCERROR
: l" {" m, V9 n0 H& l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 E1 H, t2 F3 `| MCASP_RX_CLKFAIL
" Y9 |; K& E4 ?7 n- ?& G/ U6 V| MCASP_RX_SYNCERROR 6 {: Y5 x8 I* p) ^% ?
| MCASP_RX_OVERRUN);3 Q: f# C0 O. o5 ^
} static void I2SDataTxRxActivate(void)2 G9 O1 R5 K6 ?, S$ M$ V( Q
{
( a" X8 j2 D" s6 W, ]/* Start the clocks */
0 _! u# |8 t1 {" c# z4 n; ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 H! T9 m: O3 A2 y! r9 ?5 Z, A9 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% g8 n/ S y3 g" R* q! a3 x; E- }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 d+ U$ N: C& z5 w7 |EDMA3_TRIG_MODE_EVENT);
, o3 w: O# G6 i- x$ U; WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# j S- Q1 M0 w2 B. ?& ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 w0 L; \: }. ^2 {5 C$ _: `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! K2 N; P; a7 S7 m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 s4 p0 ^" u/ R' v# [7 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 h Q* Z1 O# ]- d- J7 q4 V7 q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 s' }% h' j( eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( s/ y# }/ ]$ z}
" `# q: P! |( c0 K5 s6 G4 ^ |2 l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ h7 ]) c" ?, S! w$ F+ G$ y
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