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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 z6 k( N7 L( @$ a6 s, B5 w
input mcasp_ahclkx,
0 v! n$ u( W: Z/ h* L% F O. \: Finput mcasp_aclkx,6 m* ?1 b% Z) v# y3 q& k
input axr0,0 R0 ?6 W5 ?. n
7 ^& B: I" f; R `, K
output mcasp_afsr,4 _) V" X* f# _8 ~8 Y j5 E f
output mcasp_ahclkr,# H. c! G) `! N$ ~5 K/ {
output mcasp_aclkr,6 G( C+ h' w0 Z5 o
output axr1,
% Z8 \" X4 l- O& H' O3 V assign mcasp_afsr = mcasp_afsx;
, W0 f7 H3 a Z/ R; Lassign mcasp_aclkr = mcasp_aclkx;
- x% E. g3 d2 d7 r: y, v; W: Kassign mcasp_ahclkr = mcasp_ahclkx;' B& o( q9 r7 h
assign axr1 = axr0;
5 A6 G+ k% o" m# A5 _- ]# B3 B5 h1 l! A" j9 T1 Z- P: d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 M* P# j, f; P: C$ m2 p# {, jstatic void McASPI2SConfigure(void)
( e( f- H, j! a- F6 N{# q2 i- e' D8 }3 J4 u. b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" @& y, V3 H+ b, Y1 t2 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ g4 X. [: N# Y: B- F U, SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, l$ ~' I M% a( G+ u# I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- f, B# {4 _. A2 p; T' i4 \3 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 \1 g# N% x4 T5 N! M/ s3 v5 n
MCASP_RX_MODE_DMA);
, m# q1 }* s; j( p, h' iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 e- z, j1 e& p/ p* t3 S: d; o! IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ }. N" D2 X! P- }/ R& J; aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* `& P8 l! l1 m/ ~+ ?( qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ v# x9 N* y* D, ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' U, A) F7 s2 R' Z' n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. m* F- X( s: k2 c* V8 ~$ s; wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- A3 h# O' e" {6 a1 d7 O$ Y( ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & M; t3 k4 I, j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! T$ V. @" [' [0x00, 0xFF); /* configure the clock for transmitter */5 f9 ?% |4 c7 M% c6 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ D& d# D- C, \9 B9 ?) ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( V: q$ q: S9 I& ], G) ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( P5 G; `; U9 S$ a- ^0x00, 0xFF);
# m/ ]3 r2 K2 D% w9 ~9 m; x: V, L* W2 V
/* Enable synchronization of RX and TX sections */ / Y, ]' D _4 o7 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* t6 p y4 d+ w2 W2 E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ P1 u: z* E+ x) [! @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ l0 o: t- f0 n2 P& a0 `% J** Set the serializers, Currently only one serializer is set as
) g% k$ r4 m6 g1 [# H5 s: `; m** transmitter and one serializer as receiver.* ?+ S$ h% B# y8 ^7 A$ D: o W
*// ]3 G1 ` \. Z( G( ~1 c/ a- t8 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 f+ J8 q9 @3 D8 q/ _1 _- M! P. P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% ]; j& b% V0 E- s
** Configure the McASP pins ; K! q) w% v* @! ]5 o2 a2 Q
** Input - Frame Sync, Clock and Serializer Rx
3 Q9 d% ^1 {6 _, \" \** Output - Serializer Tx is connected to the input of the codec U, O- J9 @; J5 [
*/
5 x1 s5 ?: `5 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# w8 U1 @! w0 d7 S4 H& P+ I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) F- y* P9 w4 f7 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ e8 [3 {2 t, ~( g5 v| MCASP_PIN_ACLKX
6 |% q" J: V% \8 y6 W0 \6 @| MCASP_PIN_AHCLKX
4 S* ]: W/ b" c$ ^# g0 q6 h7 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# O/ l9 P1 y/ d; y1 J" M2 u8 ` r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; [1 ?+ b. J" ?| MCASP_TX_CLKFAIL , x. k* E7 f1 p2 _
| MCASP_TX_SYNCERROR
$ m9 ^* A; x6 g* a; C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* o& E. u8 n# B, }| MCASP_RX_CLKFAIL4 d4 I/ E7 h7 ?5 Y9 t/ I7 p, i
| MCASP_RX_SYNCERROR ' C2 @2 y3 A$ D
| MCASP_RX_OVERRUN);; j6 N5 y+ U7 [1 Z- a! k/ E' }7 w
} static void I2SDataTxRxActivate(void)2 B- @) E. V+ Z. c {
{7 {4 s# @5 J; a4 B8 P
/* Start the clocks */- h" o0 M! v5 u% ^; {. m; _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* b* K6 V# ?; [3 b+ e# ~4 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# u- y$ n4 Q6 ]9 \6 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 S: X5 ^. f8 w5 U) M, ~: lEDMA3_TRIG_MODE_EVENT);
) c4 u: Z# i5 `, {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& ]9 E5 Y7 C* w% s- KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 B8 t S: Y+ \/ i# y2 y [2 P8 Z/ kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: s7 T3 Z- K; s/ k, v/ ]- iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; T, b8 P: V7 _4 r( D, o' ^! @; h7 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ?, J8 i* T8 U; N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' A+ S8 g' A, n* b5 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 d. g* f8 {# ?7 j- @0 m2 p
}
6 H) E; P1 `: n; f" I; S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 \( M1 v. B( P2 Z7 y _
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