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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, R: [- V2 O4 K; J1 V# y9 @; d
input mcasp_ahclkx,
- s w6 n! L1 }1 S+ W) x8 Y5 p) Binput mcasp_aclkx,
7 J5 F# B* h8 f9 E+ e: oinput axr0,6 V: n. W4 u- P) l) P
- c4 c+ b" @' i# doutput mcasp_afsr,% j$ z5 k* \, {8 e% s
output mcasp_ahclkr,
0 e+ u- z: |0 Y. j& Zoutput mcasp_aclkr,- b1 b- g+ q. X3 e Z6 W
output axr1,
7 L, \: r% V+ o* N; t3 x0 U9 v9 ~ assign mcasp_afsr = mcasp_afsx;
2 k: C) e; r i6 z3 p' b9 m2 B# Jassign mcasp_aclkr = mcasp_aclkx;/ s% |( E9 h6 N& D ^" s
assign mcasp_ahclkr = mcasp_ahclkx;; o0 C* G1 [) i3 P3 I
assign axr1 = axr0; 5 Z/ E" d5 |5 ]) j2 b# p4 W
4 x9 T; K {( @, C" T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: ~! Y* l$ `6 M2 m U0 g* Z* Astatic void McASPI2SConfigure(void)# H0 e: @* y; w3 B
{0 L' u* d, ?1 U' i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ G: n, `* Y9 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& R# Z' |2 v) s, [1 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& T; B1 J" @7 j, ^1 A9 `( J0 Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: h0 b( A; q) _0 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 r9 r0 h) d3 O0 }( y0 s& N. b# EMCASP_RX_MODE_DMA);7 q/ m- z" H: J/ t7 L V8 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; H# A! B+ b5 C" z! {4 A- M+ T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% B( g* R# C5 e7 H: A( a2 D# PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - a. i, w5 K' j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) K& Q6 G' v: M8 D9 P4 d8 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) W) N% ]/ {, ]8 m' KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" x* j: R! A- sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ i+ t y- M1 J7 {% D7 AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 a( M; W' c, I5 l# jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! W. I' y- G6 f* @% j7 \' b
0x00, 0xFF); /* configure the clock for transmitter */
0 G9 m ?' ^9 \' k0 G$ UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* o, J% ]$ c/ W5 l( \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( I' E Y D; W e- ?; `! y% A& I5 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ e5 Z& j4 K* u V
0x00, 0xFF);+ C* c- z# I# K) q8 S3 a4 I
& B) W; G9 ?0 l, ?: ^
/* Enable synchronization of RX and TX sections */ . X6 Y0 l2 `8 f- l3 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 d# h% A9 t2 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! e% k# p; [1 _0 y: V) j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; |. l0 w' {8 [8 \** Set the serializers, Currently only one serializer is set as
2 v! i8 x, W& \3 {1 {8 E5 x** transmitter and one serializer as receiver.
! |& p6 Z& w. X+ T; D*/9 O$ ?" I: b- [! V. R4 }2 F3 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 e' {" }, u! ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. T6 l3 p. h- @( |
** Configure the McASP pins ( e4 t6 P4 v% }4 C1 v* N% I5 D
** Input - Frame Sync, Clock and Serializer Rx* U$ E1 W0 L0 M D
** Output - Serializer Tx is connected to the input of the codec 5 n* |! p! p/ r- e+ \$ z- s, p
*/& L; V8 x# \; }- Y! E$ L8 p& T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- w' b8 X' f5 O; f* f3 G: f" p5 w4 K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, U# d1 l& L9 v* e2 C4 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 `+ x4 D4 N9 g* M| MCASP_PIN_ACLKX& h; I& l% m: n2 A7 } l% ?: {
| MCASP_PIN_AHCLKX
4 j- v/ K X3 [4 o) L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( ~9 b0 m2 r# n. h9 ~/ c, xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - g0 F* x$ W" D L
| MCASP_TX_CLKFAIL & R& ?6 r2 S* P" u
| MCASP_TX_SYNCERROR
% T% J' p6 O H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 w0 A) h, J- { _
| MCASP_RX_CLKFAIL
+ Z8 F, q) M; a/ `6 L0 O& y/ O+ B| MCASP_RX_SYNCERROR : g1 W( i# d2 `- c: `
| MCASP_RX_OVERRUN);6 |1 b% A& N& s: f' n- b
} static void I2SDataTxRxActivate(void)
2 y: B: s+ G. y- o{* [ u1 v4 A/ {( [; ~, S7 o
/* Start the clocks */
2 T" V. w( f& Y$ t1 v; y; W) `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 k8 C! w) ~) \/ m/ uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" l0 m( ~% o, I; \+ zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 n7 `6 R8 ^2 s# G
EDMA3_TRIG_MODE_EVENT);0 U- x: b% {9 ?* ]" |0 b& W3 `2 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : R8 K6 I' H4 W' l- {/ P$ B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 P+ _% C- {9 j X0 {" r- zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# f+ H$ c$ A5 ~) C+ E7 W; P3 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( [6 z- k3 j) v" O ~) awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 W+ ]) D6 ^0 j8 M5 k5 D) W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 S6 I. F' B4 e8 V, e' pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( H2 D" t( b; E. B0 \9 o( d" D
}
' z! e$ Y( Q2 X; T* ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 a) Q" E3 K) H( V9 V
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