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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 u4 H# p, Q" K, J+ c, Y& y2 F
input mcasp_ahclkx,$ o! D8 g) Y5 y9 b
input mcasp_aclkx,& i' q" C. ~- n2 N8 M# G6 }" F& F
input axr0,2 r1 J! B, m r1 N/ C1 _
3 [3 p7 }: Y4 Y+ \) h, qoutput mcasp_afsr,
8 a$ z/ I1 C0 t7 f9 W# {output mcasp_ahclkr,9 k9 K6 h, `* C1 O
output mcasp_aclkr,( t$ k/ v% D: g
output axr1,
! \. A* U- [. g6 d4 ] assign mcasp_afsr = mcasp_afsx;9 S, }! e, L# A7 x
assign mcasp_aclkr = mcasp_aclkx;# n! @3 E5 e' O: q9 a$ w
assign mcasp_ahclkr = mcasp_ahclkx;2 `6 E8 x, n) r1 C- x
assign axr1 = axr0; 3 e0 G9 }8 X6 ?6 @ o
* ]+ G" T6 z% f4 B4 \2 B; s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) l5 x" h U4 |' K$ G1 m# m) g# y
static void McASPI2SConfigure(void)
4 u: j0 r6 N6 t5 t/ {( }. c{
& b7 c y- T! k0 d% Y2 U& J! wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 |; s# F/ {7 X( n2 p5 Q$ S0 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! C6 C5 e5 Q& N( WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& L) a! m6 Z+ q2 p+ I$ K3 K' OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! f7 e0 o1 B7 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 C- J5 s! A1 l$ KMCASP_RX_MODE_DMA);& n, D7 v) I c# D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 j9 W z- l8 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" w' a' u( B6 s4 r5 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 g: c: A% J3 C* b* t- v8 rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- l; J6 r9 P# l9 a/ n' J4 m k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
r6 [4 {9 e8 _8 b+ q) ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 H0 n* a' V( d' B, Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- E3 S$ x2 R4 e0 N b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + X) c j0 b, ^+ R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 ~- k6 r! |8 T5 E
0x00, 0xFF); /* configure the clock for transmitter */
1 Z7 Z1 t0 P' }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 s% F! t9 Q, N8 g: g8 j: NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" E" c# n T/ r6 t" PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 p5 Z3 n& b* ~- F+ E2 w5 B0x00, 0xFF);$ L- _* n5 l& ^* s2 r
" y* U; T8 H6 F, f' H% ]5 ~/* Enable synchronization of RX and TX sections */ ; K+ L0 c3 x" @/ A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& h3 g( U% T* L. nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- e4 [+ _( @+ m. s9 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 S1 s s4 @" ~** Set the serializers, Currently only one serializer is set as
$ X* n [3 x1 s' d' q1 {** transmitter and one serializer as receiver.) R! W& ^; f) {4 I
*/
8 I( P6 d5 r# k% ^3 d: uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# ?0 M+ c4 V2 H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# S* P# ~: }$ t# Z r** Configure the McASP pins
3 d$ K5 T% k% k, k* l8 Z** Input - Frame Sync, Clock and Serializer Rx$ r2 {& `3 ^, d5 I+ r/ G
** Output - Serializer Tx is connected to the input of the codec , s" W& E' `% f% ?8 O+ w8 c
*/& G* V. n ~) h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 Y* P: f6 H# _4 t0 A; v- g2 W0 Z9 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! n# N j# s* `, d# c. ?: Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 t, y& [- x" b3 c4 Q
| MCASP_PIN_ACLKX3 W7 @( I2 W$ Y/ B" ]% J g
| MCASP_PIN_AHCLKX
+ R* H( O5 J/ f9 p0 l1 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% m, y w9 m. s, S1 b- f8 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' f$ h& _+ E* k! z$ r, J h8 z1 f
| MCASP_TX_CLKFAIL
, ?$ x# G( Y* b8 h| MCASP_TX_SYNCERROR
0 y' Z2 h+ M, [' U. x' B3 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ~4 q J$ S+ O& m| MCASP_RX_CLKFAIL4 Z( O% m+ u7 v: b5 b6 G
| MCASP_RX_SYNCERROR
. m# _6 ~, i/ w& `) t| MCASP_RX_OVERRUN); X: }, N/ h, F c) R; H$ L* v
} static void I2SDataTxRxActivate(void)
3 @9 X- u `! X4 H- g{# [4 W1 z+ z% q% \
/* Start the clocks */
; a& e7 G/ n, D N9 t) {) TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' @# T7 E$ O, i/ F( ^1 D/ `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; E/ R# u2 s) N! ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ P& n) ~8 I8 p n" J3 @6 i7 e( J$ o+ F
EDMA3_TRIG_MODE_EVENT);
+ G! h4 s2 f# P/ B+ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 Q; C( F" d8 s- Q) \9 }+ `+ k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ \4 Y# g/ J* D1 ?" O3 O* x& iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* h, W2 d& J2 g+ A9 a/ [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# I, g3 W9 e' j5 Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 K0 I3 y8 L @- M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 U+ f7 Y' f9 y& h- `* rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
d9 Z- A9 _7 {# z! F; U. d}
8 g9 T( n( x* d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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