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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 E9 |$ V; q/ A# V- b6 v
input mcasp_ahclkx,0 ?$ R2 R& a' {
input mcasp_aclkx,1 f$ i& A2 J8 G' m9 W' R4 h
input axr0,4 G2 y) N7 k) ^
$ f5 V! K6 M4 U* |output mcasp_afsr,6 s+ { Y( D+ b
output mcasp_ahclkr,
( @0 ]) X$ a2 i- {- Koutput mcasp_aclkr,8 c! ~5 o1 A' ~! _3 W% x) f5 Z6 I
output axr1,) X! x5 L8 b( d) m0 D
assign mcasp_afsr = mcasp_afsx;
; N; B+ i- J6 k, k+ }assign mcasp_aclkr = mcasp_aclkx;
. b0 v( d# t% Uassign mcasp_ahclkr = mcasp_ahclkx;! v! Q" ]" q6 n% m3 P D/ c
assign axr1 = axr0;
* S2 R( m. g& s# H$ Q5 _$ }
8 g1 s+ w, v# x2 {/ q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* B# E( f( f6 a/ qstatic void McASPI2SConfigure(void)
9 R- B8 | k) u2 D( Q$ b4 w [9 T4 F{
) J% \ S: @2 z, ^; c1 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, x" g" Y7 j$ F; p! g* O. R' E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 A7 z/ F( \2 S$ V& U5 _. g9 Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 @* z, `, e) T( S8 O, EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) K& p$ D. w+ @2 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 J" k1 m0 a) I+ q2 ~MCASP_RX_MODE_DMA);& U$ t5 m+ D4 Y: [8 b+ }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, c9 k2 b- D6 A3 q( g! d* e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 y" g$ a* F9 |. B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" i3 r. u" {3 |; CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 L5 }6 }% g, WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 [- m& ?: F+ M0 e2 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) |; p& R" N% M% L) O! S% o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 k1 G4 J' Q; T8 k% X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, e# w' b9 O T' e8 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 R9 o% k C' `% |
0x00, 0xFF); /* configure the clock for transmitter */
3 w/ y0 ?: o! \! }' y& CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* d6 w7 H0 ~: f5 k/ [) O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - k2 s4 B8 n1 @6 C/ s; f) V2 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 S6 c$ M- ~9 T+ T/ ^0x00, 0xFF);. h: N5 ^/ c% w( \/ I+ _
$ v: [3 k+ h# {! M+ p
/* Enable synchronization of RX and TX sections */
# B; r" h* ^; H: ]7 l" [% NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ C% @& I/ P8 [) `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 D' x$ R$ [0 o: t) l" xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 l1 K9 w+ U% d; a0 x0 G** Set the serializers, Currently only one serializer is set as- m. `, f& \, h
** transmitter and one serializer as receiver.
3 \( k$ x, e! e4 C*/6 G7 N m$ Z& Z4 V; B2 B J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 B. z3 M! D6 H9 e. a8 T2 e9 p i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) A+ m+ N: |' x" y$ S- d
** Configure the McASP pins . e0 M: u* {5 O" q
** Input - Frame Sync, Clock and Serializer Rx/ r3 r0 L$ ?( k m q
** Output - Serializer Tx is connected to the input of the codec / k2 r: z _! {. ^
*/
[9 l+ b" s9 Q3 o' DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); l! J \7 A5 i; b( j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! R/ S6 B/ G" m* A9 N% ^, S2 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ r# f( A3 u8 Y: M
| MCASP_PIN_ACLKX) n8 {5 t. Z L" a ~% y/ E
| MCASP_PIN_AHCLKX
% X4 W$ k% W3 v. p) j8 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- t1 L0 u! d2 L% V1 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 I% O0 c3 d3 L* r, I* }" F& W| MCASP_TX_CLKFAIL : j9 M% o' R. C& U4 b/ Z! z. ^
| MCASP_TX_SYNCERROR) z1 o; N0 ]: b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . x$ z2 ?2 e# O& s* D
| MCASP_RX_CLKFAIL
: j( m! f; l% ^0 L9 {& f) V' m| MCASP_RX_SYNCERROR
3 l% I8 d& [ ^: }. B8 O| MCASP_RX_OVERRUN);
7 F( n* R+ h7 z} static void I2SDataTxRxActivate(void)' k2 _1 c6 k) y6 P* Z
{
l, X$ w/ F, }# `+ D+ M/* Start the clocks */
i u' {: b2 j7 d4 t2 @5 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( `) J+ F3 E5 a. \6 D; xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 K8 t) c9 s8 \& H9 l0 Y0 s# _3 @ y: A HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 f6 _) Z0 P1 m
EDMA3_TRIG_MODE_EVENT);6 x0 W: D5 q3 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 j4 E3 @: W$ f4 q% w0 Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 h* O8 O+ n/ Y6 F' VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 d0 k# ]2 V. W. }9 g( b/ g; ~) JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 Z7 j7 i; @- P3 u' s0 n/ ^9 D( s6 Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& F* y4 Z, m6 d, b# D% w, ?, T4 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" G1 [. }7 F: y2 lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 N4 Q4 M- v r$ P7 L; Q} 3 W# Z0 N5 F/ Q" ?, A. C# J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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