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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 g5 B O& j6 q5 Dinput mcasp_ahclkx,7 f) M0 O' @$ U% y2 A4 x
input mcasp_aclkx,
& k& Y# h2 m5 m; z0 uinput axr0,3 i/ x' r- i! r8 S) \! i4 c2 j
& e+ U' V7 A! \9 ]4 V# _output mcasp_afsr,
7 A: m X ]! B3 M& poutput mcasp_ahclkr,, t' I) P5 v: k# W
output mcasp_aclkr,' X7 e# M% E8 Q8 R; \. O
output axr1,- V% e4 c$ M! f V. E! L
assign mcasp_afsr = mcasp_afsx;, _; u7 |: `0 s: A ]8 U( c& G# Q
assign mcasp_aclkr = mcasp_aclkx;
0 h9 u9 T: h+ V- ]* u6 [assign mcasp_ahclkr = mcasp_ahclkx;9 S, u% @2 S, u* n/ I
assign axr1 = axr0; # z- }* l( u. E3 t6 A
|* c5 L3 s0 t5 i6 S7 H# h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ J8 X1 e( G" T& i8 _static void McASPI2SConfigure(void)$ K/ N/ o( K' Z: Q0 V, @4 O& r+ [+ j
{9 G) [4 O0 N" h, J/ U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* U f3 P6 {0 C( I$ x/ U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* c C% L( t; d0 i# q5 E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, X8 B7 V# x9 {* Q0 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) j6 ?! H. Z3 r' p. x% }3 O% wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ~: ~* b! a0 f: j+ c! x
MCASP_RX_MODE_DMA);: q9 A/ y! Z8 C/ x4 C5 |5 {( a) I6 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 X# G+ G" w, r0 C X7 w W, O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! E: x9 f6 U" p0 y# O4 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ ?9 E) ]* `6 E3 z9 i: \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. S8 h+ R7 H8 n9 mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; v" J: \; V uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: J+ h- F/ ~3 Q7 M2 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. Q7 K; m* \' EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; @& |% ?- o7 m# z! _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( n" i2 P: p* S0x00, 0xFF); /* configure the clock for transmitter */) [0 I A( m9 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# E- s5 G( c; s+ w; B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 W. {- q1 S4 S* s% F1 SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- T( _4 A" u& @3 p! V$ S0x00, 0xFF);2 {& Q0 B: L9 ^: K* j; d. G. P$ G- U
, i( w, A5 ^9 R, V3 x
/* Enable synchronization of RX and TX sections */
- T0 r+ o) N ~- q2 pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, R- K) |/ m. L. n" R, n/ U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" H4 s0 \ I, ]$ {- S/ w1 u. @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 P) `% Q6 l9 B5 U- s" _
** Set the serializers, Currently only one serializer is set as
3 L" O7 k* A% O& R1 f( Q x9 v** transmitter and one serializer as receiver.
6 `% i9 j$ [& T. \: ?: o/ X" e*/
. ]! |* }1 P( N3 f6 j5 T3 w8 p2 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% n. \% l! d' I+ K' _8 U1 u9 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 s1 X0 r t4 y0 _/ t
** Configure the McASP pins
1 L" O+ c: ?$ d: [+ G** Input - Frame Sync, Clock and Serializer Rx
* L, Z7 p" m# R** Output - Serializer Tx is connected to the input of the codec 5 @' d! K0 B, J8 H" d6 a0 h1 v
*/9 I$ C: c: B1 s! p' } x9 h) {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 w6 A8 V9 ~5 {6 `& x0 }" P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ D6 W/ F! g, J$ U' |1 g' `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& k+ {' W6 s- W0 P. k3 w8 ]- O| MCASP_PIN_ACLKX0 c' Z$ ~* A# h9 j* o z
| MCASP_PIN_AHCLKX
; i7 s, O: D( n, M$ Z2 X0 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: m3 I7 c' U) P2 r: j3 W* g! S. CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR F; a H; C* q, i O O" s
| MCASP_TX_CLKFAIL
& Z; l$ {. @" d& b| MCASP_TX_SYNCERROR. X6 N: t+ m7 N/ U+ t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 t" ^0 U% I0 j( O| MCASP_RX_CLKFAIL) }# C$ V6 s/ I) D, S
| MCASP_RX_SYNCERROR
( r* [, y- K. X, h| MCASP_RX_OVERRUN);
! M7 y( t* c: W5 ~, {/ z} static void I2SDataTxRxActivate(void). }( q- j1 s( ~8 `
{
7 Y& `# T' g7 O: p/* Start the clocks */
6 k4 A: g7 t$ ^) K% q, eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' S( m; c1 o3 x8 S. M- g, |- wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; X. b+ R* A; r% q* Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) b: g. d% x0 @* d
EDMA3_TRIG_MODE_EVENT);
$ r$ H9 w+ r7 D$ rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) g- a+ |2 I) Q. }, J, ^( i/ q8 F& ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 a- L; N) G" G( a. b, V5 p, v5 j# [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# p5 q6 ?4 z" y* S2 Q& a5 {# `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) d& `. T/ [4 Q0 r5 A1 M: h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ h/ }$ q) ^; f% O4 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" H1 q- v: w+ R: XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: C" T# r7 t5 t# }" Q2 h
}
; G& \, U$ o: n7 t. u: F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 d6 g" f2 L3 B2 ~
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