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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" G R4 Q2 p$ w& I- o' r$ Einput mcasp_ahclkx,5 W+ @. ]$ R0 ?( T& C& k) S
input mcasp_aclkx,7 R( \" }! Q4 |. l7 s0 L1 \! ~
input axr0,$ ?" J- {- U7 z$ T/ Z6 r
; D* o, U3 l" |' y. m
output mcasp_afsr, k: E4 R0 f0 \
output mcasp_ahclkr,/ u# T* Z& r4 K8 ~6 Z- ]
output mcasp_aclkr,
" H; W F* s7 q, f4 xoutput axr1," Z; W% z1 t' W5 X9 n" v" c( t
assign mcasp_afsr = mcasp_afsx;' H! j/ N* y) V7 G/ `7 b' j `
assign mcasp_aclkr = mcasp_aclkx;/ Z* E1 I9 I! Y6 O" f. c
assign mcasp_ahclkr = mcasp_ahclkx;& D. K6 I) x8 r# V5 o
assign axr1 = axr0; 4 T. O+ O$ q6 v1 A. F. y" s1 q
: \$ S" [0 G- J0 j9 ^. ^. ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 e4 r& J! t- |/ x; {+ ?. a7 xstatic void McASPI2SConfigure(void)" w, U) b2 a% s% g& h! c3 q/ Y
{ x+ \, U" E1 V. ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. n$ E& C8 b$ [' {8 b: K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! R- W- ^6 O- j) I9 V6 E6 p4 j' BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% A7 I# w% ]) N* RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 h- @8 F3 x( P0 n6 K1 N- \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, H6 ~( r/ T, ~MCASP_RX_MODE_DMA);2 F# r7 B v% X" r" l& n" X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 x% H! K5 @5 D' S6 C4 i4 o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ _" X; E) B4 n# x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 c7 [/ C5 j2 G8 S! `( G" f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" E# J: o* _) J. z- e! D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 }& }* E1 c7 e) c7 P- R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 G% t8 u/ S; a7 I; X" P; V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 h2 b/ C0 ^0 f% N; TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
G' W. E% X( R$ a4 G, t7 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 K4 S$ f' L8 O0x00, 0xFF); /* configure the clock for transmitter */, Z! ^3 ]9 m/ g6 }6 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* S9 _: _# V1 m" G# B6 y( i. k- U5 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 h! [# b. i5 S% AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 d4 W( f" O% \1 `* D( j; m0x00, 0xFF);$ b) f" T% e4 T: Y7 n/ m/ {+ `) N
! \; e b! r' r; j) J7 r. D$ ~/* Enable synchronization of RX and TX sections */
; N9 u( J! B& f: S8 h- }9 d+ v. T dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) ?5 b8 G2 B; N" O( n% x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 G" B5 }; }& G2 ]4 z! E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- d. Q# @+ o6 F9 }& [' ^9 h** Set the serializers, Currently only one serializer is set as7 E2 [4 K5 K9 g4 Z& C5 h( g
** transmitter and one serializer as receiver.
3 Q1 U8 F2 N# U) f*/$ @1 A/ {9 a$ M3 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* M( m4 t w4 h# h2 k3 H+ [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% @+ V" ]' Y6 i1 L
** Configure the McASP pins ' m! t" W) S0 |; Q3 m7 X9 l6 w; S& ~
** Input - Frame Sync, Clock and Serializer Rx5 u. I; b- k' w5 B
** Output - Serializer Tx is connected to the input of the codec
2 k/ J1 x, Z2 _1 Y9 p4 P' X0 w# j/ O7 @*/
# f3 D! G6 S u6 b2 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- F0 A- \) [2 P! O, I t% D3 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 z J' b9 h2 z! C; B) t! wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& G2 L3 \0 G9 _& e) i
| MCASP_PIN_ACLKX" s4 g8 x( P; J6 J2 I
| MCASP_PIN_AHCLKX
9 {% X$ U. F( f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ U; p& c# P( N9 j* g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: w. r1 C, X$ T/ ~" ~| MCASP_TX_CLKFAIL . d2 T7 K/ f% c) P( d n2 c- Y
| MCASP_TX_SYNCERROR
+ u$ a% d4 N+ d2 n( {% d- A) q: c* A/ @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ p' u* ^9 [3 h' j! p" v9 M| MCASP_RX_CLKFAIL6 k. f+ }' k7 L# \
| MCASP_RX_SYNCERROR
2 y' |! i& A# {# v2 I" U3 K( _2 x| MCASP_RX_OVERRUN);
( n, B& o. s8 k} static void I2SDataTxRxActivate(void)
5 {% @9 \9 i% T{$ ]: w3 I; i0 i. W( e( L- |
/* Start the clocks */
6 P, _8 } N: |2 b( J$ v0 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) H4 j5 S- [2 F8 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. q$ \+ @+ w( t9 U) C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 L; j1 z1 a# Z. H( m' qEDMA3_TRIG_MODE_EVENT);
, R4 n" ?3 m" Z+ G( KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 |( {, v6 H3 W1 u# O! l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" \- I6 X2 n7 ~+ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 X& L; u3 f9 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 ~ O) y* i! @7 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ X8 I$ {) N# m# _: e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ ` @- X0 Z# X$ v# _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ ~, _+ H3 ~9 c6 F* S- A4 {
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