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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, G% ~) x) I h' n1 Finput mcasp_ahclkx,
, m5 F# G' a" D _8 F9 \! {" linput mcasp_aclkx,
9 n' P; s% @ h: f Z* [7 G* tinput axr0,6 j# B0 |$ b( Z! E1 e6 g# p
4 ^1 ?& {' }- l) q2 T
output mcasp_afsr,* m C6 m, H- s& Y) m5 z) m: |
output mcasp_ahclkr,
) N& A' W$ M% {/ F+ Eoutput mcasp_aclkr,
! Z7 C/ D) t& J! soutput axr1,
9 D* O- n2 ?) X; H1 L: ^ assign mcasp_afsr = mcasp_afsx;
' J1 D* f6 {9 c7 G' ^; A9 Iassign mcasp_aclkr = mcasp_aclkx;
9 Z4 c2 \2 N8 _( [# Qassign mcasp_ahclkr = mcasp_ahclkx;
1 D( z4 ^2 w* {0 N( w. Zassign axr1 = axr0; 8 Z5 v5 H9 d5 i1 b7 M/ }
1 \8 {4 s( @3 U8 ~& |, U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& V9 _8 x2 e7 R# vstatic void McASPI2SConfigure(void)
7 P, o" E; y+ y8 E1 C{
7 }9 @8 i, K) P* yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& q) x* b: k1 Z" h' [8 ^& SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// {# E" `& J( i% q$ S2 l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" Z& J ^! l9 _3 v6 K/ @6 S3 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 _! x) O, \) l; l) \5 T- r( E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 A) r/ J0 ~0 e w2 L5 J( b, TMCASP_RX_MODE_DMA);
$ N/ g y; D+ ~# ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 k- G/ T+ ~+ }7 k- e7 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 |9 X( ~. P& y. ~) J `! ]/ M. b5 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 U, ^ ~ w' g$ U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 X0 s$ H" ]& E/ tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" M! x3 Z) {2 P7 K0 n1 MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, D4 m4 g6 O2 C& R6 c8 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% z4 D4 j( P9 g7 ]6 q. `/ V( ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 d. V% W; K" e- O0 H8 F& R+ b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 ~1 E. u" n) m, w6 Y
0x00, 0xFF); /* configure the clock for transmitter */
+ p) F0 T( k. U! z% F7 U8 D3 TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 A% F+ k8 j+ V" S) J( r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% r& p G0 F2 Y' KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* q. h; W5 h+ a7 P8 d9 R: |6 G7 A
0x00, 0xFF);
1 M2 R& c/ s f
( {! R/ G5 G# f3 R/* Enable synchronization of RX and TX sections */
, i* g+ M2 [, H4 F8 d0 y% }4 Z+ DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- ?( B5 R! A, M" X0 d8 G- Y0 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 q" m+ X& c* l, w$ I& ^. p2 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 I$ Q: |7 g# e. C0 @- @5 Q# o** Set the serializers, Currently only one serializer is set as
; m: O0 K V; Z; y0 i6 g** transmitter and one serializer as receiver.
& r+ Y- f( r2 z% G, t: ^, t/ }*/
' w: k. s, X2 ?1 k/ B$ J. BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 `( e7 L3 g6 k0 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 v+ y5 v+ y. ]% k8 T2 V, {8 b** Configure the McASP pins & r3 h/ P8 a; B P; Q+ m
** Input - Frame Sync, Clock and Serializer Rx
W+ O7 z( |* \. ]/ ], C4 j** Output - Serializer Tx is connected to the input of the codec
7 T5 x" R+ e! t4 O @8 h, t, V" u*/
* ~0 L# [7 q- ]% Y0 n% X8 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 T6 w9 T, \* \9 N9 A) N. h5 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 G" t* b }% I1 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ]0 `5 u9 q0 }2 S. E4 ]( o- c# } l| MCASP_PIN_ACLKX9 Q8 `" S2 H! b* I& C. p0 h e
| MCASP_PIN_AHCLKX7 c1 p" y& G3 T$ g. f O1 y% u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% p* a. N8 a4 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 M$ J, ~& ]: x- d
| MCASP_TX_CLKFAIL
1 \1 T2 Y. R$ G| MCASP_TX_SYNCERROR
! R [: D) x Q4 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 M1 j: J8 j- a| MCASP_RX_CLKFAIL, q. O. N+ v5 `. _; N4 L
| MCASP_RX_SYNCERROR
! B$ F" ` j# |$ l: X1 p7 ^7 P| MCASP_RX_OVERRUN);
) B; C- u! S; F, ]; h0 H4 A} static void I2SDataTxRxActivate(void)
* Z- a2 T( V+ _+ U+ V{
" U0 r# q! R8 J$ o/* Start the clocks */
: M+ o2 ^; X1 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ \2 ^) H y @: D; ^3 ]& x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 | W# D+ o% t6 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% d( R* d1 @$ F6 @EDMA3_TRIG_MODE_EVENT);
_) q, ?- u4 T& c6 z9 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 a5 U9 g; Z1 M: _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. s2 ~$ e @% Z" g: q" w( C& W$ Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, T+ G4 U, \: W8 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
{$ o# j: P; {) }7 X: {0 C* r bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' v6 w. o A! H9 i v$ R- pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 k9 s/ K+ ^& h' K* o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 d& x7 Y* W' H} $ j/ M7 v, N, W6 T; {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) O- q/ C! q0 p: v! ~
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