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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& b' Q" ] W) {" V3 T! tinput mcasp_ahclkx,! u+ _/ V6 ?7 p$ P) j( g8 v, h
input mcasp_aclkx,0 l/ a4 ]' R% ]8 j" k4 F) ^
input axr0,2 R/ b$ s( ]6 i: s& y( m6 ?! k
3 f# }9 G4 v: ?0 T% Y2 X1 voutput mcasp_afsr,2 H0 O8 b2 Q- l2 g
output mcasp_ahclkr,; E: b& W( s2 N+ b" h* J
output mcasp_aclkr,
) O i$ s9 {1 i) goutput axr1,
' ~& G/ ~4 K8 j. R/ [/ |$ T assign mcasp_afsr = mcasp_afsx; g) M- a0 Q+ J: h% J4 m$ J' b
assign mcasp_aclkr = mcasp_aclkx;6 ~2 p" R$ x) U! J! C! n* H9 l# `- X
assign mcasp_ahclkr = mcasp_ahclkx;2 S& p7 j) P: `/ t+ G8 [
assign axr1 = axr0;
) ]/ M1 \! M9 ~) `' U8 S9 d
0 U8 }; f2 f( D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : [& x+ }# _& q8 x
static void McASPI2SConfigure(void)2 k- `- \) J/ Y7 {9 l) ^& S
{/ t: P$ {0 p" P1 b- M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 Z2 M- j" G6 X0 n; k m" F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# H8 `! q% a' K8 T7 c5 ^* p2 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# j: p, C* {& D8 Y7 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ |4 q, C! P `$ B) v, o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ^4 O/ J3 G2 F5 w. i0 d
MCASP_RX_MODE_DMA);! V# ]: D, v: b" v- ?0 } ?8 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: _4 s$ ~1 ^5 Y* }" n' V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- \6 k: C+ {9 M4 B4 j: RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , z/ p- w1 G7 H. k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ?4 @/ j+ W r" s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 A) k" Z& N& q7 L) T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, |: U# _+ u1 d- D% GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ g/ O1 A0 j; X l8 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * ^, A) B0 C, b# [8 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# ?+ Y1 l6 [5 l. U) x6 q: P" [. j0x00, 0xFF); /* configure the clock for transmitter */
3 X/ Y' L0 b4 J/ dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 E9 a# x' h+ T& ]5 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( M1 o* I2 J) \0 l! g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 \+ @3 c m2 j6 ]- \& I
0x00, 0xFF);
* q6 G [( O; b6 O* { A2 V0 M5 v p
/* Enable synchronization of RX and TX sections */ x) W- s$ z+ K4 M4 X4 \, W# @. N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 O6 U, u/ Q: ~# }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# E6 b; Y! ?/ K6 p( e J2 _' T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 p( N3 y8 e% ]8 `" \** Set the serializers, Currently only one serializer is set as
4 Y8 L6 ^% F0 l- e* i** transmitter and one serializer as receiver.
. ~* ` X. Z( I" t. P*/; w0 s( ]! {/ a3 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' L+ V K% A7 Z% H+ v! ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' y8 ~% a* E- D- v/ w! o2 Y5 }** Configure the McASP pins 1 j0 K2 z% z; c3 ~& `( n
** Input - Frame Sync, Clock and Serializer Rx
* z( P% y9 c/ K$ c+ { w8 V** Output - Serializer Tx is connected to the input of the codec
( _& p2 V0 \, r c8 K% Q*/
9 X* ]; f2 i' \. x$ J& KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( p$ M1 e" C$ v# aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. ?# Z0 F) r5 s0 @( eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 P1 q- T, w5 e) i0 v1 H k| MCASP_PIN_ACLKX2 t; ~1 a; u4 e: _) T) t
| MCASP_PIN_AHCLKX7 H; j P# z5 Y$ C6 u" X! \1 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; _# b7 h# @: E, W" g- p- ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' o+ C5 H5 U2 j| MCASP_TX_CLKFAIL
) {! m! C' N& n( Y6 N| MCASP_TX_SYNCERROR9 ]7 }0 p* t) X. Z+ i, e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & y& P5 }" B S; D: T8 B
| MCASP_RX_CLKFAIL
! L3 i2 j4 X2 u+ r) k| MCASP_RX_SYNCERROR & ?1 J3 g8 ^: K
| MCASP_RX_OVERRUN);
* V( {3 J' W! K. B8 n2 {4 j N, x} static void I2SDataTxRxActivate(void): S. G; N5 i) h9 j; H- O8 I# C: c
{% B; }1 r l6 O# G6 R
/* Start the clocks */& K* Q/ J$ |, D. v$ I( @3 {7 Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! K# i, ?/ S% _& @" J! P2 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 H5 w! a4 J: ]& G5 ?3 B) sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 t, ]& ]+ U3 w* o8 L/ T6 N
EDMA3_TRIG_MODE_EVENT);
# ^ j, y. W/ V9 \( k. HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 V) u5 [' D; G0 u/ T7 a4 b4 l( @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" S) j% Y4 ~) F6 u6 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. |6 [, a/ I4 l0 y2 h6 t5 s0 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" d2 ?8 g3 j! M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 M0 T0 x" [4 {3 ]/ o3 ?7 }, ]* s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); }7 R3 ^( e! F" O1 m, i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. J9 x. p- [) q3 j+ }( b1 j- r
}
6 M2 _9 d. m$ N! S4 | T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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