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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) x" W: Z x# z2 H3 Y# p
input mcasp_ahclkx,
& n L$ h" ?3 H y- Linput mcasp_aclkx,% b4 S- s; I! F" b# ^1 B3 S
input axr0,4 B( V& d. G$ j# g1 j4 x
% _# t% ?6 a) H2 P v
output mcasp_afsr,
1 R( y0 Q9 L7 L/ y0 u2 F" J# Eoutput mcasp_ahclkr,7 ]' F7 Z" _. N7 A& [$ v
output mcasp_aclkr,
! o( U6 z* e, c% D& j# h* _1 W+ soutput axr1,, d# n# T6 r7 ^+ A Y& }
assign mcasp_afsr = mcasp_afsx;
$ R. Y. \# S3 o Z+ {, J& ~* v# cassign mcasp_aclkr = mcasp_aclkx;
# t' w+ c" R E6 g. }assign mcasp_ahclkr = mcasp_ahclkx;
9 C& \; U$ o6 F6 C6 Qassign axr1 = axr0; 9 p4 [" C( t- U/ }0 |6 E
& _: l. n7 r& S- e; T: o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 {) }) d3 T9 ^6 T% t7 t
static void McASPI2SConfigure(void)+ Q' b& ?6 a& c j
{
) x O+ P) k3 b2 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 ~5 Q! }/ J' f& m% I" k! \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ C% l$ o8 d& _6 Q) ]: lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 }4 Y# x0 V. N/ HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 G7 M6 j2 h6 Z- G4 q, f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ j1 A# q7 M! w7 G. ?
MCASP_RX_MODE_DMA);* B ]7 s3 c. ~! g( t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 J- F. i- M( `9 t% H: \, iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 N m- q( `3 N2 D. q' r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 V" n/ ]% X4 h" b7 x& M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 Q7 n/ T- ]! C6 M& \6 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 G# R' T! P: ^% T6 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// x0 S3 o% y* j; I+ l1 h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; U+ |# I7 W; O* z. }; X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 H1 S5 `1 z6 Q/ T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: {: w0 r0 a7 e+ Y2 l0x00, 0xFF); /* configure the clock for transmitter */
% w2 G+ w$ n. i& p( y# s r: ]( bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' l( }, @( Z1 c9 k2 Z% p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); F; C* U& v# N/ p( ^+ Y% R+ w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# N9 o! L) b9 R! e, I$ O7 \
0x00, 0xFF);
- b! x( A- R9 ]/ W
) Z1 x; W3 Q! s: w/* Enable synchronization of RX and TX sections */ 6 ?5 T% U/ A' s! s, d, d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 o# J9 p8 F; i# \- w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& w1 B: B% C; f% T4 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( d/ M& Z& z9 J4 W# ~8 Z
** Set the serializers, Currently only one serializer is set as" E' o1 Z/ `; @! B1 z
** transmitter and one serializer as receiver.
( o- X$ |$ N! X*/
! ?7 {0 K& t6 W$ a; D% ?. JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( r; ^, X& q6 V' y4 V. W% S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( H. u; T# K! U* c** Configure the McASP pins
) [, y# r8 g" D1 J** Input - Frame Sync, Clock and Serializer Rx! y8 K# W% ~7 }7 S x. N' q
** Output - Serializer Tx is connected to the input of the codec 8 T9 P- }6 I0 F+ R/ o+ e9 f
*/3 _ \4 Z& l, G) U3 U* a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ L- H2 J$ x: C+ V2 b$ q! FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! I8 |# u c0 @6 U5 f0 A* HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 a. U" V& z- O| MCASP_PIN_ACLKX
! X& X5 {0 R( h2 b: x! E| MCASP_PIN_AHCLKX
+ U$ I2 v1 ]* @$ K! M& ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ T6 C, @) j1 j; |; v9 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 x* Q" O- U, n( c
| MCASP_TX_CLKFAIL
+ x$ B- o0 U) o: j; N7 y| MCASP_TX_SYNCERROR) J9 W/ e4 P% N8 E' t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ c, z6 M& `) u" |. Q, e| MCASP_RX_CLKFAIL# T# Q- P- n% u& P3 X8 R$ J7 H8 e
| MCASP_RX_SYNCERROR
+ R* i8 f: M3 F| MCASP_RX_OVERRUN);1 X2 v) J, I" f2 }/ w' F
} static void I2SDataTxRxActivate(void)
6 J0 Y& |) y# s/ S{
; K& h3 t$ v* b' }8 c! L/* Start the clocks */
5 f1 [2 y. X$ Z8 Y4 N* f/ I8 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 u/ n( U6 _' \- C; @/ g% Z0 WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 B- |5 o. k Y! `# m l: v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
i3 e9 C3 V5 r0 ^4 k+ {' i4 y3 d. K9 _EDMA3_TRIG_MODE_EVENT);
2 x" j: o7 u3 v; p# IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 ^3 @: r' `/ p) m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" I8 F+ `1 Q, q3 K# }$ q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& |# T1 Q7 p& g4 m; |1 [; LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. b8 E- b2 X9 L; n" I Y' lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- k0 J7 r5 n; |. Q: R+ w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# ~. T7 Y8 r0 x4 U3 u" H' R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, T1 v }- ]9 [! y4 R: C: K
}
- _0 D7 x9 w: j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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