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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& Y0 I, C) D( xinput mcasp_ahclkx,$ X3 h S( c- a% u$ u }
input mcasp_aclkx,
# \* V; A: s% m7 ~input axr0,
! \" | m* s% X2 V( i+ g1 K% `; `7 r: Q! P
output mcasp_afsr, w; f0 J: J( `8 X
output mcasp_ahclkr,
. z7 o4 h6 \; q M. Z1 Poutput mcasp_aclkr,
2 s7 ]8 U R' \, G+ N A F* Woutput axr1,
# R5 {. ~8 c& c$ X- p5 ~# t4 | assign mcasp_afsr = mcasp_afsx;
, I5 I/ a. @( J/ E/ Q( Bassign mcasp_aclkr = mcasp_aclkx;* |' e3 x3 E; l! n
assign mcasp_ahclkr = mcasp_ahclkx;
; Q( B; o( G- R' \assign axr1 = axr0;
: D5 l- |+ j: Y% w$ H' u7 N: e6 |% O& o8 s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
^$ y- p% H0 O0 k8 T# B; E2 v \1 G" jstatic void McASPI2SConfigure(void) {5 `: W: Y: H( q: k7 r0 @
{
1 K: J% U( X1 O1 L- {$ rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 D3 h1 B# F; `. f3 S+ tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 f; b& Q4 h- I+ E5 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( \5 h6 U, i$ ]/ b$ m" K( aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ U$ k; D( z3 n4 {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 R1 o/ e* J8 Q3 K0 y" ]1 wMCASP_RX_MODE_DMA);
& y# b" D' T/ W* Y aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 O$ z! h* q6 m: V+ T+ nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 P3 u2 l5 I7 R5 T o5 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % q3 }- I& P0 z+ ?. Y% U) s! r" v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' C6 N" W& }7 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& ?! y% q! }% Q! n3 C0 M9 X8 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# `3 @$ I. a. E0 q9 n+ _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ x! f! q w8 Q) m! |8 L0 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ [2 V; e% W1 Z; t; H# w! w& uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& L, W/ \0 M' o& q# ]0x00, 0xFF); /* configure the clock for transmitter */2 l# P8 A* ~0 t& B5 [9 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% o1 I. f, h. EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ `. U3 b! s, hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( H/ W% a: u5 ?8 o; `- C5 P% k
0x00, 0xFF);2 x) b1 u' q0 ]$ h6 U& g+ E
4 q- D h$ T* _5 R7 [* ~" H% u
/* Enable synchronization of RX and TX sections */ ; C8 ~$ |( _3 W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# Q2 ~& Q( p* q/ KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# h0 J. s+ R0 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# Q) r8 M7 }* K. z- u** Set the serializers, Currently only one serializer is set as1 u& {- j: g( n) R+ v5 |2 u. n _
** transmitter and one serializer as receiver.9 U7 H+ ]' W* ^7 I# {* n V# ^6 P
*/- z Q. g) I) R* {$ [+ d; T9 w- h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) ]5 G/ x. w% D$ A6 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
}) Y0 W2 j( I. s& {7 p** Configure the McASP pins
8 `( v% q( \/ E** Input - Frame Sync, Clock and Serializer Rx( c9 s. b ^4 C" y4 s
** Output - Serializer Tx is connected to the input of the codec 7 ]2 e, A9 v$ U. B- a
*/
1 s" f5 h9 @' S9 b5 M! T1 ^# wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- G5 H; L* O" ]. Y3 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 ~) q+ d* I9 p B0 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* m! }8 r. r- `/ s| MCASP_PIN_ACLKX
, k2 {8 a6 p3 \0 r| MCASP_PIN_AHCLKX \, ^4 h1 |; x2 U& x4 M+ w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! L( i- U3 \) L0 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& X& ]1 [- [$ f! Y+ [" Z% z8 n| MCASP_TX_CLKFAIL 2 x8 Z- c- z$ d% X O% Y, r
| MCASP_TX_SYNCERROR
$ ?: C; }$ h, x/ {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : _1 s, Z0 `6 m8 X ?5 I3 y
| MCASP_RX_CLKFAIL
7 C: {" ]4 m* x4 |1 W q2 ^" c| MCASP_RX_SYNCERROR : Y# g! Z* i$ l$ Q3 _! Z- M
| MCASP_RX_OVERRUN);* g6 S9 N/ n4 r' @0 s& {
} static void I2SDataTxRxActivate(void)" v. W; F$ x0 Q1 t5 W/ k
{
) I( L4 P; h! ~; D) N8 v/* Start the clocks */
" a& ~* X9 y5 r% S7 e0 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. _( \& g2 K; T8 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) Y, ?& Q" P, s6 k. M. U7 X: D; YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! |: i$ P; u( K( z: ]+ z7 dEDMA3_TRIG_MODE_EVENT);
4 V4 N6 m. u% H6 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - \7 \: @( ]: V5 z8 h; X7 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 o+ K- f: S8 K- X' g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" z& e0 ^9 \5 I- J: XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% X0 V6 {: q' d# I7 M4 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& q- B& C: ^. T" @- B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; Z3 A3 o0 G8 i' f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ {1 d" s- K- X. x' n} ) P1 l% q" I1 L$ V/ Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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