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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 {& R" w: m' a+ {
input mcasp_ahclkx,. u, c$ y, E: S' W9 M: X) N6 r
input mcasp_aclkx,
$ a6 _3 N7 O3 x/ l& @input axr0,( `" z9 f I$ m9 g+ W5 P5 s: @& x# N
) Y8 B& n; e9 Qoutput mcasp_afsr,
1 k5 x. k/ }, J* {5 J# M) y, q0 Woutput mcasp_ahclkr,
& o; [8 a2 D- m, c! Noutput mcasp_aclkr,
6 ?4 `! B2 q' R4 d, X8 {output axr1,
, G2 D! }3 G9 A+ }% s+ u assign mcasp_afsr = mcasp_afsx;) Z! @! V( y. m
assign mcasp_aclkr = mcasp_aclkx;$ K8 @: P/ D1 k+ Z: V/ e, D
assign mcasp_ahclkr = mcasp_ahclkx;
5 C2 I. ]) L% F2 e3 ~. ~; Lassign axr1 = axr0;
7 O1 U. E: ?! c' O8 H3 k7 I h) K2 }7 }+ y! l9 i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # c. h, N$ T8 t' {) @
static void McASPI2SConfigure(void)3 N; h+ y2 r/ z5 u4 [
{
* S1 T5 N; Y% Z5 s; aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 E. s9 C7 z1 y- a$ y0 G( P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- Q( \, n; G( H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 n$ {& u- s6 W# N$ i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 _+ j) j3 g1 ~+ B# N: U @6 F9 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 r' U( W# H2 D( T: \4 `MCASP_RX_MODE_DMA);
" {& O2 p9 e5 }$ S2 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& J" u# N* P5 g% F& s8 IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( H7 m* ]) L5 ]' C) T: _( FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 ^1 x) A- {/ [4 H* ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ y$ i: W$ s) H6 p9 o# R6 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # L) G6 O9 l$ Q, R ~ G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, _1 p/ o$ _0 O, G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 T: O' d2 r# S; L! A9 z @6 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 z l" C; B7 O5 O% a& u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 r# F" ]* k0 V- A0x00, 0xFF); /* configure the clock for transmitter */
! `, \! O' r* `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 k. q& b. F: R- E9 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! A5 J4 g1 E+ G; h4 C Y- P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 V' p# M5 w0 f. R5 G! w$ B( R0x00, 0xFF);3 X3 O7 P" ]$ e, O7 Y
) Q9 c% ]! q3 S- ^/ Y5 v2 I
/* Enable synchronization of RX and TX sections */
L) c( }$ }: U9 wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; ^8 V F8 d$ d! {+ M2 O* n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 }# X" F7 W% M" i! c- lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 B3 \, @/ T. I! I$ R** Set the serializers, Currently only one serializer is set as2 O6 I& f+ t7 a- I5 g5 E
** transmitter and one serializer as receiver.
% ]; _4 ]; ~3 l7 S( A*/# \' U3 E% h" A6 s; Q8 {& y& J- j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 h1 p$ X L. D* @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( V3 ~4 H4 }. T. T9 o+ e
** Configure the McASP pins
: U' H" m$ i T1 s** Input - Frame Sync, Clock and Serializer Rx
/ h! z* N5 u0 k5 s. X) p** Output - Serializer Tx is connected to the input of the codec
& k" O8 a/ p' t% A3 B( }% \! y*/ y0 t+ Y7 H% F0 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% A7 b0 C! U5 g4 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ q2 ]" h6 a! Q; G3 J z& r: u+ OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 E! C, s6 E$ N+ O0 n0 p
| MCASP_PIN_ACLKX
' t- C5 W6 ~3 ~+ X1 s& f! h7 @6 B| MCASP_PIN_AHCLKX
( \) a* q+ A/ J' r/ _9 s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: S }% L/ ~0 y5 K0 n' g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & `5 {+ m1 d/ Z5 e! N) _' h( ?2 v
| MCASP_TX_CLKFAIL 5 l9 m" O# S8 b; O$ x4 u
| MCASP_TX_SYNCERROR
I6 L. S1 L, o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' t. A: X# l* B- E3 f+ D
| MCASP_RX_CLKFAIL
( ~9 b; G+ r+ U1 b0 K W| MCASP_RX_SYNCERROR
. D* S% H- Y- E l( h7 j| MCASP_RX_OVERRUN);3 P: Z) r. r. y; y7 x* u" {
} static void I2SDataTxRxActivate(void)
T" p* n3 Q- A) O3 P{
3 d9 a6 b" |& f4 t: V7 D3 V% @4 S/* Start the clocks */0 ]6 F5 R4 k( `* c6 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 J; a- I# Z9 U+ V, Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; U1 M$ {! o( K; _7 u1 w7 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 a% D0 Q* O& D# O W |
EDMA3_TRIG_MODE_EVENT);. q% Q% o% ?6 D! G' \( g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 X, r$ p. R0 w& GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 H; S& h$ O; v! p0 U6 v0 t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* S* t# a& p- v2 C! r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, v8 W% r; Q3 g" W- Y% P0 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 s& D% Y$ s" ~0 e% ^* F$ z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. Z1 }1 p0 Y& u: S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 i/ I; g# H O
}
/ {/ {/ N# t% a$ p: V+ |$ T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 O4 M& M# z0 x l+ K1 @
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