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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# Q' {$ _9 m9 f( xinput mcasp_ahclkx,: Z' B+ |1 A! _
input mcasp_aclkx,
8 J# v: p+ b8 T5 R; l% x0 u& ]" J0 ]input axr0,% i7 R: B' F3 e3 H+ u
- _: R4 `. C# i6 ?' G& woutput mcasp_afsr,; q- p. L2 j3 L4 L7 H
output mcasp_ahclkr,
) r! }% z5 y: N( o/ o r5 I7 ? }output mcasp_aclkr,
2 ?5 P$ q; v' |+ w2 Q6 [, A1 U: Foutput axr1,% w# c3 o* ~8 @8 _; F; G
assign mcasp_afsr = mcasp_afsx;" e5 Y2 N7 T. [3 p* V$ W4 u
assign mcasp_aclkr = mcasp_aclkx;+ A/ \( V; w) @$ Y1 [9 N- F
assign mcasp_ahclkr = mcasp_ahclkx;
& \, D* }7 C0 B- W, R* Y! N( k7 massign axr1 = axr0; - B6 d" P' e2 \+ }
' ^/ \- l0 S4 ~/ E1 K, S( z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / V7 K# R3 k5 I8 ]
static void McASPI2SConfigure(void) t2 H% y% T0 y& x3 J; @
{
: A4 m' |5 [4 B/ {+ @* I, }% E6 o. g+ sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% E& x4 g- e$ p9 Y5 X5 L( g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, |. T# y M( W0 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); p$ |: H% c% X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& m& Z b/ `" D9 u4 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; u4 ]7 V/ l" v8 |MCASP_RX_MODE_DMA);
) e8 l5 F, T1 j. ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" F" g1 ~- z. m& l5 h, YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 H0 A0 e( _/ g; b8 f% ?5 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
}0 `/ K8 e" \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 _, ?, t: J/ F' M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ U# c, C0 m0 L0 |5 CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, o3 ^, _( C/ J6 y0 Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 U* M$ z2 j }7 @" ]( [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 @6 b7 T4 @7 _" C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ ]+ Q( z. a. w& \0x00, 0xFF); /* configure the clock for transmitter */
. K/ j% V2 ^0 m( J# TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ a _2 S; o" ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 ?& {+ K4 Q4 h1 R* K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- X( ?$ c# A/ }- v0x00, 0xFF);% L/ C- \- W [8 ?( x1 t$ f1 |
1 ?# _8 P% s4 T, ^3 n/* Enable synchronization of RX and TX sections */
{) j& ~; B2 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 U( p6 h* A7 p, l rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 M7 i6 b) B- M5 K+ G6 @" d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% X6 y$ `; M7 t
** Set the serializers, Currently only one serializer is set as
! d- J0 w" D6 ~1 z: a& x- G** transmitter and one serializer as receiver.
* c- b9 m" B8 n; n*/; Q6 A- h9 d, C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- h" y( ?! ~% g( I# Y! [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 k* ^; A; F+ r** Configure the McASP pins 7 C1 G7 a7 K5 Q& _" V3 D* a* m: E* Q
** Input - Frame Sync, Clock and Serializer Rx
+ v# r1 E1 }) ]' e** Output - Serializer Tx is connected to the input of the codec
6 |& P) H) o' K% R4 ^, m*/
. S3 Q6 }6 Y& } x1 [6 s, r( tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); g/ \7 g, b- ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! `4 l# e6 l. V5 Z5 `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ p* x2 k' L: ~8 ~* ~- d| MCASP_PIN_ACLKX( D. n* s3 j6 J6 e' F; l+ x
| MCASP_PIN_AHCLKX: t- o* e+ G& j( o1 h: \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 \" i7 B* T% F* Z* ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 a( q; ^$ M( {3 p. u7 || MCASP_TX_CLKFAIL
5 E* Z0 _+ {4 _# @% t* v3 m. W| MCASP_TX_SYNCERROR2 q6 t, w+ W; J$ I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 b5 D0 z; N% [9 S- k
| MCASP_RX_CLKFAIL
' E( E V7 A( f& {: \| MCASP_RX_SYNCERROR
. o1 S. x' m+ f& e( e4 g0 n| MCASP_RX_OVERRUN);
$ g, B2 g7 o8 U; U2 @2 N' p' {1 `} static void I2SDataTxRxActivate(void)
9 B% N+ b8 X! _& U! i6 V{6 W6 @2 x6 w! f1 E
/* Start the clocks */
% {+ d1 i1 E) s1 L! E$ _* k1 I- R2 k8 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! E; i W1 f4 t. B% F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ x$ _2 G7 E0 w" N; g9 z4 f4 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ c" x& c6 F3 n( y
EDMA3_TRIG_MODE_EVENT);
1 z/ ^( a* I% s NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 z: K- \4 V5 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; Z- f& W* [1 J$ HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 {" o9 i3 q$ }2 a" j+ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ S/ c9 F% Q: R; _) I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' a: E) \6 p6 d" [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 j2 D# y4 x# O) R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ Y0 E- P6 b4 w. ^. }- Q
} 4 ^8 v( k8 ] I; L0 d8 v* L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) t" T+ i* D( S
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