MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" ^: g- Y- G* J( i- jinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
2 j9 r7 K) h5 X+ i' y! w2 z
" I9 [4 Y9 I4 d9 e) j: I  ~# qoutput mcasp_afsr,
output mcasp_ahclkr,
5 \: K, a* i0 p% ^7 e8 f/ {4 voutput mcasp_aclkr,
output axr1,
9 _( J2 w" `6 J, h2 J  u# _$ j

assign mcasp_afsr = mcasp_afsx;
( c7 l% ~3 k# q) {# Iassign mcasp_aclkr = mcasp_aclkx;
4 O, p- U4 b! z# s, ^; h) passign mcasp_ahclkr = mcasp_ahclkx;
5 b6 T+ ]3 r) R  ^5 vassign axr1 = axr0;

( O& b) ]5 [1 ^7 Q8 l8 n6 i

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

8 ?& L. C0 ~# r7 @& ?0 v

static void McASPI2SConfigure(void)
{
* h6 _6 s6 s% m$ n( g, _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" h* o# a' W! P1 @McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
! r! V# r1 [! BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- w9 F0 ]4 F4 D, J- cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z$ I4 M: _7 q  D& g$ Q5 R$ DMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" u  C: A. q5 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
  O3 u2 W9 @! G  H2 r  EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
- H; @( V# Z5 O8 v4 j1 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% A; Z5 r6 E( C% d; }( o3 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
) W. c: ~9 I5 \8 ^' p4 @& ]: AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
, L! g3 ^. U, }0 i/ _** Set the serializers, Currently only one serializer is set as
# U! `; n" {" u** transmitter and one serializer as receiver.
*/
1 M9 d. ^, H1 U6 m2 XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 Z5 e8 c& B1 S5 a6 l& {) s( aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
$ p8 X) |. d0 Y& m/ Z7 j** Configure the McASP pins
! L% a/ P. y0 |1 ]( B* t: T* e/ {** Input - Frame Sync, Clock and Serializer Rx
% H0 y8 t1 e* O+ c4 y; X; n** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. y7 n) R3 f. Z: i4 I0 s% FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
+ t: R8 Z& Z8 ^- {. K| MCASP_PIN_AHCLKX
# ]' F- L) u: H' p% ^| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
. w4 H% T3 L% tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
# C( X& R8 e1 X6 I  r| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. C, K% [; |% }9 h| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
3 B1 u1 _( @. ~4 L| MCASP_RX_OVERRUN);
. [* K- T' a) f}

static void I2SDataTxRxActivate(void)
{
) ^* P7 K: z$ k  Y/* Start the clocks */
8 F3 @6 `  a7 a. S" KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
+ k: _: w; `3 L& j# x' @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
) h1 {" \' J- l! @  _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
/ A' C$ o; f; ?) u( Z, QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

/ q* X! V" h6 C" \8 y. Q! b/ A

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

  X" Q2 J2 z2 W" c