MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
9 n- Z9 a: L, u* D: X) M- v6 ?input mcasp_ahclkx,
3 u" M" g' `4 Y) R  @input mcasp_aclkx,
input axr0,
* O) i9 f; d* U- Q* O
2 [9 b0 `- x2 x8 d: goutput mcasp_afsr,
" Y# I6 R* D, _! Y( a5 Noutput mcasp_ahclkr,
output mcasp_aclkr,
3 f& d8 F6 O3 b+ joutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

& M& d9 {* p5 @1 y6 Q

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" E' l2 I+ b1 V( N1 J2 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
1 C6 Q/ l  ]7 Y6 j  n; {& b4 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* z  G3 V  d/ ^8 h* sMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 N* d6 f; G+ S; sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 H# O! V: q4 a' J: pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 ~1 [2 f0 \7 v  UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 {2 o( Z+ p' [# u  `( j0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 M- z5 M' Y7 C; V# T( s: a3 o$ |0x00, 0xFF);

# |" a$ W3 _2 C- Y# G  z& l4 b/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
) A( a3 P8 A% V& K6 F6 w: n9 |** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 q0 @) a9 j6 {: u" hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
: {* E* o" k' c, L+ g** Configure the McASP pins
7 W! ~6 O& k/ y+ i9 R** Input - Frame Sync, Clock and Serializer Rx
+ d- T2 D# o9 B$ d* L: H** Output - Serializer Tx is connected to the input of the codec
8 F  O7 I: X  z' ~8 n9 L0 u*/
( P  q# h; x3 fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
6 e  d8 y& C7 j  f4 R4 v| MCASP_PIN_AHCLKX
( Q' r( A6 \9 h1 ~) b0 n| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) c" f  a8 A0 R0 P% O- }" h' iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 ]  ]" _' n; Y2 D, C| MCASP_TX_CLKFAIL
- u# y' |0 ]4 |$ t& |9 u| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 ]7 P9 [; J  a( W. K9 Q| MCASP_RX_CLKFAIL
3 M. H9 q8 c' `| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
3 i# W1 S+ ^. ~- D1 z" g}

static void I2SDataTxRxActivate(void)
( U$ Y+ K( T8 f' V$ g! W8 |{
/* Start the clocks */
# n( _  B6 Z, m" n7 ]# \$ p7 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 Z$ y5 c5 e& {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 `" V% {- q3 M' E- [. h! HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
7 w9 t5 G3 B8 p" k/ S2 p  @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ w8 h& {  C! ]$ cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% _. m5 A7 t1 _* z* N3 r}

+ }- u" `# e& c# i9 O4 k+ n

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

: E. d8 U, N. P; g# a* }