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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: S4 N- f& z( W2 G/ ]input mcasp_ahclkx,: p L& p9 ]: `/ ^: r* H. G- Z" K" H
input mcasp_aclkx,' _" Y- L+ q- c% W) N2 _$ [
input axr0,
% `2 l' } Q; z8 J* x0 B8 C# H9 ~ S0 t( X- v
output mcasp_afsr,% L0 Q5 d; }2 g; `& ~; @. P! \$ M
output mcasp_ahclkr,. {/ O7 t% \9 y5 [5 E6 ?
output mcasp_aclkr,
: ^) J- _! k: b9 Z; a9 h5 z5 doutput axr1,
$ Y1 S6 A2 @! m0 t5 V3 Q+ K assign mcasp_afsr = mcasp_afsx;% l0 V7 v, m- E- i; w9 ?$ l
assign mcasp_aclkr = mcasp_aclkx;) ?1 _' o. a, j2 q5 B8 M! B; V7 q
assign mcasp_ahclkr = mcasp_ahclkx;
4 f2 r7 M5 j+ g/ bassign axr1 = axr0;
3 ~3 B+ s1 c# U9 T9 S, y1 H3 d
! b! N; Y* @2 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) N5 H- y* J! l$ f7 L
static void McASPI2SConfigure(void)
& a" t( d8 @$ Q1 ]0 h{
7 p! D, @9 b3 o5 @' L# c. }' J& gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! w* j" F$ O9 W+ _3 U7 H+ v& u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% n9 C; Z; d, j2 l' T, w0 W% G; K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 ]. t9 f. ?9 E" {9 T9 Q3 D+ J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- ]' h$ O3 H. W$ i l; b# F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: n, s6 w8 Y0 b- [MCASP_RX_MODE_DMA);
8 N. \5 m/ q6 t( g, r5 ]; D# w. k( tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 E7 t' R# l0 e# ~( Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 [# A G' Q' N/ @9 d9 B# o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 ~- n. @; {$ D/ `* o) j) NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) [) L2 |: J {# G- n5 |& E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ ~( e; ^0 L5 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 n S: k6 }- p# `: d# `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; z7 C/ c# q9 f i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( X; t, I; [. ~- _: sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. b# X% q7 y9 l# Y" I0 t0 ?
0x00, 0xFF); /* configure the clock for transmitter */2 z0 c4 ^& d* A6 f- }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ q" x/ q$ j: m! r2 w, O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! C: p! r/ G" Y4 s: V! R9 M0 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: J5 V( r! ^( o4 Z& r1 K- Y6 b0x00, 0xFF);1 M: p ~! F; S' h/ n0 g3 {8 A- j
% X! U1 o- l' q$ M" P8 m; x4 S
/* Enable synchronization of RX and TX sections */ ?* _2 ^7 ~& [. e9 K2 j) R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, V) P2 H k# H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 h( k2 v& _. I" K9 pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" x2 g/ _ L: q. _6 K
** Set the serializers, Currently only one serializer is set as8 {& b% k6 f5 u: v
** transmitter and one serializer as receiver.
( M7 _' `% G- P) B*/" T0 N Q0 e3 v0 h# Z! O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- x/ V- o4 m) P" m" Q2 v' ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 i: q# |% J8 e3 C** Configure the McASP pins - ~& P$ g* T+ D. Q+ p! V! {
** Input - Frame Sync, Clock and Serializer Rx
( \0 y. |: @7 ~** Output - Serializer Tx is connected to the input of the codec
9 L9 T( @$ b3 J, Q A5 e*/
6 l* [8 r& y4 H: Y1 j. V4 h6 nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; I; P& | V! ~$ k" S- ~& g0 [6 \% F) ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 p( L7 W) a k' F5 V0 A7 W0 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 F. f J8 s/ s( y
| MCASP_PIN_ACLKX
- j' y* u; Q/ t- C% Z| MCASP_PIN_AHCLKX
& H$ I0 w+ W; U, v+ o) L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 c3 @3 Z6 l6 L7 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 g! f& |; e7 ]* @. t. L| MCASP_TX_CLKFAIL
5 c2 X. ]+ t* E9 p9 w| MCASP_TX_SYNCERROR
! K, F- t' e9 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! ~! g; `5 U5 G" p| MCASP_RX_CLKFAIL7 j' T5 {! Y) L
| MCASP_RX_SYNCERROR . s' D+ U8 z8 ~; \* w0 Y
| MCASP_RX_OVERRUN);# _8 g- t& ^' G2 m; U
} static void I2SDataTxRxActivate(void)( o% E6 A4 i1 v1 E2 `
{
4 E9 W2 e- e, e. q1 r' Y8 S4 I/* Start the clocks */: j& ~9 B3 Q9 E9 b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ C$ S; [) P: j* p5 IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 U9 o7 b( z0 b0 gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( v# p, `( q/ U& @0 I, |# eEDMA3_TRIG_MODE_EVENT);" k$ V, O! A2 Q" c* P) h& O+ Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * g% Q3 H" \# n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 o! V2 o+ X- i/ y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( J6 W3 v/ E, p4 g3 S( GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ e7 N, p' a& t- _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. i5 C7 \; d* {; U( y3 N! G3 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, N# e; F* V3 n5 Q0 c; }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 X; K, x7 C, R# |& H2 ?* _" }
} e# {* {" C; b9 y0 O. x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! z! c9 H. m) F1 q+ v
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