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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: O: Z4 A1 @' `2 }/ O: Winput mcasp_ahclkx,7 ?7 {( _/ A5 H
input mcasp_aclkx,
1 w" l5 C" W! s* j$ e. yinput axr0,
: e) V$ l* s1 T# k$ ]6 L* {* R- g, C8 u8 D2 |
output mcasp_afsr,
/ Y4 }$ ?6 e# }) e; ooutput mcasp_ahclkr,
; W l# ^2 H$ joutput mcasp_aclkr,
( q6 w4 y* V; P1 }* L3 Doutput axr1,
# w1 w7 ` E. H assign mcasp_afsr = mcasp_afsx;' P6 V6 a" O1 i" {8 N2 X0 P( Q$ B
assign mcasp_aclkr = mcasp_aclkx;7 A# [8 R# ^ {6 ~. B# g8 n
assign mcasp_ahclkr = mcasp_ahclkx;
" Y, v- p: H$ M/ G# ?assign axr1 = axr0;
9 b# l7 X7 {0 r" p+ b/ _" Z9 a7 i+ z; [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 G0 \& E; ~) v7 R" \5 }, nstatic void McASPI2SConfigure(void)
1 r3 D9 b0 t: ~1 i0 g8 l3 y{
7 _+ b$ b& j* K, Y6 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; \$ R0 D# F( c- d+ d: h- F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; b8 o. M- V) c: O; _+ P2 pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ t/ w1 ?& Y4 ]& t1 d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 E# ~, W" s* W& K5 I6 ^ `/ u5 M$ cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( l" m- ~/ C6 s0 n
MCASP_RX_MODE_DMA);( F/ |( T$ a k& q, I& \, K( ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% b! f2 ?5 ~( i: n. N" V+ I k9 n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 Z3 d6 K8 t5 q3 K R% b M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 u j$ Y8 S: p0 e$ i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! I6 S x) |4 U. d' D" v5 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 g8 ]% h- m M' p, ?8 w7 H- B1 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 c4 b' O, l- o- }/ @- l' T3 J0 j' E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! s/ ^& p( B5 {: D0 h- @- d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & O' G, f) N, o: v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 b9 E* I1 E% w2 J+ M6 _
0x00, 0xFF); /* configure the clock for transmitter */
) N% Q# V/ {. I/ qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" x, K3 r& U5 @5 f( T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " A7 p: s- Z b/ a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 ~; q) h1 L0 r9 L m( R+ ^4 M0 h
0x00, 0xFF);& T3 {+ q: L" n% w
9 P2 m' I+ X7 q, R+ B% ~/ B' s5 G
/* Enable synchronization of RX and TX sections */ : D& q; R" G7 F8 ^. z# b E. q& e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 h- \0 z+ v4 U/ l& {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ H3 B. b- \4 j* { x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 m! I% D) N* {1 v% P6 R* [** Set the serializers, Currently only one serializer is set as
( E$ F3 y$ A$ R' y** transmitter and one serializer as receiver.
' a& [- i& C3 J: ~- f7 ^& s" s9 |*/ I. x4 o4 j/ `6 q& [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( C+ I; E) ~. S0 f/ Z( X5 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: _6 e1 H' p8 ` l; t
** Configure the McASP pins
+ s: ^1 ^+ y$ \0 B** Input - Frame Sync, Clock and Serializer Rx
. }2 j/ o" O! ^9 [, k/ m** Output - Serializer Tx is connected to the input of the codec 5 E8 [+ v+ G5 x! l! }+ `
*/8 s/ H% `5 Z7 q b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- G, Z# `0 a5 |9 ^0 J3 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; y' K) S: _9 s$ F1 p" T: ^. \" {- ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 g9 U. H) l, d! z9 J; ?5 |3 C, T) n' ~4 V| MCASP_PIN_ACLKX
1 _/ O2 w9 a( V- t7 z9 ^| MCASP_PIN_AHCLKX' [7 T% @- A% l, P* V. x5 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ `- o6 b: J- T" X) L: NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; a1 B1 V# v6 r# i" D( v| MCASP_TX_CLKFAIL 0 p: X K! a3 p, d5 R, M3 e
| MCASP_TX_SYNCERROR
: x' b! y& S i) [3 w- t, i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ U' a5 x$ l0 N( y' h/ b( x| MCASP_RX_CLKFAIL
, e/ H2 x. q8 ]; W4 c| MCASP_RX_SYNCERROR 2 _: O' H2 ]8 ]1 u$ B ~8 Y
| MCASP_RX_OVERRUN);
" o2 t$ D) B6 I4 N' B2 W+ l} static void I2SDataTxRxActivate(void)6 ^+ L9 ]4 j$ f: c) N$ n# f
{
& [% z) m! [. b/* Start the clocks */( `& ^' d7 Z$ A, C) b9 Y; }3 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 b5 B. Y" s' z$ QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 o6 n- {; P- e5 C9 Z$ t1 ]) j# WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
R/ U$ D2 ~6 B( B: o/ T' WEDMA3_TRIG_MODE_EVENT);
/ s0 t1 m6 u+ JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ a, G5 |9 R1 R% A4 ~, d& Q. i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ]* S, U( m/ G- F7 ~' O0 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 m$ R0 a% `# {4 Z: {( _/ mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: \! G* V) c% q5 C% r1 E* q7 D/ B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* `8 |4 w7 Q% c$ qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. |+ M5 x: z8 a7 o5 J4 c+ S# V3 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 N* V, o! b5 ]4 X3 ]5 B+ ~5 S}
' u! q t5 j% ~7 Y" T8 ^) k. r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 I; Z# F1 H) Y4 U; s- b/ Z
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