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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, J& z/ M6 U$ L4 }2 ^8 ninput mcasp_ahclkx,5 a2 H. P$ h/ u8 {* d7 \; M V
input mcasp_aclkx,
+ [5 T/ \1 k" H( X9 hinput axr0,
, E2 O. M4 a$ p8 ^0 _& N Q1 C9 L1 T! m( L! D& V; T5 x
output mcasp_afsr,
2 O; {' m, @) M4 Z4 E$ a' V; f% loutput mcasp_ahclkr,
( b7 c6 A. l7 s$ J+ T) x, woutput mcasp_aclkr,
- z, }2 B* Z0 N7 W% v# xoutput axr1,) a8 m4 d) a: q: E( W4 z" D0 y
assign mcasp_afsr = mcasp_afsx;
1 m9 S% a+ t. s* Sassign mcasp_aclkr = mcasp_aclkx;* [) d& |' s, i& F7 H4 [* \
assign mcasp_ahclkr = mcasp_ahclkx;5 y1 J! u* I" n# ]. K c
assign axr1 = axr0;
9 j0 `" _# K- O8 d% V
' K! U8 `1 j" W% J# P& Y2 J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # [- g! f& A: n5 s
static void McASPI2SConfigure(void)
9 ?; ~; j* C. K; e9 a{
( x W$ P0 I( K0 ]2 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& n3 C( G! [' p* Q1 q" [$ C. F% X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: X5 I, `: J; {; p* y% d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# e. A, ] f+ F; Z- _: WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 }5 D3 s: U& C) E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t2 D7 a8 f. m- _
MCASP_RX_MODE_DMA);0 D8 k" N: W0 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 n# A5 A- w: a. }! ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 h7 F; U- _$ z3 U) Z2 x7 v# B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' c; A- t9 }5 A& m- M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 t- i" k5 ^% {3 ]/ [* F% YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 _1 ~1 p0 ?* l/ u- E2 Y) M6 ^5 T0 J- `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 U# [' K, m9 |3 xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- p2 W% h8 X8 j& E$ f, U# gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 T2 ^: S9 A0 g2 M4 k" Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) S. T3 o7 y* z
0x00, 0xFF); /* configure the clock for transmitter */- I. ^* e1 t+ Q9 x- ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 n( K0 k0 P2 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 p% Q! g3 S% |# B6 {9 y7 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ H1 g# k4 o c. L$ [+ E/ o( C5 Q5 q8 u
0x00, 0xFF);
2 N# y$ ?, F# Y8 ^& ^$ d+ l' [4 J) U3 m' A w" o
/* Enable synchronization of RX and TX sections */
% [% K2 ~1 T$ M1 d# ]0 N( v) N' XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 M2 L2 X8 ^, uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 S" Y( r$ N h2 j1 h7 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( j$ ^5 d) G& N2 D5 X
** Set the serializers, Currently only one serializer is set as* T/ ]% g+ |' T3 M) w
** transmitter and one serializer as receiver.4 r" n, A( k" C0 \# X9 w
*/
/ ?2 Y; e; s' a ]% D7 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 r; i7 [8 A) @3 n1 T5 |0 a; UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' R8 v$ a1 ^4 S8 r** Configure the McASP pins 3 D6 }" `4 ~! ^0 H* E7 I2 o0 q& c
** Input - Frame Sync, Clock and Serializer Rx
) {2 L* k: H& X" a7 b3 i' {** Output - Serializer Tx is connected to the input of the codec
+ D' e h/ T0 ]* P0 b8 W9 l*/
( K( Z% P1 R0 z3 x4 E4 r4 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 R" }' a- ~' n% ^ r# CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: s3 @5 ^4 M' ~: r |2 v0 x7 i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 S' h2 U0 \! v) q) w: r& ?' |8 G| MCASP_PIN_ACLKX& |/ Y+ H( U1 U% j) p2 K- g
| MCASP_PIN_AHCLKX
L7 j5 Z2 o' w* _& }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) V1 [, L7 V& j( r% H" ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. a, z2 u1 `; |, K& d| MCASP_TX_CLKFAIL ; ? i& a( j6 M; _, e
| MCASP_TX_SYNCERROR) T Q9 x) P( a9 G4 V9 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 N8 e7 f0 I7 Z+ }| MCASP_RX_CLKFAIL$ c! u( o0 n3 Y$ G( I
| MCASP_RX_SYNCERROR
* ]& f; L! b( h8 Z| MCASP_RX_OVERRUN);
1 D6 I0 ], n. A9 S} static void I2SDataTxRxActivate(void)
/ f+ ]! k: V8 _9 m# Y{
3 _- R, E3 |9 l4 \# M/* Start the clocks */' b7 h4 Y# u4 a3 q$ u3 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ c& Q; J' b' b4 H8 E# XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* V+ {6 L! Y8 X/ U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 [8 d! q( K& j |% @EDMA3_TRIG_MODE_EVENT);$ R+ f- Z q3 C, `* @: Q* F! N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & K. _& Z2 C( X" u! s+ v8 G3 y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 c7 Z. h ]/ `$ i3 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 u+ U: d' j1 W/ j/ n3 bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 \$ c. l* b! k( ~5 Z" w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# O y" A7 ~! U, K/ KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! a8 w" |8 X& @: K4 D! L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# R, u( r, S& k6 m$ M6 M
} . r3 p5 }8 s3 I. A/ a+ o' g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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