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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ H# h5 M" y- G3 {5 [input mcasp_ahclkx,
2 q c. N8 _* ]2 R7 p* e/ U' linput mcasp_aclkx,
1 e( i9 X2 j4 e1 E0 kinput axr0,, d$ J% T6 @ u) h, l: o
" ~5 L, J' h6 O- _2 goutput mcasp_afsr,/ C& b: E8 C R3 `# W6 g6 Q7 ]
output mcasp_ahclkr,2 @( V' G# N1 |8 T# P, M0 i" l
output mcasp_aclkr,
- ^2 p9 |! D8 _& woutput axr1,
M8 u2 h8 I- u' ^* y; a assign mcasp_afsr = mcasp_afsx;" D: F" ]' i, n
assign mcasp_aclkr = mcasp_aclkx;; v- }( Y8 |" ]
assign mcasp_ahclkr = mcasp_ahclkx;
5 l1 `8 J$ ~$ F: i. a: I& {assign axr1 = axr0;
# L# Q v& i; z, T+ x$ r+ V
/ K; k0 {) r/ |0 @: J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% l& _% ?% a& G- a$ Nstatic void McASPI2SConfigure(void)) S; o% s* T1 S) t' x+ p1 k. C5 T
{
" I3 H; @' h) t$ NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 S3 ^, h, f5 }; W( o2 C5 x8 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* P, m ]) {7 M4 b( y# y8 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: j' T( x% i6 O& N5 x7 E6 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 P) Q9 j( h/ E, r# e$ b7 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, o5 N7 c0 S A# m
MCASP_RX_MODE_DMA);
: f$ h. v8 c y$ U: l) ~% P0 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) o3 Z, M: O3 l: o) nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ @ W! i: J" v5 }1 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ s J& h+ X0 C5 D Q4 N# q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' X4 I; e H- G( u( z1 [5 T. _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) ?! r3 H- A, O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: G7 {! U' i# p( l& LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! h% y+ G( _. }0 p, Y6 @# u. PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . v# l( N. X: R- U- ^7 s% N. Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) x( x# u% P$ A- q8 {
0x00, 0xFF); /* configure the clock for transmitter */
% s: M9 Y" G( a$ Y$ R. LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: `. P6 ]9 J3 O: q( u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " }! C8 J2 v4 X a9 \5 v d% x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 \: R% ^% W2 W: y2 X0x00, 0xFF);3 k2 }8 F. S! l
& o& k' T }8 `/ S$ B
/* Enable synchronization of RX and TX sections */
o6 c7 c( [9 n+ z% B' }( V5 wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* a% N/ M% W8 `8 P* [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 O, d2 A& V* P4 B% _( h! n ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. S% r& } b" z- k$ P- e0 A** Set the serializers, Currently only one serializer is set as
0 g/ G3 j% ^2 J** transmitter and one serializer as receiver.: x) u7 }8 M, y
*/
- U. k% F6 |6 X& |$ qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 R* r8 y s c+ f" w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( h( r. [1 j/ x1 {2 ^% P2 m. j1 L/ M** Configure the McASP pins
W o! Y( J; S9 D** Input - Frame Sync, Clock and Serializer Rx
' j8 q ?0 t% g8 _. y** Output - Serializer Tx is connected to the input of the codec , E6 E' R+ T2 x' [# w+ [8 s
*/
0 ^6 q# k3 h' F8 q, }' S: cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 ]' ^% H+ D; n) G }" ?! K' |) B. A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, h" o: s. \; \/ tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 P9 ]! v/ G- X3 m| MCASP_PIN_ACLKX
& t3 t" |8 }, s. j| MCASP_PIN_AHCLKX. {. w- E& }' ~9 i9 g/ m) U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 r! I) H. D% B8 x% K4 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' l8 D, W- B, [4 E' H| MCASP_TX_CLKFAIL ' s2 B) e& ?8 f/ a Y I
| MCASP_TX_SYNCERROR+ x9 Q7 o) ~ c K# Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 b' Y9 d- O' n| MCASP_RX_CLKFAIL
( h5 Z7 C+ v1 c% n, i8 r| MCASP_RX_SYNCERROR
# W" ^0 Z/ L7 t2 t$ I% a/ Z| MCASP_RX_OVERRUN);3 y; i. D) s( S1 {* I* s! `8 l( J: v
} static void I2SDataTxRxActivate(void)' y6 V# O5 F0 y6 G0 B! ]$ Y/ x
{
/ n$ i$ t& n; l4 B( `4 R/* Start the clocks */7 ~2 k4 F0 R5 t# m0 p* T5 v! o4 o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ z, B: T3 D! a3 t* r: b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. n4 I# [1 R1 ?' a nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, e( K, l2 C( y( }5 U( R% SEDMA3_TRIG_MODE_EVENT);' Y, \6 ?# k3 T2 _6 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! [. |' k& }$ b$ _ A! K. p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" W+ v1 U" {5 M3 n8 O% N: u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! E9 H$ V" O7 ~& s- d+ f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 Y1 v! X0 V6 q# |+ }7 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% E( m0 E6 N$ C/ A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: L8 Z$ K+ {7 [. B* QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 b2 o5 |* d# E% B1 c. i}
% P* f/ [- \& V3 n) L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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