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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 J9 G1 T) p. N
input mcasp_ahclkx,
" g. [, n* d* C, w# o: linput mcasp_aclkx,. W `' z) A! H5 J* S
input axr0,
) E v5 t+ } X0 J2 u: a5 T3 A: d; {3 ]9 P- \/ J
output mcasp_afsr,- w: h+ i0 g( N$ [# U8 \2 V
output mcasp_ahclkr,5 _. P7 p/ G- `, {0 m9 R) w
output mcasp_aclkr,6 j/ m$ f* ]7 L: d
output axr1,' v* `' l' _% J' X9 ~
assign mcasp_afsr = mcasp_afsx;
- |. Y, ~/ u) p: X8 h8 zassign mcasp_aclkr = mcasp_aclkx;% n7 O# y8 \! `$ [% q; u) E
assign mcasp_ahclkr = mcasp_ahclkx;
; l. T$ \4 O% p; Nassign axr1 = axr0; $ H( N1 o: d7 V1 m& `: ], D
: `. {9 }8 x" I; @( z' X3 `" Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% G' ?! O5 j( F4 d% pstatic void McASPI2SConfigure(void)
9 D& u3 a4 U6 `! {/ e{
* u, w: x! {, Z- E- OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 P+ f' j0 P% _) D. A. LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% M2 }& o# U) x F7 B$ a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' l- `* a b. k, }6 o mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: N# e' _" ~% S% q1 a1 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 y8 e0 D7 {7 [: P5 v( ?# w) T
MCASP_RX_MODE_DMA);& X) N# L# H1 ]) u/ ~& b* G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," H& x/ V3 I" y. a4 p& P$ y" L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) M K2 A {7 Y. B* q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 b" A5 H" z- S# t4 T2 h& BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 b( L0 Y1 | P3 I9 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * i' l* s1 c* g' O- V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 E; m! I( C- G; B/ ?6 {5 ~4 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 J- l6 _; R& ]+ j+ S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; _3 t9 f& F( t2 G* Z/ a l: ?9 k$ ~5 _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 W* u2 W+ X9 ]* T
0x00, 0xFF); /* configure the clock for transmitter */5 O' ` Y1 T, S9 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: K+ W- M; k; n1 H& Q; QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 F% L: \; `* k) ~; _7 _! M& O. n+ T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# B# {+ ]8 E7 x- m2 x0 N0x00, 0xFF);
& N. [6 H* n( ~2 j. J C1 D* f2 x
* z0 R+ G. r7 I; S( u/* Enable synchronization of RX and TX sections */
# d* b# D; ]8 ? }! }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 [5 j2 s' q7 x9 g' k) n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 O% U$ v* j& _8 B& Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: B8 [: d& T8 ?& @, O0 ^: H# P) y** Set the serializers, Currently only one serializer is set as. ^0 F. _& G; f# N0 U! |
** transmitter and one serializer as receiver.
; m5 q7 O! [- L* M*/6 d4 q* W8 l, R* P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 e' \" M3 J- _( T1 ]8 q Y4 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! O. ?* W1 {4 y' x
** Configure the McASP pins " K& I4 @3 B1 T) L% y* G3 F
** Input - Frame Sync, Clock and Serializer Rx" \- p* Q' x; t) J H" t
** Output - Serializer Tx is connected to the input of the codec
/ k5 X4 Q' }% S6 r5 B' D& n) ]*/# Q( ?1 {4 T- A$ {8 e+ C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ m3 X0 ~2 b. t: h: X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 r$ X0 S8 R$ r9 [* B1 A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( @# \/ }) l9 _( ^' O# N! |9 A| MCASP_PIN_ACLKX5 [; T) ?4 u3 _9 y5 O& @
| MCASP_PIN_AHCLKX
/ j5 F7 }9 n4 a/ F7 h! q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 {2 v6 j" ?4 U0 Q' Q* x5 ?2 g3 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 x/ w& U/ U. F: T- p& g5 j, u| MCASP_TX_CLKFAIL 5 X( W! J" u4 ^) P( Y( d) e
| MCASP_TX_SYNCERROR3 L+ E& p. e0 X6 o c6 N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" `$ B- g+ T5 y, ?% }& ~| MCASP_RX_CLKFAIL
8 l' I9 Q1 ?" O7 w p| MCASP_RX_SYNCERROR
. P4 J$ R2 f, L2 C| MCASP_RX_OVERRUN);
+ f$ p6 i% ~( x) a2 U; C: J} static void I2SDataTxRxActivate(void)
; {( U& P- N" e. B{
( \/ j( ^/ U1 B. G1 N7 Q# A6 m( M/* Start the clocks */" n: M& q( W$ ], e9 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" e8 x& q8 i# c5 i6 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 C3 Z& k& r+ J/ |* i1 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# u# \: m) f9 w# j; x! MEDMA3_TRIG_MODE_EVENT); ?4 v6 e% g! M( G* p5 q7 D+ P. \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: V5 B o0 C& E" i+ S/ _* \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. Q" E% r8 I3 f+ S: _4 W n- s( ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( Q6 Z2 M! b0 r- _; dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( t3 G/ }5 o$ k& Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. g) s% p) |1 y" W8 X# j0 I# RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% b. J- [2 X* o1 U* y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ ?# [- ^- {3 _. k( ?}
9 g8 L% ?7 z0 [6 O# U! W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 D, ~2 }1 b2 d& ^# O( Y& d, u" [% f |