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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 ^; f) K+ w3 z9 g" U
input mcasp_ahclkx,
2 M0 @. Z2 m% w/ y. q5 z5 J* einput mcasp_aclkx,
0 I! {/ I+ K1 P2 o _0 Binput axr0,
) X# r7 W) p6 p! Y
8 N7 x& T8 {4 v. g8 ]output mcasp_afsr,
H. P! S( |8 m2 B" D6 Routput mcasp_ahclkr,
! v4 R( \ M+ H) u# r2 e( p/ P7 Toutput mcasp_aclkr,
- F. f# D7 i" `6 k5 doutput axr1,
' Z. k. F0 ~6 Y p* k) ? assign mcasp_afsr = mcasp_afsx;. D8 o9 e; W; O/ M3 T/ z
assign mcasp_aclkr = mcasp_aclkx;+ v, [' r1 Y1 V% h* P8 R
assign mcasp_ahclkr = mcasp_ahclkx;
! X9 d* V' e' c1 iassign axr1 = axr0; 0 [8 A. O1 m$ J
' I/ B3 T5 i( `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 e. h- L5 l. |' @& A1 ustatic void McASPI2SConfigure(void)) z2 [: w/ ^% _7 |# r J/ |0 y
{8 ^8 `, s9 j0 H2 Z. O" J! U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- r0 t- S! f& T) V) N4 y0 H8 R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" k1 S4 _7 r' e+ N8 F, KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
U2 `6 H8 q& T$ @( o# M& FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 K3 Y' t3 g0 j2 D. ]; s* BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: Y, Q& h/ q) z' m }
MCASP_RX_MODE_DMA);, c) [- L7 }: y, x. s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* k6 ]" E# R% ?1 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ m% V2 d$ q9 C/ r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) [1 q I+ B! f0 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 I- F8 T0 L" l/ FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 w5 y/ R. D5 i& C/ fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& K1 X$ p. i( r, r- K' M# Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, D; r. @' }: h" L! sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' U6 s4 o6 E) |/ qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 k7 A8 A4 ?* N- O% U' Y
0x00, 0xFF); /* configure the clock for transmitter */
! V/ ]" M# {2 x& B7 d. o8 e/ cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: ~, B7 a: T% t. x0 E" o0 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& b4 @; c. C4 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 D9 N$ d- E7 H0 C0 s
0x00, 0xFF);
/ I0 l8 G1 ?8 S, b0 ?4 L7 \
, n4 }* U+ a) i- f/* Enable synchronization of RX and TX sections */
4 Y8 q# E- m' J1 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 e/ `9 r" g6 B0 m9 ^# `6 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 @0 Y. I7 o. V) g/ wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& v. y, X( A1 ^: e: v** Set the serializers, Currently only one serializer is set as
2 W6 y( I7 n6 P- i8 _2 p** transmitter and one serializer as receiver.. p2 b/ y2 ]/ j% p7 l, p) m9 q
*/
& J* ]- ]) B' X# o, ?/ pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ t9 l( e- |5 s# h- Y. Z3 y% k9 GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ]9 d$ f+ ]9 @** Configure the McASP pins
/ F7 [! a; d( a5 Z** Input - Frame Sync, Clock and Serializer Rx8 U, X( F3 K% y: ?
** Output - Serializer Tx is connected to the input of the codec
# I' i) |) `4 e$ M0 [*/
* }# P v, T3 X4 m, A( ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& a) H% W) V0 Y" Y+ t% S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); n, T( Q: ?) y5 E( z; k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 m; e, V4 l9 M| MCASP_PIN_ACLKX
" `) r' e9 d! _- A| MCASP_PIN_AHCLKX) \, I7 X, ]9 N% P3 M) ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 m9 ~; f3 n, k2 P8 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ e$ t( {2 q6 `9 H" H8 _; `* X
| MCASP_TX_CLKFAIL
! J+ ?) j; ?3 |! ]: E| MCASP_TX_SYNCERROR: U2 c$ w2 s( k w- T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 m+ b* e' b8 L% J* ~
| MCASP_RX_CLKFAIL& o7 d& {! J j
| MCASP_RX_SYNCERROR * N5 r6 R) G) z3 l, N: R) [
| MCASP_RX_OVERRUN);9 B% N, H9 ^/ X/ }. N3 n
} static void I2SDataTxRxActivate(void)5 V: [& |/ u7 H* C: u8 l1 [
{
/ x/ v$ }5 `8 y/* Start the clocks */
, k3 ^8 ]6 h% l0 ^/ W" I7 t, WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ H4 b- H, A. o UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( |* [4 j. v+ J; i* o9 c |. HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," N' M7 ?) R8 Y9 D! Q4 j
EDMA3_TRIG_MODE_EVENT);4 l' Y( o, n! [' D: t" I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % I& Q9 N6 u7 q$ ~( ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 V7 O' y Y& E# ]9 _# y EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 f! b/ v. z8 y' |+ FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* m0 k8 F0 W6 k$ E6 k- \# }& qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 w+ X# i, t# d( a" X+ H# j- MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' K r: Z! r% G$ V7 r- }1 Q# X& n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* s7 C: u0 V/ A1 P) N6 i# H/ v
} 2 D$ k6 O- f3 |( W0 k' ]$ i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + c. T4 V5 }" F
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