MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
: O/ s* [" }% E: Q% Xinput mcasp_ahclkx,
input mcasp_aclkx,
' d6 j. [0 s% V" a2 winput axr0,
# L' k1 E, E8 g! v- B9 g. g
  e% }' @: w+ J5 ]6 [output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
, d' \1 B0 a+ G: sassign mcasp_ahclkr = mcasp_ahclkx;
% F  Y. w. p2 F; o* N% a. ~0 G- wassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
4 v. v# @! j4 A4 m5 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, @/ K$ d& n, I+ h+ z$ g" o# B& gMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
% a4 P# s- N' f- v$ g) QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. E; J1 i" g: B2 I( V- BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
/ _3 V4 d" I0 W' M6 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. z) D2 t, s8 p) {' ZMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ o/ ~$ F- k" W# P4 F' O% R, p2 KMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ M. a4 m; t3 f2 u; i% \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 T# e: X+ Z4 X8 o; IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 s: ^6 W! D9 `$ d0x00, 0xFF);

/* configure the clock for transmitter */
% P* f: O) ?' E1 _6 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! m9 p) W! T, v( e- m# p2 d5 X) zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 R0 \4 P4 j+ o" L3 j0x00, 0xFF);
8 \. U8 m. N' J9 T5 u: v  ?
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 Z% S3 P/ R/ G4 ~8 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# h+ V1 y* G* R3 S/ n& H& H2 I; x0 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
. a* F+ d% |2 {; k% [  Y** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
  L! [5 h  t9 Z+ `" L6 R*/
0 D# b- h$ Z% VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 f( b$ _) z5 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
" C/ a: B, ]& F( B; @*/
9 s% K9 `: R+ u3 s3 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 ~8 _) s  ?1 ^9 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ j  K1 C# J6 k  A| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 l" Q( j4 R& z% |, h| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- ^  u7 i/ m7 y5 V1 g| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
0 D, o. ~0 Q7 w| MCASP_RX_OVERRUN);
6 d3 @$ ?4 P' }}

static void I2SDataTxRxActivate(void)
{
* U% a' B3 I) b! M3 a/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 U4 S' o2 g# R( X5 H/ ?EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 C+ s% R# N  l% T# v$ OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
8 F, [, @4 T3 P$ ?4 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" u( [5 @% m, x2 P* l3 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 G! G/ ]% M1 E( I4 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

: F! P2 f+ X; U

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.