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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 i* r; {) ~( F3 Y0 I3 x. }* W
input mcasp_ahclkx,9 h7 h! s4 ?8 i, Z- }' {
input mcasp_aclkx,1 \: b! u; q. L) O) s
input axr0,
+ w+ M6 @9 G, N" Q( A: j
6 N2 y; V4 x/ d& v0 J# C, aoutput mcasp_afsr,2 s( s1 U1 k+ M9 _# W0 `1 Q
output mcasp_ahclkr,, Z) w4 D% v' g' ^/ d% f$ {
output mcasp_aclkr,* v1 v. {" C8 _2 u4 q# N
output axr1,
) V; j q* ^8 y0 _ assign mcasp_afsr = mcasp_afsx;- A+ ?+ |8 C" K
assign mcasp_aclkr = mcasp_aclkx;) E! U* Q# M+ U+ q' m3 M7 f
assign mcasp_ahclkr = mcasp_ahclkx;' r6 k6 F# K O7 }1 d: O8 l
assign axr1 = axr0;
! C) n4 l, D# P8 M, j: S; d( p
$ G( E+ S* h: }9 t. Q i3 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( {; [# T( v9 N! S, Z/ istatic void McASPI2SConfigure(void)
$ Q# u0 w2 ~0 B7 d( ?# h{ v: B4 E) D! ^+ i5 M, M) w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! [) T! f. u5 Q6 y; {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, `% J# E* l5 l) o yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 j, r4 S( y& VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' C5 X9 f1 [+ a( A3 t& M" lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. h6 S+ s: X% X" h& zMCASP_RX_MODE_DMA);. t1 W0 p( F1 y; f) h& @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, Y% T: P6 e) {& `0 l+ DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& {% i, s& Z& L {+ U: ~7 \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & ^; R m7 i; b. | R9 W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ B* H2 {# Z: W! a2 G5 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# c, P/ C; _5 v9 e5 M7 K i. H' WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# {( p. ]3 m5 d$ p Z4 F4 A; lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 V4 _" o/ I' v2 R# V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 ?/ \4 B. L/ [8 s& p }, ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," ~$ D4 l o4 [6 A
0x00, 0xFF); /* configure the clock for transmitter */
. h3 X C* O- h( Y C- HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 J+ B5 R% Y0 N2 H( B9 J, z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' b5 R: v. l& @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, C' z' d) \, ?$ l# N0x00, 0xFF);! N& \8 M, W+ ^/ C
/ C! M( t7 ]% u0 Y5 e/ B4 J' t! h/* Enable synchronization of RX and TX sections */
: k, s6 y Y/ i+ c# d1 X! [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 e( a5 k; ? F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* H; B1 k: b5 |" H% d" y& b0 q, Q4 ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 N. r0 A& O' G5 w0 `( {/ r. u
** Set the serializers, Currently only one serializer is set as
( ]5 y& ? W3 f& @** transmitter and one serializer as receiver.
8 n, m2 h3 Z4 z4 @4 A0 P& @7 b*/
( b: j$ z3 ^, {# J! ]) C5 ~" ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 T# Y6 r+ Y- @% t# N3 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 c/ J; m6 o+ ]
** Configure the McASP pins
6 \% [% |2 E# C) Y& c x** Input - Frame Sync, Clock and Serializer Rx
, V* F2 i( u1 w/ U** Output - Serializer Tx is connected to the input of the codec ! t" }3 k5 R$ b
*/
7 g$ q1 _# h1 V8 z% \7 \( ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( Z1 j0 p6 m# C" c9 h) C4 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) h9 L* l& `/ o8 n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 B# J, S1 C$ u% Z2 G
| MCASP_PIN_ACLKX
1 K% |& Q2 S0 V B' A5 J# I| MCASP_PIN_AHCLKX8 I. X" o, ?% Y; N$ k- @1 u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 g/ K9 ^& u' ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; f0 D; u: s6 K- Z
| MCASP_TX_CLKFAIL : c5 K* n) u9 ]7 }1 g" W, r
| MCASP_TX_SYNCERROR
1 v: b$ X2 \8 h5 p" u' X- s. k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" f$ Y; b5 D# L% [2 e| MCASP_RX_CLKFAIL
$ E8 j/ J8 \6 R) ?; E. I5 D| MCASP_RX_SYNCERROR
5 c% c1 N+ ~. h4 P+ y| MCASP_RX_OVERRUN);, }% o- p1 B/ Q5 s$ D1 `
} static void I2SDataTxRxActivate(void); T* ^3 f! | b$ K2 G; b
{
& ]4 f- N9 b8 z/* Start the clocks */ `1 V" A9 m# q0 X; W! F8 @9 t" g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% C, A9 j+ u+ h, }( S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 `6 `, l& r6 g- J% N1 n- j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, z, p* u: y H% D$ _+ ]! F0 z) W$ b5 b
EDMA3_TRIG_MODE_EVENT);# a3 Q% l6 q1 R8 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; k( g6 s" U6 l! [& K1 K7 OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 J1 Y) W2 y3 S4 ^' q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; n5 Q W/ e' {3 {% S7 Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ l; C& C. u, k- l, e, b. q# b. x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 h1 J( B6 U6 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 _$ y |$ i) \" a$ OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& Y! o6 [7 @* z: ^, }6 j
}
) q9 h2 D2 U9 x6 D/ p0 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 s; d8 P" e, Z, y5 E! s8 o
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