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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 D: ]' _, j, s, J+ H' R
input mcasp_ahclkx,# Y& b6 A5 o6 v5 x; s/ N' f
input mcasp_aclkx,
, z" C. X5 e1 x, J+ x+ D2 ^input axr0,* e& s9 Y: j' F& R
2 E" B) `8 e/ n, ioutput mcasp_afsr,/ o, P% m" Z5 Z
output mcasp_ahclkr,' N, \5 x; D: D+ H
output mcasp_aclkr,
0 @. s5 G$ s8 {8 E: O' B6 B2 H9 Youtput axr1,
) ~: E8 q8 ^; G# _2 x assign mcasp_afsr = mcasp_afsx;
- X5 [% J$ X& Y" K" _assign mcasp_aclkr = mcasp_aclkx;. V6 f; }0 w4 b: ^
assign mcasp_ahclkr = mcasp_ahclkx;2 {+ E& o& ~9 m' T2 t: k" {
assign axr1 = axr0;
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7 v2 W5 B. @4 L4 n4 a1 T2 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# y' A8 H; `6 A( I# }static void McASPI2SConfigure(void)
) d' D) R# u4 z{( Z F H& [. K$ U) g0 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 U4 {# v) V' XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 w3 S3 l8 }! J3 K: C: A n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# v9 _7 a! {5 U; }; MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# V4 i2 w7 d/ j! C7 {) n9 S+ U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ?6 M% o- N, L" t! F
MCASP_RX_MODE_DMA);
) r! g1 Z5 H( b+ ]# f- hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# y" b4 M- {, t0 E( O4 k. hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 R$ J. o, V' U. t9 T( S; h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 C0 K0 J2 `2 i# S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& a, e4 z8 W/ b. C% _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 ^/ Y1 W4 ?: }) B$ H' A! K4 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ e4 g5 R& G% m {; y8 Z) AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 B# {1 T h$ }! X2 q$ T W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " C6 H5 F% w" s! O; g; k; P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' R" f' M7 ?0 E& {5 ~; u- Z0x00, 0xFF); /* configure the clock for transmitter */, x# y2 z% ]6 [3 {4 T! T7 _, l7 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! |6 J7 p/ w- `$ l! ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' K: R! `# U8 a2 s/ M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 q: L0 o1 l, U4 F$ f$ g
0x00, 0xFF);/ } {/ U- A3 I3 w4 h% l9 P
- ?/ x) A# y' B$ F' T/* Enable synchronization of RX and TX sections */ % t8 D. b3 U V2 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) x9 u9 m/ C' ]7 o! b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& \ l8 ?3 \ c! M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 z" K4 e) `2 P+ C1 d+ A
** Set the serializers, Currently only one serializer is set as
: N/ x) j7 q4 n3 s: r** transmitter and one serializer as receiver.) ^, G' p& z: c8 S2 b/ K
*/$ N5 \8 c, I; T$ G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; o `# Z. |4 n, s# ^5 c- {, k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, k4 T, W) k5 a T( j5 ?: J
** Configure the McASP pins
7 m. \! P& a; z6 O' i6 R( n** Input - Frame Sync, Clock and Serializer Rx
9 Q- Y$ ?; t, N% g/ s/ w- x** Output - Serializer Tx is connected to the input of the codec
' G! T# ~: L" d" H8 J& F: W" }*/
# h$ `& G4 s/ X4 R& P6 Q8 z# P \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 v6 L8 W; G9 N+ Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( W2 }5 J( u# Z, s6 bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 S% ^1 M9 _$ l: o
| MCASP_PIN_ACLKX+ G4 x( c7 D6 V. n$ c
| MCASP_PIN_AHCLKX
5 ?5 v S/ e5 T0 p' N5 }0 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 x( _1 u+ _( b# p' T1 p' F0 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! ~5 F' Z% l- ]' G| MCASP_TX_CLKFAIL
! n0 G( M' }. W7 ~4 I2 ]( H) l| MCASP_TX_SYNCERROR; s& S q5 g' S# B8 \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 ]& E5 f( \& @& Z| MCASP_RX_CLKFAIL
" l9 v5 l( r# `& f- p| MCASP_RX_SYNCERROR
- j( T0 y' w& r4 n| MCASP_RX_OVERRUN);$ t; Q7 s" `# h X, j$ I
} static void I2SDataTxRxActivate(void)& k/ E3 R0 {- s3 q9 h) H
{
+ r% j2 l6 B9 b/* Start the clocks */9 J; l1 I/ O8 W, w0 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* f# g1 h7 |( r- RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) c# g# L$ P& x5 a6 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' j1 J: J* E5 ?) f% z9 LEDMA3_TRIG_MODE_EVENT);% K4 ^2 S5 }3 @' f {1 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ] p0 s Y; ^+ \4 w1 ^7 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! \. w7 {( ]1 j. k+ {3 E/ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; F( g$ D( ]% j( O. T! V. c8 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# X! c8 q( a0 Y7 E8 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& e: p, [2 `6 U1 N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- U9 g6 R3 k# d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# X* l( g3 h+ U}
8 d. F: x( p# c( v0 P) ~* }3 i! z# f; g) j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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