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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 Y m6 @5 ?) J9 {7 h5 iinput mcasp_ahclkx,3 X: `6 W' t& Z) {0 E
input mcasp_aclkx,/ g, X3 h* Z- `) P0 i
input axr0,* e: w- Q. o' e9 q# M6 Y* H
8 d, R9 K z1 f* |output mcasp_afsr,' Z( m1 }$ a& b' D- Q' D
output mcasp_ahclkr,& v5 c3 g% O- U7 m. g+ A% a' k1 Z& [
output mcasp_aclkr,9 t6 \8 S( C! ~' {* ]* [
output axr1,) |- ?+ _9 w! i
assign mcasp_afsr = mcasp_afsx;+ F; U0 l$ r+ r$ A
assign mcasp_aclkr = mcasp_aclkx;
4 V; d; d9 p/ O" \2 x* c) Vassign mcasp_ahclkr = mcasp_ahclkx;; Y3 H& V+ u) V0 ?' n$ G6 ~3 e
assign axr1 = axr0; 4 O9 c2 E) e$ P8 ]. S" |9 j
- ]; i8 _; Q0 e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 c* ^3 j- c+ S) jstatic void McASPI2SConfigure(void), f, c2 {5 x/ _& x& ]( n1 [
{
3 T+ R/ Z9 i! k2 S) B% g2 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 A8 ]# M1 C' ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 G; U$ H6 g/ u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 ?8 G( ^2 M2 U0 d! j8 v. C3 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- S+ M% u7 ^ r8 i/ a+ o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" J5 _0 h$ g7 IMCASP_RX_MODE_DMA);( B6 P% y1 F# J C% h" H6 G- e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ V0 L6 p; ~* Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- \0 f- b& a: x: O9 kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * @6 Q7 t; K/ `2 P6 A2 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 g0 E/ @* b# d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # l! G: j6 o2 B( B7 C; U3 H( j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% j! x; W+ Q) o* b0 i; j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( C6 n9 h8 x8 F6 D3 `5 S5 @8 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 q" g: v3 x4 i% LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 _/ i7 A8 P+ S \) T0x00, 0xFF); /* configure the clock for transmitter */- r) y- S. g; C6 I3 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- ~1 m' S3 ]" P9 B& n! ` D) o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; B6 T- \8 b! D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: f3 z+ ?$ m* @7 b0x00, 0xFF);, v$ o6 m5 q+ _0 a0 J8 `
' o9 \, l( T4 h5 D9 L/ z/* Enable synchronization of RX and TX sections */ / E/ {: [' |$ ]* x1 w0 B3 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. [' C6 _: L& |0 ]% D+ nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 P" V. J5 {2 Y9 g* n# x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& f+ k3 l. D; I
** Set the serializers, Currently only one serializer is set as g0 W% q/ q3 J, Y; M
** transmitter and one serializer as receiver.( W- U/ M0 o- j9 E+ P
*/5 G3 y, k& d+ u7 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* o' \/ o0 I" c3 b0 n. j wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. u" Q* `: d& d3 E! K) U
** Configure the McASP pins
9 J" A: r/ K2 [+ L! I4 W** Input - Frame Sync, Clock and Serializer Rx q( t; r7 e# n G
** Output - Serializer Tx is connected to the input of the codec
9 j1 c ]$ ?) C) v' G \& n*/ _2 s3 n3 z0 W6 S+ `" c# t7 P3 M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- r- B; W9 h2 G- C0 T& H- fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); _5 ]" S! @% Y' Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ^( w6 M' D6 K9 v. r| MCASP_PIN_ACLKX
1 a! `1 G/ ~& u2 y- s9 d| MCASP_PIN_AHCLKX! k, M% v; o1 h) \" E: Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) r- W7 V. M4 t8 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( a' k! j+ [4 m3 R- T$ w& P" G| MCASP_TX_CLKFAIL 0 Q9 v. [5 {1 {
| MCASP_TX_SYNCERROR
8 |4 j# z: v+ m0 J& i0 x0 V, [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 x+ x. g2 ^# T1 X& g
| MCASP_RX_CLKFAIL
9 z- U0 j0 _9 {| MCASP_RX_SYNCERROR
4 `: g8 _- ` @' ^| MCASP_RX_OVERRUN);4 L8 h7 K2 [( A+ Z
} static void I2SDataTxRxActivate(void)8 }# \2 L3 ?' Z
{
& O( L" { Z/ r, o/* Start the clocks */
, K5 k* A' l( s4 u2 x* cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' E7 _) Q$ D' Z' ]$ M- Q u* H& dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! h7 A: W% K* V* fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) p# B- V# t7 f5 G7 `8 \; R
EDMA3_TRIG_MODE_EVENT);9 D' ?" W: g8 Q/ `3 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& C, u8 ]( Y& Z0 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% @+ j M$ k: Y# A5 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ o$ z O; e; Z* eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// i6 X( y5 l) H0 O" A/ w! f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ O% d# v0 e1 O ~8 ^4 X8 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 b& N0 J) o' o2 r: z# c3 ]4 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' Y& n0 {8 P- Z. ]}
" G X' m/ i: G7 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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