MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
; a5 \% O. v# Z1 D. w+ O- D5 kinput mcasp_ahclkx,
input mcasp_aclkx,
6 a* t# u) G' u; Z) Jinput axr0,
, z6 o. s4 f. V8 Q, T2 q' U
output mcasp_afsr,
output mcasp_ahclkr,
8 ~5 T8 H5 A1 [9 {7 \* @output mcasp_aclkr,
output axr1,
5 Z# V, p8 c% k3 E& K" c

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

2 Q8 ?! O2 `! _# @
1 K3 D) ]  T- A1 W5 @

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
{
6 a; c' v3 t: p: K- H  O* u0 o3 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( Z4 Z3 v7 A  d. ~+ B/ {" TMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
/ t4 P3 X) g6 ]' }; q; EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
: e" l4 K. [, Q& {  I) fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- A5 y% Y! [( NMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& u  {" s+ i( @2 i" `2 h: S. aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 R* e) B" _1 GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
' [) B; }$ P4 p) j& VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 i- @' r: z+ U1 E; V% eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 D: F" m: c4 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& N0 w1 h5 B* ^  d3 s/ g! G" |0x00, 0xFF);

5 Q5 G+ w; ^! c# [( T/* Enable synchronization of RX and TX sections */
3 h8 m# C; E' s& }! ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 L; X4 C4 V$ D8 Y$ k) r+ g# cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
  a5 ^( |& y( E** transmitter and one serializer as receiver.
*/
1 C# q4 q* I9 X) D3 e, ?" OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
8 [2 R: X2 Z  N1 C! ~** Output - Serializer Tx is connected to the input of the codec
*/
' `" U6 I' ~3 A/ J* n, BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* N& G( Y9 P, c/ ^- t! N3 H' P+ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: N- z! l9 l8 ]& `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
1 \% h6 S6 T; `' y  Z9 ~| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
$ A0 k1 i+ F/ c6 `: OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) m% \6 w2 ^/ P" g| MCASP_TX_CLKFAIL
/ Y- K/ |' t# C2 W| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! _  U1 a+ r/ V4 || MCASP_RX_CLKFAIL
2 M1 T- I/ N" ]8 C1 b# v9 e$ {% _| MCASP_RX_SYNCERROR
3 L! p7 e- I1 G4 S| MCASP_RX_OVERRUN);
! Z9 B7 p% H' A6 `" @) b}

static void I2SDataTxRxActivate(void)
{
+ y/ {0 E/ g5 a/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
3 E, J' w4 Y: Q& |9 R2 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
7 N( x. t) ~5 @  D5 ?& w9 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 ?$ P. \. r% R$ T& F; o) JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
- j, [1 F' A* J  n5 c2 c+ awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

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请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

3 [8 L" s" Q8 R; e$ w* ~; h