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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) @& B; `/ F, m0 j. l( Hinput mcasp_ahclkx,! E. z1 C+ Q! y! Z
input mcasp_aclkx,
, k5 S, J9 G# W {* [3 a" winput axr0,; a2 ]* `! t A! O4 \
+ k; } S# }- X: w
output mcasp_afsr,5 f; i! U: J+ m5 G/ t
output mcasp_ahclkr,- T$ e1 V( F! g2 I% B% e
output mcasp_aclkr,
: A% U# u0 [; @: Koutput axr1,
% W) U' E2 L! `7 [0 Z) U5 a assign mcasp_afsr = mcasp_afsx;
$ \) S/ p( M1 z& B8 T# E0 ]7 o- l6 Iassign mcasp_aclkr = mcasp_aclkx;, B7 e; k) U0 _$ d( z$ ^$ A# q" \
assign mcasp_ahclkr = mcasp_ahclkx;
) n' Z9 f$ u9 X |' C* zassign axr1 = axr0;
* B2 ]% U6 E+ {* y/ v% h! G, c$ j. I k/ A: D1 d+ h6 _6 Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 s5 f' Q+ A+ n$ L7 {, Y
static void McASPI2SConfigure(void)
/ g2 B( M0 Y! t- d6 B7 Q{
' {5 a% ^+ V0 x ]/ k6 Z" V* t+ tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( X7 O- w. X! K9 l( Y# [+ w9 q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 N- K6 c. Q( s. w7 O- `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; R+ ]7 [5 r" a" x. z* Z2 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- c1 }- N; P! _1 Q4 s# \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 s0 p0 x; D! a
MCASP_RX_MODE_DMA);
5 x* n( ^ { ^5 K$ w9 E. F' gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: T( u( L; x) J1 W* q" w& tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: x% d0 z/ \; ~; u/ jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . Z. r( U; ?+ a$ O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% }0 `* B3 O6 T" L) r" D! I. r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 ^+ c& u: E' T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) K/ g, |/ a! Y/ Z2 f0 @: JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); d; f( V5 x# w( F% i1 u( a2 v: d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! L! ?+ Q0 L' |: p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' U4 p* |, R: L+ y$ p% H' E
0x00, 0xFF); /* configure the clock for transmitter */
4 Q; m# p2 |; G CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 s4 h- Z$ W/ z: B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " a: a* L/ |9 ^; u% G% y/ W: @+ [" x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 [: R5 |2 L# L' y4 B6 }5 A% ?4 X
0x00, 0xFF);4 Y% p, A7 P' S4 E2 O
0 Z ?# D6 @, I- V1 \, p; j/* Enable synchronization of RX and TX sections */
2 L% @6 v; ~! _/ U5 P C, _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! k0 o! m% T; q* _7 ^+ H/ W( H: }" lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& \" f' l& z. m% A7 {: S! L: |2 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 M$ F7 [- ~/ P$ f$ O9 k" ]** Set the serializers, Currently only one serializer is set as
4 t' \6 L8 s) X! ~% |0 A# D** transmitter and one serializer as receiver.1 |8 i, e: Q4 |4 f/ K" }
*/
. F! C5 Y* r1 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. a8 Q+ b+ ~ G+ a4 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 _2 X3 o! p' ?. A
** Configure the McASP pins
. Q: }8 l# I z% ~** Input - Frame Sync, Clock and Serializer Rx1 s4 f9 U; y: j& b, R6 I4 H! g
** Output - Serializer Tx is connected to the input of the codec
2 E. _* W' C" _8 ^4 L*/+ n1 { E( r! b: Y! A& y' e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) S1 o) M" b+ }/ t9 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 `3 m) I0 H1 [* C0 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 Y& S& p. R( K' ]9 _( F$ K
| MCASP_PIN_ACLKX
( r' @' m) L: Y, [8 N3 H+ U9 p| MCASP_PIN_AHCLKX/ I' [1 U+ ^) l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 T4 u9 {: A7 H2 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 y! G' B" Q. d$ Y4 U& `| MCASP_TX_CLKFAIL % `; D( l+ ?) V4 Q8 N# o
| MCASP_TX_SYNCERROR
: o) r: s! @: b6 c8 A' Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " U) B" }8 D$ |9 N f
| MCASP_RX_CLKFAIL& i& y2 f0 \6 _- V) t
| MCASP_RX_SYNCERROR " g+ i/ K, g; @! E+ r. w
| MCASP_RX_OVERRUN);
6 ?8 P) Q8 d# B4 I} static void I2SDataTxRxActivate(void)4 \- j5 [! P) [
{
7 X# e8 L0 W, ~$ W# j4 Y+ v$ [/* Start the clocks */
( H5 J8 Z! e! S% mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
M6 m6 a+ S: g- p5 ]! |) \; P* RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
o) g- H: L" i; E9 I" W- R2 ^7 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ @- M5 H) ?6 L( a/ F$ p" \EDMA3_TRIG_MODE_EVENT);
1 m0 K" p. s _4 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # L+ M B8 {2 r: s5 I R. s- `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* F9 G# M. {4 [3 q* a8 j0 e3 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- f3 i& }$ G o9 @6 _! b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# E- J7 C0 n9 G! P! e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ ]5 f4 l; W& s2 p- SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; y1 T. p0 T: W2 `$ yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 G, _6 H8 h$ R* \$ [* y+ N3 [} 4 K) d* S g' T; E4 x% F- k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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