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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 t8 b4 }# P9 E8 L& g# n
input mcasp_ahclkx,
4 p8 r0 h5 x5 ?: C% k7 O3 |5 b* Iinput mcasp_aclkx,5 X L7 p9 u3 \
input axr0,
1 z5 l m/ c+ V0 d2 d- @; @+ ^4 r0 g: A8 S9 h+ S
output mcasp_afsr,- m7 z0 O& k4 V* ?
output mcasp_ahclkr,
) O" v& c6 M$ B2 t" Xoutput mcasp_aclkr, ]! z( t; y' |* Z
output axr1,
5 x% p; F) v" @+ J% G0 d7 G assign mcasp_afsr = mcasp_afsx;
6 ~1 `8 j4 g! R2 eassign mcasp_aclkr = mcasp_aclkx;
: S/ d* q/ H ]assign mcasp_ahclkr = mcasp_ahclkx;9 n$ L3 Q- ^+ ^; f9 m9 w" q
assign axr1 = axr0;
7 x- T% ?. [* q- ^$ t1 Z8 i9 i+ u9 b+ {+ }" N+ g0 ~6 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % m0 c4 z. ~ Y& c1 s2 z
static void McASPI2SConfigure(void)
+ ?, T4 U% m8 {8 N6 q0 z{
1 J4 t6 K: v+ b) E5 f3 _( ?McASPRxReset(SOC_MCASP_0_CTRL_REGS); D% @* x1 \) E) a: x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' m4 ^& t, R* ~" F8 o* YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! p1 s! p5 B8 K. dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 g& X7 t# m! s" m; ]+ tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ~, O3 ], }4 Q5 n- h& ~
MCASP_RX_MODE_DMA);' H- y) N9 p# v+ Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 {/ Y$ d/ l1 }% E8 K) GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ [, R/ X4 J9 b7 n3 S5 ?, D% VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. m, [/ t% e; j( r- w: L9 p6 A2 AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
N0 j; n' k! f1 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 [# g' B9 Z7 @2 q7 l8 _: B: iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* ~5 C9 h" f/ E; KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); W3 v, t0 z$ x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 Q0 {1 U4 i/ C# hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- ]) r9 @$ L2 {( M
0x00, 0xFF); /* configure the clock for transmitter */4 }5 h I2 f1 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 h6 r& x k0 \2 @0 }# P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
u+ O* T! ~0 E5 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ P+ r S7 Q; _8 E
0x00, 0xFF);# f' K) p- S/ w. f1 D' D$ ~) x: r
5 y9 @, ]5 V6 A6 {# P/* Enable synchronization of RX and TX sections */
+ b; K5 j, u9 I) [" g4 HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 a0 J+ e# E4 y! X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, t3 z8 t. B3 w2 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 Q4 e( ?7 j9 W8 ]( |6 y w' m
** Set the serializers, Currently only one serializer is set as
! {) T! L( ~: s \; M+ }7 L' B** transmitter and one serializer as receiver.! ?* Y0 V# S, e7 p% R
*// E0 j% U Y, I k) T9 }- Y$ o K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" |. q# T7 c( A. h5 u5 I+ lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 P7 E" s# e) `6 e3 ^, i** Configure the McASP pins * s0 v2 k }8 v6 x w
** Input - Frame Sync, Clock and Serializer Rx
$ B8 s3 B2 a# K** Output - Serializer Tx is connected to the input of the codec 7 z4 _0 K- x) F: M. N
*/
( i% v" j# j. e1 K3 CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); L# J$ z# h3 Y ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( A3 ?3 b. `- D xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* P. j* b- y4 M| MCASP_PIN_ACLKX
; p O9 S( _/ V| MCASP_PIN_AHCLKX
5 b: }: W0 e) K) c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. H) d h T7 `: e. NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ L. `, \1 G' U7 M| MCASP_TX_CLKFAIL
: n T9 D1 S- A' t6 @9 M9 W5 V' w| MCASP_TX_SYNCERROR f. I2 {1 D4 d% a5 d% G7 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; O4 z$ {3 Y6 U- j$ {# h8 z' t
| MCASP_RX_CLKFAIL
9 `3 C X }8 h T3 || MCASP_RX_SYNCERROR
( G, a. M: \" e8 \' Q7 n: G- G| MCASP_RX_OVERRUN);
: W8 P5 y3 e$ d* D3 b6 |: \9 B} static void I2SDataTxRxActivate(void)
@7 o4 Q" q( g5 d% [# r" s{ y1 y* k0 W5 |
/* Start the clocks */3 n: m3 {1 \. S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ b: i- F; {' G& I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, J+ u. B; |" B4 o6 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' n8 ^( }$ E- ]! I- `& _" FEDMA3_TRIG_MODE_EVENT);
" D$ w+ [, G- E dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! ?/ B6 _) x* j- t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- ]5 Z8 [ ?3 f3 n& q! E8 oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 ]. ?1 [# I9 y! D8 e# SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 A& p& w9 S7 X4 l# Z- F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; ?4 l8 ]5 [# _0 b% UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& q- e7 [( N8 G; p; G+ n4 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, x: B' e$ s4 J' g
} 2 o4 z5 L; `1 l5 I p" W8 K4 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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