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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 W% M" w7 K) G9 F% V
input mcasp_ahclkx,
' Y( d+ w: ~9 x, Uinput mcasp_aclkx,& b' T& J5 M: Y" k8 e( J! K
input axr0,, k$ B, Y3 j0 a8 O0 c
, x. _" n/ n! l4 y0 @1 loutput mcasp_afsr,
; {9 k4 @! J6 o4 }. z: Soutput mcasp_ahclkr,
1 ~+ Z' L$ H" L @, w. N* ~output mcasp_aclkr,& w! O. s, O: ~+ O {; N
output axr1,# q' i/ {: a( P% s6 y( G
assign mcasp_afsr = mcasp_afsx;! J+ G Y" k5 X5 B" @, _3 {0 q
assign mcasp_aclkr = mcasp_aclkx;
- B1 I* n I. Z: Yassign mcasp_ahclkr = mcasp_ahclkx;6 L2 d% K) |$ x, ]
assign axr1 = axr0; 6 I2 H' v( Q) B$ O
p3 ] @! x# c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ ]& S$ C+ l& y( jstatic void McASPI2SConfigure(void)5 `: W% ?* r# }! @' e
{4 W: u! y- c, X" e8 Y! W) h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' c4 ?. y$ ?$ K! H' Q2 ?9 {- qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# z2 {7 h( q3 Z' Q8 z0 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 P. [$ A8 I8 z2 k) _8 |( Y& z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& S8 x* K: Q- o" {2 q0 Z. Q2 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& F" M$ _1 X5 W- M9 U+ c( f
MCASP_RX_MODE_DMA);! |$ }% w& L! K! A8 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, c4 ]# M1 r$ {2 SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; h4 N6 k+ ~. z# i0 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ T. u0 m, M! T- t) i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 H9 _* ?. P' P a. HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- A2 x; O5 ~) |, K6 w6 k* y! aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ q2 z0 p. n" E- S3 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, u% i6 Q# M, f' [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + {" A5 |( Z3 ^$ {7 E; C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 }$ q/ r L9 Z/ }0x00, 0xFF); /* configure the clock for transmitter */
! n8 M8 ]0 m: x3 S7 W% ~$ qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 E( U$ }5 D) g! p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; B$ x1 H' u9 @. _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 o3 T1 y: I- _2 T* n, g7 V0x00, 0xFF);4 S4 w" l# f: r+ A5 |
) Y9 x, X5 ?* S# k% Q, @- |/ o/* Enable synchronization of RX and TX sections */ ' V7 g3 o( P4 |! [& P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, v2 T- ?5 t; i7 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 G \* m* B: X$ [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ C" o( F/ _8 @% q$ Q
** Set the serializers, Currently only one serializer is set as# h1 r. O! B/ f0 w
** transmitter and one serializer as receiver.4 @7 ^& a' M. S3 \6 Q% @; B
*/
1 c' b' k$ J, w6 ^+ VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ y$ h4 }6 ^4 L( l1 u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ L7 L' y6 {" u- x$ l2 e
** Configure the McASP pins
: l( C: n+ T( j2 h" q. q" K* o** Input - Frame Sync, Clock and Serializer Rx; m s: ]/ `$ ^4 v: J/ i. ~+ u: c
** Output - Serializer Tx is connected to the input of the codec : m, S4 c [' w/ M8 T
*/. \, [3 I4 U! J. o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ | O& E; f# c1 `1 d. c- Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# J% H) l4 t% h6 L1 S+ _+ nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- x( d% X: [4 W8 [3 || MCASP_PIN_ACLKX8 X) a+ {; w3 [' j
| MCASP_PIN_AHCLKX) a1 Z3 h& k9 h; U' R# E9 W C& L- \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ d5 c; ?( J, s6 C; N1 q& A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) @$ `- ~6 T3 j- V) H| MCASP_TX_CLKFAIL 0 a( t* c4 \ c" j& T- D5 X! ?) K
| MCASP_TX_SYNCERROR
& T5 ?0 c, q- t+ u( m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 T* ?/ ^' R/ F5 h0 U| MCASP_RX_CLKFAIL
% Q4 y0 B, h) l8 w3 H8 _| MCASP_RX_SYNCERROR
6 n2 T8 P, h: G/ V' J9 j| MCASP_RX_OVERRUN);; o! [: T2 {" H! ~) ?
} static void I2SDataTxRxActivate(void)& `# {4 d9 O2 c& X5 R) l7 y
{
0 S# o) N/ U; {' c$ m2 B/* Start the clocks */' t/ l6 d! V4 l1 c+ x8 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
Y* E/ g' c2 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& x ~8 ^' U; L% l$ j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- V3 l, c, b- A4 X
EDMA3_TRIG_MODE_EVENT);
8 u( w7 k7 |" {$ E; NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, P" W: P4 P K7 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ z I" V* `4 l3 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 }3 `0 y/ v. S# v$ Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* m; N) e) R/ v) ]0 x; Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 @; A3 x2 ?2 U' e+ I9 T. a: a: wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* t( P; R: p2 O$ S; M9 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 O1 O% M8 G' j6 e}
* z6 f2 ~' i; `% s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. c3 J: r V/ p' [
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