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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- H- f% g2 m/ Q# s3 ^
input mcasp_ahclkx,
/ g8 p' D( D9 o) U1 F# O( `4 w2 ?input mcasp_aclkx,4 L8 @2 ]! j' n K' I: q& v) V
input axr0,0 z$ s. r. S2 T& E( _- n: y
7 J6 P2 H5 [) g: j" _. T; {
output mcasp_afsr,3 a7 U$ d/ s6 z
output mcasp_ahclkr,
/ u; e A7 C/ h9 [output mcasp_aclkr,
$ a: j, f3 {( {$ |# W/ E* ?: Aoutput axr1,
- G' T7 ^# r: B. O assign mcasp_afsr = mcasp_afsx;% [2 M3 ]2 w1 B5 ^+ R" O- I8 P+ j' M
assign mcasp_aclkr = mcasp_aclkx;
! Z) X9 k; ]( k: R; C5 v* Oassign mcasp_ahclkr = mcasp_ahclkx;
1 {* y$ q/ W8 Kassign axr1 = axr0;
% F; e* u3 {7 F! p2 p8 A
7 C1 t9 p- [9 X. n3 u/ y; C% u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; [' M, a* |# t' k! Y
static void McASPI2SConfigure(void)4 I; a: M0 G2 n- H/ z* u; h ?. K
{
0 I% S" z) O& YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- E/ P! L- C6 G8 d0 ~) o \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 f, f* `, j9 U( |- IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; o; {" C. V# l- t1 y* yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 [' N- P$ h/ w$ ]3 t9 T% dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ J3 F7 p. f2 |% M( F: YMCASP_RX_MODE_DMA);% ~9 H/ b5 ` R! s, L6 s9 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 |" K2 d) N2 l7 O, A5 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 U* a6 I$ X% pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 M4 z% l$ E# U# D, a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; A, P/ U; C* j3 o/ Q: ~ q d) RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 [- a1 C$ I7 e/ @" j, JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: w3 A, u7 N+ q& U' o4 M9 A3 HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 B3 b, o) G+ o# w( y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% m5 f% \- t* V! tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 _% w1 Y4 h7 r& m# e, w0x00, 0xFF); /* configure the clock for transmitter */9 D; j& q2 x b3 v+ j% |8 F* b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! [2 g$ b1 N& D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 R* Y: W4 V5 S" ?, TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 m3 }1 W/ Q& _3 d& s
0x00, 0xFF);
5 ]- F, @( |/ \: p
u5 Z2 h6 u3 F- l/* Enable synchronization of RX and TX sections */ + d# J0 G: ~( m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" m6 z7 y. ?; w$ z @5 n; O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& I- W- A# J L5 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 a* P4 g9 p$ l! M2 H! u** Set the serializers, Currently only one serializer is set as
2 w/ F5 M; i6 a** transmitter and one serializer as receiver.$ Z9 s, b5 r3 e: V& l
*/
7 N8 [# f6 y- D# g0 z: ^' YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- b0 n( x$ L& }: v2 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; i3 `* T0 {+ h4 {9 d+ s h$ {
** Configure the McASP pins
. l0 T! X" \# |9 s** Input - Frame Sync, Clock and Serializer Rx
1 c" C/ X- a/ G1 g N6 x% i6 j** Output - Serializer Tx is connected to the input of the codec % `: C( a# ]" n2 [( g: s
*/& U2 p- Z& x; q A, [4 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ ?6 [; j. X9 E; p# [/ }/ OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ q; F4 Q! b* R; \* k5 |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ N7 l/ r/ W+ B9 a3 z| MCASP_PIN_ACLKX$ X( Z6 M& p1 D* j) J/ w% ?# ^
| MCASP_PIN_AHCLKX
* w, s! l/ A# m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" n0 M2 W4 a& Z/ z6 ]: k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) j! N. j; M c/ I/ T% A
| MCASP_TX_CLKFAIL 3 `' d& b' z3 N6 l% T$ v- [+ D: U5 X
| MCASP_TX_SYNCERROR" J6 o2 `9 e* N; f( |: J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. A k6 K$ }; r V% D' `! g; b| MCASP_RX_CLKFAIL6 r3 a( D# i" l, @% n
| MCASP_RX_SYNCERROR
3 h3 ?. f: q* k| MCASP_RX_OVERRUN);5 ~& k4 c( O" T/ o8 _: r
} static void I2SDataTxRxActivate(void)
R* E5 x2 o) E, l{
9 M; X. d |" L$ Y+ P7 J$ B/* Start the clocks */& {5 _( f: {# b1 m- b5 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" E: X: l3 v, G9 d6 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ k8 l; r4 x3 Q8 E5 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 b" C4 o9 k2 [0 zEDMA3_TRIG_MODE_EVENT);: \: D4 g. Y* d* B! r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 \; D, n" y- q) H8 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: o7 [6 e& A e) k0 u& qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 ^/ c3 ]8 D% X4 j& y: I6 _/ P5 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 M' x3 A$ w( G& K8 w) K* G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 Y3 D, m9 B- O2 J0 z5 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" V- Y+ k# F. E* l* {) LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) I* l; p; r" @/ I: i/ R3 N8 R
} ' z% m+ ]+ |/ O* U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 l$ X5 k$ |( h8 _* v
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