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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) E( i. m, V" y- }! y+ m
input mcasp_ahclkx,
# K+ P% ` _& b$ `input mcasp_aclkx,+ T- K( T) \: a% k
input axr0,/ H& k) ^9 f: b7 E# ?
2 @1 O4 f+ L6 n- o8 s+ Zoutput mcasp_afsr,
7 s G7 ]5 g8 D/ {output mcasp_ahclkr,
, I+ E' V2 m/ p, U+ soutput mcasp_aclkr,
6 A; B6 k2 ^0 ~* M4 coutput axr1,
; j8 t. m ~- E) Y6 G8 W7 M) P( ] assign mcasp_afsr = mcasp_afsx;
# K4 G, f" x2 p1 Lassign mcasp_aclkr = mcasp_aclkx;8 D! o" |; b a5 D
assign mcasp_ahclkr = mcasp_ahclkx;6 ]8 o( c' }. m
assign axr1 = axr0;
! M2 _* D9 \6 u; U4 [/ t, y8 |# J% [+ t% f& {; s8 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 V$ \+ J" [3 G6 h, D1 Rstatic void McASPI2SConfigure(void)
0 g# }! Z! L9 \* l# {{
; ]# a# \2 I% E6 M( t9 x! P7 PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% h. Y/ H: h7 g0 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# V$ N4 D! s. C4 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 u. J7 w7 N/ j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, n: f% ^% a3 qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
M7 G& d! w2 IMCASP_RX_MODE_DMA);
# w1 W' |& B. h0 @, `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 E: H c C u8 e0 O9 ^1 U1 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 m+ @% I* j1 L1 ]* OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 P' e" s* O! \& C- K3 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& m+ J' O* \0 F! U8 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( _: w) P/ S, ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 j. t4 Q" T( M8 V7 c2 sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# M5 O4 P; Y* ]( \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) ]8 D! }! ?' e2 T) vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 K- {5 M9 O" [+ p' R) I" i/ Y0x00, 0xFF); /* configure the clock for transmitter */0 s6 P! G2 \; E& E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 r; m. U) b7 U, x) l1 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 b+ x8 f" T9 g* N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* X& a4 l' t" R9 i+ ?$ y
0x00, 0xFF);
- |) _0 Q' p% p Y) K! ~# t; }) G" F2 g1 ~3 G/ t
/* Enable synchronization of RX and TX sections */
( |! H8 A! L9 O' [- o: \! JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. L6 J' `# ^& Z2 p, W/ p; r- `# h: D" eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# h! i; K: G8 W: }0 l3 j1 H @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ f9 W- [- K( ?# S* d
** Set the serializers, Currently only one serializer is set as& Z3 L" E+ b- x
** transmitter and one serializer as receiver.
g9 j& ]! B1 e*/
. K, E$ Z+ E. E- h% e4 G% MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ J; X" ]3 g) g. ~3 M( M* ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! v4 C! b# p8 |8 t
** Configure the McASP pins 5 [8 w6 U( I2 P6 B5 C/ m
** Input - Frame Sync, Clock and Serializer Rx( Z! c) ~+ ]& y* v
** Output - Serializer Tx is connected to the input of the codec ! L. }( h6 S& y3 ^% V, {1 }3 G! `
*/+ }* N z' X2 u0 l- Z9 @6 B" }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! s# c0 h$ I: R7 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 F3 B; S5 Z! j: w7 d& Z8 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 U( ]1 i0 G4 g5 c| MCASP_PIN_ACLKX( z$ X1 B3 Z# N$ ?0 n: T @9 s
| MCASP_PIN_AHCLKX
$ b( a8 M2 ] t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 j8 k( B( Z; O' E: _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 w5 u9 X. L: v* L: d| MCASP_TX_CLKFAIL
! p2 ]$ A' Y! ^! j| MCASP_TX_SYNCERROR
; \; r. N7 ^1 m& [2 b1 k) p ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 V; \. ]. Z* I4 [; \+ t| MCASP_RX_CLKFAIL
U0 B$ V- S. I! q9 @$ n+ z| MCASP_RX_SYNCERROR
# V1 w# E! C! L| MCASP_RX_OVERRUN);
1 _7 m1 V, J( r} static void I2SDataTxRxActivate(void)4 M% V& \$ Y) b4 Y( ~5 M
{
; |% N+ r* X' E/* Start the clocks */
& A1 X8 T6 V; s( l* \( m' [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" E7 @- }3 Q! u- U- y' ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 A( _4 n7 k4 g0 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 R$ _9 d* w! R
EDMA3_TRIG_MODE_EVENT);
# f6 a& {/ Y% O) SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% l3 M2 h R5 S% `4 Q7 a! jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// W' r, W z# x" z/ o1 U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 h$ \% }6 a0 U$ \; K! a8 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: P6 f* a' }9 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ `, [: q3 L/ Q* S: Y) ^' K# v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; Z* P* \/ X+ S- VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; i9 `: m! ?: W: h- `7 E O$ E
} , i( ~7 a3 [3 x& ]& b. v' C* b7 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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