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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 L% M6 |& f2 _
input mcasp_ahclkx,
9 S5 `( n; Z E) ^input mcasp_aclkx,7 x, z, N6 I: U
input axr0,
* P( [4 L1 s" V6 b
! m' `3 E- S0 q1 Coutput mcasp_afsr,
( R% R0 ?. b/ j: ioutput mcasp_ahclkr,
2 f; J* }4 ?( ]" P/ M+ h2 D% ?$ P Voutput mcasp_aclkr,
+ y/ \" v) p: }7 y* Foutput axr1,+ Z) }) V- Y+ H& ?1 }( U
assign mcasp_afsr = mcasp_afsx;# ?1 E( @4 M8 M$ M
assign mcasp_aclkr = mcasp_aclkx; J. {, N9 L! B* a8 _5 _
assign mcasp_ahclkr = mcasp_ahclkx;
, L0 q/ ]4 b9 S, _" k, Cassign axr1 = axr0; ! U- w# m/ A) n8 r9 g0 R
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ D* k- f* z# X1 [8 M% Lstatic void McASPI2SConfigure(void)
' F9 l: ~# m4 y5 k7 {3 ?9 X, V{: K% m; T( Y& _: _" G! n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 i& u1 _% b; H; o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 C1 @7 b, G7 I5 q- A" o5 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 `. r/ T* o) l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ C8 y% a5 W7 e7 D3 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ^" v/ J' k FMCASP_RX_MODE_DMA);
. S) D9 d5 {7 _9 G$ l. PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) E% @ K Z0 D: w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// D5 ]' H2 h+ r) P: ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: y2 V; l/ J6 W X1 P% lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" y$ d; p, b0 m* Q: l a6 J) ?$ iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * E& q7 w" X- }" p' |: m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 V/ n3 Q' o5 v. e6 O$ y: S8 \5 Y8 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 e/ r" }" B9 O+ A. U! B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; `' g7 z* ?; ?; W0 l3 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, F! b6 w6 X8 v
0x00, 0xFF); /* configure the clock for transmitter */7 G4 J* w! J6 s2 Y6 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* z! G8 {! d: S4 i3 p$ Y) M- l6 q, X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 r1 S5 V# q# x- `! o6 b% y6 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: A+ M6 b( j9 {# p. \0 C5 |) l: N' d0x00, 0xFF);
* p- ?# y( ?& N2 ~! I9 {. O; B5 _5 N' v( T
/* Enable synchronization of RX and TX sections */
8 W3 G2 J# i( A3 S. _% vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ S* p! J" V' P+ n+ `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ `7 t2 e. y. _- L+ Y! _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' k ~7 ^4 |2 u; ?3 v# q
** Set the serializers, Currently only one serializer is set as
2 b5 B% z4 n1 O% ?$ T5 L' f** transmitter and one serializer as receiver.
; i) D: I4 |5 m w8 t" ~*/
% _8 B n1 O5 Q$ j8 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 c8 s* z0 w K' [* p+ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, N5 s+ ^+ d" R5 x/ \9 k; ?5 e4 s** Configure the McASP pins
$ {: ~( C# U* U* I' C** Input - Frame Sync, Clock and Serializer Rx* r' f9 O2 Z4 V1 k T
** Output - Serializer Tx is connected to the input of the codec
3 b! c3 O! ~* Q7 g2 D" t*/
! O- N5 \9 G3 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 ]- q2 f) d- p9 A! \) _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' Z: N3 B- s1 x( l H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, s$ x5 y) P; c9 f/ q8 `+ x
| MCASP_PIN_ACLKX# `1 Q" W) C" U0 P- B
| MCASP_PIN_AHCLKX
) u1 K# j. X: I2 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" k: I3 O* j3 X" e& LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 Z, B% n( c( x) ]( E. ?| MCASP_TX_CLKFAIL
! Q% G! ~* ^: c! ~+ b2 h6 U8 N| MCASP_TX_SYNCERROR# u, z5 W2 ]6 a0 [: B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 n$ c0 N3 N K M3 f; W# B8 x% a
| MCASP_RX_CLKFAIL% a' `0 W6 h. |1 ^+ f' e6 v
| MCASP_RX_SYNCERROR
6 i! z8 O. t7 _& o+ v| MCASP_RX_OVERRUN);) Q9 @# L6 [+ @0 V2 z! i
} static void I2SDataTxRxActivate(void)0 T+ ~# J* M0 L1 X/ n! O
{- w7 H5 j; G4 Q
/* Start the clocks */
8 G# i) t& k, X4 u# ?3 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( x3 h ^. D, W. J; YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 z8 |' x+ v" w7 J) {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 F' B8 y6 ~$ y J2 Z! e3 r
EDMA3_TRIG_MODE_EVENT);# Q* K8 P$ o# I% a8 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) C8 |1 e) m8 I, w G4 {, d! AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' k& J Z" M% s7 d$ z3 x+ xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 j: v: J1 C! R" V! \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 x# @- @3 D0 v, z8 N; N- W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 V( \3 T" [% u# A/ M* H" g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ [) ?) c7 t0 K+ S) s. JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, [) a4 _, k. Q7 x5 u} 3 u u6 J2 H. ?0 L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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