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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ R; ~7 { H& w
input mcasp_ahclkx,
o% M7 B0 L' p# ]. Ninput mcasp_aclkx,8 p9 v* r+ T9 C' Q) u
input axr0,1 d% n& \- v$ v6 L: @
9 N/ P3 `$ J& O! f. L
output mcasp_afsr,
D1 S% J2 j$ C: D9 S6 }6 X6 U/ Moutput mcasp_ahclkr,1 u2 l0 k. J9 E" a+ R! d7 s
output mcasp_aclkr,# ?' C% N1 N" c- k1 T
output axr1,& K$ s. f6 j- R) j, k0 A/ ~. f+ k1 T
assign mcasp_afsr = mcasp_afsx;& e# x2 V. v) |& x1 B, G1 j0 S
assign mcasp_aclkr = mcasp_aclkx;, W L% x, n1 } l. _# \! C
assign mcasp_ahclkr = mcasp_ahclkx;
0 y9 w, q* |% j4 c& C$ b* qassign axr1 = axr0;
7 f# j% U. n& p" v& j8 a) Q! F- x: g6 h9 T7 M t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 e& r( \' \% ystatic void McASPI2SConfigure(void)/ w+ g: ^8 Z z7 M8 p( e
{ R: A R& [; o2 o4 H& h. {2 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( n/ m( w' ~- b' w7 ?/ h. |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' l9 u" x+ J( Z+ b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. _% I8 ] ~; q- F7 s/ JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 }8 @8 y- \ V3 c0 B" x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 S0 W: A- z; a. i8 N4 D
MCASP_RX_MODE_DMA);: Z2 R g0 K. x# B4 }1 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- ?/ B+ R4 G% g/ l3 r! @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 ]( l) ^8 n" N- d1 f$ |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 U- H ~) W% s4 h4 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) j, C. I' s) U. X4 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: c0 p4 z% U3 K" d- {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// f2 W' x# o6 n$ m* n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 z8 C1 s- Z9 }3 V# Q- V/ v {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 c4 ]: } y) S9 g I7 ]2 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# ^! @. k8 x6 A) |0x00, 0xFF); /* configure the clock for transmitter */+ s% W7 j, Y' y a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. {/ D& s, f, ]$ J0 s' dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ g( ]6 |5 Z1 ?- CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, A: X" r/ a7 l: z6 f
0x00, 0xFF);7 J- ~9 \4 G2 b. ^
?6 y" a: e3 M8 t3 _
/* Enable synchronization of RX and TX sections */
1 H) W; C6 b% O* _- q. {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& [8 _5 v6 F5 S" S8 r6 n0 p( f, B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 {: N' X1 |* V; m2 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 ~4 F: L. f/ n7 e# c- F** Set the serializers, Currently only one serializer is set as8 {; P! w9 {$ e( g/ ]
** transmitter and one serializer as receiver.
! a- s7 h3 ?- P7 _, g& c& c*/
4 ]1 p" G4 @) V3 ^. gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 v2 b# u% d1 y: Y2 A; o& R+ V$ }; |! z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 q- ~' i0 a d# [# y' U6 @7 X** Configure the McASP pins
7 {3 f2 {# j$ C+ w; I! Y! w** Input - Frame Sync, Clock and Serializer Rx
5 {4 T9 P/ r* T3 L# F+ p3 x$ @- ^** Output - Serializer Tx is connected to the input of the codec
3 M) o. v/ H) |*/
. m' M# V% L6 [4 `( t1 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 B, }, p+ N8 ^( W) X z" L8 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 f, B3 U7 e) r# h/ E- ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" H2 K" c: Q( I) O, I, f| MCASP_PIN_ACLKX5 I) Y& E& j. w& }' P
| MCASP_PIN_AHCLKX
: A* J9 M# a5 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 {9 {# n& T" V9 H: ?: o) y5 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - B6 f7 {# j5 A
| MCASP_TX_CLKFAIL
0 D7 p4 \0 C- C9 y| MCASP_TX_SYNCERROR
+ E9 H9 f" [5 X+ |3 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" O; U9 D. u& h |- y! H3 U| MCASP_RX_CLKFAIL
; a; ~% O* p t" N3 A| MCASP_RX_SYNCERROR # A [4 n1 O4 Q2 t
| MCASP_RX_OVERRUN);
. I) j& `& z9 d7 e \2 d} static void I2SDataTxRxActivate(void)8 v2 d8 {$ ?' G, e
{
9 j- T& |% R0 J/* Start the clocks */
9 T4 C: N7 B6 \. d+ E) S r$ aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 O+ r' ^2 U; g3 w8 ]% `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 `' ?; n; ?2 q( r( U2 B6 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 @2 G2 `# X+ e- J% B( |5 EEDMA3_TRIG_MODE_EVENT);, Y' O1 Y! \' u' X" l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 ?" j' j; h0 j1 j9 m- M6 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 i2 M# M/ O) {4 q/ d) U- e/ g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, W5 l0 s6 b3 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" U. _1 f4 K+ k8 z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" V, \& E* y. N, x* ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, g- Y3 e v) m0 q7 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- `( Q, M$ k/ U, `3 J2 H( x1 u}
$ a o. C7 \% }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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