|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 ~* U% e/ _2 N: A4 x) ^( g
input mcasp_ahclkx,
) ~; S: X6 }2 {+ x9 binput mcasp_aclkx,3 ~# y" `* K5 B8 e
input axr0,9 w8 B, v3 L" `1 x9 s
_9 C4 C/ ~3 Y p
output mcasp_afsr,
. I/ C+ [, c: s( woutput mcasp_ahclkr,
! L& C- R1 c+ _ e9 @output mcasp_aclkr,* z0 ?! `8 p6 \* C+ m& N' N
output axr1,
: a Z i1 }- l; w$ {7 h& ? assign mcasp_afsr = mcasp_afsx;' @3 {( R, l z7 a+ g
assign mcasp_aclkr = mcasp_aclkx;; {2 G4 v: p0 X) k1 k, H! [
assign mcasp_ahclkr = mcasp_ahclkx;8 B- d4 E0 t6 A
assign axr1 = axr0;
0 E. i! F! x7 L' z- I3 p# e) x5 e8 ^8 x2 [; P* }, H* G' j) j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 z1 u3 X/ g, U1 H1 D$ pstatic void McASPI2SConfigure(void)
. Q2 v; i+ d( o- d, i1 b# f# s( w{
c% b9 V. z' x1 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 M+ `: n1 [: m8 O" }$ mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; o% m0 f- W8 I* s7 @% t# vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( {: P4 `1 n7 v% |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' w" |" C! p+ N- G, @, j" kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ~. O8 j8 Q+ @/ D9 [9 j0 FMCASP_RX_MODE_DMA);
, c5 A a+ y# ]* g: p% N6 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 G* u5 @ [* D2 l% u O) u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. P, m* c' g% eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) A7 U$ \8 K$ w8 r! h% r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* X' R& N" j& y7 z9 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( C. _. U( O# VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ I# l% P. K- t" _8 tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! \7 H, F: P. {* H3 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ g7 H, R c1 H1 h& [5 E% b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ a+ |+ q: c/ @7 b* T/ ^8 z* A0x00, 0xFF); /* configure the clock for transmitter */# I0 A* O; c2 Z& X0 X4 Q- ]) m9 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
{0 P. n1 c0 F5 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# r1 M& n4 _* k4 @" MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 A* c: t1 u! p4 S- s& k( I- v0x00, 0xFF);5 o+ ]8 J P2 i! v
$ Y. ] K# K4 c6 R; J1 N
/* Enable synchronization of RX and TX sections */ . }! Y: j4 S" s; [( m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 n: s. u% n7 V( C% U ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: K4 M% M3 K. q5 b {& V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 Y( W6 V" n% A6 @5 G* k** Set the serializers, Currently only one serializer is set as* ^; Z% ~' R, [# {7 I. |3 ]
** transmitter and one serializer as receiver.2 A8 H0 r: ~+ v+ @# e. p
*/% c5 O6 X. f Z6 j' S# ^5 [: H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 h7 h' H# T- L0 M$ P9 e3 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( \& V ^" r$ d7 J8 E5 \; |** Configure the McASP pins 5 c) ]- v9 ^& @6 z# H& J" b0 x# }
** Input - Frame Sync, Clock and Serializer Rx
0 V$ N; L" `5 G0 `! s** Output - Serializer Tx is connected to the input of the codec
% S7 K4 g# S/ [4 a5 ?0 k0 x) S*/
u, M. B8 }9 U' RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 a+ c) A( U8 }$ \* q$ \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 I+ f3 \, W& v3 B, N, [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- |5 {3 F1 r0 o/ v| MCASP_PIN_ACLKX1 Q% h [. J1 r- C, i$ p
| MCASP_PIN_AHCLKX( I6 a! S: K: |( p, P) G5 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 `7 ^0 H3 n; ^$ A1 U3 m" pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ M5 Q4 M/ S9 q| MCASP_TX_CLKFAIL
& _/ I8 `: X: k% D C# O| MCASP_TX_SYNCERROR& p7 k- c- ]7 d% ?3 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # ]. L& b& l6 u( d) @1 N0 e1 P& n3 ~8 V
| MCASP_RX_CLKFAIL
2 L3 w+ `% g2 `! j2 l9 t2 v2 d( Q, z| MCASP_RX_SYNCERROR 0 ~; R# R: i9 y0 m
| MCASP_RX_OVERRUN);6 L. o! p8 O: U
} static void I2SDataTxRxActivate(void)
4 H2 ~, ?/ Q, S( u# C$ V4 z8 u{# ]8 {1 q, a* P: i% B+ p: n4 L- f
/* Start the clocks */
- Y- V" n5 q4 ^" m. Z! q+ lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 t7 b/ n# N5 {0 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: B' \2 s4 D! x* S/ f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) t- x N" ?9 X( t* m8 q, I- oEDMA3_TRIG_MODE_EVENT);
1 P# D, e& P, nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ Z- e9 L% z& n6 R r/ WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( @$ V9 J b& ]( q# {. |# m( NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ M! i a" ~, a8 i" QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) M D1 ]2 G, w9 a) ?- x9 g9 Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& A/ ^9 q m j- P& w0 C- X6 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; y7 V- J2 m' F# B( b1 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" G5 J0 u' ^( p0 b
} 4 E2 B5 r3 W9 S. j7 F4 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
, w% N9 W, C# S$ M, o |