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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& G) [6 V! ~ D3 x
input mcasp_ahclkx,3 t$ Q6 K7 m2 _, Q" d1 p
input mcasp_aclkx,2 g( y( K! E* Y$ \" `0 T! @) _
input axr0,
( a# E2 \, K# H! h, V5 c" k+ O; m. n6 j8 |8 I% c
output mcasp_afsr,4 D( y" w% @+ V9 y9 i3 O
output mcasp_ahclkr,
9 \8 I& C' \' z# F' Doutput mcasp_aclkr,. d! a. R" I& D' C0 V
output axr1,3 O. k& u) v2 F# r t7 M
assign mcasp_afsr = mcasp_afsx;% L6 A- H$ T c" [
assign mcasp_aclkr = mcasp_aclkx;
8 g' E2 x$ s: V* G( kassign mcasp_ahclkr = mcasp_ahclkx;
( \: z8 T! G) _' z& qassign axr1 = axr0; ! z. a" j+ r# p* j+ Q7 j
. s2 L5 L5 a, y. e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : \$ x6 Q: r, @0 I( M7 C/ t* ]* L: a3 l
static void McASPI2SConfigure(void)
5 |- ]( C$ Z& f{: P& ?( ~' j# ^9 x$ s: h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) E3 D0 P& F; b% HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% R* N. S. a1 @: u! c5 a" j' J& W' [8 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) U" s4 j6 N+ F2 |3 F" _5 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 ^; ]$ [% u+ S* t8 gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 g* n; b. V% _, o5 i `MCASP_RX_MODE_DMA);8 X# ?+ ?1 G3 l' B3 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 |& h$ j- d: ?5 q& W* e" g9 d& a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' e6 s" S4 w# t3 u% x5 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: G! h7 M6 q; k: _2 K5 z" RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" d: G# A: H" U/ N% u6 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; @ q4 S; G& P8 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 |/ L* g+ ]: g/ K/ V- ^% l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 m, j$ J% Z" B0 Q+ O1 w0 t5 J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, C# S$ X& X9 @ r/ A, ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- y7 _; J9 i7 @4 n- V. [; M1 g0x00, 0xFF); /* configure the clock for transmitter */
9 n7 ~# b {- u5 L G- R! D rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 p. N! b0 `( `* J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / b4 p1 Z8 Q! \: x: f- A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ T. g" P# ^; \) } s0x00, 0xFF);
2 w% U" W2 [9 S9 f: p' x
# ?+ p) g6 ^1 G/* Enable synchronization of RX and TX sections */ ! O- A, w8 D- |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- ^3 }9 f4 _+ e7 l1 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Z$ ~. @: g" _5 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 k3 b7 N2 e* a# {& Q8 k( O! b" I: D4 S
** Set the serializers, Currently only one serializer is set as
+ u* p9 h" W( x9 V, ?$ j' w# r** transmitter and one serializer as receiver.
' ~! `" k9 U# J1 n$ i*/
8 Y! k2 |' O% I3 Z" ]! oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 m! z- |5 p/ v8 f$ G5 ~ ~& bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, V# |& `1 v. P" T% f/ {** Configure the McASP pins 4 b* a9 n7 c( }: S y
** Input - Frame Sync, Clock and Serializer Rx# o5 s o- t4 k5 |2 e) E
** Output - Serializer Tx is connected to the input of the codec . p& D. h+ F2 h% s
*/% v( a, s" E0 c- m8 v1 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* ^8 j! l/ t5 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* x. D+ F2 c, Q U- b$ O9 N, m2 B. kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 ~. }7 G% Y% p' f| MCASP_PIN_ACLKX
* @2 L# m9 w5 {$ i9 A| MCASP_PIN_AHCLKX+ k Q" A5 I7 r" Q+ n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ e& C8 R6 d: V( @+ sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / Q! y' Z7 M% ^) T
| MCASP_TX_CLKFAIL ' R% {* T0 d' I5 m
| MCASP_TX_SYNCERROR
' n' |, \$ \* Q9 W7 J0 H3 w' \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( Q0 X/ f! q- O: }| MCASP_RX_CLKFAIL
: L& {; v. }" N| MCASP_RX_SYNCERROR ( W6 w4 h* m1 P8 F: a9 v
| MCASP_RX_OVERRUN);; J1 _0 T6 Z A3 j( p7 ~
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
* F5 h2 o. d, ^5 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) s& z, m3 P8 w- c: IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" G" D* ?" _; r6 v: b1 v! c4 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) q. Y& E6 m; Z( l9 L4 E4 _
EDMA3_TRIG_MODE_EVENT);1 Z* ^, G6 B. C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % B# ^' _) _7 w$ A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 L2 i( }, Z) g) a/ U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 I2 m: n4 L3 R1 W( S7 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 G0 l2 |% k+ \1 G; I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) d0 `8 h7 z! uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
{9 w0 x% r/ V1 a8 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, m. N" v7 P8 i& X3 }% L6 ?} 9 K, |6 A/ p+ p1 `# D9 x0 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) O" U( u! x# c1 e; H
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