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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 E& x m% \3 `) R( Z! j+ yinput mcasp_ahclkx,; Z0 @7 x a" O
input mcasp_aclkx,
/ v3 L* c; @3 p3 s: Zinput axr0,
$ [! D& R0 ^; C; e
6 ^; b$ a& g# U8 C( Q/ Z" Routput mcasp_afsr,! P1 _8 a( M9 Q% m) w" Y5 Z
output mcasp_ahclkr,/ t( i' e" K- \) K! L. U5 c. K
output mcasp_aclkr,: l2 N! w! o m
output axr1,
9 v3 O3 C: T( C. ^& N assign mcasp_afsr = mcasp_afsx;
+ D( l* a8 V5 c- F' \5 iassign mcasp_aclkr = mcasp_aclkx;/ t6 U: Q0 o' V- ]/ z/ S
assign mcasp_ahclkr = mcasp_ahclkx;" e( V- ^! H' z% a
assign axr1 = axr0; : v( L8 j( t1 m7 M& S7 _9 m
* n9 R1 z8 I+ y: `& q! _4 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ |% D6 l( }& p# ~! k+ Ystatic void McASPI2SConfigure(void)
3 J1 k0 k, m$ I' k& Q. b6 Q{5 l! p. Y# D( t$ L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& P B) Q9 @6 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: B) s! _* O9 b KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" P0 b4 S4 I7 |( O* D1 K: YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. n2 } v% y9 B9 ]0 Y* A3 ~, vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 d" L) P1 b# p4 I! q" eMCASP_RX_MODE_DMA);3 F) z1 M* E3 p& l+ j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& _( v0 Y4 Y' Z5 ?% U2 U2 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; {$ J, O( i) \. I* n6 }' BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' j! I& P* }5 [4 M3 z, MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- x z$ D2 e& C, c- h3 g7 B% J+ w( X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - f* F3 G! ?6 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! {6 D/ H- T1 q y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 B8 X8 E3 z0 r) p1 v, y* @0 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) n! ]: D' v9 p( DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 r2 u+ P' W! @4 e' T- v2 |
0x00, 0xFF); /* configure the clock for transmitter */- h" N, x+ ~6 E( K- | l$ Z+ t0 Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: ?; d! t0 u& ]4 h. j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% Y$ g; F: ]" s$ J7 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ \7 j2 u4 ?, p! f: ?9 Z
0x00, 0xFF);
1 a0 d. L4 { e3 W0 w! V' v2 ?5 t( u" q: m4 Q
/* Enable synchronization of RX and TX sections */
6 L U7 k$ m& X/ LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ F4 j+ B7 I6 m. ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% t) ~) H3 q" r# \0 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 P% y5 t e4 I, T** Set the serializers, Currently only one serializer is set as
: M1 C; t } _/ u% D5 ?** transmitter and one serializer as receiver.
' x0 J5 s# V/ _" Q! } u6 |*/
/ C5 c+ B" o0 S' o! B1 D2 IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 {6 u% Q1 L; o) Z" l" DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# {4 W( E7 o* k. D4 Z** Configure the McASP pins
$ I' j$ U8 [ I9 u; W** Input - Frame Sync, Clock and Serializer Rx
. j; V* O0 @' H+ K** Output - Serializer Tx is connected to the input of the codec
$ K/ D( R) F' y5 U% g% v*/
% u. ?3 s* B s: `6 f' K! I; Y9 x, Z; QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- G0 d7 ^9 P2 d8 z' e+ Q& t0 R8 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% N* j' a! I5 p0 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) s, E2 M7 X# i7 M$ J# y% s' q| MCASP_PIN_ACLKX
8 W/ `+ P d" f- h7 T4 T- k" j| MCASP_PIN_AHCLKX
7 z8 ?' C& o0 C! y' H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! m; \ s. J0 S3 ^- F E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 Y& {0 m. H; x| MCASP_TX_CLKFAIL ! u9 V( @9 ?9 O4 _1 f
| MCASP_TX_SYNCERROR: \" U5 K& L# u0 j: g+ S4 a3 s9 X% Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / N, w, R5 X7 G: b2 k# g
| MCASP_RX_CLKFAIL
" R4 @3 }. B& J. P& a: w+ L V6 @| MCASP_RX_SYNCERROR + U5 f6 y& u1 k; r5 G# v
| MCASP_RX_OVERRUN);
2 y: S5 U# s% ^! z2 j$ p; O5 x; @} static void I2SDataTxRxActivate(void)
. O8 |8 V$ r5 E& n- @{
. l4 _, F6 { w! l/* Start the clocks */5 E: ]. }5 ^: G* u f& M. E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 A2 ^+ j3 b% V( ~. o6 e HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ _, F( i; x6 H z2 t7 B: T5 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 ~$ W/ S0 j9 ^# k5 h! TEDMA3_TRIG_MODE_EVENT);
% Q" [: X( r p W* jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 z9 \4 B) x6 w: F7 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% S" |4 U0 A8 U' t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ Q' A% `" V/ d9 S6 _& kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& A" S2 C1 F% m' b% G# ?, f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 d. T+ B% j+ b8 h- r i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 f& x5 T/ K$ u# a; T- Y& MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" }' ?, x5 J3 s/ b6 I: n: Z} . b4 P9 A4 ]& w: |$ Y! u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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