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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 G% `* f, g) Cinput mcasp_ahclkx,
- H+ [5 M4 W; {4 K) l" t2 ?input mcasp_aclkx,
2 t7 E, W; ^) E3 a7 pinput axr0,' e* Y8 o. \1 i3 S- M6 K! {
* I: [9 Q* V7 R% houtput mcasp_afsr,7 v0 e3 d6 M& B) B/ `# P
output mcasp_ahclkr,2 X& F' K, N) y- f, h
output mcasp_aclkr,: f: ^8 Y8 {2 w& \3 f
output axr1, N, m+ B$ h$ {3 E* b& \7 `) q+ l
assign mcasp_afsr = mcasp_afsx;
) h+ g9 a8 P2 [4 Q5 Yassign mcasp_aclkr = mcasp_aclkx;
$ P' k) d. @3 O8 Rassign mcasp_ahclkr = mcasp_ahclkx;: \! O4 M: ^" O. e, _
assign axr1 = axr0;
6 P' }6 d# i& Q; o2 A/ t4 @" s; Q7 [$ w, y; J8 z+ j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- M7 m1 Y N! Tstatic void McASPI2SConfigure(void)
$ s" l7 Z$ f7 n7 f" c{0 r. ?( q6 Z- O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 w. \3 y' A) m; \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; F; `- ^! _% T0 U% d/ t9 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, \( _/ I6 I9 a8 `; T4 f3 N5 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, L3 \9 C$ o; O# `( Y v$ O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 F- f5 d3 i6 J Y. v- s& q, {5 d" iMCASP_RX_MODE_DMA);, y- C& V+ l& P3 u5 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. h. i! \9 ?. l ~2 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% B% m. F3 F4 \3 [; i! N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. a: @. j1 i. ?9 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 T3 U/ W$ P6 I- Z, P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ n, u4 o$ ~9 ~2 t% c- E) ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* Q! H" Z3 n/ R* ~7 h: DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; z$ f8 `* L' lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 c* M( D2 q* X7 s8 ]! K4 \/ MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," |: I: {9 Z# Y/ g
0x00, 0xFF); /* configure the clock for transmitter */( v# f, R5 B1 U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& M; i, H& u; g! Y; n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 ]+ T9 S# T* c8 E" g8 f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 @/ D9 B% B2 n% o
0x00, 0xFF);6 P% o* H( \+ I- S) _
2 Z& P, L; L" Y% _9 b2 l N6 Q
/* Enable synchronization of RX and TX sections */ % ^0 Z6 E- k( [0 N, o9 K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: H* I1 ~1 [ E% kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" r) p+ w! a) ^* i2 c% k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 }; j3 F2 [" `, r4 L4 d9 }
** Set the serializers, Currently only one serializer is set as
1 j' E. ~9 T' a** transmitter and one serializer as receiver.8 @ \7 L% f& n6 P) q8 _. k* l
*/
+ ]+ m! u$ ^% _: L0 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 l, G3 W s2 v/ f# ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 a5 H, M, k+ Q5 w1 ?% O' `! k
** Configure the McASP pins ! ^2 K& N) T6 z! H% W- M
** Input - Frame Sync, Clock and Serializer Rx$ ]' G% q# p! J% x% B1 s
** Output - Serializer Tx is connected to the input of the codec % d1 f1 s! J4 ^+ }2 m, f1 ?) U
*/) e4 o$ g Y7 w& M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' I& k: n- ~$ {4 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 E+ i* m( P9 o4 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* u3 L2 g' B8 U$ z| MCASP_PIN_ACLKX2 M4 T! J: x: g d j) `' ?
| MCASP_PIN_AHCLKX
* B& h+ ?, w% q" [5 s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, B$ o% P" E, D5 p8 T8 z) G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + ]/ \* Z! T; o! f. y
| MCASP_TX_CLKFAIL
( L! W3 o' P1 V5 E# M| MCASP_TX_SYNCERROR6 y1 v7 c) p+ f: ^5 U# t; m5 X. _% s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
L* ?% v, Q0 _1 G$ Q D5 N+ E# j, C| MCASP_RX_CLKFAIL- J1 G {* R/ S
| MCASP_RX_SYNCERROR
7 E" u# @- k7 L1 Y9 O7 o| MCASP_RX_OVERRUN);) D. d" ]8 A" @! \4 \
} static void I2SDataTxRxActivate(void)) `1 a: C! u- s. v! Q+ T. F( W
{
2 P: t# @# j$ ?3 Z9 _7 w: h6 e/* Start the clocks */, U/ G/ {/ _' H, _1 u; Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 Q2 N Z9 G4 m1 s' c, X. Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// S% y- B9 i4 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 T$ M" ]* f" Z( Z: Z* g4 f
EDMA3_TRIG_MODE_EVENT);1 A6 y) o$ \# g6 S) ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 ?6 S5 W( ~6 s$ ?, W& k9 z; h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- h5 E8 j3 {6 xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# P5 I, S7 ?5 z1 h/ @: H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 g! _3 h8 m6 P- q. x4 u; g4 Z2 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( `5 |3 ?& H9 [ |; D1 s' U; q8 E( ]: Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 x. w) H8 {2 g- l$ @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; X+ i0 X2 k7 b9 g3 z2 k
}
5 C `/ l1 W7 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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