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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 d7 v- i _& X+ d1 g
input mcasp_ahclkx,0 X4 p7 t" }- Y+ u2 |9 J$ N- o
input mcasp_aclkx,. q8 ?0 E; P4 I* x: {
input axr0,# n* u2 O8 S( v, P( ~, I
8 O% @( l- Q$ F* R- Y+ [) T5 w" boutput mcasp_afsr,% |7 [% c$ X }$ n0 k, P8 {2 r+ e
output mcasp_ahclkr,
$ y6 _9 \" ~4 S8 d% ^+ _output mcasp_aclkr,
9 w- t* u+ s9 O0 `& Koutput axr1,5 g" ?4 }# g$ g+ A1 s5 j8 j$ w
assign mcasp_afsr = mcasp_afsx; h" P5 D! ], K+ p/ ^2 P3 K' L; {' h
assign mcasp_aclkr = mcasp_aclkx;) [" S* _, v- d3 K0 E
assign mcasp_ahclkr = mcasp_ahclkx;
/ E3 _$ R& k) |assign axr1 = axr0; 0 d/ t& I5 d0 l) W# P
1 \+ I: v* j4 a2 E. ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 }" J2 N) h" ^+ f# r5 L# o8 ?
static void McASPI2SConfigure(void)
$ d. a$ ^9 i6 z7 S, ]: c: m9 h{/ `. f) K( A) `5 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* {6 g+ X' n: G' s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. s- H+ i4 E0 e7 J2 _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, U- z! x/ a2 `2 i* M; ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ W: g+ \/ j+ X6 t. }) I; b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- W& I4 {5 d3 z# a2 E3 }, `, S& }1 MMCASP_RX_MODE_DMA);
9 q7 ~# }! {: C0 P- u+ Y; ?) gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ M' n6 V7 Z( X( D3 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 l7 L/ X# k9 O+ ~% S1 L4 Q! h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " H5 ~7 j- ]6 H8 } F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; t% D4 n% O7 {# P( P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# |6 |; f, ~) E5 _* kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. k4 f) Y: y. @2 v) g6 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" }7 a$ U, l! K, }8 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( A# ^5 ^7 T" [0 f, L8 o* ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 T- X7 c! O3 K+ \' {& ?0x00, 0xFF); /* configure the clock for transmitter */
8 b3 p; F. ]* G9 \1 ~0 c2 `: t5 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- E2 i) `6 s, m; q8 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ C& k0 |4 g2 a7 |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 s7 n9 ]" N( X0 M
0x00, 0xFF);' r$ h) A u/ |4 M
7 H% `3 D3 _( M- Q7 l$ T& w
/* Enable synchronization of RX and TX sections */ 1 a( \/ a- q6 [& \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: v2 y+ P, d: A% b( @% N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" \; T" h: x7 P) q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 z+ o# h% s# O/ T/ T* m) R1 a
** Set the serializers, Currently only one serializer is set as
?7 b" d- d6 r9 c- B v% [( g** transmitter and one serializer as receiver.
$ v7 W3 B6 G. m% h l4 O1 D) b*/% j" W; ]+ \+ w( U* h8 i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* p/ t1 W9 b! D/ k* `5 C W* fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" f+ j3 L# Y5 w t4 W
** Configure the McASP pins
% D( Y: p' ~" z/ N** Input - Frame Sync, Clock and Serializer Rx
6 U0 j; m% G, P** Output - Serializer Tx is connected to the input of the codec
6 Z& B3 x: d( o*/. k& `* ]( t5 w# V2 X) K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* ~5 V- y7 m, y1 F! |& |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# v. I! j) t& g0 h8 H0 {" u p7 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 I7 g0 R2 n/ ?7 o- Z* T% k. I
| MCASP_PIN_ACLKX& E6 f2 s1 [5 _0 _- G0 F
| MCASP_PIN_AHCLKX
5 F U3 K2 m+ q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- _, Y2 U V7 r0 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : a1 _* T1 U% P* }" L8 c
| MCASP_TX_CLKFAIL 3 S9 O$ c v6 q2 }. z: P
| MCASP_TX_SYNCERROR! P/ B1 b( i! S! c0 T1 a( }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ R6 z! d! n: h5 _& d| MCASP_RX_CLKFAIL. z; n' b7 e& Y0 R7 X. D1 r
| MCASP_RX_SYNCERROR
?5 T7 [# j* p4 X& l2 S. {| MCASP_RX_OVERRUN);, k% U8 @* B+ C
} static void I2SDataTxRxActivate(void)
4 X5 Z% r; M3 D' T* e9 d% P2 W! N{; S% E0 E$ A( k+ f
/* Start the clocks */
# `& a9 h; T% u# U; Z- zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( J2 R2 H7 ~1 ?. k( ~5 SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 `$ D* \. Z2 E& R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ E0 z% i L3 K9 d6 pEDMA3_TRIG_MODE_EVENT);
+ v% G& h6 I) Y- P3 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / y3 K9 o6 K7 o1 S/ X% [1 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) n" m1 e6 q$ J8 } z) T2 X& ~: _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 p% y9 }) v/ E ~* }4 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" z8 D+ q6 U: @, F- Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( I& O; }( S% E2 b# O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" S( e" e: K3 A* fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- ^6 r6 N; O, {}
w9 c, o2 @. g5 r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 R% ^1 k" P0 W( y, { e0 b3 K
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