|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& J6 W9 K- |& O9 {3 V7 Ninput mcasp_ahclkx,
( ?; D1 F7 {: l) d5 kinput mcasp_aclkx,
4 c' n3 r/ x2 ginput axr0,- f) W- O; n" R7 Q4 d! c5 \
7 K5 S! o% I" t# p" B+ Foutput mcasp_afsr,
+ E* z9 }# ~1 D2 i `# V6 noutput mcasp_ahclkr,
2 f5 u! w8 v- H$ ioutput mcasp_aclkr,- D) Z2 T! o0 G0 d o* M1 w
output axr1,
8 v9 J& J% z' y0 m8 z8 G# n, I assign mcasp_afsr = mcasp_afsx;
& @! D! D& x7 h6 [" C7 p/ Fassign mcasp_aclkr = mcasp_aclkx;
. D h6 n* E0 q2 C4 u! u5 Yassign mcasp_ahclkr = mcasp_ahclkx;
1 F* W* b3 V" g# H" }, Z4 l/ Q4 qassign axr1 = axr0;
1 ^1 b6 o' |& e% U3 A6 f& w; M/ i6 L. x+ B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( ]" z9 X! A3 x4 {& I
static void McASPI2SConfigure(void)
3 r8 Q6 X- \, Q' Y{
' m4 A; [# M+ l! lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 G; k! i1 |) L' P; |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 J' P) Z$ ]4 ~% wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 J" y! h% i1 e$ o0 k8 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% m3 q' z. g7 Z4 \$ `* n0 r+ }5 m; d5 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* t! k Y* }2 ]; G' w/ Z2 V) FMCASP_RX_MODE_DMA);; y: u! ?; y$ a0 L" x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. g& |" I: s4 c. v* g4 x( |& ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 Y8 X* q8 W. t3 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' g! P& o7 }% v9 N7 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" o# |7 j/ i \( }0 c& }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& p( F- N2 v' a. V( t7 MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ H5 E7 J, t! l( g; P7 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! q w# o+ a1 d. }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ l/ A1 c" j% z8 F5 \/ I f+ vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- F4 T& u. T0 T0x00, 0xFF); /* configure the clock for transmitter */3 y% O. x) S% I" X! Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 w+ q; }8 L, H( d3 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, g& s1 k& N# }! p; `/ nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! @; B1 V' P o8 p% l0x00, 0xFF);/ I# z8 |+ t* R! j- Q: ^' x
' X( S5 B9 y3 S0 z/ g/* Enable synchronization of RX and TX sections */
2 t$ [2 b" A" r6 F8 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: E- z) k1 c- @1 fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 b* M5 d1 N$ `3 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( E: ^9 h2 @, k$ h$ q7 C3 z; w
** Set the serializers, Currently only one serializer is set as
$ m2 S7 x/ @; k6 K2 m5 [) J** transmitter and one serializer as receiver.8 _1 |# V6 F5 I" o5 \+ d
*/, w; n6 Q4 h) n$ k v- A E$ ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 }# ]3 L1 }" G( B/ c0 v+ {) M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 g4 L3 K& x* E0 E, q& c- v% U& f0 @** Configure the McASP pins
$ I8 F0 v N& {% ?4 Z2 u** Input - Frame Sync, Clock and Serializer Rx1 f. g5 C6 b( @* k6 w
** Output - Serializer Tx is connected to the input of the codec , \! Z3 ?# \# T& ~2 @3 {
*/
1 A! I R# ~ a' n9 AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 r+ O$ Z2 o, x1 y' T8 j3 e# A7 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* R, @. [/ p! I; C# X" S0 R6 E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! N' y- A2 V9 H! `| MCASP_PIN_ACLKX x! h. R5 J) [* b$ e% @
| MCASP_PIN_AHCLKX. s, u- h* H9 c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 x( H+ ?6 h2 s* l+ N' J; E3 L/ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 d6 A: Y- B% E( y$ h4 C6 Y e| MCASP_TX_CLKFAIL ; `# z* f X" v5 x! H, U
| MCASP_TX_SYNCERROR* C! u/ ]# m3 A% m+ L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' V% ^6 L# i0 g! N z
| MCASP_RX_CLKFAIL
$ x" \! b# L2 K" f+ W# [! p| MCASP_RX_SYNCERROR
- [ ^5 c# j; Z0 M% J5 [| MCASP_RX_OVERRUN);8 g# h$ q% h1 X; k3 E( @; @
} static void I2SDataTxRxActivate(void)
6 ]: C( b* X: \9 ~& F; w% R& s{1 }* F7 g* e: h
/* Start the clocks */% a# G2 q/ ?3 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 I* @6 W% S/ k, W4 z" P% }" [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; `6 a3 V) C2 B0 x3 G1 s7 C; z( q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, ~ _6 F& {! \! C8 W% y
EDMA3_TRIG_MODE_EVENT);
+ [9 _: `( x* B; N6 E. n6 `) gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' F* q* G! W# [- l3 b2 e# u5 Z! S- q' Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) J4 s- x5 N* D- ~& i4 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% G( Y/ c+ y( l0 y& Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, T/ w, R) ?4 b4 k2 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 k+ L# M4 ]; u. gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); c$ g, f$ w! t( m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% R6 z' T' m8 [% c# k
} & |9 z; x) `6 ?- I3 { t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
1 A- X) I! U U7 C0 z; ?* _ |