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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ o( q# t2 i! b) A
input mcasp_ahclkx,: s4 V1 h' c \0 J/ Y* ]
input mcasp_aclkx,
* s: B5 \/ l+ Vinput axr0,4 w9 {( f2 S7 J) M
Q1 `7 J H: P3 B; w3 M
output mcasp_afsr,$ n9 K. Y3 ]8 c* {7 |
output mcasp_ahclkr,
2 V8 }6 a* H1 \ uoutput mcasp_aclkr,% m Q1 n; P! l; Z2 l t0 z
output axr1,
. t/ Q& j% f1 U) J( f assign mcasp_afsr = mcasp_afsx;9 E4 \0 p9 ?. O, }& f) A
assign mcasp_aclkr = mcasp_aclkx;# I+ y; X* q- }; }
assign mcasp_ahclkr = mcasp_ahclkx;0 u- o0 Q) V2 @
assign axr1 = axr0;
$ _& S, I) H% S
- G2 p3 X$ e# ]- _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! `8 t% X. _% W' @
static void McASPI2SConfigure(void)) X! O+ ~+ s" P( y0 m3 T$ q
{9 ~' {" n3 H3 X' K4 Q! l0 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: [! [& r y/ M5 @" G) HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// v5 v( O R5 n/ e0 L, w8 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. x* k% T; m2 m) K' X; z# }( S' }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- j/ U2 D) n& PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& o$ [7 A9 \$ f4 f0 @$ ZMCASP_RX_MODE_DMA);
' z$ K* b" p/ f" ^$ A! jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 P! }& [3 i! j% T2 J8 i" j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) R: |" @( u& l/ |+ o4 K/ a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 k9 ]1 j/ k; EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 S2 p' Z. }/ n. z- b' o2 q8 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # [4 b3 B3 J9 G% U( c0 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 B$ {) g+ J7 a( a( j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 w+ U! F) Y. l! _) P# F$ A- f8 {6 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& g2 C' p7 J3 z5 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) v& {- d) i: ^& s3 r; A7 ]$ U9 A0x00, 0xFF); /* configure the clock for transmitter */
8 J( R: S) z9 y7 o+ _! E% B t/ MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* |) |8 P9 r8 O+ i/ d$ ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % g3 j8 y) W* X: H7 I5 N, ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 l( d# ^. b( t) k4 Z2 n* X4 r
0x00, 0xFF);! E7 M" e; f) k/ G5 F! i! N1 z
* h6 q; M- l+ y5 z( B- C/* Enable synchronization of RX and TX sections */ ' F3 T+ W" x! e5 v; i9 B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% u# B* _# n$ \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 u h4 J5 P) I3 d4 R8 [' NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) w+ W) H3 V( J' J1 Z: H$ w- f
** Set the serializers, Currently only one serializer is set as
# `3 c" u$ `7 e+ Q** transmitter and one serializer as receiver./ W6 G% f* t3 b5 C6 f
*/, M; j0 |" S& L! e" x. E* M, J/ C) K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 a& C* T1 C0 d) o! BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 |$ L- r- c' f5 b** Configure the McASP pins : |2 h- W" f4 n
** Input - Frame Sync, Clock and Serializer Rx
5 r" ?, R6 r7 ~: A* F** Output - Serializer Tx is connected to the input of the codec
" b9 v3 l5 X b5 `*/
9 d) ^; {) T" JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 k) g+ i: r* T- r' N, e( B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 z L' q0 V( i5 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* R" Q, [5 s2 s1 O: Y/ Q
| MCASP_PIN_ACLKX' G, }' w$ d3 c
| MCASP_PIN_AHCLKX
* S! _$ k* @) M6 m4 U5 O! ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ [: D$ X" p4 F1 [% x3 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 S. }. V# L' K2 t* u; \) ?
| MCASP_TX_CLKFAIL
4 b! U- {5 H; U8 Y8 {' f: L7 l| MCASP_TX_SYNCERROR* C5 I( G1 J5 y4 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& V- S. W* A7 \3 J| MCASP_RX_CLKFAIL
& B, w. K) W! _ S$ H$ W| MCASP_RX_SYNCERROR ' E& ]: V: t! [
| MCASP_RX_OVERRUN);
9 ^$ `: ]2 N. z& z+ t! c G: k" B1 B* h7 ?} static void I2SDataTxRxActivate(void)- M( \: y2 ~0 g" O
{* H5 F/ S" r* }/ P% ]9 s
/* Start the clocks */
8 b0 l' g$ i+ Q* dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ b5 I d6 z( O3 |- N9 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ H* Y7 }* ~. K% U% ~8 e' C0 m( g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' Q% ?% I8 p; Q8 E( F* e
EDMA3_TRIG_MODE_EVENT);" C* s# ]* P$ X# n+ o) L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 _/ {: P; O. Q$ E; ?; {; T( @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* @5 K+ q5 |2 m+ I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ l/ o3 z. k2 f* j' J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& S- C( o7 B! v5 q, \9 K% `" gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 A, h) S R( j+ S. t: ]. Y- t. W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! ~0 P) M2 Q% |) MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 x, ?+ Z3 @: d7 z} 5 U& J8 ^1 J9 M9 f2 h( D& X/ s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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