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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 c" I5 n0 U! e; M1 z% _input mcasp_ahclkx,9 b: A6 ?& B- _2 r2 c
input mcasp_aclkx,* E( l) [8 V4 B: g1 \
input axr0,) ^* O% U% V' D' F6 e
9 \$ v& k9 a3 c7 n9 p
output mcasp_afsr,
: g( g; B' v+ r5 J: x+ ]output mcasp_ahclkr,! Y' D, C/ g6 ~7 A+ D" a# c1 t
output mcasp_aclkr,
9 |" e& N: V0 L! L8 xoutput axr1, B+ s! D* y3 A& r2 u
assign mcasp_afsr = mcasp_afsx;% K* T4 P$ w" W4 D( f
assign mcasp_aclkr = mcasp_aclkx;, V0 E+ e S/ b( @3 l9 Y" `
assign mcasp_ahclkr = mcasp_ahclkx;
9 W, r) w, \; e+ v- s1 G9 zassign axr1 = axr0; , B# m) X3 J8 c& D3 V" z7 {1 o, V
8 G2 W0 ^. w$ c& \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& |5 |) ?' T3 z( v$ R9 z. i5 U6 Y* Ystatic void McASPI2SConfigure(void)6 x/ P3 u' H# S" W/ s3 v {6 Q
{& U+ k4 X' G) R5 G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% a/ R' ^# l" [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* o) Y ~/ T( S! k/ x `4 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 n& N/ Q* Q0 F9 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ m6 m) T8 G0 [! \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' g& g+ j" ^8 Y0 d, n
MCASP_RX_MODE_DMA);
# R- S3 L( f; L2 s, \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, H; _' {# w, m$ l5 U: qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: f( J- h6 i( N/ f! v: g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' a+ c4 j- Y) V q) c& W* W+ Y1 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 x' _: Q5 k5 g p4 R$ ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ Y/ i. g- Z3 `1 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' |+ @) E+ c. q& K! ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 f! s9 k9 I6 W: R; }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 X2 }$ D% v+ v: n+ t) iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ]1 l8 e Z1 t, b% E) b5 Q
0x00, 0xFF); /* configure the clock for transmitter */* @1 ?0 Q! w9 ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! V2 T, b+ S" n+ ^. X: ?5 m3 H5 U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! G* m) N4 n0 N0 p5 d h. d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" Z& H1 `. L" k% F& {6 B0x00, 0xFF);: a- U& I8 F$ A2 b' A4 g
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/* Enable synchronization of RX and TX sections */
! t8 ?, x1 i8 |$ }" NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* [" \* t$ b) V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 @2 f8 J9 b: Y" i c3 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ v' ?$ z- k2 f0 J5 Q# ]( R** Set the serializers, Currently only one serializer is set as" |3 D$ d" ^, d0 R1 V
** transmitter and one serializer as receiver.
4 e8 _3 _) |) L9 D2 @* O; U2 {' q*/
0 Y1 P( |8 u: H, T! q8 P$ _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" y9 ^9 j0 A/ B3 \' S- RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
U a" s% t+ A2 Y5 T** Configure the McASP pins & S+ ^$ w/ R0 P2 B% k
** Input - Frame Sync, Clock and Serializer Rx
! W/ U4 Z" T- h+ d- \. g** Output - Serializer Tx is connected to the input of the codec ' E) ^6 t' F' Q/ F
*/* e) K H1 V; \6 L$ [* |# P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# B1 V1 a% e& y0 {# {- E7 d" i& L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' Q& L' U3 m! H* c4 n1 U# }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 z3 b/ q4 e% W
| MCASP_PIN_ACLKX
& d; g6 E1 a8 _ F| MCASP_PIN_AHCLKX1 C+ `6 f4 f K7 b0 ]9 a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% t' Y; p' l# w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) a) C0 P8 ~( P g$ c6 _& `| MCASP_TX_CLKFAIL
- |4 e5 N/ Z- g| MCASP_TX_SYNCERROR y5 m `8 v$ z( G( w# C+ S1 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ I: d7 ~8 s) ~; `# T/ a9 w7 [9 p# I7 g
| MCASP_RX_CLKFAIL' Q/ V. U6 M" \, n; E
| MCASP_RX_SYNCERROR - ~* x) E/ y- O: u$ {: e9 _2 V, p
| MCASP_RX_OVERRUN);, s4 @9 h3 e! l- t* @
} static void I2SDataTxRxActivate(void)+ L, t' t2 Z' e( K1 U6 {
{
) r* p: V' a/ c4 ?/* Start the clocks */
4 ~1 ~" K3 d1 AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ L# _1 G7 V: g& v& N# ?7 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) `4 c6 c; F" W+ I8 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 ]/ K! z+ ?0 V0 ]+ ?8 A5 m
EDMA3_TRIG_MODE_EVENT);
: ~3 y4 a7 P4 I1 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 w) m7 c; t1 S9 O$ CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 R) Y7 C6 a! N! S2 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 R V2 `" Y2 s3 S' E0 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 V, y, D, y/ R4 L% m: Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 s8 E. c9 g0 M' r* J/ Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% D/ ]6 ?4 V5 F9 F5 f2 j7 A* g$ ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# G/ {" a) k% N2 `
}
" v' `* @0 Q- i8 ^( r. f& A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 H% O5 |2 J( A0 v/ C
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