|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% O' F- C& I1 ]7 w, R
input mcasp_ahclkx,
b+ [4 X. Q3 \1 V3 \" c* B8 }input mcasp_aclkx,
5 l( t' H# j6 ~- I" `, hinput axr0,
* g7 R& l& x8 b; u6 A% t* L) Q5 g
output mcasp_afsr,
* Y2 L8 {) J9 Noutput mcasp_ahclkr,9 ?' j2 ]1 O0 `. }2 s: F+ I+ V
output mcasp_aclkr,4 h8 O$ }7 W/ T. V3 _5 b- q- l0 D( ~
output axr1,4 R- J* g+ ^1 n! i, D. z
assign mcasp_afsr = mcasp_afsx;! W+ B3 s# Y+ D$ [7 g
assign mcasp_aclkr = mcasp_aclkx;' `! `$ o q/ h. y- B1 R' {
assign mcasp_ahclkr = mcasp_ahclkx;
: h: r( J; l9 B$ y( passign axr1 = axr0;
. \" V, v6 l+ c' j
2 G0 B+ J* C" j; {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 f1 H0 @ k x# Z& ] ~
static void McASPI2SConfigure(void)+ T) N& d! i* \# o
{
# W: d: m, r6 R+ v! ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ o- G0 W& w" O. M) gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* S+ h M, J( G2 ?! z7 @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; t% U; k# H: Z# l" {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 Y2 l% T6 ]. _2 tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ~2 F' d, `* e4 y
MCASP_RX_MODE_DMA);
3 g; `. F# H% X8 k: f: KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; x/ j4 G$ M: {/ y; ]* p3 Q( l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// M; I% `/ @# N9 r/ f4 ^" b; f; |1 d1 _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 u# O/ l8 r1 Q0 u" z% Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
i) F2 G1 X2 l3 b, DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # h+ \# t: K3 }4 K8 J6 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// {9 _6 v7 D$ j D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); C; o& a2 l* ~" N( P; p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , g3 y5 B2 ]/ ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 U: M( L" A5 m0 x: |7 }! r0x00, 0xFF); /* configure the clock for transmitter */0 B2 J* x7 A( l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! S& s2 Y c7 \7 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. f+ |, g+ }# i0 {* J, [# PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 ^2 M0 o) U1 m
0x00, 0xFF);
9 x' K; h7 t8 V! O- r7 m* o: I; `; U$ g' ]4 T$ ~4 m' C% n4 K' ~+ ^7 \( b3 S
/* Enable synchronization of RX and TX sections */ ) M/ t4 B9 l5 E* w3 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ w! h# \. T% r$ ~7 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% j" Q6 w/ c U1 Y7 j6 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
k: B; ]1 j! Q' C( ~! {** Set the serializers, Currently only one serializer is set as
5 {# Z5 F, O5 M( |$ o1 j5 \** transmitter and one serializer as receiver.
C5 r5 H9 m- H9 W# }6 k$ R*/9 c; }: a" C; l, T, n' {# d* p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 `$ x9 i2 e# k+ u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ U6 g8 t: s: t$ A b; Q
** Configure the McASP pins % ]7 u9 Y# o/ |- [, ]
** Input - Frame Sync, Clock and Serializer Rx) L: r- |+ `# z& p! S2 o
** Output - Serializer Tx is connected to the input of the codec ! J. o% t, t( G; U4 i/ H
*/' c" I" y1 Q$ u2 `0 Q2 W: a$ k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 l% }& b& }. o5 T$ z9 T! c! K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; s/ M; b) j$ E( w# j5 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 {( f) o% x* j; U2 \9 J| MCASP_PIN_ACLKX7 Y" D( n3 n! P
| MCASP_PIN_AHCLKX/ ~2 f% U; b# t y- y2 l8 J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( U( S- l! r% U" ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( I8 O8 q" L9 f# ~
| MCASP_TX_CLKFAIL $ X& G+ n+ X) a+ _ ?
| MCASP_TX_SYNCERROR
. r6 N. X. M+ |2 f" Q& d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 h7 r ~% C" C7 a2 n" A| MCASP_RX_CLKFAIL& T w+ t% \- s. l" S
| MCASP_RX_SYNCERROR
- P K( [2 N$ y| MCASP_RX_OVERRUN);' |0 z8 b. H+ B3 `5 \- C
} static void I2SDataTxRxActivate(void)/ h/ D$ F+ M; U* r3 E
{7 _4 v8 P4 j2 I6 m6 c8 {' r
/* Start the clocks */1 y3 t2 w5 M1 G! F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, m4 A5 ?, f- P6 H5 ^, S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: |) F& l( w' N XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 e- Q& b! S1 i) rEDMA3_TRIG_MODE_EVENT);
/ S, b; |& A* v# ]" aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 U( U4 N3 d+ f* ~# z) F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ y- V! a" k9 R7 B( p3 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- z) L$ \. f7 ? G$ u. hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 ^0 u- a9 }2 K% e- p; m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 D9 E5 Z# i, E! `8 e; m: F# r$ x4 n# ^3 cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. N2 w& K, u s9 E) ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 M' r; V+ N8 x7 l2 G' z+ B
}
$ u/ b2 o9 @2 h, O, a F8 Z& d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 _! w" g. z- x2 ?! l* ]
|