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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( m4 J5 j3 M2 h3 n3 Zinput mcasp_ahclkx,% y% l a* x! ?! g& i' j
input mcasp_aclkx,! s0 ]0 ?. B0 b: G3 u2 y
input axr0,
% o1 t# E4 R3 U* y
. Q9 o" }8 F$ p1 h q Joutput mcasp_afsr,( [( ^7 O- d: Z' F; i5 p% P
output mcasp_ahclkr,
- M! e7 d/ Q* H( ]/ houtput mcasp_aclkr,$ { C" ?+ z, f. @& {) }1 E
output axr1,% B4 [1 x- Q x6 R L# e
assign mcasp_afsr = mcasp_afsx;
: {' i* G; t! tassign mcasp_aclkr = mcasp_aclkx;* j4 X5 m8 I6 F
assign mcasp_ahclkr = mcasp_ahclkx;
$ I0 E2 T7 U# P0 passign axr1 = axr0; 7 h! q/ p1 X* a6 B, r
7 L& K6 o: r; r) m y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- N4 @( E L3 Q5 t# m6 o# vstatic void McASPI2SConfigure(void)' t+ q- Q9 L; G" S
{. k8 J/ b3 }0 I6 B' Z! b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' S: e! G1 }( U& p, h: |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 i$ d" E& K7 g8 O. U& g5 f' cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 \+ }: L) P9 o7 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// Y) q: h, l$ H3 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Z5 l! D' U+ _/ k
MCASP_RX_MODE_DMA);$ T& Q9 c9 z: I1 k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 K7 |* j6 c# `/ _* }8 y# r6 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 t# [5 k% L- qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / v( b/ y+ e. ~9 l& \; M' j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 l T( v! v$ W& r4 j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 U2 O5 T/ P4 B6 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ F2 t# w8 N& P# \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& W$ k8 R' f" k6 k& a: K5 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 K3 }% L/ M% u$ {0 g+ D1 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 x: O% L& r; m: e! F
0x00, 0xFF); /* configure the clock for transmitter */; w/ Q+ G* B. Y; I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& A, R; |1 u) f2 D* Z' G4 m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% @5 G) v C+ P7 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 T* E0 U1 l: B+ p; ^
0x00, 0xFF);
/ U' a M7 w/ C2 j
$ Y3 r; q) @$ }$ C3 s/* Enable synchronization of RX and TX sections */
3 e4 G0 G E6 ^+ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ]4 {" R2 L, K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# x; ^5 G' [! F1 f5 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ R4 V$ \5 E) R. q* e* W0 f** Set the serializers, Currently only one serializer is set as( |/ v0 J% T% r7 l& c% k e
** transmitter and one serializer as receiver.
" p6 m E3 o U/ @* L; W*/
1 [1 t0 S, P1 f( |* T( L& G# EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 P J* u" X b" m5 z7 T* u3 f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ n0 n; S" A/ I$ ?! g** Configure the McASP pins % [: q* W8 I g9 l
** Input - Frame Sync, Clock and Serializer Rx
- @% |; v( _& n1 @: w** Output - Serializer Tx is connected to the input of the codec
+ j$ S1 Y9 c; h*/
" N( n% s( i0 P2 {5 k! d) V* ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: s% ~4 U ~1 h$ }0 |3 aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 I0 J8 b4 W3 b8 X+ l- Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' q$ x* G% e6 j/ h| MCASP_PIN_ACLKX+ v: \$ U2 p: M2 j# ?6 u8 c2 d
| MCASP_PIN_AHCLKX
) _6 j% a) }5 X8 J7 @1 e* u4 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ Y- P% q0 S, u6 h1 C9 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( ^! [ x. y( h( X0 G- `3 v| MCASP_TX_CLKFAIL ; D" F: w; D/ h$ r4 y" v! \! l9 I
| MCASP_TX_SYNCERROR
: W" V* c7 z. a3 c% a- ]8 S* j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # Q: i$ |. W1 W" h+ X5 k7 u+ l
| MCASP_RX_CLKFAIL
+ C( ] @# F% E* X| MCASP_RX_SYNCERROR
; r# C8 F S# P/ V| MCASP_RX_OVERRUN);/ F5 [5 H0 W: @$ H. f
} static void I2SDataTxRxActivate(void)7 M/ d) ]' m/ ~0 U; |& X
{0 l+ b) Y. |" `
/* Start the clocks */: F9 L" G g+ c, `" w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& n( S) Z$ `: c5 X# Z- h A$ l7 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 b/ @* t% J: O, P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 t! o7 d0 K$ G' h5 E) hEDMA3_TRIG_MODE_EVENT);
, W# X3 D3 |. ?& x LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 ]6 X. r6 p+ h& e/ a- g* v' ?2 i( ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% y4 d3 m5 e( P2 S% X4 {- u. f' B& [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ y7 ?0 p* O" c |. KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, H8 [3 H' H$ C3 D mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// }5 e* ^( c. p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 k' ]: |9 ]* x9 F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* U I! v% I0 d0 f) H3 J} & f: t5 n' `2 y) ^+ E" g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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