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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* O; u8 x. V5 L& Q2 [
input mcasp_ahclkx,4 ]$ R3 U+ g' ]) A
input mcasp_aclkx,
% X( f5 y0 v8 Qinput axr0,
; W1 ^! c% z7 `6 j! ?3 e3 f+ M
output mcasp_afsr,7 O, J5 ?" {& M
output mcasp_ahclkr,
) m8 y7 T( G V: voutput mcasp_aclkr,
* @1 [2 v/ _: l& [7 ]+ loutput axr1,% ], O, O1 y8 g/ \5 X0 C" z6 S
assign mcasp_afsr = mcasp_afsx;
4 w2 Q, u1 V4 }4 J* Wassign mcasp_aclkr = mcasp_aclkx;
' u. j( f, Y2 }/ p! a) D; xassign mcasp_ahclkr = mcasp_ahclkx;. k; I- \9 m; `4 o' j+ v5 x
assign axr1 = axr0;
9 Q+ ^- A$ g4 ]0 u' Q
5 X# ?; r% E% w! ^4 V3 @. ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 S S2 \+ r; n+ n. w4 xstatic void McASPI2SConfigure(void)3 o5 ?, \) S) w ?
{
9 B2 l) i8 |/ I% M, ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 a1 ], z0 r3 {. a5 h; P' Z7 r7 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) s3 U7 L8 r" u+ n. R, B" ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 |( g' F" D# x/ yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 E/ q/ ^) O% ^* z1 N8 Z2 ~; XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 L/ P, H) C: A+ h2 N- L Y3 X# f" T
MCASP_RX_MODE_DMA);
0 S" u5 n! [5 c; j; q$ P: MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 t4 c1 b* z$ W1 A. i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 K5 }- C: J* F: U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 i2 E4 ~2 I: a0 [8 k& y$ @0 w; ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 c7 K& \/ X8 b* CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % W) l0 G2 ~6 U% o8 g) u6 q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: R2 u- e+ \% P2 w, s9 J8 l$ FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" G$ ^5 c2 J8 Q3 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; A; n, J: @$ w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 B) q& W+ T& g% X" @0x00, 0xFF); /* configure the clock for transmitter */- N# X% C F* Z$ R5 S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 c* a% q7 [: L' _6 }1 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . C6 g! ^/ t+ n/ M( `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, @0 E5 V) ]5 C0x00, 0xFF);7 J) _ u. V' t4 C
6 ?* s8 q) e0 q1 p& P4 V7 n N/* Enable synchronization of RX and TX sections */
1 ^8 G4 S( i' WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// l+ P8 @4 N9 B- ~6 a. |) T2 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 K& w0 O8 X V [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! ~' @- n4 U3 v! ]4 j( w3 s** Set the serializers, Currently only one serializer is set as/ h1 @) E$ K$ a9 n7 W/ H4 [
** transmitter and one serializer as receiver.& {7 p) s! b; C9 n7 b/ |1 _
*/: D5 ~9 f1 ]! F* x) W5 q4 j3 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% \$ _- K) q2 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 [* D$ ]) S0 B" p5 _4 Q% b** Configure the McASP pins # J; Q9 g# u4 V* x' \- c, Y
** Input - Frame Sync, Clock and Serializer Rx
- e* Z& S% h. V2 G) t+ ?7 y** Output - Serializer Tx is connected to the input of the codec ' U# m6 C V" s) K7 ~
*/# m8 s/ |3 y% U8 ?* g/ X" p1 u% B. Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 L1 m: t+ W4 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: K6 l' q+ P& m- iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 x: d$ C2 b& I/ t3 c. F
| MCASP_PIN_ACLKX
7 Z5 u9 j; x4 A' j* t0 R+ S| MCASP_PIN_AHCLKX
' Q- T( ?) ^2 {0 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 B( A( F1 k" M8 K9 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 ?5 `) v) }. Y6 x
| MCASP_TX_CLKFAIL
9 w" G" M7 d6 T% k$ g1 `| MCASP_TX_SYNCERROR- X3 O( `7 q0 @) q( g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / e$ i* n- b! w" Q4 U% Z& r
| MCASP_RX_CLKFAIL
- ~. ?( Z2 [4 `1 T" ?+ p| MCASP_RX_SYNCERROR
+ l2 Q! l. w9 u# A+ n' D| MCASP_RX_OVERRUN);
3 i3 k) c4 b l( p0 g2 y# J5 w$ W} static void I2SDataTxRxActivate(void)3 a% M: q B; x, U
{
3 V9 \ l M, t' b. K9 b/* Start the clocks */2 V2 z1 G; y- U& g/ n+ Q$ h. r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, d- ]0 G) h9 \' ]+ MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; o" y0 @8 A U# R+ L0 W3 t/ e( M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: i) f: T( K J2 L* zEDMA3_TRIG_MODE_EVENT);# d& L9 i' o) _5 J/ U1 K; e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % y0 q3 k, l r* j1 Z# \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
_0 L7 ?6 U$ jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 w( J- G3 l2 R0 O+ L/ s9 a1 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! x! L" J) W. @& fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# t2 L2 V$ M- @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 |. U2 I; X; TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 d' s. z$ ?0 K1 d* S
}
0 `9 B- _: M5 l! L. p: @( K q8 i6 F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! m- w: N5 X- T" G+ E: b2 f
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