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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 @1 G2 y! y+ E6 ]) m+ vinput mcasp_ahclkx,
. c9 _# o' A( W6 n7 n& Vinput mcasp_aclkx,* F( I: N1 {# O9 q4 R
input axr0,5 a0 T0 z. E' t8 B
# Q4 X ~% u; J% ?' y5 foutput mcasp_afsr,. F. `% R$ \: O7 @. L2 |4 G4 y
output mcasp_ahclkr,
; V6 F7 O: \& ~. Joutput mcasp_aclkr,
& K# f5 j4 {8 Z* H! Xoutput axr1,
5 {0 g9 Q# q, z# R0 L* @ assign mcasp_afsr = mcasp_afsx;
D7 j$ l- E& d; Aassign mcasp_aclkr = mcasp_aclkx;' m+ h0 F: J/ ~$ Y( {
assign mcasp_ahclkr = mcasp_ahclkx;
6 f: }/ w' @" j" u Q/ Massign axr1 = axr0;
3 i; `3 y, M9 Y v8 i$ Z. P7 c/ W( R7 s! M3 m9 v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 b1 U, b0 |0 a' @2 _& x5 Q+ N
static void McASPI2SConfigure(void)
! M2 O" X. g+ K" p& |4 S& A$ B{
7 y: k5 w2 r PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 C$ Q' w' |$ s6 y* EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% H6 K1 A: n. l+ V! PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ a9 R2 D+ g0 w3 Y. [* f' a# K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& B1 p$ v% r0 y& d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 M n" N% n4 z: HMCASP_RX_MODE_DMA);3 h) ]: o: h- E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 A# Y3 U9 K" G* D& O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 S+ F# `' M8 l* n" L8 i' }3 E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 x( r5 C4 A9 F' R/ Z* K4 ?$ n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 q8 A% |% e7 z% } l' v }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ D b, w0 w3 X, j# I$ TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. T( \% b j: Q+ Q( R' g, A6 k; L- aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 p/ `7 t- q# |/ Q& g. I% c- j' f1 E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 v2 r+ P3 @ q2 d- T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% L( L* D' V: X( E: Z
0x00, 0xFF); /* configure the clock for transmitter */3 m! O5 R# {2 z$ t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% t. w' ], y$ j: C }( K; I3 NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * {* ^% d7 `1 Z. R1 F6 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! h. v$ [4 C. |5 m5 l: _# g
0x00, 0xFF);
+ L. w5 P, q$ ^$ u! L8 l z) i! M5 g0 k
/* Enable synchronization of RX and TX sections */
% g+ `( z- Y7 L# @$ JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 r& A- ~* C+ z4 U3 o, v+ Q; w1 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 ~% g$ v; V' N2 ^$ O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- _3 i3 |& r* Z5 I1 F9 ^2 @** Set the serializers, Currently only one serializer is set as
" V& ?7 s! J) u, d! t! _% ^** transmitter and one serializer as receiver." e0 ?% |) j" T- k
*/
9 N( ?' R* n, S5 B9 p, nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* l0 y. V$ A' vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- y. t/ E9 R) E) k6 N1 m' K
** Configure the McASP pins . S3 D6 x3 h5 Q; Q4 W9 z
** Input - Frame Sync, Clock and Serializer Rx, R( E# m6 W. N3 ]- o9 \
** Output - Serializer Tx is connected to the input of the codec $ G2 C8 q. q& [: G Z
*/! G# M6 C( `3 K, _ [6 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 s1 }. Q0 S; I7 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 F2 X& R* I" E% N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ u _5 @5 r! W; \- h: x4 n
| MCASP_PIN_ACLKX
" f/ e1 S% u1 F- q- W3 P" n$ v| MCASP_PIN_AHCLKX
& M5 k4 ^% u" O! Z* M- d5 V- S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 V* B7 ]. t7 k; s \4 R6 N( q# {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# g5 m6 H: w+ X6 f! C: N| MCASP_TX_CLKFAIL 7 ^7 t& ~, r4 t9 u
| MCASP_TX_SYNCERROR9 ?3 `! E/ c) x* f {' \: f. I( T0 h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 {4 M$ B/ Y% w% L, L6 Z0 ?| MCASP_RX_CLKFAIL" z, K# _; O- K* f$ ~: K, P/ y
| MCASP_RX_SYNCERROR * v$ X; j+ w. l* P7 ]" D
| MCASP_RX_OVERRUN);
9 O: o. R1 D" f- F} static void I2SDataTxRxActivate(void)
, \7 Q3 R9 g8 i1 g: h) d+ ^4 v{
, }2 d3 u- B) N5 ?5 n/* Start the clocks */4 b8 \8 X& e6 a* S% [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 E3 i) z7 W- ~( AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. R0 n- i9 j3 |' _! HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- L; b" j# S8 r! V6 Q$ o8 f$ ?EDMA3_TRIG_MODE_EVENT);
6 {/ e/ M; e: ^" {3 j9 F0 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ~' Z7 V! A5 R1 ?3 AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* j- P3 y4 m2 l# M; @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ w5 }: T* @4 w" U5 \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; P$ [9 w0 F5 Z5 m5 I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 o# S ^4 o; [& X2 ?( fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. G; a8 I$ e7 m* ?0 Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, w) t" b, x: {. x' @+ J
}
# _ X; P; z2 X0 T1 L% L: `$ V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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