|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ e, y3 L. c' }3 v
input mcasp_ahclkx,1 a% V, Z, `7 [9 S1 \/ z
input mcasp_aclkx,! H0 D* z4 m: n
input axr0,+ n- ^ f/ V/ T2 }/ }8 Q
+ m% } i k/ f4 }7 I
output mcasp_afsr,& ^5 ^0 r& z- L
output mcasp_ahclkr,. w5 R6 c& `- v. r% I
output mcasp_aclkr,9 {% h# X4 m u" a/ f8 H
output axr1,
$ n, \2 p' ]0 [ assign mcasp_afsr = mcasp_afsx;3 N$ d' s! F7 s6 H
assign mcasp_aclkr = mcasp_aclkx;0 F* n9 E: t; A* p
assign mcasp_ahclkr = mcasp_ahclkx;
3 @. q) B# i" a; K0 e; M0 Xassign axr1 = axr0; 4 u: V: j( ?/ q) P6 ?& D
2 i- I0 M1 \$ f% L- ^ t' f- I5 f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ G% G8 g( O1 P; T. fstatic void McASPI2SConfigure(void)
( G( z9 e U4 ]. T1 s% u{) m% M5 I9 p, | O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 U' U1 M7 M/ _; ] M3 c; l; | w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! T5 `1 K# v2 s# a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; J( v4 n& C' e: _5 S2 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 c \- M/ _3 ~" r9 L+ W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Y0 n$ R6 L1 u4 ]$ B* CMCASP_RX_MODE_DMA);3 I) c$ |5 y+ Y: |( M* R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 q* z: Q0 J* q+ D! r$ v$ fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 ?% y h- q5 l8 n2 D- T+ z4 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 z5 z% W6 t( w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% k' a0 x. K. t3 h7 N" h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 l- Q1 r% B* s& Q/ Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! u1 l7 \* T7 J* e2 S8 \. H. ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ y- k! D, K0 v$ o- L7 Y( [4 C9 b' BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 p! Q' p; \: B3 w/ q' @. |; |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. G# Y. q. W4 b+ u3 T) P" y
0x00, 0xFF); /* configure the clock for transmitter */
4 D. [ g! v6 w/ `7 J. V' AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& t( C4 Y: R7 _( H! {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! `+ Z% i' y% x" ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& h/ } j1 _$ }4 [
0x00, 0xFF);
* o* G$ A; B( r. j% P
5 ^* d5 U# r9 Q! Z/* Enable synchronization of RX and TX sections */
( q& g( x) b+ [7 a( nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ f' l& X2 z @0 }5 J! M2 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 m; M' d' k( {* j9 T: kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 ?9 p0 D8 Y' F+ z** Set the serializers, Currently only one serializer is set as
; t r8 P% |4 ]$ r1 e- s** transmitter and one serializer as receiver.5 T0 @# x/ O. W- q7 O5 a4 G
*/
- S! z& O. j4 ?! \& L4 c/ w2 dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- u/ {5 M+ S4 G/ d3 I9 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** n7 s9 M, Z/ |! K4 m
** Configure the McASP pins 5 L* j7 \8 M3 n
** Input - Frame Sync, Clock and Serializer Rx
+ x1 @9 m' r, @2 Y/ @** Output - Serializer Tx is connected to the input of the codec
\' |/ {5 J/ p9 i*/8 F* g: |* D+ S# Y! l% ?7 [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 \" L9 V, r! t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( B$ c) Q" p) M( m# c3 \. J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ a: d! n6 ] ~, b. K" |
| MCASP_PIN_ACLKX
/ M$ P! J( y6 t| MCASP_PIN_AHCLKX, G0 j1 P. p8 `* c1 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( `/ E7 E; ] J. fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - g: k/ U! Z, n, U) i4 i1 f% G
| MCASP_TX_CLKFAIL ! d6 i& u' o# m* g4 U! [2 W
| MCASP_TX_SYNCERROR. } g4 R+ G( q4 d( V& @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: |' {; ]4 h/ V# P; y| MCASP_RX_CLKFAIL6 }8 D, {. @; @& x6 j: o
| MCASP_RX_SYNCERROR
) C' b9 B- G, E1 M| MCASP_RX_OVERRUN);3 u# B2 z+ n" l% D1 t1 D" y
} static void I2SDataTxRxActivate(void)* L$ C, x; j3 E% N( x$ k; S
{! p0 C% N. g% P' k- }7 N; S
/* Start the clocks */
5 m( [! t) e2 L% e' ]2 E0 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, G# j( W1 U# A1 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* L" D7 y. X, R2 J( y d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; p. ]) w& G8 [+ c1 \5 {* X
EDMA3_TRIG_MODE_EVENT);" z" F w# V7 M; R+ s2 u8 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 C: K! m8 {% x+ v8 v0 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% O- M- ], p* _/ K0 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 a5 A4 C7 e4 t: HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& B! F, Q) H; l9 \$ e, r( {4 ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 n5 h7 C* Z1 x- o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' Z9 V5 ~' I* d R, R: }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; E, Q1 D$ N! `1 _} ( ?+ m) x# {3 k4 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) w# k x' S( o5 p0 M! k+ O
|