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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 r4 o( z. Z8 X2 s
input mcasp_ahclkx,
6 ?) p/ C7 ^1 j( C" oinput mcasp_aclkx,9 {, q7 n) S' D6 X4 f6 [2 h
input axr0,
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5 I) v, T4 S' j8 o# Y8 g; N$ v, poutput mcasp_afsr,
2 R' c, U, q, D4 Goutput mcasp_ahclkr,( q( w6 q1 `. A( |- X+ W' T
output mcasp_aclkr,& c, ]* S) I7 {& e! W
output axr1,( d+ y6 q: N( o, E/ l) t
assign mcasp_afsr = mcasp_afsx;
( R1 _7 N$ o' s& s0 q5 qassign mcasp_aclkr = mcasp_aclkx;
- M5 J+ s7 d6 w7 F; o7 Tassign mcasp_ahclkr = mcasp_ahclkx;6 D6 a- H$ \6 h: Z/ y
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 U! I' B' b5 o) C/ M
static void McASPI2SConfigure(void)
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; ^9 Z; W) r/ `/ w: w* c! ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 {$ L* c4 B( h9 f/ Q) D8 \McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
K& v4 e5 H x* i# X( ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* Q3 [8 z. Q- I" p% g; WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. m5 u3 W" d$ r( m7 o1 U8 K5 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* H/ z5 i5 c$ ~ p t5 \# D0 {
MCASP_RX_MODE_DMA);* z( T2 q: L5 c/ I. h/ H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% G/ O: r, a9 V9 N; _& S7 p) {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% ~! t0 E2 N4 h& K. T5 C& P: a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + |/ {1 Z* b9 I. F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& `* s ]3 P7 E( z2 s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, p3 G, P m4 P; ^; k7 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& z- I+ i0 H$ C+ I2 @ H" _4 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# w: @+ p3 g9 U/ SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( l4 m+ |% z: HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; Y0 R. I$ a( T# u1 |0 O( p- F
0x00, 0xFF); /* configure the clock for transmitter */
: V2 f* ~5 D$ \( N7 h% g3 j/ HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 p. R1 m, ^6 @, sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& M, e, V. R Y. v$ c3 P' W& ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& D0 ^6 m* C* D: W
0x00, 0xFF);& X, } }1 `1 J, {; x
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/* Enable synchronization of RX and TX sections */ 7 p" L h8 F, I- A& o- T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 ~# f' _9 G0 r8 b M Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" r7 N1 Q, N4 `4 mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 L- ~7 T4 ^' S# H3 ?( r
** Set the serializers, Currently only one serializer is set as( H$ _/ [$ S; D P1 v0 B1 p
** transmitter and one serializer as receiver.* U+ X9 ]2 R6 q# s
*/$ g }' o$ J0 t# K! c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" m. u2 A6 G( H+ j6 I! Q& R4 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 B4 f X( W6 Y/ A; A2 \1 f: q** Configure the McASP pins + m, ~% T" r7 O: W
** Input - Frame Sync, Clock and Serializer Rx6 }, J; I x) [5 i8 |4 q
** Output - Serializer Tx is connected to the input of the codec 1 S- B! |7 H8 F* q( u0 j
*/
4 o. s) ^ G) U8 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( p2 g$ y+ Y- R7 B6 d) Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 c/ b) B( W5 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ E& ?3 S$ G M1 x0 s8 D
| MCASP_PIN_ACLKX
5 W T7 W( H$ ~) T" `| MCASP_PIN_AHCLKX( A6 D0 W( K# A7 b! h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; y! t$ k7 D% b! \0 N: _* X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 C2 V5 ^3 J( c1 {) R
| MCASP_TX_CLKFAIL 2 r% Q" y: V7 u" b& v( `
| MCASP_TX_SYNCERROR
0 v2 {3 J2 M1 r7 m2 U) ?, i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . s4 c3 q3 o5 R$ B" ^8 m7 U/ A
| MCASP_RX_CLKFAIL% n& x0 |2 T1 `+ ~) y: k5 \
| MCASP_RX_SYNCERROR ( Q e0 h. }* g# o. g
| MCASP_RX_OVERRUN);
# a' E& |. n1 s7 @5 S4 a+ q, a Y/ ?3 {} static void I2SDataTxRxActivate(void)9 Q, I1 l' _' t0 c# z9 s2 Q
{
5 @! g: J5 n0 k/* Start the clocks */
1 Z% c5 W1 d) I7 N: LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 k/ }. y# u4 p( V9 p& D4 r7 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) y! n Y3 N4 V4 i1 ~; j* l! V0 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 G0 |" N: x' g" l$ q7 X) Z2 nEDMA3_TRIG_MODE_EVENT);
5 \) C. a4 I) b# SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! }0 A7 W9 c9 Q# N3 r# gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 |4 |- P1 ?5 _2 g& i5 G2 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 [$ g% d' k0 p. x/ H4 N, T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! S* h% S M. N+ B. Q: Z9 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& {) H1 U3 o% h$ q& \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( D8 K; |3 J$ Z2 Q% X- X. \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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7 z+ d# C* \/ z3 C1 L4 j, \- [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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