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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 [2 V- n: B; f/ k3 ?8 ?& l. M6 e" t
input mcasp_ahclkx,
" S, B p: [% Q+ s) _input mcasp_aclkx,
' {* e2 E, X% d/ @# h: Qinput axr0,
. Y9 C1 D8 }2 L1 S3 K9 g2 _/ m3 O1 K" U* ]
output mcasp_afsr,
2 H7 Y, A2 _% ?/ loutput mcasp_ahclkr,- t1 v, H) D2 ?! k5 c) x/ z& X
output mcasp_aclkr,( L( y( X7 S! `
output axr1,
- J7 |9 P, o% X3 E! ?: { assign mcasp_afsr = mcasp_afsx;' Z6 `8 t' A: [, H4 F6 [) Q
assign mcasp_aclkr = mcasp_aclkx;
( H8 [# D+ N3 o$ K) \7 Gassign mcasp_ahclkr = mcasp_ahclkx;5 e" N! r3 A# k( K+ {: z) |
assign axr1 = axr0; ) L9 Z, ?0 R8 m% @* ?# @
7 f v; b& @3 a. m% f$ k8 n0 v, C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ x0 Y! r' B+ e5 X% estatic void McASPI2SConfigure(void)
0 C) Q2 R8 B f! x1 q) u. W: H{8 [, Q; d0 l) b5 W) x0 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
H# q2 [+ ~9 }" SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 A$ C9 Z. I/ P0 p4 ?/ o/ c+ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: K4 `" @$ a3 ]* U" T) L9 f; mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; H4 s9 ?2 c s: j* A) F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: U$ M# R- Y) b4 t$ @0 {
MCASP_RX_MODE_DMA);5 y5 f: H9 z N- w" v7 e- z2 ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 F8 k% R2 G% z& V8 h) E& L$ ]7 bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# c( y7 E; { z6 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 V, C- t9 e0 C2 \: r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
s7 D! s4 V& E, z# O' b. {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, O: l0 I4 b3 M+ M# A# L5 x3 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 m V. q% x" ]+ C2 h2 c+ J/ l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 H4 y* @# } g" g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- O! X/ C- M5 R; t3 Q# ?+ ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 R5 d: B" \, {$ H0x00, 0xFF); /* configure the clock for transmitter */$ N b( @; Z) q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( J! @6 S, [' {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( z6 t9 q' q( ^2 ?2 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. G1 {# O& o a# ^
0x00, 0xFF);
: M/ B6 a2 n3 D; }9 w8 o( Z2 [; y) t- S% G
/* Enable synchronization of RX and TX sections */
4 N; b7 N5 E) p [5 T, P% sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ D' x& }1 \* l( QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 N- m+ z4 Z4 A# TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- r$ ~% S1 A' J+ O( ]) ]
** Set the serializers, Currently only one serializer is set as
; b w# y- H6 |) G** transmitter and one serializer as receiver.& }, \. y$ P5 b. [- s2 r/ R
*/6 @& x1 m$ I* q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 D9 Y2 J0 \' {; D/ {, \+ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' J- S+ }% j; w2 Z; b4 f! |4 V** Configure the McASP pins
+ ~6 m) C5 c& k7 Z. f1 N4 ?2 q** Input - Frame Sync, Clock and Serializer Rx
2 r9 P4 K2 i' J** Output - Serializer Tx is connected to the input of the codec 5 O# S$ v8 M$ G9 O
*/
9 Q+ I. ]5 X/ p5 T3 p$ JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* a3 z; C& X3 y7 @3 M! e" U3 d5 N4 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 @$ H+ v8 _; O: YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 k# N$ ?; ]9 F/ g. B| MCASP_PIN_ACLKX
: m: W7 T; M. }; ^| MCASP_PIN_AHCLKX$ C- a/ p( a9 r/ Q( H9 V* L) i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 Q1 V) o( L' ]3 @/ `) d4 D* p# [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ c, L) _1 F; Y0 q| MCASP_TX_CLKFAIL & {. _& e) s- Q8 a0 O
| MCASP_TX_SYNCERROR
7 J6 F6 a% T% a: u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 L. n0 y3 z# C$ V# o% P$ I( F
| MCASP_RX_CLKFAIL
+ h& U# S% b3 Y3 f8 W& }% E* Q| MCASP_RX_SYNCERROR ; e+ z; ^% o3 r. J
| MCASP_RX_OVERRUN);/ e" k- I0 G0 z& B1 {& o# c0 G
} static void I2SDataTxRxActivate(void)
8 {% w1 c; Q$ G# m; F7 i{9 I7 X9 n/ ?. r( j* M9 b" f
/* Start the clocks */( M$ c% y$ \ Y* v9 X( ]1 _- o. P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- }% e7 b" Z$ y8 C6 x9 F: k( ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 ?* t: v: L8 s! nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" p) z& }1 a$ N# C4 B* p" WEDMA3_TRIG_MODE_EVENT);6 P2 V/ K. g* r3 G8 w+ P Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ g+ k6 t- A: g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 t0 e( l% M" C% F6 a& r- d* y* e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 e0 G) \3 M+ n2 Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' R& m4 u4 o1 F# F+ g# ?. \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" v" |6 X! C1 q+ G7 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* q+ P+ E7 {. ^; e( o6 _+ i# U0 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 X. I7 g1 ~0 K
} 9 s1 O: h5 ^2 c# B: j+ w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # W8 ~! o8 t7 Y c" Y0 H& i- x
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