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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. d8 q: z1 S* iinput mcasp_ahclkx, m! Y5 z! G5 \- g8 @4 {
input mcasp_aclkx,1 K0 S6 A# i8 x" u" E
input axr0,, Z9 U6 m C1 h: g- |* G
, o0 j+ i G& ^+ j/ ^& woutput mcasp_afsr,5 }$ E2 ^6 R; i1 |+ B
output mcasp_ahclkr,# `4 n0 w! H; ^* P9 d% Y0 y
output mcasp_aclkr,2 E% @/ p5 ^! S: U$ M8 a
output axr1,
8 \( M% K G' E1 g# ] assign mcasp_afsr = mcasp_afsx;1 {- r/ U1 v; Y& F
assign mcasp_aclkr = mcasp_aclkx;
) N) L0 [5 |: X3 E% Q$ Z4 Z) dassign mcasp_ahclkr = mcasp_ahclkx;$ {% ]$ U& U( k9 J
assign axr1 = axr0; & R! K7 g0 E: h0 e6 P
2 P9 r4 q3 q& k4 X+ a1 D+ H _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 J& R+ R- X1 o7 }( c
static void McASPI2SConfigure(void)
) {- R; L5 h& b. N- ^8 N{
+ s( p5 x- K8 i1 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: \( M5 {6 O7 E6 `7 G. Y" o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* M- \+ T, P2 g- x2 D/ s: O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); W2 H5 U2 M2 F* w/ T' U' [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& u9 ] T- Q$ K8 `0 }) Q6 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, `9 @* n* W; ]6 W: dMCASP_RX_MODE_DMA);3 n9 C+ W/ o# U- N2 F7 D& s9 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 c0 g- D5 r/ Y& M+ _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# i2 l- E$ l: {% d) f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" p4 B" a3 p S& EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; W. ? J- N4 j0 j* LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 t5 T3 T5 Y4 D' w) F8 iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 ]7 i/ _) [% n% ]: _1 BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 i( S; e' u) X9 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& |- E4 E! g; {1 ~! vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) s4 ^! W5 ]0 ^6 N" h0x00, 0xFF); /* configure the clock for transmitter */, x' ` k5 |& t s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 b5 X' E* B* L- |/ Y- R8 b yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * B# l' R7 u: c# Z1 `# p* R; [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 R: P- r) U$ f8 C6 F! P8 \# Y3 v- ^
0x00, 0xFF);0 c; D# c% q% C2 c. Q' A- e+ v7 F- c
# X0 U+ o) l9 w+ Q( |1 ~/* Enable synchronization of RX and TX sections */
- }; H5 Y# I, W6 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ {4 N) c8 T M& U' K' Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" a& I# @' N7 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! D2 e* C* R9 i* S
** Set the serializers, Currently only one serializer is set as
2 S$ k1 J4 U1 G0 p' W0 ?2 l' O& F** transmitter and one serializer as receiver., y( w5 S8 S# ` r* m u& ^0 l; r1 M
*/
+ x* f* i/ z8 K: YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* ?3 N/ o6 ~5 I3 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 h1 f7 v6 g, }0 \2 z1 w
** Configure the McASP pins
+ u' g% B" v* X6 f' n" Q2 I** Input - Frame Sync, Clock and Serializer Rx# z: |7 { P( v7 t) `, I4 q
** Output - Serializer Tx is connected to the input of the codec - b! D0 h; ]0 I. c; c6 \
*/. D) o9 Z: w6 @# A0 h9 f c8 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% u P, j5 _* z; N; h$ vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); B3 I3 c* l3 C. @& {, D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, ]2 n; {8 I4 N0 b
| MCASP_PIN_ACLKX
+ A. K- ~8 S1 M! i| MCASP_PIN_AHCLKX
2 c0 B# `5 D' z$ p3 y* j- g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' P1 k+ G9 \: Z4 J& C0 H; C8 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( d* C9 r: r: v# i3 ]/ n" k7 S) B
| MCASP_TX_CLKFAIL 9 y3 [; N- l8 o: }# q9 g
| MCASP_TX_SYNCERROR
" c# Z- ^$ t# A3 j9 H5 a6 X4 M T2 ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* `: l0 y1 P, Z: m) a D| MCASP_RX_CLKFAIL
2 p) L9 r6 C+ \2 |: h2 I Y* q| MCASP_RX_SYNCERROR . V! w$ n/ v. L$ k/ h L9 c8 l$ s
| MCASP_RX_OVERRUN);
4 G, G" e h- S1 N$ [} static void I2SDataTxRxActivate(void)' Q- U; f/ g, l
{
. {7 j) z) M/ e9 E+ Q- L/* Start the clocks */+ D6 g* K C- q. p6 @# V8 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' A, [. g% d I @& V9 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- @# \8 i" Z* k7 w5 x4 k8 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' b2 M, M: v4 r$ `. c$ I
EDMA3_TRIG_MODE_EVENT);9 E; ^# u0 [7 f( ^' _2 E* V) O6 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) \* ^* U, B$ k4 B% v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 i8 C2 M8 A: i6 Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 \8 l5 Y# R* M7 S, eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, X$ h8 W9 T4 b7 h# |! x1 N) n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ g/ b- Y/ ~# ]4 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ l6 O x- y0 Q; w5 ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 v) f( e& T, g4 W$ K
} 5 l S# |+ g9 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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