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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 n. l+ j! J! d4 [ R* pinput mcasp_ahclkx, ~4 n4 n0 k0 a9 b8 W# B" p
input mcasp_aclkx,
/ Q3 x0 T5 c" d* x! Y* {0 Y1 p. oinput axr0,
1 h9 r6 O- W# D: A7 i; f% y+ F* O9 H r+ S& o
output mcasp_afsr,: \: }) u1 t( m% ~9 p$ [
output mcasp_ahclkr,
. A: s/ n+ w8 r$ Zoutput mcasp_aclkr,1 q4 X" @% u2 a
output axr1,7 x6 ?+ n. B' M; \ A" x
assign mcasp_afsr = mcasp_afsx;7 m; f7 t. Y: w& Y9 p
assign mcasp_aclkr = mcasp_aclkx;
0 ]* c* l! [! A5 m% |2 wassign mcasp_ahclkr = mcasp_ahclkx;4 G# ?( v4 b( R8 b6 C9 m3 k' j' W: V
assign axr1 = axr0;
5 Y1 X) Q% M4 u0 c4 b
1 R/ O& ~! L( u& n. H: x, @7 U& r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : L0 i" a; j2 |: P$ E' a- K
static void McASPI2SConfigure(void)% x% {: @% T" R' N {6 N: O
{
! [ f" [! }' d7 h: @3 l- |McASPRxReset(SOC_MCASP_0_CTRL_REGS);' y ]) X! L7 O* u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 g$ u# e: U$ b3 Z. o, K# V5 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 R9 T+ @* ]3 t3 {9 \* Q6 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 c2 t- ?' j6 z( fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) i+ A- }. @6 R, o! B3 c& c
MCASP_RX_MODE_DMA);
& z$ d+ }5 a2 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# O: J/ w' k1 o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% L2 l8 R5 P) `& ]0 j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / m7 J1 U- b/ k8 E: g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; ~, A$ P' H" T. O w0 f( L* U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 e* h6 A* J6 w# e3 T6 }6 l0 w' V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 c$ Z3 D# v# S8 ~8 J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 l. y0 t/ m3 i% n& n9 ^+ }3 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* A& O3 e2 S1 O! c* y; `1 z- O* {& ?2 d3 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; G5 `) H5 f4 @2 S; r0x00, 0xFF); /* configure the clock for transmitter */
0 L6 p* H1 @* H( u6 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ T8 E$ _* P g' u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * _: D% n. @+ Y5 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( g) {6 Q( E$ ^3 k( O* G0x00, 0xFF);
6 x! H& D# q) [4 S9 c8 N) l; D. {% W! M0 F
/* Enable synchronization of RX and TX sections */
9 J5 e7 F" @5 L7 f3 l& |) v, V/ f* x' ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* X7 I1 D8 |: ^, lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* U% n1 E7 R v9 `+ ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ |' V! S$ e+ O' Q+ ?- P
** Set the serializers, Currently only one serializer is set as% Y" b* v% O. R6 S: \) a
** transmitter and one serializer as receiver.
; m. w. o- c, ?1 ]*/3 Z0 g0 G t, k: ~$ F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, W2 y) Q5 l! A4 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( E& H6 ~* L, V7 \+ l+ \- V% [** Configure the McASP pins $ r: b+ p% u7 `3 J d/ F B# G5 y
** Input - Frame Sync, Clock and Serializer Rx
7 d" U- G! U: M9 h$ y4 x0 ^3 w: ?** Output - Serializer Tx is connected to the input of the codec , W9 F) S( d% B0 F% I
*/: k1 u. s/ S' b5 W4 Y; s" i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. K0 z, E& m$ n7 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 {, ^9 z# V/ t. p7 O* @ MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( V7 X. i4 z5 r: }0 ~& V9 Y9 q| MCASP_PIN_ACLKX, ]% _ E+ J! K( i6 U, c% s
| MCASP_PIN_AHCLKX
8 E7 t9 d* M$ N3 y L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# w- s5 c( K, w+ }0 H4 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& h; d& t2 c! _; t' p: B4 _| MCASP_TX_CLKFAIL / x$ V a, G* e
| MCASP_TX_SYNCERROR2 g* W" g3 c. k V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 n7 E$ \! L( ^0 `2 z
| MCASP_RX_CLKFAIL
9 F8 M i7 p& F5 l| MCASP_RX_SYNCERROR & E" N0 o: Y# j# |8 n" B
| MCASP_RX_OVERRUN);
d( o, X2 S' W" I2 s$ P} static void I2SDataTxRxActivate(void)% l2 j/ J: ~$ f) i" G8 `6 @5 D
{
6 S% [/ d( _+ f& O. Y/* Start the clocks */' A6 T2 {9 o2 X n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 c/ f+ [3 C( J2 d j2 c: E, Q- BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ t9 A, B3 r) ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* V0 b9 c1 _& \+ [( m( {EDMA3_TRIG_MODE_EVENT);
2 L3 q+ |+ |" g) ?0 Y1 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * H# a$ P+ Z* F# X/ G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 D5 K5 P3 p8 A( v! @0 O4 j. [0 |7 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* n: k$ s# q$ ?+ g( V4 h. X3 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' j; B, _2 `7 g1 f0 L- \$ R' `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ A1 L; J% O& h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 J' ~5 v# w5 F# S7 O5 m. U- D* gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: u: [$ A( g0 E( @" Y+ P# T9 \} ) m1 [+ Q% _2 Z, s& K" Y6 J1 {! g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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