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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ g! T% h |/ E# P1 \( h7 t
input mcasp_ahclkx,
4 H1 i7 l0 ~3 z+ Y- cinput mcasp_aclkx,; ], j! U" u9 L# |2 h
input axr0," s- w0 l6 s) a
1 }+ y9 l8 a6 _. I2 @" S& Routput mcasp_afsr,
) M+ z5 \& h/ U5 soutput mcasp_ahclkr,$ q; L2 X, H+ f
output mcasp_aclkr,9 D4 o G# I, ~4 l. G. A* }4 Z1 _
output axr1,
9 T# [' P# c2 `& L, t assign mcasp_afsr = mcasp_afsx;9 E. i: N4 L: V' n6 V! ~$ x. Y
assign mcasp_aclkr = mcasp_aclkx;
p' T4 {0 v! ]" m8 o+ z9 m# `assign mcasp_ahclkr = mcasp_ahclkx;
( |" f2 C; l6 u+ F5 P# ]. k; aassign axr1 = axr0;
+ Y, N! i8 o7 b- y8 Q, v8 C. }3 M4 z4 J& }/ |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 u1 N0 B% @ J; }- @static void McASPI2SConfigure(void)
! a S L N7 B# q! k{7 g. n2 C7 K4 |. \* K1 |, K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 Q+ o+ G5 w& h) m+ R& RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 r# O- X6 Z! s5 l" Z$ o) c, c- |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# A# R M0 e7 Q. G8 T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
J1 u4 ~ o% l' E# G% hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ e) F' v. V7 z" B" ~* pMCASP_RX_MODE_DMA);
8 j# s3 ]- E& s& p- O. q% d1 H4 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* T% i5 E. _/ VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" Z' J% \/ |. b+ |1 F7 I8 U- y! t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 H, {- x& i# p; X+ O) v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 e: q' Q- }' S% e/ |- [5 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % X; J$ I P( |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 @! @+ K4 Q2 @: ]' a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 Q( Y/ f4 ~( L* h0 V% A% y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 q- [- l4 z0 H# ~7 A( [" Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ R) E) h2 I7 G0 j& J& U3 H
0x00, 0xFF); /* configure the clock for transmitter */9 r7 D. a9 ]% H7 }6 a; s. ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
B8 n+ n7 C6 B: }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( W( g _- a; [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ ?' P0 {# }3 M
0x00, 0xFF);
) ~# M8 v* a$ l9 x, O( ]6 r$ F& {- ]6 k
/* Enable synchronization of RX and TX sections */
# a4 F |, K; I- q5 ?6 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& a: v" B/ U( h, U2 qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 ^ r+ [% e" p/ p7 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( t* N9 A: D7 d0 X( | W** Set the serializers, Currently only one serializer is set as
: T7 Y# ]# @+ g/ J6 U% ]** transmitter and one serializer as receiver.
9 I3 s" F( O# \1 k4 c2 a*/
& c S0 T/ K O" P& RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% V- @% W: y# l/ K' ^* k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 a. y0 e4 o2 ~, J8 {) W9 Y
** Configure the McASP pins " n8 _5 O- M# Z, q" o
** Input - Frame Sync, Clock and Serializer Rx
2 ~$ n' L- V/ `% ]** Output - Serializer Tx is connected to the input of the codec
) A& \5 p) v0 R" w( {8 o' A2 _*/
8 F2 F6 h8 u; v0 y7 ?0 W0 u0 y' DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); e6 }4 r% a3 ~/ S6 H# b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 U0 j; [2 a( T& F: c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" h: U2 W7 J- C. u
| MCASP_PIN_ACLKX* E' p r ~5 T+ W% @
| MCASP_PIN_AHCLKX2 E7 p0 A3 U9 _6 H- H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 ?5 n2 Y" L' G5 t: i7 u6 Y" }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # u' j4 W. Z) t4 {8 J
| MCASP_TX_CLKFAIL
+ ^6 F; ?2 O4 e$ [: a% R+ Z| MCASP_TX_SYNCERROR
# ?0 w1 B% O: G0 l( t0 {$ H; \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% r' N& C* ~4 E( s/ |) J| MCASP_RX_CLKFAIL" G* ?9 w# o4 n/ ^' W& c
| MCASP_RX_SYNCERROR ' B6 E8 ^+ n2 R+ q C
| MCASP_RX_OVERRUN);* [3 p- g0 Q: q# }. Z" F
} static void I2SDataTxRxActivate(void)) Y) H6 @9 w6 A( W1 e% ]1 B7 T# m
{
% ?0 U/ S m% p6 t% o1 i5 w0 p/* Start the clocks */7 O: L+ D* y% y8 F' a+ N7 E) G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. [1 n8 ]4 |9 n. J$ t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 v# ]1 u, T( J( f5 `! m5 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- n4 w+ Q2 U$ D3 h1 T' j% cEDMA3_TRIG_MODE_EVENT);
3 r! ]4 }6 g8 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * z7 L8 o/ X) A6 r' Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: I2 {3 @$ B* N1 }2 J; }; V! W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ `: x" Y; `/ b! WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 C$ |6 U& e4 s( L; D4 ~1 Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; i; q7 H0 q6 ?+ R( M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- M" G3 b5 Z' i) m: u* Z: zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 W6 D" M5 m) ~
}
1 r5 _7 f9 q8 g3 Q/ l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / |6 h8 M1 v, W- w5 M& M! ]
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