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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* j( M8 C D1 t0 ^$ I" Y7 Finput mcasp_ahclkx,9 P+ p- v- m% ?2 m" q9 M
input mcasp_aclkx,
' O) [( b5 v2 A( Xinput axr0,
, w* t7 _) n4 }+ m7 A, F
7 Z- S9 t1 P8 D) d6 toutput mcasp_afsr,: o+ M4 N" `, Y& y' |
output mcasp_ahclkr,3 ^% S( C( Q9 ]* I# e" u/ I
output mcasp_aclkr,
! w+ n! g. Y3 q) z# l% eoutput axr1,
; @% d4 ^6 O8 b! u/ c0 f8 V2 v assign mcasp_afsr = mcasp_afsx;7 P" s1 d8 A5 o; J* v
assign mcasp_aclkr = mcasp_aclkx;5 P6 N$ p: q/ x: j# I; i
assign mcasp_ahclkr = mcasp_ahclkx;
( S# ?* q6 r$ z/ x" sassign axr1 = axr0;
1 ^" ]7 E$ f: p# h) v
. y d i1 o$ j" e$ a, `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 n) p% Y) y) w' l/ T* T) _7 _static void McASPI2SConfigure(void)
+ u/ `% _/ z# ?) }5 e$ W{
. h8 M# T" z. v% FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" K+ {, E) J8 Z( V) B+ ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( n8 R* z: ~& \5 p( T8 I3 b( VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. C$ _+ V. w" n$ Q( A" ?0 Z" c# [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, L, g) F' L1 d, Y0 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ]& j7 X& P0 X3 j- Y/ T0 ^MCASP_RX_MODE_DMA);
# o$ J; Z4 o; ~+ o( zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 g/ B2 }; V. x& K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" I g f/ Y( f2 M; V, V7 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) A0 E% Y9 [+ x3 r. R% G j6 |+ K* D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 v, l0 W+ t9 y) x5 h: ]% X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 O& L W1 A9 b- ]. f5 n7 NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( r W& l2 [2 Z1 a! J! I8 L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) k7 X2 ~5 M/ W. ?3 q) v& e) U/ `& q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! T- E, i: `+ x' g6 T% T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 y) `: T( M9 O
0x00, 0xFF); /* configure the clock for transmitter */* i X* _( C$ f8 k5 p1 K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" r/ G' r. B+ `- i1 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " @/ ^5 C: C& |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 l/ S+ D6 V+ O# x% R$ V$ x
0x00, 0xFF);, b _4 ^; z" ^$ ]4 Y N9 {9 v
* ^( }! {4 `9 B8 ?- r, L
/* Enable synchronization of RX and TX sections */
% b5 o: x; c! Z- dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- ^* s) Q% I9 Q7 Q# p+ L. E/ M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. J- D3 ]. u8 x/ Y4 Q+ }% b3 G7 {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 @5 a! S8 f, h** Set the serializers, Currently only one serializer is set as
* Y& q ]6 B' Y7 y# W9 f( [6 S- C** transmitter and one serializer as receiver.
) |- a$ J# B6 }; a; X( a( w*/5 O |, ?+ C: Y+ a$ Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ x6 z; l' J/ i1 S) C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 r3 {+ z2 O+ ]7 H5 O** Configure the McASP pins
( i/ v* G$ W8 W9 n! W9 ~: J- K7 k** Input - Frame Sync, Clock and Serializer Rx
7 C3 @1 J# Z F** Output - Serializer Tx is connected to the input of the codec
4 v$ y# Z7 ]- t3 B, ^ d6 r0 K*/
6 e/ o$ _. V- k2 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 o" x' u" j* g& S- o4 Y$ YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 Z: h/ Z6 g" R8 }2 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* }/ M5 B) x4 O3 s* o1 r- T
| MCASP_PIN_ACLKX# B0 V* l1 a8 J4 z
| MCASP_PIN_AHCLKX6 g a) s+ {. Q- B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! q/ |. Q$ h6 G, `3 p PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( {' b# ]) X' b& k| MCASP_TX_CLKFAIL / m- Y( r! R2 W! ]1 }
| MCASP_TX_SYNCERROR
- ]3 G- b3 d I$ V& Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * b7 b3 q* i; g* y* W8 t; y8 L) |
| MCASP_RX_CLKFAIL- l6 M4 m- u* F: M! l( y
| MCASP_RX_SYNCERROR
* P) T4 ~8 @0 _- H+ E2 l2 J, C7 w" P| MCASP_RX_OVERRUN);
$ ?3 M8 l$ u# d4 L4 C( L7 m} static void I2SDataTxRxActivate(void)
, W+ p' j1 d+ A{ |0 o7 @* d9 e( P* S! _
/* Start the clocks */
% N! ]2 ^9 O4 `0 W/ n9 K6 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" M$ P5 J( j0 H, @# P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: h( W0 @( X0 k2 o( qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 y5 I) S8 _+ z6 wEDMA3_TRIG_MODE_EVENT);3 \3 s5 }' j& ~! o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ M' T3 V F, G$ \& fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 U: P4 t3 }9 ]1 @ ^" b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* V- ~+ o; \0 c1 m3 ?" H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- T3 _) i# B3 N. k- q0 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 y6 o5 c+ \ a. l8 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 e4 e- N! X* ~/ K8 l0 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 }, T1 Z# @# E
}
2 Y/ _- A+ w Y' }1 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ m4 T% G& Q) g1 m |