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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 G+ d" J& ^/ S" C; Q1 t5 _+ jinput mcasp_ahclkx,' f* p+ j2 J6 K: G0 J
input mcasp_aclkx,
/ M- t+ w6 d5 S4 u! s7 Y% n0 U8 finput axr0,* v q7 r6 J3 j2 g1 l7 f. ]
& D. P. J4 X/ \output mcasp_afsr,
, m9 ~* a. r" U$ H% ~output mcasp_ahclkr,
5 j: e) T& w8 z6 H* N5 q' H1 Voutput mcasp_aclkr,- z3 U2 g8 Z. m4 L3 n
output axr1,; }# a, v+ C. A7 K0 V9 [2 X
assign mcasp_afsr = mcasp_afsx;
: [7 U- x# D7 m, U3 | _4 eassign mcasp_aclkr = mcasp_aclkx;5 k- s! B3 C8 ~$ F3 t8 ?+ g
assign mcasp_ahclkr = mcasp_ahclkx;
j5 U! ]. \/ Z, Massign axr1 = axr0;
4 g u+ K# _' ]" Z0 N/ A
* Q5 w8 G2 i6 ^7 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- u, H$ P! F1 s: F% X( h; _static void McASPI2SConfigure(void) j6 H6 C3 u. g" v9 A" I4 K
{! e* ` j; w3 |& |- H, [( m& f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 A. c& }. B" w4 u) J. h/ J Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' ^7 Y8 p1 V- L8 E; ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, V# A- y" G: ^: Y- G. f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* z2 D5 x }4 M+ D+ ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ A1 ~2 s' ~2 h! X, z- v1 D- y% z
MCASP_RX_MODE_DMA);: L i% T& ^4 d8 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 j% }: g' q8 ~' c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! u# Q$ L( p4 \ D8 @* Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 F O; p0 p1 N) [3 j% N7 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' q0 _+ m: s Y( |0 r4 z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" ?: d2 Y' W6 u9 I% LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 u3 Z9 B$ i$ E3 @1 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 S" S8 E/ b/ H' Y5 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ K" a. j; q- R; z; M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& ~4 @5 m9 \8 x' B0 N/ P$ R
0x00, 0xFF); /* configure the clock for transmitter */$ d- N) Y; ^% j$ B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. j }) t- R( O' T3 L5 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. l: @. g7 f0 h; l/ ?4 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, r6 v6 l- n( N s& _6 |" \1 O0 j0x00, 0xFF);4 h3 I* Z1 t9 m) N/ @. U
2 H- d$ X2 X7 o7 U+ J
/* Enable synchronization of RX and TX sections */ 9 v' S4 ^: @& G4 }4 [) W. q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
i/ o$ k. {0 X0 V1 c& |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- J, Y6 V! y' I9 k. z. JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 ]: d" U3 [. `/ B5 d8 I
** Set the serializers, Currently only one serializer is set as7 { a1 A/ h' H9 h1 t+ [
** transmitter and one serializer as receiver.
8 M9 T2 L5 [# Z. x- @/ S*/( R) B, l& O5 b4 E/ T3 H: S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ~% l, I# P6 O' E) i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 T4 {5 s# j& p. z3 e
** Configure the McASP pins
* Y' e: q w! {! b* `0 j% ?, D& H; C** Input - Frame Sync, Clock and Serializer Rx9 l4 f0 q0 O- H4 Y# O" D
** Output - Serializer Tx is connected to the input of the codec 3 r* p! s# O/ c+ w; J; v5 c
*/2 B% o+ d2 F& b% Q7 P& p3 C4 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: Y2 Z$ K1 K; P z F1 A/ ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( x9 O% y: D+ o: E/ N% ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" r. W; k: v- [# {1 P
| MCASP_PIN_ACLKX7 Z4 N3 S/ P; D8 t
| MCASP_PIN_AHCLKX
. }+ B1 K3 y- ]1 S9 O7 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 p: C4 m" X+ H) Y; [: y2 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ P! f; C! w. r
| MCASP_TX_CLKFAIL $ z: u0 B3 D3 O- L7 @8 ]
| MCASP_TX_SYNCERROR
- \) v6 ^" y( V: r) ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- n8 D2 H& n( D8 u6 R| MCASP_RX_CLKFAIL' Q/ q2 k* K; f. v; k
| MCASP_RX_SYNCERROR
e; g: M b/ m9 {9 r| MCASP_RX_OVERRUN);
8 P9 x9 k- [3 v; Y2 d* y} static void I2SDataTxRxActivate(void), k$ f3 a) y9 p& m
{
8 d% A+ J d* ~+ C0 K; f# |% t5 B( v8 b/* Start the clocks */
; u/ I+ L5 y6 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) {- c% z c! n/ M! Q: |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 ^# t2 t8 |% e' i% h5 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. k# G U7 ~: |* c; W
EDMA3_TRIG_MODE_EVENT);8 P0 J5 L+ n3 g& f- s& r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! n0 }$ N8 S P) Q$ sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" W, e' W) y) H3 Y! y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 Y* f+ B, P( k S1 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) O$ g1 F* k2 [. X. X9 J, y% Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ ?$ Y. k# U ?6 K0 l5 [0 Y1 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); u, o% S& ^9 U0 `, T; i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 F' P1 x: F4 ]! Q$ X% m3 T}
5 _; R5 e7 @* h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
3 @5 g+ F2 F- S3 T+ H8 [( d$ G9 l |