MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
' @) h( o2 A. J) |0 F0 e5 dinput mcasp_ahclkx,
input mcasp_aclkx,
; A# c# m5 h' ~! binput axr0,

output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
( A' f0 _) ]: w% b4 {! {  y- }output axr1,

assign mcasp_afsr = mcasp_afsx;
( C8 }- y" N- b3 B# `/ Y8 cassign mcasp_aclkr = mcasp_aclkx;
4 n5 Y; M. e5 R1 v8 m1 o* eassign mcasp_ahclkr = mcasp_ahclkx;
$ o4 R/ P8 A+ u) ~assign axr1 = axr0;

4 C+ g% u' o. v) I, x$ Z

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
8 o# p' ?3 k5 q. j+ U/ |/ g2 q{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 S1 i, J6 Y* L* LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 Y6 F, U! T* W/ w* MMCASP_RX_MODE_DMA);
) u% H' ?+ Q. \- s- E4 ~1 {; ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 d) L, [5 _. T8 \, Q& L1 [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. c. Y3 z+ v% T! n, d1 s, w: W/ f( ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ _* H/ c' b. p( Z% @9 l2 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: K" n' ?% |8 Y3 A' X2 K0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ ]! P2 I* @$ {! m" v" t% Z" ?/ sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 ]0 _& r6 I7 ~* |3 }0x00, 0xFF);
( W1 Z" {5 j  J1 `
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. e2 y) r7 j4 j" k8 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
6 _% F! w) J8 d9 @9 G& S** transmitter and one serializer as receiver.
*/
3 C: j: O. e: eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# ]7 T8 d3 `+ w$ J3 N! f3 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
. V, v/ Q. K8 [** Configure the McASP pins
$ m2 r' E/ V4 l: }4 y** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
8 s2 B* I, i3 g3 A7 A*/
  C5 \* \! H6 v  u3 O7 O+ O0 q2 d& CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* y2 L  N0 S8 a3 l$ x0 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) M% x0 v; N: d| MCASP_PIN_ACLKX
" A: s* O) I' q| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
0 j5 A& |2 e/ G1 z. g$ c. T; KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" s4 K0 F) n+ N7 `| MCASP_TX_CLKFAIL
/ `! Z/ ]$ o' q| MCASP_TX_SYNCERROR
+ G: r' l, T. B1 o: F  Y| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) }' |( O: u2 A  X5 D# s| MCASP_RX_CLKFAIL
( `2 Z2 R# c' I; E- H0 i2 @| MCASP_RX_SYNCERROR
7 G, c) g3 t* y+ w' }1 S' u8 D' F| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
/ Q& B! ]" ~2 j) |{
/* Start the clocks */
/ A" B( D! [9 P0 d# gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- j+ W* F, _3 ~" Y  F  MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
: I! O) @/ j& REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 N6 W+ s( E2 V; C$ b2 t6 @; ?, i2 mEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
) j0 l! N% D2 s# V- e8 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* R0 H. a. P: ^' h, M+ x2 bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 @) O: A3 ~& q" _$ M( M0 F}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

5 Y( ~- M/ H/ ^+ h9 B' `, a' M9 C+ C$ E