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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. U4 Z: C+ q' I2 E: xinput mcasp_ahclkx,
6 I! @) u* \4 Z4 Dinput mcasp_aclkx,+ S5 [+ ^' U x ]4 n
input axr0,7 Q2 q) i' l# z4 M, h5 c
, o: i% {1 P0 H/ g# d% T0 woutput mcasp_afsr, R3 V- E8 h9 ^6 L9 T
output mcasp_ahclkr,4 m" \& r( n: o9 I! O* J9 h/ \
output mcasp_aclkr,3 d! e3 D( B# ?/ ~' _. z
output axr1,
2 C$ _1 C. [& R1 L; G assign mcasp_afsr = mcasp_afsx;5 Q: |9 {7 A$ O4 k6 W5 k
assign mcasp_aclkr = mcasp_aclkx;
. W, w4 w+ N% l: c2 cassign mcasp_ahclkr = mcasp_ahclkx;- R! g9 v" s8 t& {5 H3 ~: V
assign axr1 = axr0;
p" Q8 d8 w3 L9 v
- R0 N* ?8 g' @: f" X9 Q9 V$ c9 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. |7 m; x( f; s8 H0 o* e& q) a3 Nstatic void McASPI2SConfigure(void)
P& }3 Q7 J8 R( J: D f8 C" @{
7 ?3 o0 f: ^2 b# {% J3 XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 }3 P7 r, z8 W4 H1 n0 J7 Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 l3 k$ m) g4 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* m$ W2 f* k7 Y: a; kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) y7 ?2 p3 _+ o# z, j, k* `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! l, K0 w& n: iMCASP_RX_MODE_DMA);, Z& D, Y0 G2 t; i* d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 [0 h, f; Z3 s" d7 b _+ t& z- wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 I) g G) \7 t6 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
g4 y! K, a# Q6 Q5 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ y- E0 k/ ]4 x* n: C. RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ A0 a% D+ ~' h) Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 K4 b L. A! }, J W& Z9 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( y* S0 F3 e/ [& A' t, o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 F: g3 s% c1 y( {) PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 v! F& C" c$ ?' {; g0x00, 0xFF); /* configure the clock for transmitter */2 g* B$ ]- x6 n) s) H6 d; X4 f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ t% f" r: }# t3 ?/ GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' A, U) M" T+ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 o K6 T5 \4 H K$ f8 N) g
0x00, 0xFF);; q7 n" r/ u6 ^2 F" f" ~
6 H* |4 V8 W& v2 w6 A/* Enable synchronization of RX and TX sections */ 9 t% _8 y5 m6 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 ~6 L7 I3 }2 Q7 B: e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 Z! w3 i5 @8 Z# s0 Y# `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 d% h. N: @* c4 g4 L, i9 d
** Set the serializers, Currently only one serializer is set as% L; H# S1 T1 T# U4 N7 I2 C
** transmitter and one serializer as receiver.
% u( B3 @* y# j5 ]" ^7 ^/ l: [*/
3 t) }4 q2 P( p. SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" V) Y3 I* T+ D3 Y) A N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, h4 R9 j# A$ f( n' b1 n+ E, b T- g** Configure the McASP pins
! O5 P; y# y: ~, G" } g1 D** Input - Frame Sync, Clock and Serializer Rx
$ d& y% X* @/ G4 j0 f! e$ |** Output - Serializer Tx is connected to the input of the codec 3 E4 U: p8 c$ _3 Q; z, B6 i9 d
*/3 B0 r" L! t9 e. A& ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ ]3 L. L$ {2 r7 t* XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
E+ U# S& M( a5 JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 s4 x- U5 A. B| MCASP_PIN_ACLKX# F) [" b, ?0 @; S4 J/ o1 k$ `; o
| MCASP_PIN_AHCLKX
4 r9 u Q6 m V# ^7 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// P$ j/ L1 L+ }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) B$ B2 `* z9 I; Z+ S| MCASP_TX_CLKFAIL " H1 @ ~5 P. Y8 z1 C# ]
| MCASP_TX_SYNCERROR
" J' h* W9 @% U7 U1 O" b3 r4 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 z7 U( c/ L) ?. @7 r| MCASP_RX_CLKFAIL
7 v8 U+ }5 f. d1 o4 P' M| MCASP_RX_SYNCERROR % P3 Y6 V$ c" p$ c- ^4 ?$ I
| MCASP_RX_OVERRUN);( e6 ~+ C5 `2 f. y
} static void I2SDataTxRxActivate(void)/ Z3 O# S' t. E7 x2 {8 T
{' e0 J- h$ Q' H3 ~8 f! N: n, y) C
/* Start the clocks */8 [" }# K9 l# Z0 b5 }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ @. l1 i( x$ P# N3 d, zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 _- N6 H" B! { M. X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( Y. [$ O' w% N* j sEDMA3_TRIG_MODE_EVENT);
* `$ h4 q, a( @, f. mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ C" r2 @8 w4 i7 y! Y0 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 h g2 }% [. s( G2 Y" z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! V; }0 ^7 F4 F2 S$ y7 z( M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% z$ A; o5 v' ?1 {0 b' `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ Z4 I* t" m, z H. s# }; L$ r. s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 y2 b4 z" a0 n. TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 g: E2 M" u; ]5 O& _3 x. I
}
- s4 c4 b: B$ v6 m3 L2 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 p, u v: P' W# a0 S% G4 S
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