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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, }+ l7 q9 m% Y& sinput mcasp_ahclkx,
3 e! C* X: B( b P' ]/ C& Y6 sinput mcasp_aclkx," ] Z" Z _! Y: F) N6 O4 l( x4 c
input axr0,1 a, p+ {! j( c: f/ M8 [7 ~
c5 o H$ g/ J/ ~4 youtput mcasp_afsr,! F+ }% F: C3 ?6 y4 t( `4 h# C
output mcasp_ahclkr,6 x* W( T, o" B1 U" M2 p0 G
output mcasp_aclkr,
8 \: |7 _% }- P& F. ^output axr1,
; F# c0 T! [( d7 v assign mcasp_afsr = mcasp_afsx;0 M" {& }: l' D* m# H* Q
assign mcasp_aclkr = mcasp_aclkx;! V% T. m, K8 i
assign mcasp_ahclkr = mcasp_ahclkx;
: X& T$ ^) L. j# E- H" B( oassign axr1 = axr0;
9 u, `* r! n- X i4 ~7 ^
$ f' L# ?0 m3 `0 [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + A& { a3 J5 W
static void McASPI2SConfigure(void)
( h, @5 A5 J( d{- [1 H' a$ o0 m7 d- d$ c5 i" U1 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 f$ y9 u$ h' U7 Q$ G4 g lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 `' H& l& M& a) d3 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 k' Y+ w) [# u& d8 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 Q$ e) D( _. b3 A; U! c" }1 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ q% z+ E+ m& g% D) m6 R9 `; s7 R
MCASP_RX_MODE_DMA);
6 E' N) V) I' m1 A' ?* {2 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 \% ?9 j- {1 P4 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) W8 |7 e+ e9 ?. sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) n6 k9 Q+ f, j( G5 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 U) x/ Y6 q& g2 Y/ Y% X+ K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. |! W( ~ W+ q% J) b! }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ a9 c- Z) k" I* w v, F& p( g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! U$ Y, B3 B, h0 L/ B/ D0 [" Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * ^% x) _- S% I- L1 a5 L7 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 @& B( b* j0 o* |! j0x00, 0xFF); /* configure the clock for transmitter */
6 A$ F& w5 y0 I. z. `5 kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 `' M) f3 x7 K! P( G- j0 ^2 U ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . m, u t3 _1 n; d6 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 N8 b9 N0 g1 ^3 ?* N2 ]0x00, 0xFF);
3 U* @# i' ?, }7 u$ |' V7 I7 p& W$ {8 b0 O$ G0 B' @
/* Enable synchronization of RX and TX sections */ ) ?/ }1 [- v' J. ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- \; \- D O4 @5 a. \( F+ }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ _* x, t$ F( U: t6 Z% X8 y( SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' _' C& k& y% x( o3 a5 p7 h** Set the serializers, Currently only one serializer is set as
. @$ U0 ?, Y1 E* s! t/ B5 X** transmitter and one serializer as receiver.
- {8 W- o, g: E8 ]' b9 ]* D. ^) ~*/& ^, }; w! E1 C, L) X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- G, T5 P, x o4 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" _% A# r" S4 H# U# a** Configure the McASP pins
6 a' P# x3 [ |% V6 S' p( s3 G" k** Input - Frame Sync, Clock and Serializer Rx: Y4 O" z/ m0 q {1 {" Y
** Output - Serializer Tx is connected to the input of the codec 2 F# ^% F) e! s9 Q( N" ]% y9 q9 O
*/
# S( N! g: h/ V1 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! ~- l4 U0 L5 j1 u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; m$ Y3 P. }* }/ y/ \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% \; c2 g8 W5 v" J- s1 [| MCASP_PIN_ACLKX; l/ y f9 M( X. g5 G
| MCASP_PIN_AHCLKX
8 r: N( _/ x" j0 q2 Z, N0 ~" C( Q4 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& \/ J! T% Y5 M' G( |- @0 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# }0 k: v* _& x1 g7 q9 F; Z, K| MCASP_TX_CLKFAIL
& D! G3 [4 R6 R5 l: |: o# _& ?| MCASP_TX_SYNCERROR
+ e- |8 u4 e8 F1 q" w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 q K1 _! A! O* K$ T1 t. p: }# P| MCASP_RX_CLKFAIL
C: d0 z8 ^% w& Z) i; x. y| MCASP_RX_SYNCERROR
( @, F8 z# S, k6 V+ e| MCASP_RX_OVERRUN);5 H S" g& I4 j" D! Z( T" h0 U
} static void I2SDataTxRxActivate(void)
- |7 ^" d- Z k2 u. a: q{
& n$ K8 B' @0 ?2 q$ |& m0 b/ r/* Start the clocks */& y9 K Q: G0 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 |! w) T' N# F6 ?' \9 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// ?/ M6 A7 M1 Q7 U% x; f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& o* ?" E @& f( Y- H5 t
EDMA3_TRIG_MODE_EVENT);* }% a- Q0 p9 x c! Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % ^+ x- Q6 L' X- O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- B, ^2 g2 c' P6 EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 l: f6 [7 ]/ Y$ ~1 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 J6 I; d+ a5 v- G6 L! zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& t. n$ r$ r a6 N) d+ j3 }- w4 ?: L2 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# ~- j( E, H+ @; g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 A y4 D$ s4 b+ r5 {: N5 I
}
5 m5 `' m4 z7 ?3 _: N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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