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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, t) ]9 y+ w2 X$ I1 d
input mcasp_ahclkx,
- |6 }3 e& Q& S! E& Sinput mcasp_aclkx,
0 N6 i( T- e5 |3 sinput axr0,, ~+ G, ~) T& e7 v
6 o, {0 N1 S$ |/ P* X
output mcasp_afsr,
; W6 M9 x, ~2 q+ e5 Noutput mcasp_ahclkr,
' h# ~7 a2 @3 v( H9 N! routput mcasp_aclkr,7 I/ C1 T! t/ ]( b7 [* J
output axr1,
5 @ L1 S- P- ?! a! G assign mcasp_afsr = mcasp_afsx;
7 a$ R) n/ f( z: ^. [# z) z) Yassign mcasp_aclkr = mcasp_aclkx;) |$ B7 e1 `! ^ C |! k6 A; A$ ~
assign mcasp_ahclkr = mcasp_ahclkx;5 t: m5 x6 P |5 D* N
assign axr1 = axr0;
. Q$ ]- y# {9 v
: {1 p+ `9 U. Q3 {! R. W; f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 O2 t+ K/ h/ @+ _( W
static void McASPI2SConfigure(void)3 A' m. T0 B/ L* z% Q; a5 Z
{' L& J; s' @ [* ^* d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, T; A! h5 P5 p+ f% c1 @; w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% `) N. @/ L8 c9 N: x! t" q/ V) I) R: ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- m+ S9 `3 z% ^" W* \* F, V2 r6 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 R. m' r. D: u4 \9 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ k- W. M! b5 B: d5 _- ZMCASP_RX_MODE_DMA); |3 }7 s9 d( x( l ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 W6 _2 d$ K0 O) P2 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' L/ N. l' L$ \) \' @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( I5 U5 o: K, h$ C2 N( ]5 \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 t0 F* t- N. U$ f; T% i! q% [' ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / y! O- X+ z: b: M, F# p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 J' J9 R4 G ] N' P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ W* w! C# F$ Y1 ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 t( T4 @; }! b$ J F) R1 ?& fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ Q! {7 \+ Q) ?# l7 d6 U
0x00, 0xFF); /* configure the clock for transmitter */) |+ r2 I) @; V. x% N1 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) V! L2 G, [, H" ]) [) W/ JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & L/ v2 _" e l! ]& T+ r4 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. e, d' c% @( G
0x00, 0xFF);
7 |0 f" m# D! @- K
: E- @7 K. y8 ]0 Q/ m k/* Enable synchronization of RX and TX sections */ , s% Y( }" J+ T: L+ A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: _* i, O- U, ~, _& _2 K' O7 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* V' @! }) q/ `! e8 E6 b# h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ Q4 P& w6 {7 J; z C
** Set the serializers, Currently only one serializer is set as0 y9 A! d' s/ B1 K
** transmitter and one serializer as receiver.
- s6 R _, T3 c0 o. A*/7 F( z9 Z/ p% Q0 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; ~( | }. b; A) U2 |6 _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( `6 m% S' q" `$ Z V, q- X
** Configure the McASP pins
7 C$ N- _: u1 q! b: y9 H" `5 C** Input - Frame Sync, Clock and Serializer Rx+ H/ X# E3 }4 |
** Output - Serializer Tx is connected to the input of the codec
" I! ^1 p9 ]# {6 R( h*/: ?* W" K" `' T- h' e6 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& X* J6 s9 n# b j" b% d, BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 U! o/ o' |/ ?5 t2 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 I7 E2 F2 \9 V4 J8 m3 K, B
| MCASP_PIN_ACLKX
* f2 n& G2 E3 i7 I) g- a- F| MCASP_PIN_AHCLKX
* s, A( R0 P) j& r2 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 ^6 `5 s. M3 w1 U0 p9 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 z5 D/ ^! D6 s6 y8 N0 W; _7 q
| MCASP_TX_CLKFAIL 7 B# g4 |; i l9 V: c" _( t, @5 p
| MCASP_TX_SYNCERROR
2 V0 e+ |2 ?5 A9 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR k. T% z: M+ q3 `0 F( K
| MCASP_RX_CLKFAIL
2 \ L% k4 o6 s7 W; c| MCASP_RX_SYNCERROR : Q6 K) n9 _$ a! r
| MCASP_RX_OVERRUN);
# m2 t$ V8 f" K4 N2 ]2 Z1 n} static void I2SDataTxRxActivate(void)1 |5 d# n! v4 g5 K) {1 |" p u
{& ]$ g( y7 [2 l) o* I( m
/* Start the clocks */3 [) K* |/ G; z# t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 x. f- i) j8 c( }- fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ Y& A/ U* @. QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 { l5 _% A6 a" b. tEDMA3_TRIG_MODE_EVENT);
) @& e3 O; K X! h: q6 X2 B, [$ w8 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# ?2 z* l" Y. W8 `3 }( gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* g1 b3 g- w; ~, }( r2 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& T4 u, M# ^; H+ f" m; @- lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ Y% Z, n* O9 ?1 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
H8 @( }6 `) U% r4 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% v: L; n" F6 M& S# o9 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, t- W( c: n$ p' y- E2 U, }
}
; g9 J3 ~/ \( Y, J3 s9 J& L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 h& ~/ ^( M3 u0 P* w# [7 r
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