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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ |' N. x3 e6 Q7 V7 r; Xinput mcasp_ahclkx,
$ [ N7 A! v* Q$ Cinput mcasp_aclkx,( p% z2 T+ }- y; x
input axr0,! R1 o% E; C0 N" z4 t r7 n# P% N5 Y. b
1 X; t" u* `6 Z8 k
output mcasp_afsr,5 L% e4 U j# U$ k1 {$ Q
output mcasp_ahclkr,
- C) {4 {) ~# D% Routput mcasp_aclkr,
8 n+ Q! J& Y5 v$ ~) ?output axr1,+ Z, D+ G% E8 j, I! p' B
assign mcasp_afsr = mcasp_afsx;
5 F; a& S% r. E+ Z+ n% x6 m9 Gassign mcasp_aclkr = mcasp_aclkx;- G! w8 ^$ H/ O1 [+ S& g
assign mcasp_ahclkr = mcasp_ahclkx;
7 u9 ~' Z2 y/ r- |' F! uassign axr1 = axr0; ( Z# q$ ~. q; }
9 y; \. Y. M. L- u! A# x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ [! B0 a6 f" |: rstatic void McASPI2SConfigure(void)3 k* r# ?9 X b, Q
{
( `1 U! l; ?" W" sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 I- a6 q" R+ p( GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 {( P% r1 i9 q; `' k& ?9 y6 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ |! a+ y$ J: N8 F8 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% R4 s; q6 B N3 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 R9 `; m' Y' Z+ K5 C: e2 y
MCASP_RX_MODE_DMA);. B' |5 \: j, D- W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! e, T" W( X* D9 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 W: y" t7 \ X, h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * z0 n H* t: z2 N# ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* ?# A2 R: z6 I6 z* }0 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! h) z3 |" V7 k/ n! n" w+ K+ j$ r& eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 S4 b4 y! V6 H$ R) \) D; \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' B& t0 w. L, L! { {+ M- j: |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- D, J4 O* D2 q) U# H) m( JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# }1 d: c& B0 I0x00, 0xFF); /* configure the clock for transmitter */
3 e9 s" |0 I+ K7 f3 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ W$ N7 ~4 u/ ~# ^) n3 k4 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : _* L6 G5 T* \. C. q% s4 Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% e0 u" i3 K5 v& p. q: u9 F0x00, 0xFF);0 \& u4 B0 u6 H" A' S$ [% A; d' m
. S. P* _% g" d. ~5 F0 _$ D' {/* Enable synchronization of RX and TX sections */ / d% U! V$ N9 G& k. v" Q: i) v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
M- A" _% r6 y) FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 @! N+ L: I( N# v* w- g& qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 O; B+ d V: j/ y$ Y( Q** Set the serializers, Currently only one serializer is set as
5 Z. Z% D" I5 ~8 W+ h# C! @** transmitter and one serializer as receiver.
2 p5 a4 q" y% B) w*/
& B0 e( A( U" a+ Y* PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 {. D+ Q$ y% _2 Y: o( W- u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 S; M' J4 U0 f
** Configure the McASP pins
7 }' `+ J" s0 W/ `2 z** Input - Frame Sync, Clock and Serializer Rx) O4 s. N1 ~( q8 y
** Output - Serializer Tx is connected to the input of the codec 5 {! e7 l, n0 R8 g8 s: J+ @
*/
; n& F; W2 n1 J0 f0 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- K6 s7 F; ]% k4 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ d! Z$ Q2 y. a/ R2 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( j/ e4 x# Y; t- ] b( U- x6 @- L| MCASP_PIN_ACLKX: Y) h H1 s8 p) J+ D
| MCASP_PIN_AHCLKX, r! e2 S7 E. k; Y& M7 G5 k2 Q8 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. G) k) y3 B: \* v6 A( }4 f9 N1 L' m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , a5 ?/ _' _! Q. T* D, K7 _4 w
| MCASP_TX_CLKFAIL 0 B; X) a! Y l7 A- ?; F
| MCASP_TX_SYNCERROR/ A+ e9 \, w7 f( m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % H" ?) P1 Y/ L+ z+ F
| MCASP_RX_CLKFAIL% U7 W3 S$ `# g9 ]$ Z
| MCASP_RX_SYNCERROR
* ?6 b7 z4 R8 R0 M( u, i* X/ {| MCASP_RX_OVERRUN);
* k5 E; F- J0 N4 N' ^' ]! I# w, T} static void I2SDataTxRxActivate(void)0 T( @. Z3 d! Z* {. f
{
# s: y& P) @( J/ K/* Start the clocks */
6 h2 R4 C i3 f" BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) v6 m5 b. g5 T0 u- M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! U% x- i+ t2 v( S6 V# k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 W3 ^( J7 U% H7 M7 U
EDMA3_TRIG_MODE_EVENT);- Z. B$ ]( }0 ^! y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 |, n$ ~. Y* m# N4 E6 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 s2 s! @. M. y& N+ z3 E) h: sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ a) J5 C2 X- V C( s& T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 q! w, |4 H) `% a9 w- g, R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. p3 z- O' J. v7 Y- XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* B7 }8 i! G, Y% _5 |& b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" q8 u G% ?( J8 U0 K* l, x
} - C+ c% E+ {4 u2 b; u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; e, v% Z. B, ]5 F9 L5 P: u6 ~6 ?# e
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