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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ b! ?3 H) w" d" s/ R; ginput mcasp_ahclkx,
; }8 }- f' O6 }2 q6 l3 Cinput mcasp_aclkx,: c, o# ~+ J& p+ b" Q* O
input axr0,
, Z8 O* y7 U6 R& C
5 J) ?; [3 c) W0 P; J6 Boutput mcasp_afsr,
: }2 E* _! m8 s$ n' O, m% y1 noutput mcasp_ahclkr,4 b7 Q9 o# `6 \
output mcasp_aclkr,9 }9 u% l# l! j' k3 b: ^
output axr1,) `: w! @8 z2 V1 N" \
assign mcasp_afsr = mcasp_afsx;' f5 H1 ^$ n _ U
assign mcasp_aclkr = mcasp_aclkx;
! C+ Y- F1 w: h! vassign mcasp_ahclkr = mcasp_ahclkx;+ n# w5 k, |8 F y; c2 @
assign axr1 = axr0;
+ N9 ]% N1 y5 ?3 a: n @; b5 `
% T B) c2 M4 `1 m1 c% P4 s. @5 L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! [, y6 c: b3 g5 Z, B. B8 A- L% I0 zstatic void McASPI2SConfigure(void)4 m/ I, b4 F- i$ o6 ^1 x
{
( j3 z7 C5 h, Z# o' eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" e8 h( X" c( ~# n0 ^1 ?' v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 O7 `0 M {# E% NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ?# @: e0 v. J8 _# s# MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 Q8 A0 ^ R3 U3 M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 ^ b9 i: {5 c& ]1 h2 y: b- J6 x
MCASP_RX_MODE_DMA);' M! W! @+ J# O" V+ w0 ?8 h* B8 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 y" {" J- d6 l0 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 I0 Q+ E/ s) g- ?# nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% n8 P$ _) v2 E4 c: d. K1 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); F, f; k2 f4 K7 @0 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . Q) M5 W7 C/ C* Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
T( @8 j$ V# O. \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" Q) ~5 ^* L( t. f% ?, I7 N! bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 M) G t o% G9 e. b% C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: n2 A# X4 ]0 q" G5 U- m$ b0x00, 0xFF); /* configure the clock for transmitter *// m5 L/ A, f% S2 t, E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! A, o9 x I% t. g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- p: W1 B# m1 |) G" eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. R- m. _6 s3 W
0x00, 0xFF);
6 l- r: e1 j2 R$ _- Y- m; c; h4 q; t; J- o. w4 k; c- D
/* Enable synchronization of RX and TX sections */ , n7 Z5 y0 A! w5 S' H7 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 \5 w7 d d# C# _. I4 f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ H9 u3 l- r$ n, Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ W# U9 U' ]. o. Y6 O# r; S/ n' Q** Set the serializers, Currently only one serializer is set as
# X" D3 j- i" P& r# v8 h6 ?, U. m3 ? q** transmitter and one serializer as receiver.
( T, b, T- ^8 O2 k*/
: l2 M3 Z* C3 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& M. |; L0 D4 Q# h( b8 O& DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) O+ a' f+ b! B: a+ _. {+ e** Configure the McASP pins " H( `$ F. T* s; ]: U; ^
** Input - Frame Sync, Clock and Serializer Rx a: D1 R+ a$ M6 G
** Output - Serializer Tx is connected to the input of the codec - m( |1 V# M5 v- H, G
*/
7 j) J, f8 ~/ A q# ?) [& fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( S+ J. k& f4 p6 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); L' ^ Z. S. o, d) f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ o; X8 O- L+ x) p: B1 h
| MCASP_PIN_ACLKX
5 L# Y2 b- D4 O/ P, G| MCASP_PIN_AHCLKX
; d5 b/ z' t/ `% e% R2 ?4 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 ]9 y$ @3 g# D. j0 W% J9 q. dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; I2 @" k7 x! B; e) x' v0 _2 c
| MCASP_TX_CLKFAIL : c0 ~; o: g( @( a$ p! m \7 n2 j
| MCASP_TX_SYNCERROR
8 i l; `1 F7 f& c$ p( e) g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 T9 I9 Z5 | ]* ^" l* V% I| MCASP_RX_CLKFAIL
. `$ P8 ~, t t9 ^( g) h| MCASP_RX_SYNCERROR
) |# O! u/ h% E& M. V. b- K$ v; i| MCASP_RX_OVERRUN);
( S# ^+ J( c5 g d! d" @} static void I2SDataTxRxActivate(void)
' Y# X! L; ~( z5 ^9 z{
% v9 _4 C% X# U5 ^/* Start the clocks */
' h' c1 ~5 J, n9 R5 @! S% nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' M- t+ N. q/ dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
k8 P! ?4 n7 m, {8 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* N$ n9 [7 H) m
EDMA3_TRIG_MODE_EVENT);
) s4 m. c1 D/ {. w) VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 a4 t4 D3 D7 C& _- {4 M T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 m, _! F5 f* tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 C% x; q3 L: P$ R p; O" s5 Q3 ^, h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 r/ |0 {$ k: y0 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 i' b$ O8 n) ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 m$ [1 Q& X2 Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" c1 K, I. E( N5 K& S5 g8 ^& u}
8 a$ @% M- d3 c) @5 p$ `2 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 x3 _2 K" y9 |4 }! P+ m1 z
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