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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 ~+ D* k7 T% t7 Zinput mcasp_ahclkx,) [, j% N2 P5 Y8 K+ n
input mcasp_aclkx,/ F- o' g r0 o( M4 e& ^
input axr0,) x9 W6 O/ G: W
9 m: G/ k; s1 V4 Y6 F) ~
output mcasp_afsr,
2 H' X8 P8 D9 {% S5 v# houtput mcasp_ahclkr,5 T# G; J1 B4 \9 ^, { P3 H* G
output mcasp_aclkr,
( s# o8 F$ g0 R& Q) Z# ioutput axr1, E: r9 r9 C4 h: D
assign mcasp_afsr = mcasp_afsx;
; r) [! M% y6 A5 @; xassign mcasp_aclkr = mcasp_aclkx;4 R* K3 [: ~5 k
assign mcasp_ahclkr = mcasp_ahclkx; H6 `" q) o- m Y% T7 Z( Z4 ]* l( `
assign axr1 = axr0; + y' Y. i" M: {! w5 H
$ m- H& I+ J, W0 K1 Z- S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' X, g& Z2 l$ Z+ ]1 k V
static void McASPI2SConfigure(void)
& j2 r# I* n: n# }! z8 j{9 B6 u4 c9 P/ x* a# M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 y/ W0 d% P3 ?' D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 [) e4 I- a# t- p' M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 ?: u$ J" Y; E* ?3 k4 v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! k2 u' G6 j+ T0 V% W# F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, }9 r7 t; U: a% i) gMCASP_RX_MODE_DMA);
2 r9 c m" L2 c* Z$ _7 {7 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 d A% G: j6 S- b, x+ n) h& g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: Q/ l' ~' `. q8 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( f& l4 m* }( P! YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. d. i6 [9 P7 a2 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' ~! L1 u) [% |8 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ [, [. h: ^: R& T6 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. i, Z5 Z6 ?3 J" N+ E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
}/ h( L Q9 [/ \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) Q9 K) n% `: u
0x00, 0xFF); /* configure the clock for transmitter */
* `- W" F- S: B. eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 V2 ~. Z% z& J; z+ o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . F) G" U. N, k, ? C5 S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: v7 U$ {2 u* \: u7 q( b5 A0x00, 0xFF);- J" }0 q: U# J0 E( ~
- e1 c0 \" v* F) P! s
/* Enable synchronization of RX and TX sections */ 6 ^5 A0 p2 C! E! B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ K( f w) s# |: s* G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 o8 E+ @% a. F1 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 X# i" j! v# {1 @5 |6 k
** Set the serializers, Currently only one serializer is set as
- s* b) o# U( O$ x8 `** transmitter and one serializer as receiver.
0 b2 a0 F1 Y- X2 s1 x: b, k0 I& b# `, e*/
* i0 Z6 O% H% T* Q, \3 Y4 iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: n% t ~# u( }1 h% C6 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c1 }& y4 z1 L- ]* Q/ \7 _! {6 q+ i
** Configure the McASP pins
8 K# m9 p% d$ Z/ [( R" i2 O** Input - Frame Sync, Clock and Serializer Rx9 K+ z; A ~7 J. A& ?
** Output - Serializer Tx is connected to the input of the codec
; H E* x9 e1 ^$ ?( e*/2 Q7 |7 Z% o" S# f, N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# ~, y( Q7 M2 m8 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' _- `: `$ i: Q- a4 H6 p; `5 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 v2 Y8 D, T' g+ R+ s
| MCASP_PIN_ACLKX( c- `1 z( n, S' H% K
| MCASP_PIN_AHCLKX
2 p: p* n. Q' M6 Q1 m) K' P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 {) f* y0 k+ g# J* m: BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; E- X! ~+ P) `
| MCASP_TX_CLKFAIL 3 B( c# \* a' K! e" }
| MCASP_TX_SYNCERROR
+ M6 `$ c+ v. _8 @+ C& I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( a7 P7 R! g$ P: @' G
| MCASP_RX_CLKFAIL
! \% Z G$ v! q| MCASP_RX_SYNCERROR , B, k; d/ G2 k
| MCASP_RX_OVERRUN);
0 t$ ^. g0 w) H! Z y" _} static void I2SDataTxRxActivate(void)2 Y U) }3 L5 Y+ Q: ^ x
{
8 H; ?1 S5 H, s3 J/* Start the clocks */9 h5 ~6 F, p! U$ Q/ n1 G* `# h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# m3 B, z+ m: A! t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) n3 H0 D a, Y4 p4 ^* v6 D0 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% @& a `8 z, u" Q8 t4 j
EDMA3_TRIG_MODE_EVENT);
8 A2 D5 u, o& U( w* pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 M8 d5 r$ Y- Y" ]- E4 S3 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! {1 T. {8 f5 d0 ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 r& N7 x8 k. X* U. \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 g! ]5 p# p# @, V, n3 H- H( {, owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 u! q- u) a# p, I* P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 c4 n- @: P% ]. U9 h# X8 o0 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 h9 J' C( q% Y0 k9 E* k/ g4 F
} - b k0 K7 {* ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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