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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! U) V& J8 Y, A! m
input mcasp_ahclkx,& V2 K( A+ z" X$ h3 G6 p! l" {7 o
input mcasp_aclkx,
" j( P4 E4 J, F: q( minput axr0,
$ }/ Y; i* a4 f% }7 m
$ a) }9 I* e# N$ S9 ~1 N7 Moutput mcasp_afsr,
1 ^% y& k7 o X6 Noutput mcasp_ahclkr,1 o- h' y* @# j- o3 L" S
output mcasp_aclkr,2 h! V) i! j$ ?7 }: {
output axr1, v% v% t: b0 i$ J1 A; U3 K
assign mcasp_afsr = mcasp_afsx;+ x0 ~) S d" v3 U2 \/ D3 o
assign mcasp_aclkr = mcasp_aclkx;% v) U7 b I1 K( Z( W4 T
assign mcasp_ahclkr = mcasp_ahclkx;$ B- @' d/ G' G+ U7 w
assign axr1 = axr0; * r3 `4 t9 N" e+ d. t7 Q, X+ v: D
3 u- z5 K4 k8 F, ~- P2 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 h3 i, g) A! Q" T0 ~( hstatic void McASPI2SConfigure(void)$ E8 ?6 [/ i4 h7 z8 t# p
{
8 V3 V4 f N% P. LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- b! j' i. h4 |% ~- w( o0 j& J- eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// v( O' I- A. a- W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: i- P8 I' b) C {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" s% @3 [2 f( c3 @2 a; q* @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" O! V7 K% b- P7 ]MCASP_RX_MODE_DMA);9 w U2 k7 d `) b. k& S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 M7 [: S4 }6 ]& u o( ^2 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ ]5 S' g# W+ z, t4 [$ M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ G' I @( `; U, `0 rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- b n" V/ j2 {, k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 ^, A' z# k) j: |( m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) X, h# W% T: k2 k7 g. I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: R5 p4 D9 W; s" ]1 M+ H' G3 w( q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- p( t6 P- N3 \; \: F5 l% h/ {( YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. I( ]% C O! b6 T
0x00, 0xFF); /* configure the clock for transmitter */
2 ^( q. s/ X" L+ _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 A' b$ w9 F0 w, K3 u* e6 U+ SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 h/ n1 i7 B: l: ]6 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( c6 W7 Y M. k8 W+ M3 ?* M0x00, 0xFF);
5 r, `+ F, f3 r# {/ \2 T
3 n% e* d2 x' ?" b/* Enable synchronization of RX and TX sections */
& e6 }8 s7 h6 K0 x: XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- \" D7 ]/ `. z3 N- j# Z" q* g$ vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 W- c* h" B6 X$ ]0 {, o" f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 g5 G/ k% k* U
** Set the serializers, Currently only one serializer is set as/ n9 F, C; o W7 n- s u& b3 r
** transmitter and one serializer as receiver.
. |4 K: d M3 r4 L; @2 y. o*/
0 W' B8 r ^; cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* e2 T. F+ |( u: M, nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: o$ X" \# p* |- H6 v6 O' J# O** Configure the McASP pins
9 H( a) q. K: K: V# j: ~9 ?$ P) c( \** Input - Frame Sync, Clock and Serializer Rx
! Z/ f, B4 R9 Z6 Z$ i0 g5 }** Output - Serializer Tx is connected to the input of the codec
- e( t& u$ w! {. Q- g& L8 A, ?*/( H2 \* |. I! Q" E5 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 y" {1 h& `9 q! o/ I6 v4 {) M5 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 \2 l* J% S4 f1 r$ B6 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 i" R- f! j3 o: A/ u
| MCASP_PIN_ACLKX% v8 i2 M; ]" t" d7 H
| MCASP_PIN_AHCLKX
! b! L( Q u! A+ N( [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' k0 s+ ~0 m% [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 a( |6 N# D a/ U% H5 f9 g K* H' @| MCASP_TX_CLKFAIL . f$ w) C8 D" d: q( C& a/ t: y! ^
| MCASP_TX_SYNCERROR
1 N: `+ q/ Q& a: K( b5 K& S! X+ y9 {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 R9 L( z G+ @
| MCASP_RX_CLKFAIL
# t6 N% d# u& O. ^| MCASP_RX_SYNCERROR 5 U5 `! ?2 _3 D: q8 [: [* x( J Q( X
| MCASP_RX_OVERRUN);/ Y' V0 A' U9 I* n- A# \
} static void I2SDataTxRxActivate(void)
8 X& |0 R; z8 u4 p{, j1 ?/ A; x9 k: F+ G. q `# B
/* Start the clocks */
+ E, u+ V$ m O) C6 d7 C) R( bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* p% q( ]/ X3 s2 F3 K0 i0 p4 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' t8 e4 j* j: G8 h% p+ x% v$ u7 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, `0 M: L, d, N9 k5 ^ e$ A% K
EDMA3_TRIG_MODE_EVENT);) ]- c/ g; e$ w5 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ z- p, y) X. ~- r+ d2 a3 B5 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* x% [/ ]5 F8 I1 T4 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" J. n; t7 e1 M7 K7 m; y! gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) E! u$ o+ `- q k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ~/ i0 _4 U8 o t/ N# d7 D8 K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 D9 S& M8 \0 r2 E5 l( S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 m( |1 p! Q. H- H* ^2 q* k} ) |1 ]. [2 ` l8 }9 a0 z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) y* c* u- B( d4 E" m( K
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