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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; x) Q! G* p5 ^, V1 C, |
input mcasp_ahclkx,6 k' }4 ]. I ^/ x
input mcasp_aclkx,
( D; w& R7 ?! Q% m$ M* tinput axr0,
7 |1 D0 _, h5 H |) q% h6 p6 j5 ?3 S
output mcasp_afsr,
! b/ g9 u$ o7 }) ~; Soutput mcasp_ahclkr,$ V2 D* ^' J, ~0 d6 `5 z. E
output mcasp_aclkr,4 V/ |7 }$ c0 R- V' \' a
output axr1, z, @+ ?. F8 [ z0 q j+ {: L
assign mcasp_afsr = mcasp_afsx;
8 e( H. \" h. x5 `; [ bassign mcasp_aclkr = mcasp_aclkx;) D6 @. x0 A4 l, i
assign mcasp_ahclkr = mcasp_ahclkx;2 N" m' T% Q8 W
assign axr1 = axr0; . I0 K8 R& {0 c4 b+ u$ T, Y5 O% u- F+ i
) }7 r" b3 `3 m$ }* \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 [0 L2 `5 C( d. C% Estatic void McASPI2SConfigure(void)
# w% h6 s' d8 o" W6 l- n{
2 T, D/ x! J4 Q" @' t. [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: h5 v7 Z$ f6 B; g- T- N! XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" x: C0 g" Z" k5 ]( K. ]. W8 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! a# s o0 i% uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 }* l! p7 `# g5 b% C$ _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 T& L, T7 K/ f: dMCASP_RX_MODE_DMA);
; M7 i8 I" i+ H R/ k4 h9 T; qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, \, F) E3 d, t/ ?' C/ k5 u/ k! m/ G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* C H/ s7 P& o' VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! w4 q7 \, g1 R% n2 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* `8 }+ o) v) S8 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
S$ A* \; U( }( q9 o: gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 I5 r8 I( c3 y" O) pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; f" ?5 ?/ L! ^$ wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 U1 Y8 X. S9 f) p/ `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 b; k) P2 e$ d: C; q @! c
0x00, 0xFF); /* configure the clock for transmitter */
/ x" I* W+ S: I# U# s( U/ d+ oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. ]4 z e, \7 }; l6 t, x, [; _9 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 }; g2 f! |% ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 ]7 A, F: s6 C+ M4 K
0x00, 0xFF);7 u' ]# b5 @% ?3 Y. {3 I, J
7 ?. u1 X4 w6 A# b/* Enable synchronization of RX and TX sections */
( E0 S) y0 Q& M2 k8 b& NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- k c5 B& R% XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 h: f+ b( w6 c" z( |7 L* O. uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 U1 @9 h% W* d* ]** Set the serializers, Currently only one serializer is set as# ]1 f9 U! o, b
** transmitter and one serializer as receiver.
. C6 C- I7 A2 M+ T. Y*/% [6 t4 ^* e0 t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 o0 ?# q0 q5 D' }6 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 J5 w2 g! z9 m! c
** Configure the McASP pins
/ Q. k7 u0 H9 j( w% G- ^, {** Input - Frame Sync, Clock and Serializer Rx& c1 q, {) v# j: I# c
** Output - Serializer Tx is connected to the input of the codec
% Z8 i" ^! Z5 `, X( ]*/& S# ?* f4 n9 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; a) a0 b# M: X# o& vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( L; w7 R6 `1 B. r# f1 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 C$ P' |) k1 V
| MCASP_PIN_ACLKX8 A4 s8 e2 L$ A4 `% I
| MCASP_PIN_AHCLKX
' e1 S2 K7 e R3 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// a0 v( S( E0 F% `" c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : g* j. o; G, H7 r& Y3 W
| MCASP_TX_CLKFAIL
s0 v( f- W2 O' P' ~, N| MCASP_TX_SYNCERROR' J5 r, S1 k' t- |: Q; `3 h( |3 v% N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 G. R/ G7 i% @$ e- G, s8 r* N| MCASP_RX_CLKFAIL
1 a3 B. X5 M; Y4 U2 T| MCASP_RX_SYNCERROR " V) m# m( n! U# _8 I: G i
| MCASP_RX_OVERRUN);8 ?, ]9 P) A- E3 p9 q' c6 N2 y! [
} static void I2SDataTxRxActivate(void)
5 O+ T6 [; r% P- Z$ V{
4 O0 @9 @9 |0 Y& L2 H( `! `. e$ e/* Start the clocks */$ u! H3 ~) R+ n9 j, W, ^& ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) U. q5 a1 \, Y; w8 Y& O" hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 q- L/ }8 N8 I. [+ c {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* v9 g- ?3 s# M$ ~EDMA3_TRIG_MODE_EVENT);8 Y8 @* M) B6 j% c- S0 h3 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, e S! e9 q9 c$ o/ ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! B6 s J2 W4 Y, P a+ W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ G. J" z; C- F! \0 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 Y& {7 `( y* {- t$ Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, k8 E2 Q Z- q0 a4 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ K5 \- c1 Y( m# o0 Y7 {3 }* BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( x' q+ q1 ], h* A} ' j6 f4 K: A! j/ ^3 e% y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 B0 W. L% O' C% Z4 {8 ?
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