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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& H& T; I) m9 s& h6 N' R
input mcasp_ahclkx,
1 l: W0 A: g" K% @input mcasp_aclkx,, ]$ O" A2 V) _3 b
input axr0, Q& G! Y% H2 q+ w9 W M
* A0 e- U# k9 j1 U7 B! C
output mcasp_afsr,. k, O+ w# _: H
output mcasp_ahclkr,. w% J* r( t2 Y; `1 n
output mcasp_aclkr,+ j; f. y4 E+ _5 m- y H
output axr1,) x5 p3 w! H3 \/ E5 X4 G- P3 s% J: }
assign mcasp_afsr = mcasp_afsx;
3 q) v) s- p+ `5 b% E1 p$ Hassign mcasp_aclkr = mcasp_aclkx;0 M1 I9 M: s& H5 ?1 X
assign mcasp_ahclkr = mcasp_ahclkx;
$ F1 k% D# |0 p" Lassign axr1 = axr0;
7 l! _- o5 H/ Y. o9 W5 O& j! Q! F a9 \! W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " A" N" x/ F# C8 _5 e
static void McASPI2SConfigure(void)4 Q2 y) ^0 Q# i2 w
{
/ q% R- e9 @8 P7 c- s+ m. A5 s# l- p$ XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- @) c# }3 g Y9 N, X; U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% @! c2 D0 Y9 l2 v. f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& d/ m0 r# `" f* b O, f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" r( Y8 | s+ [ Q# L9 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ f. H E2 \- B X) l3 ~$ Y8 MMCASP_RX_MODE_DMA);1 k" o. Q5 e, u( p8 n. r5 m6 V$ j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 W. |6 M4 d O- q& B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ [" K. _" Q [* R" IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / j2 k& v) S; H$ l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' F2 v8 ~2 }$ C. eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # y1 \. a3 q$ L, m# k( B1 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 X- F) t& W2 J& i& ?) G6 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- S1 v4 {. q! t7 H$ I$ `- }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* F3 ?" Z% f0 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
Z1 `' Z4 M& y0x00, 0xFF); /* configure the clock for transmitter */
5 N3 T7 q1 B) v! `9 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) F I" [5 \: U- l1 [* ~- _1 u5 |' a" `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" Z' G) `3 o6 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 W! S% f5 w# W5 G0x00, 0xFF);7 J4 z( l2 j: R0 _2 @! ?- L; X0 u
3 ?8 o8 l0 f5 ]- K' y
/* Enable synchronization of RX and TX sections */ : \ S% O4 T' l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 I9 c' E$ U* _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" }9 \; V* @" e) _: z" L8 W/ o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! a# a5 |$ H) b( k+ N' X** Set the serializers, Currently only one serializer is set as
, ?" }/ \ _+ `4 C8 R5 l% W** transmitter and one serializer as receiver.
9 [( M5 J' \( D I! k9 U' y2 L*/+ j+ u3 |' B0 j) T( z4 Z0 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" i+ _0 P1 B; w" g* k* Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* V- U+ {3 v: k$ x0 M: A! A; K3 J** Configure the McASP pins 0 N4 I" N: m$ A& E, w
** Input - Frame Sync, Clock and Serializer Rx) E: Z! c0 O! ^$ y; |6 ^: t
** Output - Serializer Tx is connected to the input of the codec
( L- @: b) I+ c9 O* t*/
, w1 Y C8 }3 ?" D+ C0 j& xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; }8 y" [3 Y/ j3 p$ zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' g( S! v+ C+ H6 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' @: _1 \: n9 K# b6 t7 ~| MCASP_PIN_ACLKX' K+ O4 l+ M" J7 _3 g# d
| MCASP_PIN_AHCLKX6 G$ Y, ^5 i, F' A4 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 R* }$ |* M$ B' C/ n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 C( E5 C/ }* H5 b2 a/ n; d| MCASP_TX_CLKFAIL : y9 h# _6 m; Q+ F5 ^3 _- I& u G
| MCASP_TX_SYNCERROR
- H9 @% K) }$ n! ?2 q4 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & @% V' K- q0 y2 k: O1 C
| MCASP_RX_CLKFAIL, G0 j) A2 p' L$ d" E
| MCASP_RX_SYNCERROR
9 Q, y; S9 @" j, w| MCASP_RX_OVERRUN);
) e9 n& E% f% g6 z P F" i} static void I2SDataTxRxActivate(void)% w, @8 X& x8 B. @: i1 w c; c
{
/ o- j5 W- `+ g+ K* ~4 Q/* Start the clocks *// }+ B! t. d& s5 ~" U" N* L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 i2 V6 y+ L% ?; \% n7 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# T1 y% a. v) x, O+ D4 ]" ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# Z; b8 t; I+ v0 }EDMA3_TRIG_MODE_EVENT);
. S2 n4 s% z: N3 N- |) r' u3 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- `; M8 f9 z6 \8 t# @9 B9 d1 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, J5 |* p( E# Z9 ?! E$ z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 G# {: j% [6 l' j+ M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! v3 |$ c8 e4 g/ ]8 ?, [0 I0 twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 O. ]) h% K8 e4 [9 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 ]3 ` Y `* X9 Y! y5 d# @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& l( I7 K4 Y2 j- k: s
} 6 U8 |# E' y! G) F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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