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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, f- ]+ n! l. }9 T* m' y* ?input mcasp_ahclkx,
& P, b, P% d4 ^5 \2 i ?" h: i! einput mcasp_aclkx,( d ^3 d& I' [$ A3 ~5 g" N
input axr0,
; r+ I6 a. a, ^ d2 |0 ?1 W D4 ^& l
output mcasp_afsr,6 `% C h! |# ?4 Z! [
output mcasp_ahclkr,% |) ]' @2 ?- \
output mcasp_aclkr,
: ^6 V7 }% O4 s( t* ?. F7 R4 zoutput axr1,
; K9 ? @- q# J0 \5 y; y4 t assign mcasp_afsr = mcasp_afsx;
$ o, S+ z! J5 q3 _) o% T- y$ `assign mcasp_aclkr = mcasp_aclkx;( G0 i0 \4 } Q) `; s( w4 y
assign mcasp_ahclkr = mcasp_ahclkx;9 u T0 T: O9 I5 C1 i# v/ F# t
assign axr1 = axr0;
/ F7 o; u) b! M; m) ~- O4 ]
& z; N: n+ Y8 Z* f% J& W# A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ l. h9 ^/ M2 P1 D$ \static void McASPI2SConfigure(void)
3 Z0 u" }: k6 u{
1 o8 q- Z8 D$ Z8 H2 g5 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 l) @8 _0 L+ U9 {' ^/ G9 v, U: k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- O9 ~7 P7 v- M9 D3 z6 Q$ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& c& t1 D5 B* ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 c% v' c" S# CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, I' n) b z# D' i* n
MCASP_RX_MODE_DMA);- g/ e6 l {; o, ]+ D' u* m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 H/ ^9 d: {7 Y$ L& ^3 E" h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! X' W& ^$ H8 d0 x8 ]2 |5 y8 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ g- e1 W* p( K' l+ uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 i4 c& Z7 q* z# i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 B1 X! F9 g* D8 M" xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; G' k. s C6 _1 D% v" CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 y3 u, C" C1 P% P8 a+ L: ?+ v8 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 a& E7 E9 f2 p9 t0 X$ p" ]& ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. x- K3 W. E3 q0x00, 0xFF); /* configure the clock for transmitter */
. d; M2 y* G$ u9 N" _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& s% e c+ j' v$ C' V5 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 l9 E* C5 w, { }4 C0 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 _7 W3 o- p4 f& Z: _3 ~: y: J
0x00, 0xFF);
3 T# Z3 F. I! t" K- q
# U: J# k2 W5 H/* Enable synchronization of RX and TX sections */
; \* N- Z0 M$ {+ F- vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! D+ f8 z# r/ hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 _: o7 l) Z, V. o9 g$ q) m/ n" ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! _! I: q5 U" T* S" R: z' f- F) i
** Set the serializers, Currently only one serializer is set as8 n# V7 f/ |- r* N: S
** transmitter and one serializer as receiver.
. U% N+ Z+ q" t$ O; K2 V*/) u; }; S% A% p- u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ z5 y# w& C. D M0 m- m G4 H/ O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 @* L, s; G8 Q% M$ D% G- R3 j
** Configure the McASP pins ) `7 }( S8 u( S, q0 q
** Input - Frame Sync, Clock and Serializer Rx2 e8 S- p" @/ y# S7 r
** Output - Serializer Tx is connected to the input of the codec * E$ o& p* L3 }3 t# J0 @, D
*/
/ h( I! e5 t& j nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! ]: {/ P% e2 V$ l, RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 D+ \7 {" C9 E% Q3 w! |0 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' c8 |/ t' }0 Y* I m
| MCASP_PIN_ACLKX& q, t4 k* [* V R2 M, g
| MCASP_PIN_AHCLKX
5 ?9 T2 y; v5 ~4 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. i# j8 u5 S2 ] M: Q6 z* G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! u+ E2 v, B4 J/ A+ [
| MCASP_TX_CLKFAIL
( K6 L- M) d, } l2 [% T| MCASP_TX_SYNCERROR
2 X O9 V" U& g& ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ S+ p9 z# c' g8 o+ @' Z0 ]| MCASP_RX_CLKFAIL
; R. q9 A: `( ^( {, O| MCASP_RX_SYNCERROR ( M" C$ y* M$ [% p, `8 } u, u" F
| MCASP_RX_OVERRUN);
: g. O! @; J/ t$ V! Q) ?% k} static void I2SDataTxRxActivate(void)
( e# G7 {5 ]. N1 x4 s2 e{
' `9 O" r1 x; t6 h0 Q4 Y1 r) y/* Start the clocks */
/ K, O# j0 a4 ~5 U: V5 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! \, z2 [! P& l) d- F5 O v" E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( ~, B3 C& y' F- k9 C- `/ O sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ f% y1 l* b" N4 T1 ]/ dEDMA3_TRIG_MODE_EVENT);
: D. [. A m0 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . e! R! l- L2 l- Y5 K) i- y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- L V8 O( |6 C, {7 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; O# I+ T/ O8 ]1 C3 I; i4 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& O% F" c1 G& c# c& lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) C9 U9 o) s) Q7 o& zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, [# b$ a& T3 v; o: S. E* _4 n# I% L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* v( Y1 |% O6 R) _" ?5 S- Y: b}
+ @5 u- t9 }8 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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