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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ _0 c* F; ~, U! Winput mcasp_ahclkx,
: [5 U. O b9 w% U3 }7 F) l9 Oinput mcasp_aclkx,8 N6 _+ j! H4 y k2 ]! J8 b% e
input axr0,; P) [5 U# O3 J1 _+ m, f. P( f
2 z7 k, j+ h4 Z$ n3 x K+ Z
output mcasp_afsr,
+ N1 n3 _) w" e- w, |4 Routput mcasp_ahclkr,
1 u6 |' q4 Q4 a, w: Routput mcasp_aclkr,! m% v+ e4 P- `
output axr1,) w) e; z6 B# p" y
assign mcasp_afsr = mcasp_afsx;2 d! X! W) O) ^! o
assign mcasp_aclkr = mcasp_aclkx;# k+ S6 I% h: D2 ]3 J/ Z5 y$ w
assign mcasp_ahclkr = mcasp_ahclkx;
7 k) ?( H+ {* c3 Eassign axr1 = axr0; ! k6 f k* l! c/ H7 i# I. x1 J
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& c" M4 U3 _ V- R9 nstatic void McASPI2SConfigure(void)
7 ~6 Z2 S3 K1 O, j7 f{
0 c, z; B- O) q5 d( mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 P* U5 `* b X$ ~3 r# O! |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ k4 n' l, X. h* OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& {9 A6 k/ {$ z' R% `: N* vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ r( k9 y: M# t. y, `9 t! rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 b/ G+ K0 M/ w& n' B- O' A! G
MCASP_RX_MODE_DMA);% x4 H! M! ~ l1 h$ A: U( h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( p$ Q0 ^4 k7 h1 @, bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 n, k# i! K7 Z2 B* i- n% ?1 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: J# y. B) s( _9 n2 W1 W* wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& q# ], r7 B0 y- b3 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - k+ j" |9 [# y6 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ c# W/ a7 y# D H& vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ z6 N- Z8 V: S$ IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' ~. Q+ C* g) M' d& o9 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 O6 D% @+ d0 I, o: u8 n/ l+ w0x00, 0xFF); /* configure the clock for transmitter */
0 R- t9 |, w8 y' b' A& V7 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" x0 ?' J# V0 k7 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% E% v$ P4 q* u; o: y: {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, ~5 b; H+ A8 d: S
0x00, 0xFF);
2 t! `. H& y. }- `8 x
! ?% O6 I; H$ m# | O: ]; x9 ~/* Enable synchronization of RX and TX sections */ , l# z6 d, N6 r7 q7 \- F$ k" d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 p9 e+ ]5 x+ l9 Q; E; h+ |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ y4 r* B9 o4 Y8 w2 f% X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 v2 P7 [7 k" ?" c& N** Set the serializers, Currently only one serializer is set as/ ]( b) l) }# r% w4 A$ @% y$ R
** transmitter and one serializer as receiver.# J W( F3 g/ }! }6 F
*/
; o4 H. r! J/ m8 {" VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, E) K$ e4 a Q, U$ h' G$ f# I8 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& r' t: m/ B- w- F; \1 X) q
** Configure the McASP pins 2 x8 U8 U/ | D) f* n/ E
** Input - Frame Sync, Clock and Serializer Rx& E& n3 h8 x6 f- g& ?2 {6 E( P
** Output - Serializer Tx is connected to the input of the codec
1 {1 {* B5 Y# g, @3 ]) v*/ J9 X7 t0 c9 z- C5 Z$ d7 v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( F; B: b; P, B# Z# d7 V" u7 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- v& x" o H; ^: B8 w& I/ cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: E& E; @/ S# y; p$ Z6 ?4 p| MCASP_PIN_ACLKX; G' M! _+ M e/ G
| MCASP_PIN_AHCLKX- T5 o1 X" G, c8 S* T7 z( P/ V+ T/ S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 x+ Y- r1 C! Q3 I% [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- h- c) h2 s" m4 R| MCASP_TX_CLKFAIL + @" r; k2 T: e% o7 b# }( }
| MCASP_TX_SYNCERROR
6 E! U: F3 l7 p6 _+ b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : H# h% }: w. ]. x
| MCASP_RX_CLKFAIL
0 [: s6 [3 |* a) \1 E| MCASP_RX_SYNCERROR
( b, {3 f W- s0 t| MCASP_RX_OVERRUN);( P- B( S1 I# H: B% T
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */. v5 m( p4 ? p2 H/ N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 O$ J7 U/ }% @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ x' \9 d) `, V( uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# `# Y: i8 i( _% e" tEDMA3_TRIG_MODE_EVENT);
) r$ u6 `& [ R' v4 A3 y4 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 |% A7 M8 @% k' P5 C9 r+ m$ `4 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 o6 F, d6 \5 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" D4 E' _) p' Z, c7 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( U; N: }% C7 L/ @" T6 twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 L$ o5 `0 r3 b: t4 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ ]( P* {) @ K! k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 O& z: H8 f$ o: G+ O$ _- a
} " b V' `' E) A/ @9 n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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