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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' w" j( W: W9 r
input mcasp_ahclkx,
. ]) }3 @# x" o' a) [6 a: x1 Ginput mcasp_aclkx,( L; r$ Y, `3 T+ ^7 @' T- N9 R0 D
input axr0,
$ C6 w: V8 e) h+ v# u8 b
, w8 F0 C i) Y* K$ Youtput mcasp_afsr,& Z9 {1 H: d9 R, U; c
output mcasp_ahclkr,
2 l! A7 o% h# a: ^" ?$ g, M4 O$ ^output mcasp_aclkr,
3 E$ O+ f m8 Q$ u" ?, `, Woutput axr1,, H: {* P# |' `7 W
assign mcasp_afsr = mcasp_afsx;$ i. u# z* X5 G3 A" Q
assign mcasp_aclkr = mcasp_aclkx;& V# l2 A7 y9 }5 r$ w7 `
assign mcasp_ahclkr = mcasp_ahclkx;
# ~# l4 Y/ j+ L9 X D7 Jassign axr1 = axr0;
4 B1 ]( J4 u! ]1 z% U8 f
; h+ H3 u# N8 M2 k3 s; q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - V3 ~( ]! n! D7 i- S
static void McASPI2SConfigure(void)
# ?+ ^2 Y. N1 X1 y9 E& O5 j{% Z4 p/ q Q- C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 ^* z2 `( w. H5 T" }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- _9 \& t; H4 `, f5 _: `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 S4 Y& u, C/ ~8 ]' b1 T2 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, ~0 c* m- G1 y7 B: tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& \7 P+ l1 y7 A+ C# c$ i
MCASP_RX_MODE_DMA);% S- T! t& a5 r8 [& [' l7 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 M; l2 k; o; |" j9 Z, V2 ]' ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 v9 Z$ I1 ?0 p+ Q$ JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 m5 w) Z2 h- d1 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 L3 t$ @3 X9 D. @9 A; N- S [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 I! o2 z6 [8 X7 H% U8 RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% R' h7 { s, D7 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, T2 j1 h% ~% l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 e- { y& B& A, X/ ?2 V) Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 z4 e, I: t2 y- W7 C$ n! s0x00, 0xFF); /* configure the clock for transmitter */2 F+ L6 W. j5 K' D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 M* ?# m% c& f* P$ U% y6 z5 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : a7 _" E. H6 i0 { Z4 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. M7 g0 d& z& ^% t1 r
0x00, 0xFF);; d' Z% p5 y( c* Z
, Q+ n" t* ~+ k6 A/* Enable synchronization of RX and TX sections */
7 x/ ^) b6 [1 O" WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 {; M w( F* t" Q1 @4 A5 @$ f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); S/ ?' c" |0 N. p8 d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 N+ P* I* s2 j/ g( |** Set the serializers, Currently only one serializer is set as
, e, i5 X3 r, V0 ?5 J; J** transmitter and one serializer as receiver.
: e% y8 [* P) d+ C$ u) L; G*/7 c% V2 N6 R' p$ R, H. Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ A: n* b! z' J( JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# y3 Y( p3 ^) m1 ]# ?, @** Configure the McASP pins
; Q0 q# D) C" n1 D. ]- G4 I& c** Input - Frame Sync, Clock and Serializer Rx
7 f# S& a/ X. ^/ t) Y q** Output - Serializer Tx is connected to the input of the codec
' Y/ P- g% k, P0 x*/
2 V% I% J( D" T/ Y* p" D* GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 t" X% P' C% |) j1 d2 y4 c ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: K, x% K9 c" A; H( T9 @0 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* s# r4 y l1 E8 j8 P% E6 ?
| MCASP_PIN_ACLKX# o! C' d9 R0 A4 y' V* b& n% k; e6 d
| MCASP_PIN_AHCLKX
' W1 W. G4 x0 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 o% d. K! X0 F3 V# [* S: xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 \2 \& _% F' u1 `3 I" l6 Z
| MCASP_TX_CLKFAIL , |% o" [- n$ `2 N# W' \6 F- q
| MCASP_TX_SYNCERROR
& T) Q: C W3 N i+ z# N F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 `( z1 g1 u6 t4 o0 W| MCASP_RX_CLKFAIL
S0 u5 ]7 Z, d8 h; I5 T f| MCASP_RX_SYNCERROR ! B9 ?6 @# k" }
| MCASP_RX_OVERRUN);: B" K4 g' {1 c# Q9 z$ S1 s
} static void I2SDataTxRxActivate(void)
9 u/ P' _3 D. U7 ~{- {9 s z, ~/ N' }4 a- D
/* Start the clocks */
" p# y$ c0 i( X1 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- x3 q# u) B8 j" V. tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 u" m3 i# A+ a1 B" y4 P1 `; \* p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" m, z9 ~8 P8 ~; A( \8 w, s3 t- vEDMA3_TRIG_MODE_EVENT);
9 }5 `, m/ k5 c z; n: V9 R! iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 [# t) H* B# v" m/ FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% }+ L- |+ U- k4 e6 j. f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ^+ u* x$ X( X1 i8 K ]2 P8 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' ~. s' ^; P& \. }( e) X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 x! g6 v( K& E5 H" H" H3 A8 ]7 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
?4 s, n1 H' U3 a) U( wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) U6 p& m( l# Y; b. c* y
} , o3 c: g9 y% R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : C% X& Q5 {# M% K, L: O4 l, n
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