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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& m! ?$ R, o9 t8 V' J Z, v* S8 c
input mcasp_ahclkx,) j2 p$ Q& v8 }, Z( r
input mcasp_aclkx,3 K/ ]9 \1 _" m/ P; ?! `
input axr0,
, B+ l8 V1 V2 c# g
9 {% J$ v8 K r. b; J- Voutput mcasp_afsr,2 j; n7 s- ^+ w0 p* {
output mcasp_ahclkr,+ i; T4 m. L S
output mcasp_aclkr,5 h1 h+ A4 ^0 g8 | C8 j' h) z
output axr1,
+ B; r' g5 [9 V6 ~# ^9 g: X: Q assign mcasp_afsr = mcasp_afsx;9 X& f6 ]8 s3 e4 U( S
assign mcasp_aclkr = mcasp_aclkx;) W. y. C8 S- W8 s
assign mcasp_ahclkr = mcasp_ahclkx; ]( Z4 p7 _" F& b- T, x( y/ h4 W
assign axr1 = axr0; : G8 U5 J. k1 w; h! T v7 v( p! l
i7 @; L$ s" y. r; m" v4 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 C" _( U8 k' k5 `: t t+ k* m) Ystatic void McASPI2SConfigure(void)
( Q6 K' O0 L( T. G& e{
/ m2 n5 H4 f0 @4 y3 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# V0 y0 q8 i1 }& g8 Y8 y! Y5 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# B; x0 X1 Y) g, f) BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 e* B& w& N Y. q$ ?+ C9 b/ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 {. e2 y+ M5 p+ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 I; a# j8 [0 G X
MCASP_RX_MODE_DMA);
: k& W' v* k# @/ YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 r0 M# u3 F/ R3 I! M2 @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# Y& g1 R4 l" B" B3 E0 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- Q) @# p T6 [- }7 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' e2 z' D3 C* Y- ~4 A F6 b7 v5 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 C" x: X: ?* `% U3 ]+ L$ s) B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) { S0 ^: `& s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 [4 y# X2 Y% C) M; w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " D E: s# f& U$ N" ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 j2 v1 v6 F1 z
0x00, 0xFF); /* configure the clock for transmitter */% `% }8 E: u# X4 U' x* l, }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 r% z) [, J. C2 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 b; [# E7 t2 p" I' z8 {% Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 s* C/ _% }+ X# r0x00, 0xFF);1 _, u! u, |0 q/ `4 \
6 s. X0 N/ I' `8 @ ]- q, w/* Enable synchronization of RX and TX sections */ . _& c* m X/ G e/ ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# @- u+ j6 M, u, JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); Z( R$ V' s. Q" [* R" p) K. N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ K9 ^1 @) w$ G** Set the serializers, Currently only one serializer is set as: G4 g3 e/ f8 |6 I& m8 W
** transmitter and one serializer as receiver.
: F o; u8 O% ~4 `5 W# [8 S*/1 `* {& C# t3 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 w/ T" S7 Q/ s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% v- }' S" p. Z
** Configure the McASP pins
; k2 u3 G+ s* L2 a( w** Input - Frame Sync, Clock and Serializer Rx
; u# r: d6 A0 M. }/ d** Output - Serializer Tx is connected to the input of the codec - Y+ S! T* Z' s9 ^2 C- L
*/
' ^) s, S1 J. l7 c8 Z! N3 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 K: I; y8 ?5 b, pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 _) S0 c( K+ }, P! h8 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, K9 b; s% R/ L+ R| MCASP_PIN_ACLKX) c& j% A' h6 D3 ]3 _( [
| MCASP_PIN_AHCLKX* r! ` R3 u& R0 S" F6 |6 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" `0 {: u, t: q4 R$ Z1 jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
c6 y* ?9 n! _* c9 W% L+ {| MCASP_TX_CLKFAIL
/ j$ Y( i6 s8 Q* {1 \| MCASP_TX_SYNCERROR
9 W9 {7 d3 e5 N3 Y* G# `% \& A5 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 t# ~4 f5 `2 b, u& n" L| MCASP_RX_CLKFAIL
$ u" U1 M( `/ P| MCASP_RX_SYNCERROR
3 {7 D) q+ p$ z" Y D| MCASP_RX_OVERRUN);
, ^5 `# m' d- M% b% n' s} static void I2SDataTxRxActivate(void)& g) N- Z! S0 n, v: K
{
! e0 M$ R+ u& ]1 ?2 d8 p/* Start the clocks */
1 D* y3 N- x! d. n8 G* M' y+ pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ B. A D- k" D5 C$ C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 v, I+ W. |8 G9 s# ~5 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 }9 a2 E3 |5 Y/ T
EDMA3_TRIG_MODE_EVENT);) k+ _- y2 r0 b6 Q0 q3 V; @4 }. H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% d0 Q4 Y4 i- b& H5 a; q$ VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& T1 N, a5 P9 L& J+ \) Q u4 H# SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- e. [8 e8 _4 G7 f: F+ L: s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 [& x0 p4 P- A! j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! R# d G! g) a$ g( a! `" G% }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; [+ X8 H' K4 r2 {% M7 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 z+ [4 M! _3 B+ O, Q# V
}
- b2 d! }! N+ F$ \( k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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