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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; v% C: B( P. P2 R) ^& z
input mcasp_ahclkx,/ @7 I" V5 \2 { e3 q* u
input mcasp_aclkx,
; z" q2 X* _" P% G5 Jinput axr0,3 ?( o3 d7 ?0 U: e
/ I* P$ j4 b6 u: n
output mcasp_afsr,
5 V- ~! V! u0 [) h" R! b. coutput mcasp_ahclkr,3 r! q* F' B6 o
output mcasp_aclkr,( U. M, s# j" h
output axr1,
$ m4 W1 j2 @2 \" p, } assign mcasp_afsr = mcasp_afsx;
D' [) l3 \3 @2 ~$ Gassign mcasp_aclkr = mcasp_aclkx;
" D+ l) A. l6 `" f( V8 r; Eassign mcasp_ahclkr = mcasp_ahclkx;
. P" j c, E& x& `& ]. k: \assign axr1 = axr0;
H+ O) S0 k( t! y5 V1 z4 p+ f0 q) l3 K& i5 p/ i; j8 T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 s& L( X S5 ]) p1 V* a
static void McASPI2SConfigure(void)+ r {4 M5 H! C8 c' M' P$ T
{; \* ^* K, R7 \ B$ r/ e- M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. [, w! _: i. u: {5 T K3 K2 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 n7 h) K5 s; ?- C6 I e' }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, A5 x4 R1 u6 L, k7 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 S5 ^8 W$ ]7 O: mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( _$ o2 o" |; C! ^- eMCASP_RX_MODE_DMA);
$ X, y* j6 o& o$ ?$ q) uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 o7 |3 N O5 R3 R8 `3 yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, Z5 A% T( `5 r* e7 @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " g7 C1 A8 d* _4 }& J" R$ l# v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 m& Q9 B; I+ @. o4 k- q3 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 K4 \$ b+ |; C0 f+ Y+ mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% D; M. T5 x; W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( a9 U6 p2 Q! P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 q+ Y: `6 P5 q7 r) x9 z' i" M* r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," R2 A6 j9 Q2 C" @% @
0x00, 0xFF); /* configure the clock for transmitter */
2 f6 L2 q# {! P! \$ hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! \; H" O2 [( {; `' ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % ]1 z) F$ `8 u# r% h( p& P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% s; n$ o: v1 R5 M0x00, 0xFF);
# c; s) a: W+ e4 d; N
0 Q2 T3 m- y2 f# U* m/* Enable synchronization of RX and TX sections */
1 h& Z5 l* S- p8 V! gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% ]5 b+ C5 [+ M- `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" [4 o% \+ B0 D2 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ v. y a" S3 d, ]/ _** Set the serializers, Currently only one serializer is set as
# }3 B5 Z- ^ t% k8 k8 H** transmitter and one serializer as receiver.: \/ [( _/ N5 a! C1 W
*/
; T; x' L6 ^: e6 h/ Q1 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( o# H9 t" L8 g) G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, K' t- d+ K$ W, M+ l. U9 G** Configure the McASP pins
0 [3 _/ z5 x1 P8 E- R** Input - Frame Sync, Clock and Serializer Rx* y3 }$ f+ z8 K
** Output - Serializer Tx is connected to the input of the codec
6 A" T9 g! c( O& |' a- b*/
% j9 k9 m' e5 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" O# i% ?! ~5 h4 d; N2 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 Z# M* X6 n5 z7 s7 W& h- zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 T) n6 x/ u, s| MCASP_PIN_ACLKX
( W! j$ s8 j8 w" z, w8 v| MCASP_PIN_AHCLKX* U8 A1 T; o+ f4 z2 Y0 D5 C5 h" l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 W; R1 {+ [, o( z, T3 {5 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : v; k6 _0 z A, t+ Z+ g
| MCASP_TX_CLKFAIL 1 C3 m: z8 y4 f& ^) }# p% u6 A3 C# D
| MCASP_TX_SYNCERROR& Y& v. b8 o+ {7 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) w1 ^# z, W( m% [' L
| MCASP_RX_CLKFAIL: ~3 |) d9 t- G# N7 R0 n
| MCASP_RX_SYNCERROR 6 L( M) L7 j- ]
| MCASP_RX_OVERRUN);
- L* |. R* @- j' x% D" s} static void I2SDataTxRxActivate(void)( U" ?$ l) f/ ~' |1 I& B/ i8 x
{
+ g3 }9 i& t& }. Z5 @( C. S" T) p D/* Start the clocks */
\; e3 r. V8 I/ u/ Z) OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- u) U3 E9 w) l7 ~# A# J, kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; ]; C& ]1 g9 P( CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," s" u1 F! d. E) }
EDMA3_TRIG_MODE_EVENT);
1 {7 R/ K! `1 m3 q# kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , l' O" M! h, `8 E7 F# k4 T7 h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& F- }1 C/ p! v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 m+ N6 F' U0 X8 C+ K3 ~* ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ y# ^! g) A4 \! I; M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 m$ v1 ^& @% W/ K# O% t3 S& {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ p5 D% M* Q6 ]8 V/ c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: c6 ^2 q* T9 [) Z' N} 8 v1 F' [. j/ ^, k f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 _' s$ X1 u4 }( _2 p. X9 R( @
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