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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ?+ {& |3 I0 Q$ linput mcasp_ahclkx,
6 q8 q; m3 c# cinput mcasp_aclkx,: \; z. ~- k& p" ]' q ^
input axr0,
* ]* r) k/ Y/ q3 g2 g' a/ D3 d
; P* E4 n/ o8 X* e2 U& M* goutput mcasp_afsr,
* [/ }4 g( J1 ^output mcasp_ahclkr,
9 @$ p+ W1 E* zoutput mcasp_aclkr,
5 e) Z! U. f* W O s' J Qoutput axr1,
: W1 |4 r9 I: P assign mcasp_afsr = mcasp_afsx;
2 z' A: S9 w. k8 Q6 aassign mcasp_aclkr = mcasp_aclkx;
) s- F6 o# L. P3 P m! g* gassign mcasp_ahclkr = mcasp_ahclkx;6 F2 a7 n* J1 \8 Y; X2 M" B
assign axr1 = axr0; 7 _# m+ L8 F4 g
$ _# w9 s. E. n6 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , z, X- U6 O- V
static void McASPI2SConfigure(void)
5 R+ I' v) w0 B" Z- D4 J{
n, s: G$ i3 C# x9 U3 VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- a1 M" h. j8 }8 B" O8 V- U8 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 p: R: u' A" j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ?6 J- I7 G; z! d' j. j* A, L" vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& T8 \" @3 `( X' E# t& L5 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 j5 D! @& W' a7 s ]' _MCASP_RX_MODE_DMA);
' v7 ~ O9 c! h) W# BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' n8 P+ l0 z6 T) o2 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. \/ q1 A# a. l# S) s& Z- wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: y7 y% e! b2 }9 V t* E% ]+ x% x! ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. z& E. J; ]8 F7 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & q( f3 @) X( X6 S! v* q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 n- F/ n5 S5 a2 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: g2 B$ x$ f6 s# m; b4 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % g6 F2 e) I9 `! I& h, h! w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 c, X6 Y7 }9 U/ F$ \5 r8 o, ]
0x00, 0xFF); /* configure the clock for transmitter */
7 L# s3 @1 i0 R4 p+ [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 Y% C h: v G, g% z: _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& E7 F& f; V) L# h4 r% aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," h4 {; C2 u4 u# l6 |& c( m( f
0x00, 0xFF);$ Y7 F7 w" b, z+ S3 d
5 Z1 `4 m% t0 J8 _- Z# G3 Z1 I" w/* Enable synchronization of RX and TX sections */
: ^$ Q7 n, r+ aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. F# ~5 n( ?8 V0 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; n3 t# Q% f9 v5 o$ e, rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& K4 Q! L4 \* m1 `" T** Set the serializers, Currently only one serializer is set as
6 ?; ?' B3 ~ l5 q3 D. P0 q** transmitter and one serializer as receiver.
- ~' x! _. c" M- U*/, ]% X: f6 `+ B4 a% d1 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, e; N9 `5 S0 U9 T' P" ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' a2 I, \# {- N! S** Configure the McASP pins Y* L3 Y2 i2 o I. \
** Input - Frame Sync, Clock and Serializer Rx
) f# u. U, K* Y n% Q2 g** Output - Serializer Tx is connected to the input of the codec
. X7 E% z/ n0 c' `5 ~# Y5 u*/3 ?9 \' v7 Z+ I2 n9 S8 j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- u2 W. Q, D; m! t- q( ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( D( x3 B4 T- d( s7 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; ^8 j' a# J4 T1 w
| MCASP_PIN_ACLKX& m! e% O8 ~8 Q" u; [
| MCASP_PIN_AHCLKX) {+ G' V# r5 r, E5 P: L6 T: e a. Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; K8 [. S9 y5 P5 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 @' R5 M. i! N; H- T9 j5 I1 |
| MCASP_TX_CLKFAIL & n1 R3 w5 ? e8 s# s
| MCASP_TX_SYNCERROR7 J# o0 K* m' }" A: a$ L5 v+ }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 ^5 O0 T1 V* A. |0 Z; u| MCASP_RX_CLKFAIL
3 d& `1 v. }) }6 n2 U& G0 s' r$ H| MCASP_RX_SYNCERROR
2 Z/ Q' P, x" m| MCASP_RX_OVERRUN);
- v2 Y0 E$ O6 N0 j6 V, N) `( k} static void I2SDataTxRxActivate(void): c) c! H9 D$ B4 P7 k
{ U6 y/ Y7 n3 [& F7 [5 `; C- T
/* Start the clocks */
3 {; Y' N: v0 c- ]; A1 B3 {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! f" C0 A- G) X/ W8 y. t/ F; ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 s: \( N" f6 g p6 O! X( L' u7 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 l2 ^% o( Q5 i |; c V6 n5 v
EDMA3_TRIG_MODE_EVENT);
- D7 `9 y. E$ uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # p0 w9 f& ~2 R: X; M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: V( n4 M4 @/ s8 R$ b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% H; c3 x' }: x# n: B2 u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 P) F6 g5 ]. o$ x1 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 S% {1 q$ l' m# L0 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 }* }' |/ J7 l I& o% |6 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 M1 ^% V# N- i' B9 S% |) G0 @
}
1 o1 t) }+ l2 G7 e# P7 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - M8 Y$ e/ R d1 L: X$ g. K: S3 F" E& r
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