MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
+ ?; L1 k' K& T+ }5 L/ W% vinput mcasp_ahclkx,
5 O2 N- ]0 i# _+ v  Vinput mcasp_aclkx,
  x. l+ W* P9 r7 finput axr0,
( u, a  S' ]2 w
  n  G  ~' @& O" N2 I* M# Routput mcasp_afsr,
$ a7 X3 g7 E9 K& _, s, moutput mcasp_ahclkr,
: W  X/ r  Y: i& S1 {4 \output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
& q. G: M( D: Zassign mcasp_ahclkr = mcasp_ahclkx;
) q5 f3 Z3 I) }5 |assign axr1 = axr0;

& c+ j0 F& A  j3 g
9 N8 B) Y" g. K: c; ]# D" k

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
+ V1 V$ _) ?: x3 b9 |' `* `5 J' m{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( W8 E/ o  y& \/ SMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
% F8 a# w2 q! h& o* A8 \) M, fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Z2 D, P$ B( r6 Q; V* K" p( w$ DMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 \) i5 \7 L  X$ x7 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 K$ i) q  d4 L7 [( m8 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" ~1 r# M2 Z0 L3 f+ }+ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# {/ [- v" j: {4 ]  u5 u0x00, 0xFF);

/* configure the clock for transmitter */
) N1 {& b; a4 _& D' m$ `/ MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) S7 F5 F: T4 l0 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* m' u4 Z, b9 v* a" J  {4 c; t0x00, 0xFF);
* E& z: \4 R* E! H( Q
! S6 [. g' B5 W) @( \* p' G/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
! N; k* m; r% d6 ], fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
* C5 o9 d5 e5 K- v) r' c; M** Set the serializers, Currently only one serializer is set as
3 w. X8 W( D. }! i5 }6 z! W** transmitter and one serializer as receiver.
*/
1 X1 I, x+ @9 ?- i& ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" _; @) Q2 w( M# l8 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
  @7 \: w% ^; }0 j3 c8 _5 G, F** Configure the McASP pins
# o- h6 J. r3 u** Input - Frame Sync, Clock and Serializer Rx
' d4 \9 k# i! D+ {** Output - Serializer Tx is connected to the input of the codec
$ R  F& L: R0 M& k9 y/ H*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 k( P  X- B* b3 a* JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 g) x* A# l  Q; M( k) XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% W& v0 }3 y: }! `| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
. l( R& C& H3 ~" H- ?| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 G! E& E* z; c: t7 h5 H) k) a8 z| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
& y8 X$ H2 y% C' J* M/ |2 U| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
. z& ~9 p$ b8 ]) Z7 r}

static void I2SDataTxRxActivate(void)
6 A# l/ }8 _1 n0 R* a" g9 k{
: I/ B2 \! \( g3 y! h/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 X. k# Q& H! L- R6 \9 ?7 dEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
6 Q' `2 C) F: FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- u* Z) ?  w6 U$ i  [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
( D* l& Q+ u& v- Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 v6 L$ |" H  _* X: E: J# {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

/ P4 Z3 y! z7 @3 ?

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.