MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
: S. k/ R" Z; I$ h2 Ninput mcasp_aclkx,
input axr0,
. o) ?, H+ h) A2 I
output mcasp_afsr,
output mcasp_ahclkr,
# Y* o) h5 r& f+ p; ^; e3 Poutput mcasp_aclkr,
output axr1,
& M, F5 a. k# ?

assign mcasp_afsr = mcasp_afsx;
0 S8 ^4 L# V* @! Z  T" g  I5 M7 Qassign mcasp_aclkr = mcasp_aclkx;
) `; X/ }2 H6 @  q8 |* Jassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

- l( |/ l2 |, U, a

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" i; G3 M5 u( i; K- V5 K# E8 A. R* AMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
8 A1 l8 W: ~4 I/ \* KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- y' M& v& O: g# \; vMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* z. {3 k; v. O* v9 ~0 b  t' lMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 H) n9 g3 K. q; w+ q0 w. M+ HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ `7 l% `$ X1 l/ Q  t+ |* Z/ UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! \. [8 c+ N0 o/ s( o+ X" M; ?: rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& ]& W  B* ]6 ~$ ?! c, q" e7 TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ c9 o- r% t0 j) x/ a# T) n. c2 d$ f+ G0 t0x00, 0xFF);

/* configure the clock for transmitter */
; @' T' J$ |* R( o6 E* Q, g! cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 Y! h3 H  i! lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
  l; V2 q. A: |1 |( T; s; [0x00, 0xFF);
' U. g; r% j0 \( S& P
1 _" l9 c% n9 @" r1 K& j/* Enable synchronization of RX and TX sections */
) s. \* e# I/ R8 b% f! @' tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
! l& n' c! g- q. [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
0 Y% D/ J  b, F( d( r, e2 C& P** transmitter and one serializer as receiver.
$ X6 F% f6 p! ~+ o) D9 v" z1 ^*/
/ M' n' a0 m5 x3 s7 u3 `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
+ y* X$ L* `! A! `7 S** Configure the McASP pins
0 {0 n6 k$ F$ [8 U9 t7 g* ~+ h** Input - Frame Sync, Clock and Serializer Rx
" L/ k+ h4 X/ n2 @$ V** Output - Serializer Tx is connected to the input of the codec
1 h' R# K8 t' c*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; k: }+ w1 R1 w- N1 H$ eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) i+ [6 c( R2 j0 x# I- c% nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
$ p- q% l- k" i; N7 Q| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
. P$ |: n. {+ K% b' k: P| MCASP_RX_SYNCERROR
$ F' e, ^6 ?: D+ m| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
) T! r  k& ^# [6 s- L/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 U% q' m* {  Z' j+ ^- tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) {* M0 m/ o( A6 }3 LEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 `8 Q% _( E( s( g, A/ V8 U. H2 Z1 m, G: QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 V: a3 K6 w0 u. \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
: y' u& `' V; N8 ^7 ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
  P/ p/ O( t0 z4 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.