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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 b- @; V: W0 }input mcasp_ahclkx,
2 c, h { G; N r0 {" O3 j2 [input mcasp_aclkx,
5 v6 T9 r, d1 x2 n* c" Pinput axr0,4 @, \/ _% u1 h, M1 U; Y+ [
# {5 ?% V/ W6 \& b1 R, z& s6 Koutput mcasp_afsr,
: U% m b, g& goutput mcasp_ahclkr,6 y4 s, o- O6 g" s- Y1 z
output mcasp_aclkr,1 w) J: `( T1 @/ C2 X& ^
output axr1,) D+ Z' R3 y* L. {+ m
assign mcasp_afsr = mcasp_afsx;
# v8 k! d5 ?3 L/ ?assign mcasp_aclkr = mcasp_aclkx;' e7 [# P% [5 G8 `& M9 s9 p/ u
assign mcasp_ahclkr = mcasp_ahclkx;
% {" c3 S# W. @4 c8 B/ xassign axr1 = axr0; 6 ]3 R& n v# T' M4 h+ p5 q! b' x
! R0 a2 Y; `$ b/ ]! W! U9 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; i; F/ Z' ^& `3 n) M' z3 c
static void McASPI2SConfigure(void)
( Y" E! b* k( u0 \{# M8 P, _) l% M8 e5 g% \* o$ G$ `7 ~$ L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ k: [- c! p" l1 M3 c# [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 A( f" H* }9 j0 f7 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 Y& `" g) A8 Z& m4 H6 r9 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. ^7 d+ t: `% @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- |+ j( u- ? z* X0 H
MCASP_RX_MODE_DMA);
1 a' }" J* j+ i: `7 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 K+ V6 v5 i. W- a i. }9 A/ k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// V* m0 R; B! S+ F- E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 M4 d6 s5 @5 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# `% [) H$ Y7 ~7 f4 S& c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 P- x( ]; P! O! u: IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 Y3 T; a4 c( e! i Q9 e. |- {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 y! m* ?2 \7 M7 B7 ?9 C0 g4 F fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ K6 V: G" R# ?( i8 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 |/ f3 m1 o# {7 b
0x00, 0xFF); /* configure the clock for transmitter */2 e+ L* }2 A" u3 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( @) q$ n$ B+ P' Q: F( f' \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 K, E& U: h4 c( u/ U; A9 V: u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: Y1 G+ S# ]3 ?' N0x00, 0xFF);/ m3 Z X4 T' N6 Q% w# J( h
- q; H' v. p; p7 Y8 T8 I% N+ J/* Enable synchronization of RX and TX sections */
/ z3 Q( n3 l* i( S1 ?1 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, C. k1 R% K& }1 k- H' w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, n5 H" M+ T! v# S. R1 k- p- G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 W( K* f7 c$ g' |1 K** Set the serializers, Currently only one serializer is set as' ~; y6 c/ D5 o4 _; a
** transmitter and one serializer as receiver.
6 ?2 o% Q; m$ |' j" m0 v*/
. \- [; C `6 P1 s& |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. P; U7 ?1 k1 i1 ~$ ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: X; S& Q8 l) n# |
** Configure the McASP pins " J7 _. K3 Z( P( T$ a
** Input - Frame Sync, Clock and Serializer Rx3 a( {8 d- y# F/ P
** Output - Serializer Tx is connected to the input of the codec # y/ Y& y0 {9 Z& U0 R$ \& O2 T
*/; z. H% x( ^1 Q) b# j" Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" C) S1 |- I5 l# y- p6 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 R/ E- ~ k& h Q+ D5 [5 L! V {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ s8 I0 R# s5 t' L) S, T| MCASP_PIN_ACLKX, a% E$ B: N) o% X% F
| MCASP_PIN_AHCLKX
1 ?& B4 t5 A6 N' {' D8 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, M$ N( D5 I" sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 k, T( B( b3 a' O, V; [ W| MCASP_TX_CLKFAIL & t$ A5 p, G% G0 v* x+ s/ ]
| MCASP_TX_SYNCERROR+ I- ?, G/ l* U5 Q0 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . \% d l5 C# m( F2 d! i& G
| MCASP_RX_CLKFAIL
* r% G3 I& Z, r _| MCASP_RX_SYNCERROR
7 b; q4 u6 t! Q# C$ y| MCASP_RX_OVERRUN);
- c, Q& j1 q, T: k- T} static void I2SDataTxRxActivate(void)$ Q; Y$ ~5 Z' |
{3 V* c& Z: v; ]# {# j+ c
/* Start the clocks */
/ k( Z, A5 a% j m# ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: S; i6 R' L( M P8 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ [* u* }1 b. E; JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, F A: R4 j9 e! z# P) U0 TEDMA3_TRIG_MODE_EVENT);
: X, d# d! T, e& v3 D( v% A0 P- bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 D9 i/ Z, F6 r1 r2 o* R6 ?; mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- P' B$ S$ b1 o. t, v1 }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" S) B, C& S4 |( F! ~1 ^4 y! RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 @/ x* H: k* w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ R* K0 L/ `4 w5 Y4 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 d3 m; c1 i! o& s! a- G( I8 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) k7 x8 }- P3 a/ C; F4 B# C}
, m4 s* T& q7 Q5 [, H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) S$ \. ]! z2 B9 [3 x% Y" s
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