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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# b: k7 R# B' z8 Y) F$ l! @input mcasp_ahclkx,
+ C7 H* ~; Y" I4 _input mcasp_aclkx,
4 s; k+ Z; f6 z. ^0 [2 X4 jinput axr0,
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output mcasp_afsr,
! F9 K* ^2 r# V' aoutput mcasp_ahclkr,
N1 x& P! e3 p; |' S" }output mcasp_aclkr,
; a' V$ V! U! u2 l4 @1 S8 Zoutput axr1,. N5 Z* ]) A* g3 m: ~
assign mcasp_afsr = mcasp_afsx;6 \+ F4 |6 `8 ?- p3 E1 U! D
assign mcasp_aclkr = mcasp_aclkx;4 D4 I( v# k" ~, X
assign mcasp_ahclkr = mcasp_ahclkx;- b; C* k" v* @$ c" g) r
assign axr1 = axr0; * M5 w$ c3 { ?7 W( l# ?
0 v$ m( y2 v$ D3 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - k2 R) k7 v! _1 [
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 C' a1 U9 b& l& E2 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 B$ p1 R" D7 p6 ?, {5 I" y! h1 jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: r6 e# U7 `. d* _5 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 s3 B3 l* m, u% F% K" C+ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, S" N- [' z K- @" C
MCASP_RX_MODE_DMA);
6 q2 x5 y' U/ _7 Y mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 q$ q4 K5 d' k% F: P7 p. EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; i2 B, T! S) v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 u, ~; P$ g p8 B5 p/ E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 y" G! |1 I1 _' M+ b- n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) @ w8 C1 S5 H6 z4 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; h* I, V9 X& [9 E4 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% `# g" {1 `* ?2 ]% E' SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' h4 x+ V! P% w5 Y! c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. D5 ]- W1 W6 O0x00, 0xFF); /* configure the clock for transmitter */- D# b' O( L1 W4 T9 A- p* R( L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 t I0 i: O v! q" t* n: A; _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 Z. \: B( K' R" h! S5 Y3 A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 {4 G, E1 ]* [ a# x& P0 Z
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 7 {" |' [" \0 {- _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, R' u8 ]* v* i! h' I T& lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) ^( F* _% |- P1 E0 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% y+ r) O0 F9 G T1 b' ~/ w
** Set the serializers, Currently only one serializer is set as
) M' P. a7 E" S5 N- J** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ J' i4 i& `$ j& [6 x2 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! @& @, Y" y' o* D0 N
** Configure the McASP pins . h" ^9 V9 B: v
** Input - Frame Sync, Clock and Serializer Rx7 ]+ P; i2 S, R7 r
** Output - Serializer Tx is connected to the input of the codec , i: z* h; M2 h5 W5 n' F% I
*/6 R, x& o) D- y \( g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# p9 T. p E& ^% [: i& |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. T* Z& X6 ?, @! F; L( o: K8 @) jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
e1 ]$ K) P7 e X: G% d/ || MCASP_PIN_ACLKX- K0 M' D$ O9 K9 K% T( i. H- s
| MCASP_PIN_AHCLKX
& Y. z6 Y4 w' O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 g* v3 n8 I& [0 z: @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 M4 g( p, G0 `2 {8 R2 A| MCASP_TX_CLKFAIL * \& t! ~9 i+ A, [# w9 q7 b& d
| MCASP_TX_SYNCERROR
. w; z0 ^0 |* || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : ^; i! I' u8 L" M. [6 B5 A
| MCASP_RX_CLKFAIL; N* y) Z7 U# S* o+ ?% z2 l8 z
| MCASP_RX_SYNCERROR
. L7 G$ f/ `$ `) h. i4 F6 a$ Z% N| MCASP_RX_OVERRUN);9 }3 g% q6 ~' l; O( H9 W& s
} static void I2SDataTxRxActivate(void)
; j/ n* k3 c; c( U/ m# W& @8 e{
- O! A/ Y7 g, O! V, K9 K9 f/* Start the clocks */) F/ K8 T/ M* G! @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 o" i, n* w$ X' \* z$ Z" M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% X8 Y) A: q1 N m( ~! mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 B! ?# {8 U9 t1 ^0 ^' A
EDMA3_TRIG_MODE_EVENT);' f4 w5 h$ z) M2 T# ]0 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& @% g2 w) I$ \/ w7 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" t: s, \! Q; r; `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- j7 m6 n% S/ Q1 f9 I# _/ @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ D8 y& N# r5 Z$ [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ x9 o0 X s8 M. E# d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); F) M U+ B* O, l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* {5 Z: R2 T& j2 [- k% U} + Y* E5 P: y# ~: \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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