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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 J1 o, \( c f( p8 jinput mcasp_ahclkx,1 |/ K9 W: ?1 j6 B: h# r5 |
input mcasp_aclkx,
% X, ^ R/ l: W, B4 `6 ]input axr0,
3 E: @0 V1 S) F! @0 `
& W8 Q. W, c$ X) A5 q; Coutput mcasp_afsr," i7 u. J/ z) F8 a. j3 v' }6 v
output mcasp_ahclkr,
' f; O, L$ t0 @output mcasp_aclkr,% U9 t( J# n& E' i+ r- L3 y' f9 `
output axr1,
9 }2 y r5 g1 m" T assign mcasp_afsr = mcasp_afsx;# f$ @& f; c5 X4 o' ?( I0 S
assign mcasp_aclkr = mcasp_aclkx;
% M' y9 N0 a* }, h4 N- Eassign mcasp_ahclkr = mcasp_ahclkx;
q! h: w3 v G8 E- xassign axr1 = axr0;
' V1 q% f: Y8 L; I6 e, Q, A4 k9 m! V/ a( I M9 A6 J4 A; H. g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 i$ A! O! |7 g _ _
static void McASPI2SConfigure(void)0 l8 r0 l5 ^) R, P( J7 a* A, K0 Z" E
{
$ p& C+ d( N% ?; N @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& d0 I9 E f' P0 _& @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# N4 [; }7 L' S/ CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 N) u/ Y* X. d3 E: ~1 @/ ^' R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 Z: V2 g8 U d9 e2 O' ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: v5 J- U* C: b. ~0 g( ^0 M. v
MCASP_RX_MODE_DMA);
7 U" Q$ z# X% P; D. i" _0 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ~# Y; _1 Y4 i" e) C3 ^0 m! YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 L N% R% \% r" s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ t6 D7 F# Z* e6 C( m. D2 n/ `2 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 j7 X0 q* a; x& u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 }6 A3 D' X3 O: Z t" y4 c- JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 C" p# K7 _0 x4 p6 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 K- G b2 F; g3 V+ g& D/ y! m3 y/ I, @5 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # B) W8 W3 y; ^/ V8 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ d+ h$ S- {4 `+ R T) S: w0x00, 0xFF); /* configure the clock for transmitter */
" e1 r- r3 t, I0 i D: cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# ?9 N0 ] x5 L' u& k& [2 L2 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; o6 L O M9 l( n* K# }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ W1 t% i3 `5 Y6 l3 _) X5 z
0x00, 0xFF);
2 Z9 d: D7 r5 ` N
( J1 l( K" ~$ c/* Enable synchronization of RX and TX sections */ , c2 W* Q# j* }" M' F& d* K h6 `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ s. z3 Z8 R6 h4 p/ n( L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) `' `$ ?2 F2 H7 f5 D; ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 s7 q7 l' ~0 D** Set the serializers, Currently only one serializer is set as
- G! H, T, e1 _ s) T0 h: Z3 ]** transmitter and one serializer as receiver.
& Z3 f' j) t# ?+ x& y: o3 M$ S9 [*// O9 g) n) f G1 C' x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! P6 p+ ^) X' n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 ~. w* b% ?1 s( {3 V
** Configure the McASP pins
( M& i0 \8 D- _7 \: C/ m% }** Input - Frame Sync, Clock and Serializer Rx6 Q' Z$ o" o# r$ j* I
** Output - Serializer Tx is connected to the input of the codec
* ~! ]% L; r" X*/% X% G: n. T& t" s, o5 j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 {" \5 F: y% \7 B: s/ `% \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
T# K! m# L8 g7 |- {/ e# LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" u# {# B/ w; l6 H4 H; v
| MCASP_PIN_ACLKX8 ?" u. k7 Y; T+ T$ J
| MCASP_PIN_AHCLKX/ A; X6 ~5 h$ _: G; k% Y% o4 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: R4 k, y1 l0 h7 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' ?: J3 S2 G% ^1 y b* ^ O3 D' Z| MCASP_TX_CLKFAIL
/ f$ X3 P' J( C0 || MCASP_TX_SYNCERROR
+ z ]. e. R7 ~ d& d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; n' g& j' {) l) O6 ]
| MCASP_RX_CLKFAIL2 ]4 P3 @+ g# Z
| MCASP_RX_SYNCERROR , V# G- H# K, ?$ C
| MCASP_RX_OVERRUN);7 L; g" d9 Y1 B/ l T3 r
} static void I2SDataTxRxActivate(void)
3 f' M: B/ e2 s. g% M- k4 X{9 j( t: E2 p: R0 W
/* Start the clocks */
/ @, z4 r8 B7 X6 ]9 B& F! F% X2 X# _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. V2 V& w6 G0 ~% l4 x+ cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 E' a5 O" O6 N7 \2 R+ J/ o. _0 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' i* M% C, M4 q5 s# K
EDMA3_TRIG_MODE_EVENT);1 N, W, I: d6 ~6 r# N% h4 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 T) s* V1 }" S4 |6 ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 @) i6 K# V9 |: P, A. WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 H# V$ K- m8 @6 p U0 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 o( F6 g0 F% G9 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 j) ?- J) V, J0 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, d3 q, e9 F6 W' Z! _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ C- F. [+ U' W} g2 l$ k2 ?0 U* z$ K1 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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