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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 A+ a* V; |6 ]9 K# u* {6 [4 f
input mcasp_ahclkx,% Q3 L5 r8 X2 ^+ O# b4 I6 M
input mcasp_aclkx,
$ A* v& w4 y, vinput axr0,2 T8 n4 ~* ^$ B) } z
( \; K" e& b- |7 e; k) m, e& poutput mcasp_afsr,% S! l. J2 B. o
output mcasp_ahclkr,1 P6 N+ D. K8 C+ R* q) M
output mcasp_aclkr,
/ ]; A4 H" I" S$ _' C+ |output axr1,# q1 m5 p. |1 L! ~; S2 j
assign mcasp_afsr = mcasp_afsx;
& R. @# W7 M/ g/ w5 K* `: Dassign mcasp_aclkr = mcasp_aclkx;
3 c4 C' O3 V% I7 `5 ?3 G/ cassign mcasp_ahclkr = mcasp_ahclkx;! T8 ? ?3 A ^6 K+ @% C! L+ C) D' [
assign axr1 = axr0; 3 k3 m3 E- C# |! M! j8 c
0 _9 U& o5 C; b* S( A7 v. q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # e1 D8 j* s5 N! o( ?0 @; z
static void McASPI2SConfigure(void)
0 u7 d) U. I8 \2 {{
9 [7 q! I" a6 J7 F8 v* jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 P+ T' o# x$ ^4 \+ [" _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 A- E2 \+ Q1 j y+ sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 s7 w( M' i; _" {/ CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* S* n$ _, p7 `- W* p# K- v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- z, m3 V6 Y6 U
MCASP_RX_MODE_DMA);
: t8 {% R/ ~( N; y( [8 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( @2 s$ M t, V" f3 Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 w: {1 }2 {4 E" f: e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + b7 P& ~( b. O1 F: S, d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 B) k' b+ Z' x- Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 E+ A4 `6 N, y" d/ \% zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. b. D+ c6 g" x, F6 H* t. a2 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ W1 p/ ~3 s: p5 K7 z1 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; `: H# E% D7 `7 `) AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 p# o" E3 _4 x; t. a4 i: r" n) X
0x00, 0xFF); /* configure the clock for transmitter */
! l0 n/ A# T3 O% J& n, D2 m0 TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 c$ n1 J, h& c+ ? aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" q$ X/ Y: e; ~$ I7 d! ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- |) W$ o+ s- D+ P; `0x00, 0xFF);
2 t2 S5 Z( `, u$ M& s* R9 N. e- z# b. N8 k; A+ G8 P+ V- ^5 z9 V
/* Enable synchronization of RX and TX sections */ + T3 D: d! u! i/ A, r2 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( [; D/ R$ R2 t8 ]- [( A' Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 U r- x& e8 ?/ z jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: q6 p6 f$ O p+ {+ `9 O( Z** Set the serializers, Currently only one serializer is set as; k: l4 m6 G- n L
** transmitter and one serializer as receiver.! C0 \8 v* u& r% y, B$ n9 B+ U9 l' I
*/$ O+ S, F2 F$ z. i: H3 e4 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 m' u- o5 }$ o# X$ P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; J; |: `5 a& P" R5 l6 P: P** Configure the McASP pins
/ m; u2 c5 j3 T4 j" V** Input - Frame Sync, Clock and Serializer Rx
7 j# x# ?( |# B6 k7 f6 ]: s** Output - Serializer Tx is connected to the input of the codec 5 b- q9 c; l5 E% r- k# m: z
*/$ P0 H. y4 e, |+ n7 P0 D& p# M0 v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- ^9 a0 w: {; H. qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' W! o7 {. ^& Q. d$ U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 M d+ D4 t3 [2 q$ o
| MCASP_PIN_ACLKX2 v3 T" }5 N( A. V6 r. j
| MCASP_PIN_AHCLKX
# j* Q+ b" G# e6 U: {, a4 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 g3 Q3 _1 m2 M+ @/ ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 e8 y V8 V3 z9 r" P| MCASP_TX_CLKFAIL - y4 l, L; ]- H
| MCASP_TX_SYNCERROR' B$ z5 U" S# Y5 p) @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % h) a1 R) ^1 d* J- T
| MCASP_RX_CLKFAIL* `# r$ B. M1 ?5 \
| MCASP_RX_SYNCERROR
$ S+ X) h3 m- j+ B8 }| MCASP_RX_OVERRUN);8 N) P7 e3 g7 [
} static void I2SDataTxRxActivate(void)
# ]* u: x! O' C. J' h x{
+ ?- y3 _3 h [& Q% S# z0 f I/* Start the clocks */
0 ?8 p4 c8 u5 \3 B$ nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; p3 [& H( f& J$ o: b4 u* ^" u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 C) G% Y& o8 Z, L, ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: i% B& `+ v9 ?) [EDMA3_TRIG_MODE_EVENT);
+ {+ Y" e. F1 W" P$ A4 j" MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; k& C4 l( _" E; m1 s+ PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 Z6 L" u1 }, O5 J, ~% n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) X* l$ H( y1 V6 I3 w f; iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 c/ Y I; i+ a) ~* N |# s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 U2 J6 }: w3 R' Q; M) l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# p/ X1 G% {0 _- Y8 q4 k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); H! R T' k: T
}
8 _* i4 t. Y; Q- ^2 Y' F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , m N" f8 Q% |& M; d
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