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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ K ^! E' W% L* Q
input mcasp_ahclkx,% c4 G$ }* M& L; Z2 V/ M
input mcasp_aclkx,
- F# I6 ?( h& ]8 O* ]1 v7 s- m j! A0 Kinput axr0,
- J9 W; m/ K+ C
! G# b( Y# o) U, @- _& X; F- Moutput mcasp_afsr,
6 E6 C( {) t; @( X( X# Ooutput mcasp_ahclkr,
& j$ F# a* z5 f# youtput mcasp_aclkr,0 e; F6 c1 x; T) d
output axr1,
! b b3 j4 Y0 {4 ?+ `0 s; ^ assign mcasp_afsr = mcasp_afsx;
. M& i/ u: z# r+ G! [assign mcasp_aclkr = mcasp_aclkx;
& Y D, D9 `& t: M& v& P6 ^assign mcasp_ahclkr = mcasp_ahclkx;+ x$ i9 Z+ O1 z3 o0 L
assign axr1 = axr0; ) |" c X9 l; B* W
/ V# [9 z' _; q0 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 Q) i6 r1 Y. ]9 a% s
static void McASPI2SConfigure(void)- k* l3 G/ ]# k5 b
{$ n/ R4 e2 H* A+ o. d2 n& H }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# I- s! x4 [) [1 t' Z. |/ n h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 y1 y* n( b4 H" B) E* x# k: ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 u, Q- D, ], T# H( n2 FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) |. }$ d: N7 F# J( t( X; G, u v$ m p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# A& `) {, D7 @, p. }3 r* j( W
MCASP_RX_MODE_DMA);
" R& W t7 m( V9 ]8 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ Q1 V( ]4 V& i$ ]. ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ V( P& O% c+ D& u' ]9 `9 |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ G: r$ J3 r$ B, q# ]" H5 m0 _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 |: r) u( X8 w7 _8 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 L* T, ]6 Z1 |. }9 q wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( {. S% J3 Y8 z2 L5 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
U' ?& m' |, p) |0 m- F% ^, DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 T* R7 w; g$ q$ @1 n8 ^5 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 S+ B( J- f1 h7 a! `9 t
0x00, 0xFF); /* configure the clock for transmitter */
+ Q3 ~8 m1 V! A, i! VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 c5 \2 Z, K% K0 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ l" v5 z# Y# N) y+ GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," v W# k" Q1 q$ G. {
0x00, 0xFF);4 w- k1 ]3 I3 d2 y4 `9 V
; J2 t! T7 E8 X' _
/* Enable synchronization of RX and TX sections */ % [2 {1 h. Z' S2 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
z4 r( l2 c. d0 c' y/ O0 h% R lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& f q' r' o! x" E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 \* X P9 I9 Q# p! l5 X. V3 ~' }$ x- Y6 n
** Set the serializers, Currently only one serializer is set as$ X/ K& O4 M5 }& [0 V7 y( e
** transmitter and one serializer as receiver.
+ d- z5 \7 ^6 Z: Q*/8 o: I' R! | W' X. P2 k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- [! M4 p' [, y- e0 V/ Z+ p! T( o+ v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 M4 J2 v' R/ q3 S' L0 z
** Configure the McASP pins
8 V5 L; h \, P** Input - Frame Sync, Clock and Serializer Rx$ B& @2 ] _1 C+ C# f# x
** Output - Serializer Tx is connected to the input of the codec
8 X( e2 s6 ]. C5 N* R. v/ Y*/& n! C, L% ^8 s$ ^! k" j# ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- \; o+ p1 S) A) |. e2 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 ~4 }" W; V" ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 }$ k. A2 y+ p| MCASP_PIN_ACLKX
+ o) [3 b. `% e8 T| MCASP_PIN_AHCLKX: v, }/ K, e$ W8 C( s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 ` ^' H( _; x! d; \8 I5 Q' s5 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / J1 ?0 h3 @8 @+ c! q( i% s
| MCASP_TX_CLKFAIL
" V6 p; @& z5 u% e' e' r T+ C| MCASP_TX_SYNCERROR' a* g1 u5 p# |* Z- E6 T" Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 c! P7 `" W+ I$ M3 A% J| MCASP_RX_CLKFAIL
" H, o" I9 a/ S1 H9 {6 N0 Z| MCASP_RX_SYNCERROR 2 M, w# {+ o1 y- n9 z- V" l
| MCASP_RX_OVERRUN);! f; q' E8 z7 H( V9 J
} static void I2SDataTxRxActivate(void)$ @3 \1 {5 U0 s; C) \9 E
{
3 A ]. q/ t/ Q/* Start the clocks */' g" T) i% y0 v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& O7 n8 l0 A2 q6 y6 K5 L- ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% I, r: h$ m$ c; ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* J) ]+ z4 C: M6 X! S# B' U- oEDMA3_TRIG_MODE_EVENT);' Y7 e( u! m3 C2 l$ E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 `+ S# C4 D1 E$ p( c( Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 ~1 t' h* }5 V3 a1 w' t0 YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- Q: W, y3 `' O' u: R. l) I0 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 m) |$ Y' z O) J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 Q) G, A3 e! x( ?3 O& ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 `2 m: \% ^8 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! |2 f3 ^; b" X6 k* W$ u
} " n/ _1 E0 ]; t/ B k- i% e8 X7 N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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