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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, n0 Y5 l$ t! e! M- F( Linput mcasp_ahclkx,/ B- }3 h, ?8 }1 @* m
input mcasp_aclkx,
; y( l5 y3 L0 X7 e4 Hinput axr0,
4 B3 d/ M+ l5 f# O' Y% o" U! l
3 W( I! ]/ g( F# H7 U: noutput mcasp_afsr,2 }' A7 t0 g- E) u8 N
output mcasp_ahclkr,6 K# B. m2 V% x2 y- F
output mcasp_aclkr,2 ?1 [/ p. R4 ~, G
output axr1,! L( Y9 r; E' ^! [* a4 c: I7 C
assign mcasp_afsr = mcasp_afsx;
1 f- y n8 m9 J+ m7 vassign mcasp_aclkr = mcasp_aclkx;
" A6 s$ F# j0 X! n* C6 ^2 Tassign mcasp_ahclkr = mcasp_ahclkx;% v2 q( ^" I7 b3 P# q: ]# \
assign axr1 = axr0; 4 H3 w& W) g- g9 `6 |
/ ?# y* {! m1 P3 L( k2 ^! b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 p( _% b. l4 m
static void McASPI2SConfigure(void)
8 v5 |0 z* L# p8 W6 S7 c# W" o8 Q{
" K5 n6 e) L% W( ^: ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' V8 U0 D- {" R- H4 I+ {( J$ Q( V) _+ OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- K. _% ]+ i& Q& T' c) ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); m0 ^% c" \4 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! L! \, L, V8 x9 ]/ \! R# y6 H9 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ^: u$ H" E; l8 |( t9 A- \) `8 c" n1 Z
MCASP_RX_MODE_DMA);3 w3 L6 j9 G; n9 k9 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," I' H$ N `0 @+ L9 G% b( g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- F/ e, A8 A8 X6 h1 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 b% N2 i/ v2 E. J" z) o+ G% c K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- N$ M; S, [3 u# Q- A5 ~- E( _& DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. O3 D0 P. B7 j( o; T2 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ Z- I- s7 H9 ]- H' @, \ wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: p5 b* W' B& \' h# \, ~, n* {- P P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % h2 s+ @' x: U3 F' r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 i4 f$ ^3 j' l4 `$ j9 {3 k2 P
0x00, 0xFF); /* configure the clock for transmitter */
& ~ z6 B3 a$ v* kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ `1 Y8 {* \6 u' [7 ^2 R7 M6 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 P. W$ l o6 l' f- g2 W1 y) q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ T) C/ L- p' R \4 S. f% l3 S
0x00, 0xFF);
$ L7 ]: Y3 Z) E k% E; f2 d2 f( T
/* Enable synchronization of RX and TX sections */
& _5 X9 Q. o) O5 e; K2 P- PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 n, p5 Q8 F7 u. Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 ~* z( a6 D, {3 b5 N1 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: D5 u: v' X/ @5 g n** Set the serializers, Currently only one serializer is set as3 F* k; V) p- @$ ^
** transmitter and one serializer as receiver.
2 M- y: b+ L8 B/ v. x2 M*/
, G8 u m8 W7 {/ {. ~# JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 {0 W6 @* p; ^% ^6 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 w% P8 f9 y7 R! i8 {6 t) `
** Configure the McASP pins . O! S n6 M7 k* U9 ?
** Input - Frame Sync, Clock and Serializer Rx
1 w% l6 w5 n. ~) W% k8 j. Z** Output - Serializer Tx is connected to the input of the codec / x3 n- E% E. s1 b
*/
$ P; A+ S7 d- }3 n4 d0 \; h: fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) p9 T8 x* p1 t; Y- i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" \5 {5 M1 D @9 o' i3 Q$ }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& w( Y) l. V7 ^' w/ I
| MCASP_PIN_ACLKX# y& \# U- J/ a3 \$ R+ V9 e6 {
| MCASP_PIN_AHCLKX2 T6 _. y u( w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, m6 C; T! u' @4 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' e" s1 u5 a" T# O2 r
| MCASP_TX_CLKFAIL 6 K# _" i7 E' [5 Z
| MCASP_TX_SYNCERROR4 f& Z2 B" ^2 x+ P$ ~8 @. M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! E4 n; \% e. Z; q; \" _2 @: i# c+ ~| MCASP_RX_CLKFAIL) C/ i/ a8 p: ]! j
| MCASP_RX_SYNCERROR / |2 a* D0 ?; `( z. q
| MCASP_RX_OVERRUN);
$ f; e) J t l: F( z' V, l} static void I2SDataTxRxActivate(void)* P6 S* H: A# |4 b9 d) A
{6 F8 j% V6 [# J: r1 s3 w, L
/* Start the clocks */
- _" d- |' i# t$ b" h" g2 I1 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 V4 F& {$ N! e( J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" U r% }- t# G- l/ W: M6 P' O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; u% G- t# Z- @7 c( {
EDMA3_TRIG_MODE_EVENT);9 x T. L2 t) ^3 W7 l t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: k1 j7 Q) W, JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 ^0 `) v9 |% X s# {5 tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' O9 P$ j, K0 y, |* H8 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: N$ f: u7 N* ]0 e/ L3 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 y: S- t' D5 {$ U/ UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) C5 ]( b/ P) {8 V7 n. M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. l3 c2 z* P" q' u% S7 w} ; L- \: A" N; |% [( }: H z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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