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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 R& Z5 K' V2 q# ginput mcasp_ahclkx,
$ |' e0 I, ?! s: r5 Hinput mcasp_aclkx,+ {+ ]+ a1 k1 i l+ G! [& \
input axr0,
+ t( Q1 G+ K) Z& X1 }4 p* V7 x
1 N9 }! z# v* S Ooutput mcasp_afsr,
2 A8 a, f4 C/ W# {" l! t1 aoutput mcasp_ahclkr,
+ p8 u! n* F: J' ioutput mcasp_aclkr,
) W2 O" w: R/ h2 i7 \output axr1,6 q& W. _% D m/ f X' j2 M
assign mcasp_afsr = mcasp_afsx;& b9 P* w4 I2 `) z7 d6 E# N
assign mcasp_aclkr = mcasp_aclkx;. k( T, [, ^" ^7 E/ T$ J
assign mcasp_ahclkr = mcasp_ahclkx;4 u4 B# D: ~; G4 i" D
assign axr1 = axr0;
0 d3 I2 W+ r8 }6 E( E
7 G9 K U* ?! @ `0 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 M# p8 x- M, @% F
static void McASPI2SConfigure(void)
" U5 z- h8 L/ _; J{
( n' U0 H( f! zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 \- s6 O/ M- \+ ` V: `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; V r) E& y3 H7 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* w8 n& R4 q# c/ d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 l5 }3 z, H$ ^8 A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) v( Z+ \( ?3 B6 Q) wMCASP_RX_MODE_DMA);
( I6 y) \) }6 e9 v& p) t# zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: I& n2 h. j6 ?" @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, ~- s" R/ q3 m0 m1 b1 z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " p5 B0 l, P2 F6 g2 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 m2 U: i6 O% OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 n8 b. G8 f5 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; e. B, `1 g6 l4 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); H0 B2 b4 }. e% Z I& `+ f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & {) L$ ^* O7 ^% R( l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 n$ W. B+ x& `5 S. R0 P
0x00, 0xFF); /* configure the clock for transmitter */
6 Q. x* D, c# R4 ^. J% M2 m! XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 Y: M) q3 S8 w4 P. TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
E2 y, _7 o6 vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& T) C- [8 G* ~ F& Y
0x00, 0xFF);
& w% I+ O0 |; W; @. \' F3 N4 u; @6 i& s6 U" H
/* Enable synchronization of RX and TX sections */
) V8 b* P3 p/ A+ H' P9 X/ uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ q$ P7 O. I; yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; e0 Q: E4 P- Z. u& N$ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 `0 p5 O* |! Q4 |* c** Set the serializers, Currently only one serializer is set as
1 X I7 e& ]% B; J** transmitter and one serializer as receiver.
/ ^1 V* X8 S4 j* ^$ r*/2 o) c' R. k- Z7 d! A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( V( S( H* D+ _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) V9 s5 \" ?+ q6 X* J** Configure the McASP pins . ^/ E% l) w- G$ s; F* W5 E) M
** Input - Frame Sync, Clock and Serializer Rx
`+ |; N- i4 k ]- Y** Output - Serializer Tx is connected to the input of the codec
& ]" \" K( L) r) {; M*/
) z0 |3 ~4 I/ u7 K3 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ K: C Q% I+ T2 @& m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( F8 w- w! ]( d6 F. r& r7 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
n& L3 K+ K! m+ t1 n) `| MCASP_PIN_ACLKX( F5 O3 U* ]6 d# ]% Q' J( M) W" d
| MCASP_PIN_AHCLKX
3 a* l# H4 `% D3 F! @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; S0 ^; q k5 t/ G; I9 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ i2 R! |# w1 x& d/ X+ [: x| MCASP_TX_CLKFAIL
, x; m; t' z t3 @" J| MCASP_TX_SYNCERROR
0 J- C3 O3 @4 z# U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( i* H4 ? ^6 e* Q1 o| MCASP_RX_CLKFAIL8 t5 L# ?. ?$ z* o) T9 T9 t3 U" J
| MCASP_RX_SYNCERROR 1 M0 e! p O G2 h p: Z' U8 [* E
| MCASP_RX_OVERRUN);
& U: C! w9 n) W$ m$ o} static void I2SDataTxRxActivate(void)
; H& o2 X$ X$ w1 f6 j4 Z# G{
3 `( u+ N( F; ?. R8 S; ^1 h6 s/* Start the clocks */
3 {7 v3 z: B, K' d5 PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 D" Q u. g+ w5 C2 B, y5 j; ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ k2 Z; {6 k6 W% bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
B0 [3 ]8 _% A# [$ R, s% |EDMA3_TRIG_MODE_EVENT);: s; P1 d+ {6 [0 O1 ]/ Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # D9 u Q1 Q. V$ a: ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ y4 R% W" {/ w k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) L b- f! k- {+ a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 c1 K% h& N8 U, ?8 s/ x. v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! Q, {2 m" [. ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 J+ t9 Y7 X, z7 k# n6 ?* EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 ]/ x! ?* g5 _0 ?, _
} 0 Z; F' {5 a) M$ Q0 d! j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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