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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ k4 G1 W, r4 a4 zinput mcasp_ahclkx,
) O8 `0 S" ?- L( o: n$ I, Ainput mcasp_aclkx,, Z1 k T0 A2 T! u+ E% }$ v( v
input axr0,
6 C; ]8 o( O% Z% n. J* ^, B' n) u% X2 d8 ~3 }7 [
output mcasp_afsr,
. s; \/ @6 P+ i }7 t: L( O Woutput mcasp_ahclkr,1 i' z1 |- Q. }
output mcasp_aclkr,* `% U$ H% D! n8 L) q) C: J
output axr1,0 K P, T* F, p( ]$ [, k( A
assign mcasp_afsr = mcasp_afsx;
* G& a* v2 L+ lassign mcasp_aclkr = mcasp_aclkx;
k' x. v4 e% [0 Q; O$ ]* eassign mcasp_ahclkr = mcasp_ahclkx;5 ^( ^" A- @3 W+ S+ Q, I4 W
assign axr1 = axr0; " O, M( s. H3 H% T; v
2 R q8 Z# Q: N% n$ d2 n- v) y- ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ ^) V0 k' }% }static void McASPI2SConfigure(void)
$ C3 |; C: ?/ d h* Y{
% k. C# a' O7 C8 u1 \; [4 d7 |; Z7 vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 v% p+ l, Q+ d1 }9 A' n& D0 N- kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 a3 f+ @, i" i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 F S/ V- g+ Y7 l2 J. ~% IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& d8 \% t! }9 P3 R8 }& w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& d3 s! F# `% Q- @. s/ l8 Y
MCASP_RX_MODE_DMA);
4 Y+ `5 Y% i+ p3 b2 o1 p! i+ p1 U. VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( M3 R' g- J5 K8 u( S1 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 x8 I2 u* Q# CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 H% w9 ], L4 i7 t; N* O! RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' J4 Y, E/ n, u" @! \4 Y) ]% }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, F: {4 Q4 P$ x; L; uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! X2 [* T$ P h/ c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. `/ U. ^* y; Q7 Y1 q/ }1 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 M j' v8 d7 E6 Y' E" f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, ?: l& J! M1 F5 v: H% N8 A, R0x00, 0xFF); /* configure the clock for transmitter */
2 m6 i& w4 u5 {+ r' w5 CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- I* A X q- B# `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " M0 k3 n e7 V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ M6 \2 Z# R5 l* V
0x00, 0xFF);
7 E4 Q( K) b0 p0 C) h7 N9 Z
' j4 _4 m$ F; n, |4 K7 ^/* Enable synchronization of RX and TX sections */
# s) I3 \3 f1 }6 A/ ^4 T* h9 r8 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 N' N- _0 G2 s! v! G" u) C. t3 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& y* W0 f" Q( V r9 W/ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 I3 T1 G, i$ ~% I** Set the serializers, Currently only one serializer is set as" E5 V/ u! c! @
** transmitter and one serializer as receiver.
0 L0 l, b9 v7 n& A2 y*/
, U. f. r" I8 g( t, L9 Z& MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ w' y% }; l$ E3 ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, i' |& ~" P5 ~
** Configure the McASP pins
* x6 c' a& Q: y& k1 E" N6 ]8 w** Input - Frame Sync, Clock and Serializer Rx# S6 J3 X3 _8 Z' S
** Output - Serializer Tx is connected to the input of the codec
( Q& A6 M& b( h( @*/
- U; _+ ]( ^, j0 j% s" aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 Y7 e" y% ] c- x: `$ @ C4 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ | K( m9 T- j: f7 Y4 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& w4 T3 l6 d3 Z* j/ I4 a& K2 s& _
| MCASP_PIN_ACLKX' g0 u r* r5 Z# o8 j% ]
| MCASP_PIN_AHCLKX
3 v2 v; i; R \& D8 q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 W F6 O# R2 S3 `1 M3 I4 y2 V! `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 a5 V+ X: @8 @. _) W& P| MCASP_TX_CLKFAIL
( e9 b! j3 W2 }6 M, {4 d+ { Q$ x4 }| MCASP_TX_SYNCERROR' u( C: b: b3 L( u" b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 H% N! C6 _) A# ]) [
| MCASP_RX_CLKFAIL
$ R/ S3 t4 o4 E v; P| MCASP_RX_SYNCERROR 7 D1 q: V* M5 h' e1 W/ w
| MCASP_RX_OVERRUN);
$ C* `, \/ X2 |! e% B} static void I2SDataTxRxActivate(void): v4 E! r3 G# K M; g
{; s6 a% X( o1 G, c2 ^
/* Start the clocks */
; L0 a& K0 S d8 y. d! ?1 g; v$ vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 }& B/ }3 Z: I5 X# s8 S( a3 J: h& o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
x, Z+ Z( D& t5 E% B [- @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
D6 N' K% I" w7 v; d& `EDMA3_TRIG_MODE_EVENT);
+ t3 J& v- {3 T$ AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( I' {# [. j4 C4 |$ m2 k% R8 ? F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 d4 o0 b0 E1 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ x2 C" x2 Q5 z0 `4 Y! @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 d1 j D4 f0 K1 Z: N( {" zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% s7 s, n' t9 I4 Q5 V) GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, c3 g$ O% }; \4 C0 }7 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 Z8 O. ~! [' S- R
}
9 f& F3 P; H7 Y% a2 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 N4 Z- F; }2 v: q4 ^
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