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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" ^ k5 |) E9 [# D* z: finput mcasp_ahclkx,% I6 m- `4 g+ Z
input mcasp_aclkx,) y# ^. C2 y3 z' k! @
input axr0,- w3 X R+ h& S: w
+ _* E( j4 U+ b; J! u4 [output mcasp_afsr,4 y: X2 k- l! i9 p0 _0 t
output mcasp_ahclkr,7 Y* h& O' x% B0 v- ]& p
output mcasp_aclkr,
% \+ v" f+ R9 Y+ y1 aoutput axr1,
" U- T1 i% R4 z0 C& c assign mcasp_afsr = mcasp_afsx;) S3 e8 j% D$ o# ^( ~" [7 u, v
assign mcasp_aclkr = mcasp_aclkx;5 [3 X/ w* d1 Q X5 p
assign mcasp_ahclkr = mcasp_ahclkx;
# }! A. V3 \4 X, rassign axr1 = axr0; \' ?, Q9 C; {/ ]8 E8 ^) E" P
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 }9 j( a0 V& Y
static void McASPI2SConfigure(void)
( S" d1 b+ ]! T$ a{0 {& [2 Y8 l+ }! d) }8 S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) Z: q0 U( t' L! H% l1 h$ W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! B0 w5 S! W2 @3 j* E/ f7 `$ oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* X; d8 e9 q- R' N5 o ~$ r% ~& L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) G. c7 z/ B0 c# \9 u$ P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- y* B9 Y4 [0 _! b0 K! }
MCASP_RX_MODE_DMA);# ~% J8 _( g, S6 E! w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; C% m# ~0 E. b- N, }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 O) Y5 @; O% }. }5 ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * y# Y4 i0 }1 q5 t/ B* Y0 H7 X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% `& i, @* L/ E# @) d; F4 n& |( iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ G; w9 n) V! E# m EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 W7 W- c. C, Q* {; ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! }4 ^* u0 i( g5 \! u4 J2 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ^* d4 P$ P6 [3 C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) Z+ S/ ]! D) b2 J2 e( r0x00, 0xFF); /* configure the clock for transmitter */. G% @- s7 J. Q+ z8 Y1 c4 ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' A i( J9 p5 A) I4 N9 X/ u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 s+ S/ r' i" T1 e0 gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ o) K' w9 b( U$ F, T5 _- P2 w) Y6 O0x00, 0xFF);( w: K k' a; z3 w
0 a. P' j9 g2 [, Q& H: X. o4 [
/* Enable synchronization of RX and TX sections */
6 @3 ?6 R* m: W# n+ HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 Z1 w7 i; x7 x" O& H+ i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 W+ z* ^& G6 k* ]% I' m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& X+ ~3 `, z2 M+ ?5 z# P9 k** Set the serializers, Currently only one serializer is set as' d" b9 w5 G% g K6 W2 Y* |+ x( _
** transmitter and one serializer as receiver.
9 Y1 V; b1 I3 K' N8 x1 `7 _*/
* P( W0 L4 \. P* C8 K1 C2 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; z0 D+ w* k4 w' U0 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, N* p$ N0 C0 k2 n1 n* g
** Configure the McASP pins ( _! G3 C+ v* I& Q- t9 X! |
** Input - Frame Sync, Clock and Serializer Rx
1 ^3 I, ^3 u8 ]* g: e** Output - Serializer Tx is connected to the input of the codec + c- o( G2 ~1 b( o1 S" ?/ T' f
*/9 {( F0 `+ w; v7 Q, |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' ]8 E5 h: R, v* ]: IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" T. P7 ~- L- X3 F v/ _# T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 \3 N; i* J; X+ G9 \! K$ d& L& e
| MCASP_PIN_ACLKX9 z! k7 c, M4 h
| MCASP_PIN_AHCLKX
5 ~& |& Z4 s/ i1 b* \* h3 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" R- P2 p% k8 _+ B$ `2 E8 _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- B, n/ m; r- `5 _| MCASP_TX_CLKFAIL
" G; r* R0 x. l$ k$ z1 || MCASP_TX_SYNCERROR0 X; V" D8 ]% m5 Z( Q. l' Q5 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 o) t X- W6 o1 A( \! G+ q
| MCASP_RX_CLKFAIL4 c g* L) @% a+ Q1 Q$ ^9 v
| MCASP_RX_SYNCERROR : i2 B4 k- ?) Q" R* H# F# i
| MCASP_RX_OVERRUN);: Z. m# Q8 B" o5 r3 H i/ ~( H
} static void I2SDataTxRxActivate(void)
: x& c9 b' Y$ T& X- I3 m; e. Y& T: v{
3 C/ i5 P a( }8 ]* S: y/* Start the clocks */
8 g, h5 p& Z, z7 m; j$ { k* vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 Y2 V$ J1 r& N J$ ]! v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" C9 s; a7 J; y5 V k. p7 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 { A, @" |; t3 T5 l6 C" _
EDMA3_TRIG_MODE_EVENT);+ z- M9 _: @9 p4 v1 C7 `' e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# c- i+ H M* Z9 dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& S( J0 l" c% s' s2 F* H$ |7 N) ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ T! ^2 y, ?3 d- ~. u' f' H& \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 p( `! l3 f+ I ~ hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. O, j2 |% V3 i5 U! e U- S9 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" W% T7 n8 S2 z: \" l" O5 _4 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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% z$ F( G0 l& z( L+ u* y y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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