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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% V. _( n2 `6 M' Q1 l' Minput mcasp_ahclkx,
! n* V, a0 g# t M N# [ c! R9 Rinput mcasp_aclkx,! }* v4 U# F$ g! x# N' y
input axr0, @7 e# t& I1 a4 t
% U% |! ?$ j% N7 ?0 }& T: Loutput mcasp_afsr,
( ^) R& x5 D* e- O8 routput mcasp_ahclkr,! g! K) W7 h+ P$ F1 m: c `
output mcasp_aclkr,
0 h5 y$ k. W1 D; U% J# U, ]% _output axr1,
# @5 {1 z2 ^% V( o! ^! _ assign mcasp_afsr = mcasp_afsx;
1 |! m8 o9 N+ Z, G% Z$ @assign mcasp_aclkr = mcasp_aclkx;* g' s* c* p0 Y# r
assign mcasp_ahclkr = mcasp_ahclkx;
# m$ |& T' E: ?9 k* q+ a- v! Yassign axr1 = axr0;
4 p2 k7 ^& J( ^
% l6 U b& `1 N. U. N( G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 u3 z Q! `1 l v. s* \4 N
static void McASPI2SConfigure(void)5 a+ M g: q$ E, m- K4 A" X
{
2 y" U5 ^2 S( T# d# v9 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 y) M: W' a: K3 ~" R1 }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 _7 X! ~9 W& N' z; hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 o& W* c2 _8 @7 q. `( ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 N6 e& f: [+ ]2 J# PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t6 } s0 W# r8 y2 @* h
MCASP_RX_MODE_DMA);+ a# ^. ]2 N! Z6 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& Y+ D' `3 j3 s( U+ xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" M( h- d+ Q- d( ~2 d6 S' \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 N& ?: C9 a) S. f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 T6 S' j2 W3 b2 H; }8 K, WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * O& O2 V9 ~& K" |1 E, \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 X/ R8 }( E E( M1 A: b8 p3 z( bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* A; q) d5 P7 W+ {* E. M$ N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 r' g) w: v+ w& G( i5 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 n8 ?; O0 j1 `7 ]. n0x00, 0xFF); /* configure the clock for transmitter */6 ^: ?. W0 G5 H' F7 L5 {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 B2 q' Z7 H# I; o0 K" w+ j7 u7 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' n9 @' d7 d. @7 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 i) @" h; X5 j- v9 ?
0x00, 0xFF);
8 H G; q; x. z" V6 Z7 {5 D/ N% o4 r
/* Enable synchronization of RX and TX sections */ 8 m7 D. h1 K6 ?. W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 C- o" [2 m7 F1 t& g) ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( q Q. {, @* G7 i `, D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 D, E3 F& g3 M7 a
** Set the serializers, Currently only one serializer is set as
1 A: y5 p+ a! A7 h** transmitter and one serializer as receiver.
* a/ u* b- q" W; P*/
1 Q ~0 [5 B, o5 B* PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% z2 Y) ?( P# _' I4 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' B3 f6 ]) |4 ?1 \( z4 c! a
** Configure the McASP pins 8 w: z6 k. E- v8 y
** Input - Frame Sync, Clock and Serializer Rx. r; Q5 ?* y% i7 ]
** Output - Serializer Tx is connected to the input of the codec
+ x/ z0 V0 k9 t, v3 ^5 X( B _ j6 G*/
# L* v5 m9 Y! s0 _, f1 XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 s/ w) D& a. H0 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; H: B, C Z2 l W( N, `/ N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' ` n" l) `" m+ z* _| MCASP_PIN_ACLKX: A/ o; H, f9 x
| MCASP_PIN_AHCLKX
" ]3 x5 U8 N& Q( H& Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* x/ w ?3 i9 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * ^9 `. b, @/ n! f1 l2 }
| MCASP_TX_CLKFAIL
8 l# f8 v9 y9 g# |2 V& E. Y# X| MCASP_TX_SYNCERROR' I4 t. E* ]3 e9 a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 D6 p& ?8 W/ S7 G1 v# M
| MCASP_RX_CLKFAIL
6 _ B* c5 y r) z b% Z9 `| MCASP_RX_SYNCERROR
- F1 N/ K( f, o, Z' L6 m| MCASP_RX_OVERRUN);
. G9 `/ q1 V0 }2 N} static void I2SDataTxRxActivate(void)
2 g* u7 q- Y7 T! ?7 G% V8 U m{. W0 l% D3 k& ]* R8 U/ A; g2 F
/* Start the clocks */1 \+ y$ r7 [7 U5 Y7 t0 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) {( V, k j. ^2 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ R9 N2 ^7 b4 I8 b) s: j: s7 B; D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! \5 q5 e8 ?9 C' T, \* q
EDMA3_TRIG_MODE_EVENT);' S. W: h. o2 `4 c2 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . ~! ?1 j ^1 r8 g' e2 S% g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, U- V _5 G( ^% D$ DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! N3 G. Y7 S( Z/ Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' a2 b1 |- x+ M) q0 X" ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" c; J" D8 B2 E' Y7 n9 y7 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: Y# Q5 G. [2 c$ p4 E/ x, D. ?& sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" o' ?7 B) n6 @# N2 S! [8 h}
% V( U! D5 Y& R+ ]$ H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * N+ M: F+ q* g- D5 `
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