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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, [$ n+ A( R$ k4 }, S7 x$ d
input mcasp_ahclkx,, h+ ?; d) }; K; ]/ O) i. Y1 i
input mcasp_aclkx,; {: p# ^; O. k/ c( n8 P: L
input axr0,1 G! U# h5 e3 E% `4 C& v2 Y3 B
7 g9 j0 C7 H* k
output mcasp_afsr,2 m( ~3 X- A8 A7 y9 m3 P7 K+ I
output mcasp_ahclkr,
0 g+ h3 V& j) toutput mcasp_aclkr,: S7 T1 p" i3 _0 _6 {' n- C
output axr1,
" `, s/ f; h# l/ a; e assign mcasp_afsr = mcasp_afsx;
) r- I# j; f' L2 vassign mcasp_aclkr = mcasp_aclkx;
# `/ i2 J, r* }1 ~- |- Yassign mcasp_ahclkr = mcasp_ahclkx;
. L! l/ U6 h% B3 t$ @9 h( ~3 Qassign axr1 = axr0; * T" E) a3 P3 G5 o) E/ ~5 ]6 ~
5 E9 B( M* f2 e. n( |5 D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 d' a7 G, m0 c/ e
static void McASPI2SConfigure(void)/ x! Y8 y! Z4 s8 ?
{
6 ^; C% ^6 m2 u# u5 v4 A4 XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, s r, \% t U# `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 D- G/ `2 I3 o7 W( H) z; R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 ~8 |, X J7 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 i. F( L1 Y8 m( q8 L' H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* r _% f" M$ K5 n! X- ? L. cMCASP_RX_MODE_DMA);
5 O& M' M5 D! w& \9 w2 U, w0 D9 u9 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# C# L# {9 U* T) pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" A0 z; V2 n" J1 P' ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % ]# ~- H3 ~( }# h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 \$ v4 | h$ _6 L# F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 _8 m$ t t2 J' L$ G$ uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' w4 w. E1 x3 |/ S! J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, D( ?$ F C0 a; `% z4 ~6 j2 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 ^# j% W5 ]! y7 p; E, n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 G$ q/ n4 \/ o- B
0x00, 0xFF); /* configure the clock for transmitter */$ n. ^& c9 W! L$ c/ n1 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 Z# j$ }4 y2 |* W7 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ z- |7 Q0 }6 }2 `# u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
]$ k1 b4 K) m* D/ u' z! p0x00, 0xFF);2 H. M6 o( x! g4 v+ {2 _/ b3 M
4 [: ~; o3 v% h. T( Z: X, s
/* Enable synchronization of RX and TX sections */
, O/ W+ W t3 M" F8 D& aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- a& q# V$ O& }- lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ S# t0 Z4 R2 Y. M. A- rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
R- Q- w6 p9 }6 r; n8 I** Set the serializers, Currently only one serializer is set as
& J' B+ v$ ^. A: Q; D9 b& W) l9 ?** transmitter and one serializer as receiver." K, |) R2 G+ o, M" `8 d% Z
*/. H2 J$ M' u9 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 z; L @; n( G" i& b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. b1 J8 U! |- s/ K" p7 R
** Configure the McASP pins
4 E: ` L" X9 \** Input - Frame Sync, Clock and Serializer Rx
; n9 M4 p. B6 p" {** Output - Serializer Tx is connected to the input of the codec ' ^. d- [- L& b8 z
*/
, [( u" t6 r( J5 @1 h8 Z5 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ r& i" `; a# B- U% t& s7 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. ]9 q4 \- k$ e1 m6 ^( _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# J. q. B" L) E) }+ r$ ^
| MCASP_PIN_ACLKX: D @- K( [9 Y) b2 E) h
| MCASP_PIN_AHCLKX
% f+ j* k+ ]( {) T" V( P* w# {6 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// t: V" t7 H& L3 I& r8 U. l( m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , G( x( D/ m- N7 n+ J, ^
| MCASP_TX_CLKFAIL ; d: W( @+ @& e4 v8 \$ w
| MCASP_TX_SYNCERROR G1 b; y9 N5 w& Q5 J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; W! n: S+ @0 @$ O
| MCASP_RX_CLKFAIL
0 A0 h' L6 i# H5 w6 C2 K| MCASP_RX_SYNCERROR ) p* v( v, _0 B Z; G G2 x. j( ^
| MCASP_RX_OVERRUN);
$ y& b5 }% I+ ~} static void I2SDataTxRxActivate(void)2 Z# U4 x+ |9 {
{
6 t. ^5 P& ?1 L$ `/* Start the clocks */
* L! `. X* D5 p1 N* U& X7 _7 k' J- p2 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& }- ^$ e; b1 {! y3 w: M( l* H8 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
{$ _0 H2 k7 |8 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, _7 f- u1 U6 Z# c6 jEDMA3_TRIG_MODE_EVENT);
& ?6 n: X0 Q. K* L' MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# Z# y7 d7 p9 u& EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ S" _+ N+ E) P- x; N6 \* E3 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 U. L' E- T4 h- P+ L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 r. W8 Z1 h9 [4 V. c. r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( L \' |4 }0 P& x" \, A) y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ P. o7 \) z* y f4 |& P! GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 g8 t: |! ?2 L3 x7 Z1 J
} # r% ~' G5 I7 x/ l, t- h+ O. Y/ |( z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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