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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 ]4 C0 ?# b' O3 `2 M
input mcasp_ahclkx,
( ]5 K# h# D& F0 B0 l; o8 Ninput mcasp_aclkx,1 h5 d* l0 d/ Z+ p
input axr0,
: J0 [/ K% y, U; a+ T' A+ ]5 E- A! b4 U q9 A
output mcasp_afsr,
9 ]9 ~ Q; i# J5 D( R+ Routput mcasp_ahclkr,/ O1 f: ?# Z5 Z0 r/ O+ o: H8 _
output mcasp_aclkr,) C" z8 N3 l t1 n+ @# q& G3 s
output axr1,( S8 @9 ^/ D% X/ @/ H
assign mcasp_afsr = mcasp_afsx;
+ C$ Q2 i7 L3 m5 r7 e+ zassign mcasp_aclkr = mcasp_aclkx;
% q! A _1 j6 a8 ~8 h7 _assign mcasp_ahclkr = mcasp_ahclkx;
$ F- A9 s5 L+ {6 b4 lassign axr1 = axr0; 9 e7 c. X) x" n. d1 W+ d4 Y9 j3 c
: g- L" N6 t7 S8 U7 `" {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 r$ r, }# e# {$ q/ U7 d* z5 q s
static void McASPI2SConfigure(void)
5 t# o- m4 b+ D3 Y4 p6 m{
2 r- J# j Y# Z$ V0 \5 o1 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( L0 X7 Q4 l0 y& C7 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; X2 F3 J5 K' m, g/ sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- D* }( M0 |1 Q, pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" V* j) N6 ?, P2 _7 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, \0 ^$ R, [3 d# ?( ^7 u5 ~MCASP_RX_MODE_DMA);
8 w0 ?& L: c1 y3 m. ?2 ^* U: ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 M2 l7 Y, I+ F4 P' F& g: c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 p8 x+ G V$ u6 p+ J- B* h3 L- l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 D0 Y4 ?* u1 w0 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 t- a/ ~$ Y7 `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& Y" A9 B0 C1 W+ Z/ t K, iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 N O+ W9 m- b3 L0 @. ]4 IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
s; m$ ^7 ~) ?1 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 d8 ]) l# \/ ^7 T3 e' \# c6 ]5 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 d) ^4 x7 O/ f2 @0 b# U, Q
0x00, 0xFF); /* configure the clock for transmitter */
' k8 m! ]# H p F# @$ {" ?; oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
C. [" r" ?! eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 Y1 \* Z$ S' K* `0 P* x! V, @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 l( q' F6 R. q0x00, 0xFF);
1 [8 P6 U* U/ F D7 @1 d& |' R( E/ @. z, \/ T
/* Enable synchronization of RX and TX sections */
! ~# p A; l- x- ^4 w! wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! x0 a4 V" @# f: C# p( |0 Y" V6 fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
m' L) r" |& J+ C8 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' B W! l3 V+ [! T** Set the serializers, Currently only one serializer is set as+ F, ?# S% i. f9 d0 Z+ s+ e3 l( L
** transmitter and one serializer as receiver.
1 }8 V" b; e7 H/ j) r# B! [/ _*/
" X+ p# K/ s5 M3 q; R4 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- O# H$ F# T2 |% ?: e5 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. _1 Q% L$ p' X0 \
** Configure the McASP pins
, M1 V% y; s( G, r z" h** Input - Frame Sync, Clock and Serializer Rx$ x7 a/ X- k5 @0 M; l. e. d! j
** Output - Serializer Tx is connected to the input of the codec
! q. K0 T* L# q5 R*/
* s& E; w) V5 x' P6 V& n, VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); N0 g$ ?& [5 Q% D+ w2 p! h! k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ l/ R* C/ w) ]8 T1 O( N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: Q9 D4 m2 y+ l1 U* a& d& u| MCASP_PIN_ACLKX
. L4 {6 o1 _( y| MCASP_PIN_AHCLKX$ t \9 ]2 u1 p6 a, i; T5 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! O c: a" d2 Q& kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; {' J G, C# a' O| MCASP_TX_CLKFAIL
7 W/ k% E9 W$ L/ ]6 Q, O- o| MCASP_TX_SYNCERROR9 q+ Z" X9 G% t' g: @9 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ {7 O$ C( `" t! O| MCASP_RX_CLKFAIL
1 b" I, O% {6 Y ^% w1 m8 i| MCASP_RX_SYNCERROR $ p0 Q) a7 z# ~8 t
| MCASP_RX_OVERRUN);
! h6 ]# h! Q3 P, E} static void I2SDataTxRxActivate(void)
" L' U/ J6 r( L: D: W1 o{
% h. K, D1 w/ L ?2 ~. c9 G+ p) L/* Start the clocks */
: B+ e2 m$ w3 b6 w" d4 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- r! B. G. c% A/ A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ ~( N/ M$ d% j; T+ `# {# z MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 _6 b! \: H |8 q0 \% Y2 h' {4 \
EDMA3_TRIG_MODE_EVENT);
, F6 Z. j& Y9 ]( l! qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ }* x5 S+ c* i/ QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ d- g- C3 y/ v- d* n/ q$ n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
v* u: b- e7 l, C t; iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& J5 }: C6 V& y3 z0 `0 `( C/ Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* G2 u% V+ G- l* W( W: d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; W8 K- \0 C& D: [1 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( b! \0 I. c% O( {" [! l; x7 {
}
1 R: B9 r2 ?/ Z' S9 ]2 F4 f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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