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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# ^) _9 W& e, C8 H3 L
input mcasp_ahclkx,9 ?: k) W6 Z7 A5 M
input mcasp_aclkx,
( o4 u8 N* `0 r8 d' S9 h# kinput axr0,
/ [0 Y; s0 V' K. ^- W* _: k4 ]9 w( u5 f8 l
output mcasp_afsr,
$ M8 f( r5 v Z5 xoutput mcasp_ahclkr,
( l% H. ?0 k% O6 E! ]output mcasp_aclkr,
6 C- i$ i" g$ g! f3 }7 noutput axr1, q; B" r. N0 l/ [$ Q; U% w" N
assign mcasp_afsr = mcasp_afsx;
; I5 e6 M4 w4 k3 J2 h/ p. nassign mcasp_aclkr = mcasp_aclkx;
2 q5 @8 i* b& r2 Z/ X) W% oassign mcasp_ahclkr = mcasp_ahclkx;* b; T% P5 M+ x
assign axr1 = axr0;
$ N. ~) v- s' ~) w1 Q, `* @6 j7 }' I) @1 C# L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 F$ x2 u( \4 _7 P+ q' {7 `static void McASPI2SConfigure(void); B+ ]/ W o2 G3 D
{
/ I2 ^# w. t" v6 E' Y1 m, rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, s$ n; O @9 kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 k% O3 D) x/ s% Y9 E% I: t) ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" }4 M R6 u* l7 w# `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" N3 _' F) j& i. T8 t% ~$ f5 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ~' C8 X4 h& d8 t) kMCASP_RX_MODE_DMA);# F+ ?+ }+ e! P! u% m: Y4 P4 ^0 a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( J/ C8 P" \. M6 F6 i$ N6 i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 R, D1 E9 M; A# H+ `7 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " a- m9 d% e6 u7 Z# N% j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 V9 c- E3 J3 p/ P$ z s/ c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& d* c9 F, M+ K0 @9 ^' aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 r( O5 z2 c m2 Y# E! O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, t# J8 I- I/ N* B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% i4 v* x d- }8 c. nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ _4 G, w( L- Y/ O0x00, 0xFF); /* configure the clock for transmitter */9 Z4 ~( [! H) L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" q# w7 v! A& t$ d9 M8 ^# @( {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & i4 x; m6 m. I% a4 V, ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 ?; c# ^# d- T" o2 w3 E
0x00, 0xFF);
" u5 W( a4 L" n! X% [
: z h T0 N# V6 R/* Enable synchronization of RX and TX sections */
' C+ H$ \( |: F2 \) c$ ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 \& \$ @, m0 X, Y% D9 ?$ AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: E0 W, r# ~5 w k. n% d2 Z/ mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 S9 |( o* R: j. u: J** Set the serializers, Currently only one serializer is set as& E" P+ U4 \! ~, j+ `
** transmitter and one serializer as receiver.3 |( ?7 ^7 o. R2 J& T- b! N* b4 p
*/
- V7 V8 f7 x3 X0 a- t& M# XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 I, U; Z+ r. @" Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 ^+ s2 Z. i' l
** Configure the McASP pins
$ }9 K+ r. G8 {# t** Input - Frame Sync, Clock and Serializer Rx
2 J9 i' f ` l* Q- I: J% C9 s6 t** Output - Serializer Tx is connected to the input of the codec
- v* B0 B% u5 C# m, ?" |*/
" s% D: ~# j4 D1 w& ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* _7 J; B& p3 y- p- FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 m0 U7 t+ T O$ {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* s% f) _7 U' b. u' t, n
| MCASP_PIN_ACLKX6 O, O4 ]9 \0 V- M, A$ ]$ ?+ T' D
| MCASP_PIN_AHCLKX% C5 U* N- o3 f0 C7 v6 z, @# X' L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* U/ i {: h( i5 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ j$ {6 j3 \ ?% Q& X5 D* W2 y0 a3 u5 W| MCASP_TX_CLKFAIL
$ k- T K' M7 m| MCASP_TX_SYNCERROR
0 S1 n0 U; V% I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* J+ e. a1 m0 c/ p B4 X| MCASP_RX_CLKFAIL
6 a' E! G1 \, w2 d| MCASP_RX_SYNCERROR ( }1 B. |* D0 h I
| MCASP_RX_OVERRUN);7 b1 o( d; Z+ O; D" F! ^
} static void I2SDataTxRxActivate(void)! H- T0 a' i8 `: ?9 E# n9 V
{
$ t2 s& p% x8 z* B4 [/* Start the clocks */9 i8 G# {5 B2 V& O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 O4 w l, {! Y0 p8 }% A( G* T2 ^7 JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" j; y+ F5 }' r- c3 o1 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; p9 G: \" z9 nEDMA3_TRIG_MODE_EVENT);& G- [5 }! b+ t7 [- w, m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; H& Q3 O1 g( {4 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 g8 L3 [0 m. U; Y( V- F7 Z& AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 X+ C+ Z& x) w* f% J5 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 Z8 q* \+ @" n$ _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: X" Z/ u9 v$ m% l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% Q7 V8 Z. H) p/ _7 H& H5 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); ^% x; C, a8 J( O
} " R# V! |+ Y& E) l$ H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 {) _6 o1 Q/ @( z; s6 ?% T
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