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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- ?( v5 h& v, E5 u# Y9 S; r" M, Y
input mcasp_ahclkx,* t+ I" Q3 G: c1 J8 m
input mcasp_aclkx,: g- T+ q7 v$ U" V* q
input axr0,
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* j4 k3 I/ D1 uoutput mcasp_afsr,
- u+ |9 \& a( Z$ y+ T) m( z+ Ooutput mcasp_ahclkr,2 I+ v# S1 i) h! v: J% \2 `; o ^3 P
output mcasp_aclkr,. o. y# Q! a% u- j# p4 y. g# [
output axr1,
4 b4 \, r0 `! _: L. G' e _ assign mcasp_afsr = mcasp_afsx;
$ U6 U6 ^( ~) D& d1 [ d* w3 hassign mcasp_aclkr = mcasp_aclkx;6 g7 l' i; c \3 ^8 } E3 Y8 X: l' a
assign mcasp_ahclkr = mcasp_ahclkx;
/ ~8 t# W9 l- V+ O+ _$ u4 eassign axr1 = axr0; 9 \2 q1 V5 t! u
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 W2 ~7 O6 k* n: D vstatic void McASPI2SConfigure(void)
5 k, \- B/ @5 x) F{; S- N$ f- s: F5 |* ]* R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 U, g2 k, M- T; C4 o8 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: y$ `1 x: u8 l# ] e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 V1 C; J9 x7 j: ^0 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. z2 x6 D% r/ l- B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- H7 ?" `' m) _1 m+ H, w
MCASP_RX_MODE_DMA);
0 ~: B) |8 g' ^& \7 H1 F2 `; E# S3 Y6 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& L% K6 Q9 a. I; [, }$ D& XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 U/ W# J) E3 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
A" [2 J; j3 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' Z' O/ v1 H, L4 T$ hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 g4 Q) C" i- _* f) B' c* z, O9 \2 P4 NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ |# J- t8 l6 m8 x: R! T' HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- w0 G9 `/ a5 x& m' [ G! E( c& nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & A) p+ G. R5 x0 N2 C9 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! {5 y6 _, u7 d# m
0x00, 0xFF); /* configure the clock for transmitter */" `& \1 C/ K6 y' @2 B( C1 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: _6 Z3 n& P eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " ~0 K& L' P: F; D. E; ~" {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* b/ I) M( d" m) i" q9 a
0x00, 0xFF);
1 E& X7 } ^( o8 `2 g/ t
+ Z D4 g; `8 r2 e! W% U/* Enable synchronization of RX and TX sections */
" R$ p7 K% }# `6 G9 r. aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- l5 c8 u2 r. v9 M3 q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 `/ w$ U6 E. T8 jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 B; ] j! R+ n {3 a" |2 r* ?
** Set the serializers, Currently only one serializer is set as
/ F4 w4 d! G8 d6 R( r** transmitter and one serializer as receiver.
/ \: C9 H/ M8 Z, b7 u% E/ S7 U6 E*/
3 e5 c8 C' ?6 @' r# F V& iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ d" \* X4 H) v" g2 ?. }9 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 E4 x a2 z; t** Configure the McASP pins 6 z% g4 ], u Q, P, T$ y7 W
** Input - Frame Sync, Clock and Serializer Rx1 u# F6 [) N3 K' ^& c5 y
** Output - Serializer Tx is connected to the input of the codec 5 }3 H. H7 X5 I8 b5 i; L$ p6 W9 i
*/- ~3 y |. _9 @# D( ~6 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& g5 O( r' M1 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( V$ |4 Y* b! U! O# b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ H/ Q, [. ?# M# X% Z" I. E| MCASP_PIN_ACLKX" a. s+ L) ~# l9 K
| MCASP_PIN_AHCLKX
: ^9 W0 l+ D7 B0 h7 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 w* A+ i% Q' j& p/ ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " ^) w4 X' q2 c* E# L e" S7 b
| MCASP_TX_CLKFAIL
3 R9 L; F8 M, @1 m3 B" @( F/ D| MCASP_TX_SYNCERROR
. D, n1 X' r5 @6 O" ~7 Z3 E' t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , @% i9 U' e" e/ Y y! [8 `5 }
| MCASP_RX_CLKFAIL2 F& K! d; N2 h5 Q8 Q& m
| MCASP_RX_SYNCERROR 1 a/ G$ Z- V- H/ Z) w$ I# i' }
| MCASP_RX_OVERRUN);
# K- ^1 u( c9 H3 n1 x- Q. K" D} static void I2SDataTxRxActivate(void)
8 {' q6 X( \0 N8 ^4 M' I5 [: |{2 I; J) g- h, n0 \$ I% A$ V
/* Start the clocks */0 ?" D, K+ C/ B L, i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- m3 ~/ }* Z1 [( ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ]- B4 O2 u+ O, ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ K3 a/ N* C7 ^+ x
EDMA3_TRIG_MODE_EVENT);# }1 C6 s1 U n; }' e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * a h, }+ m9 x4 Y( J/ l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' h2 u) f8 }# s$ t t3 V! \5 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) D6 l, C& M! G6 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 P( O9 Z1 I& S+ \/ k6 Y2 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" M8 d+ c9 s: Y6 t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 j! c1 Z! u* S) d% J% w% J% ^4 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ I, E* u0 c* Y5 Q6 N} + O9 C3 N8 Z X. [# g: O6 g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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