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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' D$ p2 e7 p9 j& b3 l4 i7 Q
input mcasp_ahclkx,8 p1 V2 `$ v% _, E5 L0 }
input mcasp_aclkx,
: h0 N6 [5 @8 V4 e. |input axr0,/ K' ^ J! G0 L$ k
# d: m+ m. D4 a6 routput mcasp_afsr,7 R7 \2 L' `$ J$ g
output mcasp_ahclkr,
. I+ y8 ?$ k: Toutput mcasp_aclkr,
- G$ _) W6 x+ x: u* noutput axr1,3 r/ a1 u5 w% S, ^ q
assign mcasp_afsr = mcasp_afsx;5 L6 c% e1 i i. r/ T: k2 d! ^
assign mcasp_aclkr = mcasp_aclkx;
* e/ @: s6 {8 j) t# gassign mcasp_ahclkr = mcasp_ahclkx;
7 Y) e5 P# L7 r+ S. ~+ h0 aassign axr1 = axr0;
6 L7 c1 b7 G: J& a x9 O0 a* c. c. I) c) E6 C7 |& O% x4 C* t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& X4 r2 `+ n2 i! Wstatic void McASPI2SConfigure(void)
8 {1 P5 N: V; i1 c$ k8 _{
1 r+ q% I: Z# _, DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# ~5 H* v ?5 i$ V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' {" G, K6 t( D5 I7 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 _3 I+ R+ L, [1 a1 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 v& ~3 q! t7 P% q; J7 \ ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 O1 k+ e+ M5 O0 M& \4 x8 yMCASP_RX_MODE_DMA);
2 c* M) `) a6 S+ Q' E _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( f$ u, O) Z. M0 R9 T. F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ [- i6 i* Y8 |) C! B3 a" H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - ]7 T1 w9 @9 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( ]2 u9 W' m) g; G: [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 f) A" G' V& W% r* _* mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. ]7 {% w; ]9 c9 r* J# p& vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- U0 W8 W0 i" F6 U# S' i% eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
~5 t" F' [ n3 c) wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ P$ W7 z0 j' d& z
0x00, 0xFF); /* configure the clock for transmitter */
s! o3 y/ {( ^0 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% ]4 w: M" K, [$ i8 ]$ ]$ @) q' @* V* a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # Z6 p. ^; b: L3 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 ?/ f# S K7 v+ q% ~
0x00, 0xFF);2 |( ]& }6 b3 p/ W' c" @1 c
+ n# L. Q( j. Q4 s/* Enable synchronization of RX and TX sections */
+ k) f7 f$ R1 g% H _. M+ D) hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% f# l* V! z2 R& e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! ^/ ^6 m. W6 F1 G: bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ l4 @+ T% E# j: c** Set the serializers, Currently only one serializer is set as
6 q. v2 c$ C3 @** transmitter and one serializer as receiver.: l8 c2 ]( b: s7 G e; W
*/+ d: ]. w$ ^; W* f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 N4 }2 W$ t F q2 Q& n( j8 z7 d; dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! z/ ?; R: b5 A9 I \** Configure the McASP pins
4 X' G, U6 F9 X" N$ [; v: _* w** Input - Frame Sync, Clock and Serializer Rx
, H, t7 G6 [: m2 |) B** Output - Serializer Tx is connected to the input of the codec 1 }! \4 {) n( @2 K( G
*/' {2 c6 }; K! X* [8 j0 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 k( `5 [& D. }6 F% S6 O! a/ g- u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 K8 D6 C% E' P6 F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, ?, z( j% _ R, S# || MCASP_PIN_ACLKX
2 N3 S7 F, N1 r5 y1 u8 R| MCASP_PIN_AHCLKX
- s+ Q9 l' [: y1 F* q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 e3 K: {0 O( mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 @% n0 l" M9 q8 M| MCASP_TX_CLKFAIL 3 d% m R4 h3 a. R! E: l: p
| MCASP_TX_SYNCERROR
- @0 N1 ]" r( l8 w' \1 s' u# G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 r: C: ~! k) E" m' O) G| MCASP_RX_CLKFAIL
7 L% k# I$ |3 M. }! j" L# K, f| MCASP_RX_SYNCERROR
0 U' e1 n$ T* \8 y) a& ~7 b| MCASP_RX_OVERRUN);
( o; _% L( p6 \, \+ E4 M+ S} static void I2SDataTxRxActivate(void)
5 w+ Q O4 {( {* n: H+ {{, M3 Z, l2 u4 T0 S) u) X. @) R
/* Start the clocks */4 v l1 @* G# Z& O* |6 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* n! Y1 M2 I$ G" c) t0 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" e G* k9 S6 J3 x" @1 o% A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 S: c- Z9 N) {$ F3 cEDMA3_TRIG_MODE_EVENT);
8 \" \' o8 `7 v2 o% ]' z" ^3 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% b7 b" V7 f+ LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( s/ y/ d8 m( q% B3 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 ~9 L) Z+ J2 x0 J! O# [+ o* IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, [ D" M# c; v6 S- V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 Z/ Y. B4 H7 h I3 e) h# M) P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 ]/ B x% _, h C: a, Q! @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: J3 i$ f; a. r6 u7 N: A. b
}
- O! \; `% C0 g5 Q3 L+ ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , M, Y, W: T v6 a( W/ g9 H
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