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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* t- c! c8 f/ d8 F; Z3 O
input mcasp_ahclkx,9 z, P) m$ y- x6 z- B4 p K, A/ e: H
input mcasp_aclkx,
' J/ h0 X* ]# k$ }! S7 \input axr0,3 P9 u/ M( W$ E/ h6 @7 ^" S' `
4 F& @5 S5 e/ a9 A( h
output mcasp_afsr,
/ @7 |; T! U) s0 Moutput mcasp_ahclkr,
/ `4 k" K7 O. s. routput mcasp_aclkr,
9 D$ _' a4 v- s( P2 v3 \* Youtput axr1,' T* X# I3 }; y: v7 Y
assign mcasp_afsr = mcasp_afsx;
+ R o4 X- L$ D& I5 ?4 I- [assign mcasp_aclkr = mcasp_aclkx;
: v! _6 J- s, ~ Lassign mcasp_ahclkr = mcasp_ahclkx;
4 F. V# u$ g/ z, hassign axr1 = axr0;
; b4 X% p2 c( B# Z: a5 R) T3 U* o! \/ |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ T$ N" q0 q$ q& l6 Mstatic void McASPI2SConfigure(void)
4 R1 u. O; p% e4 E1 }/ _4 M{" T' ?0 y5 v; i1 E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 ^, B( `% o% H$ F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ i1 v" c" j, O7 T% B0 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* Q1 A: a4 C, s5 k7 w% e* V2 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! |% X* @( ?/ d9 R- N& I$ c0 \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ X( f; A2 a! _) J5 o2 i. a
MCASP_RX_MODE_DMA);( p% m+ D5 \& {# D7 l" d0 m8 L8 z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& s8 |5 t% C; m$ h0 T5 K r. iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 o* ?+ G, [* S/ iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % N# W8 l- l9 g/ }' E5 x, Z( b: M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 {; z, d: @1 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. {$ J4 `0 G" D% d P3 V! A; [7 Y* eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! a' n* F) } T6 }) PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 `3 `4 H* U1 {% H/ kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' P0 u# V ]$ jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, G; ~# |% \7 v/ Q5 s0x00, 0xFF); /* configure the clock for transmitter */, k+ D ^- ~& h' x! h% d& v8 j& z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 r* {2 B0 j! \ q, L9 l1 O( N/ P+ vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ u( e- a; n0 W& eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 J9 m h' `) [5 x4 X* q* f1 z
0x00, 0xFF);
. a& T b. [: j9 A5 w% z/ g
. `0 Q/ a! ~( ]. v8 Z/* Enable synchronization of RX and TX sections */ 1 ~% ?) I; J- z! Z8 d. x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ S4 i$ |, R( QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% q9 l* E% d9 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- x: v1 a d! C, J! z$ J** Set the serializers, Currently only one serializer is set as P; r9 w, ~- m, Y# N2 p7 G
** transmitter and one serializer as receiver.5 w" Z% u9 b3 U7 a8 R
*/, Y3 w# K. ?' R$ Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- V- K7 a3 O, z, i7 X6 l8 j5 J! `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 u# W" y" H2 {* b** Configure the McASP pins 5 }/ I u3 t: N
** Input - Frame Sync, Clock and Serializer Rx4 P* C6 \+ d& A1 |& D
** Output - Serializer Tx is connected to the input of the codec * g, l- l9 v2 U8 R) u" L# V
*/. ^+ i! `0 m, J4 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ M3 [. w$ S1 u4 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 Q; O# M+ o9 t; h ]4 J$ {0 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- S- W, B T9 v# ^" [& d$ z2 b% d9 d| MCASP_PIN_ACLKX
( y: F B. F6 M8 q3 X8 T0 |- \- ~| MCASP_PIN_AHCLKX q, y6 u0 b4 {/ q2 C6 D# M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) B6 B% x7 j7 T" e5 o) `& ?9 b6 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# {& M$ _; C5 {8 V/ H| MCASP_TX_CLKFAIL
; n- M: l& [: D# n| MCASP_TX_SYNCERROR4 u$ r5 _9 e& i3 \# V R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " s0 q* @: f- a! E7 t# r; @
| MCASP_RX_CLKFAIL
& W3 ]5 ]) W7 Z' W4 U, [| MCASP_RX_SYNCERROR
8 ^2 ~( B; F3 _- V| MCASP_RX_OVERRUN);
$ z* c5 p5 ?$ c. Q} static void I2SDataTxRxActivate(void)
- L; W9 q* p) c7 Y0 R{' k+ A" |- v& n( _" N
/* Start the clocks */$ c1 K5 v- j5 }- B+ Y1 U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. F8 n* R2 I9 T, s( j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; F4 j. i4 ?& g, `' R0 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; F% H+ u2 U" j! OEDMA3_TRIG_MODE_EVENT);+ Q6 }! R9 M) @5 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ H+ }; z% M4 `) M5 H$ M( c: DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) O' I( U' G4 Z# z+ t7 oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- `; u" R! @ y7 a3 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% a' P" I4 {( r! F! a, [3 j/ j9 C/ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* ?" e9 O' R: F u3 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& S5 S: Z5 m2 R. t; S4 G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' Y$ f+ S+ I- a* A9 w8 i}
' ]8 |; c, L- i! y! ?, H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ z& u0 O% }8 Q" x Z- q
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