|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ [; [& N; O# k. H5 }% V$ H' s4 iinput mcasp_ahclkx,
$ C/ T8 b( i' G ]input mcasp_aclkx,
$ H: v. f" O5 q/ g7 Finput axr0,
+ R0 a' o) a" D, I8 J: R6 a! B$ W: O5 ?9 H3 Y
output mcasp_afsr,
! S: m4 r9 e/ o' g4 l: F% j4 |. uoutput mcasp_ahclkr,2 f% P. k; h& B r X
output mcasp_aclkr,
! h7 z& u. V# ?$ w0 f9 coutput axr1,: E& O4 ]" s( R) {
assign mcasp_afsr = mcasp_afsx;1 ^1 L/ C/ \& o
assign mcasp_aclkr = mcasp_aclkx;
" z; C& b9 T! d$ n8 |9 @assign mcasp_ahclkr = mcasp_ahclkx;# L2 {8 \$ t" V$ D. z) A
assign axr1 = axr0;
/ D0 e# P" v% \ r# s# h! r o' t( s' k( M0 C q) _" H D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! k, u) P8 ^% {* U8 p+ n7 j, lstatic void McASPI2SConfigure(void)
- V* y4 d$ |, ?& R2 a' ~3 V7 x4 ~{
8 C3 D' l W( @ RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 G3 l4 w E4 [* u. K; g0 c# A4 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& F3 {9 ^# W6 V: G4 a1 \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- e* n& @5 \5 z" U4 q1 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// R& g: ]% Y+ }+ N0 H X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. o1 f& p6 o( u$ e3 b8 u1 _
MCASP_RX_MODE_DMA);; s# Q' W+ Y2 M+ r. m5 O! W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 l- q/ P5 D) GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ U6 e( z9 J& W% G9 p6 }+ F( [+ p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * [; Y$ F {: z+ S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) N% z3 u7 h! L3 }) I& H) k7 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ J1 h9 H3 H" m% L2 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 n! D; j- |3 x9 [+ e" y0 `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ {8 ~' _' m- J2 [8 N( u3 n3 N/ ~6 F( AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 N; A0 M$ V5 O- d4 j" |1 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 E9 g$ z4 p" Z2 L) A. ?0x00, 0xFF); /* configure the clock for transmitter *// e% h6 ^, Q4 e# u0 s- N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% D- u5 B" I* i0 \1 ~; D9 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 M# p. d* Q+ n# ?3 _6 Q u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' f1 t6 l0 G& _& d( D. f: S+ V; h9 d7 A
0x00, 0xFF);( a& S* R% V) ?& p
. K( }, s0 `' i# k% |/* Enable synchronization of RX and TX sections */ ! f- P+ U- l. G5 B( r$ J9 |/ H* V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ a6 M4 d: j( hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. E6 G5 R, _- g: h- i. ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# p$ `+ i9 S: i3 c
** Set the serializers, Currently only one serializer is set as
9 w; E, j; r! |& P. P* O& M! N9 t' c** transmitter and one serializer as receiver.
$ f% X: R/ h, Q! i |% A% o* s! c1 f; E*/# i. c$ ]) g( J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 `; P7 @1 J. B d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 m/ N/ ~* t2 i** Configure the McASP pins
; \5 s* U8 X/ v% `, Z) c** Input - Frame Sync, Clock and Serializer Rx
4 w" z* g5 M& `2 a2 d" L% W** Output - Serializer Tx is connected to the input of the codec
: m& ^* @0 @4 u( L5 B: O7 m*/1 H* Q4 C: J9 o* h6 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ i2 ]3 J" i9 \# ^9 ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 Z* L+ ~" {# @ ?; O3 u9 ?) RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 ~2 X- p7 a' N# C| MCASP_PIN_ACLKX
2 w+ F4 E' G2 q& }4 b1 G* u: C8 U3 r. @| MCASP_PIN_AHCLKX
3 T6 H# M1 @$ C9 p' u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 f/ m& t# A1 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR {5 n/ |. W. @. S% z! N
| MCASP_TX_CLKFAIL
) }, H0 U) z. {5 |, w8 ^| MCASP_TX_SYNCERROR& L$ Q5 l& v( t C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 e3 `, g, M6 E8 ]
| MCASP_RX_CLKFAIL
y) c: x" g% A| MCASP_RX_SYNCERROR - X7 N5 R9 h: Y/ c
| MCASP_RX_OVERRUN);6 u- d$ j' x6 r8 s8 j% ~
} static void I2SDataTxRxActivate(void)
* ?1 l! r6 p+ M1 [. s. X{! g+ O3 b. X- o4 w# V7 M
/* Start the clocks */
- A( f' r( L& `+ zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) ~0 t! R1 \& ~. @& M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ q/ p9 y% y; L/ W% nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ ^$ w- V S4 lEDMA3_TRIG_MODE_EVENT);3 N( h# O8 x1 f7 C8 I3 z% k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ Y' m$ |# M! N5 QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% C( x2 E. h8 |0 Y) R! U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ M8 S* O P, Y: [; \5 y/ }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 B* ` G2 y( _' c# Q8 g2 T$ ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( m1 v4 ^7 H1 ?, u5 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. W! I/ G1 {* @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 v, W2 O7 a# r2 x/ T# f
} 9 `+ R! r5 b! o0 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " f9 R; f; Z( C/ N) y% }1 u
|