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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# L: {6 c6 E: ^4 q% O
input mcasp_ahclkx,+ v" T, d- r5 [. Y9 ^0 s
input mcasp_aclkx,
# U l1 c8 N0 t/ l/ Sinput axr0,
* k- \' U# Y1 T% `0 N
9 G1 Z: b5 C4 f2 I6 I" c+ Ooutput mcasp_afsr,* M* l9 {9 I, q! D( D
output mcasp_ahclkr,
! R# X% C# n7 B( ^- @output mcasp_aclkr,
* r0 p, b7 K+ `# E& F* I; joutput axr1,
6 Y+ ?9 X% B' M3 }2 D+ c' U assign mcasp_afsr = mcasp_afsx;
/ q& i1 Q6 o) h2 b/ S) m' oassign mcasp_aclkr = mcasp_aclkx;# {" ~' h7 e4 B) x6 Y8 n. y
assign mcasp_ahclkr = mcasp_ahclkx;5 ?% Q% v. |4 I/ J) B! c! y! V% T
assign axr1 = axr0; 8 K4 a a1 M9 S; b
( d/ q: W+ I; t) @& W: o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . h, i" ?. C7 d/ i, M; r+ Z) e
static void McASPI2SConfigure(void)
6 q! D" s4 L( n% [* V, k4 C{
# C" N- ?6 b, r$ U2 gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* y4 y* N" D/ w; a# z: d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ f- @% N* W$ q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 s0 Q4 [7 w3 u+ B4 l2 q; _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' ]7 ~. y1 v; u, e2 O$ u( ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) ]4 t! k. r# \MCASP_RX_MODE_DMA);$ z# c- x0 k( n3 A# w9 v1 F; z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* f; s, }, ], L5 k" u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 u7 ^3 J$ j8 [2 i; HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + q R% O4 t* Y1 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 G7 |7 F. F8 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! c* \, q, v7 H4 s& R2 s6 P/ xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; C. Z& _# c+ E0 Y$ J( Z8 `: B2 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 i* Z1 G" n) q# x5 d. [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 m0 [4 B2 V: @0 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! P; h# T4 c$ H, l9 ]( _0x00, 0xFF); /* configure the clock for transmitter */
) F f! r2 ~8 X3 z! u% wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" A$ k* W3 w" e/ V8 { A+ g5 `9 V G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 [; a: j- K) u# U# _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 B$ v2 \5 ]5 W M' q- |" ?' M1 i: g* R0x00, 0xFF);0 ^1 P0 }0 i0 |; c) K% w- \
5 \- N; p( ?+ h' J7 \' y- [; a/* Enable synchronization of RX and TX sections */ + C2 y. J9 F% L; E- r6 O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# M3 H e6 ]4 s& w0 d) l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! |0 z) g" f& s2 x4 O& E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& f; j/ r: O# w5 J* H/ U** Set the serializers, Currently only one serializer is set as. |$ R; c3 l* W5 U& q
** transmitter and one serializer as receiver.
2 c' M7 E, o. M: F1 D*/4 D- K" p& c1 j7 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! c1 x; s9 T( B, K: y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% P+ p" ?& ^( h3 p/ }
** Configure the McASP pins 7 W" y8 U. q0 g+ e$ C7 q2 c
** Input - Frame Sync, Clock and Serializer Rx) I7 s! H/ J' [) V" b3 b
** Output - Serializer Tx is connected to the input of the codec
) q% x R0 y* x8 Q*/! M) h) f) R1 |& `/ O' n8 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- D( v5 t& r3 H5 z2 U; Z( @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 t2 I( _" c. o) h& yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; U5 A$ l S: {# s% A| MCASP_PIN_ACLKX. ]6 j5 j2 T v- \
| MCASP_PIN_AHCLKX
3 J) l; b# M" || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' J/ R7 A0 z& {0 k+ X) s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 C2 Z' o; C) {. |' Q5 S| MCASP_TX_CLKFAIL ! M3 b; {/ z; l" O3 |# p
| MCASP_TX_SYNCERROR
3 [7 e0 U! P& T1 N0 C9 \! H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 l; d/ X ]/ a( i0 l2 C| MCASP_RX_CLKFAIL& T; ~& c4 J8 v8 T' ?
| MCASP_RX_SYNCERROR
8 a& P$ ]- j/ Y# o3 a3 F+ h; C: {( m| MCASP_RX_OVERRUN); Q& ^- V4 o7 j& R
} static void I2SDataTxRxActivate(void)/ |) b& }; X3 ^9 v
{2 [9 C. P+ ]% W: S: z
/* Start the clocks */
) I! H4 ]1 Y H7 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ S5 q( f' t% s5 J5 H* UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 C. B0 j3 f# j6 M) T* C+ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' K2 b* _7 b6 `* ~( `6 {
EDMA3_TRIG_MODE_EVENT);; V$ h. y _: N o4 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! a% f) X& |7 V# H% c1 A9 ~+ hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* s! I% _$ y; [# H/ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ }/ E; S/ `5 L: O/ D5 {- {) Y* cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 p& V0 {2 k* _& X) b3 i# N, Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% w9 l. L( ~8 i' ?0 Y/ [1 O) hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 }7 o) b1 N8 Z% ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' J; {$ L9 u7 x+ b/ d+ W# C$ y}
, }4 U, Q3 A6 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : n3 e8 I9 R' c* x2 e( O/ h
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