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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 W; m! i1 [7 f% i
input mcasp_ahclkx,) b O$ W9 l. f$ }* ], Y; f3 H5 l
input mcasp_aclkx,
' d* l' A1 U- g& |8 ]' E0 _. J' Kinput axr0,$ e ~# F0 C* Q* w! { Z6 K* {) }
0 W0 |1 S" r+ F L. a" V
output mcasp_afsr,
& ]5 q" m1 E4 A9 O) e) w& moutput mcasp_ahclkr,
& M& z8 B, ^, T7 o. `9 r4 d- zoutput mcasp_aclkr,
$ ?( V+ x3 n- v0 N- W5 ]+ G6 a! Toutput axr1,
2 r, Y% K( b- e" O" z assign mcasp_afsr = mcasp_afsx;- H% k& n4 u: l q- h7 z
assign mcasp_aclkr = mcasp_aclkx;
s* [) }: y# \* V. u9 J3 w$ A+ iassign mcasp_ahclkr = mcasp_ahclkx;) ]: w7 L6 }+ S' i2 {1 s
assign axr1 = axr0;
% {# i) r% f% d% b; t- @
( O1 f* z9 m. U; V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" b& ?# @2 Z9 C. [static void McASPI2SConfigure(void)
. T m, j( v4 R G6 d{
: R% |# `! w t$ V9 Z( oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 L2 y! \% I8 ~6 k) v. E6 c% l, I! t. aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ H, P4 F& M5 ?% P F: i) U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) ?6 R, T( l T( pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ A) V0 z% [) v$ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 S6 H" n; \/ mMCASP_RX_MODE_DMA);$ U4 h+ V3 V+ m( x. \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* H4 V: l6 ]* t9 s# I% a' G; ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 f2 v, Z+ s- H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - B3 Y% e" u- F! [; X# k" b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 L; |+ ^% }9 [: I# gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, Y* L* `! v% I0 `% m, v' l6 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 I* z( p/ m6 E" ?4 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, K0 h$ h; G1 m. }! D+ ?8 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 ]' e, Q* \: Z, [9 r' MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; Y. O' M' D; Q( N5 u8 f; d. z( }0x00, 0xFF); /* configure the clock for transmitter */ {9 K) J! u% v0 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 a# m) p; c" G3 Y2 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 b1 G) l' Z1 P' _0 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 k$ s" ?5 m4 w
0x00, 0xFF);
' N/ G4 g) F8 _- l8 u6 g7 v
; x& Z: s( ^4 l+ w% b2 B/* Enable synchronization of RX and TX sections */
) C' Q. g! {$ `7 u; O+ ?& p7 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 y/ }3 I1 v& R. S! \* YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ H9 w+ ^3 X O2 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# z( }# }; \: Z** Set the serializers, Currently only one serializer is set as1 k P3 O& d1 Y" ]) ~0 u. y b
** transmitter and one serializer as receiver.3 m7 ~6 c. Z# d+ {/ J- g
*/; M ?! g6 j/ G% J; K! w' U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% t$ {3 e6 c6 B% @) wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 _- x( k# } ]
** Configure the McASP pins
4 ^" ~9 u s' s0 P/ `** Input - Frame Sync, Clock and Serializer Rx
3 j* ?$ V8 c% f! n! [** Output - Serializer Tx is connected to the input of the codec
9 f# N0 f+ _) P) K9 o( m; B# Z. P*/& w, M/ V: ` j3 `9 b1 ~ B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- @3 `% n( U7 |, V; g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 t/ L& K8 v, j) F0 n1 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 {# r9 F& Z- P5 d9 F! ~2 B& a) }$ T$ H| MCASP_PIN_ACLKX
% H- X$ ~' {+ W$ E4 i* D| MCASP_PIN_AHCLKX$ m( s/ F9 [; W3 m3 z3 {% e2 L' H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: B! K$ k8 W4 F I ^2 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * k" ~6 n$ b' |: x/ M
| MCASP_TX_CLKFAIL
+ s3 c/ u/ V x2 E% || MCASP_TX_SYNCERROR
% r$ f7 H7 {. i) q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: j# t2 V) y. A, ~| MCASP_RX_CLKFAIL
0 m+ u+ E+ P2 f1 s( k7 c; s| MCASP_RX_SYNCERROR ; m' `* d8 D8 M! D
| MCASP_RX_OVERRUN);( V2 `/ S% ~9 Z' z \
} static void I2SDataTxRxActivate(void)
& J9 F( U& z' d8 a{
! z2 B+ x/ H9 N" _) Q8 d9 t* K/* Start the clocks */
4 ^* `! N+ Z H& c$ kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- ?9 y. K; ~8 j7 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; ]3 A' j/ W p4 S- O" a0 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- N2 y2 k- h0 b$ T: ]) T q( _) Q8 r
EDMA3_TRIG_MODE_EVENT);( q4 }+ ]7 c/ e7 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" h( I4 w4 q6 V, hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" i9 V6 D$ ~2 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- K; M+ [# N* Q6 \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, x3 O0 N# i3 N/ E- ], P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& i6 d3 v* _; _$ y" {7 CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ ^+ E! C# V$ @ }5 @ b5 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, t0 H% Z H h- Y! T" B}
: M; w8 e* T$ ~7 R- D/ L% J3 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 r# d5 K. F% Q* p" s; ]" U
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