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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( G6 r$ N- F* U4 T2 H7 \1 pinput mcasp_ahclkx,' q& ^: B; \ |7 p% v6 [/ s1 k6 Y; x
input mcasp_aclkx,4 c% U$ H7 z( B1 T5 S+ f6 |
input axr0,
. |& u6 O! Y1 d
9 c4 J) Z' J8 K* k/ ^0 foutput mcasp_afsr,
1 J/ ?4 E8 H; h9 ?5 i* youtput mcasp_ahclkr,
$ Z' W! @/ e9 X' Q' Z# ooutput mcasp_aclkr,$ ]( r/ x A$ S8 g
output axr1,
" N3 |; X# z( x0 w1 J' y: F assign mcasp_afsr = mcasp_afsx;
5 V) m0 l O) }5 nassign mcasp_aclkr = mcasp_aclkx;1 m2 L7 I2 F8 X; B
assign mcasp_ahclkr = mcasp_ahclkx;
6 d% y- P8 b' d8 A1 Jassign axr1 = axr0;
+ E1 R7 @& Z1 v8 {( D4 H/ ~8 q9 X
# i& a8 R, c: [) i C% ~4 J5 I4 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 P& E9 s) N# S5 a( l
static void McASPI2SConfigure(void)
* G" Z6 ?' u0 W& F0 n/ W/ u{7 b8 X/ L- _' G" c6 T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 g N! _% V' IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ }5 R# K$ ]: k JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ M8 I1 B& z( n# s" S5 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) P8 P* f4 O# k! {. J3 `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* `0 N! Q! E* |! x4 F
MCASP_RX_MODE_DMA);
" B- I; V* R7 x1 g6 Z" R: rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 G% w0 w( C" A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" {( J* _4 H2 J7 [4 `8 v! |& x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; u7 Z c0 P& r5 b& ?. T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: Y7 i9 T2 w* @ Y5 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : J) Q' g5 D$ q8 O3 D/ b% [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// S- Q! M, f4 s; A; x0 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& }7 y1 | Q! n' w) U; e9 T* r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 k% [* c" j, W/ {6 M. {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ w$ H8 p6 A5 d0 d6 M0x00, 0xFF); /* configure the clock for transmitter */# a; X) f; u+ W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- O7 F" _/ V8 P. S1 [9 f( `" C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 |- w& g2 V$ a3 q3 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, t' @4 S: m( |0 ^0x00, 0xFF);% {5 k5 E; d5 l9 n( |2 J
) L+ e) X) j: Y! v7 e" Z3 H: b5 W
/* Enable synchronization of RX and TX sections */ ( D9 q1 L" Q2 `+ k% [; G( B2 L5 S; a2 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" h% d; a. s1 k @; z* F* `: UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( o+ J) \3 E+ ~( s/ B3 j% NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: f( [5 b+ m7 W8 \** Set the serializers, Currently only one serializer is set as
/ p" f- L' [: X- m) B [** transmitter and one serializer as receiver.' ^% L( ? U. E4 e; i
*/
3 H- Z; L! z4 m8 |) ~: H8 r3 G/ uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Y3 T9 w4 h* N2 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* J' q x, n5 E0 a
** Configure the McASP pins ) F8 H& I7 R. N4 k9 h X, h, E
** Input - Frame Sync, Clock and Serializer Rx$ \! T) ~: t8 B8 r6 M8 l+ s1 A
** Output - Serializer Tx is connected to the input of the codec
7 h/ c5 b) A2 e' ~$ G& O4 `* ~4 K*/
9 _9 N* Q6 t$ _3 c4 b( |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) X8 V9 E+ E7 {" b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 G/ D; `9 [. v" e4 x% \; p3 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 D2 U) ?- `, @& ?% z8 v9 y6 ]| MCASP_PIN_ACLKX
+ t# {8 f3 m4 r2 r' d| MCASP_PIN_AHCLKX
9 x& _6 R R9 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ K3 k8 ~$ ?. N7 g$ ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . }/ h4 V& @" K' Z
| MCASP_TX_CLKFAIL . ~6 v5 H' |2 l- j x
| MCASP_TX_SYNCERROR: e; |1 M z ^& J* u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ B, \! [/ D& q" b| MCASP_RX_CLKFAIL5 S7 v n/ r# X
| MCASP_RX_SYNCERROR
: {! p' ?. l' a0 L| MCASP_RX_OVERRUN);
* B! I, L2 z# A9 m1 _4 a} static void I2SDataTxRxActivate(void)
- G- v8 a% i; I' c0 X/ ?9 L{7 C, L1 @8 } R
/* Start the clocks */% J. w7 |/ \& v6 A6 O0 ]/ s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) t. t! x) M; y! {2 l/ nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 g/ R6 [5 m4 I3 s8 k; _; _) E( w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ ]3 }9 ]! w# h9 E- G8 l
EDMA3_TRIG_MODE_EVENT);8 b( H, K: U% [$ k/ B$ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" v- |7 I2 i8 W! X. |( _3 g0 _6 ?3 c5 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 h5 Y7 H, |% OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ S- e) c Z6 z R# r$ @- K5 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ Q3 r8 H0 T0 ~) B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& F" K2 z6 `% H6 v" z5 U r# _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- U. ~, {3 d& N/ K; E$ c& S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% k# N% \$ {$ K) b! A# Z}
c/ e; c: B! _/ b. ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' F* Q" {2 A8 m% H# s1 {: Z
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