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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ S a" B, l4 ^% I3 Uinput mcasp_ahclkx,
8 v- j; f) q7 j: c( X5 tinput mcasp_aclkx,
9 a m/ {+ O5 M" Finput axr0,2 v/ Y5 B3 `8 P7 T
$ _* C* [! `/ soutput mcasp_afsr,
9 i" I+ F& k. m- @, t- G6 Uoutput mcasp_ahclkr,( A- x+ X! f4 G
output mcasp_aclkr,
) T; c! w2 m6 Ioutput axr1,3 n2 ~# N9 y/ L6 v! n
assign mcasp_afsr = mcasp_afsx;% i' @" g- g" ]8 n! E8 G$ ^
assign mcasp_aclkr = mcasp_aclkx;( }9 D$ H* s9 z0 K
assign mcasp_ahclkr = mcasp_ahclkx;3 \6 k, r3 D% v3 C1 W7 _
assign axr1 = axr0; # \- w# \1 _7 X
& V9 O7 [( v3 `* d& v0 a: H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 p" I' g% O& e- P
static void McASPI2SConfigure(void) @( X3 V+ A# R1 C$ j
{
, ~2 }' m. S% s- a2 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ v% p/ y/ s( d% ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 ?6 a* {! p% }( bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- R8 Q0 R; l: _ ?4 v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* y9 a0 i& D& cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, {% [6 d4 @8 k% h9 U# s: |# C, q& ~MCASP_RX_MODE_DMA);
1 e+ d/ r% Z& u% m& H3 NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 U% T7 S! l! W" T/ V2 ^& qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 K) u8 Z0 b; X" E" ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + Z6 A3 [; z& Z0 B: N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: }' k% T9 \+ Z8 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 z% [" M+ U% K# a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) Q5 [/ {* u" T8 S0 c) w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ ^- K7 [2 ^" u& v! t. cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : d6 `1 g# V- k* g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," @5 V' i$ o- b! i2 t; b
0x00, 0xFF); /* configure the clock for transmitter */. ^4 X1 d9 H0 [% ]' t5 `6 g" w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 R) \8 o; e, T6 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* V$ p9 K, @$ L RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 S) v5 Z7 f! R2 S8 G& R2 `
0x00, 0xFF);
9 t8 _, z) h2 | k. H% F e% u" T: T6 ?7 L- G
/* Enable synchronization of RX and TX sections */ . D) i2 V+ n4 L) b) H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" E" H: [1 R6 \" \: w; k$ ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ W( n4 L$ h- D. ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 B0 l# J8 P4 ^( p6 z% K1 [** Set the serializers, Currently only one serializer is set as
5 f8 j J1 ]' W" i3 b% V7 P** transmitter and one serializer as receiver.: w- ?7 D! j* t4 z4 y6 Y8 I* i
*/
0 W) e0 W) ]" f+ a% B" b8 @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 h4 C3 N3 c4 N4 G2 Y/ @6 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ ^4 c- |* E$ v6 p, J
** Configure the McASP pins
0 ?! W2 \7 B2 [6 n) P: m" F** Input - Frame Sync, Clock and Serializer Rx
+ |+ o& T, [( b9 o** Output - Serializer Tx is connected to the input of the codec
! D/ a! r+ z4 _& _2 I*/
9 J& V/ d; t* \4 R! d8 }. k* qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 o) y) Y2 S2 T( c: IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' Y, ]/ H# ~* ^% w# q1 V. F6 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; f, v c* @( B# o* p9 u4 @| MCASP_PIN_ACLKX2 C) L. `& w2 T* @
| MCASP_PIN_AHCLKX7 _$ n3 u3 P2 R# ~+ ~% W2 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 b/ N( }) U9 i3 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 D; N, I O, d. a$ v9 ~| MCASP_TX_CLKFAIL
& C) ~( s0 k' a1 ]7 E8 Q, o9 k+ m% |; U| MCASP_TX_SYNCERROR' }9 ?0 T1 v+ Y- p; i. p' y: L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR g& s6 t5 y8 W6 T* w
| MCASP_RX_CLKFAIL
* W5 u" \2 C* W| MCASP_RX_SYNCERROR f/ ?& t9 ^! g$ p( m
| MCASP_RX_OVERRUN);
. S# d B8 j* s) n: @: K} static void I2SDataTxRxActivate(void)
' h/ H& n* ?. m( H9 R9 Y{
$ |" N5 X# g' |+ q* C6 S$ |/* Start the clocks */' i( L6 g# `* O, J, i X! z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 E3 \/ r( F# N0 \5 b" e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* D4 B- O3 V) BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 @1 i" s1 y4 q* q5 Z- `
EDMA3_TRIG_MODE_EVENT);
4 ?0 L9 j# k/ \3 B- l: eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ B$ |$ u( z. `" G/ s. Y: uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: y- _% |* A0 n& {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 [1 H3 R( x5 f# g+ o9 p# y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// K% M" w# |/ R' V5 Q3 T& ?# M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. g8 }* z! {. `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* M# A7 H/ y: Y" E# |2 u8 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! f, r/ U7 l5 l4 _% |
}
% F( o4 o" f n- M" M; u, T' I d. p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
( [9 S0 G# m' U Q- n7 ` |