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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 Y% ?6 W' h; `$ Y/ k2 l& ?4 b
input mcasp_ahclkx,
) Y& k9 z; c& C' A9 y8 A; Kinput mcasp_aclkx,1 N. E6 y% R: p; C
input axr0,* ]# O9 @1 \: V! B! H
8 E8 |2 Y$ s1 M, O7 L: y8 Ioutput mcasp_afsr,
$ M; e" }9 B5 S0 y" {/ }output mcasp_ahclkr,
5 \3 [3 S$ ]3 t' ioutput mcasp_aclkr,
) g& \# K% g5 L+ _2 Toutput axr1,
l3 w4 i, q( |1 F! ^' z assign mcasp_afsr = mcasp_afsx;# j0 |7 E: C! W- r
assign mcasp_aclkr = mcasp_aclkx;+ }0 \; i9 y1 K) F$ \7 U W5 }' d
assign mcasp_ahclkr = mcasp_ahclkx;
# u3 q7 z& U1 r$ Zassign axr1 = axr0; " x5 G+ i- Z6 k" Z4 i
' T) S+ F# o/ m* j* g8 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. E& b3 M6 A! @4 g" _static void McASPI2SConfigure(void)) q& r+ q1 B C0 w; G, M
{9 b- \* Q9 f: r0 m( W; j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 P& T# j$ `! g. i; L" j: o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 f) E: f0 g# H. b% d6 m2 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* D" N2 S8 i2 z {! i% }0 h' rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# {: j O' W+ t8 G0 gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% y% t+ Q& b$ R. mMCASP_RX_MODE_DMA);
) H4 h, W* x7 C! @# Y" S$ d' ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. x0 c3 p* c; j7 VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 [8 V/ j2 K9 R8 E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; U! M ]! l+ Q8 C5 V* yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, `1 T* B0 M, q! v8 A( I( \" j2 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 S" y; N+ W1 Z% XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ k' B1 G1 k8 R' O% [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, |2 }7 N/ A: l0 x) f- j( V U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : U% ]. \+ i4 P4 Y8 h& B7 M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," E/ b6 h: D$ t! I2 e
0x00, 0xFF); /* configure the clock for transmitter */
0 Q' c4 g0 `* s. R* U9 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" m5 a i* N* R3 E& Y1 W' j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ I- }5 i0 Z% _$ \8 }' f3 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," G2 K8 u$ I0 K) P# T! `5 b
0x00, 0xFF);0 w8 M7 a) S8 b. x s
% a5 H; m7 q3 h0 s8 V
/* Enable synchronization of RX and TX sections */
' E9 J, A, i# H, F( vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 B- w3 J. m' H8 |* lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% V; y, g9 `( { A1 K% `2 t3 y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ h7 w m/ u& L& Q; n4 c
** Set the serializers, Currently only one serializer is set as: X) \# K$ R, ]( b2 }, N: x
** transmitter and one serializer as receiver.6 X) K' F: ?6 P0 ]* G0 }$ U/ v
*/# ]5 k. O! f3 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 T' |, n7 @0 F1 t& ~6 e- ]" B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 i2 z/ C, x) w
** Configure the McASP pins ) v c! {, h0 z& ]( `" h* z( k
** Input - Frame Sync, Clock and Serializer Rx
; d* T* n" U1 C2 Z& `- ^" j** Output - Serializer Tx is connected to the input of the codec + o% S1 V/ c6 D4 @* I5 g
*/5 q) D; f4 c) P+ P& g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, k2 |& a, i2 X. j( lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ O4 c) ~" S9 g; f! DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 ^# G3 ^- P: K c$ u% h8 |
| MCASP_PIN_ACLKX$ v& U+ U- ]- s. T
| MCASP_PIN_AHCLKX K' f2 e- c6 d4 m) L& \# a6 ]! x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 {" h& U( N( u8 y. AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. y7 z4 H& s. p| MCASP_TX_CLKFAIL
) K, O$ G H+ A. a* O| MCASP_TX_SYNCERROR
1 @3 Q C6 u. W9 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% @5 `1 }$ I+ i7 Y| MCASP_RX_CLKFAIL% |3 ]: p5 ]( [+ k5 p" U& e1 k
| MCASP_RX_SYNCERROR 0 a# x% n+ P& ~6 _! g4 ]
| MCASP_RX_OVERRUN);
5 N; }, y D8 Q} static void I2SDataTxRxActivate(void)
" ~* E3 f1 ?) U6 A( R9 j/ J2 X k{* F( Z/ {$ b6 J6 W& w! {" |
/* Start the clocks */
4 O& I( X" }1 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 }+ \: k+ t/ i4 `# c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ Z' `: }8 ^3 J! N) @, O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ ?, _# i3 V3 s% l4 |
EDMA3_TRIG_MODE_EVENT);
& X: k: f2 B; I8 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ^! N! M k: V6 t( t1 K7 k9 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 I4 s. \1 W2 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, y. ^5 z' ]$ X, g/ }; DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" ] f5 S! m0 G5 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( q8 Q* L4 @. f8 T1 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- j/ Q6 R8 L. a2 H; }* c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. V, D% }' j% A" P" ^* x
}
+ w1 j0 x; E! j/ `6 m- U3 B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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