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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 A# r) v1 N/ M' |& |2 ^9 Oinput mcasp_ahclkx,
' Y9 E9 d) J6 Kinput mcasp_aclkx,. u" h" C5 J( \# S# Z7 E
input axr0,0 S8 A" _# _5 c: i) F2 _ R
! d9 u7 S r7 noutput mcasp_afsr,* c% ~' \7 g, K) J2 l7 T& m6 W) p
output mcasp_ahclkr,
; K( Z9 @! { G) p2 Soutput mcasp_aclkr,7 Z" @+ J! S3 j2 f
output axr1,
) h$ C' d- P1 M- s2 ~ assign mcasp_afsr = mcasp_afsx;/ Z5 T0 J0 y' r9 |4 l: J
assign mcasp_aclkr = mcasp_aclkx;
" O* i1 Q F8 t% ]assign mcasp_ahclkr = mcasp_ahclkx;
4 z- G& W# {3 _3 {assign axr1 = axr0; + s; @0 q+ I7 l2 n% i9 ^/ \4 ?
7 C1 J: r% N- m. @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 X( e# o/ m; O- Sstatic void McASPI2SConfigure(void)/ _, H' z Q% o& c
{
8 t& k1 F' E. i" M1 t/ Z- B) V& a4 W+ vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ _, G+ c$ k9 g4 d8 P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! A/ e; R3 W) x( L5 x( ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 b& R) _7 b0 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: F/ _9 D0 g/ G" S; jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ _$ ^# L4 T+ D1 O( i! P; J
MCASP_RX_MODE_DMA);" _2 X9 H, ^: X9 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ b* P# i& p& q; C0 Y) c2 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 x2 R/ ^8 x( p/ R/ z+ o! j) r4 r1 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: [( V+ |' t3 ^6 {* W- a& t# HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* E- S- z% X: W4 e) o n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 r0 V) j1 P8 d |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# z& J& u- N0 [, Y2 n2 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" {# @1 J8 \0 |5 ]9 ^2 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ L/ Y4 m: c2 t0 { zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 K/ q* b0 ^$ ^0x00, 0xFF); /* configure the clock for transmitter */- m! s7 @" S* C6 S9 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 D8 z+ N2 F9 a8 M5 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % q( P# m' V) ]4 Q( m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. |# \) O- S4 n1 I" S/ F4 T+ k. m0x00, 0xFF);* d) i [8 [ ?( I
1 g x" K0 B! {# e/* Enable synchronization of RX and TX sections */
2 c. Q1 z( v& J) p9 C4 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 Y# i* g5 e% p4 i% b; XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ i* ^& {" {8 N* H7 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 k9 P5 {$ S1 _- w
** Set the serializers, Currently only one serializer is set as
; ?( }7 N k. s5 g* k ^0 q- O** transmitter and one serializer as receiver.
0 X$ c3 A; V( i5 h*/3 Q3 y* C+ s3 u F2 K# _: H! T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% t1 I6 y+ j" q6 N8 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 n( [. P7 x6 L$ U
** Configure the McASP pins ' X9 v, z+ e: H6 f9 G: A) O5 ?& S
** Input - Frame Sync, Clock and Serializer Rx
K: k1 }4 K: s; m$ p: g** Output - Serializer Tx is connected to the input of the codec
+ n4 B: t2 O2 f2 Z2 M*/" d O) j0 X/ M; ]* n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" c5 {% c9 D0 G' a) l9 z. o8 Q) lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 [, ?5 ?. S- a, Z2 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 ?% ?5 q# U" ]7 e' X
| MCASP_PIN_ACLKX2 J. p1 u1 t" C0 L
| MCASP_PIN_AHCLKX
0 ^; w, `7 E5 ?, A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 b7 V; k8 G! j' \& x* D. AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR `$ J% c, ~) R4 ~4 j! P& ?
| MCASP_TX_CLKFAIL ' U/ A5 Y# Y. @; k& h
| MCASP_TX_SYNCERROR
% B3 F- n/ l- l& M. j+ Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 {) x1 F9 n" x* A
| MCASP_RX_CLKFAIL/ f# F% E: A1 X* r6 Z9 F
| MCASP_RX_SYNCERROR
$ u& i( @. z( Q$ f3 U: ?1 K- x| MCASP_RX_OVERRUN);8 Q2 |& n7 l7 u% c2 I7 y' J3 V
} static void I2SDataTxRxActivate(void)
8 _* G- _; M" T3 U5 L; X$ z{9 T2 {9 \" q$ q2 ]+ d
/* Start the clocks */
6 O% W' S2 b O) CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
Y! W% c5 ]7 F9 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% E( h2 f' _) j) i9 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* o& [; x% t# ^8 U" x. a7 H
EDMA3_TRIG_MODE_EVENT);
% N" b0 t o( G( D* ~# KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; _- x: H( Y, r% J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! X: K; [3 z) QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ?, O# a! s6 P( u9 N# j' x/ z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ Q; }2 m" ^6 f" W/ O8 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- f+ |! p8 J! {3 e) QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 R$ Y" i! U' }$ A N7 d( m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 W& q, \1 \, V5 D& ]
}
& _$ P- x! f* J, K$ a; t! U# m$ o* r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & W7 j$ b0 S7 j# F% w$ K8 l" R
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