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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 @" q. `) m/ n* y
input mcasp_ahclkx,
6 D, ^7 Y, N7 g9 M4 L3 ~: a& \- Uinput mcasp_aclkx,: }% s& l) [, C. b, H1 d+ A) ?" @% p
input axr0,
. P6 J. l# a: M" w0 v2 e; Z" t8 }5 r4 X8 Z- C: c8 V9 E; i1 ~; x
output mcasp_afsr,
9 }- H* N" w3 t4 R4 K* p. eoutput mcasp_ahclkr,
: \ D) B% Z& d' _0 p# ]; ]* w( routput mcasp_aclkr,
1 _9 O% J2 I# Y3 h7 P! ^, P" loutput axr1,
5 s r5 Z; t3 b. j9 d! N! h: x assign mcasp_afsr = mcasp_afsx;4 C9 |% H+ m; o5 r5 \; t- |, R
assign mcasp_aclkr = mcasp_aclkx;1 R" T& n9 |, i1 G$ E4 b
assign mcasp_ahclkr = mcasp_ahclkx;
+ f+ }2 v9 R7 s& V, G' X7 uassign axr1 = axr0; 5 I7 j) S+ J( F% l$ Y2 L2 P
* t- z& A! R" {' p" `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 s2 i6 D, ]. ]+ T K* n x: o6 ^static void McASPI2SConfigure(void); l+ `9 V6 f5 B9 ?: O
{
3 N+ s1 E. Y" a/ Y! }McASPRxReset(SOC_MCASP_0_CTRL_REGS);" }7 X4 ?. J4 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ q: }# U; C \' y: P5 r7 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Y6 O% N- U/ W+ ^8 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% |* Q2 }1 D7 J. c" e" p( [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 u4 l8 n) x% c% A X' I5 E8 f6 p
MCASP_RX_MODE_DMA);
1 \$ Y1 Z. V* SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ L+ W5 _! T9 O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 q2 P Q/ m0 X2 \5 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: b7 [! j3 o5 P9 ~% S* f; V1 iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. }2 B$ | @+ `9 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 c9 x$ R! l9 A) q* L8 U8 f' [/ a" s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" o4 K% T- h- M& V1 q/ V& d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. K7 }1 ?7 L" o1 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. l/ n% x# a. s- ~2 f, V; w' rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 I# V2 O+ c* \) G2 v. a0 x0x00, 0xFF); /* configure the clock for transmitter */
! m$ i$ P) r, \, t1 {' u4 S* @& r& EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, C5 M" T4 p) b; UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 J/ O9 d! j2 P0 h7 s Z3 W+ p$ h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 T+ @2 w( e, l/ t5 ]
0x00, 0xFF);
]! y9 b) R5 u4 v& ?5 }( q
3 Y4 k9 Q% ?2 O- Y; }2 S- z0 E' M/* Enable synchronization of RX and TX sections */
3 j* S4 K$ c( R5 R+ `- eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 s! p- Y6 Y: {5 n; b, L+ gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ h) n1 Q9 d: w( L6 P0 c. f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! W3 Y A; q, q7 P) P. l4 F** Set the serializers, Currently only one serializer is set as
& B) O* R* L# k- l" v** transmitter and one serializer as receiver.3 e0 r0 Z# ^; T. Z5 ?' C) O0 K* K' z
*/
1 I2 S7 ]9 X- |/ n) @ g- V" Y2 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- i. R5 J+ E& g+ y& \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& v7 `9 {* U8 X* ^+ V- ^** Configure the McASP pins # F6 n3 [2 C# A
** Input - Frame Sync, Clock and Serializer Rx8 k. R3 \# M3 K/ N' |( z" M! j
** Output - Serializer Tx is connected to the input of the codec
3 v5 `) I6 \+ w" o: e. V6 a; c/ C*/
: @* Z+ Q+ s' a5 M3 n" [4 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 l# n D6 H+ {9 S( H; ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; @! D: a# G' r( w" jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 _3 p3 h! j! k c| MCASP_PIN_ACLKX, I' B( y& S" f
| MCASP_PIN_AHCLKX0 w/ c( r# t3 S: p$ X. n! g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# h; v. @+ K: U' \0 s' Q1 X9 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 ]6 Q5 M/ ~& }4 L- A+ G5 v
| MCASP_TX_CLKFAIL - @/ t6 ^6 a8 x0 i
| MCASP_TX_SYNCERROR
+ E! ?# L# {- d( P) h6 W$ Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 O2 @) l* F8 ]- G) B! s/ l| MCASP_RX_CLKFAIL
/ Z4 T: v# u9 ~6 h4 {| MCASP_RX_SYNCERROR
% m) c1 U( H: q" z| MCASP_RX_OVERRUN);
4 D- w Z: o( u% k" X# x} static void I2SDataTxRxActivate(void)' n# `9 J s" g: e2 n% Y0 K6 [0 O
{
3 k# d8 R) o* S ?. ~( R/* Start the clocks */
; `6 O) f& [/ M% y3 g8 i- bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( ]5 t: v$ ]7 G Q' c, L- h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! n. p- y. h2 Z3 K* I0 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# V* v& |0 m y2 _& xEDMA3_TRIG_MODE_EVENT);5 |9 S. P% m7 [2 b! @1 t: L% @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 g; \% p3 U& H/ N+ R! S* nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 V/ ^9 S0 g: [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. t: ~) S' t; \# y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 T7 |4 q: p5 h% q5 a" P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: ]' P# H: o* M. yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) r" \, Y& B' U, E! k' \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* P( ~& d9 b" v1 P} $ E7 o0 f# d) s: ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 M: Y. F, K- p6 n
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