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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 C! N" a) b! z( Linput mcasp_ahclkx,
# Y# N6 o4 J* F; Zinput mcasp_aclkx,
) R, ^+ X5 K# p+ r- g/ }2 Rinput axr0,
$ u+ f/ N! g. f o. F. q" I1 y: P5 H6 {5 L2 j8 ]# E2 v
output mcasp_afsr,
' {) w: P7 X" J1 m) M+ Loutput mcasp_ahclkr,
7 H4 f- ^' g2 Q& g& ]output mcasp_aclkr,
$ Z1 O2 o( @4 g; D7 ^/ Poutput axr1,
) f, Q2 R- Y- A: T0 U. } assign mcasp_afsr = mcasp_afsx;
' h7 t0 r# g% q6 l4 A# rassign mcasp_aclkr = mcasp_aclkx;
6 X: {. i: B. E+ I% zassign mcasp_ahclkr = mcasp_ahclkx;
% Y. x) r. x6 Z- Tassign axr1 = axr0;
% k. c m& l. ~0 s2 E- f
, F" ~! d7 e1 V" u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* D8 a. z. F: X+ ]4 sstatic void McASPI2SConfigure(void)
, N- ?) b" v' R- }' [' W1 q0 K. g{
& Q8 O1 Q; X: T- DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- K9 @/ {+ D, u) F/ J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, ^: M$ ~; O# D( u0 u! |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 g0 f6 y: g2 p; \3 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 v2 e4 r% L l! U; D* _8 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 }, A! N# @4 F- t* jMCASP_RX_MODE_DMA);
. v3 N3 f% T* h/ P0 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! c; ]0 K0 `8 v6 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, ^5 I$ M+ v" k" t$ ?$ v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & R; J& h- I7 ^4 o. q7 |. x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ `! {( r* \5 n' E. c% S5 W* V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: U8 F$ z! b9 x5 _% dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: S& } ]+ n2 z( rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" i: S9 P. V8 L1 {3 C% B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, A5 q' e6 @+ c! A$ E) L4 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, Y3 T* E% o( r% r- p2 R0x00, 0xFF); /* configure the clock for transmitter */' H7 g7 _" o" |$ [( w" l) i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* _3 k* }$ n7 j8 j- c) r( E O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" t2 [. T; d, {0 k; q8 \$ bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. L* o( f: c1 h4 j# U+ m0x00, 0xFF);
, }6 I: }- J/ `& x7 v
6 P8 p" m, {/ A) G/* Enable synchronization of RX and TX sections */ 1 n9 t7 r$ b3 R7 d/ N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) U6 }: a) G$ jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 t# d% X8 }6 n( d( T( |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ n3 v0 C7 u0 o0 I4 l {** Set the serializers, Currently only one serializer is set as
9 O @$ z6 z( y8 w4 j: d3 i) ]** transmitter and one serializer as receiver., k& a8 v: u6 }3 I* h6 H' {! W& H
*// b Y+ a& V; m& h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; y& y4 g+ {) x% D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) l' v& B2 c# o8 ?$ {
** Configure the McASP pins
. g& u7 q/ S$ R, j2 m2 u" z' u5 m** Input - Frame Sync, Clock and Serializer Rx6 S) ?. h7 J4 d% v
** Output - Serializer Tx is connected to the input of the codec " ~% w/ j/ q& V; B/ F# `2 Y
*/
& ^5 O. j5 w) J6 R1 |# aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 c% c: ]- P0 b- U7 B6 h6 a2 K( tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ K1 k" F6 {2 ?" Z- x. f! CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) \% v- {5 j. l9 c- T1 ]. M| MCASP_PIN_ACLKX: I! `4 A, s! C3 o" ?7 v8 Y
| MCASP_PIN_AHCLKX
; R$ _% D5 r1 j4 g8 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 A. J8 G" v1 Y3 y: E' \; nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 C/ O$ U K) ]| MCASP_TX_CLKFAIL
5 F0 ^' j7 }! Q$ b| MCASP_TX_SYNCERROR7 M% e8 d2 i/ {1 c9 k4 l2 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 G8 h" u% k. n$ Z3 j; Y% Y| MCASP_RX_CLKFAIL0 V3 o; t% h% i3 X3 ~1 a: G
| MCASP_RX_SYNCERROR
% y/ q1 h! [. C: j, ^| MCASP_RX_OVERRUN);
. l/ [! _/ W+ j4 |9 S} static void I2SDataTxRxActivate(void)) P/ z( W5 k- H, q! r2 \
{
8 @" l" x" z/ e3 r7 h/* Start the clocks */
; ]& |( ^' O- \( n+ W; j2 U5 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 [5 R: `7 `7 i; A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 i9 ]) ^$ v& E( @" b1 t* [6 d# \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," B' A; Y0 @8 N
EDMA3_TRIG_MODE_EVENT);
* q6 C; ~7 M/ j3 @% c' w+ zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 J4 h1 Z- u. `& ~8 x" o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% m+ ?1 T% s1 B4 F( v8 oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ c6 F6 K2 _+ C1 O9 q% E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' r) ?6 r9 v9 b) d, rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% s# l b) \9 Q( V/ [2 z7 c2 S% h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' |5 R! c5 y3 r1 q% w2 }/ s" K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* u6 G" I! h" B3 i( h5 ^
} ' U" \& Z/ Z% T0 J; T; [1 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ U/ B. p/ j1 T* }1 _4 T
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