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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 Y% N9 w! B" ^/ \input mcasp_ahclkx,
- B8 H# Z3 J! b) t" ]! V* i+ ^input mcasp_aclkx,
) L/ m4 w+ q$ J# @+ O7 cinput axr0,
8 y2 A& Q! l% c
* ]% v. k6 P0 koutput mcasp_afsr,
A# T, b( L1 j) M* M3 U8 k9 S3 `/ [# ~output mcasp_ahclkr,7 l3 i1 O$ I9 G
output mcasp_aclkr,
! B' E5 ]0 [! v( o/ {- [9 eoutput axr1,
S! C0 P ~( `8 I G- s; n+ y assign mcasp_afsr = mcasp_afsx;0 [/ v7 F' Z ~
assign mcasp_aclkr = mcasp_aclkx;
- a; h; @$ z# e {2 m% _assign mcasp_ahclkr = mcasp_ahclkx;
1 X: l x7 h7 ^5 F( L1 sassign axr1 = axr0; % k% e0 r% |+ _8 M5 r6 Q
' _. n/ a( ? {! c( h0 J. m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 X- A" v7 {+ X1 S: h3 ~/ ~
static void McASPI2SConfigure(void)! G7 }, R( F4 J( _
{( I4 w' n( R4 h, Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 K. d& U: Z& l, I/ N' ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// Y. k5 r/ f- r+ f/ [! v4 L' W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ j( f8 P9 S2 j7 g" c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 f6 E- c6 E/ |& M* J- P. J! g# CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ @+ D- G& f% v+ ] ~5 P* Z
MCASP_RX_MODE_DMA);
A# y6 z, b, z, Q( bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: t; m/ W5 y M: j4 g& T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 v3 M9 T7 I c4 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; e0 Y/ q( f. c1 G3 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ~. G, e, _5 _( h' b: O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # q6 \+ o7 V& v" w& Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) f$ U! T; q* n2 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* d8 f \* D6 F& c; z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ M2 r$ x, g( h* ^" q; w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 s/ ~9 d6 B7 i$ S' T0x00, 0xFF); /* configure the clock for transmitter */. q; I( c$ C" \5 {9 f9 ]2 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% T( U/ A0 x ]2 ?) Q1 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 }; ~% y2 @- q& F3 a: h8 k7 r, kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 M# m3 q0 Y: k0x00, 0xFF);; U. E: h" _4 e/ X- u1 t
# s! _$ S+ R: L; c* d) v. @' e
/* Enable synchronization of RX and TX sections */
/ Z9 t6 q$ w) q3 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% y2 [/ k+ h' ^/ {/ c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 n. E: H6 _6 R2 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, \' b* T8 w5 v! |0 V
** Set the serializers, Currently only one serializer is set as
4 T. e, r4 L9 s! \& g** transmitter and one serializer as receiver.% t0 c0 L. K/ f6 L2 Z, K( K: n
*/
6 s! {% O' ]1 @0 p2 h- R+ qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 O% `; a, r, ~' \; t) d) XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 l/ h; W, P h' q3 Y3 g7 A4 M** Configure the McASP pins : `6 i, \7 V2 ~$ Y2 ~# J
** Input - Frame Sync, Clock and Serializer Rx, T: j; i/ `; u" R
** Output - Serializer Tx is connected to the input of the codec % ]2 E3 Q1 A# {" T. S) [, U. ?
*/
! ?' z/ l" V4 e6 t* @! ^6 [, UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 c3 Q$ X/ I/ M9 E, BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 S) o8 i0 T8 p0 y8 y9 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 C8 C" r- n9 L$ z
| MCASP_PIN_ACLKX' G4 G& d( z7 e; z4 C
| MCASP_PIN_AHCLKX6 `; ?. x# q8 l! }) n" e7 \9 g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 Z& \. F/ t m5 S% q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) Q" D* T s& c- E7 `
| MCASP_TX_CLKFAIL : U: u6 S. L5 M& g4 F
| MCASP_TX_SYNCERROR5 O6 f) ~. O/ D7 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & U; j8 { t" `: I2 [
| MCASP_RX_CLKFAIL
6 v# b4 T# W4 Q7 M- N# d8 P| MCASP_RX_SYNCERROR
: @- F" v m4 U4 ~- }| MCASP_RX_OVERRUN);
9 ?6 p# E3 s+ f! X1 k1 X} static void I2SDataTxRxActivate(void)4 e! u" c: j6 O9 [
{- L) S. u! s+ W9 ^2 h, h3 C% b
/* Start the clocks */
$ A% e# z" K, p8 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ l1 k& z# A' c3 H8 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# W" n& X6 s4 C2 ?# z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- ^* z- y" e; G h s: jEDMA3_TRIG_MODE_EVENT);
! K6 `! B* d5 C* |2 L% @1 v+ yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; J' P, `/ {( L( i0 M$ w4 W6 AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" ` l$ Q6 j: EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: s2 W3 `& {+ y% s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' Z5 r$ h2 {% O! ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 Z4 J9 X G& S* s- ?5 R9 i& S1 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 T' ^- |, x6 M( x" N2 w) k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ \, a9 F3 K- w% m0 D4 c/ ~" i}
2 ~ ~& {7 }" g9 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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