MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
% @, ^3 Q4 R- x+ _input mcasp_aclkx,
9 I% a1 P: z+ R- k. @$ K( m9 }input axr0,

% p+ e4 J; J5 Toutput mcasp_afsr,
/ {7 w0 m: F% e: Y" c( Koutput mcasp_ahclkr,
output mcasp_aclkr,
. H$ {% I( O- R6 |$ B( V8 Ioutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
' Q* y' G$ y2 K* t: Tassign axr1 = axr0;

$ A0 \& t8 W% L8 T
+ v/ w& S2 d9 I; P/ p  K0 }

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

) {* h6 P4 k3 h" E

static void McASPI2SConfigure(void)
2 `! I0 V0 s' r; N  n" o{
2 U9 P1 h' b" S( A, RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
6 V' Q; l! S1 |  L2 I: |- rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
9 M! h# |5 a1 e% w3 X7 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 R3 ?( x. I* n2 n$ Z" xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, g) M3 L1 ]& R# g0 }" O% e: ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
- s3 |/ i' D1 y8 y2 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 f" ^6 _- R+ m* z; l" Q# SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 m8 J3 p. I: `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* E7 p' }* s; Q- U3 |0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 y! k; u# j$ ^! Q8 X" pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
2 d  D# R6 p/ j9 D+ W+ K4 i( [" GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Z1 [) g; n0 b* qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
' ?9 C, x2 d7 N) p& u5 K" f5 z4 u" ^*/
; G. q+ w9 r& j: p: [9 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
& d0 M; k8 \6 K' b3 w** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
& V. H, [2 P6 B7 r*/
4 E3 G/ R: ~- Q) CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, d( w: B2 E- T) D6 L' yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( F4 u* t8 m8 f| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# ?) M% F: w% x9 c2 d. m| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
0 ~% w( _4 L& I. g/ P  i+ p| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
$ H4 c8 g% O* I( i, l0 S7 V6 A| MCASP_RX_SYNCERROR
0 X( ]/ i: ]4 l| MCASP_RX_OVERRUN);
7 [# x) T1 _  A3 u0 U# j}

static void I2SDataTxRxActivate(void)
  }6 {2 }' E8 G9 o+ S( _{
+ l+ M' H' f6 W+ O  ]; N) P8 _" ?' ]/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
" C6 G2 |' e$ L8 @: T5 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' o3 b' @5 D3 \4 j7 U- d0 Z( `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
  o5 v1 H- j  S: p; u. V( _6 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
4 G: u+ S3 a& c3 s* S: C; @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: n9 b4 ?9 N' D/ n& J+ b! ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

0 n4 @4 [3 u+ K, I; Y6 i" D

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.