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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 n- Z9 a: L, u* D: X) M- v6 ?input mcasp_ahclkx,
3 u" M" g' `4 Y) R @input mcasp_aclkx,9 U0 l* |3 z; L
input axr0,
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2 [9 b0 `- x2 x8 d: goutput mcasp_afsr,
" Y# I6 R* D, _! Y( a5 Noutput mcasp_ahclkr,$ D; @# a: j1 c& T; j; H& Q
output mcasp_aclkr,
3 f& d8 F6 O3 b+ joutput axr1,) O4 v9 f0 q1 X7 g: A) `
assign mcasp_afsr = mcasp_afsx;. V8 ]9 [: `9 m! F: W
assign mcasp_aclkr = mcasp_aclkx;! ~, O; n) h0 z' ]0 ?
assign mcasp_ahclkr = mcasp_ahclkx;3 D4 k$ m& c2 [ \5 C& ~
assign axr1 = axr0; ) p( v6 v: |2 z, O# \
& M& d9 {* p5 @1 y6 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - C/ h- q' A5 A1 a( R! ]: a7 m
static void McASPI2SConfigure(void)7 x2 i4 l# H% R) c
{2 |9 r) @; r8 ^; e. x/ h# R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; w+ k+ ^# ~+ Q p, p" C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 U2 H& `; b* W# B0 H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" E' l2 I+ b1 V( N1 J2 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 C6 Q/ l ]7 Y6 j n; {& b4 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# {8 t0 V1 j/ _% r1 D: d- u
MCASP_RX_MODE_DMA);, M& \& a, q7 c8 P- z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* z G3 V d/ ^8 h* sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 j) ?) M# {2 ]0 |, m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 N* d6 f; G+ S; sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ y% D: w5 T$ U* F4 D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' @' M& Y* b9 l. {' A- J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 b3 _" D4 L) y& A; H3 w" P8 z5 U7 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 H# O! V: q4 a' J: pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 ~1 [2 f0 \7 v UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 {2 o( Z+ p' [# u `( j0x00, 0xFF); /* configure the clock for transmitter */2 b* r) Q) G4 s; _+ B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 T, E: a- j& a, ?4 u1 a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 z8 w3 n& ^" s# r5 L* z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 M- z5 M' Y7 C; V# T( s: a3 o$ |0x00, 0xFF);5 z5 s9 z; r. [$ R( W8 E5 s
# |" a$ W3 _2 C- Y# G z& l4 b/* Enable synchronization of RX and TX sections */ " x. F, S% u D0 x$ B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! [8 C, N8 x* `/ F+ n& ^" J; K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( H4 ^6 F* g/ `' z% g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) A( a3 P8 A% V& K6 F6 w: n9 |** Set the serializers, Currently only one serializer is set as* g- G" _" O# w- Q, b& I/ y
** transmitter and one serializer as receiver.- K0 W% N q, _* J1 E; x, ~& `2 R
*/4 A9 R& E5 ^: b, ^4 D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 q0 @) a9 j6 {: u" hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: {* E* o" k' c, L+ g** Configure the McASP pins
7 W! ~6 O& k/ y+ i9 R** Input - Frame Sync, Clock and Serializer Rx
+ d- T2 D# o9 B$ d* L: H** Output - Serializer Tx is connected to the input of the codec
8 F O7 I: X z' ~8 n9 L0 u*/
( P q# h; x3 fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ b' V. c6 P: X; r m9 q1 r6 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: H9 X0 N1 h& j- \2 H( u, i" w; A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. E" R; P E' i+ l1 K4 ]+ R
| MCASP_PIN_ACLKX
6 e d8 y& C7 j f4 R4 v| MCASP_PIN_AHCLKX
( Q' r( A6 \9 h1 ~) b0 n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) c" f a8 A0 R0 P% O- }" h' iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 ] ]" _' n; Y2 D, C| MCASP_TX_CLKFAIL
- u# y' |0 ]4 |$ t& |9 u| MCASP_TX_SYNCERROR2 T2 O `& O! a0 z; g% \4 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 ]7 P9 [; J a( W. K9 Q| MCASP_RX_CLKFAIL
3 M. H9 q8 c' `| MCASP_RX_SYNCERROR 5 `) I: B/ x- t$ B$ ~8 ]: n9 |% Q
| MCASP_RX_OVERRUN);
3 i# W1 S+ ^. ~- D1 z" g} static void I2SDataTxRxActivate(void)
( U$ Y+ K( T8 f' V$ g! W8 |{! Z/ D9 O( z6 n+ Q" m
/* Start the clocks */
# n( _ B6 Z, m" n7 ]# \$ p7 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 Z$ y5 c5 e& {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* x# H# \, a+ i B F: S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! ^7 X* i1 g% B2 _
EDMA3_TRIG_MODE_EVENT);! g% V: O. G$ w7 V# \% E, ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 `" V% {- q3 M' E- [. h! HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 w9 t5 G3 B8 p" k/ S2 p @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* j$ W9 u& ]. _! ^7 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( n( P7 {4 N, y% a# g; r& x& g( H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- u5 C! v+ p% p' i6 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ w8 h& { C! ]$ cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% _. m5 A7 t1 _* z* N3 r}
+ }- u" `# e& c# i9 O4 k+ n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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