|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& l( |& O& V ^. b" N
input mcasp_ahclkx,
/ R+ q, o2 i4 I' D, B. w4 Z/ I( V1 G8 Binput mcasp_aclkx,, U4 G2 k: Z( g- y1 c2 F0 |0 a
input axr0,0 k$ G9 b1 @" ~1 H; Q4 y T
& f1 F: h% s4 ~/ ~output mcasp_afsr,
+ u! m1 m, B% m4 n( L6 c3 @output mcasp_ahclkr,6 C2 _0 ~7 Q% a {% U& y
output mcasp_aclkr,4 I% y1 e! u O( I" C
output axr1, M% S# N# l/ |* u& I6 B* a
assign mcasp_afsr = mcasp_afsx;# A* c; H9 {1 i) q$ G- S& \
assign mcasp_aclkr = mcasp_aclkx;5 e3 B1 E7 B! r; h& V9 k
assign mcasp_ahclkr = mcasp_ahclkx;7 W2 a6 m _( u" c- q
assign axr1 = axr0; 9 g& V, n/ b2 ]: p% y1 j
3 e F' S" g1 G$ }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 N" k; ]: L1 g
static void McASPI2SConfigure(void)
! J5 S+ V, e! c, g# a0 F; i! j8 e' R4 ]{
6 h) \; f6 u3 d/ \" H, B" KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* u% S8 }7 `3 R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 j" f7 x; t( V* d1 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 k; Q$ ~0 y4 `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: n0 p: ?2 h, a m1 M0 u: p4 n( X- p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, d5 l6 K+ l7 Q1 M
MCASP_RX_MODE_DMA);
4 G& ^. N. x% R) O& kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," F% M# b7 s: v& k4 w' v* e% r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ M) i* e: p+ LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 P* u0 ^. N/ Z$ B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* Z9 F. n; N2 @# U: fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + g+ A' C+ n( L; ^# h( Z& i" d6 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; j: b! [- c2 lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ L8 o% _4 O9 z: }& e: Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! @& R/ b7 k4 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 A1 N2 i9 {4 @
0x00, 0xFF); /* configure the clock for transmitter */; A1 w3 Q# p8 L% b( Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 A, h/ K" m6 h* C& O1 U& e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; ^2 N5 W+ p+ T- m, q$ ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ F" N: s3 ^5 N! m- }+ d9 A0x00, 0xFF);
) I7 _4 U: |1 l6 j u
b6 p ~; U/ j0 o/* Enable synchronization of RX and TX sections */ 7 E8 }4 W7 R4 i5 F# `7 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 [1 e9 U' i& e. Q$ y& L4 G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) ^ e( g2 ]! |3 w+ a* L( tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 E( d3 ~- D5 p4 j5 i" N! B, b
** Set the serializers, Currently only one serializer is set as
5 R6 g- _6 W8 p, u, d6 t% b4 T** transmitter and one serializer as receiver.( P4 }0 S& Q. }: e
*/
7 `! B7 \! ?) y3 p6 X" l; {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 X, ?0 C) p+ ^+ T: x1 F$ [ ]* L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ z- O' i5 L; U% v' s; c" d
** Configure the McASP pins 8 ]) [% z! s5 m7 J$ B, X
** Input - Frame Sync, Clock and Serializer Rx
2 Q5 e' e* g- G& k* q/ `** Output - Serializer Tx is connected to the input of the codec
3 G4 M! h9 W7 L) v' ?/ u*// q9 z$ }. o. v. R% I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 M7 n& E$ s+ q I# M1 A. V) e% ^2 |7 c, ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ g2 V2 }2 K7 l. ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# A4 C( U& F8 k2 B! U2 n% t* e| MCASP_PIN_ACLKX8 T/ y/ C, x* ~2 l7 a& c
| MCASP_PIN_AHCLKX
2 P1 t* f7 q+ P8 ~5 `4 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 p0 [' r% g% j3 ~+ NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % ]8 [ h2 F( [1 g& s( x0 A
| MCASP_TX_CLKFAIL
. x; t5 K& j* [5 J# E& A0 ]3 P| MCASP_TX_SYNCERROR) d, k* P/ ]5 Z$ q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 B2 e$ P, u) Z7 }$ M# m8 Y( C
| MCASP_RX_CLKFAIL- S" [) a5 U4 k+ `# h6 I' b
| MCASP_RX_SYNCERROR : r) i" x: @" T
| MCASP_RX_OVERRUN);' e7 U7 D Z+ j4 A! `' C# }( t
} static void I2SDataTxRxActivate(void)
& y R' I$ h% c0 ~5 U{1 ^: O" c! [. A2 F0 t; G7 U
/* Start the clocks */
8 @) D/ J& L' m- F# MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: I) C# ^9 ~5 ^7 p! Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( m, \! V V9 M8 p+ QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) A9 d) ]& a/ O+ bEDMA3_TRIG_MODE_EVENT);0 r' y4 V+ |( n3 h6 o: J8 p" x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 j& E3 w w$ A; ]7 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# z, n- W$ ^3 F" _" u9 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ ]+ g! \6 U- M* M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ?7 s7 w& s- g3 Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' B( Y, e; w& a( D" X) }- S# A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, {6 y! C0 S7 M4 P5 _3 Y0 E7 y& u' X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 e, o! Z/ D' p! z( [# m( L9 u# i}
, k7 }. z) L8 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ Q; a$ Z: G/ a' l# X) p |