|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* t' W* P( W6 |3 U5 s1 L9 D: }input mcasp_ahclkx,! q9 Q$ h% {0 \9 V4 ~
input mcasp_aclkx,: ~8 |' ^. ^3 F7 k1 Q% ?
input axr0,
?9 U% {2 R* e) n7 ]: D3 A2 h; P" v& v
output mcasp_afsr,6 x9 H6 s0 c2 Z' j* R
output mcasp_ahclkr,
! W/ k" v! h+ i4 |output mcasp_aclkr,
# I3 Q4 I6 e+ o* t9 Voutput axr1,
4 f! o+ g: P8 M* g& } assign mcasp_afsr = mcasp_afsx;: L0 C* X( q6 _
assign mcasp_aclkr = mcasp_aclkx;& J9 h6 s; Q) O" T
assign mcasp_ahclkr = mcasp_ahclkx;
0 X! J0 b; ^, ^9 f1 @8 K9 o- eassign axr1 = axr0; & a! K+ I% Y, u: k1 k! L
& j- ^- P. j% k& ~" S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 g6 e: L7 c6 A# ^4 v5 Fstatic void McASPI2SConfigure(void)& X' C. w* Y. ]( _, n- v. z$ V$ B+ \
{2 ?. u. p0 F6 w6 v; c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% a( n' a0 ?9 B3 V( g7 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. R m" V% N( ?3 p7 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# }, D$ [' N* xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 E- g) O+ n$ L0 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' q7 I( B& S4 x: u$ m; Q ]MCASP_RX_MODE_DMA);3 k2 N/ o+ y" N3 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: e4 n J& z) m7 [: N8 f$ i9 ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 b& w- t9 K. m7 H+ J6 NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ H" Y$ J) n G0 @. w4 D. b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 o2 w. ?* z4 K l; R- f# Y: g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' i8 |( Q# T# O, A8 k0 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 _; K ]- E2 n- E2 rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 X4 G9 z6 a& V& w! E' V. t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 c: O/ I I: q$ \1 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 n+ [3 \$ G: b: m/ V$ a
0x00, 0xFF); /* configure the clock for transmitter */5 ]8 \: i$ O6 l+ D% Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 ~6 W* Z# ?' v e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ i8 Y/ |' A; J, g* TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: }' I$ q0 m& N a: ]" n! M
0x00, 0xFF);
7 ~0 O5 H) }; X& r
& h5 U) U$ c8 T" k* g0 z. ?+ c' k' h/* Enable synchronization of RX and TX sections */ - g2 a' u) R9 e0 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 t$ {# j5 f9 E2 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 c) w! M, I6 G s: s8 n J& v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 k9 E# e. X3 d% X* L' ^** Set the serializers, Currently only one serializer is set as
7 o+ Q4 g1 Q( C! |, P: I** transmitter and one serializer as receiver.& R \ b- \5 i* V% |# D
*/
X* f7 @; }/ R' c1 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' A8 L" k) Y( c8 {5 S+ ~2 ?9 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ j" S6 w. \4 F3 A+ u$ U
** Configure the McASP pins m8 J" a# G; X
** Input - Frame Sync, Clock and Serializer Rx O! L/ } U3 R# `
** Output - Serializer Tx is connected to the input of the codec 6 q' u, A8 @) c9 f+ S; U
*/
* C# [5 Y; h7 kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- y& U' F# d' G) m* [" v- x" R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 S% l: ^+ E1 s5 E9 R8 n- k) zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 p( n3 f8 }/ |0 `
| MCASP_PIN_ACLKX0 d" v8 A8 W$ b' @9 Q/ |5 A' ]
| MCASP_PIN_AHCLKX8 N8 {+ u. e# k& R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( _" f# E3 L1 j7 F, M4 j5 s6 E) AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 e" ] G% x/ [2 ]7 b
| MCASP_TX_CLKFAIL ; c6 i/ w0 `- d+ O
| MCASP_TX_SYNCERROR5 x# _( y5 \9 P. m1 K8 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# n8 e* f) h; j" n4 b| MCASP_RX_CLKFAIL% [; f# x2 s% q; P5 u6 j- b, [2 |
| MCASP_RX_SYNCERROR $ } w2 Y* @3 y; x8 k% O4 A- {# o
| MCASP_RX_OVERRUN);
2 \) k% ? Y/ G} static void I2SDataTxRxActivate(void), ^! s) |" V7 e/ i0 @6 W
{4 J4 l8 Z8 S" N' F% W
/* Start the clocks */
* R" @2 p" G) w7 w/ tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- r1 E0 i& U) v% `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. |6 P+ d/ |/ `. ]/ a1 U+ d ?6 q* R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ P, \2 h# k& u8 n8 n( G; CEDMA3_TRIG_MODE_EVENT);
' r1 P0 J# e& N: u9 G' ^1 N$ K! CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 l: F# A7 k# Z! s1 {* C8 \* ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 a! P1 t$ N9 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 F# Y0 z4 D% V/ u% P( }2 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. E1 p. u) g3 a9 l. v! @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% i& l2 M3 B) x/ D6 s# b% e4 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! i4 O- C9 v" S0 }4 |2 |6 E" [2 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 [& {+ o/ v( ~, r- y; W} ' y' X" ]; ^7 {6 L% A( o0 g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , l- z7 S; |' V/ i- r
|