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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& I- g5 \6 M+ O! W+ Winput mcasp_ahclkx,
* G2 D' h+ Z. i! S4 ]input mcasp_aclkx,
8 R. C4 s( i5 t- Vinput axr0,2 Q# i' y* r4 v3 P& M: z4 W
! O2 t, L$ H; f9 s" w! v
output mcasp_afsr,
4 [- Z" I9 I2 `( Houtput mcasp_ahclkr,, z; @1 U) o' w# \4 s) w: \& v) c8 C
output mcasp_aclkr,
5 }1 [% o2 }/ o& [: _output axr1,
8 B7 h' \$ v8 A1 O0 t assign mcasp_afsr = mcasp_afsx;* e- T3 T* K; ?8 P8 \# B8 S
assign mcasp_aclkr = mcasp_aclkx;
k1 j! Z U5 A' o& h& ~assign mcasp_ahclkr = mcasp_ahclkx;+ D- c. K# F5 L" U
assign axr1 = axr0; : x5 x7 r3 Q0 T* F4 Z1 J
4 d) _! D* v( z. |* O" i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, q `6 H+ d1 N- E6 hstatic void McASPI2SConfigure(void)& y+ t) u6 k) A1 A$ e* l7 s
{
V' e/ O$ o- u( c- w8 H. xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( c# c6 ?# ~# ~2 e N0 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. B. s5 g& {+ ]8 G3 I* f& t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 w- i ~7 Y( y0 dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 O. w; v9 n' c5 E4 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ [# A8 u" P' x/ @% ]' x) rMCASP_RX_MODE_DMA);$ U4 H; @& r4 G) m3 i$ x2 y; t- }9 G1 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) f# k, A: C/ X( I) S& c- a& v$ u, M1 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& x d( l* g' s- @; u' v: ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 T+ \% P4 k' l, w' S3 b# J% F& P& t5 kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# u a* {1 c$ m! UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) ~ G! [- k, b3 Y+ B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 F( Z0 V0 H& ^& L8 H$ kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 T& e$ e9 e9 l% G5 @ e' E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ i z1 |( p; x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% E$ @. d8 ~& D( F
0x00, 0xFF); /* configure the clock for transmitter */
5 k. Z' H* K' e2 [# DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 z" i3 n J- C' M/ AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 Z* Z, Y. Y# F S8 I) P( |1 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- G9 _/ b1 V; r
0x00, 0xFF);% l+ l" q" Y) ?# A" K9 r* S; _
/ P$ j& J9 P3 l F. o& ]" E8 d/* Enable synchronization of RX and TX sections */
$ R' L7 M! m" E& I: ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- P" U/ ?0 E' j$ |9 B+ z) sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 `1 y' w( D# d# tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ N0 ^) b) f+ ?6 v' s** Set the serializers, Currently only one serializer is set as
k+ d4 F' V5 w( A) u6 f' F** transmitter and one serializer as receiver.* y# U! M& b+ _8 P7 [$ n
*/
* s4 y: B! T7 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 k+ l, U% D( i5 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. G2 o& C0 v% M6 f7 T9 U0 O3 M$ D' }; X
** Configure the McASP pins
- U+ B7 k2 M# ~0 w/ w- |** Input - Frame Sync, Clock and Serializer Rx
|% i/ j( U0 p& v5 r0 K4 m** Output - Serializer Tx is connected to the input of the codec , o& z8 @: \" Q4 N2 C# O' ?, l
*/
5 G: U9 X" c+ U( y! Y: qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ R& O8 H% H3 a% U( h' {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ W4 z* ^. X2 r, U4 t5 ?9 z5 f6 r1 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( D9 R/ E2 n) g) Q4 Y
| MCASP_PIN_ACLKX
5 X; k6 a2 i2 E! ?/ T# N5 v: p' O1 G3 q| MCASP_PIN_AHCLKX
, S% T |& o1 G- R& Z2 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& m: F8 e$ _) T. u% P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & P; m0 d- D, F+ I V, W6 y6 Q. {
| MCASP_TX_CLKFAIL
: l& P3 w7 \( y8 I+ G2 l; ]| MCASP_TX_SYNCERROR
6 h7 J q1 O/ z# j' l, n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & M X2 N5 Z1 T/ r
| MCASP_RX_CLKFAIL" y2 q2 a. j u
| MCASP_RX_SYNCERROR
; G' e7 `. @( G7 ~! _1 N7 N! }| MCASP_RX_OVERRUN);
; V2 M* t- ?& E: ^: A) ^9 M% _} static void I2SDataTxRxActivate(void)9 x# a+ @1 g* W- l
{6 y& g1 R- W* a# r$ F
/* Start the clocks */
" u- y. c0 c3 O3 p/ uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ `, |4 ?7 e( f$ sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( L, K n9 f* t! \* F: n2 Z0 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 w* c, k3 B1 }" L+ V/ T) Z M
EDMA3_TRIG_MODE_EVENT);
+ @, O5 w; u! m+ YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 ~( r3 A# X/ u& c5 J2 K; u+ Z5 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 N9 W5 T U4 T& w& zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; J$ Z5 u0 k" F6 c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; S5 |% b4 S4 y+ Y" ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. H; @5 M" E, ~% ~5 ?9 F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. `/ Z0 y7 X& Y+ n5 C9 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 p+ Z8 [- g) O. z- C}
6 K) z. f/ ~0 W# _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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