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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 y: C. [/ u+ |: `( G2 C4 kinput mcasp_ahclkx,
5 d! n9 s N* ^; K1 ^4 ]input mcasp_aclkx,/ V9 X A$ Y5 q) M K+ `0 {7 h5 z
input axr0,
+ V( R/ W0 y2 s3 N- t" a6 b$ b
output mcasp_afsr,$ M4 I* n7 M' V$ C& t- m
output mcasp_ahclkr,
! F; ^; Z- z& ^+ s) `' Noutput mcasp_aclkr,
7 k: B. L+ E$ x& O" u2 R2 `output axr1,5 x0 B7 a: ?! x* Y+ l
assign mcasp_afsr = mcasp_afsx;- Z, R. Y; N* h j! B
assign mcasp_aclkr = mcasp_aclkx;) w- R* m: I6 ?4 U
assign mcasp_ahclkr = mcasp_ahclkx;
6 r% ]1 l+ R V( A0 R) q& bassign axr1 = axr0;
, X! `+ F: Y2 O+ a" K# d. T/ n0 p# [) X7 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , g' `" M) q% A" a) {
static void McASPI2SConfigure(void)7 p3 P( A* d7 \' H
{$ x8 f9 C7 R. ~* ]3 p+ V- k/ b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( r- G! t% }* o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( Q- y& Q/ T1 V# ~9 }/ }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% v5 }, j- r$ z: U) Q# }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' y/ l! p+ f+ e, [) s; A6 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 o! w" Z% m; E
MCASP_RX_MODE_DMA);
5 @3 W6 N4 O2 I! W5 V. sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ w8 a, C" ^8 D4 r: {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) F4 T, P7 I5 H) ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; M2 s4 Q6 g: g" S2 N* WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. k# h# s/ k' R6 Y! q1 v# X& K0 g; k. UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ q, P. l% o: Q" O7 ?# a4 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( R8 P; S5 t3 }( v$ N, m2 M1 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# n# f% ]" c! N' ^0 W, zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 c& _* ]0 h( H$ {, L, T* k4 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ ^9 g w1 j0 Z. o9 D
0x00, 0xFF); /* configure the clock for transmitter */8 @! k9 C7 S3 N, u2 A. h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); S; U" B- e/ B% P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * j4 r6 R& A! _5 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, M3 {8 z* g8 u* ?, R0x00, 0xFF);* W" w a6 |5 L- `4 {
; v4 f$ ^0 y$ \4 |9 P7 u* ]
/* Enable synchronization of RX and TX sections */ 7 R: z) d1 u |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: K/ l' b% }- i6 D, W2 G. c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; x1 k2 ~! y; u4 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( V7 B) o7 x X2 Z. s0 I" h** Set the serializers, Currently only one serializer is set as
, ?1 u9 W) D( g7 w, T( f" X** transmitter and one serializer as receiver.
+ G: L) E0 o, K( A( K*/
! Q& m! F9 T" _/ O! cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- c( o" Y' d: y+ G$ v* S; BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ~, O; W" Z, R; i9 z, T% f** Configure the McASP pins
0 E0 }" v5 `2 ^1 x. q% K' n** Input - Frame Sync, Clock and Serializer Rx0 G+ Q! Q& G* }8 g: F
** Output - Serializer Tx is connected to the input of the codec
; l, I$ \9 n& J7 c$ p% S*/
- q) B a6 b' {. Z4 s7 @7 fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: x0 J* U/ r, O! c2 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! n4 H7 L$ A+ H; D% i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: }. [( z+ ^0 p' J1 K4 r| MCASP_PIN_ACLKX
$ w# x' V: z- ~0 v; [* {| MCASP_PIN_AHCLKX$ W! t) h( ^# w7 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, K9 x( v: ^/ {, }2 S/ W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 m" B4 v' y, ~4 }4 ]9 F| MCASP_TX_CLKFAIL : H$ P, s2 F2 v- s& r* ?
| MCASP_TX_SYNCERROR: t- B9 y" z( u- u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " ^2 L7 h0 n" c/ h% A; w0 n
| MCASP_RX_CLKFAIL% V3 J# G, E% I) N# T+ ^2 `9 j
| MCASP_RX_SYNCERROR ; X' j3 Q1 [; Q+ x/ S4 ~
| MCASP_RX_OVERRUN);
2 L$ D) D' Q! h/ O2 C5 r} static void I2SDataTxRxActivate(void)- J0 a* {" `) j$ L, q# a
{
, f; s8 T) N0 G3 P/* Start the clocks */7 A( a" L' i! m% n( V' S. V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ |5 }; s) `" g/ xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 w) C2 ]- ]7 q* [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
k5 w$ q) |# V+ O/ z4 ~, ^EDMA3_TRIG_MODE_EVENT);$ Y( d# s! B9 ^7 g( {: ^1 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; c! m" R& q' d/ xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% i, `6 Y9 k: ]: J; U5 _- X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& C8 L, I9 m, h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 e* E( U# o: Q& Y3 `& Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 a9 \/ R/ L$ z1 [( X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& ]& c0 h1 {" H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 a2 C5 G. Y5 ~1 F0 ~
} 4 O$ Q6 U+ i" |" B2 E8 K; Z; f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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