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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 `+ i6 b" u4 n& M6 u4 finput mcasp_ahclkx,5 {/ b& G1 l. R
input mcasp_aclkx,
5 \2 c+ m- O; P. y4 y' K/ a) Zinput axr0," G) n/ Q b# ]3 Q) G: G* E- H
( ^' v! Y3 w7 \/ d r- Ioutput mcasp_afsr,
2 N% T. Q7 P+ Z8 K$ G3 n' ?' [output mcasp_ahclkr,
/ l& \. M3 S" Eoutput mcasp_aclkr,
3 s' c: B t+ Q5 Q* g$ poutput axr1,
/ ^2 S: }% j3 e) i: M; D! `; ~ assign mcasp_afsr = mcasp_afsx;
- p- ~" V7 S; q( j( A1 oassign mcasp_aclkr = mcasp_aclkx;: e; P x2 M; U2 L6 A# Y" w
assign mcasp_ahclkr = mcasp_ahclkx;
9 A1 G# c8 a" E4 m# }/ M7 p+ I) xassign axr1 = axr0; 5 |1 b2 D6 t- c
$ S; m5 ?) I2 R* f: ~' g/ E" A9 D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 u- G8 w+ ~, Zstatic void McASPI2SConfigure(void)
3 X) E `& G2 N5 [{0 D7 z3 m: E; x4 U% Y/ z# v9 o5 i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' v. n! {; k, ?: Y$ m# x" m8 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: L+ m) M: X# d0 y0 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( f, e. k f- p& S, b) {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& |# d" a% ?, e, b: D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
b' L7 _$ h" ~" R4 kMCASP_RX_MODE_DMA);
! s5 H: s% @5 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 {$ r. H+ n) K( e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. O" M2 i) ?+ H4 V* o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; _" N, D: @4 C% T, J$ h) s; H2 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* A/ ~) W8 Y. _+ E' uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" \$ C) _9 M9 t' M' |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 h$ [7 ^6 U `* }) e' c0 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" B5 S- U- n7 C1 j! H" A8 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 D1 D6 C( k7 ?& ~5 L6 Q! eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 j* M' J+ o' t2 X
0x00, 0xFF); /* configure the clock for transmitter */
% q* e% i/ v9 J, @8 V6 Y& @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 \" k+ c, z. t) A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ P. g. I+ {/ ~" v1 R% H- g( FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 m* f, U& S2 K P j5 m* d* l9 |7 w
0x00, 0xFF);
2 M. ^" Q# L# }1 u
) p: q0 Q) k8 b7 [6 ~/* Enable synchronization of RX and TX sections */
/ O" V- a9 B% M: M. ~# s4 g- J* uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% {5 R. f. _' l: d; {& \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) ~: m; M- L' C, p2 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 m! R( c, ]- D. c3 m* f** Set the serializers, Currently only one serializer is set as
+ @, K% P) ~6 Q, ~1 b' m** transmitter and one serializer as receiver.! F/ P% P4 h5 |: W" y: x4 O
*/
I" a; i' t1 o- e* j/ NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( c. x/ ` @, u, d* @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, \+ ]( e- S% X* z# s5 G5 s
** Configure the McASP pins . G/ c$ q, p9 C1 J: u7 R& g0 K' `
** Input - Frame Sync, Clock and Serializer Rx& r* x# K: B/ y5 O. f& `3 e
** Output - Serializer Tx is connected to the input of the codec
h p1 h; G7 y3 `# _+ t*/7 G g9 h: h0 u% I2 X4 M% A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 u# Z! H2 Z: G: \9 q( n4 A6 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: Z/ g& A1 m* ^* y, ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 g% A2 b' o5 X| MCASP_PIN_ACLKX/ K8 Z0 m& X. |
| MCASP_PIN_AHCLKX6 I! x3 d8 G+ A. J" o5 p0 ~% D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 h" K' q {/ d- B( r. C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; v3 m5 C( f+ U# ?
| MCASP_TX_CLKFAIL - \6 _8 Z9 B5 T' c) n
| MCASP_TX_SYNCERROR
+ r9 I2 v- H7 |. e; w. e! v. l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 w( Z T- t4 x: ^1 d) [) {) P
| MCASP_RX_CLKFAIL
4 e7 D, Z- U0 V2 i$ Y| MCASP_RX_SYNCERROR 9 p$ ?! D5 e4 B$ S- M
| MCASP_RX_OVERRUN);
, H7 M" X" v# v; S! h. r" w0 W} static void I2SDataTxRxActivate(void)5 @6 g! C1 `, i5 s/ C# {
{
. S F M; J" t* P% C& n) l+ ^/* Start the clocks */
8 u9 d0 T8 F0 Z& ^# Q9 b) HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! `$ z9 t$ t; v/ X0 K8 H- }' h" r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 ]! ?. Z! T7 _' V' d4 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 ]% j( F5 v/ B/ SEDMA3_TRIG_MODE_EVENT);( r, M4 E" t3 p4 m$ Q! I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 k8 ~5 o/ e% C6 @- YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 C d1 _; y% h# W+ i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; K# C' b+ D- z0 ^! o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 ~# @5 O% \- F: ]- w$ ]3 ~. |* i0 Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' b( I' Z% S2 G& h9 H! z( s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- G: j, r/ [- P& h0 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 m( M r) L* P
} 1 |0 }) d# i4 g8 g, B( c. u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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