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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 b! F" C: x8 J- C4 k1 m+ \
input mcasp_ahclkx,
8 @' K$ `" \5 n" m7 minput mcasp_aclkx,
- e+ j: ?9 M: r9 y& }+ d5 e! ~input axr0,
9 ~5 z. T/ }* K6 M7 \
) R5 m7 ~6 Q+ c9 q% V3 g3 Ooutput mcasp_afsr,; L9 T( \8 u5 ^' v2 w/ W! h
output mcasp_ahclkr,2 Z- C; Q& w6 h! y3 O3 {
output mcasp_aclkr,
# I. g) y3 l1 P8 F& r* m3 Uoutput axr1,
% B. _- B% r7 `) N: I2 N, s assign mcasp_afsr = mcasp_afsx;* ]* K7 V. Z# t' e! Z8 K# C6 Z: `0 S
assign mcasp_aclkr = mcasp_aclkx;
1 R6 [- ^& C) y; ^7 Oassign mcasp_ahclkr = mcasp_ahclkx; m) R8 a8 A7 q# h8 ]" \
assign axr1 = axr0; 2 M; ^( Q" U$ L4 d
& Y9 Y, B+ T' `5 V6 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- n1 N) Z& U) rstatic void McASPI2SConfigure(void)5 I" X( O0 a$ o
{7 j! _3 D Q3 q9 Z. L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 M& H$ ?' q2 `' W* U, I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 O7 C( X* E: e/ \7 e, K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. j3 i" `% U4 ~6 [8 bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 q: Y, Y U# s7 [4 o9 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ^! J& h5 b; h3 RMCASP_RX_MODE_DMA);) X( O$ ^- c! f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ?! B" I0 a3 i o# D# D: S! A! K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 F# I- x# F1 E" T- _& nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# ]0 e$ `, `0 v1 d7 B! d* S0 K" s0 o' v* ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 H0 v* o" V4 \$ x0 m/ l7 x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& x$ z* Y6 x9 Q: V. GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: `) {2 J' a6 I8 R& T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: e+ h; D! ]3 e, a* d1 j8 N: }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 }# o7 u0 D6 }9 S2 ?/ }0 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 y5 p3 s. B% L3 y& _7 v! g
0x00, 0xFF); /* configure the clock for transmitter */
( h& o% N1 K! Z" H" ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% l- d6 ]4 \" d' p2 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 ~4 o6 |' d1 V' ]! ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: G+ G+ l8 `" I' p. F0 O, p( F$ M
0x00, 0xFF);
2 |% s) v; }# r; h+ n* V$ z
, m6 T$ p" l9 ~! i& P/* Enable synchronization of RX and TX sections */
R6 F) ]4 l5 z S' a) BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" E7 { q1 K: t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 v% `+ k2 |7 |) W/ pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 Y/ n; F, n2 J2 \
** Set the serializers, Currently only one serializer is set as
( @6 K( ^ q) P+ A' S** transmitter and one serializer as receiver.
+ U+ \: U( n% B2 k*/& {, ~) K% i) {+ [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( b' L* Y7 Z: N# {; H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 c" t/ h+ e: X3 {/ z
** Configure the McASP pins 0 p; f/ K p! C, z
** Input - Frame Sync, Clock and Serializer Rx: B7 K0 ]- V" z
** Output - Serializer Tx is connected to the input of the codec 0 {+ b) `& s; L
*/
5 P. `1 D- ?; U/ C* TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 U/ v/ g$ ]( C% R2 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 G) i- G* M5 p) V5 `( t" u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- G4 n& C" t! `7 S4 @3 r5 Z& r
| MCASP_PIN_ACLKX
v( L. g( y, T! _4 R, ]% V| MCASP_PIN_AHCLKX
]. M; n. |" B9 |( Q) S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ ]+ O' n0 I. O* _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / @( Z+ O) T/ \7 l, y- Y/ g
| MCASP_TX_CLKFAIL 2 b! W8 e0 j& o/ O, F
| MCASP_TX_SYNCERROR. S: D+ A; E& R) ~8 B- g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 Q9 s; @3 H5 T6 v
| MCASP_RX_CLKFAIL
; Y5 h3 l N0 G Y$ V| MCASP_RX_SYNCERROR % g# a0 n- t' {9 P4 a
| MCASP_RX_OVERRUN);8 _: H# G8 S2 ]) W6 q5 B/ ?* O
} static void I2SDataTxRxActivate(void)
- X; K6 i. I6 S3 @& e4 @# e{
; r- u o; O _+ w/* Start the clocks */
$ h4 v6 H4 H& C, Y" [* F0 uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 f. a0 o( O* r, Y: f) R: {: GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
D$ s3 W) i, g' v* g; MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! F4 Y9 P3 Q8 G6 v6 nEDMA3_TRIG_MODE_EVENT);
( P! f* J$ g( g0 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' v8 {5 x7 p; Y0 K; ?. y: e9 d }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, Y& d' D7 E3 @+ `8 v0 \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 n2 z6 A& Z. S; v7 C& }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& L# s# F. h9 w y2 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ Z1 f' L" Z' d& ~2 ]4 u/ ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" J0 n, c4 m* \* v/ @- n/ Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* N) `- X2 n" K0 }5 U} + J3 F6 k5 X) K3 C. J9 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # S$ H9 c) [# }. h1 v
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