MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
! _& u' _# Y8 ]5 Xinput mcasp_aclkx,
input axr0,
- L' D1 R* |* l( T' |) f: \: S
3 C" p: i- j+ u+ r# b& _output mcasp_afsr,
output mcasp_ahclkr,
* Z- P" p2 U  K- X6 ~+ d' Z7 Doutput mcasp_aclkr,
" m+ p4 V, e+ Zoutput axr1,
* ?. h8 t$ l& z% n5 r# v) E/ @/ p% Z

assign mcasp_afsr = mcasp_afsx;
' |0 R4 l) f% H6 E6 Xassign mcasp_aclkr = mcasp_aclkx;
4 u7 Q' \; ^! |* q7 T. \) Aassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

3 C$ ]( r9 K4 B

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

1 B7 E6 D4 n3 R2 n9 s2 X

static void McASPI2SConfigure(void)
{
( t" K! u- R- s/ uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 z- o, i& Z3 n) j" ]! SMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 H4 K& E4 R2 S* B/ m6 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- |- f# {9 Z: ?3 E4 ?6 X) ^( u% u  ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
" R* u# |  r# [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
* l! y  b1 Z0 h5 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" w' g, L7 c# [' |* \1 a' dMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' E+ B* A( l2 B: l% T8 z/ h6 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 T" @- K2 K* A/ d1 l! C0 s) S' L( D" t0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. `1 U/ z4 a' \  b/ qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! A% o- R: d! V: Y) I. z5 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, \7 e  t& a$ O2 x7 k, V+ [3 w) \  Z0x00, 0xFF);
5 z( J4 h% d' O  G6 y. @
. b  N  t' D* P/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
) h/ M+ [9 G7 G9 E5 `: B1 J. ~1 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 O8 q! ?. K) b% h" w/ P% vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ^  n; Z3 m1 L& C| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
# W1 I% @; g% c- F6 b# ?! n* h5 C4 @| MCASP_TX_SYNCERROR
0 I9 I9 }( w* ?! z& a| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
1 z6 P4 b3 Y: I" D) L8 y# I| MCASP_RX_SYNCERROR
: d- Z/ L7 c6 ^3 r- B# Z| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
  a6 f! I9 m! a/ A/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
) t2 I- V: a% ^3 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 k" I* h* r: ~) l( _" m7 d9 l: BEDMA3_TRIG_MODE_EVENT);
, ]6 e' f) d3 Q% v3 R4 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
8 W+ b/ g" u1 k. z0 g$ XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
' d8 a9 D8 W( B; E- }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) m* {; e6 }2 U2 U$ D2 D6 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 J$ }% x- t6 K8 p& [}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

; Z/ k, {! F+ T6 o2 f# [! F