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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( T4 b, i$ G( y3 t
input mcasp_ahclkx,
- s% W& K0 u4 Q$ S: uinput mcasp_aclkx,
) D9 D( d. p2 A( R0 I5 ?input axr0,3 B5 B% u' v3 L
. ]- M" @% N! o6 Y: ^' Aoutput mcasp_afsr,6 I4 f. A& I/ Q; R d
output mcasp_ahclkr,0 Y7 }, K: Z" c7 |' o& d/ Y/ O
output mcasp_aclkr,9 y+ T$ N* N4 J- k
output axr1,) j+ Q7 {" Z9 o; x; a D
assign mcasp_afsr = mcasp_afsx;' m2 I# r# z; h! \: m+ ~% L$ \
assign mcasp_aclkr = mcasp_aclkx;
3 g$ H/ h: g9 l4 T' rassign mcasp_ahclkr = mcasp_ahclkx;3 B; f! W0 p2 ? p) W S+ v" v
assign axr1 = axr0; ' s5 Y4 ?! E/ J; |9 t
\( V- h/ P- i' S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 ?5 X% X9 O+ q {6 o. s
static void McASPI2SConfigure(void)
1 b8 O3 m. [- q' \0 h0 {6 p{
6 `2 [) _ |+ V* CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- r7 E6 m+ a( S2 a% H9 l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& S- ] n1 I4 f& B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: D; v1 X. D; v( o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 \+ F% J$ `$ XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 k, q: z4 U/ }3 G1 m5 P& v6 G
MCASP_RX_MODE_DMA);
/ f# B4 A- x% h2 R6 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 j( y. y! F& e1 n' z# a: zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& ~3 U& H; I' [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - ~8 m) C8 l1 Z/ {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& g/ w- y" p6 l* A5 V4 G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 C v$ n* u- n* g6 I. P- zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ o9 |, J( D: r0 I" a3 o7 i8 VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 Z3 a% W( {. ]; fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: m) d6 M0 X L+ D: M- s( HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( i+ x3 t1 {0 s( H0x00, 0xFF); /* configure the clock for transmitter */
7 p* D4 }1 u& g" uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ i) Q% Y7 i! _0 s' P; mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & m# v8 p6 X5 z% x2 o0 {/ w( [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. F* e$ t, i% n* w1 M- o9 k! a
0x00, 0xFF);
" D: E! ]% [* O0 }& F; i# {( T1 d
3 ~1 t0 v! Q- b; o% A5 s/* Enable synchronization of RX and TX sections */
( _( j) l2 p2 m5 }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 m- @5 z6 D- ~( XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# q! B- J" F4 N7 f4 O: a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" K p( B# w1 ]( d1 T- h** Set the serializers, Currently only one serializer is set as
9 Z, t6 E% Y* a** transmitter and one serializer as receiver.
9 `# E7 k! r8 p. m*/9 |/ I% Q- ^: L$ [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ i1 U3 s% O9 V+ q2 l! K( q% hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 [4 o7 I$ i4 `+ @7 |9 j, I' W
** Configure the McASP pins - M+ @2 N# c e1 i+ v: u* X& {
** Input - Frame Sync, Clock and Serializer Rx
- P# |- ?" n6 ~0 L** Output - Serializer Tx is connected to the input of the codec 3 b. m" `( }* p( J8 J/ K; G
*/
3 ^8 H3 l8 y8 I' c2 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# ~% B, s3 E7 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 q4 A# R/ o+ E; L, v9 f. N7 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( U/ B& C" F1 g O' P/ d9 W
| MCASP_PIN_ACLKX
1 C5 w- L& V# k |7 J| MCASP_PIN_AHCLKX$ b1 M8 d* Y# l' P& L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 |: @1 b0 h ]* Y6 H$ T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 x m9 f d4 x7 f| MCASP_TX_CLKFAIL
+ c: y/ I$ k1 {4 }# l| MCASP_TX_SYNCERROR
5 r O0 `3 x. D0 B* K# d b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' x7 O; S- U3 K$ d9 o| MCASP_RX_CLKFAIL
. {* @2 f; w) V| MCASP_RX_SYNCERROR * ?3 f9 `, F, V* Z0 v3 s, T
| MCASP_RX_OVERRUN);/ v- O5 h R# k7 W8 J7 N
} static void I2SDataTxRxActivate(void)
8 P9 \4 O. A( z: B- y{
! M B" W' C* z2 k1 h/* Start the clocks */
. f; k( u; {+ Q, P( Y) aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 _4 Q! G' k1 S% V: g" Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, D1 h4 v4 A2 [7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# r% d: _6 s7 c- x4 `4 k
EDMA3_TRIG_MODE_EVENT);
S0 z& X2 Q( y5 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- w/ Z& n" o: m; [) y1 K; ]' UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* s$ ]) y# M5 w! ^* \9 ?) IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ z( B5 u: o( K1 p) R& f$ n3 P# l; FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 P4 w0 f+ g/ V) d* h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 H* k0 J. s$ c* z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ o9 ?9 G/ O3 w+ T4 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 `/ P: g+ }+ A/ |" K7 g
}
* ]% B4 u. p9 ]* E) D: H z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * ^+ L$ r v7 R) p7 C: o9 Z( U( ?
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