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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ ]. J9 z1 a1 N5 `- n4 P
input mcasp_ahclkx,4 I/ A3 U" N5 }3 K- c
input mcasp_aclkx,1 `* B* o7 `! C
input axr0,
; ~: D- Z7 [( _2 h" `# z" g+ H. u" v: c5 O! c
output mcasp_afsr,2 T: p0 j! d/ @/ m5 |' l' ~% j
output mcasp_ahclkr,
% _% \/ E0 t% \ i% u+ h7 F, ]output mcasp_aclkr,, B' Z" V1 K) I# K- u; W
output axr1,
" Y1 l# Y4 T% ?8 B assign mcasp_afsr = mcasp_afsx;( j4 ~% l, X( z( w1 L- M/ T+ H
assign mcasp_aclkr = mcasp_aclkx;1 {) K- u$ C7 O2 \" m( L4 W. x
assign mcasp_ahclkr = mcasp_ahclkx;, ?4 t# x2 e) j+ b. o
assign axr1 = axr0;
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$ o# P3 l' M9 K8 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 z V- n: C9 w3 D8 ^% ~* m* J% W4 r
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);: }: T) Z, H% l2 T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& p1 v. p4 F% M; w. M" O* W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ x9 C9 x+ W- X/ G! x7 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* j( g7 G5 s; e2 Z1 [) a( k# v8 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 o! F- {' D9 T* l) W" O
MCASP_RX_MODE_DMA);! N+ }& H7 O0 {# j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) `& j& r7 j6 @" G2 k) b5 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% _- d$ t& N; f: X$ L2 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , e& ?4 e; P& P, s. P' a! v( F5 s4 o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' r+ m. j# |& H% m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( j% P5 \- M+ X% Z' e5 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. U: {9 F' I* }! \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: x+ {) X, D5 c, n( O; V$ IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ p0 t4 F! i& w4 @% pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 S& R- r0 j. |! f. h
0x00, 0xFF); /* configure the clock for transmitter */7 o' n' J. Z2 k0 O l. J. G* ?. H8 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 D* G0 W0 }9 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 O) a9 Z8 x( V' L3 q- i4 N8 U) [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 E3 O J5 _. g. p; J0 s0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
+ n" E& W _- a5 t) xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; F( q$ ]) T7 C& \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 ~! W# d5 B2 _, @0 w& aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 l- {0 b* j. {+ k) x5 [1 a: t1 D) o** Set the serializers, Currently only one serializer is set as( U* d+ X! O+ t0 _4 j& U
** transmitter and one serializer as receiver.' m4 U% i5 X$ ~- ~1 a2 S
*/) [' o1 T, x* H9 h, l: `4 V& w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
B% y5 e1 m+ h+ @* t0 o0 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ @% E) s! N3 z* b9 x3 R
** Configure the McASP pins 9 R' c- E& ]6 ]# e0 g. E4 c- t% m
** Input - Frame Sync, Clock and Serializer Rx
8 s% x, l& I+ R& [! h# h$ x** Output - Serializer Tx is connected to the input of the codec & s" N& {, B. r% [* i6 Z& o g
*// z7 Q# `+ W: D; C: T, p3 F- B, ~6 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 C" R1 }2 v% G2 aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ ~7 I7 n6 M. F, D; t p9 j# XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ ^, i" @- h! K" I9 p1 h, C* Z| MCASP_PIN_ACLKX+ X) h6 W6 e& {# Q7 c3 L( _' C' Q
| MCASP_PIN_AHCLKX: u- S* [* W% j( O3 F. u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: J3 w/ m0 _/ ~4 f* P$ a! m3 G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) Y" I5 ^: H# ^, v: ?! Z7 e; B
| MCASP_TX_CLKFAIL # p- n% ~" U0 k. n9 C" R; t
| MCASP_TX_SYNCERROR
" A5 j# b7 Z/ T6 ~$ n! F( Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ i: Y% O, j- {& Q3 z, J$ e| MCASP_RX_CLKFAIL
c" p2 w4 p# G! Z| MCASP_RX_SYNCERROR
' H2 S$ N1 k. i% S| MCASP_RX_OVERRUN);
- b5 o- k5 M6 y4 Y) B# U} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
6 ^% g' F9 }0 F% @7 s' ` t, v* tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! S( ?& d, S1 H( f% Q/ E, G; VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% N) {& ~( n2 n9 N7 A9 R( CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 \% v' I1 f4 t, x& }EDMA3_TRIG_MODE_EVENT);* r; m2 E9 Q2 V0 ~! B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 U+ m: x! D9 \' C+ ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 F0 U4 e) ?# ?& a9 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); b# ]2 {5 C/ o$ z7 B# r& ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! @ \+ k* P0 g; Z8 v& `& k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ o5 m' M% ?# L2 KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); I+ Z! Z v1 V- j3 z0 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& D, L4 a/ W) G5 H; f4 J7 i; F
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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