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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- x) r" ]+ l2 |! ?0 \7 qinput mcasp_ahclkx,
; ?( v* }+ ~& z5 U+ W& {input mcasp_aclkx,+ L5 h) L! c% _0 j) \) W
input axr0,
7 ]6 f" m3 n9 ?8 b# k2 Q: {5 n" A6 A6 Z( q( g3 B+ Q
output mcasp_afsr,
/ {0 @3 D0 l, q; P$ soutput mcasp_ahclkr,; H. q( ?3 r8 [5 }2 @! n
output mcasp_aclkr,
# T0 c6 Q" H/ {2 B) C% G; g1 Loutput axr1,
# Y7 L* a1 K; D0 Q2 r4 V; A assign mcasp_afsr = mcasp_afsx;
8 A& V6 X* m$ B6 V9 U4 _assign mcasp_aclkr = mcasp_aclkx;+ S" |; t' b- B1 Z, ^
assign mcasp_ahclkr = mcasp_ahclkx;
2 M0 l1 ?; O& U* z, R3 ?assign axr1 = axr0;
) U, y% ]: v( a' f/ [
7 p3 p0 R/ k0 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; j5 {9 p) D' K h# o* Bstatic void McASPI2SConfigure(void)
/ c A( _. h4 ?; H1 ^1 T{
. f' o, y+ h8 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* E. {4 i% o1 J8 @ s% [+ N% W$ e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. h" ^5 m' ~7 d# g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! x `& E2 b4 k' @ [! eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# h2 b- R6 }1 F7 e8 S& o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 v! p. r: ~3 o: {MCASP_RX_MODE_DMA);8 a+ B) `- u& q" C- z6 k, R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 y x) Q2 i8 P8 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# G/ `5 V9 q" V) z8 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! b6 u# d$ c, u) U1 ?6 ^3 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% `" C! _4 R R9 } F+ k* i! MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 U. ^5 `7 e5 r7 i& f. `. }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- W7 u h: n, ^2 z3 N" P" R1 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 F" ~3 N0 l1 `3 `' g6 z# kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 }3 ~! f1 X4 j zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ [' L" q6 ^3 I+ F& j# }
0x00, 0xFF); /* configure the clock for transmitter */
4 q Q& m# h d* a$ QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 u& y2 r, ~# g& @! m4 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 {; E. C/ @/ ~; O# u* ~8 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 `: u9 A: Q; R6 v% n1 k
0x00, 0xFF);
o8 r; a8 O( y: I7 p" g3 |7 P8 H2 F. j- D9 s4 n
/* Enable synchronization of RX and TX sections */
a9 v8 m) z) FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 x- i* Y2 p3 d( }0 i" g* jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 A2 C5 c' I7 a* y: ?# d% tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ v. H& |8 [4 q- `8 S8 E** Set the serializers, Currently only one serializer is set as
. s- m4 c4 N( k# a** transmitter and one serializer as receiver.# h& _8 S/ Q& P: h. r5 ~5 _7 Z
*/; \2 X% s5 }* ]8 L- }9 f" n i8 ^" m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- e& }+ N& x$ E! B4 T+ Q( M* [ ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ A( r2 y: p$ \- W6 H3 w** Configure the McASP pins
. d" L5 U2 `2 m" ~1 o3 {** Input - Frame Sync, Clock and Serializer Rx' L \" v- A6 ]; _: x2 U6 C0 D+ k
** Output - Serializer Tx is connected to the input of the codec 6 l. h: D* s& \1 p
*/, l/ L& Q% y: s$ ?) T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( w p( C" O z" O" D5 j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" |: V5 ~" u9 i7 I7 P' I: FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 R$ L8 [( o; ] ~% ?* f. r* u) B1 y| MCASP_PIN_ACLKX
6 E" n9 f' O! p/ J0 o| MCASP_PIN_AHCLKX' f3 D; I) { u: b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 Y$ J) S! ^, `, [, H. `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ P5 ^8 ~! P9 u# t5 S* U4 C| MCASP_TX_CLKFAIL
' \( A8 _, q) p8 N+ U| MCASP_TX_SYNCERROR) a) {2 E) a- P( R; X k& \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 M$ s& {+ O% n| MCASP_RX_CLKFAIL
( T7 M; a6 y0 p. u" p# c. H| MCASP_RX_SYNCERROR / ~: w* i! }# @1 v, i
| MCASP_RX_OVERRUN);
8 J: ]5 t8 R' V6 `6 `! z$ y+ {( y( A} static void I2SDataTxRxActivate(void)' g8 r5 g4 C0 p6 W9 j9 a H
{1 [7 T; d6 C) P- @
/* Start the clocks */9 @/ K- P+ i. z7 l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); x- ]" h& R5 _; Y. l# W' X2 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 O6 a! _. W- `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
R: S2 q6 {6 ?% j Z3 MEDMA3_TRIG_MODE_EVENT);) I! W' z1 S# d( W5 w7 ?" {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 D; V4 o& Q& V8 H# N' m; l$ @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 w4 G* l4 }& d) Q8 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 y0 b f" h: i) \8 ~. }- _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; W/ T' C) ?/ A. o4 l# d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" l2 I5 u+ p9 N3 t& r& F6 t, P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* G0 r; c* f1 S# w" W0 F& CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 g+ f; c- y; g. e} ( Q5 {. N; L4 A. l, v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) {- G* g2 g+ f! ]8 m* X
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