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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! E8 J2 |. @6 _# zinput mcasp_ahclkx,0 h1 B5 U0 q& n2 u( Y
input mcasp_aclkx,
0 q' B2 d7 G5 Pinput axr0," D |: d# {# K
/ v4 s7 f) C7 J |: L
output mcasp_afsr,! W4 W- R1 R/ i4 B( t1 E
output mcasp_ahclkr,& z$ u1 x+ u9 e
output mcasp_aclkr,
( N/ N8 V5 z5 D% W) A9 _, toutput axr1,: j$ b; p$ v* m' `% g0 D6 n! u
assign mcasp_afsr = mcasp_afsx;
- d" v! f5 Z% \, zassign mcasp_aclkr = mcasp_aclkx;
) w% T u0 o9 {8 l) O! z' ^6 Yassign mcasp_ahclkr = mcasp_ahclkx;
6 ^) ~& R) s1 i, q q! N5 eassign axr1 = axr0; - s! H/ L. P5 Y6 X
0 _6 X. `7 h3 E V3 U# {# [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ A, x1 H, r: n# A" D
static void McASPI2SConfigure(void)
5 \2 p# s( B) ^+ E; ^, ^{; r' K* V1 N. h% e( P/ b, @3 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 ~1 r( ^' J; k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 f# K( J; D1 ]! G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& C3 b |3 D- c, b7 t, `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' J0 v( d7 z) y5 {; sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. k: Y6 m8 }$ ZMCASP_RX_MODE_DMA);; O2 J2 I3 g7 e9 v3 }9 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. L: }0 y. ~! r3 \) @8 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& r/ l4 D O9 \& b) |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& N& z5 D3 g( w. bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. Z- w. U' {0 B! Y: u) u$ _1 ]( [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " S9 a/ O4 P) [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 X" ]" |3 \* D( p: M9 M# {8 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; L5 g/ ]6 G+ K( o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - M0 v# c7 T( t5 S5 j, K) d6 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( G( ^9 V& k" t4 g4 ~, _2 z; r0x00, 0xFF); /* configure the clock for transmitter */; d3 O8 m, @( T; d4 m9 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ }0 h% l9 W* t3 r, ^, ~" I% _ e5 \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * a$ O; z$ E# u* B. I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 L8 ?* }; ?) p- Z4 G+ h# t
0x00, 0xFF);2 g* c& w2 y1 S. j& o1 u) d: X8 l
0 \7 k/ q2 [9 z6 z/* Enable synchronization of RX and TX sections */ . e( |2 W) D# \0 }$ n4 D: i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 r4 W6 f7 M, |3 ]# HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 G- C: a4 ^0 c7 K [2 D7 Q/ k4 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 a$ u( B) s3 M# b, n% z** Set the serializers, Currently only one serializer is set as
/ l# u* F% C- M9 I( [- Q' }** transmitter and one serializer as receiver.' h% N# [+ F, A4 w+ g0 {
*/
7 g9 U n6 z4 b9 M: C" `" |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 z) L5 Q2 k# Z$ q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& ~0 X" E) @# ?
** Configure the McASP pins
- p7 \2 b+ [% u** Input - Frame Sync, Clock and Serializer Rx) G. t4 _ p1 v4 V& _2 @1 H
** Output - Serializer Tx is connected to the input of the codec
; R, m" ~5 W; V2 q4 {8 q. T7 c1 C. @*/3 H" @& C; }9 r8 Z1 `" u, s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 B; N1 r' i! u$ S4 s! Z2 \: j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& }, l% m$ V8 o, }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
c: Y" }! U1 K8 J* W$ j: A| MCASP_PIN_ACLKX
# f. Y/ H) ^) V2 c# R+ V$ E. W| MCASP_PIN_AHCLKX* a+ }5 g6 {8 \+ P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) u3 C! F; v3 s5 |# p2 t) N _! F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 v* _' C7 J4 a& f| MCASP_TX_CLKFAIL 6 l) ~: P' {4 t
| MCASP_TX_SYNCERROR4 ^1 r* x! `( Y% [/ a9 [8 Y) q% v& X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 C1 ?! x+ s/ K/ t/ F| MCASP_RX_CLKFAIL8 b3 A- _+ b# {% \8 z g
| MCASP_RX_SYNCERROR ; ?/ q8 p* @. v& H6 R J# A7 D
| MCASP_RX_OVERRUN);
4 `3 g. u5 d- `2 z7 o} static void I2SDataTxRxActivate(void)5 _5 r, _2 b) Z- Y0 h" h: `
{& v) y/ V5 w' D
/* Start the clocks */
3 e. \( c. p2 O' r/ [' C$ oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) u3 Y+ E% e2 e6 m( E e: {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& C1 y1 P+ S6 z; g3 ]6 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) r& J2 q5 |0 {, I8 W0 d/ _! T
EDMA3_TRIG_MODE_EVENT);
, a- X' l% c! @' x+ ~' ^1 V$ WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ A# [8 o/ O J% s1 ~ dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ }) R2 q: X( f( Q! Z3 e. M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ?8 n6 W" `# H. S8 L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 J" [9 X! l( A+ Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ `8 i: ~6 Y5 { _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! C5 @% _' c4 k+ ]7 r* e( Y/ UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 C( i, D; n4 i$ }: [& A/ a, ]}
" ?. b6 t, R/ i8 k3 m6 Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; r) @; d: m1 A- h
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