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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 o$ x" N- u; d% @) @9 ^
input mcasp_ahclkx,
3 K) M) o/ v% {input mcasp_aclkx,
2 Z3 e) o8 `* n: e4 s) ?; jinput axr0,% o& e: i$ A% D8 M
+ D I" m3 Q) [" f1 Ooutput mcasp_afsr,
6 g7 h+ X. g9 T0 }output mcasp_ahclkr,/ ]3 W$ ]" e3 Q1 B% q
output mcasp_aclkr,, n4 b! y. V9 S
output axr1,* e+ ?' f$ d& \% O6 v: |+ Z
assign mcasp_afsr = mcasp_afsx;$ K* a0 R, v& f6 }. W
assign mcasp_aclkr = mcasp_aclkx;( ^0 Q' K7 Y$ I; E
assign mcasp_ahclkr = mcasp_ahclkx;- E; d, J9 m8 i& n8 i/ ?; H! u
assign axr1 = axr0;
% n( \% Z8 L5 E, B; r) }" S2 u, C
$ E2 Y q/ o5 v' u/ T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% S: g9 V9 A9 O. b+ }- ?8 p5 jstatic void McASPI2SConfigure(void)
: ]# k7 h$ U; M{# B7 P6 ~" ^1 U2 H/ J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 T6 c% @+ K3 ]9 WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 d# a9 s1 S" U& R! o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 f( ^1 S0 `( H. R% g8 s# |# a" UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" a# b) z/ h8 ~8 e( n/ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& k2 ^+ \- q2 X
MCASP_RX_MODE_DMA);& _9 H* V3 B; q% u% E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* l& c3 X8 L% f* iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) ]6 m `( ^& [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 W& Z" M9 b2 k8 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ f1 K. ~- s& [# Y$ i1 h/ q9 q5 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % p3 c$ ]6 A; p' v1 d: r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# |7 C8 I4 p) B( \' l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% g8 c+ S1 \) M5 f& v& s k: V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' i. l+ O; d& z. m+ tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! T- p) U% r; x) e f; N& f
0x00, 0xFF); /* configure the clock for transmitter *// T2 @; @2 P6 ?! N5 A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* K J' b6 y* L% \5 A$ y5 z+ FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
|" Z+ t$ W# X! Z( [ b- Y' gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 Z6 |# t* V+ a; G2 G2 v1 r: i0x00, 0xFF);
! p" q4 K _3 f9 l( [0 q; ~9 O5 K% {: I
/* Enable synchronization of RX and TX sections */
1 ^ Q' {8 c v* [* ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 {/ O( X) {: G. M1 `% N7 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 g+ C# G$ t! b2 v1 F I8 lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ f+ c6 b3 g* c. f: o2 j# P, K. Y$ T
** Set the serializers, Currently only one serializer is set as
. L( z1 \) x9 C, }% O1 {) C5 B** transmitter and one serializer as receiver. f/ |) i! z! `0 C
*/
+ ?7 B/ ]2 h" U- r% aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, E4 P m' j( _' T" @" ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
E0 C& F; t+ G* z** Configure the McASP pins
" ^+ E1 z" K4 X" f7 d- k** Input - Frame Sync, Clock and Serializer Rx; n2 u/ I6 ? V% H6 k1 r! ]
** Output - Serializer Tx is connected to the input of the codec 6 E! s p8 ~9 ], y
*/ ^& ]: B& o, |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 H- D3 A( V4 {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 F) \/ t F2 G% JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# X/ Q; [5 S) h' I3 ^- W
| MCASP_PIN_ACLKX
% g' O) Z/ A9 `! K8 ]9 X6 e% J3 b4 g. N| MCASP_PIN_AHCLKX) ~( d. ]& g" ?5 ^' @. l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 Y; \9 ?. I: v, ~" ?/ ~7 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 j/ x7 J8 P: B' N3 {: C) E, i. b| MCASP_TX_CLKFAIL 3 H ?/ j2 n' s
| MCASP_TX_SYNCERROR
0 d( _( b+ n( s) m! ?. ^( G! O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # p* A. |% |( [4 x
| MCASP_RX_CLKFAIL% D/ G6 R! d# H1 i" L. \0 a
| MCASP_RX_SYNCERROR
( N: t: H- h3 P3 t| MCASP_RX_OVERRUN);+ l/ u: U2 o. U" R2 i. r6 Z5 ^
} static void I2SDataTxRxActivate(void)' v: b. f6 z4 X7 I- |
{
) o* b0 P; o- V) q& a: r6 y/ P/* Start the clocks */. O8 O% x1 z6 E% H1 _, d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: u% ]% l2 C3 o& k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- b- N% c4 t- `+ m4 K' {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" P( R6 b+ p% EEDMA3_TRIG_MODE_EVENT);
; o2 U' E1 b( F; ~$ [* \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & x) a& H9 T0 x5 W+ g' Z7 Q9 q- b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) X" ^- x* @( V& M$ n0 _5 xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ i% ]( g! e, y( ]8 ^# W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ S4 h8 s7 S1 d4 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 S# i$ ?# T$ v* _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- |2 S5 r# w+ y& H8 A& U. D- |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 f4 m# t6 M9 f* Y, T
}
- _+ L' b$ Q" H3 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. D2 z- K; H/ L1 d( I2 x5 ^. Q
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