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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# {6 {4 _& e9 l: B' qinput mcasp_ahclkx,
1 x; {' l6 R4 t$ c9 [# ]input mcasp_aclkx,
2 w4 \3 W0 {( q/ u7 G) xinput axr0,
0 Z. d7 `6 i& N3 }8 L3 C
- s" ] P2 [) D; H: O4 joutput mcasp_afsr,7 e# r5 U6 |8 c1 M- e
output mcasp_ahclkr,
' x x8 w3 t: L8 Y. f7 l$ {output mcasp_aclkr,4 Z W3 E8 k/ A; j
output axr1,
6 V* D9 [" Z, v assign mcasp_afsr = mcasp_afsx;
0 Q& _. [% j' X! Q. Rassign mcasp_aclkr = mcasp_aclkx;
% S% `1 B3 \) v0 X; Uassign mcasp_ahclkr = mcasp_ahclkx;
; l$ G- c1 k1 { p: n- m! Xassign axr1 = axr0;
4 Z4 r8 K0 K- l6 [) \. o3 k6 y# w3 F3 q( k% G6 C( _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 q) j }$ Y' D' m2 Rstatic void McASPI2SConfigure(void)
2 S; G; L, c! [6 I{1 `" w( T2 I& o% O' ]' _, O2 v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 n( o9 `, m; z( @" f! N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 `4 S, C# J; ^# y4 A8 B/ R" P8 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 j F C5 E1 F0 p+ I" i- e8 e) GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' _ G" b6 g+ j1 r& r, G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* n' `" l" L2 L% Y5 A8 b, WMCASP_RX_MODE_DMA);
9 ~; R" k) C0 R9 _0 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ^, d$ u9 i( Y/ V) }( N! J# j" a5 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 i) ~/ ^+ G E; \& r5 i5 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ ~$ b& i! ]8 ~. x2 w! RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 t9 p; i$ O! Q+ e3 ~3 l0 S( ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% ?8 B _" D6 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" Y; l+ Q0 }. d+ E5 FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. S4 m6 q7 |4 k0 A5 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% U5 U" {# |" s- T |- {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 [% d6 W. d$ ~# w( |( S7 m8 u* M0x00, 0xFF); /* configure the clock for transmitter */! \& E3 Q! {% r' |9 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
J4 d8 O6 r e, `5 k! Y* @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) [, v' @, j/ o& Q; KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ P6 R0 S4 ]+ E6 K0 a9 ?# h/ ]+ }3 \9 h0x00, 0xFF);
( a8 z" w$ [+ s$ P7 j" \$ D* w& Q \' s$ h% M$ @. L6 D1 N
/* Enable synchronization of RX and TX sections */ 5 |" U( u$ z) E. V, _1 S3 g6 J8 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 Z; ?( { U3 \) o1 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* v8 I7 }& f y3 `2 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** g- r7 @) U2 V7 H& |: d9 G3 T3 U1 S
** Set the serializers, Currently only one serializer is set as
( r; ^$ ~' c. d5 n' o: W. a8 u** transmitter and one serializer as receiver.
$ ~/ K) U: G: f' q) @*/
3 W8 ?& ?4 U) W* K; |: uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( f7 \3 Q; R, O8 g3 N# T9 z& ~) G _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 X7 }' y/ o& W
** Configure the McASP pins
6 K ]: A# q0 ]. m2 m** Input - Frame Sync, Clock and Serializer Rx
. O6 v" s3 n. k# R: w4 @$ x** Output - Serializer Tx is connected to the input of the codec
" X R9 Q$ }, N; P. G& \*/, ?2 Q3 j3 I0 A0 d, \2 ~# K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" w- @5 S" a/ k; y, b/ TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' L+ {5 k. [3 K# k M; x9 t% z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. L! X G* V' ^* ^
| MCASP_PIN_ACLKX
' G, _. U% U. a9 _! u& n# F| MCASP_PIN_AHCLKX8 J* c. [$ n* B$ \6 Y1 g$ x& W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 q7 B: V% j* ?% h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 v9 B1 c" w, R2 l; N0 f, r( i) G
| MCASP_TX_CLKFAIL * e, ~) y! k% _
| MCASP_TX_SYNCERROR, q3 k; \8 s/ n+ Z( [7 Y) Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' n+ [7 a! \' q- F
| MCASP_RX_CLKFAIL3 f2 y( W7 c9 y" A) ^+ W2 Z. A
| MCASP_RX_SYNCERROR
' r9 Z1 z# s. @| MCASP_RX_OVERRUN);
4 u9 A) b' u9 Y' R1 w} static void I2SDataTxRxActivate(void)& ^2 r$ j4 D4 v) ?1 T
{# |1 G5 l8 F6 K3 B) \5 X
/* Start the clocks */" N8 {, f) |( s+ c; [3 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ k& L& S$ N6 A0 I: R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, U0 n7 t3 m& A4 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: D, t5 M, B$ { f/ o9 [2 ]EDMA3_TRIG_MODE_EVENT);
g9 w+ ^6 }0 n2 a9 d5 T$ p0 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 Y7 ]* z& F" ], u2 D$ rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
G+ |; g0 b5 E. GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 d5 q! z/ J( u0 H, Q3 A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% v5 A9 s+ `" d" Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( J D' H6 L- x. i6 E6 I+ x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' z) z8 E* w' F, y. e, G: \, P+ vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; n2 ], `! o, ]+ X* {( W% q}
2 [# [! j0 O5 R. Y7 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + O. \/ Q, A, p/ g3 n
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