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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! u/ J( |" ~) l0 o2 z% }input mcasp_ahclkx,
: X( l, j2 D4 E$ Y5 d+ h* [8 Q$ Ainput mcasp_aclkx,2 p1 k% I* J) K# g$ N
input axr0," y* e# p$ V- X5 A
, u9 n- C( J4 L+ ]2 x% W7 @output mcasp_afsr,
6 ~/ Y4 r# W: }7 X8 v9 ~3 Doutput mcasp_ahclkr,+ d' I V4 i8 I" o
output mcasp_aclkr,' u8 _& k/ G' Q* [8 U( w1 O. j
output axr1,$ q4 ?* ^5 M* f0 r$ H/ Z0 e) b
assign mcasp_afsr = mcasp_afsx;
: K: }1 F" N0 P! o8 Q4 sassign mcasp_aclkr = mcasp_aclkx;
$ o! Y: O% u, U) @/ Passign mcasp_ahclkr = mcasp_ahclkx;* `' s9 m3 w& M% H! P5 |
assign axr1 = axr0; * `3 J: O; \2 r) t' I4 p
$ Q: d I" d4 ~8 T& E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 s) C$ s; P) E5 G- n" Q7 K3 M+ Qstatic void McASPI2SConfigure(void)
) u1 j8 B. L+ X5 G7 H4 L{# I: z( M# T7 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, a& O* H! h+ ]. |5 T3 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% [$ C( ~9 @" j3 W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 Y9 H T$ P0 F9 D+ AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ X9 v( v. c) H ~# x. F& kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 C, ~/ B4 s9 f P! wMCASP_RX_MODE_DMA);
T1 l7 [. @) S. @9 Z$ x5 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) V0 _1 z7 {; o% O/ q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ Y1 }+ f+ N' Q7 X8 B7 o& p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 K, @' Y: A8 ^5 x% l! u+ r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 }3 Q6 T$ k$ W2 w" b; W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . d, F/ [$ @1 q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- k+ N, P5 [4 K$ q" KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) d. ` O! B( W! B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 [% v# o& @- w* SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 h, C! c7 N0 x8 [! o/ z: v. |0x00, 0xFF); /* configure the clock for transmitter */! a* I2 p/ G2 X% U2 a5 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: r5 A7 L9 e1 I& z- u3 d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 T7 F& K% `( d4 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 k9 m" Q$ g! p
0x00, 0xFF);
. L- V/ A6 K' C; d% M6 X$ |$ P8 A0 H& U6 t
/* Enable synchronization of RX and TX sections */
% F: f& R; i, @; k G- YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; `. X0 {& G$ ^' c# w6 H5 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, A, w% d3 E2 f; d# M- XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 h* Q0 ?: ^& T" y
** Set the serializers, Currently only one serializer is set as
/ c# }3 U/ @. H. g** transmitter and one serializer as receiver." l. ?$ V* b8 D1 k) N3 ~) ?& ~
*/4 A+ n4 j w2 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; w% ]! _+ u* `4 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ g" p; Q, q9 W3 O' ^) j7 M# n' b** Configure the McASP pins 1 H2 p5 V' s9 ]6 W
** Input - Frame Sync, Clock and Serializer Rx
" F* y0 [ q1 D** Output - Serializer Tx is connected to the input of the codec % i: J* p" h, ~; ^ d
*/* K# Z4 E, [+ b8 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& p2 C% S1 o! F* R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ V: A1 r8 m9 y# MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ s$ G' L3 I Y4 j3 y4 m: z
| MCASP_PIN_ACLKX) R; |8 k/ s! y$ k
| MCASP_PIN_AHCLKX; i6 ^. |0 r% p: W7 c L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 Q; v3 ~" W0 S4 D* ^- o* ]2 G/ cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR g/ [2 |5 o& ^. X$ T
| MCASP_TX_CLKFAIL ) ]2 z* x& b) R/ \, @: I# p! [5 d$ [* y- R
| MCASP_TX_SYNCERROR1 U6 k" _# L3 P' U3 x. [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % w! }! w0 I" A8 i5 r: q1 ]/ S
| MCASP_RX_CLKFAIL( ?1 }2 b6 |8 g7 |3 ]
| MCASP_RX_SYNCERROR
9 \5 c$ o3 f$ f/ O| MCASP_RX_OVERRUN);
5 h; k$ a. u a' h2 G7 c( |' a} static void I2SDataTxRxActivate(void)9 P- ]$ T& ?7 Q, m9 r1 j
{
0 e1 [; e. D$ w3 k+ i" |' Q/* Start the clocks */# F1 I4 C$ `% h9 {! B- d, G$ T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! ?/ E7 K; t. o- W. F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 R1 ]/ }9 O& {; a) n. U) u* G' Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ z( `3 ~9 Z8 B# s' l: U
EDMA3_TRIG_MODE_EVENT);
! ?% Z4 [2 W K2 ~; s, V P* `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % E* @+ m \& `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* Q- E# f: `) w0 s: Q# |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); [9 r; l4 G6 A' i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. E, k' [% Y0 G. n. Z2 v8 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ d) L; S# k5 M' j/ Z8 EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ i4 d$ y. k7 E* K$ z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ f' ~" @( w% [& w+ e" G0 p
}
. l& m7 E% R/ d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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