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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," l( a6 k' o8 q/ o8 j
input mcasp_ahclkx,7 F4 R- e7 V, z+ z" U3 J
input mcasp_aclkx,( h, d# A* A( x7 R. X1 _
input axr0,- e2 w* w& }, ]+ }7 S" n* e/ R S
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output mcasp_afsr,
1 M! y$ Q. p& Xoutput mcasp_ahclkr,
0 ~( @4 n5 X/ c5 Xoutput mcasp_aclkr,! U0 k q4 I5 v; {! H0 G
output axr1,
/ j y8 `6 o' h# J, {8 @! ^( S! ^ assign mcasp_afsr = mcasp_afsx;
+ M) v7 H* _* e" P$ z' Passign mcasp_aclkr = mcasp_aclkx;7 b, x( W4 i) ~" K( V c( v
assign mcasp_ahclkr = mcasp_ahclkx;5 Q0 b: O# U: t! E( T
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! Z4 m! [$ J( d/ I
static void McASPI2SConfigure(void)1 `: }& v/ k- `' q
{
U+ d0 y c3 w8 E. w7 M+ JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 Y5 J# Q1 J/ K3 d4 y" d/ TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" P+ L t+ L3 }& k. Z. w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# p4 N9 v, ~0 L% p5 V1 ^! j3 l! [, S# |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; s8 R8 B9 w8 c' {# c( V& P' j- FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* E. {1 n. J% _, \" }& c
MCASP_RX_MODE_DMA);5 B; h" p7 d' h) X5 s4 N7 A1 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 u3 `/ S& i1 w3 C5 W8 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, R5 V/ H4 a3 C; X' g. V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ u1 F2 c, X2 N3 x" yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 ?2 j1 v; G2 S" W2 p. ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' P _' D6 {' w8 r0 A) z, @! jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 C4 o6 f S+ K6 E1 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 L% Z" _: i+ }( i3 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / R9 ^' _' k, q: B p) E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. B: \7 T, x# b8 r1 a: F
0x00, 0xFF); /* configure the clock for transmitter */
0 y- R3 b; P! p, U' ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); Z8 m' U& J3 t* o0 Z& }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 j6 s% e9 s( A8 s; c% ]( c% r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 b5 B, R; [9 m- f2 y0 d
0x00, 0xFF);
0 E9 n$ E x/ W, l+ K1 j# Z& m0 L3 e8 W8 p( P" U! I
/* Enable synchronization of RX and TX sections */ - b, Q% W% ?+ H+ j: E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 L3 [2 }7 L$ T. x% u- K- U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# w# E o+ `, C4 z1 Y: [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# x3 P& k6 R1 J% `/ L
** Set the serializers, Currently only one serializer is set as" l% @. D) c7 D2 {3 B# L
** transmitter and one serializer as receiver.
3 u. O. j5 {( V2 C7 O: J*/
% Z+ d* o# \, K; K7 R& s. c3 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 ]0 e; @" l8 H5 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( h( N2 ~8 D; `7 n# H) `** Configure the McASP pins
" h% M$ L/ D0 j0 b7 \** Input - Frame Sync, Clock and Serializer Rx
4 M0 I, I) ?+ Y) |& G** Output - Serializer Tx is connected to the input of the codec
1 R$ W" K2 e! p! }' U*/
7 h8 L- k, o9 O% H! o/ mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 F& b: l5 Y- s. M/ H1 o C7 z% |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 }3 _* A8 U& C0 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% G. |; F. q# q1 }6 r( h5 p/ J
| MCASP_PIN_ACLKX
/ f$ \- r* n x. z| MCASP_PIN_AHCLKX
6 S1 m u3 w/ T. P8 `& @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ A6 E/ \8 q9 k- WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - M9 s( H8 A$ ~
| MCASP_TX_CLKFAIL 6 g7 O( e- x3 Q' r
| MCASP_TX_SYNCERROR: i" N3 y3 A* B2 F6 U$ i& \% h" c5 s; w9 `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. U& U% G# C% {( c1 j$ q' r| MCASP_RX_CLKFAIL3 u& w5 Q3 N. N" z/ q1 J
| MCASP_RX_SYNCERROR
; e3 m$ f4 f9 t0 p| MCASP_RX_OVERRUN);! K& `6 @& v/ D e! ]
} static void I2SDataTxRxActivate(void)
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+ D$ i ]3 p- U- H1 g/* Start the clocks */" R( U6 C3 e, p/ m* g$ h* F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 z5 P. O5 a: H9 |8 ~% iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// q6 i1 r+ @) k) x) m, h3 g6 z2 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. ~1 F a& C3 m4 K% q4 L7 A. N' I
EDMA3_TRIG_MODE_EVENT);
7 C8 {; I B( [1 x2 p! BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; S' a+ j' S& k, q% t; ~3 XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) _1 d7 a& j% L7 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* q d, Y$ U& j- fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 \# U c- Z" I* I0 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 I/ }8 i( v$ f! f0 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ M: c0 C8 ?* o. [. U/ j8 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# H) f( ?; C1 a# N. b) W
}
5 G2 Y- E+ \, u4 L6 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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