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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
B5 R4 B+ S5 i& J3 J$ x: oinput mcasp_ahclkx,; R$ _8 Q: ]6 [
input mcasp_aclkx,: ]$ q# y, F( [& ]( B0 \: E
input axr0,. S/ ^; x% f; K5 F2 Y. @2 p
: v/ @$ m9 f4 D: c' ]
output mcasp_afsr,) f6 R& R6 Z1 s- f3 A
output mcasp_ahclkr,
% s4 ?1 I: x _/ T& ]+ y `( woutput mcasp_aclkr,
1 h2 L6 C6 a) A9 routput axr1,
' g, r- A5 M8 ~ assign mcasp_afsr = mcasp_afsx;
) t- l8 u U; I* rassign mcasp_aclkr = mcasp_aclkx;# f. C1 T3 c- n$ `7 r2 \" ]" [
assign mcasp_ahclkr = mcasp_ahclkx;( {9 B7 e2 R" F" U; y/ s4 ]6 k" K
assign axr1 = axr0; - c2 _) _4 l6 O9 R
: I4 q7 U. J: ~+ @4 A1 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: ^' m5 ?" g& J7 ~5 Z% u |( n9 cstatic void McASPI2SConfigure(void)
8 _9 |# U+ S) l{- B: t& k+ t! ?3 m7 r. E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 p% K. H! L" t- J/ @0 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# j4 Q6 S2 d6 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. b4 a. d9 r2 r1 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 t, v! [4 H* p: k( r4 S& N/ n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. Z$ |3 c. n* o* Y3 n/ ]3 p
MCASP_RX_MODE_DMA);/ `( X/ O, b7 Y+ a! d3 S( S7 i0 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; f* I) s$ s9 G" o' G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: H( s1 j, y# B# k2 g/ n$ cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ ]) y( f. A) d9 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# ?' m0 c) @( e' Z0 o# bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / h* D% U% G* u7 {( ]2 M3 j0 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! w( a: \* e3 Q# g' }5 ^& D8 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- z0 c% g/ _- O) Z7 u+ A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 R$ y. J* E3 X A9 _. mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 O9 V( C! q( N0x00, 0xFF); /* configure the clock for transmitter */- l7 {1 @9 C2 i7 _5 {3 \5 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# ]* W* j) m7 }6 o: w3 `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. z& ]+ a; ?0 L, Q2 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. @) `/ G& e, j; ^
0x00, 0xFF);
0 j) w" k* M( i3 o ]1 b$ \% b7 M3 h3 x& G2 d6 j
/* Enable synchronization of RX and TX sections */ # t; u7 _; T" {8 Q2 A0 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: G- S2 x) x e8 g9 T6 J1 w; oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) }- o" |$ V7 l% o8 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" Z& a% @1 w8 x- E
** Set the serializers, Currently only one serializer is set as
3 Y/ R; M0 ^, j- s9 M5 }** transmitter and one serializer as receiver./ k, w4 @% U! t/ f; z
*/. i. V8 f- e i; ^0 e4 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; `: D7 S. c/ c; d8 w/ U1 F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% U% a, ^; m1 i, R5 q7 |# x8 @; Y6 Y** Configure the McASP pins
5 ]' G! W' j' c! W2 w9 \** Input - Frame Sync, Clock and Serializer Rx
! Q% }! u: L ~** Output - Serializer Tx is connected to the input of the codec ' j$ T H6 K) q9 l/ @+ M& u% q
*/! i) S( Q4 \8 `9 }9 Y- a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 f% u0 Q0 L! l& _* SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 [6 ^! f+ p: L- G% p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; u7 B' K" r& H9 J( U6 B0 V, v| MCASP_PIN_ACLKX
* b, @, S( H/ y& S2 U C| MCASP_PIN_AHCLKX5 w% v) U6 }, p$ [, ]/ V7 h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* k9 U0 j0 h8 S2 f" q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* l8 J% V8 @0 i& M( r| MCASP_TX_CLKFAIL
% F2 f$ K6 j) b# Q s! _' Z+ P| MCASP_TX_SYNCERROR
3 s) j- N3 k, x( L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 ^# t" B1 m! v B& L
| MCASP_RX_CLKFAIL
) ^1 b" [7 a) F& s4 }. J% s; v| MCASP_RX_SYNCERROR
( f" g& I) g+ G( L| MCASP_RX_OVERRUN);, Z" [& j i. I) Y) O7 y
} static void I2SDataTxRxActivate(void)
" }- x9 I3 Z2 h{
7 h# n( O& T9 @. t: w0 l/* Start the clocks */
, A9 c/ u) R" fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* w; r! C; d% r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! |& f- z- H0 f: A$ d0 `2 q( ~+ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 f2 Y7 Z, R0 ?" S: N a8 p: wEDMA3_TRIG_MODE_EVENT);
: h2 {3 [, K* h- b4 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! m( z4 b5 n- q/ ]( f. O- {, \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 p2 M' f/ E" [2 n9 j+ h6 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' Y. C2 c) Q0 m2 ]" l& h+ ^0 x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 z* P4 H$ g0 d; a W" i; Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 Y% M0 V) `" V7 s4 p: u- _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 Y6 _9 Z( e3 k$ M5 A9 P* oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" g E7 v% ]: T1 ~7 I
}
( e4 J( H. }" O: ?# E1 {7 t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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