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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- G9 c, e" C* C
input mcasp_ahclkx,
$ V, E2 S, I+ \7 Linput mcasp_aclkx,
. n+ N- j6 B5 m% y; w7 r9 q( winput axr0,
9 O: B; i2 z& P* z9 k n c
6 n: D% M! }8 C3 T$ poutput mcasp_afsr,
) ^0 ~- n8 b- l2 W0 y8 r0 Poutput mcasp_ahclkr,+ {8 v- ^" \' D: Z
output mcasp_aclkr,3 F( Y& ?' q8 Q% m( J8 l& D
output axr1,
1 u4 U/ ~7 Y: ?! t3 m assign mcasp_afsr = mcasp_afsx;
+ Y; W9 P) {7 v& b) @assign mcasp_aclkr = mcasp_aclkx;1 n( r& U7 m9 z3 x# a6 p
assign mcasp_ahclkr = mcasp_ahclkx;4 [: \& W# B+ r: E m* ^1 w
assign axr1 = axr0; 2 T# V( J" n0 f+ N& G
1 ?$ v8 i- p a, f# m5 m( \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % H4 U" g D4 E! f3 ]3 ^8 ^8 v8 I" O% V
static void McASPI2SConfigure(void)
h/ J# E, r) x; y# a( ^{
+ p- V: d. x6 n: M' c6 R2 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 w/ B7 z" k- [+ O, x4 S( G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' H0 d! W( V; f |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; c3 f, j8 c7 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& S" r. F0 K$ @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- P6 C B, r7 x2 s
MCASP_RX_MODE_DMA);
! K! @- ?% f' V1 J, @2 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 |- l3 a6 U4 F; R7 H+ t3 ~% o1 bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 T4 }" J D4 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 E: [1 Z/ Z$ @$ B" t& w4 w" ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 m& w0 }9 r5 b# k4 x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) o. _0 T' ?8 b2 C0 R) iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) ^& `& C) t" R4 i- ~7 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 |: G5 t% e% x' k2 j% kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
^ j8 m' v8 l* ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ u+ r, Q) l7 v, z/ u5 l. f0x00, 0xFF); /* configure the clock for transmitter */ `3 S8 E' x) [* G; x0 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
[. q% F' o: dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + q% b+ E( d- K1 H: U: a$ `) n& S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 n$ }2 Y, J0 K$ u
0x00, 0xFF);2 F8 y$ `2 x( p, x% C9 R
* p; ]0 l9 I7 d
/* Enable synchronization of RX and TX sections */ 2 ]2 B# @7 ~5 q! q( }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: Z+ r+ L7 g \8 e7 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; a" w! Z) E' l; d( \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 ]+ \9 p" L8 C2 l- h0 H
** Set the serializers, Currently only one serializer is set as$ |6 B* u: _, R# `& E3 p" u
** transmitter and one serializer as receiver.
5 E( n4 A# Q& L( L*/7 v" n# S5 y E, L; k3 e* Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 ?) I- w4 O T+ K$ p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 Z2 R1 O2 S1 v d M
** Configure the McASP pins
4 U; _# d" D& I b+ W: X: f% D** Input - Frame Sync, Clock and Serializer Rx
{: w% u2 p( y+ F! K' L** Output - Serializer Tx is connected to the input of the codec
' W5 _' C8 E+ ~* g' q*/" V1 J1 ^6 ^3 k2 M% T- o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 n" [+ s7 z: XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" \! h2 G, X; {# V% ]' t/ X$ I3 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ ~5 D6 ^5 q% B, {* ^/ v
| MCASP_PIN_ACLKX
, q7 ]/ L' m- B+ L4 p+ s! x| MCASP_PIN_AHCLKX
/ j8 d, f" [" d5 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 P7 Q' {# h' q' S* r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- ?8 e# s; G/ H3 K4 P1 B, j| MCASP_TX_CLKFAIL
4 }' B- D( j& z# z6 l# m9 W# P) Y& t: v| MCASP_TX_SYNCERROR
0 a# t* i: J6 M0 h) W/ i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! V& v( a( m: V& s; G& A8 t; `
| MCASP_RX_CLKFAIL
5 C, V7 i: b9 u: F| MCASP_RX_SYNCERROR
) U4 l$ z; s7 I. d* W| MCASP_RX_OVERRUN);' X D! v9 R0 R
} static void I2SDataTxRxActivate(void)
9 E0 l2 B0 g, Q5 b7 Q M{3 v# w, I: A; }* A4 }3 T7 f: }
/* Start the clocks */6 {- {% h( `4 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 q# F/ w- H; M- I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 e4 f$ L, `4 _/ a9 z1 d; Q. Q$ m& s1 M1 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; T& T5 c4 B) ^+ A
EDMA3_TRIG_MODE_EVENT);
k# u3 e; Q1 }5 j$ M X8 w% T8 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ V& c: b6 i6 W: h& U* m6 J, nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. h" V5 R0 j8 sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, K/ Z% _- U# b0 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 ~$ c8 H4 _: h2 b* rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 B0 R) V9 T4 F; X+ S# xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 K! \0 h1 z7 m8 R5 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( G7 t+ ?" ^3 j8 |7 {# x
}
4 \8 z. B; e0 O3 v7 _* L Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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