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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 L {. [. ?5 C, w
input mcasp_ahclkx,8 C, O# B5 n4 C4 y4 K8 v9 [+ {
input mcasp_aclkx,
; T, m4 ?: @! k9 Qinput axr0,
0 k' j5 ~$ v9 v8 h6 H) {2 X2 e, D* O
output mcasp_afsr,
2 M" ]- m( |9 Z5 coutput mcasp_ahclkr," M" V( j' w0 P$ T. x( y6 |
output mcasp_aclkr,* f. B( G; L Z: \) G$ H
output axr1,
3 K& H6 S3 A, x: K- R1 h/ l/ [ assign mcasp_afsr = mcasp_afsx;
2 _8 a1 J2 G; v% ?. `assign mcasp_aclkr = mcasp_aclkx;% g* I/ ~* J: Q: ?( Z5 }5 I+ p! D
assign mcasp_ahclkr = mcasp_ahclkx;; Z2 f4 b1 k3 [, [
assign axr1 = axr0;
0 j" @2 m6 a+ `. S1 x* o0 h3 ]+ u" E+ Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% L% b- Z1 Y, r" W7 W: Y& _static void McASPI2SConfigure(void)
! R# U6 Z, q, g( _{
" K7 _$ j$ h2 W8 C, d% ~% R wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 E0 s& C ?; J. K+ i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 G6 A! J$ o- IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 h1 y; n9 Y( K9 y/ g0 j6 m( QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ C& m: |. |4 n V/ \* t0 ^) [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ w% J3 D7 @0 N4 M+ \MCASP_RX_MODE_DMA);
, P5 g+ M. v* l6 x9 r0 }# u9 B4 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ f; Q4 i9 m! A/ V5 @5 M [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ o8 y& l- h3 [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( W5 Q; C2 x, i$ H( Z" T0 x8 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 e$ A/ I( s) E( \" d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ l3 w5 A/ m5 g- p: O. Y8 {3 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// z! x0 N5 N1 Y6 P, i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 Z/ M1 B4 \4 u+ FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 A/ g0 M R+ G0 _' cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. G3 T2 L$ O# [9 {0x00, 0xFF); /* configure the clock for transmitter */
1 Z5 }2 I/ { T5 m( ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 R7 d g1 P ~, d8 i" d$ ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * s0 i' B4 c7 L5 f) L' X! p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) }7 d8 t ^3 D3 U0x00, 0xFF);1 {2 u w- B& E4 H
6 h9 y/ U) P$ d4 E) \, F/* Enable synchronization of RX and TX sections */ 1 d% X$ D0 ?- T5 l! D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
Y% B% [5 ~ |% s# d7 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- v( K; f9 w1 P0 u1 X4 e; NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 e, t2 f- L* A! J: D) p% ?4 E
** Set the serializers, Currently only one serializer is set as
- h( X$ V7 W3 F+ k' f8 m** transmitter and one serializer as receiver.
! v& } _5 L0 m% M4 p*/) s3 _- M2 o! u. U+ B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: m V. s L0 r0 u0 @+ WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% N6 r$ C0 ^8 |/ c5 ?6 D. }
** Configure the McASP pins 6 E' I' M+ O# a( ?9 P) B" M
** Input - Frame Sync, Clock and Serializer Rx/ @, {1 L) Z" q! [; U: ? k$ [7 d
** Output - Serializer Tx is connected to the input of the codec
0 T+ y& s) z! S1 F+ r*/
) q$ e; s# X# k( l+ @( aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( g- o, v4 F# Y3 s3 {/ @$ g! P8 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
p/ K$ H7 h; N" DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 A t0 K0 K) `. v' l* K$ k
| MCASP_PIN_ACLKX- G+ x4 L% [4 a& t9 I
| MCASP_PIN_AHCLKX
) r9 c0 f C" U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* g& o" s9 g) K, EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 ~/ M* _- U" w4 Y9 e
| MCASP_TX_CLKFAIL 9 r N# |# I( _5 ~3 ]' \
| MCASP_TX_SYNCERROR! `- [: t! o" M" y) z- A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR R1 n/ D2 u2 j; @# t& O
| MCASP_RX_CLKFAIL
& g. {8 \' t* f* W6 o| MCASP_RX_SYNCERROR / ]2 O% ^: u% s n# g e
| MCASP_RX_OVERRUN);
8 u% G6 }& ?7 w1 ^, Z; T' \. l1 p5 ]1 J} static void I2SDataTxRxActivate(void)
; ]1 Z9 j+ V& q6 o5 `9 V% @{& q8 ?. z! a( x; t5 X. }; g0 |
/* Start the clocks */
$ ?/ r( J% v3 g( SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! U6 W# I5 @2 ~. j) p* m3 |' `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' a R1 Z$ B0 p z2 P- fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ O6 E1 @) t% b4 n. b+ _EDMA3_TRIG_MODE_EVENT);
, o7 K8 y3 N3 A. \( AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & n/ B1 x' J9 M4 e# e, ~; J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- U) h. `# R0 q+ f8 L/ w% v+ r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) q1 }% [" ?6 x1 t+ v! U8 s4 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ [2 \3 Y! s5 A6 p( Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. h. P7 Y; y! J+ oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 m9 e3 n0 ]- a) s: g! D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 i- a! O( D6 Z! N
}
* v& Z3 U; X+ ?, f6 Z! y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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