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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; Y) ^1 D: M4 i p% ]
input mcasp_ahclkx,+ u: S# x8 Q7 O- T3 D6 J# g6 s3 U: d
input mcasp_aclkx,
3 j% | K2 B5 i3 E1 Vinput axr0,
, f) `/ o' `: `1 I- l+ i# v5 l0 l3 ^3 _
output mcasp_afsr,
1 B4 T5 f7 ^3 A3 @& soutput mcasp_ahclkr,! L' E p, M3 _5 O9 n) I0 V
output mcasp_aclkr,' K- W+ N1 o& \2 j1 t
output axr1,
- Q; f# w" g1 E4 Z5 Z assign mcasp_afsr = mcasp_afsx;. M) Q0 y0 m, D! I6 K/ i
assign mcasp_aclkr = mcasp_aclkx;% y0 u; o! K' v( f) D
assign mcasp_ahclkr = mcasp_ahclkx;- G4 A3 P9 Z! n; I0 v1 \
assign axr1 = axr0; ; i% n3 V' ^0 D
; \5 m# p% ~$ [" { D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( { i; G/ J3 i
static void McASPI2SConfigure(void)
1 n- T! @. M! i0 `3 x) y F) A{
1 G0 {8 A% _& o' x0 rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: `3 y9 e: L. R5 r k& u- X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 D- p: l' ]/ s2 q* KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" J0 d p# `- s6 M. r( H0 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// X9 l' U8 C8 N: @. E2 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 b ^. `: q6 l3 ^6 ?7 ~MCASP_RX_MODE_DMA);; [/ L% h2 T) g; @" S. c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 @) ? x+ \: |: ]6 {9 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 Q% Y* o" C3 p Y+ M4 r0 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 v8 E) G: f5 r9 e1 ~" u' P# W1 _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# O/ a9 r- J9 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 o) [- ?) t- e, c7 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ }: d% ^( a9 Z& MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# \3 ~6 b8 v4 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ]! q8 Z: T7 FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) N7 c! `/ {) P
0x00, 0xFF); /* configure the clock for transmitter */
1 U) @/ p/ |( o: h2 h9 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' U3 E6 z9 z4 I) S g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 E$ E9 T$ g* @5 O$ y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 ^1 R! B1 k D9 D) r x0 M
0x00, 0xFF);
5 I' d O: J6 X5 p* t+ [ b& O, ]! ^0 ?7 K
/* Enable synchronization of RX and TX sections */ . c; C4 R' c# m) r: n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. [) B, J" w7 w: l) pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; H& Y }& q2 V& u9 ?4 c' M/ aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ T! Z+ V+ S; I& E* I** Set the serializers, Currently only one serializer is set as
7 @$ |! x% m* B% r$ c** transmitter and one serializer as receiver.
1 s) V! D0 j7 P: f*/* | r1 a9 I8 d. d1 e& I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 D) f2 b% C& U/ t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' Q: k+ @2 n6 U( C" P) }( C6 l** Configure the McASP pins
4 K+ ~- G' e0 L; }- Q** Input - Frame Sync, Clock and Serializer Rx
0 C" x) K; Y y# z) M** Output - Serializer Tx is connected to the input of the codec , j* t; `7 i. u1 k' {
*/. n: n) F$ n/ I2 }7 U% I6 Z- \, _6 `; I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# }* g% J2 M( D$ N1 l$ p% o6 O! bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# T/ m: u! ?0 ]1 i8 ^" J1 z& eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 d/ E0 n+ {. s4 X| MCASP_PIN_ACLKX) }$ I* H6 z" r; I2 y% S
| MCASP_PIN_AHCLKX3 \: ]& m3 h: p1 s/ `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# K8 D. T% o7 \$ L* x: kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ a D7 N/ Y- u& e| MCASP_TX_CLKFAIL , N$ O. J1 V) a0 L) b& y: D; G% l6 j
| MCASP_TX_SYNCERROR
8 ?9 N2 |5 B$ v2 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & |+ |+ ^! e6 I3 d5 T; U1 k
| MCASP_RX_CLKFAIL
& i* J9 A* u8 Y0 P5 G3 w9 O1 G| MCASP_RX_SYNCERROR
" |+ \6 {6 `& `; `| MCASP_RX_OVERRUN);
7 Q% f2 p5 T, F) \ {# N' r} static void I2SDataTxRxActivate(void)5 k+ v; A) Q8 C" z% ?' {* w
{8 G5 }- L3 E& y0 `' v$ n3 O
/* Start the clocks */+ D, w: B( N& Q$ Y2 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) {5 q$ @4 }4 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. g- r5 h ]% g$ y+ ~: a% j0 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
a5 K# a2 H' D# nEDMA3_TRIG_MODE_EVENT);
6 I9 `, k; I2 N; IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' {/ M6 s+ u* o4 R7 G' IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# i. j: f( ~- S3 b5 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- c7 k: y3 H6 Q4 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- _2 _: M9 s3 n# N: Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 k/ H+ A+ s7 G+ G/ f& _$ s7 i# {7 L1 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; f0 G/ A) }4 s. w7 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, G+ D) ~6 q1 ?} , Z3 f1 b$ I# G9 i; a/ f5 Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 {8 \, F, J0 d7 U: M/ ^
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