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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ P/ m8 g& D' W- P: U3 }3 `input mcasp_ahclkx,
+ y( R, L" h0 N+ o2 winput mcasp_aclkx,/ L( F8 d, m( W+ l/ z" }
input axr0,- w1 i8 H, ]; j+ ^# e ]1 L! S
K& c: s! `% |9 u5 Q% W3 zoutput mcasp_afsr,
" b; Q$ y6 t) g/ b) ]output mcasp_ahclkr,4 {6 |4 K3 {4 Z h$ J
output mcasp_aclkr,: ~- ?$ B# p. t& J
output axr1,
) R! U1 X3 H3 [& Z. U% C assign mcasp_afsr = mcasp_afsx;
$ j& d0 |& ?) t( ~assign mcasp_aclkr = mcasp_aclkx;! j5 `. s. ^% ]; n8 h
assign mcasp_ahclkr = mcasp_ahclkx;7 e7 M' n! }+ z f$ D0 n0 z: x
assign axr1 = axr0;
$ U2 h/ |( z& ^# b' K' g4 M: Y
! Y) o$ _% ~9 Y, ]7 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. c: l- V% h& P$ w9 f6 X; b K3 Qstatic void McASPI2SConfigure(void)
k9 S- s1 `; g5 U, |{
% r% x- `: }8 Y& O5 C$ g( CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. I+ {" ^; m% u- w3 X+ eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 I2 @. y& ?+ v3 d- s( U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ D& z6 \7 X' h5 W5 J. }5 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! H& b( i! L) X1 r9 ?( \( }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' z$ j. G9 E; P# Z( L! z2 s3 qMCASP_RX_MODE_DMA);% V' g' x& C+ L$ @# G. P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, U3 E( h3 Z) H! D# R% M2 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! e( X7 J7 A8 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" x, u* U# T$ j s/ t. ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; x2 x# u7 y7 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ Y/ N7 e% Q+ K; T y0 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( A- k! m) W3 c6 W4 t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 g1 f) J# x& y; P, F: `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( h" f9 f$ ?7 g: F! r' J& L! m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 u# E, v! S8 P0x00, 0xFF); /* configure the clock for transmitter */9 `; d6 W1 U1 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: [4 F9 @, w0 ~" y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' M1 `4 m& K! s, \* oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* P5 A2 e. \" w+ m7 |- U0x00, 0xFF);+ }3 ^6 m, ^& K
$ M/ ?/ u; l% p) X i' R7 c
/* Enable synchronization of RX and TX sections */
- N/ S. {" k f5 E, m) xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( M2 g0 C1 S5 u8 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) z, P# N" X( ^7 ]4 R% o; Y G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ O9 b2 q1 B& i& e% b4 d- U; Z** Set the serializers, Currently only one serializer is set as
, B8 r2 h- M, ?. k: d: B) y$ p/ p- I5 l** transmitter and one serializer as receiver.$ ~5 g0 Y0 d6 W
*/0 h+ k7 p8 i; {9 u" t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 ?; w. F" u3 I2 q5 n/ k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 ~! v: n; d, Q g1 U- `** Configure the McASP pins 9 w* |$ y {) [! W5 x
** Input - Frame Sync, Clock and Serializer Rx8 q: V: `2 m% Z- c. h
** Output - Serializer Tx is connected to the input of the codec
! [6 a* a, @' H/ x5 i* d*/7 ?; X' t/ z% A6 X l0 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 A- J {/ ^( K8 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& h; A' e0 t5 G; z( }+ t) GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 L+ y+ O$ y; j# N' C' f| MCASP_PIN_ACLKX! X$ r) p) {# o, D! e2 [* j
| MCASP_PIN_AHCLKX; n, {, T v/ K# o$ |5 R' O) U& y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' \5 t6 ^+ q6 ]8 l. GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 w. n; g( K# B3 A+ S4 K; x| MCASP_TX_CLKFAIL 4 I' p, J8 N" E: v4 ^2 y
| MCASP_TX_SYNCERROR
% G; A t C9 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 k+ U; R$ R- X( o: d| MCASP_RX_CLKFAIL& v9 L# p2 q1 P( A/ p0 d3 h; T5 E
| MCASP_RX_SYNCERROR
, N5 ^6 N( W2 Y3 o9 Z| MCASP_RX_OVERRUN);
% l0 A0 t0 z5 m! z} static void I2SDataTxRxActivate(void)
6 G7 Y: y; }7 c& m{
5 A" X( {( c6 Z& X/* Start the clocks */5 C; y. Y' A( {/ }6 V: s A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 u7 H, o; B2 k, Q* n) S3 [' q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 Q: t# I6 S: Y5 B9 m8 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 Y" s1 e) K9 ], v. {
EDMA3_TRIG_MODE_EVENT);
( o) h- i0 J6 X2 `/ l- N% NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * E& `6 g8 W7 X2 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// U( @- T/ a4 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ R$ c: y3 y- \ d, K" ^5 f2 d" SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// x0 q* `) p* G, D, F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) T) g3 [( `& S9 f+ n6 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 A% y! F+ V; c& V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 v' ]7 E# {0 }+ ~1 L2 Z}
; E3 v: A+ Y; i1 L$ }5 ~- ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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