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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 i: _; H" T- xinput mcasp_ahclkx,* L6 E% k' q! w- B
input mcasp_aclkx,5 \) G! F" h( j1 S
input axr0,( k# @8 V# B: d; s3 U
: w4 u+ g% l. Foutput mcasp_afsr,
' \2 x0 S. K# f- Toutput mcasp_ahclkr,
* V& G9 B9 \/ ? C$ Xoutput mcasp_aclkr,* \, j# D# H6 j3 `2 B! Y
output axr1,, H& d J) Z4 T% x
assign mcasp_afsr = mcasp_afsx;
9 i9 E! y& R* a, fassign mcasp_aclkr = mcasp_aclkx;
: r N2 N' \( h3 `assign mcasp_ahclkr = mcasp_ahclkx;, c+ W) C8 n+ T: \6 [. t
assign axr1 = axr0; 7 [6 ]8 F9 M# c$ @9 R
T: m7 m* L0 k0 ^$ d: Z) p v: J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' r8 N& x0 I2 B8 M% w9 W: z' t; N: s
static void McASPI2SConfigure(void). D' L+ t. T& V( `) T8 f/ i8 E: L
{
9 c/ H! A9 ~( o) i/ X' o/ h0 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" K, @3 \' e; O, G" HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; l1 I3 [- ]5 c7 Y/ y& _+ n2 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ N7 u I( k5 o& ~* k4 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ e m7 h2 T' E0 |# [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) b, F9 c1 {+ y1 |) [
MCASP_RX_MODE_DMA);7 Z5 e' c/ B- L6 t2 V) T7 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 D6 M+ v. S+ p. f* v( h. s! F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' C8 C4 E* Q; D" m9 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- O. [ y: n; C z( Y5 D0 ]8 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" w i7 o+ }% x2 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - ~' p8 @1 E7 @# h m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 \, j, `* ]- `& c: yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- {: B* x9 M& H8 ?% v& @1 p0 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); X0 d: t5 _3 V7 ~, u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, g s' B" l* d+ f, I/ i
0x00, 0xFF); /* configure the clock for transmitter */
$ K/ z4 h- p( c9 y; k$ L. T3 U, {; RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); n7 i2 M* W! n+ b7 p; @& G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# g0 B; S" f( i0 k, L: LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 e. t/ r7 R( b
0x00, 0xFF);+ F( R5 E7 c2 [3 p9 x$ p% h/ e. D% b
& e d s b0 o, D) u: H
/* Enable synchronization of RX and TX sections */ - O: _; n, Z6 Z j5 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 _0 A3 ^& |/ j9 q( D2 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 I8 W# g8 n' g! F6 B/ L: {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 y: B4 U4 N9 m, p* P" v** Set the serializers, Currently only one serializer is set as
& E5 H% M* E# ?% ^" g) j** transmitter and one serializer as receiver.4 l4 Q ]5 ]9 T6 n' c
*/
i) ?4 z& W1 u8 Y9 S6 O7 p# ^% FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' E9 X3 m' M7 t4 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: p+ c4 m# Q1 D2 p1 Y/ m' d1 S** Configure the McASP pins " k; O: G9 \8 |4 d C Q5 w* i
** Input - Frame Sync, Clock and Serializer Rx6 g8 R. Y5 K$ @, A# b
** Output - Serializer Tx is connected to the input of the codec - F& y$ P+ j5 N2 k
*/1 P' S4 Q+ ]* w1 V$ P2 Y, ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( Y! z! y- R: jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: x7 P9 I: a: g- p7 C5 u6 f2 b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" F8 T0 {5 ^ ~. R
| MCASP_PIN_ACLKX
: u+ X/ c8 F# o! g! ^0 R6 M3 }( B/ C| MCASP_PIN_AHCLKX8 X- y. l. s' n2 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& U' x2 G8 N, O, p, o9 p* G0 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' `: S1 L: Y# F6 X) q1 l6 R. l7 t| MCASP_TX_CLKFAIL & m" [# D. P- h; W# i+ g& u1 r
| MCASP_TX_SYNCERROR7 y y9 K8 W# h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 K* E0 K; A3 L1 {/ a| MCASP_RX_CLKFAIL
q* u1 e) D. j| MCASP_RX_SYNCERROR
" G$ p9 B. z2 [9 R5 C| MCASP_RX_OVERRUN);
$ M& p* A2 Y( d! v' j# S7 b} static void I2SDataTxRxActivate(void). N- c% K5 N) k. Z) P# f. B' F. Q+ w' d
{
1 w! c& e E6 \6 ^! i, O/* Start the clocks */% A6 |# a+ T# Z- j1 k+ b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 p+ D6 \* n+ v! ^6 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ u6 D! e# e! P& D. e+ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 }8 z% E# ~; r G/ f2 _0 Y, g9 }* ]EDMA3_TRIG_MODE_EVENT);
' I4 ?4 L: y: o. A0 B# DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 ^- b) w/ z0 b- u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: H+ W9 b5 X% h$ RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" I4 @- P% C& ]7 a: Z9 h2 uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. J! j4 ]- q: H1 _- u5 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 D1 Q' R& n$ V6 o4 g5 W0 p) ]# }: N" ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 \* ]+ r/ `9 w. k; k. x7 y0 c) R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! a& C- ~8 h1 o" Z& `3 S
}
) c6 z X6 Q$ v2 c6 M, a$ n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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