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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 H* T4 @1 @# ^
input mcasp_ahclkx,) D6 Z+ r5 q% s7 S, d; `
input mcasp_aclkx,% y- q, T$ q: o2 _& A. [4 s
input axr0, j, y2 C# j4 ]: A; X
2 [ @: x# q" o0 T1 K' k: C' k toutput mcasp_afsr,' w. M" ]6 V! f6 x" X' Y
output mcasp_ahclkr,8 I. ]# F; `: m$ y, K
output mcasp_aclkr,
* h# l1 ]+ U. h; t7 w& Youtput axr1,/ U2 z: b: m2 g6 Q! t5 L! ?) J: o
assign mcasp_afsr = mcasp_afsx;
/ b8 K* [3 s3 bassign mcasp_aclkr = mcasp_aclkx;
9 \- O9 z& m# zassign mcasp_ahclkr = mcasp_ahclkx;3 B* T2 B' Q$ u9 ?( Z8 X
assign axr1 = axr0;
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8 ^3 L3 d, X' S6 c# q8 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * u/ \3 i" m+ w$ B5 m
static void McASPI2SConfigure(void)
# V1 b& U8 |& a+ N! S{
# @& A% d0 c7 H5 u4 G# e0 ^1 p4 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( X* J, c! k6 d$ `4 e$ n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( o0 P q- u6 b* v5 Z6 `5 H# VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 H3 z' z* E5 e# B' _- s! K9 \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& q3 [' o, ?2 A- U& hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" z' a k% ?6 y( ]! z6 T+ jMCASP_RX_MODE_DMA);2 L% O1 |8 T. `, G3 o% m& B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: u! U6 S2 i+ T2 t- ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. _" R7 @4 V6 a( n- |2 w, OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - P# d9 q7 |$ O# z4 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 T: G; G C VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : `4 O$ t! `8 ?# g+ y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! E$ [0 w. ~4 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' o) T1 o0 F& K" e& I0 U @" AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; w. d) R. G3 ~% F3 t5 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. w3 o& @9 k. x* O( A: s. ^; ^* X4 Y
0x00, 0xFF); /* configure the clock for transmitter */( f3 w. b/ N5 N/ I, a) e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 }* I! B5 n0 s; l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 P7 y+ ?; s) f, eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," N4 z, ~" S7 m& ~/ [
0x00, 0xFF);
! R c7 p2 l5 `- n4 U
" z1 S& [5 K3 _4 _) R+ n# M; h/* Enable synchronization of RX and TX sections */ ! K3 P( Q: T9 ?: X2 r, o4 P$ W9 M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) D. Z2 {5 |7 M3 r2 h! c; [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 d( K5 |0 g* o% [" Z- y0 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* v7 Y6 s) `4 r: k: @6 R** Set the serializers, Currently only one serializer is set as0 Z( ]' _7 x# b4 e8 |4 I; g
** transmitter and one serializer as receiver. H" T$ u$ u% W% O' [
*/0 s* h1 }/ B& a) @6 A) O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% a0 D! a$ s' \4 t8 kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, ~# e& m3 A4 t1 S5 \** Configure the McASP pins 5 U/ T. X4 a I' `
** Input - Frame Sync, Clock and Serializer Rx
% S4 P8 r0 G( {" q8 h( d+ y. [3 W** Output - Serializer Tx is connected to the input of the codec - H8 P$ k) Q2 r& q5 D$ r. L
*/8 c" ^. I. B( O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" G9 [9 E Y* }& U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% L$ |6 g4 a/ Z! X& X5 Q( |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 M( ?- B" {( Z g| MCASP_PIN_ACLKX4 d5 ~4 w9 c$ _9 ]- Z. G
| MCASP_PIN_AHCLKX& _) j, k* N& q" Y. ?, B1 a# o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 H( i: V) _/ O$ x- p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ ^3 F4 r7 K$ R1 Q" a2 m| MCASP_TX_CLKFAIL , H$ w" y% |9 u# C& R+ V
| MCASP_TX_SYNCERROR
. _3 c# _- n9 z( c5 t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 n: e6 a' o& p: H4 }% f| MCASP_RX_CLKFAIL9 U% D# n9 w3 y. o( X
| MCASP_RX_SYNCERROR
& J# u2 H' c0 J" S5 m| MCASP_RX_OVERRUN);. Z( D9 d1 }7 ?1 m$ {/ @3 j
} static void I2SDataTxRxActivate(void)9 I G. q' J2 @( A9 T5 g& ^# k
{( x' U0 l3 Z' k% f8 N
/* Start the clocks */
; z( X* \- a. p) k- {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: ]" B6 X0 f, I4 _% P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
q" r; u/ f% V5 w& VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 P1 s! V, z; C9 I! j0 pEDMA3_TRIG_MODE_EVENT);
! [* s+ T" _( { e& v- z) b. J6 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! \6 A- j7 S v! ]! _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// T7 X( Z; _+ l V+ h2 j- c6 o7 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 r3 k3 j8 q! v' n9 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, h0 }* q# o2 `0 m; E% V0 \$ y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" S! k# U0 G3 Q3 P, p! mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, K/ p ^5 z* D! `7 s+ ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 c8 n J: n# T; a3 k}
. \% N3 A4 K6 |* Z5 _0 k$ V' X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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