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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! Q; l; {7 @4 T2 |, b/ zinput mcasp_ahclkx,
5 F! I9 R; {& |! hinput mcasp_aclkx,3 v/ v$ C8 p% B# e. I% P
input axr0,' A8 r- s2 a# |! q
G6 O$ h; \3 V& b( `- Goutput mcasp_afsr,
! d$ i& a* Q1 F: Z& uoutput mcasp_ahclkr,
/ o1 {& l5 O. `) G& L' E% }6 uoutput mcasp_aclkr,6 I- h2 Y8 l; R+ _
output axr1,1 ?8 N, z0 t0 ^: g8 R n
assign mcasp_afsr = mcasp_afsx;0 K7 G; r2 A8 H) X
assign mcasp_aclkr = mcasp_aclkx;
5 R: z. E) k* C$ Lassign mcasp_ahclkr = mcasp_ahclkx;
6 B* k8 f. I9 W$ wassign axr1 = axr0;
- L9 a' P2 ~1 D1 I
7 }) f" w* w3 q3 B1 m% `" j' ~; g* N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ t( X @6 c% Wstatic void McASPI2SConfigure(void)
. x7 Y ~+ s% a$ h+ G( Q{3 U+ y3 x% i Z7 {$ ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, k( }5 k7 N# ?0 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( T8 N& G/ O( EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! k4 \' p0 D# A; c" ]* {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% G2 X w: G# i% [5 l( {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* L; f! R5 K( [7 g6 oMCASP_RX_MODE_DMA);
/ V, }* v" s3 n$ r8 a! ^9 {$ FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 l0 E9 A g! r5 _9 i5 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- h4 \/ p+ x+ N- nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' n' ]% T+ p) F5 ?7 @1 U8 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 ^' H( P5 ~1 m/ M% J' ~+ C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, P) |' a) L( {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. e- ?) i( e, u7 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ H' n( Y" d# U0 m/ s+ X8 `" I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * X5 r1 M) L6 v' _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," t* k6 F; @! M& O9 t: L
0x00, 0xFF); /* configure the clock for transmitter *// l- [' U0 ]* _9 B% P5 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 L9 C% a3 L- T S! y( k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # t/ K( O9 o) G. ]& N2 r! y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
C" |" F. \7 C) X0 v- H0x00, 0xFF);
+ K# S9 Z @" _( d7 T/ p2 Y' m
0 t: O" m+ E; T5 D- W( T/* Enable synchronization of RX and TX sections */ & V7 A# Y, g) r2 Q9 w$ k% n# O1 A2 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 i7 k1 T5 {7 y) ?" Q6 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 J$ E# j/ W/ b% d, j* M; n! n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- k; E9 n* ^- |( F** Set the serializers, Currently only one serializer is set as0 [3 f* ?+ T% O' G* x% j' n9 b
** transmitter and one serializer as receiver.
, ?1 D9 N, X/ F/ C*/
* ~. J# U: S4 k2 SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 D/ Z8 T0 @+ V; {) J& J, ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ O. R, A: g& }: Q, r# T9 z
** Configure the McASP pins 3 k' N# P, u; a! ^% J0 i$ f% x
** Input - Frame Sync, Clock and Serializer Rx A& Q" j7 `) g6 \) k2 `9 u
** Output - Serializer Tx is connected to the input of the codec , p( s0 N" p! v+ a( R2 j" n9 A
*/
! l w) O5 v! W% ]( {2 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* Q' S1 m2 _0 \9 x$ ?6 a! {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; {& b9 v9 I( Z' A8 `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 u5 v. N! @' L0 C. Q
| MCASP_PIN_ACLKX
1 P2 T6 |4 ~' r: z% w: k| MCASP_PIN_AHCLKX: e3 W+ J3 @+ A0 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ @$ P% W5 _6 w1 ~$ _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 j$ }4 p2 h! P u1 H2 N1 H6 w3 E| MCASP_TX_CLKFAIL
4 D. @4 H% u) b' ^6 J$ O, `$ `( i| MCASP_TX_SYNCERROR+ i) n# v* V; Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + H0 I. F9 \, u2 M$ K) f
| MCASP_RX_CLKFAIL! s! P' t. U0 Q" K P: C
| MCASP_RX_SYNCERROR , B' W# w) @3 N; [: X
| MCASP_RX_OVERRUN);! g% J2 O' w, {* j* \
} static void I2SDataTxRxActivate(void)
6 S$ o: o* c- o: Y1 j2 y5 L{
$ h1 Z% i6 s/ \. {/* Start the clocks */5 o1 ?: \" X# e8 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& ~) s4 b& o( ?) QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 v) D# o- w3 E; \8 V, V; q9 G+ e' O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 O# T0 b2 y* x2 R% z& e3 a* }2 iEDMA3_TRIG_MODE_EVENT);
) k9 t2 N5 K* g; `. g xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, Z; }. L0 I0 m- c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 I$ D o! p) k9 B% ~( _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- ?6 ?+ i4 A7 N9 G0 B( x( VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 t. [7 \6 M' ?! q) r5 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 B Q& M& @# MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 _' n/ r% W+ `+ w7 r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( K' J2 s( S$ M/ n' j}
0 {7 o6 r( w2 ^6 L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " v, r! V) e$ G- ~; S, d
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