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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( j7 t) G4 b# m& c, @# Minput mcasp_ahclkx,
6 L' _# e$ A& `: @7 T: Ninput mcasp_aclkx,: j5 }3 }" E7 z/ B
input axr0,+ h# R% l$ L3 {4 M! ?! T2 |
( c) D; `' s, u9 U6 N3 O) _output mcasp_afsr,
. `6 R% \' J7 X) B3 \0 H w# foutput mcasp_ahclkr,: w4 A ?, b9 b' u* G+ T
output mcasp_aclkr,
( u9 [/ h6 c2 }0 Coutput axr1,7 s i( Y, A& \! o" b; r
assign mcasp_afsr = mcasp_afsx;
, U9 q! K, h+ G; S4 j4 f9 @* Hassign mcasp_aclkr = mcasp_aclkx;6 Q( y A; y' o; \# B4 y1 j
assign mcasp_ahclkr = mcasp_ahclkx;
; c; o+ h/ m! G/ w" H; g9 I! Dassign axr1 = axr0;
4 s( H- M8 v8 T& f) b' s
+ {9 z+ _0 D, T0 B+ }7 I' |$ A# C8 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - S- G1 F3 j, ?, ]& B
static void McASPI2SConfigure(void)+ Z& J3 C0 \) g5 x7 @# R* I- K* R# [
{
6 z, }3 ]" d( L4 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 q, ^% D: G" i. j6 h1 l, X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ D3 G* ?4 D% ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. c2 z) L6 v% f6 W! j5 l. D" v5 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 h5 p& m/ E( l) fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 d- Y7 d9 e( f3 t. ]7 pMCASP_RX_MODE_DMA);
" b0 q, ]8 s/ V' Q0 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& w8 f, c1 O# b( q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 U& i- W% S! q: ]; o2 u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ X9 C7 g( f0 f- vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ r$ N0 C3 S) n5 h/ [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& p' E) T: o) r0 O% l/ @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% u- B; x" D. f+ S# }- n& A& h' z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 K S( g# y. t1 f4 z: X" f$ qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - ~0 i& ~$ c ^; Q8 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 L7 }- t+ v. c7 Z$ X* R, x0x00, 0xFF); /* configure the clock for transmitter */ k" U" C8 g9 f/ y" `9 ?+ d% |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; p q) V% X1 @5 M T9 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 h; q. ^$ I e) \1 Q7 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& o+ O8 E; r" a5 d6 }% r0x00, 0xFF);1 T D# I5 f$ i6 }, M% |+ x
7 t+ z6 U) O3 S3 Z. e/* Enable synchronization of RX and TX sections */
) [7 g2 ?: s9 e6 HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- K4 Y1 n3 O9 B0 A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 Y! ?" [# Y' m# ~: F- i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) l* _$ V8 [7 ^ R* b" u K, f** Set the serializers, Currently only one serializer is set as3 M& S, F+ v; w2 ?; i
** transmitter and one serializer as receiver.7 A( c) s# i( E' p2 k! O# ~! ^* c
*/1 T, o: U. c, Y3 L1 h( w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) c# X3 n2 N* x T8 U7 E* PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, m( |+ \' _! Q( x) K4 w* m* r! w
** Configure the McASP pins
5 f1 F2 D! ], }! |+ |; |** Input - Frame Sync, Clock and Serializer Rx# @' _: I) G$ c$ v( d# A M) `' u0 o
** Output - Serializer Tx is connected to the input of the codec
8 h/ O5 F6 W3 u; u*/ @$ U7 k( a" [( G3 l7 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
[% I7 }% v- x) `. f# W$ zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 y8 f- ~; S/ x M0 ~$ q( yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- ]& x$ r& }7 Q
| MCASP_PIN_ACLKX) V7 N& n) C4 S0 y. e# v" T6 _
| MCASP_PIN_AHCLKX
) P2 ^: P$ K9 ~7 D( J* r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 n- X: O; e% {' `2 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' N# \: j' J, r. Y1 M0 w| MCASP_TX_CLKFAIL
+ H( F/ q1 i$ s0 K* l0 g c| MCASP_TX_SYNCERROR6 K$ Y# A9 Y. u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 u" K/ a& Y8 F. u& ] || MCASP_RX_CLKFAIL( G& p) q1 C3 Q; f& y
| MCASP_RX_SYNCERROR
( Y& m: y, o$ c- x| MCASP_RX_OVERRUN);; F2 o8 ^7 j1 q, ?% R% K
} static void I2SDataTxRxActivate(void)
& N6 c4 @. @- [9 B$ r7 \8 Y5 h; Y{* K6 _# R7 x2 q: O/ ]
/* Start the clocks */8 }( r& X! b. G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; U+ N8 T( E( G; D3 I: I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 E6 ]& u% Z. v2 A9 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, x2 n# z l2 |* |! z ~EDMA3_TRIG_MODE_EVENT);
- m1 F' F/ {5 J: l6 Q* E; nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * E9 ^7 [5 r" x& p0 g8 y& u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 @1 `. I# n+ p M9 ^; \; x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* U. Q4 i/ J3 |6 d& ^, X5 wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ X3 ^; W) t" k* [9 n& y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 V0 b8 J+ c+ e( EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 q6 M) ~' K, a. @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, `7 I" ^# E- D3 C9 p5 K3 ?6 w}
K+ y* ~5 L2 D8 j5 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 a) A+ K% l! T1 a, g
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