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我的McASP配置分别如下:! B n0 V b) F5 v/ j4 [0 U5 m
管脚的复用设置是:2 I/ k( s1 g a7 Q0 g x
void McASPPinMuxSetup(void)- Z. a& K% r+ @- z) A* @2 s9 M% f
{
! B1 z: S# H0 r% c! u unsigned int savePinMux = 0;
' T4 x# `6 `7 w8 Z' s0 \2 `$ T1 c. [ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
' ~. n4 s0 k3 r5 ^/ _+ X Q ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \0 }2 ?5 E) v2 o0 t, T1 t
SYSCFG_PINMUX0_PINMUX0_23_20 | \0 D! B) c/ i2 c9 b
SYSCFG_PINMUX0_PINMUX0_19_16 | \
& _" v1 s$ N, R b. I SYSCFG_PINMUX0_PINMUX0_15_12 | \4 a1 g7 @3 P5 x. K' M
SYSCFG_PINMUX0_PINMUX0_11_8 | \
& a. {0 G2 r' t# b6 _ SYSCFG_PINMUX0_PINMUX0_7_4 | \
5 u( F) u4 g6 L! F) U4 N' {' S SYSCFG_PINMUX0_PINMUX0_3_0);
3 ^: c8 f9 p9 ^$ ` HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \5 ]2 R6 w' }4 C% n2 ]- e8 {" N
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
: x" J; ?" [2 M% `# C PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
, i4 b! E3 ~, @$ |: O n- S' h! D PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
0 E7 j9 M, K; ^5 z PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);; K. U" q2 z1 ^! g: F4 \$ ]$ { Z
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \: @" t1 n: k; n4 B. X$ A2 J, n
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \0 @8 u8 Y" ]" |6 d' m8 j
SYSCFG_PINMUX1_PINMUX1_15_12 | \* v) i% B1 J% z
SYSCFG_PINMUX1_PINMUX1_11_8 | \
0 w# J; c3 \- b- x SYSCFG_PINMUX1_PINMUX1_7_4 | \
9 O: ?/ N7 d( m1 U6 ?& O& v, O+ u7 p SYSCFG_PINMUX1_PINMUX1_23_20 | \& P% W5 a& \' @. x/ K
SYSCFG_PINMUX1_PINMUX1_27_24 | \
/ w ?( V9 y6 z" z5 v% e* K1 H- W/ o SYSCFG_PINMUX1_PINMUX1_31_28
: U+ u" T3 C. n, D8 }6 V/ C3 B) c7 e, w );5 ~) X" }) E3 _+ u! i7 k0 R
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \1 ~ p8 P% w- a$ W/ `
(PINMUX1_MCASP0_AXR11_ENABLE | \$ r& _/ ^) i9 k( y
PINMUX1_MCASP0_AXR12_ENABLE | \
& U, s0 `/ P& R0 L* K$ e9 i/ h PINMUX1_MCASP0_AXR13_ENABLE | \
7 W# i. R. g. D9 x PINMUX1_MCASP0_AXR14_ENABLE | \' N7 q* n* _. z, _& Y
PINMUX1_MCASP0_AXR8_ENABLE | \
; D N/ C, q! f PINMUX1_MCASP0_AXR9_ENABLE | \
- S# A; ]" P7 H4 a PINMUX1_MCASP0_AXR10_ENABLE | \
& w+ O% f9 |- k0 m savePinMux); M9 b: ?) ]+ d8 ?3 D
}
* e' E5 B" Q5 ]* m& y$ q' ~4 ]' ~* B& J
1.McASPI2SConfigure(); McASP的配置程序如下:
* j& F6 ~- Z5 i6 G* i; b! fstatic void McASPI2SConfigure(void)" A/ k2 ~8 N: t1 Q1 s
{9 q( O F+ h5 L3 O$ a/ w8 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! l. A' x+ c8 K0 B. h
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
! a0 i1 x, e% t6 [0 x% k
9 H u1 V6 M+ r9 a /* Enable the FIFOs for DMA transfer */% o9 s& u2 W! n& K X! O% G
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);3 `( V. l) G. [2 j( {" x+ s
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% ^4 o) R/ r- {6 s) d
6 Z8 h- K% X6 d* u) M8 x/ H /* Set I2S format in the transmitter/receiver format units */
7 H- k* l& @6 S McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% G" ` X* q p g J8 q8 }
MCASP_RX_MODE_NON_DMA); a6 \; W9 B4 K1 k* t( U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ I# T6 Y3 ?' C) C MCASP_TX_MODE_NON_DMA);3 u; w3 b, q) c. Y/ A9 @
+ I, y& \. b$ n& R
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */# b# `* O! B: q+ z" Q5 U F1 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 E, U% u' s: `# k6 s1 U( q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 S! ]- `! v4 z1 _; a0 V McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( T3 w4 Y' q4 b6 V2 B. o' e6 ], }
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE); b5 }8 S. Z2 M0 A; r
/ _$ s$ O) x- @" F4 c# o: `2 k2 @ /* configure the clock for receiver */( }# p" M( y7 j& D& g: E; a% }
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);, P" P% O0 `( j, f2 t, g' F. Z/ _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* |( d, P+ ~/ `- E( b5 _9 e McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 \/ ^4 W! n6 f, I+ {6 N4 a McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) S( R0 o3 o, K5 L3 E
0x00, 0xFF);. Z1 W+ \6 K$ \3 H1 d. l
9 D, Y. [ z4 _8 f) N /* configure the clock for transmitter */
$ H& V+ V8 J0 c1 Z// HWREG(0x01D000A0) = (0x00001F00);
P D9 s6 }+ L- D' K h5 J. e// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
9 i& E4 T; l: z& E McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);- S- J$ m+ [7 \3 p) n0 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ I( b1 J- }) S" B McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! `* c/ h1 h; h/ R4 L
0x00, 0xFF);* G0 u' \$ k; ]3 |
! n6 I: e' s4 F$ @% D( M/ c& q
/* Enable synchronization of RX and TX sections */ ( f; h) q7 M# }) S- M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);% A1 x6 r9 j8 S- @$ t
- `" y$ Z5 D3 v8 a5 v /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 R$ B! }( y* U) y/ G |" n5 \5 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# c0 {: J& p" j4 J0 v' U! I1 N* C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" J% _+ m, ?! L& a" m0 \
# P1 ]3 J! j4 c1 a /*
8 ?# G5 c" U) c# r, n9 ?& c! C8 ] ** Set the serializers, Currently only one serializer is set as, X) @. D5 R* D6 a3 L, N
** transmitter and one serializer as receiver.
$ j0 \: t: l A+ P& n& D% y */
. c% _0 q, u) k McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 s0 Q: e3 A2 s+ s# _/ G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);( Q5 S1 U+ j" E( V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);( M2 O3 [% {0 C- @# N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);$ b7 X+ I6 F. |% Y4 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);1 w1 d/ |* n( e6 h5 q5 j# L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);+ v8 V2 D- i" N' b* J
1 E/ N2 B* p% L; Q! b5 y McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);: g* a4 a; v9 a; g0 A9 V
" p( q' V8 { }( D$ d* k9 d9 a /*
3 [/ Q" j' L6 ^, ` G ** Configure the McASP pins
2 m/ i; @2 S5 Q6 L; s ** Input - Frame Sync, Clock and Serializer Rx9 l" ?9 p: P. @ x" j* B, @. ?3 c. X
** Output - Serializer Tx is connected to the input of the codec ! f, o A. ^" Y2 d1 Z* v
*/
6 c2 ?- j4 I- l0 E McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" ~2 k( z+ k) Z/ H3 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
. G) P" `$ e# E; { MCASP_PIN_AXR(MCASP_XSER_TX)7 }/ E7 q' B0 `/ p
| MCASP_PIN_AMUTE8 M5 ?0 ?: G. e6 p0 `! G1 g, w3 x
);
6 P6 [+ z7 C3 p McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
% ^( Z" B+ w$ T: W7 I3 l MCASP_PIN_AFSX
( H3 J. M5 l% I& P | MCASP_PIN_AFSR4 U6 N2 h8 X0 ~1 B
| MCASP_PIN_AHCLKX
0 l+ N. k E+ o0 n | MCASP_PIN_AHCLKR) D+ i+ a7 }+ _3 p
| MCASP_PIN_ACLKX6 @2 k) j& e+ `" ]0 L5 V# l
| MCASP_PIN_ACLKR
+ ?" L' u1 k8 W+ p | MCASP_PIN_AXR(MCASP_XSER_RX)+ o) }9 ]* i0 b' f M( J+ W! M
| MCASP_PIN_AXR(1u<<(13u))0 W- [( D, q6 b9 e7 R
| MCASP_PIN_AXR(1u<<(14u))( G* u! F# L& v. h3 c
| MCASP_PIN_AXR(1u<<(8u))9 k- L( ]" A6 O/ g
| MCASP_PIN_AXR(1u<<(10u))" F- c( Q- O( z
| MCASP_PIN_AXR(1u<<(11u))7 U( d- c5 b( A* r5 _. ?$ G
);+ d+ S$ Y5 Q2 [# u9 |5 B
1 K6 f* }" Q4 v+ Z2 n5 ~ /* Enable error interrupts for McASP */
j4 t3 ~( x H$ t7 ?2 y1 w2 R McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
* c% J0 Q0 _% y- D2 Q MCASP_TX_DATAREADY
% d8 @* k, R$ g/ H3 Z$ o, L | MCASP_TX_CLKFAIL e! y1 G4 c1 f2 \9 a4 R
| MCASP_TX_SYNCERROR
' D- c) ~7 y4 F) F | MCASP_TX_UNDERRUN);
2 k3 B, K; [( `" Q1 ?9 l- B; W) _8 f/ n. R- U
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
; |7 F. ~8 r5 ~5 V' H8 O MCASP_RX_DATAREADY3 K6 |. ?2 Y& i; x9 [
| MCASP_RX_CLKFAIL
$ t( j8 a r9 M | MCASP_RX_SYNCERROR 0 i1 q5 r! N5 r: A, d$ V) {
| MCASP_RX_OVERRUN);
5 x0 ]. g# q' ~- f& y6 w& d//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
% b$ x% U0 X1 a% C
3 c) m4 h8 N' E: s8 b7 U1 ] ]}" \& W3 p5 i' i+ n7 W5 G; P; I$ s
" h; a7 \% ]6 F; u" t
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
- F, }6 X, p: Jstatic void I2SDataTxRxActivate(void)
3 a; o# o( j+ J0 d" w0 M4 _{
/ r8 J) I9 W" d! n$ O# W /* Start the clocks */
$ K( W3 n; U6 U( |" v- N McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ [! g. u# I3 g$ T5 G* ]5 g McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
( m L- L, i& p- k! \$ g; Z5 P e4 b8 m- c4 Q: j+ w( e0 w
/* Enable EDMA for the transfer */
4 }3 P% o+ v* Z// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, j' ]. S8 W7 `* ?
// EDMA3_TRIG_MODE_EVENT);+ }4 m+ n* V/ h! g! Q5 L
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,# s/ N! i/ z0 n$ T& J7 I
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
" J% y2 W4 K- P- y2 k$ d( n /* Activate the serializers */
+ B2 S" U; ?5 u1 c McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 N! L/ l4 N# U McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);, w5 r6 c/ x; [# f- J
/* make sure that the XDATA bit is cleared to zero */+ B2 Z4 K- r3 g H' w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
! B; f6 d$ c r- p) D" ? /* Activate the state machines */
$ D% `9 e _# k" A McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 H/ k, M! u) b/ @ McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& k+ |, l2 T# R2 X8 `
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);8 S: ^1 p0 F+ |
}
3 i/ m [( a% u2 F: z2 G$ d
3 a8 m/ N5 d0 w6 m$ [& @+ E, l |
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