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我的McASP配置分别如下:1 u1 e- G4 s- L3 {% l: G
管脚的复用设置是:
4 i2 M/ v; M! y d1 Bvoid McASPPinMuxSetup(void)
: ] Q$ V0 O( U$ @9 n) T{; n! | ]6 ?: r: I
unsigned int savePinMux = 0;4 M9 d. `, S# O5 P
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
) Q7 K4 H) o( |" }+ f ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \5 J! ^6 w8 L9 L
SYSCFG_PINMUX0_PINMUX0_23_20 | \
X' L2 {) S7 v/ z SYSCFG_PINMUX0_PINMUX0_19_16 | \
8 `9 B8 p4 h' [. O" U1 ? SYSCFG_PINMUX0_PINMUX0_15_12 | \
, m. {$ o, r) k3 ?! F SYSCFG_PINMUX0_PINMUX0_11_8 | \
! Y+ C5 k6 Q7 _( n" a8 M SYSCFG_PINMUX0_PINMUX0_7_4 | \3 q# z* Q5 q- r* r
SYSCFG_PINMUX0_PINMUX0_3_0);
3 n7 V+ [) i3 f' w& G HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
6 s0 H* Z# Z* k. V+ e# p (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \* t8 t1 K6 s6 q2 t4 N
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
2 ]0 S- }, w- J7 m PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
+ Z4 S- _- |- Y8 e$ V; f$ q6 ~ PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
" X# h: [9 G( I! I% ^ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \+ [2 U h- X; }- u, u# g
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
9 g: N D% r( h5 j6 i! a' D SYSCFG_PINMUX1_PINMUX1_15_12 | \) L( `6 W' A, H2 a
SYSCFG_PINMUX1_PINMUX1_11_8 | \
! c# C9 \9 ?! l. V0 v U" i SYSCFG_PINMUX1_PINMUX1_7_4 | \
3 U2 a: e2 J( }4 |5 w" x- X5 F9 q SYSCFG_PINMUX1_PINMUX1_23_20 | \
9 ^8 q5 Y! P& A# U4 q! t SYSCFG_PINMUX1_PINMUX1_27_24 | \
5 G8 o; g& Z) q2 q SYSCFG_PINMUX1_PINMUX1_31_28( S4 t- W3 R9 f) u* p( s
);; s; D$ V) [: Y; m
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
b' p2 p. N9 ^9 k* ?. f (PINMUX1_MCASP0_AXR11_ENABLE | \6 [; w5 m t. T; Q) @" L
PINMUX1_MCASP0_AXR12_ENABLE | \/ b- o0 Y- a! P% e( l( \+ |7 j- p; e
PINMUX1_MCASP0_AXR13_ENABLE | \
) w& y8 h7 s: E4 y0 q; v' m PINMUX1_MCASP0_AXR14_ENABLE | \4 z/ E/ |$ J( `! a( N: f( }
PINMUX1_MCASP0_AXR8_ENABLE | \$ O9 h. Z! ^6 ^/ r
PINMUX1_MCASP0_AXR9_ENABLE | \
6 @, u$ V; k2 d# s) U! {% A F PINMUX1_MCASP0_AXR10_ENABLE | \
, U" E6 K: p7 @& c4 s+ t4 [' h- Q savePinMux);* t* r+ O2 C9 ^2 y& W. }
}
+ a% q/ _* a5 `, F! N# t Y+ l; ~+ u2 L
1.McASPI2SConfigure(); McASP的配置程序如下:
% H0 E0 v" g W# W8 T4 `& s( C/ R: cstatic void McASPI2SConfigure(void)
7 P* H/ A- ?% p' J! ~{
( ^7 S* D4 k: q6 D' g McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 O! U$ J; k. e; e) ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
9 ]8 n( i' }$ J5 \2 q$ F
, g& s( o8 M) _2 P* S" [# F/ L /* Enable the FIFOs for DMA transfer */
# {) t z3 v% t# C# M0 U7 V// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
4 }3 d& L) w5 N$ t// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 m5 B# A9 t+ O6 X& t; z6 ^
5 q0 B& h8 H, c, b
/* Set I2S format in the transmitter/receiver format units */* J' S/ G# e" H& g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! \" c/ d" d! X/ e* z( l9 K MCASP_RX_MODE_NON_DMA);
+ \ {1 j# @6 F% X7 V2 ]5 N/ ^ McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* V- @* Q; r) i, @" o
MCASP_TX_MODE_NON_DMA);
2 t* o0 o7 w$ z" F! c
* A) }$ D" w& z; k2 k' c6 ^- y /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& o% I3 v0 d- Z- v. T6 X. I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 }, c. \. ^8 A9 f" U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( q H3 t q% ?0 E% e+ R McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 M& w% n0 C" t% e% N MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);# A. L) ]) m9 l0 v& C/ m% S8 q, F
& R% X+ G0 P6 z3 v" @# a. w
/* configure the clock for receiver */, C/ w1 d+ W* H: U4 T+ m
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);' q* a* i0 G0 Y/ _5 V! P2 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! V5 b- q7 W8 a! g' X McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);% ~0 R9 D9 p; x3 {' B% Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; Z) q# X* L+ n/ m6 [1 N1 X
0x00, 0xFF);
" `: G) \8 Z6 X, R% Q4 k
' H- T* ^/ O2 P6 `3 m. y. T) f% `8 H. A /* configure the clock for transmitter */
8 \4 s$ z. z) j7 K// HWREG(0x01D000A0) = (0x00001F00);9 o% V6 B) c3 o6 P$ A
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);- X# K! w* A2 o3 T: ] X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);; g3 A/ k! `1 w$ Q* v* l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 F. c$ d# H$ @2 s+ X McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& C# s8 C6 ~4 y i 0x00, 0xFF);% J( h# f; {) ?% @
. D+ m# k [* z3 B" [
/* Enable synchronization of RX and TX sections */
$ N8 d) X0 _ o( B6 x" [2 e McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
! w0 z8 l" z2 J3 p: L7 `% T! Y& h: d L, B7 k( m f
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 P& @- B* `# M9 q McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ ^* \5 b8 N3 n$ D; B' R McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& a- ~& G; u1 r6 b! T
. s* G: t* t. g7 q/ I4 ~1 C /*+ E7 q8 f: C% m1 K+ o* D
** Set the serializers, Currently only one serializer is set as
/ z; u6 i; {: e! L% n ** transmitter and one serializer as receiver.
) ? `9 |+ l! _! ^+ @) H& M */
! O- l$ j {7 X1 }$ D9 D McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 E3 v% X* O4 e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
/ w, R( }# e2 l. k' @ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
. |3 G2 @) a- k" S ^' P McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);; R ]* n& T5 E7 U( @1 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);) a) M% v7 F7 Y* R s1 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);7 A% w% S* k; k% t2 ~
3 F; D2 M' y9 W+ e! {1 } McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
4 f% m/ Z5 l( I) d! M0 V' F! I
+ { B4 ?9 i a5 w /*
: Y7 N; v" p+ G' C8 E9 e ** Configure the McASP pins
8 M. q+ \( J, f. B9 s8 ?, d: f ** Input - Frame Sync, Clock and Serializer Rx, B/ u |& F, |7 E& b$ B, L* m
** Output - Serializer Tx is connected to the input of the codec 4 Y, p' @4 g2 n9 }8 d
*/+ I1 `: I7 O8 J- y; K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 V0 ?# C" X/ v7 c1 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
, W5 \6 m' z. k# U" P1 ` MCASP_PIN_AXR(MCASP_XSER_TX)
( r& U1 S+ N( |0 y' ~& J | MCASP_PIN_AMUTE
. N9 N: ?: ~5 d- e; J) E );6 P% F# B' M/ h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
' ~% \: W b; ?$ |) E- m7 Z4 U MCASP_PIN_AFSX
3 i0 }: J" ~% Z | MCASP_PIN_AFSR
9 K7 d/ ?8 R$ ] | MCASP_PIN_AHCLKX
6 f# j6 m( `/ f* Z+ P( m& i | MCASP_PIN_AHCLKR! w8 K' b% D( O! _
| MCASP_PIN_ACLKX
+ `. E; ^) e/ R3 s9 i2 P3 f | MCASP_PIN_ACLKR1 D, t& U: y. W4 O
| MCASP_PIN_AXR(MCASP_XSER_RX)8 d* D' D7 Q* W
| MCASP_PIN_AXR(1u<<(13u))2 C8 f1 v B0 q/ W7 ?7 ^3 L& ~7 [
| MCASP_PIN_AXR(1u<<(14u))4 u9 q. R$ R: g6 H& {
| MCASP_PIN_AXR(1u<<(8u))
v: K3 ?3 _; s8 c' @. X X7 j3 l4 a$ k | MCASP_PIN_AXR(1u<<(10u)): n' _& u* V* K, q# R! T$ u
| MCASP_PIN_AXR(1u<<(11u))6 h. R0 ` n5 b& v5 _5 K
);
) N1 |- E. X" z# H" e9 f, E$ {. `# ?$ ]! H1 v0 X0 a( J7 U
/* Enable error interrupts for McASP */ O/ w) D- Y& R- S4 z; S; |9 \3 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
) {' [3 w I' _9 W% O5 P# n/ Q MCASP_TX_DATAREADY
; k9 _1 O1 G" |9 u2 } | MCASP_TX_CLKFAIL ; @- n4 a( D& G- n" d4 x
| MCASP_TX_SYNCERROR
, z8 s- a9 R7 h# [- `5 a% b | MCASP_TX_UNDERRUN);2 n0 |" r- z! ]. O
, A) ?" i/ d! u- ~; U6 g" x McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,% J' ^( k# C* m. @$ L9 q) G' o3 g2 e/ C
MCASP_RX_DATAREADY6 i+ f2 L4 {8 ~6 O
| MCASP_RX_CLKFAIL
; b; |9 l' B, V- U8 j+ p | MCASP_RX_SYNCERROR
7 B: I$ n5 n+ O8 V | MCASP_RX_OVERRUN);6 e& `: c5 i j3 W" ]' C
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
" j' F! E1 I) \8 Q. J! w3 |
9 C' X# S( |. i+ E% Z}& s- v0 M$ m8 ?
6 @1 l( T3 Z% q/ S+ R3 U) J, f; P2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句 G: l7 I: @* {
static void I2SDataTxRxActivate(void)( c( L# o1 w" V& n4 ?
{
* Q& X" u @0 P! y9 ]9 Q& C /* Start the clocks */
- c; z( }" V, ~- ^/ u: m* [ McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. h, d. J3 E2 E McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);$ P6 i' |" Z T# n6 \
: O8 L/ Q+ z2 O7 e /* Enable EDMA for the transfer */; q$ h. |2 G, R S% u
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! v8 p- @# |: K
// EDMA3_TRIG_MODE_EVENT);
! N: w) b2 b) Y1 {2 q// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 h! V/ L, \. O6 `5 ?: v9 J: b// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);) U3 r) g7 t; o* O, u6 e" ~/ t! W8 K
/* Activate the serializers */! l9 t5 L6 {; m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ r$ C$ q1 c: r% \8 K1 W6 P McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
. v. I' f+ T9 H /* make sure that the XDATA bit is cleared to zero */
' c8 u* o3 d4 @- M2 d+ r while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
' B& |* D7 P( J# m% S0 S /* Activate the state machines */% {8 ~% f0 x% V8 g# I/ { V2 W( [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ c, N m8 K' w( N' E* I \ McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ w* i& ^8 T5 j8 C3 D" j& }, p McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
7 b+ P' M/ k- Z. Y/ R3 J( h}5 c# j+ v3 F* v
0 Q( U5 u9 w# J1 G! D! l2 U; ]4 a. |: b
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