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我的McASP配置分别如下:) S ?) z) D$ S- a' @" l
管脚的复用设置是:
% I, ? N$ L, x' wvoid McASPPinMuxSetup(void)
E B; Y) R. L, a8 q{
- Q3 W+ W& F9 a9 `9 K+ } N unsigned int savePinMux = 0;
% p. J8 C* w8 W savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \0 Z. d8 O, | w! @) T
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \; A* D9 ?. |6 V6 p3 R! N
SYSCFG_PINMUX0_PINMUX0_23_20 | \
2 [- Q1 [; O* N2 Y5 L0 q5 ~ SYSCFG_PINMUX0_PINMUX0_19_16 | \
8 X" T+ A4 r" g% @ SYSCFG_PINMUX0_PINMUX0_15_12 | \
& v# w6 V! F! R SYSCFG_PINMUX0_PINMUX0_11_8 | \
# q4 y% ]7 @! B SYSCFG_PINMUX0_PINMUX0_7_4 | \* V/ K# C( k4 S/ @$ a7 Y6 W# t# M7 D
SYSCFG_PINMUX0_PINMUX0_3_0);
5 i, C% N8 H; e8 a" d6 q4 q HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \* B, u! H8 S1 a# u9 V
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \1 S/ _6 L; ~. t3 l
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
" t9 X; y/ W' D7 v PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \: a Z9 S% g: J/ @* j
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
* ^- n1 `% D; D, N savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \, r; K- m; _. x. A1 t
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \$ E0 A2 q* W8 K8 r
SYSCFG_PINMUX1_PINMUX1_15_12 | \6 r, S2 ^ U* J: ~7 `
SYSCFG_PINMUX1_PINMUX1_11_8 | \
* ~& L0 h9 h7 v, ^" i SYSCFG_PINMUX1_PINMUX1_7_4 | \
" v( O9 E% f! J/ r+ g2 b. H SYSCFG_PINMUX1_PINMUX1_23_20 | \
; F; W e$ x) J" o SYSCFG_PINMUX1_PINMUX1_27_24 | \
, a- ~# K4 E+ q9 d5 U) N( s6 `4 J SYSCFG_PINMUX1_PINMUX1_31_28
7 ^* _" U W: p, r3 A );0 P8 ^( X5 j: P# }
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
4 l+ T- K9 P7 d% \ (PINMUX1_MCASP0_AXR11_ENABLE | \
' v. m" t- ^" v$ V/ w: `& l PINMUX1_MCASP0_AXR12_ENABLE | \8 U, \1 o1 M' r/ w8 R( k
PINMUX1_MCASP0_AXR13_ENABLE | \
# L9 _, }/ U0 { PINMUX1_MCASP0_AXR14_ENABLE | \& Z V& _7 M0 F+ V
PINMUX1_MCASP0_AXR8_ENABLE | \7 m: G5 L6 h2 ^2 v/ q8 d7 O
PINMUX1_MCASP0_AXR9_ENABLE | \
! R# e. P3 ^% z8 B' D, e PINMUX1_MCASP0_AXR10_ENABLE | \
6 X9 K8 f6 r# C: U2 A savePinMux);+ o# I' N Y. v$ u. ]% h2 {
}) A6 K8 Y7 b- g4 I1 Z6 P2 ?. O: `
. ^& V |. C. U* Y: b% Q1 r) q1.McASPI2SConfigure(); McASP的配置程序如下:
8 C7 T4 m' _$ p( M- }static void McASPI2SConfigure(void)' L, a2 e! \( j6 s
{
3 T {6 }4 n9 E9 k* U; x McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ?9 Z2 g+ Z2 V- i( R: m" P& Q McASPTxReset(SOC_MCASP_0_CTRL_REGS);
, ]; F6 v# v- F. b# x- z6 c7 z5 o" Z; {$ z, i6 m5 `# z& L
/* Enable the FIFOs for DMA transfer */. u$ v1 `& T, q# ?* F
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);" O* B8 o, T0 V( Y, S
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. M* K% a, O3 ~1 L/ B& B/ z
7 ^. q }, |4 T. m6 G! P2 R/ o
/* Set I2S format in the transmitter/receiver format units */) m' u: ^# l5 [2 M5 S9 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ~! s1 t1 [/ F, d" l
MCASP_RX_MODE_NON_DMA); t2 T% c' M+ C! s# q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* q, N) ^# @4 a, I. }
MCASP_TX_MODE_NON_DMA);
1 B b3 o" n' H% Q- A- P% q: B% _3 n, Z- a; p# _- Y8 q" \ G$ I
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 K" z( h' Z8 Y/ b4 z6 [ McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 \$ |( X7 L8 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; w$ A' R; w& X; g1 ^. y McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 K, ^' N3 A4 v6 q3 g" \ MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);4 p( o' l4 N6 R# _
' P: `) k3 [, a. A+ ]# k
/* configure the clock for receiver */
& d; S" a5 C7 X' d D. I// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);9 [( g+ \# L5 T6 w2 p4 _/ \8 L: @& D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 R$ D# F! D7 u9 a, H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);1 p _4 h# X$ _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 S: V- u+ [( `$ j8 {. W
0x00, 0xFF);% r# w8 P+ Q/ X5 O0 @' K
* \1 U [! ?' B+ y7 Z) c+ _$ F7 J7 { /* configure the clock for transmitter */- P6 \+ H* o7 V8 o
// HWREG(0x01D000A0) = (0x00001F00);
/ v, L/ ^5 U# p( E; ^. ]! q9 k' T+ Y// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
" @! B6 E0 \; T( ]" Q McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
$ z$ V: S( v- _) N J& X# w: g McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ o5 c. n" ]" E) g N McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 N9 T. B) z4 w8 g# L$ M 0x00, 0xFF);
1 {! C9 U5 r" f8 B. R
7 T+ z5 y8 T# { L /* Enable synchronization of RX and TX sections */ & j* n: R1 ]* f) Y. B. U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
9 f8 b# {4 ^- O+ x# ^0 _/ e
, F+ X1 v# [) F* x /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# Y8 t. b; X1 K+ w% z4 `' i, p* K' r McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 ~0 U- U; ~8 e9 L+ Y, }* \$ t McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 y7 S3 p6 h0 P6 _) `6 T: g; e% M7 C" y6 M+ `. z8 ~7 x4 z
/*6 b6 N+ d0 U$ t
** Set the serializers, Currently only one serializer is set as
% X) s9 ]$ Q# A ** transmitter and one serializer as receiver.6 l, `: |+ M3 X5 n7 Z5 E
*/1 X6 ^3 ]0 J- ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 J. R3 u& Z% M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
$ [9 k9 Q% _: x0 A! U& l/ H McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
$ _4 D: I+ ?! f( j, L$ K v McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);: j7 R e1 D- w3 h+ H, ^8 C9 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);( N1 s- h4 i7 Q* b( `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
& ^% H# t4 ?, K+ @+ j, e8 V' |8 O S/ a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);% q3 e' \9 I; B4 W( W3 z
# D1 E% D3 A9 }+ x# X* t, F
/*
2 n4 k* g* J. Y( c4 u ** Configure the McASP pins
% k0 P3 \. p: s& ]$ c ** Input - Frame Sync, Clock and Serializer Rx
' C: L" j! e% @3 W; u ** Output - Serializer Tx is connected to the input of the codec
, q7 N2 {) b/ J) b( o7 P */
7 {2 }7 j. I& L) J* l# M McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
y; f1 g8 W0 ?- u7 x McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
# z2 }& d: `3 Q9 j4 z! W MCASP_PIN_AXR(MCASP_XSER_TX)
\/ @! J. e/ y! ~ | MCASP_PIN_AMUTE
( d% {3 l. H3 u" C2 q- S6 W: G );# m) J; c* r3 a* ]0 Q, U8 D7 w/ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
9 j6 ^) \; r& o P, B MCASP_PIN_AFSX
3 Y+ }& A* P2 c' o W! q L& r* r | MCASP_PIN_AFSR
4 v9 R9 Z/ y2 c | MCASP_PIN_AHCLKX m1 Y* T+ d' [6 @* ]# a
| MCASP_PIN_AHCLKR
0 O( p- q! P# `; O; j- }7 T8 ? | MCASP_PIN_ACLKX1 B0 d! ^5 l# ?9 Y: w
| MCASP_PIN_ACLKR
$ V* S0 h0 r! J6 x% h+ P% t | MCASP_PIN_AXR(MCASP_XSER_RX); F) y7 M$ R" E7 K
| MCASP_PIN_AXR(1u<<(13u))- X3 R: E1 |4 e$ H
| MCASP_PIN_AXR(1u<<(14u))7 ?$ v& Y- c+ [; z) ~9 K- i: o
| MCASP_PIN_AXR(1u<<(8u))
; D! b- S5 o$ e6 D K& B9 }) } | MCASP_PIN_AXR(1u<<(10u))
% d& }& I$ N$ m8 ^+ I: \; J( ?9 T | MCASP_PIN_AXR(1u<<(11u))& Z) y' m2 p9 x# N( `# W- v
);
( F( B0 t N$ y
t6 Z& j/ _. } /* Enable error interrupts for McASP */
& f7 P4 |! F$ p7 {0 G+ a McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
' _8 v: y( B) B0 d5 f8 M7 |8 F: s9 X MCASP_TX_DATAREADY, F# U6 c! I" ?; x h( L; e( [0 `; A
| MCASP_TX_CLKFAIL
6 Z4 g. C. J; k8 ?5 N | MCASP_TX_SYNCERROR/ V7 I6 q) j. y8 }$ H$ T
| MCASP_TX_UNDERRUN);4 U" K/ V o. Y# Y# ?# w
: ?! D) P. k7 h$ }6 I
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,! Y+ G4 Z2 _ y. N2 d& Z/ }" Y, [
MCASP_RX_DATAREADY
# [ b. U- W) H% D U& s1 a1 w | MCASP_RX_CLKFAIL B q* R2 E( J+ X; F9 Z! |+ s8 o
| MCASP_RX_SYNCERROR 8 ? ^% ]6 ]" D8 b; i3 U
| MCASP_RX_OVERRUN);
9 D/ j( F0 m: d( N//MCASP_RX_DMAERROR MCASP_TX_DMAERROR- V2 x1 F" ~& D+ Q
1 @0 f8 m9 A+ `. j4 _) w+ Z8 B; h. ^
}
' N: c# x2 j$ Z* W- _$ c% Y. H1 n
* R' A$ Z/ h2 i2 Q2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
& @# X9 \8 z. ^static void I2SDataTxRxActivate(void)
7 b: {) u6 d+ `7 I, ?, D{0 b3 |" j7 c4 U1 }
/* Start the clocks */6 H( ]; p( @: v" l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( T7 f0 b4 q' Z) v& W/ d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);5 b8 b: a; j* m$ @4 w; ~* P
- J& [/ R7 T- L1 C3 }! J /* Enable EDMA for the transfer */
: ]( D0 f: n1 ?8 X# Q: h// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 n3 ^' x% V- v- A3 j- I
// EDMA3_TRIG_MODE_EVENT);
# R6 ~, _9 P1 U5 r// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' D+ Q0 a7 E4 p6 t8 F r$ s/ S// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);' _$ W* z$ M4 P
/* Activate the serializers */
/ y* y4 C. S6 O+ S McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( o/ }: N! j- Z McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);8 z" O+ M9 K6 h6 b
/* make sure that the XDATA bit is cleared to zero */
: a5 v, j/ k9 @# d/ e n% R while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);& |9 t6 k4 F$ q" O, F; e
/* Activate the state machines */
- L% ]( p5 a6 D McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 s" @ l( W" C h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
c5 j' y/ a, J% ? McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
& [1 A2 S' T2 ]- W5 p}( P& `2 K4 I0 U
; v8 X: u, p, I5 m, b0 O |
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