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我的McASP配置分别如下:, J1 `" Z: a3 ^; R9 T
管脚的复用设置是:6 f K9 F: `& j0 D
void McASPPinMuxSetup(void)2 x* d! a# P+ K( h
{2 s1 U4 w/ q. m
unsigned int savePinMux = 0;! q' R. F6 f; l) ~& S' N
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \% L, u7 K% D# O: c! R
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
9 c: g+ |7 d- y7 \% R7 X9 k. V- u SYSCFG_PINMUX0_PINMUX0_23_20 | \- D) |- V& `6 Z9 n5 w0 m. v8 X
SYSCFG_PINMUX0_PINMUX0_19_16 | \2 ^) K& y1 b3 d- s9 M5 v
SYSCFG_PINMUX0_PINMUX0_15_12 | \% h) ^9 n' m C; M2 y7 T! l j
SYSCFG_PINMUX0_PINMUX0_11_8 | \
# y( c! v& ]7 s: H7 Y SYSCFG_PINMUX0_PINMUX0_7_4 | \
$ w+ L6 R1 ?, B; t SYSCFG_PINMUX0_PINMUX0_3_0);
) v& G# ?6 G. Z HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \8 U6 E/ J) q# Y
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
: d4 r: x6 w, T2 C( u* `4 K- w PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \9 U9 G; y$ i# X3 J( |
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \1 c5 ]/ k0 z' w5 N; n0 k* ?
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
& `+ @2 `! M+ x- _( C+ E( Y savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \$ S1 A# v! y7 S# K! o$ o( ~! G
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
* p2 S3 Z0 M6 P5 X SYSCFG_PINMUX1_PINMUX1_15_12 | \, t: n( o1 Z+ E7 X
SYSCFG_PINMUX1_PINMUX1_11_8 | \" W1 }) y& b: C) S- _0 u5 i* |
SYSCFG_PINMUX1_PINMUX1_7_4 | \
" f1 w( ^: c$ P6 _ SYSCFG_PINMUX1_PINMUX1_23_20 | \1 P7 o" K, }9 R5 H
SYSCFG_PINMUX1_PINMUX1_27_24 | \6 v7 V& l; T( l1 b$ }
SYSCFG_PINMUX1_PINMUX1_31_28, D v& n- s: v% Q/ u! u/ B
);
- t- U1 i' q- C( A, M" w, X HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
3 c8 W+ G4 X7 p; p (PINMUX1_MCASP0_AXR11_ENABLE | \: E2 X! I# `$ y5 q; Z0 z
PINMUX1_MCASP0_AXR12_ENABLE | \
! E0 H* J# Y9 T6 u# B3 O PINMUX1_MCASP0_AXR13_ENABLE | \
* K1 W+ b4 m! b2 g/ W PINMUX1_MCASP0_AXR14_ENABLE | \: L9 N& P2 n t6 k* [ S: [
PINMUX1_MCASP0_AXR8_ENABLE | \
4 l1 P/ }2 c5 A% U PINMUX1_MCASP0_AXR9_ENABLE | \
4 x6 p. o* D( P6 C% n/ s' L' u PINMUX1_MCASP0_AXR10_ENABLE | \
" R5 L! _% |3 g4 I% b Q8 m0 e6 i savePinMux);1 J, z& ?! D4 ^% A5 O8 Y5 }- z
}7 T4 v5 D+ H$ P, S" W8 R& l
) w7 h9 Y" S4 b h1.McASPI2SConfigure(); McASP的配置程序如下:- C/ v) G; c( v3 Q* ~0 b
static void McASPI2SConfigure(void)4 o. `6 B$ F- e4 }% u
{# j, j9 c. O: K" v% p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 }$ ~5 d% ?; i9 u' c9 u
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
+ e$ V- u% Z( [$ d& r: ^+ P% k `( Q. s ^: ?
/* Enable the FIFOs for DMA transfer */% e( B$ L& U1 o% d8 D
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);- Z( x" A- M" D6 ], W7 x
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 M& }) D7 Z* i9 s3 s/ P! Q9 Q) b9 m1 w
/* Set I2S format in the transmitter/receiver format units */
+ I v: ~6 y& [7 P9 L. _0 ^ McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ o. S5 [' m z0 S2 ?
MCASP_RX_MODE_NON_DMA);2 O( ]- n% ?! h% @: c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: N8 Y& M- N4 e2 N! p MCASP_TX_MODE_NON_DMA);
7 @5 R, ]& B" A% _7 B2 G+ j/ d3 E+ G, c
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 \# n3 x3 c# E' {4 D, j McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
w" c8 w2 i5 m. V5 ]1 O2 Q% j MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: @/ \+ w; L7 C" u) x& Y$ w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 O( C! Y* T. s" v e# j0 r$ K
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
. v5 x X c2 e9 w7 `0 r% ^3 x/ ~5 y* S7 X
/* configure the clock for receiver */' {5 R- C' f c: W3 X2 L# X2 u c0 ~
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);& C. r8 v9 y. q! G) p0 t, Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: Q" p* L) A! E2 [' l% J7 d McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);% k; E' K$ f( p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. Q. p+ ^2 n1 {: E3 D
0x00, 0xFF);- T! M* U2 Z. |9 a: j0 ]& Z
# Z1 n3 `8 ?: {7 e# Q. J! y
/* configure the clock for transmitter */
, e& E ^. w0 T4 k( d: x+ A* d+ ^// HWREG(0x01D000A0) = (0x00001F00);+ a$ B& ?: {6 U- A7 N
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);& U) z0 r/ D& T& ~2 e! a; Z7 R$ [. m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);2 O! }' j7 H$ F* S( U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ f( r% Q4 H2 R' H2 ] McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 Y& d0 G) Z: q
0x00, 0xFF);% `! N3 P$ z4 L8 a
- Q$ Y8 L3 W+ ?! V$ S5 @ /* Enable synchronization of RX and TX sections */
( Q: n) Q; U) h- W3 W& S6 A' l McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);& Q" l' x' o7 V0 |
3 E+ H$ W. @; o/ X /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; }, U8 D0 s) n1 Z7 P; R" Y McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 y" p; V1 }0 u, f, \8 ] McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% c8 E" [+ G/ b4 l" F$ Q% }
/ e$ w2 k. w) [ /*
9 Q5 w4 h6 k$ E5 T; Z ** Set the serializers, Currently only one serializer is set as
0 M* v. ~0 S: x6 X* _ ** transmitter and one serializer as receiver.5 y/ j! t n! H8 u9 n. q
*/% t: d1 W1 j' n* j7 q: O0 ]1 y, j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 S! z: r# H0 W9 Z; {$ ^0 I6 G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);. }) `# R$ T& | C# `1 I% U: E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
9 q8 p% ~9 e7 [ y" p McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
6 b; f# x& k- D4 T" T McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);# o8 @; P$ R7 P/ T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);+ [# X* y) K& t7 Y1 N( ]% M0 q3 F
8 \0 U% X/ Z) \. P% G McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
; ]4 t. O0 I9 J% Q6 L3 {8 s z/ @; W9 A6 T4 q% H$ i
/*: v% x# x3 x/ r( j) j0 r, i
** Configure the McASP pins 0 V" R2 C6 b! S) m8 S8 P; M+ P
** Input - Frame Sync, Clock and Serializer Rx
7 D4 v, q" n7 b. n: }0 k$ [ ** Output - Serializer Tx is connected to the input of the codec
% a6 a' s1 g& k- D! j4 y */* a2 P/ V1 F- d+ B4 V) ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ i) ]5 c$ L# b3 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,( s$ E) q# x3 S) e
MCASP_PIN_AXR(MCASP_XSER_TX)
9 v3 P* H7 ~9 H3 ~; J: v0 s* [. o | MCASP_PIN_AMUTE" t6 O) {2 b7 t$ Z7 D! T
);: O* ~# H- x% T( N; X/ H: x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,$ S% K# x8 Z$ l1 _: C
MCASP_PIN_AFSX% D8 d% B& r5 @3 o& D
| MCASP_PIN_AFSR
- m# _1 v# q7 Y9 Y' U/ s | MCASP_PIN_AHCLKX
- x9 k; Z# }& p9 W& `- K | MCASP_PIN_AHCLKR
: r3 p. {" j& I4 h |6 Y$ I) O0 d1 F | MCASP_PIN_ACLKX
7 [" q v3 t1 S$ E | MCASP_PIN_ACLKR
( R& o1 P6 ?( I9 U5 x$ O, ^ V | MCASP_PIN_AXR(MCASP_XSER_RX)
; G' w& D' S6 r3 p- ~ | MCASP_PIN_AXR(1u<<(13u))# ~. v C) _) H4 P# w/ V% Z
| MCASP_PIN_AXR(1u<<(14u))& g* r% \- V( h( y
| MCASP_PIN_AXR(1u<<(8u))
q1 o8 n. b2 D0 ] x) [ | MCASP_PIN_AXR(1u<<(10u))
0 _2 w8 j. x9 b7 f4 ?; x4 m9 ] | MCASP_PIN_AXR(1u<<(11u))
0 \; q9 m w4 A$ u, F7 X );5 s* ]* i9 Z! o9 I8 T
, z! C+ b, {. }" I+ c /* Enable error interrupts for McASP */$ @% W0 ]" U% e2 X z; Y* `6 T: Z) n+ }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,: Z+ f8 e. D5 E4 C& y u% b$ s
MCASP_TX_DATAREADY4 D. y! Q5 `# f$ w' x$ V
| MCASP_TX_CLKFAIL 9 C' x) i! [2 s0 O& t/ I
| MCASP_TX_SYNCERROR
4 k5 \2 L0 ?# Q0 W+ m | MCASP_TX_UNDERRUN);
% o6 `0 p" ~/ _! b) ]6 v D7 h
, s. c6 L7 j# P/ c: @' n8 Y4 J- G8 P McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
7 q1 B( w3 n& L. | MCASP_RX_DATAREADY/ Y1 T$ J. r1 l; Y. G
| MCASP_RX_CLKFAIL/ ` v$ o$ E9 R" c! Y0 _ Y
| MCASP_RX_SYNCERROR + |2 e; \% v0 E! b6 ?* k) V
| MCASP_RX_OVERRUN);
r5 }0 D& H7 Z6 n2 c' m//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
/ y: n" y( a! @& H) R$ I
+ i2 Z8 R' f) J0 s$ M' I5 j9 [}
, K, A5 \) R9 T% l5 N+ x6 x) b
5 a8 o9 ^+ l2 L) o4 H2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
7 \1 f" ?0 r5 l5 \5 d% U5 B* ]static void I2SDataTxRxActivate(void)
# O9 V1 O5 ?! C( `; U3 b6 F# u{/ c# Q( X4 J* N" {/ y* t5 l5 v
/* Start the clocks */0 K7 {+ J0 N3 o& E3 Z3 Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 r! [0 L E+ B Z- S9 N/ @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
0 |2 r* ~$ O" t6 o) h5 C9 G% e+ h5 c) ^: G
/* Enable EDMA for the transfer */! I: N- Z2 u, a, P
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: w6 F1 t- W- x/ V. _& X: U// EDMA3_TRIG_MODE_EVENT);
9 {, F; p3 V9 C- w7 [// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,6 ^% ?+ z4 W) X8 ?6 c
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);9 M0 ]* t# x3 R! h, M9 ^; }6 P" p
/* Activate the serializers */2 k% X" Z6 a! s: D1 w" S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, f5 o+ A& D1 o% l) E4 c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);' \- y4 Y, u4 e: x9 j1 C
/* make sure that the XDATA bit is cleared to zero */
# p5 p, D4 } B4 E& ^ while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);; w3 g7 ], J8 X! P) D
/* Activate the state machines */
6 o. G! n$ P: C" y McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 ^$ d( }& {9 g0 H2 u. u4 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 R. d+ b2 E! [" q$ p McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);9 t: L( ]6 f9 G+ \8 W& U
}
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