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我的McASP配置分别如下:0 C' D( s( M) {1 i: L4 ^# c, a
管脚的复用设置是:
# |5 q4 t" B: y/ S) ^/ s% ^1 }; a" Fvoid McASPPinMuxSetup(void)
1 |' H; @6 Q V. H* p8 m{
/ c6 M& g w/ Z- X unsigned int savePinMux = 0;( d! A, f& \: j7 j2 T) ` u1 h
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \0 M/ w$ ]# ?9 J/ J) S7 \
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
1 c4 j/ L) A# h g( a SYSCFG_PINMUX0_PINMUX0_23_20 | \* R9 ?! ]! l% Q# m$ q+ F, r
SYSCFG_PINMUX0_PINMUX0_19_16 | \: m! W$ j9 o" m. R. u
SYSCFG_PINMUX0_PINMUX0_15_12 | \% }: b5 m: B: n# W. M. M2 {+ D
SYSCFG_PINMUX0_PINMUX0_11_8 | \
, e( O, A. K, M+ r. F SYSCFG_PINMUX0_PINMUX0_7_4 | \
E. ~5 Q" w7 f# l- h3 F5 T- ?* | SYSCFG_PINMUX0_PINMUX0_3_0);
5 D( N+ l; d, o$ G1 _0 c HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \5 D! E+ Y: M$ `! y
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
/ ?" \+ U; U7 M PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \" M# g) z- I+ m4 [6 y$ |
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
4 C+ J& N, U1 H3 W PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
' j7 k; ~6 L. w% t0 k m l* r savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \" R5 j) W4 H* y ]
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \0 M/ I% J' k! `0 B9 X; s1 }
SYSCFG_PINMUX1_PINMUX1_15_12 | \# o8 L/ F7 k! M; V
SYSCFG_PINMUX1_PINMUX1_11_8 | \
: ]+ P4 C# ?4 t7 q# R) w' @7 `, x8 H SYSCFG_PINMUX1_PINMUX1_7_4 | \
4 x3 E/ h# q3 ^4 w SYSCFG_PINMUX1_PINMUX1_23_20 | \! E& }! q' t( e
SYSCFG_PINMUX1_PINMUX1_27_24 | \& @- A# n0 p1 \$ s! l' C
SYSCFG_PINMUX1_PINMUX1_31_28
. g! D, a1 y7 l+ n1 _7 Y );0 i& S* X8 O1 ?- y9 }; k* l
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \7 }, K' G: X+ z# { \
(PINMUX1_MCASP0_AXR11_ENABLE | \" ?% q" r7 D& H0 {. I, {5 [
PINMUX1_MCASP0_AXR12_ENABLE | \! L; W: X- X: l1 ?( k
PINMUX1_MCASP0_AXR13_ENABLE | \: K$ S3 J# d' w2 l
PINMUX1_MCASP0_AXR14_ENABLE | \* s1 g/ \1 u m) R
PINMUX1_MCASP0_AXR8_ENABLE | \
- U# s% O1 U* a7 a PINMUX1_MCASP0_AXR9_ENABLE | \
* E/ U' Y2 t2 E- Y6 ^ PINMUX1_MCASP0_AXR10_ENABLE | \" F$ \( l/ U( l
savePinMux);4 T: e( ?, \$ c) t
}
4 l' O$ w& N3 r
: u3 s" Y3 F9 x( l/ q1.McASPI2SConfigure(); McASP的配置程序如下:
1 k1 ?- x: Z% J2 J n- ^static void McASPI2SConfigure(void)8 W. \& j0 n% ~# j/ b2 c( j. u
{
3 S% N# J" t) J' J# ? McASPRxReset(SOC_MCASP_0_CTRL_REGS);* t: h6 L% |, d* q- h
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
$ I( s( \: R# s" a; }& H5 ]7 T! N! j m4 u) g
/* Enable the FIFOs for DMA transfer */- R" J9 ^2 j* }: J+ d
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
& ]5 T9 E7 ]# [7 Q7 q// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) B2 {: p. Z9 ?$ V
, @: j# v- e. ~& c. d
/* Set I2S format in the transmitter/receiver format units */
" S- A$ N" K) F6 X" I McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ a- i3 i1 u" n" y9 E; K
MCASP_RX_MODE_NON_DMA);
c4 m. G* L) }2 W2 j McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Q0 w4 ]' w3 e% y MCASP_TX_MODE_NON_DMA);
, l8 v2 |+ m( w# w# o9 y# a- A5 Z4 I9 x* G: |
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
f) b+ O5 ~2 U6 n McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 I$ X/ g* D" W: N6 R MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; L5 R0 h8 X& z' g( O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! @( k! y, c5 c9 M' l0 i
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
) g6 S: h u' t, v9 A1 b9 ?3 E& |) j
/* configure the clock for receiver */* Q4 H8 O& I3 A( `4 X% k9 ]1 O* O
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
: y5 K# [7 E+ q$ i McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 Y- g! w8 o7 j! p McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 H1 e9 Q* N0 A8 j* I McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 Y, L7 j5 }, B: y% x a
0x00, 0xFF);! Y: D% ]7 i. N8 v$ S
# J5 V1 n$ N. H8 b
/* configure the clock for transmitter */$ K, `. C3 B! u; _8 z7 |7 \
// HWREG(0x01D000A0) = (0x00001F00);" v: H9 V" m; ~; N% S
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);" D, g4 G, Y j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
i7 @& k9 V5 `, ~! u McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);/ k- h ~3 g% G+ g, {7 M2 N5 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 {5 E+ n* y g. Y# b+ f4 l# @7 i6 |" B
0x00, 0xFF);4 F! {# Q9 I) ~4 Z
& N+ _/ _& }+ t4 s /* Enable synchronization of RX and TX sections */ - N* _' m: G. N& O% _ \9 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);$ j7 W1 M3 C( g2 P# d
2 X1 S! \! A8 c' \: V* E" c
/* Enable the transmitter/receiver slots. I2S uses 2 slots */4 l6 _4 P. `8 i) c }. K. ?% t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 c- X$ P) B1 ?0 g; C; A! } McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# Z: L9 e& E. d2 k
$ A G! c8 m8 e0 l0 v0 s- \: R- @ /*
3 G* u5 |' N0 r& ]! } ** Set the serializers, Currently only one serializer is set as
/ h( |: w, O( }/ z3 s9 {- y4 j ** transmitter and one serializer as receiver.3 B* k. |; E7 k$ L6 U0 L
*/; A5 C( i) j' V, y/ ~( J$ ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 m- K. c% k, z; a4 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);& s' d! O# b2 g8 A7 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);! L* P9 g F4 s( Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);+ u \/ J( K9 M3 H+ [% B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);/ Q) p7 e% E K" w/ t" C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
3 i, x5 }7 P* @& H3 x: z/ a- k' `0 M# p% v8 T M4 o7 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);2 L$ y8 @' J8 D$ S8 h O$ @
! a2 O6 q, o6 p, U/ I m
/*1 k4 A, {- S \5 N0 B7 a
** Configure the McASP pins 9 ]( S8 o! t) X# j/ ?/ l
** Input - Frame Sync, Clock and Serializer Rx/ @3 @1 H7 ^ w q
** Output - Serializer Tx is connected to the input of the codec
0 x3 o# N7 @# f8 b u */
8 f5 r) k- ~0 P3 r5 K McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* d: n0 B' n: j7 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,4 u. N! Z4 L: c$ C& S) P- l! r/ h
MCASP_PIN_AXR(MCASP_XSER_TX)
1 u7 [5 R( @9 k4 v$ D | MCASP_PIN_AMUTE
E" W. ]' I; ^% a );
/ \/ `" y a: K2 n McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,& K- R, o# `6 T2 A2 g; h
MCASP_PIN_AFSX
2 e7 |- p# m; ]3 z, x; [1 s( z | MCASP_PIN_AFSR
$ I. c3 W, M/ F& o& t | MCASP_PIN_AHCLKX
7 q& B$ i& h" e | MCASP_PIN_AHCLKR5 G0 F$ C- F& {: |6 b
| MCASP_PIN_ACLKX
9 l" P, {9 J% G! {3 M$ l | MCASP_PIN_ACLKR
) k# g: a( G+ y | MCASP_PIN_AXR(MCASP_XSER_RX)/ W5 S% \& f( x1 _6 m' ?4 c7 f
| MCASP_PIN_AXR(1u<<(13u))( Y6 t1 L5 _4 C" d& D8 [- D) \
| MCASP_PIN_AXR(1u<<(14u))" Y7 h! S5 y4 B& x a# o9 ?: Y
| MCASP_PIN_AXR(1u<<(8u))0 I j% }* F1 @/ M9 d
| MCASP_PIN_AXR(1u<<(10u))" J8 z u) F% k
| MCASP_PIN_AXR(1u<<(11u))
& E B9 \% g, R, z( x3 f );2 G" `2 Z4 ?# I9 W% d0 g8 r) f
9 ]. _3 N0 E0 {& [- @$ W5 E c
/* Enable error interrupts for McASP */
& S0 S9 |$ w2 N. S/ u$ ] McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
9 k1 l1 K' U) O/ R2 c MCASP_TX_DATAREADY
1 G0 j2 `. m# j: m, S4 z1 w | MCASP_TX_CLKFAIL
* a F7 Q \! u+ ^* l- ] | MCASP_TX_SYNCERROR) g7 ]0 `1 r" c5 q3 u+ x" X' F2 |
| MCASP_TX_UNDERRUN);
. Q% G6 a' Y; i9 }& x# F) ?. G5 h! r5 l3 G i2 w' E
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
: q( {/ g* `3 O; M4 E1 E MCASP_RX_DATAREADY7 {+ M& J* U2 k0 f
| MCASP_RX_CLKFAIL
7 X% e7 L7 Z: s | MCASP_RX_SYNCERROR ) y- r2 K4 s3 d) f
| MCASP_RX_OVERRUN);7 u! B* O( v" d8 d4 }* D
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR) L8 C6 g8 b. F
& p- {' N* }% L7 K
}4 K5 H4 ?0 v" E/ _
6 i1 v% ^$ |4 z- I# D
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
( n1 r' l7 K& Q4 h' T+ ^static void I2SDataTxRxActivate(void)( _2 X1 \9 Q9 y& f4 u: H
{
7 U* t7 ^$ T; n% S: { /* Start the clocks */, c1 E$ A0 K1 l x: t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 F6 V/ f9 k- K# _. a* Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
: s) C+ j3 A3 z8 d2 C: \+ T
) w& \# E. \+ ^7 i" F5 S /* Enable EDMA for the transfer */
- @- c4 f4 P) Y' a4 @// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 V* R( `2 p, X# s2 K// EDMA3_TRIG_MODE_EVENT);' o9 _& z/ d+ y1 R
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS," _* L o7 d! q" o3 \' f
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
# Q/ v7 \8 l. _1 Q; z5 p6 n T) N /* Activate the serializers */+ H* M$ u, [: o6 A) H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ ~* e" j6 s( P* [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);9 T9 M ?7 p! y. ~6 F2 \
/* make sure that the XDATA bit is cleared to zero */! F7 ~6 N0 ^: Z: E# k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);' F O# O! u$ p9 i* y8 u' o+ D
/* Activate the state machines */
+ }# B8 {* V( n' t+ q J McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 I3 C+ d+ P7 c" U' ?/ o1 ?# T4 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ J9 q" T3 P- L6 u" ^4 f
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);! E' {- A, a' C$ D2 L/ i, U
}
1 [) t) j' {5 L% R4 d' u0 r! H' p' s6 Q- ]. E
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