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我的McASP配置分别如下:8 C: Q& G. r! V: C
管脚的复用设置是:
" X2 T r& Q" M; g6 _void McASPPinMuxSetup(void)
( R' |: L, v0 i1 _/ l+ U2 U{
! K- @- o" d# ?7 ] unsigned int savePinMux = 0;
: f( j+ n) y8 q+ b/ C6 O( H savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
6 R1 B+ y: g3 L$ [$ v ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
. {2 s) y! ~" L: ?. K2 ~ SYSCFG_PINMUX0_PINMUX0_23_20 | \4 q$ d! c8 O6 H$ b, p
SYSCFG_PINMUX0_PINMUX0_19_16 | \
- F! l( H8 `- S0 c* r% U) D5 Z SYSCFG_PINMUX0_PINMUX0_15_12 | \
8 |3 q& ~5 L! d! |* S SYSCFG_PINMUX0_PINMUX0_11_8 | \
3 f8 d% ^- i% p E$ {' B! M SYSCFG_PINMUX0_PINMUX0_7_4 | \
( A0 N3 w r H8 {: \& v8 { SYSCFG_PINMUX0_PINMUX0_3_0);
3 }! X( ]0 g, W" a2 S% q1 [. y HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
. D/ Y+ b* v" n/ t# I (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \: D6 U, V! B, [( V
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \( k7 H3 t; _: N! Q; G: k
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \3 v' d3 C9 A0 k2 ^
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);' C# D7 I& s7 h
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
0 ^8 _7 Z9 k2 b! @+ H3 J$ ]* ~, l ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
% L4 K) r' X+ ^1 } SYSCFG_PINMUX1_PINMUX1_15_12 | \
$ Z0 V+ F1 |# Q; s# r( j8 l SYSCFG_PINMUX1_PINMUX1_11_8 | \
) C8 @% J- \: m: v2 p SYSCFG_PINMUX1_PINMUX1_7_4 | \
( P/ ~0 B+ J3 y5 M) X+ G SYSCFG_PINMUX1_PINMUX1_23_20 | \$ _" D$ F: B5 d! J
SYSCFG_PINMUX1_PINMUX1_27_24 | \! |- }2 U, G% G9 A5 L/ h& f/ [
SYSCFG_PINMUX1_PINMUX1_31_28/ a5 U, s0 i4 c
);
% k S; i) j0 f HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
$ U! E/ h5 I4 f& w. _1 L5 w (PINMUX1_MCASP0_AXR11_ENABLE | \
n g0 A# o+ o3 G8 z6 B PINMUX1_MCASP0_AXR12_ENABLE | \2 S: W9 O5 T! R
PINMUX1_MCASP0_AXR13_ENABLE | \
3 s% r5 d0 Q" ~; D+ i' v PINMUX1_MCASP0_AXR14_ENABLE | \
: l: g0 F9 @: T/ I PINMUX1_MCASP0_AXR8_ENABLE | \
9 D: ~6 k( w2 H% @: z# |4 g PINMUX1_MCASP0_AXR9_ENABLE | \/ x5 l ~- a! a5 h6 V
PINMUX1_MCASP0_AXR10_ENABLE | \- c" J7 L, p7 f) n% `) J4 m
savePinMux);
7 y H- H# R8 ^" |- y}! h* i# ?( F+ Y0 i; `
9 I$ A$ [/ \: g5 M3 v
1.McASPI2SConfigure(); McASP的配置程序如下:1 y; h) O: N1 _8 b# y
static void McASPI2SConfigure(void)3 h# ? H" h- j# V
{
- C9 k; k8 {2 q$ { McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ P/ p3 s3 r9 K/ c0 `: _# N4 n! R McASPTxReset(SOC_MCASP_0_CTRL_REGS);
9 `7 Z# U% w8 d4 D Z. j, Z+ C* ?, Y1 W0 k, D
/* Enable the FIFOs for DMA transfer */
0 S5 k1 w7 j- L9 H4 o- U, w// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);) {% }: Y9 t+ _7 `2 H
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 N7 r7 l" h3 x8 R2 S/ h1 N b
$ S8 A1 M& V$ X$ U: d /* Set I2S format in the transmitter/receiver format units */
2 q |- _5 {/ P' g7 X: X$ q+ s McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 x5 x1 n6 k6 p
MCASP_RX_MODE_NON_DMA);
$ _" N# S o( b6 i+ Q0 f McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 D% o% p4 ^1 o3 g2 N
MCASP_TX_MODE_NON_DMA);
7 g1 r3 d6 K: J, i q# \/ D
/ q% J. `. p) w# V9 k+ \" j! T0 i3 d /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% u! _1 _; y" }" H3 \ d McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + z9 z' W: A! a0 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 d; o& ^4 [, r& ]! \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 z( f1 T* ~* Y: E# f7 b6 y# ^ MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
$ S4 _# @! K( j; Q. f; Q: U* V& d/ n6 _0 M$ X/ K W [
/* configure the clock for receiver */
3 _1 N& @2 y* v, I# W5 H// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u); r3 b( p' u# O' f8 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); p2 X8 W( m* h; Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ?/ l- F1 Y6 s' d. ^, L3 f McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 n8 x- `) \5 K8 n
0x00, 0xFF);. s7 ]. S9 D/ A( [9 p
- M" v S% T" G' Y+ A# a /* configure the clock for transmitter */* e; B* Y) `1 h
// HWREG(0x01D000A0) = (0x00001F00);; z* d" j% \. l; ?
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
( h, T. g. C1 R B- y* z5 ] McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);4 e5 `! i. m; [+ u+ j: @9 A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);) D, _0 b- s! a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
X+ r! L; g$ ?% z 0x00, 0xFF);$ W7 _% \6 Q- \5 s, ?( Q! `/ V5 a
; B! G; C% F- z /* Enable synchronization of RX and TX sections */
' Y0 Q) s/ ]7 q9 Y/ E8 r2 N% X McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);( `. W& G" ^7 A3 v
- Z6 _0 ^6 @8 q /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 B/ T7 i4 c: `( t* r$ M/ ], O+ m, H0 W# H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) k9 z2 Z& g6 e' K3 B$ ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# a& T1 B8 I% }% I# y- V6 s
! _8 v9 g8 S, s8 R
/*5 z4 k7 [+ M6 J
** Set the serializers, Currently only one serializer is set as# S9 t% g1 ~* F$ t3 ^8 L1 z
** transmitter and one serializer as receiver.
7 l: v% t A/ M8 ?) M& e *// R% W1 C& c' M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ F1 S3 q% T; w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);1 j* y# f; A7 D% {4 {' }$ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
$ C. `- G" _: S& P& y% d8 [ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
! v7 {6 J& }3 h/ G& S) T7 O& r McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);4 F1 r4 ?" g3 N' i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);& g X$ ?8 h* w$ s: _" U, B B
1 U; l1 z# H3 z. D* { Z McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
: E- z) x& }0 W9 @% t+ i* _% |2 X; B( D0 B6 t9 ]% b( q3 {( c
/*
$ ^" b2 T5 B7 r& S/ d) ^ ** Configure the McASP pins 6 M1 l9 ]. i& h" ~0 _
** Input - Frame Sync, Clock and Serializer Rx9 `. |# K3 V Z. L( z, B! c
** Output - Serializer Tx is connected to the input of the codec
9 G$ s* K6 F& ?% w% m */! N3 l _2 P" [: ~# k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: z4 S2 D+ ^* Q3 q. q" V5 h McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
3 ]# a* n* t8 s9 `% y& J4 \ MCASP_PIN_AXR(MCASP_XSER_TX)+ S3 f( {% L; ?& S, G- z
| MCASP_PIN_AMUTE
: ?+ _- F1 w$ k( J );
3 G w6 k) C! W; D6 D McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
# a. U4 ]1 T0 o MCASP_PIN_AFSX
1 C+ E& J! U6 G: } I4 r ?* I7 k | MCASP_PIN_AFSR- U$ T! f% U3 ]% L+ i
| MCASP_PIN_AHCLKX
$ u' O6 H7 m( c6 V, j. p/ W) q% k# |7 _ | MCASP_PIN_AHCLKR, @( P* Z0 Z$ ~( P% u6 X
| MCASP_PIN_ACLKX
' p( [* M+ D# D/ Y | MCASP_PIN_ACLKR5 i" l5 @/ N, ?$ F4 B' t9 ?! N
| MCASP_PIN_AXR(MCASP_XSER_RX)
; m2 r7 u9 r' F0 S$ B) ? | MCASP_PIN_AXR(1u<<(13u))
. n4 f* C- \, D8 x/ H | MCASP_PIN_AXR(1u<<(14u))
6 J8 B# w( t6 p5 u5 {! X2 J | MCASP_PIN_AXR(1u<<(8u))' | v. `5 B+ Z2 Q* r
| MCASP_PIN_AXR(1u<<(10u)), t. X x+ C, `- Q' Y* O
| MCASP_PIN_AXR(1u<<(11u))
: n# _$ y L5 n, k7 f+ [ );( t" M. A- ^" ^0 p( p
6 t/ F4 G1 a$ k! b# r /* Enable error interrupts for McASP */
+ m& ^# L! v' c4 O x# ] McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
4 [9 L- u0 \0 q4 ]( r6 [$ b! ~. @ MCASP_TX_DATAREADY
4 ~ g% i" v8 x! r' E | MCASP_TX_CLKFAIL , _5 V3 W, V0 s; R) t
| MCASP_TX_SYNCERROR
: m9 B9 a& ~3 Q* V" } | MCASP_TX_UNDERRUN);
1 }5 ^' b* U! w: G; ~! {6 E# k) Z+ w$ @8 Y6 z
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,4 s9 [3 j7 Z- l3 { c* X5 G0 [
MCASP_RX_DATAREADY+ F: a6 P0 a5 X2 c$ N
| MCASP_RX_CLKFAIL3 m& t$ h4 X: {9 E
| MCASP_RX_SYNCERROR
9 [3 [4 E# l; f, e* o6 Y | MCASP_RX_OVERRUN);
9 U- s1 K' |3 _4 v( L/ V% K" P, p//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
2 L8 M. s% U9 R5 _2 H6 F& {
5 W* h4 m% \& z$ u( V}% a+ w/ C f9 |; B U
+ I3 k p' [$ H; X5 y9 ?$ ~
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句( c' K j; ^9 Y, [0 x
static void I2SDataTxRxActivate(void)
# ` k N. { z2 l' T{
$ P5 \- F: c6 c3 ~: q8 S* s /* Start the clocks */* q3 }* c& t K( k$ q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- o8 B9 v0 J! \" C, r2 X McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);) [4 d/ U! r- H5 } U+ j
+ |' a/ h7 g8 A4 \* B o% | /* Enable EDMA for the transfer */+ H) s8 }' F& b
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 H# e1 k) O5 b% |2 |// EDMA3_TRIG_MODE_EVENT);
8 Q9 T4 v/ _- c8 S! g6 R// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,- H5 d7 v. x+ d1 ^9 h- @
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);- f+ o1 X( t( L2 x ^
/* Activate the serializers */
1 w* l6 h0 L( {# P! y# z8 p McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" E, c% M0 G) y, @ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 g6 y: N( T% P; F /* make sure that the XDATA bit is cleared to zero */
% V# Q( Q1 Z- s) y while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
$ J8 e; I9 q5 @ /* Activate the state machines */8 L' v# V. q. b' Z0 T0 ^: g0 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 a9 {! N7 v9 L0 p. x( V$ r$ f7 F: q7 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ C% J; y# j) A* {0 s
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);; X5 c5 l8 R Z5 B. Q6 E2 `1 j
}
7 }3 ?# h6 P; j( G
4 C( k$ g1 ]: S- ^+ S9 f |
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