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The timers support the following features:) l d9 h D3 Q5 {! T. b& T
• Configurable as single 64-bit timer or two 32-bit timers' W$ y' u3 n0 n0 }
• Period timeouts generate interrupts, DMA events or external pin events
7 _5 r: N+ N ^- A4 h• 8 32-bit compare registers) z% K# y4 G: ]* b' e$ J0 j4 t4 }( P
• Compare matches generate interrupt events: T& j/ k2 F# u1 C
• Capture capability& ~, t! B! \+ |6 m- J
• 64-bit Watchdog capability (Timer64P1 only): j1 A3 `* D* g: i( h1 `5 ?
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* T0_BOT: Timer 0, bottom : Used for clock_event" W( x ^# i. @3 S
* T0_TOP: Timer 0, top : Used for clocksource$ w! D5 E" h3 i/ g! j' E. R' Q
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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