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The timers support the following features:# ^6 N1 m1 c/ R+ P6 Z
• Configurable as single 64-bit timer or two 32-bit timers- Q/ c7 c/ r- l% Q) n. T/ S
• Period timeouts generate interrupts, DMA events or external pin events
7 m* G" s: R* q7 c8 I& `) H• 8 32-bit compare registers6 }; I. @1 }2 T( G0 m9 ^
• Compare matches generate interrupt events
1 y( S( z' Y5 n% ?/ j: k• Capture capability7 T5 ~7 @' M$ B% d. `/ E2 K
• 64-bit Watchdog capability (Timer64P1 only)* ` Y) v5 L& c! G
* i+ F5 x/ K c2 a7 A5 J1 H8 I/*
; ]+ \) w1 L l1 B* Y6 { * T0_BOT: Timer 0, bottom : Used for clock_event
2 Y7 F; ~% \' V3 D1 _ * T0_TOP: Timer 0, top : Used for clocksource0 Y1 F: }/ a6 T/ ]
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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