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The timers support the following features:
6 N9 X. E0 [; i2 W6 P, @• Configurable as single 64-bit timer or two 32-bit timers
3 ]8 v. B2 i3 t( `9 k. L$ Z1 p• Period timeouts generate interrupts, DMA events or external pin events9 ?5 H( p9 f0 D
• 8 32-bit compare registers( v7 k% p, z6 V) p2 Q" |$ J
• Compare matches generate interrupt events7 Q: r0 h3 M9 ~& L0 W
• Capture capability7 P7 }$ w$ E; l
• 64-bit Watchdog capability (Timer64P1 only)( ^: m# R. P! a; E# W* e* ?# q: T R
1 [* m, s- T. F: W( l6 [6 P% {8 Y
/*
5 S Q. j) N: \; k' R+ [& x * T0_BOT: Timer 0, bottom : Used for clock_event
: P: ~4 I0 V3 N: Y& i4 v * T0_TOP: Timer 0, top : Used for clocksource7 _8 T$ U- K& R9 P
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
$ V* R- S6 b, A- w; d */ |
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