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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# n- K: f h1 cinput mcasp_ahclkx,! t7 `; C$ _2 }1 V A
input mcasp_aclkx,
4 |4 k" ]. n3 A% k6 |4 Q7 J+ linput axr0,8 [/ o5 R& p8 ?1 W- Y* _
4 R- I* V5 n t- woutput mcasp_afsr,
4 P) p `) ]: n. R7 Uoutput mcasp_ahclkr,: f$ _5 q, i! B1 b2 j" }
output mcasp_aclkr,& P1 @! Y3 Y' f! I/ W
output axr1,
, m3 e5 P1 ~8 a8 n6 y1 b7 ^ assign mcasp_afsr = mcasp_afsx;
. Z* f3 }1 L3 s) z( P& Gassign mcasp_aclkr = mcasp_aclkx;
) Y1 H& b+ M1 z* s) x5 eassign mcasp_ahclkr = mcasp_ahclkx;
3 O8 F- G7 O; z1 x5 r( V, fassign axr1 = axr0;
% O c! w& W/ j0 n3 o; `9 c2 {& b x$ _. e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & u( @" [8 D4 G. u- ?& y
static void McASPI2SConfigure(void)
; I' B. J1 r/ \0 V{
( |: u) X$ ~) _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# l. X, P5 L9 j6 ] m( BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// T7 \, z. a) s- {2 h2 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 ?3 S! N& }+ b$ kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 X. f$ y' n! O) G8 zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% }$ t( d- m1 V3 l; v7 W* I3 y
MCASP_RX_MODE_DMA);
@ J H" P# f, vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, O9 W8 i( }- J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 s2 X) Q( T3 r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / q6 G/ Z' v. f6 g/ e) }1 F* j: Y. u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ e6 h7 f2 H. `9 u9 {( ^% N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 y8 G2 m+ y% d/ V( `5 \, y/ nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ X8 a8 L$ o" `) L, [, U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 N! a+ B+ F3 ~ f; j& Z* y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 h, _: [% i) Z0 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: w* l% @- U& \9 d0x00, 0xFF); /* configure the clock for transmitter */) \4 K% n) n& S% ]( e! g3 Q; X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ N- z. L1 `6 r, B2 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- B% {& A: z- E6 m% p6 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' I, T0 w' ?2 A; C, y# N+ g. e+ w2 O0x00, 0xFF);
5 u4 Y, m7 A1 }/ d# x
- o4 B t X: V# Z4 [/* Enable synchronization of RX and TX sections */ ! ~& [( q6 u7 A1 N# Y4 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 n* g3 M$ p2 Y: D/ `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 g- e* G4 {. g a! ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ V9 b: }+ g9 i** Set the serializers, Currently only one serializer is set as8 }5 @' b d1 G( m% P# R
** transmitter and one serializer as receiver.
- }6 q6 m0 ~& p' }*/
9 }. w4 q% K0 o# W- c, o! IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% w: m6 V# q. \. D, K0 i, I% z; aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ Q( b {/ y2 L4 s2 f( B0 m8 A** Configure the McASP pins & ~ g! B5 K- E, F1 u# F) a
** Input - Frame Sync, Clock and Serializer Rx
* A/ T5 S0 j, s/ U* K J! o$ j** Output - Serializer Tx is connected to the input of the codec
7 |1 K# C/ i1 J* K% v*/! S# s/ Q5 D/ t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% I% N$ b6 y1 ~. D- p: N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- F. E+ H$ J. zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# M5 B3 V1 W% h0 p4 i m6 w: R
| MCASP_PIN_ACLKX! h# E2 q. [ ~4 b
| MCASP_PIN_AHCLKX
5 F7 I! t, T( C, \) X9 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 \( u# Q3 q L2 }7 V- }( m9 h9 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 n. s* D9 Q& L/ }" W+ x9 r| MCASP_TX_CLKFAIL
. K. K2 g" X9 m- U. c- c| MCASP_TX_SYNCERROR
7 B2 p i1 `- a" o/ K: ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 P& o5 g6 N9 W9 t0 W6 g| MCASP_RX_CLKFAIL
m4 k* U' w, u9 s) M| MCASP_RX_SYNCERROR , L/ f; V7 T, S( W
| MCASP_RX_OVERRUN);$ R% z% E ~" t/ G
} static void I2SDataTxRxActivate(void). ]5 X6 Z9 m: [( u+ ?$ v; r, L
{
0 e! K) K' N. |! u5 R/ U/* Start the clocks */! m$ |& S. [, H& D0 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) i& ?& h5 Q3 o# R' `: kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 n3 O& K& ?) F' D0 h: V* p# S4 F: n& l+ P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# P/ x* E, g# G" ^
EDMA3_TRIG_MODE_EVENT);
+ P( W6 H5 g- u& U& e1 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 z7 p9 g7 _9 ]8 p0 y5 N/ s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 |) y! t {. ` e5 J R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ `/ d! n" T5 |& A5 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 [8 k! d6 ]: [! U+ e& kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 w6 J# f& _- UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 a5 w+ }. t7 I9 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( L' N# B% i0 z8 j
}
& Y0 a# [! X3 C1 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. \+ Y4 c6 r) Z M |