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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 }" ?1 Z; d. L+ v; Z! D, w( y9 M9 n
input mcasp_ahclkx,
) V4 i/ }9 I- u- e/ S. R$ q+ c$ binput mcasp_aclkx,2 W( O. t1 s" \: k
input axr0,, _4 R0 h; c6 G/ q; w
d0 ~" r4 A8 `* K$ `6 |6 m
output mcasp_afsr,
. ~* r8 |7 U4 H `output mcasp_ahclkr,2 [2 Y+ g Z: \7 W- |! C% c9 f
output mcasp_aclkr,0 ~" ]4 b! s1 G- X& `) W1 W
output axr1,: K4 Q. @5 k! {% @- t
assign mcasp_afsr = mcasp_afsx;
5 l3 n. ?4 H5 [. L( i6 Y# R* qassign mcasp_aclkr = mcasp_aclkx;
4 [& }0 d$ C0 qassign mcasp_ahclkr = mcasp_ahclkx;/ V( L) j) b# M
assign axr1 = axr0; ( O5 w# a/ d. Z
0 B8 f2 W) I" T' J$ k, M4 e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ S, k& C \, c: z/ bstatic void McASPI2SConfigure(void)
# a7 I% [3 u4 E" Z0 j{4 t0 _3 r. c0 N# u* a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 M o, L2 a z8 W1 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# @0 z+ x' ^2 S; R1 ^# W0 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" Y/ b) M0 I/ G( o9 `# D2 f! W7 I* Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 A f% Y8 k- r: n9 B) M$ A: d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, X& _3 C* k8 w" N' E& W
MCASP_RX_MODE_DMA);( D! W7 Y% E. D: Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 g- a( t+ b- S( G' s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 q4 f7 m6 Y+ O: r4 c& r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # A1 r9 C& y1 A/ J( B+ r" C1 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ |6 }" W/ ~9 D5 d* H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" M! e1 f% `6 i+ [, O# |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 u3 R# u+ o* M* ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% |+ t7 b8 q/ U# k. B8 D! dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ ]* t/ \+ q0 |" `' @ c+ n; tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: M; H4 R" I8 E. x4 U3 _! k0x00, 0xFF); /* configure the clock for transmitter */7 n* r4 N5 c; g# ]! ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, A) ~' e, m) X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : y$ O3 v% U" O' h p: ?1 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 g# B+ N# v }! L
0x00, 0xFF);: [5 b9 F$ P. F+ Z, O" A& f
' `. d% U; K& s
/* Enable synchronization of RX and TX sections */ 2 v# u( z3 f0 _5 `3 d' v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' f# L& W1 r# V7 u' c3 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 o9 g" j0 a& j3 Y7 ]+ W0 {! h% SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; H3 x3 G3 v! i. U3 B) j+ Q** Set the serializers, Currently only one serializer is set as: _9 g+ U; h# e
** transmitter and one serializer as receiver.
( |4 V. j7 n& R2 [. M6 d*/! z! N# q0 {, r$ b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; k% D! ]& P: @% `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 H. ]/ d7 }* C** Configure the McASP pins
/ _* ?9 A( g4 x$ k** Input - Frame Sync, Clock and Serializer Rx
' F. X1 X4 I7 S- C4 i! Z+ B** Output - Serializer Tx is connected to the input of the codec
# R. Y8 W, B# X- N# I( Q9 f, Z*/
# O8 {/ C' ~) q4 n' Y+ JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" w$ I4 | U. |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 S6 g5 R) l8 w& T) b4 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% t% j3 s! l% b# R! w9 n! J| MCASP_PIN_ACLKX ~5 K1 c: O! @! y
| MCASP_PIN_AHCLKX/ o0 z9 W0 Q9 ^1 C4 [/ ^* B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 O# t/ |1 n+ |3 D* R; S0 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ R8 P S7 c4 d. H0 u| MCASP_TX_CLKFAIL $ c V J. z+ Z/ t7 ?$ S: s
| MCASP_TX_SYNCERROR. q6 ^- s6 P2 Y. X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# }, t. { [, ~$ q+ \| MCASP_RX_CLKFAIL
0 Q, B" |$ v: f: P: M* k7 g| MCASP_RX_SYNCERROR
" s4 _$ ]% c% L0 |/ h+ U2 H9 b| MCASP_RX_OVERRUN);
' M! V. c; @4 ^# s} static void I2SDataTxRxActivate(void)
# @' F0 {. l6 [8 o) T+ r: d{
8 H0 H$ X% U, s" e, l# A# H5 {/* Start the clocks */
9 I) a/ d9 e$ V, C! mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ x1 k) O8 y& h3 K. ~ e6 xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ ?4 k2 B* P) S0 Z/ J9 D0 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" B. b$ \7 J. R# i- lEDMA3_TRIG_MODE_EVENT);
' M0 [3 u6 h0 Z6 T/ qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ V! c7 X7 h7 N# M& u1 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 y; b9 ]0 j# E8 A' G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- F) A( r! P5 q5 ^, x5 c+ T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( }8 P L. h; j8 c9 ~& y! swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, M/ T2 t) P `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, {3 w! z9 _6 L8 r: kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 `7 ]$ Y" `0 {1 P7 Y4 w; @5 Y
} 1 \( U a/ X& F. [8 P' S8 H' g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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