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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: k& {, ?; {* ^0 f4 W
input mcasp_ahclkx,$ j! A ^. Z8 I2 v5 Y
input mcasp_aclkx,
* V& _. y$ [) qinput axr0,
7 h/ v% E& D% ^9 x: i; q0 u& Z# v" `5 }& B- Q8 u' A x, w
output mcasp_afsr,
2 p7 ]' ?: S3 O4 ?. H0 @% poutput mcasp_ahclkr,0 E& w1 k3 R. @+ s! w0 \3 }1 L8 o
output mcasp_aclkr,0 u" `: A* q7 X8 q. u
output axr1,
, m- \' P2 M' P) t/ k8 b assign mcasp_afsr = mcasp_afsx;4 d; I% t6 r7 |
assign mcasp_aclkr = mcasp_aclkx;$ m8 Z0 l8 W4 Y5 i: D
assign mcasp_ahclkr = mcasp_ahclkx;
2 \, f2 V9 |% {assign axr1 = axr0;
- F! b5 b1 C3 U3 K
1 N% N2 O1 t0 a- A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# ^: o/ d4 Z2 K# X, Q9 Ystatic void McASPI2SConfigure(void)1 j0 F) l! L' b, j
{
1 N6 y$ L+ O3 w" u9 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 M% ^. W2 o# ~2 q9 L5 h( W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 S+ n' l# \ ?3 c7 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, h8 D5 }5 Q- V( E4 @. x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! t, f: t+ v: T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' |) g. k1 d$ _, I, J! n4 k$ q# f6 RMCASP_RX_MODE_DMA);
7 F7 W9 u' ?3 E1 y7 g, CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% n- b* N, ~ I0 p1 x% _' W1 l$ b5 Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 p4 ^: _8 L& J* P' _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 u6 R% s" ~$ D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ n2 _$ W! b! N" kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 u0 ^ U/ Q9 m! HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- Z" i; G. P4 @- `' v# F: FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# T2 H9 H3 a% i6 }! aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 A+ n0 `. D- `3 m( ?7 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ Y% T8 r% S3 m: {/ Z" B/ w
0x00, 0xFF); /* configure the clock for transmitter */3 ^' s- [! k. W6 h7 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ t& g9 |( i4 X5 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: D/ X6 E% A2 L# r5 j8 B7 f& rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: U" s% B9 M D- T3 e0x00, 0xFF);
, C0 {! J: z$ ?* K4 m% Y! T" X3 q& V9 D5 i0 Z
/* Enable synchronization of RX and TX sections */
! S, O; n8 }3 N3 J9 C$ I3 r( j8 [, YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 J; h6 K# s5 O4 O6 D- \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ c4 D0 k# u+ iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; t) x1 b' H* X9 B
** Set the serializers, Currently only one serializer is set as% W9 P* _! t( k4 j6 x
** transmitter and one serializer as receiver.
- k; M- F* v% L6 Z- l5 C! P*/) W J! o ~- Y. U& H7 Z$ c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 P% W% J+ y6 N* ^3 C9 Z$ q* BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* x3 U6 P9 V& K. z \
** Configure the McASP pins 7 s6 ]; ^7 j0 F- T/ J4 y$ l$ U% x
** Input - Frame Sync, Clock and Serializer Rx* i. o" e6 h2 Y: q/ [
** Output - Serializer Tx is connected to the input of the codec , D. K* y* ~5 p/ e! ]+ p
*/$ |: B* n ~7 R* k. i) K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" j/ ]6 L2 E! U. M% s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 A3 @: S+ v' M1 u: { L8 \, m+ BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; p7 I6 |% ? ?! \| MCASP_PIN_ACLKX
9 ~5 E+ y/ ]. u! r% H| MCASP_PIN_AHCLKX
4 N$ M9 `- [/ A1 M0 u, t# e. p( W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& Q( J5 {1 M( |9 }- u# u5 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ^8 r8 B( {. j" P' a$ J
| MCASP_TX_CLKFAIL 1 P( c# O: Z+ h% M, E" u
| MCASP_TX_SYNCERROR
7 J) B" k$ S$ X* Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 q" l1 R- ?: W& Y% c
| MCASP_RX_CLKFAIL# ~& H; X! W+ {. p. a
| MCASP_RX_SYNCERROR , j8 U3 [- ?) T5 U
| MCASP_RX_OVERRUN);: }1 F4 U9 F7 o4 J/ V
} static void I2SDataTxRxActivate(void); L& Q; `# J( u& r
{
, O. R+ I8 Q1 d/ d. [/* Start the clocks */
/ S: t" u- w+ ~( @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" `+ U/ Y ?/ b$ IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- D% ?0 J4 n3 v1 \% zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 d4 G- o2 Y4 E* f5 d* C$ W6 q0 {) EEDMA3_TRIG_MODE_EVENT);
; {" f2 a- ~& o- PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 I* T, j! S( l2 O0 T3 R1 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ P# Q" r* u' n! D: z+ `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( Q: Y+ C5 Y" l; y& _7 |" ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# e V" K! g. U2 G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ i3 k; k+ [3 e2 Y) JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ b, G. H- b$ N' {8 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; e5 B8 I, ~5 T; W3 A @}
$ ] N" r& {4 L0 J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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