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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 S) v$ j9 J! @7 v3 \& q" Rinput mcasp_ahclkx,6 f7 j2 h! a& H9 X
input mcasp_aclkx,) K n& ]4 k! l+ l) i8 _( [
input axr0,( N p' W6 c$ {$ B, m8 z
7 t4 o% Q5 v. \0 B/ Houtput mcasp_afsr,) t3 A& r# V4 ^* u
output mcasp_ahclkr,
$ C9 @4 u7 _+ [output mcasp_aclkr,
" c/ ~0 V1 }. ^, l1 Z0 Soutput axr1,
% t' s) d+ g& Q3 n0 _5 O5 j2 L: x assign mcasp_afsr = mcasp_afsx;* \* Q; V" [) L* F- g0 m$ }
assign mcasp_aclkr = mcasp_aclkx;6 p! p' M2 l# i9 S, ^: l
assign mcasp_ahclkr = mcasp_ahclkx;; V+ {7 y( S1 E
assign axr1 = axr0;
# b5 [; D( U; [8 j2 `2 n3 e/ p2 ^
$ s( h7 t% `: g$ l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" }0 f+ J5 P% w( L# @static void McASPI2SConfigure(void)8 ]! G* \# Y: w3 E- w6 q
{. q$ f4 k6 l# r0 P5 i4 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 }* T- B; u+ K0 u# S0 a1 X2 U) HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ M3 O/ S# Z& lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. V0 e( h8 e$ f% A2 n, mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ ]6 \# J$ n/ R4 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, {7 Q1 {* U! ?) O0 N; l @' C
MCASP_RX_MODE_DMA);; U* f% N# {4 t5 y9 f6 U7 N$ A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: }* N5 w( Q% y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 c5 A9 [# P. F4 {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ Y& K, _+ P' i+ M6 T3 q# T" Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" S- _- m/ Y* H* \' x3 O& U1 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* |/ [, [ u; NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( ^* @. u% q* E& E) B! LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 |* Z$ l, q2 H" h8 F7 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, p' Q( G1 h S2 @5 p r) ]7 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# ~/ t# D0 u, _+ o0x00, 0xFF); /* configure the clock for transmitter */4 D3 X L X7 j. m8 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ A5 `( s. z& {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 m I: H0 ^5 O* S& YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, Z* u+ M1 O+ N4 {6 ?# P1 P7 H
0x00, 0xFF);
3 N8 }- B2 T; A; K( a
/ x5 M! p+ r. ~+ {/* Enable synchronization of RX and TX sections */
# ^: z C# C5 I( vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) ?/ a& O5 Q, Q% C$ A* u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; u! F& [0 `# V7 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 `# q$ ]# v# n, L5 R
** Set the serializers, Currently only one serializer is set as/ P) B. S! S. [! p4 U
** transmitter and one serializer as receiver.- W/ y+ a8 T1 N- S* `
*/
$ t, j6 `. r% B- s- uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 k$ V, S% O/ ?' @0 N" @! W8 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, A& q0 U; Q6 i: w* q$ a
** Configure the McASP pins
, i+ `4 {$ L( a** Input - Frame Sync, Clock and Serializer Rx
! h. E1 D/ H; h1 G( x$ K- k# x. \$ K** Output - Serializer Tx is connected to the input of the codec
0 s+ l6 s9 z2 [4 h1 J& G+ _*/0 o7 F: p, Q3 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) V7 [0 I: [' V4 F+ d% ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. C# M6 w$ B: {9 l& LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ v0 ^) Q# \7 }9 V| MCASP_PIN_ACLKX! J+ t7 l) l4 ^
| MCASP_PIN_AHCLKX2 v2 h) n9 |# n. U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ s7 E& p/ i! V( _( m9 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 r6 p1 f3 d0 g" o0 Y| MCASP_TX_CLKFAIL
5 Y, }5 f7 d+ ~+ k. Y| MCASP_TX_SYNCERROR
. x( c; f q! o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ @0 s- j& r+ P4 ?8 g| MCASP_RX_CLKFAIL
( M3 N" P6 ~0 p/ w5 y! r| MCASP_RX_SYNCERROR 8 D: ^: z& k6 L
| MCASP_RX_OVERRUN);
( a$ U8 V, {" f, c+ n} static void I2SDataTxRxActivate(void)
9 C) e% b! T* k2 x4 B{
: R* ^& ?8 ~) o) D/* Start the clocks */) B! i( x7 x- A3 D' O# O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& D" l9 q/ e. a5 DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 z# P6 I" Z; `* F) }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, G7 M: O+ t B) e3 R; r0 r* fEDMA3_TRIG_MODE_EVENT);
/ m% A! j& l8 i5 |2 C# R: j, a, LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 _% ]" i8 n, d! [1 l( D' dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 q/ C1 f3 c `. g) P7 S" J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 v1 D7 ^/ x( l2 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! m9 J& H4 B& M4 L9 H% H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) r/ E d/ X4 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. v. O2 m, m$ e5 o; t/ {6 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, o) g9 |9 D" ]0 v# s7 n, |
}
' m# }) v8 w+ L0 L) T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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