|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 Z" y, Y5 s* f$ a U0 }
input mcasp_ahclkx,! I6 N7 ~) b, [( n+ {" y0 n
input mcasp_aclkx,# S; E+ G9 w+ m
input axr0,- O1 P$ o1 C% p b6 N
Y/ x/ }" \/ C1 O6 {7 b$ n, Ooutput mcasp_afsr,
) y9 J7 W0 g, ?' Zoutput mcasp_ahclkr,5 M' A% Y' t( ?0 \- Q
output mcasp_aclkr,) x7 V' D) a' D6 E& B5 x2 ]: y7 Q6 V
output axr1,9 }; Z+ F+ k; P3 J7 U
assign mcasp_afsr = mcasp_afsx;$ k8 ]. ]: y; `* I. \* w |8 J
assign mcasp_aclkr = mcasp_aclkx; r8 ?* g: f1 ?( ?" H
assign mcasp_ahclkr = mcasp_ahclkx;2 E: w) r' j( c
assign axr1 = axr0; 7 G2 F/ ~$ _8 S1 y; ?- z: Q9 S2 u
: q/ L c3 k2 x& Z* a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 u a) A- _ [" W3 J" ~% `
static void McASPI2SConfigure(void)
1 B+ z3 w( N$ C$ L* b: B: W{+ o, I+ Y8 P; p( i& p3 x+ Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 q' h! W. ^/ e! M4 R& CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 [/ }, m5 G- F9 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
v2 F% E; S* X4 f! ]! RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- G5 x. z- e! HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. _6 R% ~7 w& K5 g T! `, @MCASP_RX_MODE_DMA);# \6 B# @$ {; O: M, \# ?! E) y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 R: v' i" x. R4 c3 m1 U) K+ g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ h4 r+ I4 h, y. L. l# SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 @: u2 v$ Y/ U2 F* W. L6 }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" o* ]+ N2 J" UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - h: k" U2 m3 N& P' r* r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- ]$ M$ y8 v' t/ Q; V3 b2 w8 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ k% e2 {1 E( cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) h3 B# s7 H) f& o' H* J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 k% w6 g; g$ W" |: Y. r& y0x00, 0xFF); /* configure the clock for transmitter */
/ z N( \/ b2 `2 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# ], Y# C0 t' f/ pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; N5 A# [0 `& @8 u" uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 d# f* o" E! M5 O; a2 v4 K
0x00, 0xFF);
) l" G8 H4 `7 |! v _; D# F0 z2 ^+ ~3 {. @8 O
/* Enable synchronization of RX and TX sections */
0 H. f7 V& I! T9 l+ }. B1 L: ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* E( z4 f2 h/ @' \2 J/ I; n- k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! \) F1 y- E/ d. y) q; V9 A$ BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 M$ b" T' K9 a) e6 [2 b& d
** Set the serializers, Currently only one serializer is set as7 A% i6 v6 c4 h1 G$ V' @- g
** transmitter and one serializer as receiver.2 N8 z T3 [: X# q
*/8 j& P, @4 d* b! y8 z3 C9 u% ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) M0 `# s3 }# Z# MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 x6 x z" {" c6 w
** Configure the McASP pins , V3 R$ P9 p4 {% ~- m0 k
** Input - Frame Sync, Clock and Serializer Rx
( _6 y$ ?$ r7 G) y** Output - Serializer Tx is connected to the input of the codec
3 o( B# [! x( }0 } z*/
# @: B5 p& n7 I$ A. RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# P8 V8 z$ j* a# ?! bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' H( g6 t! |( _& e: PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ m, s. L5 Z9 b) }% K5 }! a
| MCASP_PIN_ACLKX
- Y, B1 \5 T: ]| MCASP_PIN_AHCLKX
w2 {( y1 n/ y0 v0 `! |1 p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ ?4 ?5 q% o6 f: bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " r' O' _& A; M' p' x
| MCASP_TX_CLKFAIL ( p F" r/ g4 W1 w! D* j
| MCASP_TX_SYNCERROR
, w2 p' I, F3 q# o, E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * X, z4 ?' [# Y1 p+ l& I
| MCASP_RX_CLKFAIL" j8 ?9 R1 B ]* R/ h
| MCASP_RX_SYNCERROR
; j5 [, l3 y# ?! D' M/ g| MCASP_RX_OVERRUN);
, J% F3 c0 O- s: j. X7 l5 i/ j} static void I2SDataTxRxActivate(void)- K& q2 ~& d4 Z, @0 E+ i% ~) ~
{; X" p) i2 Z/ G; U" i8 f) h1 e4 |- K) y
/* Start the clocks */
0 W- O8 I7 ?& x% IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- s* v! S* c9 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, t& v3 c+ |5 _( l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 M# s8 T+ S4 V
EDMA3_TRIG_MODE_EVENT);. j9 L/ E- J3 o( u- c' r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 c: [, ?: ?8 y) \) H& z1 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 V! z4 l- K3 G, ?+ e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 {( `2 }2 \5 A# Q- Q! F9 _/ x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) t# ^5 t: b1 i: H: |& }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% `& I+ b! C: ~1 ^% oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; \4 h! u$ J* U# a1 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 V" ]4 u/ d: R) o; }2 k7 q% ]} ( R' L2 U ?& c. l9 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 D7 F8 M) @9 u) N! R g |