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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 Q/ E( ?! [) z4 tinput mcasp_ahclkx,
# D( d9 \; Z. O( d$ Xinput mcasp_aclkx,0 y( j# a5 [' Y( ?' N' C
input axr0,: i5 V' D+ l9 L
) S C9 o( B+ J; ~6 g( eoutput mcasp_afsr,- }- Q3 V0 |7 b2 I* b1 }: C
output mcasp_ahclkr,$ b( v9 U2 r& o; [2 Z) P
output mcasp_aclkr,' O2 }& D. n$ J1 I3 S8 B
output axr1,$ F. m+ Q: ~/ ?7 h- Q; M
assign mcasp_afsr = mcasp_afsx;
/ P' L, ~! \3 z1 k- `assign mcasp_aclkr = mcasp_aclkx; q5 @0 o3 E# s# x
assign mcasp_ahclkr = mcasp_ahclkx;* h& l7 H9 B7 c7 b4 g" c
assign axr1 = axr0;
, a; P* i7 l* C5 p
5 ?9 z& f, }! s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 J& Q, i1 s4 t
static void McASPI2SConfigure(void)
9 @) h m3 V& e8 b0 {{; d9 R: L z. D. S( d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& {9 }$ c) c4 \7 dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 C" u$ X7 e+ j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; _ | }7 {& H% f8 y3 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 T" G8 U6 e; V( `, BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 o% k1 m7 ^( ^! b! sMCASP_RX_MODE_DMA);4 ~* T$ p1 B' r5 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- a# P) J7 T4 u" t- J8 ?0 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// _4 z s" t3 r L1 D P9 R0 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 c. h( c* a) ^+ [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, }& H3 |) b# V u" U' S4 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' N' y3 b' D- r. F3 Y) J0 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' e! V/ ~& B) g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ y! Q# a$ ^" UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 k# Y) U/ W9 ?* w: H* L; _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. X! W5 ]! @" q% r& x) Z0x00, 0xFF); /* configure the clock for transmitter */, [6 K5 e) z" L/ E1 O/ r' T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. w3 { i. q4 k* X& |6 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ F% B9 G, h! H$ Z* ]& j3 s. }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 a, e- J( p8 r" b
0x00, 0xFF);
# `2 e( P3 |. ^/ Y l6 N5 S$ N6 ?, @( u" o( e8 ^
/* Enable synchronization of RX and TX sections */
2 q( L' x2 a8 n* v0 j6 O8 i: E- _5 y( zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: h0 w9 w9 B; S/ `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! d L4 N5 e$ R! C; ?0 k( n! i' ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 ^: T+ V! t/ q% d) g** Set the serializers, Currently only one serializer is set as$ v" d6 y) z4 ^; g
** transmitter and one serializer as receiver.
9 \+ u+ U$ V" X$ p8 K/ f*/5 L: R6 s( U, }$ G2 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 V/ C2 z& g6 R8 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' g; N6 d7 P! l** Configure the McASP pins / S# f2 x! a& Y' s7 H
** Input - Frame Sync, Clock and Serializer Rx& [ ^! W/ A' p) c4 [
** Output - Serializer Tx is connected to the input of the codec
8 B" X; A4 o+ V' k0 S+ p$ y9 z* N*/
( r7 W' O+ c5 kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ m2 a' u* p1 ?) L+ w2 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ ]3 D: y/ v( L) G3 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 M4 U. v7 `# n k2 f5 N5 e
| MCASP_PIN_ACLKX! A' Z' @/ m) r7 y- s- ~
| MCASP_PIN_AHCLKX
- D( L/ s: w) r8 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 [4 z) @: [! y5 e- mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & h `+ I4 ?* G1 Q1 a4 H- I
| MCASP_TX_CLKFAIL 4 K/ q$ f8 X" v9 d5 A
| MCASP_TX_SYNCERROR
, u% I1 |! i) L8 y& M/ c" G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 ~: F* L, Z) b| MCASP_RX_CLKFAIL! w) I& h, w) {* \
| MCASP_RX_SYNCERROR
9 C, j0 U7 ^8 H Q: x| MCASP_RX_OVERRUN);6 E1 p1 _ v# O' ^: L* o5 m
} static void I2SDataTxRxActivate(void)
% j6 {& m% C5 h) L{2 X/ p, r; h- A& J# Q" k
/* Start the clocks */: g' j5 d8 f: o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 I2 j& f! x% S$ _$ S9 m( S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( n8 D6 ` J% L# R& w, |& W# F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: \! `% t% `; i5 V. L& B7 K4 |/ t" {EDMA3_TRIG_MODE_EVENT);
$ O A+ X. ~, b* ?; N# K9 B9 d HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ a3 M, l: t, p2 W" W. ~5 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 \8 A( }) d7 q6 O* e1 u& ]- J9 o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 a, N- N& M2 f3 D8 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 _# t: o4 @: W! _+ k; Z, Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 ^7 H5 s- @# OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 v5 N( }( L+ w, @( g2 l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' G" r6 t J- h$ t}
4 }, t! Q: N0 ^0 n( Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; h5 C9 H, o, Q8 O' V* W' M
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