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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# X2 h, ^' R/ i) d6 pinput mcasp_ahclkx,+ D) t. L; h: ~( h. l
input mcasp_aclkx,
! Y9 b6 O5 _" N' \6 q: ^+ b `input axr0,
" B% U8 q9 I8 h0 g% @& n
8 a! h& S9 Q e* m. ]9 Y" Uoutput mcasp_afsr,$ b. ^& N. b) l2 P& S9 V
output mcasp_ahclkr,
" B- h4 F; j/ L& T* k& houtput mcasp_aclkr,2 W) P! i1 n7 d
output axr1,
, R0 P0 v4 Y; ^$ e: T0 [9 _ assign mcasp_afsr = mcasp_afsx;
2 {8 t2 L0 n, `( f7 F6 h' Rassign mcasp_aclkr = mcasp_aclkx;
. k6 m N; ~, P2 U; z# ]assign mcasp_ahclkr = mcasp_ahclkx;
( \: \) ? L' B/ Hassign axr1 = axr0; P: S: [' [4 }8 ` W+ C) b
: H" p ?$ {7 J- |+ O1 `- h7 {5 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 `, Z8 [& a' x5 R
static void McASPI2SConfigure(void)3 k: F/ i+ X/ K+ C2 G# O
{
' X# [/ H% i, Q9 k, _& O& PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" r* w) M. E" m# k$ P. _- z* ?6 M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' [( ?. y4 D6 y2 A6 [( LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 L2 s, A9 b- q! j9 O3 y, `2 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* j% y) |8 k0 t0 b8 h5 H* [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 F6 |5 I( q6 rMCASP_RX_MODE_DMA);
& ?+ C, [0 N* }/ x# D YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& t) Q0 d1 K! ^3 Z% b5 m# m/ p- c _, X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; z$ q: K9 [5 {' |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 O+ C7 }$ r1 ^2 S$ ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. S: e- f7 a( {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* U' `) e9 O$ BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; ~: \- F& V$ r+ T9 q" h5 L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( r+ ? h+ P% X+ I$ T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) o K" p: E+ r; V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ L' l+ p" _4 E% u& `: ?: ?1 b0x00, 0xFF); /* configure the clock for transmitter */
# f& W( d! N) E0 |' eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# O: F! p5 a: I; SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& v( Z2 N; ^' Z+ _# Z4 K8 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! T1 g- k6 B ^* m, K0x00, 0xFF);
7 x+ V6 w+ ~. F
3 M% }5 `, Y; p6 }0 v/* Enable synchronization of RX and TX sections */
5 R2 P1 N. o7 c b* Q. I3 z3 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# f1 j5 l, q% Z0 o3 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 i' |# @, O8 m/ R/ n% f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ S L+ U4 F+ h# I
** Set the serializers, Currently only one serializer is set as
. H# Y& d, q3 E) t6 Q** transmitter and one serializer as receiver.0 s4 V' C% Z" ?- [! A6 J9 g
*/1 M3 Y; N. G$ z4 _' X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 ^8 o2 ^% `4 u& j/ c& \. iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& g# k7 M: K& P8 H m# e/ y7 K
** Configure the McASP pins
' B. x% E! n7 v' ?1 `** Input - Frame Sync, Clock and Serializer Rx
7 l/ T4 a% @; d% e) X5 Y' A4 O! C; g** Output - Serializer Tx is connected to the input of the codec ' D1 j: z8 \& Y6 D! ~- Z
*/& h3 I7 z C V3 x9 S- Y0 S9 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 ~) u: I& k0 [" h1 Q: C, m, @7 FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ w2 S# }$ G/ z6 a& |. jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* l% @+ _+ j& s6 e& F3 J| MCASP_PIN_ACLKX
1 j5 o& w# v m) c G X, o| MCASP_PIN_AHCLKX
+ S. i- B$ z" S& |( N9 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) Y# l( H* o3 i7 o8 q0 `1 }4 f$ D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ @& B! k0 S0 i, v! X U
| MCASP_TX_CLKFAIL
D# T l( s) x* j) I/ P| MCASP_TX_SYNCERROR
: i8 l5 h" z. R+ y' A0 W( D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 @+ T, |: l3 B
| MCASP_RX_CLKFAIL
' L5 `* r! ]9 j9 M) x| MCASP_RX_SYNCERROR : X" ?* I: M# \0 S- T* J
| MCASP_RX_OVERRUN);
) [( u2 @1 I5 g) D4 F8 X} static void I2SDataTxRxActivate(void)6 B# C$ ?: w* }* L
{) H% k! Z1 F8 n2 b* P
/* Start the clocks */2 P3 R! _( S# p0 c, L5 D* P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
e0 u9 f5 W' j. M2 u7 ] lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. m6 P, }) Y3 L9 y9 E7 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, l. B) ]) \; D- s" ~. h* Y
EDMA3_TRIG_MODE_EVENT);
/ P k6 A- f _6 ^' qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 @% H1 y2 F+ {% J, _7 W2 {% a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, m* M; n- k* R% uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- I% Y' m9 }5 b2 g6 }" S1 C( a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. @+ R+ S7 h$ F2 d2 p4 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! ~' A9 D8 k4 I9 I* z2 T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 d. M5 k. Q& b9 M7 H, C/ T5 L. QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; _0 s6 O6 I6 _5 [/ Y
} ( q" i& V+ v2 Y+ s: x5 @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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