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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& d6 J6 X( X: @5 ?* cinput mcasp_ahclkx,
^" e6 x4 A/ A! Q ginput mcasp_aclkx,: r8 f h: U4 j7 n! C P
input axr0,- Z% O2 l- g1 z7 Q/ u1 B
* R C( h0 h) N v
output mcasp_afsr,
7 T( D1 \' f; n' i' U: g7 Zoutput mcasp_ahclkr,2 t& ]$ J% B6 H
output mcasp_aclkr,# D6 M) s8 S1 `2 J: B0 w
output axr1,$ i! c1 A' t: y+ K- K( J# c; f' |* w: Z
assign mcasp_afsr = mcasp_afsx;0 m" ^) ]7 [/ n
assign mcasp_aclkr = mcasp_aclkx;8 ~* Z4 S; z2 j* H
assign mcasp_ahclkr = mcasp_ahclkx;
# n# _0 t" W+ d/ ^assign axr1 = axr0; 8 I ]4 \# [( k9 f) n
6 V0 H& W3 L; m, l1 [* ^! D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ c) c( s+ Y! n; t4 i/ A$ p: Ystatic void McASPI2SConfigure(void)
4 H/ U+ {/ |# V8 I1 n{
# b8 g& z) j% \1 O5 O6 L+ a" G0 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 I4 Z6 Q" f2 Q( Q- _+ O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- ?" U, X' }0 @4 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: O& e: \4 ^6 E" v( o3 a. uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 ~ F9 T% M1 {+ U5 D. g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ o3 }* k! T: D5 g0 Z8 g* jMCASP_RX_MODE_DMA);+ a) u& }1 u9 I$ p, O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. M' q: k; c- v! K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. Q2 H1 }% Z( |: P, g' x" DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( A* T$ |) B6 {* ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: W i; Z9 d s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 y* c' e O ?. F: O7 f$ Z0 [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ j7 _/ n4 ~- a& g0 fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# D# b X8 b- s) d6 m) S& \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, k$ D3 f! t' p# [4 M- w% WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ l+ l$ [1 g2 Y- C) Q9 i, N
0x00, 0xFF); /* configure the clock for transmitter */
2 I" V# h7 m" } ?% ~% u, @4 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; G0 z! s2 A3 l: i7 x) m, Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , }+ I+ B' A4 |4 W. V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! w, g1 h; Q- a
0x00, 0xFF);5 _! z1 F& a; }5 F) I* o4 f
/ O. O& E1 K% c" N0 k' A9 O
/* Enable synchronization of RX and TX sections */ , T6 R" w" w: \8 l7 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* W8 p1 v8 ^2 W5 N KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# [, h# S( c9 n5 c) DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' L* i: o& o6 G- ?5 f
** Set the serializers, Currently only one serializer is set as
- D6 H. t6 u; ~) }# R8 g** transmitter and one serializer as receiver.
% P+ x" r+ P& g) M8 ?& {) o*/7 R) _! [3 s; N3 p- y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ \9 d2 T# |! I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 i1 w( O$ ?' D0 s \
** Configure the McASP pins 6 s/ o& j9 k0 o: h4 i
** Input - Frame Sync, Clock and Serializer Rx3 s8 \5 C& `7 w5 I" q+ D. [7 Y' T E
** Output - Serializer Tx is connected to the input of the codec
z4 O- d9 I1 T5 x# m6 N1 B. |/ R% C+ J*/8 G) y" `( X/ _" L# z9 {0 b# @) |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- [; z( v2 j( g4 N2 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# C% W$ s" C/ F- r) \# Q2 Q1 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* |2 ~# b$ d/ M5 u| MCASP_PIN_ACLKX
6 \. t' B0 b. V; g| MCASP_PIN_AHCLKX
5 {+ B* y1 ~5 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) u% R/ @8 _/ M2 U# c. Z3 |1 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ a) H: d/ v& ~) f6 X| MCASP_TX_CLKFAIL
$ C; @' U# `( A3 X* Q! X) e5 M& A, a| MCASP_TX_SYNCERROR
- D; q( Q1 P: j0 _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " Y) ]- M; R+ K+ r3 F4 u
| MCASP_RX_CLKFAIL
1 b/ E5 t& X! V6 h1 @% S) B9 ~, Z| MCASP_RX_SYNCERROR
5 g' q( |/ o5 W- A| MCASP_RX_OVERRUN);
$ ?! w2 y8 z; ]} static void I2SDataTxRxActivate(void)3 b0 _3 O# c7 d1 Z1 N
{0 L1 E( G* n' j2 q& e0 H
/* Start the clocks */
; A4 {! \7 G9 P. q+ t! X" YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 C |+ Q! I: C( i! C; E2 r eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 Z' V6 N; d8 `1 X, z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ `% N3 Q B9 j# oEDMA3_TRIG_MODE_EVENT);
/ n* Y' f! R/ p0 Z& s+ g3 t" yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 s4 }( |3 y* t+ W% W( s% q( M- D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! I w% ~) B, l% E4 P8 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 I8 e2 T8 U( Q" z8 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 I" f) E3 u% o! u( Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# B0 _; M' L1 B1 b) j% TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 b1 s' e0 a, F0 G# S* Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 D$ Q c! w0 K$ ?2 X
}
! o. W' w$ T% E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * o& C8 k9 w. l3 o* z: H5 H
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