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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' A- n; _0 B, G' D, [input mcasp_ahclkx,
, {/ l6 `( K& \: d/ }input mcasp_aclkx,
3 ~) ]/ Q+ z4 Q5 O) P' Tinput axr0,
+ K/ G/ f; t; Q$ I$ n( }1 n
# m# k) k, p! Y: S- E+ B1 p- v$ Doutput mcasp_afsr,2 g/ g$ m* g g1 A) h! a( c( R
output mcasp_ahclkr,5 ~1 x. I$ i- c! i% U8 j6 `' C9 c
output mcasp_aclkr,
3 R9 }: t+ x- [4 {0 Toutput axr1,4 o% q/ C9 x, {. ~; H' q6 T
assign mcasp_afsr = mcasp_afsx;- @0 e- |+ q! r" ?
assign mcasp_aclkr = mcasp_aclkx;+ c+ S& E. l8 [# `
assign mcasp_ahclkr = mcasp_ahclkx;8 k. v, Z! R8 T
assign axr1 = axr0;
( y4 q( c0 F, a. S( g, o% Z; v9 `# e. i% P) h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 {% M0 t- ]2 U$ L- y( Y3 n! Qstatic void McASPI2SConfigure(void)2 q1 a0 Q2 L# t+ j! ?! _" w2 d
{6 ]: v# N. M7 y$ b! _7 Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS); Q9 i! A6 L8 c; Z3 P3 n6 @' p) x K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ {; i! K6 B6 B- D3 e2 z6 w% n2 sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 n c9 c0 e) ]' O: H6 o& DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ K- P$ b& w' S" B' Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& N: R! ?4 d. \
MCASP_RX_MODE_DMA);
1 {6 [0 M3 I" z. H6 y3 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: y8 [; E6 R, Z7 _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- I6 F& X) G* d& V6 c& f$ v# AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ [3 J( A, K) z0 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 _) o, f7 I* N( OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 }7 g$ w- d n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 ~2 m5 c2 [% ^3 Q( S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) C5 G9 g$ Q1 |, A$ v( }1 M# u, WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 ]7 P0 w9 J' i% y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 @: z1 k! L' r1 c% y9 _
0x00, 0xFF); /* configure the clock for transmitter */
3 a3 ?/ T9 ^# G/ f9 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 w$ A v6 J. J3 I' @1 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 k% J% c& Y. x7 H4 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! A9 e9 h9 Q) Q! D. y
0x00, 0xFF);7 h- L. l6 S' H; x/ z, P$ a0 c
* M5 L" \, P2 \0 ]& X/* Enable synchronization of RX and TX sections */
% g( G6 Z; a3 Q# ?! F* nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 _7 m6 m# `: {8 O* z# XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 U8 v" R, D5 J# t8 {2 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 P# N5 \" r( k$ f) R** Set the serializers, Currently only one serializer is set as: V8 n W5 N. A7 }7 K4 L
** transmitter and one serializer as receiver.
b# d- [7 J# b0 a5 X4 @9 m8 B*/
& m+ v% R3 f2 c' w+ _8 _- E1 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* ]# m4 b4 ~* b+ C/ nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' J" u: F9 {* a1 S$ p' Y
** Configure the McASP pins
* H$ D- z& G+ P** Input - Frame Sync, Clock and Serializer Rx% m/ D+ c, h. f" Y# S
** Output - Serializer Tx is connected to the input of the codec 0 k) A" v6 ~1 M
*/- j6 E. ?, U$ G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: G1 J' ~2 x& u r3 X2 n( \) y ~+ K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
s$ y, g: t( FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. `, |2 M! w$ `
| MCASP_PIN_ACLKX
0 F9 l# f' x3 G7 ?" Y2 c, {| MCASP_PIN_AHCLKX3 E- Q6 {" k) k" o" s% _, x( o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 I7 `8 ~# c7 s) N+ c' I" X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ z2 @. B6 p( {6 I| MCASP_TX_CLKFAIL : S# S$ x" Q8 P- X$ o$ c
| MCASP_TX_SYNCERROR
! [ {* _% C% h* D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 B' f( W& e5 J
| MCASP_RX_CLKFAIL
# P4 {! U$ n: n8 P6 d6 T| MCASP_RX_SYNCERROR
; f& J0 Y; U; S8 G| MCASP_RX_OVERRUN);
% M4 A8 R- V, v a) I+ E} static void I2SDataTxRxActivate(void)7 N5 G: X* Y" I3 l
{/ Z+ M$ L" G. I @! n$ y
/* Start the clocks *// X$ z, T p" R& o, j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: @3 R; i6 B- G) l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 z( O# h9 q1 o, F g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 r7 p- ^* P. X1 ~ L) \, j% M0 k
EDMA3_TRIG_MODE_EVENT);
. |, v. @' F0 P9 ]6 r/ y' oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! p, |5 [8 w' i6 V& z' W( w% D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// P/ n% G( V, n, O! a1 C* L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# d. h% v, q1 {6 Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 R9 T; U: S% h" hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. S6 o6 E0 Q( t& W; ~9 [9 ^0 s# b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) Z, u R1 x# Y: f3 T( V9 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. \& b0 a. z" A( x& U} ) Q9 r* K, d$ D' Z& U- B Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , p' \- I1 T: {0 d
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