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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," L# c+ E! @$ g! I9 W' T3 P s
input mcasp_ahclkx,/ R' S, i, a0 T3 l" q
input mcasp_aclkx,- d. \9 p4 f7 N. D) x3 y* k
input axr0,
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output mcasp_afsr,2 b+ u* Q5 ]- [3 V! O; z
output mcasp_ahclkr,# @4 d4 d7 V0 x1 H6 i, {
output mcasp_aclkr,
1 ~ N5 W, g l, ^$ ?/ \output axr1,6 k' f9 l+ U( ^0 H3 b `2 c
assign mcasp_afsr = mcasp_afsx;
3 x) {' m; Z$ cassign mcasp_aclkr = mcasp_aclkx;
3 x3 L% [: c+ T, f3 w: p' Oassign mcasp_ahclkr = mcasp_ahclkx;& T+ B8 t: F6 V" I# Y& P0 R; ?5 U
assign axr1 = axr0; 5 u' q/ j4 B. B# t! g. p8 E! ]8 [
: c" r. s( N( x7 O; l: u5 E: r$ B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: z! ]5 k' W+ V6 z+ W7 H9 astatic void McASPI2SConfigure(void); b7 c% P+ Z9 t9 y/ l/ I8 ~
{
6 E E/ }. g5 C7 `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 P0 q* q+ h6 M. UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! d2 v% i# c9 G# L# \* Y( J: b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; O' I# c4 n; ~7 p# A! A3 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% L# ^$ d9 @# }( K @, m2 N: OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ^2 m: y3 `' p0 f) ZMCASP_RX_MODE_DMA);
, a4 Z; _7 U3 G+ @: x1 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ m3 D: Q0 Z9 g1 C$ Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ r' P0 @, l/ _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) ~0 h2 P; `! Y9 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* |6 m- P- R+ K; jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 T: s q# p+ d' }, q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& `6 c/ |( K6 l2 ~8 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ P' [6 u' t* B5 ^4 T/ p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . E: J: {+ c. q, M' z6 r: p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," g3 h2 y+ `8 R% C- f+ q2 [: }) `
0x00, 0xFF); /* configure the clock for transmitter *// M1 p2 x: U5 N( K1 S* F d! l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 g0 }( Y" g2 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 ]& C" J3 m$ Y7 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 A/ z# w! X" d0 D0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 1 i1 z* y: n! O% \) d) S; |3 J. Q8 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: P0 O; _, p# q1 H( G" J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" C1 G" ~. H# e1 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 F O" W1 F9 e( [** Set the serializers, Currently only one serializer is set as1 x& H# a! i& l" D- v- U
** transmitter and one serializer as receiver.
, i6 z( S2 K; M5 g! w5 O*/
6 B8 j* z8 s j1 Y. S- i9 w, mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ _7 N7 i$ K* c5 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# A' j9 V1 Q4 L9 G% X7 }/ b: x" i" d4 G** Configure the McASP pins
9 C: t0 j5 R2 z" N5 Z7 O5 K+ Z% Z** Input - Frame Sync, Clock and Serializer Rx6 y+ R8 l5 ^: N! v4 X1 g) D) M+ `' U
** Output - Serializer Tx is connected to the input of the codec
+ x2 Q# Y- x! o' v9 M c*/& I4 o- Y* V8 W$ O6 p+ X6 M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" D* m$ T3 @' ~' Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* t2 d3 m# @) ^& X3 F3 y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 G0 X) a2 N' i2 D9 z9 \! H| MCASP_PIN_ACLKX
" h0 s+ u0 g" Q, @9 }8 l| MCASP_PIN_AHCLKX( W4 s% e- G3 G3 J5 S1 K2 h( p: m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' @! `0 M }$ PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + \8 W9 T& u8 H9 u. i: u6 E2 ?
| MCASP_TX_CLKFAIL - B$ H2 _* K- i6 a
| MCASP_TX_SYNCERROR
+ P* w7 D' D$ V- l8 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - }# e+ i0 K( F: Z* l7 z
| MCASP_RX_CLKFAIL) _ u/ ?: d5 X7 X
| MCASP_RX_SYNCERROR ! b0 j0 _% G. Y3 B) [
| MCASP_RX_OVERRUN);( n5 v+ y+ J! g5 T' R h9 }
} static void I2SDataTxRxActivate(void)
$ Y/ Y! @8 D( @* x' l4 X# z' p$ s{+ x n9 t( ~# _7 U, k
/* Start the clocks */0 u! u/ D$ w5 R2 n. m2 t: f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. c8 _. v* X* _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' m, N7 Q) |1 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 t3 O- V, Z9 m6 r/ v
EDMA3_TRIG_MODE_EVENT);
4 m$ U6 [$ G! ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ d6 g4 T3 v0 b$ `# a! y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. X" z' D( W. @3 a9 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 w5 U2 R7 k. e6 ~* {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 D4 A7 v; {) H7 A5 @; \$ b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 H9 ^) H' F9 ^( C3 j, I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. @3 j9 T% p& v [- w6 v# C0 AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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