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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 y; W/ y! k: e9 }input mcasp_ahclkx,
- Q: y; M( [. yinput mcasp_aclkx,+ X( H N1 X3 L
input axr0,+ e& X* |9 Z- Y# _ G
& ?! T4 k2 w3 f' f) C' F8 Y
output mcasp_afsr,
/ y! c( f T2 h% ]output mcasp_ahclkr,
3 s0 k) r! h% w9 L/ f7 g" Poutput mcasp_aclkr,' h1 C% F% q# [# [9 j* p- P
output axr1,: J O$ J" c7 o" {
assign mcasp_afsr = mcasp_afsx;
' G. `$ c! ^2 f5 _& F- `4 Eassign mcasp_aclkr = mcasp_aclkx;- a( L6 W7 Y: R! e W
assign mcasp_ahclkr = mcasp_ahclkx;, O& W, M$ D% q
assign axr1 = axr0; : n$ X. V' p( L0 j# a/ T' Y/ d
5 H" a+ e& Y# ]7 C+ S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 a! A. K3 ^( i0 Z% s
static void McASPI2SConfigure(void)
7 \2 C6 Q$ ?0 a# O{
$ D1 ?: k2 A: d4 [: r) }. ?" \McASPRxReset(SOC_MCASP_0_CTRL_REGS);& ?' N; v% j7 R3 W: p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# a0 j% U7 T& H: U2 lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ f) j) H: M4 E, L0 T, fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' [- D) W7 W' h9 l; M$ ]" O$ o) g9 O4 x2 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# X* Q: ?+ w( S9 M: H9 \5 S- _$ z) zMCASP_RX_MODE_DMA);# i; ?3 I4 m5 O( J# z4 C/ |( s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 {% l% L# [, O v$ `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: I/ g! f j! r) Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . G3 y" L) s% m% V+ P- G2 W. y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ i# o+ i4 S: d3 _3 D% r% F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 A/ Z6 W2 G1 x& @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) Z; J# l( b4 F. BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 O- w5 |1 Y, k. iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 i( U6 E4 z; Q3 V( EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, [' @" i3 |% e$ ~- i! Z
0x00, 0xFF); /* configure the clock for transmitter *// N* A" N1 d3 V L. @% W6 @& @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 Z$ p% Q$ w5 [9 k% B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * [% j! a% s" C% P1 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# K! V. O# X$ b4 F3 h6 m) D0x00, 0xFF);/ i9 P- `4 D, Q. c, M: L
, O* {) t B* p5 ~/ }$ N2 w
/* Enable synchronization of RX and TX sections */
& [ g1 ]/ R$ u% u$ QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 C* l( ]$ V# _% AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) V8 D/ }: ?: T6 Q1 S0 ?, bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
Q6 X! }: d( E# R* d: N8 m** Set the serializers, Currently only one serializer is set as
$ Y) E. T7 C: \* f9 F L7 x** transmitter and one serializer as receiver.2 l0 T! H% R" F
*/
6 c0 w# t: s) FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; G1 A" d/ ?- y7 R' MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% j8 |. J" m/ U0 h! g, z7 F7 D) p
** Configure the McASP pins
( N7 g- f& {, d/ L$ `** Input - Frame Sync, Clock and Serializer Rx
' ]& W9 F3 H0 @- p: ~: q** Output - Serializer Tx is connected to the input of the codec
0 _: X) ^8 r, f7 h' t*/
; C V- V; b& [2 y7 ~& P xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# H7 I2 z) P) W& X# M$ {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 C' w7 z' y: O$ w. q- d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# l {( l' h% \! c
| MCASP_PIN_ACLKX
& G9 H% H- k1 H0 L| MCASP_PIN_AHCLKX
" c9 e- W4 z6 D* ]$ [) n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 Z8 ^) u$ z b6 I% @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
`7 L+ C e0 @, S| MCASP_TX_CLKFAIL
6 i1 {! t7 ?, o& W& q' h+ Y5 W| MCASP_TX_SYNCERROR
4 E& c2 J% K2 n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 [" W" Y. a, g3 c
| MCASP_RX_CLKFAIL8 V* E l! y! T/ N
| MCASP_RX_SYNCERROR
1 T2 y' p9 b4 g% u/ f, X' M| MCASP_RX_OVERRUN);5 U" U6 y1 o0 I5 l
} static void I2SDataTxRxActivate(void)
; G9 D$ [/ K* B& A{
8 O( h3 d5 d6 U; g3 R/* Start the clocks */* {( ^& O4 }5 N% ]3 x" Q6 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 b8 ^0 M: X0 }4 FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// O) M" U" n' M% F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# L- n) u" O/ _5 A" x) P
EDMA3_TRIG_MODE_EVENT);
9 N& v1 O8 H. YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ G- t) A# o' r) A( {; b9 n+ bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 j6 I7 }6 [; C' Y k# E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 A0 J/ e2 s' O3 b5 O& qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( a( _+ C& z6 _( G2 i, D/ @2 c( Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) S9 Z" s4 C& P4 T/ w2 a9 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 y6 X8 K. I3 y+ y6 e6 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ H- l, l$ t# A$ q
}
9 G: O4 ^- [# N( a& I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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