|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," H+ G# E8 n5 y+ ~- t3 k, s- V3 E
input mcasp_ahclkx,
7 K' y' ^% P; Einput mcasp_aclkx,
4 E3 K, u ^. M) t2 V" S7 }+ Vinput axr0,
. B1 g3 a6 q) Q1 D7 g- Y( ^; \( l! k5 ^
output mcasp_afsr,) \6 \( ]1 ?# `7 B. J
output mcasp_ahclkr,3 n+ f L) X; J1 Z7 F9 [# z! G7 m( M
output mcasp_aclkr,2 m" L: I" u2 P3 ~( z1 R
output axr1,4 Y( t( b* L! J: i4 `9 J2 u
assign mcasp_afsr = mcasp_afsx;
* a( n/ I! k/ ?) L; l+ X' U% W8 aassign mcasp_aclkr = mcasp_aclkx;
: N; @+ i+ I8 U7 g0 |$ C+ |assign mcasp_ahclkr = mcasp_ahclkx;
7 D B |8 m4 E( iassign axr1 = axr0; / V( U- f* \. S
- _1 V5 o2 b( F5 R. ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- T. x- x! Q: M; tstatic void McASPI2SConfigure(void)1 K. c6 S+ f5 K0 z1 W* e
{
4 ?2 A, s* u1 M; ~* N, [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
b. H) y) F- v# x9 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 B( f/ c# s [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ ^0 e- X* r0 F4 D2 p8 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 \; Y4 [9 Y: s! V, Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 I/ Y6 g' _+ |" V2 hMCASP_RX_MODE_DMA);, ^; A, n; k5 a) c& ]1 {% m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 O8 H# Y. f# b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' H3 z$ V* P* v2 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 I# X- _, N; C' a. v* p+ X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) R5 l9 D l% p6 F; W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # J1 w5 q( w0 |7 F4 e' K& O# C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ C4 Q3 P& [7 J* S/ c6 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) h, y- V! U$ K0 [0 c, b* [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 g# O4 u7 I0 r8 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% u. B7 h- O% m; ]! S
0x00, 0xFF); /* configure the clock for transmitter */
5 Z# g! {) t9 k& s2 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 }+ \9 B! R6 ^: Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% g. k5 U8 D$ {3 O w. t6 P9 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 B* G8 X$ [; F+ J5 ?
0x00, 0xFF);
+ l8 u3 A5 i/ r; O- {& k3 [) Z: Q6 U* r9 H0 ]5 v! @ n' j1 P$ y6 X! C
/* Enable synchronization of RX and TX sections */ 9 |- M0 l5 L! t9 q- Y7 m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: p2 k/ S$ X* XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 {/ F5 V7 l1 o, o' f9 lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! T, p, X' Y3 W2 h** Set the serializers, Currently only one serializer is set as
' Q8 l- y" e1 h) }6 t3 C+ f' Q$ P** transmitter and one serializer as receiver.# `" s* s. _5 o1 M7 o" I0 g5 q0 o X
*/* m h, [, Q: K4 q' L6 v8 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 M1 M7 J. ~* j' A2 V' g" n) {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 ?* y6 U [7 U1 ^** Configure the McASP pins
/ u. M) p# I p4 A8 D4 [** Input - Frame Sync, Clock and Serializer Rx
; B X( o& T; S: w8 ~** Output - Serializer Tx is connected to the input of the codec
5 @, ]0 [2 {6 L+ J; M! _*/
. |$ e* P' _0 @$ DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ ^9 ^4 X" n* \; eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* J( j; x+ c! Z" n4 N) Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. x) b/ c6 y0 C! t0 M9 K7 e, s, U| MCASP_PIN_ACLKX
; n- ]) ?5 Y9 \' w| MCASP_PIN_AHCLKX
$ B8 h$ Z. k8 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 {, K5 l. p+ x r5 ]! BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' Q. z0 i8 F& f| MCASP_TX_CLKFAIL
& b# o1 |/ q4 m: o& h' u" N| MCASP_TX_SYNCERROR
2 P6 c9 t% J1 V& C6 d& o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" G8 @2 B5 I: B: n5 a2 S; b% |. g" [| MCASP_RX_CLKFAIL( i1 c$ M% V% @4 Y7 {
| MCASP_RX_SYNCERROR 3 z: s+ }: S/ s: a
| MCASP_RX_OVERRUN);* R( I4 k9 x& F
} static void I2SDataTxRxActivate(void)
& J/ j& e4 T1 K6 {% s* ?{
6 ^' t0 G0 V7 O+ ^+ ~9 w/* Start the clocks */. Z* U; f$ O; P, p4 Q& W/ \6 U! J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 d1 ]. k4 E/ y; t% l; OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ ~0 u1 s1 u" C& ~0 J8 T$ j$ NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 r4 Q S0 K9 k7 G) s5 YEDMA3_TRIG_MODE_EVENT);
6 [. r$ z r8 e) d9 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ Z( t0 F" u4 T6 \2 K" J" c. sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 }4 y7 u0 r! G. P) o7 R SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% J5 o! \ F6 b8 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, z( f! W- S# ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. Q0 f# P; Q; ?9 k* Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
L3 P/ {! |. ~. D- cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& t& f( D4 V& v1 w, Z% ^}
y0 M- f5 z- N) P4 |( o* \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . z1 C y+ K( Q" ?" @1 j
|