|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# H6 {7 Z1 L# m& y/ b6 g9 `
input mcasp_ahclkx,, G/ ]: e9 B7 ]* ^2 k) G3 d- v8 M8 N+ ?/ ~
input mcasp_aclkx,) x. v- S0 m$ ^) Q5 ]% S
input axr0,1 C t3 N; i: r6 `
' w, U4 d$ t+ k O, woutput mcasp_afsr,3 E# D7 E7 T4 c K1 W; h
output mcasp_ahclkr,
8 T# c) U. p+ q+ a5 F/ T5 k! soutput mcasp_aclkr,1 x0 F/ |8 e$ p; {, P( O- N" E
output axr1,: t, r1 A, z# v" z9 J" H
assign mcasp_afsr = mcasp_afsx;
- y+ y0 U. L/ G6 b+ k% k& ?) oassign mcasp_aclkr = mcasp_aclkx;
. T& D; m; B3 p! c; G; A4 rassign mcasp_ahclkr = mcasp_ahclkx;
* L# M% S& X& Y" p2 `( a r0 Rassign axr1 = axr0;
0 n( E8 X8 ^/ K3 \6 ` S
+ G' U/ `; J) V: V* ~; h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( M, N- J# c/ e
static void McASPI2SConfigure(void)2 [! o5 o) Z4 u% s' t* G. ^: W! W
{
3 P i7 o4 \* k' M7 I, \McASPRxReset(SOC_MCASP_0_CTRL_REGS);& ^2 [" z) O _; x: }8 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# x1 l9 e$ m v3 S6 ~+ qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% ?1 q. }4 d2 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 I4 M& T9 t. L ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Q. x. P3 u' q& V) m( r; {/ k
MCASP_RX_MODE_DMA);
( q/ R$ ]) k k, Y9 n* {9 C3 X/ `6 B& pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Y& X5 N) d( D& ^5 _# V8 I% J+ SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, O: P ]! ^$ r/ ?- CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( a2 E+ \" v0 Y/ V6 I* W) ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' |" _* H5 \* `. B8 E1 F& VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" i( M, Y( r4 y SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ P/ @" a7 ^" E% P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" z6 n& X4 s3 [: b- [5 K* eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ @7 J/ L* u4 [. s5 f: Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 q' t( S) t% M$ X4 Y4 O/ y: w
0x00, 0xFF); /* configure the clock for transmitter */, R; c% H# o' a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# R: E; b$ @ o+ U. E7 b: rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% Y: f" f) w, f0 D) ]( sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' a! t! V) D1 H/ @0x00, 0xFF);
0 p o y5 t1 H# ~% h( x$ b9 J# p1 I; K) f6 W; {: X: j/ r' [
/* Enable synchronization of RX and TX sections */ + C/ o9 l% B& _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ x* j+ f* u) R. J- a( w3 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. P: |% x$ \* B+ y$ I( x0 q: g% \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; V* `5 [3 K& j8 \ p
** Set the serializers, Currently only one serializer is set as
* C$ ~5 V2 j: D+ z** transmitter and one serializer as receiver.
. X' B- r* I* O; m+ G; J* g*/
' Y$ n8 q9 u Z! xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ l/ t* b8 U/ S; @9 c+ }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. o+ I! E. J) p. ?
** Configure the McASP pins 6 f; r( H4 S o, E
** Input - Frame Sync, Clock and Serializer Rx
: U" U+ Y; f2 @( h** Output - Serializer Tx is connected to the input of the codec
/ ]7 \# o5 |9 d* S*/
" b3 [6 y/ R1 N, s+ z! D5 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 V2 n, N' R* `% \7 E9 e/ cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) \1 r N$ o" {) D( c1 Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 o3 z! y& G( R$ D/ A4 L! H) r; i* Z
| MCASP_PIN_ACLKX
/ t" \: E k# \4 I| MCASP_PIN_AHCLKX
; v/ \2 R2 n2 G6 n4 j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ I) x2 o& P. w, o; \7 ~- I# G2 yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
h2 Z: \4 l, f2 g$ J! i; W: j( t| MCASP_TX_CLKFAIL 8 Y- ]% T) W* e8 v# `* T
| MCASP_TX_SYNCERROR' [6 s" j! S9 ^. H3 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * Z( H& s, n& |
| MCASP_RX_CLKFAIL7 b0 W' o, U. R, J o7 J9 h0 W- ~
| MCASP_RX_SYNCERROR
0 j7 p( v! z) N o M# }| MCASP_RX_OVERRUN);
0 t0 t: X% `. v! N- \, c' ^} static void I2SDataTxRxActivate(void)
* m! h: @. f( N3 P5 Z{( R) o4 ^# E$ v$ m9 j: M
/* Start the clocks */; u( d3 h* f/ ], U4 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- c5 v: I: |! w$ d; M6 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" e7 | g0 ~0 u& J/ K }. h0 @' S% ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( S; @. `3 u+ j! M% y+ k
EDMA3_TRIG_MODE_EVENT);
) ?; i/ t' ]+ O" t0 A |/ b3 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : j& S' h' W) F; q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 m6 S0 h3 B3 d, L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& D1 w8 Y4 D4 u; }/ |5 k* b- ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 v. a/ y4 T! f9 F; x. kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: i* X3 K$ b2 C" G& ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) J( U, X" U& f( G7 c# `1 IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 p' q% G# b8 _ U}
+ a; i; h- t2 `/ u* ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 V. \- S1 S0 h' S5 T" x |