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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 Q! w$ {3 G" ?
input mcasp_ahclkx,8 Q* e- }5 [- ~# }0 N" [) i, m# x
input mcasp_aclkx,
l: T \' p' Cinput axr0,
# Z1 J, j9 M0 d' h' ^& v8 U9 Y) U' \3 R
output mcasp_afsr,
d* ?5 ^: p W# ^$ Loutput mcasp_ahclkr,, ~; k- k h6 c3 ?/ P" h/ y+ V
output mcasp_aclkr,; V9 G y ^ X l. R
output axr1,# ]; b9 O0 a* `4 K" o
assign mcasp_afsr = mcasp_afsx;
0 I& O- O9 ?: M3 u% b: ^assign mcasp_aclkr = mcasp_aclkx;" A4 [* o% J1 H; i6 H
assign mcasp_ahclkr = mcasp_ahclkx;6 x3 d6 ?' s( A* P
assign axr1 = axr0; $ [. p4 x$ }4 |4 ^' C! x4 m" H
. n+ a2 a6 Y+ B: C+ Q! l d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! O2 {' F& k' j6 y" X! H4 w
static void McASPI2SConfigure(void)
: X0 \5 T& I, ^% }+ v{* i5 ~ O% {, \ P: u9 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 {/ ?& t3 f& G& T# T2 @( y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 ?9 F3 Y$ K7 m* q- Q; a9 J" Y3 x+ ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ n; d' U9 p* P- q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( \+ v$ i2 l3 T5 r# H1 E* G0 q2 `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; V& ~3 g+ t& ~7 G+ ^& TMCASP_RX_MODE_DMA);
4 E% p0 {& g" H @/ L! w( t' x4 S4 X0 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- }7 A3 E! v0 a( @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 r' K. D. k# S% p- V. lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 q1 K& m4 N- Q! G3 ]% Q# K+ f# L7 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 c; S" v, U; Y+ e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + ~6 a5 \. f2 L6 S) }* v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) U, y: o1 s" k" a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 o& H1 [+ v y4 u0 D* \/ R, R& ], a: OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
[8 ]8 q% O3 A7 x* Q" VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 B; x& ~) O0 h
0x00, 0xFF); /* configure the clock for transmitter */! @, z# Q- X- S/ S" p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 b0 C$ w0 a, T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + z2 }1 a, s5 N3 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# e7 e/ P% I8 d* w8 l* U& r
0x00, 0xFF);. R/ j0 a$ C7 Y
$ J" c/ ~, G, `) R) A% M2 i A! i
/* Enable synchronization of RX and TX sections */
# ^# u6 y( S# nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 Q9 r( q! v" N2 Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* v7 U) r4 t. Z" @6 |. s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 O Y4 Q) O8 I6 R2 d5 q9 f/ w** Set the serializers, Currently only one serializer is set as
3 G4 e7 V; m- l; Z** transmitter and one serializer as receiver.+ r8 c F2 D0 Y: x( c& C) G: G7 i
*/& n8 P6 f/ ], n8 r! p* h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* k6 j3 T# U# \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! d4 S- m1 u& s% m6 P** Configure the McASP pins
0 y1 g5 V2 y3 M2 t; O** Input - Frame Sync, Clock and Serializer Rx T% U% |3 C8 C; Q. r( L
** Output - Serializer Tx is connected to the input of the codec
- t4 d, p L t9 v: \4 j*/
# g( _, m# v$ T. t- kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 Y. E4 Z) i7 Z/ V8 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 H; f" H% N4 J( Q: xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; }) m$ J7 |; {" U( O6 F* a1 R+ I| MCASP_PIN_ACLKX s. U; X" Z& ?
| MCASP_PIN_AHCLKX
0 t8 E; A' L% ]7 d) u, B2 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ Z3 K# q* g7 ]" c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# m: V7 j+ B+ G# k. ~! m| MCASP_TX_CLKFAIL
0 d( ~6 e8 ^5 Y# @2 Y+ \| MCASP_TX_SYNCERROR$ D. R E6 O. g6 L! o. a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , c0 L; J/ T4 k& D
| MCASP_RX_CLKFAIL
; n+ K8 n( m3 I| MCASP_RX_SYNCERROR
2 i ]; W/ h* ~# ^% c% b- O$ u4 ^: O| MCASP_RX_OVERRUN);$ u1 e1 F2 f; J- I$ M8 ?
} static void I2SDataTxRxActivate(void)
5 ]4 ~# m7 s; y6 d{# b+ r6 r6 p# t" Z
/* Start the clocks */& I' n2 N8 p: P% J) I# d5 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; B B' h# u+ Y% V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 ? J: `) C R1 s3 k/ S, L; L2 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ r) `9 p; g/ e, @
EDMA3_TRIG_MODE_EVENT);. C1 e; x+ k% E9 ^4 A% @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 q/ a$ K, ]4 K _: b! `+ z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ _! s# V3 L4 _6 G5 P: P3 f& G" }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) w0 g' `2 G, s, @- j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* c. @1 d4 n) m7 d+ X e3 N. P, _0 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, C8 k" a( u9 I% }7 dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. q- o; b4 g0 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* ?: T; ^5 v2 u2 m}
2 _! e- m! y6 @# W$ {- h) C$ K! R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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