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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 s) |. [- J7 \6 V1 y% R
input mcasp_ahclkx,
# |+ @3 n: r! U/ linput mcasp_aclkx,
5 g) O% p/ e9 t- }3 c5 ninput axr0,& V) R7 f; K8 B. g
% D, q* @* X9 ]
output mcasp_afsr,
; _1 \2 i, V0 e5 koutput mcasp_ahclkr,2 ]# }; b2 f* @" N
output mcasp_aclkr,
. [; M# J! E2 @5 n. S) m7 T- V- U1 ioutput axr1,* v: C; C; J! y" y1 H1 o q
assign mcasp_afsr = mcasp_afsx;. \* h( r9 y8 D: s: j; U4 j
assign mcasp_aclkr = mcasp_aclkx;
) l! L2 D! c. v7 f& sassign mcasp_ahclkr = mcasp_ahclkx;
/ Q$ Z+ E2 P1 l. E- Z" bassign axr1 = axr0;
- K7 \6 @# g1 t* T+ q
& ~8 L- V p) s4 b, ~( Q- j- h2 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# q& _; E2 F$ W t( n. Gstatic void McASPI2SConfigure(void)
* O8 N5 g% S& n4 Q/ S& q{, N1 D3 o+ J0 @7 m" J% {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. Y1 x1 k9 H5 c6 G$ SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 E# D0 R* n# Y; ]& _ s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- s( G) z2 @+ D) S& k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 E/ H9 n4 p) h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ?8 Q# e$ A; v# FMCASP_RX_MODE_DMA);% P8 P5 H4 g @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ^" W/ M4 O) H7 bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& @+ J& z" P3 o, k2 F5 U& sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ h$ S! r1 o9 p4 T" X+ k% q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 l) z9 n$ D! j6 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 E# X# e- D* [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, p v/ @. }9 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); ]/ N; i I- [: l- Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 N, W& O1 ?( q$ W! s; v# p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! L7 _( Z* t; r7 p3 D# o0x00, 0xFF); /* configure the clock for transmitter */
) P- \* D8 s/ I# v5 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- X1 V# g4 q, ?2 T- wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 t5 c6 B, T9 _) i8 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& u# h H6 W# {( U- z' @7 R0x00, 0xFF);
1 o [% D0 D( R: x9 T! F
: R8 I0 Y) _8 k/ l& P* G) m/* Enable synchronization of RX and TX sections */
5 @6 F m4 M6 R( eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. i7 _* t* N4 s, f8 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 L1 K/ i1 d* m; BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* F9 t* A, I$ i7 \** Set the serializers, Currently only one serializer is set as" l, L* w- k2 M* Y6 O( j% Y
** transmitter and one serializer as receiver.
3 V9 @1 x9 t$ f9 a* `" D1 {*/. b, F7 C( |& W; L3 S' U0 G7 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& u; e1 B' }2 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. \: [1 R' I* ]
** Configure the McASP pins 6 u# U4 c' x9 ^1 X, m: ~! B
** Input - Frame Sync, Clock and Serializer Rx8 _# S( I' M0 [
** Output - Serializer Tx is connected to the input of the codec
: d/ V! M# K( P' `*/
+ X, x, d6 q2 I6 X4 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# R0 W2 j( P3 b" l9 W+ gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 q% W- B$ ~8 w5 i, f' sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ I! Z( W0 l) s& {! @" C
| MCASP_PIN_ACLKX
; [5 q9 I+ p5 J; U4 B| MCASP_PIN_AHCLKX4 K5 ~7 F% ~0 `! Y( P \+ @' o5 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 k+ O5 H% B ~1 t' I- PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& y' w7 ~! v: q C. H( E| MCASP_TX_CLKFAIL " D3 t3 w/ Y% N. G* m+ O
| MCASP_TX_SYNCERROR
1 E" c* {- w1 @# z% D* T& g" Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: o8 p, O: w. |0 }1 K) N/ V3 U| MCASP_RX_CLKFAIL: o) V6 W& q2 Q, r
| MCASP_RX_SYNCERROR , K3 Z3 q7 w" ]$ m" ^' P7 L/ Y$ Q+ |
| MCASP_RX_OVERRUN);# I1 {" V9 A( ^. t
} static void I2SDataTxRxActivate(void)
+ y0 B- s. a3 F, Q" P6 N' ]{
/ L; P3 ^2 S0 h5 Z* c+ N/* Start the clocks */
+ ]2 V- M7 F( Q7 r% l eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' s) s4 o; [5 Q$ X% P1 X# i% fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 L$ J N8 B6 G) m4 E$ @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" m' B/ ]" P6 Q4 i& U* q6 |EDMA3_TRIG_MODE_EVENT);
2 W& g* p) V$ M* [; `9 M$ g, {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 ]! Z- R0 \- N0 k( |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 {' Q0 |& N5 b7 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. ^5 q" W1 H1 J- X* J$ k6 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 k* x# I. M- o. a1 {0 x( O: {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) W8 b7 Z4 |8 {, `/ Y: F0 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
{2 M) ~; A* ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- H/ f; d& r4 l2 C} , i* u( F+ a, d2 p! ~3 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 h( Z+ Y7 Z! _- k% l, c
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