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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 u, S% r& S7 | p
input mcasp_ahclkx,. i% ~9 L" f: o* l# o
input mcasp_aclkx," q! `2 _+ |9 i3 v
input axr0,
) k9 x) M% a+ t$ k* C8 w, p7 @/ f# @/ Y; }6 s3 l' W" x/ y2 T
output mcasp_afsr,
0 x, K. r* \5 h, K B4 n. q9 q0 o+ Woutput mcasp_ahclkr,
) z2 s/ i5 h/ J3 P% k/ Toutput mcasp_aclkr,, z% @8 y# g' Y
output axr1,! K3 b- L/ c+ G$ b; Y5 S1 P% ^
assign mcasp_afsr = mcasp_afsx;( A; w5 }( _: q; |$ u# C
assign mcasp_aclkr = mcasp_aclkx;
. x/ L1 A2 ]% d7 q. F; jassign mcasp_ahclkr = mcasp_ahclkx;6 ^! N3 c& ~# z5 I$ n, m0 }
assign axr1 = axr0;
+ Z$ c4 L& p- E9 Z
5 v# g9 d2 D" c. H5 W& T; H# U/ O: }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : I4 X7 E1 k! c5 f
static void McASPI2SConfigure(void)
1 Y( O0 S1 g& g: g( ?{9 G1 I) }8 D* R; }9 R: L) I4 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- ]" C! D2 d" I) p- G, j4 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% Q$ |- b: h+ Q" ^5 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. o- _2 N0 ]* o+ n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. ~( @! }" `0 I: T. wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% v' b. k5 H5 H C( t) N6 [, t! O: TMCASP_RX_MODE_DMA);
) s2 c& t! [9 D- ]; ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% O% j1 K+ a3 a7 j! t3 }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 F; h' Z9 Y; T9 x( r: Z* ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / j4 U) T) D. P$ g/ O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ \( _/ Y+ m3 ]! R. w( [/ ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 {0 I, a% g1 T/ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 i0 Q% `# U9 G- c# [8 q) [; Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 P' |9 z7 _7 c7 @* m6 S/ {( x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 ^, w$ D7 `5 ?0 I6 @* U# JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* r4 z" ^9 g% `. ]# Y' F6 ]0x00, 0xFF); /* configure the clock for transmitter */
# l4 I8 H5 m# w* MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ V" }3 {, l! L5 d2 d7 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 E$ ?. @+ Y+ |- d u! ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ C7 c ]; V% D9 v. X$ }2 {
0x00, 0xFF);# j( C* g7 @" c* c! L3 t; L
5 V$ Q( f( J% L2 O+ V
/* Enable synchronization of RX and TX sections */
* C* U# W. G! o: q/ b0 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 U$ j4 J* w7 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# u2 D, k; F! f8 |& b1 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, i" P0 d8 ^* _. ~** Set the serializers, Currently only one serializer is set as
4 r- y# n1 ]( q% t4 e" m0 l# w** transmitter and one serializer as receiver.5 Y4 w' [4 U2 {" r/ p" ]
*/
% k1 o5 o# \* Y8 f0 z( Q% R2 R5 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 D) i. a9 p$ _& j; s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** D6 k( ~9 v: w. V; H: ~
** Configure the McASP pins : p4 Y5 \; U( s9 x
** Input - Frame Sync, Clock and Serializer Rx
( q- N$ ~* `5 V* u** Output - Serializer Tx is connected to the input of the codec % ~+ F9 d) Q$ B2 k
*/9 { P( ~9 m V, d' c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# _" o, ?9 K* s e% `( a$ bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# i5 u" T0 [2 G) W, r4 n+ DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 L d3 R w5 A& b| MCASP_PIN_ACLKX
1 {' M( Q& t* G! n& G# `. `. C l| MCASP_PIN_AHCLKX
2 v7 M. j, q$ B. f& U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" ^" M- ^( j* G, s" k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" w {8 v8 ]2 F8 r1 |3 T" A| MCASP_TX_CLKFAIL ' M5 z" c l% _+ I: E! N
| MCASP_TX_SYNCERROR
0 ?/ L/ W# q1 M" X: I6 Z$ I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 @! Z9 x4 R/ j" X. S7 _0 Z
| MCASP_RX_CLKFAIL
4 d. F3 G! H1 `- G! k2 f) \| MCASP_RX_SYNCERROR
3 n3 E6 r, Y0 J| MCASP_RX_OVERRUN);, c- o" b' @% Y# d }
} static void I2SDataTxRxActivate(void)8 o- j. L3 {/ Y6 [8 v$ i
{9 p/ _3 ], s" f' }3 n
/* Start the clocks */
* g! X/ J) ? e! l8 @7 ~. E- x2 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& N& e4 c. v- n( v. k, j5 H* ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ ^! q" }7 y+ g& O2 S H5 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, o9 T# a/ `- x0 I
EDMA3_TRIG_MODE_EVENT);5 V2 r8 b# r8 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 ^5 F ^' s5 Q! f% n7 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ O9 h, x. s9 j W4 V: V( }( o/ C& ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! t/ n6 {" G$ [& g3 ?( l+ K% i; g, Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 s' p* k* `- S; w4 X( Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- Y$ }" A7 w0 S9 C" k0 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 E3 ?5 p5 I$ i H% ?2 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 u: Q7 L6 Q9 Z- }+ u1 _+ F
} 3 _1 D& e% Y0 Z( N% `. y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & z% p$ s- f8 ]1 m
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