MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
- u) V7 |, f  I3 L9 w! Y/ xinput mcasp_ahclkx,
input mcasp_aclkx,
; s! ^2 Q# [3 B1 |1 O* ]) u; Ainput axr0,

$ z% ]- a' @' v+ h+ ], Ioutput mcasp_afsr,
  f. N1 v$ |. m! P/ ^output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
; O* h- d. w8 {assign mcasp_ahclkr = mcasp_ahclkx;
7 N& Y6 e9 y: b2 U# hassign axr1 = axr0;

6 K% ?* N; }& g( B

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

8 D/ L0 N% _9 X6 n# u+ R5 v( b

static void McASPI2SConfigure(void)
{
6 `) y; |/ t, |5 k/ FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) N0 E( A5 e* ^$ tMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 l: u3 }& f6 J# t$ [1 GMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& m+ Y6 o0 G( N: z1 Y3 ZMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* l3 C) t: b, v# J4 j. I- N1 d* p; AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
7 W& Y8 m" s3 i3 y! MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! \1 J5 V& O. u; f5 g/ C* HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 [1 q, D$ P, V5 {) O4 S& U: D6 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ C/ o( F$ U# p& Z9 g( _+ G4 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
# R2 B3 ]% H6 U# v4 c$ P' c% c5 V2 w# lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
# Q. C; F( b" ^# P. VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
0 {, O" Z) m8 J$ x9 S** Configure the McASP pins
$ p, h" Z' l: ]4 l# }** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( x3 t% y8 n" a/ j) e1 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 P# n! s9 M+ l/ x| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
1 l$ |- I5 ^) ^/ ~1 _| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
7 Y( l) C5 X; Z  {; ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; j/ G8 t, [4 K% G/ g| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
5 v9 d- i! x; Y: ^| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 M: ?; A7 q% y- E| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
; S2 i7 i% a. U1 Z1 B| MCASP_RX_OVERRUN);
; H6 P. V9 C4 W! ]- d: o7 \. [}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
1 A+ q3 n- M/ [* y7 \% jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* U/ Z( D" w7 M. q5 G* uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
/ E& w5 I5 v7 G- g- yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' ?# v/ H: a4 V  B9 f7 q* HEDMA3_TRIG_MODE_EVENT);
& z- Y+ r+ }( _/ x# P/ V* ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
  U1 {- l0 \# q2 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. y9 j; {+ M2 I* M$ G4 T3 V, h3 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
# C6 V& H% S, b6 m7 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
3 U. l2 v, |0 z# pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# t5 H3 r# m0 {' v" ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 f2 l1 u2 @. E1 Q& m; N}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.