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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& \+ _. }, O( C }4 G
input mcasp_ahclkx,
: S; r! d# m+ G" b) F" x0 Ninput mcasp_aclkx,* E, W( y: R6 B1 N1 Z$ E
input axr0,: w6 A) G6 F) J/ S
1 y& T7 j- q$ B3 T, K' r; {5 L7 B
output mcasp_afsr,
" J9 H! @. p! U, N0 Toutput mcasp_ahclkr,3 x9 Y( P; |" q( Q
output mcasp_aclkr,
: {+ t0 {4 |/ h" qoutput axr1,5 E" B8 P, j$ w- m$ J
assign mcasp_afsr = mcasp_afsx;
6 x+ k% n8 D7 U0 g2 oassign mcasp_aclkr = mcasp_aclkx;
% N+ \0 Q2 z7 F/ _/ Vassign mcasp_ahclkr = mcasp_ahclkx;( {8 ^, E" y3 L7 S# T; S4 X
assign axr1 = axr0; 4 Q1 W% W- s/ p
) ~2 Y9 L8 M7 c7 I/ a4 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! [. b. K( h$ T! Cstatic void McASPI2SConfigure(void): \: G; G- {( F `
{
% j8 A+ B% w7 s6 p/ e8 CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 j9 r; V9 e0 i8 Z4 f; UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 M1 F( J: G% m6 ~1 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( b) [: B- h2 g" w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* ^/ K. H$ ~" p7 I: s ]+ `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 v# P# J7 F2 Y
MCASP_RX_MODE_DMA);
K* o& N; @" W$ |; v1 `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 W; x# x7 u8 b1 zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 W6 H9 F y) u6 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* H% Q- @$ h) R* E% e) C) G2 Z) Y) SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 [2 y) K5 n4 S9 d) @0 \+ ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , h. Z; ?1 q$ Y. u/ ~. R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 [$ }& h4 K( x: H: f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. P0 C4 J4 p6 O9 h/ P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# r8 _2 S# n: H5 Y* w. I! j( sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( a- B! u" q u0 l2 T
0x00, 0xFF); /* configure the clock for transmitter */
7 c! W3 h) G- l" m _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 L3 j% F* K; M/ M G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 h9 y% i& C+ B/ }6 y+ h- pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," f2 E# D) N; x% g. ]# _5 f* P
0x00, 0xFF);; F5 r3 p8 d4 ~. D* J5 I
$ z6 p, T% Z* `$ ]+ ?/* Enable synchronization of RX and TX sections */ - m: ]) `9 K! ?) B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ w/ K' x: b0 S; h# \" L/ G- p/ V% WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- E! M- f6 B! ~: p& Y/ ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 d0 @) q% Q- A& @** Set the serializers, Currently only one serializer is set as
# b* o3 T- N+ s% k0 a( p b- F; f** transmitter and one serializer as receiver.3 J, W: \. D2 p% r1 j9 x" I
*/
! u% o- [4 h' Y- w. j6 n! `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 L/ j6 d3 T; }$ `( wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 `2 `* X7 Z! N$ l6 w
** Configure the McASP pins " A0 T: q) ]0 C2 y1 B
** Input - Frame Sync, Clock and Serializer Rx
/ f$ C( b/ E$ v6 d** Output - Serializer Tx is connected to the input of the codec
' s6 ]' |* D) s* V" ?*/
5 S! |+ m8 i5 Q4 o! g. oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. x7 O4 }. f" h- D' e; _7 a4 T, LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# f# e/ L9 E2 F. n7 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& \0 D- y; ^- M8 }8 {| MCASP_PIN_ACLKX
! W5 i. g% l* Y$ G| MCASP_PIN_AHCLKX
+ v1 C9 j* w5 o; k; [: L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 n0 _5 ?+ [% @% J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & u3 D: I* i K1 G! C+ S0 t3 ]# B8 X
| MCASP_TX_CLKFAIL
. [/ c2 W- R. |, N2 K8 _. Q| MCASP_TX_SYNCERROR
* m' q( k& U. |8 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! g5 d( f( C" ]7 o# Z
| MCASP_RX_CLKFAIL- y X" N* k8 X) H; U
| MCASP_RX_SYNCERROR
& A5 C% u7 J6 j6 p' Y5 @: _| MCASP_RX_OVERRUN);
" e" b* u" L$ k, @! G; [} static void I2SDataTxRxActivate(void)
; F/ {2 X# a g( `- z0 P* ]7 h{2 ?7 e M& p; E0 k+ a
/* Start the clocks */
4 C: ]- W5 o( h8 j8 }1 E1 L4 E/ dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ _1 C9 U7 G3 f( k- V: TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ k; [. G) k! C: a1 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 y& a/ x# b4 \2 J) x* g2 ~$ p
EDMA3_TRIG_MODE_EVENT);& A8 M. U1 p9 G+ j3 E$ Q. y' o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) o( l! A7 ^2 b2 K5 _: WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 y" U) _5 [5 s' yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- z3 d/ |6 Z* W$ h4 c3 K3 x' sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 F' a2 d. P4 Y$ ^3 ]2 y% ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 g m) @ O6 S4 r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 K3 C& `: p1 Y, F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 P$ {) o0 O- y+ H/ z% v
}
' R E: q! `2 j! ^0 a" m1 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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