|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 C: a5 v! b A+ W% |input mcasp_ahclkx,8 D+ M% B( v4 l6 v' _
input mcasp_aclkx,
. c. [$ U, |# Uinput axr0,
6 x2 I! j" L1 @- I! q$ p" o
% H+ {+ Q# j, `+ k/ Foutput mcasp_afsr, i: S8 s1 w7 h) D3 j* J" L2 y
output mcasp_ahclkr,
5 N& ?! n) u5 w! woutput mcasp_aclkr,: M: Y1 _5 g4 k, @
output axr1,
7 t( r% V4 H: c5 M2 [ assign mcasp_afsr = mcasp_afsx;2 B4 v8 s+ p& j# {5 u3 l+ c. h
assign mcasp_aclkr = mcasp_aclkx;1 }. Q- ?- G1 `0 C2 g
assign mcasp_ahclkr = mcasp_ahclkx;
, F1 B9 l! a1 E" Z3 O0 z& yassign axr1 = axr0; ( M3 {: R3 w% O F% n. V! f& {$ Z, N
1 u3 n8 D) a, |' W/ u( l: _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ q, u# J* x5 C: y: X4 d, Lstatic void McASPI2SConfigure(void)
( R( @# [: A% u( u- T6 @. ~{ F% _9 Z1 u) l C6 v0 ]/ I- G* J9 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ D2 m" T# s+ U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ F* N y0 b, V% B9 _' y: s' x; \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. O6 F$ H+ H1 z, p& oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 _ f5 x% K# L6 L( O5 i- X% ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 ?+ c) t$ i" Z
MCASP_RX_MODE_DMA);" I: t# d) I5 G8 N( T# N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( Q8 y% Z. r& a) h0 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// v) T4 D; d/ Y6 a* a7 Y; j. t1 Y7 l/ G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 \1 Y* u9 G3 k. m4 F# ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' f* [7 ]3 S& [) R7 h8 D, ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 L( u p9 n# ?8 `4 C, D' X/ ^6 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 @7 d3 }. a& F/ ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 X! [$ `3 l! K I0 s( r8 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, J+ v6 T6 H- M$ Z8 _/ HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& V: X9 O. H. A: [, H A
0x00, 0xFF); /* configure the clock for transmitter */* C7 g9 b5 \& T' r: v+ c: A$ {+ O( ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' Z3 J q4 B1 d/ s$ S! f3 dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 J4 s \! Q \; `; r* c# GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" q% |3 `/ R4 U- P( \ D0x00, 0xFF);
; f* u5 M i* t, d- d/ E: K, Z5 ^- }7 Y
4 i7 a% k; p9 u2 }8 L- W$ J; B* `/ {/* Enable synchronization of RX and TX sections */ ! j* y. A+ @* Q8 R3 q0 ^+ _) r. f0 s$ R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# g; x* C# E/ x G% {- LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ ?4 W' A; d0 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% O- j/ C( s; g& l** Set the serializers, Currently only one serializer is set as
, O2 A5 \7 j ^) r: H) ]** transmitter and one serializer as receiver.
" U+ o- `, A; p4 D7 @" C*/; B5 M7 _/ p, l2 l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# S3 c+ z4 a( g- U# K/ Y5 ]$ U% w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! _ }5 _8 I1 i7 c& p$ @** Configure the McASP pins 5 h; s& a2 e9 ^( [$ h4 ^3 i6 x% Y7 g
** Input - Frame Sync, Clock and Serializer Rx
( N4 b5 f0 j. E1 B** Output - Serializer Tx is connected to the input of the codec
3 b9 o6 z9 W D" ?- D) @7 Z*/$ r T* `) B4 |. `& `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( |- a' }+ ^ D7 ]% z `& k! ~! zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 e H# p B8 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! T4 M7 T! J0 W! U) h. j) [: d| MCASP_PIN_ACLKX* D& ?# g9 o+ L- p( |9 ?2 B# J
| MCASP_PIN_AHCLKX2 {3 s8 C3 N) R! ~# k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) K3 l3 Q/ W3 @4 w+ h1 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* k; |5 R$ |% @4 [2 R r+ c| MCASP_TX_CLKFAIL # ]" ~7 n L8 V% ~8 c0 W1 c; {8 \
| MCASP_TX_SYNCERROR
8 l' ^$ e8 ~2 l) V; E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% G2 ~/ k1 {3 J" d3 H. r) P, a| MCASP_RX_CLKFAIL
0 |! e4 I+ d8 i8 ?: Z4 L E| MCASP_RX_SYNCERROR ; j/ `6 k0 O* s; V+ h3 F- F z$ P0 x
| MCASP_RX_OVERRUN);0 I% E/ `0 `& B' L$ d
} static void I2SDataTxRxActivate(void)
- @8 v2 K0 v# @5 A{: b) i1 H* D2 j# y+ s9 j) _
/* Start the clocks */3 G+ S, Z3 T. ] V) ^7 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 K5 E/ F4 T: ]; X6 g* x* M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 E% N& \1 j" `$ W" h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 _; \: u5 I$ F
EDMA3_TRIG_MODE_EVENT);
; `- }* F* F/ C! ~5 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & M& J4 p8 g' q" _7 i$ U6 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 \( j. S; D& f" t2 @) s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 q2 X' N$ O8 A+ P) K Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 F1 ^4 b6 v& I$ {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ W( q; ]* X+ ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 Y: [, Q0 N5 o/ m) Z8 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 Y) G# D, s: Y( b+ y; C" _. i} , z" y( p7 W: t; ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # u' v' o' @+ P
|