MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
3 j2 C7 d  s4 W, @# B  o- s& Zinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

) X8 C- c0 R  d/ Aoutput mcasp_afsr,
output mcasp_ahclkr,
$ f8 N- Z* ?) w/ f' q. Youtput mcasp_aclkr,
3 M) N/ D) {8 a: L" Houtput axr1,
) x; d' L, J; `& b% N# O

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
5 V5 @. S! \+ _+ \6 F- Iassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

7 c* P& n$ z% }: a$ I% q

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
' G) T/ b0 L& @7 U( y; g{
4 ^3 D! f+ W2 O' G+ Z( u+ OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
! x! G& G4 Y% f& fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! q0 {! w* y9 Q: T4 S! U8 Y, AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
& _2 s1 M* T2 Z( f; g3 H4 P/ I0 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 \. X' y! F# MMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 h0 s1 B4 ^! N' K3 o& {# m% J2 E2 QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
  U) s+ P- J; D( r1 O( h6 @- g% a' lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 D& u; n0 u3 \( }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
  P8 w+ i9 [  p% }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% F1 ~( W# s" X/ L0x00, 0xFF);

/* configure the clock for transmitter */
9 b4 M' x" l/ b! L' a2 XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# Q8 {5 X9 U, kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 Q( H0 s/ [: Z4 |' eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* A5 h0 K1 m/ E1 V* ?$ b0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
4 G8 s9 s7 f; h0 w4 {) k. mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ ?% f! x5 n4 T! N% SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
! _& p# O, ^2 x*/
3 M6 F# D% j* b, y1 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 d0 R& n$ a% U- m* ~" ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
, N( M: p0 ?7 h  a9 x+ ]** Configure the McASP pins
! _. @7 |! ^  b8 l/ Y- `$ W** Input - Frame Sync, Clock and Serializer Rx
' n- K" C0 {1 W6 w  N** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! r* ]1 E$ x, l# HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 D4 [6 U; a. j0 O, Q) ?  mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 N7 I7 {' U# m! e5 _0 t6 M) O| MCASP_TX_CLKFAIL
$ \0 Z8 `  B# @5 i/ a2 o| MCASP_TX_SYNCERROR
0 r4 o6 I  d# c, w( }| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
- A1 a( l5 l# s. D/ Y; x| MCASP_RX_OVERRUN);
+ `; ^' Z- q6 G& @9 ~* b+ X}

static void I2SDataTxRxActivate(void)
{
' c; t* l0 F1 }9 o' `/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 Z8 d5 c3 n. b" J0 EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
; y; l7 w1 i2 X8 G9 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 h4 A0 ?% |+ P* L1 ~0 PEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 L: ?8 c: q+ s2 p3 |9 ~8 {& qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
7 \1 M$ |# n! p9 v: T9 d- T" t3 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
; K+ |$ U2 U* @; j$ w" f5 v. ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, N' W. X7 K$ `$ J5 w$ V1 ~}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.