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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 H2 @' f/ J" P. d0 P4 dinput mcasp_ahclkx,* N" S2 m- p4 w7 ^/ `( ?3 I
input mcasp_aclkx,
) P! a7 i# `/ w7 ~+ D: O% Ainput axr0,' f0 k8 K8 V. i1 ~# n. J! A
! G# r* d/ u# p3 p# y$ foutput mcasp_afsr,+ n3 P: J6 N+ X! o, A
output mcasp_ahclkr,
% Q1 x( p1 ` E$ p! E; Z4 F- koutput mcasp_aclkr,; `$ f. ]( r* A0 ^2 g& [
output axr1,) [: N! \9 l& w+ Q2 _# _ ^
assign mcasp_afsr = mcasp_afsx;* T3 T. {0 S F6 [/ H* }2 O+ Y
assign mcasp_aclkr = mcasp_aclkx;
& o, n0 A. G7 g1 y! J( _' ^assign mcasp_ahclkr = mcasp_ahclkx;5 C8 S" f) { E$ t; e8 j1 T1 t+ r2 B) {
assign axr1 = axr0;
" [ B E i2 ^9 w$ l- t; a
) p% B) p! {- u7 U/ D: _' G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! [7 F6 V2 z: Y6 dstatic void McASPI2SConfigure(void)* z0 V, I- w+ {6 T8 j. V
{
' ^9 M9 e$ n5 L. v! D( x" O( rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ `3 V! F2 H- S; E0 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: w$ ]9 ^+ L/ t9 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' {4 P* M: p, W: F; j& `" O& LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 m. i/ ~) ~! z3 _$ n; W8 z( z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," W$ u! D! _6 ]. m3 A
MCASP_RX_MODE_DMA);
5 P: \8 H2 g# [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 g' u1 |1 f8 ? Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( c8 Z3 s, Q% H" c7 w- ~: @: PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " n3 ]5 E* O4 X! u& ^1 v( y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: }2 e+ @: Z2 s/ y- T+ nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & |0 w3 i# G' k3 C4 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. `+ r* n& g4 A+ p, X3 Y$ aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: F2 P% F }4 D5 N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 H5 ]& w: M( F- I# B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 d9 `& w5 O# h7 `
0x00, 0xFF); /* configure the clock for transmitter */
, @3 f2 D% ^4 ^& [# k1 ]) l) GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 [ i2 H( z+ u8 A3 {" F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 G. n: Z; V+ i, C# bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- f) M5 b# z" S3 G4 v
0x00, 0xFF);
$ e& R* @, G7 n, P+ l% l: @/ Z! N, ~) S; N: P: ~1 G0 f' x
/* Enable synchronization of RX and TX sections */
. y$ i4 B- c+ z e( tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 ^2 h# {7 ]1 z# wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, c6 x! R6 _5 o8 T" y0 |" H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** R% G0 M1 W% \$ V
** Set the serializers, Currently only one serializer is set as
9 _' R% u, f( H* J2 H0 h** transmitter and one serializer as receiver.
5 I( P& h* a- A0 Z: r2 Z*/( X- a4 v o! \; v$ j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 a8 K" H! v" H' ?4 O5 wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 h7 P/ R5 @5 g+ @3 [1 g2 t4 W* O! c
** Configure the McASP pins
4 D+ r1 A, [0 H( Q4 C** Input - Frame Sync, Clock and Serializer Rx5 J& f- d& y O* w
** Output - Serializer Tx is connected to the input of the codec / w- G1 w7 R' w$ d! n
*/5 @2 K" U0 X! B$ y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- l# o4 T5 V$ m1 \# _0 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 v1 h+ j6 x& v/ x O1 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) A9 X3 Z. R5 D5 {: Q- l| MCASP_PIN_ACLKX9 Q: |' q4 q. t/ o: @) z" O4 Q
| MCASP_PIN_AHCLKX* n1 x9 ~7 w4 p. a" C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// P3 Y2 ^5 r8 r, \3 y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 { _2 G! Q, y+ M; R| MCASP_TX_CLKFAIL ' M+ s+ \' G" J$ L
| MCASP_TX_SYNCERROR7 ?3 f8 I+ K7 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + K' ~" w/ G+ d$ A
| MCASP_RX_CLKFAIL
* k: x' c, m, d0 k| MCASP_RX_SYNCERROR . [( e) `5 w! D* y5 f8 I' b# K
| MCASP_RX_OVERRUN);8 p( _% s1 h' |- I+ X
} static void I2SDataTxRxActivate(void)
H! ?8 u8 Q* ]{
% U6 y$ A& o+ ]" b/* Start the clocks */
5 Q3 ^% l! h- YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; l: n- w# Y. L. u% a P" fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 X9 F2 E% X/ w# o/ q" y, ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& x; s3 n3 A( m6 c9 U6 W+ J
EDMA3_TRIG_MODE_EVENT);2 q7 q0 L0 e7 Z8 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' D, w6 d$ R* o" X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// }9 u Y( d% n* A i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% c. v( m" {8 a) K' k ~1 r% OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 B' _9 _, k! c, D+ v3 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 r& k1 ]* B7 L) W; wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 S( w" `& V. _+ P& P$ N2 G5 J' K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" q8 k' {+ @- F, G) O$ L
} : e5 u. f) V- B4 T) X$ L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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