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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 e y0 o$ v( N
input mcasp_ahclkx,- K+ m: n9 \/ `( E% J
input mcasp_aclkx,
/ Z5 K7 p6 [: Y0 y6 ginput axr0,; R' a2 K3 n- |9 K1 f
7 U$ H+ X5 S( g/ @
output mcasp_afsr,3 |8 a9 A) j1 H7 k3 e& ]# X( E( B/ Q
output mcasp_ahclkr,# K/ W5 d3 Y+ G
output mcasp_aclkr,/ s% |2 T# A) q" A: J/ W
output axr1,
4 A7 q# ]4 L9 K6 v# N assign mcasp_afsr = mcasp_afsx;5 v" r8 B% r' F) n( v6 E3 S
assign mcasp_aclkr = mcasp_aclkx;2 N: G8 S( W0 H2 k5 C5 f$ Y
assign mcasp_ahclkr = mcasp_ahclkx;
A" o+ j5 G* a1 H! i0 E; f3 Vassign axr1 = axr0; - |2 q1 n2 M) J( Z( G G1 q
" |0 ]+ f3 j# D* y; x9 d7 F7 b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( s# {5 R5 W; Q+ k) x
static void McASPI2SConfigure(void)$ w. n3 @% L0 u9 m* f
{
/ `4 ~2 n! R& P5 s/ @- L: i2 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ g7 N; T: ?0 ?$ LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# I/ O S- d/ S0 z% u+ a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! V7 S! j1 l! q( X7 ]* ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( r7 b* Q/ N z- ?$ |$ d# y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ n% X9 S S; f7 J JMCASP_RX_MODE_DMA);
. V; G- y k# c* l- r1 d. rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; A2 [* a7 Q% H% p5 n3 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. X; u! q9 t8 j& v1 y. w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 m! t0 F3 x$ t# l8 e- T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( y1 u, E0 ^% W" v+ H, Q2 x/ s& ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( @6 w) Y) m$ E' |4 a8 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, h# o5 H- o O( K. M9 m; G+ x G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( A9 k8 v* n9 C+ L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' y+ S+ M: A' i2 n& h7 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; b5 ?& S6 N7 a W4 j0x00, 0xFF); /* configure the clock for transmitter */ p! S9 a" s0 p% m' S" N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 F8 M" M4 R) b* S, Y9 n9 t& i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' `3 K' K! b+ V1 d. s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 L" X) H1 x( ~$ E) f
0x00, 0xFF);
/ d$ J4 b$ ]! B0 b" `: ^5 P$ n* N* w; c/ [
/* Enable synchronization of RX and TX sections */ 7 F( V! O4 k9 ]5 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! g7 A7 S$ G, hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 q6 H' ^+ X6 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** u9 B; N1 p" q* N
** Set the serializers, Currently only one serializer is set as
! ?* C! X' M# a0 ^+ z: d# K7 `** transmitter and one serializer as receiver.; Z; q+ {, j4 W
*/& B8 Y7 {6 G, k0 n [. c1 k) I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" A5 s" G& B6 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 f0 u. i k x; R** Configure the McASP pins 0 p! N* p6 b7 P5 D: x
** Input - Frame Sync, Clock and Serializer Rx
]% d8 I# e5 f( M z** Output - Serializer Tx is connected to the input of the codec 1 f) M, O, w) r8 l
*/2 F( i! |3 z, q6 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 N& h6 n" N" Y: LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 q' e8 z8 C/ ?- E" n" rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 h- B3 D/ \$ C2 L| MCASP_PIN_ACLKX, F4 V: o- z' N; W7 x5 x
| MCASP_PIN_AHCLKX( u' p# n' ^2 x5 }; X9 x. i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 E% t& V/ C9 h3 M" }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 y' S5 d4 F1 s! W# s- }9 y
| MCASP_TX_CLKFAIL : @$ x6 J3 e% m- R& H
| MCASP_TX_SYNCERROR
7 O' E) e! T! o' R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 y. e' y9 b$ y A0 q- ^
| MCASP_RX_CLKFAIL
; {% g" m/ @7 o8 P0 c| MCASP_RX_SYNCERROR ) N- f# @' [! l7 k/ `
| MCASP_RX_OVERRUN);
, C9 {; O7 x4 b4 f} static void I2SDataTxRxActivate(void), q1 \3 R/ v3 R2 l. t" s
{7 q: l! o1 Q7 t! o$ f2 ~0 x. |" t5 L
/* Start the clocks */
) \" o$ J! W2 z7 C( D- wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 x3 N2 {2 F5 j; ~1 R% o+ m; L' HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 l& D9 H/ a' R' W3 m" R4 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% S4 t# ]4 f8 W4 y, b; h* DEDMA3_TRIG_MODE_EVENT);
7 a' A6 U& K& F/ N. LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 V) [' B9 ~1 O% \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 v: ?% h/ q, k6 C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! W+ o8 L, `" |0 ?, H+ g9 c- aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. t/ O$ }" q+ k% Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 j. e6 H! Z$ ?5 k# SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! H5 i' u* O) k" b; o! tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 |1 \& W- i, x8 N, I
} * N$ e3 Z% G) C e6 A2 i5 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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