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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( e" ^5 k7 {. |* F0 y% Y! w0 G
input mcasp_ahclkx,
; q' J8 _, h2 Y Q/ d6 `; G) Zinput mcasp_aclkx,
: ^0 X O7 @9 X& }input axr0,
- p. n1 ~; h1 g% Y" Z
p/ c1 U. s- k2 b5 poutput mcasp_afsr,; H8 [* g. u* q, t/ N
output mcasp_ahclkr,. p5 r! H. W+ z7 y7 M
output mcasp_aclkr,9 g; o6 y; q. i7 O$ q0 P
output axr1,
; B+ l/ u4 }9 Y6 Q3 E4 Z assign mcasp_afsr = mcasp_afsx;8 i0 M0 d5 {0 o4 n) L h4 l! E
assign mcasp_aclkr = mcasp_aclkx;
! S* N1 J3 a. R* R7 Kassign mcasp_ahclkr = mcasp_ahclkx;
D! B$ j5 W& h% Q4 r% Kassign axr1 = axr0; . C* [2 W" l: w, Y, Y% c
- W9 E- V2 G$ f/ K6 K5 z1 } m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! Z% S& X, o" \/ t0 r
static void McASPI2SConfigure(void)
' V5 l* u4 ?$ ]2 I: K& e- k. q{
1 B1 ?8 l5 M, A: uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& X& p5 s! D0 [3 A" ]& {% WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. `, [0 O# C7 a" b2 D+ E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' Y8 c z, J8 O5 D! d5 J# }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* p6 f( ~9 e, h: `) O% Y4 A. Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ~& x( l! R; Q" k, ~MCASP_RX_MODE_DMA);
, b' g7 i6 U' x1 H# ~9 e5 _* OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. Y# {" e! l! L% `3 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- F; _& x: h$ W: c9 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; l9 s! V# q5 Y. VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 m% @! p' O+ \ m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 P; J, E4 d, R' u4 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- n; ^- s, R% u3 W8 ^/ |. {# QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 A2 o$ j& x7 o4 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& q- e8 h' ]8 c& {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 g1 o* x/ s7 F) c# d1 t
0x00, 0xFF); /* configure the clock for transmitter */; h+ n- n0 V" A8 p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ ~' T) }: _# J$ q. T% c" RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " c* Z' a' L- c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 p8 Y/ I, n4 }* _& e" \
0x00, 0xFF);) |/ y3 b, a* ?
- X2 h# L5 G1 U7 w6 I3 v% W
/* Enable synchronization of RX and TX sections */
5 F9 _( }) X8 K6 o2 f( v7 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& Y( k7 [2 y# HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* @) ]1 y8 C' \/ t/ bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ C3 l1 B9 i8 k# }7 }5 C
** Set the serializers, Currently only one serializer is set as
( q3 y3 x/ C* m7 ?7 h- w- e** transmitter and one serializer as receiver.' \1 c3 m' K1 V9 M/ h6 d, _
*/! ^4 _# `/ m# d- `9 s6 h- ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 ^; F: u% y2 C7 x: _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 u+ | F! K- E( g
** Configure the McASP pins
& t/ \2 e% W! M# i4 x$ L. z3 q** Input - Frame Sync, Clock and Serializer Rx
4 p+ F# o% e7 M6 D0 }4 M** Output - Serializer Tx is connected to the input of the codec
& T- u% v% f/ | f' i*/
( N9 F0 w1 i& f! W. V. [6 Q( QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: a9 h/ s8 z! E, e! C% Y; k/ m7 g' Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' v/ d7 ^$ C" r3 {' o+ M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 s* C+ g5 e1 v7 v0 r# a1 }4 V| MCASP_PIN_ACLKX! ?* |1 L, ?# |; g( j, @
| MCASP_PIN_AHCLKX3 L' q, t- b0 |& i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ]; Q: D3 p% f; U6 M' g0 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) w! g. M! M: ?: f2 e# ^: r+ ~/ O3 L| MCASP_TX_CLKFAIL ) m6 L, f7 v j% x$ J5 t: ]
| MCASP_TX_SYNCERROR
1 H( ]" p4 w7 \1 S7 \1 [0 H8 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 v: O0 O3 s& ^1 \: N4 M| MCASP_RX_CLKFAIL
) J/ ^" ^# V" p( c0 U+ Y| MCASP_RX_SYNCERROR & e% J% y: g# z/ E1 j9 a) W
| MCASP_RX_OVERRUN);
- C6 z$ R2 k6 Q7 L2 l( ~} static void I2SDataTxRxActivate(void)5 u7 @5 s/ t+ j/ N( N( i& g
{$ r- n* h4 I! w' T8 o/ X7 L4 _4 A
/* Start the clocks */
# Y8 z$ `- E7 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 r8 @) M! G& x3 H# `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 F. U" @9 a" [7 w$ {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- o, o' Q1 z! M4 w! w
EDMA3_TRIG_MODE_EVENT);
7 n% H: k3 S" b* z# F! }! H t' L$ F. I8 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* e# v# c% K! m8 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; K' F. b9 s0 n" n# K, |0 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! M' p9 a& c+ J5 |. Q4 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) v4 v- k ]; N* B0 h V8 V. Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 m* C5 }2 Z% w: d) b* f* N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ y1 r% {. [; r# A9 Y1 {( `2 \( HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ c" v1 `) x$ U! [. U9 A; ?}
% l% R. T' ~! ~, `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & I5 I! i& {8 S' ~6 g1 ^
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