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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 P) N0 S F% e0 A/ {2 {8 y. l! Tinput mcasp_ahclkx,4 x/ B+ ]% A5 b& a
input mcasp_aclkx,% F/ p' m) e; @$ g) q2 V. l
input axr0,* H* a6 k# w3 `. K: Z: ~* n
/ i( l8 }! G" L- w( s) Eoutput mcasp_afsr,6 n( j1 s9 Q- x* Y, {8 A- G% A
output mcasp_ahclkr,
: P# d# o) \# u$ G2 Koutput mcasp_aclkr,' C+ r b6 J' g6 |3 J
output axr1,
" H4 b0 w1 A1 d8 S+ T3 F assign mcasp_afsr = mcasp_afsx;/ [$ `4 z5 f4 C% s
assign mcasp_aclkr = mcasp_aclkx;9 M3 G+ c Q% t. a: o
assign mcasp_ahclkr = mcasp_ahclkx;
* ?; M+ r5 w4 [assign axr1 = axr0; + U+ b, f! b6 f& F: ]
# }* F8 s2 G+ `6 w; I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ m: V" \, U7 e2 ~
static void McASPI2SConfigure(void)0 h; `% v- `5 `: I* V' C5 m
{) _8 f/ v/ Z! K. ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 A v) _1 R8 l+ K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 c2 {0 v* C0 \0 _4 T3 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 U0 \8 H& R( X' }1 [( oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 }" _" _" }* AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 r, @# R& E) EMCASP_RX_MODE_DMA);" ` R. D7 |9 k0 ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& h t, W/ K' N7 u( BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, d) v% i g- q5 d+ D4 I" }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 c+ p; v2 P6 i( |& I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 m& @3 ?( H' t- Y% E) D r4 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, c) a( K# V+ l6 N- o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 j l) C" {- u. C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% [, s. r, n& X5 G6 s# CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( r9 w. o. Y0 E" ~3 _; L" r& vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 t) T! }7 m7 z3 e* r2 _' @
0x00, 0xFF); /* configure the clock for transmitter */1 K6 @* I& u+ P- j! N" n5 x: H) z L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% ^0 D8 t7 W# I; n" N3 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( ]( V& b7 v6 [; b9 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* ?, A) I+ T, |0 J# a( }" R0x00, 0xFF);: ?% I7 s) S) D# N f- g7 W$ I( K$ B( A
+ R! m+ v6 h0 J6 L
/* Enable synchronization of RX and TX sections */
' a- I( i8 x( _0 z% WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 e4 C# q* I7 i3 f1 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, h* g( C# J" E% D) w/ k( T* xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- I9 a" d/ {% Z: m' K% p2 F
** Set the serializers, Currently only one serializer is set as& a1 h6 f2 [; L* N& o% a( {
** transmitter and one serializer as receiver.$ x/ k! L! }6 h9 ~ z+ e7 w4 L
*/" _* G% s4 a/ x! K' T3 N% F3 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ Y5 P! ~: u0 A8 W# D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 O; A/ }5 g: c0 r2 s) F! v** Configure the McASP pins
9 t0 v3 r) _0 s0 `- K** Input - Frame Sync, Clock and Serializer Rx
+ a6 h# H b4 B# {** Output - Serializer Tx is connected to the input of the codec
% k- J- |( F$ u*/
4 ]. z9 g/ p/ n1 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 ^0 ^0 w! r' r. X0 w: t* h) UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& B' H4 u3 R& P/ ^* U: bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' M; e& L" Y, o2 f% }( q7 b/ ~| MCASP_PIN_ACLKX
' ]. i! V4 t$ i$ [* {| MCASP_PIN_AHCLKX
C% ]- ]" b8 q( || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 j9 ^7 h9 D! k' Y' s/ V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) z$ I; R& h( @7 b* x0 u2 O5 V& P
| MCASP_TX_CLKFAIL & y. g# S$ s' ]' U! C
| MCASP_TX_SYNCERROR
) r" ^) R$ U0 Y J5 X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# P) l+ L! Z; O F2 [| MCASP_RX_CLKFAIL. {& @( s2 @: h/ Q' G1 O
| MCASP_RX_SYNCERROR
4 g7 G! i, Q6 [# D4 J| MCASP_RX_OVERRUN);
! n9 i! d8 ]' F- |6 c. U) W7 @- G9 ~} static void I2SDataTxRxActivate(void)4 z5 {7 }7 w: W, F+ _6 d
{
5 K0 L+ L5 y: H/ s! u5 \( ^% s( D/* Start the clocks */" G4 b H/ d$ E; ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& v3 x1 B1 }& [: c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- z! V8 m# ]& k, k: m6 I' t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 b9 d$ V6 @9 h+ C7 UEDMA3_TRIG_MODE_EVENT);
0 X; a. W Y& G. `1 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) W% H! o: R3 V& w2 q; y, u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& s) c+ y7 a9 F5 g0 p4 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( ^( v$ h3 S5 u) F) KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ \& d4 @# j; f' ~2 Z e3 s# awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 ^; K4 \/ `8 K$ O& m* C5 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ R0 E" v! Q; ?6 c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% u0 p3 E: K! T) x0 b) D- O' K' n' s}
; v+ U$ g' Z5 I+ c' ]6 L- E7 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * l. d* Z6 }( d3 S: i
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