|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' B0 s# s+ J+ n' ~$ }- uinput mcasp_ahclkx,
5 A! ^% ]- q! g& T% |( Linput mcasp_aclkx,
! }- d) E! X2 sinput axr0,5 [ c F% H6 E, |: b. K' T2 H- Q+ ]
: S9 E( e9 j, u. r8 koutput mcasp_afsr,% |. W1 E- N. e# v5 |) r
output mcasp_ahclkr,
* N. S& Q9 O/ d' p youtput mcasp_aclkr,
! s1 i! Y" o% ]8 E2 j, E# d" Xoutput axr1,8 h( b5 f2 h6 _# H8 H; ]1 V
assign mcasp_afsr = mcasp_afsx;
3 U: {: Y- v6 _! fassign mcasp_aclkr = mcasp_aclkx;6 i% A$ E, J7 d- Y9 I, Y- w
assign mcasp_ahclkr = mcasp_ahclkx;
2 G2 `9 P( j8 K0 [, Tassign axr1 = axr0;
, B q2 w$ E# d/ Q' u2 m/ v' A+ Q# a, M, n5 G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 [* r# i- }4 Z1 K0 y
static void McASPI2SConfigure(void)
* A5 Q1 E3 k+ B{; \+ [! U& C; P) X5 b- e; i8 r' }, P; K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 C5 ^- B5 {" x, k! R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; x ?) }9 a3 Q! M* S9 {9 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 u& p0 G6 d4 d8 C0 qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 S- j% W; D9 b+ ^. F+ `# N7 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ y5 J, f1 t& O6 B/ p
MCASP_RX_MODE_DMA);- O7 q( x8 g* B9 p. M0 B* q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! R- `: ?% ?7 ^: I- Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 @" F# w5 y# G; G6 J& t, _5 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) X4 r2 r% @0 D: s; A9 \# F3 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 ~3 j6 ^6 {/ V# A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
U& \" I4 U/ IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, X/ A( K* ?" |9 h& R6 c; c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 ~/ \" `7 p5 Z5 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 W4 z- M0 k0 n- T: \7 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* Q. m/ M5 h( d9 t" h+ a' @; I0x00, 0xFF); /* configure the clock for transmitter */
. F' z2 G9 q \" FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 k1 M6 v; v" U( MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; s0 b0 V9 D8 a9 x4 u# j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! C5 u' r+ e7 t3 A0x00, 0xFF);
3 @5 g4 S7 l6 R& |0 W
2 K# M% u+ k6 `, N( C$ a% |4 V/* Enable synchronization of RX and TX sections */
2 j/ {6 h& w8 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 }8 `) p4 | ]* y1 W7 X% \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 L3 \6 ]# Z, ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' J+ m3 G: O5 y! x% `+ B" c3 A
** Set the serializers, Currently only one serializer is set as- w/ W5 k6 O; \) l+ X3 T
** transmitter and one serializer as receiver.
2 k- B4 \0 C5 A( j" I4 |*/% N3 f7 L- B+ M0 _. X/ n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ q1 n! w9 `; ]1 N" uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ J0 o. ]* t! ~, z/ c( u; y
** Configure the McASP pins
+ ?. z+ y) ~6 q1 L, i** Input - Frame Sync, Clock and Serializer Rx
+ k0 W, y% U2 T6 M- H% \' J** Output - Serializer Tx is connected to the input of the codec
" V$ T/ G7 F3 \5 \5 W8 ?*/# z! \; [# r0 d6 L% W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) s5 d7 ^1 f, hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 G5 U/ k1 z8 R) NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ g" @9 P2 y; \$ ^7 i; T2 i
| MCASP_PIN_ACLKX
9 T' ^& ]! J/ i6 ?6 g7 E- A# y, w| MCASP_PIN_AHCLKX7 X- O r" }& ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( h+ }) W0 ^* Y( ~$ T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 F. i5 {& x% a; V3 ~! `( \' k| MCASP_TX_CLKFAIL : d0 `; g3 g* O
| MCASP_TX_SYNCERROR/ x# ]+ H7 v8 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( V9 L: B% p# d5 P# R0 s| MCASP_RX_CLKFAIL
. U5 @7 X5 {, F6 Q2 M| MCASP_RX_SYNCERROR
; W5 x8 y% l, C9 H* S T9 S- e6 ]| MCASP_RX_OVERRUN);
9 o+ D6 p$ S6 V! ^} static void I2SDataTxRxActivate(void)5 \+ k# x9 v. z
{0 y% x. Y, s- b: j, I2 e
/* Start the clocks */4 z6 t, W5 v' Q! @8 D9 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! ^; ?* P- }& R( d9 g4 C% cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% P/ L& _( t6 ?" B8 y; u5 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) O5 V: y: u; @- @
EDMA3_TRIG_MODE_EVENT);- ?6 ?7 O% r! e; ?5 d! x" l* Q5 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 T2 [8 C: U6 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( ~8 N7 c% s9 Q' j' J" IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! q3 x# t! x* ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 k6 g. Q$ c- x; Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 R, G& \" q4 V4 k1 _1 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( b; N t3 R8 S* Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ u0 ]3 N1 i8 |* w+ U4 h' n+ x
} , L8 p5 ]6 q4 G& M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ a- P0 O! n# \. b0 V$ D% K; r |