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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: G3 h! V; w7 ~: B. Kinput mcasp_ahclkx,
3 P4 A5 f; w; G' w( Y: Tinput mcasp_aclkx,
' ~3 s$ M9 }5 X' j+ Hinput axr0,. N# |$ J1 t" a8 |8 {; p
8 r' y9 F6 N/ P8 K
output mcasp_afsr,, W4 `# f' v. U, o
output mcasp_ahclkr,
4 r6 C/ m4 q2 D/ J5 {output mcasp_aclkr,
! V7 l* N2 W3 E& v, @output axr1,* _3 a `) s. d* [1 t
assign mcasp_afsr = mcasp_afsx;4 B- J7 @* g+ U
assign mcasp_aclkr = mcasp_aclkx;" f# `4 R1 l# l' v9 R
assign mcasp_ahclkr = mcasp_ahclkx;% y: y1 e4 Q, ]3 J, s
assign axr1 = axr0; 5 |0 ]7 L* J6 [& V. l. s2 X
3 h+ ?6 V$ s6 d- \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; V S+ \1 R3 ~) [! \. `
static void McASPI2SConfigure(void)5 b6 U/ u5 n) ?/ h7 i& ` A% a: E7 J
{$ Y0 B" \, [( N, P, C5 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: A" t/ r: T* Q' v; }* I1 ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ |+ }! V0 X1 x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& D$ J5 g0 E0 l# zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) }) [& X k- z) W9 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 I! w& z) K/ W1 H% \* `MCASP_RX_MODE_DMA);2 O6 ]1 W5 a/ U( y, K9 m. \7 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 A; j. T; H) D, f$ r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
^! L2 g; a- Z/ Y% I7 ]" UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: P! u4 v# J9 f. P/ \! fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* G/ `5 U5 l, [! d$ b% O: J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ [7 N& T& J! y# u- h1 p7 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) C; M5 p& f8 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' A9 p6 ^3 p" q* M# yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) t/ V5 r, B1 |/ D. U' ]; H* x/ vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% u7 y, M. v3 u; r: R9 O0x00, 0xFF); /* configure the clock for transmitter */
. p8 F5 U* C q, {1 A) gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 Y0 ~ f2 L4 s7 \3 z0 f) _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 z' [1 ~1 P& t' S0 t( [) IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- {4 S# Q C/ p
0x00, 0xFF);) }0 ?! S/ L2 f! H3 A9 S' l8 l# ?
$ Y2 {+ ~3 v4 o; _8 [/* Enable synchronization of RX and TX sections */ 6 Q* s5 J) m: P# |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% s6 g1 \, }" z7 e- f! D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 p1 t( r7 {- Z! S6 h$ s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' D Z) F% W8 Z) q( ~& G7 v. f0 T3 T
** Set the serializers, Currently only one serializer is set as
R: ^3 f; z+ o0 S+ w4 U** transmitter and one serializer as receiver.
. X. y( `3 ~, x9 I& h4 {*/9 ~/ S6 W# \; {, m: i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: F/ U+ A5 m& X, MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 h. C2 g$ u3 Z9 G3 b** Configure the McASP pins 1 V$ c6 L6 N; O; p/ O
** Input - Frame Sync, Clock and Serializer Rx# U8 A0 H" q9 I$ j4 f
** Output - Serializer Tx is connected to the input of the codec 6 o" m1 |# L/ r$ S1 q+ V
*/
4 X! j2 i% Y( A# `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. ^/ A% Y! V( B3 D: V5 y5 YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ f9 p: Z& ?6 q# z. f5 w E9 k6 b; _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 Y' ]9 d1 J. N$ F5 ~0 n2 Q& K| MCASP_PIN_ACLKX
/ { v, }5 Q/ [: u| MCASP_PIN_AHCLKX; K4 Q1 \2 _- t: }( R! P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& z6 Y" L& o! S2 g" dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& j5 b+ z' @7 x7 j3 R. F! G( n' @| MCASP_TX_CLKFAIL 5 N8 E$ o. x9 D# n' F& @3 K
| MCASP_TX_SYNCERROR
6 x1 r [/ Q" ~. g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ c. [% d; I% p, v' q# x4 A0 E| MCASP_RX_CLKFAIL- q# O3 N4 m q+ {7 r; B
| MCASP_RX_SYNCERROR
% x" i% G9 u$ I4 i3 G9 C1 w) || MCASP_RX_OVERRUN);
! Q3 b6 [; g& u) g- A/ M0 ]} static void I2SDataTxRxActivate(void)
% ~" r& H' V; [$ s$ l{
4 q' w( g9 q8 }/* Start the clocks */
8 @, `% \6 v9 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 A# g9 T, o& C, N/ h+ O9 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: X# D( _4 d0 v+ k O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# o2 d1 ^% A7 d' K) xEDMA3_TRIG_MODE_EVENT);
: `/ I2 a) A% F | `- oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 }1 E0 X3 @( ~/ P9 X( ]% _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// ?5 x: {+ f- A6 a% s( Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. i, ]! V' |: d$ T* b' w; IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% N* S8 C/ V5 M7 W( r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) N. Z* d- S6 L: pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ Q0 s/ ^. e: U" g! n! S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 \! X4 P( D3 C
} % q$ b. t. y1 ?: |& W# X: m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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