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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ E1 T! t/ d* J2 n# \input mcasp_ahclkx,4 J) s7 h8 e7 a5 B p
input mcasp_aclkx,$ ]/ G1 v7 f; {/ i. g
input axr0,! g" P0 x& w9 r. N6 V' V: \: B3 |4 M
2 T* S. J$ X& ?. |! Foutput mcasp_afsr,
2 v6 q9 u" _, W& j; t/ z/ boutput mcasp_ahclkr,
! I) L# Z" P' V% ?, B# o+ x9 m2 K+ _+ J' Noutput mcasp_aclkr,
3 M! R! f: F( b: foutput axr1,
' Y" N: t6 G2 X7 H- \ assign mcasp_afsr = mcasp_afsx;* _" p: W$ {5 P" u
assign mcasp_aclkr = mcasp_aclkx;0 ?! P, }; y3 T' f6 k
assign mcasp_ahclkr = mcasp_ahclkx;2 L# n# a/ k% q+ n7 x m
assign axr1 = axr0; 6 g, H& ]: e q8 h9 u1 s4 Y5 r
, B+ P0 z6 Y4 v( W1 x6 I8 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ l, a4 y" S- m% j5 @
static void McASPI2SConfigure(void)
1 _5 \% \) n! Q0 P{
1 D% r; S: k4 T9 W1 A2 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);( J! L/ ]/ H* i/ D$ ~ e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% S+ O a) G+ \5 _" r6 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& u7 M! F' h' ^8 g9 b+ F# JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' Z ?7 v7 |1 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; P/ D0 o p5 v) `- I! C7 ^. N+ f) f
MCASP_RX_MODE_DMA);. x$ U9 I! ]0 \( K& p* X" x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ~9 r4 l! @2 i! v( Q) ~( Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ Z5 Z" n" [5 M8 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 s6 n2 V5 q% ?$ j) [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 D! d! U4 ~! R* k* ]+ JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! E: |3 i; L! n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 S+ m6 d0 V: C: u+ \' X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* F: I7 L7 c7 D: ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 _9 r4 R# r: c) p1 T [, r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ p6 w: y0 o' P$ T6 @) w( v; e
0x00, 0xFF); /* configure the clock for transmitter */
& I2 n/ Z n5 B1 G6 b3 S0 p( S" qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) M6 `7 k0 k9 W2 p# n% f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 K3 Y, S% U* t* ?& A z7 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 d% F) g4 K. }( {: R0x00, 0xFF);
9 Y$ _! i# s, x' S7 M( H/ x$ F9 `9 X8 |1 ]( S
/* Enable synchronization of RX and TX sections */
( v9 T4 o& \: A& rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 Y# c7 V) B- G, k% o/ _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 y) @% d& Z1 J$ LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 b6 {% b7 F. v! d** Set the serializers, Currently only one serializer is set as# Y; S$ h2 k9 V# q4 V
** transmitter and one serializer as receiver.$ z! b5 } n3 q6 J& ]9 V5 n, p' `
*/7 H [5 {& a- b/ t* k5 j* B+ _( {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# j7 t3 N- } g' }; w; l, N2 h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' Z; {* o( }0 [) s0 y: K" L
** Configure the McASP pins
' H' {' t7 |" P; B5 ^** Input - Frame Sync, Clock and Serializer Rx; J& I% o; d# j8 l2 E0 c5 c
** Output - Serializer Tx is connected to the input of the codec ; v9 d& v( ^- F- G- q6 d- o
*/1 x% e- ?" H: j, {/ g6 j3 r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 u4 g z) G5 q, F0 @& JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
c1 L+ ]# T0 j$ bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 o2 F7 i% X/ b% \0 x8 u* A
| MCASP_PIN_ACLKX
2 I: C* ~' |! d n: b| MCASP_PIN_AHCLKX
/ W: y* x% _+ r1 ^1 [8 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 W$ |9 M1 `0 E* GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % r6 |5 t6 V: {& h
| MCASP_TX_CLKFAIL
1 F" D0 k/ V0 f2 u# [| MCASP_TX_SYNCERROR
M+ d% E" @% @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 P+ C- H# U; O) V1 G* t3 \# V4 t3 R6 L| MCASP_RX_CLKFAIL: l: |! D5 P7 a5 [* M) n
| MCASP_RX_SYNCERROR
4 L6 {- ]4 l4 l4 q6 P" ^8 `( r| MCASP_RX_OVERRUN);- z3 i0 B' D9 U9 m/ g# n& A0 Z6 i5 n
} static void I2SDataTxRxActivate(void)8 N: Y" k5 f# M9 u- F9 j6 L
{
* m+ d6 N( r4 v8 K' z; [/* Start the clocks */ W9 T+ D' g$ g; d+ N( n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* L& h' u5 p- V9 m/ X1 U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ k( w$ t& I# m8 U1 H( uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 V- A3 ^0 o$ V) j# A8 n4 }EDMA3_TRIG_MODE_EVENT);" v# a& ]! p& g" U9 y5 e0 E3 C; g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 l- m7 \( ^3 U( ^+ R. K! Q% [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 K2 M) z) C4 s- lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 A, Z1 l: o h1 P4 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: ~0 T* }& J" N* J" Z/ r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) \/ L7 _ y0 P7 ]. O- TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' d5 p0 a' m2 v5 T8 Z9 P! d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 b# _4 n1 E/ @3 q9 Q2 k0 r% j} ( Z) f3 V8 c- _5 o, r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & U e5 @% }$ J1 O
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