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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* L/ D/ \; x2 a& [input mcasp_ahclkx,- G1 g, y$ B" c
input mcasp_aclkx,! P' i$ m& l/ m1 w5 {$ U
input axr0,; G: x; n) }: x w
x: Z6 S8 B0 R. u& ^) \& Woutput mcasp_afsr,0 y: j6 k5 V, z2 h
output mcasp_ahclkr,! {& K6 b. z9 `( d5 D h- B
output mcasp_aclkr,# O/ s& `1 z: w( m
output axr1,
# }7 o2 ?/ d- ~9 i; [- s6 c7 z assign mcasp_afsr = mcasp_afsx;0 s, R$ T" t* ]% [+ h
assign mcasp_aclkr = mcasp_aclkx;( g- q# A9 _4 X6 Q! [
assign mcasp_ahclkr = mcasp_ahclkx;( u/ H7 A# Q% [, j: s9 L
assign axr1 = axr0;
, c, \ A# q9 r0 o+ s i. j5 t$ Q* c- e; T) ^4 W4 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* o& I) O! Y) E/ m8 rstatic void McASPI2SConfigure(void)
1 M* u& n, {- q9 ^7 Z _8 a- f' D{
8 I6 G& P: R! |" H0 s+ \* G. Y$ iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 `% {8 e$ c' w/ `& B6 Q' J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 Z1 L2 y0 Y, K& f( _/ Z- ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, P& h8 C' ]3 n2 c4 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- O" g! J# _/ N, R. y3 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 @# o+ M9 b- j# y$ x/ h" jMCASP_RX_MODE_DMA);* g; B; V+ @1 E2 W4 W Q# I' w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," T1 z# `+ Y' ?) T; x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// \2 ]/ ~, i3 j5 `9 ]4 e. k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( B. M- W' ^6 R4 AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 M/ c+ g, O. Y" A4 j* W% f5 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- i' t& d/ L6 O# t7 P. OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- H2 ~& j/ K% \2 l3 D6 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 w( F; p ^: i4 l) w k2 [. C/ g* PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! `$ {: Y8 }/ e- l$ V [& hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. F' c* u8 o) I4 s4 O1 c2 n1 W
0x00, 0xFF); /* configure the clock for transmitter */: }( y: l: {* P9 z7 ~+ ?6 O; l# ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. \' k4 u+ s6 l9 ]. P/ `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* H) b, y/ P/ c- x# TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 U0 k. C$ Z& C; s! k0x00, 0xFF);
+ ?. M) P4 W- L
& ^* i8 b4 k5 l' c& D- ?0 d/* Enable synchronization of RX and TX sections */ # O H6 r# G* p! p- _# i9 W3 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# f% I' O/ [, \4 h8 }% I+ M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 j" T) c2 }( z. l# M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& `5 l$ }) _% l5 K9 ]
** Set the serializers, Currently only one serializer is set as
, c. j3 l. J7 f9 ^9 ` @** transmitter and one serializer as receiver.) N# _: a$ [% E) K
*/; Z- r* F& `4 i8 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ X# A6 f$ V5 i$ o' r- |9 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' M7 \7 M: R, z9 F3 Y
** Configure the McASP pins 5 H3 N; j8 C3 D" }3 K0 g6 p2 P1 s+ b
** Input - Frame Sync, Clock and Serializer Rx
" ?8 _; K5 E6 P3 E: Q. v** Output - Serializer Tx is connected to the input of the codec 9 n/ i9 D( i& h( D# k( j
*/3 C; z" n/ m1 `7 q. D- H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 B" D3 y, z4 ?! ]3 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% X' b' v) `' fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' }3 y G, W9 M6 D
| MCASP_PIN_ACLKX
r# }( h2 z" W1 z$ ~| MCASP_PIN_AHCLKX
2 N% {1 F, Y5 B h' Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- t$ g) K2 L4 a# U" A3 Z' E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 B& A6 q1 j/ g/ K0 p& y| MCASP_TX_CLKFAIL / O# W9 k# y; U8 @3 ^
| MCASP_TX_SYNCERROR3 g* C& B7 i( D! K1 o: x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ Z+ v( F9 W- l; X7 s! y| MCASP_RX_CLKFAIL
8 d* D( V* w! r- M| MCASP_RX_SYNCERROR
+ ~0 d; u% e2 K% j! J| MCASP_RX_OVERRUN);7 _7 f7 E3 z8 \/ S; i! q
} static void I2SDataTxRxActivate(void)" U0 s) A' J: H9 q M3 B, z
{
S/ u4 L5 H) N7 N5 R/* Start the clocks */
+ Q" J. L- t! [- Q eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ d, p# r5 k E7 ]- N8 j8 l. S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 h- B3 m# K oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 K/ j U6 P8 l8 x1 f7 y4 fEDMA3_TRIG_MODE_EVENT);4 m$ }) p& B) ^2 \* l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 z3 h) Z( ^& q+ N# x/ E+ y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 F" \* l( d bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: m! d. _1 P) Q) [& Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 j! ~3 Q2 W/ `3 n0 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" a3 z9 ^# l* ~. I- z5 g. b. G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 b7 v C! D, ^- E" ~% |! oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 }& k( ^/ S- d}
' y- ]3 t: d( J/ E( C1 V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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