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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 x0 P C0 g) ?/ e* j4 k: z
input mcasp_ahclkx,$ d& j) t: v6 T% h! k [- n' n
input mcasp_aclkx,
, Q3 F; I2 N* x! C0 W( q qinput axr0,! }& E+ Y) @: ~; b
& g, ~# x. G/ E* noutput mcasp_afsr,
9 u7 f* @, J, ^# C) L8 zoutput mcasp_ahclkr,, C x2 G2 d' ~, ?& c
output mcasp_aclkr,
0 b8 K. H$ w$ {& m' Qoutput axr1,
, i! N+ m$ N# d& x# v assign mcasp_afsr = mcasp_afsx;0 h6 o' }" }; Y0 t$ V- S
assign mcasp_aclkr = mcasp_aclkx;. O( X" z" \- N6 M
assign mcasp_ahclkr = mcasp_ahclkx;' n$ v. H/ Q5 h
assign axr1 = axr0; . J3 ]4 h! e5 \
) [+ z" C e$ k% x6 E' f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ Y' v3 M$ m! ~8 Bstatic void McASPI2SConfigure(void)0 K% O, p* m; x* d/ P1 N4 l9 P; E
{
/ i7 `7 b% | tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& g2 x* @9 e$ k* YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ K, t, b/ R) N( `1 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 I9 r# t" d7 h6 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 T# N8 e" s- k* k. S t9 `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 o7 B& s6 V/ Q; i- g
MCASP_RX_MODE_DMA);
- I! t- _0 u2 W( A5 y* m4 f' D9 m+ GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: q% `2 v ^& ^" _* |8 I0 A# QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" y2 D1 {4 F& T6 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 e' g2 f" s9 @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) @: _. A4 D: [! P9 E0 B: \- N3 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 _6 L6 c m% I& D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- m0 i, ]) V7 D+ n5 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, ]5 f$ P) M; ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 a t$ u$ |: e9 ]7 q$ O; }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. u1 E( ? O' t: K1 ]; h% ?
0x00, 0xFF); /* configure the clock for transmitter */& `8 f7 R( D$ z" Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 |( B) \* }0 N( \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 o, z4 k/ V/ r. K, f6 r" eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, N: r7 O0 B3 ^, K1 G: k$ A) E0 ~0x00, 0xFF);
1 _& F" Y) }- P/ M" _1 V
3 W* V$ J1 R0 E" w$ Z b/* Enable synchronization of RX and TX sections */ # N W1 J2 R7 O1 g$ c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 _0 b5 ^0 U! hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 o, z8 }7 l5 H- J L! ~- }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 z m4 | I+ P+ h3 a2 H# Z
** Set the serializers, Currently only one serializer is set as& Q T! d4 f) I. E5 Z2 U' Y7 u
** transmitter and one serializer as receiver.
: V) H( G! O0 q* ?- S0 k*/
3 K6 E2 x( H; `5 e* w% n0 M" }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" D- m5 f# R5 ]7 p; P8 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) g+ x; a9 e# t7 H" f; r, V* q9 x** Configure the McASP pins
A9 _. ^# V9 Q2 A( E** Input - Frame Sync, Clock and Serializer Rx; Q1 L+ r/ s, c+ M3 h
** Output - Serializer Tx is connected to the input of the codec
& U( |2 r- v6 U/ N2 P; u$ F, {*/' |1 W3 i& ?, q- D8 p+ I8 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( N4 _# n4 E, _$ J" q3 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 w- i& S4 t' O. W Q1 y) fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 c. @6 h; D) `
| MCASP_PIN_ACLKX
$ O; q o" E4 @/ V| MCASP_PIN_AHCLKX
/ L( X" t0 i2 ?( P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& R: |/ j( K& O) B$ `- S9 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ k0 d: Z" a, I5 d| MCASP_TX_CLKFAIL 8 b! }2 j0 B1 w9 Y* X
| MCASP_TX_SYNCERROR
# v, I& u1 e; K' }8 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 u( I( g% N! q( U4 ^- t( B% G# ?# w| MCASP_RX_CLKFAIL: z* w) O7 C8 Y/ m7 O6 J! d' R
| MCASP_RX_SYNCERROR
, I+ \3 Y) t6 T* V| MCASP_RX_OVERRUN);+ E) r4 B$ K4 r3 L5 c( x
} static void I2SDataTxRxActivate(void) Q7 z/ n) t4 Z& h `3 W
{
5 p9 c! d/ H1 r3 c/* Start the clocks */
6 D- z/ ~( A! |0 IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- _' N2 R+ _$ T$ F2 D# hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ^% o0 _4 X& Z3 u f+ G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; f! Y" v; f+ u vEDMA3_TRIG_MODE_EVENT);
: g( ~1 m( J% ?# x7 }1 U) fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 w! D( y% G7 N* I* p5 b8 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 t( K7 q( o5 b( {7 h$ J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
U/ h. Y: y- B" t: b' fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 M3 I1 Z. s. c# m3 N( C) Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 y/ T% B0 A) ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 n0 P# n' r, d( b, T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: S, y3 S) F4 q: M( X* A9 F" f}
. u9 U6 w" I4 z% m5 Q2 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 V% K* H8 G x- v% O
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