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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* Q1 ^* {7 a- Y0 Qinput mcasp_ahclkx,8 Q; ]3 C: M; U7 @- o4 s7 c+ o
input mcasp_aclkx,
* K0 L! G, O2 n" v# d+ Finput axr0,
. [* A' s/ A4 V/ _' }1 Y5 D4 H# `5 H, W0 Z& ?+ ]/ ^
output mcasp_afsr,
, o' v, H: a# n9 O }; O$ j3 Ioutput mcasp_ahclkr,
! l4 W' H. x$ [! V5 Foutput mcasp_aclkr,
5 l* Q6 s3 H* [0 Uoutput axr1,+ r9 c" x8 S) ]% l& {$ Q
assign mcasp_afsr = mcasp_afsx;* s% X$ R+ @* p0 _5 N" J
assign mcasp_aclkr = mcasp_aclkx;( O6 ~( W' \! f& X0 r7 [4 \
assign mcasp_ahclkr = mcasp_ahclkx;: E7 i# t& |% w1 V) D$ C: A5 x
assign axr1 = axr0; 2 r; ~, M) x' D6 B1 \+ s
3 X( q$ U' v" f# e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, Z' @+ ]3 I8 U' `$ cstatic void McASPI2SConfigure(void)+ f1 F$ W4 J/ z
{
1 t4 Y% X8 x3 f! ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 N# n& a% r8 f. S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 P, T$ r) M U) A1 f6 x/ ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 r8 }7 }4 @% y" R. \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 ?8 I- L/ r; g, f% {: h0 W9 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! l3 o8 f( K4 w# k5 x) Y$ ]7 S
MCASP_RX_MODE_DMA);' r9 e/ E, n8 I, p7 a: U. R+ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 l# t, X* x0 x/ p h' P7 d: HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! J! z+ C# d6 [% ?6 D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- i$ g T2 k, t) Z, j8 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ K" D/ b1 _5 a, FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! U( c1 G* i4 ~, W1 m: ~" ]* w! GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 K9 M$ m, T& P7 q; P& LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ y& Y) ]' [- S1 ]6 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 X7 ~, F* h# K6 M6 UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: _2 \9 b' ?$ |# A* G& u9 z
0x00, 0xFF); /* configure the clock for transmitter */
9 `1 d$ p4 K; G; m! _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
D3 S& S; _! c7 e( {9 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 L. a) @# u+ E$ S. `8 L: P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- ?! v( s+ v* K9 l" K2 @
0x00, 0xFF);. }0 h9 S8 E- F. _( T
. `6 F. J5 ], i1 H/* Enable synchronization of RX and TX sections */
" Q6 T- a' D& E7 `# L# G% IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- D7 q8 Q3 k( V' G% e4 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 c+ O9 b: }4 S' e2 s" HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
D w, F, H5 U9 ^& v( D/ l5 d** Set the serializers, Currently only one serializer is set as, O+ D+ m) i$ P5 Z" W
** transmitter and one serializer as receiver.( j N: ?0 ^, z3 v! x
*/
- T% ~1 D% u+ ?* o5 Z: XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ D, o' y5 |% t, D7 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 {- |8 V* n% R, ^6 f6 r5 m
** Configure the McASP pins $ }' U: t, N& \- I2 O9 H1 R; d, G
** Input - Frame Sync, Clock and Serializer Rx+ A- Z s. _9 \4 F
** Output - Serializer Tx is connected to the input of the codec 7 P+ G2 }" F3 I/ f( Q
*/
3 }4 [% _# v1 O4 @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 f! O6 J! \/ l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 {; ]5 ^ h( ` C4 e+ v8 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; [/ M9 b3 T0 {4 S( a! L
| MCASP_PIN_ACLKX2 c. d3 N( C8 b9 U' d
| MCASP_PIN_AHCLKX
# W$ u& h6 c4 \: Q' z4 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& S( w N: Z) H! k7 `+ J1 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 w4 f9 Q5 d c5 @
| MCASP_TX_CLKFAIL
. V; u% e/ e" r9 ^( [% d| MCASP_TX_SYNCERROR# X( ^7 X5 Y* R' |; q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * h! a/ r, j1 G4 \3 a
| MCASP_RX_CLKFAIL8 z7 _2 k* D' T" P# j
| MCASP_RX_SYNCERROR 4 d$ ? u7 D, X3 K
| MCASP_RX_OVERRUN);
6 ^' h: s2 z' O7 v* P% V} static void I2SDataTxRxActivate(void)2 \# L7 F% L8 L6 Z, M! [. h4 V, L; |
{- X! Z( @( S# B
/* Start the clocks */
+ L$ k2 f- v9 ~+ b6 R A3 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! F+ [3 E3 G" ]4 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' K1 h$ o% T# X( w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- h7 G( r6 j+ c$ Y1 ~
EDMA3_TRIG_MODE_EVENT);( W6 g; u1 H/ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- t/ P: Z) q2 J4 `) I" y; I ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ Z0 P9 s+ k( G/ i' V. c4 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) ~6 T& S r1 {- s( ~# ~# e! ~* RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 n+ X$ k7 y, W3 I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 h- e# N+ x5 f7 n6 |( C M1 T' {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ i+ x: U. Z$ D; DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 B5 }% O3 Y& c' o+ f8 H
} & w( O* f% B7 C R( B0 B0 \6 \5 ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ `& Z, @ f; Q) w5 @ i7 v |