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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) t9 x2 r0 z' w( e& W/ k3 q- {" oinput mcasp_ahclkx,+ [& r' Y3 |* g" j
input mcasp_aclkx,
: f7 C3 m; M; P( F( ~6 Q! yinput axr0,7 }: ^4 B" ?1 D! ]) |! a, s2 L& ^
% l, J, X: \6 q1 A6 Coutput mcasp_afsr,% {! {! Y/ z9 L) q1 \" l" Z5 T# o
output mcasp_ahclkr,
/ ]% s7 N& l% ^0 V$ Moutput mcasp_aclkr,. j' d* `4 i) x# P; j
output axr1,4 c8 W2 ?* J# c* B
assign mcasp_afsr = mcasp_afsx;
e. I2 P( q6 x |0 {. Uassign mcasp_aclkr = mcasp_aclkx;
* B* U, c" z0 v* q3 b. t! Bassign mcasp_ahclkr = mcasp_ahclkx;. D9 f( [6 k4 k$ q1 ~7 b
assign axr1 = axr0; ( U1 m; g: Y) ~$ ]
4 I, n) g/ X' e" K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( c' w7 x: m1 D, A! I4 }
static void McASPI2SConfigure(void)
. I) a' }- ]: |" O6 {{$ {; F" s& C. g9 J3 o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! D. u8 G7 Q9 t% D& d% S$ o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 G! _5 w% b$ E5 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 ~" i2 i# Z& M* a% S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 x0 s Q# J5 v( P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ L4 Q+ s [0 x
MCASP_RX_MODE_DMA);; l1 l; {& p( x; Z( \, Q; z; U4 G9 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, z M& y+ r5 @) ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 F: Y6 ^! I% v. n% n( j2 m! _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 N7 E6 S0 U: t" y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 z* x# @; F/ ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: Q' Q* u& q# K0 w _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 D4 V/ d; k2 g0 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 x1 \- H' A0 u- ^# l- U H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 u/ g$ a$ n% I uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 K5 [2 s: E: g9 `. \1 f
0x00, 0xFF); /* configure the clock for transmitter */. P3 D7 N" ~: x! Z: @: p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ I2 }4 e" l. `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: Z% N5 B5 T& K+ [+ K* b3 i' xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% c! M7 {! P# A4 }, C* |: }
0x00, 0xFF);$ z0 \. x% H! `" l+ U5 t
8 _: `+ _) Q [- f8 q6 {/* Enable synchronization of RX and TX sections */
2 G( @! _; ?0 Z4 k3 E( l4 Z0 PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 s4 t% ^' X J3 ~; I" }2 e- W/ x4 b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 M) x4 g8 l# h) J: A% j9 ~% N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( g" p& F' ?. h0 ~. m$ L5 N/ t** Set the serializers, Currently only one serializer is set as4 O+ X6 D" ^# ?% {
** transmitter and one serializer as receiver.' u2 k4 j; x: e4 Q5 x7 A% w4 n* c
*/
+ S2 ]" ]' W- ^& N J" J& w. |2 g% IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ ~% a: O' i- w1 o- t9 b1 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 q; l, _/ y+ h% u** Configure the McASP pins " q9 K4 ?, r9 M( X1 {
** Input - Frame Sync, Clock and Serializer Rx
( [( a( V0 D. L. b; I** Output - Serializer Tx is connected to the input of the codec 3 I3 G0 r$ q# w: e8 m" K
*/
9 }- }+ M/ y! R1 l( UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; r. J4 J z0 k! J6 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: z% Y ~/ M3 A& J7 J& T sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& T2 |% @$ g5 Q; N| MCASP_PIN_ACLKX
& j) f) {9 x/ y; p; L" ]| MCASP_PIN_AHCLKX0 B" I" {9 X# Q1 I' ~, S$ a( t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ j* l7 m3 E$ a$ v+ @ d& y; U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # h8 ^$ t$ Q% e: ]
| MCASP_TX_CLKFAIL 1 [; b& s+ a" Z7 L: y* z
| MCASP_TX_SYNCERROR
. {4 J. z7 N* [& j0 V# D: D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 s% f# n9 z" l$ f, ]- _
| MCASP_RX_CLKFAIL+ l1 Q/ c6 M# C3 K- P
| MCASP_RX_SYNCERROR
& G+ Y. i2 I, M( }9 H6 F3 b| MCASP_RX_OVERRUN);* e" m, ~6 D! P1 \
} static void I2SDataTxRxActivate(void)4 Y' ^2 q- M {6 b( E
{4 I* A2 Y* W! t7 m
/* Start the clocks *// G; v+ P ~2 a; V3 c& K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 G4 e$ }* S3 X4 M0 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* [6 d( {* ?# r- R$ A7 N: y9 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( ~! H6 n, Z6 P) ^% e! }EDMA3_TRIG_MODE_EVENT);) [; j- D w& f' E- C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: x U; q6 b( n7 p+ bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ M3 Q% k. u; z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 x* p" A$ D8 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ }' W4 ?% L: X& a8 s( l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# z2 I3 K) z* vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ U/ O. V/ z; H5 \3 [; ~7 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ Y1 Q# m2 c, D) F6 S
}
$ n( ~- Q7 g! p; E, m4 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' M% r/ {% M8 ^! h2 A" z
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