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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 T/ k/ x* c, V/ \$ Uinput mcasp_ahclkx,; n: _$ ^* Z( m* s. K7 c! }
input mcasp_aclkx,4 M; }0 i- W* ?7 P% i0 m
input axr0,
- ?. E/ }! f; X' O; J0 o) H/ _
7 c& ?# Z5 I% _- i8 e' ~3 w: ~* Voutput mcasp_afsr, C* p3 _9 U" I" H4 |7 L2 g
output mcasp_ahclkr,0 N% Y; A) U. f# }# d# L5 f4 q
output mcasp_aclkr,6 R1 H3 k# r7 M
output axr1,; I9 T) k* y$ A3 a @5 }. j
assign mcasp_afsr = mcasp_afsx;
; p, y2 Y7 V7 ?! E7 E0 E; ^; Vassign mcasp_aclkr = mcasp_aclkx;: B V+ ^$ U- P4 X
assign mcasp_ahclkr = mcasp_ahclkx;! M& w* m( }( b6 X
assign axr1 = axr0;
- Q b; @& Q# A" u5 G% H& Z3 c2 e6 @( n p3 ^, V& w1 P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& b5 u% f( i6 S6 C1 `, lstatic void McASPI2SConfigure(void)
% d% n2 Q" D5 i+ c4 u; c, ^{$ z G& o7 {% G4 G0 a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 \8 d+ x& Q3 ?- V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 z9 x7 J' }% f3 W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 K% \' Z1 |. N9 a b3 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ w2 D/ G7 o( y \/ C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) k5 O: C+ q; _/ M/ J' pMCASP_RX_MODE_DMA);* q" ~5 Z$ Z4 a; {7 q! `, j5 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 ~& i `9 w/ Q5 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- j' p% N9 P1 p( TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! o$ W; a4 m$ OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) H/ Z3 K& k5 p' g' d, c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ k$ D, @+ W4 `3 q, S8 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( V5 P( ?9 F* Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% f" _4 Y6 f7 K {' W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; F" i& d0 n$ x& b$ K8 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 R8 e+ b" D5 q3 V' G3 b1 Q
0x00, 0xFF); /* configure the clock for transmitter */
* ]9 n4 A2 {, C7 U* TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' B- Z% ^2 x1 y L7 `/ I( a0 E7 D7 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' x# j: x/ y* x0 y, L" f" |/ oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 W7 f k" `* M+ y5 [" C9 i8 A
0x00, 0xFF);3 y0 c3 m, v8 p; }
* o1 q& h: B% B0 i/* Enable synchronization of RX and TX sections */
+ L3 R" B. U7 M$ ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
r6 o" E! n4 S3 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 z3 Y3 N2 u( @5 f" D* hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 Z' H5 y: q* E$ g! ?** Set the serializers, Currently only one serializer is set as
0 d/ z: _5 L& Q, J# _0 I1 g** transmitter and one serializer as receiver.) D/ a, P* \" }) v
*/) J7 [0 z1 z6 v* e: ^% y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) U! |( ?- ~* m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 o' V& X7 y5 w9 Z0 h
** Configure the McASP pins
$ i" Z1 C+ ~$ C0 P** Input - Frame Sync, Clock and Serializer Rx
( g4 o/ [3 i9 ~9 b+ O** Output - Serializer Tx is connected to the input of the codec
e0 F' G% v7 s' \) ?- o1 h*/( C; W* y0 `% E* n. c6 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. z, H" M, X# _5 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 d0 j; I& ~9 g- D. bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. H& K% b5 L* M2 K6 I0 S| MCASP_PIN_ACLKX$ V7 Y! ?8 a& P' b# u8 o
| MCASP_PIN_AHCLKX0 J) j, ~! D3 I# k5 c& M( H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* l) F) m$ M% l& ~; ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 a" l( U4 x' w% B2 l| MCASP_TX_CLKFAIL # W- C8 R; t+ z! z: Z& ?
| MCASP_TX_SYNCERROR5 c% `- H' i) W' c$ l0 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * u# d8 o4 Q8 t+ T v/ ~
| MCASP_RX_CLKFAIL
$ g" x% {0 f. g7 w4 p| MCASP_RX_SYNCERROR 9 ~& l5 w' v! T2 m1 ?
| MCASP_RX_OVERRUN); m4 R& T8 }$ a2 b& { Q9 e- O$ \' f
} static void I2SDataTxRxActivate(void) g+ S( Z4 Q2 u* o
{
' V# `4 I/ F% A) r/* Start the clocks */
k7 b% D' C6 C% q- BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. J1 N" i, ]' Z& J% D, q7 b, Q1 r7 XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 c% G7 W5 c/ L2 N" C, ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ [! B* X) `9 n+ D& ?" ?: z
EDMA3_TRIG_MODE_EVENT);: L) s C8 A/ w v4 Y. p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 s$ q& n+ l! J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# `" j& R$ J+ N' b- E4 a5 p2 X1 }1 FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 r, ^' Y$ `1 J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* F* m( c( r2 ] n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ I+ d" O+ r# M0 f5 f$ H3 b/ H/ XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: w, d+ A/ ?; m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. _. M: A- ~) W# [
}
# W% o6 F" C' N' ^' [; r/ _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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