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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
|* E- a5 N- E* _+ m9 q# Finput mcasp_ahclkx,+ Z- s' @1 b5 e- y4 g; I
input mcasp_aclkx,
2 b& y( l' e1 F# d9 b' Iinput axr0,; X$ S( }6 l# a6 A. V
5 y% M8 U s/ D" boutput mcasp_afsr,
5 S: P% q8 c. @output mcasp_ahclkr,+ u4 z) a. c# T+ m& L
output mcasp_aclkr,
4 b/ b) P8 b: W; Q; R. Ooutput axr1,
' i# p4 A' s# b m1 ] V* u- b assign mcasp_afsr = mcasp_afsx;
6 I3 Q2 [: L! K( n5 ?. U8 C9 P- hassign mcasp_aclkr = mcasp_aclkx;
- F& Y+ I; j! M" i7 [7 G8 J" E9 Zassign mcasp_ahclkr = mcasp_ahclkx;
" {5 N8 e* a: vassign axr1 = axr0; 2 w& z7 X4 q0 E+ n$ R/ P2 D! u" q3 ?
! w! J9 G; u# f; t2 D0 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! n) p4 u6 u& d0 K1 V
static void McASPI2SConfigure(void)- S9 E- }$ Q- e% K
{( S( N0 ?: C2 r/ D j {' N' o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 v5 U5 e+ g \" {# s% Z$ [1 [0 `: V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ N; A# h# U" d8 O N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 e `- q3 [, d% \- VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( ^# H3 D; T0 B m% N6 _8 e5 H+ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' F$ B( l+ K5 x! ]1 S
MCASP_RX_MODE_DMA);
- K7 v& [4 Q7 \3 o# y( pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& K4 F$ s( O3 g! L6 w) X. P J+ iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ G0 n2 S) I, o: ?4 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 D* h: B6 q3 f7 K* l3 d: k6 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, V4 N- Z( M# h8 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( J- S# b: Y# }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" s$ u1 l# H1 {- a! |0 sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. p5 n5 E2 O9 M2 oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 ~8 q" @8 f" |6 a% R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ ^% ^7 N6 ^) r3 g0 p0x00, 0xFF); /* configure the clock for transmitter */+ b: a" \% p" Y. D$ N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( j; L E' P2 Q3 G2 M! C2 J0 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& E" W% L' ]. ? p) C, y/ W! I2 y5 GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& ]& e( L- [# C! Q( R( t0x00, 0xFF); m; `/ l' ^8 j, q0 b
# m- C4 d5 J3 |. f/ l/* Enable synchronization of RX and TX sections */
; P& O& q4 P3 s9 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, E) R+ T. t0 j% r( d: ]3 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 f4 n1 e( U% rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ v6 R. [; F% U& U$ \* V** Set the serializers, Currently only one serializer is set as3 l0 F3 `# L' W# R) r, v0 f- M
** transmitter and one serializer as receiver.
0 B) S% X$ g) g- C" l*/! e, z5 `) a* b6 ~4 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. o/ n( {: k$ j0 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ z3 L: D0 G3 t6 v$ @# w$ k' l
** Configure the McASP pins / R* x8 _: G, t! U
** Input - Frame Sync, Clock and Serializer Rx5 W Y) h+ z9 u& R- _ y: H
** Output - Serializer Tx is connected to the input of the codec " V5 I; E9 {' q. r* i7 e
*/
! K( c# i5 l# w6 h: n7 z9 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) v* z X6 p4 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 p' J# K% C& a1 j3 N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( g6 r, e; h" w9 p5 z8 `7 ?| MCASP_PIN_ACLKX \2 h3 C1 ]3 @8 R
| MCASP_PIN_AHCLKX
' f1 X# D5 S; G' U! y' ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// N V% `. U, p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - \+ h! K# |6 s4 n* c
| MCASP_TX_CLKFAIL 6 q0 q$ o% J1 w6 ~
| MCASP_TX_SYNCERROR1 [- s6 Y# ]0 e3 a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 d/ n! V2 D" x9 f5 h9 y9 m
| MCASP_RX_CLKFAIL
- S; M: D! l4 c! _5 S/ T| MCASP_RX_SYNCERROR 8 F0 Y7 d! B G7 Z1 q6 X
| MCASP_RX_OVERRUN);
) ^1 K0 w4 s9 p. g& V} static void I2SDataTxRxActivate(void)
0 }" U" t i+ q" W( D, m{
% I x/ R$ M% a/ R9 `6 U/* Start the clocks */
0 ~. k4 L3 S! e5 v8 u9 j2 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 S# h/ b. ?. I5 r' V/ z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# K$ `& a6 q: j& C; ]4 V% c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 o$ ~+ m) c( CEDMA3_TRIG_MODE_EVENT);. V' k8 v6 g* G0 _4 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - j3 y: b7 f4 ]- r+ o. `% f* K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) U& T' V9 w, N3 ?4 _: A) nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ l& f$ i( t' o" n# I9 Q5 iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: g/ {4 K- W' ^6 H- z0 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 x$ l; O' f6 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; |2 A: B& u F7 t9 }8 ?, i% l5 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" c# E4 {0 N/ h' S
}
! _- M5 d* I1 k' f) h, h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ R# }9 }5 x( J2 e4 Y% x
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