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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* i# l/ X& S# n7 m: m& J
input mcasp_ahclkx,
# P1 M8 J; b& K4 v+ sinput mcasp_aclkx,4 W0 Z6 X! \" L R# E/ ^: e
input axr0,
% U6 }6 Y* L1 M7 Z% N' S
0 O0 p* H0 N9 F3 Z$ Zoutput mcasp_afsr, W# v! v9 V' |
output mcasp_ahclkr,% u1 }7 X, _) N& j1 u% _3 R
output mcasp_aclkr,
/ A' H! L5 Y5 B: loutput axr1,
6 k& G7 {! i5 v# Q1 A, h assign mcasp_afsr = mcasp_afsx;
1 Z( T3 ^$ K+ N8 S0 c' x5 h4 r2 rassign mcasp_aclkr = mcasp_aclkx;: z$ r/ ?* x7 I- `' @
assign mcasp_ahclkr = mcasp_ahclkx;
2 O0 D- _$ \+ V- v! ?" C/ g( ]* gassign axr1 = axr0; 9 ?. n. y. o" }
0 j$ `: ]! w' z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 D0 v0 Z- w0 P' b2 dstatic void McASPI2SConfigure(void) N$ [, a' N3 p) w" F
{
' I1 i% i( w: l5 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' B; I5 l+ h; }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 K3 V; M( R9 R' o- U6 y- eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 i* H8 `! Z7 I U! ~4 N* ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# O }. I8 ^( L; {8 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 D$ ^" z) S+ T! Y& H: v! kMCASP_RX_MODE_DMA);
. z; M% {2 c+ o, i7 yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ^6 Z2 N5 J2 s, P6 ]$ q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' n; W* I6 B: i3 @6 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , L- Y. v/ g f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% G3 j H3 c% P: q. iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ q! {) @2 O! E0 N+ jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' u2 s- _( o" S1 q& b5 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: [! [! A4 B+ J" X; a8 R1 MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. |, f& B! V/ c$ T) NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- _. X# ^) w3 x" I# {
0x00, 0xFF); /* configure the clock for transmitter */5 v$ A/ t) U n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* o7 X; e: H) H. @0 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 d9 E: r U- t! ~+ x0 Y" Q1 f9 H: NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
E9 Q* v& Y! `( y# \0x00, 0xFF);1 b8 F% X# Q+ z" V$ n2 \( Z
5 H& B6 w. a' k2 C; b+ ?% v4 S& S& t
/* Enable synchronization of RX and TX sections */ ) ]- ?* w6 Q' Y Y5 c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ f4 z0 s8 v4 |- [- O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% ^# p. ]& F5 c; P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 ^8 b8 b' o4 C" [7 x/ `** Set the serializers, Currently only one serializer is set as
6 Z' ^) ]" P2 M" l! z** transmitter and one serializer as receiver.
! \% e3 n4 Y. {*/ c7 m' v' X7 e$ r( U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 l8 c- {% o9 d9 ^& D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: Q* A) U; x, V: C( N** Configure the McASP pins
% t1 L# M4 D( m8 ?& m B* ?8 h) E** Input - Frame Sync, Clock and Serializer Rx
7 ^/ M6 y! y3 {3 I0 H( M2 ?2 l** Output - Serializer Tx is connected to the input of the codec / m% Y# A6 z. n: W
*/8 m! o2 u; E$ z3 K, n5 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 {1 d$ u$ v& b0 |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ m4 B. b6 k6 G' l8 G* z; @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 R. E e4 P5 ^& j1 e# ?| MCASP_PIN_ACLKX
1 f0 _% {- ]+ A. G' `# c* O! R, p3 ?| MCASP_PIN_AHCLKX
# w6 A5 g1 s* q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) W$ o1 Y) G( c& @& MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 s7 s- m2 g, }$ o% \* Z4 Y| MCASP_TX_CLKFAIL $ K7 g' v& c! f3 L2 A
| MCASP_TX_SYNCERROR
4 \6 i4 w7 V0 g) A* p( m# ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ W- ^1 o" C0 ?& R1 L5 P: ^ K h u
| MCASP_RX_CLKFAIL' N* u" M/ G& v" I* S' e7 {
| MCASP_RX_SYNCERROR
, e! L: F& a! T1 Q$ || MCASP_RX_OVERRUN);' w8 J8 \9 }! g$ c8 x/ V3 S i
} static void I2SDataTxRxActivate(void)
. o3 m9 `- X- o- o! ~% G{1 m* ]0 \0 ^ M: P7 P1 w' L; k
/* Start the clocks */
: b% Y2 B- i/ D+ SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 t5 c5 `6 b8 d! k, B! d4 @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# [. r! a3 e/ C1 Q+ |. REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ I+ E2 t& i3 x o0 u( b
EDMA3_TRIG_MODE_EVENT);
5 w) b& Q/ N0 a2 N8 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 k5 B' o3 v3 Q& \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: T$ e7 p2 p$ B$ p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( j( |1 s8 r6 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// n. J1 o+ b1 Y1 b5 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) K) U1 k; \$ F2 s# \" B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 G s5 B) t5 t# _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 g/ w# Y0 Q2 U}
+ L/ P! `7 a: O% X6 L6 N4 `9 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , Z6 Q' w/ ^* f4 C
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