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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ D9 S; @( z3 S0 s1 h9 d$ T) r1 winput mcasp_ahclkx,
C6 C& L n1 ginput mcasp_aclkx,4 I# I5 X' p$ v+ }* _& D0 y0 A
input axr0,
; N I$ q2 K5 p1 n- q8 D: j6 i. o! A% b
output mcasp_afsr,
3 w4 ]2 x$ k* s( @# |4 s0 R# foutput mcasp_ahclkr,6 |1 [ L1 w. n( U
output mcasp_aclkr,2 N7 K7 H3 m8 x/ h' d9 S
output axr1,4 E3 U9 h5 o& R+ j5 m7 Y
assign mcasp_afsr = mcasp_afsx;* ~ E! E& H# y1 U7 L! l( W: o
assign mcasp_aclkr = mcasp_aclkx;6 u" K$ m. B2 F& U
assign mcasp_ahclkr = mcasp_ahclkx;! v. @) s' e8 `" l5 Q& r
assign axr1 = axr0;
1 x, R* V c- i8 w: y$ b: N3 R# q) K# u1 Q2 B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; V! v; X+ t. m7 }8 q: k3 estatic void McASPI2SConfigure(void)) N7 z. g% [# R1 \
{: h# q/ ~& \6 b* P1 a g) W/ m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% j+ }4 n! Y$ A( l" i z7 \: sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// C; s8 A0 W' `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 a- r6 C' ~! P3 ~$ p7 o; C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# C- `1 J3 I! |; b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. `" }" s+ }- `4 r0 o( SMCASP_RX_MODE_DMA);' v" m; s S* k1 E v, |# [3 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) p0 u4 z& Z8 X, p8 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. ^/ N- p$ Y$ u3 h* G' BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 P. ^7 |; V [8 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 \0 T6 p* x5 \9 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! T( ]: l3 g6 P# V. d( C- D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ P2 o( x: l& S3 R! V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ T |- K+ D; hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, c: ]( U a7 t8 t9 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% F: M9 Z$ y0 d; I5 C `
0x00, 0xFF); /* configure the clock for transmitter */4 O& n- n8 b9 o, K- o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 `+ {$ f7 H5 m0 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! y4 k j- w# L1 q7 Y. H+ H0 {! S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ y; N. k. ] w0x00, 0xFF);! C2 U- v/ k% {& i. S+ e
3 m; A" |9 E, @ L" H" x4 P% v$ P5 ]* C1 g
/* Enable synchronization of RX and TX sections */
6 P& ~( n5 }. q7 Z3 L: Q2 T( GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 V$ }2 d. N, @: o" C/ ~8 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 V. I, G( Q# W' y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 ^! r. A. e% {. `7 m9 b
** Set the serializers, Currently only one serializer is set as8 Q1 l% e2 F2 O
** transmitter and one serializer as receiver.% t& E- f8 E$ F/ I; X
*/
0 ]0 w+ r Q' N2 l. Q' sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. ~" H5 Z: N/ `1 \8 K7 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) k" a& p3 i ^8 y% P
** Configure the McASP pins " H! p/ q3 M5 @1 u
** Input - Frame Sync, Clock and Serializer Rx
, x' O5 }: l7 ?8 |7 O# @** Output - Serializer Tx is connected to the input of the codec + g+ R6 E+ H$ a, _
*/5 K9 W: @# \2 E3 o: @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 j, N3 v6 y8 P: t! Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- Q1 H% W2 Q+ E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 |* K, C- y6 P$ {3 Y% l j| MCASP_PIN_ACLKX
2 u- v! D. b* m% t \8 t| MCASP_PIN_AHCLKX
5 C8 S) A+ _3 K. j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 q" f% x4 m, EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' E2 `- l O7 j$ t' ~4 b
| MCASP_TX_CLKFAIL , n; n0 e9 d1 ?
| MCASP_TX_SYNCERROR
$ r& u; T3 x+ B2 h5 W: |/ [- ^: G G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 z) N0 i7 q1 u# ` t8 `7 R) D2 R
| MCASP_RX_CLKFAIL. A* T% s2 m* A" D( a7 R
| MCASP_RX_SYNCERROR
1 M9 z r1 b6 S* ?: Q| MCASP_RX_OVERRUN);( z: o+ V* W6 n% N/ H
} static void I2SDataTxRxActivate(void)
% [4 l; X9 t4 K! N# o) J/ ^{# r9 d& V% ^& o; g2 P
/* Start the clocks */9 K* _% \) G/ F1 L, A0 A8 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- d: U5 ?3 B; x8 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! P1 Z1 O! n7 z, Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 R* E/ L7 X7 C6 D7 N/ q
EDMA3_TRIG_MODE_EVENT);' p: g8 J+ b; t9 r3 {& x! F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) U! d" M: K- N- Z! n; J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 `6 ]+ v6 E% g8 u2 ]: p. c% @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) p9 V/ m) y4 \' P. x1 t* B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ]+ }" X& y' C3 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 v6 s8 r$ q+ Z* e$ A9 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 D" E5 b3 s7 `0 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- y$ n1 {8 x/ c, j: y1 v}
* ~0 E( s* T9 K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * Q" m3 s* X5 \6 y) i) {
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