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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," ?( O! c& h7 p3 k
input mcasp_ahclkx,8 v) e E; \! C; [. q5 K& Q& \
input mcasp_aclkx,
. V/ D$ N" n" b$ S6 finput axr0,$ z5 f r6 ~4 H3 e; ?: @" M7 ~
* N; t# [% O; o
output mcasp_afsr,
/ n: f0 H( X! l) U! Moutput mcasp_ahclkr,0 `, i% |+ k6 B* D- U7 J
output mcasp_aclkr,1 w' f! B3 i8 @ P) E+ I$ U; a
output axr1,) d# |8 K0 c6 R9 N" w
assign mcasp_afsr = mcasp_afsx;8 b/ e U6 g5 e5 r9 N5 k0 x9 ^% U
assign mcasp_aclkr = mcasp_aclkx;
" x7 J' A3 D: Kassign mcasp_ahclkr = mcasp_ahclkx;
6 y' ]# a7 q v( ^% W' x2 }assign axr1 = axr0;
4 K+ _$ ^; C; {0 x
9 h/ S7 v8 o* h# g. @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; E# p+ x& [+ E7 A5 @ zstatic void McASPI2SConfigure(void), h. W- `1 P: Z& H: @+ \7 A
{
3 k) o* P8 \" w! I3 b6 l6 cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 C# J: }% Y: z( }/ z! K1 g/ l/ T! U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% Y$ G! t6 y/ YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 q6 _8 ?1 m! g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 e Y' K% g- J" I: m8 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," ^ I& f6 z: h, Z
MCASP_RX_MODE_DMA);3 ]# A R5 b) J; d* B6 y# e% F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( y( ]: c7 w L" h! h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* {* w) L* A8 S& j! p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 q% e. P3 l+ o$ A7 H8 Z$ I/ S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 k# X) F+ [( PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! R5 l% e4 ~0 P P* ?: I% u" o& gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ N- F& Z5 K9 S! @2 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. N5 J# {4 a! o% a( cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , ^- j; _* v6 n8 ^ A5 k2 k) r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; g2 a% p* m9 `. N, `/ I9 v
0x00, 0xFF); /* configure the clock for transmitter */
4 O) X2 D: l1 i$ J4 V9 M# VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 @% J3 i: Z8 j0 [: d, r! f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , |4 n" D3 ]7 |. J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 z8 |2 {2 K8 J
0x00, 0xFF);" G2 Z/ U$ E" P5 y8 M0 e
% Q- s2 h6 ]3 B' l/ y2 c# ]: S. ^# O9 P/* Enable synchronization of RX and TX sections */
6 P) b4 s& j9 k& [5 X* L/ BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 h- j; v4 W. \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 P3 ?3 ^: E7 E4 v& I4 X, ]% l4 d6 x+ i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! d9 i6 [0 M0 k' \! l# _ q( [
** Set the serializers, Currently only one serializer is set as
+ O0 u" p6 x7 R" p** transmitter and one serializer as receiver.
& S# c* k- K+ b% n8 p*/4 D7 {. o( q! T( }7 N; A! X4 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ q5 [ b3 Q/ C- u% w+ w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) L! q7 Q$ |( ]5 _' |** Configure the McASP pins ; X2 y. M/ g' ~6 u* y$ D, O" Z
** Input - Frame Sync, Clock and Serializer Rx8 ~" @/ j+ ?5 U/ n) O4 R5 W
** Output - Serializer Tx is connected to the input of the codec 6 }8 T' a1 j; D/ }+ C9 c$ V
*/. q! v9 t; [( |" F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 a+ R3 p$ r$ k+ |, j/ c- t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 e' u) n1 Y, B" ^9 `+ c% s3 T8 D* i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. Q' K( \7 W+ d| MCASP_PIN_ACLKX
1 Y; g) P" V) v0 a( A| MCASP_PIN_AHCLKX
) T( r: L( R. A% c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 W$ y4 h7 J4 @$ `& RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 O3 u7 k8 S" F9 ], `
| MCASP_TX_CLKFAIL
, N8 Z+ w2 u# T- O| MCASP_TX_SYNCERROR
2 _) M ? ~0 G3 t/ {6 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , D0 ?! X' K/ K+ F: g8 m
| MCASP_RX_CLKFAIL# m4 ]& }+ @1 z4 B3 k( ^6 K
| MCASP_RX_SYNCERROR
, `( l h0 }% b. t3 J3 d| MCASP_RX_OVERRUN);
k% G2 A) i/ m. e- c. w' ?} static void I2SDataTxRxActivate(void)
6 S- q2 @% c# X+ n{! W5 j I+ j% O: D, ?! M
/* Start the clocks */
( x! t' M3 Z2 t6 `5 g8 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 b7 M$ H/ @. ~- q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ M: T. `+ i' `' m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& \3 C I8 r7 u+ O0 @7 yEDMA3_TRIG_MODE_EVENT);
5 k$ R1 H7 _* X' q0 o& R: w$ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! O2 R' g+ W* }: ]5 a2 `( |7 T8 d1 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, v h4 V1 K0 F5 Z2 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 W( w% i3 v/ F( i; g. D# Q/ @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( e! \ o4 c7 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' q4 U+ A, h# O1 ^6 F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) p7 X* x; [6 O8 }7 k+ A- WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ {* ~4 h1 F- R; ^/ k$ ]% T7 i}
; v. y, ]2 t8 B w. [3 L0 S* G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " A. C" p- P1 v% S0 K S: y
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