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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( ], S/ D- W5 Jinput mcasp_ahclkx,
4 E1 l. N6 S% b* f; \input mcasp_aclkx,4 W) _* C3 E$ M, d: K( s" [
input axr0,
* Q+ m# h9 X3 f! S" B" H7 h9 P9 g- t( U1 S# P
output mcasp_afsr,- Z1 h* m" L& I; e$ o
output mcasp_ahclkr,1 [, |( W* h2 e& Q$ c$ z+ L
output mcasp_aclkr,3 z6 K4 q* m/ [9 W6 {
output axr1,2 I% g f4 U7 b; s3 M$ B9 [
assign mcasp_afsr = mcasp_afsx;
0 F; [6 u+ e0 w4 Zassign mcasp_aclkr = mcasp_aclkx;+ Q- I, f# s0 T
assign mcasp_ahclkr = mcasp_ahclkx;7 K% o2 O1 m. b+ n8 J$ s2 o( I* z* Q" k% @* _
assign axr1 = axr0; % N3 p" w6 W) G7 R- V
. O" W& j' u8 }9 O" k+ L! `6 Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 u/ V, S/ i" Lstatic void McASPI2SConfigure(void)2 d/ n; v t/ u$ o
{$ j2 C7 W( F! N1 y/ Q" g$ d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. M2 r& O7 ~6 v( s' g: d" k. ^1 MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, q/ b7 g; V K, P" v6 H8 u! k4 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ p0 }& S4 W5 @& w' UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
i0 I& A# |; h5 D2 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 Z" E4 `1 E4 C
MCASP_RX_MODE_DMA);
5 i! }4 [4 n) k% R, SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) r3 V$ e2 P* b/ c VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* ~, h L8 R2 t2 A0 H9 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : ~) o! i% P7 U9 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 b6 {, K. n) c# LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # @7 ]" W) O1 l* C* T W8 J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 m: M% [) U# M& s- b, ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); a; J& ]. M: U" f e3 A6 f$ @: X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* E' A8 F+ U' K5 o0 F, CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 _( a7 t" D5 k8 ~9 }' D
0x00, 0xFF); /* configure the clock for transmitter */
8 }" s8 p6 [+ l8 w8 C, F$ GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 l8 @0 ?! ^& Y+ [# K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : \( W2 e. i d% a$ ~$ r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# H5 X8 O& i8 J8 n5 ^7 o. Z
0x00, 0xFF);9 ^ C2 Y& F7 r3 F
8 @9 y, `& R4 n- D# |, U
/* Enable synchronization of RX and TX sections */ : N! w+ K; n' k: j" i4 L, c' `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: G) ?. n) |* [# ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% s0 t5 [1 i5 Z& {6 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 w, c* N4 O; c8 a2 ?; a, q
** Set the serializers, Currently only one serializer is set as
5 T9 E+ ^! w( `6 B8 @ ~** transmitter and one serializer as receiver.2 g$ x6 k3 G7 x `' V6 G+ r4 l
*/
: }1 L2 l4 { ?% uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 ~3 U3 T* S# |- m# d8 J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 P2 f2 v9 Z3 j3 P** Configure the McASP pins
/ Q- i: U% `/ ~2 k3 e* O** Input - Frame Sync, Clock and Serializer Rx
' O5 P1 ]; w! P5 s6 ~** Output - Serializer Tx is connected to the input of the codec
: H0 ?7 H: B8 M2 l*/% S2 j* n. F% s% L+ }4 U0 `4 v/ q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
T$ \' J" C7 t# U: ?/ ~4 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# X& k: Y) ~& E9 ]8 [- o- }! uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& R, @7 j* _( }) h
| MCASP_PIN_ACLKX
9 @. a; l9 { ~0 F% {/ y4 c| MCASP_PIN_AHCLKX: C$ o6 k4 d5 I- p, Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# Z- m7 K& p' b0 K% z+ V" T9 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # K+ D; o" J- Q5 ]1 _) C& z
| MCASP_TX_CLKFAIL
3 l' @: o8 i. E, F: A% j* C| MCASP_TX_SYNCERROR$ z$ z* K4 k! E: ~) G' `, F3 ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ [3 M8 v+ Y( r| MCASP_RX_CLKFAIL
- F! R. b/ B& E" d| MCASP_RX_SYNCERROR
5 f: t' t# F/ y/ E/ r+ p| MCASP_RX_OVERRUN);
% e0 F2 _+ L+ r+ w} static void I2SDataTxRxActivate(void). C2 C5 C' `6 q( ~
{
" w! X8 M# C* Y9 T& _. D$ R: F' i/* Start the clocks */
0 q$ Y7 Z# \ s7 O! b) |! O$ W# NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% }, c/ M1 Q2 p8 h4 P/ B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) V8 M% ]% }# E% _* }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 _/ M/ T6 @% @: q' g6 j* J( ]
EDMA3_TRIG_MODE_EVENT);
$ R2 v$ O F" q9 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 c, { T$ N/ l" ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" o1 I" F5 ~% j$ P4 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 x U) r. E( N% Q [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' `$ J d9 C7 | t0 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; m' a) @, Z1 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! y7 q. E7 C; E8 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ [$ U t1 a! I+ a
}
9 X0 f7 r t( o6 r9 }% N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! z3 e& H9 g2 a9 m* E
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