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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% j# D% @3 q2 y/ q6 L9 _, j3 U1 ]
input mcasp_ahclkx,
- q2 F; R0 o( A: X: e, g$ A% Hinput mcasp_aclkx,
: r2 q2 L+ T( ?9 q& ^3 ?input axr0,. C; N7 ]! U" ]; g; S2 J
& y4 v6 Q# s- N5 [6 w2 a: n, `3 u
output mcasp_afsr,# B! a X# k. A6 J/ p; o5 s
output mcasp_ahclkr,
5 G8 W: t4 v3 f$ Doutput mcasp_aclkr,
3 t9 p: Z) G6 b Y7 O& @2 D, youtput axr1,+ b. a! M& d }" a
assign mcasp_afsr = mcasp_afsx;. z7 o4 C: `, Q/ V
assign mcasp_aclkr = mcasp_aclkx;0 p" g& J* S0 y+ E6 a
assign mcasp_ahclkr = mcasp_ahclkx;
3 L) p! f! y5 m9 aassign axr1 = axr0;
7 _8 W ~6 j6 N8 n' c2 z" C5 ]3 d; U& H! y) o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# I8 @8 B# M1 L# L! Gstatic void McASPI2SConfigure(void)
6 N8 Z% ~8 ?6 H: v2 v0 D{3 ?: \& h7 @/ G1 }+ u+ u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ w% B5 _3 L- \4 Q8 e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ G+ k- V7 P. p5 G% b, y8 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 Q9 c" t. Z- w, r, PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. E* ~$ C' ^7 {- }0 h5 vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# r8 f% p2 e& QMCASP_RX_MODE_DMA);
# g* `1 f# q; t/ G* S* [5 ~8 Q' P% XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& {. u' m: g0 U/ ]5 G2 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 `- |- n; k& N/ q6 B' r4 i0 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 ]; E+ @' k. `! e/ q& X% O, VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) Y+ b& c2 Y4 E+ A: s1 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! k1 y6 i" A( S2 g2 g2 K, Y8 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ D$ i$ F+ v \7 L: r3 G1 m) m2 ` E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) @+ ^* D! E- n8 b" V f7 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * `3 ~, |( d8 `% S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, l7 ]/ G9 `; X8 W
0x00, 0xFF); /* configure the clock for transmitter */( S9 U7 e6 z* s4 `& G1 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 x+ l: h: j; j7 n4 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 f+ |9 b R5 i. q& Z1 vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( e L# ]; i m# A. F0x00, 0xFF);" G$ P/ n5 {( S# z
7 ?4 p. `; T5 _; E' Q- N9 C
/* Enable synchronization of RX and TX sections */ # E" F9 w, W4 p& Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 H7 N/ J) ?- N. d$ \) R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 Z/ C1 R! P6 }( S; m/ A4 [' u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 A. y# R. |- F. \$ L8 T$ ]** Set the serializers, Currently only one serializer is set as
; Q% b/ k; r3 C+ M3 D** transmitter and one serializer as receiver.
( P& F0 M* T) x8 ^( ^*/
7 \8 X+ k. n: @' lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& g5 M, p' T: x" G; [# vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) `; r/ }0 |9 {+ r( j/ z2 w8 i
** Configure the McASP pins
3 p& X2 ~4 v9 _$ p3 _7 I" H** Input - Frame Sync, Clock and Serializer Rx
$ R6 m/ E4 S' w) b2 Z: C# M** Output - Serializer Tx is connected to the input of the codec & v6 c( ~, j4 h+ b+ a
*/. J$ s1 E3 E4 C4 O$ u% q8 V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 _8 _$ t# @( l& w+ m5 g) ]7 C, C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. E! e6 |( z: U/ j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 X Q+ S$ I1 R$ J+ }| MCASP_PIN_ACLKX
- K3 p$ J. D, \; z% Q2 O! @1 I| MCASP_PIN_AHCLKX+ v, U0 o |, u6 M- I1 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 [+ X. q; k0 q. JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ I* j6 J- ?4 @) b| MCASP_TX_CLKFAIL
: e& k& u, M8 j9 f n& [| MCASP_TX_SYNCERROR
+ k; w& G) d0 ~8 W. N- j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" T3 C' h0 P: V/ I| MCASP_RX_CLKFAIL, u# i: ~& [* _; {2 z% y
| MCASP_RX_SYNCERROR % u1 G# ?: t* q) ]0 l. h) p
| MCASP_RX_OVERRUN);6 y5 `2 f7 \8 `7 M5 Z: F& F
} static void I2SDataTxRxActivate(void)
9 P% J5 h* W9 U1 `$ e7 R( S3 w" M{8 O2 x& z" k3 e( W) f
/* Start the clocks */* U; L* U+ Q, U' o# U9 E% V) q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" N1 ?3 |; s3 C3 Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 D( b1 ~# _- B4 m; aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ {- C U% e2 e% ~EDMA3_TRIG_MODE_EVENT);% Y* B; q( ]) }+ M* {7 |9 R2 x# U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 ^3 E3 D3 L8 n; `+ vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. c4 i2 `8 D6 y6 ~: V& l5 G) g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 h. d/ ]4 @- B" ]$ u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# Q# A9 N* V( p5 o5 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, Y0 C( A7 F, w3 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 c8 E: C6 N6 E4 ^$ f9 O6 A. RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( m3 u# z+ {! g5 W* o7 N. T}
* j! h/ K/ \# I$ t+ }$ b3 l& W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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