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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! V# R9 B$ f3 b: i
input mcasp_ahclkx,- W& v: B# U3 w/ I! B- V' ]# b
input mcasp_aclkx,
7 W2 Y! X, d4 s* |- O3 k, q! Binput axr0,
" Y2 s: A2 r& a9 {& F
( o8 x7 o" v: q) {3 Qoutput mcasp_afsr,1 R) \1 A9 W8 {
output mcasp_ahclkr,
: U: H8 m( D! Q. ^9 ?$ foutput mcasp_aclkr,
: p7 a5 c; }7 a3 `2 U( R4 Loutput axr1,
% e I6 V* F6 A7 Q5 P assign mcasp_afsr = mcasp_afsx;
' D. A @( o f4 _' }assign mcasp_aclkr = mcasp_aclkx;
( v: i' h: \# ?7 M. A% M; Zassign mcasp_ahclkr = mcasp_ahclkx;; h# d+ v ~- W3 X c$ h3 s7 M
assign axr1 = axr0; 6 z+ |9 m8 ]3 N5 T+ w% b- K0 n) _7 e
/ c+ i4 q2 ^4 H+ K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) p3 n8 w# Y' O! Q' E( mstatic void McASPI2SConfigure(void)9 k- I* ]& b% a' o
{
: P3 X, N- ~! f$ N8 o8 iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ K( r, X& ]7 V2 w6 }, d6 j- qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 W& K5 u# R% f( U& j, q& O/ VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# Q7 [) u5 d! l o ]; H5 x0 M7 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! f' M% u6 ^! L. U7 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. E# h) x' h; g# N
MCASP_RX_MODE_DMA);
/ U4 E# c) g" N; W3 Q! ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Q9 \ [: [/ d9 U" L4 k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ _. P& ?" e8 \+ P3 C( g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : H6 j) U' y4 Q. j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. V4 [6 ^; \! F; D0 [) q+ f8 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' Q P5 Y: N( n. k9 z; ]5 x+ K4 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 V$ i9 {# r- N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( E2 b6 [$ H' ?6 {" HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 H* \& ?$ s8 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' p% B$ |: k" J# {4 Z7 O0x00, 0xFF); /* configure the clock for transmitter */
( J/ I- h8 _8 JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: W+ k' p" H1 f j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 q- g+ g0 b* R5 S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. K4 ]6 \6 a( G) z
0x00, 0xFF);8 M+ L8 G! M' x' {! O
8 V, \( g3 B, D2 Y) M& }6 M/* Enable synchronization of RX and TX sections */
! W( ^7 H6 j) L$ YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 |; V3 Q8 N4 B- k) Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# V# R) h. |: T* D4 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: f8 _3 ?! z7 @' @% k** Set the serializers, Currently only one serializer is set as
' g2 W+ @# ~! @& T** transmitter and one serializer as receiver.
7 g5 G' u+ E3 B; o1 M*/: a) f& `3 i" `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; g. y- p( F" a3 C# EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 _+ O& D3 I2 s" f+ D, H2 L** Configure the McASP pins
: n9 I m' \ I" w! w** Input - Frame Sync, Clock and Serializer Rx
9 t& o0 U& o3 ]. ~/ D% P4 P) B, D' @** Output - Serializer Tx is connected to the input of the codec
) T# }* e9 O7 P6 l9 @4 m*/
t; _- G* @7 q1 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! d' _' ^! H# S+ |5 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ u0 x8 F7 D2 R* a$ \1 @$ q; f( {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; t, @% a3 L0 u
| MCASP_PIN_ACLKX& j$ ], w: Q( ^
| MCASP_PIN_AHCLKX" I; K8 l8 K9 J/ \; _7 D1 _3 a8 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 y# L3 r. O* U5 @9 y- E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 d6 w' C1 S0 u4 g
| MCASP_TX_CLKFAIL 9 F* x9 D7 [0 w1 E/ T
| MCASP_TX_SYNCERROR7 x4 f/ e* {3 X1 o2 |. z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 I. A; P1 D! F5 u. Z8 h7 P. |! m6 V) @- a| MCASP_RX_CLKFAIL
3 R/ p. s% K$ Q, [/ A) i| MCASP_RX_SYNCERROR
0 A2 g! i3 K% o, ]% P6 K| MCASP_RX_OVERRUN);. [2 q( W+ i6 C% e
} static void I2SDataTxRxActivate(void)
- |; G) _8 u4 L: t; o! I{* r! Y; L) O6 Y% E: e3 r5 ]
/* Start the clocks */
3 F( Y* U, J/ z$ j1 \, k IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- h% m4 P0 p4 H" O9 j6 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% S5 T1 W% s+ m2 C NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 _4 w" x9 I( L. }8 t: HEDMA3_TRIG_MODE_EVENT);
! c2 o' b9 ^1 C$ f; v* O. _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 D7 L0 Q) j1 F6 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 f6 l' @, |& U, J& F5 o H, w: Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" y+ ?2 G7 i0 f" h6 ?/ F) dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- D. K- p" }" }! ~8 U M" L5 Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ F/ T/ d( a: c1 ?, mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ J9 k+ l w( Q& @: e3 O7 J ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 U4 `0 p- U5 W! X; P" v6 N
}
/ Z! @# O5 c) n8 T/ y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! t7 a5 h3 G, G' m* i
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