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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 z5 B& _8 K5 Z6 Iinput mcasp_ahclkx,
# d# B% }) j3 u+ j: u# Ainput mcasp_aclkx,
2 J, T: J% G( m8 K, Xinput axr0,
, r! ^; f: n0 j1 r: B: n. V& B3 I
1 `1 r6 J, w# W. a6 `output mcasp_afsr,
9 A& E7 w) t* h5 Y2 zoutput mcasp_ahclkr,( R! t0 Y4 I$ v
output mcasp_aclkr,
9 A9 A4 d( {$ |- koutput axr1,+ G: b5 U) B. L3 _: H& o9 B
assign mcasp_afsr = mcasp_afsx;! F* G2 h: e; f3 X9 A! ]
assign mcasp_aclkr = mcasp_aclkx;: U, L' _6 [, N' h/ P
assign mcasp_ahclkr = mcasp_ahclkx;9 j3 l9 X% c c- s/ R3 W& d6 L- q
assign axr1 = axr0; + Y7 Y+ m. }/ a2 d7 S" {
$ g9 r; U8 n* v9 k8 ^& ~9 B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ u* j5 z+ V' jstatic void McASPI2SConfigure(void), S+ Q& q }% p- q' Q% I
{
' t; Y( ?( [- e1 R7 g6 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& v! X# C0 q; [( b1 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 B) l9 ^4 ^; O8 z" s' T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& t, C- C2 w+ J: i% vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 e* l! {# o/ W/ h: Z4 @) t2 x; O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* P9 V- z: z9 d5 D. I; y/ BMCASP_RX_MODE_DMA);
/ o3 ]. b, \: f7 G$ x6 H6 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& y/ O( U+ A; @/ j0 L/ j7 c6 Z! H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% A4 v1 T' y6 U& w) B9 `! f. ]& u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! f$ f/ z% t; A. `7 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: q! b. r; i$ q0 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * C: X. t# F% r( c D$ y2 h2 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" h( m( Q: L' L' Y- e' mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# Q2 V- E/ R0 s. M% v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ N" J5 j' r0 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 y% W( X6 X& J6 m( T8 h9 h0x00, 0xFF); /* configure the clock for transmitter */
$ [" p Y# D @! UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% m& y) X+ H5 O- Y- y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! U# ]& q4 t9 M: X6 C2 o; X- j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 w! c3 L# N7 j3 B9 T0 h( B0x00, 0xFF);$ O0 r. F1 W9 C, G: \8 x: p7 l8 F( x. X
7 k& v* j. g, i% k; j6 c" u
/* Enable synchronization of RX and TX sections */ % h. C; {: Z1 y9 A* A7 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& _6 c3 v! c# R% T8 c1 B+ QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 A* L8 Y& g* w/ @5 z# A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ c5 V6 G q, j. m, z
** Set the serializers, Currently only one serializer is set as$ Z: Y3 t r0 F0 V+ h% J
** transmitter and one serializer as receiver.
. w2 H4 d8 V' D5 g# [. C*// D5 @, r5 ?4 x" u. s5 I! w3 `- L$ t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- d/ ~4 z8 p9 P# g% w, c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& G! G* X7 m/ g8 h( z5 y
** Configure the McASP pins 1 d' F9 ]2 P& C
** Input - Frame Sync, Clock and Serializer Rx: ~% \2 H, y. N) q" F) k
** Output - Serializer Tx is connected to the input of the codec 7 O S3 S- C" d3 k
*/8 c4 O; Q8 h) U9 u$ e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ C' X; q9 ~+ V R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( u- h' [5 u9 f+ X# SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 `, }4 `2 g5 Z8 K+ N8 h4 o, U
| MCASP_PIN_ACLKX- C: A! U, Q1 i, t: @; P* X0 a
| MCASP_PIN_AHCLKX
0 p2 p5 r3 U5 S) E) ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. V/ u/ e8 F( tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* {. E( H3 H- K _| MCASP_TX_CLKFAIL
5 e) x# L4 ~2 }/ M| MCASP_TX_SYNCERROR
- D* c8 c3 j8 V/ o! Y# q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 B- S. {$ o* G; `) k: C| MCASP_RX_CLKFAIL
7 J7 x6 M5 X- c, l8 i| MCASP_RX_SYNCERROR 2 a8 ^9 y8 X# L! r1 D3 a
| MCASP_RX_OVERRUN); d3 ~3 A5 a! d
} static void I2SDataTxRxActivate(void)
4 C' W1 |8 J4 W1 E* J5 L{
1 p$ B/ F5 c: ]; D/* Start the clocks */2 d+ o( Q+ S2 x+ _; @. i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( e$ w/ c. ~% e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 w, w8 o* o1 c& ?1 B) jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 a4 X ^1 B8 Y' v. a2 B
EDMA3_TRIG_MODE_EVENT);
$ A1 }; H' z, l9 ]0 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 X# N1 p% z5 t, r% c9 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& F! F R/ Y1 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% g/ ], J* M3 r/ C1 F5 j1 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# |* U# C( ^; i5 `, Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// ?4 `$ E L! W$ y6 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& Y! L6 _ j. g4 q9 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ Z' k4 |" Q' R* |} / S. p: F h8 p5 h# x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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