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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 G6 F2 ^$ [' o( [, c/ } T4 t
input mcasp_ahclkx,
- \/ t7 e: ^' Y t" L3 g% p' H7 ~input mcasp_aclkx,! ^6 s# M6 A& p5 O. W
input axr0,3 {3 v2 Y3 U$ B& F: I0 w
0 T6 q& [: S1 I: @1 `: Eoutput mcasp_afsr,
* r# Y3 y$ j$ \. A' k- Soutput mcasp_ahclkr,
! D9 k# a- |# B1 {5 g+ S# Ioutput mcasp_aclkr,
3 U0 j! ]$ {8 z- T5 M) N( ]% Y, @" r1 soutput axr1,
6 }6 B7 T8 y8 s# c2 o [ assign mcasp_afsr = mcasp_afsx;# x' |. \, n* |& L. ]2 @1 F& L0 l& U
assign mcasp_aclkr = mcasp_aclkx;6 j# y' a' e/ \, c' w% r0 h( n
assign mcasp_ahclkr = mcasp_ahclkx;
3 e4 I! F/ a/ L8 W+ A9 Kassign axr1 = axr0; $ k4 r) ~/ Q9 C$ _( R. U, R! A
6 r" F# A4 K! Q% X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ E5 l% X4 ^- [; x3 sstatic void McASPI2SConfigure(void)* C; { E% N+ m, n+ t- I6 J
{
9 m# V4 J: s4 x" N, }8 D! N" ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);; g8 y- m3 ^$ K$ u/ t0 |; b/ Q5 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 E; T% k+ I2 C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 r6 O" W; L" E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ G! z/ B: O+ }! ~2 E/ y# ?2 \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- T" _+ I+ o6 [- P8 o$ d8 VMCASP_RX_MODE_DMA);
' Q3 V% S7 ]* S3 \" {) w" zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& n2 ^2 [+ V- C" N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, P( S1 Q0 K7 I9 m- a! H* @9 f% rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , f0 Z9 ?( N; p5 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 I7 {; D& ^9 }! T. E, i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) X7 w2 B2 A9 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% M. \& |* q+ E" |& W! @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" r. r3 L/ B- b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: |/ V0 i$ X6 M" ?4 K+ C TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& p' x9 H4 b3 U, g0 T/ o, }, V& s
0x00, 0xFF); /* configure the clock for transmitter */
6 C- s% P) C4 U4 y) J% h( pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; l) ^% J9 m8 Q9 r* ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % I0 O7 K; c0 J$ f2 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' }1 H `) v7 c8 |7 j. A# M* h0x00, 0xFF);
* e6 V/ l( A$ x3 i5 x1 T0 n9 ^8 c# k; S
/* Enable synchronization of RX and TX sections */ / {; w5 C+ U3 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' g1 E8 m0 r. g! r2 b; P. FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 ?9 n" c ?4 | d0 m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& z% V9 K, _' h4 ]6 S$ A** Set the serializers, Currently only one serializer is set as
% a M* {/ V: E$ r** transmitter and one serializer as receiver.
4 a h3 y Q" c- I*/, M8 m# H! w& \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 Q1 J3 D- { r7 @/ L! B" q( tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% M5 S: P. _, I4 i** Configure the McASP pins % f$ u# ^& P7 P7 ]
** Input - Frame Sync, Clock and Serializer Rx
6 ]" w( @+ l& b** Output - Serializer Tx is connected to the input of the codec 1 @( J1 K" }8 N4 N! U9 W# t
*/
* O3 X+ @" G4 c* zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* h1 B9 p2 Y5 n& i( Q+ X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 z$ }; c( E* E# i5 kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 E! T7 _7 W7 v# G1 L+ a4 Q8 p| MCASP_PIN_ACLKX; [8 R+ _# }# A# m0 u5 j1 I
| MCASP_PIN_AHCLKX9 V+ q' e* X6 p' Y1 x6 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
m4 a: c' t. {9 V" Q4 v- N" cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 i2 p( k. G9 B8 D. l* j
| MCASP_TX_CLKFAIL ! Q( A4 o: _" J9 E+ u. n
| MCASP_TX_SYNCERROR I" e) o& c# t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR U5 z2 x/ K, I' F0 G
| MCASP_RX_CLKFAIL* t. R& H5 g8 ]6 ]$ [5 K4 q
| MCASP_RX_SYNCERROR
5 \, [+ U$ |& d$ t+ y' Z9 c: d| MCASP_RX_OVERRUN);
$ ]: t/ k. n9 Q) p} static void I2SDataTxRxActivate(void)% D a0 |; _, s h+ Y
{
! F$ q+ b, U+ q! y2 I% r/* Start the clocks */
$ ]' N9 P( N8 d+ B3 k& fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 Y1 r9 s! _# I; m7 i8 h2 r5 N5 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, u5 t* J# ]; k5 @1 y# u' ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ y6 o8 b* m6 u! Q8 g% p
EDMA3_TRIG_MODE_EVENT);0 p: K. C; ~4 z, F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & q. |5 a5 `& v: u% ~3 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- z/ Z |9 k% r. p$ J& c9 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# W& `6 L' E8 G& b4 z& ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 t" E$ M" V3 C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 q; ~9 j' _, N( c) c) T% {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ M) j* V% @. m5 d# E$ y" |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 n1 s8 a" c& T) B. _
}
2 z( k3 Q7 i0 g& R; T6 j/ d! |: `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
, `8 ^5 n* L) }2 w0 X/ n |