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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 d9 b2 A) M* t8 R: Tinput mcasp_ahclkx,
F8 g% B: S! T8 y! u0 k% `input mcasp_aclkx,: {+ U9 _6 k6 P) L5 d
input axr0,+ u+ j3 Y' Q' z" H9 ~$ \
; D! W# m$ t) O5 S
output mcasp_afsr,
5 C/ |" l; N( l/ R; Woutput mcasp_ahclkr,
/ N: \. m; X: g* F% qoutput mcasp_aclkr,
, V2 x$ ?/ Q& _/ j2 y- t+ y# k8 R1 zoutput axr1,) N% Q' J3 o) u1 j( Z) j
assign mcasp_afsr = mcasp_afsx;5 ]0 o% {! p& n4 D. Y' b9 Y
assign mcasp_aclkr = mcasp_aclkx;
& B; k3 l; B ?5 {) J Nassign mcasp_ahclkr = mcasp_ahclkx;
8 M9 Z+ k1 ~* E/ D" E9 D+ P @7 Kassign axr1 = axr0;
' j6 U, M$ j8 D& _ V ]% X2 \8 m; b0 Y/ _6 H" j" }5 j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " @" J7 w' \5 }3 U0 `
static void McASPI2SConfigure(void)% y! A7 ]4 Y1 v' C7 q
{
5 s$ y: t: W' K6 g" G/ g6 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 i0 x/ J0 h9 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ s- e$ h- i- l/ K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 @; [ E* w" B2 K; i, T( Y# xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// U' ^- x; L% b8 d2 I) |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 K/ q i! b9 p5 H% d
MCASP_RX_MODE_DMA);5 b- H# V9 f2 ]4 v: Q4 H: E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ ]1 `1 @. H% {8 }6 \3 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 G4 D2 f$ k p2 \# I( Q. PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' S8 q5 p/ k2 F" K6 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& a7 a5 M7 g7 mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 A! C- z* t2 Y6 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& ?0 ^4 L& r/ \7 k0 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; h+ U4 M* q# e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . l' j( _* h* t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 K* `2 d+ o" v& j2 b" o0x00, 0xFF); /* configure the clock for transmitter */
( i! f" ^0 ~+ }9 ~" jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 c9 `3 O: R: t2 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. T2 k: b0 |, m& R. u- EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 C6 E5 O- |5 ~5 M
0x00, 0xFF);
# b6 Y! _1 |5 ?% ?; v' `: D! \
( \3 h" u* n! p2 h/* Enable synchronization of RX and TX sections */
4 @: p5 p* _* _2 x# n/ bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ x+ u7 V' s2 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ h; @" i" A5 U# w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% O- o& q& a5 m0 H0 A- D2 W, I! O** Set the serializers, Currently only one serializer is set as
1 ]' @0 V$ K( M0 F** transmitter and one serializer as receiver.
' s/ j( c/ S9 G: s*/$ O; u8 ?5 p' k+ V* ]5 a2 N+ v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 B* B$ }9 X1 _! S1 y" a) a$ W6 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 A9 l, N) J' e- `0 v
** Configure the McASP pins ; `( a/ B% }4 O9 v
** Input - Frame Sync, Clock and Serializer Rx# ]9 q1 a) V0 d) {' h% |
** Output - Serializer Tx is connected to the input of the codec
" V4 D ]9 K% A" F: b- z8 y8 M*/
/ ~ W$ ]& y; QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. w8 u1 }1 O+ [ e8 D* r6 O$ w5 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. c8 Y* [7 \ i4 z( ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 N% w& c# p7 V+ I" k( G
| MCASP_PIN_ACLKX
2 v& q- c @9 ?, w+ o4 Z' ^| MCASP_PIN_AHCLKX0 X" f/ a4 P7 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# e5 ~- c( B5 K7 l, n3 l8 ]7 k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 l/ a6 ~& [ g- l| MCASP_TX_CLKFAIL ! p1 F! p2 V/ o4 [ u, m
| MCASP_TX_SYNCERROR& f+ c. a7 _7 d$ z& Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & f$ ^& w; Q3 H3 D
| MCASP_RX_CLKFAIL3 y$ X r8 r) a! |
| MCASP_RX_SYNCERROR , t2 _7 K' f, Z
| MCASP_RX_OVERRUN);
2 E/ d8 M0 q8 z# X4 I} static void I2SDataTxRxActivate(void)* B2 h* s) d2 M1 w" B3 M( x) `
{9 p3 \4 g# o6 U5 Z- [
/* Start the clocks */% p* r% y, X% m0 N) M. x: |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% P% {) l6 i4 C% dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' E3 w' F3 L% l0 l+ x+ OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 e- ?& y7 Q [4 |/ M. J
EDMA3_TRIG_MODE_EVENT);0 F* U4 T) s, r8 q( l0 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . `. C& l8 p6 e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" k B6 g( `+ L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 J- _" m, a# Q6 S( P+ p5 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 B7 I9 }. \! |1 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# m1 x; |7 e9 f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. k3 U! }& g F% {! ?) l8 s& ]( MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# n" X, a! h' e3 W}
" `" \7 d* j5 @: p9 ?1 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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