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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; {9 ?% C8 C" a- ~5 t' c) h( b( jinput mcasp_ahclkx,& f- m8 W" Y" | u f3 \
input mcasp_aclkx,
9 i! g7 @; V3 I+ Vinput axr0,
/ p) H$ j$ Z: B
0 |7 Z, Z1 M: n) }output mcasp_afsr,. w0 t/ W! C f
output mcasp_ahclkr,
6 |; V& B- c* C- r4 t+ x! b) Foutput mcasp_aclkr,2 `9 j5 R2 n S
output axr1,9 F& p+ W7 f- K. c' [
assign mcasp_afsr = mcasp_afsx;
/ E0 C% o4 i1 Y7 z9 y, { Bassign mcasp_aclkr = mcasp_aclkx;' s% M0 J6 `) z# f
assign mcasp_ahclkr = mcasp_ahclkx;) ]5 a _; x+ k8 S6 ~
assign axr1 = axr0; 8 T! b- G2 V3 d' B
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : o2 j1 M Y7 x! V! u. X" |
static void McASPI2SConfigure(void)
1 [5 P( @4 W0 R& b{- k2 Z! d6 B: |8 E& ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. {- H5 Z$ ~2 ~$ G( A- W0 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 u9 S2 ^0 _, A3 P% C9 J1 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" P! d: B: M6 i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. A; \* Y2 a- |" r3 x+ }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) X: u b& ]& ]% K
MCASP_RX_MODE_DMA);
5 o+ p+ o6 h" s' p% GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 l1 z- x: g9 ~7 F- _# a, ^+ F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; O- J3 f- I2 j8 d. G$ ]# g% `) }; OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* m7 q; T( V6 X6 x5 jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ u$ Z; I8 l6 S7 \! w9 j1 t2 w1 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ C/ h2 ^/ K* C$ A6 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! Y6 w3 H' K% u8 K, Q: c$ k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 [% u% A7 C- e, U' Q; n4 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# l! |' w# A1 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: H) j* N( H! R* B& r
0x00, 0xFF); /* configure the clock for transmitter */. k& w1 t" o. g! p2 y% f8 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) A u0 _9 F6 T3 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 s. @7 s, I3 S- R3 w7 `9 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ k7 L" K% [( q0x00, 0xFF);
2 J9 B5 R; f0 H5 q+ @: W! E6 i
: y5 U2 u" H8 W8 ^- d& w" }1 [/* Enable synchronization of RX and TX sections */ 0 C. |8 d4 B" f8 y0 s0 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, j& G2 z4 e) p& b, `2 @, YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); v& Y# Z1 k3 |5 O' `* \3 t$ K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** ~8 x9 n- [1 J. q. T! {" W
** Set the serializers, Currently only one serializer is set as/ F+ T2 g8 r. H% c: G' ^/ a% q
** transmitter and one serializer as receiver.) a. I, y6 _2 [, B2 W7 y' Q
*/
+ ?3 I* W' W$ p6 V k5 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
M' ]/ ?: K v$ }. {& ^& YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 d3 m5 @- L& k. v** Configure the McASP pins # f9 v# f _& S2 `) a- H
** Input - Frame Sync, Clock and Serializer Rx; }( l! k: Q s3 u& q
** Output - Serializer Tx is connected to the input of the codec 5 q/ A) f( Y( o6 Y o4 ]0 y
*/
$ p. i4 ?6 i% Q2 Y V- |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; W+ b' I1 y+ Z! aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% A9 B' h0 c0 S9 m4 ^7 `# uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. D, T3 R9 r7 @6 a1 X& R# ~0 y| MCASP_PIN_ACLKX6 Q2 f Y. n! L n& w! e3 U" z
| MCASP_PIN_AHCLKX
2 D C, o7 s0 L: e5 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! w' s8 M, l! D% A2 K2 b; ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' B: o) u1 D1 ^
| MCASP_TX_CLKFAIL
5 I6 ^3 C) m1 [9 K| MCASP_TX_SYNCERROR
' r' |3 a: X6 k0 c2 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- c2 K" f0 R* c, o1 y: ?| MCASP_RX_CLKFAIL
' J# y4 Z6 D, e C% T| MCASP_RX_SYNCERROR
/ A" [! `/ x6 J$ R0 B8 w: b, W6 M| MCASP_RX_OVERRUN);8 G2 f. {. S U7 Z/ b# O
} static void I2SDataTxRxActivate(void)6 ] `, H# {- }1 _+ J9 m1 ^- n& I
{
' m% h; p t: H, z; S7 B% e/ t/* Start the clocks */
s8 L7 D/ B$ b. R m0 i# d, oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 R& e ^/ S. T1 D$ OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ N2 D! _1 X) ~# O: f! I; {3 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," y7 }( I! N6 g! k( Z
EDMA3_TRIG_MODE_EVENT);
' E7 H* W3 v K0 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 [. ^3 G& X+ E& U S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 o, K# o' A) P# z4 G' X$ C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; y$ S* y6 b; e' |( N F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; X7 w. X* Z4 r J1 O/ l* V2 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; x' T0 e. C& B ^4 h% u: cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& h& W. U6 ]" i. }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# o! C* }2 r8 b* r+ l
}
6 g' q/ g4 N+ x5 v6 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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