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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: J) q2 O3 m) ]! einput mcasp_ahclkx,
( h& j0 K6 d2 R/ F' ~' }8 Dinput mcasp_aclkx,# i- I( c5 K7 G+ l/ Z/ ^
input axr0,' t% [7 Q1 {9 J# m3 |
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output mcasp_afsr,6 s! ^- A6 d9 [1 ]; v+ [& w9 w/ r
output mcasp_ahclkr,
' m$ Y3 g: L% r/ Coutput mcasp_aclkr,
4 r' k3 Y L" d0 [: B; F. koutput axr1,
8 ?+ o! i+ W# r: a% p2 R assign mcasp_afsr = mcasp_afsx;3 ]# `. w$ I0 N+ P% A' a0 s
assign mcasp_aclkr = mcasp_aclkx;6 C+ b: n! K( Q9 m( j, s
assign mcasp_ahclkr = mcasp_ahclkx;
: ^, J! T( p- D" y3 K6 _# F dassign axr1 = axr0; ( P' c4 V3 \1 X: Z) w5 h
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 D0 T ^& o& v) z! I1 i C- Astatic void McASPI2SConfigure(void)5 l; s. n; g) k) V7 Q9 k' h
{& l& }* S6 T9 p" H- J+ w# ^! Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 @% p4 H; v; v h) ?6 H( a* I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( X! A: H1 {$ l! O4 j2 ~' U# ?, mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) l% M1 v: @+ X a7 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ E: ~( I; p0 l# S9 r: P7 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ r4 f% X# N3 K' |" ?* ^8 s* Q, B
MCASP_RX_MODE_DMA);) y# b% j/ _4 R6 n3 A7 u0 i8 c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 M- z; d2 {& z6 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( A x! f; b0 _6 h6 aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 w' ?7 `4 V2 e' W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ?, z: k- U% a% @$ i* KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & |: M$ Q- Y1 g6 y b. q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ _' } Z* F9 {& i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! Y- q& W! Q$ V# W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 \! G5 ]" x) MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," f l8 `7 ]& n5 S: b
0x00, 0xFF); /* configure the clock for transmitter */
0 F* A% }! ?% N) o; u0 L: f6 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) X: T: H: x! ~9 C# t1 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % N$ U1 H; b: H6 N. g$ W3 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ X# P9 p9 W0 s# n' z0x00, 0xFF);" `) y `0 k1 ~3 m1 e6 C; ]; [$ s' W$ e
7 Q& x; ]8 L, F4 m% i# w3 Q/* Enable synchronization of RX and TX sections */ ' A2 d" r8 x& ~ V. S$ _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( E" p. G5 K$ g1 K3 [+ OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 C2 R% M4 a4 N/ z" d! F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& L2 [$ N. c0 T
** Set the serializers, Currently only one serializer is set as
- n, R$ ~4 {% M0 r** transmitter and one serializer as receiver.( M+ D/ M/ M# T8 a" p5 C6 t$ N
*/
& u F) F3 R1 D* n0 |0 D+ I( pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: A. ?. x: n8 r" }& {1 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" E( E- P. @8 {$ b [: Q' o* s
** Configure the McASP pins
5 m& ^8 M3 I( l7 V( n8 @$ [** Input - Frame Sync, Clock and Serializer Rx
; Y# _+ v) `3 e8 V; v) J** Output - Serializer Tx is connected to the input of the codec 2 r- k! B, T/ H/ E' c
*/& L8 Q7 h5 a/ g2 A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% l7 `/ m. U% Y! S) PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! s2 g: K1 D3 D8 O5 C% d& Z, r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; E. {" S3 [, ^ }5 r/ `" Z1 N| MCASP_PIN_ACLKX
7 j" P' K# o" g/ o; \, c9 m0 x/ O| MCASP_PIN_AHCLKX
3 r* n! h: Q6 P' N6 M: |3 X6 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 H$ p( `; u N( @; F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 P$ ` I+ P3 Y0 h2 M$ J/ h| MCASP_TX_CLKFAIL
e2 e, a$ Z; z| MCASP_TX_SYNCERROR
& w1 F* K# i% J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 u. ]# z1 Q& L Y# e V| MCASP_RX_CLKFAIL+ v. v. @3 ~2 a. j3 d- X
| MCASP_RX_SYNCERROR j0 L$ B8 B2 b" o
| MCASP_RX_OVERRUN);' }6 ^; n9 {" H3 G
} static void I2SDataTxRxActivate(void)% H9 x, ?% R' S" l/ c; a# D4 K
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/* Start the clocks */9 j: T: s3 g6 I# r/ I; A& O* Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 n Z1 `9 \) h# t# X/ yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
h/ I; t% _3 K/ c. Y$ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, e+ ^+ r! \& o4 T) q2 S# C& o
EDMA3_TRIG_MODE_EVENT);
, z+ v' h0 ` m% D8 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , q- { E& G7 e4 c7 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: z3 P$ y3 u% t) cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 X' U2 I6 j" I% l e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' ]* Q0 ]+ H0 g4 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. b$ S' D! R1 L' Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 J7 Y: _2 Y+ K& Y) {. l8 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 y& \+ w, i/ D4 U
}
) p* M3 S8 U, ?" _2 x+ F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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