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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 e% J6 j9 Y; m2 w* u4 ?input mcasp_ahclkx,
, O, t( k$ X# b" P/ p9 Binput mcasp_aclkx,4 {: _$ B9 D, r6 T/ n3 _
input axr0,
) e) {% h/ @* N* W
* i! p" ?. A: [output mcasp_afsr,
& v6 V* A$ K& i4 routput mcasp_ahclkr,
9 [7 `0 H* \2 D0 H }output mcasp_aclkr,
4 a. A- G+ k" i: W3 Coutput axr1,! P% w2 C( A ?1 N* F( \/ @
assign mcasp_afsr = mcasp_afsx;5 q J+ H. ^8 F' q' D5 V
assign mcasp_aclkr = mcasp_aclkx;
1 k$ p# T4 }( G1 |assign mcasp_ahclkr = mcasp_ahclkx;
% M4 m' l- z0 t0 c4 e# v" dassign axr1 = axr0;
; b' A8 l+ s" _
3 M7 S4 M2 c! [% `' O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! K1 Q# @% p: rstatic void McASPI2SConfigure(void)6 \# [5 N; x/ _; ?& h
{8 w2 D* P6 {' G: F! }7 g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& T5 K5 F; @! O4 w3 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ s! f! }, A$ @4 Y; p0 G5 G9 d' Z% eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. z$ z% y# g3 g! k! W6 S( r' I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& H* v' x2 N) ^/ c2 A# eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Q5 x5 y j# A$ uMCASP_RX_MODE_DMA);
- e" V. k% x u% }6 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 X. o/ z9 K) |5 p( kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, A2 T, [9 S/ c5 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: q' B) y# P& q: f g3 }, bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 X- @7 w8 f7 F$ ]$ Z; ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ `, Y# U) S! D8 e! uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 Q) S- i$ c3 C ~+ H( E6 Z6 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. R; h$ x Z& d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 O s6 @# {" Q2 ?* K9 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 D/ d4 P$ C; o7 T g
0x00, 0xFF); /* configure the clock for transmitter */" n8 e: I% P( N' t F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 I/ C3 d3 q7 M( u! rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ o, ~+ K: O3 XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# E( u" S, Y0 }+ k2 w* o; u" ~8 |
0x00, 0xFF);
/ d, y7 C4 l- C1 @1 H
7 `$ B& B- {( y' s/* Enable synchronization of RX and TX sections */
, Q* a0 q! W% o; ~8 g* Z4 ~ NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ h1 a7 U' F" l) J1 ]2 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. N) K7 L: A8 F7 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% u: o, d1 Y* s) |& g0 _' ~** Set the serializers, Currently only one serializer is set as( z- ? `/ g5 Z2 ^/ m A7 \
** transmitter and one serializer as receiver.
9 ?+ C" V! ^5 u" O*/% g- K6 X0 l! E! J1 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% X' J! x1 m) t$ _1 S0 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
R5 z9 c) h! ^( g- }** Configure the McASP pins : {. }# A! v1 Q/ f
** Input - Frame Sync, Clock and Serializer Rx: u, _7 b, T [3 |& \( K7 d
** Output - Serializer Tx is connected to the input of the codec
3 d, F4 x( m" m7 p" i& a*/+ s2 H% U+ @5 Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 p. u1 [* Q- }2 G6 f9 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 o/ ~8 E( T4 ]: B# L2 G9 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. g c, D5 p5 r, C/ }7 E| MCASP_PIN_ACLKX: ?" k' T x$ T) J7 S0 l* C
| MCASP_PIN_AHCLKX
' Y' [+ q: k7 o9 K) c& o1 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 ]( g$ a/ }$ {& R: X9 w/ V; n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' C& }$ i/ J4 v0 ?2 T| MCASP_TX_CLKFAIL 0 N" r7 V5 c7 M- G% ~
| MCASP_TX_SYNCERROR W" Y i4 ~+ Q6 @& x- X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 c3 T) h/ X; F" c1 H$ F/ o& a) d& E
| MCASP_RX_CLKFAIL
" h3 y8 ~* o N( p3 \4 q+ Y| MCASP_RX_SYNCERROR % c2 |+ A0 P* l
| MCASP_RX_OVERRUN);
6 M; D- v( |, J+ h! K/ P- l6 ~} static void I2SDataTxRxActivate(void)
h+ ^0 \, J: T+ f& D{
2 }1 K# C9 `' t# ^5 c# ]/* Start the clocks */
m3 z5 k& Q, ]0 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ {' J3 q: \2 B" M5 h/ D9 u H/ \4 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 D6 D7 o* n5 a Y0 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* ^, R5 n: @" b( c2 ]EDMA3_TRIG_MODE_EVENT);
( b- k7 s( d% ?: XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; p: Y3 d6 S4 ~: {. W% ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
R: H$ B6 i$ p7 `$ i( eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: g* k( Q! S& T$ R% P) q2 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ O- J# y; z: N7 N5 z2 _+ ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: C$ t$ N& T- c+ Y9 q- sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ C8 o$ v' E# C% K$ b1 i [/ U# U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ ^, ]1 x0 p7 \8 V' x2 l3 z0 }: |9 J
}
0 a7 ]0 A' U/ l* t* x6 O1 k: \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 T1 T+ T$ V! l: b5 A, c$ l
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