|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 V: K! c( h5 D: Q0 Linput mcasp_ahclkx,
3 t/ r, ^, y- ~: P- Qinput mcasp_aclkx,& ~$ u+ g' _. n. Z# m7 M! A6 [# v
input axr0,7 t" p( U9 n: n1 q6 D
$ z& B" E% _' h8 i6 p" Z
output mcasp_afsr,+ T( J: z2 O0 v
output mcasp_ahclkr,: B# i- @2 |. j) \+ c
output mcasp_aclkr,+ _: k7 X8 k. s7 K
output axr1,7 ?% b A; o: `4 x0 c2 V
assign mcasp_afsr = mcasp_afsx;
7 [9 R' Z6 h$ i! Iassign mcasp_aclkr = mcasp_aclkx;
' J: f' {4 |0 e. f' o4 massign mcasp_ahclkr = mcasp_ahclkx;
4 i+ e# c) j) i. C) cassign axr1 = axr0;
9 n* J6 x% M8 w9 l, P% l! w/ G; W: @$ ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 e# [6 M$ [! @8 ustatic void McASPI2SConfigure(void)
* u7 g( C& b3 n" a/ E& C{
& u# K( |! i$ OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
I ^( x& Y1 t2 ^( V6 J+ q' T9 Z0 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 c3 r5 n" d4 z o4 L" _4 oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ c. f& w1 H, t$ }' K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; R: e/ d9 b; d3 \' |8 O' a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. r+ Z7 D- z" E Y s( NMCASP_RX_MODE_DMA);/ M/ N: I; y8 J# D& `6 z n. ]- a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 D+ Z8 b* D! H& E' jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ j: C7 `7 @) t/ Y' N0 `! Z) B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 F+ O/ D7 ?3 b8 A" f! IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 ]1 B- Q3 W# l$ u. j5 J" fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# U4 j4 c9 `1 S5 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( d, s* p; [5 y( sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% [# w# l5 K9 |7 K* Y1 h# g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 r% ]3 c" o3 iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ ^8 L* r/ [& G7 A0x00, 0xFF); /* configure the clock for transmitter */3 S" ]7 i# a2 L' h: Z, ]" R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 M/ O# N- p H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 b9 I+ J7 l! C i9 X& jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& p. N& A s; A- n: e; U. e0x00, 0xFF);3 X/ n$ K- x, ] |
0 p: a: Q( ^0 N4 a
/* Enable synchronization of RX and TX sections */
% V8 G q' I; p( eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. e4 _) S4 ~. S& P4 ?& I2 C1 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 L" h5 M% _9 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ j3 b9 w! w; \. k4 t# U
** Set the serializers, Currently only one serializer is set as
7 W" e, \1 y0 G** transmitter and one serializer as receiver.
p% J) G3 f! \2 m$ O4 C*/
4 e* G. u p, {3 {1 k% vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 B7 c% X3 M& a, {) R6 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
r' w2 g& j; K9 b4 _** Configure the McASP pins
7 X* }. I2 T! t/ x( B, H** Input - Frame Sync, Clock and Serializer Rx
9 C( }8 E. a3 V+ | |2 ]** Output - Serializer Tx is connected to the input of the codec 9 @7 Q9 Z, M$ s, u7 }4 D7 o) w
*/
- _0 o: K& W% G0 l8 {- [ lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 ~. Y! n. F3 I! t; e: x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 i. X( j# u% m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. Q0 E- t, N" b! ^) m| MCASP_PIN_ACLKX5 {3 m+ c. O a' V2 W, H: [8 L3 A
| MCASP_PIN_AHCLKX
. i7 R% [) y, T" ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& C( C" K6 ^2 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 w) T5 ]* B# t2 i9 V+ D8 ]! c
| MCASP_TX_CLKFAIL 8 C$ c+ s2 H1 S4 f( _" \
| MCASP_TX_SYNCERROR
* k% L0 R% }0 F" o1 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 V$ h9 [6 Y( y| MCASP_RX_CLKFAIL
m' Z# B$ D: B| MCASP_RX_SYNCERROR ; T3 Y( m( X& n* Y( u
| MCASP_RX_OVERRUN); U# y! V4 q# O$ R1 B
} static void I2SDataTxRxActivate(void)/ ?9 n- P% G2 B, N
{
9 e& w6 h+ n2 V/ z+ X( d- S; y/* Start the clocks */0 r& s1 p. n$ u! v; D. V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( o) g2 [+ e5 F- E4 Q8 O/ S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 J; {2 k# ]% [& OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# n3 [' ?4 N/ R6 g/ |
EDMA3_TRIG_MODE_EVENT);
' w+ L' q" }5 H5 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: N& h; [2 v- r4 W; I& nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! r, i+ T% ?. N( p( H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 R, N1 k& a9 A7 l( S' C' kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& M; D6 i; P, ~- ^/ l; L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* p& M2 \* {% l5 @6 Z) oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' t1 ^0 P% f i% q) |5 ?- a7 p8 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. k, r; w/ x8 O, F' F} ! A' T/ ~4 U9 t$ S; K- K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* I9 B+ @- {# {* g& y2 U, W1 U2 R |