|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" Z% e% R& q$ c* w tinput mcasp_ahclkx,
3 E( g. k P# J' @input mcasp_aclkx,$ Z1 b4 k _' Q9 _. o
input axr0,4 W7 ?$ n9 E# z0 ], d
5 A( y# Q' ^& U8 u @0 G
output mcasp_afsr,
1 C$ B% u; M0 ^ J2 [. ]8 Woutput mcasp_ahclkr,# U, J1 e5 H$ m( G/ Y$ i
output mcasp_aclkr,
6 r6 Z/ c% n l4 n) K2 Woutput axr1,. x g' H: M4 R+ C
assign mcasp_afsr = mcasp_afsx;
) W; V6 i; B* {% c) v8 Zassign mcasp_aclkr = mcasp_aclkx;
1 O, f7 k/ O5 T# R7 Massign mcasp_ahclkr = mcasp_ahclkx;
% b9 c, z( }6 V" g% T" @1 ?# uassign axr1 = axr0; / {, b6 ~- \; s
7 _8 X2 g- {- i6 ?3 \5 Y. y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 }. @2 f* Y5 \6 p
static void McASPI2SConfigure(void)
0 _9 V0 E. {' w3 V+ G; [1 N{# l4 v% Q7 v2 }$ B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 U0 q+ k8 a/ I6 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& w5 v$ O: j9 F: y1 K% cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, X' j2 O& O: D# A) P2 }" u/ p6 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' v+ B" X+ e* k+ Q4 | W- oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- v) _/ E5 P; f# M3 H3 y, ?# N3 SMCASP_RX_MODE_DMA);
$ C7 q) p8 U* e; E! x+ }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 h1 o. Q& n& a/ H# B( q" y; eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 Y2 D0 {. ?" D9 TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 p( a% `$ ?4 Z T# T( I5 M4 [- ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ }' D( h% {- C! H, K7 A0 q% f$ eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 j+ X% I: d1 z" q) u5 u9 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& x- g! P9 z S9 f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, l6 |9 d/ I& {, x* UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& l2 y! I$ |5 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: k, d, j" w7 a
0x00, 0xFF); /* configure the clock for transmitter */
& k, {; P. r* O( h4 f* D3 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 @3 v% R( Q$ K1 N$ _- L0 WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 ^" h8 M0 N4 z) h D, s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, U2 s+ u) |0 @# I B4 Z0 ~4 ?) r
0x00, 0xFF);
/ d# o% }+ z4 V0 ~4 `" W5 v* y; r% |9 L4 N5 M/ S# y; C
/* Enable synchronization of RX and TX sections */
5 {. u) Y( H* l6 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 ~) n# r( e( V% I# S" [& l" k$ |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# m9 }. e9 Z5 D. j& M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ e' r3 o. M& \6 Q8 p# t9 u
** Set the serializers, Currently only one serializer is set as1 G0 c% n: A& C5 R: W, X& l# c
** transmitter and one serializer as receiver.
: x: b: X$ `# i" ^2 }. r*/
; z" P4 U! @8 e, h8 X# f3 O, fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% B1 U' W) r2 q/ z( K3 FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* L/ U% t% e& [& d/ h** Configure the McASP pins
2 c( e+ l" y! K: \, u7 l** Input - Frame Sync, Clock and Serializer Rx
7 ^3 W6 F$ `& z2 n A" z. C. n** Output - Serializer Tx is connected to the input of the codec 5 T- u5 i! k+ q( @5 ^( F ~
*/0 Z; G% ^- l' y2 T# T, X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 l- L( z) n, }1 KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 R+ B9 k1 b! G: x9 X" SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) a0 g) T( c' N| MCASP_PIN_ACLKX
, _+ q# \, D; k1 u" i7 k7 x| MCASP_PIN_AHCLKX
2 R; _+ W6 S7 o$ W- B% f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 `8 }6 O" b. c8 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 k* |3 b. Q: H3 q! m
| MCASP_TX_CLKFAIL 5 E' {* S# x' R8 H, z/ p
| MCASP_TX_SYNCERROR
) o/ c' Q4 ]9 f& ~6 |2 b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 J$ \& i A! [7 J
| MCASP_RX_CLKFAIL
4 e1 [- Q! m" M% G( u| MCASP_RX_SYNCERROR
2 f' I* n/ a, e| MCASP_RX_OVERRUN);( D8 z$ Y$ M+ k1 f# ~
} static void I2SDataTxRxActivate(void)- ~9 S! U+ M1 t% N" x! N' Y
{3 B4 x& d2 D* o" i: `
/* Start the clocks */ z: d0 H5 U) y4 w, L) X, P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( R' ]+ |! o1 {- z% _9 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ y; d. T( p. I7 j2 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. ?3 y& r4 L, A: P
EDMA3_TRIG_MODE_EVENT); r. _& B" H9 f" U9 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . N- ^/ ]6 f) A5 ^! c" H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 S) C8 `1 A s8 T1 b+ V5 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ A7 \7 O% V: W- l' E! iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, B7 |- X6 O) d7 N# r5 E, ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 w( N1 b; W. l: Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) l; V& _2 j8 ]0 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 }/ B3 {( _1 n. Y
}
( ?; Q4 | e: I7 R2 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; T# [& V9 W2 }5 I0 g( ~8 c7 d, ]
|