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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 [2 x% ]$ ~8 W, V5 finput mcasp_ahclkx,
! u, V7 q% }/ ~+ P' Zinput mcasp_aclkx,& b8 _3 G+ \" o$ i( _! G1 U
input axr0,7 _. [% W1 b% Q- w- h5 f
7 V* I" q! n% h& J% c; l" Loutput mcasp_afsr,
# W% F' o5 y# z$ w! ? ~+ m9 c8 Ooutput mcasp_ahclkr,
3 F: l/ Q6 V! F9 X" }output mcasp_aclkr,% Q3 u, {8 R" [. P
output axr1,: I$ C" l, Q, H2 r( M! k# a
assign mcasp_afsr = mcasp_afsx;2 q5 N5 A ^% F1 L, e
assign mcasp_aclkr = mcasp_aclkx;
. n. s' A9 u+ W1 X9 a5 N6 P: ^assign mcasp_ahclkr = mcasp_ahclkx;% T' B$ ^# f: O' {
assign axr1 = axr0;
# G+ q/ {/ D+ f+ J) W+ Y! |' Z# t! A* ]. l: P: j' r, {7 N3 ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 i. Z& D% R3 v! u8 a: l0 N/ \4 n. Z
static void McASPI2SConfigure(void). q! q8 [6 D$ s }2 @# Q4 j
{8 Q# y; G; ~: o8 U' a* X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) d+ r( i4 o1 [# XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. P' `+ L6 Y; H' Y/ T% N% g. d( _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 m( O& h, p4 d$ P/ m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 T6 d. d7 a* h F; R! JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* \. o4 z! J+ L0 E0 K' R, w
MCASP_RX_MODE_DMA);
- ] c7 L- Q% w- g3 p! z$ nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, b; [8 P N' I, l) y6 g* LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. r# B( [# Z* {+ @: M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, N7 a: c( d4 p' M8 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 t7 B% Y/ Z( ]+ _ K1 m, [% D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : R9 |' w$ I7 Z) u, A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// _6 j% A! ?: T H, Y+ X8 u, K! E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 f3 X- _: f/ p" [, P5 e" f9 }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); r; O1 z: j, I1 y3 v; i" j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
^+ O: ~ Q4 m# |; B" r( Z0x00, 0xFF); /* configure the clock for transmitter */0 {3 |* E r$ Q+ v2 Q9 p6 h k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# ^' m, I: |7 @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 h3 F' Y# i. r& i' R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 E d% ~" V* ]- B" V2 ^
0x00, 0xFF);
. V1 A& H; g+ w1 ~( j
& A; A0 n' c* i6 m; s/* Enable synchronization of RX and TX sections */ 7 C+ O% w I" H# S9 y) Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 E$ Y; X0 j2 l: FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! T4 [) s' H4 b2 k; i4 D: ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, M, D2 [: |1 r$ q' p4 I** Set the serializers, Currently only one serializer is set as
: s! m2 h6 V( T4 [" v1 Q: X** transmitter and one serializer as receiver.
" t: m$ U: _. u& a6 a: X*/( [6 `6 I; I. o) u' U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ y% k) N \ R) P. r/ a% f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" ~8 r' j/ X5 u2 i, r* Z/ y** Configure the McASP pins 8 l, L0 l* U9 k# {* S
** Input - Frame Sync, Clock and Serializer Rx
# _0 s" P" i! d8 ^3 M** Output - Serializer Tx is connected to the input of the codec ( f4 X9 p; Y' s
*/
( j2 A. U) c; `. iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; w" A) G+ Y% G$ d* m0 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 v$ Y' e% T5 k3 g+ @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ i5 U5 R& g6 y' N" T
| MCASP_PIN_ACLKX# K+ Z! d/ @& a) K
| MCASP_PIN_AHCLKX: y, z- \. q0 R& H, C7 N: ~2 T$ l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 O8 y! x" p* v6 }$ n$ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % n) w0 R6 J2 i5 w/ [! h
| MCASP_TX_CLKFAIL 9 X9 g0 T" t% M3 c& b
| MCASP_TX_SYNCERROR6 Y* l) j! t! \( }% |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' l% @+ u3 w0 J1 V5 P* m| MCASP_RX_CLKFAIL9 ?: H! I. L; k' R
| MCASP_RX_SYNCERROR
* m8 _/ w$ E+ g5 O' O| MCASP_RX_OVERRUN);
4 g8 g* Y7 y Y+ w: Q/ d} static void I2SDataTxRxActivate(void)- b! M6 d9 F1 y& z3 G3 Q( n( ~
{. Z5 e/ J3 y; N7 C
/* Start the clocks */
I- W, ^- m/ g% v0 B" S' H. K! s( CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) D- v( D R7 \2 ?6 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 g; E4 M# ?8 r; @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- ?! s6 r8 W( |& q8 IEDMA3_TRIG_MODE_EVENT);+ k+ H. H! v v/ E5 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 r( c; u5 c: F0 {8 j' h9 D8 ~1 f. yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, x! D9 r; A5 i% U; @. F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 G# L) f1 }" G- M2 F/ m" a) LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& r# |4 V% F' k% T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' h, ? a9 N* y8 j7 t3 @* H. F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ r6 h5 g0 i8 C8 N% U2 }; BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( Z' _' {. t1 i1 j2 ]} 4 m: d- s* F9 X/ t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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