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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* t' Y2 n2 w3 y. s; O- _, e
input mcasp_ahclkx,
, X( \7 Y; [" s9 ^ Einput mcasp_aclkx,$ L9 p% z0 ~+ @) x
input axr0,
: B7 [8 }& X; L. N) o. Y4 v" D- h) w4 \. B2 l; @4 D
output mcasp_afsr,7 M: _5 l$ a) j
output mcasp_ahclkr,
Q! O6 {7 r5 }+ Q5 z, }+ r' xoutput mcasp_aclkr,2 z+ f, C! U8 Q6 M; @/ Y
output axr1,
( i: c1 `* L" y" S; d assign mcasp_afsr = mcasp_afsx;# F# ` n$ ]* B9 M
assign mcasp_aclkr = mcasp_aclkx;
% p9 f8 x% X% k- K# F/ U, _assign mcasp_ahclkr = mcasp_ahclkx;
' a S& @- P- a: massign axr1 = axr0; & _9 b. J2 c$ p* j( p
8 s2 J9 b! K' _' O9 _( j% _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 P3 k8 I% _& ^3 f3 Z
static void McASPI2SConfigure(void)" D& @3 ?7 ] ~( t" J
{+ e$ p2 p" _+ y. {1 e/ ]8 h: }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& g4 c- Q) K |9 z- ]3 E1 x) j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, q% ` M. q- ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 X+ m6 j, h$ O; X5 o+ X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 c! |" O3 A. w; \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 @, W- C/ r* {" C. ~5 m5 I3 P
MCASP_RX_MODE_DMA);1 A2 g& A, z" s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 L3 {$ P. p: M) }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ~% G- J1 f: ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & \+ K+ t& {; Y! X9 D$ u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. s1 N) v1 D5 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 k% W+ Z O9 B1 c/ FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 J9 R& U: I$ v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); O8 e; e$ l; v8 T1 S- j* g6 d6 V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( y& T" j) M: Y$ t2 u3 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 D3 }/ C7 x/ N2 }. a6 k1 g0x00, 0xFF); /* configure the clock for transmitter */, h# A- Q; e8 M# l) I# T% U0 c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 Z+ u6 |: X+ L% N# G6 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! k6 V; W+ E; v) Y! _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
x& ?6 b' G# M; E8 l3 L; D" a0x00, 0xFF);
3 l0 H* v5 T/ S$ T' H$ ?, V! Z) \ |8 H/ X1 ?0 u
/* Enable synchronization of RX and TX sections */
2 \; i5 i$ p' X% D' \- BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 z% I8 s. o; _$ i& c' rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ ~ K: c5 v3 v4 l9 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ X7 _9 I/ O1 {# j$ s1 D
** Set the serializers, Currently only one serializer is set as7 I0 e/ ^/ `6 {9 D7 b4 Y) w
** transmitter and one serializer as receiver./ c+ w- t( U8 a0 x
*/8 z: g4 x+ `( [9 H) _0 x3 F; p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& a+ H E- B- _( ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* T% k$ C- a7 I/ s$ h
** Configure the McASP pins
( n! C; Q i8 l% z# t** Input - Frame Sync, Clock and Serializer Rx
1 R5 w: z" p* t! O" w** Output - Serializer Tx is connected to the input of the codec 2 X. N6 A$ ?2 }+ b1 _) y
*/8 v6 g, w [1 b+ v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! r" k3 b8 k2 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ F5 J/ |6 L' K2 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ |# g- {1 ^; n6 A$ F5 e| MCASP_PIN_ACLKX
! q L5 h- @" S+ K" E| MCASP_PIN_AHCLKX
+ S, F3 B0 ?+ n) M+ D2 o/ B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 w* ~# z f: O( @" G# p8 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / ?. g% X- i1 A
| MCASP_TX_CLKFAIL
) {8 g6 J4 P: b0 @6 A5 L| MCASP_TX_SYNCERROR. o( ^" P% S7 W( y0 h3 m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
v1 f* c; l# ~, {! Y3 e" W| MCASP_RX_CLKFAIL
, Z2 i& T3 k) k2 P| MCASP_RX_SYNCERROR
# Q2 L, B% J$ l+ _1 T. r| MCASP_RX_OVERRUN);+ t# [4 K6 _, ~0 f; _5 W# d
} static void I2SDataTxRxActivate(void)
4 A5 n9 Q* q9 s- @1 E{, H/ {, B) Y1 Z1 V, P+ F
/* Start the clocks */; F) {' e; R. n' b& h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* _9 r; p, S" }5 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: I1 O) i$ L" s; V- AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, E3 ]# |- ~2 q# |EDMA3_TRIG_MODE_EVENT);
4 t) X$ i1 M' m$ l( z$ x1 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& N; U I3 {2 m7 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' e( ]: \) S% l# w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: M4 J. C( u& LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ u* Q z f2 R$ h8 m3 Z4 W: Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 R. B4 A1 q. W4 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: p# }$ M& J5 U2 x( u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& [( o9 o4 B3 |0 \: E} ; A/ d7 b& b; g# m! O( C! K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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