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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 n" |4 m* U2 V; A& ] [8 B
input mcasp_ahclkx,
/ |. B4 E; @6 R& B, n- @" P% k# tinput mcasp_aclkx,
g# X; L" y, |/ u9 @/ ?input axr0,
9 p3 [2 `3 R: N* X) A# V( a8 S
; {# C6 c/ D% l6 Xoutput mcasp_afsr,1 d5 S' e$ f- u1 h, U
output mcasp_ahclkr,; p& ` {0 h1 v; v4 N& W
output mcasp_aclkr,3 z% B/ h: f R8 n
output axr1,
/ Y/ U' ]6 R) d, h assign mcasp_afsr = mcasp_afsx;
( V+ N4 P' i9 g6 g0 passign mcasp_aclkr = mcasp_aclkx;
3 l y/ Q4 c# n- J5 N% zassign mcasp_ahclkr = mcasp_ahclkx;
9 O! C7 s' W1 ?. Z7 `; o8 rassign axr1 = axr0; : A7 I& W5 ?3 |. T( b% \5 G
# Y: {* J& B/ X4 P: o; Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# u* h" c' i' p$ g2 Sstatic void McASPI2SConfigure(void)( U! U L9 }% P% x2 k1 x& v
{
8 t3 q& n- N# U$ h0 v8 \, RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) o# ]& K7 F/ K: m1 k" f9 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* J. y( g/ |- A: v! h. x' ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# c* R( R8 S: }3 SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- N$ `3 q" v' k0 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Y# y4 c9 J3 \; CMCASP_RX_MODE_DMA);
( ]2 i* Q* E& N$ t+ R4 H: T! ^& l$ i5 HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 U1 x) c' n. Z" QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 g% O: X! n. `, J+ ?0 M" x' m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" J( l; _& W+ M6 c6 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( L' r b. V) ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 W) E% [& N6 ^: `2 E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! C2 u* J8 w7 U l" c3 O/ AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ v, A n8 @3 Z( h$ l R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * ^3 H0 P# ^/ _% S* W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," r$ U# I" U, y) _9 I1 ^
0x00, 0xFF); /* configure the clock for transmitter */
0 C& y! G$ q, kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; q" Q& w! U, dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 e* e9 _+ L' s) v9 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 p5 Q& g. [" }: E4 q1 t/ r0x00, 0xFF);* U+ y7 v8 Y: b! ]$ L; M X
" [2 P) F8 d; P1 ^4 Q/* Enable synchronization of RX and TX sections */
$ g) i J" `, j3 |. b$ G5 T( _) zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// {0 F( I' V. C; C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 J6 |' X" K% [; l6 Q) }- t/ j" D$ ]+ n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% p1 U0 d3 e" S6 f4 c$ z6 [
** Set the serializers, Currently only one serializer is set as/ D& X! a/ B% T
** transmitter and one serializer as receiver.
, O; F9 p7 `1 }0 Y5 K' {% G*/% Q7 _( ^* o$ H5 A8 B& V8 }+ ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ n: `% B9 T- l1 C$ KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. ]9 F$ D2 Q- x, w8 s
** Configure the McASP pins
: n9 C x3 n6 V; l** Input - Frame Sync, Clock and Serializer Rx+ @; ~$ G7 D1 q; R4 T( u
** Output - Serializer Tx is connected to the input of the codec : A5 c0 R9 d) R* O1 n" I
*/* h- h9 K, L \1 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ C4 d: V, p& o3 \0 g6 U0 T2 B6 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 E m( r% @7 k% |; FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' I, y: t+ N( q# y9 s8 u8 y
| MCASP_PIN_ACLKX
1 t& T/ b4 q+ J* |" p| MCASP_PIN_AHCLKX
9 [0 D0 V) {/ O; o$ J: j% d1 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 N, l! w( C* z4 A/ [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
L0 o$ s% W0 A9 L' ?; G% H2 {| MCASP_TX_CLKFAIL
5 v5 v P2 p) _. ~( q| MCASP_TX_SYNCERROR
# M7 O3 D: A* v; `$ S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ ^7 y/ G5 l+ I+ a( C" S| MCASP_RX_CLKFAIL
; X4 k, Z }+ S| MCASP_RX_SYNCERROR
3 S5 u# a1 |6 U( M| MCASP_RX_OVERRUN);2 |- U4 d5 M. q6 s5 Y( D
} static void I2SDataTxRxActivate(void)" p/ O& e; y7 ~8 f, ]2 U; S4 X
{
/ m9 [2 N" P7 `7 X/* Start the clocks */+ T$ ?: Y* Z# H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% G0 C6 C) ]8 N2 a- i$ D: u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; k5 H) z! p4 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 M( D. V O) S' f# b: f. a. V8 v
EDMA3_TRIG_MODE_EVENT);
) g8 I+ R: Y9 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - A1 Q7 R, J: \8 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* r. w( T3 Y9 }' H- h; j6 NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ }5 ?' w; n& d" D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ _- q) o6 f1 C9 c7 Q+ ?/ h: ^8 p" k; J fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) w% ~1 K t/ S# h! K5 w, H' a& _8 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); V" d$ x3 @ }; A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 |; t) T% a& z}
6 B0 E: Q4 g* p# Q3 }9 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " b1 g6 w. R; R: \# M5 ~
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