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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( }' Q: D" K7 Y8 n$ V
input mcasp_ahclkx,
& `' b& ~( G E+ y, e# V' ?- w: k) pinput mcasp_aclkx,4 [9 _1 z, `* @5 p3 l5 x) _; s
input axr0,( j, H1 k6 ]3 {0 l2 Q. {5 B
, C: b8 f; q2 s/ E. @output mcasp_afsr,
( p' o0 A$ K$ h. z0 qoutput mcasp_ahclkr,
. [2 @+ Z Q3 H& d* A8 K6 G7 U3 Qoutput mcasp_aclkr,' l9 Q1 b. N# J: O T
output axr1,; D" g7 ^; j2 ^0 I: F& L1 p
assign mcasp_afsr = mcasp_afsx;
4 i7 X! Q o: Q4 o& z6 Gassign mcasp_aclkr = mcasp_aclkx;
8 X; o9 f( X2 ?# tassign mcasp_ahclkr = mcasp_ahclkx;! [' {2 k r) D! X
assign axr1 = axr0;
* c5 N. h1 J) l7 T; R+ t. Y8 t2 C/ q1 q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : B7 Z% E+ I4 I0 i7 W0 ]
static void McASPI2SConfigure(void)0 x0 S/ ~/ f- y
{
" A, {& N. _( x( @# \; f- X jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, y9 I2 I0 S* t7 b) O* A( a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 [: Q! b) W+ F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) a- u* K* H. ]5 Q# |, }0 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. z6 y' s L. [3 T$ O8 q( M6 m9 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ x( W4 P* \* O9 ]MCASP_RX_MODE_DMA);# e8 D, {9 w% D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 i6 J+ w& R B. q% ^7 d* H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 d0 ]5 @7 d2 v; G! A5 I& U( M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 n1 V6 l5 V0 a, D S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- [" U5 B5 F3 ~8 a% s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 |3 s* j0 F1 W2 m' j! C! O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ d% M5 _) W" w( ^8 s6 R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 S3 @8 U3 V4 C) q# `$ H. Q. MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ c% s- }' ]8 \# E$ x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
p! D; n" u7 q5 `$ D! i0x00, 0xFF); /* configure the clock for transmitter */
4 W: A3 p. S. h$ r5 j* z3 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
M+ U! _: O0 q) GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- b5 Q( X- B4 a/ HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, h/ u& p& v) t& ~. s* X. W0x00, 0xFF);0 D1 U% Z2 w, e6 L0 q6 a
* F& L3 ]$ h8 e( Y* M
/* Enable synchronization of RX and TX sections */ & i$ K& A$ I7 l- p" h# H0 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 o5 _2 C) |0 L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) q' d- X m9 G: r, t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. |# j4 z! V: B+ J: s
** Set the serializers, Currently only one serializer is set as
) w# X3 p. h/ h% G: P/ O** transmitter and one serializer as receiver.
( c* {7 b" r) H, k*/
^4 V$ ^3 l0 F, T1 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: P; A: j; K$ C o! A; y5 o4 E2 z% O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" F' i9 H6 J9 C) G( o5 X** Configure the McASP pins
# k- Z6 a4 S4 z3 ]0 O4 y** Input - Frame Sync, Clock and Serializer Rx! Y$ a6 S0 v4 ]+ Y
** Output - Serializer Tx is connected to the input of the codec
! ^. R' s4 k( z' K! _9 Z4 D*/) U1 }0 K7 D' D. z, x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 p* t. l5 k9 f+ X# J; aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' f: W) n" y1 r! z0 x# vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' p( n* I* \4 F( s7 C3 || MCASP_PIN_ACLKX
% [. _; |2 k8 X1 t| MCASP_PIN_AHCLKX
/ c$ b* Y) }% t# C$ y$ T1 k7 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 l) e5 C. A& O5 H% x- ^, b$ UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 k% L( z+ ~* C: r6 e4 O% u
| MCASP_TX_CLKFAIL 6 G" K0 m2 z9 w- [" c' [+ N
| MCASP_TX_SYNCERROR, A* F: b8 Z2 c+ ?- H- T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : L9 C7 g' v; r# J/ R! M
| MCASP_RX_CLKFAIL
3 u! f* n( l, | Y$ l| MCASP_RX_SYNCERROR
! R: w( g2 N9 }( X| MCASP_RX_OVERRUN);6 P! e, f; H8 e) r
} static void I2SDataTxRxActivate(void)5 I" _1 {2 {- M1 I
{
' p! t% X5 ^3 y6 O& \/* Start the clocks */: w( R8 d8 P# z! o% F& |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ M5 y _) Y: e( [' p" W" F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ h# l" S5 R4 {9 W0 ]/ s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; {( R% w% J0 g# x. O. dEDMA3_TRIG_MODE_EVENT);# q, @4 o" k, {& L( c* n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ ^5 c8 s% V }. e2 m3 e9 W/ hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% ?) f: v e- H2 F/ w3 j0 X2 x( ]* S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 R, o3 E2 H4 ~' AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 B. Q3 [/ Z1 R% w8 a/ |! t+ `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) h7 F! _! f1 g- F9 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" d! h& @8 O! n8 D' U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( K- S2 |, V, P$ i
}
( `0 ~- b- Z; P2 Z5 {& v, i+ O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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