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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: i% \! p U8 ^7 A! o% r# c! }: s
input mcasp_ahclkx,/ t* D6 _7 g5 T: w; j& L& A5 ^
input mcasp_aclkx,. L: S7 K1 P0 J* O2 _$ [: s: w O
input axr0,* o4 a$ n1 q7 p6 o$ j: ]8 L
P3 i* c! P) K* Poutput mcasp_afsr,
% u) c q, T( J9 ^output mcasp_ahclkr,2 [, k! w6 N4 d5 }/ X
output mcasp_aclkr, @* P; t; _( J" N
output axr1,
0 z5 K! Y# H0 [; X assign mcasp_afsr = mcasp_afsx;
# m: j$ C5 w4 s; y/ D! r% c3 ]! e- [assign mcasp_aclkr = mcasp_aclkx;
: \$ k# |8 Z$ R2 Y. zassign mcasp_ahclkr = mcasp_ahclkx;+ {* }5 k7 o- a1 `( N
assign axr1 = axr0;
+ [* T w$ E0 D4 i1 `& N6 H; i6 ~ M- M1 A5 s: |2 |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 I4 G) k/ U9 Z% x/ ]static void McASPI2SConfigure(void)+ w J; e+ ^$ m7 f. E: g8 b
{
( @* o3 N$ E* f7 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 U! L7 {0 k5 U/ r0 l k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% [% _$ Y( z$ E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 r$ z: r. Q; S: }0 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 f. {# i6 O' L k; d) `' C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," }: f% R& F* Y6 ?' u! Z
MCASP_RX_MODE_DMA);
, z! k) y4 C9 e/ {. g8 q9 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 z' g8 [+ J( d: a0 Z/ v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 a4 h( c0 ]+ M# Z7 Z6 `( ]6 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ]( ~$ N5 _) k4 S* r5 R, FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! S+ M; y3 H. h4 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' Z; q' p& ?7 v% O/ X' L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' F% \) F! A% c0 E% _. n V8 c6 O7 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 E$ O* U8 c8 X4 U2 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# Y* X+ Q$ @6 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* @: e/ _+ l. k7 i2 {, w/ V
0x00, 0xFF); /* configure the clock for transmitter */
8 O8 m+ J& p+ {' GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 R& Y6 N0 C' R' I2 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) T8 Q y5 ]! z* |7 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, O) f3 k# I/ y. s5 H0x00, 0xFF);4 o. o$ m6 N8 _; b: k# u
5 h) H' ?- r- U/ z- I3 ?- B: b' k
/* Enable synchronization of RX and TX sections */
. _3 N s' \0 s: gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 B6 ?2 j9 \7 Q: G5 |& g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* h* u8 e" M6 |; ^- A# y: {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, N; F0 R9 B& j6 K( m** Set the serializers, Currently only one serializer is set as# e: B$ e. ?1 m
** transmitter and one serializer as receiver.: E3 v" R2 x4 F, s2 p: j
*/7 N+ S% y! t) [* P% [* o1 H; r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ k. [! I& D0 _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. k* I& P- K) k0 j& z** Configure the McASP pins * u* h W( w4 P. D. U, m
** Input - Frame Sync, Clock and Serializer Rx
& A- t2 r5 N K$ ~** Output - Serializer Tx is connected to the input of the codec ! y* ]* R3 q+ e8 X2 X( A0 W
*/6 V- h3 z' A+ L8 e' ?+ U0 \3 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( }# n- x- m( M+ r5 ?6 M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 A3 L$ |, G' `% J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% i( h: J8 O/ k+ G
| MCASP_PIN_ACLKX% t% a5 s& m! `5 w6 {& `
| MCASP_PIN_AHCLKX
5 l5 o+ k# j# f+ Z, q' O) F0 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: l' Y2 Y+ w. L" P9 b2 y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . I4 F" j Q3 D; v5 p5 X# O
| MCASP_TX_CLKFAIL
7 o' I) i* L) o6 I# Z. b| MCASP_TX_SYNCERROR
a1 P" q7 v6 U2 d. m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ K/ o8 W" y3 y8 T| MCASP_RX_CLKFAIL2 z& H' P$ i6 M+ @/ p1 m" ~+ w. B: }
| MCASP_RX_SYNCERROR
+ G h4 ]: t# ^: Q3 r5 @: {| MCASP_RX_OVERRUN);. c/ W' l5 T4 h! I l
} static void I2SDataTxRxActivate(void)2 [; \" _8 ~+ N. ?2 G
{
6 q( S, k0 M/ b/* Start the clocks */
9 }8 G4 T. B7 K5 G3 E, }6 d, o/ KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
\% C- |2 m( CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ h+ F, R6 c, b4 k0 X9 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 S! E& T" V- ]7 f1 J; q, V, ~& L* gEDMA3_TRIG_MODE_EVENT);7 w, b! ^% g& R2 l# q% g8 f# ^( L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 T7 W" c/ e0 s3 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% n% ~0 ^/ f0 N7 v, T3 }- e8 }2 hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) ]) O% e0 w0 `6 S1 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 L$ N! X9 y6 i$ q& K3 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% o/ L& p. }) T4 C- d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
N0 L' X f& d$ D+ N# GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! c" F0 O8 `3 `, J" |% g. ?} ' ?6 [/ \) a% v% p5 u3 N5 b4 p; D3 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 w5 l8 }2 q6 g- C: j1 o A
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