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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( O& M/ F0 k- X7 I" g5 p3 R
input mcasp_ahclkx,
; @4 B1 L8 w- r" e) L* ?& einput mcasp_aclkx,) i* {8 ~' R# u! p* W8 d e
input axr0, P' M) t+ T9 K2 S f8 n. ?8 K9 G$ M
, v8 [+ f0 N! Loutput mcasp_afsr,. l }- S- v+ {( C% A! o! f
output mcasp_ahclkr,
( A+ Q; Z, z- F' } Moutput mcasp_aclkr,
1 x, M4 l( x+ p" h! Xoutput axr1,
0 G6 A9 P6 }5 z! m8 t8 | assign mcasp_afsr = mcasp_afsx;% b' z' l$ e) q
assign mcasp_aclkr = mcasp_aclkx;1 ?# \$ L; ?3 c
assign mcasp_ahclkr = mcasp_ahclkx;. z% Y( y8 \2 M' V$ q; [
assign axr1 = axr0;
) l4 d3 R7 l ?6 d1 u2 H) C5 t& k( W6 N7 M/ X: B; S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % k, T) W- h4 R) p' G0 Q: P: T
static void McASPI2SConfigure(void)
2 K; P: B3 t5 r. l; d{1 b/ B- o. \" I+ o4 e+ k- x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 |7 Y' g9 q! ~" S/ MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ v$ P6 \, {$ Z4 v9 g8 q( @: R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 C9 K. _- g. z+ J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# r* q. j/ r% _" i9 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! V+ F( ]: Z' [, N; Q2 rMCASP_RX_MODE_DMA);( }+ t8 j1 u% w2 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' v6 e: D+ y0 h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 t* O# i7 V& w7 J3 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* }. {- {% e0 `4 J7 Q yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 _7 t, {1 n- K& m8 q$ F. s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # v5 Z" q# Y5 t1 L& T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 {: ?! F$ Y/ W9 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 V7 `* t+ N( z& f. H t) [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , [% D" c4 q, }" V) m% }. r+ w& M7 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 J+ O: z( i* u7 k0x00, 0xFF); /* configure the clock for transmitter */% w0 U8 J) O& e: [3 B( t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 @ a; P7 s6 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, \* G. D: i% R) Y6 L* z4 ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* A1 |: ~! s) `$ u+ c5 r
0x00, 0xFF);8 U: M" R: k7 @1 q
# m1 S& C8 X C3 T0 D: Q* u
/* Enable synchronization of RX and TX sections */
2 S/ Q7 b: S$ v8 ?+ _; wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ `- N5 Z! D0 H% ?( e+ k! _( j: SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ {0 m/ P/ n- M! [% b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( J$ u9 w8 l4 d- A, @& y2 V** Set the serializers, Currently only one serializer is set as/ _# \# v! n- I3 {1 b
** transmitter and one serializer as receiver., D3 l' |" X; L. T9 ?" G
*/
H8 ]8 Y4 l( ~! Y$ f7 }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 H1 ^. t. m" @6 X9 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c2 ~6 }+ E/ O! c# s/ f
** Configure the McASP pins
2 @0 r+ z8 W. H3 c' J( }9 a** Input - Frame Sync, Clock and Serializer Rx5 b6 B; [4 I5 _1 |
** Output - Serializer Tx is connected to the input of the codec
& p( b3 [) P8 Z9 R+ o3 Z m6 a*/
, ~% S. ~" t6 H) m5 fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 R& g$ J4 A3 i; I* R$ \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- O" f5 s Y8 O* wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 g+ P* I' A( I% u| MCASP_PIN_ACLKX y( _( K- g7 k+ Y w
| MCASP_PIN_AHCLKX
8 |1 I7 j5 g) `# U! O1 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 z& Z! T1 h0 H6 K' D9 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ f8 \* g; M3 a3 o7 J& Z| MCASP_TX_CLKFAIL
3 W" D l0 y }& e& r& ~8 A x$ j# ^| MCASP_TX_SYNCERROR
% Z* U7 g3 g, W ^) C; q ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR M' u% C1 x- c5 S, l5 m! A, R
| MCASP_RX_CLKFAIL) Z0 z J5 Y2 F) G: }8 L
| MCASP_RX_SYNCERROR * h; D5 _4 {6 ^* [: N) \
| MCASP_RX_OVERRUN);
% D# V4 p0 i) `# O6 R/ Q} static void I2SDataTxRxActivate(void)
9 R* ~, Y* T9 Z, @8 t- g{
. Q" E/ H7 S S/* Start the clocks */
+ J# O) r# ` S6 DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 j4 E% g+ i, R0 z1 d8 E2 b) r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" V" Z9 y( B) m8 |$ B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ C7 u) e" F. Q# k$ Y+ `
EDMA3_TRIG_MODE_EVENT);
! ^2 x$ c5 C# s. C3 O9 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" w& ~! c/ }9 r& lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 L% u g$ m2 X7 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, d) e: B5 v2 Q, }! H1 i; D3 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 B& A9 K$ U, t$ z$ v5 M1 z5 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. N6 h9 L! g- r- X3 n% p6 C2 H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, W. c- P( o" m) C" }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( p$ X+ g( E- _! _( l: L: v- J# }$ D
}
& i$ }# M+ j8 ]0 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 \2 h" b Z: ^
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