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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 b% v' k5 Z& ?% T/ ?2 Finput mcasp_ahclkx,
% C8 K& Z' z. o/ \input mcasp_aclkx,
- N, t+ T1 x! S+ f3 Y$ Einput axr0,
% d. I. H& b, f* v: @
+ [2 h, a4 B+ E! M# ^output mcasp_afsr,
: [. {/ {$ ^4 K# O" j0 ^* p; Foutput mcasp_ahclkr,
* M) ^- D: Z1 X, I3 o) P9 m/ [) zoutput mcasp_aclkr,
8 e9 E. o. E/ V! n$ K, ?- joutput axr1,2 o; g. v5 r! V1 @, `. G" Q' k4 B
assign mcasp_afsr = mcasp_afsx;& @' k8 _+ V1 }3 l6 ~" i
assign mcasp_aclkr = mcasp_aclkx;7 `" x6 K1 z. o- I/ N3 |1 i
assign mcasp_ahclkr = mcasp_ahclkx;
* X1 J* f2 H, J. ~. `* `/ v7 G, oassign axr1 = axr0;
+ [- I* P8 h, m- H8 J
+ [$ Q* K- O8 p- y5 a/ t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * s6 F& O$ R& _/ R
static void McASPI2SConfigure(void); c3 g" Y6 K' g: x$ Y( d& x) s
{
0 m0 }7 z) f1 K$ d, eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. u+ _ i. _- S: ]2 n* N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! x$ S0 r( O( V, J5 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, @/ [2 y; k, K% O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 K; d. H* n9 g. m( |( \1 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 `! F n7 h2 ?4 S: bMCASP_RX_MODE_DMA);
, F. g% L3 `* g3 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, X/ z# b- H6 G' i3 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 |" P0 O& y- e- e- kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. ]# E& U* o! ?: S; d4 MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# |% @8 h! g, A# HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 o8 y- v/ R% zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, `/ y) @# b4 F/ d. y- D* c# cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) e5 {9 T, P7 x6 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 e: H7 {. y( qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& y: B1 S1 y1 @. m" {& Y9 ~5 z0x00, 0xFF); /* configure the clock for transmitter */
5 I9 L7 m7 w- K. cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) M/ A/ Q4 w0 i: A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& h8 T: S6 k- CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
S& T/ a# L; Q0x00, 0xFF);+ |# F6 r1 M9 b" q7 X
% U+ m9 L: K$ V4 | t
/* Enable synchronization of RX and TX sections */ % K3 c, U' l- n2 d' _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 z9 g; N: v& N4 d' j. HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 W; l: b. G0 a- T9 y/ VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( A. U# \8 I/ x4 V. k** Set the serializers, Currently only one serializer is set as+ a( n ^. z( l, j2 v8 }
** transmitter and one serializer as receiver.
* Z6 K, d' S3 p) o d*/' }* Z8 o% X- u- J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 [5 o; ]( g4 z! N2 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** I! `* h0 Y5 v( G
** Configure the McASP pins - }1 k8 t I$ g5 |+ i( w
** Input - Frame Sync, Clock and Serializer Rx
) ~( U9 v' o, C* \4 Q** Output - Serializer Tx is connected to the input of the codec
. r0 f6 {( S7 q) ^) N*/& X3 F m* N9 U/ m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 J$ y4 I' ^' u# @( r# C. m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" G3 j, q: P, G* G4 u: |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. b, v9 X! k- e: V8 T4 i2 k* V
| MCASP_PIN_ACLKX
9 P; G; ^7 L- M8 F" N! c; H- i" x| MCASP_PIN_AHCLKX# j5 X% V) m5 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 N% Y& X: v$ d( \( o6 P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' I5 X$ j6 o6 G; R2 D
| MCASP_TX_CLKFAIL 0 e6 t2 r1 D" o4 ^. `
| MCASP_TX_SYNCERROR
' B$ ]8 @. D; W# ^% n4 [' Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 W3 f' D4 w* V" H# A! R0 J| MCASP_RX_CLKFAIL! O7 a* R/ |2 p3 F* W
| MCASP_RX_SYNCERROR 7 H v. C" O' A4 j! l
| MCASP_RX_OVERRUN);4 b9 F9 H$ C" i/ B2 R. a1 `' y2 u
} static void I2SDataTxRxActivate(void)
: C. {! m$ O# n, X{; o R# b0 Z/ R7 m* N
/* Start the clocks */
0 o* X/ p3 W$ GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 w2 B/ n1 Y& YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 L6 [/ F+ s+ d' @9 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 F# \. }7 n* U; ?5 h7 _) h
EDMA3_TRIG_MODE_EVENT);; ~+ }) m9 X" I: X3 f7 _% z# R) p2 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* L" E, \# ^& ^) X h0 @# jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// c- t5 F. n; `, u; F2 d. o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 X( L6 e4 j% o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 R7 _1 @; X) }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. w2 N( L5 \- Y2 k) TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: c2 D9 D' k1 f! ]. d! ]- U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. F/ \7 }; b' C- c}
8 n# d; O* I* M1 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
z# P8 z( m% ?& y! M& o4 r6 J. y7 s- X% X |