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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 o' b9 B2 p) v9 k6 [input mcasp_ahclkx,
) Q' c' y( P' q. v: d, _6 ]input mcasp_aclkx,* A4 h# @: z; s$ a8 F
input axr0,4 ?5 ~( H& m" V/ ?4 b
0 T4 s& |. X; x1 A4 ?+ w5 Xoutput mcasp_afsr,( J" V3 l3 w: k
output mcasp_ahclkr,: @ d h y \
output mcasp_aclkr,) c' }$ I* }+ C+ x7 [" ^
output axr1,
% W7 ]$ N+ T3 a" l assign mcasp_afsr = mcasp_afsx;( a: d7 v( |1 I" h
assign mcasp_aclkr = mcasp_aclkx;" m+ t2 r1 Y! A1 I4 b. c
assign mcasp_ahclkr = mcasp_ahclkx;
/ X( g3 [8 a ?# |: k3 _assign axr1 = axr0;
& E& W$ D6 c' S+ |; q- E9 T" G. |' _' g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' A) x3 s. @: w+ Rstatic void McASPI2SConfigure(void)6 Q$ N! O9 s3 P4 m
{$ ~. C* p4 Y, T+ z( ~; J$ g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! q6 B' ?! E% G5 |% g- I- AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 ^0 n/ T! n7 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 d9 X6 w, i$ d5 k- L3 k8 z9 l# gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 e, R4 W5 U4 {" r: l3 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ?) c N. N: a H4 H2 |MCASP_RX_MODE_DMA);
, M, J+ x/ O. G2 N/ V: [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- F4 D1 R- ^: h4 I( L$ U/ w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ o) h' `+ Z' o6 j$ E, {9 p: B& M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / ^* S' n$ h j1 B( s4 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: o0 \) u& N; ^# g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& ?1 F. U9 a9 K. GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: s4 s, V6 Y- e0 T; {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 v0 f @* l9 `; ~- g, @, ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ [& J! {5 ^8 `2 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, d( i* T* _$ Y" t& N3 G* J, P3 G* ]
0x00, 0xFF); /* configure the clock for transmitter */6 }* z1 C/ d( _) V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- M7 P7 d) X4 w- }" t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. `4 H8 p9 B3 ~$ C: m. s" L' dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ I2 `$ W% G; e; |6 a1 [0x00, 0xFF);
8 ^0 o8 V* Y+ \ I0 T) s5 \" k1 y6 s/ r& e( s) K9 h k* x
/* Enable synchronization of RX and TX sections */
1 _" L. p; w- q; T l6 E0 r, nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ~3 M m# H7 t" i2 j1 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( L, J; B9 |3 E- u- S5 a" ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 }& U$ p+ Y Z' g+ N. t** Set the serializers, Currently only one serializer is set as
8 R* l# B0 Q6 b" Y& k** transmitter and one serializer as receiver.# [0 \, `$ ?. ~4 k& ^
*/
: r' Z# B0 w0 H4 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 D# c) ~# g* X F& B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 Q) F- Z2 W( e8 o# f; d
** Configure the McASP pins $ q2 ^0 C* @ d
** Input - Frame Sync, Clock and Serializer Rx$ ~# R& s" h+ _
** Output - Serializer Tx is connected to the input of the codec 4 e8 L/ h. t: V, Q& O( C
*/5 F8 D) w9 L+ @; x7 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 p* P; Z L3 B0 v; ]9 P" o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% y `$ d1 G$ y+ v8 M0 h. S- F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ B, T6 x0 u- H1 l2 x| MCASP_PIN_ACLKX8 r* n7 \! O$ G( Z: O7 a
| MCASP_PIN_AHCLKX
9 r3 U3 W: ?* @6 F8 l4 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' L# Z2 ?+ S I h: F: IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 }* {3 y9 X! U. Y| MCASP_TX_CLKFAIL ; q) u1 K! Z8 A
| MCASP_TX_SYNCERROR
' t6 o. w' q4 K9 f& @- N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& g+ R4 h/ W# S5 n/ G& K5 D; o. e& I| MCASP_RX_CLKFAIL
8 ?- c8 C) I. e9 @" m$ j3 ?6 ~| MCASP_RX_SYNCERROR % o$ @3 t+ [* B: [5 r
| MCASP_RX_OVERRUN);2 v5 ?% l N; Z( G
} static void I2SDataTxRxActivate(void); f" g$ p1 T* C6 |2 ]5 L
{
6 H2 H z2 c5 k/* Start the clocks */8 P: D R n' x, }7 f9 d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 D, T# @# N1 d2 @. @, VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; {; w1 G2 {! y. f x) E- b3 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 |( n" M3 i9 X0 DEDMA3_TRIG_MODE_EVENT);
3 I" Z$ E2 A) |' rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & A6 ]/ c% r7 b7 L0 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 ^' Y1 B# `% e" @/ rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: E9 n4 N& i. j! b! ^. ~5 _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! R5 U6 i: A+ z( _8 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- K' H$ a$ I# V- h& a. I% \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 S: {. k9 y5 [) WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 s1 o& u$ {$ q/ @! Y
}
4 J& H2 I! v; W3 ^, D6 B: @8 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " \6 h4 G0 e" y4 |
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