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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 W# E e2 u6 Minput mcasp_ahclkx,6 E' N. y/ \; H8 u& u% |; j- J! o. K) m
input mcasp_aclkx,& B+ \, u t3 D1 @9 _* f" s
input axr0,
! K. K: V; [) r& G2 b, @1 j( \3 y# h
output mcasp_afsr,
7 f/ p& {) c1 u& U2 N: Q) Zoutput mcasp_ahclkr,
' \+ H# E0 H5 n1 W. _output mcasp_aclkr,: o3 G* G7 U3 Z6 i$ U
output axr1,
6 W6 Q x: V n4 [2 x1 m# `' ^ assign mcasp_afsr = mcasp_afsx;
3 W( [% M8 g1 }7 T) yassign mcasp_aclkr = mcasp_aclkx;
! N; Y! d- h- w0 Qassign mcasp_ahclkr = mcasp_ahclkx;
]9 g' }0 _# C" Wassign axr1 = axr0;
' m: w2 K' F( W8 ]: ]+ E! V' P+ I% P$ t% K' ]0 p; V* y) `. a8 w; c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! q E, I( `' ]
static void McASPI2SConfigure(void)6 M$ T0 [( J+ [
{
% o4 j" k: C6 L- kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' f3 S- C$ `# S( P- G) E7 P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" [1 D& x- h, c, ]4 s2 n& v8 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ _0 j, J1 [( A XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 Z$ Z) l/ L; V9 N' w, h1 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) D* d$ h" h+ V% H- a4 o" v
MCASP_RX_MODE_DMA);
* F% W! Y( F7 S0 l) Q: |+ XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: P/ a$ M* z5 R7 a0 E; lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* U5 c6 L! z; e4 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ o9 t" a: e% _2 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- [: t4 {5 F, CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 [/ f; k0 S& c! t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% A# }8 A/ w6 s" ]" e) i/ y% w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& Z! W+ ~3 \! I* Z9 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 `$ e$ V: v" cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 k' `( o: ~1 C2 S- `( g; [0x00, 0xFF); /* configure the clock for transmitter */
' C& y; q. z- ~: d$ RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& d; J- d4 G- g1 {& e. D% | A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 Z& o' t8 z6 @! ?) HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- K! O. e+ ^+ t, M. l0 v( d
0x00, 0xFF);
" G5 @2 u* B# t1 q* i* Z- @ o
" A, C& ~0 h% C$ U6 G$ I* w& z5 T/* Enable synchronization of RX and TX sections */ 5 ~7 k. \8 |7 w% w) Q0 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 L& B% n9 e+ b+ h0 {1 ?: }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 _! V5 Q1 c2 M$ }3 l5 a1 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ \" Q4 [0 c0 s- s' v: Y2 `
** Set the serializers, Currently only one serializer is set as6 F& {1 L7 e+ {* j( ^
** transmitter and one serializer as receiver.
: i5 L. k0 R0 y% u8 ~, ]; U*/7 }; Q! X) |/ t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' R$ T9 R6 q0 S- B: |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 G+ V( c, [* {1 V3 u4 X8 Z** Configure the McASP pins 0 Z( @" S. ^+ J" _) B; w9 l E
** Input - Frame Sync, Clock and Serializer Rx3 G% ]+ ?3 W3 {# z1 b. ]; ~1 ]
** Output - Serializer Tx is connected to the input of the codec $ p9 p: ]" k: O9 Q# F* B# [& Z: _* Q
*/* H; G) B1 o0 I. s; h# ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 x6 Y: j- H3 O% x/ V5 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ o; b! s1 o8 z; {' Q# s5 _+ s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ O6 y# A5 s# c$ L/ \. o| MCASP_PIN_ACLKX9 V2 `$ @8 D1 { F6 C6 {8 X; `
| MCASP_PIN_AHCLKX
- |2 J Z) x9 Y# U6 }8 U% I T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, n* |$ m! i& e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 _) `8 M- w- a& ~ ~( Y- I& T, W
| MCASP_TX_CLKFAIL
/ V" Z; f& s/ d h8 `" k| MCASP_TX_SYNCERROR5 M8 J3 }- D, G2 y. X( \$ \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; e2 J8 M! B7 z" @$ _ b: s| MCASP_RX_CLKFAIL
' ^6 t- n& |$ i& o9 O" l0 K| MCASP_RX_SYNCERROR $ G2 M6 z4 ~: R" ]3 ^) b
| MCASP_RX_OVERRUN);
/ x( @7 l% P: Z+ b3 L} static void I2SDataTxRxActivate(void)9 U: Q' c( i2 u9 b' w9 C9 h
{
# M. |; t, a" e/* Start the clocks */
9 q' v T1 a/ c; ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); `4 h- p" @7 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- r3 d! J; W* w8 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# f2 T1 Q! q9 a( E& p. p# j2 W
EDMA3_TRIG_MODE_EVENT); p" d! R3 O$ h! }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % U, h+ d% ~; l0 F4 ]3 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% T* @5 k. H) n I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 H2 z. z( i2 O. y9 o) H9 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
G+ L- d7 G6 \ j9 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' e' C( \. G, i s# z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' n: u! r @( _ Q! [" L0 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 M' U) i# W* l} + R1 \% j& b" |5 F e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : V6 k2 f- ^( N3 D2 A
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