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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ w8 T- ~9 t5 M2 S$ i- Y# Y& x
input mcasp_ahclkx,
( g6 g2 `5 [% |+ Y- rinput mcasp_aclkx,5 Y6 P0 ?% c# _7 C7 H
input axr0,* a# Z' k3 v0 Z4 a; w. T
L" r) ]7 x) E3 Y
output mcasp_afsr,
4 R8 \. D+ d: r2 v' poutput mcasp_ahclkr,
$ G9 _4 q+ A" T! @output mcasp_aclkr,: o, a4 Z: |5 z; C/ l
output axr1,: @6 z8 `0 Y- W7 o# a. Z; x8 I0 E* ^
assign mcasp_afsr = mcasp_afsx;% O* {7 V, I; G/ I/ x
assign mcasp_aclkr = mcasp_aclkx;2 s. g) W- b" Z* G6 h8 f
assign mcasp_ahclkr = mcasp_ahclkx;
% z1 j8 D$ r/ E2 `3 y, b2 {assign axr1 = axr0; 7 u# Z0 ~3 X5 t- D
; |3 W# Q# F+ C) q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- M' O6 I6 |9 ?. j3 ]2 Kstatic void McASPI2SConfigure(void)
8 \& l/ @" i6 ?3 F; U{3 Y% c; ^5 V; ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ e4 y& E& y# RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// ^: o- H2 @! V3 R4 q+ L4 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* c3 L6 l2 a, a$ l# VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ Y* e5 _8 }# t. vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 d. w: O1 e- g; @- s+ z; |MCASP_RX_MODE_DMA);$ k3 _% X: z8 @' A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! k. n5 @( x2 s6 D0 J* i T7 a' Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
C, J4 [" d4 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; R. G7 p* D6 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* q; r, {1 T9 _* iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 f' j4 c! U# J0 ]! [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; B% ^/ L* r& q0 a8 T/ FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- H' N9 H" ~2 d3 p2 _& g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & T$ m U( _' V# T9 r! @4 T. w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 d$ R* e4 x/ |3 I6 c1 `9 y/ C/ A0x00, 0xFF); /* configure the clock for transmitter */
: I1 o+ B; d' p6 j# wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. f v0 l' x8 e' i5 m; u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* B u7 Y" T% B- j) _: ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! p- s+ \3 N" i& @( x3 D6 H" z
0x00, 0xFF);
" x. O2 B4 ?( K4 c
0 e1 Y$ d. w3 L3 O! A/* Enable synchronization of RX and TX sections */
' ]/ W! m# `. j0 d. M# [% oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' z; n& k7 J) q9 J4 O/ @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
T( p$ J. u# E# J1 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( ]8 G! G# b4 L o+ x
** Set the serializers, Currently only one serializer is set as6 i: _' Q, @- S* E, r. d+ f6 i
** transmitter and one serializer as receiver.- [' _* p. ^1 Z o7 D2 g4 E) h
*/
6 T! p* v* F9 V$ GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ s, v- `' R& p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 C4 e" [3 D2 T7 n% {; b
** Configure the McASP pins
/ e4 i1 _2 U Z8 K& [9 s** Input - Frame Sync, Clock and Serializer Rx
3 W% N3 l4 F( f* \. e** Output - Serializer Tx is connected to the input of the codec 8 `! r [" u# p$ h# k
*/
5 d7 C# B- T" V" J) L H& v. tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- A8 w, \8 P8 L# b: ]9 `$ Y4 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) E' Y: b8 q4 A2 nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 ^' N8 t4 D# A1 d: x5 T/ M9 M( C| MCASP_PIN_ACLKX
& k; g# ~6 E3 p% \" F+ e. v| MCASP_PIN_AHCLKX
3 B$ t# L# e1 y- k* j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. E2 v. G. {7 wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 t0 @0 I4 Z) t5 A' \5 i4 I| MCASP_TX_CLKFAIL
: y) P- j7 @& B| MCASP_TX_SYNCERROR
1 l$ D$ z- x% r; `8 L( x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 I' D& v, ~/ Y9 [: D7 R- {3 O| MCASP_RX_CLKFAIL* {9 ]- o2 R- }! g) m1 c
| MCASP_RX_SYNCERROR
, }# [0 B* G7 B) f! p, t: v1 U| MCASP_RX_OVERRUN);6 F+ S! O4 N) A& T# W; `) [8 }
} static void I2SDataTxRxActivate(void)
{ ]1 i, G+ @& ~{
6 s4 _/ |6 u' ^0 B/ `6 j' y8 u; M/* Start the clocks */( \- X0 `. \, E. ^( d8 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! @, G$ S- z) c0 g8 \3 ?, wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ L3 z6 M6 ~ P0 J5 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 `0 b( |2 h; w; Q c
EDMA3_TRIG_MODE_EVENT);: Y) x6 K) i* j6 P' i6 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" W) n0 @: S4 _* `" u# PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// Q; d" e* E) b* w3 t9 c. C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- Y& k, v! w+ n) O- nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ L( g4 v1 M- m9 Z8 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( J, |$ J- I/ n4 h3 x( f2 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. J1 D! e. D( E+ P ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 c! F2 Y3 W5 e p) f/ [
}
6 S: _4 n. c7 v# U# Y i0 a, d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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