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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 ?$ f4 g0 n( q- S! E
input mcasp_ahclkx,' Y( b( [) J- C k9 h+ b4 O; z- w( s
input mcasp_aclkx,
0 w Y7 C: x* m4 |input axr0,7 `( N9 W7 q4 b- K! x- b
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output mcasp_afsr,+ J5 D2 U$ H7 J3 p1 S; s
output mcasp_ahclkr,
6 k3 g, W" W- _* G5 coutput mcasp_aclkr,4 n4 N4 k5 z7 H2 ^ R1 O7 T
output axr1,
1 U7 ^' \9 T7 |1 d+ y" C assign mcasp_afsr = mcasp_afsx;
. M/ H( J2 L' Q kassign mcasp_aclkr = mcasp_aclkx;0 ^4 h) F S/ L" I- ]3 J7 l" S, a
assign mcasp_ahclkr = mcasp_ahclkx;, P4 a! C4 S9 k
assign axr1 = axr0; 2 @- T( ?/ D' R* G" b; ^/ ]
7 r: S1 }: V3 `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 U* W* J( l7 d- J# E& Z! a
static void McASPI2SConfigure(void)1 t* {0 G) w0 d0 o
{
& z! x+ l$ E, ^' u/ U9 v2 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 g3 e0 b, V+ J5 f$ q4 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, U' f0 ^. M9 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 x% W7 P8 s5 C* |5 d1 T9 T) NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% g- M2 i$ ]* ~: q* f( ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ]+ z/ H: A0 Q4 ]2 a% x
MCASP_RX_MODE_DMA);. L. h6 a* ~9 R3 o" C( f; D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ W$ z( A. `- V3 D! Q( _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) t) |1 F# ^8 A6 b/ ?. @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 j2 c7 w$ f# }) ^5 u' EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% t7 n1 U0 a! `! { h8 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; @# G: p6 P/ y9 G$ b# W- U2 CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ G' r& v) ]" x0 H" `- o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" v! w( u8 X) J' H$ a1 D: P9 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; M' w$ ?7 _7 F3 ]/ f" A- FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 u. h3 F4 |6 Z/ U
0x00, 0xFF); /* configure the clock for transmitter */2 t0 B [7 F2 Y) o: K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 E! n& I) n$ G: R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' j0 K! t/ ` ~2 i% q6 o7 U5 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 c; r; M7 S$ F3 ^$ E4 b
0x00, 0xFF);% v# B1 M0 a! v; N
7 i2 D. T9 e7 \" |. l, Z2 y
/* Enable synchronization of RX and TX sections */
+ Z. X- b+ t$ c6 }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// }" T' f+ a6 }- \' z- l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, J: ]5 L! p: k: ]1 x3 D; y' E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) e/ G- Y5 n V I S) N** Set the serializers, Currently only one serializer is set as
, Y) S, R1 X3 n1 |; Y, e5 @) N; o4 n** transmitter and one serializer as receiver.
4 o/ E5 g7 h( Q*/
( n; Z9 I/ r5 ]0 d- T" U/ ~! M! TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% [+ g+ a) B( }1 i {. Z9 p4 @! t; qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, n- d5 [' [& b) Y0 z# f** Configure the McASP pins
$ ]% e T+ P# P d n** Input - Frame Sync, Clock and Serializer Rx
* j! e8 g' o( D8 {* d! Q9 @5 N( e8 Q** Output - Serializer Tx is connected to the input of the codec 9 ~# h9 P" s1 ~& b% h/ o
*/
/ x! F& h* M M9 S( v8 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 s6 M8 `0 `1 Y6 `, _7 L) tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, k# f' I& U! c* ]. R( GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 i* L' i4 B1 q6 `| MCASP_PIN_ACLKX
$ O9 h( T2 f( O' E2 c# P| MCASP_PIN_AHCLKX
: h; `& Q8 v: K. p7 w4 J. ~$ i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! M2 X; y; |$ y/ M$ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 ?# x# G0 g. A, e# b& p
| MCASP_TX_CLKFAIL 0 F9 m0 n2 a$ ~( G
| MCASP_TX_SYNCERROR. d4 o4 h1 x( V" c; @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * d9 X1 S5 C% S! g4 g
| MCASP_RX_CLKFAIL
9 F4 C) A, v5 L6 ]" E! U7 {$ g| MCASP_RX_SYNCERROR
* s" a V! f( q( r4 z. N| MCASP_RX_OVERRUN);! Y3 D: Z5 D4 w; ]6 W
} static void I2SDataTxRxActivate(void)/ }$ ?; @: s8 L- x2 Y# |; f
{
2 S V% @ ?; N3 @$ C/* Start the clocks */5 w# w0 E3 M$ e7 t' g4 r! I* H7 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 P) Q$ j0 B4 a1 J% V( @2 a$ m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 i4 j+ B) z( u1 v+ E; _1 ]4 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' j$ Q4 N1 a% B7 N5 ^5 n+ cEDMA3_TRIG_MODE_EVENT);/ }( c* k9 K+ s0 R0 B* ^& _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ ` Q* I$ I* i* k9 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- d5 @, f9 {3 Z6 I7 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( M b- i, b5 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 X8 E# v) I8 H# f a$ \4 K& H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; A: k& R; f/ sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 s: l7 {$ T! E( WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 z0 O! u' Q7 `}
& b( m0 o. G9 I) e6 i P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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