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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ c# t3 ]5 P# U/ ]# N- P' K( O
input mcasp_ahclkx,
^9 {7 d% u2 Jinput mcasp_aclkx,
4 L: E3 X& |+ Q/ l- p* ginput axr0,
3 F3 x8 n, ?8 E1 C* W" V% L; m$ S& u
output mcasp_afsr,# ?4 S) B; D; r
output mcasp_ahclkr, P# T8 e! E0 I8 ^
output mcasp_aclkr,
' s4 I9 C' T, i9 }output axr1,( m. d; L. b# e# P9 ^9 {
assign mcasp_afsr = mcasp_afsx;
8 ~0 H/ k9 }. Xassign mcasp_aclkr = mcasp_aclkx;- p) E1 O( N( f5 [1 z1 C! R
assign mcasp_ahclkr = mcasp_ahclkx;
6 p9 O6 h0 l. R1 H1 ^8 Passign axr1 = axr0; 0 q! x3 v0 D1 x0 S! i" B/ U3 m
! }) L7 T0 ]2 D9 z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- |( \) W' X& V7 _static void McASPI2SConfigure(void)1 I% H8 A/ [+ g. b9 {
{5 F9 W. K$ `, \) z) |- C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ]. v% ^2 ]" d" Z; I7 N( }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. b' Z3 c# l m8 q8 E# VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! y, y* Z0 e* z& ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 Q3 d. W. R {4 B' s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# a+ l4 e" K' k; f/ p0 U2 C/ t) e
MCASP_RX_MODE_DMA);. P5 z" L$ K; i: x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% `9 W/ x# h. X" D& B) ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ O ^+ a) V1 d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # i9 X) r/ G0 M0 e0 Z. H$ W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 ?% S2 V$ q" q3 h2 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : j, j# }! C: n5 Y1 I2 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* I# ?; N4 \* d- Z7 s( @4 t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 w, |8 k" W: @$ J# R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % v# A; {# G6 k+ D5 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( W" A8 q8 T& {" O/ n; V' U0x00, 0xFF); /* configure the clock for transmitter */) Y' \1 b+ d+ W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: S9 P) [7 {1 K5 l% z- l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , |) X0 n& B: N- _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" r+ H; n' }2 v0x00, 0xFF);5 ?' {) \ S k1 d# z$ H& Z
) u4 @% J, q3 r& R5 ?1 v/* Enable synchronization of RX and TX sections */ . O G' t% P- J9 M7 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ b3 X) V( m' i6 Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: l) n9 v5 S8 ]' S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" C9 E: _: F0 F# I8 N1 s4 G
** Set the serializers, Currently only one serializer is set as3 h7 k% L& f6 ^5 b! }% G( a
** transmitter and one serializer as receiver.( X" R# w3 p/ I3 x" d
*/0 }4 {, ^! K0 e# M6 Z/ ^# U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' D2 a' D* @8 e8 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 I- a3 z4 }8 l% x( K2 t5 {% T) }, U** Configure the McASP pins
% |* }% G4 E! X! v7 `' \** Input - Frame Sync, Clock and Serializer Rx
7 K3 }' I5 Y& g5 ~+ Z. c** Output - Serializer Tx is connected to the input of the codec ( Q7 o3 [' A! ]8 M
*/
m' n" S% u4 s% z* KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 h4 X {- G+ O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' Q! Z" b/ M1 r4 m% \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 t" @: x' d, X% f| MCASP_PIN_ACLKX
1 L; j9 U. n" f: W$ @; l% T6 _| MCASP_PIN_AHCLKX
1 F. T, m8 S" N& u0 X+ r7 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' h/ m7 I: @7 Y- C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! s% U) a1 n2 H| MCASP_TX_CLKFAIL 7 m- k) O) v- f' ^! l
| MCASP_TX_SYNCERROR: l( l/ ?5 i8 M: d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 [0 C! ]" A+ ~& g/ b8 M
| MCASP_RX_CLKFAIL- E' m' D: E5 H0 z2 ]" n( g% a# D
| MCASP_RX_SYNCERROR \+ g2 v6 {. M& F! y7 B/ n
| MCASP_RX_OVERRUN);5 |& c; k" W( F3 L& o/ r* K
} static void I2SDataTxRxActivate(void)
3 K& \: I" ^. P. ~; k- a{
1 ^% ^ u3 L/ ^" A; P# p/* Start the clocks */. U4 ^1 | `9 a5 t, O. H' i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. U k2 U6 W% y9 G+ l. J! l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 a. _9 P1 C1 p- E9 f. C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 Y+ N6 o, W" LEDMA3_TRIG_MODE_EVENT);- R& ^) L- @% T+ T3 X' Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) n9 n# j7 l' S6 n3 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, H: C# R( a& C0 l/ g% T2 s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& F' Y/ S4 I% q5 V: T Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" X3 W" D6 P6 l, L" J( h5 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 w# m% q+ ^, C) ~" _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% }( j. `% J& ~/ n) o8 c$ X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
i2 H5 i& J/ V& u% E} 9 ^: l, F- ^. p. Q1 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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