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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, S5 j4 s' ]; X& I2 H7 u5 Y
input mcasp_ahclkx,! h8 Z2 R- x2 Z2 g3 J. v5 b
input mcasp_aclkx,7 c" @# }7 N: T$ a& _
input axr0,
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output mcasp_afsr,6 ]- t/ ^, f) N1 D% i X) b) a
output mcasp_ahclkr,; Y) ?) t& }' w9 w, @1 q7 Q0 y( z" m
output mcasp_aclkr,
5 M7 t. y t' [2 Qoutput axr1,9 U5 Z) k K a! C* z
assign mcasp_afsr = mcasp_afsx;
) U5 i: k- x" `% T; Z( `1 iassign mcasp_aclkr = mcasp_aclkx;! w) P$ N) c5 d1 P8 h
assign mcasp_ahclkr = mcasp_ahclkx;
7 P2 a7 e) b/ n; g! @assign axr1 = axr0; , b; D7 {) c- s/ t6 |' p
) x# d& t/ Z" M ~; p- `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" I7 z% w! T' @1 h$ h& Qstatic void McASPI2SConfigure(void) q4 |1 w+ X: x4 M! q. i) t
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 K. D* g. ?$ ]+ d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( p" C! Y9 m5 N1 o: _8 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% N7 T- v8 x4 z; R, e! r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 v6 Z# q ~: y; @# _. vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 R* p' c% m( y: K( E
MCASP_RX_MODE_DMA);/ ]4 z% e* Z9 P6 O8 h! z/ h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, o6 [& _, L; D& G, E# qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 Y" c2 x W7 j. f3 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 d+ X4 [! k, @9 J* L9 J6 N0 L! fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* h: L7 L+ p+ S- L8 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# J5 s* x0 o/ N7 w( _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: m! |& I8 [1 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 S( Y5 e6 S7 I& j. }) BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( E: F$ {1 n2 ^4 ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, {. e, Q! X# T8 u1 R! b0x00, 0xFF); /* configure the clock for transmitter */
* g) g z, W1 \7 i) z: gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ m. T. k& H' ]! CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& f& P8 Z& v3 [- j7 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 P0 ~1 U/ a! b" n& y% t0x00, 0xFF);; Y1 F. \ I0 }1 }
( d8 B/ E$ ?7 z/* Enable synchronization of RX and TX sections */
: f `0 u! B( B4 y+ QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" ?2 S0 R& |! m# V2 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, g5 u0 }: K; O) {- N7 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** l* Q/ d% C0 V! y
** Set the serializers, Currently only one serializer is set as8 u- ^, B! H. P
** transmitter and one serializer as receiver.2 L# w+ D; {0 C; z9 m8 _& s8 @
*/
7 l# m7 m1 @) c8 X \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! i9 O, x# { Z: Z4 c dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ s. i0 e% l/ a3 R; e
** Configure the McASP pins
5 F3 p( u. `( V% h7 C9 b8 B** Input - Frame Sync, Clock and Serializer Rx
, t! X& F; M; c- c% [$ J: U0 X** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' u' ^7 r v, W- F! a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 z' _1 ]% B$ M3 I5 A x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 B7 U" N2 x" h' n7 n: R# P( Y| MCASP_PIN_ACLKX
9 m; L/ L, N# R Z| MCASP_PIN_AHCLKX
5 [' Z( X/ S6 I2 y9 u' `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ S( O G3 T& w1 D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " A& I- C9 i J8 M2 @) p1 j
| MCASP_TX_CLKFAIL $ Z+ }7 j' Y# \: E2 I) y
| MCASP_TX_SYNCERROR8 t5 G D6 i# q. n. X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# B0 a+ l% J1 w4 U/ ]| MCASP_RX_CLKFAIL
- H& i6 b$ U& @! W, I" `| MCASP_RX_SYNCERROR
5 C8 [* L6 A% m8 u; U+ T/ ^& B| MCASP_RX_OVERRUN);
% S6 C! b% \5 H: R/ [; g} static void I2SDataTxRxActivate(void). ^ q) j4 H' m( |1 T7 s
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/* Start the clocks */+ A& l- q5 k0 I4 Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- t. M, n" L6 L4 g- z. |) H$ q3 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# T4 \: W3 n( K" `; s" Q; {/ X4 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 Y) P( h$ W, D4 H' L! Q
EDMA3_TRIG_MODE_EVENT);
& d6 \, t' Q0 c. JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , E4 J6 V6 J1 V1 E' p3 k7 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 p; w8 D! `* s( N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; R9 K! e- o- dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 X7 [' X6 B* ^2 t0 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 g8 g- H/ x( t O3 M8 D$ Y4 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, J% v* h( q# _* o- M9 Q* y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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