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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ p3 d/ u+ t. L5 ginput mcasp_ahclkx,
1 Q/ y. a" Y5 [input mcasp_aclkx,
8 t- O. }( N/ ~. yinput axr0,
9 s) ^! t; |' e$ E' Z) A" i
, M) ` Q8 J. a. ~4 joutput mcasp_afsr,
s( x0 P2 I; p( }7 n1 u# qoutput mcasp_ahclkr,
$ p3 e, M6 Q8 v6 A6 q0 r& Toutput mcasp_aclkr,
3 _. J- {9 F$ B) v& u. moutput axr1,) @; B c3 ]/ k" B
assign mcasp_afsr = mcasp_afsx;
1 O1 g/ T& Y) ~- s; P4 r- ?assign mcasp_aclkr = mcasp_aclkx;, d1 B# A- O' \( J* i
assign mcasp_ahclkr = mcasp_ahclkx;1 ?7 k' u" x. ?$ G5 G; @5 w
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - k, _6 O) `( p+ r
static void McASPI2SConfigure(void)1 m" l2 N$ B5 x
{. r; O: Y: {1 F; ?$ A0 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" Y; X3 z7 ~4 M3 \% X% H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
y2 @: s$ c( kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# A2 P; u0 P' N4 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& p3 f9 c# L* @8 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ y: H% P5 z! X g2 wMCASP_RX_MODE_DMA);
0 h( e3 q1 H! x: c# S; [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ u* z8 o( f) r2 x6 P' S }) n' h2 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! k9 {3 q! l8 `7 t$ j' F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ r y/ g5 o- \3 ^1 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, x/ d3 b8 `8 U" r2 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: M6 W. l2 ] |9 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* w- C# p2 P) r8 l1 T E; y i+ eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 j; \1 a1 @' g8 ^# u% ]" DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ W7 U0 x$ f- U; Y2 M; xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 o% x- O: L0 q
0x00, 0xFF); /* configure the clock for transmitter */
4 P! ] q" D! [/ V1 e$ o1 Y4 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# _( m [/ S O; i! {( |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ g3 c2 R8 E# I) y; n% t) p, eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. y6 @; ~6 T9 B' q7 U0 O5 y0x00, 0xFF);! v1 S% v" Q! u R1 h& u
P8 ^& [/ {, A8 @7 P7 J; n, Y: v/* Enable synchronization of RX and TX sections */
# X0 V0 c. ^* {4 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// `) b; n; E+ P' q2 K5 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 B! w7 I) i8 k. }) G0 V$ h7 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) S) ~& h- F4 e4 t! ^ E. z** Set the serializers, Currently only one serializer is set as% @) ]4 X; e# @- u0 p2 z1 X
** transmitter and one serializer as receiver.; R% n O& E$ r( V
*/
. T! L7 P8 {) @) V# uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( `. b' g. `% c% c- R8 FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** [2 ~9 E4 y6 k! F: ?2 z
** Configure the McASP pins - o# d% x2 w5 a9 k/ J
** Input - Frame Sync, Clock and Serializer Rx
+ \( o5 e9 n- F! O2 [** Output - Serializer Tx is connected to the input of the codec ! j. X7 J8 b9 a
*/
1 i2 C G5 w1 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* H9 d2 M i5 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ X5 ^$ U7 j1 e! UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ |/ g! M+ O6 [$ J& A2 w
| MCASP_PIN_ACLKX
+ A8 h9 a, r6 z/ x9 h* P| MCASP_PIN_AHCLKX& |! e0 p2 W- ?3 l# K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; f- @% `, U+ F+ Y& W# ^3 P; MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * C( Y. R$ e, n9 O
| MCASP_TX_CLKFAIL
9 x2 r3 F6 q t+ K# F| MCASP_TX_SYNCERROR a; ~* J/ R( M; W/ I# B" M7 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) ~5 c7 B9 h7 F. m p# j| MCASP_RX_CLKFAIL
7 l0 n$ t# v3 e! H+ n1 C* _) @! O| MCASP_RX_SYNCERROR 4 f: V' o6 }# B! ]% U4 K8 a
| MCASP_RX_OVERRUN);
! B1 m3 a( M0 Z* j c: u! ]; `} static void I2SDataTxRxActivate(void)
* V6 h9 x' s0 h8 {7 Y/ f+ a3 T' E4 ?{/ @/ X. r/ F; |# f' d. r- p0 o6 P
/* Start the clocks */* G5 b p. {. z# d( M( f( `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% n) ]" _% c, \% a+ vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 c7 m$ `# F! z J: x9 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 {6 s1 F8 \4 Q
EDMA3_TRIG_MODE_EVENT);
, U* e/ l, l+ H# fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 e8 w. n9 f- @5 k4 a* k" M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( c1 o( [" B. s( ]+ T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 e; l& L, Q. S% a$ C, n4 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: T4 T+ M; k W+ d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 v. S3 E6 X1 I6 p% D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 E! w& q( y! q2 l" FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: S5 C7 Z5 a$ k/ c$ d( S2 I- V0 o( m
} 1 Y% J: ]+ Y5 L% a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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