|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 F) P$ ]8 p8 Y. o& iinput mcasp_ahclkx,
9 Y2 C+ S3 A0 V! }input mcasp_aclkx,
0 d6 N# K9 b- p4 S# p& K; y5 ~: sinput axr0,# V1 F$ w1 }4 I7 h7 f
6 e( y" P: M4 Qoutput mcasp_afsr,
' N. D; _1 F9 G! t0 ]output mcasp_ahclkr,% f5 l( Q! r# z& Z8 i7 ^8 ^1 M
output mcasp_aclkr,
% g I* N$ s: L8 doutput axr1,
( H( C* E. N8 A W: t5 d' t assign mcasp_afsr = mcasp_afsx;& V! ? x0 F: i( ~ u0 g
assign mcasp_aclkr = mcasp_aclkx;1 f7 l& X1 ~* d2 ?
assign mcasp_ahclkr = mcasp_ahclkx;
9 m, o% r- q: ~2 w2 S: P9 Qassign axr1 = axr0;
# t X. y% I$ |0 u5 p: G7 K9 N8 m0 j+ `0 ~. l8 q( `! d+ k, m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 |& z) {( S9 E* j2 z+ Qstatic void McASPI2SConfigure(void)) } |9 v. G% g
{
# M5 D# T" U$ y" T! Q, q M8 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! V% ~! `- d5 [4 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ I1 z. O3 A2 Q6 }3 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& W4 q9 b; q' w7 f' @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ z9 E& g' X. p/ l3 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. W: v( f1 }, ~% R* O0 S* s* ^
MCASP_RX_MODE_DMA);
( S6 o2 e2 k2 B" m# S- A+ i% M3 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 E4 D u4 ?7 S2 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* j& U" W# X6 j0 J/ l. O' i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - m6 F) Z. @9 `7 x. m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 K: A. u3 c/ S/ c# P. j* a0 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 u1 s# S4 h. {" ?# q# ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ ^( n, c' @' e% e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ w/ K( Z3 d1 ~) a4 U" V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 J$ |! i1 G+ E- p! _9 ~7 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ f4 ^/ f9 G! X" c, b" h
0x00, 0xFF); /* configure the clock for transmitter */
0 K" a- D3 r2 i; VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 `% j" y8 j- W1 S+ k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 V6 t7 d* I d' L; QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, d w2 P$ j5 J7 y2 I2 ^1 ]; ^$ `
0x00, 0xFF);; r9 y) A- z8 F) r- a+ `
m$ m t0 G8 V: u5 e* e" m
/* Enable synchronization of RX and TX sections */
3 X+ {8 V1 j5 l8 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 x+ O4 w% y3 O6 |0 L* x9 {5 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. g& t% I* ?$ b6 m0 A: ^9 r( A) R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ z- D. {: y3 h. \# e* x
** Set the serializers, Currently only one serializer is set as
. T7 y" M v' v0 T! e2 H; s** transmitter and one serializer as receiver.. {3 s. r W! D" F8 `$ Z, J) w
*/
t, r7 M* O- `' w* mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ M" b X7 t1 A* k0 O$ j! sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" n s6 g4 O9 f6 E** Configure the McASP pins
2 W$ B6 O# q! Q6 S2 v7 J** Input - Frame Sync, Clock and Serializer Rx8 \6 }" b2 g) d; A. t/ S* f
** Output - Serializer Tx is connected to the input of the codec ; N1 E; X$ C% ]& S: y- G$ Y! K6 ?0 e
*/
I% M H3 }! D6 A4 O3 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 M! T1 p* A7 j6 s" T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( E$ } J) k- x' F7 e2 G! g: K0 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 _; p- m0 \+ K( j- [* t| MCASP_PIN_ACLKX5 r M3 Y! |9 q
| MCASP_PIN_AHCLKX
( h8 S3 g* _* b( ^! q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 e& d+ U1 ^+ E6 S) g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 |/ h, n* ?4 K, z7 I
| MCASP_TX_CLKFAIL & r! N) P4 J. U$ W l$ Q* D% U- X) V
| MCASP_TX_SYNCERROR! U& X1 d# U+ m, `" \0 g3 \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' H; c5 B8 k6 `! D! r
| MCASP_RX_CLKFAIL" v; g6 t$ y9 h- K/ e
| MCASP_RX_SYNCERROR ; o% m' i/ z7 Q- V$ [
| MCASP_RX_OVERRUN);( j9 q6 G4 c$ }+ n! N7 C
} static void I2SDataTxRxActivate(void)
z! ~9 G3 X. n{0 ^5 E6 `, W6 }4 _! P- }* g k! }
/* Start the clocks */5 O% V3 u! Z% W$ W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' \2 u3 U* V3 L! PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 E1 N! _ ?. T" AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: M0 S$ s0 |' g6 |: C
EDMA3_TRIG_MODE_EVENT);
% R) R3 M. U' @' MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " W- \1 D) o' y8 F- C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 J$ i! L3 G. U* |0 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ h; i9 G6 k5 e' Q/ ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; H% w( f; V0 X# B+ |) Q5 K& W! A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: ?% h% s1 K0 l! Z0 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, D# W. k( n' r9 A0 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 @& `' p+ h* N+ x* A- O
}
9 Z! j9 I" h& t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 [. U2 _( t# q+ k
|