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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# w2 A2 Q; q7 U5 Z. Q4 u# Y
input mcasp_ahclkx,
: S. U6 g V6 D* pinput mcasp_aclkx,
& `* _) b' p% A4 O1 w: Q9 s5 Minput axr0,
$ G/ M% { O4 F" G1 e, l3 L0 q, | C* {" Q* H, S3 \ \) @1 u) @
output mcasp_afsr,
$ D" y% ]( p' q7 @9 V3 Doutput mcasp_ahclkr,
~+ u G# M7 `) X O9 `* koutput mcasp_aclkr,2 C9 i7 g8 b/ e' D/ U: q0 b
output axr1,8 Z$ X9 ^3 A, _+ ] D# Y
assign mcasp_afsr = mcasp_afsx;
8 _' R: t! O' y0 fassign mcasp_aclkr = mcasp_aclkx;
7 q' S! @! t$ Y1 ?assign mcasp_ahclkr = mcasp_ahclkx;
( Z) \ Y8 e" s+ j; u( r4 fassign axr1 = axr0;
; R" t/ y# y6 Z
2 C: ~) j, P( H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' i. u: U0 ` Z( w; gstatic void McASPI2SConfigure(void)
' j- [# ^ T R' _! `; F% F' `" y{
) x+ O/ s% R# x6 I+ L% H2 z$ ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);: W4 H8 N1 R7 K6 q4 E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! W( s1 S3 J$ j: rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 Z+ X* g& D2 ~+ _9 ^2 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& G r# H1 S8 h7 a& s HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 o7 R B: A0 E9 w
MCASP_RX_MODE_DMA);
3 R2 h9 I6 x/ s4 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 A( ^7 V( h: I# \: ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ m2 r# a+ A% n. O7 l# Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ [5 `3 p9 V8 x# a: a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 e. f$ D5 r& C+ g" T# j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) I" a! O6 @' k& b( Z% lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. u' q: r b2 z3 g- z; Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 W `0 ]: G! B- ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # {% t- C* b2 M0 ^. ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) z5 S+ @) B0 A* E4 l0x00, 0xFF); /* configure the clock for transmitter */- q' M0 |4 _6 N: o" K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 J: `8 X& q. G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - o/ T& m* k( X5 q7 a! D) e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 S# e" Q1 N$ J' }) Y
0x00, 0xFF);
0 p# z2 R* b3 h! M6 m1 C* b. i( K/ f, x: z- V4 G
/* Enable synchronization of RX and TX sections */ 4 K5 ~/ W0 K3 n: T9 V/ j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: w- e3 w# s. z/ }: q7 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( z: p8 L( h j) Y1 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 f2 a8 J7 k6 K$ c t, L1 H** Set the serializers, Currently only one serializer is set as
" {/ J5 ^. s. \; r. c8 D0 E. \& s+ B** transmitter and one serializer as receiver.
. C2 o& {- ^ c( H*/
% S/ O! c" M# D6 X/ m( [, P2 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 M* o- `/ O$ z- N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ M! q z0 Q0 R9 h% a: e [** Configure the McASP pins
) Y$ R+ c+ u3 H" m, Q7 ?0 l/ Z** Input - Frame Sync, Clock and Serializer Rx
8 D) l: f$ y) t7 ]; o/ F8 k( G** Output - Serializer Tx is connected to the input of the codec
4 e8 V2 ~# L2 Z*/- k7 m; t6 Y l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ [& F. {, n g* b4 r6 j- z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ h& t8 a/ u+ G- e$ J) p6 t4 J1 ?' UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" Y5 b" B5 \& q% M" J- v0 T| MCASP_PIN_ACLKX8 g0 I$ A- c- c" Z
| MCASP_PIN_AHCLKX
4 S8 ?6 ^2 G- ?; D1 \0 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- w3 D6 t6 F6 L6 ]3 r8 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " m% W. d) _/ {
| MCASP_TX_CLKFAIL
. E% \% t' v2 {0 t" L2 A| MCASP_TX_SYNCERROR
9 v6 l+ r( Y- o& g! j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- w8 ? w2 D$ }( F' P9 x- U& c% s| MCASP_RX_CLKFAIL( A: r7 a* Q, W1 M1 m* X
| MCASP_RX_SYNCERROR 7 }' V# }& l. s
| MCASP_RX_OVERRUN);+ e8 \% e6 j4 s( Q5 \" u. f/ S* O
} static void I2SDataTxRxActivate(void)9 f: j' b- C. z: s9 T' a4 h
{
5 ]! ~1 L* z* C3 E, A( Q) R( v/* Start the clocks */
3 q8 d" n6 c" j7 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: h- l" v% H! N4 Q, q* DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 I% p0 h* l' l7 f" F6 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" B* p5 s" s1 zEDMA3_TRIG_MODE_EVENT);
1 K- U/ F9 [1 g# @: ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + ]' q# a) c, q U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ h5 d" W/ b+ \7 EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% l( F* X+ u2 I# \, BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 k; {6 `0 m, E2 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 J3 H7 D& r# W- B) R8 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 Z' y4 S2 Z9 ?. Q) U4 w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 s2 x3 L" P! _2 Z9 Z5 V} * q9 Q1 l3 }. t+ [8 ?1 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + p* k8 l e* r% g* ?7 ^
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