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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 u) ?: v3 h' M
input mcasp_ahclkx,5 c) _+ d$ [% v
input mcasp_aclkx,( A$ h* g1 i. C5 y: ~
input axr0, a. e1 T3 d2 C- H7 \" `: Q
9 d- h- b5 a4 _% u( L. }4 G) noutput mcasp_afsr,
" w+ h! S" H" Q2 voutput mcasp_ahclkr,# S$ S3 V, E' b. ` t9 K& O
output mcasp_aclkr,$ |3 u& f% n0 i5 w+ |. P
output axr1,
0 m4 l8 F* y \8 @+ h% s assign mcasp_afsr = mcasp_afsx;
N G8 X1 Y) A, Bassign mcasp_aclkr = mcasp_aclkx;
6 W: [, P: {! {! m1 i s5 tassign mcasp_ahclkr = mcasp_ahclkx;3 m8 D, w4 q' ]# U; \
assign axr1 = axr0;
( m! N; t% y1 {' a% D3 D" @- e+ C( S) @. B3 W- f5 ~( v8 r+ b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
_% D: s2 n! Q! y1 Q7 o* fstatic void McASPI2SConfigure(void)0 \1 a5 j- k1 h+ A7 A. k
{
+ x# {5 c* t0 f/ F* ?7 }1 d7 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 x3 ?6 r2 i7 E$ d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ w! l4 t5 n/ gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- S: m$ o2 n9 k5 x! q5 ?% E1 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& D7 O* s. ~' \& D2 b( s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& h" C p1 ^, A! s8 Y
MCASP_RX_MODE_DMA);
0 T7 p/ |6 {. ~4 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( o. n: w- R3 J% ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; M4 L W2 m! e% [9 ]2 w' j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 E4 u5 a! W, k; m6 S- c9 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* A( x! N+ @/ E) D8 MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 k% y% L2 i N" g* i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% H. ^! q" b4 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) U+ ]0 U9 f$ o6 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 j) {& A8 G& F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 t4 y! w' A- t9 r0x00, 0xFF); /* configure the clock for transmitter */
% B' G- \ \0 k3 i v! j- \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 X L3 i* z! Q' sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , @$ b3 e/ C7 \1 V& d, Y5 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; o& d- l4 f) Q: [# X, S0 I5 r0x00, 0xFF);
) F- G. d- c5 \
2 n- P. Z \9 ` n/* Enable synchronization of RX and TX sections */
! ^' ~$ U6 n3 Q1 X" X' p* |! kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 H3 O! P! o6 v2 U" M* p5 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ k- @: Q9 E, d/ Z; ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 V4 ~1 {: u' I0 r, F, G
** Set the serializers, Currently only one serializer is set as
7 A' ?" C/ K# t** transmitter and one serializer as receiver.+ _, @ q6 C& m0 z5 b- s5 Y
*/
' o9 w0 y% [4 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. n( \' l& I$ B1 i3 A6 E1 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) C7 _5 R& y7 \8 C6 D- R% H
** Configure the McASP pins z) |4 |9 N N6 S* U2 F, c" g
** Input - Frame Sync, Clock and Serializer Rx
' C* W1 ^6 W ?% j; i6 w** Output - Serializer Tx is connected to the input of the codec 7 E! h: F+ q2 d" ^+ ]5 }. K2 k
*/
4 g7 c d4 R7 x1 g$ V* p( u( yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 _6 @. j! ^5 J/ r; D. E7 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& T6 b% v9 y) `5 W8 u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" n) w2 Y. b6 m* U6 t3 j| MCASP_PIN_ACLKX% p0 l; R( E' H* P
| MCASP_PIN_AHCLKX2 j& l3 E( E4 U- a- n9 t; v3 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 X* L* Y' |) S( u$ DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 V. |: ~& \% Q' E3 p2 F$ y
| MCASP_TX_CLKFAIL
; Z0 U& d% |1 c8 o$ g7 D| MCASP_TX_SYNCERROR- @2 i! k0 E: |7 P; A: Z& a- u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 ^9 @: i+ n6 _| MCASP_RX_CLKFAIL
& o; z% y) \! f3 r| MCASP_RX_SYNCERROR . r6 N$ W/ f! x( N L4 }
| MCASP_RX_OVERRUN);
! ?7 a0 R- T+ Q* z} static void I2SDataTxRxActivate(void)
* j' K, `, Q& F4 J/ c! |{2 s( z* J! K3 v# w
/* Start the clocks */9 S0 z! q* W9 |& r! l) C1 y- R/ v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 a/ A; A9 s9 u( kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 }# x, I8 j- v7 L3 c. S: z: |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' k2 N! V& d6 g# g; g9 T4 QEDMA3_TRIG_MODE_EVENT);% H- H" E" x/ [) t, J1 ]! P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' b! O0 }8 h4 P" V% d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ y% |9 x; }% e5 u( C5 j; u/ U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& p7 f1 ~0 _$ H! W- C# qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; w; [3 [& Y2 K7 b! T; Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' V+ \* \# I& v4 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 z2 d+ k5 B! ?0 w7 ]1 d! wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ T( I" u7 i* |3 q}
9 p) S, q: _2 w: W0 r: Q( ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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