|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 V/ D2 c0 ^+ [( q2 d6 u* tinput mcasp_ahclkx,/ y/ O S( v; M; W1 O
input mcasp_aclkx,
) k3 A+ _) e3 ~) x( F- oinput axr0,
* C: Y2 }% M5 F+ s5 r: {& g
+ n/ ~3 I: u" C; V6 P) ioutput mcasp_afsr,
( a2 B0 O! V$ t2 k4 C- Xoutput mcasp_ahclkr,
/ s4 c# z0 M) n% Toutput mcasp_aclkr,
: H7 j' f" Q+ A( s$ b3 Qoutput axr1,
' S6 K9 U* b5 P1 w4 ]! r4 ^ assign mcasp_afsr = mcasp_afsx;: F: Q) g* d! w k! ~% P
assign mcasp_aclkr = mcasp_aclkx;
& V/ ~9 Z4 z. j, X' Xassign mcasp_ahclkr = mcasp_ahclkx;
/ e& |, K# \, i. o; a* _) z4 w" vassign axr1 = axr0;
! R8 y8 l/ o8 W7 H8 D0 H- ?# ~! M) t4 Q% |* L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 a5 r/ d8 d; ~static void McASPI2SConfigure(void)* `& W+ u9 w! O
{$ B# o7 P/ ]( Q( w3 [$ j: T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 P, ` B0 @# A+ h, |1 q+ ]( @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 l; N K# U: G4 W$ L# O2 \+ q q9 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); P8 U: b# g5 q% j |) S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 M1 I9 z! Q& w, t, O7 G& X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# o" g. f1 w6 j# Q6 R3 b! o7 BMCASP_RX_MODE_DMA);% _7 m0 s: j% m Z/ P( w3 k X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 }& I2 m) C. m- }9 N6 Y% ~' V9 HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- X% e$ Z* m! ]6 m3 o" E) f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 ]+ B. K4 D# Y* W, |# z' ~3 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' p. L8 M" l: t5 ]8 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! e7 l: S' v w$ dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 ?, e. p5 ^; v8 L! P" k8 B- [5 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' Q" k) a! d$ U6 Z1 M, k3 m+ v. k' rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: n# r& @% I. A5 M9 b) nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, c) o- F% v- u* W; w: @0 T O, |
0x00, 0xFF); /* configure the clock for transmitter */
. N3 M' _% x( y h0 ]0 K! E! G a+ ?. X& OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* P+ q/ F {+ O8 G# ?( ?0 m" jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 e2 Q) Q3 @, h9 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ ^' I- v# a* B) L) v8 ~: o! x& L
0x00, 0xFF);0 J+ S$ R) p- R- {, J; J1 B( V
( o8 h0 J$ C5 O, m D# }
/* Enable synchronization of RX and TX sections */
4 @8 W; A3 i" A" UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* P; G3 O- F# wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# _+ m f+ W& N5 |" ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ @( ?- a2 V# \$ \* C! _
** Set the serializers, Currently only one serializer is set as6 R! s( @' p7 p7 U
** transmitter and one serializer as receiver.3 |6 Q* N" y$ [7 v) h6 b
*/
4 s; ^: y4 ]6 W* V* vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 h. g3 t! I! P2 [5 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 Z: n8 c& q9 q& J8 E7 R
** Configure the McASP pins 2 u( u* i4 l% N$ v7 z( v5 r
** Input - Frame Sync, Clock and Serializer Rx
2 T5 f9 s5 h3 X** Output - Serializer Tx is connected to the input of the codec
}' c" s# ?7 l+ e, f; X; Y; s*/- h. M% X" x' [8 ^% w) s* R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: z( V& h3 Z# h7 u- x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' c1 c4 M9 g ]) e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 D6 f" I" V) x| MCASP_PIN_ACLKX
# |3 U- @8 u6 B; [1 E p2 C* B| MCASP_PIN_AHCLKX* q. g$ A1 j5 F' Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: X; \$ k6 f- N9 x0 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; h. y o. ^# x4 M* P$ c% _| MCASP_TX_CLKFAIL # Y: b, c) f" X$ {
| MCASP_TX_SYNCERROR/ l* i+ c$ [0 H; o; _$ ]& a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, d! U8 p' _1 ^* B1 F| MCASP_RX_CLKFAIL
' ]6 F* o' h3 G5 y( I8 l$ p4 P| MCASP_RX_SYNCERROR + B( e0 o6 r: w3 o5 o
| MCASP_RX_OVERRUN);( W' b6 F& D* B9 g
} static void I2SDataTxRxActivate(void)
9 w) N) C% @ e6 k$ e' t* x{
, E% n K2 U, c3 y/* Start the clocks */2 [+ h3 V% {4 N/ C; N$ R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 @# h+ \( V7 r. ^( H; n/ M, g$ }2 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 E0 h' M7 U' ~/ w- T. z% \) w5 U% aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: z' l7 `8 |7 l2 V. l+ {1 g9 `& W, zEDMA3_TRIG_MODE_EVENT);% l8 n6 m; k& W" O. o U: \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! q r. s9 _- f% A+ E! E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 V/ j; W" z% o4 a' x6 `! aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 f$ @, B1 U3 C; j6 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 ]2 r) G: t8 A$ U' ^4 H$ M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# U: S: b; X1 J8 P7 c1 l5 ]% b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* C; y- e% r6 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ k9 H# t: d2 [0 |
}
& o% o5 O. c6 |5 C% d9 q" Z! p; o3 G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 T$ v9 z+ ~1 c8 X& j! ]
|