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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 H& [; A0 ] C+ c5 \6 w4 {input mcasp_ahclkx,2 y! ^9 W1 u1 ~
input mcasp_aclkx,( N# |4 b* L# Z p: ?% R! u
input axr0,
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" V; h( y3 p Qoutput mcasp_afsr,7 ?( @; y3 ^2 N. {
output mcasp_ahclkr,! j9 x |% n( _# }- V A" }
output mcasp_aclkr,
7 x/ L- Q" Q. g( moutput axr1,
# Y' Q; J; k P# m assign mcasp_afsr = mcasp_afsx;7 B4 j8 t. P1 E" G' q% m- y0 j
assign mcasp_aclkr = mcasp_aclkx;- w! U6 T7 Y. A+ g# Y4 y& D
assign mcasp_ahclkr = mcasp_ahclkx;" i: k6 T5 f6 Y9 x
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% K- m) ?- w# c9 l5 o' n& ~$ _static void McASPI2SConfigure(void)+ K6 q9 T. U! y5 T3 n2 H7 |7 g
{$ z( O- T4 H) x: [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 W! M: s" T c9 ~9 i2 i8 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 g/ {7 U' Y4 ]( l( [: |4 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 B" Q' U8 P" G1 B# ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// O/ o$ ?- f5 E. f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. Y. M( K9 x j
MCASP_RX_MODE_DMA);
; S8 m; g# S6 G* E8 l% n1 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. m1 H9 r/ V7 X6 B- o+ e( QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 q. [/ `# {& O& n4 A# p5 I* H- hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 d* q; U/ C9 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 _4 H7 F4 P( O8 i3 q1 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 f1 E' M' |5 ?* ?; q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ p; P9 e `* g2 I0 z3 p; {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 A1 L7 @2 z" Y* Y- gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, N z; T. h7 t! H) [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. ]) ^5 K3 e, l3 v0x00, 0xFF); /* configure the clock for transmitter */! Y/ D. a; c' C0 a+ U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 E/ L' @$ v5 f/ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! e% ]. g7 @% l" @2 r( p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 C' a* C* B! r8 Y0x00, 0xFF);
/ L0 }* p: j3 X k4 ~2 ^7 M: d# w5 B
0 U2 M2 f. S" }: Y( r+ D' t" T/* Enable synchronization of RX and TX sections */
5 z6 b! m E4 B! H' l( bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% D( _. y9 z- }2 ?8 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" j( d5 B. ], d# i8 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: h% k+ j, d7 i2 k4 k% Y
** Set the serializers, Currently only one serializer is set as
1 t5 B' Y7 r5 L% \; c** transmitter and one serializer as receiver.
. V% f4 |) {0 d, Y# r*/4 G; e6 F; R. i2 l7 ~- I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- K1 G; ~ P8 Z/ f/ LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 j5 t( B; b8 c! s** Configure the McASP pins
7 I% ~/ z$ z. H3 x1 L# m( v0 ?** Input - Frame Sync, Clock and Serializer Rx# q, L2 I2 a& e" C4 t
** Output - Serializer Tx is connected to the input of the codec
$ ~* z- n) D, g*/' w7 M. Y% v/ ^3 R6 P/ u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ {, g8 \2 b ^/ Y1 w/ RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& O8 B5 j2 S- m; R' m9 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ U: |* n" m- `- L
| MCASP_PIN_ACLKX$ s; W z, C" f3 O+ D0 m8 s
| MCASP_PIN_AHCLKX
m9 d' c: N9 @8 h) M3 q! @- \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 m9 y5 n! W" p* r# M4 p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 G# e. J, o" ~
| MCASP_TX_CLKFAIL ! Y" Y; J3 M5 L+ y
| MCASP_TX_SYNCERROR/ d3 F5 o* X9 E" U9 x7 c9 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 D- C! a9 ]+ i% k9 o. P( P; b
| MCASP_RX_CLKFAIL$ h$ u$ W- L O& q4 a6 y
| MCASP_RX_SYNCERROR 4 F9 f1 u! \5 [
| MCASP_RX_OVERRUN);% j d- Q0 {, e
} static void I2SDataTxRxActivate(void)9 ] B. ]) O% o; v
{& T2 E" q/ ]0 A% j6 j
/* Start the clocks */
* P* N% u( L1 |* n3 s8 I: N* YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 T; t2 ?7 z0 k1 l+ ?1 X$ r, Z+ V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ X8 M1 @; b" e5 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# ]& t' ~9 i& h, H3 vEDMA3_TRIG_MODE_EVENT);
# z, Y5 g k% q u( p2 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% `1 g# X: H$ o- lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& v6 m0 z: r6 c" }/ I9 W* ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; g+ ^6 a0 o* @: W9 ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; Y; b+ H% I t: L9 q8 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( Z: k! Y" q1 B, L8 y& E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 z0 V, T4 N# ^' r( t/ bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: J) h9 b! X z- [5 W9 ^8 w
} 0 ~( F4 Q3 Y9 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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