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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 A$ X" P' n. w5 ninput mcasp_ahclkx,
! m/ t1 ]& t, h1 K, l& Q0 xinput mcasp_aclkx,
# U$ j" n! v1 `9 Pinput axr0,8 L7 _2 [& F5 k/ [7 E4 e$ T1 ]+ J
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output mcasp_afsr,! w8 x7 S6 }+ b7 U9 v
output mcasp_ahclkr,
5 n' T# K& q- R4 N9 foutput mcasp_aclkr,5 I% ]* ? w ]6 N% P5 P
output axr1,
( g5 t) f/ Y% D+ I! u! k assign mcasp_afsr = mcasp_afsx;
( e; `7 q0 J( _* s- @! C% xassign mcasp_aclkr = mcasp_aclkx;, |7 H% U5 X H( a. N
assign mcasp_ahclkr = mcasp_ahclkx;
: p( @" j; [% M* m, x4 l6 nassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* z9 G' {0 s0 p2 ]static void McASPI2SConfigure(void)3 }: E+ i3 y1 m' n' |
{
# p- G, m: t: W" y$ K1 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) ]) {3 k* R) Z4 s) ~/ s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 f! n; @' |( _0 e! [! WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& v( |) [# K. r( d0 H& K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) Q% J; h4 R; e1 y2 Y& l" j: O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& E# ~5 n1 f' @ Z9 @' ~. J; n8 y9 U% A
MCASP_RX_MODE_DMA);% m/ [2 \0 r4 o5 @6 T5 P2 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, N5 v# W2 g9 L6 _# \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 A1 t7 [. z- q2 a" z& ^/ f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ i5 W9 _2 L: [* o9 N; AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
Z2 A9 E* o, Z6 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" O! _! E7 \) }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. y( I" ^4 \# A" l( R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% |2 ]6 P* `' X |% C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
`9 R6 w) f$ h" P1 r% s5 D( CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" U# m n1 W4 f: n8 m, G0x00, 0xFF); /* configure the clock for transmitter */
2 O8 @9 o; f; l w8 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, N& A! w1 Q; ~- D8 H# rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* x* l! w8 b2 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ Q$ Y" @, F" @; K9 j! [0x00, 0xFF);
/ U( L( O) H% u: w4 j2 h! d$ g2 _5 x; a2 ?' R4 K) ~. f
/* Enable synchronization of RX and TX sections */ ( O2 k+ K$ S8 Y2 |5 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 v- u& h) u+ K' J- GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& d" a0 X! A* d+ B( m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" t- n9 F' k7 c6 _** Set the serializers, Currently only one serializer is set as7 r, v* C$ D+ C8 |6 J9 S# L
** transmitter and one serializer as receiver.
5 E: v) ^6 g' E0 D) v0 s# h*/1 m3 f9 c: w# x5 E- F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 \* f0 l W; K& s( Y. [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 c- X* w1 m* d0 R9 e& b** Configure the McASP pins 3 K+ {$ U7 E7 V% q! a; Z. Y
** Input - Frame Sync, Clock and Serializer Rx& D1 ^* r6 }* J: g/ r$ x
** Output - Serializer Tx is connected to the input of the codec
- M n, v) g* F9 C- r( s; U*/: J& R; H7 i+ i* T, G; b- j/ c% n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 Z( _" C! j/ V# b6 b6 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 g& d2 I% e# n$ @" m% Q3 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 {; A1 d: ~, l+ f& i+ b6 _| MCASP_PIN_ACLKX- o/ F% T$ a. ?, w: P" B) C$ @
| MCASP_PIN_AHCLKX2 h$ R3 t- T! @& |6 O, M: S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 S8 f4 m8 @3 ^$ Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR W6 ]& T# k1 X9 G' G3 R
| MCASP_TX_CLKFAIL
* b v: G+ g4 A6 C H# w* W| MCASP_TX_SYNCERROR5 x5 G$ B4 ~) n; c7 G+ X* w) p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 g! s( _) L* a/ I| MCASP_RX_CLKFAIL1 T9 U. s1 ^1 C, [7 U
| MCASP_RX_SYNCERROR 5 [! h, J O2 E5 R* h
| MCASP_RX_OVERRUN);/ j; y5 K! n- F. {
} static void I2SDataTxRxActivate(void)! ~) {4 p: W* I# h
{
: ?1 `+ [) g. q F5 P# l/* Start the clocks */5 T% ?+ g" P/ w6 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 g2 Y) m9 a9 v9 {8 p: I* {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* T) _& C+ p! p7 b5 F8 e: qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% I7 ~1 b* e; g+ Q3 S( Z, bEDMA3_TRIG_MODE_EVENT);' P+ L" n0 {+ c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# R% y3 o9 K/ j( U& ^3 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, J- D$ s( u' k, t. P' C& qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); d5 ?8 E# o) Z* o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) o4 W% G4 _6 y) ]) ]2 Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 t4 `! Y: m+ B7 a( r6 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. K7 K. C/ s4 R8 H: x8 C2 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, [1 n5 u0 a$ N
} : A# d5 X4 v/ B$ D; ]0 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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