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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! o- _# f+ D1 Q2 a9 U+ N6 kinput mcasp_ahclkx,# U I+ @! j M |$ S
input mcasp_aclkx,
* {5 q8 {# m4 k+ finput axr0,
) r' ]& D1 S8 D+ x
$ @, j' Z# F, V$ o* ?4 routput mcasp_afsr,$ J2 _/ }; N f( [( m
output mcasp_ahclkr,/ ]9 e4 b! S3 ~& q
output mcasp_aclkr,
7 K8 J1 Q# g7 Y) E; q; `3 goutput axr1,
0 }2 d; K5 g4 I! C( b assign mcasp_afsr = mcasp_afsx;
4 X. i7 D! [3 T2 ^0 j4 }3 ~7 T ]3 Passign mcasp_aclkr = mcasp_aclkx;. G0 S- W1 z: C5 e
assign mcasp_ahclkr = mcasp_ahclkx;; l: W. V0 A) }8 J0 }$ `
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: `% d- @2 U O# s/ g" f8 `& w1 lstatic void McASPI2SConfigure(void)
7 @$ G1 E9 b% N1 X- I; ^{
" d2 g2 j: A+ x0 j1 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 v6 N5 ]1 h: v3 m, tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 K6 b3 _5 Q/ T! e/ h1 lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, h1 I* O' T6 h- H9 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: |: c% |' j N% i* r7 d7 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" r! c% W( b o' {6 pMCASP_RX_MODE_DMA);/ k/ w: v# M! L- {! W1 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
n8 A8 \7 y( t: \1 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 c4 d1 a z! {# S& tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 r8 [' Q2 H! UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. T3 c/ B0 C; L1 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + v/ C1 u: P3 c- X0 U' O t1 X( K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 t$ }- y3 w, n/ |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 J9 }# @( }9 o) U; z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ L6 q5 l: P' a+ m6 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 X- ~3 e- O6 m6 K# L# I
0x00, 0xFF); /* configure the clock for transmitter */
! E; U8 S0 J" S4 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* a, n0 B: s( ]% S- S9 C1 }( W# B/ B% FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 `+ {* J* p: M. h9 ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% k7 P9 S3 l7 d0x00, 0xFF);7 Y* Z1 A0 Y/ p6 D, v
( ^* K1 ~: c. p
/* Enable synchronization of RX and TX sections */ 9 I, H' K. @# F. n+ @: f+ r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 P! \7 E' f; d! @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 k- G W0 P; d5 p9 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ E5 x: |: b, q# K+ i1 n** Set the serializers, Currently only one serializer is set as2 a+ m6 J8 _/ [* ^5 H& m1 u
** transmitter and one serializer as receiver./ l3 L& o" e8 f* B. K) y2 Y
*/& e& ?/ |# e0 h5 L' k" X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ ~, g Y1 ~4 ]0 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- |+ o7 g' x2 X; a** Configure the McASP pins 5 b" r+ L4 p) Y; ?4 m7 B$ e" j
** Input - Frame Sync, Clock and Serializer Rx
) K4 ~: l8 E( z1 i0 C5 f. w& y** Output - Serializer Tx is connected to the input of the codec
- v" n: S ^7 M/ ^& Q i1 d) c*/- t6 \& D/ [% h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: e; b6 p0 I, d; U4 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ z( h1 z1 C5 p: X/ {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& d5 u d0 l2 X& p; Y% k/ [. t| MCASP_PIN_ACLKX7 w' W! I W/ c3 P4 o0 V+ f
| MCASP_PIN_AHCLKX7 `) [; l2 k) L U9 `. [) t1 p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' Q: `1 j# y" W, J: E" ]; {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* l9 R4 ~' U) e: ?' b0 D| MCASP_TX_CLKFAIL
0 T6 N; O/ l- i2 z2 i; a: @* c| MCASP_TX_SYNCERROR
; F# v+ J1 J: Z7 P8 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 e) h: j' F) j3 s) ~( q( x4 X
| MCASP_RX_CLKFAIL( ~- N% B f2 S+ Q
| MCASP_RX_SYNCERROR
* }! t. }( }' F3 q) S# x| MCASP_RX_OVERRUN);
) I/ k- o" w7 o4 Y6 _/ |* Y8 A} static void I2SDataTxRxActivate(void)
# ]5 B% G; F8 h& m2 p{1 R/ N; v: O p9 {& q' i$ H
/* Start the clocks */
5 X6 X, W, D2 }' F* z& E a- O& \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' B: j# l+ t; E" {8 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: E( [+ A1 M# NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 Q* G5 G3 _- h
EDMA3_TRIG_MODE_EVENT);
* I( N& y: N4 g+ {0 G6 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( k7 x( d- E* _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 I5 _5 ?" A$ t9 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" G6 ~) C+ y$ P9 f2 X) CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- g0 G9 o7 K: ]: zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 ^) L8 ~+ Q* L* H( D8 u$ A' N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 G- ~& k, k4 K6 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! Y9 e- c4 }. q# H6 a2 ]0 l
}
6 s( f9 Q) B* b& d' h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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