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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
H. D! I0 \+ q1 `input mcasp_ahclkx,
/ C! r- M; O" I6 K0 Q8 finput mcasp_aclkx,: l! i3 b0 T' I3 K1 N4 N6 }
input axr0,) ^* L$ x: s6 d" T
( [9 I: Z$ A/ a- x! Toutput mcasp_afsr,$ g: a) I% V, m% y7 c/ Z9 X( M
output mcasp_ahclkr,
_. `3 h- p! u- u3 z' y: aoutput mcasp_aclkr,- I# Z, k! E4 r- d9 g1 b
output axr1,# i8 p" Q! B: b4 A. c* T1 P/ ]# b
assign mcasp_afsr = mcasp_afsx;
. B6 g7 t( v3 |" Y( g/ m" r7 aassign mcasp_aclkr = mcasp_aclkx;1 I1 H0 h4 x6 C8 X- }( }2 h
assign mcasp_ahclkr = mcasp_ahclkx;
" x' p. E" m Y7 h% H+ uassign axr1 = axr0;
: a! F% G* d J3 `2 g" Q/ a1 |. Q1 C9 h8 W( C/ I/ A: _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ m" M& N3 t6 k9 o X) f
static void McASPI2SConfigure(void)+ V. h7 }" F1 O! @2 R; ?
{
) E$ _) ]: ?1 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ j/ ~& _- Z) m2 ?4 ~" d8 l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& N$ j" V; O9 A4 {0 f+ i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' ]/ K. ]! O8 Z0 Z. p _' i; M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ E6 M* b# X/ ^2 L+ p3 ?3 r9 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 t' U& `- g1 o2 `: E1 j6 p! z
MCASP_RX_MODE_DMA);
& u7 U2 \5 y. s3 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 i' H+ ?( \9 \4 S7 W `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" ^$ s! Y" g/ b' Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * B# a# s% S* G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; I+ O T3 W/ U+ U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " G) y/ Y1 `6 T" l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' {" f- _. g% f' K) ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
J( v$ ?# f+ z' C0 {& |, Y9 aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 @( ?: c* z- T$ p+ V% V# B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' j2 b$ N5 D8 H
0x00, 0xFF); /* configure the clock for transmitter */
% H" N; ` Y% ~& b3 u; B+ iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' w+ {% o ~" g, @/ R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ l1 W4 B( v0 i% e4 j! ~5 O9 `. F5 o fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 G4 |4 h5 U9 p7 N9 u* y. E0 ]0x00, 0xFF);
7 [' L) ~0 U! z; I* Y5 v6 }
- B. T3 h/ Z4 j" {7 B" w/* Enable synchronization of RX and TX sections */ 8 u- S# H+ I8 o0 C5 M" s+ ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 N+ ~9 R& m; `5 h+ I, N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! N* K% g4 {( G1 O3 g: q2 @6 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 t1 L) ]! Y8 u* `7 w9 n9 }** Set the serializers, Currently only one serializer is set as
# L1 N. i. X1 S' S2 K. N- J** transmitter and one serializer as receiver.
4 ^4 K, b( _- k: I2 j( @* x) c*/) t, V# u3 L1 ~ g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& a C% P9 c0 Q+ W8 d% M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) C; P# \% G5 b2 a** Configure the McASP pins * K4 q2 A4 x' J5 O2 ^ W
** Input - Frame Sync, Clock and Serializer Rx( H& N$ e8 A0 \3 z1 g9 m
** Output - Serializer Tx is connected to the input of the codec : w6 h- L% d. {, i
*/
: Y; g% \$ P) p4 KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 z, h- F! }: [" u4 O4 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ @- p5 a! U% H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 G5 c% ]' J" U% h9 d1 G1 x% l
| MCASP_PIN_ACLKX; G1 D, E5 f- V# g) t) B8 Y1 m
| MCASP_PIN_AHCLKX; u! @$ Q% }, k7 ^6 i4 [1 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 d- m8 J% X" u4 c; _: A% Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ I: Y2 k5 u' U, _& u0 d
| MCASP_TX_CLKFAIL 1 }. A1 P/ t7 Q6 P+ q: ~: z
| MCASP_TX_SYNCERROR* @' y. D6 l. k- `% G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 \; `+ x A0 Q8 I( X8 T c( C| MCASP_RX_CLKFAIL
0 c; O3 O5 B2 G6 ]| MCASP_RX_SYNCERROR |7 g! Q8 L! N0 n: W/ S7 F6 f
| MCASP_RX_OVERRUN);
; ^: C' y! ^" P$ x} static void I2SDataTxRxActivate(void)
7 H8 K' D$ o/ o3 |{; S6 k' }& M; i# C
/* Start the clocks */( E% S2 ^; ^/ k' o7 j' a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
_7 {, q5 Y) rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 F4 Y8 N) {2 _5 [( B2 ~6 O$ q! b* `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ X' A, W- i% N$ {
EDMA3_TRIG_MODE_EVENT);
6 W$ \* H8 a& L2 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 L* Y- s( l& }4 O N5 b/ O ?: {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 m6 z5 P/ _" nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 _4 p, x, ]9 T% ]8 f. X2 qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- @/ ~ S9 m6 \ @/ m6 j, ^# n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
x1 \4 ~/ k- Q( K5 H" s% b6 \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, u. J u9 B [+ \5 H9 S. zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 Y6 @+ b3 T; f" ]$ l/ F. F} 2 T& p& g8 z/ g6 l+ T" \7 y0 b& j8 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / h+ ^* | a% U# m( S4 Z/ Q
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