MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
% t( Z) R8 L! _6 z9 Q& b% rinput mcasp_aclkx,
& [( a8 D  {6 B+ ]# einput axr0,
9 L+ h2 a( a3 J2 N* r' [
output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
; `5 C4 }) y2 houtput axr1,
1 \2 f# G  ]7 O9 ^* ^

assign mcasp_afsr = mcasp_afsx;
9 ~+ ], R8 v" f  cassign mcasp_aclkr = mcasp_aclkx;
" s9 N( t( `2 Q" Z2 ~# Lassign mcasp_ahclkr = mcasp_ahclkx;
7 ^6 v! u# L9 V9 \! Kassign axr1 = axr0;

3 |& K0 q/ [5 v$ z) s; b" d
8 x6 A  ~6 M& S! _" c

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( ?# s& v: Z5 n& z/ n' e

static void McASPI2SConfigure(void)
5 D+ D) s8 V7 l% g: n{
1 v+ a& k4 p( f% j- `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
  H9 \3 `8 w9 p3 P. C$ V# I! MMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
" S5 I( R. [* n! m6 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( c5 }0 \2 V  S; m; {5 |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
7 L7 A# B& E# @, k9 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 W0 B. }: e  Y# C2 BMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% b7 r$ z) q/ O4 Z1 H5 t3 |" VMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ Q7 z4 o2 @& j% r0 z" Z1 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 W0 @, M) O5 J* j9 s; }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: ]; Z6 `( Y4 }5 a( ~. yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 s+ b7 d3 \' {. B6 F0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ p& b* Z2 U6 `# Q( N/ J1 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: T% f2 Y2 O: ~: Z! L+ p0x00, 0xFF);
+ w. v3 a7 c2 X! @" M
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ L, @) R. t  _( ?) s4 i5 Z3 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) v& R  a0 U" w( n, c( CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
8 V. X0 X7 v" S8 ~** transmitter and one serializer as receiver.
6 k/ `/ E* s% s5 ^& m7 N*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
' I. Y; L; T% x0 \- }( \% \** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
; k0 p% x8 e" q, z; c; B, F" m*/
( T. m; x0 H$ j3 `* oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# Z7 l' U" J1 N| MCASP_PIN_ACLKX
6 c. D& K( ]4 [! `; E, a& o3 ^| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
- R' {4 B/ |: @" W' o9 LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
. ?) ?/ \8 |) W}

static void I2SDataTxRxActivate(void)
% _- C' u+ s2 L! n0 G! j4 ?0 i3 o{
6 M& w; v% n: A8 i8 G/* Start the clocks */
) b0 W) r8 L2 q7 @; R8 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 H( `2 c' m  F# |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
. U* g- F5 o7 qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 M/ I( F: k/ T, h" Y( ^2 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) _3 S0 Q0 n; J! \9 {}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.