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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 b* l1 }# g2 j m
input mcasp_ahclkx,+ w1 v6 v- H3 l. [# r6 T. I! l
input mcasp_aclkx,9 u( Q1 \" G' p
input axr0, o$ I/ ], E6 V
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output mcasp_afsr,. F4 c* V% C: u8 j& \( t1 T9 v# L
output mcasp_ahclkr,7 A0 f A2 g5 Y d7 D8 R) G/ G
output mcasp_aclkr,
4 X- U, I+ S* E! D8 ] b9 Youtput axr1,
2 J# s$ U1 s( K assign mcasp_afsr = mcasp_afsx;* p5 |6 a2 K0 ^- s& M; C& h
assign mcasp_aclkr = mcasp_aclkx;- p* B8 |; Z, j. q& U. [
assign mcasp_ahclkr = mcasp_ahclkx;( X% E9 u, F1 {/ B4 ?
assign axr1 = axr0; 4 ?: e3 M6 _; F* _$ b% @' T5 w+ j
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 U; R5 Q2 Z0 f7 }7 Tstatic void McASPI2SConfigure(void)3 V$ t( x+ l6 ~8 J# A/ @% J* Z, k
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* S+ H6 p' _1 w0 }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ `: C) T( h" I9 B$ L3 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. e5 e$ i2 y. P' w/ sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ Y# w/ ~6 D9 ?4 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ~; L* t, P2 ]. e- ]
MCASP_RX_MODE_DMA);
8 Z. i: f; }) |( G! r* v% m) r: dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% F- f* A- {* h+ y/ r. iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 g6 g0 R# W2 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - Q) x4 g* s) v4 p4 W7 q* L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. P X1 l5 G" X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- x2 u1 Z/ U. `& `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, g+ a7 A1 i v( i$ C0 g: t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% K" Q! E/ X4 D5 J6 G& b7 Q Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , F2 Q, s. g3 k" w( Q) G& }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ o# N3 g' @$ }% [) ~1 ]0x00, 0xFF); /* configure the clock for transmitter */
( E" `& h/ N3 O' t9 EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* B% W3 b8 G) F' `2 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# N4 Z$ b% W0 L; pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: Y3 ~, k/ w( U0 D
0x00, 0xFF);8 I9 M- i% m. l# \! p& k; M5 m
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/* Enable synchronization of RX and TX sections */
: B2 O1 a* q5 m$ I u+ z# n# t7 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ D8 Z& l' C* k$ C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: C8 q* s; B6 N4 v" ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ i# \. v$ |" V+ J% E6 ^/ ?5 h
** Set the serializers, Currently only one serializer is set as9 K5 y+ ?# i4 _' n8 G
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% q9 C1 f5 |% g* y% E9 U3 Y* F# {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& f# N! Q# A |+ }
** Configure the McASP pins
' B5 `; f ?- {. N' R0 X** Input - Frame Sync, Clock and Serializer Rx
E5 H* |1 b7 j$ Z% g+ m2 ]9 G** Output - Serializer Tx is connected to the input of the codec
# `* \4 u! j U" e3 Y*/
9 Y% p+ m S( x) o2 a- pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& { U4 G! c8 K" \ l, h) K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ B. a/ P8 p; ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 h. Z5 I: {8 g
| MCASP_PIN_ACLKX
' I. K6 E. b- {: w, }2 H| MCASP_PIN_AHCLKX
. d4 R2 i" X; J Y' {$ v2 L2 s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; z( d# h( V2 N/ j- h3 ?% M RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) @7 V9 ^/ U) o$ @5 Q+ _* n| MCASP_TX_CLKFAIL 5 ?% L8 G" x: E9 I1 Q% J
| MCASP_TX_SYNCERROR
. @# O* _5 ?: F; ^% |7 X; i8 Y2 Y8 N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& N$ c; G, }$ x* w* Q9 ~# h2 h| MCASP_RX_CLKFAIL' K( ?) n& Y# o/ Q
| MCASP_RX_SYNCERROR
; c7 M, Q6 Z ~' R. n| MCASP_RX_OVERRUN);+ F# c9 L4 N8 T6 e6 A6 f
} static void I2SDataTxRxActivate(void)" D1 u+ O$ v1 f5 @9 D$ B
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/* Start the clocks */
- P, t5 {5 l5 `% T- PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( o K6 Y' A4 E/ VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 f; }# V5 P+ T7 d* F+ i2 k0 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. @$ K; b$ S1 b/ REDMA3_TRIG_MODE_EVENT);
" b4 c% M1 F8 K& `% _% wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - T0 r7 G% ^/ B2 ]9 o: U( Q8 I# [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 @$ \. X# t AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ v9 K* t; D7 f- A k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 P O! ^ B7 V/ v: n# B, E" [/ Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" c) E1 V' @* L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- `2 W3 M, x, }4 j, I7 l) s/ [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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