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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 U4 l# {* Y& x$ }& P7 einput mcasp_ahclkx,
* [$ Z3 ~, F; k$ T2 Yinput mcasp_aclkx,
* |$ ?: g- W3 }: h2 I1 e Iinput axr0,2 K& d. M b( m
& a( h: v) m. k% voutput mcasp_afsr,2 U- J& H- X( P9 ~1 j5 X- }$ r1 Y; w
output mcasp_ahclkr,
" c) o. C" X: L" Q( foutput mcasp_aclkr,5 ~0 s9 t h4 O/ }) M X! v/ X
output axr1,
2 {6 z5 p" h" _+ u assign mcasp_afsr = mcasp_afsx;
9 U E$ v6 r% V) N3 cassign mcasp_aclkr = mcasp_aclkx;" F( m' q7 u0 i
assign mcasp_ahclkr = mcasp_ahclkx;
1 K* {) `4 M" I! j) G( ?3 a- Passign axr1 = axr0; - x' d5 e) Q. w6 G% ]/ u: s) v- x3 r
/ ^' ]1 f8 B6 M% ^8 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# C: o! Y1 J, K: sstatic void McASPI2SConfigure(void)- J5 L: r/ f i% r
{ b7 k# V. `" Q- B6 {5 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# v9 _1 k5 o! x0 i) E% F' K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, t% K! f$ H* i% a! s! m( z9 S+ TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' f, D6 B% H" N7 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- L$ m/ R8 p& l, [ MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 L/ [2 p" ~; C- d3 a
MCASP_RX_MODE_DMA);* e, G- R% z0 K: y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 E6 f, @& J; E' h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 _8 o2 c3 a- KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% z3 A- }2 |1 G# b% RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 X! I# S% v! M- e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 w4 A# _5 j9 V+ Q# ^% J# s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ^; |4 g4 x0 G' Z: M+ XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 \; z3 E$ f6 ~* G- Q# k; V3 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 W4 G- W/ A$ m0 o# Y6 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' x* H0 q U' m( o6 f: B& S0x00, 0xFF); /* configure the clock for transmitter */; `( Q% h: `1 v$ Q/ C$ f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ h6 e( r9 s: T* aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( }2 o( T/ s/ m# B9 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 H: F2 u. Z. b2 A) Z4 t0x00, 0xFF);* Q3 c4 w2 N M: F6 G( b1 l- `: t
( F5 `6 N7 V# {; {$ i/* Enable synchronization of RX and TX sections */ * O6 c4 a# D: j" @3 j1 o) ?, V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) e% A; A4 o/ y& }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ D' \2 K: ?; ^7 d. A4 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 J' w. F8 m/ I2 m1 W** Set the serializers, Currently only one serializer is set as# g% a. V$ T& r6 ` G0 A. q9 Q
** transmitter and one serializer as receiver.3 x. @' M, P$ v1 h8 u
*/; B$ V& s- P1 Y, Y2 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ k; e8 D" E/ X* y$ OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 K8 w- a2 r- i3 k. O+ y+ }9 v** Configure the McASP pins 9 W N/ `$ S, f9 |
** Input - Frame Sync, Clock and Serializer Rx
0 v: }5 |$ o7 Q6 z** Output - Serializer Tx is connected to the input of the codec . m( t. H3 o1 ^ `# x
*/
% Q7 g! B& ?) R1 d( a8 H3 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 V/ ]2 M4 [, K7 w- ^$ T* E0 L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. [* r3 }; n, m3 e) b4 b3 o" MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: x/ |" q4 `) v: i
| MCASP_PIN_ACLKX/ r3 }* h0 ?3 y
| MCASP_PIN_AHCLKX" Q" T2 I6 c6 ?: ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 ~6 L+ Q( B1 n' r% `5 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% A- x8 o4 u- R5 I' d| MCASP_TX_CLKFAIL ' s5 a* L4 r' V8 h; }& h
| MCASP_TX_SYNCERROR
+ Q+ r/ p1 m j- ~ `5 L" S O" S: }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 J0 ^4 |* G3 g| MCASP_RX_CLKFAIL
s) S! o! x# e" Y6 X( \! S| MCASP_RX_SYNCERROR
; z8 E8 E5 m7 ?| MCASP_RX_OVERRUN);& Z8 \) p& `" i; l! `2 s& F$ T* w
} static void I2SDataTxRxActivate(void)9 }- y& P! h3 w4 r
{7 i3 ^$ X/ O7 ?1 k# t0 O
/* Start the clocks */
; Q* h8 z [3 \9 Y: T0 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 J4 E. b! D7 \$ B0 d- SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% J; j9 p, N, \* E; l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ `: B4 M* U- b E0 O1 {EDMA3_TRIG_MODE_EVENT);9 g5 @, {# ?& D7 ^9 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 A' f# L6 s: I. p" NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) d0 {6 ]) y& J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 W3 K$ m* C' L2 ?- c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) q! `3 v7 v. ^3 g) A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 Q0 L T0 C! @5 @3 a7 l7 W) ~- g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 F) ]& [- q7 e5 @# E2 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); b& E% _9 ]1 C# n- ?5 b
}
5 t+ G |$ A2 [8 C- h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ ?6 ]5 p c) ]3 F2 V- v! x
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