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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 m p* z! ^; Vinput mcasp_ahclkx,
9 t9 p7 w: g Q Z$ A3 s" }input mcasp_aclkx,
% m0 q" v" T( ~5 ?input axr0,
8 B8 h, Q' N8 w% F! C
& h, @5 e( \' g0 m* joutput mcasp_afsr,
2 e. n5 P" N0 Ioutput mcasp_ahclkr,$ b- W4 N3 t" H5 j, G
output mcasp_aclkr,
- C4 o9 i3 n7 h7 eoutput axr1,
5 f5 W! O3 g( `6 G assign mcasp_afsr = mcasp_afsx;
* ?$ {- e4 D; D& O9 X9 U" B6 Oassign mcasp_aclkr = mcasp_aclkx;+ k* ]6 w, G( ]3 }
assign mcasp_ahclkr = mcasp_ahclkx;7 U! U9 E; \( M8 Z/ u2 f6 r
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 l8 W( v1 [$ ?5 l* g I2 U
static void McASPI2SConfigure(void)$ ^- o/ ~8 n" t7 z9 x9 u
{1 k1 h" ~% e0 O& p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 @4 f$ s }0 ~7 n8 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ A4 z$ A- P% V; v* p2 B4 t- t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
@# _+ Q. e, ~0 P6 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 X. v' N6 L% w t2 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 V" z, Y( D2 w: x& b0 z' Z
MCASP_RX_MODE_DMA);, o% c9 C4 s+ H5 b: z3 O- v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! y3 X% W2 {% C3 ^' K( F1 ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 k2 @3 b" D/ p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ A5 j. [, _( e+ hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) ?4 E3 C2 V& h7 g9 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' \$ d* ~ X6 P, [+ ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ [7 m0 G# U/ }/ w$ q; |/ h; r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* N+ B& m" I% T1 |& y# w2 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 B, j$ @( d7 W s9 F" t9 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 h/ I' { ^4 w5 e; V6 l0x00, 0xFF); /* configure the clock for transmitter */
7 Y! u/ b) o; a0 @/ b7 f& r% @, yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# x$ a/ x2 W, ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- k* S* _2 f o5 \0 ^2 f% WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, N4 q# u% }8 p
0x00, 0xFF);
. i- G3 O( v5 y9 n; |# ?) \' X Y) N. ~# m+ k( J8 d
/* Enable synchronization of RX and TX sections */ . n: N; P) g, V$ M( [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. j* H( ~0 M# n4 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; E' O+ c) p- t# wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 ~. S1 M) s; t; `; r
** Set the serializers, Currently only one serializer is set as
# n6 t z- _3 \( o** transmitter and one serializer as receiver.
! k5 X5 K# E) R( X3 @*/
% ]# [& p' d. kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 L" d0 R: ?- e5 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ~# ?; L2 F! p; }9 N! L** Configure the McASP pins
4 Z; H+ ~3 p3 S0 S+ u** Input - Frame Sync, Clock and Serializer Rx/ O) H+ `8 K0 Z+ R: ~9 n- V
** Output - Serializer Tx is connected to the input of the codec
( j5 Y9 _( l9 y9 b' y*/& b0 [5 n" c$ c0 Q' X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" l# s8 \, U( E0 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 I" [. E( m0 b; A* dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
V f3 F1 I: ^6 l# k1 p| MCASP_PIN_ACLKX
; P4 l3 Z9 p2 c3 L( [| MCASP_PIN_AHCLKX
+ j+ i4 C) h" u$ s' _; r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& Q* C. W$ H2 P" n8 Z! w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 b m, l; a, l
| MCASP_TX_CLKFAIL
8 ^9 p$ R1 C2 h| MCASP_TX_SYNCERROR: i6 P" D' [, d- W8 \. {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 b% H5 w0 H# Z! S1 }
| MCASP_RX_CLKFAIL, o( ]/ P3 Z/ q. x* Q8 p
| MCASP_RX_SYNCERROR 0 m' h' x" u, b+ [, p( K
| MCASP_RX_OVERRUN);
/ h( E6 Z8 X( ^% }0 y} static void I2SDataTxRxActivate(void)8 Y# d6 a3 ]8 U0 r L W
{4 a( r( }$ x# N. [
/* Start the clocks */, a& Q0 M' I$ x) K8 O, S: D! d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, I. s/ B& Y% k$ {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 h* P& Z: F v" E5 B; zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# ~' B# J6 X- k- S- t
EDMA3_TRIG_MODE_EVENT);6 E/ P# O% I0 G9 h; s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 f8 y/ E8 |. H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 i- d: \* R. V3 j% T8 L. J! l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, V3 G9 A# |( m5 Q% Z4 R! `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: [: U' S( [: ]6 ]3 M! u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. s. n# e. v% H2 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 b/ l9 e0 D; r) s5 G8 R3 s- @6 C y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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