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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* v1 W# v+ ?' k# \
input mcasp_ahclkx,
+ H% W9 j' [7 L$ m: E. ?input mcasp_aclkx,% Z( n0 v1 ~* \. m4 H( \
input axr0,
# z8 K- J4 d; C. W7 f1 v3 B$ L& W4 K- E( n7 \6 H
output mcasp_afsr,
T! T6 `7 k$ k1 @6 t+ youtput mcasp_ahclkr,
: f I/ t4 |" E8 f& Q& `$ coutput mcasp_aclkr,
1 z+ [ B$ V. ^( T% _) L9 eoutput axr1,
/ L! Q. J' S* j! S' {9 W/ L assign mcasp_afsr = mcasp_afsx;
# [- T+ p3 t" F* H k0 P2 L% Eassign mcasp_aclkr = mcasp_aclkx;
( u/ R) S5 D8 y7 jassign mcasp_ahclkr = mcasp_ahclkx;
9 \5 [' `8 t# ^7 Cassign axr1 = axr0;
( h! V) h( S* J9 b+ U1 I2 L. j$ b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 _" g; u: S5 z
static void McASPI2SConfigure(void)
, P- X* C2 m9 ]( |6 K; h' z{) j: Z: Z9 v$ T" @0 [. U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ ]4 X1 Y4 x+ p4 t% A9 H& G4 F4 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 I& ^8 K9 b% e1 u. v( ?3 N; T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 H0 I) l) }6 A1 I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 j+ M3 X6 C) F) ~0 i) a4 J, X! yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* e2 [, t) j) f: B& e0 cMCASP_RX_MODE_DMA);* [! F0 P, d% R" m+ {' B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 B; n- D5 ~. A& c0 W0 b( q; ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 _ E/ c; u* P8 D; V h- vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, h1 W- ^6 y7 p; U: V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 e- E2 `8 k* w6 ]: D0 L8 D8 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + f3 Z3 |! {& |1 c- g4 G. W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 O: z# O* n" g6 p2 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ u- `& C% }; ?3 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 a @# o* R+ \' Y7 E# Z) Z" \4 s5 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* c$ A" o4 p6 `0 o5 m4 S
0x00, 0xFF); /* configure the clock for transmitter */
6 K9 o, u/ J1 s7 a" qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' Q0 V' G; ^; o/ d6 w1 w7 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! t* p$ _7 I" E7 p$ \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 o5 N3 q( t2 A; l: Y5 z( t
0x00, 0xFF);! }# I2 X- L8 x5 b1 ^) o4 B. G" Z- C
8 G8 J8 E4 [0 c- {4 e: O
/* Enable synchronization of RX and TX sections */
! n6 x) _0 @3 V# Z( HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ A! [) M. S" y$ z0 |8 D" h) Y UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ M( K4 _, T( c. VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' A& ]/ B5 t+ W0 b& d% x, D
** Set the serializers, Currently only one serializer is set as
0 e; f3 O$ |- R. y** transmitter and one serializer as receiver.5 `, A( b7 \: H
*/
3 [, N w1 H' O/ A) C8 J6 P) h' J- jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, z/ h+ y& B6 K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 V* w+ Q; P5 S7 [** Configure the McASP pins 1 V- ]! h5 Y9 p- o3 x: ] C8 u; c
** Input - Frame Sync, Clock and Serializer Rx1 O, m: O" h8 M* ~/ R+ p% e6 l
** Output - Serializer Tx is connected to the input of the codec
0 K: K/ ~. q1 {& D7 g*/( w6 G$ y) X- B- W4 a% {3 {9 }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); A4 h- {0 Y. R i/ Y/ A+ h! O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ x' A" b& k1 Y7 C$ N1 d' S2 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* h. b3 `8 Y9 d% b. s
| MCASP_PIN_ACLKX/ Q4 V$ G9 W2 E; X* R, ?
| MCASP_PIN_AHCLKX$ ^# T8 `4 o9 [& V' r# t8 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, @( w6 x" V [. `# j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ~/ E( a+ W7 ^ ]$ C/ Q
| MCASP_TX_CLKFAIL
* D2 @4 G! i6 b/ C5 [| MCASP_TX_SYNCERROR) Y# i+ O E% x4 ]! w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # v% |4 [7 W* L" i) S* b2 f
| MCASP_RX_CLKFAIL( s w t5 @1 b8 V ~
| MCASP_RX_SYNCERROR $ J; D9 t( _) z. P, \
| MCASP_RX_OVERRUN);/ C v) ^' {; b' m( `) t( _
} static void I2SDataTxRxActivate(void)% s! R2 _4 E6 E1 B( |- k$ Y5 _* p
{# W* O/ d" V# V; q8 ? U
/* Start the clocks */$ |5 }, F& C+ J% X6 d' V: V9 n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& s5 M8 ^% _0 N" ]4 N$ s7 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. V3 C8 W* t1 y* i& UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 u5 M4 G4 u: P5 ?EDMA3_TRIG_MODE_EVENT);
b. d7 {+ [! S0 u/ \* W; l, x4 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : P2 n& w0 ?' ~- r I D' c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 {8 ?5 p1 _# n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ |& S1 K. h4 Q3 ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 u8 R, t& ~2 c Y) N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* {! @- f0 ~# M' |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 t7 F( j" a6 S$ | U: L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ Y2 w9 u Z9 L% i
} & Q* p& D+ }! p' Z; w* b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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