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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 `% \( D, B0 e7 O$ C1 U# z2 |input mcasp_ahclkx,
# q7 H2 r3 f, r2 _4 sinput mcasp_aclkx,6 h$ q& e% j+ t
input axr0,0 F! k, s8 K6 b" E, W
+ y9 M' {% d5 u, i/ _
output mcasp_afsr,
/ g7 d9 b2 \5 d4 m) Joutput mcasp_ahclkr,
( c7 |: b* k3 M3 U% Moutput mcasp_aclkr,' I) K/ B V; j/ k8 G5 g
output axr1,3 O$ u; @4 j! s
assign mcasp_afsr = mcasp_afsx;! \$ M" L, T( _# f2 v- [* _
assign mcasp_aclkr = mcasp_aclkx;
- V0 c" i+ L: V6 {" U% vassign mcasp_ahclkr = mcasp_ahclkx;
" k$ A% s K+ m' rassign axr1 = axr0; ! j6 k/ x; L3 r/ w5 }& d7 ?5 S; `3 |
# N" h" |2 X7 x- X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, A4 P! B8 p& Z8 } D n3 Sstatic void McASPI2SConfigure(void)
/ f( @$ z# E8 @7 C{" \8 ~! |, z# K- q7 w: U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& u- |5 X& d' g9 d* l) aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( a& q6 c) B. O* l, R' d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 h5 x+ y4 U- p6 ^& ? O; T* c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 ?$ f0 n) ]+ W/ Z. vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- R4 n; A3 q* O- [: ~2 q
MCASP_RX_MODE_DMA);
, I# G4 z& g& A+ h' ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 P: f) H/ n6 n, w$ e) r' M4 |7 p/ iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( U# {/ S) c( d/ WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; F' {9 w# d& E5 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ ~! b) U* K& W" K' |3 |( F: w9 E; a$ iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & x- S/ w$ l" f' d) Y4 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, L- F' c, ?; x( U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ a& R' E% q, KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 z* y+ ^- R* h# ~% Z& z- YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; j1 {: i; Q- q) P: ?1 Y* p% x4 ~
0x00, 0xFF); /* configure the clock for transmitter */
( x5 A* J) G6 T# Z( bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# P3 K! }- u* N( z- iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 t2 D& c: ~# X& P8 R' D4 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* i. I3 i; z- w( G" K0x00, 0xFF);5 i7 b( |: o) U4 e: v" T1 Z7 \
+ z- C' @& p# A, [
/* Enable synchronization of RX and TX sections */ , x$ x4 k$ I3 X- L4 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. b. H X, Z2 o7 ]7 v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 I2 Z% f1 e+ M* i4 {. l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 ^9 W5 J; w, a, v/ C$ k
** Set the serializers, Currently only one serializer is set as
3 H5 B% e/ @7 ?6 Z& C9 q* ^" U** transmitter and one serializer as receiver.
" j# B* Z( K+ v3 v9 F9 z*/3 N' u0 B4 u; K7 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! F0 [6 b/ `+ ?: r. jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! K% C& ?6 z" O8 {0 ]3 k U6 J** Configure the McASP pins 7 l" m' J6 N3 E( A5 t4 X: p2 s4 r
** Input - Frame Sync, Clock and Serializer Rx: |7 s$ |7 Q! B. ^; ]9 `
** Output - Serializer Tx is connected to the input of the codec : m% p9 J: ?" y( \
*/6 a7 D( g1 W8 G' W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) N& `+ y* ?' E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ j3 c. B3 N n! z# s& gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 x$ _! e' M+ @5 {( N| MCASP_PIN_ACLKX, V' X1 }6 s+ F8 E
| MCASP_PIN_AHCLKX& |7 d+ [1 o4 L1 V% W% ], Y# s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 p/ o6 ]( C# O) ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 N8 H1 D% L7 P3 M& r0 o. [| MCASP_TX_CLKFAIL . ^' u% v$ i6 h
| MCASP_TX_SYNCERROR7 X1 g# d" Z+ Z+ P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % s( |% f- ?- M9 C; s! r# R0 ^2 Z
| MCASP_RX_CLKFAIL1 f, Q- _# E5 X5 H4 b
| MCASP_RX_SYNCERROR 3 k. f4 \- Q6 N# x$ m9 j/ s5 K
| MCASP_RX_OVERRUN);
5 r$ [ S$ X4 r" n+ G} static void I2SDataTxRxActivate(void)
4 |6 k7 }- p" x J( y, t{ _; H& |" t, A
/* Start the clocks */
p' e( ?: {; e- L8 A, N4 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 t7 |$ G/ y" s) |% m" xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. ^+ I+ B. h; ?8 w3 h& }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ Q+ k5 C1 N9 u+ y2 ?" T+ wEDMA3_TRIG_MODE_EVENT);2 C9 ?2 @$ |; D( `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 M6 h* x% Z2 M+ l* |* d: Y& y7 l, {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% g: c% D/ |2 g; I1 E0 \+ V7 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) Y3 A" i: F) F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) a: p* f0 F5 r' E0 I( X, U iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 v1 ?2 v6 X$ e3 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 h: H7 A- _1 gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& g9 E+ i0 J7 m: ~) |1 c+ ]} 8 U* N& Q- x4 o; G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * O1 N) O1 n! ?+ h' R
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