|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 \7 _) P Y1 M8 b2 G/ @5 Z
input mcasp_ahclkx,7 ~, V1 z# H0 R! ?) w5 K. B6 [- t
input mcasp_aclkx,( H5 [" |# i+ \7 s* v2 S
input axr0,
+ @5 `3 g2 D& A6 b# a
, G: `' W) D' k& Youtput mcasp_afsr,
( {: U1 [) Z6 r X* ooutput mcasp_ahclkr,
/ l/ E- v; @. j6 v$ Goutput mcasp_aclkr,
2 s& l3 ?0 m4 y; Foutput axr1,/ t' x: x6 h' w% H; h
assign mcasp_afsr = mcasp_afsx;9 ]9 G) F/ v# D& ~( w! k
assign mcasp_aclkr = mcasp_aclkx;
3 O) U2 I* e/ [% v( l/ W @ sassign mcasp_ahclkr = mcasp_ahclkx;
* Z% J% U" F7 y$ [6 g& {assign axr1 = axr0; ' ~. |) J) l0 u
! k- f$ n. k9 ~3 k5 [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 `) |7 ?1 r2 g' K
static void McASPI2SConfigure(void)
3 {# N" w0 U5 g6 W L0 f2 e; Q{
" T# t8 R |& q6 `& b& H! d& TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. s6 C% a3 g3 u, v! m8 XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- K- r8 P2 Q6 l8 j1 u0 Y$ T0 n RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 z1 x: }. W; z+ |4 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 T6 ^, T/ {+ t0 ^9 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ Q: p0 q! f: {& |% _$ ZMCASP_RX_MODE_DMA);
2 m# u' x1 d' S! k2 {/ lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 h& D0 \0 l; D$ w) T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 e. a/ K7 v" V) U+ M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, g. g# C) l2 l9 Q% D/ aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 D9 t0 P( v' M% O- }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# c" l4 o2 O3 }* V2 ^0 u- cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 j* H2 `; f7 [9 ^# q# G$ O9 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 }( ]% u# q2 f) t8 s7 x7 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 P2 Q# z+ c8 l$ XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 ]* E# U+ e; u
0x00, 0xFF); /* configure the clock for transmitter */+ M5 J" \ P! o) a1 X/ L+ t( l. ^' k2 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% i7 x8 P8 Z; I. F2 o) D6 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# E7 y- F; t) {1 n5 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 H2 R; Y! i, ^$ i* U9 X0x00, 0xFF);; B! @9 \" Q" B' x8 h3 E3 w
2 }% h" o% C {/ E5 b1 M+ Q
/* Enable synchronization of RX and TX sections */
* s; s2 u4 v/ U8 \6 |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 w( q; q7 H+ t+ m7 b; |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 z3 q* }1 D+ j t3 A4 I' ?8 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 t, P" f. o( ?9 x& _3 Q# ]* W! _** Set the serializers, Currently only one serializer is set as
2 F' t, a! V! Q: M** transmitter and one serializer as receiver.. Y1 L5 \: ?. M5 W4 Q+ f
*/
* Z6 ?, N3 ^$ CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 p; H( S1 w! c6 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- C0 X8 w( t1 \; C** Configure the McASP pins 2 G8 i0 B* W p! ?
** Input - Frame Sync, Clock and Serializer Rx! B& `3 A$ b( o @& Y) _
** Output - Serializer Tx is connected to the input of the codec 6 V( F$ K& Y" A
*/
1 k+ b/ q( c4 Y& t+ S6 g" o3 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' R! c+ N% C8 k* [# J& L2 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; B& A) ~ ?3 ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 L' c; J5 s7 V, T+ p4 `% H
| MCASP_PIN_ACLKX7 |0 Y2 W6 e0 p# U* V
| MCASP_PIN_AHCLKX, a+ }4 k7 I% e! B5 m9 r5 ^2 f; q1 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 M3 R: a! F" |/ i8 W/ t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / { ^$ n' r `8 o- [5 _: X
| MCASP_TX_CLKFAIL
Q' A! D p" b& B9 n| MCASP_TX_SYNCERROR
$ ~3 g4 i; j% n% m% Y' _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ M; g+ F4 l) t5 D) L| MCASP_RX_CLKFAIL
* i' B, B# g6 B| MCASP_RX_SYNCERROR
, y& A- J& ~* v; W) t| MCASP_RX_OVERRUN);% [8 E2 V# d4 N r. _
} static void I2SDataTxRxActivate(void)
3 P J9 h3 u* e/ A{0 C/ m$ q% s& e6 `7 p3 A
/* Start the clocks */
% W0 A+ d4 _, Z( V& XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( ?7 f( H6 w5 P9 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) p$ O* S, |) @" {5 s0 Q# f Q4 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ q5 q- i- R; s$ Y
EDMA3_TRIG_MODE_EVENT);
5 _; \3 H; j: W" U% v PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; S. v- q: w& U: f9 r# f+ EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( u7 l% |, b( P) c! |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% _: V& W* m$ B1 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 w" @2 m3 D. c- e4 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 N& B3 e2 O# V0 b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 S* H( l- c- A8 L: P8 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 I" v% c. `5 h. n) r0 ]( j6 x
} ' Q- N$ D2 g& o9 M- L6 P; m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- q- ~/ \$ Q) {! ] |