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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. M5 m( P8 m, e2 q: S% \* Zinput mcasp_ahclkx,5 L1 {2 ]" R& U/ f
input mcasp_aclkx,& e4 D9 H0 s! Q& B& a: J# C
input axr0,! y% y* x. D# @
& U; V: Q2 s& Aoutput mcasp_afsr,+ a6 A9 `$ O' L+ [: g6 s4 u
output mcasp_ahclkr,/ ?" d' d% p! o! M- D7 l) b* C
output mcasp_aclkr,( ~2 T, o8 d4 @; q/ Z
output axr1,
6 X6 P& V7 T' t* G" a& Z6 ?7 ` assign mcasp_afsr = mcasp_afsx;9 j4 u6 z. n* k3 l* u4 q& E
assign mcasp_aclkr = mcasp_aclkx;
! `% ~$ e2 d. r5 gassign mcasp_ahclkr = mcasp_ahclkx; {/ T) A6 U' ]1 Y6 ^9 P& [
assign axr1 = axr0;
0 ~" a/ r: {1 o( b. A J- H* T% x1 F0 N1 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 ]' [+ h( B- v* {6 rstatic void McASPI2SConfigure(void)
. T% M a9 J- Y; O7 h" h{8 w, U! W* o+ W+ k2 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ p. c2 G5 B) S( ] B7 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ m3 v4 |3 D1 N& g! k% NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ M* |6 O, m& T& ]/ uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ i# @6 h* B8 v, B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ X" |8 Z' A9 ?7 ^0 Y- }2 w1 |MCASP_RX_MODE_DMA);, @. Z3 `, ]4 K z4 ~9 `7 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& } O" f+ e8 R9 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! D4 m- w+ s0 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & t8 C, o# G5 B5 Y( [( ^+ K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: b- Q5 L6 G Q9 L1 W: }8 r& D& Z' UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! E- p& `# A+ Q, p, h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( [+ n G; _" q. S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% A" K; R7 D7 G. p- T1 q9 x5 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 L% X# t U& v0 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: }6 u) F9 h b
0x00, 0xFF); /* configure the clock for transmitter */( f# ^8 U: Q' t) P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% z. n2 b9 _ C4 e! KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 |. S5 H/ f: J' h2 }; oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! |9 V2 n( ?( c2 ^
0x00, 0xFF);$ b6 V- R# M% p% D' k5 @- ^
/ X1 d: E/ z& o: }# j8 L- G
/* Enable synchronization of RX and TX sections */
5 q; T7 D5 w. P% V2 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 Z/ d' Z* O& L( M; L& Z1 D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 @- l/ k& X( J' E& x+ BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' B) J. v) H& { T( @) a% g6 N7 ^
** Set the serializers, Currently only one serializer is set as* x: G1 d! G; ]8 D! Y
** transmitter and one serializer as receiver.
& q8 G2 h2 b1 E; Y$ U*/
1 I* ]. u; M7 t/ G0 X4 Q# IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 Y3 ^, Q0 } _" U! l8 O) qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# d4 g2 e: F/ q: `9 B** Configure the McASP pins * u2 P8 |# `& n' s1 k. D7 c' F
** Input - Frame Sync, Clock and Serializer Rx
0 r) K+ n. R9 O6 i, n" t2 w** Output - Serializer Tx is connected to the input of the codec
/ l, w( I2 l4 O*/
; e$ q5 y: }9 G% N- V7 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* j0 I! [5 S2 b- j& Y: C0 E" s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 F) L9 V' [: V, ^# \9 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 U) X" l8 {& c( r4 B! L# y& E. S# X| MCASP_PIN_ACLKX9 i7 E$ O4 i# Y w
| MCASP_PIN_AHCLKX
: k5 e) ]6 H5 C1 m% p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 b( J% P2 N+ N* p: l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / k' K$ D1 S9 i( j) M4 G6 Z
| MCASP_TX_CLKFAIL
; c9 k( U6 D& O" p3 u O| MCASP_TX_SYNCERROR
/ a, c* c& B0 F- \2 t% C% a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 O" s/ r |9 e& J6 v7 a# p| MCASP_RX_CLKFAIL: Z$ k6 [" i1 H5 S" @; F% `
| MCASP_RX_SYNCERROR
+ C5 _: r4 g3 y, x| MCASP_RX_OVERRUN);& c6 `8 G. J2 k
} static void I2SDataTxRxActivate(void) C# h0 d5 q" b3 F, {# Q, v
{5 v- _8 l! F! T W: J
/* Start the clocks */0 s. |+ O. M$ J0 q1 P7 s D/ c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 F) S9 c8 r4 n- b9 U2 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 I: j2 j* H4 p' n; yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: B+ U# U+ P! u# B
EDMA3_TRIG_MODE_EVENT);' o5 B+ [# i3 q5 Y, u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 `1 d* |% e( M! j+ s% c l# E' i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# T; g- {' a @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 s- v6 U: l5 {, H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! W+ k' u; F1 h8 V7 Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 D& Y- @& }9 i- g% I7 F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( ]. r' k8 C/ P8 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: h3 e5 `' y# I2 [+ M6 n
}
5 `6 r3 V) H5 H: d7 M0 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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