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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* n X8 C3 {# f% d$ Einput mcasp_ahclkx,
' L0 ^6 V; b% q2 ~input mcasp_aclkx,
" I1 q$ u% L# `( C) Qinput axr0,
$ V/ h" b6 u0 }$ n4 d' q5 }% }* j) I' }% q# \2 J
output mcasp_afsr,
~9 }8 H. Z/ I- i% H }& xoutput mcasp_ahclkr,
1 _5 I6 G, B v$ Y& D2 { A3 {output mcasp_aclkr,) g3 ~1 H% T- g3 w; B
output axr1,
' U! K1 i; s* n0 @, `, v2 g assign mcasp_afsr = mcasp_afsx;
$ e1 m; D! ]( `assign mcasp_aclkr = mcasp_aclkx;5 i1 z+ g2 V# H
assign mcasp_ahclkr = mcasp_ahclkx;
8 ^$ M9 P- T8 `8 Z: y: {8 X$ a' D# }assign axr1 = axr0; $ s# b1 Q K+ u( _% j
* W% g- P- h4 G; C5 Z, X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; }% V3 [% L; `6 g K: v0 Vstatic void McASPI2SConfigure(void)
1 w! J9 z( g+ X9 r0 J N{4 S7 D5 m% j& U$ K5 A: w! f# e8 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! |, r0 |% D5 L- l9 F7 @. oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! h% I5 G* _2 v0 |# y9 F( B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- W! C; n# V* q. ~. wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 A8 i# O/ U( G) }& O* \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% m( _% r! y& d& PMCASP_RX_MODE_DMA);
4 e- N$ z3 o- D7 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: s2 G4 M2 T# U, AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* E0 t) ]' Z4 q. ~9 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 M$ G$ ?" {+ U1 Y* L( L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, h( S7 A/ r; w& OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) c, o: V2 r9 b. L4 c) NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 {* z' l6 {7 f5 n! h' \$ YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- q. v: E2 \5 b4 j. D* k: n0 ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Z+ ~+ C3 ?1 n7 X4 QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ z. Q T9 x X' v
0x00, 0xFF); /* configure the clock for transmitter */8 p& o2 N+ c, H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! ?* ~) B' d# I! l% w" m4 M+ u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* C0 K0 i8 ?9 [( n! b' tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. o' W0 \" K2 h2 f8 @; }6 f0x00, 0xFF);
" r5 g$ s9 ~4 d; x2 e1 B
* \1 K& E X# M9 p/* Enable synchronization of RX and TX sections */
# d1 g3 a2 `: j& O( K! ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ r \! H( w: w o8 Q1 f4 d7 W- |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. I% t5 G# \: ~+ o$ s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
~$ F% l7 H. F+ J9 ^* G** Set the serializers, Currently only one serializer is set as% k+ k: K4 O6 D6 O
** transmitter and one serializer as receiver.
# \; Q; ^) [ [& T, e*/
! J8 ~0 j% S* D9 `% G/ Q+ cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 s, ~3 C4 [% D- B! l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** e" c6 X# p' Q5 S" S
** Configure the McASP pins 1 Y X2 F( C" g8 _! L V
** Input - Frame Sync, Clock and Serializer Rx
/ f! e" H' P1 D/ }, d** Output - Serializer Tx is connected to the input of the codec
2 `) X- Q0 y& I1 j$ k$ N, ]*/
# x4 @5 w o7 G+ p$ \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 n5 H+ j/ G1 X; X9 B# i; O9 B9 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% v- ^; H4 ~5 R% x! Y+ m" q0 F3 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 u4 ?8 r/ ?* Z- y| MCASP_PIN_ACLKX& M4 ?1 V# s" }6 m) {' C
| MCASP_PIN_AHCLKX) N, K3 W2 b q* s2 w4 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# l( y4 m: A, F6 T/ oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! {5 v5 t+ G( e M& W/ E: ]| MCASP_TX_CLKFAIL
; K, h, v- ]0 E; J4 o5 [4 z| MCASP_TX_SYNCERROR) O! g1 [$ G" h7 x* c* q+ }" S* P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) n( y. T2 \# U1 e v% P4 h
| MCASP_RX_CLKFAIL
& R# b1 Q* j! s| MCASP_RX_SYNCERROR 2 E, ^) [: v6 Q9 v( g: j) l
| MCASP_RX_OVERRUN);" K8 N: w. r, H( U! y
} static void I2SDataTxRxActivate(void)3 a. L. G0 n c/ W* ]7 c% D
{8 i. C: _! X. J1 W% [; e" X
/* Start the clocks */9 `6 @$ M1 `, U/ M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 a2 ~4 q c. @. [ C% GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! P2 W) I; k! @% k' |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# e8 u$ d% k. {! q1 ?" R
EDMA3_TRIG_MODE_EVENT);- q' B& [" |- A( b8 Q9 D, U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " {% w7 @+ |/ ^4 g9 W- Y2 Y; p& b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: D) R) _+ C6 d6 F! V% M$ j3 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 e: L4 i& n) b4 U% x. {5 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 f# [; ~+ U; ^! G7 }( w. _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 ~! l, F- x! {1 ~8 q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* a& X3 A y4 _0 z! s, vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ B& C* o: M3 n% b$ U) X
} 7 K. X8 F- v7 Q6 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * o4 w2 k1 h2 h* L# `! T, V( T L2 X
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