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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- j6 r! q2 ^9 o/ u
input mcasp_ahclkx,3 L$ Z; a/ B4 S0 }3 M7 g1 W& V) f
input mcasp_aclkx,
+ y: b- C% |# K' @* y8 e4 J# qinput axr0,, a! H" p. Y9 H2 Y$ M) `- _
" N3 o9 L6 {' g: Q; woutput mcasp_afsr,1 [8 A9 l+ I) `5 r4 j
output mcasp_ahclkr,* @8 P/ y D$ b7 E n: k, a: |( c% r
output mcasp_aclkr,& M0 }# X) C9 s6 |* `7 O3 m! I
output axr1,4 G+ I* G5 D. ?, X5 a9 }& a
assign mcasp_afsr = mcasp_afsx;
& v/ E+ K: e6 N. P+ ?& eassign mcasp_aclkr = mcasp_aclkx;( v9 y$ V( w7 Q& G/ M5 _% |
assign mcasp_ahclkr = mcasp_ahclkx;
; y+ `. A% c9 j( v9 E$ Z& i K/ Lassign axr1 = axr0; 0 a: d0 c* ~" }' W; X
; {) I& E* ~) J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 [' \2 Q5 Z L* z8 Z- M P
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 m, h- W, S8 }$ BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: g' v0 |2 b0 P* j/ r RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! v6 j H) h7 D5 c* F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 F R8 W/ M) J4 I/ {0 J4 ~2 z n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 f8 ]' f% c! u6 f/ H& i& Q5 _
MCASP_RX_MODE_DMA);
7 `) Q1 V8 U" F# jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: K8 S, _ h/ h" `/ P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' P1 `: X; j6 h* u3 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) w" O9 k0 M$ @/ eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; W6 C$ ~7 f# B6 a/ nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # Q p, ]7 O- M4 Q) g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: h1 W! A1 m. h: Y9 M8 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 `$ F* P* N$ b* ]' m: H8 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & E: n8 U# o: _- b5 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 `0 Y) l9 a* V0 m# C% ]) L/ \0x00, 0xFF); /* configure the clock for transmitter */* f& N6 u4 K4 Z% H, i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ ]! j- {2 x3 L1 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 G: R. l6 \# s4 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 e( [( Z# A: y" a3 o0x00, 0xFF);0 O+ ~& b! {/ T6 u2 e
/ ?1 J F' ^, ~9 m0 X, n
/* Enable synchronization of RX and TX sections */ + z* ^, F8 T7 \0 p% G O0 p: J7 c8 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ E6 O" _; z1 W8 W; t: n3 TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 b% a$ |8 B1 p5 l- O# pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 Q9 _! X) |0 c8 D% H3 C: o** Set the serializers, Currently only one serializer is set as
# y h; i) r' H4 {; |" j** transmitter and one serializer as receiver.
' `9 l, Z! V: O, A" p/ s! C4 j*/
3 D( G, M8 B" y, L& BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 }) m# C5 K. r: b0 K5 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" I+ w/ S- P/ u/ M6 w0 ^- I( Q+ B- k** Configure the McASP pins 1 u& p+ ]5 a3 ^2 U7 [
** Input - Frame Sync, Clock and Serializer Rx- o3 {3 N# o9 v+ y. r
** Output - Serializer Tx is connected to the input of the codec
2 k' X4 I6 t9 ~5 R*/4 M K4 f1 S* ]. m9 r' j6 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' i$ J" n7 f. L- u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& m, X7 x& r, x) M8 v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. f3 _3 x& d+ a# X! \# Q| MCASP_PIN_ACLKX# ?( ~1 ^. c; H" W1 P8 ^
| MCASP_PIN_AHCLKX: |+ W5 h! U* v2 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& K0 f# v0 k# y& ?% [# c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& f/ q" c4 ]) N) d| MCASP_TX_CLKFAIL
8 H; L, v# k0 }! F| MCASP_TX_SYNCERROR
0 z9 }. Q# P" N6 j0 ^$ F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) I( {) a6 r' }3 y! F& t| MCASP_RX_CLKFAIL! p6 _- N) D D" B
| MCASP_RX_SYNCERROR 0 W6 d7 f' u( e, G
| MCASP_RX_OVERRUN);4 L4 Q4 v- X& h; k1 T: c/ }
} static void I2SDataTxRxActivate(void)
. z. [% c4 J8 f! H# r; N{
$ a2 C1 v6 Z8 J/* Start the clocks */
8 M& _$ i t0 V3 X' X8 C% JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 C4 l1 P& j& x3 P1 I0 l) A: X$ aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) ?4 g7 r( J4 M* t4 j( ~# q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% c* K' o+ P8 o4 sEDMA3_TRIG_MODE_EVENT);
/ Y2 ^2 W- q" Q3 Q- a* X0 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, M# ` c B1 ]2 y: UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ B J" W: e2 @. D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 @/ [7 Y. b% P1 h7 ^ V+ h! ]- i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. C0 [9 G5 O, Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. p+ b3 L" o9 ?# i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& k, v- r& }, J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 J" X5 `4 R' g5 r g% c3 {} 2 \0 {: I5 [* ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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