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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 M& i2 z$ i \0 N9 `input mcasp_ahclkx,
- D1 K+ Z5 Z( N9 N( S M5 N# w4 vinput mcasp_aclkx,( f1 ^# u0 M# H3 k( P1 l% }
input axr0,; k: H7 X& y7 z
9 O/ M: D \4 e6 d/ ?# K8 Z; E
output mcasp_afsr,
2 O! q1 R2 R% l& Moutput mcasp_ahclkr,
9 Z: E0 D+ j% n0 f2 m( |output mcasp_aclkr,& I+ S$ @3 p) X I# ^2 d3 c! f
output axr1,
: `' Y# p, z+ Y% `% m+ ?) v assign mcasp_afsr = mcasp_afsx;
7 g. u6 _" `7 i) Eassign mcasp_aclkr = mcasp_aclkx;
$ a8 A( V7 a. y) U" Kassign mcasp_ahclkr = mcasp_ahclkx;
0 s* r2 c6 P8 ]9 L; \6 Z3 Wassign axr1 = axr0;
/ z9 i$ ]& t3 k. n$ J0 M
3 {" T5 G$ N* U7 G4 ?' i5 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 B8 v. x* W. I' n. G- Sstatic void McASPI2SConfigure(void)& o; Z+ a* R8 k6 j7 v v& C
{8 u3 w/ {5 y3 ~ x9 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: b0 }$ u4 r6 O5 m, ^( V9 L( ~1 S7 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 T T& l" h* x4 B! M9 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! z$ m1 ^5 q9 S* E% TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 `( j& S4 o7 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ^$ _0 c5 f+ W% _% W: H
MCASP_RX_MODE_DMA);
% ?& r8 V% ]+ YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ?7 I4 ?9 N, O+ EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* }" F/ O3 p3 [0 w$ S5 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 v9 v3 K- s: _3 C! M8 O BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( V, a' _( X- l$ Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 h; l( v8 D1 ]+ a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& z' x4 C) W3 R$ s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 T) u+ M- C4 X: B; r; L9 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , S6 L0 C: v; s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ c( b9 P3 m& r( l1 u: q
0x00, 0xFF); /* configure the clock for transmitter */# _/ @ F( @ E. F+ h# Y+ f7 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' f9 S3 [9 z" F& Y8 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 e- U. I- f5 I% a0 h! aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," a$ s' S% @: m2 W( q
0x00, 0xFF);
; {3 } I, u; G' [ n+ t3 x7 M) O* B' l, o( q/ m& J
/* Enable synchronization of RX and TX sections */
e# c7 H& P* q6 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) d/ G$ }; _0 i" }. G6 [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ ^* |# q! W6 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ P* d' h$ S7 L% s$ p! f
** Set the serializers, Currently only one serializer is set as7 L6 @( p, `* |" _9 E1 t
** transmitter and one serializer as receiver.
9 X) W* X, F0 e2 ~* n*/' r% H& @. h; ^+ p) }$ H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! m! w$ ^3 F7 [* m7 @9 Y, DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% ~* |' b' l9 `
** Configure the McASP pins
: n1 P. B$ b& X# q: b# U8 ?# g** Input - Frame Sync, Clock and Serializer Rx
) w9 a2 Y& E- B8 ^2 L% N9 W- J* l** Output - Serializer Tx is connected to the input of the codec
* {3 q. `; ^. M; X* w$ j2 \*/
3 s) |0 |" t( r/ _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- n, G. `' ]1 Z5 p1 {' T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); {% n7 E* S* Q) d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# ], d4 t2 o9 C) m {| MCASP_PIN_ACLKX
+ d5 Z2 [; V4 _ D& `' `| MCASP_PIN_AHCLKX
0 e) g9 B/ t& C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: A( Y- U6 Z7 Z6 t5 Y' R. C8 `0 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 c5 o( Y0 Q6 Z0 o X| MCASP_TX_CLKFAIL
8 I7 `7 w( j; Y6 B| MCASP_TX_SYNCERROR% m: M5 @. e* J7 i# ^, Z1 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / S/ m) W4 E# d: N
| MCASP_RX_CLKFAIL2 h% u9 t/ v o5 O/ b1 M8 n$ ?
| MCASP_RX_SYNCERROR : n5 H0 M% l4 {! R
| MCASP_RX_OVERRUN);
0 c3 E. U4 ?7 A/ p7 s} static void I2SDataTxRxActivate(void)' k1 B7 X. H. L1 A, a
{
5 O1 m R0 W: j! B/* Start the clocks */2 a3 I8 V r3 L2 G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 k8 g% n* P- }* `2 U2 u& HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) g; R; O# L* D6 A+ a3 q; ]" q) VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' `& ~: |4 k: W, `( VEDMA3_TRIG_MODE_EVENT);
) ]. K- H6 i6 l0 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ }9 i$ G: G1 g4 Z4 M3 |5 ~ xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% f; y! |& D g5 l# J3 T+ f2 X5 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: i8 X. c7 |1 t; I+ [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) o1 y, b9 o" v+ pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( \, O4 f/ T6 f; P1 a' S" ?" W2 `4 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ p9 q" E }* S# t0 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 e. \* R) n7 c/ m- l, i0 A% E: D
}
9 V& C2 E+ I t% A3 p! {0 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' `$ m* u: M1 [7 `: z3 |$ A
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