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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 ?' w( N4 q; t" B+ v
input mcasp_ahclkx,
& I# A1 e4 _* M- }# Binput mcasp_aclkx,5 p5 N/ A8 T% b& {
input axr0,
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$ Z! E8 ?& _" P* y1 \5 z- [output mcasp_afsr,9 `% s( c3 _8 Y% @
output mcasp_ahclkr,9 x; ^7 M& D7 \ y+ B' k2 k2 t! G
output mcasp_aclkr,
& P/ M# L8 P+ `# P4 boutput axr1," L4 h; @5 I" `/ w5 f. z8 s6 M3 g
assign mcasp_afsr = mcasp_afsx;3 s9 V& }5 K( G, i4 Z( b( l4 f
assign mcasp_aclkr = mcasp_aclkx;
1 t6 A1 s# ?$ _4 Kassign mcasp_ahclkr = mcasp_ahclkx;/ d p" l" v: f4 e/ F9 w; Y
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& V* m M! n; Y+ b( M7 Xstatic void McASPI2SConfigure(void)
9 `: \) [7 [2 f0 q8 W{
) T! m4 [0 ]/ W/ ~/ N4 k% _McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 g1 W3 q3 k! o3 @% e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) |0 _: q/ h2 c: d" c/ l, x9 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, ~5 R5 E+ F0 y& T. _! U7 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) `* I; Q% ?- U$ a! H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& e+ H6 M! z F& ]- f l
MCASP_RX_MODE_DMA);
! e- X0 E$ W8 x7 p1 c: O$ d- {9 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( }" U9 L3 a- WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! V- w- ?: s: f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # X3 R2 F5 P* N% A' G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- N" I6 _3 K# q$ K2 d' \9 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , ~# g9 W3 G7 ^% O& }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// R! g, @" T$ _ j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! p/ K' m3 C9 Y9 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( l$ f, P3 T/ R4 o0 Y# N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, P; N( N6 S2 r6 r
0x00, 0xFF); /* configure the clock for transmitter */* Q j D6 c+ S) g8 b4 C: y# k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( J' y& m& l1 Z# V, ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# Q+ V& p. R9 r: qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ c! I$ S7 ]9 {% k6 [# Y
0x00, 0xFF);
' G! A. `$ O9 L4 r0 l% M, |6 ]
2 {. _) Z# S6 m; _' ~/* Enable synchronization of RX and TX sections */ , N5 [+ T8 b1 K& ?7 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- o+ @8 O* u; k% _, x8 A+ E+ P3 qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% l3 \, U5 r3 Y( LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 U8 q* ^& P6 E* x0 T** Set the serializers, Currently only one serializer is set as& A/ k* U' Z3 e- S
** transmitter and one serializer as receiver./ T, U& t5 _, n
*/( Y- J2 X4 M$ m7 J7 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 G7 O* {5 p$ `3 X ^9 L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 Z6 X7 X M3 r3 O) F/ J0 A** Configure the McASP pins 2 l- _7 I1 U- H6 v! v
** Input - Frame Sync, Clock and Serializer Rx
& [# h4 x" E& f' V- F, v9 ?** Output - Serializer Tx is connected to the input of the codec 2 W; s! F" L3 W- B8 x+ l
*/
0 d6 l: ^; u/ e4 U" rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 y9 n J( }6 P; a+ b; KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 w% J4 [ K1 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 G# a1 T _5 h
| MCASP_PIN_ACLKX# C" Q5 E! |6 }2 A# j
| MCASP_PIN_AHCLKX
5 z- a h3 Q0 B4 H' `) S$ i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ z" r3 ~" A. r) _ w5 h8 {' M9 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' @" c0 U$ X6 O
| MCASP_TX_CLKFAIL " {7 r; x" |/ v4 Z; O6 Q
| MCASP_TX_SYNCERROR! r8 \2 K8 z D0 ?% i* _, O% |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " k/ F$ @* s6 u! f
| MCASP_RX_CLKFAIL& z/ n- e6 x/ x) C( m6 A6 R
| MCASP_RX_SYNCERROR
2 d; @$ D& I4 Z6 I| MCASP_RX_OVERRUN);9 u0 L' s% d8 b/ e {4 ?
} static void I2SDataTxRxActivate(void)
# K' |' [1 M2 K& q* V{
3 m8 n3 g( n! F: n& E+ r7 Z/* Start the clocks */
2 L8 W2 k S' @5 ?- eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 _2 z& e/ ^# H: X$ nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 }7 v7 N3 p( ?5 K7 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 i, V* U4 K& aEDMA3_TRIG_MODE_EVENT);
! ?) y( U$ v, L- E8 U3 z" PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! N& K; { U0 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 o) B( {, k8 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; a! n" X; S2 a4 T! M* vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. s T" w1 A7 C; Q3 P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ `1 j! v7 M; {/ i5 \; |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 a, F1 i* @1 Y% |! U' ~: `: A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! U8 {+ c4 h0 z' U ^; }' ?
}
: H0 M [1 T: s0 N$ b5 R9 k5 t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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