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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( L5 N' x# u& t' E$ G @
input mcasp_ahclkx,& e4 J. X: P# ?7 u: t1 X
input mcasp_aclkx,$ E5 z4 F: [, @, ^ r4 Y
input axr0,: A* A1 ?( v/ U3 r% j
9 s, |/ z% m- f" C/ Ioutput mcasp_afsr,
% L& D; b4 a( L6 X) Boutput mcasp_ahclkr,
) N* Q2 h5 ^+ ]6 L% ^: y Goutput mcasp_aclkr,
* m. j' Z" f* E# p4 A' @output axr1,
/ t0 A. S3 v# a- ^, ^2 s- S assign mcasp_afsr = mcasp_afsx;
6 K; s6 ?1 N" |; [* M& j' i7 cassign mcasp_aclkr = mcasp_aclkx;4 ]# J% Q- ]7 |
assign mcasp_ahclkr = mcasp_ahclkx;
: k: J H0 b( cassign axr1 = axr0;
, ^9 J; p; A) r7 S* V6 m
; Q. F% J' M3 ?' u! y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % @8 g+ n; ] L h6 L2 y `, W
static void McASPI2SConfigure(void)
1 ]$ w4 ]& d6 K4 Q{
6 J: ?9 _+ x3 g' q' SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& \, T G1 w( Y! KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 J; Z' P. x& w8 e3 {$ j5 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. G' j8 O6 W5 @, o3 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' n, S) X# j" p. l9 a) L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( D# c# ]$ i# T' ~MCASP_RX_MODE_DMA);
3 Z" G& \" f* c0 q# Z* pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 d3 b! u, ?/ b' c7 n9 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- m+ W& s: P; C/ P8 ^$ Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( W: D, m0 _4 n0 I7 z. p* y# @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- \# \5 w2 N" D; t" K, c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , D1 r) L% v+ P( _# M6 v, h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- |8 ? p0 c5 c4 J4 s% b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, p" L% i1 B& t0 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; G7 e# _: g% X; D; }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; T3 C& @# P3 F0 \2 t- T1 L
0x00, 0xFF); /* configure the clock for transmitter */
9 G# U9 w l8 X" ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 n3 R8 p% x( L8 I$ i9 c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" ]9 |1 u$ Z& TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( _# w. k+ A5 ]/ U; p# g" l7 d* G1 {
0x00, 0xFF);4 f2 A3 y2 i' N! P1 Y0 ~
; {9 Z6 h: z! ?% S3 S; q+ G1 ~/* Enable synchronization of RX and TX sections */
' c+ x. z8 m. `2 P g( l4 M) JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 g/ b9 o) q* z0 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! K5 _: {! ?$ a+ `& K+ R2 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 a5 P# s( l# y* d+ Q# G7 z
** Set the serializers, Currently only one serializer is set as
r9 Q+ h9 w: u, c) Z1 u0 ^+ z** transmitter and one serializer as receiver.& ]9 `+ K/ q3 o; E k( s
*/3 B$ r5 S0 Z4 i) p, K2 E# k0 e0 d7 l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- O) N i: o& t) A' f7 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- h+ {! a0 ?9 Z8 [. V** Configure the McASP pins + _( X# z5 x; j. ?, I7 L0 O
** Input - Frame Sync, Clock and Serializer Rx
' w$ t0 d* u8 d x9 F e** Output - Serializer Tx is connected to the input of the codec . A9 } y, r# P/ O* [
*/
0 q1 F4 P% H7 P! y$ x* t7 r6 {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! e. f; }9 q9 J+ V, w gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' }& W6 t/ }) y& P' `& BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 j) ?% e; @. G/ g( T) d
| MCASP_PIN_ACLKX
3 Z! a6 D, U# s( n. @4 O9 d/ u| MCASP_PIN_AHCLKX
- ^# M+ K( j& i$ c0 Y% x: }1 N% j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' k) K: P1 k- oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 u2 o/ Y+ b- I5 Z" _ r| MCASP_TX_CLKFAIL
8 q O- v. i! A| MCASP_TX_SYNCERROR
3 s0 |7 O8 I1 q% S2 U# e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. Z+ q5 q( p: w4 z' ?| MCASP_RX_CLKFAIL
+ X4 g9 y, Y- x+ Y$ j7 u# Z| MCASP_RX_SYNCERROR
. g* F0 p; c' h0 U. n/ L: g| MCASP_RX_OVERRUN);
5 [# Y8 I1 ]3 _. v% L/ `/ q} static void I2SDataTxRxActivate(void)) A4 Y V" v2 N/ h
{
! {& M$ I* L( ]/ @ F1 ]/* Start the clocks */8 p' X" \1 U/ V7 g4 B5 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 P$ X( g6 E2 E; A0 N( _/ Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// Z: O% e$ v& I( G; n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ G% l' b- L0 [$ B4 T; j. d& @
EDMA3_TRIG_MODE_EVENT);% @: |5 U6 F L9 u$ w. t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 m$ e- y( J( c! s: e0 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! W; s. n' i6 \+ dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* G! D/ H7 i' [ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 `) T1 u5 g* t, F6 G; y v1 R" Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! t; i8 {% D% U1 i- l1 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 I/ N- o" A5 ` s% {5 s5 s( {: aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ @" ?+ F; X+ K; J}
1 k# h J" N4 K/ o4 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : d" G: `1 u8 P+ C& r# c/ b; }
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