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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 x: E7 k$ b; G% ] Sinput mcasp_ahclkx,
q1 R1 f4 t3 N5 N, minput mcasp_aclkx,
/ V0 ^1 w# ]8 Z: l5 U4 xinput axr0,
" n: W, S' D2 l/ u' D; x
) k x) Z+ R- ~$ r/ G# boutput mcasp_afsr,$ m; m4 Y4 ~$ w: `
output mcasp_ahclkr,* M* @* g0 j! E1 U! ]4 N
output mcasp_aclkr,
% j2 K, o }9 T$ ]" e: Koutput axr1,
2 U8 }1 r1 z' a& s' w2 G assign mcasp_afsr = mcasp_afsx;
, C: i, r6 P1 Y* A0 {" H ~assign mcasp_aclkr = mcasp_aclkx;. v6 D7 k* b1 ~" T4 m- O1 \
assign mcasp_ahclkr = mcasp_ahclkx;- n: a+ Y; I) V! C
assign axr1 = axr0;
1 j0 f r4 o* L0 z( v4 ?9 G7 N/ u0 h) @8 g1 l; z2 G5 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" p7 P* u& B( T1 x9 h9 Bstatic void McASPI2SConfigure(void)" p8 b2 ]. O; S% t' E9 s' x3 m
{
6 X# _ N9 o" x1 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% u* _" Y! R7 W0 g K1 }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; `' j! ~' ]; W. T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ \, {* X% i9 `! d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ A% Q7 z8 f4 j; s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* G) L) @# }0 `5 R2 W4 i1 tMCASP_RX_MODE_DMA);
4 i1 K* g g5 o- VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 X1 A5 q+ _" o1 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' @( }% n. k* X. q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ H2 H5 F* q# m$ j; H, ]4 tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; q0 {, ?* l% x7 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 U/ N" L3 L+ i A- z& B$ FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) n0 ~4 Y' l5 @& R/ S; C* y$ uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ `: @" x1 ^- t3 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / }# \5 p1 a' W1 _' l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) K) p& r, c# O6 ?0 }0x00, 0xFF); /* configure the clock for transmitter */
: b# o' b8 e$ YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. k) r! \: X9 ~) _( ~, ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, s% I* I6 Q+ R( y. \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* |1 q3 }+ s- C" u$ \& Z
0x00, 0xFF);( j+ x( p4 `7 a$ s0 j9 c
: u4 m8 V* ~5 @2 O9 Z
/* Enable synchronization of RX and TX sections */
T( M0 y$ @; ?7 eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 z! t# K: j9 j, B& }! e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, H5 q( E0 |2 L; h9 l8 q" m( OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& I# L& z( I7 _* n** Set the serializers, Currently only one serializer is set as! W9 L/ }% m5 I
** transmitter and one serializer as receiver.. X/ G6 N( d" L
*/
4 U5 ^" L# z/ n4 V. |" w; {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- F1 v( n3 }4 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ `' E1 Q, N4 [. c** Configure the McASP pins % a* m4 ?. k- `
** Input - Frame Sync, Clock and Serializer Rx
. Z! A+ F+ g6 y# O( P3 i7 Q** Output - Serializer Tx is connected to the input of the codec
% E0 m% s$ k D+ O m& [*/
! v' r1 t6 ?% c% Z9 R) CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 v |' [# F- b. G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ r- A, y; c6 d( W8 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: h: \& X( N7 A" w8 f3 w/ g& u
| MCASP_PIN_ACLKX
& f" [* V# e8 e1 ^- X, [3 A| MCASP_PIN_AHCLKX
' {7 I( f" o' E; Y( d4 y! R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! _) d$ S$ i! j3 b! k5 ~7 s. V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " W$ z _' I: v' H( T( e
| MCASP_TX_CLKFAIL 4 R4 O% P* X' ], ?# U* J9 g
| MCASP_TX_SYNCERROR+ o% J8 n4 Q1 a/ R0 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 C& m0 k4 R5 ]: f) l6 O' B% u| MCASP_RX_CLKFAIL3 U, B+ I* l# r
| MCASP_RX_SYNCERROR
* @) C n6 J* I& j) X/ E| MCASP_RX_OVERRUN);( D" B R/ }' {5 O! P2 D
} static void I2SDataTxRxActivate(void)
! a* g$ V& e# {; Q x4 v& M7 f{- h( ?$ j4 H$ |0 s, u$ L
/* Start the clocks */
) R3 t0 A6 d. G( x& _- aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ `' R4 a5 L6 A% e7 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 l% f K) t1 ~/ X* S7 z: k7 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' U$ T$ ^. s1 O/ Z8 _$ O. [EDMA3_TRIG_MODE_EVENT);3 z1 w2 r0 b y7 s7 u# u4 x4 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 R: W% T7 v1 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: s7 P" L t* S7 I+ i! [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& n R) S1 M1 j4 D" ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* H5 o* {: t& b" w9 t! P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 d+ u* t, s1 m3 tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. |4 l# I/ B$ o( V9 u8 }6 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 Z1 }4 e3 F7 G w1 y; z}
3 \7 U: [ B2 L2 ?& i! B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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