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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! E' L$ G/ ^/ g. Z8 R( Q
input mcasp_ahclkx,
5 f7 n) |9 v; N* w2 u& b# Yinput mcasp_aclkx,5 x+ u1 K9 D5 Z6 B# v
input axr0,$ p& m, S9 Q6 ]8 z' M E
( a: J3 O& G$ |/ Ooutput mcasp_afsr,
( j0 ]( }/ o, g: [' W2 goutput mcasp_ahclkr,, g- x1 H$ C; z) @
output mcasp_aclkr,
( x! }+ H+ M6 `' ^6 F. Koutput axr1,- H8 q+ @& V- u# y* B0 G. w' n
assign mcasp_afsr = mcasp_afsx;! v; A/ f0 r6 Z t4 |
assign mcasp_aclkr = mcasp_aclkx;& |; N0 _3 ^& S/ j+ |
assign mcasp_ahclkr = mcasp_ahclkx;1 R! O& w: J- U7 m& Z4 o2 L$ Z: C3 o
assign axr1 = axr0;
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; N R+ U/ K) `5 l. Y2 b: p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ j( q. Z1 h$ w6 Tstatic void McASPI2SConfigure(void)2 D1 I( ~* P" d( ~) M- ^* j
{
' L, c& H/ ?# { h, i% LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 U/ U2 d Y# _0 O$ H2 F. g/ c9 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 x1 V4 i- N# J9 `3 @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 c, F5 \* |2 ?, G4 E' H" _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 C$ P3 w' w, b2 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" I) A" l* `8 z- _" vMCASP_RX_MODE_DMA);9 i( C7 u- H! g6 _' k s0 u- g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* b- j" Q3 U/ f" M; l) [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% H) L1 a* Q. |; Q) P0 T) hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' C u+ T* H4 f7 z( u0 B$ g) i1 ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# Q, u, H1 u* Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, q% u4 {: f( A [$ G4 y5 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ O' ]- s( g9 _% a- DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ \% i( W# \: R$ w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 I# D9 {7 l# T: c! wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ ~: w: C- P# \ F4 @( o4 P# h0x00, 0xFF); /* configure the clock for transmitter */( J) w0 z" T5 W$ j6 H5 v, B" u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ Z4 I& ^& F' M+ p# j7 X( z1 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# C. |4 ]! C0 q- v9 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 F) x ]- {: V5 A6 G0x00, 0xFF);
X; C2 M& k9 x, z4 T9 S& |* z3 u* H* R$ J7 H
/* Enable synchronization of RX and TX sections */ 7 ~" h! H& H; b4 o4 @+ D0 _: k6 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; }3 q/ n: L8 q9 S+ [: m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& W3 s" H( x" p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" j2 P. @) ? s! @4 b, g% k
** Set the serializers, Currently only one serializer is set as
0 m4 Y$ F. G. R& A0 J) v** transmitter and one serializer as receiver.5 M4 I6 j) o8 L C. e3 j) a
*/
- }* N3 C0 j+ x+ sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! T$ |$ P% ^" ?( b( DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 ]0 ?# `# L7 X$ B2 Q) H** Configure the McASP pins
1 E; A# u6 F) {' W1 x! j** Input - Frame Sync, Clock and Serializer Rx* `& B4 x/ T) w! b3 s. Z
** Output - Serializer Tx is connected to the input of the codec
$ ?4 @7 O6 t& Q, I8 X$ ?, t- b*// A( r( d! S$ i$ f; x: Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 N) O, n7 P" G- x7 q& w; U" EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% u2 _3 X- y# y" V4 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 O6 N. J5 L) x- h4 Y( j! [| MCASP_PIN_ACLKX- m" v! S9 y( k- p5 `- _
| MCASP_PIN_AHCLKX1 n! [9 s8 a7 U) n& s6 K% Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" E- V6 e l6 A O7 j6 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : a2 T) Y4 R0 b
| MCASP_TX_CLKFAIL
6 @6 G+ b/ v+ j7 p; Y| MCASP_TX_SYNCERROR
5 Q3 W" W$ Y/ A4 p3 q/ y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : `) W/ k% w2 ?# v: y* V
| MCASP_RX_CLKFAIL
# V( w2 ? T! y3 c| MCASP_RX_SYNCERROR
& t) d1 l, ]+ c% R+ N# ?" _. {2 M| MCASP_RX_OVERRUN);. \1 K/ S4 @5 u4 a4 f
} static void I2SDataTxRxActivate(void)
3 i" L# D/ H4 w{+ R, i* T: R( `1 l" J
/* Start the clocks */8 u+ G& R' S S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( o+ W# s1 F) {5 }$ n* uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( Y; {# n' s! q. qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 S( }4 R: @. w" a3 ~; L
EDMA3_TRIG_MODE_EVENT);
1 R, y) l* g9 x- {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 ]" S: e6 ~/ s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. |4 r" j4 ~( E3 G M5 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ T% Z9 W$ q: N% _( z# K# yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 t6 ?3 M( c/ X5 A7 \% Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 N8 B0 i, b. k3 S& r$ ^1 d+ i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ m, n. t( X" b6 H1 j( z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" O. ~2 e- z" S# ?} - Q+ R6 c1 E8 i8 J$ d: z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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