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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: r; e0 M8 g4 ]( L8 r! J$ Hinput mcasp_ahclkx,
$ C7 P6 U0 u0 @input mcasp_aclkx,7 Z" u. F0 @0 Q8 I5 \5 ^
input axr0,% w- N' t" `$ D. T" m; t5 C
: b, e$ A/ X" s, e! R
output mcasp_afsr,5 w+ d; s& Z: s1 K* N5 v" h
output mcasp_ahclkr,6 R) `+ B7 C3 X0 l3 f6 s* d8 _
output mcasp_aclkr,0 W: M% }! Z4 A. m7 a
output axr1,
. q# S9 R8 u1 ~ assign mcasp_afsr = mcasp_afsx; o, ~; V- w) D; S7 A$ X. w1 V) P( J1 p9 x
assign mcasp_aclkr = mcasp_aclkx;/ @# l/ B# D) R. b! \) _0 F
assign mcasp_ahclkr = mcasp_ahclkx;2 ] v# e) G) t1 O# k
assign axr1 = axr0; % l5 o5 b' {9 h4 s$ W5 j
4 _9 L8 Y9 a; Q+ b" p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, ]( @: d4 U( mstatic void McASPI2SConfigure(void)8 w( p6 ~6 A* L
{
3 R: H+ Q+ n& ?+ L9 O b2 m) C8 g8 W# bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 P8 H) X( t/ K& I8 b! W2 J0 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" t2 R% j2 _% V4 T- MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& `7 `& t0 |% B8 m9 qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 s0 d3 ?+ A. u* PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& H$ D9 I# `3 [MCASP_RX_MODE_DMA);
4 ~/ I+ a# q/ U5 Q+ T0 Y- u1 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 _3 K2 U$ M% Q h0 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( n2 _7 p% N \5 B- P" tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: |3 G' @. V- q+ P" C% uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 u/ q( n- O1 a3 Z8 G% l/ ^0 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; ?# e# S( { u4 v9 ~. Z$ G7 r( yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 H2 D$ r8 A8 o; z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: m* ]0 q, E$ Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + |/ q; l: m5 C- N+ O! d2 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% z6 a* }2 a+ t0x00, 0xFF); /* configure the clock for transmitter */# v% {- c- ~% X2 `6 @9 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 M* G, {+ E7 C1 A( ^# b$ Y) s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# D! ?$ Q, r; E9 dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 f: V( `1 E) ~0 K; D/ ^6 W& r
0x00, 0xFF);. D5 l1 ?) a% h
* B) m3 L( L+ S% g! t/ i2 c* ^
/* Enable synchronization of RX and TX sections */
0 _6 M3 e4 ~, L$ u' ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// y; k) Y9 ~1 D" w9 ?. m! K- O9 K. E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 z5 z: u, H' l2 h3 F8 L. rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 D9 L2 f) ]$ E. A% Y' @* f
** Set the serializers, Currently only one serializer is set as1 V7 V) V# ?2 x6 }. ^% E6 f
** transmitter and one serializer as receiver." j! i% ^5 L( i' [, W1 E9 [
*/
, D4 ?4 K! x0 {, i# KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 y5 V2 Y/ p% |/ d- |6 h+ {. z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) s/ }* i4 c) K b
** Configure the McASP pins
! H6 d6 l2 n& J, m** Input - Frame Sync, Clock and Serializer Rx8 d i4 d# o" K) H
** Output - Serializer Tx is connected to the input of the codec
, @( e1 M" @' H*/
A: ]$ d" c+ I JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. ^8 g% M' g7 V3 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. t1 f+ H9 K4 ~: h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% x# q/ u, m7 v" @/ g. t; D| MCASP_PIN_ACLKX) O% A7 O! @0 e, h
| MCASP_PIN_AHCLKX
; O9 _" z, o/ p% w( r7 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
N. \1 ^# K1 W5 q2 Z YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, Y) s! k- P _7 J) Y. x| MCASP_TX_CLKFAIL
/ r4 w; s3 D5 A! W) }| MCASP_TX_SYNCERROR+ L) }. A) m5 i7 J5 F: F/ P3 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: U1 o# T' m0 ~# A1 d* ?| MCASP_RX_CLKFAIL3 `1 V8 u( s( u
| MCASP_RX_SYNCERROR
! [' N* U# ~2 \0 ~| MCASP_RX_OVERRUN);
7 O* x, a: M, {- U$ M9 D} static void I2SDataTxRxActivate(void)3 x5 a6 A* H0 X8 r
{9 @2 L& Q* s0 ^7 O. q e- B
/* Start the clocks */
( [5 m' R& r0 _$ \3 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 ?0 O& Q: ~7 x& T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 w7 c8 ^$ P1 i! G$ b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- I, g5 E) z3 x
EDMA3_TRIG_MODE_EVENT);( T0 w3 U" w+ B3 `% Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" L. l! T4 b" IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. U7 q0 w6 u9 ?7 Q; f# H( gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) j; w/ n) i8 A2 ^2 r. L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ \6 j# F8 _4 P% y7 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
S/ \' X% |% N, g4 }0 z4 j1 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 j; {+ {9 P r# E0 s( QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 s/ K9 F% [, e0 S0 A5 ^. C} " _: ~& Y9 c( f( X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . d3 a+ H6 I J e
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