MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
! g3 e8 O9 X9 g  D+ ?input mcasp_ahclkx,
input mcasp_aclkx,
7 Q8 m! U% \6 h* y! l) Qinput axr0,
% d/ T7 }  {4 f5 d6 C
output mcasp_afsr,
5 w3 ]+ h" _6 v; toutput mcasp_ahclkr,
output mcasp_aclkr,
) m5 M, o. z8 k  ?output axr1,
2 b# }2 d1 [9 R1 o; {# ?5 {7 J

assign mcasp_afsr = mcasp_afsx;
' w3 Z- D; i+ J. C2 B  Dassign mcasp_aclkr = mcasp_aclkx;
* z8 a) b6 R9 b2 p1 ^* Passign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

: C; q8 a  B0 X, l; N8 @, }

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
- L# K9 o: G# \0 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
/ T$ k. l+ Z. _7 g" jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( h* d, @" ~; [7 }5 n' a2 W* c0 XMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: E; s6 K! J  G3 O/ u) l- mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" I1 W( Z7 S" J+ H5 i* HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
; X: z7 L' q  T% Z0 V4 a  O  K5 RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! C  ?/ c) P' b8 Z3 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
0 R7 A- n( w' G& Y( ~# I
# d, |1 X7 F$ v! P# I5 Q/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% `: d% M+ o. g4 B3 d** Set the serializers, Currently only one serializer is set as
# C$ e4 W* X; M; N8 w** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
0 w8 E+ @6 J, c*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# y# B6 ?) ?, |8 P! r" ]% RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& C' i1 X! M. wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% R. x) k9 z/ J/ j& P| MCASP_PIN_ACLKX
4 W0 n% _* s* |; J6 }| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
. c1 N% Q9 a3 S/ _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
6 p- K$ n9 }/ w. p4 O: ~| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 c# G2 B7 h% w% F| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
% e. s  ^3 j. N- {- w| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
5 l0 T' x8 r/ W  z# h, w* X. t{
" U* H- I* i) W  k/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
0 b# k9 v  {( @/ G- P8 p  R9 y! q6 W/ q$ mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
1 ]. \4 i& q/ n  C5 r3 R4 Q+ oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ~# w7 B& u; eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
' N* k, Q# E$ z0 DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
; z* s. k& N, T2 i4 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' F" f  M& C( N- @* bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% y* Z4 [( y& l8 U}

$ S) ]$ B. ^0 G+ m  q9 q& C

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.