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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 X( P: n; J2 L% o" Z8 @6 d; ?input mcasp_ahclkx,
$ |# n, n5 U/ h; i* Einput mcasp_aclkx,! R$ q- v0 {& Q
input axr0,4 [, v# |2 S0 H. a7 h6 [; J
: z8 D1 X/ M, q$ ^' }" h5 Woutput mcasp_afsr,
: c6 `8 x# ^' P9 `6 u3 houtput mcasp_ahclkr,
' i1 Z4 j8 Q$ h: S- {8 D8 E3 \9 eoutput mcasp_aclkr,, v( T# y& F. X4 F# B& y
output axr1,9 c! q& m' c2 P q: ?7 K/ g6 m
assign mcasp_afsr = mcasp_afsx;5 |) W2 c6 b9 X* l1 r) x, C
assign mcasp_aclkr = mcasp_aclkx;
8 ^( g$ |: G( D/ p7 B7 k; Nassign mcasp_ahclkr = mcasp_ahclkx;6 H G; Y$ ^# q7 F; J+ O0 B4 ?" N
assign axr1 = axr0; : ]6 q# [% F+ g( F2 w
) c, ?! I4 M' t/ c( v$ b4 H5 P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 _0 e b1 Y1 J, k( `. A1 dstatic void McASPI2SConfigure(void)
! m7 r" I1 k, u3 H" U{
n# y) R7 R( l$ F; CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; |: N5 z+ z) c: S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" j; |' Y& [) k$ n! E- i: iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 @3 u. q- J/ g% z% d0 m" S2 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# X' d+ Y/ ^) S/ k6 E! W! o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) _7 S1 P& ]+ n- R' Z! y
MCASP_RX_MODE_DMA);
# S: d5 q. j+ k- n4 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," \9 [2 _7 z0 f/ J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ V" J! ^4 E0 A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% V. X# L0 U: r* _# C* X* KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 e6 v: V$ u1 v* _5 Y1 e3 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 l$ s" W- y. {. W6 R3 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# u _0 H! n) d: ]6 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ A% u* Z' a0 C2 v9 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 p5 D% C1 H" s0 l Y K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& A9 W9 _0 {# r3 x O3 c5 Y
0x00, 0xFF); /* configure the clock for transmitter */
: f$ Z: Z$ k1 f7 g% LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 M4 d4 ?' G0 e* w, JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 n- ?) W% \& ~- f$ \0 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( r+ ]" b0 Z0 s
0x00, 0xFF);
/ B F9 U/ G$ j" Y8 t2 y5 K6 w6 v) ^! v4 _9 {! I# g
/* Enable synchronization of RX and TX sections */ ; e7 @' y$ s; R! N- ?8 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 P. d- p5 i( Z3 p. y& OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ^$ v! n/ B! aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& H8 r% l- r9 e) n** Set the serializers, Currently only one serializer is set as
/ p v# {' W0 a2 z** transmitter and one serializer as receiver.
' _6 [. |2 `, U" X) V( N*/
# a$ e, P+ h/ S' CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- Z8 d, q6 A$ c$ \) ~3 [1 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* \, Y. J1 b) |. D7 y0 X* ^
** Configure the McASP pins
: x. ^" ~6 o1 [. ]- e** Input - Frame Sync, Clock and Serializer Rx. t$ d- `9 X: ~4 v' ?& ]: N1 C& v
** Output - Serializer Tx is connected to the input of the codec
- y; N% H+ u Q; e4 _*/# i$ L! Z$ J H% @9 e. g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& D5 ^& ?9 w% Q$ }) r: Z, q- R( `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" i/ }& y3 U+ u$ b% v# xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 R l) t+ |1 `8 C R
| MCASP_PIN_ACLKX; S+ r# `; O$ J" L9 \$ c
| MCASP_PIN_AHCLKX& |. _! U( y: I8 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 H! W0 U, G% t& l; eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
_+ r/ F. ]7 \" X9 ?8 m3 ~ H; M| MCASP_TX_CLKFAIL + T7 k% E5 a# w8 i
| MCASP_TX_SYNCERROR
4 `$ h9 k5 z- A5 t' p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 U# T! V2 v4 k$ D Y% S& s| MCASP_RX_CLKFAIL
1 k) |0 W: t1 g: O- h| MCASP_RX_SYNCERROR , S! g7 l! k6 h8 `
| MCASP_RX_OVERRUN);: k& W0 E) L) \4 M( {/ R5 K6 ]: I* ~
} static void I2SDataTxRxActivate(void)
6 l* |/ s8 n7 D& O{
9 H: a" L* G$ D6 c0 C) T/* Start the clocks */6 y+ ^) n: [5 z% l9 B0 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 S s2 ?6 Y5 T2 Z8 J1 e T& J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 m5 h2 P- J# [- ]2 N0 c& \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, l0 B( s4 [0 |- ~& g
EDMA3_TRIG_MODE_EVENT);
: Y9 E0 q4 P3 ]6 L1 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 k( H# w! O" [0 j9 Q3 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& V W ^; r% j$ b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 ~+ }+ L+ g" t8 r& U6 s6 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: n% t$ d9 p9 {6 X5 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# z% G0 F% v* c7 V9 _$ D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; K( b/ ]8 ]7 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 y, Y- i. O+ v1 i5 U} 4 i2 z$ Z2 C# Y- q9 d1 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' m7 u- \# I; E; M+ m9 E
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