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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 J8 `+ w9 w" e7 i6 R7 f4 Finput mcasp_ahclkx,
' K( ^# i8 V+ f* x/ sinput mcasp_aclkx,
, ^) S% e; Z! K+ a& a# minput axr0,# o( j, Q/ p- Y' E4 J) C
* l/ \! t% q# v* {8 X
output mcasp_afsr,7 X9 G1 E0 q8 j+ r* t. y4 i5 X
output mcasp_ahclkr,
/ i& e# d \/ F: ~- V; |output mcasp_aclkr,: u9 c% C% m# U2 Y3 {2 Y/ V
output axr1,
" c9 O3 G( ]3 o8 O+ {& }& B9 H2 m assign mcasp_afsr = mcasp_afsx;
5 r' B4 S1 s# Yassign mcasp_aclkr = mcasp_aclkx;' m1 s; I% u' O# L( \7 ], V
assign mcasp_ahclkr = mcasp_ahclkx;
3 h' C( ? o2 H: @; Q; ?! J, Iassign axr1 = axr0; ! i9 O/ D3 |0 b. I5 h
* i! N# s/ D3 k- I1 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " f# F# i5 j( W: } D$ ]
static void McASPI2SConfigure(void)
1 D9 [8 N4 P% k# O n{6 e. `8 [, S7 Y5 j3 J7 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 h# {2 B, k( I( Z- H- ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( |, N0 ?7 T1 E) Z$ j: N( YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- z. o/ a- x. FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ D+ [! W3 {) D% z: VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( M, d( `: j- D, `) \/ cMCASP_RX_MODE_DMA);# q G X1 d/ Q4 {- y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( m6 _9 z# D5 [8 _& oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- R4 H! W6 d5 V) V6 D, \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - ~( Z3 \+ k0 e4 {( O s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% H5 H& {/ o- t0 I' f& |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 n6 ?) Z4 J! K8 k& M7 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 ^& _6 U6 |' O8 v# y7 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- U p! b1 P! `3 @: n% i6 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / q$ i* t% V/ g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# P8 \+ K. T2 K5 F% O/ e0x00, 0xFF); /* configure the clock for transmitter */* A. p* O$ l i8 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" a7 G/ A6 h R* M3 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ [5 c r' q2 Z- y# ]9 P4 f! WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& {# J: B4 K) F2 Q! t9 n- _6 z& \' U0x00, 0xFF);7 S) G ]( s6 R' m+ |4 Q- F
; Z+ X# N0 ]/ g. _7 i) n/* Enable synchronization of RX and TX sections */
: T! `7 H& P+ w, c' ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 ` {5 R& r* _6 W+ H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ r% W8 z2 F. R; j0 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, w$ d% l" F6 J2 h& O/ K% L! K
** Set the serializers, Currently only one serializer is set as8 v& K9 @6 \5 j1 I% z5 `
** transmitter and one serializer as receiver.
9 H) `) O& o' |) W2 @+ o*/; S& O7 \& a5 r! j* v% V! m9 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ h; V7 x0 _$ S! g* T) x, Y8 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
o1 j" E9 Y( h( ?' Z** Configure the McASP pins / L4 D, Q R5 _" J* L, U# \
** Input - Frame Sync, Clock and Serializer Rx
5 l, ~' J$ e( U1 t) t$ y** Output - Serializer Tx is connected to the input of the codec
3 M3 b2 Q7 d/ g" ]( ~5 }*/+ M8 V! ^7 |1 i5 e; ]/ e& U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 N8 Z) q6 u5 m7 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, m* n1 ?8 a5 A: Q, `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: f; a1 R& [3 m$ |9 B
| MCASP_PIN_ACLKX: q3 d4 c3 K9 ~" D- W* r, W' n
| MCASP_PIN_AHCLKX; R% O$ G: l( {& G+ j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 C; b" |8 Z: S, s7 u% V) Z% [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : U2 q0 y, Y; S4 [7 J O- V) c
| MCASP_TX_CLKFAIL : C) i% P( F. P( b& w% ]% ~. N9 h
| MCASP_TX_SYNCERROR
6 ^! i6 Z1 m( R& c) N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 M \' ~: P, V9 y5 Z. ?6 ^| MCASP_RX_CLKFAIL
7 D+ [4 D e ~' m/ O| MCASP_RX_SYNCERROR 2 F: U+ x) \: w% ~' d0 |0 _
| MCASP_RX_OVERRUN);! S$ F% h; R& X* X8 `
} static void I2SDataTxRxActivate(void)
6 Y1 T: j! s1 f2 T{
& d* a3 z( { i' d/* Start the clocks */
4 F, H7 g% E0 w$ G# t% D+ HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 W& L/ m) m$ O/ B2 [' I4 n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) f6 m8 m/ V' y& L( V6 g5 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 Q! w6 Q8 s( u" Y5 v. v9 K
EDMA3_TRIG_MODE_EVENT);
* [8 A; F, c J$ O0 u( L& P CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 }( g/ c- E! H" C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* `6 {2 M8 u* I- Q- f1 m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. s1 s! _ x9 n' q; D5 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 U' Q* o; Z: g; I \( jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 z1 E5 Z0 e) ~2 p5 Y6 Y1 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 U5 X: c- m0 k5 I5 x2 p9 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# S9 ~ L4 {' a# D3 E& D$ C} 3 X: U# F' e, U. |' y( J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 U( J9 U- _3 ], S w& o+ x
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