MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
! c; G4 J5 U  ~0 n5 U# E. ]input mcasp_ahclkx,
/ f% O1 A- H, Z" G, pinput mcasp_aclkx,
) E) u: [  r3 e8 }input axr0,
: m7 `& Y3 R( ^
% {$ ~% y" j3 L/ boutput mcasp_afsr,
output mcasp_ahclkr,
" Z9 ^9 ^/ @5 |* n8 ~8 youtput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
5 o3 N- [# R) L! ]* Eassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

) }, w/ y, z* m: |/ J9 ?0 [, q

static void McASPI2SConfigure(void)
{
6 ^9 a2 G4 {% z) z# f, _; S0 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ~. M0 _! D+ Q, O. N; p. JMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
5 M8 ]* J. J! B. @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
3 |8 Y% r! P0 \( P/ N& {* g0 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( b  ^1 P6 M7 z9 _2 UMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 S4 J8 Z  f" @/ O: {& E$ ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ ^7 Z& P3 m( D+ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
3 x7 Y' B& e, b/ YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 P' x. x" L1 M; b5 f0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ ]4 _- g, X5 F) B, ^0x00, 0xFF);

# X4 _7 a8 B  Y5 d/* Enable synchronization of RX and TX sections */
# P* A6 \' d' a, F8 \8 F2 l* AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) g- t9 @/ k+ v( T8 t1 M% x7 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
, M! }9 o! D$ S** transmitter and one serializer as receiver.
- X! |) p* j7 f0 p: O/ S; s*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 U1 ?9 y8 ]3 v+ ?# DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 U& L. n" X3 g$ ~** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
9 a+ }; q) U9 _" o* m9 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
4 \) m, Z. f# ]& \* k, @| MCASP_PIN_AHCLKX
- ]2 ^8 V3 R! O; v1 B3 y0 T: B| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
. K6 H( k/ |& S5 A% U) \, W$ S" z1 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! x% B0 C& n- T; t| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ u( c( y# ?* U  B! Q; w# j| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
  }& ]' T7 O7 L- N' T| MCASP_RX_OVERRUN);
/ h7 K* x' M& a0 A* S- m: c- K}

static void I2SDataTxRxActivate(void)
" U7 [$ x$ H$ M/ x( `{
/* Start the clocks */
4 M2 q% X, l8 W' X' V0 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 n' T: m1 m# v8 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
; R; f4 V/ S1 O3 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
( Z% d3 h8 {, q! V, l. fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
) g1 I7 C; _# u2 g7 b! \2 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
+ F- |( n/ n4 N$ \  f; I9 L' ?1 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.