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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& T& F) W' U$ i! E1 {& C9 J8 I7 G4 s
input mcasp_ahclkx,
3 S$ w0 a/ P: S7 | V! Uinput mcasp_aclkx,
- u5 L0 d! T8 G! K S( ginput axr0,
- V( H0 }* _4 w9 T. ?$ {# j+ j* l; i& K4 D
output mcasp_afsr,
" [/ b1 X( S$ B% p; [5 a% Boutput mcasp_ahclkr,+ G) L) Z ^5 \7 Q& U
output mcasp_aclkr,& [& f9 _9 C. }5 @% I
output axr1,* e; I: l q% q _7 f) F) x. v
assign mcasp_afsr = mcasp_afsx;# Q2 D& l! `2 P( }9 z0 P. W. j( a
assign mcasp_aclkr = mcasp_aclkx;
& C4 H- x& k$ Z' {# ]+ k" Zassign mcasp_ahclkr = mcasp_ahclkx;
2 f! ]- P5 d7 P4 j3 \assign axr1 = axr0;
; M& ^% H* ^, d, R4 @ j& _. W* B- d" {" x/ f' ? V* t5 F, H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* w8 o: n$ n) R3 S; q9 b( cstatic void McASPI2SConfigure(void)
$ b6 o- L0 q( A8 Y8 C{: G% s) t6 Z. i2 S- {* B8 {: m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ ]% m+ g3 E& h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ B! }1 N" ^' r' ?8 _+ B/ R1 b/ m( nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 w8 `( D! k- A$ d4 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" `% _- z- `: u% e2 Q- OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! V( d3 ]$ b" m! T$ z6 V/ LMCASP_RX_MODE_DMA);
7 |, s' g. Z% a2 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* h% X5 v6 w) {! M. j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' b8 ?' k% d" D3 W% a% m4 C/ JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
S, ^) |* P6 A2 \, s" u% kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% f8 V) Q" R5 z8 _- X x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% w4 V5 j& H, x5 T% `# yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- t' z1 e* j* J4 I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; C8 e* R/ S, ^. n- ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 J' R9 C/ J3 S, iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, P! }- @" L3 q
0x00, 0xFF); /* configure the clock for transmitter */. f" X! S1 c. E: `3 ]% y& T* Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- [2 ?# o: `' [' iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, M) b1 F% M t* u1 s( R! [$ QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 B1 U8 V, q8 Z6 x0x00, 0xFF);7 G* ]& Z% J: v3 f
* V' r u9 c" L; N; i% ~8 j, N0 |/* Enable synchronization of RX and TX sections */
@+ Z* k) y" @ j: _$ KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 Z0 M3 [8 T* Z7 a9 K" u' F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 g# w3 e. W% C# J; z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 u0 z g" W# }1 f9 G5 K# h9 o
** Set the serializers, Currently only one serializer is set as- O5 n" x8 t7 s( q' [
** transmitter and one serializer as receiver.$ `% b8 f c! V! U$ H
*/
$ a$ J7 R! Y5 T$ @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 {7 P6 N5 z+ x7 m: a$ W, l: s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" |6 z# _, c4 y5 Y; p* K' `/ c' L
** Configure the McASP pins
; A0 b2 T7 Q h1 W6 U) E0 ^** Input - Frame Sync, Clock and Serializer Rx
+ d( |' D- n s** Output - Serializer Tx is connected to the input of the codec . V* f2 X" @4 H0 B6 M
*/
6 P' r5 K# }0 M5 ^) FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* y k# b" r9 w- ^% d5 j. l! W0 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ O) Q$ ]4 `5 I. f: d' KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 x1 ?9 ?6 n1 ?| MCASP_PIN_ACLKX% V8 x3 [& F& ^" u8 V( @" D0 N
| MCASP_PIN_AHCLKX
j% |3 h( T; c. {2 F& S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ s) F( S7 k2 X0 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 ?. _3 V% ~; R8 T| MCASP_TX_CLKFAIL
, w4 [( E' _+ E8 T, f& F+ l0 u5 N| MCASP_TX_SYNCERROR3 u- W: q& K6 ?. H+ a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ A0 U) A9 ^2 a2 o| MCASP_RX_CLKFAIL2 ]# L8 x& d( Q/ }' A+ B
| MCASP_RX_SYNCERROR
f" {3 o9 c% {( a+ V( O8 v( ~| MCASP_RX_OVERRUN);
) S; y9 i5 f' E} static void I2SDataTxRxActivate(void)0 r4 F' q* W7 b& a% g5 n
{2 n4 [" D4 N& q. Y
/* Start the clocks */
+ M, ]# w4 d: ?7 {! o2 r0 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 S: |1 G; w( v7 d r' m4 F- @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# r3 }2 S7 M- ]7 ]% h' a1 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 J. c. O! G) |0 T# T. b9 HEDMA3_TRIG_MODE_EVENT);
( s& N! t9 C: }3 m# @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; J3 ~- q# K7 z" [) c: B0 EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 H- i" a( u$ E0 c5 Q0 hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( K) Y8 v: l# NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# O/ ~) J6 I: U. D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! h1 i( W1 c* S6 S( D- d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( Z/ Z2 Q6 `' Y0 b+ h8 k2 l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 C+ L7 C- P! R/ i
}
& }) h- u6 f% g; r7 B! \! d' t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 T& [$ f, _4 g3 e
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