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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 R Q# x) n' r5 N! H
input mcasp_ahclkx,9 h1 r+ F% N3 `% ?
input mcasp_aclkx,; Y; o5 Y3 v( }! b4 c8 K" C3 f
input axr0,
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( U( B% Y( w2 a" A, loutput mcasp_afsr,
/ q& h/ Y1 O# ~; P& _- q$ [output mcasp_ahclkr,
* c) V1 E& P7 Z. V2 boutput mcasp_aclkr,
x- c: O8 L5 u% poutput axr1,
# \' @# x: [1 B' A! c' C' V assign mcasp_afsr = mcasp_afsx;
- `- i& ]8 g6 qassign mcasp_aclkr = mcasp_aclkx;
* h5 v3 [+ k2 B( @- ?assign mcasp_ahclkr = mcasp_ahclkx;1 e p6 ^: V( `5 J' j
assign axr1 = axr0;
3 V* n; G+ W( } \3 ]" t
/ E. T7 R X) g- a' L+ [1 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! B* |% b( K- f) \static void McASPI2SConfigure(void)
' `7 ~9 T* \2 Y2 v3 z{
?+ z( g( n% B7 m( `- RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 W+ I1 T1 d7 t- Q9 I3 g8 m, d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 W3 R( [& h' a" M3 C& j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 w" Y0 L% t1 w, B0 }: Q8 P4 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- d9 v" n( d2 _$ u# p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 w9 L4 }3 |8 X1 x# O" Z
MCASP_RX_MODE_DMA);
3 l; @ U9 {9 g( u% D( Z3 S4 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) c. G' M% r( ^) ~" I4 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- H: V" q3 [! `; C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 ?, [6 B w9 ?1 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 u) F( U) M" w9 z9 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' x- u) Q; P# f# ~1 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ | P1 E2 `2 ^/ w- J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! p* G0 h' J6 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! Q/ I1 W/ ? k6 N% T( R& v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! q/ z$ Z& K5 T0 L7 ?
0x00, 0xFF); /* configure the clock for transmitter */- Y6 |9 T7 K( y) e( c1 A! I7 e& r+ r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 r0 O8 [+ I) g* G. H& I) S- p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% @( x' j% |! Y& o, f6 U0 D& ^: tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
k6 ?6 {1 S0 q1 D# J. d0x00, 0xFF);% Z; v# O n/ G, g7 w& J# C& w
3 [' @/ K# A% y, S! B/* Enable synchronization of RX and TX sections */ , k/ C5 l- V+ j7 |5 ^+ X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: T0 C" f1 ~5 f+ W/ P+ E) a+ e$ o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 @7 b# }7 Q$ L* |9 e# e$ x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** P- N! e% K% r. y, d
** Set the serializers, Currently only one serializer is set as
; O; @8 T4 u& ]4 E$ m4 q8 `** transmitter and one serializer as receiver.
5 C9 `+ c- p0 @2 _8 B1 P*/
3 s( b6 v' T. X. M" mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* t4 I1 e) U# E* g/ H, ]7 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 l6 q7 O, K y6 U3 Z/ A; S** Configure the McASP pins
! z8 m) ]. G9 F( Z4 w& F** Input - Frame Sync, Clock and Serializer Rx3 N3 P) z. t7 r
** Output - Serializer Tx is connected to the input of the codec 2 ~$ Q8 s) j- Y1 {. b& K
*/& e6 g3 a( e9 O$ T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: k' V4 o: A9 s/ _' YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 d: ~6 W$ h; u0 H# c% bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 p7 ^" q0 r' n7 P$ R( E' Y& `| MCASP_PIN_ACLKX
1 ?. x n$ ]/ o. J- C& T! R$ w| MCASP_PIN_AHCLKX
/ F/ R6 ^4 c0 U* K9 v- F R- h- J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. [: F7 o- E% T9 B$ G* t: ^- LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 ~0 ^ d; s# j( l% k& q
| MCASP_TX_CLKFAIL
# H M y3 n6 B- F| MCASP_TX_SYNCERROR" w+ k7 B2 ?8 m5 A! Q' R0 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% F: y8 F. n; ~| MCASP_RX_CLKFAIL- D! G/ J) m1 M$ _) m, c
| MCASP_RX_SYNCERROR " {+ i9 L% S9 W8 C8 u& }8 A
| MCASP_RX_OVERRUN);9 z. U: \5 j/ J) G3 T' X9 I
} static void I2SDataTxRxActivate(void)7 U) A. t' ^6 ~! z. a
{
9 S3 K- p% v3 U+ {6 i( ]' M/* Start the clocks */0 q) J% v$ x/ n9 g4 m* |, G5 A) ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 w3 e( |( Z4 h( E5 e4 F4 I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: e) s" j- O1 M7 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
@5 c. P/ ]& [3 _! \EDMA3_TRIG_MODE_EVENT);
" Z) g9 X# k9 F5 M2 N" z, A# ]( J& MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 Y& l8 K# s. [) \8 k5 P1 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" G2 A" c4 ~) E" m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" e4 w. `* P- U, l* D( J5 w0 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: t9 B3 H' q/ h6 u/ _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 R% x2 c9 {: Q5 |+ c0 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 ]) }& O+ e4 N% a# Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 ~8 g) _/ l; k) s8 o: ]
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