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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 \4 n& g0 X; K8 Y
input mcasp_ahclkx,: d X/ C5 U' [
input mcasp_aclkx,! Z2 | o. h& l" a" _
input axr0,
, o, W* O: d: M V/ ?. F2 D3 D" E8 }1 f( _& R( ]0 L) O4 M
output mcasp_afsr,
1 p7 N6 \& e4 J; ~output mcasp_ahclkr,
0 u( F# E. i' Aoutput mcasp_aclkr,
& I" `9 w; d+ |$ [0 N& moutput axr1,
) U5 _; ?( U* N$ S" w+ S assign mcasp_afsr = mcasp_afsx; A5 B+ ~% C/ O D, M7 W" X/ L
assign mcasp_aclkr = mcasp_aclkx;1 m6 N. a5 C& A: B5 F3 n' D; C0 T6 u/ z
assign mcasp_ahclkr = mcasp_ahclkx;
. G2 l/ m/ |. `# s2 f# i( Z: s$ uassign axr1 = axr0; ) _" J; C5 D8 M, t
' }- Y6 \+ b, H$ D q8 X! v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( }! R: m8 ^' J1 z; z
static void McASPI2SConfigure(void)
& v* y. x* w0 S# q! u4 Y+ y{
+ b4 f5 x' A; S/ N' ?/ b' V/ jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 H; A) O6 V0 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 V# y, O" O: ?7 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& D5 R/ r7 [; }( K( c9 d0 GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( d) e( e1 ~. n, r( _7 t0 V" n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, j. k9 o0 Z9 E# D& b
MCASP_RX_MODE_DMA);5 q, Y* U7 c" K% T* K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) G) g& x1 ^* R8 ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 O" ^* F* X; A7 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * I2 ^! h+ w* v7 _. w" c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 @5 b: Y; s- g; @. P( ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # x) D1 o% f {8 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ a/ p( G1 |- j4 U; u+ JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. }4 w1 Q7 t' s$ k7 o1 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 D* N0 r! I. t/ a, g5 p9 W0 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" y- H2 |7 A7 t$ d# S0 ~4 d0x00, 0xFF); /* configure the clock for transmitter */; w" v4 _5 K+ A" k$ f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
c; l L, `, n. b$ ~* e' E3 {% m( p9 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& F$ u; B+ r2 |6 A# bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, Z4 l& P$ R! r9 Q- x3 K
0x00, 0xFF);% i0 ?8 P: p$ `3 c9 h1 B, d3 I
& p2 w( b: N+ U! o/* Enable synchronization of RX and TX sections */
: N- y, Y- {& iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. |4 l q$ F% B9 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 S2 k9 L1 ?. j4 m/ xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, V ]' S) V7 r% ~( B( C** Set the serializers, Currently only one serializer is set as
% q \6 m" ]( ~0 o2 \* \** transmitter and one serializer as receiver.
+ J2 u1 @0 H. o' V; v" b*/
* ~8 O8 E$ {% w1 A! F4 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' i" Y" K, {* p# C5 t7 e9 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! N2 q! n2 q) ]8 t+ W$ ~** Configure the McASP pins
3 g9 ?& J# O q( s% @; U2 I** Input - Frame Sync, Clock and Serializer Rx
`9 b( D8 W7 v, y( o, m** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; y$ a0 ~4 R( A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. b0 t) r6 o# r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! ~2 \ ], S7 d7 J$ E || MCASP_PIN_ACLKX4 X, G) r, Y$ U9 d+ p$ I
| MCASP_PIN_AHCLKX5 U- C" c. ~2 l7 h) G* U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 S; ~' N# b3 v! u3 g8 |7 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 _/ f M) J3 I( x
| MCASP_TX_CLKFAIL
: o1 B: l4 |) z2 N6 r1 M! I5 w* y| MCASP_TX_SYNCERROR
' `3 a2 f9 _6 l: F) @# }- m/ p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" j3 v9 ^3 [! p9 N& F4 I( O| MCASP_RX_CLKFAIL- ^/ P6 R% E5 s
| MCASP_RX_SYNCERROR 2 g8 G$ o1 a9 |) v- h
| MCASP_RX_OVERRUN);
, _& H2 I( l! ~! n8 k' }} static void I2SDataTxRxActivate(void)
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/* Start the clocks */( J2 R5 b* _# Q. d5 y' J" Z( v- x( w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; w$ `, [0 p2 Q1 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! U$ Y) P- N5 c! y$ _/ }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* ^7 y, x% [* m( i1 C3 p ^3 [# \
EDMA3_TRIG_MODE_EVENT);
$ S$ Q' J1 H& d w/ B4 `. dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 k- v4 t% a/ I5 Y+ w9 S xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* G8 }4 Q/ O/ Y( X* I- }; t' HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: [( v: g) w' Z* p5 S) L! T) ^+ Y YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ [1 E1 j; v: ^' Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 H, C$ |6 o; p! KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, k/ `* }) L, e; b8 n/ LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% x, g; A1 Z" ~; L8 r7 T% o
} $ u4 r; S) a4 U$ C$ e9 f. T! t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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