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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 ^' }4 B3 W( k
input mcasp_ahclkx,0 N: `! g1 [2 M; s( c
input mcasp_aclkx,
( {; f* U; z+ d* Ainput axr0,
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% C. j( z- [" qoutput mcasp_afsr,7 }5 I% C' t; N2 L( q5 v* v
output mcasp_ahclkr,0 g, y& r1 _' {
output mcasp_aclkr,
& J+ @- j8 M' h; U2 doutput axr1,
6 ?+ ~ v/ k7 g assign mcasp_afsr = mcasp_afsx;
' k1 {% Y1 C) D, P% V aassign mcasp_aclkr = mcasp_aclkx;
/ \! ]( i k7 Q. y5 ~assign mcasp_ahclkr = mcasp_ahclkx;$ L& `/ Z4 L9 Q9 o' r
assign axr1 = axr0;
$ a- I% v. f1 Z/ ~- d/ h* V! q
7 H7 k, U; a; a$ z; t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / O, K0 Y: ^5 r: `- }. v& W& {( ?
static void McASPI2SConfigure(void)" d) Y Y; d* F
{
3 ~; h6 W9 [' w3 G! tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& S& L, E. t2 b6 H) m; s. B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ Y) _0 ?- l5 D3 t& ~, TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* \: m1 l% Q* s" z, \5 zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 c) E4 d; n- o8 Q) k: G' j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 r8 _0 P5 R/ L# a$ G
MCASP_RX_MODE_DMA);
6 C, Q6 _( K& V% p- GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 Q6 r @8 `0 w/ r* KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- [0 u+ m$ }8 M; dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( c3 z+ Z7 d3 F, x. BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, |5 c4 f3 }9 k8 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 Z( r! M T* N7 z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: l" w& ~# r# J. H" |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" d6 ^. \3 _& E# b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 x F/ g! d8 `8 ?, H0 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," f! b6 W) R4 a& Z
0x00, 0xFF); /* configure the clock for transmitter */
/ g, ^7 X5 D6 W' L5 ~# tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 f- O& a# P& m1 `$ ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 @1 L' L7 V& b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 F9 t7 t" T3 {! K; B
0x00, 0xFF);
9 Y7 T7 ?& L" }( N/ M
5 l! w( W+ P+ N q" E' ~& j/* Enable synchronization of RX and TX sections */ # i. H2 _# O" l5 V6 y: S, E0 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& q: T+ N. F5 y7 P* vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& ^, C: G4 h9 T2 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 r% \* p7 J* c9 k
** Set the serializers, Currently only one serializer is set as
8 l* j; Y4 _. r0 v** transmitter and one serializer as receiver., @0 b% u; E Y. ~
*/6 ?! `2 t( J M6 D$ B2 q$ z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% m" n* r6 l# \' y. Z& w" T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& R+ ^6 J j' u5 A; p+ d- @/ F** Configure the McASP pins
7 _- b6 x, i8 Y' q0 H4 Y* h! j9 O** Input - Frame Sync, Clock and Serializer Rx! r( ~+ Y# m. ^4 R( a
** Output - Serializer Tx is connected to the input of the codec
/ E7 ?* l j5 @7 x. @*/
! m+ g1 A' i9 M4 A9 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: J7 g% \% `4 M5 J, PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# K8 _6 H' i# d% ?) z" oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" E/ C) i) P3 `% G! J| MCASP_PIN_ACLKX
+ Z5 ^( i) N: t0 S8 N, n9 u( d| MCASP_PIN_AHCLKX
2 E9 u, \; ]4 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 P6 A/ F" u1 iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! A/ u+ N0 f3 v0 o- D| MCASP_TX_CLKFAIL
; r8 C H* ^7 ]- R$ V' i| MCASP_TX_SYNCERROR
' n# c: q" ]( s. i8 }; Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' v" N( i. @2 R: d& \ _9 `
| MCASP_RX_CLKFAIL9 q' g# A/ x* ^2 n6 Z8 P: w
| MCASP_RX_SYNCERROR
, v& X* r" v; ~/ }| MCASP_RX_OVERRUN);
* J% M6 T( D4 j, T* X} static void I2SDataTxRxActivate(void)
8 l; v- ^& ?8 Y$ e& K5 G6 ^' a! _{
* u7 }/ _2 l( D" C/* Start the clocks */
7 q! g- @# x( tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 b% E+ }" ^" _9 p1 h# e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" s2 q6 U s6 B' J* [( C2 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) y( j3 P* u) A3 i1 _- P3 Z
EDMA3_TRIG_MODE_EVENT);
4 m1 M% _: V$ N; `: NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 M6 D6 e& I. u2 |) e; QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. K1 [% v" X$ _" D% |5 w1 g( wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 I/ b% j! Z+ Q+ z7 m7 a: P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 n% a8 c+ ~/ o; M: I1 d1 h. Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 g6 \+ |3 y& UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. z( K5 P# ~) }6 N7 r' yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! V+ E6 }. C5 c& T! A; D$ X. [8 F} 9 d6 w d6 b+ i: r4 X# [+ I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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