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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
d6 i$ R7 w2 u6 J' z7 N$ `2 Sinput mcasp_ahclkx,
% L; ^' r* }' q* j; \input mcasp_aclkx,
2 o; U% w3 N$ A7 Sinput axr0,# s" Z! Q/ P/ y7 Z4 S* z
9 R) J. {. S% l# X" c1 A8 voutput mcasp_afsr,% n: p, L+ K) U+ _2 b5 [% U6 C# v F
output mcasp_ahclkr,
$ M4 ^) p% S6 foutput mcasp_aclkr,
7 q. Q9 y3 `; J- P, {1 K& k4 koutput axr1,4 E& w" z6 V: z8 r C: r
assign mcasp_afsr = mcasp_afsx;
% E# S5 A$ H( ?3 B0 w. yassign mcasp_aclkr = mcasp_aclkx;
A8 l; e1 r$ }6 _8 U; Wassign mcasp_ahclkr = mcasp_ahclkx;% o7 o X9 h. ]2 y6 f
assign axr1 = axr0; 6 G# I# [+ |- h
5 H# @; u+ g5 e$ t4 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 `( E4 o( Y8 C/ s3 E
static void McASPI2SConfigure(void)2 v' v0 K2 B: T- V& C7 H( j
{8 T- E- }; h% V! Y' B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 E& v) g8 R& N$ W) `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ N7 [; r9 y3 W" ?7 g+ c% j/ E% PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 E/ v z3 s( \# V$ W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% D" ~; n8 R6 w& z3 a0 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, T; c/ K& g& H% q3 x) M# ]MCASP_RX_MODE_DMA);' S2 _7 q8 U% [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& f3 I3 P! O, K( B: sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 ]/ b. g u# \; fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 O% x2 o% j5 i( c% O2 z6 N' Z* QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! `1 D9 Y. y) SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 G8 M8 R4 x7 |6 O( o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 m" [1 ?+ ^- N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& K& ^+ M8 y5 p% ^. W: ]: j9 l, [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * C1 @( E( W3 ?, P% b1 p6 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) R. m8 J* D8 r3 S" P2 h0x00, 0xFF); /* configure the clock for transmitter */- p& N- y8 N) u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) d. y+ w& R8 h" w* \( z+ \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 d, l% t% a3 e6 n& C, `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) \1 C5 G) B( T: d0 ^% v2 v
0x00, 0xFF);8 c% b! U2 Y% [4 m
9 S: D$ L- I4 W/ b. \" D8 Q$ |
/* Enable synchronization of RX and TX sections */
9 c3 i+ }8 P9 i9 F. tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& R0 e& q4 d" hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- D) w+ B1 i; u; c" d% q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! F5 G. x" k( U1 L+ v** Set the serializers, Currently only one serializer is set as7 c3 @2 D4 r1 B1 F* u' c
** transmitter and one serializer as receiver.
# m9 s) S9 Y$ K! h9 c. ]. S*/- E9 `& X" q% @; n' ?7 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); j6 m, h. l, ~. S9 v( p) Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ D) _4 c1 p* w7 }& ]7 F) C! n1 p
** Configure the McASP pins
) S/ B% P4 @, e. S& o, x& q** Input - Frame Sync, Clock and Serializer Rx- u6 Q4 g# s- ` x* q
** Output - Serializer Tx is connected to the input of the codec
- e" N( g/ r Z*/
- w" A4 C0 t- u: `! z+ m# m- AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; H, `2 K Q" k; bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 N4 j8 m3 V6 D7 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 q$ w6 ^$ ^( m2 Q/ p$ [| MCASP_PIN_ACLKX
% g5 W! f, V- F" @$ t8 y! Z# e% B/ v| MCASP_PIN_AHCLKX
+ ]6 ?9 i/ M! A. R2 t2 T3 D+ z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( Z# s7 g! H" o5 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. r" x9 L+ S$ H' X| MCASP_TX_CLKFAIL
3 T9 w) r$ F' ]% ]2 h3 D0 ]3 r| MCASP_TX_SYNCERROR
. r; p0 ?* D, D6 o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! V6 O% P) f! B+ b, Y3 L| MCASP_RX_CLKFAIL' X3 Y$ Y! m n ]
| MCASP_RX_SYNCERROR : g& p% g6 {1 {# O) {( n
| MCASP_RX_OVERRUN);
) i7 ?2 ?& q* r5 e% o! l1 y; |} static void I2SDataTxRxActivate(void)
8 k" q z' g* `: v{
3 s# h, S2 J7 O8 ^2 @& U P! ~/* Start the clocks */
8 Q% T) V% V& O( k$ LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! [5 |6 }! b0 K. I2 P: o& FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 W* K0 i, G. T( K& O3 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# [7 y5 f$ _8 {" I- y( d9 A
EDMA3_TRIG_MODE_EVENT);6 {% o+ B4 N; t9 B# e9 F1 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 q0 y) H r# m2 Y3 T" ?8 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& T3 x6 B/ S( N: E% H5 g4 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! f& P( `, @! z* [7 M. IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 |) L" ?1 k/ Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: |/ b+ T$ l5 D& o, J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 y7 Q! c3 L3 K) h7 T y( \0 s) m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 a4 R( x; m K% y- ~}
2 d, A- Z& K) R0 \7 J& |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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