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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 q" Q- W2 ?: k2 m" _7 F% f! A3 y' c
input mcasp_ahclkx,' o# u4 A( X: V7 V* V
input mcasp_aclkx,1 [3 G, q9 G4 E
input axr0,- q, |. V" _5 E1 V1 L, c
6 L% q; T: P8 j" t
output mcasp_afsr,7 Z) G9 y& V. N
output mcasp_ahclkr,& w1 } d, p: g, ~5 l' l6 r5 Q
output mcasp_aclkr,
# h' N5 R% v( Y; s* \4 Uoutput axr1,8 j8 X- W9 ^8 m+ h. ?0 q
assign mcasp_afsr = mcasp_afsx;
6 M3 v2 |4 i H+ Iassign mcasp_aclkr = mcasp_aclkx;- G; T7 M' x$ `; k! t
assign mcasp_ahclkr = mcasp_ahclkx;# _6 h" J5 g0 K& t% n( L
assign axr1 = axr0; 6 v& }) P" n( ?6 P4 u
j: |5 @. }. f# V/ j# u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 q) t. h+ e) o
static void McASPI2SConfigure(void)5 |/ ]4 i( |8 j" j
{4 P' ]8 H) d; _2 U& }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. Q' S6 w+ M( ?' s7 \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 d9 y n' [" p: _) j3 ~# ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 j/ S: d2 P3 k, D# c! E9 k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ~1 F" ?; X; V; M, E* [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 S0 n! L& f: y0 ^$ \
MCASP_RX_MODE_DMA);: K4 v! P5 o& x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: w% E; ~& x' c+ @" E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 Q: n3 A) ] `1 d1 _, @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 j3 n* C* s: q) j/ HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 q. u; Q2 U; R0 Y- e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + i, @1 R* i- w! O' \6 z* f4 \. C6 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
z* Z( b; Y. W1 w1 c* [) z9 q+ Z' ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) ~3 K* ^* o) e( l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ m/ @8 ^1 U( R: C+ p. {; o9 qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ i, c3 E6 n5 s& ~- q$ I0x00, 0xFF); /* configure the clock for transmitter */
0 {9 C6 }7 K! wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: o7 M' s6 z: q/ W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
D) Z5 I9 `3 s2 E/ oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# s5 |' G6 t: u; Y0x00, 0xFF);
* C I4 D; }. ]6 q6 G3 x, n! U( \1 S8 [& N0 |" V* p
/* Enable synchronization of RX and TX sections */ ( v* c1 M, W m; G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 K' l, p9 R; J/ d' n9 Q; n$ N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! `( x3 a/ C* k/ _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& d7 w+ R# x& k) a. m** Set the serializers, Currently only one serializer is set as/ C( ~5 {1 f1 r; v1 U# g3 Z
** transmitter and one serializer as receiver.& j: f( J8 J( u; n9 }5 ^; Q+ c
*/
& h! T6 b) {+ i8 H( LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 |" X8 J) p# D* u6 ?3 J/ AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: K5 X1 ]. i& T. K0 d9 o
** Configure the McASP pins
8 O1 m. q6 I' j I7 V** Input - Frame Sync, Clock and Serializer Rx1 O/ E5 n9 k! E6 l) G
** Output - Serializer Tx is connected to the input of the codec - Z& O/ r* S1 T& t! g
*/7 R7 P5 C4 a2 H1 b6 B. W1 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 O5 g( |, J! B6 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 N; c- ?' m2 B$ g) I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* S3 S# W+ B' l- |& D| MCASP_PIN_ACLKX
) O# T2 b; A H I; O# n| MCASP_PIN_AHCLKX
v* e. A, X% m- u" f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! S; P N( E$ O6 i8 Y3 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 M: C6 Y+ E j& J2 Y& n* y
| MCASP_TX_CLKFAIL 5 s8 D, x/ k5 }& a1 e
| MCASP_TX_SYNCERROR/ ^5 g& C% w w* w& v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " ~+ ~9 ^6 a0 t. S
| MCASP_RX_CLKFAIL- R2 {# X8 s! Q/ C8 g% U
| MCASP_RX_SYNCERROR - H% W" I. _" i- J# I$ N7 q
| MCASP_RX_OVERRUN); ~7 ^# Q }/ E& ]$ T. S: r
} static void I2SDataTxRxActivate(void)
4 x* ^" ]7 k- t2 i% c{. y' V& S; L" \) P, _
/* Start the clocks */" A3 R: p0 x$ u. f r+ u: C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; P' n8 z' T- T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 \- o) `) T, o9 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! L# N* z* Y0 O
EDMA3_TRIG_MODE_EVENT);& b C8 b4 V4 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- `" P' \* Q+ K* qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* c* J) n% L7 p( C0 [1 h' N! aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; e/ U: Z4 W* t+ X6 N" W+ {) ] _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
V/ V' ]: a* n! Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* x$ a( z! |/ R# c; v7 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 o8 q, ~3 w7 w9 }8 \$ Z) cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" Q- i5 V+ D! B8 f2 m} 2 c/ K# p# e( u7 @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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