|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ {& Y; L0 D* @4 {3 S' [input mcasp_ahclkx,% ]% P) y3 }5 S: f% O9 ~+ j) g% w: ?
input mcasp_aclkx,
& E: S+ Z1 \. @+ s, Zinput axr0,
: A! Z3 P& e2 Z U5 x$ Q' Y( }$ H1 S9 h5 |3 q7 |7 J! h7 {
output mcasp_afsr,
- v- z8 z( y1 |* P" b& ]output mcasp_ahclkr,5 C* s( s7 M& f( e4 \) d
output mcasp_aclkr,( y2 F0 D- K9 |9 _8 [
output axr1,# ~' j" v6 t) g) G; V! T1 c6 l
assign mcasp_afsr = mcasp_afsx;% r( W: ~! {' _' P& D
assign mcasp_aclkr = mcasp_aclkx;/ o# o( O0 I5 D1 ~+ \3 u2 E
assign mcasp_ahclkr = mcasp_ahclkx;) K5 W! ~* w7 y0 B1 ~
assign axr1 = axr0;
! b) J( {# G, m6 u
$ e/ B% a" H" z0 y0 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 |* {. C4 x6 x( ?. |
static void McASPI2SConfigure(void)
@4 [# ] u/ `- n t" T7 j/ r{
& g* |4 V1 o# @; W, aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 [3 B( W4 E$ s$ R' R U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 d) H$ ]3 H* s% p' d8 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
N9 d4 F8 v. n4 E/ T# z3 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; b; g, G2 g7 V1 ?& A uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& U$ S! d1 `1 ^+ S
MCASP_RX_MODE_DMA);
: Z- I9 O# E9 J7 jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- p) R) R4 J# h1 V, n/ d+ B- x6 h: \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 }- n7 u% o6 P2 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; G& @# @! S; m. y, L- e5 H4 r1 C4 }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, J. | c$ V; q: j7 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- o. |' E8 z& H$ D6 `5 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// X7 b2 T% Z8 b$ Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 B4 o$ J3 ?7 Z7 w3 r& s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 w, l4 y9 G. L8 c, }) Q5 Z6 D: aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 ?" G6 c% d r- h( \
0x00, 0xFF); /* configure the clock for transmitter */
+ H7 {; j1 V1 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; p0 A6 [* u0 G. s* R1 z7 r/ @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; d+ \0 O% S4 j( k5 Y. l, O' ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 m! C. Q# z8 n
0x00, 0xFF);5 G% G: Q; u1 M) A
1 R# A7 U: l6 {' V4 f" {/* Enable synchronization of RX and TX sections */
$ m1 e8 T% E# D' S1 e, HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( {* i! P' K& A* c# }6 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; A% c5 @3 o& ~5 E( ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** N4 K9 q8 s* S$ N- }- z
** Set the serializers, Currently only one serializer is set as
, y$ N4 S: E0 x** transmitter and one serializer as receiver.' }/ f) [! n' Z, C
*/
# e, }% |: G4 `7 H6 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 D* u- m5 f( |6 v: KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! T' x( ^0 t% E+ A1 r& z! A
** Configure the McASP pins . y5 X5 w: L# [
** Input - Frame Sync, Clock and Serializer Rx
3 ~ }, Y& T& o, p g, j** Output - Serializer Tx is connected to the input of the codec
0 W( a3 X. M4 `2 f*// ?: ?- ?; t' m5 p+ _& Q- A, D! q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 l8 D5 e+ Q, z6 o1 \; }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 R8 b% @, b# ~* N3 ~, S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 v; B9 r; x6 N& W$ i# i
| MCASP_PIN_ACLKX
9 b: e0 x3 ]' v) m/ J! J| MCASP_PIN_AHCLKX
8 S* a5 {) @2 J$ C- X0 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 B8 b* L/ x- {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! a8 N3 ~& h1 `5 w: O| MCASP_TX_CLKFAIL $ j2 C3 |1 b& m* [) k
| MCASP_TX_SYNCERROR
* ~1 N, b" L: J$ ]# n: i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& H# k" {9 t, f% ]| MCASP_RX_CLKFAIL
: }, A7 K2 A& z K9 ?| MCASP_RX_SYNCERROR / ?( Y) f1 |/ i; u
| MCASP_RX_OVERRUN);1 }9 f1 ]* y- H6 G4 V6 L2 a, z
} static void I2SDataTxRxActivate(void)
# h/ X8 H2 W# s{. V3 a! Z2 b) t% ~8 d
/* Start the clocks */
. z/ X4 g3 }' r' c9 u$ nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 d/ y- ]1 A8 U" V1 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; c" m1 C$ C# n* w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. |$ {5 b' g" Z3 L0 v! J* vEDMA3_TRIG_MODE_EVENT);6 R+ l) ]6 Q( a' n6 J# P6 G0 s# P3 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 W1 @/ W; ^) A1 h" i& a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ C* T; t6 Q$ I4 _2 Q# a S2 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& f' I- y N; M/ K$ Z6 R |1 F, e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' W+ U. H1 d. b- i+ g0 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ t4 t, @3 | ^, N* PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 d) [$ k% k) {- a# g& TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, N$ U9 C' p2 @3 g5 _! F7 y
} ' ^- V! a; q! U9 V3 I- t$ T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& h% g o6 S. {/ J) n |