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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( Q$ K# K4 o6 u7 Uinput mcasp_ahclkx,
& `6 Z8 ?6 e# `1 j9 g7 M2 a) o8 b4 Ginput mcasp_aclkx,: `/ R; }, G& g% C+ N9 u, ]
input axr0,
& l/ n6 J. C, w
& ~! b! w8 r' k) j# uoutput mcasp_afsr,( K5 N) }0 k) ^# l5 F. f& [; s
output mcasp_ahclkr,! }, w q+ m4 h0 T8 W
output mcasp_aclkr,! g. [9 \& c: A7 v$ o# u
output axr1,
$ L. x l) x. W. C- l assign mcasp_afsr = mcasp_afsx;0 Q K+ H# O( G; [+ e5 S- m
assign mcasp_aclkr = mcasp_aclkx;* j& e- w7 M* s2 m1 m0 q8 ` o
assign mcasp_ahclkr = mcasp_ahclkx;
5 y' |7 M- \! Bassign axr1 = axr0;
, B' I8 V6 L9 x9 E3 ^9 d& Y! _+ B5 J* g3 F1 Y- Q# y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & c }. x: P2 C: K& ?3 z# S
static void McASPI2SConfigure(void), S+ Q3 |& Y; s4 d+ A& A/ K
{
9 q% e: O2 x" f& Z+ V3 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& D4 B; \. S8 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 _2 s0 C! k# x3 p4 p) p( J2 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 p3 P v1 j; T- zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 O% a9 ^: c; t8 ?9 i6 l# p, Z9 {2 vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: `; B0 k( Q# O" f
MCASP_RX_MODE_DMA);
1 v' A" i. ]4 Y8 }3 t$ f- uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% G) w2 o# C" L7 [/ X; _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ f3 p( U" j5 c1 p$ JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- `& _6 i5 \+ B- B+ ]9 Z/ B# [( SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: j. O" D" A& p, i. U! A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( {# |% n' _0 q: aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, P. y% p4 z4 A8 |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( V& V! l: l0 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 P/ Y* }6 I, B; ?7 v" z4 Y0 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; G X, S, @/ K+ r0 l/ w0x00, 0xFF); /* configure the clock for transmitter */
3 s/ |. b. @3 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 x) `5 @* {; ]* P% e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ~8 N; @7 o; O- S7 R! r* kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' q N/ U/ e& x4 Z1 E9 P0x00, 0xFF);
0 R0 {" s6 Q( V& C. T/ U
7 j. q! v8 z7 c/ n4 N. f/* Enable synchronization of RX and TX sections */ 2 \" R0 h6 |5 c3 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; Z! O" j) y. g3 S5 [& O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) o" J$ e% @$ Y) f3 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% o+ C/ X7 w& E: n; ~
** Set the serializers, Currently only one serializer is set as, L" l9 I& g* Z$ P) D0 o- v
** transmitter and one serializer as receiver.
) [- {+ l( z4 f*/
) F- x8 H: u* R% d$ q! lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: Z4 X# ]" I1 X+ cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) g# A# s3 _; z) F9 X/ B
** Configure the McASP pins
9 a5 L$ g( W2 q** Input - Frame Sync, Clock and Serializer Rx" U# n% c) h7 _$ n9 L9 q
** Output - Serializer Tx is connected to the input of the codec
/ O, M* R. d2 o& ?' B& E*/* I% [/ T2 T- g$ W$ i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, g; |/ k! I' X- rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 K, X: C! _6 ?% C; `/ q! Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ O' v, C' E* P$ m' k: d7 e4 q| MCASP_PIN_ACLKX- Z$ R' E2 a" {1 D0 A
| MCASP_PIN_AHCLKX4 x$ J/ p% p5 J. c& d% ~7 x% `6 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& x6 {/ P8 l1 r$ Z8 a, n6 Z W, vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 P4 G( V; b ]% N$ i$ q7 y, n
| MCASP_TX_CLKFAIL
) u" @+ R0 N( X1 @2 t0 S8 Q' c4 B| MCASP_TX_SYNCERROR
$ w9 s! P: c# Y( S) t2 X; J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! E& Q6 o! |! w8 k| MCASP_RX_CLKFAIL
|; t1 z% p8 c. l) Q- F| MCASP_RX_SYNCERROR 6 B( b5 I* e9 D/ P; c |
| MCASP_RX_OVERRUN);
* [# z* L8 E6 s* E8 i. l" Z} static void I2SDataTxRxActivate(void)
) b& \" f8 ~) A% x- }! i( w{/ }' b# L3 S0 M, A9 k
/* Start the clocks */
3 L0 s, m5 D7 c9 p+ u+ i: B' VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. {+ F' m7 ^+ o! U( PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& B- p4 B% O) q5 T# \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 _; s0 u& T/ k
EDMA3_TRIG_MODE_EVENT);
4 G$ [, a; Z7 g& vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 S& S3 S+ F/ `% x- |5 Y: Y3 |7 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 r5 `' I+ t- pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* B9 B- @1 ?& x: y& h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- n$ M: @- ?! kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- }/ S' l6 `3 w: k( F8 T& u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: F2 u! |, k: G2 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& {/ j+ h) Z6 ~0 ]
}
. J: j+ P: w/ }- u$ T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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