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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: y6 f+ Y; h) S$ o }4 [input mcasp_ahclkx,. b% _8 j# D6 L& W7 ^6 R4 ]4 U
input mcasp_aclkx,+ e" y1 v/ j# w& R$ y
input axr0,1 ?3 \$ a( P( W- ~ z( e* v
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output mcasp_afsr,# `# j7 h' y/ P( B* D
output mcasp_ahclkr,
$ W0 A. q, G8 N: T7 k$ Foutput mcasp_aclkr,
: B7 w) g, }; p9 U3 }$ _output axr1,
( J# s) g# ]0 V" K/ H$ v8 S assign mcasp_afsr = mcasp_afsx;
7 C: _- u# z$ |3 z- j: V( Uassign mcasp_aclkr = mcasp_aclkx;
3 T% ]! s9 e9 G" n, s7 R% V, C3 [0 bassign mcasp_ahclkr = mcasp_ahclkx;' g- P6 R4 s8 S" U
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 D0 S' b( i" A' B
static void McASPI2SConfigure(void)
* S# S5 [, u3 A1 G{1 \9 u2 U2 o0 ?* p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 Z. {, I( j4 {/ q5 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- R! |4 `( X+ }- _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" t0 ^4 x6 Z$ g+ [( NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 E7 {" P: M- V# f O A; J$ S5 c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, h+ K' a- w& g) {, s& V4 l
MCASP_RX_MODE_DMA);
7 s s/ x! {/ A( p, f# H4 I; fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ X: @' S z- V) oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 s7 |2 u' x3 Q, n0 Y# R/ ]* f5 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; c/ Q8 b. n* u. h$ l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 I3 d4 W" m0 c2 S$ z/ `' s: e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 ]( c7 i1 z/ S- ]$ m! j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& D% H) c5 z* {, y% ^# X' _! U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 L7 {& I3 S& jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 r/ W/ X9 s F: b i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 A1 R4 V R8 B/ ]/ c" U
0x00, 0xFF); /* configure the clock for transmitter */: q# \; N# G# n8 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( `) ]. \$ F: ]) E3 ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
V) s+ _$ B6 a: H0 y' O- C) J# e0 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 b% B) Q. x, o2 D
0x00, 0xFF);* H# C) e& O2 e
; a" }- |0 t7 ~9 U- q# ~
/* Enable synchronization of RX and TX sections */ # Y1 h4 Z3 t; K0 }9 }1 N; E7 h0 {. S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 J* j3 o; Q7 k9 n# B% `3 b9 H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 W8 ?: c5 L0 J( c" v, O# U- j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ w! p" k6 E* \ q1 _9 W0 [
** Set the serializers, Currently only one serializer is set as2 J$ P, B3 r$ b3 @2 i7 _
** transmitter and one serializer as receiver.0 _- J. X3 z3 F! B* [4 u
*/
8 b9 p# G5 D# Z1 H) w+ T2 g3 F4 y( ]$ EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. P& m$ V( j& c1 F5 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ]3 H9 [7 U5 V' b% Q** Configure the McASP pins 1 L3 V0 R! l S2 |* G5 q6 ^
** Input - Frame Sync, Clock and Serializer Rx2 M8 B+ L* P9 J) j1 S
** Output - Serializer Tx is connected to the input of the codec
4 u, `, j6 V3 [0 P7 a*/
. S5 k7 o/ @, |; M* {* b; eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
?! P0 Z9 @$ s% q0 v' `& [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); Q H4 p ^6 p) k3 C7 Z. u6 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 M4 ~/ w; i" g3 X# O
| MCASP_PIN_ACLKX
# p1 S+ b+ i% d| MCASP_PIN_AHCLKX2 j* c; P9 L# g' F7 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ P* j9 E1 [3 M$ Q5 \. i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 j5 W! {/ x& I; V* k
| MCASP_TX_CLKFAIL # q2 c$ K9 n% l
| MCASP_TX_SYNCERROR
4 N4 G+ Y w. p* k9 Z2 L G$ h$ C* f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; @ _" f+ l9 g. k( x4 l8 || MCASP_RX_CLKFAIL/ f( ]/ u# W0 J& j6 |6 U: a
| MCASP_RX_SYNCERROR
. \$ q8 P' P$ D" i| MCASP_RX_OVERRUN);, J* c, D3 \" }. x' K
} static void I2SDataTxRxActivate(void)
# j4 D% B/ o& z I- i& z/ n{
O4 N, D0 j8 p' C! r/* Start the clocks */
3 H% I J. c- s- ]5 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& H/ d' U! C) ^3 y0 a8 RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! z+ o- A9 L6 Q- B7 K" C* W+ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ b6 \7 h! t/ }/ Q7 [- d
EDMA3_TRIG_MODE_EVENT);; t8 m8 o7 |" c; J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, a# h5 K5 V3 T7 {$ U. {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ ~/ {; @: I) |; p2 r3 _8 z3 t6 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! h/ u9 ` D1 P5 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 e+ |( S p5 A" |. n: _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ P# S( q$ u1 w) I$ P5 K7 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 W( C( Z( d$ Q( {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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