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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. p0 R0 }) P6 b3 g6 R( t' Vinput mcasp_ahclkx, z, S, z; g. F! B" I8 h! l0 q
input mcasp_aclkx,$ C. K6 A8 ^) ?. h
input axr0,
1 |% u5 t [7 Z x* y9 u+ j
D$ s; R0 `8 G& F0 k1 ooutput mcasp_afsr,
7 s* f) s3 t1 }/ ioutput mcasp_ahclkr,
( O3 s' G7 @& C" o" eoutput mcasp_aclkr,1 l# Y" E, n6 O# f4 `6 {* J$ J! v: |* l
output axr1,
+ b! v( U1 _+ X7 `5 N) K4 g; ` assign mcasp_afsr = mcasp_afsx;
8 g& U6 i% M' E* c/ Iassign mcasp_aclkr = mcasp_aclkx;
& U) X6 @; Q8 }( v+ [assign mcasp_ahclkr = mcasp_ahclkx;4 ]6 m/ f% ^8 l0 w4 q
assign axr1 = axr0;
+ A5 W: [6 Y6 }% G2 H( i2 ]' z" `2 b6 h8 ]9 C% @$ D! m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) X/ z1 @0 Z U' t3 {! A
static void McASPI2SConfigure(void)
/ I Z4 P; u- H6 T* r( p{
9 o. S5 t2 X* b7 ^2 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ y1 o" ~& d0 n& ~/ q+ b, J& w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ x+ {" G5 E! L8 u3 k. a- L" z- p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& j# m! x+ {& A$ Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 e" O& ~/ a) y6 k$ q! L/ aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- f2 I# p2 ]4 J; z6 t
MCASP_RX_MODE_DMA);
# ?& W% y: ?1 D: UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% _/ E, M4 g+ x9 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# G K1 D) K( [" ~; _6 I% {, iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 u5 D" E t: E, d" D) g/ h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. ^5 x- M* [% G c; n. U( L8 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # a$ Y. X0 @9 F$ C% {5 N: F( W. K8 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 {6 ^$ g* U! v! d, a, A9 f5 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( }3 w8 f7 D# K0 n; y8 ]$ w/ S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ z& H" ?% J% ^7 I- M" I! t0 R5 t' m5 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 _# d6 r# R* H( [5 G3 i& S3 ~0 B% U
0x00, 0xFF); /* configure the clock for transmitter */
$ D1 @6 y$ r% O: pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ a/ _8 q( |- q% o. zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " j8 q/ Y7 `: v+ Q; p! v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 j1 h% h+ S% `0 f
0x00, 0xFF);
% @+ ~" b$ V( F9 A8 n4 U! ]' O0 j8 R' v! r* G2 k# B
/* Enable synchronization of RX and TX sections */
. I, N& }4 {8 v2 R6 \) j6 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( Q6 ?0 N% r. f- ?( P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; H/ B6 \7 D8 \* nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& H# H1 \, `2 g1 _& e- m7 m** Set the serializers, Currently only one serializer is set as
( s9 l, x* K# Y6 Q2 E, L** transmitter and one serializer as receiver. [) l0 v5 u* B3 a
*/
W6 @: @$ X2 [! [- H3 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); [# k& I4 t0 [) Q+ {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- k- m$ w+ i; t( a/ a- R** Configure the McASP pins
" b8 \! A+ W( ^** Input - Frame Sync, Clock and Serializer Rx
; w, V7 g0 x) ] W2 ]1 n$ J** Output - Serializer Tx is connected to the input of the codec 5 L2 P* e) T7 {. _5 R( P/ C
*/
7 S9 m6 s* q, f! j+ S2 ?2 }) {* TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" y& d2 c; \1 C6 N7 h! ~/ kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* I' y3 m6 p0 J# m M3 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' `+ T3 }+ i0 Q" a1 H| MCASP_PIN_ACLKX
3 z5 _/ D `$ ]) v8 || MCASP_PIN_AHCLKX
: Q$ f# K4 s% i2 @6 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 V/ Z: M: I u, o- Q C3 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 _; H! `) M' F/ ^- u& E9 \
| MCASP_TX_CLKFAIL 8 r" J6 |- L+ C$ X3 `; S9 s) x' M' o
| MCASP_TX_SYNCERROR( K5 U7 C8 \" s) v- i8 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * T7 [8 s v+ E @1 o- J
| MCASP_RX_CLKFAIL
* S0 j) k! N: H+ K% {; B- R+ P| MCASP_RX_SYNCERROR " V p; N$ p2 D* K
| MCASP_RX_OVERRUN);
/ Y C. \# |1 o$ ~9 w} static void I2SDataTxRxActivate(void)
6 E7 Q/ H% M& w{: l% n" L) E+ N" D
/* Start the clocks */
% { F' H5 O8 o7 B$ [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ @1 i+ e" x' S2 F# P( H4 n# G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 @4 q# m/ S: b. i) C8 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- X) o2 R; C8 O* D3 a4 T
EDMA3_TRIG_MODE_EVENT);; s4 v# B+ b3 g: |9 R! {7 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" u% ?. @ K) a- N* }* uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 M5 C0 J, P; J. zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: \7 l" I1 W# Z! v9 e, _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 h& ~3 N" I# K0 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' X% G* j! }7 ~' x F3 t* ]. C8 B: L9 eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
m+ H0 L; v" f0 W6 I6 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 k7 R4 g N, Q4 N* _5 y
}
* _* m" T ^- R. E* S4 l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 N' G ?" A& j1 @4 N( v
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