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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ ~: u& u! h9 ~ ^input mcasp_ahclkx,
. x0 G! f3 O# T* _# oinput mcasp_aclkx,
7 N5 B) |! v" Ainput axr0,$ I1 i& Z7 q+ B/ i5 D- C, a+ q
N% C' ~& X' R8 q$ I0 aoutput mcasp_afsr,
+ |" C" l) j- h8 d9 ]9 [output mcasp_ahclkr,
7 y) d9 B6 ?! d6 `& j# Q7 Zoutput mcasp_aclkr,1 r7 ?+ F; K2 c6 q
output axr1,
: X/ v# B9 G* B2 Y: { }- ~1 t$ u assign mcasp_afsr = mcasp_afsx;% E% @7 K. ^; R# c
assign mcasp_aclkr = mcasp_aclkx;
$ \/ M' ^$ V7 r' u" Z4 I1 lassign mcasp_ahclkr = mcasp_ahclkx;
6 b+ ?- S% r; z( R/ a( p, N5 oassign axr1 = axr0; $ [# I9 H) q5 J4 w( _% O4 F. h
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # u* r! Y2 g0 U$ i
static void McASPI2SConfigure(void)- n5 P; D( E/ E. a( f4 i$ I
{- {. n1 n4 x( z9 s; \$ @8 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. e6 d+ ^2 `7 G! m1 R3 K- u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 [+ n6 X" Q, O% B" }! R& l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 ~! _5 W9 s- F# j, w+ F% j/ i( lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# g* c# K* @$ p9 w) M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- F, i* y& q, b- x
MCASP_RX_MODE_DMA);0 d: D6 ^. g% e8 b4 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 y u7 l3 c3 X) m: U2 ]2 F1 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; D) m; P+ i! }! s* N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- ^# I& x' O" i! S$ fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, }: w1 K7 ?+ I/ T1 F& oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 M. R9 T4 q% ]" X' _0 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# }" b% w* j# I$ z" F1 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 w9 F3 G5 c' ^2 P3 y* n4 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: J+ W2 {( g% l; ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 c3 J/ b' C5 F' p0 W, \0x00, 0xFF); /* configure the clock for transmitter */
( w% L6 |, W& c2 B. mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 |2 g, d* k9 \5 d# u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- F/ ^- r7 J) g4 s4 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* M- p# d& ~. }. n; _; i7 f0x00, 0xFF);
7 @% c- E! k6 i7 Y& Q1 m. J2 [* ]( V: Y+ I
/* Enable synchronization of RX and TX sections */ % B ^: {! p* {) g- k% R$ f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ F+ B) W* i/ Y2 j4 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 ^; F9 ]* t3 E2 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 u& I; f. j+ G+ `* x
** Set the serializers, Currently only one serializer is set as. K @0 B! R" ?, z: Y- f# l
** transmitter and one serializer as receiver.
$ Z% [" y; B& y0 q4 ^*/
3 B& {( X% ~- Z3 K- f1 \. SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- t3 J% J+ C( g9 |- W0 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, B& @( W( u1 U
** Configure the McASP pins
$ p( t2 B2 w0 ^ N1 P9 k" T** Input - Frame Sync, Clock and Serializer Rx
1 F- j% I. q) l! N** Output - Serializer Tx is connected to the input of the codec
; W/ H8 m: c5 X9 ?*/
4 G! P3 ]( b' C+ EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 x' b* M- X( ] ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 w- Y3 N; I4 D2 ]* P2 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" }+ f: n5 ?. B9 o; y; \: j
| MCASP_PIN_ACLKX, B( a$ c b3 w* o4 M
| MCASP_PIN_AHCLKX
. g& h9 q) I4 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 h1 z# n" K% J, J/ {. d. n% IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" P) y, A% o% V9 }* w| MCASP_TX_CLKFAIL
2 ]/ T$ ^3 ^" _5 R/ T| MCASP_TX_SYNCERROR
* a1 f1 Z0 J8 Z7 N1 M' _+ @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- |+ h/ b& Q6 B- c q| MCASP_RX_CLKFAIL+ G% O! c0 k' f1 b1 h
| MCASP_RX_SYNCERROR 9 h0 O0 F" ]* U' f, E
| MCASP_RX_OVERRUN);; G( ~4 V+ n1 V. b O# S
} static void I2SDataTxRxActivate(void)
6 `7 \$ y5 [9 u: Z' L{
& j% ?! {; L7 i4 A' |, o/* Start the clocks */9 _3 ]6 @* h ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& E9 w$ c$ l* x5 U& vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* ?1 e2 ~0 P5 r& s& j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: z9 W3 O% B2 l% s- V/ fEDMA3_TRIG_MODE_EVENT);
# h C6 I* }; t FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 P- Q% Q/ M. g6 N% v( s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; A0 t& M+ w0 B* T8 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 a6 n2 V% ^& n) p( l" W2 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 ^# l$ r1 R4 c# gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ R% F3 K3 A/ |! @2 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* E: l9 {5 A5 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 x4 u# a6 G# S5 I! F# E( T; z8 z
}
/ D4 p1 r, S; }1 P* X' ]8 X+ U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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