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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. P, d5 t/ w3 Z. J2 c) R& t% e3 Xinput mcasp_ahclkx,
) n4 p) @7 |( e+ K2 ?, h2 M- M- Binput mcasp_aclkx,
* w- u8 u0 ?0 ~% _1 S" iinput axr0,
$ b# H0 m; w& a5 S
4 |2 R( M9 H- Y+ z6 ~9 }output mcasp_afsr,
i4 _) g$ A2 ?9 g/ J) q" Coutput mcasp_ahclkr,6 @5 h( a v- g( ?
output mcasp_aclkr,( V* S, F/ Z8 Z- L! g
output axr1,
# Z( J# y- q, y" e j* @( b5 w5 x assign mcasp_afsr = mcasp_afsx;) S% w0 s3 |9 X
assign mcasp_aclkr = mcasp_aclkx;1 u5 _5 {9 S4 H: v6 I
assign mcasp_ahclkr = mcasp_ahclkx;# {2 C7 L: P3 K! j: W
assign axr1 = axr0; , f' `" M6 `3 J, d
7 {9 a6 T3 S; N1 _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' ~& M+ O* g/ G, R9 kstatic void McASPI2SConfigure(void)7 P. Y4 S* G& T, Q
{
8 {( D5 E: ]# T5 HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# O9 S" f4 I5 n8 l1 b8 U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; m% S2 c. e/ I2 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 a) J8 J! o; ?& _' j' V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, o( v4 A' x% `# p& O$ j o, G$ o9 {% dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 k4 M# \# o& X! ]9 }9 w0 p& v2 W
MCASP_RX_MODE_DMA);. V& X6 I9 P, I( H9 \2 t3 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 N% }' K4 n: ~% J% I( uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 j I( C/ v0 Y% T" }" `4 ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 T3 b! ?$ A/ o. F* M* ~& @8 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); o% O3 X8 u% |1 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 e) z6 X! g- {% rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! z# Z `% _) c" t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* p, L* {% P5 r. h- l. h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / V: e+ e6 J4 X& \8 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* s! @$ }. m9 Z1 ~4 {
0x00, 0xFF); /* configure the clock for transmitter */
, F9 ]/ s* L8 L1 H# ]3 W' MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: n: C- E& n! ~& \) B: a$ k0 Q* t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + X! A* M& y- p; Z! I" ^+ x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) w4 z8 I1 b9 I" K
0x00, 0xFF);
, b, b# Z, R# F
' S( ^4 P/ c7 }$ o$ L/* Enable synchronization of RX and TX sections */ ) H( T; l3 f0 E: Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 Q8 l0 c. _' i( N( dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ h3 _' T% r& z0 U _' t8 X$ I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 R! J: V$ A# a1 a+ W
** Set the serializers, Currently only one serializer is set as
6 d3 T0 E q8 ]' M+ P6 O8 p8 |# V0 Q** transmitter and one serializer as receiver./ _6 P# e# {- _6 L
*/
. L) d, G. C# S& ` Q) Q: vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" B6 D+ k7 f; l9 b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' v2 y5 ^0 e# j( o8 G7 M** Configure the McASP pins
: q! P6 r3 N' ~# p* |; q" A** Input - Frame Sync, Clock and Serializer Rx% ^2 F8 t0 O+ B; J1 s
** Output - Serializer Tx is connected to the input of the codec
' d1 J1 S6 w5 n, |+ x*/" {5 y3 B8 t) Q. s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- R' H, c6 J0 A: \2 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* l5 `) W: y7 ]4 m1 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 e; x! d' f8 \, ~% A2 i& Z| MCASP_PIN_ACLKX
2 D0 E8 ~5 E+ g| MCASP_PIN_AHCLKX
) T5 R* P8 s, `# a! g. v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* \: [2 }0 [+ y/ I( U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 O1 B2 D; d+ I3 |3 V# W9 g( O
| MCASP_TX_CLKFAIL ' G# i. Q% R* O& F
| MCASP_TX_SYNCERROR
& [0 Z# s$ d, j2 c8 L) G* Y `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / L% Q4 L; }2 P: B0 \+ w0 |9 N
| MCASP_RX_CLKFAIL. J0 F' f& F9 N' l5 ^6 s! R; h
| MCASP_RX_SYNCERROR
3 u; Y" }' s8 B| MCASP_RX_OVERRUN);
7 }9 w2 E+ Z) o8 C! H7 j: H} static void I2SDataTxRxActivate(void)% A J% H: m5 i" W6 {
{
T) G4 V2 ]# n/ V$ b9 j/* Start the clocks */
; Z% n6 ^3 B SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 m& H) A2 |4 ~1 Y T% }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// e. k# \# k8 [/ O* T" x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ g6 b1 F V1 U6 xEDMA3_TRIG_MODE_EVENT);
5 [8 u8 V- d, e& o$ V0 O3 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 J. ^+ Y/ N, ~, t. `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( X/ S9 c& |) x& _, t: ^# d8 y! }3 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 ^- V+ H+ j- R* Z4 B+ M: c6 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 _" s+ Y* x- f: jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 k) x; ~7 Z H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% k# h, d2 b0 n4 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: Q. c% q4 f" _( D7 ]# h" v* K. ~# ^
} 4 I: [4 C8 H& V7 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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