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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ [; ^: ]% }& Minput mcasp_ahclkx,- c8 E- D _' N" o8 ]- z5 {
input mcasp_aclkx,$ e$ K% r" L; X2 ?* @* S
input axr0,
: ^ V5 F" t. E5 A* Z: h7 D4 P! b0 A+ S/ U2 t
output mcasp_afsr,+ C" U1 G' N g l( Y
output mcasp_ahclkr,
- |9 C6 _% [0 _8 g7 ~: Ooutput mcasp_aclkr,
! Q3 `/ O" f" x- w2 T% E: R/ ~output axr1,
, t2 E% Y& P v; b7 X/ o4 i assign mcasp_afsr = mcasp_afsx;7 }" x! q3 ^) e7 f
assign mcasp_aclkr = mcasp_aclkx;
* f- j8 w: Q7 I; Aassign mcasp_ahclkr = mcasp_ahclkx;8 [' W4 f P, M, G p! H* B
assign axr1 = axr0;
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1 m/ k: ^" X% t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 P& F k; h$ ~# ]/ A/ V2 w
static void McASPI2SConfigure(void)+ Q' T% D- q4 H/ l; r3 X) z
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 L. ]0 Z- _& g7 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% w2 i; O1 ~" C& E- @( ?4 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 V: f0 E3 |" w" |' v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 H# \; c" ?! E; J' d! yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 m/ Y4 G% h2 b" [- j. `MCASP_RX_MODE_DMA);
7 M$ @" K8 H* \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( A' W6 r* Z6 Y: Z' Z0 s2 k- hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 t0 U9 i$ Q; J. P$ i. a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% @7 G: J+ |1 Q7 R* x; bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- z! D' m& m$ `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 p5 p4 T; F) ]1 Z0 j+ H ~* i4 |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* ]: z* w! P. ?! \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- p2 E/ X( ]4 ^# F7 w+ V+ u- D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- l. d1 ?4 W" M& rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& [9 h6 j$ X2 G0x00, 0xFF); /* configure the clock for transmitter */& N+ Q7 V0 _- U" [ w: p q0 C3 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ |' h& l' ?! |+ m6 C Y: ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 W/ V" N `% c/ i" d8 R& k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- u* k; B6 F0 {' X8 M: D% |. Y+ G0x00, 0xFF);
; l- m+ L U0 q: f2 @9 N' t9 t" b+ l" A* Z- l
/* Enable synchronization of RX and TX sections */
1 W! s7 ~* X xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* O" G! o4 k9 B1 ]& \! s, P( c* |: T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 {* S" ^. C$ O! \) H8 S- L0 |9 l# GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( B# f1 H( v! v/ D$ v j** Set the serializers, Currently only one serializer is set as
8 X$ |' Q/ H7 `0 C' W6 q% @** transmitter and one serializer as receiver.
' V( { Q* Z, u6 U9 F7 l# z6 [*/' T+ m* O8 n) u9 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ `/ B5 s6 t/ w3 f3 V5 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' K, U" h" j' i- h6 S# Z0 q** Configure the McASP pins
/ W0 `+ D( b8 |** Input - Frame Sync, Clock and Serializer Rx
% e6 \! `4 B# k. C2 L/ _** Output - Serializer Tx is connected to the input of the codec
& z, C' p1 @+ y' U/ c*/" \* S2 i* ~6 A* o' [) z2 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# n! w" Z# V4 v: @! f$ n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# q/ s' T8 m* u. [) }; f* p1 F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 N& k8 F3 q. u7 W3 k| MCASP_PIN_ACLKX# M( @# K1 ?/ D9 l- T
| MCASP_PIN_AHCLKX" L; x* M4 l1 z1 T2 O9 \, b9 |( [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( T6 o, p6 z/ R) }3 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& {, z& q4 ~. n6 H8 C4 f- k! S2 O| MCASP_TX_CLKFAIL ! R" T: ^4 \1 N* O3 }1 X
| MCASP_TX_SYNCERROR/ T6 |7 L3 a: d6 ~# a' E% a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) Z% R' V5 A: s0 w) p| MCASP_RX_CLKFAIL
* a1 z8 S' n3 v7 x7 ^| MCASP_RX_SYNCERROR
3 a( f3 r. P# l n$ I( r| MCASP_RX_OVERRUN);% w! N3 o' \/ w. Y$ o1 n6 N
} static void I2SDataTxRxActivate(void)
+ V. V0 n3 ]4 N# W{
- C' F( ?) P t- m0 w% f+ n/* Start the clocks */
1 u- ?, g) p8 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 s" j4 S+ K0 }, ~ x0 Y4 x& [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* G7 u& c! Z" T* l8 L) O1 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 N7 o/ G' ?$ A5 a5 i/ v
EDMA3_TRIG_MODE_EVENT);+ f. }+ u6 `; B1 ?0 P {" n( z* G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * ?! a$ I& ?* T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( v$ a9 x e" p6 b3 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" J$ T# m3 A9 Q! T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 j2 r( ]" r# c5 e# f0 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 c+ ]7 Y& m) ]9 f" {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. i# o6 L j- u8 o# T. E5 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# n6 Z5 }& c6 z) ?
} * ~. N7 d5 |: v* E: Z- d* b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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