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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 X- g# x6 f( Qinput mcasp_ahclkx,; ?- x* h* g! n
input mcasp_aclkx,& m2 r0 O/ S5 K3 R" m
input axr0,, h* }' y* {* u7 w& B1 T' Z$ e6 p
; D5 S, n3 i* z; L! |6 houtput mcasp_afsr,
6 A" }0 I3 e& {5 Y9 I' K, q# ^% Coutput mcasp_ahclkr,
' t' K- Y3 Y' W5 q; B) ]output mcasp_aclkr,6 b0 c* H7 C, [' G& N
output axr1,% v. |; f+ i* {/ T0 k. D) ^
assign mcasp_afsr = mcasp_afsx;
; _6 _2 i9 ^" U9 W7 K2 h! C: W! Bassign mcasp_aclkr = mcasp_aclkx;# u G. f8 y" y# E0 ~% g
assign mcasp_ahclkr = mcasp_ahclkx;
# h! K# O( ?+ V2 Y3 Sassign axr1 = axr0; ) e0 h, r; K6 n7 Y! I2 F" s
% L L4 W8 X( [. }9 F, k+ U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 Z+ D+ e$ S+ R: Lstatic void McASPI2SConfigure(void)* y: y0 b6 h6 y! X+ p/ Y3 @
{
- H) ~7 y* o" u p8 ?7 f3 S8 {8 iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ p3 j+ z2 y8 e* x6 f, D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# O: [0 O A7 ~ u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, ]& n* P Q+ ^7 T/ }. V4 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 b4 H% p. }' P4 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- I/ K1 A& d1 J! ` q. j
MCASP_RX_MODE_DMA);
" P& } |& X7 K3 g xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& C5 f0 f1 v: Z# W6 l/ `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: N6 f1 S$ r1 r8 r, R: o' o0 }% x5 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ @% ?% h2 ?1 f, M4 rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ n: ?' O* X0 I, k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 K) Q4 ^2 p6 W: E: Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 Y9 e, F! G5 m7 E/ @5 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 e6 x# |! R L6 D5 @: C8 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# z3 j2 q% K# b3 r! H( z, |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
I( s* S7 q( J- |* x: }0x00, 0xFF); /* configure the clock for transmitter */
, k( ^3 M- u9 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# F; H; D3 E# c% I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 H2 E8 T/ M/ B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. Q. A5 ^- X1 O3 C, P- b
0x00, 0xFF);
# a0 V' a9 \3 O6 Q/ w8 I. f( A2 w+ T7 E! A4 [$ U
/* Enable synchronization of RX and TX sections */ , l; L, i: W0 V. R' z( i, k0 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
^/ a% ~0 k! I; d7 g$ ~6 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 N7 G1 P% b% @% k1 D! Q; F9 p/ sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 C. M3 o. h* B
** Set the serializers, Currently only one serializer is set as6 K- H% }! e$ n% W
** transmitter and one serializer as receiver.
* T0 b; B$ p+ r; I! B1 e+ P% b$ a. |*/6 a/ n6 [1 z2 N" O# y, {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 t, J4 e5 Q B5 q' ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c% B ` W( k [
** Configure the McASP pins
& q2 h8 n [- J+ e: g9 D** Input - Frame Sync, Clock and Serializer Rx
$ P/ h' A+ u6 b" }4 \8 O** Output - Serializer Tx is connected to the input of the codec
6 Z* @, u' w2 h; b*/; `& r5 L( x1 k. i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 B. U; d( ]: c6 O& T" @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ y4 t( @6 y1 b' J/ }2 K/ |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 @6 ~: z6 Z" ]7 z: D| MCASP_PIN_ACLKX6 c- s/ W; `5 W
| MCASP_PIN_AHCLKX; [9 }; }$ G# u1 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 ^+ a( h' ?" S. c/ ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) G) U8 l4 |/ J5 O7 W| MCASP_TX_CLKFAIL
. s+ s. B4 F" ^* U7 Z* `| MCASP_TX_SYNCERROR( Q- e- g- D# [+ \7 w1 L4 M4 {* f) X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 S& e T8 ]8 D5 w; V
| MCASP_RX_CLKFAIL0 n/ x: f. m- R. P" e; _
| MCASP_RX_SYNCERROR
5 @4 i1 f3 i$ c" {# p, V3 F| MCASP_RX_OVERRUN);
/ F4 ~8 V' k4 { o} static void I2SDataTxRxActivate(void)" l0 } F3 e9 e) x' H4 l2 W
{; N O5 S h+ ^) W- m& D
/* Start the clocks */5 t( ^+ z+ W1 B- Q. f1 Z, o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 H v1 Z) c; I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 [6 @ E$ t) K& E$ p; |7 N4 R* F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, J. ~& ^' C# s" p; [) C
EDMA3_TRIG_MODE_EVENT);
# h4 c- |7 |1 V O4 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- g* @) g; U; E2 b4 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* w5 H2 s+ ^: T4 C* m: B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 p5 I# E4 }7 [7 c; ~2 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 W9 y n* a) V m1 G) ^" z: iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 g/ d% P, W% f, P; U q7 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 P) D6 X% |" ~+ T) D# o0 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& ~ f8 @5 }4 [) m% J0 c+ C& D
} 2 h1 i2 l9 I% S. l/ d& ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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