|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ c; S6 J" N: t, M9 T5 D8 L1 K
input mcasp_ahclkx,! ` Y' I6 z: A* n
input mcasp_aclkx,, D+ l' |/ E2 p& g" z
input axr0,; K- l! v* @/ g% r ?, @' [8 T
" C7 |2 M$ |! i# L; Z b7 j$ f
output mcasp_afsr,
$ ]+ h' d* ~+ P d Y* joutput mcasp_ahclkr,( |; M u- k1 `" m: G: f5 |
output mcasp_aclkr,
* n; E% H. y+ Poutput axr1,; E& D3 I3 h6 g# x. ?" \
assign mcasp_afsr = mcasp_afsx;2 i) u7 U, w: [- Y8 D
assign mcasp_aclkr = mcasp_aclkx;
# O, ^5 r5 x$ L8 |assign mcasp_ahclkr = mcasp_ahclkx; D- n, d' h6 c; k1 }9 N. J! ~! L
assign axr1 = axr0; ) I) p. U# m4 P8 _; \ `* I+ b6 z
/ P0 ?9 O/ L9 q; W1 u! q. K+ Y! {2 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# j: ]9 W$ k' K. H/ K# b8 Jstatic void McASPI2SConfigure(void)% D% P, U3 }% [
{
9 b, o6 c( F. r: L3 Y& f# {McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 h9 G# g! G O g* N5 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 D* Z6 e- Z0 t( DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) U9 M' o. `, t; w i6 C; _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 O4 Q' _2 K n1 Y* w$ ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ e ?: w/ V+ D" s* g ^
MCASP_RX_MODE_DMA);
^0 {3 y5 W3 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
F/ ^. Z3 C! [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 I' U9 I, U d* J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 v- u4 I6 G0 X/ e7 r0 v3 N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 z. Y& m; d# I/ D4 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, [; l& S$ {- P; @3 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 Q& g7 ?7 [' d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# I8 D! ?8 ~; ]4 ?! GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, `1 M0 H2 J% v) r9 e) `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! L. C. f' g8 D1 ~$ V& |0x00, 0xFF); /* configure the clock for transmitter */
, K w: O( g! n, ^; L2 P0 B. b. PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 e5 p$ S, ?+ t& ]4 k2 d2 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Q" G. J& x- }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, Z/ A8 w/ N9 r* t' J
0x00, 0xFF);
" r# t7 k n8 M9 c" T+ `
0 ?' j9 k# j$ T+ ^/* Enable synchronization of RX and TX sections */
! I' t7 v) f/ kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# Q9 @" @6 p) M1 r" Y5 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" L3 S# Z" e1 b1 S6 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. N: v O4 e; b0 Z$ ~; N' Q** Set the serializers, Currently only one serializer is set as
3 i6 ]' C: _; T/ i+ }** transmitter and one serializer as receiver.
7 E( P! }& x( U*// M3 L; t1 s' h( P: V, x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* E2 ~6 v7 W$ c. a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) C% O0 D6 T( f! w** Configure the McASP pins
; m" ]0 C8 K& o$ T" \$ t" ~** Input - Frame Sync, Clock and Serializer Rx3 d4 L' f5 l! n
** Output - Serializer Tx is connected to the input of the codec
3 A; _8 a' a; y; Z7 w6 K8 \*/
, C" m1 P- `* J% vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 c- r. s, Y# z0 \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ^0 c9 J8 I9 W9 M( V0 U; X! T# A, RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* ?3 g( M: \$ l
| MCASP_PIN_ACLKX
; D! q( J9 ^, Q' a& e# H| MCASP_PIN_AHCLKX$ z8 ~8 N; N* f3 s; Q# v; q7 t6 B) @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% `2 l6 T" ]- u0 n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! q" T$ E3 ]" Q6 [0 C: N
| MCASP_TX_CLKFAIL 8 s1 n L3 |- o: }0 z
| MCASP_TX_SYNCERROR7 e. P5 y! I& P: O& C* D) K% D; `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 W Q$ J0 U) @4 O/ ?* _
| MCASP_RX_CLKFAIL
7 m7 d5 j0 D% {+ J| MCASP_RX_SYNCERROR 3 J' h/ n; y1 f; P* z
| MCASP_RX_OVERRUN);
4 ~" a% ?7 j, l8 \, y: t5 d} static void I2SDataTxRxActivate(void)
0 O' p: ~; N" c/ o' u8 ]/ F. u{7 W. D5 r: C( t s7 h
/* Start the clocks */
( z0 A c0 B: k1 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& ~( u% ?: w# k4 b4 }( [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ E) i( u" A" Y- G5 C7 Q2 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' x& f, C% t5 H
EDMA3_TRIG_MODE_EVENT);
' N, [' P, ^9 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# }+ \! q3 }8 ~7 P' aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 r7 Q, Z( F2 l& w8 q" W/ L) mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 v8 g6 f5 U2 E) _ w7 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 U% L3 X" j. ^0 u/ m8 N6 N4 y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! P, L r) s: m2 L0 U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 `3 g" @% @4 x" |; }+ U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" R" W; _5 s/ ~& {; c0 `+ D
}
$ B# w0 b( O$ ?; c% H: Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 ^ b9 g7 P3 E+ S- U4 ] |