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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# }9 L3 n( l$ H) j2 C
input mcasp_ahclkx,
1 |4 ?; J& e/ U8 x: O% ^3 Q6 X5 Q3 winput mcasp_aclkx," K k4 q/ v9 Q; x0 z
input axr0,
0 r/ f( j& }4 M G
" e0 m& }8 [% Z/ \7 Q6 g' C6 ]: foutput mcasp_afsr,
4 o7 l+ W0 E! q8 |/ I/ i+ ~" E" m# Zoutput mcasp_ahclkr,
: a! Y/ F, \& H& v* i6 foutput mcasp_aclkr,/ d! f! j4 | V x/ K
output axr1,1 f& `0 f* ^* a2 C' g
assign mcasp_afsr = mcasp_afsx;( X0 ]& o# ?6 `0 g
assign mcasp_aclkr = mcasp_aclkx;! d( p- n" }. V5 h) O/ J1 }$ s
assign mcasp_ahclkr = mcasp_ahclkx;
* G- l) ~: G" Iassign axr1 = axr0; ! w Q) d- ~' _. B/ g7 c$ ?
. ~; J( h- M$ E2 @0 j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , H3 f: ?1 E* n; ^, V, m2 r
static void McASPI2SConfigure(void)
: L# ^2 \. l1 G1 N {- f{4 s" T+ }9 |* [' ?, ^ A+ v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 O! S+ b9 k4 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& I! U$ ~+ `& uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. @. T. C$ d4 ]6 s) x7 @% qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// g* ?1 \/ r7 Z! Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: X/ m& v$ Q M NMCASP_RX_MODE_DMA);
" p" l' Z. G) r; c: S- rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* M. h$ u0 L u# s# m# l5 Z7 D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ L; h% t) Y4 V, \; W' f% VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : ?) O, S* o" a6 |9 I g" y0 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' d& g( E5 \! Q O! XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. o6 M8 _0 ^% ~( O4 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: r- l' |( N4 i4 s# X4 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- [) m7 n2 p+ w) lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 Q+ Q( Z8 _' Q! I Z2 @( |. [4 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 ?2 v; P# `& u3 m
0x00, 0xFF); /* configure the clock for transmitter */
* h; t* k) p/ ~. D- gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& ~6 s; I5 j3 ?2 K) `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 m8 G( |0 I% p. |% n( }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 o" }' Y4 @2 j# K5 e, S
0x00, 0xFF);
. q; \1 c& E/ v5 H" n
2 g7 }' K' k0 f( X/* Enable synchronization of RX and TX sections */ . H' n! n8 z/ h% J2 w/ t) e! w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( v0 L6 Z( W: d5 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 D) \- W' B* e$ n* Z# q* JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 A8 C' \8 Y: Y+ A
** Set the serializers, Currently only one serializer is set as
* S) c1 W' K- |: P& h4 v** transmitter and one serializer as receiver.
( Y' Q' }$ }, e2 C R*/
2 ]: P+ M, E% c! u* \- N* R% tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: D: }* H; A% R% B1 i/ W% qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 O# v& S: Y' k- h/ [; D7 q- I
** Configure the McASP pins
) p! K! K7 D7 R" z** Input - Frame Sync, Clock and Serializer Rx& G' [" ?9 a# }/ P
** Output - Serializer Tx is connected to the input of the codec + @5 L- m7 f/ [2 h& g& K. D$ x
*/
0 ]# u2 }, Y0 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ U3 e* V' s4 M# X$ X5 B- cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 B; e1 V' o9 M8 i7 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 O; f/ G/ F# Q8 {
| MCASP_PIN_ACLKX# `1 L4 Z2 c6 g. f2 j7 J
| MCASP_PIN_AHCLKX! o+ M$ Z4 b1 k" t$ r; `5 Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% G- I% D7 ~' T6 y9 [* v4 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " Q. \$ g I+ E" ^% `6 ~$ |. ~
| MCASP_TX_CLKFAIL 1 E# R6 j8 y( y, M( ~
| MCASP_TX_SYNCERROR
9 G2 \8 Y+ l+ J, N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + J4 m# e1 N& _
| MCASP_RX_CLKFAIL3 g' [1 H$ K8 n( M
| MCASP_RX_SYNCERROR
& v, \ I o2 A| MCASP_RX_OVERRUN);- V; C. N* p K1 K: x
} static void I2SDataTxRxActivate(void)$ s/ f3 v8 s. i" u+ o0 V1 A
{: r% Y6 I8 E' \) t! K* y: J
/* Start the clocks */
$ L" {5 `0 r, T. l1 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 v4 n5 [1 m9 l4 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ I9 w: p$ u; z$ O0 O, jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) S# ?4 q; F u0 _# [3 C; e8 v3 z& d
EDMA3_TRIG_MODE_EVENT);6 k; r" K5 t4 y' t9 x( y' c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, y7 Z1 Q5 u# c1 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 E' c# k! L' z: [; F' \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ G( K% I- y u- F9 R6 X2 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 A. x) i" I( N" {# E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// ^, _3 R2 F/ J% T& f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 E. b- k4 I3 d3 X& n* l. UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 ]% W' {7 a% [! ]} + E1 L( U ~. P1 x; @3 B1 f' l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 a5 U4 p- `( ]
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