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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, c6 m% U+ ~! N p. m9 J6 s6 i- Minput mcasp_ahclkx,
' k0 g( @4 Q Ainput mcasp_aclkx,3 H% v7 C8 N* r7 o; r6 n
input axr0,/ U2 N4 m. J8 l1 c. G8 j
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output mcasp_afsr,
5 }5 |3 E$ O8 ~- N: coutput mcasp_ahclkr,. m# K9 D! U! k( [2 i. l3 R
output mcasp_aclkr,
/ z! ^1 v. V3 B% Y: P( S: c* Voutput axr1,+ S* c7 T6 a4 {) I8 [# o9 L
assign mcasp_afsr = mcasp_afsx;* m/ r9 F" g2 r
assign mcasp_aclkr = mcasp_aclkx;7 ]* q g" g- v# B
assign mcasp_ahclkr = mcasp_ahclkx;; i: @6 \+ p$ j
assign axr1 = axr0;
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4 J5 o' e2 ?7 |* y& N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) r5 w5 {9 S0 ~2 B7 U
static void McASPI2SConfigure(void)
* F* ?% {8 L0 H. x% O* t2 M{3 p4 n! J) p6 U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; X! X* G! U4 Z" B& Y. \* A) UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( U( Y2 z" h3 E$ IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- o, x! M& H! j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& E% Y4 `7 K( h+ ?$ g/ B( S% C. iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
W# [* N% A) L6 f$ B! r/ N7 CMCASP_RX_MODE_DMA);
0 |$ W: g' K! _ f( oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 ]$ s+ X7 p! [/ @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% i* H2 r! I3 G4 t' A1 ]9 t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ C4 A# b) L& q- J; PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( @' f6 T |' {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 J* Q/ h# V9 p6 {% UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 W7 [% N B% k. j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; ]9 N$ g4 F$ z! l" M" cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" ^: r* `; |& IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 P8 U, A* W0 H* ]9 ], k
0x00, 0xFF); /* configure the clock for transmitter *// _3 n! z8 i( T0 Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 e$ P) B8 @3 ?9 z$ q) q' e; s* e/ {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 i; E0 f3 d- D% X# V( `# ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 A) w N4 Q( `3 I" n0x00, 0xFF);
, B+ {3 ?, c1 ^9 S$ V: P j2 a" K6 S- e0 E6 B
/* Enable synchronization of RX and TX sections */ 6 ~# v! |# I; [/ i/ C. N3 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 {7 j9 u3 k* _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 l- X5 r' O' }0 N6 s4 N4 J A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( }' }9 a# E' C% ~: z
** Set the serializers, Currently only one serializer is set as
. X& Z& u' b( ^ d2 R/ ^9 X** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# K R4 Y. U" @9 r: ^8 v7 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 i) R6 u9 }: m+ m0 [/ l
** Configure the McASP pins " K5 G3 A/ l; u# o. Z
** Input - Frame Sync, Clock and Serializer Rx
' K: }$ U* T% D1 n4 c** Output - Serializer Tx is connected to the input of the codec
7 C' L; v" m* X( U( Z! ?6 y*/
* {( d$ K% S [ d G3 d9 x/ H# O; sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 F" g, ^+ _. `' ^/ U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 K1 s5 _4 u3 C# g3 z3 k2 u( `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# y/ o" a8 B4 p
| MCASP_PIN_ACLKX/ F0 K% o& h+ C# f' E* x
| MCASP_PIN_AHCLKX n4 n5 ]; F5 b5 ?: E. f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 e7 {$ j* E4 R# G; `" aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 U; v% G: _% c9 z8 w8 s8 {% T* Y* m
| MCASP_TX_CLKFAIL
K- b: H; G, i/ [" || MCASP_TX_SYNCERROR
" S, d1 q! r2 Z# V" K0 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# U, \0 n- W( i: [) U| MCASP_RX_CLKFAIL
J; ]0 q1 e9 X. `| MCASP_RX_SYNCERROR
/ @ I5 c4 ] h& a+ y| MCASP_RX_OVERRUN);6 F7 \3 d+ T& `5 t" Y
} static void I2SDataTxRxActivate(void)
/ I" F9 s/ \( `& M5 u{
: o6 P3 U: X# S. G5 c( K/* Start the clocks */
" `# ] E' i* h( {. @7 h0 k0 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 U/ {0 F0 z8 W4 W' d8 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ a4 l p* b+ C- C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% k( Y8 U6 b; o0 i
EDMA3_TRIG_MODE_EVENT);
3 j: w5 o. C6 c% b* e# }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ R$ l, V8 G3 C0 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% Z8 T6 W! m) Z2 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ |0 Z! F5 c$ W8 m# V/ ^, }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 D% e/ |: ]% V; Z4 w/ u7 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 a& E: M: x5 \7 J: t9 d7 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 e( ^% B! j) b. ^ G2 f' D! C+ d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ v: g4 Y! Y, [ B0 W
}
" T i: R$ d: @/ q) \% @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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