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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! X8 ?1 |! L# V7 Uinput mcasp_ahclkx,
2 h3 E. Q. q( A( M8 pinput mcasp_aclkx,7 I$ ?% {( D% J
input axr0,% }# f+ S. T) K* R3 T7 a% O+ r9 t4 n
$ ?2 ?2 z# M4 M
output mcasp_afsr,7 A t& l" ]. U+ V
output mcasp_ahclkr,
: H" K/ m! Q1 E8 b4 r+ ?+ B: doutput mcasp_aclkr,4 z% Q( f1 t7 Q# O- s4 S2 X
output axr1,( A a! f! v$ E8 U; P1 i' k( ]9 l
assign mcasp_afsr = mcasp_afsx;( N; ^2 K' R# a8 U
assign mcasp_aclkr = mcasp_aclkx;" f) B4 M# R ]
assign mcasp_ahclkr = mcasp_ahclkx;
6 }+ k6 n K# R( u" Jassign axr1 = axr0; " S& L4 D# W- ^0 l
. N* z7 e, T, e! H- C) q! {& T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 a6 w0 d" c+ d7 z9 N+ [' O& U9 r9 o+ Y) X
static void McASPI2SConfigure(void)2 [: r- P% M5 v- ?) F' H
{
& q1 j6 Z+ w" f3 mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, L; I0 t$ Q+ E1 p. P# Z1 f6 i# FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. s3 m5 q7 A& f9 C+ H5 ]* F! SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 g+ J7 P; m9 L% w- q! W) tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# y: `) x L* r% k O- D' k/ O/ nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ S2 d& b2 X; O8 U- r0 i8 N0 J; gMCASP_RX_MODE_DMA);# V" l4 ?9 D* L' P* }* K/ ]8 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. Z3 Q+ ` K3 A1 k! r4 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ U! a( W' L- L; r8 L% W C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 k4 p% H/ I! y' Y8 r+ B* cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 b2 {, C$ w, g7 j' O' U. t2 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& L& N$ F4 n8 n8 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ d5 W4 L' W$ G/ Z+ z. v6 G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( ]# A5 N0 k3 \! [- K! X6 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 c( m* n& _5 h% M* eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; a' k$ w5 ^4 c: Y+ j F3 Z# `0x00, 0xFF); /* configure the clock for transmitter */5 y4 C( G& _5 Q& U' v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# \% Z( D! ~ T5 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 y3 R/ i' J- V% l" j/ H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. m: k( f: Q) I+ e- g0x00, 0xFF);
0 w* b- y4 c# `) C7 ^3 \, t% v5 ~! w+ X, q+ ^
/* Enable synchronization of RX and TX sections */ 7 R' q1 S u8 d8 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ \, J8 g' F, n8 r6 `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; \" g( H% @% Q: z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" p, z, X X+ o( \$ }9 l9 J0 A
** Set the serializers, Currently only one serializer is set as
]' D' A, s4 w) t** transmitter and one serializer as receiver.
0 U$ w7 a7 z+ P3 y& D2 d' o*/7 K# m# y& v* K5 ^! A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ C) P n* v# C7 x8 \9 [0 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** a' L' W4 r8 M6 u' ]* V8 N
** Configure the McASP pins % @) Q6 A) O1 Z$ W, i
** Input - Frame Sync, Clock and Serializer Rx; N, V. |7 \% j5 I
** Output - Serializer Tx is connected to the input of the codec
- @( k' H& H# X: b' |*// L8 M/ F: L3 w& j* Y9 z, e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ @& P D* J: g0 e! ?% UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* F/ b; k/ ~3 K2 ~" [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 m% u( u( L1 F5 K/ ]/ Z9 C& Q* O| MCASP_PIN_ACLKX3 \4 o1 n2 I& L/ Z8 E
| MCASP_PIN_AHCLKX
: i; j2 \/ M9 p ^) y# c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 C6 R, D1 v" d- z2 h+ nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ b/ v) C5 p/ }* h+ j| MCASP_TX_CLKFAIL
2 b6 x5 {/ P& Q9 }, g( v1 L$ k| MCASP_TX_SYNCERROR
3 _' G q6 \ _- F: ^# h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ j# ?; _, g) q- T+ ]6 [' ~6 N| MCASP_RX_CLKFAIL
6 c( D0 U8 M g4 g5 f$ A| MCASP_RX_SYNCERROR
S8 }, R8 _4 U0 l& r5 a8 ?| MCASP_RX_OVERRUN);# v1 s3 a$ X D
} static void I2SDataTxRxActivate(void)
: J) A3 Z. }' K# t+ @/ H9 n$ Y{
/ [7 B# z9 E& @0 g8 P7 I* `6 W! D2 l) {/* Start the clocks */
2 `% H& a( ], A, T4 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 H1 I, W5 I9 y/ E& yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& c4 M5 l i) r0 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- J. ~+ [( K/ ?8 r
EDMA3_TRIG_MODE_EVENT); b2 U8 m4 M+ H+ [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 C( R5 k/ W& Q% p+ s8 L! _# _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' l3 G# n7 `6 P6 a+ d( Y: J- _0 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) w! r7 q* O" f3 N' D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% V+ T! A6 `1 q' z% l; l& y- h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 G/ ?; O3 A# j+ Y4 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 P; ?$ z0 d8 o6 a) O5 O2 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# Z5 h5 P6 F. q# r}
' O7 k8 K3 O6 z8 G8 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % d8 [ J0 G/ n" U6 h
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