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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 w$ x' F- u+ T9 Hinput mcasp_ahclkx,9 q: I# n6 z7 J1 Q' K6 `
input mcasp_aclkx,7 h7 V: \! W |. e
input axr0,4 w$ j! G; S& V( T1 l N
7 u; U: ~9 p6 H) b" aoutput mcasp_afsr,
- e$ c. p; n& q+ goutput mcasp_ahclkr,7 A0 {% T+ o1 y5 ^
output mcasp_aclkr,
% A% n. w/ f8 uoutput axr1,
" M! L; C& o3 a3 R; W& L e assign mcasp_afsr = mcasp_afsx;
3 K/ ^" E% S, D, e" C) o: uassign mcasp_aclkr = mcasp_aclkx;+ I# v, m9 {: |8 R" ~; D1 Q1 C
assign mcasp_ahclkr = mcasp_ahclkx;
& h* K6 N) ~$ vassign axr1 = axr0; ' ^' C, V y& j9 e2 g
) d3 d+ O8 B# p# M7 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 k3 g* U/ d& ustatic void McASPI2SConfigure(void)
& `( Q. n) ]: n: `9 X9 _9 D9 R{
+ f& ~2 b$ ~8 ~6 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: W# U' ~6 T. Z }8 E3 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 T- Q% z% X- x! K/ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 g* M* f- S. A m2 \8 G0 Z! }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 |* W6 W& G+ L% S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," R; q2 H" E* a3 m1 \8 k( F
MCASP_RX_MODE_DMA);
$ a+ [: O5 X& Y; y' j0 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' _2 K6 L |! [5 Y) H% H, G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' I: j+ Q+ U( o+ x- l, t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& E- S# A+ o/ k$ l: {4 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 D5 m2 l5 C6 `. z7 ^! c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 o8 ~ o% T5 x+ b. z7 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' g" E$ w$ ~1 z( ]7 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 S/ a0 p4 v! J; T7 P2 q) m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( Z. C9 n0 `5 ]2 `: o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" _4 p9 ]5 E6 c5 ]0 y" C0x00, 0xFF); /* configure the clock for transmitter */
1 k& i: Z9 [3 I: p# UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& `+ z/ p% D+ n& c2 c/ C% xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ z- J2 z. Y7 x( s Z$ TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' C) K0 M" y) k0 p4 [% ~( x0 z0x00, 0xFF);
! r, p, s1 _! T9 K( h6 j" @ M( ?1 f( j* I6 R* D& d; y; u: K
/* Enable synchronization of RX and TX sections */ 3 ^& o$ p1 H& c5 `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) k- d1 u; ^$ }: \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, D+ A, _& C2 j5 E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 f1 |. \ F! O; W* }, ~- b" I# ~; M** Set the serializers, Currently only one serializer is set as
. h- b* S# Z( g4 r& o( x** transmitter and one serializer as receiver.
! V- ]4 U, F% r2 J: a*/3 c4 @: s* t2 w4 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- P5 d: b0 s6 k! K- [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- \7 h6 A" h' d** Configure the McASP pins
/ ]6 `8 n" ^' T8 P0 R** Input - Frame Sync, Clock and Serializer Rx5 ]0 F* R( w$ s0 L: Y
** Output - Serializer Tx is connected to the input of the codec
4 ]7 N5 N" c% q2 q( e- A3 A" N*/
( U: U1 W' ^7 {( J7 I LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 p2 e. @* D+ o* q$ P9 r* oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 p. S# C/ V, P) N% `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" z7 \! Y. Y3 O9 s. M& B ^
| MCASP_PIN_ACLKX' t7 k, o1 X( b1 J% [! G
| MCASP_PIN_AHCLKX6 q( J7 Z* H2 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 n8 Y ~7 Z9 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% o# \1 @' P( [0 L) z0 r) l| MCASP_TX_CLKFAIL 8 G" s6 j5 b* y2 U# a" b) j
| MCASP_TX_SYNCERROR' k, B5 |9 M" S2 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 |3 h8 ?% R* C5 J m) a: |" _; ?
| MCASP_RX_CLKFAIL3 N3 `4 E: k3 Y, i
| MCASP_RX_SYNCERROR 9 E. T% c* {& w# h0 Q, S; B
| MCASP_RX_OVERRUN);4 |7 ^7 W1 S' F" O
} static void I2SDataTxRxActivate(void)
& T3 g9 T7 s. K _/ O{" j2 |% I/ T! z1 c% x
/* Start the clocks */
# n P8 @- h- g8 y+ p. }2 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 V9 ^3 d; w+ r5 c3 `3 b! |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( |) Y4 C5 l6 f7 f/ u) nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," s+ G9 ^7 E! q5 |3 O/ h
EDMA3_TRIG_MODE_EVENT); G% Q+ D2 E: \, ^' K' R' h. E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & T9 p* h; j1 K3 d6 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 s- x# @$ a' E2 n) Z. Z, ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 }/ M) M x! Q, f% a0 U QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ \" u! U( d7 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# d1 z* [9 \: C! _$ d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ @6 p% I' z+ X3 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 Z7 D0 ?4 f Y% L7 f, R+ |, b t7 |
} : e* Q' `* T3 U+ H& ~5 R9 N3 ~. Q8 F; F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : }" Y- z' |$ |7 T5 z
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