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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 V; |+ R: n1 b- Tinput mcasp_ahclkx,3 _6 \4 K+ Z* R' c* I V" e
input mcasp_aclkx,
6 z# h2 a. u4 X2 h$ L) Dinput axr0,
) V; t: `; j& G( ]
8 @" L) m; d$ Moutput mcasp_afsr,
+ J6 a$ [, j! ?" `; Y4 U$ {! |# S) [output mcasp_ahclkr,. o5 }1 R# ^- h3 ~' q
output mcasp_aclkr,6 t4 E6 h; l7 h6 C- ]+ y5 I
output axr1,1 y4 r1 i+ Q. J5 ~5 | U; [$ z
assign mcasp_afsr = mcasp_afsx;
, ?' @9 x4 m' H/ Y/ `2 y+ iassign mcasp_aclkr = mcasp_aclkx;3 Q( Q* j' n$ b6 k2 I. L
assign mcasp_ahclkr = mcasp_ahclkx;
J# J1 Z. ?# K- zassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: S0 k7 @ h" K! ]# m$ M y- i, Astatic void McASPI2SConfigure(void)
, t+ ]2 }# Q9 e8 k{
' C+ I7 P8 l6 B2 o* l$ f; qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 |+ t+ k9 g) ?3 i- wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ ~: ^9 A" F7 W# YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: W. D: C+ q3 ^ q& x6 |; I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% y& e: h# a/ ]% f" y! bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ S; ]& Y( V4 J- \ U/ ^MCASP_RX_MODE_DMA);2 }# S% T" n$ t0 D5 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( A% r1 C! b. `% s0 H* ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, e* K& ?" T8 u3 B+ aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 m" k% N+ l, p7 P7 }" FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- p. X) [2 P* _. u0 ?, _0 I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 _/ z8 q. m, X7 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 _/ e% Q1 a, u; v( r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 W# I3 {0 H* s( C$ ~: H3 [1 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- _% C5 q+ [$ ?; Z# JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ m3 b4 g( o- K( I' u: s
0x00, 0xFF); /* configure the clock for transmitter */. _ e/ [( c# g( H' B, n% b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
]; r5 U, _) w% VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) N* r U+ W1 c5 I! o7 S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' M7 r5 z% P5 `, Z# m
0x00, 0xFF);/ k/ w& y8 P- m/ I
; M, b! b/ q. y8 w, l! G
/* Enable synchronization of RX and TX sections */
5 m. t% V2 r5 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: q m8 L$ X5 E! E iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ y( t& o! x9 q G3 u8 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ }3 L/ r* k- B2 K6 P% c
** Set the serializers, Currently only one serializer is set as
3 W' P0 r* N7 t8 H" b1 v4 \1 C6 ?** transmitter and one serializer as receiver.* {1 f' O6 E z
*/
- ]! f) @6 }/ ` n" OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. @/ `: t2 L0 p6 |( H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 G! h) g3 h0 B/ X; P/ E& i" Z1 O2 _** Configure the McASP pins
; L1 R H! B3 g+ L' n: U q, {** Input - Frame Sync, Clock and Serializer Rx) d1 s- M: m4 I7 o4 j
** Output - Serializer Tx is connected to the input of the codec
2 c6 Z T; q; Q d. f*/
, b2 y0 a4 ]4 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' q, R F6 g9 q; }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 A, m$ R7 W) c- j- I2 \8 X/ `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ }* y; X w6 x
| MCASP_PIN_ACLKX
9 ~$ x1 s# `" z* n| MCASP_PIN_AHCLKX
- U" f/ m$ Z' y2 l8 }6 i% m( k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# F+ x$ f* M9 T: k. W5 G1 [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 n: k z: E0 }3 m' W5 A| MCASP_TX_CLKFAIL
6 Z+ y: B' ?' Y) z7 \6 s) i| MCASP_TX_SYNCERROR
4 g5 s" t5 I- X# V' T6 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - f: j) @) R9 d6 I" A# ~
| MCASP_RX_CLKFAIL
) V4 f% W4 p8 G/ P P- \| MCASP_RX_SYNCERROR 6 x+ T0 N" ?+ x9 j8 X( m
| MCASP_RX_OVERRUN);1 W# ^% P# B* |0 z" L) |
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
, w/ \3 {$ x2 }4 ]! N" G7 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' W5 u% M5 Z& P: B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( n' Y* M7 N) u7 z2 m w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# P' g9 ?# L& p7 i1 D6 P8 M9 mEDMA3_TRIG_MODE_EVENT);
: r( o; X2 n; S0 L5 C( v$ H1 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . B* |0 ?) S9 ? J* b( ^5 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ L( e+ f0 d& ^7 w/ H4 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ]5 E# w% `4 h; h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 j3 x/ Y" q- z1 X0 O1 C$ C' `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 I+ \2 |4 J& ?- ^4 Q& E P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ i% m6 m. J1 n! ?$ }" v2 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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, P2 c$ G. g# G0 e( X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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