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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 Z+ S( U3 Y% d8 O" ^. H* d3 M
input mcasp_ahclkx,
* f8 z& e9 ^: n2 Ginput mcasp_aclkx," j* n9 _! ]7 F2 @( {( R5 g: E
input axr0,
! x% k* o5 l8 t: n9 p% d2 v6 |$ U; {- b/ s- d/ a; C2 V
output mcasp_afsr,1 M6 g7 h& v1 i' s$ ^& I! p
output mcasp_ahclkr,
+ i$ p# _ W1 K6 g+ I6 D% Uoutput mcasp_aclkr,) [9 p( ^/ {' [2 Z/ }- q; l6 ]
output axr1,+ D% f5 H. h( h3 X! w! Y; V2 w
assign mcasp_afsr = mcasp_afsx;
3 Z3 {- m: l6 T1 b/ jassign mcasp_aclkr = mcasp_aclkx;6 z0 A6 g% @* K* Z+ c6 [- X$ z2 [# M
assign mcasp_ahclkr = mcasp_ahclkx;
4 v& @& b, \! w- W2 Aassign axr1 = axr0;
. ]; }) i+ i% y6 N9 k
9 E) u; n+ e* u, {. m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 r i0 ] T1 I$ [% y$ s/ `8 bstatic void McASPI2SConfigure(void)- q0 t* w, I! q
{
( i# i: n2 [4 ] QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: l3 V' U Y# Z" l! w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. t9 j3 T3 ]& d/ {1 a' T( T1 VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' v0 E6 G* Y$ [% XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 D5 b, ]* w6 }# p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 R6 z% C3 s# Z9 p* I" sMCASP_RX_MODE_DMA);. M' I! }% J3 k: k; S Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, Q+ x% b6 k$ Y( r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 ^; Y1 V/ ^1 \9 w+ g5 O {/ uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! E+ R! g) ?( B {: o& M- bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ H9 q4 U: Z4 ?. N4 d8 U6 Q% ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - i2 x% f0 e& X, K4 @$ n0 }5 u n" U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// r! B; a w! @3 ]- ~3 L+ p0 a5 D9 r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 t8 X* G5 a# h% MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; d K2 ]& a, J4 T' pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" g0 f4 q( ?% F i- W2 T0x00, 0xFF); /* configure the clock for transmitter */
+ {! X7 r0 `7 Z8 N: _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% m4 R# d+ O9 P3 _- N6 s$ e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 R+ A, ]* V0 g, G1 v# x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% l, p% q, A) W' p4 s# l& z1 L
0x00, 0xFF);
$ p* i8 _( c% _8 ?2 _6 ? j/ l1 q n- F, d
/* Enable synchronization of RX and TX sections */ ( I7 z( H# _: v! r! M4 M" Z( ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 C- F9 p0 L7 |) \% qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ q8 ?, {$ K& F8 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% z8 m; x5 @+ I8 F- j# z** Set the serializers, Currently only one serializer is set as
1 |4 P# `8 i7 V** transmitter and one serializer as receiver.
! H1 @3 w7 @1 G( {( s# `*/
. ^$ q' O$ Z( g% MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 q& I. o2 |. P1 Q: H3 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** \4 l5 w9 v$ P. K" P: k
** Configure the McASP pins : Z3 l% V, c' o. R' Y
** Input - Frame Sync, Clock and Serializer Rx$ e0 h4 n! G7 [& k
** Output - Serializer Tx is connected to the input of the codec 8 m- t7 Z( B& {* W/ W* x5 N/ X; D+ }
*/
7 O, G M% u' s3 d: n) h2 U$ l. XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. t% E7 f* b9 g/ d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 s6 J( S! C$ P: c% x/ z2 H5 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! J' A$ x3 v: q1 S7 V- Q6 O, b| MCASP_PIN_ACLKX5 ]2 f/ s1 d9 W+ f% j4 v, d
| MCASP_PIN_AHCLKX E+ S' w( `/ X- a) M' Y1 @! H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 F% m! B) u# M2 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' ~! I6 o* Y; Y( P
| MCASP_TX_CLKFAIL . f" p4 p* C$ _) }% e' P/ b. a
| MCASP_TX_SYNCERROR5 Y, o% z3 b: [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " ^( e9 ~2 x" H4 m! d( \
| MCASP_RX_CLKFAIL. N3 ?' B1 Q2 X
| MCASP_RX_SYNCERROR 7 n+ a! z% {3 |% ?) L+ ^ O
| MCASP_RX_OVERRUN);
( V+ } z, u! v: A# d} static void I2SDataTxRxActivate(void)( N, l+ ^1 @ O9 i
{, D& _+ J1 m$ V- G. q" O
/* Start the clocks */
: r! f9 {# K- o( r+ B' FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: Y2 |6 H0 Y2 M1 |8 O8 V5 D2 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& u v/ g$ G) `9 j! dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ v# Q7 y. X; n1 x `
EDMA3_TRIG_MODE_EVENT);
& E1 Q( q2 }* l/ D0 }/ s, s$ WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( F6 D4 J: \' g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- E# k8 b! O: v: O( O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
G& i' k1 c5 q# h7 l# tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// \( A( M: j5 Z5 V2 J& Q9 V4 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 w8 x; J7 A2 I# c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! n9 R' [! S. o! i2 \8 Z# x# ~; I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 Z- @3 @' J4 I; A- d8 \. J1 Q
}
: j* L& y0 \& U- M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 n5 o! Y9 [# g. a( v
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