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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' ^4 j3 A( W# t. ^6 e8 Winput mcasp_ahclkx,9 M8 Y$ T# G+ R' K2 v: K
input mcasp_aclkx,( ~; O) U( q5 V6 o3 h! F F
input axr0,
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! l4 V3 J0 b: ~, I7 d& voutput mcasp_afsr,5 b: V4 L) W8 l! O7 X
output mcasp_ahclkr," o1 ?! K% d2 z" j
output mcasp_aclkr,
9 l$ u" j+ f2 p2 Joutput axr1,
% k- `! T0 o6 _" ]- L% ]" V+ j+ U assign mcasp_afsr = mcasp_afsx;7 E% H1 q. h. Z
assign mcasp_aclkr = mcasp_aclkx;8 ~: t- |' ^! N- N
assign mcasp_ahclkr = mcasp_ahclkx;3 z) }8 ?* b5 C/ P+ _0 a
assign axr1 = axr0; 6 O& ^8 Q/ |( C4 }
5 y6 u5 t1 k4 C0 h# G1 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( F7 D( I9 T" ? M8 q4 e; estatic void McASPI2SConfigure(void)
/ V' h6 B5 p% x8 H" M; l2 }* ~{
( b! i% h1 ]0 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ `3 T; V) k4 K, t; j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ D; ~3 L, |0 @+ v# v0 FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: P" t0 l0 C0 F$ Z9 C5 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 ?. E8 L3 g4 a4 @/ {- aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. ^4 k, A- H5 p$ i# `MCASP_RX_MODE_DMA);9 P* I9 @+ Z. o) m$ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 p, t8 S9 x! a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( g. v5 @% t+ m' ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 l$ z& M% {6 I/ X9 w( jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 A3 z( @4 [; i* V! I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * w7 k' M8 M) S( J( O' @- w0 A+ W+ M3 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ ]+ V/ O% H9 ?. xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, ^1 V; `: P6 n N9 K3 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 X: a* ^& L: b* U& O; _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 S# I* r$ g. ^9 O$ e8 e3 `0x00, 0xFF); /* configure the clock for transmitter */
9 [1 o( ^) M3 E4 |$ ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 s7 d: i5 c( {( p% A+ G. q/ I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 [7 D% }, D8 Y: h# ^% z& JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ b9 f, S7 k1 K: ^* A1 Z) B0x00, 0xFF);
& _7 ~$ f* x: K# v" L" a# E2 Q& _9 g1 t9 C( N# e, C: N
/* Enable synchronization of RX and TX sections */ 4 y& ~& c: X2 q' Z- Q; U1 h. X' Q9 V* A/ |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 ?: D V6 O9 q5 |8 _9 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 R" L1 h4 [' ?9 n$ W. M8 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ @# _2 i4 e4 T& g3 n! T) R; m7 X** Set the serializers, Currently only one serializer is set as# v7 C* v9 B+ _% O
** transmitter and one serializer as receiver.
; ]0 p+ L' }7 R! U9 h*/- q9 J5 \0 M8 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" l B" l6 [: d/ Q1 @. tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% |! G' \. g# r' X; w** Configure the McASP pins
$ j% h5 r& V3 @6 F** Input - Frame Sync, Clock and Serializer Rx6 j7 d9 E- B. W: y
** Output - Serializer Tx is connected to the input of the codec
. e2 g; ^: l# k/ E*/$ J4 q) P9 @/ z9 W, }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' S, R6 j$ W1 J3 i9 U2 K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 m& ?- @. ~; I" O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& J$ n% ~1 w0 C8 H, i, O
| MCASP_PIN_ACLKX
% {4 Z4 m, H9 E6 C. J% T| MCASP_PIN_AHCLKX: `# X, T" T' Q( r/ E2 g* Q5 B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* }& J" A; A/ g" t5 Y% S* ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " I) C! ]+ H) J! a
| MCASP_TX_CLKFAIL
3 [8 t6 s% y8 z4 l3 `| MCASP_TX_SYNCERROR
6 P; w0 T- ^# e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 |$ R! U% a( l# ~! n| MCASP_RX_CLKFAIL) j" b% Z, J' x l9 O) P, H4 O
| MCASP_RX_SYNCERROR
9 c. j, ?7 r5 s( l5 E, K| MCASP_RX_OVERRUN);4 ]6 R$ Z( }' v& J4 |/ R- H$ E* E
} static void I2SDataTxRxActivate(void)7 Z6 X% p" ]9 W. n6 v* R2 Y
{
' i0 K% z7 c! ?& ?/* Start the clocks */5 g1 g. g# d+ i: p7 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& [ ~, l' m' y: `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( I* w0 E" e2 Z1 v: f. NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# }- t/ }) R! O# x2 D3 VEDMA3_TRIG_MODE_EVENT);$ N4 ~) x8 F$ M0 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 Q2 A6 n, z2 p+ K& t. M! f) R6 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! W4 u. @. K( a0 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 |. b; k7 z+ l, k8 O) GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% S& L6 o* A0 Z6 T& Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) Y+ N; h# E/ E) W6 r3 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. o$ C3 T! s# xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# x$ q. x- R) |/ C# h& w7 T) K}
6 X- [. ^3 E1 R; F7 k* E Q+ |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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