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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 U, m3 g6 }9 g( K/ I0 Binput mcasp_ahclkx,
8 O' n; I. r3 o9 m/ @, l2 yinput mcasp_aclkx,
- D! t/ _9 c" X9 |9 r6 V0 N3 U1 Cinput axr0,
# F7 c+ I4 p$ s
! T# Y) B6 z. |$ r; Uoutput mcasp_afsr,% [9 @, y- {5 B% m4 K: ~( p' ^' \ X
output mcasp_ahclkr,
0 N0 H1 J: k% f4 boutput mcasp_aclkr,% B; e7 @5 ^* ?9 f1 v
output axr1,
; t3 v& [! T5 y1 i ` assign mcasp_afsr = mcasp_afsx;' Q7 R ^, B6 o' J0 M
assign mcasp_aclkr = mcasp_aclkx;. r% ]6 Q7 Z/ B: b: Q
assign mcasp_ahclkr = mcasp_ahclkx;
: |$ ?2 C& q! e: Vassign axr1 = axr0; 6 Q d5 ~3 c+ k* b9 ~' ]! S
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 K8 q5 q: u ]4 j \, M2 s" \* D( s
static void McASPI2SConfigure(void)' q* T0 j0 k" ?: N* e2 D+ X' X
{0 B$ \6 w; r, g& C; \0 g. w/ J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ ^ i+ r& @. B r1 b3 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 F% h: V7 `/ g" y2 m! T1 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- l# A4 p3 a" ~1 m" `2 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ X, J4 r* r5 x& I8 k1 e* f5 A" pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 h, [, w: w& }) W2 Q5 r7 d( L C& c
MCASP_RX_MODE_DMA);$ J J+ B8 p# `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 ~! y! D+ ]# e D9 a& l8 W" q( G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 F2 C, j) o: n+ z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; k& A8 Y0 Y- g8 ~% ^! D+ a7 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! N/ C* U& n/ l1 I% XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 ?8 Z% U! i3 l4 R: ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- c- M# Q5 I7 |1 } i& G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 Z) K. Y8 g" D1 v; l" W2 j7 j) W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! n n, Z6 x E, w3 p1 j6 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) M$ w* n2 k7 s! D' E4 g- m0 g0x00, 0xFF); /* configure the clock for transmitter */
- m1 l" y. X3 N$ t+ TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ p2 u* b6 }0 V+ u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) e& g- T5 x( N1 g3 g" b$ p: m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 r. J( T$ {5 \
0x00, 0xFF);$ t. b0 A3 H! G. K9 k, ~: X
" W7 C/ S( W) C& l& h7 ]$ s& o' |
/* Enable synchronization of RX and TX sections */ ' V8 M% B; \# R- b+ t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) U6 K6 U( q5 Q8 w3 _4 E5 Q0 C; H: x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; q' I" c$ }" n% z. K; ~0 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" k6 f& p; d: ~+ O8 \2 i
** Set the serializers, Currently only one serializer is set as
5 g: p1 s( C- v; r- `, I) a! H** transmitter and one serializer as receiver.& x; H6 ]% Y ~* ^" U& ?# `$ [
*/
- Q4 D# m" h& s% c2 yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- u# T( [' N- P5 K J+ V+ nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 A' r9 `- z' @ }4 z8 [ ?
** Configure the McASP pins 6 }8 U1 ~( l% [% e# V( L
** Input - Frame Sync, Clock and Serializer Rx
8 G5 q/ O# A7 D' _, b& P** Output - Serializer Tx is connected to the input of the codec 3 R5 n& i) e+ E* J& d7 F- G* L
*/ Y+ h) s7 \. R3 X& d6 _* l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) u8 A6 t$ ~$ `% y9 h& F# {: I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! A7 a3 e/ [& W5 F) n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 g. Q0 h; T. H, A8 S& M* u
| MCASP_PIN_ACLKX% _8 k9 [2 Q9 E: E; Q4 D
| MCASP_PIN_AHCLKX5 Q$ V2 d) Y- z9 C9 L/ ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: a2 O* V$ @1 E6 g$ `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 G0 w+ g8 i5 H5 V+ r( P| MCASP_TX_CLKFAIL / W1 y7 |- l) o2 U
| MCASP_TX_SYNCERROR
# Z" @# {( u7 i* t$ O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- @; m- E c+ p" j, Z| MCASP_RX_CLKFAIL
' w7 D+ A3 v s9 I" A; m9 H| MCASP_RX_SYNCERROR
7 {% ]6 Q0 M+ K" J5 A' T| MCASP_RX_OVERRUN);
- S& u6 \# Q/ T- ~" O* c} static void I2SDataTxRxActivate(void)* Z/ ~3 d5 S; Z0 o% W# @1 r) Y# x
{
( t' q( H8 j; t/* Start the clocks */
; |5 s6 ^, L, R) J% pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 {) j' _8 U* _5 x4 t. F: _7 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// N5 a, E! _5 m, i" X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, o0 I) a# m3 n y6 `* bEDMA3_TRIG_MODE_EVENT);
7 J8 q+ N. B# P% F( VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 D3 \1 C" q, g/ b& z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 t: C, Z0 a3 U9 P" w" I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: J1 F. N9 R1 \9 V/ q- r$ Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& i% M5 Q+ A! l7 e Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ p, J& T8 Z2 X9 l; N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ s. i4 v9 ^; y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* Z" q4 d1 c: x} * i5 j! i k& [% {5 j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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