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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 m- K0 U, p% w4 |, \input mcasp_ahclkx,0 J1 t( o; o& R3 n
input mcasp_aclkx,9 X0 z. j, l& O. m
input axr0,
' y7 g- m. K+ q! S, S: O% `2 J# P" C/ x& j- ~& N
output mcasp_afsr,* s, ~, U' [. d/ j, E$ I5 \0 q! |1 T
output mcasp_ahclkr,3 m/ f! y c& w, N0 K, X1 ]6 @3 Q
output mcasp_aclkr, v0 y7 I& w/ A0 T6 R! m3 G" T5 [
output axr1,
( v) Q: S/ q; p4 h- k assign mcasp_afsr = mcasp_afsx;# q& V# H3 a3 O( I t; `$ _9 J
assign mcasp_aclkr = mcasp_aclkx;
' q$ D1 e& q) ]3 U& Hassign mcasp_ahclkr = mcasp_ahclkx;* x: r J8 C6 D7 Q' P7 @ H
assign axr1 = axr0;
1 K; W: G( M4 L- |% K7 A
, ]8 D5 M8 E% s3 Y* {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 ? C7 b" T3 N' F& ^- C8 Wstatic void McASPI2SConfigure(void)
* s+ G. I/ e W( w0 }" E{
4 R: D0 {! S- t% ^& e, F4 S( V! DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 h. ?5 V' \$ K( f" M/ g4 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' l2 u6 b/ j8 g. _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 p/ E3 G% Y3 W* x3 V$ ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 n" T3 G* }4 \. J7 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 c; I, C% B; d6 O3 ~% a) y; t
MCASP_RX_MODE_DMA);! T! X% N2 y- u# a; L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' p& C9 s" N+ aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) E. F" i( J( N3 r' EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. [- H; i) k1 R' p# V6 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! Y! H# t' K9 W4 m! h% h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" K& \- Q0 L$ M% J4 u% eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* n z) A6 m. I# aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& M7 [) l* _% k8 A( h0 o" Q# LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& ]0 Y: V$ u( j: RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! i2 j& [: r2 B9 n, I& p3 ?0x00, 0xFF); /* configure the clock for transmitter */
/ {: ?7 ]- p& L5 p* WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. C2 x' @, e& @4 M1 x( e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' s8 L T {5 e7 s5 P+ A# r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," T9 Q% y8 Y4 {
0x00, 0xFF);; {) O1 _9 T# v9 b
6 A& x ?" ]6 x2 {/* Enable synchronization of RX and TX sections */
" a1 t6 T( v1 {3 {( w% R3 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% O; ~# h |! ?" d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* [" ^1 i' c: J) ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: p( E2 n7 s2 t
** Set the serializers, Currently only one serializer is set as* f$ L0 d- {5 Q u% z: ?6 C
** transmitter and one serializer as receiver.: k) D$ @/ I! y7 q& I* C
*/
" [8 c0 g) n/ m$ E8 [& }1 IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 U& ^ ~0 {) e7 ]. Z3 @7 `$ o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 l% S/ w) f( j( n$ ^# d5 m2 h1 ]** Configure the McASP pins - t/ `! X. N+ a: X5 l3 S: g1 K
** Input - Frame Sync, Clock and Serializer Rx
, u& ^6 n' W3 U" b** Output - Serializer Tx is connected to the input of the codec
, x a. K! M9 e2 Q: g: q*/
* l/ V* M3 y0 X4 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 i5 D2 _9 G* B+ }- g1 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ R8 p, G9 J- s G1 r& f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; O( O- @3 t8 g6 x& T. Y
| MCASP_PIN_ACLKX- }" k. o O9 j; |) s- w: A5 N
| MCASP_PIN_AHCLKX
3 H6 d$ W" \) n& K6 h1 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ~* K9 P; b8 \* DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: K `# q: X% D| MCASP_TX_CLKFAIL % b2 T9 _9 ^- u+ P+ n4 ~* V
| MCASP_TX_SYNCERROR9 @' [, h4 G+ c8 R* Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) I: [4 A# ?) W( D' [; ~7 \| MCASP_RX_CLKFAIL
0 q& J+ P5 U5 O$ W( d( }# X' K| MCASP_RX_SYNCERROR : @( I+ u/ w) N4 v
| MCASP_RX_OVERRUN);" S. L } u- N o; f2 k8 @
} static void I2SDataTxRxActivate(void)
" t8 p# J+ v/ M4 b' ~9 t. |, G{/ x6 m( ]$ n. p R6 l
/* Start the clocks */
$ Q$ h1 y/ x* @& B# XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* s) o }# o5 `! vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 f' j" g$ ?# O5 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 W3 k2 `& M5 i- n, U" R0 x; ]EDMA3_TRIG_MODE_EVENT);
; ]; }* w2 i' @5 j7 @5 `, J7 mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 G: J, e! O g" _+ x+ P+ @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- s5 T3 @; H% A) z4 l' Z- |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" c* F4 N; ^4 N% T' ^# m$ n$ f8 I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 w+ X1 s% j6 w4 e' Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 y& F# D$ S$ q3 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- r/ R5 ^' \ q: d6 \4 O+ QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 N! v6 R, B$ C! e
}
4 w! {" n0 q" x& I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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