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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 e& O. {5 h) zinput mcasp_ahclkx,) p' @7 G1 Y7 M* @
input mcasp_aclkx,
! T9 e# {8 B { ]. I1 i- Vinput axr0,+ S; }* S$ C, H1 T9 k
1 [" l. T M) x% e, H: Z
output mcasp_afsr,( m* r; Z. w1 c+ g5 i
output mcasp_ahclkr,' R0 \+ s w; n1 \: K/ O
output mcasp_aclkr,, b/ E6 L1 o$ D' |6 w& l& ?
output axr1,
, e7 Z2 R6 j2 j7 C/ w. N! w assign mcasp_afsr = mcasp_afsx;$ e6 a( t) d e; B
assign mcasp_aclkr = mcasp_aclkx;
; \- s; Y: B: g$ K F% e- Vassign mcasp_ahclkr = mcasp_ahclkx;
9 r/ [0 k4 F4 o) P2 Y$ p7 f c5 Wassign axr1 = axr0; a9 Z! S: K2 x; t# e# z! O: A
0 |# X6 {, d5 p4 K- Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
b# G, i( c$ C* Cstatic void McASPI2SConfigure(void)
8 j V/ [/ \& S8 f1 I- F. l% ^* I2 o{+ d$ A6 l" \& u. H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ A; [2 N4 C4 H6 B, wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 h' q0 j& n2 h; z& Z, FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! ^: s; c; Q' A6 F' Y! b. ]" |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* R# `2 E$ H q- q! h9 {8 Y' h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 h0 |0 P+ O! ?/ _' E4 v, c
MCASP_RX_MODE_DMA);
1 L) J$ [0 C z$ O9 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* F B# Q$ K+ H. VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, k6 r$ W3 A& u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 c+ n% }1 Q; X, j5 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 T$ G" R( S; e/ d" B- t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 o p. W8 X9 @! _3 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! P8 R! r! ]4 v; D% P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 U5 a' Z, v% V& A9 ~$ z4 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; j2 v: x9 A0 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 _% ]2 x) D+ w
0x00, 0xFF); /* configure the clock for transmitter */
, Z5 ?1 J9 Q6 ?. v5 U0 U8 B6 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 t: v( b* i6 F3 N' p+ z0 _! \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! o: v5 t- H+ |4 I2 x' uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
C: `1 h* R; x- v0x00, 0xFF);- l+ L8 N; h+ j* i8 E7 v, k
; V4 X* [& D9 g# C# U0 s8 o) X/* Enable synchronization of RX and TX sections */
9 S( e; N' P7 z% ^! g9 QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 [* l. f. m2 N& n/ D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, v( }% F. p3 ~$ |1 |: aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 `5 c* ~( h. L( @9 S/ E3 W
** Set the serializers, Currently only one serializer is set as" L# j: u" t% `3 w' P0 p
** transmitter and one serializer as receiver.& I: L5 O2 R' k! _1 [8 l# L1 w
*/6 h% z d8 m, N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 M+ N4 u6 G L9 w( RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- G( _% e7 b8 g* U9 e, t9 |$ Y+ y$ f6 P
** Configure the McASP pins
% }9 m% Q8 z' @& I6 ~** Input - Frame Sync, Clock and Serializer Rx) F/ J D: o9 Q5 |! n4 h9 H
** Output - Serializer Tx is connected to the input of the codec : _6 a$ M# ?0 {2 _ `
*/' b* _# U+ S6 @2 y \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 f( ^4 O+ y4 ?9 `1 I- A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 U3 l- \0 ^$ f- m, D# Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 n* N- O; W* M0 b0 h
| MCASP_PIN_ACLKX
- h% Z$ A2 [* V1 f$ {2 F# z4 V( p| MCASP_PIN_AHCLKX
: m$ _, r$ l5 M0 z( D0 L0 ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 |9 C5 o4 B4 q. j2 C! O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- J) X; ?$ O( A+ ?: e| MCASP_TX_CLKFAIL
i- |; V* \4 m+ R, S| MCASP_TX_SYNCERROR, w' o- H, B) ~% b7 C5 j* V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # {2 X- w3 I9 E4 O8 U/ d% |0 s+ H, I
| MCASP_RX_CLKFAIL+ W# H$ J1 ]2 i
| MCASP_RX_SYNCERROR 3 ?4 J+ z& t* z) q
| MCASP_RX_OVERRUN);
' c, o! N8 T' D+ f' K W1 _} static void I2SDataTxRxActivate(void)
7 y# K& J. P8 s" p3 R{
/ ~& \% u. V8 Q8 i( o9 S/* Start the clocks */
2 ]9 N; \' @! V$ X8 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 W8 H5 H$ x2 i- z/ IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) {6 g* h# h" r/ L, T8 s# l2 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 k3 a# l; D/ u' Z1 t P) b4 vEDMA3_TRIG_MODE_EVENT);$ w. r( D7 A2 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 Y1 R$ ?. H+ g: n# U4 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ u0 L2 y, h3 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 c; C% `% e( p3 ] zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) c- c# K' L( w; J1 u5 ^& S- E: r7 \ e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
~7 P) n. s, _( g+ fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' Q0 N, n% c u3 }, VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ d- B) U, R- y7 W+ r
}
; x- ~3 a7 p7 N; A, o; {. s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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