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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 X' ^: x7 y& E* Y) Q9 g
input mcasp_ahclkx,
' Y; F# V- Y; Q8 g& {input mcasp_aclkx,, n4 I7 e5 \- A: }2 H N. x2 A
input axr0,
^! B0 g/ o; |3 j {, H3 Z
6 v/ o6 P( W2 Ooutput mcasp_afsr,$ T: P# Q# d5 f7 V! x5 G
output mcasp_ahclkr,2 K+ ?; U( R9 V: f$ p
output mcasp_aclkr,- \7 e3 w5 _1 H- s) Y! W4 T
output axr1,7 X; e/ a l4 D0 F. a
assign mcasp_afsr = mcasp_afsx;- B7 H% Q; ^) S7 m: H: {2 n
assign mcasp_aclkr = mcasp_aclkx;; y) J# u; R. j! F
assign mcasp_ahclkr = mcasp_ahclkx;$ X- s. x9 B, l2 X
assign axr1 = axr0;
3 f5 H; N" A! r T
8 O; L" O% Z; S D1 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
\9 t$ L; K$ x) G0 k. G2 h) P7 Fstatic void McASPI2SConfigure(void): L3 N8 P& j0 ~9 Y9 @# [
{
& n- t1 Z1 w U/ ~9 m. ~) O9 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( S3 X9 I/ ~% ?, o: ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 J) S" D8 u' ~/ k# YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); [5 Y/ F& k/ ?2 s5 p0 x+ B9 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// {1 L/ |& ^9 ^' ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 e8 }! _8 ~1 \3 ?MCASP_RX_MODE_DMA);) K' |5 r5 [$ s5 k4 w% ^' f" A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ q9 p2 _0 N" ^4 L5 E+ N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 q+ [6 y3 i1 V2 W; qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' o( c! G- m3 O% P% i" s8 W4 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* {' o0 \% V! l% |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / |5 c$ ]8 a& ~. ^4 K& j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 D, ~/ B0 e& ~; a' O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' b1 }6 J, b' m% ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ P1 ], [: P* d9 u. IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( ?" D2 {7 P' P! n) j$ A0x00, 0xFF); /* configure the clock for transmitter */
& y. q( c8 k: }4 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 D: H; m- Z. o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * [; n+ g( O0 ]. @3 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! j! [$ j, L8 ^* [6 k0x00, 0xFF);
# s) X, ]5 A( F: o; z1 o2 k) g$ v
: d3 T: q7 M7 Y' b" ]/ v+ X$ t/* Enable synchronization of RX and TX sections */ : R% p3 q, S+ r2 [9 K0 m1 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ F( R$ ~! A3 q0 y3 M( v2 k2 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( v. J! B {5 f; H: sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' e' M3 F; `0 b4 |0 @0 a
** Set the serializers, Currently only one serializer is set as
( B, @" x/ N9 V9 [** transmitter and one serializer as receiver.
. r+ X8 Y8 j* J! z6 w, f4 X*/
# t6 A( z G, [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- T, O. W+ i% U! R+ x# E: OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ j7 T6 a2 R+ m: S" q** Configure the McASP pins
( v/ o/ o) A: t# _** Input - Frame Sync, Clock and Serializer Rx
5 ^7 l+ e3 R0 k** Output - Serializer Tx is connected to the input of the codec
% f4 [ d$ b6 r' W*/
2 c; L1 R# [9 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: Z5 Z2 C0 _! g- T# h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 ]; S1 ]# W6 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. A/ W! [- N: {
| MCASP_PIN_ACLKX& y: W7 Y- Q/ B6 E5 ]! E. \ G: S/ i
| MCASP_PIN_AHCLKX
6 C( S/ m% ^! g% V$ {( W# W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ [) A* O+ q$ x# I5 v- G' ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ ~. T/ A$ x- }5 Y! `* X% `2 V| MCASP_TX_CLKFAIL
; M, O& q% d9 B+ t' c( F$ G6 V| MCASP_TX_SYNCERROR% V' r" c% R7 Q2 q ~1 o' g" M$ u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# g* C! j* j. ^2 W1 R ^' E| MCASP_RX_CLKFAIL
4 m7 h, P/ K n1 O% K| MCASP_RX_SYNCERROR ; V, N3 h2 m" [+ h
| MCASP_RX_OVERRUN);$ Y; Z# f x' \
} static void I2SDataTxRxActivate(void)4 ^$ _/ h6 w% O4 U% Y2 L
{
* e1 P. d; K" @4 t' r8 g/* Start the clocks */
8 c" e4 |4 B8 f, VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 d0 E5 A ?2 n% }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 u9 n$ _" B$ Y4 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' X( `# o* h% @$ @) V" O2 U! D
EDMA3_TRIG_MODE_EVENT); W5 G5 Q- q9 t, P2 f* a8 Z F' V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ [- y, f/ B3 ?5 T( j1 A1 GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 B3 h9 L* M. z9 n& \) nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 s3 v6 Z3 b( ~ r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 I s4 K: ~* N/ n) E$ D* A! ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; ?% h% V# K8 ]# e, Y8 |: N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' J0 [' V. u* N* P3 T/ I, `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- R0 ]* ~, S* d}
: b( v# C$ m' a/ F) ?: B9 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * f9 _" X) V1 E: o! Z" g, a* S
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