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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, E4 g( ~4 R6 e
input mcasp_ahclkx,0 \( ]1 q+ W( z& H
input mcasp_aclkx,# g, n9 T! A6 m6 k" n' U; J% |
input axr0,' O/ {( T! }, {; |0 a3 _5 G& U5 w
# V3 C# o0 ?6 b1 o& {
output mcasp_afsr,
6 L# y! R1 r; E( I, h& poutput mcasp_ahclkr,
: ?, v+ u+ d8 H/ Koutput mcasp_aclkr,3 G F6 Q# C# x' K9 Y' `0 `, d
output axr1,# R i5 ^- G% w5 ~& n, b
assign mcasp_afsr = mcasp_afsx;
* U) X7 R9 V3 B4 u* |) F% passign mcasp_aclkr = mcasp_aclkx;
1 K( J* ?) R# [2 K, R# x1 V8 gassign mcasp_ahclkr = mcasp_ahclkx;
; m; z* p' k- e' W) j* Rassign axr1 = axr0; 7 t7 ]. x- h, g
* T0 S6 O W; T9 k+ P5 [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 C, d; G% @# r* Ystatic void McASPI2SConfigure(void)0 t- r4 K* I& |4 P
{
. e0 w5 z9 P/ L, W4 q& AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% `0 }6 S4 O4 G% ~- o2 D/ ?. F$ o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 x$ c; K! `' I: s" _7 T4 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% {5 M6 n5 h( u2 G* q* t& LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 D3 E0 B$ D7 F, FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! f- h" l% i6 N6 i6 b9 {/ r$ v! BMCASP_RX_MODE_DMA);& M1 {$ C. @8 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 M; x9 c/ Q. ]0 U" vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 I, G4 K- U, W7 T8 A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: V7 n" W, p, _* iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! }6 s8 w. \1 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 T$ r6 S3 ?1 j& m8 a2 k9 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 Y+ O V. s" M4 F j# SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ r1 l. S+ r9 X' mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 w. [1 b4 u/ e- W# F$ Y6 \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 W' E& f3 y) d- j) k8 W; S0x00, 0xFF); /* configure the clock for transmitter */
1 c; _, W7 U, ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 ~1 g, \, y1 V! Z/ | hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + j2 T5 ^& g; U8 X+ g% r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! W9 S7 w% g+ u1 ~2 h
0x00, 0xFF);
" z$ u$ }6 H5 B6 d! R; R3 p' W/ }. c# g# u9 L
/* Enable synchronization of RX and TX sections */ 7 X: `8 S4 _! B: T& `& W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ _) ?( Q: z. M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 u' R, p7 w; U: T% U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 q7 \7 R, f$ I
** Set the serializers, Currently only one serializer is set as
7 C6 Z l6 }( |3 F H- v; R1 N** transmitter and one serializer as receiver.5 p# l3 q1 N( t9 Y8 J* @/ N: _
*/5 x" O1 F7 e- \) [0 w+ j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 k3 W. j j r) v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; ]( j& \. T) _- f- g1 W `
** Configure the McASP pins ; e: y) Z# r9 u0 a- ] u
** Input - Frame Sync, Clock and Serializer Rx
; @6 a; J4 ~0 s) e% y8 v8 q** Output - Serializer Tx is connected to the input of the codec
% K8 q* L" w8 J*/
: G0 a/ P* h% Z x9 ]' l- NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ I/ c; V6 _: o; T, M+ `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 y# C* f0 e* G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& f- a$ B% }, Z" v1 V( R3 @& a# A| MCASP_PIN_ACLKX/ W% \( |$ g* o( z& r
| MCASP_PIN_AHCLKX
9 \% t! e3 M) a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& S; I8 ?# d. S0 AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# e- i, Z) G$ x1 l+ P8 ~" m# M* [| MCASP_TX_CLKFAIL ' C; D2 I' r5 E, E: f- z5 b3 A
| MCASP_TX_SYNCERROR
4 C4 V8 @& W% }; Z+ B& T. A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! `1 m ~; M, s1 _: D; w8 q| MCASP_RX_CLKFAIL
) u+ o0 E5 G( @| MCASP_RX_SYNCERROR
' V1 v2 V: g, _* C& T| MCASP_RX_OVERRUN);7 ~2 S; p5 w; q
} static void I2SDataTxRxActivate(void)
$ T) ^+ V- n) G- _* R1 ~% e; v{) j+ |6 D. Z2 y7 J
/* Start the clocks */
4 Z; K% m8 i" S$ q7 t( _% GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); o* k& K4 ?' s2 S/ X- U) M4 K( c% U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 d g1 w1 n; U) j9 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 C1 _1 r& J. @
EDMA3_TRIG_MODE_EVENT);
! O0 V! a3 B# S. o+ MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 ~1 s7 w* z$ m0 V3 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: ~& P' P% [0 A3 M; A" iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 A: I k! B2 y; _# Z0 c: Y; S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- u' N; C S$ q: w- w! x' F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) j) O) w" i3 h6 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, h* m& c( H3 N+ i" K) @' ]) U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ {! m: l% P3 a' G} @! t7 c' A8 B% J' K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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