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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 S, b. |, R: p; F- \input mcasp_ahclkx,
" A/ L8 V7 [8 E8 E. P7 zinput mcasp_aclkx,8 A$ m/ ?. _4 A9 f4 d% S
input axr0,6 n0 @. a# q3 d/ F" P) b9 A
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output mcasp_afsr," P$ ?/ F0 z( i* }( Z
output mcasp_ahclkr,
3 p2 ?& Y6 G0 S) {output mcasp_aclkr, O* J% G; j8 {) P8 w7 w' R4 W5 l
output axr1,& N6 f$ R- `" y V& p4 @1 g( w, n
assign mcasp_afsr = mcasp_afsx;! k# r, p" ~. i5 p( @
assign mcasp_aclkr = mcasp_aclkx;
: n+ n m$ W. Q/ [: j9 R6 R& X( Massign mcasp_ahclkr = mcasp_ahclkx;, E6 K% i# n2 D' |" n9 }
assign axr1 = axr0; 1 |" P( \( f2 z) B) V+ \7 k) E
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 M" O! z7 _8 g' S! l9 m
static void McASPI2SConfigure(void)5 v5 _: N- G" _
{
$ {% Z- [6 \, S( t9 |" b9 i+ lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( D7 Y2 [& a; `5 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ t4 }7 L6 ~$ WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 Q; H( y( {8 a8 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ C9 W; J; [5 P" b3 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' B1 O# N; s4 [
MCASP_RX_MODE_DMA);2 |7 O' y) q* A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 E: S3 z4 r0 Z4 Q' AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 F9 G8 w% y' v9 n: U+ e- s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ D6 |2 n- M0 q i! vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( f4 h3 c5 W- s1 N; [0 c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 V+ _% @8 _5 W4 [% @) ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: ^$ o* q0 p& @% G; ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ H7 F- h! R$ ]7 Q" \. bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- z2 L8 q/ t" O" H3 I$ i: j3 s. FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, J% S4 D) j! L: ]1 z X7 c) h' }0x00, 0xFF); /* configure the clock for transmitter */0 g N! O& d9 V8 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( W# C( K" _: a d5 B4 O3 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + P S, ]' ]2 t; k% q: ^1 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: U; d0 `$ W* D8 q% E. K z
0x00, 0xFF);5 Q, K6 ?4 _ Q+ v! ?
6 [9 I. w5 X& E$ m5 P. q& F/* Enable synchronization of RX and TX sections */
: A/ J0 ?* ]/ f0 N2 ~, `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ c: F3 ~; F* ]8 B; l# c1 A* q4 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: j2 {4 y2 L v3 _. ~; m$ dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 d% `; Y" h! `1 {/ r3 j: z1 x: o** Set the serializers, Currently only one serializer is set as. T7 G* @3 z8 M- @/ Q& N
** transmitter and one serializer as receiver.
2 x9 V) V1 T! E/ ? F9 W, G" j*/
: K+ l6 Q: b: ^( DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, m% n' x% |2 Y( |1 QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 d* I" c3 \! ~: ]
** Configure the McASP pins ; L5 o6 p! S) ?& `7 x0 m S% g; p
** Input - Frame Sync, Clock and Serializer Rx- o" g. [ k' e& w% j7 Z& G. I
** Output - Serializer Tx is connected to the input of the codec
$ P, p: K2 v7 e& {*/6 p! t( N( W. N- S* H% U! U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 {7 X) L8 R3 v5 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 ^) n8 i; s" e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 b: ^ T r! P: b7 N [2 U| MCASP_PIN_ACLKX0 S5 Z" s8 F7 d9 I& @9 z. n+ y1 [9 m
| MCASP_PIN_AHCLKX
$ r: Z u' s% O1 {0 d6 W. a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* l+ @: `6 I% _+ C9 Q' H! G/ a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- y9 n' U" }( a5 E# q| MCASP_TX_CLKFAIL 9 q ]* E; E1 n8 m9 |6 U
| MCASP_TX_SYNCERROR
5 l' t8 |* m/ r$ S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 H2 W; x* y( W; Z {0 y+ Z% i| MCASP_RX_CLKFAIL
, _4 s/ _" i0 W% V( U& u2 I| MCASP_RX_SYNCERROR 0 x+ d8 n- {( t) G2 G8 B! A) f
| MCASP_RX_OVERRUN);* U& j! t% {4 p+ d K" a
} static void I2SDataTxRxActivate(void)
4 k8 ]4 h2 K$ T3 `) }{
, |8 w0 @: d$ x+ O6 w9 H6 Y/* Start the clocks */
) j4 `+ _2 c& e# {$ ], CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. D9 G1 f8 ?" n# j! K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ d! U2 i, V8 @ tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: Z# |, `) T0 z7 X
EDMA3_TRIG_MODE_EVENT);! e" A1 h( ?3 g1 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' Z* i, T1 H' G5 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ Z( t( C+ j; ^1 J9 t# ~7 e' u! l' G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ A5 l- K2 z# u/ K& i2 u. t' g) `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: V G' C$ M( h* c U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( s5 O( }. }) ]4 A- ~& @- O+ h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 L$ j6 n! M0 C- X; BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 k2 v1 z' l/ s+ D}
# F1 m/ S6 R! A& o; F t# B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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