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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 ~2 v1 x; m' B' B$ X
input mcasp_ahclkx,
' r, _+ d% c- ?8 Jinput mcasp_aclkx,2 z' X# V: _ _6 t) U
input axr0,5 `) O2 k! D% |+ L" p3 {
# }3 [8 ^6 K# s& m( k1 s. n. K" i, noutput mcasp_afsr,
' N5 D7 S( B% h5 voutput mcasp_ahclkr,2 D3 b6 }: x, k* B+ ~7 E
output mcasp_aclkr,
1 V# A6 r9 |/ o# J, Loutput axr1,; l! q; [4 A6 S1 B: X, \
assign mcasp_afsr = mcasp_afsx;
- \/ i) i7 S# u8 G8 M0 z dassign mcasp_aclkr = mcasp_aclkx;" q8 T+ a, [9 r" n
assign mcasp_ahclkr = mcasp_ahclkx;& c: o+ v* c- T5 b# ?0 ?6 B
assign axr1 = axr0;
, g B( V/ R$ j- U; M- N% a7 g
, d. {+ Z. V5 t* N! @: k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 ?, s4 O% R8 J& f) H$ o6 S0 dstatic void McASPI2SConfigure(void)/ ~2 y8 x9 y/ |, \: T0 z, S
{$ c* P& ^6 w) F: b E; c# O |6 U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& b0 `5 Z/ @) O4 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# I, M$ ~# t( f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; N2 `* m+ r$ h2 q7 k$ S8 u" K6 V4 a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 O# z% u; T0 @5 C9 P7 p' M7 @/ }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 L! K2 q0 ]; n: ]8 F6 b }MCASP_RX_MODE_DMA);
' \6 ~' D. M( `! I" c/ DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. F, A7 P: t4 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 {7 V. y, X0 y* W+ _ ?3 KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 w7 J4 S& O9 s ~& X1 TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 f+ `/ q- e; n3 Z' R) P1 N! uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# m4 q4 g& y0 u4 |2 o) f9 v3 g3 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 E2 _! k. ~% T0 ^/ ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 _5 Z- k, \: M8 u) t0 g3 t0 b K- `+ eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . x& p4 u0 C" U4 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# {4 G: h. j/ a- a- A
0x00, 0xFF); /* configure the clock for transmitter */
0 E: |+ j' h; J, D# q7 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: X; }3 b' }5 _# [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 ?; N; f$ r$ S B. [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. i% V' {3 Q- d m1 X2 Q
0x00, 0xFF);
) J) t1 i) X- v1 n' k& \- \$ v9 _4 m! k
/* Enable synchronization of RX and TX sections */
4 F; |7 i; l* ]0 J* w- r o4 P2 iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ C* t4 w( d- m! ]3 j0 o* d8 vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 a+ V' h6 V. Z+ X& c( b6 K: fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 I2 x+ m! U+ {) Y# ?' p** Set the serializers, Currently only one serializer is set as
) H5 V* `) q \' A** transmitter and one serializer as receiver.2 m: L- J' C+ l8 P. l
*/6 f4 ]. R$ E1 V, x- I5 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* U* C* i S. d" s- t! qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# q( n* K8 t0 v# z5 b- Z- N, F% O
** Configure the McASP pins - {, K: V0 \/ a; h9 x& s
** Input - Frame Sync, Clock and Serializer Rx
( B v& k: l' V- R** Output - Serializer Tx is connected to the input of the codec
* g8 f9 K. k$ `8 s5 o5 G; |*/3 a% J/ _5 @2 p2 E) C( b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 [ u) H# ^& e8 _) k5 x* j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, K5 A6 w0 x, l! @3 o' ^1 g9 v4 E% n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX u- @3 L7 t( r3 z5 i2 a- ?
| MCASP_PIN_ACLKX# U+ s% {- M/ V: g! S6 D
| MCASP_PIN_AHCLKX) u. U# J! P& q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ p5 F4 Y; U/ c t$ qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 y& B% z+ o! I) l7 Q( @| MCASP_TX_CLKFAIL
& i% J2 t+ V! R: ~, L {( || MCASP_TX_SYNCERROR
9 x# M/ O$ V- `& v& d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 c- L' k/ w7 D1 b2 E) a- w2 U| MCASP_RX_CLKFAIL
' l$ {/ [- a! w) S| MCASP_RX_SYNCERROR ) y& `/ V: J+ v6 X6 J2 \
| MCASP_RX_OVERRUN);
, u% x2 W0 j* f7 J} static void I2SDataTxRxActivate(void)
1 U4 s: v# Q2 m8 m3 A2 V4 u{" q" c, k' n: Z0 U0 P
/* Start the clocks */* @" r. L9 f8 t; [+ a( K0 _2 g( X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( R+ T& F! g* k( E3 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 B- S* B# o* ]3 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# {5 I0 J+ p% _ D( ~
EDMA3_TRIG_MODE_EVENT);
6 O$ o- z; W2 r7 q) xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& D5 R9 u: H9 V! u0 U6 S* T/ D% pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ I7 T6 X: [5 ~* A7 a; y6 M; FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' \4 ^8 E0 t" W0 |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 Q( p2 x6 `' e; T0 B) Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 v1 O5 f( D4 H$ j: w/ e0 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 U0 O, y* h- p6 R6 e* R! jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% ^+ x- |9 \7 a) U+ l} / O8 X+ u0 g3 I' u9 @1 u J- r" r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . j( m& [3 g5 a! h4 ]2 t' D6 a
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