|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. D3 k1 q- q" D: D$ S
input mcasp_ahclkx,
0 H, E5 J& k( Z k U$ m2 Finput mcasp_aclkx,. K5 ]# D, n* J9 d. ?5 }
input axr0,
V% f) L- j7 c$ \+ ?( k# u
- n% ^ y' @7 R6 Toutput mcasp_afsr,
" ^3 c8 s3 P7 f9 E; soutput mcasp_ahclkr,- }* V7 g) z/ F7 a Z
output mcasp_aclkr,
0 w0 Q& z, V; h: H% f4 o1 Qoutput axr1,
( p( l# g! F) q5 f+ b0 e' [ assign mcasp_afsr = mcasp_afsx;- O3 B5 V: I5 A% v) |
assign mcasp_aclkr = mcasp_aclkx;
: H6 R. l+ F9 L$ W0 iassign mcasp_ahclkr = mcasp_ahclkx;
/ t( @2 H: s5 h2 e& F) v/ D, `, nassign axr1 = axr0; ; Q/ K' a2 V, V7 i
, r, K- {0 @$ v% B6 ]5 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( n- Y$ O( |4 H. n( d0 @. ?static void McASPI2SConfigure(void)7 w0 @* Y! ]2 x3 z" u& s
{8 |, O+ V7 t4 j( W; M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 @) x) ~4 Z# K! q0 Z5 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 y/ [% T6 x1 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# F7 M! b# c6 C; M: N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# N9 q8 T9 D6 p k k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 M& L7 o b& l3 b
MCASP_RX_MODE_DMA);+ G& c+ _; b7 { ], n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 v: H( F9 c, U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ x# p% G( F( o ?, t% w: l& UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; J& b& H5 N7 k" M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 j5 z% r4 ?8 q* v' [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * O5 q$ I# y2 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# |; q n. B w/ u% i% K wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) w( T' L/ R, I# [3 \( XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( T/ i! O& v+ c' ]9 h' f5 k+ Q7 B; z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 q+ r- U! A+ M: M4 z0x00, 0xFF); /* configure the clock for transmitter */* J0 b8 ~% T! s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 k0 f( B5 e z" J4 W$ ?( iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 b+ Y2 P0 D2 d7 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& G/ a. W( c9 r$ ?- Z0 w O* r _0x00, 0xFF);
6 ^5 C/ f& h& G7 @! ^( M- w3 @! b. b6 {
/* Enable synchronization of RX and TX sections */
6 j d& n, ~ `2 u# UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
r; N, l5 X2 s! V, j& j+ k: o# E$ bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: w9 r' P* Z3 v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" b8 l5 h( G; a+ Q. j- t
** Set the serializers, Currently only one serializer is set as
: k; X! z4 U- { Z' g6 \; T** transmitter and one serializer as receiver.
: _$ V. ?) m- b" `& }9 W0 m) U*/
! x* k7 ~, Q; A% |6 p+ y7 ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) N7 j3 q2 B3 K5 \- \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 t2 C9 X% A- D+ V8 v
** Configure the McASP pins - z7 O2 o& H b5 ^. \4 W3 U$ G f
** Input - Frame Sync, Clock and Serializer Rx* \, H* ~# j- }9 k3 k- A9 ^
** Output - Serializer Tx is connected to the input of the codec
8 L! M0 j. B$ B0 H*/
0 g: K3 m" D3 d2 c# s6 L4 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) O( e/ j& o8 C \8 _% n% q$ KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 K" w) [3 O! R) r7 I6 y& h7 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- H1 z% ^2 R2 s$ m( l8 }+ `
| MCASP_PIN_ACLKX/ P% {& i9 V& A: G5 ^- ?
| MCASP_PIN_AHCLKX+ W0 h# ]8 m8 g; d1 c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 C. h: I" z6 X& ~/ D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" h1 E% r7 x* J| MCASP_TX_CLKFAIL 6 b9 j$ d; b6 g0 g7 r
| MCASP_TX_SYNCERROR
- s1 L6 Z* T4 ]/ e( Y: x3 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 @/ `0 v* p' J5 `* c| MCASP_RX_CLKFAIL
+ O" B4 e+ F: F3 D$ C| MCASP_RX_SYNCERROR - k, {" m G4 y& Q( b$ p
| MCASP_RX_OVERRUN);
% M0 J) E [& x2 @, J2 n2 s} static void I2SDataTxRxActivate(void)
' Q1 k6 j& F8 j- G1 T1 m{
4 [9 f+ u* E- {/* Start the clocks */) ~5 _( T9 e) G+ a9 t( s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. w3 Y" S" S1 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" `3 y' O& h& o1 B) ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) f) n6 w1 t. H3 y* wEDMA3_TRIG_MODE_EVENT);
: M' D$ ?. s5 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 Y7 f* ]6 S, J" I7 P1 R' l+ n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# S& \$ L# @" n8 e% B: ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 q: K. L4 r$ Q8 \! q, p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! \* \% n1 J) e- R2 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) K& Q8 x+ [$ {4 S n. k UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) D# V- }! }# [# G% D) bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! k8 p2 [3 O5 ~: R- G} $ l9 p' h- D- ^7 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / ^' N4 ]2 j" T3 X" A2 M
|