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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 d/ R. W4 x3 oinput mcasp_ahclkx,0 g6 Z9 [: a9 u( F, j' Y
input mcasp_aclkx,; @$ N1 C% b' l: `
input axr0,! ]# r1 V* l" S# r. z9 H' B
8 U- O" |% { |, d$ ]2 eoutput mcasp_afsr,6 x# o' ^* y8 G* D/ C
output mcasp_ahclkr,+ C# \9 S. w% P$ e8 q' h& ^6 B
output mcasp_aclkr,
1 g1 ]. I( H$ h1 E2 s6 l9 r* I) L' Doutput axr1,
) T; G5 ^3 f6 [$ ?5 M( f1 z: N1 T assign mcasp_afsr = mcasp_afsx;0 f0 P' n1 `- g# M! ?
assign mcasp_aclkr = mcasp_aclkx;
) G- I& ]4 J8 f5 Q- sassign mcasp_ahclkr = mcasp_ahclkx;5 F* t+ F% M$ U+ a
assign axr1 = axr0;
& F6 v. E: o- N7 \1 C) U9 q
' ]6 r, a1 n4 B* K+ y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% u* F7 @5 z. _- L( O5 g' Y) C5 astatic void McASPI2SConfigure(void)
5 |3 J# p7 w8 J) G. }' t{
7 P" R' M, C% D5 G4 z* u* O1 p# TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 M: [; K3 J5 T" g1 L1 y9 m& oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 |/ g* N: ^# i9 z+ |& x. tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 p# f, c4 Y; ~6 x1 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% m/ b: W& }& c" @' G& \0 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" p) d+ p; n. R3 x& JMCASP_RX_MODE_DMA);
" O$ z. b( }+ r9 r+ z& OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 k; ^+ {$ k t% H% x" hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 h" n) U! y2 i0 c tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, t( g( {- z# Q7 T! s1 h3 ?- j- p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* G0 f7 p" i s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
u5 Z+ N' ?* L0 P, g0 L7 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 R0 @1 d+ {2 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! b/ B% R9 m3 b" |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, I' _0 g7 c7 m1 ?+ O2 q9 O$ AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 A2 A4 e7 O* [; r! `, C( V
0x00, 0xFF); /* configure the clock for transmitter */' D2 b- [9 }. E( ~, t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 n$ Y. V+ U8 u4 c" d1 A' g+ D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ u/ o9 G* x5 {: c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 q2 N9 E) x* F' V6 @+ Z
0x00, 0xFF);
- w; R" k# C0 r( G9 a1 ?0 Q% O+ I) k$ g5 q' \) Q! \* A" ?7 v; p
/* Enable synchronization of RX and TX sections */ 4 c: W& Y9 d6 r) }, f1 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% W# I' U! j. k+ I! ~2 {, [8 m" HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ Y" k" Z( Q+ h* J% z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# d; b( v- f9 z& E1 r/ u J9 k4 C** Set the serializers, Currently only one serializer is set as
$ B; o4 y& Q* v2 ]2 t** transmitter and one serializer as receiver.
3 U2 a B. p( e, [0 n*/3 n8 W: T# }" p8 t+ N0 K( c# }9 n0 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 Q2 n" ?/ j3 h' B. yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' M o& D9 M7 n! B4 k+ g7 n
** Configure the McASP pins
3 n" ~, U2 D1 ?** Input - Frame Sync, Clock and Serializer Rx
O( u( {$ e3 Q0 t- {& b; |** Output - Serializer Tx is connected to the input of the codec
3 U7 z9 V% \7 ]/ t' L. U*/- u% F, K" g" F' d4 [( C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ X2 H5 v2 w. t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. w7 K6 _) v! {7 |: n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ X6 v8 t: ~9 W3 D1 g- V4 Z6 v| MCASP_PIN_ACLKX! A# K% a7 C" U: s3 m9 B8 E
| MCASP_PIN_AHCLKX7 [7 B6 k9 {( S) H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 D+ k* N2 p) v* H! o" t4 P, H$ q0 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. s N5 ~/ w5 j; z5 ^5 W& W7 P| MCASP_TX_CLKFAIL + Y! j) I% o+ g. b& }7 v
| MCASP_TX_SYNCERROR% C# V% s* B+ `3 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, ?3 C; B# u( f3 c9 r| MCASP_RX_CLKFAIL
/ E. n9 w0 C9 ]| MCASP_RX_SYNCERROR - J% m9 S+ }- V t. E
| MCASP_RX_OVERRUN);8 |" G6 {5 ~; @: ?, g5 q h
} static void I2SDataTxRxActivate(void)
. b0 s$ [5 w5 S# M4 v1 s$ S{
/ {7 g+ m; B) k h/* Start the clocks */
8 r3 l; G/ b( O' ^& p+ sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 ~; B( w& A$ `( o' ~1 R3 b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 F& x/ C' R& @( L- Q$ M1 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; X0 B0 i& J7 b$ E& PEDMA3_TRIG_MODE_EVENT);
% @4 q# [. v0 A4 n9 ^& Y* z: C x1 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 z! ~2 O# [: S ~; iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ F6 H& s, M. o+ E$ VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- h* f7 @6 S9 |, J( X4 H/ |: RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( d; S: B# h9 c; G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ H) M/ Q! @7 q. |& c# ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ n$ H! {$ a! e/ w5 p: y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: h& p3 E; R0 j$ e4 y4 y& C* U
}
: z: y( }$ |" l8 }3 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , y* S* i+ P J2 |+ H( Y$ o
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