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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
@6 ^9 [4 O$ H% m; I7 finput mcasp_ahclkx,/ T1 N* r% J/ R/ y5 p
input mcasp_aclkx,( y7 ?: q0 f# M& Q$ @: m) i4 x9 W
input axr0,
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( ?& K; r0 [ houtput mcasp_afsr,! d2 p$ f. w/ z' Q9 ?* u! C
output mcasp_ahclkr,
( M6 }' L8 m0 G6 D8 ]: l% @output mcasp_aclkr,
" F% c2 ~. i$ b' Z$ r' T$ N' |output axr1," I4 D6 `- T! f3 ]/ W J
assign mcasp_afsr = mcasp_afsx;! _5 s! l+ ~- J1 J! F2 t
assign mcasp_aclkr = mcasp_aclkx; I# O3 D: `8 E- H6 N
assign mcasp_ahclkr = mcasp_ahclkx;7 l* F( y$ F+ K7 h
assign axr1 = axr0; 1 z9 E3 |, P7 T% q% ]+ b2 h0 @; U
& @* G7 B! A2 u- m9 S: Z1 z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & r$ i( u" j4 q2 S7 M
static void McASPI2SConfigure(void)8 K& k" @" @* y
{
) z }5 q5 Y& AMcASPRxReset(SOC_MCASP_0_CTRL_REGS); L, s' a1 z6 c2 p( |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 P: I5 X7 \; F) Z' jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ ~) f9 D6 V1 H# c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ O0 M2 V, H6 N G% fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 G6 O+ q( u, o) G4 @
MCASP_RX_MODE_DMA);
* G6 g- `: F/ T: W. I- ]7 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ Y) l! |3 Q4 [6 ^4 @% B( c+ Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 B, t1 I' E4 E* x9 N/ E3 A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 e2 U! t) q: ~, b( \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 ^4 ?5 J7 w3 [, ]- w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # i! \) |* e. A/ z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 U9 v) G9 t6 _1 a, Y! v% z2 EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ z4 {% S/ v; i6 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 X: g2 n! M {1 `- ?8 D. l0 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 I8 Z1 W! v! X7 X8 k. u' q
0x00, 0xFF); /* configure the clock for transmitter */% s3 K2 F6 ?( @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ w ^ X; C! s: j' c! s$ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, P0 k7 o0 d! D6 m8 p5 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' H( u/ |+ X5 U W( ~0x00, 0xFF);
1 r2 M# w3 ^" A9 \ B! T1 H/ _4 j/ C- v- ], d) X
/* Enable synchronization of RX and TX sections */ & y. x( {( K# |6 x1 }# L8 A- i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 z# x2 S) q _' T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 x( A6 C5 ~! LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) |8 U6 a; Q8 Z" Z& J5 `% ^
** Set the serializers, Currently only one serializer is set as
0 z3 w8 a/ j$ N! {** transmitter and one serializer as receiver.8 M' Y% ^- n; m% M! \
*/- y# M; W* b7 p* i2 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; q- ]0 g! D( w9 x+ Q2 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, y3 x" h) c8 m** Configure the McASP pins ) l4 p4 o* X- f$ n; C
** Input - Frame Sync, Clock and Serializer Rx
# B/ y" X# Q4 z r0 m6 Q: e** Output - Serializer Tx is connected to the input of the codec
% j6 a: r7 c8 f( c" a8 q& a*/
4 Z' z# F. s/ P' g4 l, ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: N7 p5 T8 J& |2 |* J( y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' M# w$ E6 [% ~% m3 f6 U8 Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' {0 \4 P1 K: |% ]) Q* _' e6 S| MCASP_PIN_ACLKX
8 j+ p* k+ U, X7 G| MCASP_PIN_AHCLKX6 G& A* O4 Q! O! B$ V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 ?7 ?7 c! ~1 b: Z; z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 u8 t" }8 |$ b/ g2 r| MCASP_TX_CLKFAIL 2 ?( q- c$ d4 M! Y8 f8 T" B
| MCASP_TX_SYNCERROR) J* ]2 Z1 W7 C' N5 k3 T# M d0 S! v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" ~5 T r9 G; w: A! [| MCASP_RX_CLKFAIL
4 w9 I' u( A* k$ p) O Q3 F" y% l| MCASP_RX_SYNCERROR 9 I( N6 z; ]& H
| MCASP_RX_OVERRUN);
2 C! R0 I. C3 q m) u} static void I2SDataTxRxActivate(void)
; z8 F B( a% R{4 X+ T _1 F/ o: n) ?) }1 }. M: Z/ C t
/* Start the clocks */
' m, G; A; a# x0 G3 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 o( M: n9 y5 L% {9 P2 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: u0 p1 d( }; B% }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ G3 s5 B2 M/ j7 H/ {EDMA3_TRIG_MODE_EVENT);2 c$ n0 P! ^5 ?& T) s9 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : U& X3 l5 S( Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! Q6 r+ S8 N4 Z+ t, a0 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 Y, [0 Y4 W1 }3 h6 k4 WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ H* f, W& q2 s* F( h3 K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// G% }# m6 _$ c, `; S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, X" G& ?& V" F. a6 g2 m' Q/ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 N {$ m* @' v8 |/ U M
} + r, @8 I( }2 u: I2 S7 \0 ^" l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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