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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) l7 n5 ]4 l( v- |2 |/ ]input mcasp_ahclkx,: s$ A4 j5 M+ @! P
input mcasp_aclkx,. X* s* x& O& [8 A: [8 g/ |9 G
input axr0,
" i5 P! _3 l4 @' R. D- l; j7 d- V# F. @0 s
output mcasp_afsr,
3 M6 \5 z' y6 ~8 @! u3 Loutput mcasp_ahclkr,
/ M0 |: P! P) G. O0 {output mcasp_aclkr,
& s1 h+ C* n9 x- [! noutput axr1,2 P$ g# T1 Q0 u* u+ ^, n
assign mcasp_afsr = mcasp_afsx;
- n& A& t6 k, |( r1 d$ _8 `: xassign mcasp_aclkr = mcasp_aclkx;4 q% Z- x/ e* b/ Q
assign mcasp_ahclkr = mcasp_ahclkx;
! G2 c- ~8 J$ {- G' j% k0 q* |2 Yassign axr1 = axr0; 0 j5 l3 ^6 d6 x- f* G, {
4 C' w' J3 O5 L: A4 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ I2 c0 D/ r, F! U% c2 `3 z9 Kstatic void McASPI2SConfigure(void)
' }* Y! x4 `) l& G. r E{
& @& O7 @' a" |4 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; J& c( o! A" @; DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) b$ o4 S6 f' |* \ t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% h# [6 k2 \: Z7 V+ _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& r+ i. ]$ K# ?% C' p0 r9 I3 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: G! u) ~$ Q& h; W, k- o0 _
MCASP_RX_MODE_DMA);
7 y# ^9 O' _8 i1 e5 X* y: L$ i \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 k, @- O5 B, K' E- x2 ]' z6 uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# F6 e2 z4 V& I [+ B0 c u9 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 S: a8 K% [+ g% e- R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( o/ |/ V8 ^8 @; G0 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% S/ X0 Y& Q+ x/ s( C9 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" Z- y& D, w$ F% s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) y6 V: A+ B, Y7 r% n& Q9 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + {' g: @1 k6 Y. l+ l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) H' X$ L$ p9 a8 ~& r
0x00, 0xFF); /* configure the clock for transmitter */
, s$ g2 }8 Y$ Y1 I/ V% Z; PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: n6 k1 H( p$ o) M. c# Z* M- CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); C3 D4 f3 z5 l) [$ x2 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# @6 b4 Q. t6 L' ?
0x00, 0xFF);
% o& i! O x' \: J7 h ~+ \ H
; N$ V! U4 c8 v T2 |) D. p/* Enable synchronization of RX and TX sections */
5 g& ]# _% p. N3 E( t) Y# sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 R3 Y$ @4 z- b# [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 A9 s4 u) f9 \ k9 K- {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 q! f2 h% i$ X9 x- g& i' T
** Set the serializers, Currently only one serializer is set as
6 D! a5 r: e. `4 q" p# o** transmitter and one serializer as receiver.$ x" T1 M& l( f" Q7 Z4 D5 w2 n K
*/
1 j0 N! |) n; V6 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* }$ z8 N* {! u0 F0 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; h% q" M2 x+ G( @5 x$ Q% y
** Configure the McASP pins # D# f) v3 N, P& e0 U8 t
** Input - Frame Sync, Clock and Serializer Rx- E I1 t' n% ~+ D, L" G$ Y4 D& |1 ]# i
** Output - Serializer Tx is connected to the input of the codec 6 G4 E0 S* h! f2 z% I. \6 [% V
*/
. R+ P. z I6 t" ~5 T# J3 D/ GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! a, I: p9 S5 M9 E/ I- p, H3 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 x- c/ {) t3 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 Q9 n0 s* W0 Q" p( V| MCASP_PIN_ACLKX R6 K9 \+ v* R6 }! q
| MCASP_PIN_AHCLKX
: p1 ^8 v4 w5 C- v6 @% B9 d' m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, Y) p0 S W0 M: r' R, I0 q0 G7 XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " C+ W! ] r5 [. E: N
| MCASP_TX_CLKFAIL 1 m' a8 `- B7 i% |5 s, {+ U8 j
| MCASP_TX_SYNCERROR
' j7 N0 }5 f- [2 e6 || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # ~5 h8 f5 s# c. H! e3 G% d
| MCASP_RX_CLKFAIL3 Q+ \5 K: I0 M9 x8 w) g
| MCASP_RX_SYNCERROR
1 D3 I7 ^/ Y2 _) H| MCASP_RX_OVERRUN);, U( _" _& {3 \
} static void I2SDataTxRxActivate(void)
% g0 ^/ T5 k6 W/ o/ x! q/ T{
, Z9 q7 b' d1 B/* Start the clocks */0 n2 X, j" f, d, N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& G" B2 ]" Z! y5 q, {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 M9 G, k" M* G3 F/ m5 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ Q; y: i5 G a/ s7 O! m. W( R& e
EDMA3_TRIG_MODE_EVENT);2 I- L: Q7 O. R; L& Z% H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 A7 u# ~- X" ?& W( b- h* [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( W9 ?. S0 T+ vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 T/ @5 F* Q: d& h; M( zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: {& u1 S4 R. u& p0 t7 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ A$ P! ~8 I, j+ L; G) y7 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ N! P* I( r- p; U/ D) a) U/ N% C* d# \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 E& X5 ], |# W- g5 d5 }
} 9 T; n6 ]; i7 l/ `1 H; ^' [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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