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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; j0 D* h" o3 x9 O' E5 i
input mcasp_ahclkx,. F& w, a& a% ~ x0 Y9 ~
input mcasp_aclkx,
* V; }1 e# h5 b/ Z9 B1 D: hinput axr0,: C5 N8 G7 [ X: f+ y" S
# C0 f3 z6 p/ \+ Y7 E- n& Z' H1 U1 h
output mcasp_afsr,
9 v' B! T, M' e" r# i5 H# Zoutput mcasp_ahclkr,- u& }% r. J7 J3 ?7 [5 t& g" A
output mcasp_aclkr,0 m8 X2 Z* W2 a. f- |" G- o$ u. i
output axr1,/ Z) M9 F0 N" c+ e- y/ E
assign mcasp_afsr = mcasp_afsx;" H8 o4 Z; f& i
assign mcasp_aclkr = mcasp_aclkx;8 a# K8 Z7 }$ g! c! @& H
assign mcasp_ahclkr = mcasp_ahclkx;% U# `* f0 ?. f) H. V6 B! ?
assign axr1 = axr0;
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% J6 W6 {+ P# l3 c" [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 b8 v2 e# Q- Q, |1 Y7 o
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' p% ]! [ a. G: }/ x, sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 {5 }4 ~8 k5 H" a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' f+ ?/ ?! ]6 d1 }% _0 T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 L5 B. _# y% \! b8 r% N, P( LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( x% g8 x# n m# C- N& e% l3 v OMCASP_RX_MODE_DMA);9 u" p3 _" d1 d; t7 G- f3 t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( u8 u( n& P- t5 U: I% wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 Q5 N" {- j! {3 Q3 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' V$ X1 f2 c2 r5 y9 k) G9 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( l% @9 W X. g" ^: T0 L9 D9 F. xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 f2 R' `/ x- w8 f. q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- y8 ~* B- {* C6 s0 K3 I2 lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& f( I+ ]0 a# B7 R& ~5 o& q+ ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 R3 W% z4 K' q. Q. s4 n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* s3 |& E2 }* @9 ^7 d! S! }0x00, 0xFF); /* configure the clock for transmitter */4 ?) l, H& ]+ G+ y; v: s8 K+ e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! l* c6 t4 N( V2 W: B' T6 W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * D9 {7 t2 @3 ~' m9 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 R3 P u0 d% a0x00, 0xFF);5 _, a& P& s) h
; A) m( p2 t7 B/* Enable synchronization of RX and TX sections */ 5 |0 {7 I; B u( q% y. P- d+ ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& }4 I. ~/ {; s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! ~5 {9 G; x# l/ r/ J( xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 N6 }, p1 d4 ]# W
** Set the serializers, Currently only one serializer is set as
" \. _) X* _; u$ c** transmitter and one serializer as receiver.- i% p) o, @6 P2 g4 Z9 U
*/
4 v/ Q& Y0 @6 x( P" LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; H% ?- z. U: O- g" w+ GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; P1 O2 J7 H1 G! W D) s; q** Configure the McASP pins % R! Q8 G: B0 z& T% P
** Input - Frame Sync, Clock and Serializer Rx) F" U- x# y( V0 V _
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) ?7 T. M7 t" @" ? y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ h* M& q) m8 h) K4 r: W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: Y. [% L; A7 k3 K6 e( C| MCASP_PIN_ACLKX
7 T) a5 O7 }$ y: r* i; g& ^| MCASP_PIN_AHCLKX$ r& V: g/ x0 I3 b6 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! F, a2 } L( h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ P' d; i4 b: B% n3 \3 ^9 u| MCASP_TX_CLKFAIL
/ m% B% q1 F3 _7 I0 W+ b# h' b| MCASP_TX_SYNCERROR& E; X8 ^8 y( i: b6 o! W0 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 q! J) M2 w w7 b' ^0 [ A| MCASP_RX_CLKFAIL. v! c" D; y3 N# P5 F3 [
| MCASP_RX_SYNCERROR 7 L" K1 X3 F* m& Q P- j% c/ @& ]& B
| MCASP_RX_OVERRUN);; @- T N$ n9 i. q+ z; I
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
3 V8 k x8 N/ G }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ u5 C& f4 m' n% g. k! H) ~" E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 q9 x C3 G/ j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 [+ W0 h: c: F0 m
EDMA3_TRIG_MODE_EVENT);# e/ J& P; ~8 ?- E5 K: s3 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) {$ v0 B: ~: e e3 o* E9 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# |2 D; t* o. K3 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 C: O/ k' X$ G" ^7 e* lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 @+ `7 [, M/ K9 ]! e0 Y: h u8 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 U: D/ B% e* J- DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 J2 ^' v1 N2 v; KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 j! w6 @* u3 Y3 N% K( {
} ' Q! x$ R4 w. \1 t2 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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