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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
_( B/ M* q# L. _input mcasp_ahclkx, }0 j4 B/ V" {* T
input mcasp_aclkx,0 c0 S" m+ f" f* [' X3 J' d) r
input axr0,! f2 z' v0 a# w U3 m
) D6 A: J$ h$ B1 v5 ?output mcasp_afsr,. y, p2 M2 R( h+ P
output mcasp_ahclkr,; o4 b, K4 r/ t% P. G3 k0 @
output mcasp_aclkr,
* M& M6 {- g* F1 c0 A! G7 z. M! Goutput axr1,
* |- G) [% c4 [9 u# q assign mcasp_afsr = mcasp_afsx;1 X5 b" O( Q0 {, ^& ^: J
assign mcasp_aclkr = mcasp_aclkx;" c* j- p8 G$ c+ j! Q. ^$ H7 j- G
assign mcasp_ahclkr = mcasp_ahclkx;
4 |, N' A9 N, y# o& f$ T: n9 Jassign axr1 = axr0; J6 N* i; M) g
% N" j7 `& C1 R W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 t( A3 H8 a8 \9 G) I qstatic void McASPI2SConfigure(void)
t$ P5 J; a! U* u' ]{
& R5 j) h3 F3 } @5 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. e+ u Y% j5 o$ e H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
k1 f3 z3 m2 _/ a& U/ t- cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 ^; ]: e5 J* Z, h$ L& m; _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: F4 h( |! I( j' A8 b& BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% z/ O4 D. \& a' S
MCASP_RX_MODE_DMA);, I4 W- m' ^# i* _$ b( v/ C5 }3 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, a+ C3 E7 Z9 j$ U( y# \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 g* s7 H2 Z' |" c2 n& yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 D! ^! y! q0 q- PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- t. X; F2 K6 R$ `8 o$ N# T$ p# nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - `/ _9 u& v# v6 f) e# X9 W, S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% b5 x( X7 x7 T" I7 zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% P- b) v) F: |8 w+ ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 W7 c! V: _$ S8 U7 B4 Y xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* E$ h& N: \0 a; y, Y
0x00, 0xFF); /* configure the clock for transmitter */
6 u% [' \+ w9 L7 z3 {& s) ?4 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 }$ E1 b( ]8 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! ~# P/ ]- A1 N) gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# F% C7 r4 E8 `" a, m+ M
0x00, 0xFF);; E. d' R( ^3 G+ F8 `1 G+ ]
* A- \# g$ L B4 p) l' F5 [/* Enable synchronization of RX and TX sections */
; P" O. |: U' d! ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) ]% u% ]4 ~+ q# D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 g& L* Q1 T+ D1 }# Q' ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) Q8 E0 {% K, c! v {8 H
** Set the serializers, Currently only one serializer is set as% ~/ _' E: ~. ]% J. B7 F9 \
** transmitter and one serializer as receiver.
/ \* Y$ `$ Q# U E& \, M5 W/ x*/$ g; s1 h/ A+ E$ K! S/ }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 M, m; T& c# B- v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 ?- i/ P8 k7 n& J8 W9 |
** Configure the McASP pins , { I) n) m9 D: w7 H6 i% E
** Input - Frame Sync, Clock and Serializer Rx4 P8 Q7 W J% R/ d/ }5 ], |( h
** Output - Serializer Tx is connected to the input of the codec . r* P1 `" P- }# K( V$ O
*/
0 h9 z6 m3 b; P+ D, e/ R) M5 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) c s2 J7 w: {, z) t! E6 u9 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ S Y6 p% {' v/ [/ jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( L2 o% h7 Q X3 p| MCASP_PIN_ACLKX) @" k O, r$ y S2 P/ T3 n
| MCASP_PIN_AHCLKX: X7 B: Z" x* N7 }& k/ I' V9 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 E1 q$ g+ k2 n. ~0 r+ jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ^$ w( {. _: o9 Z7 q
| MCASP_TX_CLKFAIL
" _; x {, A/ y' l; o* G| MCASP_TX_SYNCERROR
7 S; F. i+ ?* T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 j' u5 e5 O y4 ^/ \ b4 z, }| MCASP_RX_CLKFAIL
* T) U$ C" D: v0 t& S| MCASP_RX_SYNCERROR
E0 [( B+ f( Z6 ]+ o' J1 T/ R7 q| MCASP_RX_OVERRUN);
T% `& p& Q7 _6 r4 V7 @" X; |} static void I2SDataTxRxActivate(void)
! H/ q8 H- }0 A{
6 x' a* [; y- s- E/ \! t/* Start the clocks */, W/ p5 F3 W. q1 G% V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' z# W) A5 V5 s' i: c. |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: |; _3 h& q: a6 S% u/ ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 e7 D, m3 I) l8 ]% H0 c2 K
EDMA3_TRIG_MODE_EVENT);
; ~; u4 I4 }+ U% {+ ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ @/ N1 z/ R6 R+ l0 S& O7 n+ h- u0 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* \7 }, _( n8 ]1 D8 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 O" e3 Z% {7 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 I; j5 J! d5 w1 Y3 s! J- Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- M4 t4 A- Z6 M) JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- t6 A3 \9 D$ d# E" JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 Y7 h( _6 ~; p# r6 F# F0 [, [* V3 Q' \4 z
}
1 v& k! J7 r. _/ Q p: ?. {8 X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 d$ V% s2 u) p
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