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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 T( b$ ]" C' T5 m2 I) h" tinput mcasp_ahclkx,$ _/ N* }6 O, v! \! D) c& A
input mcasp_aclkx,
0 u7 `, ^9 \" yinput axr0,! L; c& O/ E, S" F% `) S% }: j
$ m$ D, d) f# T, B! Coutput mcasp_afsr,$ X; J: {- t4 Y1 l% _1 z5 E k* {
output mcasp_ahclkr,; d$ s& @# Y9 m" p
output mcasp_aclkr,: O$ q) e5 M4 @# m2 ?. A2 B! p- i, _: z
output axr1,
- v$ q5 p2 z2 ~3 J* P9 p assign mcasp_afsr = mcasp_afsx;/ D2 v7 {2 b* i4 d. d4 r
assign mcasp_aclkr = mcasp_aclkx;
, {" J8 X4 V" p5 G7 ?6 E$ _assign mcasp_ahclkr = mcasp_ahclkx;
& e' F5 @$ u6 G* ]* d( O* Q5 dassign axr1 = axr0;
( h$ a u3 c, t, o) l) i \
& L; u: i& _3 |" h4 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( Z# d# t) o( P M" O" v0 vstatic void McASPI2SConfigure(void)
" `3 O$ g& I, X" t9 A{( `* _ [! z3 N1 i5 ]1 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, k/ S" p) u. x. p/ }/ cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) q: z* F5 J C4 @& C. W+ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; P4 R# u. H8 FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. w/ w7 y9 O7 Z$ }& t8 U) z9 n; ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& g" U9 P' l1 t3 {$ O" ]- nMCASP_RX_MODE_DMA);5 P5 E0 E8 h/ k# y/ t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; r8 Z/ `/ K9 [4 S* w; O4 F0 [3 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ x0 _* c; ]9 p4 z- ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 m* i! \7 D6 Z+ _5 RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; }0 A [6 G' |2 B/ Q6 h! iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- H5 u1 A9 u# X% CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& p1 r* \1 b, N/ x0 ]7 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- a: Q) |* H: j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 p& V) u( e" X9 g* \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ k1 A0 x1 u& q. B) d
0x00, 0xFF); /* configure the clock for transmitter */
) }; L- x! G" W! e& |1 ^( ]' UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: ?7 |% r, |1 Y: o7 M) K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - u5 t6 H! c0 U, c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 e$ l$ h- \* ^% t, v0x00, 0xFF);
* Q ~+ w3 V$ ?- j2 a; u7 |7 O$ n( V/ E A! I/ v* q
/* Enable synchronization of RX and TX sections */
( T& m+ k6 M+ t+ Y& }+ |& z+ U8 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 z' p5 N+ E. b1 E1 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( K% M& t0 n9 r! i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. S1 |/ N2 n5 }8 t3 A( D) q** Set the serializers, Currently only one serializer is set as( P2 V5 E- [: h, x7 a3 ?* y
** transmitter and one serializer as receiver.
: V" J/ Z0 l* f% ]9 z) m% f8 m8 [# p*/. a7 A' |; E% t* L3 k2 q$ d- x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 a- i# b( @5 q8 K- B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: A4 d! C6 [- {# q& m# M' T! N
** Configure the McASP pins
; a( K7 O+ ^+ Q% ?: Y: O: ]* `** Input - Frame Sync, Clock and Serializer Rx! [( i. q) |0 c0 q3 w8 ~
** Output - Serializer Tx is connected to the input of the codec
' L p, c) ]+ T*/
/ r$ q- ]2 I* n3 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" n( {1 }) @. @$ c9 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& }8 Q) y! T- {3 w, z, OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" B4 O) G! v" y, @. i| MCASP_PIN_ACLKX
5 t4 n% a Q8 P' U| MCASP_PIN_AHCLKX% b: J& N& G; t7 ^: B& y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ H6 o6 Y+ Z7 l3 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 ~( K7 Z7 S1 E. V" t| MCASP_TX_CLKFAIL - v3 d+ R' W: D; _, u
| MCASP_TX_SYNCERROR
1 f/ H2 M* K1 l5 _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
P T% X+ i, t| MCASP_RX_CLKFAIL
: T4 B1 f5 h: W* T' a| MCASP_RX_SYNCERROR
; K# m# r- T( `6 v2 Q o" s| MCASP_RX_OVERRUN);# H7 Z1 ]& K. [
} static void I2SDataTxRxActivate(void)
( P6 k3 c6 v8 z, e{
) i+ g; n3 a3 a9 [/* Start the clocks */
6 m: M) t8 Z% U5 a- W% SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: n: {/ R# E! i0 N8 X/ {2 X" [6 M' n' q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: a( d. F% [0 N" `% @/ s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ^- B6 I2 o4 @5 z" t8 ~8 B
EDMA3_TRIG_MODE_EVENT);+ _: ]! X( f3 u. n7 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 m3 x! b) d) j% _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 L% _5 a# n4 S( ?- ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 K2 j. d' u+ w7 bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 }! E# C7 m+ ]* Y! q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 m3 N8 O! K* }7 p) |McASPRxEnable(SOC_MCASP_0_CTRL_REGS); D; o. @7 ~( V7 y7 G( W1 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' d) o" | Z/ g( H}
! `$ a6 l4 ~+ h$ P( f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . R/ O* O7 Q% A, I
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