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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 v% `! M; n9 A' l
input mcasp_ahclkx,1 T( \; ?/ ~2 _9 K1 ]0 U
input mcasp_aclkx,
* E6 J& `" }+ Y5 iinput axr0,4 O* e/ g6 ]" r8 z- v; H! T( L
. d/ y+ |! t( i+ ?4 b
output mcasp_afsr," C8 v) J% V) c) C0 ]
output mcasp_ahclkr,
: ]& X$ o8 u4 c/ V# Eoutput mcasp_aclkr,5 X7 I d( G! m" E4 \
output axr1,
; F& Z# H9 P; Q assign mcasp_afsr = mcasp_afsx;# w* H. f' i- Z) k5 l. Z: a
assign mcasp_aclkr = mcasp_aclkx;' s9 S0 g' q( A( n: n% P
assign mcasp_ahclkr = mcasp_ahclkx;0 @% n" z ^* s+ v3 `( g2 h8 S
assign axr1 = axr0; ( ]7 J5 z# Q! B2 ~
1 n0 p9 U0 ?8 m1 h. S& l6 z, s( \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ D |3 o3 n- d9 V) pstatic void McASPI2SConfigure(void)* v! b; A3 l8 n2 a
{
2 w5 a! d6 z0 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 Y2 H1 i7 }; g4 j% p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 D6 k& @+ a7 o% }3 P0 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; C6 }+ I- s( W2 X8 e6 T- ^6 H/ ]- y" Q0 \; nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 `6 C( T# e, ?5 zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% l. @4 I1 J9 v7 oMCASP_RX_MODE_DMA);
" W' `# m/ v! CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, Q# M Q( H+ Y! x/ b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 X/ G' o" K* N+ HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; i: \' ~) |* ~! f) W# g5 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 O* A5 j' s- L3 J6 [' f) c/ P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ E" [5 `8 G/ P k FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 ?5 ^# u. E# FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
^( H4 }! O6 E; YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& @8 U1 i& F% l/ j8 x$ m$ ~# cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& ^2 p4 E/ V- p) D0x00, 0xFF); /* configure the clock for transmitter */% a) h: _) Y/ a) I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% \! f' N8 S' w( c6 Y' f1 b! \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% |4 K3 S) Q' _' W8 [4 OMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 C, X- _3 P7 G3 p# G. R0x00, 0xFF);1 {) `( E+ y' }% @' e
) O9 N8 j I' b- w8 E0 L/* Enable synchronization of RX and TX sections */ 1 s I% N; e4 i' Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ c8 M9 e% \' x4 N* S9 q) I4 X; E8 v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" _4 {5 [3 [, q7 G- EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( s3 [$ `3 P2 k E9 ? O5 U; @2 A** Set the serializers, Currently only one serializer is set as
( g/ A3 M8 N/ n/ I** transmitter and one serializer as receiver.
4 c7 ^8 i5 r& e; C4 x: n/ L r: f*/
% q5 D0 o- X! J" _8 E) LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- g Y5 L) A' }" V1 _/ K! J9 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 l1 W; e# l: w+ X5 }" \7 G** Configure the McASP pins ( R1 \" F# W! u! X3 s4 b
** Input - Frame Sync, Clock and Serializer Rx1 @5 Z6 G n( b( l
** Output - Serializer Tx is connected to the input of the codec : s) D/ P$ U j7 s" j+ p
*/
3 @) _* ?9 W; V# E( iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) N+ m3 A* I8 b! o/ p5 H" J; Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 f: g/ x; N: z, T; [3 x9 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 l# m' w& C2 K9 ?3 V6 p F2 b
| MCASP_PIN_ACLKX
4 W6 x5 J8 W+ R1 \& ^6 A| MCASP_PIN_AHCLKX) O m9 y* Z- [1 |+ v) Z+ S( V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! B* R$ `% w7 i! A. Y3 Q, o5 a, s/ VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 p2 B$ [ c5 W5 H
| MCASP_TX_CLKFAIL , ], S" M' A9 g% m3 G9 P
| MCASP_TX_SYNCERROR
5 {2 ~9 G6 _1 l# w& k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # X2 R! g. r7 h
| MCASP_RX_CLKFAIL/ H7 D& L. Y# z+ H
| MCASP_RX_SYNCERROR 4 O& N* R0 @1 X! B
| MCASP_RX_OVERRUN);2 Z$ s8 s, V. \) s) p8 ?( Q" g
} static void I2SDataTxRxActivate(void)9 f# z. ?1 M$ D. S [7 G! L
{# ^, y9 P# F; d; f2 J( j4 y
/* Start the clocks */
- n% [" H: \( @" z+ h GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! ?8 ~, P+ b) O8 U$ R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 v+ G P% Z! C, e! c/ J. IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, Q: R+ R' ~8 n9 g) c h! B
EDMA3_TRIG_MODE_EVENT);1 F g: A5 M. w0 {/ o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - W' Z' P% S* ^* j, T6 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* f+ T$ ?6 G' t' F7 G: QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) b$ Z# D' m+ }0 J5 e, M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* ]9 P5 a- n" o% e! t# Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 T \/ }% _/ F* c% c. f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 j/ i% o% D$ m. ]# x6 o! ~; B( R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) c+ L% f* G3 q. v5 c* `5 n {; o
}
, K/ I5 l$ h, d, V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 @6 }" [" A1 Z* F2 U
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