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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 k- X. J# z" i2 C- C- b6 x3 Linput mcasp_ahclkx,
) D2 d( o2 i X+ T8 D2 |input mcasp_aclkx,
3 ~* V' @2 a+ @& ]input axr0,
- p4 c9 U4 l1 G* M6 \- K3 |) v7 H" a5 p) m( t" |
output mcasp_afsr,( {" `1 ^9 c+ B! u2 n7 I; V
output mcasp_ahclkr,
5 r3 ~) t2 a/ I3 h1 h" D2 uoutput mcasp_aclkr,
" B( o* r- k/ l) _/ {8 e5 p0 \output axr1,
5 a# H- C" ]- w1 W3 y1 c- \ assign mcasp_afsr = mcasp_afsx;* H1 a& c" q" v: }) u7 j" I/ J2 W* \
assign mcasp_aclkr = mcasp_aclkx;
+ ] h' _0 T) S! R5 R1 Q5 G) b3 V6 passign mcasp_ahclkr = mcasp_ahclkx;
; w: E/ h1 t5 l9 \) u2 Tassign axr1 = axr0;
4 C! [- h5 }( M2 Y$ q( ?7 s# u2 m# L( h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 d$ N9 p, {0 c H
static void McASPI2SConfigure(void)+ B/ }4 F h# ?- X) q
{
" ^& F4 q* K2 g# S0 f8 `$ rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ {% p, G! f( o) C; BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% l6 J Y# r9 a, W7 x2 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 x6 ]3 a: y- K4 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ A3 ^ f) S3 k" Z- u8 }% WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 q# C P# F$ ^* z! w% b
MCASP_RX_MODE_DMA);
' C' j% ~* T3 M7 W5 K2 \4 V3 lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ d7 N1 r- Z0 O4 \" r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 Q2 H" h* x' w f$ f* G+ o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " M& V0 g8 R3 ]( |+ z9 ?' t. y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; U4 w |: B! e: g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 R$ |( e( l1 a* ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// V3 g4 J5 P, p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 f# i1 w) J% G9 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
s' s% j4 m @2 D+ G/ P H; r7 NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 l$ G y# E% b6 [% E$ f+ P" r
0x00, 0xFF); /* configure the clock for transmitter */
C! K. F+ M {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# b1 E. M! G' yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . o. E* Y8 L- V$ D/ ?% D) _( N# w2 M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 H1 d! L8 u% L( U" ]0x00, 0xFF);
. A( m/ C3 g1 I- r+ W7 Z9 V( ?5 i$ U) a! W9 L! o6 U3 a2 I0 L
/* Enable synchronization of RX and TX sections */ 5 S6 `( f4 R( r$ J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 X2 G7 \( |( W8 o4 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 X! o* N8 S: v0 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 t) U- I" f4 }4 d/ c4 r+ u9 a
** Set the serializers, Currently only one serializer is set as
' g6 a) |9 G% d** transmitter and one serializer as receiver.
7 ?. Y" B( w ?) A3 J' o8 p- k5 j*/8 }! ]* L- O' `9 l/ x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 j2 A' ^* H4 C0 s; oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) {- v5 r4 n4 T( K0 Q" h- r3 }
** Configure the McASP pins 0 J" G; |$ P. A2 k. m, V3 V, \
** Input - Frame Sync, Clock and Serializer Rx
5 u2 J2 [, F( z" W+ \** Output - Serializer Tx is connected to the input of the codec ! b7 Y0 [$ C0 x6 ?/ S
*/- _( i/ \1 l. @9 Z7 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, ~8 [' N5 ~) q; q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, c/ O8 r) D1 N8 l$ T3 m6 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ X: a0 `1 D. s$ V
| MCASP_PIN_ACLKX
: r* W! c. |: M& p| MCASP_PIN_AHCLKX- J: a2 b# f" c4 m1 F5 H6 r1 N t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ v6 k( b& ?; l) Q6 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# [& m) @, r" Z* G1 p; V* J| MCASP_TX_CLKFAIL " x9 y7 q7 K" i/ A
| MCASP_TX_SYNCERROR0 _4 B" U0 V* |: Z! w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 D. `' I8 D l8 v| MCASP_RX_CLKFAIL
( F9 K( w: G$ T. N| MCASP_RX_SYNCERROR ; z- Q$ P% a) W$ c( e4 h
| MCASP_RX_OVERRUN);" m- E) n$ z o) P# w
} static void I2SDataTxRxActivate(void)
6 y7 o) a, l& v% j2 u' n8 B1 s{
, M3 W5 M" q& n# _5 l; A0 z$ i# V/* Start the clocks */& X. N7 A) d: K$ d5 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- L1 i+ ^3 [# T% p# r1 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: F1 P. ?) [% i7 J" s7 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 R# `% z# v B, ]' ~EDMA3_TRIG_MODE_EVENT);$ s; n! c7 q2 G! v k2 h9 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 m8 q4 Y, `( U* Y5 ~* E, j4 U) IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# T8 @% y+ }- p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& P" y8 A! Z/ p9 {. Q& F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 U C) _) M2 ]3 s9 k2 F& t: V& }; jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// J4 d8 J+ |9 `: {+ k4 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 v1 D! L2 H* vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* [( R) b7 r7 E, D, }/ E} & C/ A3 e3 G, L. C) l8 s; H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 A+ [# h( |. P$ E
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