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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: W3 a! I d- Y8 L2 f* ]input mcasp_ahclkx,
9 Q( y1 A. p: r4 l; n, C% b _input mcasp_aclkx,
# y2 Y. O# Y- K1 ninput axr0,
& B$ }3 V+ D* P: Y) g; d" o% o3 U: W2 w( l: i ] \) h
output mcasp_afsr," O5 d6 S6 _3 z5 r5 Z/ w# `9 ?
output mcasp_ahclkr,2 R$ n4 q; u% F1 u
output mcasp_aclkr,6 v% o" g/ n- V
output axr1,, \4 S6 I8 \; [( M$ e9 ^# X
assign mcasp_afsr = mcasp_afsx;
3 x# `) D( t7 F: z, Wassign mcasp_aclkr = mcasp_aclkx;+ W& `6 E' ~; [9 B$ u3 O
assign mcasp_ahclkr = mcasp_ahclkx;' |. w0 \ S* X8 P
assign axr1 = axr0; 8 u3 b; C, h0 }0 C* R+ X' }7 e9 a
: [9 ^. Z) k3 g9 [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 Q; X& y! u8 H& L) b7 D9 ^/ B4 m
static void McASPI2SConfigure(void)
% X9 x1 O2 E9 d+ l5 K% E J{
" N* a" i3 r) O, H$ EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ O- ?* z% z: c& B; m. l* l) Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 { `) U% J( P) J! f. w$ e; GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 d7 W6 ~& [! K* t8 h n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ ~0 `/ g6 l7 K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, m& ~0 _" D: Z5 I- N7 s' W9 `9 s( O
MCASP_RX_MODE_DMA);# |7 Z5 i4 a1 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 g/ R, ]4 W+ F6 r9 Y/ N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# S" ]" E/ X: e; F( E ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& Z0 {" E, K( N, q8 @: [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 f- w! a% i& f+ \+ o6 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ l# T t% e* S9 L# T* z4 |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 Q8 _$ Y% f) O$ X( I: |$ U7 M9 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 a! y$ S! J' E6 S4 M0 F6 e. U& F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' z7 a2 X( x) n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ p. Z9 ?9 U; G3 ~: u5 f8 ~
0x00, 0xFF); /* configure the clock for transmitter */
3 n: b& ]( z- \& d, @2 R% _4 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 K9 e2 \4 D; H0 p n W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 T. @0 x. j/ H+ K0 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. t/ J% X# b/ s" [3 Q/ b1 _9 w+ H
0x00, 0xFF);
/ p+ m( R" k& {* o+ `$ j' o( k; } A3 x! b" W( D1 l
/* Enable synchronization of RX and TX sections */ 6 {- [" p. `' ?* G' A- [' C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ p* F: j0 [! K4 w' U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* V1 S$ J$ S/ S* A5 c- _/ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 e4 v* a. B% e8 u* M# j** Set the serializers, Currently only one serializer is set as
0 w3 I- d% C6 i' |8 |/ m' b** transmitter and one serializer as receiver.
3 m+ H- j1 ?1 U*/
% p7 E( L. L D. PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 h' w# P: t T: ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 X8 i z- z3 a4 p/ C** Configure the McASP pins , h% g5 @. c( X0 P6 o* H
** Input - Frame Sync, Clock and Serializer Rx# f% N( k2 x* t6 k
** Output - Serializer Tx is connected to the input of the codec ; h5 \5 h7 Z! O0 a
*/8 r+ `4 t! P0 r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 c5 I9 y: G0 B/ r# dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) Q6 A$ M0 ~ N1 `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ R, m( D+ D) m" F| MCASP_PIN_ACLKX" W2 h" @4 |+ J$ [/ K. p' {
| MCASP_PIN_AHCLKX
* \/ \+ p3 F7 M% V& u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 l. c' y1 o& }6 l; D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* b- T7 N% G" D% F/ d" c| MCASP_TX_CLKFAIL 1 J. \! k' R8 K" I2 g1 ^
| MCASP_TX_SYNCERROR
* G6 f0 J, G4 W1 || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; W; {2 S' s! e0 v| MCASP_RX_CLKFAIL9 U8 c; j( q! Z7 O
| MCASP_RX_SYNCERROR * u) X" C! }% L/ _. A6 u2 k' T
| MCASP_RX_OVERRUN);
\' _1 Q$ \/ z5 [9 s/ m1 U0 N} static void I2SDataTxRxActivate(void)+ c4 ]+ D+ h# Y' [' {5 |
{
t& s+ A; O. D, F: S. o# W/* Start the clocks */
/ |# O2 T w' \2 c' \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; Y/ e* ?0 x$ ?/ AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. j* E" v7 g5 O/ c0 l% n U3 \' V; aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% ^9 a: ] B9 MEDMA3_TRIG_MODE_EVENT); e; N0 y4 P* d2 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / R- \5 S8 {, J h R1 ~* m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 p }" y. \9 g! R" C) K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 S9 i. L: M+ p0 L0 \% h0 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
I4 h1 x6 D" N2 a/ m7 e) Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ ^1 ~( B' ^; C4 Z& r! D: bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); N) E6 C8 u; G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" {- }7 w6 ?4 ~& Q( H1 J
} * ?/ i m/ O7 E$ s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ V8 i" x4 R$ y5 ]
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