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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 }' J2 ^- t/ a+ oinput mcasp_ahclkx,* Q T$ T+ G: N7 b9 L( ~% j
input mcasp_aclkx,: {& C6 o6 d' P* D
input axr0,- W! k5 Y& `8 x5 a9 H7 q, \& ^
+ `1 f. j" |5 n2 ]" n- H9 O
output mcasp_afsr,
3 P2 |- \# S3 M& C9 x& R, xoutput mcasp_ahclkr,5 F5 w! V# |/ m6 D: s/ D
output mcasp_aclkr,
: B0 Y7 ~( i& c! K) d. uoutput axr1,
) f* x5 t3 @ n' Z assign mcasp_afsr = mcasp_afsx;
7 H1 `: S& a+ u. F' fassign mcasp_aclkr = mcasp_aclkx;
3 r) G) a; D9 Qassign mcasp_ahclkr = mcasp_ahclkx;
1 G- |; P9 V" a3 massign axr1 = axr0; ! M+ w) Q, S5 {
3 e' k `( _) g" ?$ j6 \) S6 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 t7 L" p0 ]' ]static void McASPI2SConfigure(void)
& c: N7 ~7 Z) m* L3 I# X0 [{* G* e3 u+ f* }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" y3 c! I0 l$ L4 m+ H# {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. n+ h* @, k, u j1 K, u+ E; B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 [6 G J& e5 d2 c: l( X0 W- ^4 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- p! ]! `+ U! Q; K3 U* `" f3 c- A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: V) d9 n) Q- }3 _! U- W3 G
MCASP_RX_MODE_DMA);
% G5 p# j2 ~4 B$ c' N# cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 M! s& N; b; J6 g9 R1 e9 A MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 V: _% N" g- YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' f% w$ ]6 @" R9 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; V, w4 j: n7 T. Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + Z# Q7 W. Z- r5 C+ Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- f; R' b% e0 ?' d; }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) M! J" d. l* P1 C0 |: f" h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 a1 }% ]( W8 n/ G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 I# }! S9 C* x! I4 z, c0x00, 0xFF); /* configure the clock for transmitter */
+ j$ a5 }) w: B. {1 O$ SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% \; T, n0 }/ u: K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; q% R; O) U5 K2 GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 A; |; c" j( h( U9 b# Z0x00, 0xFF);
) Y6 O' s0 }* b3 c$ V) b; _5 P9 y& u/ W. x8 g+ ^( G* A
/* Enable synchronization of RX and TX sections */ 7 Q" }( `) T1 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( V, K! H5 l6 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ x! a e. ^/ ~4 G5 L# n( oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 b, Q! A) P) l S+ h' Y
** Set the serializers, Currently only one serializer is set as
8 s2 L( V2 d( W, S! u9 q** transmitter and one serializer as receiver.$ m+ g- T0 O, \% S9 V! ~
*/; t" V2 H6 E7 \4 R6 s+ V6 m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ t J0 l/ P5 V0 _2 C K! m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 K9 C& a" B% J** Configure the McASP pins
4 u7 O, f, \* ]$ s** Input - Frame Sync, Clock and Serializer Rx
; Z7 J8 S7 c `0 S% N** Output - Serializer Tx is connected to the input of the codec 1 f9 N+ D7 M, F, x3 B4 v
*/, i$ B2 e! T6 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, ^! Z: `, L x( ^" XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ }$ S9 {: ~3 x3 F7 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ y$ R/ U: V# R( M$ `, B# a
| MCASP_PIN_ACLKX
H S# s6 Q. ^: a/ l| MCASP_PIN_AHCLKX
1 k: d4 O8 `5 j/ \2 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 T4 X% _0 N6 s+ t$ [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 L9 |# m- Y2 o( d1 D| MCASP_TX_CLKFAIL 3 T3 S& J' \7 P+ |6 M
| MCASP_TX_SYNCERROR) i# H5 ~5 E+ Y& F0 {/ w6 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 i- \" s# n8 y7 d$ e) A- y) A, z
| MCASP_RX_CLKFAIL8 Z0 i9 _! Q9 b: s5 |* ?
| MCASP_RX_SYNCERROR 2 q! R6 R: M- f1 u7 o( D+ h3 s
| MCASP_RX_OVERRUN);
4 `( ^ d0 s. [9 `} static void I2SDataTxRxActivate(void)" Y7 R- b! F" `. j+ }" ^- k3 x* L
{
. f( s$ ~8 P' O. |/* Start the clocks */8 K1 O& T8 K! a0 N ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 P, }0 s/ d' R, \! e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ i( n) j6 d, w5 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) N' V( c7 |9 h
EDMA3_TRIG_MODE_EVENT);
# g4 X9 O# E6 E% pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * ^5 a0 a( a1 ~/ a/ D4 s1 A1 y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; ~& l- |" Q. Z- K3 B, RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* }3 e4 g# T! T" A7 K* i0 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! X* T1 Z; B* E! N: C1 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ Q1 U* g/ p. u) ~0 H* BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, b e7 f% i4 N4 S* ^1 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 D6 `! T( w8 l/ C0 M
} & u$ V3 l1 E! h3 g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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