|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% ?3 g% J" F: ^7 ~- N9 k# Z, w" _
input mcasp_ahclkx,* v, ]& Z8 U G' x5 G
input mcasp_aclkx,
% J9 k" {! O! ]; z" x# Oinput axr0,% b( U& p6 ^8 E7 {5 p0 l e( W
$ E( C# e. P* z) k/ f% R( Q# o2 y
output mcasp_afsr,
4 u" W; l2 M" {2 M: r3 boutput mcasp_ahclkr,8 c% M* T6 j+ _
output mcasp_aclkr,
% P; L2 Q4 |9 o: poutput axr1,& V* s2 C7 m( D0 q( F3 l
assign mcasp_afsr = mcasp_afsx;1 C. S1 j& M& ~+ s9 ~/ s) F5 F
assign mcasp_aclkr = mcasp_aclkx;" o9 [ T. }' Y5 H+ ^7 m7 |6 ?6 q4 J
assign mcasp_ahclkr = mcasp_ahclkx;, R4 i3 F' \# L
assign axr1 = axr0; 7 G0 `% F# j" |4 Y
7 d7 n6 R t- h& H* [1 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ l8 F$ r/ Q4 g. c! }- Astatic void McASPI2SConfigure(void)
( o" k0 s9 o: `* O% A! r% d3 g! ~' g! a1 q{7 |% U$ V2 k' m# [: M5 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) C9 R1 X T# N6 ]( aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 [9 M! h. m6 h7 e4 M; k: lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, Q$ R2 Y0 v V7 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 N, T, Q# [" N3 _: n8 F: F9 D+ K# \' B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 A% p8 f" ]% H* n" Y- B/ CMCASP_RX_MODE_DMA);
- ^5 p& A" c; Z1 T$ F9 H: KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 u/ O% l) R$ T; ~( j/ |: PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) q, q$ T0 q& c- p) F2 c5 ?1 N0 d$ eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 ^% n4 F: K8 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 h4 e' R5 a# a! ~, j8 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; N2 Z; m% o8 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" |; `/ M- {$ P% N% G! D# JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 v, m/ h0 o' G; a6 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! Y3 n2 R' ^$ @1 R5 I3 H3 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! r! R# Z0 @( M1 h; ~* b
0x00, 0xFF); /* configure the clock for transmitter */
* z/ l* }6 C' K4 n6 ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- ~' m4 v1 x0 e" g) H: q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : R3 d W3 o8 D1 K& X- Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) j6 l9 W& [1 r7 R$ |2 |0x00, 0xFF);+ }7 v m5 L' S/ z
! D+ p/ T! C' a0 _( l; @* f2 Q, `/* Enable synchronization of RX and TX sections */
- n; ?5 h- I# `6 c( s S) DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 h/ L" C& f& C6 t8 m" p, L# uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 p& f9 S: G3 v1 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- _5 n2 ~' Q; ?! y W1 x! X7 i ~** Set the serializers, Currently only one serializer is set as
9 K4 W( H' L1 b& f( q** transmitter and one serializer as receiver.
: m @9 n3 T5 G' a' d; q( `0 @7 k' q*/+ l8 F8 G" X" m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- y* }4 v t) j4 z+ a2 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 [1 v% P1 T% D( H** Configure the McASP pins
& k- I+ ? X# w8 t** Input - Frame Sync, Clock and Serializer Rx
8 t k# F! l1 j8 V. f9 b** Output - Serializer Tx is connected to the input of the codec
2 ~* b o0 Z Q# Q. v3 @*// ~; A( [7 `1 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! |1 C) C/ Z, P1 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# a8 @0 w/ S# F6 J( KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) l: F: P5 l L| MCASP_PIN_ACLKX# w, s" I. @6 c
| MCASP_PIN_AHCLKX
+ v- B9 G4 Q& @* \( q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% R5 l% o4 S0 G3 L: s! C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 G$ l' a8 y$ h: G$ R" }
| MCASP_TX_CLKFAIL
' u5 V( K& F; N| MCASP_TX_SYNCERROR
6 O3 Z2 P0 j" v2 b4 M) `/ ], c0 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 A9 r# Z8 S# @4 x& l' _; C| MCASP_RX_CLKFAIL% ]$ a, j# _7 d2 _$ g9 e
| MCASP_RX_SYNCERROR
' F% {7 G2 P/ A8 |' u| MCASP_RX_OVERRUN);
( B, v& \+ \5 W/ z} static void I2SDataTxRxActivate(void)
0 F+ a# Y3 h/ k{/ i9 F2 {) W& b8 n& \
/* Start the clocks */) q+ j5 D6 F) V( O. w# Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 ?% M! o! c( M7 X$ y+ X; C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& _ Y" J. l. r0 q6 _- N }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ L# a$ Z. ]! D9 L
EDMA3_TRIG_MODE_EVENT);7 I9 y L! a$ s- @, j w8 s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 v; k2 Z+ ~- }. @- z1 {' o8 l) ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, ?, ^# H; U3 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 s5 X- j; K2 ?9 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 ~& D/ J* ?0 W' t4 ]( G; y& P0 l% ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ E, w. e* d7 f- h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' E: y- K- L4 I2 }5 ^2 ?- ?$ ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% F8 U( Y8 H+ v* ~: I8 `* X( K}
) \" O5 R8 `) i8 ?. a: Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # f; ^. G2 O0 |0 o! Y/ V
|