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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ e; S4 J! J' W0 J3 n) f! [
input mcasp_ahclkx,! U4 A6 J; c; d- T
input mcasp_aclkx," F5 W6 |6 y, n8 }- M) X7 Z, s
input axr0,
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8 G/ n( |' u. c" j& ?) qoutput mcasp_afsr,
6 `# [, S. m/ E5 K5 j0 F; loutput mcasp_ahclkr,
0 [8 x. {+ Y: Moutput mcasp_aclkr,
9 [! _# |5 ~# h! Eoutput axr1,6 r3 s1 z7 s# I% U) g7 k% T: c
assign mcasp_afsr = mcasp_afsx;% Z2 m. N5 K' G. [* j9 y6 v, p
assign mcasp_aclkr = mcasp_aclkx;
. r4 T8 M8 I2 D' f- U/ g& ^assign mcasp_ahclkr = mcasp_ahclkx;
- O4 b$ U2 L0 {% D2 rassign axr1 = axr0;
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9 Y) e$ f, M7 Y8 b: I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 H( b% ~* b `: e0 l: i& U/ O& pstatic void McASPI2SConfigure(void)
s, t8 ]! q' e7 `" k{7 y; f% Z2 d/ q: W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ ~! f) t/ @5 F( P1 G' Z" ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 O; p; q3 p1 ^+ j1 z/ yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 z, Q, b8 f/ V; L" Z+ V, x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ C5 A2 e6 V( m5 j0 T& r" \* nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, J* }5 B, |7 S& @2 H- F; JMCASP_RX_MODE_DMA);
& r$ J4 p& n1 n6 J; G' D8 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 C7 J# B& u9 p3 T O. _7 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; E9 I: k. Z( O: ~( \% A1 e4 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / K0 w) h; x4 U( F) [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# @- {" n9 l; ]" T; A3 q% H9 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# b$ m2 ~# E7 f7 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 f) B* S: I7 Z% KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 l6 g! H, X9 i8 g8 p: j: F: f4 OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 n, b. S# o$ t% q( m8 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' G+ l: `; B! _* ]; r/ t0x00, 0xFF); /* configure the clock for transmitter */6 b* \7 V; M3 l4 g( y: B: C" F* E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ W/ J: U/ d! g2 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: u; f1 E% N7 i6 O5 `; x0 TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, ^: }2 x/ G; P; T0 _4 G
0x00, 0xFF);" q% f$ [* j3 w( p# D
9 b& P# u4 S0 ?# m, W5 p/* Enable synchronization of RX and TX sections */ 8 n4 ?8 A0 d1 p$ l, ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& P) v0 d9 O; nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ I/ }. k7 B4 w( PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 N9 r# K) T" P7 w3 N/ d( @% z
** Set the serializers, Currently only one serializer is set as
2 B+ ]. @0 ^! O/ y) a$ T** transmitter and one serializer as receiver.& p1 }) P6 U8 k8 |3 K% H F- b; A
*/
' v) y6 L5 C, ]" wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# s) \: [- G: ~* N" dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ c7 z. ^* x7 I7 a3 w. y
** Configure the McASP pins
" v( S7 K7 H& x# ~4 M8 L: Z0 J8 J** Input - Frame Sync, Clock and Serializer Rx! } H4 a, I4 j, C; e3 W# {; G
** Output - Serializer Tx is connected to the input of the codec $ S u; R! g6 E3 f
*/
. v" J# ^1 l( E( V4 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" \. b" p }' y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 b8 ]. H2 n. Z8 m3 a# dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- T) u( X6 d4 n- u E' X| MCASP_PIN_ACLKX2 s9 I/ Q: d% y, A. l) o$ {
| MCASP_PIN_AHCLKX: V% _7 ` Z: M& a6 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; [/ j- ?* f1 b$ Z# S8 _) p# c4 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; l) o, i8 \; q, U
| MCASP_TX_CLKFAIL 1 \. y/ ]: Q" X- R1 e
| MCASP_TX_SYNCERROR
) s1 W% U. i! k2 Q8 G4 N4 e) v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + G/ W7 x2 c, H5 ~" Z% j; ~
| MCASP_RX_CLKFAIL$ e# d) U3 J& {5 C# u7 z
| MCASP_RX_SYNCERROR
2 U, |4 F/ [; i* q! U1 ?: U| MCASP_RX_OVERRUN);
1 ~% q# M" s/ {, s f9 {1 w} static void I2SDataTxRxActivate(void)- V1 f9 w) U. P& z7 _
{1 A5 d' B8 T* n# d
/* Start the clocks */
~8 k, y- y$ J$ w* wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# `+ {) i7 U. MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 d9 V- E3 v$ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ i3 v5 d7 T+ _& _, Z6 t. N8 k
EDMA3_TRIG_MODE_EVENT);
% f2 ~" u+ j# W$ \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 [$ c, G& M% q* r/ @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: j+ P) o, w% K7 E" ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 o+ h9 _% |9 x3 L9 Z, q2 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. f0 y7 w* m, m% P1 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% g# `1 f( H4 v4 ]) IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 ^0 B( |% P$ J2 M- H* jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 g" f" j% _; I( ^1 A( s2 o0 @2 y# @} : }; @. J; g+ z, J( X2 Q% r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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