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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 x7 K$ K8 }5 [0 Y# z
input mcasp_ahclkx,, g4 S' g( V- ^6 H4 i
input mcasp_aclkx,
d- S4 ?0 F2 _$ g' o! Ginput axr0,7 r" C0 U* M! [1 Y6 v8 S. Z n
, N0 ]1 i+ S& B' Qoutput mcasp_afsr,# m, {! r, N! \6 A V0 r) Z: H
output mcasp_ahclkr,! u$ Z- G1 ` Z4 ]: p4 l/ l7 o2 [
output mcasp_aclkr,% ?1 N( q2 h/ ]: T
output axr1,' V$ @: C' P# E
assign mcasp_afsr = mcasp_afsx;
! A" Z3 N* U) \" S* j" I O' |assign mcasp_aclkr = mcasp_aclkx;7 h7 B# [; ?3 T9 s
assign mcasp_ahclkr = mcasp_ahclkx;! F9 @0 ~/ m) ^! T4 {. b
assign axr1 = axr0;
; j. R4 R4 g. W: W( b" d
2 k1 H' B7 @* s4 Y. u6 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ b% f4 p6 y% n: q: xstatic void McASPI2SConfigure(void)9 L) b+ `# V& m
{) e" x$ c0 S* g$ o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 Y$ `+ V% q) C+ cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 _; J- B' {5 D! m9 @0 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ b8 A4 s* R, l0 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 e6 j& E2 D4 O) S- ?$ [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; P# ~5 }7 T: g; p* E j( p
MCASP_RX_MODE_DMA);
0 B& v& W. K" n& h- E; ^; SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- s# E' M3 \6 B: c, o( x6 u" ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
_4 x6 w; U- [( R$ lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 J" r# T/ ]" U2 }, u }& DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' o7 r" t! x) f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ ~& D; q( O" F- T+ mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 J D# X( ]4 s1 p2 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); s4 c! b- g' L. h5 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ s1 ~9 \: e- X- d- m" TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, F) J' Z2 f' v/ F6 C# ?, m- D8 t
0x00, 0xFF); /* configure the clock for transmitter */
; ^# \: v& @; Q; Q4 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! p: [* q) Z9 u* H- z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' l$ U7 W; `1 J& U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 _" r$ k- C: ~0 B0x00, 0xFF);
' }5 ^3 b q' k; o$ X
1 q# q" {& M' |7 Q+ U% t/* Enable synchronization of RX and TX sections */ 3 _: x" T0 v9 L: x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! i7 [7 C8 C+ |2 j' n9 Y: G$ z! `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 q, A/ O6 y; d3 g1 r6 V, HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 X; P6 h) q# [+ M; t
** Set the serializers, Currently only one serializer is set as
) V+ x! X( O: O. ?2 Z** transmitter and one serializer as receiver.
4 c6 f/ q! q$ T5 G*/2 G3 q$ e! g7 r" E* F% Q7 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 e" h+ I5 j5 k- x% O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# x) n3 i" L1 M# C5 Y6 J! ~: Y
** Configure the McASP pins
- w) b, k, K! d) D8 }** Input - Frame Sync, Clock and Serializer Rx2 K; i8 }: i8 F6 x
** Output - Serializer Tx is connected to the input of the codec : X. U4 `9 g( m/ W, \7 M
*/
3 A! h7 M# O7 s1 C; fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 p. @4 u1 F1 e% y) f6 P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& S3 i! ?* l; B6 O. U6 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
]6 B* m, W9 l/ D/ O: p0 `& \| MCASP_PIN_ACLKX
( B* _' B. x' G2 q# G| MCASP_PIN_AHCLKX& x0 O( b# a& [! x0 y. g ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// g5 R1 z5 l) @5 D' }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 W" t$ g ?, ~3 _0 t5 u" V1 w( I2 }5 e
| MCASP_TX_CLKFAIL * a1 S+ a& s; E6 i$ L" t
| MCASP_TX_SYNCERROR! K5 F1 a& c5 j. u0 f7 g: t! i2 L0 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 W" L' t/ u+ X. |$ u6 a9 M0 {! v
| MCASP_RX_CLKFAIL
+ V- p) l9 n+ {3 |" y| MCASP_RX_SYNCERROR 3 o' Q; x0 v3 [% z3 ?
| MCASP_RX_OVERRUN);- Q' e7 ?, J* _- d1 q& ?
} static void I2SDataTxRxActivate(void)% `5 Z: P3 h1 r1 Z. _
{
( V7 @( `$ R6 U( I/* Start the clocks */
* b9 ]# `1 O! \* @3 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 S$ ^$ Y& D$ M, h+ T/ x" t" O! hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// \$ A' H' v4 Y! o6 Q) f0 W: L+ s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 u3 I, q3 Z: D0 q& R0 n3 nEDMA3_TRIG_MODE_EVENT);4 h0 ]+ j$ W! e4 a/ L; M/ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 ?- h+ k+ [* l4 k% h% {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) A. D- t* j3 p- d! M CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- j4 L8 C* C& S2 s7 k/ iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; H7 O2 P' [+ u) Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ h1 Q1 y/ e9 j: u8 u; U% n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 \( q! M6 g8 {4 D- p ]6 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" R/ `$ |7 K9 U/ A9 B} 0 T" V# F6 ]( l) Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : K6 M6 i! Y$ z6 c# S. W
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