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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! ?$ H& |3 A2 {. _% Dinput mcasp_ahclkx,4 t. o8 y# ?, L8 {% k
input mcasp_aclkx,
0 V, ~0 ~; ?" y5 U4 ] G% ginput axr0,
2 j& k! N o+ \7 D9 D
9 z3 w8 h( I: T! c7 y1 V2 ooutput mcasp_afsr,
1 Q8 ]/ K1 p3 f6 _: I; D2 Xoutput mcasp_ahclkr,
/ T- t5 F; z" |* t2 ]output mcasp_aclkr,
* a( _& l& }. |% doutput axr1,' y9 f& ]( P4 N% p l9 }( V+ I
assign mcasp_afsr = mcasp_afsx;. j7 Q4 v& o; z
assign mcasp_aclkr = mcasp_aclkx;
1 k [& I0 _! n1 p6 tassign mcasp_ahclkr = mcasp_ahclkx; u0 z1 d' }5 x4 V" V
assign axr1 = axr0;
& Z( ~: T$ j% w8 r+ |% k) [+ W- T2 H' C+ o. S5 \8 e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
P2 A) v: n/ H' E! r0 ]/ V' ostatic void McASPI2SConfigure(void)/ V9 V& X) b# s2 S
{( v& y' x: Z* P6 G; q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 C) L. L F7 T0 S$ X, n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 o: F0 j' ?' _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# Z& X) e x( M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. P! g$ B% r, B$ m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ?' S/ E5 u0 q2 l' ~$ G, U( p3 w( a
MCASP_RX_MODE_DMA);) t6 c; n! I- w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) D1 ~$ H( I1 f& @1 |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 t1 n: X/ K. \; X7 T9 Z: X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 a! `8 v0 N7 s: n7 [6 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) c. U4 R% z) [( R: ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 k2 A9 Y) I* u- O/ T% \: O; G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* v8 i& E7 ?% L4 b9 X4 |0 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 i9 P j) s- N9 P4 O( f; D5 @4 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' [! q2 j8 Q% D- E* F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 R+ I. h5 i4 z. L9 v: u# V0x00, 0xFF); /* configure the clock for transmitter */5 b2 H, G: F( Y# W% q! W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 G: s T* A6 O+ e: F( @ hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- G7 P% L. }# ^$ r5 d+ w2 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- |3 N9 w# o1 a4 A2 E$ d% n
0x00, 0xFF);
. l. x" L. ^* a- W+ e/ ?% {. O) `% D& l# @% j( u* V
/* Enable synchronization of RX and TX sections */
, y7 V: W0 h, D# z" d6 Y9 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 y, R$ g+ g3 [8 B( h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ B8 r/ |& D2 @$ ?$ l. TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 ~' ^/ {+ V8 h& I** Set the serializers, Currently only one serializer is set as
- W- j- C |1 w# a** transmitter and one serializer as receiver.! x2 J1 h d6 D& w0 W t; M% Q. C
*// G& ` J' J7 V1 x- S# C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 ?0 @. s8 @) `. x4 Y5 P8 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( f' c3 z! n7 Y( w% J% v** Configure the McASP pins
7 E: Q9 f/ K2 o p- ~** Input - Frame Sync, Clock and Serializer Rx4 o V: G5 q h# g5 }
** Output - Serializer Tx is connected to the input of the codec
, \3 ^, ]# j$ o. G9 K*/
* `' R9 p2 |' T& S' mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 X2 v0 h! L W8 Z4 ^' m. t6 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
M& ^9 _; E M4 l% g* n4 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! J% I% s9 s6 ~+ e
| MCASP_PIN_ACLKX
1 v( t! e0 x- ?8 y) Y/ n) p| MCASP_PIN_AHCLKX5 d b% x4 m- @# J0 x# _7 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 t# q; Q; R1 e* v* `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / \4 _: c0 m: {% D& ^
| MCASP_TX_CLKFAIL
% t; T$ u9 M+ p# j, l| MCASP_TX_SYNCERROR
* r, d8 Z( d" [4 d- d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 k* {; X* I* [) Y% C" F% \| MCASP_RX_CLKFAIL
1 c' j3 e+ A; ^# _- E' w) Q| MCASP_RX_SYNCERROR
# Q2 @" b; z3 r| MCASP_RX_OVERRUN);
& a' G5 A1 t3 o/ c} static void I2SDataTxRxActivate(void)
: Y) s# H- d+ a/ m5 e{. G# z, |# D$ j
/* Start the clocks */ ]/ d/ f% o& @- X$ \9 P/ I3 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. i' @% |: W7 i& w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 b! {& T. q |. Y8 o) w1 {0 [, U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( X i- G$ M- a8 ^
EDMA3_TRIG_MODE_EVENT);' }; |6 D* n4 G" P \& v3 m+ q& L! }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 t( B' O; T% P. g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- L% D( [0 v# l% x! J( cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) Y% T$ G4 [) n& y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ l6 v! R& X4 Y. W1 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ x0 A2 k3 ~1 {/ X7 c' N4 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
p: e2 {' @2 U+ Y% _! P; i" TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 o/ w* D! { _7 D: w* ~
} , u B# |6 u p F$ N- r V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 C, U, U0 j1 V( }; E7 D5 q
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