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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, H4 @: X" j& o3 v
input mcasp_ahclkx,
! T2 `1 P# V6 e. qinput mcasp_aclkx,
) A0 ?/ N7 U: s; Iinput axr0,2 V8 ~+ y' |$ O+ U; P( n3 `% K; ^4 R8 A
E4 C" o9 e: ?4 moutput mcasp_afsr,* |* W9 v0 i( C6 K, [
output mcasp_ahclkr,/ a* U0 r$ d! i! r r* N0 K4 y
output mcasp_aclkr,* r" m m& m$ d' [* y
output axr1,
+ k$ Y: m' U9 U# E1 o/ s P @ assign mcasp_afsr = mcasp_afsx;
7 f7 T" W! L9 Q1 ~4 Bassign mcasp_aclkr = mcasp_aclkx;
8 |& y0 V1 i2 Cassign mcasp_ahclkr = mcasp_ahclkx;
. ]2 I" j! F$ f8 fassign axr1 = axr0;
& c3 v# b. w2 y
) _% ?5 I' F$ Y' k& _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) |3 |& v- E' b% |# L( z
static void McASPI2SConfigure(void)
( ]9 q8 \1 }( f2 X. ~{
1 A; b& H3 ?& }9 |. U' |' b6 \5 S! K, JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* x5 _) {; H5 L% n- p+ {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
\5 z; H6 g& ?- N- s T7 Y- \7 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& w2 W6 L# u7 Z# @" o. FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 P4 }; z8 b* M2 m& o& G$ R5 l2 j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' B$ q9 S0 o X g$ ~& u& _/ T$ p
MCASP_RX_MODE_DMA);
8 q8 l V C# ]: R: |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ b5 y' W9 a" J& D B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 Y6 P9 v; \; V0 Q* [; Z% u( d9 \) k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 y% ~ n$ O& ?) h; p7 H( U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 Y" e. M" g# f- e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ i% P0 M( O6 Q. hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" Z: t( p! l+ j& EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 W3 L/ A+ Q, o* Y% |( o( \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: M: z+ _$ P( M- sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" u# Y: {5 I# C$ D' B: k0x00, 0xFF); /* configure the clock for transmitter */0 _- X9 {" w; x0 Y+ W& N% X% M" ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); j8 P0 w% J% { X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , t/ A8 f" {$ P* [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& H G5 k8 W9 \5 i+ u- E; A! r9 f
0x00, 0xFF);
: c. p& B+ K" Q* H. w6 @
7 v2 \+ P+ M2 z: V- J; J4 W/* Enable synchronization of RX and TX sections */ 1 ~. P& J8 u; a- ^$ g# f1 ^, e/ P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( ]9 ^7 ]5 g" Q+ I0 B4 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 U7 t3 r1 G6 l# r7 p/ KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 f0 k- a! J1 R$ }, K3 n6 U
** Set the serializers, Currently only one serializer is set as
+ K* |6 J2 C! s* P** transmitter and one serializer as receiver.
: ]9 f* j. Q; g1 @ |*/: H( E7 G6 K* U y" p) p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- w# ]2 v* c) c& |$ a; B2 s6 M; D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. r- l' m" l$ B2 I* e% U4 U+ c( A) k0 x
** Configure the McASP pins ) o2 J5 u2 y8 ^# ]4 c0 S
** Input - Frame Sync, Clock and Serializer Rx
1 a9 c. }! B, ^; L* u% c' R* \** Output - Serializer Tx is connected to the input of the codec
1 s, O' Q% T4 H3 ]7 Q*/2 Y: `( b* {1 y0 m6 C E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: ~2 w- r- y; M/ d+ P+ t( q$ y0 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 k$ @" O# [+ ~* H1 u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* W! }7 t/ V h0 t& h. g% @| MCASP_PIN_ACLKX* h" y3 M- ^6 M# \0 B8 O
| MCASP_PIN_AHCLKX
+ s2 {- u, t& l$ E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: Y5 i* ?4 o$ h' v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 ?+ w' t, T( `6 }& K6 C| MCASP_TX_CLKFAIL
7 ?* `. Y+ H* t| MCASP_TX_SYNCERROR
5 ?6 ]1 m* [! j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 P) C; s$ b1 }2 P+ H3 [$ D6 y
| MCASP_RX_CLKFAIL5 A; N+ p# O+ c) A# D* U
| MCASP_RX_SYNCERROR
: g* b: H' p+ n- x+ z7 q| MCASP_RX_OVERRUN);
' O; g, N# a1 J# _} static void I2SDataTxRxActivate(void): }& H! q' Q: o( D' N- K! w' Q
{2 Y; S- o/ c# G' y; z
/* Start the clocks */# M! ~9 U4 J" x# ^# [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ J9 f8 ]0 ]. V) h* n3 @3 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 U& h: g, c0 L6 U4 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 n$ n A2 W5 f& H
EDMA3_TRIG_MODE_EVENT);+ U# b0 a9 r& t% ^' @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 a# Q, |! B- W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% t: p7 ~+ b( V/ W1 w0 m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); h2 W7 w! V) Q! ~" q {0 s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
o- n2 D7 c* J$ r1 W2 K @1 ^3 t: Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: h6 G( }! f1 J1 R0 gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 Z, k+ S0 W+ C" K( f$ k4 t6 k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 q% i3 q+ F5 k! m8 k} 2 ^9 Q! `( V- ]% Y* f8 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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