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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. c/ Y \; A" O" linput mcasp_ahclkx,
5 m) Y( Y4 B3 v/ D9 }! e- k( \9 minput mcasp_aclkx,- j& ^4 \! [- S
input axr0,% [' _7 d5 F5 P& `! H; F9 r' j
p3 Q+ A5 B' z5 L% A
output mcasp_afsr,
$ p+ z3 @0 p8 q! ]0 Ioutput mcasp_ahclkr,2 Z2 G9 Q9 x+ L! u0 J8 R: ^
output mcasp_aclkr,
/ g9 k V- O9 `) a9 Z* }) A+ noutput axr1,2 a7 M! d4 u* c2 I: N
assign mcasp_afsr = mcasp_afsx;
" U" P& V: O) I0 l! l+ B7 m6 @assign mcasp_aclkr = mcasp_aclkx;
0 E( e" h* k) B* d' p; u Z3 |assign mcasp_ahclkr = mcasp_ahclkx;
8 F0 q; H0 W* |! I% `assign axr1 = axr0;
3 ]" {+ r6 a2 y( M1 D# L
3 W* J" n( t6 }9 V" w2 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; ^1 `/ r6 G1 }6 \" R/ A
static void McASPI2SConfigure(void)2 P2 U& D* V7 O, u, m( w8 A9 P) }$ N
{
( Y# k, A. i* oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ \6 D# z% w5 Q6 m, y6 j7 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& m: R- c* m6 Q0 ]: O3 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% ^$ G* C% ^. N% L' mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 ?9 e6 ?+ N/ x. s) V) NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ x# Z5 w& K2 x! b1 U) _6 ~MCASP_RX_MODE_DMA);
) M- U/ P& w7 ?4 H C" BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( \( y+ j- l7 D- m' R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, x4 c/ f3 |* {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 d# y; o: C5 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* N1 v, N! R$ ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 M/ B' V; E7 }1 Z* t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% ?# W5 M4 Y* M! D& ~1 U9 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 e& Q2 \; u" [- u- m+ gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" r3 C% V% g/ _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" [. o% w. |% _. ~6 t0x00, 0xFF); /* configure the clock for transmitter */7 H1 G8 u" B7 \; C+ T* V0 e) M' ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 N2 k4 t- Q! R7 R0 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 F4 ~" R% W, f& s: I) t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: E5 f/ o, X# v1 x8 i0x00, 0xFF);; u3 e/ P) j& F+ u/ n+ G
$ _4 _" q8 B0 g/ l- X5 b, @6 u
/* Enable synchronization of RX and TX sections */
0 o9 H% d$ X2 T& [; G8 R' x% j1 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- _1 ^* |! U- p5 g) u% ^( RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( s7 v: t6 P$ p8 @: J6 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 \$ o! [- V7 u) y3 v2 p
** Set the serializers, Currently only one serializer is set as
& a7 J+ k7 S+ ]# l% b: d6 ]** transmitter and one serializer as receiver.
% I& d/ k5 I! u8 P. l*/% l5 h1 h% N& X; A6 O& P3 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! s0 V; V0 |6 U- `1 m4 z8 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' }5 d, v2 b( H# @) m2 E** Configure the McASP pins / z2 Z0 M+ r. E2 |" B, \* w
** Input - Frame Sync, Clock and Serializer Rx/ s+ R1 q4 X: ]: B
** Output - Serializer Tx is connected to the input of the codec , ]( u4 s! a9 n+ ~4 D
*/
2 q3 y% c, | |9 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% G, c3 I" D/ x9 C" q2 Z4 v5 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 ?! Q) |; p1 J! W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 i g' d( b/ l' [| MCASP_PIN_ACLKX
0 j' i" s9 n8 G2 q/ o8 D {| MCASP_PIN_AHCLKX
: r: [5 m/ v2 @2 B3 ^& j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( M! ?! z3 m5 pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 J P& f" _. Q. F* l( C" H2 W
| MCASP_TX_CLKFAIL 1 s' W: }& Q6 n+ \ f
| MCASP_TX_SYNCERROR2 [ T5 F2 Y5 K$ A; w2 \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR W4 O0 b: s" ]7 r- K9 M9 A& `
| MCASP_RX_CLKFAIL
# e7 ~8 h- u' u0 b: D| MCASP_RX_SYNCERROR & R1 f4 M4 l* m8 @3 ?. k
| MCASP_RX_OVERRUN);
1 q5 O" b5 _( Q; @' {4 ^: \* y} static void I2SDataTxRxActivate(void)
1 V3 x& G& T! c5 |0 }4 f. x{3 ]+ T u; V& D3 M2 G
/* Start the clocks */; ^1 w; E# w; C2 A7 t8 s; \: u I8 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* i1 l" W3 c, |6 x2 R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* q& F! E# r6 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# G" S$ q7 X' }3 z. V
EDMA3_TRIG_MODE_EVENT);
( y8 P! I* J/ Z$ J) XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 D& t. V. o1 ?. E) h% }' yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; W- p4 ~/ d% C# x- TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ A" ]* m7 Y+ z' j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 Y8 L8 j4 H* |0 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ X# X" f8 `. c d+ C9 F* z8 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 k: R0 |! z& w! c; M" HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- L% C2 d# ?' t' u- }- u: b
} 1 k! I. O/ A" W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 p5 S' l7 K0 n/ \( s, X2 K+ C
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