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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* D1 _' ^7 o; o( S) M1 binput mcasp_ahclkx,
z' m1 Q' Z' _/ s2 |6 T) I }7 finput mcasp_aclkx,4 g9 [' F- ^9 \ b# {
input axr0,
( w- d6 ^7 V! i9 n8 i, h- J% H, w" u# q
output mcasp_afsr,
) {/ c" u! R9 M$ f& h1 t/ T& I+ moutput mcasp_ahclkr, ] `! M4 h1 i# K) u. P6 m% Z$ z
output mcasp_aclkr,7 Q# m- C. a2 K+ }. `7 o
output axr1,
8 c0 ]% H Y2 v& H- w0 U assign mcasp_afsr = mcasp_afsx;8 J1 j* j# M |
assign mcasp_aclkr = mcasp_aclkx;
! v( B4 E+ O) \+ a; g4 C! }4 }assign mcasp_ahclkr = mcasp_ahclkx;7 f6 l2 X4 Q* F+ u, H
assign axr1 = axr0; ; }( D N6 K( u/ t# u& X7 Y
- f F9 P! I+ _: S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" t: g) e9 [' Istatic void McASPI2SConfigure(void)+ k1 h# ?7 O& |+ D8 [3 l' |# k' _
{' L+ U6 @1 T+ q! @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ s- N4 P/ D6 w/ \! J: U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 s+ j2 j; J5 H3 x; ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( k' e: H9 b6 W: ?8 N$ N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 Y: ~. J8 E2 f; l8 }- P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ c8 Q. L# k- w; h
MCASP_RX_MODE_DMA);
/ n, W N; ~* k" L& u1 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 V5 h1 ]- f# l* I1 i% [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ C+ `, f+ S u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " T* q' k' B# I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 p) R$ B* G* L/ qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; X. C. X7 q, R' {! IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& t/ w t4 B: v( PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' k6 C5 r/ S- u+ P( {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* t8 ^) }( J# `# rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: j4 j3 H% m0 d, d' c+ `7 r0x00, 0xFF); /* configure the clock for transmitter */
' Q3 j6 q, f& r- U) U. d0 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 |/ |: r. i" P* B' T. f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, `% s# M$ {5 Q+ XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! U. m/ j& V* c
0x00, 0xFF);
0 }; g' V% p& T3 }2 n( D$ h4 ^
; W* ?! g4 h+ h- M, H9 A/* Enable synchronization of RX and TX sections */
4 @) D' F( m4 C5 U, w, P+ DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 X; g7 |; D; u6 o6 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Y! U) g+ ?* Y+ S4 K9 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" |2 x' {. B3 K( l! P& G' E** Set the serializers, Currently only one serializer is set as
+ ~6 l% R) j$ v) R. p** transmitter and one serializer as receiver.- [ f y$ I+ C: u R4 F
*/$ [1 I" Q: u& F8 y# P; c* h/ h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* \- m: g( p s, }; O, S8 [# [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 Y7 M6 @5 c, X' X7 l2 T# a** Configure the McASP pins ' W' _* a; M, c9 p: A- p6 V+ A
** Input - Frame Sync, Clock and Serializer Rx
$ I" q1 L3 X `/ @# l** Output - Serializer Tx is connected to the input of the codec * t- z# }5 b8 F+ n6 s. y$ a) Y% q; \
*/0 K; o5 @! l" B6 L [6 h2 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, u/ ]) e+ [: z, l5 ]5 Z9 QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 G! {1 P1 g. vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) m8 P* I% _. W+ a| MCASP_PIN_ACLKX
1 _* s# w+ ^% U| MCASP_PIN_AHCLKX8 e7 q i. S) ~5 Q% S* N( `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* C# ^( y6 m0 f& [ D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 P- f* o. h& t q2 ?! D| MCASP_TX_CLKFAIL
, v4 D* E$ n- v7 {. \2 M7 r$ J| MCASP_TX_SYNCERROR
8 l9 i9 g% ], A5 ~4 ]$ P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# ~8 {* e$ K5 @, m% _8 K5 {* A* v. [| MCASP_RX_CLKFAIL1 t+ [0 j: R0 H7 Q
| MCASP_RX_SYNCERROR
$ G" n3 K# E# p/ Y) x. _ d| MCASP_RX_OVERRUN);
% D5 D( ?- ~$ n+ `/ R) K} static void I2SDataTxRxActivate(void)/ i2 M7 L2 b& H4 P, }1 y
{
$ k" \# V( b: d; y& g2 ^/* Start the clocks */
; l% i V, `% Z, ]% S; z% X- pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
`& o9 J ^+ t; [& s" s, K# yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 L/ I: M7 L, t5 f) u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ g4 @: |4 w- d. V5 |EDMA3_TRIG_MODE_EVENT);
+ I6 p! b& ~0 Z# ^/ Y4 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 J. ^6 |* V6 S; [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* U# u" U6 I0 SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! a' s' B3 W6 y+ F+ W% }8 I+ L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ F2 H6 m, Q; {3 n% j7 j+ uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ a* V& C: }3 L- s0 S2 s; Q' d: GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# I+ y& C) h0 N: ?- ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; X5 n) \( Y5 D5 E- Z} # P, U0 l @- T: t( c1 X9 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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