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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! v/ D7 s. F( s4 P; I
input mcasp_ahclkx,
* K6 x$ N5 d9 p+ Winput mcasp_aclkx,: v" n% s1 }: x* ]4 R) E5 H
input axr0,1 Z7 T i: A. h" x5 }
( U+ ]5 @* R7 M5 ?
output mcasp_afsr,
% h/ B' M' |/ A/ l6 _output mcasp_ahclkr,
2 y4 w" N" I* B+ aoutput mcasp_aclkr,
1 ^+ _( s( n2 j4 a+ f8 ?# Qoutput axr1,
+ g8 _; Y8 A8 _ assign mcasp_afsr = mcasp_afsx;
3 {/ H5 k8 z/ b: H/ ^assign mcasp_aclkr = mcasp_aclkx;2 Y- B3 U$ \8 a: C$ V( S( o
assign mcasp_ahclkr = mcasp_ahclkx;
6 W; C% u, ~0 j$ V$ e, massign axr1 = axr0;
1 v$ M1 i8 h' w, v, |
, }2 x9 S+ _. X1 T$ l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( e: `: |( e9 Z1 s3 u) z& Wstatic void McASPI2SConfigure(void)( B7 V p& W- B$ @6 i: K
{9 K4 r+ B/ j `1 z% d. b% m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' U6 l5 B2 W7 v, w7 e; O* h. M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. ^+ S4 ^! E6 g6 p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ V+ P) m7 F9 J" G/ |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ {( }# p6 S! U4 U9 {) M- oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( i5 m1 Z7 @# w6 _( x5 e
MCASP_RX_MODE_DMA);
% l, {) V5 [ i, l# y- ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! j5 D/ z0 x3 t- s+ w$ A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; R, [) U# f$ O# u0 s3 D* C! `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 n- S. W1 p# f5 x) v# `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" H: W* G( I# m1 CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- x9 J% b* q* G" u& B( s6 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, f& x8 n- a6 H( i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ u0 C) Y- R0 ?4 ]' {: E4 Y) BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. w t6 y* K* R8 O, H1 BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: G7 n3 K* c3 r/ _6 ?# @
0x00, 0xFF); /* configure the clock for transmitter */6 ^( F5 f, T9 h# Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ O% O( @: p( T' t: \+ w8 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + K; h) T% S" G9 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 l2 K) k: j# ^/ j
0x00, 0xFF);* C2 y( n+ ]' E
% S+ W+ N; _* m# \) j" i
/* Enable synchronization of RX and TX sections */
- {2 R9 J* T$ A$ LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* F5 `: D" x# [4 x% |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 i- S' z; J+ E9 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* C$ x n+ i7 j: g) x; I** Set the serializers, Currently only one serializer is set as
1 ^2 k( q. A9 I1 f7 E# M** transmitter and one serializer as receiver.
0 E. y+ G4 W6 F2 L, N1 j6 T*/' o7 q% a9 g. j" {* a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 Z Q! ]" k- f) T, B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- A# j6 U4 \1 b. P
** Configure the McASP pins
! J6 e/ M. l5 T1 j" E- }" s** Input - Frame Sync, Clock and Serializer Rx& r: o" L: F0 y0 ^- `8 \
** Output - Serializer Tx is connected to the input of the codec ' ~7 @$ Z% s& [# r* V
*/
2 H2 A" ]8 T4 J; @" o8 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. a- c! l& @% R( l8 c' ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 W9 C5 h- _' |# m O! [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 K4 A) C3 }( ]$ R! I0 T1 R| MCASP_PIN_ACLKX
& R( y/ Z6 F+ Y/ N0 J$ T5 ]| MCASP_PIN_AHCLKX
" u+ W% l5 T/ M) j5 `9 Y4 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 ? |. m. `) W& ]; T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 o# u% K; S9 Q* P% @
| MCASP_TX_CLKFAIL . s" e8 I7 P; t6 G
| MCASP_TX_SYNCERROR
( |4 }1 R, F! q* n4 ?0 K2 @, o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 L9 v5 _% G& E2 _" X2 || MCASP_RX_CLKFAIL
1 P% j* Y. O8 b9 S5 {9 A; [; N| MCASP_RX_SYNCERROR + Z) }; T% ^) j0 Y# I! k0 [( e
| MCASP_RX_OVERRUN);7 n% f7 q8 f, d: c. z1 O
} static void I2SDataTxRxActivate(void)+ c- E- T+ E9 w" G+ J
{
2 U ?, Y$ W+ h; W- O1 ?! ?/* Start the clocks */. a: P4 g" g1 }! p- L( Z1 l D! n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ c7 C& L, T2 m5 \9 b1 E( V. GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, g: c' y( p8 B+ J, ]' tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 f) i$ ~7 |' e4 O- jEDMA3_TRIG_MODE_EVENT);. r( h% z- o/ Y! L, \' H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 C8 a7 b) C! dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! k! ?1 \: c2 j$ N0 C* L2 n1 J( c# |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ l: m; @. a N( Y, p' g* ?4 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! |* U# r4 n, c% |9 ~$ K7 v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// [0 h0 U6 A" Z5 ?4 \* ]/ a& U ~, U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- @3 h9 p* v& |& I( dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 a- j# Q+ T7 Z- s1 I5 P
}
% d, }4 K$ o+ e% l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & \- F( J' n$ v a, ?( T
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