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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 G0 V& H. H. Cinput mcasp_ahclkx,
, u& A* ^, |1 [) y/ tinput mcasp_aclkx,
5 k' b4 x+ W5 e, [% e- ]1 [" ginput axr0," N( W/ A1 H2 }7 D% S; p
$ Z' ]2 y: D3 p7 i
output mcasp_afsr,
+ |7 K4 t5 T I( C4 `- ~, Loutput mcasp_ahclkr,/ r' a( k5 {" ]! t [
output mcasp_aclkr, _- y3 I4 M4 U
output axr1,5 z1 f f6 l8 S1 `- }
assign mcasp_afsr = mcasp_afsx;
5 c7 {) |1 l% Y; |4 x5 uassign mcasp_aclkr = mcasp_aclkx;0 z0 M* x$ v0 M! s
assign mcasp_ahclkr = mcasp_ahclkx;
5 Z) i" I X6 ~5 e7 Zassign axr1 = axr0;
, c3 p- j% j( P' P2 Y9 x) t! `
$ P4 J: o* h) z& ?; k) G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; t0 P) v9 Z1 U6 F+ pstatic void McASPI2SConfigure(void): Z e" Y" E7 K% j: c8 j
{
) }! [( ]/ M9 m4 F' QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" F/ T) x/ p H4 u& a0 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 d T+ S' K+ f$ k+ XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 r% @4 r. l3 h' u7 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; m) f% s, Y7 D* N6 Z- x; c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ s% U7 F% u: Z8 W! U
MCASP_RX_MODE_DMA);
& g! q. P! M1 D1 `7 J c+ F4 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ X% \7 f+ b9 j: f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* f* |" a3 v: d9 x; p2 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / @5 ?! X4 a( C4 l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. \2 e z; W" z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' m" i1 \2 Y- w: G: W: {- b: x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 i! C, D2 v- m$ pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: Y" I7 D) |3 Y) |. wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 l9 E/ L+ e! L4 z) e+ k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, i$ U7 p) |5 r/ U4 y6 l
0x00, 0xFF); /* configure the clock for transmitter */' _4 a" a' k) h5 A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ` Q+ Z! d+ [; q; S+ H3 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! \% C- Q0 x" {+ p: MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* y2 q5 u z2 V2 j' y! e4 h; {
0x00, 0xFF);. |4 P- @2 f) n$ T9 }+ [5 x- C3 v1 S
# W" j- g: } s" g4 ]* z$ C
/* Enable synchronization of RX and TX sections */
' {6 n7 |7 w9 Q+ S$ cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& `& {- c3 P0 y$ [" D+ }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: J. x% E! X2 l8 e8 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ \& N5 g: U: Z2 z3 |/ k1 y** Set the serializers, Currently only one serializer is set as
3 S3 x( ?! U: J, w# G( F** transmitter and one serializer as receiver.
/ Q; U$ Y4 |/ g" p5 Y*/4 i- p3 [8 w4 @) d3 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& B4 J4 t( G- K5 f: X' PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' F# q1 L! r" s/ z; S** Configure the McASP pins
, c1 U# E( U5 l+ e. C! v$ F** Input - Frame Sync, Clock and Serializer Rx
7 a- N l* C/ T5 b2 J R** Output - Serializer Tx is connected to the input of the codec
9 y; ? c, E0 T. U( ]. q*/, P( \, b- A. ]0 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& U8 j; c. W9 t- ?+ [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# @- r# F' T* J( q k. Z' S2 |6 UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( H+ P/ W( b" o: t| MCASP_PIN_ACLKX
" N+ ~3 ?$ v+ Z# }" J| MCASP_PIN_AHCLKX
+ ~& h0 Q" V( _4 k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! d% e5 ]' I7 W [: WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 t3 ^5 I6 `; v3 d0 g; q* n5 N
| MCASP_TX_CLKFAIL 7 k& r* B. r. g* F
| MCASP_TX_SYNCERROR
4 `2 z* T7 d5 K) V' @9 L7 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, y" @, E* f8 n, u0 }| MCASP_RX_CLKFAIL# @% c$ W$ i @! ]
| MCASP_RX_SYNCERROR
/ z6 u& p5 M; j; K- l& S4 D1 L| MCASP_RX_OVERRUN);
$ f0 |# j, M5 O2 Z} static void I2SDataTxRxActivate(void)
5 f1 h* F9 E# ^% |7 K4 q/ i{/ t! U9 T8 n5 D/ s% u
/* Start the clocks */& X' G, ^. J" R" T! v8 P) @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 `) A6 q" T, h) F9 P8 x/ zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% @! y! R; i; E0 B2 _5 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 g: o7 K) {$ H" n& E
EDMA3_TRIG_MODE_EVENT);
( n; C% Z% k W0 R8 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 z0 S a; d, k$ N j, {' r7 s ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 p, C( F9 G$ D$ Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- W1 ], y' s% p2 f" Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! ^! J" J! ~6 v8 f* `4 b* E5 U/ e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" I; [$ |% c* p- Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 O, G( R5 u( d0 k* o2 J5 O& nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, o* P# [3 l9 e5 U( @6 v} 3 E2 ^; e4 J) C2 V9 ]( C3 \, ^3 @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) _; O: M) Q3 v' Q( o9 j
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