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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& @) D! R5 h( y1 ~- e A* X* v
input mcasp_ahclkx,
0 n Z: C- g: C0 v: winput mcasp_aclkx,3 x) r/ Z. P6 {0 N$ W! U$ B* L
input axr0,
" E1 l7 m& `; x% x1 e) Q0 g& \4 Y% e2 b
output mcasp_afsr,: A4 N8 ^0 u5 g; o) h
output mcasp_ahclkr,9 ], y; K3 ^$ a$ F1 O
output mcasp_aclkr,) D7 b; _/ o, T+ X- ~
output axr1,
# f L1 D/ m( y$ Z assign mcasp_afsr = mcasp_afsx;
# x. p) ~# v" E4 w+ U- C- Xassign mcasp_aclkr = mcasp_aclkx;& r U R" n# p- Z. O! I
assign mcasp_ahclkr = mcasp_ahclkx;
; y( E: N0 g7 j4 y; f# i/ yassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ^6 l- _; y- R. i3 \
static void McASPI2SConfigure(void), l) L. d3 M: G9 m+ a
{
" H4 ^! Q8 l/ J& P" I5 d% ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 ^2 F; b8 q* @- h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% ?, d2 R. [* g5 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 f1 Z+ {& d" ^! G' z& u, fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, d9 _$ t. x0 W. J6 @ z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 Y+ ^9 C3 b, ~: JMCASP_RX_MODE_DMA);
3 m8 b2 c( @0 O" n3 r, mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ?* V- e* J. N, P! }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 J# l# S. E% |+ v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: y$ L+ \0 F6 o7 aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' e; ~& z+ t# A8 X6 b# G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 m% q! J# R$ T: O h5 b0 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 t& l, T( J" P+ h; bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 u/ _( I) t. n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - h7 X$ z! q9 L* z9 f* r7 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ ~9 \+ o, X, }9 K' {/ |
0x00, 0xFF); /* configure the clock for transmitter */
A4 g0 k6 O2 F* qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 K3 ]" X" |& U! e$ ]( aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , T, X: {9 H- e" L% r) H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% j5 U8 h0 A/ c6 g e0x00, 0xFF);0 C# ~6 X4 s: u$ ~/ R
! W& }, X" ?7 {* Q5 u/ y, `
/* Enable synchronization of RX and TX sections */
" Z9 f ]5 ] I7 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ s( o% }7 d. ?# H/ OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( J1 n7 w: k7 C! [# P _6 jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* k# P$ V& P3 a, y6 A+ ]# J
** Set the serializers, Currently only one serializer is set as9 y/ J& m3 x/ [
** transmitter and one serializer as receiver.1 j* a7 e) w6 ~6 n9 ]: T
*/+ d4 O+ C! S9 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, x e. m4 j* \ X! m& P: |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* A' y& m' x, U$ ], e1 C F: s y** Configure the McASP pins ! X/ l/ }+ N) {8 `3 X- ] f/ P; D3 A
** Input - Frame Sync, Clock and Serializer Rx3 Q4 f m- ]7 D7 N$ l) M& r3 [
** Output - Serializer Tx is connected to the input of the codec
" s$ F# T8 {) v, w; U*/& s# F; O, Z2 o' e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 b* s. W0 D+ u7 C0 n0 O# pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 Z0 C) ?% b9 A: G/ v) KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, j/ x' e& e( ^; l
| MCASP_PIN_ACLKX) n9 D- ^ w. L
| MCASP_PIN_AHCLKX7 R6 j3 q$ A( f. f6 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 z: _( q0 z! v) Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . W) N: e0 o' B
| MCASP_TX_CLKFAIL ( I" R6 _# n* y% e6 ?* U
| MCASP_TX_SYNCERROR
9 x) W. V: w Y" c* m& N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / ]/ J* p& O; L9 m9 H( Z
| MCASP_RX_CLKFAIL
/ C ]# z( u! D3 U3 k| MCASP_RX_SYNCERROR
9 y. N' \3 ]3 N* T( g6 ~| MCASP_RX_OVERRUN);1 A J; M7 [+ }1 \2 L
} static void I2SDataTxRxActivate(void)
3 f9 s. N& \0 l" G; i" E2 S W{; f/ w) D) W% o* c/ Q) i
/* Start the clocks */+ T2 H" H) L) E2 H$ l& P$ t" o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 k2 h! a% F7 \% A0 L, UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 r" B8 v. |6 t* `) aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! M$ ?, O4 ~/ g: i/ U b0 oEDMA3_TRIG_MODE_EVENT);8 W% E1 K2 R, y, r* W- E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 l C4 R4 [% u1 a. PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. e8 h2 r8 V+ s1 A3 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 @$ ?% @+ I- |6 E& Y, |5 pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: Q- i$ t: a/ P9 z2 L5 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( M( V0 W3 ?3 K6 Z, j! ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, @/ N8 G4 T. m+ Q: |8 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( T) L0 V1 o' S$ ^# r8 Z
}
1 p6 A; U# ` [! j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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