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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 |# v! ]3 b) oinput mcasp_ahclkx,: s3 x; Z5 V. M$ S' X
input mcasp_aclkx,
! D9 O" I3 Y5 U* q8 Q k0 D+ winput axr0,0 Z. q' W; y" ^7 y
: k) D ^2 @: ]% B
output mcasp_afsr,
9 l$ j8 I5 e8 l/ k+ h9 G. I0 ?5 G joutput mcasp_ahclkr,$ L0 X" ~6 i5 e( P( |. C
output mcasp_aclkr,4 b3 q* j4 _! a; I0 L2 Z
output axr1,
0 U" R9 W# ~% s7 i assign mcasp_afsr = mcasp_afsx;
0 W& g' a5 M: \$ rassign mcasp_aclkr = mcasp_aclkx;( E6 S. u9 a! [+ F4 l
assign mcasp_ahclkr = mcasp_ahclkx;
6 T; t: s" J9 [4 w# L5 N! Gassign axr1 = axr0;
' j* e' [- v0 R. z2 W) L) ?# o" _ i, n2 ?# c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( t# x. K( c+ j4 fstatic void McASPI2SConfigure(void)) m0 |$ k' e/ A2 l+ t5 C# Q. Z
{: ]8 J+ x3 g+ }. ^/ C, X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ ]$ L) a, ^. _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 }9 g, P4 l2 K% @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 S2 n9 W8 f# L( n! b) T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: z+ A) I- J2 M3 u5 n4 @/ cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," `* F1 Q+ e; ~/ C2 ?
MCASP_RX_MODE_DMA);) c) N. _2 F& q% \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- \( n8 g) M8 S N+ D) i7 X1 [8 i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 }# t: D1 _: g* J1 k5 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . V: M1 l; G: I/ e- o- |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, Q, @8 G2 v" [, U; T& M8 |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : E" e) W. ~& B) H, c } Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 z! Q; n1 T8 N" N6 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 _& @2 [4 _0 s& w6 Y' J) _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 m+ F9 Q9 y r6 j) L* MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," \9 U: S" W5 q
0x00, 0xFF); /* configure the clock for transmitter */9 ?+ A) U E7 S. I9 j6 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 F" }, g. a% HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ h4 G2 K& y) n @; X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% O- L u* |7 b$ { ]& l0 c$ i1 F- g0x00, 0xFF);( x! p7 ~& z* S
: g/ F! @/ `/ l3 q6 ^' G/* Enable synchronization of RX and TX sections */
& e& l& |% O6 x! m3 j" N, AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 O" C3 m$ ^5 x1 S( U; m/ VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 L6 i+ M# x4 d; ?; N- `0 b, f% IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. g! _3 s" u& A. A** Set the serializers, Currently only one serializer is set as
! W: A' i2 ~! V** transmitter and one serializer as receiver.6 W& `/ [' G1 Q" K% e4 B
*/
! \. V( p/ c- W5 R/ l8 j/ zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" l) \& _! g8 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
y1 ~) z, f+ E# w M** Configure the McASP pins 3 z: u& y$ O i5 x
** Input - Frame Sync, Clock and Serializer Rx8 Z. f3 m/ ]5 s6 x) j3 }- U: D
** Output - Serializer Tx is connected to the input of the codec " T3 j6 g; |1 c+ z, z) j; M
*/
" h5 l3 I) W/ v2 L1 q+ C/ H$ ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 o. E' Z0 `1 w4 l, ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 b h1 v# c% h6 }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 A& Y9 Q. @0 \$ Z% l
| MCASP_PIN_ACLKX) V3 n. s% ?7 C
| MCASP_PIN_AHCLKX; {% b6 p a* H+ g- N6 v6 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 Y2 b7 ]- G4 x4 y: X1 \" R; ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & n% o4 ?$ V, S5 T+ u5 Y
| MCASP_TX_CLKFAIL 8 m; Y+ n4 a) \0 g" ^
| MCASP_TX_SYNCERROR8 E/ e; l$ Z: }& f- p! `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' _& |) d6 d5 x7 n0 ]| MCASP_RX_CLKFAIL
" i, J" A4 ~, f3 p- k4 T| MCASP_RX_SYNCERROR " y8 o0 R. M6 _& j. D
| MCASP_RX_OVERRUN);
* U# I( t/ x+ J Z" h3 Y1 T} static void I2SDataTxRxActivate(void)8 E. P: n, H, _
{
E, N6 U* }6 {7 Y3 |/ ]/* Start the clocks */
4 b, |" E. d" m5 h1 U( y! G HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ X( I, U' m# j1 _3 u* h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; [- a- ]/ Z8 m6 Z* f" o0 j1 |# h) TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& K$ g. \! t, w, qEDMA3_TRIG_MODE_EVENT);
! a" ]" F% m9 Q! D, q. v3 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * R6 o5 `: Z9 r! Y" B) z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" {" z/ O# t0 @3 }- t# AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
H) X' Y$ d8 l; JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 F# p& W' L) g6 @5 n: F7 d" L% dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: l' W) D* | H7 `7 P9 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. e' q! p( d- ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 @! w8 w. a7 W [) n6 Y, ?. q}
: D4 i; s7 t- H: d' P3 Z" g7 E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * V$ {1 u4 U7 n, D/ P3 _% m6 r! R
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