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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 j" `+ f% S- M. }+ V6 hinput mcasp_ahclkx,
# J7 C0 Z& w. o; O- W* Y2 W) Ginput mcasp_aclkx,
; Q8 [' Y) h" ]- ?# ^& iinput axr0,0 q: c7 c. ]2 o
0 v+ o/ r8 X: f
output mcasp_afsr,
# V/ U# s9 G# `9 H4 Woutput mcasp_ahclkr,/ o, _* i: R$ f% Q# _ Z
output mcasp_aclkr,
% @; z, a/ @% i% ]: Boutput axr1,% W1 R! p& q; z
assign mcasp_afsr = mcasp_afsx;( F! H! P }9 r' c" e% R( }4 m7 a3 |
assign mcasp_aclkr = mcasp_aclkx;9 `* Z+ M+ y7 { }1 H7 R# e
assign mcasp_ahclkr = mcasp_ahclkx;* h+ T9 w0 Y6 [6 Z. g! K
assign axr1 = axr0; + h7 l% m: Y! `2 y
8 u1 U* G8 B# N k; D6 n) @9 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: o5 s& R9 H Q7 e- w# w/ g8 J7 qstatic void McASPI2SConfigure(void)6 M m! a, }% a6 P. B1 x
{
R' {& s0 b) a8 E4 C0 y6 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- V% g; a9 c o% V6 C; ]1 ~8 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) g2 y; _! _2 M0 e8 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 {; `5 j$ R& l- T- @9 ^. d, RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# w" O! k7 N3 c3 }! }. D* mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 }( i( B' [2 yMCASP_RX_MODE_DMA);
8 h9 f# t2 _8 w2 r9 |5 YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ]8 |, s3 Q M% }, u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" |7 B: M3 @/ [" PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 [& Q6 Q `# m# u$ V5 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 q1 H; }/ w! ^/ i( `; X3 G* xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 s9 m" e7 O+ _2 K( }! d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, R& j C7 [. d; n0 W" DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: h9 _- V% P% h. A2 g. z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / k* }* e, G" A/ y, G6 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 q$ |: n# c1 d2 Z# `* g, \0x00, 0xFF); /* configure the clock for transmitter */
5 n( X: Z. |2 w# V* P4 I0 N' BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 i9 Y* b( ^- `0 H2 S0 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 m; ~2 [ M: {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 b: P4 {' j1 \" j- u7 Q+ f2 m* E5 q0x00, 0xFF);
' I5 o, O7 @/ g8 e' N3 C% I2 @# M! n# A$ B' Z, c
/* Enable synchronization of RX and TX sections */
- a! x- L( x* I0 s" L! k* K6 j# rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ S; W( C5 l1 O( ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, n4 G4 _7 q" Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% v5 l+ D. ~/ C/ V) A% d9 V! v% ]: l
** Set the serializers, Currently only one serializer is set as
: c: {, g- d( H, [** transmitter and one serializer as receiver.
% e9 z M$ z& t% D- Q*/6 O4 G* Q, i% o4 L( O( `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( @7 U. Z$ @' ^3 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" s8 t7 u( B, \1 S, f; r4 O** Configure the McASP pins , B2 f7 a& G: E" C6 ?4 I W* n& }7 S e
** Input - Frame Sync, Clock and Serializer Rx) \; E) D6 v; P# |7 I
** Output - Serializer Tx is connected to the input of the codec ) P, D3 i3 x. D0 T& k" V& C
*/ e6 y! C8 k: H3 C+ } A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& x( W& Z/ U; O; s* uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' h- B$ c- d' ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 H5 |1 y3 i2 C3 p! x8 A
| MCASP_PIN_ACLKX& K! L0 Y7 U! D
| MCASP_PIN_AHCLKX
$ b2 E+ d @: B1 K! K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 r' ^* t$ n( W$ G+ J* G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- A/ O- m$ ?$ X7 z4 x| MCASP_TX_CLKFAIL % d1 Q! {. R5 O: Y9 ^
| MCASP_TX_SYNCERROR' P2 I- p/ l, ~4 V% T7 a# _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & c! a4 c% e6 N! A F) ]) b. V* s4 q% q* K
| MCASP_RX_CLKFAIL7 y& z7 y2 d9 M( W
| MCASP_RX_SYNCERROR 5 w1 ?# L# g! C# n0 V' y, c
| MCASP_RX_OVERRUN);
8 z) G' G8 s+ \} static void I2SDataTxRxActivate(void)9 u+ j# @ f) r' N! E
{
0 D+ \" S1 x+ s+ [8 Q) d n: S9 _0 ]/* Start the clocks */
6 v' W7 l8 `& T0 X' p a; jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( c* g! K+ ]" P+ I2 w- c4 Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( ` K6 a; `+ n' D1 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# m8 _4 Y0 r! M% a* Z$ X. q, qEDMA3_TRIG_MODE_EVENT);
$ ^: v6 _# A( ~ n7 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 l! } e# t* H: k- P$ d3 |) _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ t( p6 q6 U* s* M7 m* c7 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 F) j& W F& K9 H8 M0 A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 e( a9 w& l, C+ ^+ H0 o- F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 \4 Q* t* ]- i8 F( O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 F5 `2 Z1 F5 Y& S& P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( T" E( d% T+ e7 V}
9 z* q/ S/ s h. ?+ }4 y; u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 K8 q" p/ b" n9 a! G
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