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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, Z; e# |+ F' X% W9 C: H& l, l, Hinput mcasp_ahclkx," V3 f5 {: s& T
input mcasp_aclkx,
% V1 z: l& F3 {2 Qinput axr0,! i/ g; p/ I. J. A) l6 J- W8 _
* Z5 q6 w! q% F9 [5 voutput mcasp_afsr,
6 I; [; H- t; s4 ?" n# O3 F9 eoutput mcasp_ahclkr,: | e( B/ o o$ a
output mcasp_aclkr,
7 J) K ~% v poutput axr1,/ v4 U; |" p% N& t3 S' l* f5 z8 K6 S
assign mcasp_afsr = mcasp_afsx; k( e( q% y0 L
assign mcasp_aclkr = mcasp_aclkx;
& z- d5 L& n" G: t% Nassign mcasp_ahclkr = mcasp_ahclkx;" y) I6 _& x2 G& W
assign axr1 = axr0;
# T8 n# M/ j4 B+ e9 `# V$ N" }1 T! E( I' e" E. Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 T4 K# t8 v. U& ]2 J6 i7 Rstatic void McASPI2SConfigure(void)
8 R& W) A8 ~2 v0 Q9 D{' X2 @, T9 g( f$ N5 w, g( c8 G0 W; ]9 u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 y4 R2 s8 f4 u1 U& J. f+ j9 e) W+ hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ L! d" i H1 k8 h3 z5 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' m0 X$ @+ ~; yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ Y w# w4 S$ `4 W' s8 I6 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ B! t( d; B, `! N( O% z1 D0 X
MCASP_RX_MODE_DMA);
9 T6 M* ]" N: P& o2 s2 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ~7 \/ `2 x F( I4 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 [# X- d2 P) g# T$ B/ O0 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - T% H6 ]) j# y. d7 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 j5 X. R, [+ a- X7 k' W8 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % O6 Y8 K2 R6 H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" v" t& {0 m/ u6 z+ f6 S [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ G) M! e2 A# x E% y# K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 |& D3 k7 D. n# G5 ?, SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# p9 Y( g- f( T0x00, 0xFF); /* configure the clock for transmitter */& f8 d$ E" G8 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ X" c& V- e. n1 l$ R) uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 n5 n {2 S+ Y$ I4 r% |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- I) C* O$ ?) i0 Z- b
0x00, 0xFF);
9 n0 m* f+ F8 c/ ~8 L8 f# B/ C& G1 P) J9 q! P( Z w
/* Enable synchronization of RX and TX sections */ & b% y% U3 W! j6 L5 T8 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; z6 ]; C" d! ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 T4 W6 s/ t. Y" D, Q# w6 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 V+ z6 x: L2 A+ {, m! v** Set the serializers, Currently only one serializer is set as
! T; s* u) O) x, Q( E& ^** transmitter and one serializer as receiver.
2 M* x, g. ~# r: p o' U% ]3 x*/
- ?4 G, B4 J: ]7 e' n! CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; \$ i) W C: |" vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" \5 F4 b) S4 K
** Configure the McASP pins 8 I2 E4 c+ d& j& b2 _8 E
** Input - Frame Sync, Clock and Serializer Rx
9 |" g) [! J' s! c8 _** Output - Serializer Tx is connected to the input of the codec
8 w$ F8 J1 d) N( f- B" b*/! _2 h5 n5 ]# K9 @/ B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ D& p8 O5 E2 \' ~- X/ VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 I1 f$ R1 j+ o( j0 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% H; b; _( @; ]
| MCASP_PIN_ACLKX' w7 G% ~( L1 v: V4 \; }8 u4 {
| MCASP_PIN_AHCLKX) N! l# _ D, f* ?9 K5 y0 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: E$ c2 t0 a% b% e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ J; }" y& L3 F+ C' t0 l| MCASP_TX_CLKFAIL ! o8 E% O T. a* Z/ [5 ]) ?6 ?
| MCASP_TX_SYNCERROR: F) e# b( @) y+ ?/ T8 Z: |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 S- j1 V/ }- V, M- j) l9 L6 k| MCASP_RX_CLKFAIL
7 x7 p9 u* }2 X, M3 Y. {: w+ S| MCASP_RX_SYNCERROR * J9 @/ _+ R. A1 l
| MCASP_RX_OVERRUN);( [7 ?. [1 z, Y1 y4 x" s, Y
} static void I2SDataTxRxActivate(void)9 B0 {+ }2 N6 w5 Q! p' u8 _
{
" r$ h$ k7 a; I/* Start the clocks */2 G+ j0 ~8 y" |# ^# y# G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; Q5 B$ d; r* r4 L0 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 n7 M2 s% ~/ t0 l6 U! |9 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 Z9 i7 t) W8 ~) h+ t% M$ [
EDMA3_TRIG_MODE_EVENT);# e4 r. ]3 q7 W% Q9 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, H- }3 s# Z9 d. ?1 v- W& {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; ?; y. \- ~! I( P0 F3 r' w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: a6 J! t, l5 Y6 J$ y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 _ I- k" I2 q: t6 ]& mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 c7 y; v3 S ?! L; xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# G/ |) `( i+ s* J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( }* f% I4 K$ P9 {5 v3 Y} 2 s* l# C3 Z5 r: c7 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 e/ }! y% Q, d$ {& Z+ p
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