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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," [1 v7 H3 O" S/ T
input mcasp_ahclkx,& Z! n) p+ M2 ?" r- w5 g; J
input mcasp_aclkx,
$ z& o: O z4 {: O" F x; a: Einput axr0,/ b* W* v/ R9 k4 Y: F6 a# x
! x& i/ h! M- x! ~( h& O, voutput mcasp_afsr,1 C5 ^" A; X( E7 E5 B0 B
output mcasp_ahclkr,
1 ^; h8 ^: T$ G. n$ P" X6 ?output mcasp_aclkr,( y. ?( v9 g6 p/ | K( t# \
output axr1,
$ d( \) f4 \( A, O7 ]5 I" j/ B, } assign mcasp_afsr = mcasp_afsx;
/ Y/ h. _& o' b' w% y0 ?- q+ ~8 Z& iassign mcasp_aclkr = mcasp_aclkx;( l$ ?6 O8 v* }. ^! W" M& ? M. s% }/ T
assign mcasp_ahclkr = mcasp_ahclkx;
) B; @6 G! H P& P4 _' xassign axr1 = axr0;
/ @$ n+ V+ m3 I# }$ j
+ J: `' _1 X4 ~: P9 U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, w! u0 W( D t" |6 Sstatic void McASPI2SConfigure(void)
) i) E+ W8 @$ i* ^ U' Y7 R' Y{
$ ~3 f% V) @3 v7 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ T5 ]- A" A2 e2 Y, W! n& l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' U$ u: q; d6 O; ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, \) U* Z) q/ P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 u6 D/ n6 ~, G. R! a6 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( k) ]2 z2 r0 o4 Y+ ^MCASP_RX_MODE_DMA);1 d( f- ^! C: y: Y/ L8 ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 S6 j8 W J! ?. ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- m) ?* D J& F# p: p: J( ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( ^- c3 ^' M0 w# l! n- DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% [" D- S8 u; |" s) e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& \- ~3 n7 ^ z B# I! _* h+ S0 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' H4 x4 u7 e' z$ eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: j' X! I) ]$ f( A1 W, I# ?; J# EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 F# c# R9 {$ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. P: G. P/ }: [2 x8 B5 Z/ b
0x00, 0xFF); /* configure the clock for transmitter */& s9 S6 e8 Z( w& v/ y' R8 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 p* y3 t, f" s- X) C6 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, L K- M @. C7 m& M9 h$ kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 d9 w( r/ x1 g Z0x00, 0xFF);9 h0 O/ E2 L6 m/ u" C% L
( L) j9 Q( J' _. a/ }# d9 E7 P; n; s/* Enable synchronization of RX and TX sections */
! o, [: [) [- L+ ?) w1 U" ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) C+ e* S# f7 U) X0 L5 e# X/ LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# O% H9 [! E) G- n( d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ c* Y/ N; T( X) l
** Set the serializers, Currently only one serializer is set as% L, K" u+ \( Z9 U- m% Y
** transmitter and one serializer as receiver.4 _8 Y: i4 H V( @3 ~4 Y# [
*/$ `- s/ X# r$ h- z6 G% ]9 {: n) |% ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 y! U( j+ s+ y- d" G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ t. l8 s& {% j, @, j! R** Configure the McASP pins
# F: Q7 P6 Y2 e! S** Input - Frame Sync, Clock and Serializer Rx
0 p3 g. K4 v4 e, f: J. @: }** Output - Serializer Tx is connected to the input of the codec : i5 I; t2 A- x# c
*/9 _6 b/ w3 T7 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 z7 N3 `+ q+ ^) Y# P# w* i: HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) O* v! m% q' a1 w+ {( DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. J* l$ ^+ v+ d' u" U- }) v| MCASP_PIN_ACLKX4 I5 P+ K9 F6 N+ T# v# O1 Z' s8 |! m
| MCASP_PIN_AHCLKX
" w% F/ C9 P/ f! j: F2 {2 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! W1 L1 C6 b L- m7 F: g6 p, P0 o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 @# \+ S( U3 E. |! a1 k| MCASP_TX_CLKFAIL
+ `9 c/ ]- t" z4 W3 b6 v| MCASP_TX_SYNCERROR
4 G+ c& f; ?5 c2 ^4 D( {8 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! v/ m' e8 E5 O5 g1 A9 ?2 h
| MCASP_RX_CLKFAIL
! B' e# o2 i" Y7 s2 q1 B| MCASP_RX_SYNCERROR - r% Y7 ]) o! X
| MCASP_RX_OVERRUN);
O, u5 ~, O- Z7 V7 |} static void I2SDataTxRxActivate(void)3 Y( H$ v* T! s, I1 u" R
{- {; |# e2 `7 b9 r
/* Start the clocks */7 F- G. ^, U# d/ [1 ?2 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 A" t, m1 o; F4 t8 F x2 h: n& G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ u# p4 R( _9 M# p5 j2 y( EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 z) a1 y3 K, v# Q$ E& x( J( C, f0 G. _. nEDMA3_TRIG_MODE_EVENT);
4 B1 E6 O* E8 C* S7 f: D( lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, |5 A+ z4 d6 L, ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ V% p: d) p, W) q- D) OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 H y3 H7 o7 x# o9 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 a$ E2 v/ Q5 |, H, _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' Y1 A+ }0 P1 P l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 \/ R4 a' M Y2 E0 v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" l+ T$ N2 \, ~4 n. C
} ) n0 W: O; }- k6 z, S4 H# d" F% N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! g& Y* h3 `7 g2 c
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