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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; z, S- U: C& i1 o( \& ~input mcasp_ahclkx,) H" F U! l7 T( D
input mcasp_aclkx," I: B& F+ M; {: M( [3 O) p& `
input axr0,
^. }7 l: Y1 d7 t8 A; X% s6 V- r, A* J6 {' y+ L
output mcasp_afsr,
) j$ K: n9 o( xoutput mcasp_ahclkr,0 G1 }. q9 L2 {" f% Q% l
output mcasp_aclkr,
9 G) Z! K V9 E, q' S6 d0 ]& Koutput axr1,
1 ?% [$ r. D% V" [; ] assign mcasp_afsr = mcasp_afsx;
& C+ [6 B" i7 Sassign mcasp_aclkr = mcasp_aclkx;9 |; J, G& z5 E4 j: m6 X$ T
assign mcasp_ahclkr = mcasp_ahclkx;
& m. {) q$ E1 C5 a6 sassign axr1 = axr0;
; {1 r, j- W+ r2 `$ Y- i& x) s, V
; V" ]8 u6 h; x) k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - W; f; \) l; l2 `
static void McASPI2SConfigure(void)+ z# K) S- |& Q# V
{
. \5 g( c( _9 W) f8 U. KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 |, p" I! ^5 f5 o, o% vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 y$ F! j& k' ?# ~% `( z9 P. U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 ]7 `4 M- A. H) AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// |7 l" ?" T* a9 s. n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 X' Q6 d- `4 }4 w/ i' d
MCASP_RX_MODE_DMA);! q6 Y2 e) [( ]! j) i- V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 E+ z0 C7 C7 }( m; nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" ?! L) f- r1 x6 ]1 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; I2 d. M* R1 K" j5 _5 H3 y, `& `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ c* d) @1 X; x% A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 i" U& b) }0 U/ E0 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# w5 Y% N" f. |1 I- r/ X: n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 _1 k! U$ r( ]& X! d1 Q2 b. R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% U" i& ^7 z1 Y) o. k- tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 g4 i5 r0 |; L
0x00, 0xFF); /* configure the clock for transmitter */
% o6 ?; e2 A" ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ q7 t' n5 \2 q+ q. E( rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % @ o( Z. C% b# [4 q( Z" ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' J1 Q5 r# [8 c) l. ]+ C4 q
0x00, 0xFF);7 V5 h" H) A' s" o U0 o) q
) q0 O9 H2 R% r: ]$ k$ b+ Y' P/* Enable synchronization of RX and TX sections */ S# ]% m$ E+ r5 Q' F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; w X% D! Z; e2 R, ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" q& g+ `: z! [( P2 hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: c5 {' ]1 |5 m( B; `4 `( m( @
** Set the serializers, Currently only one serializer is set as8 c' P& \$ J) ~/ }5 V/ g6 }
** transmitter and one serializer as receiver.
2 d7 `3 i. N. l" y' i9 O. O p/ x, x*/3 s8 j7 B9 x/ I f, x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 u9 R S j+ ^0 z# M; l% l% i1 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 u8 ~$ [! B* M! f \1 @0 S8 m** Configure the McASP pins
8 a- W$ _# m4 m; O** Input - Frame Sync, Clock and Serializer Rx# V. M! ]5 [/ \7 h2 l0 u
** Output - Serializer Tx is connected to the input of the codec 9 K, k( r! S: b
*/
6 I: w# }/ ]$ h, _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 R! K# {3 h1 p1 n8 z2 h3 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& I: Y$ M0 g% P9 N# D6 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% a5 _" j8 l9 z+ |" ~0 M$ \+ m
| MCASP_PIN_ACLKX7 v6 H7 V1 \) ?' Q$ ?8 |$ h) ^
| MCASP_PIN_AHCLKX
, Z5 [, C% k) }5 C% G9 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& i7 P' B# b& V1 a$ BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' P# y# N+ T/ K" {' `, M4 W
| MCASP_TX_CLKFAIL
' @/ b* E; A$ b. `6 v- || MCASP_TX_SYNCERROR
' U S) @8 \0 p; h% l# [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : w7 |* a$ V9 _6 L% l
| MCASP_RX_CLKFAIL9 s; Y* Y5 E% @; w+ o1 k; k
| MCASP_RX_SYNCERROR
P t" m3 ~$ |: d( ]| MCASP_RX_OVERRUN);& q/ K$ f8 C* g) X: Y
} static void I2SDataTxRxActivate(void)
: j0 z' x+ L/ Z8 \; ~{+ [7 F/ w* [$ x6 o( Q! {) j
/* Start the clocks */! G8 O0 Z4 `4 ]- k7 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: Z+ o9 {' x4 h9 C( j' {: _, hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 a J6 ^& ~! e0 y A) c8 ]! L" u5 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! ?) c+ V& S- X! {6 n& t8 @
EDMA3_TRIG_MODE_EVENT);
$ Q+ }( W; M5 V' GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' {0 F v T( p5 j% ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, K- ] N3 u1 i+ R; RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 w2 K" O9 ~+ C; V# K# H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% w {* s" A9 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 P; z7 z$ N4 z' ^& L9 y/ R/ ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
Z% h4 f4 q; T9 L8 l- zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& w% e0 C, A* i/ R}
* G$ t7 m& b5 Q" S2 Y; Y: P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : u. z$ A6 W) c$ J: ~
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