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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 @1 \5 `( X) I
input mcasp_ahclkx,! ]; Q' X2 u% R+ M5 h! _0 D2 [
input mcasp_aclkx,
3 Q* r0 m; I" l, K5 cinput axr0,+ L3 K! ~9 g, ~3 F% a
& p9 K% c9 i* d1 p) g& S* D
output mcasp_afsr,
3 |# e9 l2 N1 Doutput mcasp_ahclkr,
6 j4 [% G; E+ X# R; `output mcasp_aclkr,8 ^5 B$ q: b( a0 x
output axr1,
. i/ ^3 w3 g8 e/ k4 _ assign mcasp_afsr = mcasp_afsx;- n0 x, A9 _- u/ P, b4 X
assign mcasp_aclkr = mcasp_aclkx;/ |5 q3 _# Y! Y. g
assign mcasp_ahclkr = mcasp_ahclkx;; H% n5 l$ m8 a# n9 e1 V8 Z
assign axr1 = axr0; 0 J5 Y0 F2 d' a, h5 z. e8 x6 ~
7 d( ]) s6 L5 `$ m9 |4 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' m/ Y7 b! } J' H: X F
static void McASPI2SConfigure(void)) a+ t! O6 d' d5 n {( m
{
2 e& Q4 y- \. N- B" \McASPRxReset(SOC_MCASP_0_CTRL_REGS);, F: O: O# x. g5 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: m; x6 G0 U6 |1 e( p/ ~! `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 ], @! G2 \, N1 E$ RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 N6 a$ b% K% q. W2 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# I/ N* e* `5 C7 Y" @2 q7 a. _MCASP_RX_MODE_DMA);
! s3 g% R3 ^/ W/ b( m P$ ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, N9 v* S$ u$ X2 U p# yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% y* ?6 T5 p0 B) o G! W, F% IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % c9 K( i- w, L R! [# ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" _, q* L$ B' l8 W9 `( J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 n; {7 |9 Q1 S) v! {5 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 T0 W$ S, |* T7 |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- B- X+ K. L# O& D" ^- v% R, t& PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. b* T, `8 s" S8 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, D3 N4 {1 C+ P7 Y
0x00, 0xFF); /* configure the clock for transmitter */; ^" m+ ?5 j3 e8 s6 u! F( w6 x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' t. L0 `, a3 `; i" {" c1 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" b/ B9 K( T7 t4 c% bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 b8 l/ {7 e" A- E" `0x00, 0xFF);
0 {9 F: y+ H' c1 ^* A6 B" _) w$ _% n7 ?8 m) L' H+ E4 U! J% n V! T _: z
/* Enable synchronization of RX and TX sections */ " p% n( b$ C8 ^0 h& ?/ @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// c& o/ }4 P. V4 c6 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 e* i0 O+ h8 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 W( X% m V4 p% w: }' r; j
** Set the serializers, Currently only one serializer is set as" ?) f8 n7 Z3 o
** transmitter and one serializer as receiver.( ?; }4 [' p# v3 }0 r! X5 Y0 j4 r
*/
" }; k0 ^: Y* OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) h: h( H; t* J( w+ A7 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& [' ?& V3 [ l8 {& L** Configure the McASP pins
$ ?7 }; `2 f# d6 s: d: Q; ~% k** Input - Frame Sync, Clock and Serializer Rx8 K& ~! f3 t; n- y, o. I a
** Output - Serializer Tx is connected to the input of the codec 5 T# @/ L: R! u6 F
*/' R* a' Q1 g3 V& v0 @+ Z6 V, P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: x2 d* D3 q; e OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: x/ G+ ~# N+ L% b9 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 @( k: x0 r U! u. X1 E
| MCASP_PIN_ACLKX
1 f$ b) H1 h9 ~2 `6 h I| MCASP_PIN_AHCLKX
& Z& q/ \8 h5 s% j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- n; Z H* E2 q3 @' Q# F X7 P% I; w% lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 S! z! G: N' h% }& o| MCASP_TX_CLKFAIL 8 I: z4 |2 ?* u0 B) w
| MCASP_TX_SYNCERROR" w$ J% p* h; ]* d8 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % X3 o# p( E) [; V
| MCASP_RX_CLKFAIL
0 G7 }9 b$ e* ~2 W7 K+ P| MCASP_RX_SYNCERROR
; f. w% @, l9 ?* Z' [6 b7 }| MCASP_RX_OVERRUN);" k; ]6 r) N) x8 W- d
} static void I2SDataTxRxActivate(void)
% ~/ }+ F; p+ _! n9 z" j5 t; H{9 G M7 R, }- B2 _
/* Start the clocks */
o* K1 |+ F7 ~0 W7 N4 a2 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# l% ~& g3 g3 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# @0 h* c# e5 ~& JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 n, D0 q. ]+ N7 J9 ]
EDMA3_TRIG_MODE_EVENT);
2 f, ~2 q. R! t0 P) L1 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / I }' M/ o# u( }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 @" @8 e8 v3 M# o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 {) V. k D% o0 P, w5 ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// S/ b' _! h0 r1 K- a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ ~3 U: I$ K! C9 {6 ?9 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 e# T4 o0 T7 @, Z9 j2 J" G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& d7 O% W1 \* D/ T}
; L0 v" F3 m; c9 q* S; t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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