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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 w6 H5 ~% J9 dinput mcasp_ahclkx,* d( N! x( V7 b$ f9 f/ V0 Q( R
input mcasp_aclkx,
( Q2 S+ Q; V, v3 @input axr0,3 z5 @- Q F( p6 a3 L2 X g
6 E6 D+ D7 f1 P/ g9 m
output mcasp_afsr,
4 K, ~: l! x5 K8 |5 H0 G' B( |output mcasp_ahclkr,
2 q# l' v9 C, V4 Noutput mcasp_aclkr,
8 ~$ W3 `' o: i# `# m& }output axr1,
: m3 ]& A" @- ~; u assign mcasp_afsr = mcasp_afsx;% }0 J2 i. z4 N' Y2 N1 o+ }. ~! H- z% N- d
assign mcasp_aclkr = mcasp_aclkx;7 S( H( G: t! c, _( {, X
assign mcasp_ahclkr = mcasp_ahclkx;
: \$ s6 [/ b+ R/ Massign axr1 = axr0;
( m# Z! C: R3 R9 N
' j5 G$ D, x, w3 H6 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- p/ U9 \8 v! k1 s9 ]static void McASPI2SConfigure(void)( R9 O: p! m) p: A \2 a6 a# \; k
{3 B3 q E% d% o1 a7 c/ B8 {3 P( i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ u2 o5 T0 J% m" [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! {3 {$ D; X1 P7 Z" DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' w, |+ {7 z* Y; |7 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 @( C0 N% g8 Z* c7 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# f/ A: W/ W) SMCASP_RX_MODE_DMA);5 L# l \; C) c2 |, n2 t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 L% k R" Q' H$ v% v) I/ T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. f* w1 K! Q3 K! e/ O' Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! R# |4 W! ?' `: h7 g$ y0 v+ w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' |2 W% r; [' u- n& y1 ^1 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * o0 U) I7 |0 L! M9 Q0 g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 S. ]8 q( u4 K/ P; x, }+ B" NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); n- G/ T2 D2 X3 V8 ]/ r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , _ l, N0 |; D6 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 p0 k- `0 A7 J: _0 M) u' e ^
0x00, 0xFF); /* configure the clock for transmitter */! M5 q) |' B' e6 p. m8 ]+ s6 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ c& K/ E" j/ T) V$ U# x6 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - B' @% w" x9 d) e V# I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; r) B7 y) F8 O; a0x00, 0xFF);
( K1 F' e9 e% r! A! E d4 k* i! _2 S2 t6 v8 z6 Q& S9 M
/* Enable synchronization of RX and TX sections */ . @# a" W# {* {5 I* B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 _, `0 a6 w- y0 XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; W8 i# a8 {% n1 h7 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; K& R% }& p# H0 g* ^" j) E& k t
** Set the serializers, Currently only one serializer is set as7 p9 O* ]! y$ F) {0 R, e
** transmitter and one serializer as receiver.
' _/ X1 {; |, C' |*/
7 N( h3 Q+ o% f v H, p) jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 S. C `+ x7 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 |0 p9 @7 |* C9 e- ^& Y! O
** Configure the McASP pins ' G) e- c5 P7 ~
** Input - Frame Sync, Clock and Serializer Rx
6 @4 Z1 J: U0 l: f& j$ r2 }** Output - Serializer Tx is connected to the input of the codec 1 J7 z/ ]2 B& H) c
*/
[' f1 s& \7 W8 W; n8 A5 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; e# w+ L" o5 k) X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( [* T$ s' V3 g/ zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" X/ ]9 k. ^. e5 v3 t
| MCASP_PIN_ACLKX
# ?2 Y: ?& c/ `3 {| MCASP_PIN_AHCLKX
0 n- M: l6 a$ j" z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# K6 {5 X8 K" c: Q3 [! m# y$ [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " U. @+ R% ^! ]
| MCASP_TX_CLKFAIL
% x( P+ e0 c T+ t; Z. M| MCASP_TX_SYNCERROR
" K6 m2 `/ X( M8 r4 j1 ^5 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- W8 o8 V" K0 k6 n| MCASP_RX_CLKFAIL
2 h+ D, y/ b+ B| MCASP_RX_SYNCERROR
* _& Q7 J% w+ s& }0 _& z/ S| MCASP_RX_OVERRUN);
' c4 T/ B# ^- a} static void I2SDataTxRxActivate(void)
/ D2 G! B R" l6 q1 s* k- V, H{2 f% E. z& g' Z! y) e
/* Start the clocks */
! {, z0 F" w$ I4 `2 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; } L' d U" U& a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 f) k w+ C- n, b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; k" P9 ~' I2 d( Y
EDMA3_TRIG_MODE_EVENT);
( T T( }& Y4 r gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & H+ d3 L5 n# h, @. i) k9 b5 n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) b4 o2 z# p0 ^6 l. R' c. R; t5 L y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) _) _ m- x4 b$ |% w! Z# j) i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 o7 }3 S; ~2 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! U& m4 R3 k2 h V7 W, k, TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, w6 ~2 j: a1 U o& R; a5 n3 r* [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- \+ ]0 n0 y; m
}
+ P6 j! V! I, Q8 j. m! [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. d. M4 y. T6 k) ~! X
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