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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: e" X# U" i6 U) ?! finput mcasp_ahclkx,
Z% }% \- ^# E" K' T# a% H4 Ninput mcasp_aclkx,
. x; n7 ]* t7 T* `' Q( y) K0 `input axr0,
% `) }& i8 _; {2 U: P* `
" d, l0 N, j. r# \output mcasp_afsr,5 z6 a# D* j, O) D
output mcasp_ahclkr,9 f! D+ _. z7 y- @ q7 S$ A
output mcasp_aclkr,9 P6 C" Z5 t$ H: x# }5 ~$ R
output axr1,- n% I! U( f5 A) D" G$ u( N' n
assign mcasp_afsr = mcasp_afsx;
2 d V, h) b4 ]) Nassign mcasp_aclkr = mcasp_aclkx;
' R% ]$ f7 ?0 t% U1 w! _: }7 n3 s, Massign mcasp_ahclkr = mcasp_ahclkx;; }% @: t# T0 p! t; K; G$ H6 f
assign axr1 = axr0; 2 f1 g: k& Z4 S, [5 b6 N
2 `" U' \8 n+ d# k- D: e# X( j4 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & d0 t9 T4 S# D* C m
static void McASPI2SConfigure(void)3 Z0 c' N/ Q3 X8 i& a: ?) v% l
{
! X5 ^7 n1 L2 L! y9 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 M5 A5 P/ M9 ~9 k# SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. g* x5 Q' y! j$ pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& l9 R6 H L2 l8 S3 F$ gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- O- S5 m% I, N( Y& [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) `0 K" q0 t. G3 A# FMCASP_RX_MODE_DMA);2 V8 e. e! k2 i4 s8 i" ]" J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 b$ j. k7 N- b( J) c W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) d& b& n/ F3 H0 S- b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ t1 M) ~; i' h- R% |) bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ `* w7 Y) A$ k5 ? HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, Z, Z( V) ~6 y+ b) |3 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) y" n4 m9 d) @& BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 f3 g3 q1 [3 U2 `0 AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! P4 d4 D. x; C- ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& x' R! j. J; H) E4 q- P; l$ e9 l
0x00, 0xFF); /* configure the clock for transmitter *// x/ @9 j" q# J9 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ Q0 n; n. c$ J- `- r, f: HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" M2 ^9 w) C' O* g% iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% X5 t9 [0 E; z8 C% u
0x00, 0xFF);/ s! m" g$ [1 K* K/ t
- g# m7 e( y7 B% `! h. `
/* Enable synchronization of RX and TX sections */ 7 A4 n9 q; s; T6 ?% F6 n( t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; X% ]- j5 p5 i! J& S* OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 v. i7 r+ W1 oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ c% N* D8 W! D( R6 i$ i
** Set the serializers, Currently only one serializer is set as
! s7 y& d( T7 T @4 y [6 q** transmitter and one serializer as receiver.+ A$ X- X X$ G0 M8 |) L
*/% l) ]4 \' H$ Q& e) K% ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 d) [+ F* L8 A' j Y8 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) V2 T' _4 l. K; {
** Configure the McASP pins ( F4 [7 c. N2 ]/ H4 h4 j
** Input - Frame Sync, Clock and Serializer Rx2 ~; [$ D/ c5 v9 a# s! S3 l5 @
** Output - Serializer Tx is connected to the input of the codec . w! ]! y$ F/ l5 E. Q( M
*/
+ W0 z w6 i+ A9 t! jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 s; ]" y! e' |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ o/ G. L: Q) H( gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ?8 v: k3 b* I/ q/ S| MCASP_PIN_ACLKX
. M0 W+ N+ V0 o" A| MCASP_PIN_AHCLKX r2 q" ~! u+ L% Q9 O% i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" ~/ |+ z% }* J0 X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ] K/ n6 a2 J; U3 g
| MCASP_TX_CLKFAIL & ~( L: G7 c1 Z3 o0 \1 L
| MCASP_TX_SYNCERROR5 q! ]9 ~' Z) z- I& _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 y1 z8 k1 O( Z- n) ?' @
| MCASP_RX_CLKFAIL
2 G: L7 t" b: w: w0 j| MCASP_RX_SYNCERROR 4 u Z; S8 |5 ~; ]4 N
| MCASP_RX_OVERRUN);2 H! s/ n+ E6 p7 J/ E" v
} static void I2SDataTxRxActivate(void)9 e6 |5 c. c7 V3 Y; M& }) X# f2 J, T
{
) U- {8 S H$ _: Y6 e, T- H5 [) L/* Start the clocks */6 ?3 w- N9 n% ~2 Y/ D. U# C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% M7 G4 x" s' x% }3 T' a5 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 Z8 I6 \- n3 Z/ L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# n$ O- @' l- M% \* y, Y
EDMA3_TRIG_MODE_EVENT);& |# A1 S3 S* t. l3 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 T, n, V. d8 }5 Q! z* WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 n! Z( ?1 _! V+ w' ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 U: @/ r! \& |: F" pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( E6 \6 b( G1 f0 u% a O$ xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 K p, f1 }* K; Y% O0 V$ \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 V, Y' u4 k6 C; W' x! v; \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( ^. {7 ^+ }8 G1 y
} 4 ]3 d% [4 i/ ^5 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % }& O5 z2 e. Z h1 D
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