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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, Q* I9 a6 n6 N$ s
input mcasp_ahclkx,& y: Y, Y; u& m$ m6 K2 P" P
input mcasp_aclkx,2 w. T, ~( ?) v% N, U
input axr0,
: P; D8 u+ n+ K0 A3 ~4 g" O |' c' I8 o, x5 \
output mcasp_afsr,5 A* k# y4 ~' W [' i5 U
output mcasp_ahclkr,
7 M' a4 P: ^; Koutput mcasp_aclkr,
) m& l g) @! w M) Woutput axr1,8 r. E( D0 x; b8 M0 p& e' ^
assign mcasp_afsr = mcasp_afsx;
% Z) r8 x3 {+ U) Dassign mcasp_aclkr = mcasp_aclkx;" k* Z2 F( ?" P0 j; ~1 d; Y4 C
assign mcasp_ahclkr = mcasp_ahclkx;
; d5 z7 q, v2 C' W/ m# Massign axr1 = axr0; 5 V# K* {( ~5 V
$ k& F. }8 L: E D/ ~5 T& S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 q N) f, O) Wstatic void McASPI2SConfigure(void)
6 J- J% f& P2 I7 B" ~3 L{
" f$ t/ C! y, h' [& i6 a' mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ f2 A% c) q. l9 O. v" ^' P6 eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
O; w; B7 f) {4 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 T& G3 [7 J& n( _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! h! d7 N; [, f, sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
P. J2 h7 x* _( eMCASP_RX_MODE_DMA);
4 e5 S5 P$ c( G) P& T7 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) I( P, f9 z( W8 j* h' Z; M* t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; n7 d* v: ?# j8 j" h5 y/ c3 G' t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. s3 N( G$ d/ k+ }3 Q4 N7 L! Q5 B) _6 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 q, y$ a5 j! T3 c' d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + Y, z! M! n9 Y" ~$ R" ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 K1 |1 m/ M2 ]8 t0 {: DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' e' c0 L' T) m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 s+ q) g0 g4 C$ k1 g; ^: S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 y* e. }: z0 h7 H0x00, 0xFF); /* configure the clock for transmitter */
l* ]. A8 M+ O W, JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 l0 G! Q2 Z, ^* X2 [' k2 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 b- G/ ~( i4 G& h) K# w% `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 D5 S" }1 r+ W! p5 d) g; m
0x00, 0xFF);+ l8 a2 E- b7 f- J
]9 w9 G/ _+ c/ F; o/* Enable synchronization of RX and TX sections */
0 E- [! ?) r. D$ i( @7 _% QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 }# H+ M6 _! A0 c/ V, zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 \7 C6 |) O+ y. Q1 e" f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- R% n, Y; Y; _1 c; w' x" b
** Set the serializers, Currently only one serializer is set as
7 y" i: c$ }' G% X( B+ O" a4 [** transmitter and one serializer as receiver.8 U& z3 j/ g y( L9 T9 \# l
*/; _6 F( D6 p1 l$ B: K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& l( d# Y! ?" }0 G+ k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 I$ o' _( d. g1 [! z** Configure the McASP pins
7 B4 i, s5 f, i+ y! O" o** Input - Frame Sync, Clock and Serializer Rx
( A( ?5 v6 H5 O7 |6 ^** Output - Serializer Tx is connected to the input of the codec
* E& B9 Y6 _; [4 |2 c2 W3 V, G*/: X& W, R1 S; ~, D( z* ~* a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ M8 Q3 ?- u8 G$ ]- q0 ^* gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 c& W# C+ N8 ^) p/ j' p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 ]2 `% Q# g1 F
| MCASP_PIN_ACLKX
! d9 \6 O4 [: k1 q| MCASP_PIN_AHCLKX
8 z. P8 z8 }( s' o1 Y6 @8 [6 v3 i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" q8 ~7 h0 K% `# y0 r* g, E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 y/ `8 t6 O' `% T% G| MCASP_TX_CLKFAIL
" E. G8 b; y" d, R7 V' a| MCASP_TX_SYNCERROR
9 _5 G; k. [7 Y% C. }. [7 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / n8 A9 f, x$ p( w" T7 B
| MCASP_RX_CLKFAIL9 P8 V: w2 g1 W+ k
| MCASP_RX_SYNCERROR
l' H. f% h% Z( e| MCASP_RX_OVERRUN);
5 ]4 ]/ x( i: |* \! N4 S) a} static void I2SDataTxRxActivate(void)
/ R X- ?* E, M k* B( q2 s0 l$ c{
! G4 c4 |& N: y5 ^% ~( s/* Start the clocks */
[; }/ J! Q& `- L+ ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 [' \, _* V# e0 s9 [+ S7 }; z6 b( }/ `8 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( r" E* J8 f. D+ |' ]1 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 |, T/ r6 [$ z% Y1 V" KEDMA3_TRIG_MODE_EVENT);1 k V& F3 d9 k8 ?3 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 i- d; l6 r+ W# L8 T' IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' L! B$ y( M! }# S* m# G5 Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 f* {" L3 J$ \4 c3 I8 h& S# e& O3 [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- l" }& o. [. ^4 h2 @) Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ B5 K: U+ @3 ~$ h' \0 B8 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, M( y- ~" r' vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ X$ T3 i. U' X; I
}
|7 M2 m- p1 a, t. ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - M: n( g N- J& G
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