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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 y- l9 D( N) x" ^1 }input mcasp_ahclkx,. d# S: B1 F' `' {% v0 f
input mcasp_aclkx,
$ j& g! k$ V% c) O# q7 \input axr0,
$ G0 m9 {9 r3 P: ]0 k3 P
3 O. c0 J# z* h) W; d6 g- woutput mcasp_afsr,4 K( Q) Y4 v6 I* Y/ L
output mcasp_ahclkr, V3 u: c* V) }7 ~ c- u
output mcasp_aclkr,
5 F( i* E( L0 Ioutput axr1," @, M O9 d2 q# u/ j
assign mcasp_afsr = mcasp_afsx;
) w( p$ h% ?7 x0 y/ Q" Lassign mcasp_aclkr = mcasp_aclkx;
6 k; Q# L; x! e; m7 D# |, E. Uassign mcasp_ahclkr = mcasp_ahclkx;
7 F3 @9 y) Z' z0 |% w) cassign axr1 = axr0; ( B3 y! W: d5 i; K3 o9 n) d
5 Y# e& _# B& r" I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 N ?) C& B# L4 ~# p7 R
static void McASPI2SConfigure(void)' m* r' v- o( [0 N/ p9 ?8 ^
{( w |$ d; @, B# r2 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 ]# q$ G! Q+ e# r9 O& F' dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ J1 n4 K* E2 Z" e# G5 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 ]! L! l7 I9 C+ j0 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& } t$ z$ c8 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! B3 f y! ^9 E0 o& n2 l8 ~MCASP_RX_MODE_DMA);
3 Q# |: ]$ N' J1 |3 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 I1 _: B* Z+ k! a* p7 x3 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, z3 y1 m0 X$ k' P' ?& ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / |- M& u$ q0 @% D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( E" i6 O+ z- r3 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 Q' z& d" x' F( D; }( y p3 A1 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" t8 P* Y; K5 W, O$ ~5 E* P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 G; T) r% ~8 ^: t) g: @1 \5 E- f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* w9 s/ o# d6 P( G' n. w4 ]5 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 Z% Y" u" f8 I
0x00, 0xFF); /* configure the clock for transmitter */
* c2 @$ D) Y dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! |: A) X7 x2 h U; x( r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ Z5 ` h0 {. D! }' \7 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ]3 a+ t+ A" N _0 E
0x00, 0xFF);/ Q2 M" v' [' e* {% p; O+ ~
/ p" S7 Q6 Q. i- h% c; ?/* Enable synchronization of RX and TX sections */ 0 {4 e8 `: L3 q( v2 U1 e2 |, _* M5 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 B/ \7 e# v% R4 h+ _2 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 D% o: S: G7 b1 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
Z4 Y1 y+ R( u** Set the serializers, Currently only one serializer is set as4 B, V. ^0 |$ H1 C) N
** transmitter and one serializer as receiver." U" Q4 T/ \% m
*/% }0 `; o+ ]6 `: m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. f1 ~( c+ q: i+ M3 O5 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! s7 n' T" i8 N; W4 N
** Configure the McASP pins
5 |4 j. m s' }' q/ N/ K0 `** Input - Frame Sync, Clock and Serializer Rx
8 K: I* `& r1 E5 F** Output - Serializer Tx is connected to the input of the codec 2 Z" K$ J! V. t4 Z, E0 O
*/
" e& j$ q: [- ]" }4 @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& o- ?, _' P- Y: C: RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- [) ^3 t3 |! @1 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ w& Q$ Y9 n$ P4 ?) p0 g, U! ^| MCASP_PIN_ACLKX* _2 g% f) n/ n3 p8 a8 A
| MCASP_PIN_AHCLKX6 x1 z2 n) v4 g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 {7 i; p2 u. j2 LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 v4 I7 V7 _2 A5 E! O| MCASP_TX_CLKFAIL 8 `: e, {. {4 u1 A" i" U: Q
| MCASP_TX_SYNCERROR- T; O0 P- T2 V3 y' Z; g/ \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 i8 s2 k* R; B6 m( n
| MCASP_RX_CLKFAIL
' e, T+ v1 ~( }# T' ^0 T Y| MCASP_RX_SYNCERROR
# ?2 \' | S8 N: M) Z- a| MCASP_RX_OVERRUN);# T; u/ R' m7 m- H, d* `
} static void I2SDataTxRxActivate(void)
+ \3 z0 I* A: g% q4 f{
5 K! M* t/ f r6 @3 P9 e/ S/* Start the clocks */
8 N" \3 @& i, u' W1 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 e4 A4 K0 j2 F( {0 e0 f2 ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 A$ d& x; F# h0 r I( a6 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ?1 X S! z/ Z" |EDMA3_TRIG_MODE_EVENT);
4 y" i2 R" S& ^/ P, X0 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 Z2 K# f7 k( P/ X! A8 {8 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& M% v0 P2 r. [$ s: R& cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! U9 f' @2 H/ c# ?# M: c. {5 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 g) H/ p8 y+ D1 p2 a" dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, v7 M+ v4 t) `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ |1 L5 v# _0 l% y. ^; s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& I D7 V+ g; h' h+ b. u. L} " r/ C. H& i; b( p% L( b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; Z1 Q9 ?5 V/ P/ ~$ B. l
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