MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
* f9 b* p) Z% x2 c1 q1 m" N, Sinput mcasp_ahclkx,
6 {: Y, u, n5 Y$ _- [% v( ]- {input mcasp_aclkx,
input axr0,
0 V2 L4 ~$ [5 p. d6 E( n
output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
, Q9 T/ A8 c) Coutput axr1,
6 E# ^3 t, G: E2 j4 K) |

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
' `2 {0 ~" X# Dassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

. T# M0 \. Q3 k$ p' j; p

static void McASPI2SConfigure(void)
+ ?& p! H0 o! i{
1 B; f4 W% ~, O+ A$ b& rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 K' r. X0 [, h6 b3 w  G* z3 U8 [McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 N5 X! e/ N/ `  IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
0 b; U4 h! G: f! R7 Z) n4 G/ HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 `4 @2 s" n% m9 _. u) gMCASP_RX_MODE_DMA);
5 T! }8 E& a& n6 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Q) z9 R8 ~& z' tMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) i: j& F2 w6 y8 D- EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- Z7 a# ]& K3 H" r) KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 T1 c8 M- K& T1 p  Y2 S' cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
( |6 X, `  S$ ~7 k" ?0 mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# a* |+ S" P" S: w  w5 P0x00, 0xFF);
9 z, X: ]! y5 M- ?. a: I# v
/* Enable synchronization of RX and TX sections */
1 x& Q, L' {+ i1 @) ~) i. b6 f; }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; T/ E( M1 o" q% L3 a2 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 n, t2 v: h1 R* L0 S9 L1 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
5 t3 f: y+ D0 X; y* _** Set the serializers, Currently only one serializer is set as
7 v( c7 H+ n9 d  _; u! s  @** transmitter and one serializer as receiver.
*/
1 Q+ w" `2 U: k6 _1 I3 W, c# C+ IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
8 _8 n) @1 o; S/ z/ i5 W& {6 U** Configure the McASP pins
5 Z9 _8 X5 w7 p2 o* ~, m% X** Input - Frame Sync, Clock and Serializer Rx
4 x7 _  v* p& {6 H: _* y% n** Output - Serializer Tx is connected to the input of the codec
3 y/ @9 Z7 m" t*/
/ f7 ~6 c- K8 a  b6 X3 N3 g9 E' bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 u( b" ?% i( b" U. p# MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
1 v; b, I% E+ j| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
9 A$ z. N. {; H| MCASP_RX_SYNCERROR
' O' n1 q; X! J0 \| MCASP_RX_OVERRUN);
7 o2 ]3 j0 l3 S$ y, D}

static void I2SDataTxRxActivate(void)
{
2 n6 c8 d, f/ N# B, f/* Start the clocks */
+ P* |/ V8 V' I; lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* \3 }! b5 v9 g0 C0 _$ OEDMA3_TRIG_MODE_EVENT);
' j0 k3 e/ ?) ~& B5 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* O2 }0 H/ x' p. f. O% X7 B1 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
. R. O/ B  S& jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) A7 F0 F- O& x$ D3 Z' v8 f/ d6 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 |- Y: d/ b9 r: k% d" S5 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

# f% A( r+ W1 v. U7 _

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.