MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
9 G3 Z8 d" D( Hinput mcasp_ahclkx,
3 o" y! z3 k& z7 _3 y4 E6 Dinput mcasp_aclkx,
input axr0,
) ]  Z) B/ }9 y$ b1 b8 l* W
9 R8 K- h" O$ U( t8 |! qoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
" r) `7 B/ o( T% f' {output axr1,
: ^$ f2 p3 k: w$ P

assign mcasp_afsr = mcasp_afsx;
5 Q. @- p  s( v- y! y' rassign mcasp_aclkr = mcasp_aclkx;
, K" ?" o7 N$ `" Rassign mcasp_ahclkr = mcasp_ahclkx;
: \, M; ~1 {9 L0 v$ {! Oassign axr1 = axr0;

- K  i% l& k4 n
6 R5 N7 ?: ^5 w" m' C& O1 N' h6 w

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
$ n, J- {, o; c6 v& ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" Q' r) p" Z& G- ^7 `5 g; R% VMCASP_RX_MODE_DMA);
9 o  k1 x* _4 v) O$ w# cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 j: H8 c/ S' ^1 m$ b8 }! {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! S: n& l# I: ]6 K0 I4 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 ~! _. R( W/ e6 `. h9 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
% x0 g4 [4 a* {2 x0 S
/* Enable synchronization of RX and TX sections */
  M- o2 ~( `! [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
% X7 _) |; Q5 o4 N8 qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ~% l/ G* {7 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
; }- k: h0 r8 S4 a** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
8 L, s+ w+ c, uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
  i( }# x) G4 N2 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
8 r/ ~9 l6 T% J/ _. P# Y7 t9 G** Configure the McASP pins
* c9 e8 c7 g, F$ W** Input - Frame Sync, Clock and Serializer Rx
- ?+ C8 Q% B5 x2 M8 z** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( R( o6 k7 ]" kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
4 e' I) J5 B3 n; ^| MCASP_PIN_AHCLKX
  V/ e  D9 G# ?4 x| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) l7 Q( H1 S- n6 Y2 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
2 t( ~& R: R& _| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
' O: B: p/ i/ Y| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
# r$ \" u6 G3 |% f" Z! n& O}

static void I2SDataTxRxActivate(void)
{
0 m. n+ p1 o" u3 s1 t4 _; z/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& |, k$ {1 {# Z8 l3 H$ hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
9 x4 w1 r; `9 N4 w! LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ \5 D* o. X( a/ j4 B  z' wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
6 G: c1 ?& n+ P. U) [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ Q7 O9 w, p! }}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

/ k9 c% s: ?) \& {, W+ u