|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 y9 F9 X8 O) Y1 S+ N3 x. L
input mcasp_ahclkx,1 ~. N, K# N0 M4 W8 m
input mcasp_aclkx,
, @+ H0 l+ [& M4 z: J! }. ^; i* Q: }input axr0,
* f& c. Q+ i" N8 C8 {9 y$ g9 V7 B5 g. F9 C* O: p
output mcasp_afsr,
2 c: Z0 M8 g6 p) Q2 _: t$ R5 Eoutput mcasp_ahclkr,
( \9 s: p Z: `! doutput mcasp_aclkr,
# F6 i1 o1 A$ p# L7 a* r5 Y, Routput axr1,
, Z5 L8 {# n4 o& n- }# {& t# K assign mcasp_afsr = mcasp_afsx;7 s( x- P6 l& f0 r
assign mcasp_aclkr = mcasp_aclkx;8 B+ w4 j2 P* h3 [& y1 Q/ {0 ~
assign mcasp_ahclkr = mcasp_ahclkx;0 k: ^! }" E2 E& |; e
assign axr1 = axr0; 5 v* q. h0 O. L2 T$ D- z# \
" l; Z3 `* q7 S6 Z2 X& l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- \* p6 c0 Z5 E$ o! V/ j+ H zstatic void McASPI2SConfigure(void)8 T4 V' E7 c0 f
{; `) T7 A: @' a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 l3 a! l' [* w) EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 i( ~3 `! F- z* V9 B4 ~& o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 A! X) X8 W# W# l7 TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ m% i, D6 W2 U; \4 D! K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" {; Y8 j9 E- S0 e$ g* d9 F9 qMCASP_RX_MODE_DMA);
8 U ?% O- t% _6 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% {$ T Q, d2 ]8 |8 a: K2 W2 e2 V: Q* d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& N+ c0 B1 P% s: Z3 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
T) M) H/ M% O. E1 c! @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 Z" E$ _3 E2 l( x3 X. QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " H3 R$ V! h; m6 X2 _$ S- Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! w3 J0 D! J) [/ O: nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
s# b# u4 H7 D7 Y: eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 s- l2 E, k, e5 `& ?, D" C4 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' M7 B2 y8 |5 N8 }, a0x00, 0xFF); /* configure the clock for transmitter */
3 G' ^+ t& a! x& y/ i) g9 P: XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ L$ k1 w2 D) V& ]3 I- n% X# zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / g" M# U3 W5 O' {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 H5 r# F: t% g5 @$ m3 F$ ?% s/ \
0x00, 0xFF);
, _6 ~, ^+ L7 I+ r
8 Q) [- ?& E1 \8 }/* Enable synchronization of RX and TX sections */
0 W( p4 N6 f7 U4 e4 e* wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" s% f9 I9 \7 E& MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 E; v# z( R( C2 `5 u/ YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 V0 k' u$ W# d! U+ h4 k9 h0 w( o** Set the serializers, Currently only one serializer is set as3 n: j$ q0 \( k" d: E
** transmitter and one serializer as receiver.1 b! J& l/ M j; |
*/
8 f8 @ X9 y, L; ?0 f; cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ F# s9 k7 y5 BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 o- s2 B8 w q/ n% T** Configure the McASP pins s4 u) T B. M& l
** Input - Frame Sync, Clock and Serializer Rx0 R7 ~ @) J! h1 u
** Output - Serializer Tx is connected to the input of the codec 9 y2 g. T8 U3 O. D; B
*/( h- b/ o) S1 Q$ \1 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ m9 z9 Y) q5 n& A3 V& [% `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* N6 p3 p/ {. A1 p6 i6 R3 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# b3 S+ l" y4 X% F4 O( d4 D; T
| MCASP_PIN_ACLKX% p) _2 ?" c7 [/ T7 y' ~2 m
| MCASP_PIN_AHCLKX2 S# ]$ H( j2 W% H4 E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& W* w n& \. l9 y( s3 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR A9 Q# f; ~% o3 G9 Y3 a
| MCASP_TX_CLKFAIL . Q* K" h$ E3 Z! H* ]# G
| MCASP_TX_SYNCERROR
8 _" X* z$ X1 M4 G7 u; o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 @7 m, Q* M% v5 e! E
| MCASP_RX_CLKFAIL
1 N6 W5 P4 |* A0 ]( ~| MCASP_RX_SYNCERROR + g" c$ n9 s0 f( ~7 \
| MCASP_RX_OVERRUN);
9 O4 s- k& n( g; _; U2 R, H} static void I2SDataTxRxActivate(void): a* C" [5 D& R5 y) \1 ?
{0 |" t- ], n: Q. p& ]: y
/* Start the clocks */
% O. A6 [+ K6 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( J6 R, x1 H. y' Z$ p# WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; s1 m) @# t# K$ T( r; G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: U4 [1 G, ^$ f
EDMA3_TRIG_MODE_EVENT);
! W2 ]" s2 E, [& ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* c8 p* k& P+ w! XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 Z6 T/ } d% F' J& TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% }9 C1 L- T& f0 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 C b5 q1 c; l X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! y6 Y/ ?% j, }5 B$ V) R- X5 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 v- G' D% y* F" S, _, _$ \: V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- z; @' e% k1 g) |. C1 l}
7 G! r4 H7 t& G' ^% i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! G M+ h5 ~- b2 P" K |