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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; L: h! r# {0 qinput mcasp_ahclkx,
$ G. [( S8 X) S; Zinput mcasp_aclkx,
, |$ Y2 d$ V2 P, kinput axr0,
0 ]7 k4 K2 j6 h2 g7 A! _$ L( O- A) J. I0 c5 @
output mcasp_afsr,5 ^! S9 Y3 {; E) |/ O+ B
output mcasp_ahclkr,5 I: k! I8 U$ W" s3 O. X# m
output mcasp_aclkr,- |% j+ X3 ^) t6 w6 b k
output axr1,
- s6 _- P! q5 J assign mcasp_afsr = mcasp_afsx;
: t3 r) }! E+ \9 f, zassign mcasp_aclkr = mcasp_aclkx;
( l6 R1 Y; W2 k- v1 D( K0 l4 c6 cassign mcasp_ahclkr = mcasp_ahclkx;
5 a# \3 u. m* ^; w0 |- ^; B* F" zassign axr1 = axr0;
5 I/ S1 f0 T4 @7 P5 S+ F1 u1 m
* e5 y. `. t: T) r; n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 N a$ T; Y. U
static void McASPI2SConfigure(void)
; U0 O1 y0 q5 r% E{; C5 f4 E n! T: J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; A3 \+ V& j) S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) @& ~9 f8 }6 N) B" W1 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' T; Y% H/ u0 e2 F7 O( NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( Y, o3 S, ^+ w5 \9 g6 \( ]( @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ ~0 R4 ^3 S, X. R4 {+ h
MCASP_RX_MODE_DMA);: Y) p" a% o5 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. K# p/ M+ z0 I& M2 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. H( B$ X* Y: F% l) p8 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ?& Z5 k7 j2 y, d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 h7 m6 u: @2 A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ T( v; F W6 ]5 A! S EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ n {- @. l8 N* l* ~; N2 i* b8 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 l% T0 W# C5 [) ^* R, w& S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + _- |( \; X0 g. n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 c& m. ^1 x# k% Z- o) y0x00, 0xFF); /* configure the clock for transmitter */
% S# P1 l4 L3 m7 c& dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& t' t8 `- J( l9 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ f& S" F' q9 A2 @$ q, NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 [4 J# `$ v% m3 x+ H# _6 v0x00, 0xFF);
) ]* i" v/ _# e- M: @
' d# ~/ D `4 F* I/* Enable synchronization of RX and TX sections */
" o. S( I! g$ C1 ~; Y& m% ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 Q( G# z* |- W+ P! NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 v. b2 r, o2 J8 s2 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' {% ]5 q/ @2 U- R, q1 x
** Set the serializers, Currently only one serializer is set as
% n- N9 I8 O( P* u* v! u6 S** transmitter and one serializer as receiver.! f3 l w0 \: l
*/
- s5 S s* E; a/ Q& P1 G7 ?' MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 U4 T9 b8 X. r0 { H3 c, ^- C, E0 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; v+ C9 Q% q/ A2 s% a& X/ V- K
** Configure the McASP pins ' i) G; o2 z2 C! |% R
** Input - Frame Sync, Clock and Serializer Rx8 ^; \- u2 m# W/ k& z" ^
** Output - Serializer Tx is connected to the input of the codec
. c* f) h* }& Z0 N* Y*/
& }* K" Z" E ^1 H1 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ u7 s7 Z. M" v4 ?/ L5 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" c7 |1 L% E/ A8 a7 V, [( [* U% q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) q, v5 f: @; K+ Y
| MCASP_PIN_ACLKX
u+ f; @- h4 b Z5 e( V| MCASP_PIN_AHCLKX
' t& S. M M) \2 B& c7 T+ F3 E9 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! s# b+ [8 D4 Q" _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# H: M$ H6 f! ^, q| MCASP_TX_CLKFAIL
0 ~1 C0 _. P: j' V' M4 v& @| MCASP_TX_SYNCERROR
! H# D" }* D6 s3 B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 A; P5 R* P% k+ v. f Q8 g) [| MCASP_RX_CLKFAIL9 i/ u C1 M" q5 P3 C4 I. q
| MCASP_RX_SYNCERROR 2 A4 a9 S& [3 d0 |1 j4 q! u
| MCASP_RX_OVERRUN);, K0 q }. N1 V. I# Y
} static void I2SDataTxRxActivate(void)
6 I/ }' v: B" {{
. W+ X; p# U7 {9 h' U/* Start the clocks */0 f! h2 M0 w, E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; j) z2 v: x, k& ^7 y& R2 W/ \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 u; e+ R' Z1 o. v8 e( oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! g' z( F& ?: R% c: ?! c3 x4 dEDMA3_TRIG_MODE_EVENT);8 V* I9 K8 p8 T" B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) i2 b5 D9 ^$ p& r3 C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ x* V" q# v- p. b7 _# @8 `0 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" a( O# ` u+ ~' [8 p! @5 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' m$ W& _' y- t$ s7 @( t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. } m. ~+ ?& o' J6 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; Y9 y5 V- ~- `, mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; u6 p) M4 j/ g5 ~( d7 y}
, l0 ^# C7 N ^3 W- c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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