MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" C1 i" T9 |# l0 B' ninput mcasp_ahclkx,
input mcasp_aclkx,
1 ^, z  c3 _' D; f7 H* \$ A  minput axr0,
! W4 R) E- ~! P
0 {7 Z0 S+ s0 |! P; ]' E/ M4 Youtput mcasp_afsr,
' k" w# B+ t) j- p: zoutput mcasp_ahclkr,
output mcasp_aclkr,
! W3 p0 g  U* a! l% E" M$ u* z8 uoutput axr1,
5 _9 G( U. o' K' T+ L3 E

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

( _% O# E; `) s( F* v
, l6 y0 {* e" k( N; Z9 T7 u

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
9 {, e$ \8 T6 ]/ i% }{
' D7 V9 p8 z: E5 U6 mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' s5 C. h& G# w; q$ V+ {+ {McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
% c* E1 L* R) x4 t5 C2 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( ~) e. s9 q, o: p  K( i' ~4 Z3 X. VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: L8 a+ |/ c; v! M. i; y; w9 M- pMCASP_RX_MODE_DMA);
, t4 w9 a& G. B+ V; rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ _( |% m+ T: |' h& Y" \1 T% sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. `) h) V: B) K$ J1 T0 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 E! P4 y8 u* E  ~% ?" l$ JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! [' c; O. g; S. ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; w5 m+ a# N5 Z5 w$ ?0x00, 0xFF);

/* configure the clock for transmitter */
/ W1 o) e5 M& x. V) O5 S# s' fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ I( d  l' E2 D3 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
- C2 f# l- E$ w9 }* c. @
+ H* ~! s$ g( Q$ z/ h( ]/* Enable synchronization of RX and TX sections */
: K) t. C% g1 Z2 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
, N6 o7 J) X% u/ Y+ G7 h: ]) hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
* N9 @; ]; K2 g: D! p$ m7 q. L** transmitter and one serializer as receiver.
*/
1 Z: R$ ]0 O( Y: kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. B( u$ y, J2 ^- ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
2 O! \) M; z( o0 d2 w# y8 C* a** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
3 m( R. i3 b8 k** Output - Serializer Tx is connected to the input of the codec
$ Z1 r, e* \$ X*/
- S/ s/ v% m+ \, r+ fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
% M2 g0 B2 h$ Z$ _3 }9 P| MCASP_PIN_AHCLKX
2 n/ Q0 C& A# ]2 T. F6 k| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
, p* U% j4 z. W- l5 \. X* G7 @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: i( o. b, z) G! u, ?; e| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
% l: \( b8 i6 @( q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 V# f* I9 U% V2 z| MCASP_RX_CLKFAIL
% ^5 z+ h: P# e( D: c* k| MCASP_RX_SYNCERROR
5 w  U+ {  E& v, z' p| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
6 ?$ f% e* r8 z) a2 I3 e7 V{
; M1 U0 n3 j1 V5 w/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ t! o  |3 s1 a" \# `  g/ v+ J* ZEDMA3_TRIG_MODE_EVENT);
8 X  T& _4 P, C1 _0 m1 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- g/ R4 B  E+ J' @6 M2 @/ F. ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
' E$ M1 o7 T" C3 {( }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* g4 ]; r' m- CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
( N) P+ T; s8 `6 b  W* eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.