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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: R/ z4 M3 \$ H1 v4 d8 z dinput mcasp_ahclkx,
, {1 c# h% s. D' Hinput mcasp_aclkx,
7 ~/ c: e, q1 J1 ~; C: l3 {input axr0,' A/ ~# J0 u: b( T0 t1 c& A7 c
- ?$ T/ B; M5 K* }& F. z
output mcasp_afsr,* w3 m1 f% @+ s, r) m; D
output mcasp_ahclkr,1 ]; Q3 S% W9 m( X( W
output mcasp_aclkr,# ^1 |0 q) R. q$ f
output axr1,, `9 D O4 M9 w( K6 a3 q
assign mcasp_afsr = mcasp_afsx;& r) f p$ e) _2 E- r: F6 Q" ?
assign mcasp_aclkr = mcasp_aclkx;, @7 I# m. G! V! z+ d
assign mcasp_ahclkr = mcasp_ahclkx;
: [( w/ I. A* D& Y; p; dassign axr1 = axr0;
5 S8 d t, g. e2 f. q1 \4 A6 U- {) p, j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! x1 @* f+ P& i* N5 j7 l# Astatic void McASPI2SConfigure(void)" g2 B, s3 o3 P$ V0 o, C! p
{
2 p% m9 X1 y$ y; N. `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 h* W4 q, G/ h. X- B |0 nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" X0 R l8 Y( G( oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 t7 {: X, N7 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: V& n+ i2 q: R/ \" l$ D9 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
t% E* V! n' h7 B+ L h; OMCASP_RX_MODE_DMA);8 K$ n- V$ d( n5 _& R, b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& M/ Q2 V. {9 m$ M5 M9 o1 S6 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* j; K# U. N6 l: G8 n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 u; P+ }; q. U* h1 W5 W4 {- a* ^$ jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) k% d7 z- g* j: X- bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 b! q% w; Q4 F! ]$ T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% |& F5 m6 @& Y* Q* cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 Y" Z c2 N; E. O, E8 B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . e8 c0 z# T) q% O" E3 c& C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: R" B& U* g9 a5 G0x00, 0xFF); /* configure the clock for transmitter */
6 u$ z8 i0 ^+ }) r7 o3 `# o1 q4 kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 i! B' R. Z" N6 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* a! _8 Y( e0 w6 t$ {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," Q! |+ g6 f: L) |* T& Q8 T3 \( ?
0x00, 0xFF);( ]! a' |$ B; {3 k* `8 h" v$ a
5 n4 A& v+ o6 [0 a8 B1 b$ r7 X a6 Z
/* Enable synchronization of RX and TX sections */
0 o" r3 [' s0 X5 tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ ]' ^1 S1 \# _+ b# |. TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! H% M2 X0 d5 ?7 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* e2 y0 {* V$ I0 v' v- F6 C** Set the serializers, Currently only one serializer is set as: g' P9 ?; l) Y4 X, q' }
** transmitter and one serializer as receiver.
9 ~7 X5 h, i' }6 t# ^& V*/5 R- y8 H# `% @: r3 H: l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, x# I+ w6 P' t: U: x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 y5 H: O( u/ v# ~5 f% h0 O8 `- ^' c; M** Configure the McASP pins
: z" O! i, @/ ]' F) m9 h/ Z; H** Input - Frame Sync, Clock and Serializer Rx
\# h& ~' V+ N** Output - Serializer Tx is connected to the input of the codec
+ k5 U: C7 J7 w# p- v- U*/
1 j) X L j+ `0 G$ wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 y- E! W/ ?1 o, B/ hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 B! Y- k- `9 \& n/ ~( YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 C* w) E. [1 I7 q0 F" t- K) R
| MCASP_PIN_ACLKX; S4 s" T: I, n. [9 g
| MCASP_PIN_AHCLKX6 a) H( D- a0 a/ \8 j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 @' b! D! K0 O3 K1 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " X7 f% @: n, y+ }' W( C0 U* N' q* p& [' g
| MCASP_TX_CLKFAIL
* k$ n/ T7 M4 e `| MCASP_TX_SYNCERROR5 M0 t# o6 l5 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 l0 {% y% o" u
| MCASP_RX_CLKFAIL/ O3 \* V$ J. X; M3 Z6 e7 i
| MCASP_RX_SYNCERROR * H) B+ Q) K u% Q: _
| MCASP_RX_OVERRUN);
' ?0 h) ?2 r! ]& F: f/ w} static void I2SDataTxRxActivate(void)# {; B {' b4 q* S. @5 q0 v
{
0 p; N- q) Y8 o& w2 q* ^/* Start the clocks */5 ^' \4 w4 m% |, N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 @* @6 y$ [8 L5 o' x2 Y+ gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" o: q$ h2 s2 z# ~0 l- D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# q% D7 }4 p, ?. `* K4 EEDMA3_TRIG_MODE_EVENT);
- a, i6 |8 G4 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# X( l+ H" H. P& U x. GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" r Z0 b! J2 H* g+ R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' n# y% {! e+ t" _1 ^9 @. J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 B/ L# Q0 W) i5 v0 _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ Z* ^' N. O) \2 A; V% f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ W( a* f' j$ o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; c% }6 F; p+ {3 | z+ j
} ( t3 \) L6 J7 R0 G! o+ ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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