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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, \7 t9 C$ i' P5 e
input mcasp_ahclkx,
" W$ z2 v* P" m$ Jinput mcasp_aclkx,
6 L4 ^; L) e3 l! E. u, }3 vinput axr0,
& O2 C2 Y! ~8 l4 ?( c: ]5 T; T6 Y) g C. c: G) O9 C; U" v0 N3 t% l
output mcasp_afsr,
0 t! l7 Q+ W2 C, {) z1 W Z5 youtput mcasp_ahclkr,# r/ S) N! w, V& k# u' w
output mcasp_aclkr,
6 A. J7 _! T5 o$ ~: eoutput axr1,- y; p9 u- T- B! D+ ^ F* M' N" C
assign mcasp_afsr = mcasp_afsx;* i) I, ?/ x; J2 l$ K
assign mcasp_aclkr = mcasp_aclkx;7 I# U8 c7 b6 ? ]9 l- N( g
assign mcasp_ahclkr = mcasp_ahclkx;% D2 ~, J' v& i* b* C
assign axr1 = axr0;
2 Y S0 A$ F# Z% m, n
- R5 @ h2 [# e7 m% D' D) Y3 M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - T3 A$ Y5 R' m( C
static void McASPI2SConfigure(void)
! ?# p0 H/ K0 q$ c! i0 h9 j/ I{ q, q3 ]; e% e6 M( {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ P N, Y2 W1 c/ P5 R' e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 E( S6 |7 p' z* g; K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, [- M- L8 R T7 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: E; y; i o, r5 s: {2 P: nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 q! g- f9 l' r, Z4 N& s. N% T8 jMCASP_RX_MODE_DMA);
u3 R5 W% U* U: r: V' H' JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, W3 F# H/ W8 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( |7 y' u/ Y2 x1 K) H% C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * D! Y; @" `+ g9 h8 ]7 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* t2 n, _7 { z8 y1 C5 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# i* X/ ]; i; c! i% n8 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 Y) J1 k: V- f. m' z8 N' Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 S) i& X# r. I) E# s! t: ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % g' N3 V7 O" f) R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) [+ L {4 T( l0 a5 J# v' B' s' I
0x00, 0xFF); /* configure the clock for transmitter */
5 l! L1 ~) v9 ~' N+ hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 y7 W( R$ v, `! dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 t2 R, g) E7 c' e- S; Z* iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 z' {& @4 I1 E4 E2 o) B0x00, 0xFF);; S! ^* [, H4 g: M- |7 M
$ O& q: ^$ t6 S, ~
/* Enable synchronization of RX and TX sections */ & b, V5 {" _! T5 {# k1 s' _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# \, L" N% x) m* Y2 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); K) f0 m% a/ L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# P- \ ?! D! R7 q
** Set the serializers, Currently only one serializer is set as
3 Q- H8 N- t0 X, Q** transmitter and one serializer as receiver.
7 j! f* a2 B" ^3 s2 y* \*/( x( ~, v# [, H5 y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 F, C/ X. h' t9 F# a% T' yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- Q/ `- V8 e- Z4 c( C** Configure the McASP pins
7 p, I% u( U7 c0 g# |4 K. i9 S** Input - Frame Sync, Clock and Serializer Rx
& d H1 t0 N; Q' U/ a0 g _+ m** Output - Serializer Tx is connected to the input of the codec * V1 v4 Z0 ]) N( J9 N
*/
! n( v ` }5 Q. W. V T5 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 Q: |, B; E) b j1 u& JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% h) Z+ A7 `6 o" o# ~4 c; u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 F1 Y4 W7 _0 f: t) \| MCASP_PIN_ACLKX
$ W8 a9 ]8 s( G1 _! s3 x! C. K| MCASP_PIN_AHCLKX7 f1 K$ X# W1 @1 `; v+ d7 o- _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 S) M( `$ E' M% a% wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 R; E# L O+ w% K1 o5 N9 ?* a
| MCASP_TX_CLKFAIL
" @6 p3 U! T$ p# A" n) P| MCASP_TX_SYNCERROR
; c8 ^4 Z6 v/ X- q! u: `- L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 w* q% c8 \# R
| MCASP_RX_CLKFAIL
# I; o' ^; P& ~3 s" |$ ?| MCASP_RX_SYNCERROR
. c# }5 P; U1 C: D9 B1 l| MCASP_RX_OVERRUN);
$ o1 p& d4 F' b" x3 \* O" U} static void I2SDataTxRxActivate(void)/ e9 L7 J7 k! e; X8 Y: d
{
$ o9 _+ T8 ]2 n* a* v6 B, e/* Start the clocks */" q i+ G1 `: ]9 p6 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: q, u K6 Z6 {" I7 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 p" k0 @* L5 {. BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 Y9 q# ?) y% |5 V3 A& }# E
EDMA3_TRIG_MODE_EVENT);
' Z8 x: F+ D4 @0 j% XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! r) X1 |1 S' j7 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& {3 e; a& C0 B uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: |# @( F H7 K6 U' H7 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 I S* b/ |9 n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& j* H* \0 p6 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ W. I- ?( i8 x( z# Z+ U% kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. e7 m3 S: g/ I3 X" {; L
} 5 Z7 m5 r/ V3 E5 @1 G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 h: \0 q4 z" p! r7 p
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