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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. }+ R( @5 ], ]2 ?
input mcasp_ahclkx,: i( W8 M) G" d; K
input mcasp_aclkx,
8 x( D8 p/ J) _, G# y9 c: hinput axr0,0 |- W: `/ T. a4 b5 q( A
+ P" s. g+ E/ M3 {
output mcasp_afsr,
7 h7 S2 e. _/ G: Z4 e& s3 \- Houtput mcasp_ahclkr,
5 _8 p3 T* a! W X" Toutput mcasp_aclkr,
, t, _, N! }+ F) }output axr1," x3 F* S" R* V2 H/ x( D
assign mcasp_afsr = mcasp_afsx;
+ g, l" [8 ]7 W9 v9 O3 q3 Zassign mcasp_aclkr = mcasp_aclkx;* S8 p7 j( k: v
assign mcasp_ahclkr = mcasp_ahclkx;
# u: [+ V/ j/ i9 V/ B+ u/ ]- jassign axr1 = axr0;
; {3 V0 l/ M5 r. m/ j" W1 D4 |- Q4 x
" R. U0 S% S& o: u( k3 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . j/ u" [' I+ s
static void McASPI2SConfigure(void)
6 K8 ]7 f1 \% d0 K, O{
9 b/ i" l6 |# F; |. D0 g2 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 s v2 s8 S0 T x w7 p5 j1 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" U2 `% m8 }, w) E/ J0 V3 W( B# W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; C2 t c# t) |& ~5 G% y1 G3 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ J& m6 i" z% A) B, GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 M# j- b6 z$ H8 B1 w, |( h* d
MCASP_RX_MODE_DMA);0 c2 e( [7 `; b" V. k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," C' V$ d( j4 t* H( T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 ~5 r9 V3 R9 S0 c* ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ z6 Q: R8 ~0 j) z( Q% }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 C5 `' V' p' \8 E/ s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' D9 P* f5 P7 h5 k& R' Q& z3 R2 ~5 a9 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 F* k3 G% w+ z" L8 V8 o$ d0 hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# Y ^ S' V$ G9 P% P: v c0 C5 z# B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# [2 z6 k/ I" X( uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ ~# W& R3 N! C: _& @& k. f8 G
0x00, 0xFF); /* configure the clock for transmitter */
5 F- P) O& B9 `! ~7 i( |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- v/ `2 X0 B) n& F3 c5 g( bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : u3 ~6 I9 p$ o1 F; K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; i" O" ]5 T$ [3 U4 M
0x00, 0xFF);; R- z, Q- `% ~2 R
, a* g! ?$ y- }2 X6 p: {( k/* Enable synchronization of RX and TX sections */ v0 R! W7 o' u) J8 L d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# U* F4 ]9 C- E R4 d( @1 L* \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 Y5 M5 v& A! g1 T* q. L. I5 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ M1 s& V( ^5 p* {6 o** Set the serializers, Currently only one serializer is set as: T: U' g7 J) K1 m! O6 p
** transmitter and one serializer as receiver.
- h# L6 z* |* k4 L( k* O; i*/( z, ]2 T8 _" @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# J) N- J E5 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: j3 K& g5 R2 _) F0 s: G) n** Configure the McASP pins % y/ b* }5 P/ I& H, S% j: v0 H
** Input - Frame Sync, Clock and Serializer Rx1 u% @5 w7 ~5 P
** Output - Serializer Tx is connected to the input of the codec ; |- V1 Q- v- i$ C3 x' u
*/% F9 y* x) Y& t+ P- P" \6 k6 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! B: a5 M6 ~) N3 ?% p) iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" o3 m( v' T2 ~9 ]" _+ }5 p: o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 J1 w0 m! V- ?7 U o& O0 J0 R7 n
| MCASP_PIN_ACLKX/ ?% O6 R+ _: G) a
| MCASP_PIN_AHCLKX9 Z* ^# @; S) \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! I! k# d# c6 ]( jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 P1 f8 j3 r+ ?3 R! ?| MCASP_TX_CLKFAIL % M/ B6 E# m9 u( A
| MCASP_TX_SYNCERROR* y6 v- u7 b, a8 [0 [& S% j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 H" y( O# e$ R% Q! C7 L" @| MCASP_RX_CLKFAIL8 A5 N5 G2 k E+ b3 Y* M
| MCASP_RX_SYNCERROR 7 |: T7 D2 q3 E8 r2 ^2 k
| MCASP_RX_OVERRUN);
7 O5 S- T0 Y G, ]" m) B1 i} static void I2SDataTxRxActivate(void)2 N* E& v1 n7 \9 Z" o
{2 h/ T3 p; b5 O% q2 u
/* Start the clocks */
8 X( ], z& `: r4 h% M- ^+ N! ~# c9 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& p7 p6 P3 y- g- P% |9 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! [$ U+ i/ a7 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& g) N5 y8 I3 t+ z. b
EDMA3_TRIG_MODE_EVENT);
9 o# G: j. k. T7 C+ L7 a( vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ z8 J2 s& R2 c# T) }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% d8 | l# K- v C2 EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 E# J) K0 b6 [* VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: I' |2 H5 i% m3 k7 p: mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ e5 r" w% u/ U L0 b* h7 sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 F1 F% M: x0 V6 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 a6 b# j F" \}
8 H/ i( N5 \; h7 ]* Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # h+ l5 [- t$ r+ G8 E2 Y
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