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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! C2 U5 [+ k- F" R6 [5 M5 L0 i8 oinput mcasp_ahclkx,
g3 |4 \* \( Ninput mcasp_aclkx,1 J" k" b/ |. _* Q& c l4 s
input axr0,
7 X4 f5 T7 W0 x* d+ s
7 F) G5 |8 m9 O+ H* youtput mcasp_afsr,
4 N+ k) |' K3 H0 Koutput mcasp_ahclkr,
0 a i) B4 Q+ s4 Q+ b joutput mcasp_aclkr,
9 K8 R) i$ V5 o2 [# A. N) Noutput axr1,/ l( N; _8 V. |$ a! V2 |# ~
assign mcasp_afsr = mcasp_afsx;' z2 u C, }) c$ H& d$ D
assign mcasp_aclkr = mcasp_aclkx;
, M+ U! ?" |! H/ Y4 d; Massign mcasp_ahclkr = mcasp_ahclkx;% U( D4 x8 a7 j" H6 N0 I
assign axr1 = axr0;
/ n. z2 L n z) a1 y0 a3 x% j k- {" A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( `+ `0 A }8 Y$ [/ Wstatic void McASPI2SConfigure(void) k G' |. m$ I f$ y' D% i$ J; g" \
{# g$ q2 H2 }2 G. F* R; l* s$ d% C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) S1 k3 c; b& A g; N9 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& [9 e4 g7 ~) R; r5 X# SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! K/ `$ W8 c* y6 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: I! x0 Y& r5 W7 v" ~& YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( q0 h$ m- G4 Q* v- E
MCASP_RX_MODE_DMA);
6 v$ |. e: u4 v w; g1 q5 z! h/ uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 K3 X" b y+ L2 S9 e& lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 c; T9 w0 y1 h* e! ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. x1 M, \" s$ \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- i. R8 ]7 A' I3 |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( u; o* r" J; u1 e0 V3 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# q8 t# A" Q+ @: a$ ?9 V% xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. c1 ^+ @% \( O# Y9 {) K; K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 ]& }; l% y m% O0 {9 G* F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 s5 z, m# f7 |0x00, 0xFF); /* configure the clock for transmitter */+ m! P9 V/ A5 h% l j3 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) N4 n2 `7 D# b3 c- o, M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: O! N7 ^% |7 X" u3 W9 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- k$ u. u5 v. f7 R! X4 \5 @0x00, 0xFF);
2 T4 `0 ~+ q" u/ {' K" _: A4 C7 m i! z( B
/* Enable synchronization of RX and TX sections */
; J; ]9 f! G6 Y6 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. c, `% A# m6 P. }+ B" l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. W3 `( M6 \+ }7 A1 X- @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 M! q6 A& F0 `5 v0 |0 s** Set the serializers, Currently only one serializer is set as
+ d: D* U' y) p% e: {. j7 ]4 `** transmitter and one serializer as receiver.% k Z, x) J6 D8 W
*/9 P% z+ A3 W% I' D; |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( U \) K4 q1 z6 U9 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 H: W A4 a( q- d! o2 b9 S. j
** Configure the McASP pins + f- Q6 _0 t/ d# K; ^: U+ E+ ^
** Input - Frame Sync, Clock and Serializer Rx: J X1 m! L% P: J# t, `
** Output - Serializer Tx is connected to the input of the codec
2 K% L5 R- y) L) i2 ]4 p; F*/6 K7 z5 `+ \) t( T- Q. _- p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& }! Q2 V7 r* k6 X+ ]4 }( f, Y8 M8 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- d. F- ]( _! i" F" _9 L7 ?( v0 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, R5 i( H3 O Y' I$ }
| MCASP_PIN_ACLKX
1 k+ A2 r5 {+ U: R" y8 k| MCASP_PIN_AHCLKX
) Z1 j8 Z, S! d/ i3 E+ @2 ]8 `7 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 T) z4 O1 d' H6 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! l6 h. @ x& q: D| MCASP_TX_CLKFAIL * t+ _, P( ?: u! R0 b
| MCASP_TX_SYNCERROR/ |; x! u& P: x5 v5 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - F$ c0 Q9 w9 Z4 a( ?/ C1 k$ ]
| MCASP_RX_CLKFAIL$ F( N! @: D3 P: ]% _/ K& W
| MCASP_RX_SYNCERROR
8 H5 U T$ h, K" G: x. {| MCASP_RX_OVERRUN);
: c2 C/ x: k, J5 s% U} static void I2SDataTxRxActivate(void)8 y: Z& | |: a9 Y* S7 h( a& h) t
{* k/ o$ b% I8 T+ H6 j
/* Start the clocks */( u5 l7 q% f) m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
C5 ^: _5 ~3 c! a7 gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- B, j H6 e6 ~( ?3 j6 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( B, u D' K8 {& \' Z$ G( A' v
EDMA3_TRIG_MODE_EVENT);; D/ D( V5 @0 }6 T# [( b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 m( u. @1 `4 i, q2 k9 P3 H4 o* SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& C3 y/ I8 ~6 K1 ~: A3 j6 {& vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 k* D) F1 a% B9 M4 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- R) |- F' z( Z3 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ F; V4 K! U% r8 R5 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 ]' d. p6 S5 s7 y' g, b5 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" j( Q$ F; [/ A8 M# A: A( x7 {& Y}
- p: i, c4 H# T" [; i& [- t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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