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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( T& ^" g" S0 [; M6 ?" b+ ninput mcasp_ahclkx,2 J x( e1 V4 {
input mcasp_aclkx,
: E' Q2 X5 J# R: x' G6 g# e/ Z$ Qinput axr0,
0 |+ o& Y! Z2 W {. E' U. i- J% d1 q7 m" `
output mcasp_afsr,
; ~. c1 E1 m7 ]+ q/ K; b/ o( Q5 houtput mcasp_ahclkr,
, q0 T7 ~9 e5 k' V. Ioutput mcasp_aclkr,
~9 s" [% ^1 f9 V( X6 C7 e. Youtput axr1,
7 p0 g. j* p1 Z- A" V$ P assign mcasp_afsr = mcasp_afsx;
; \! q1 }: Q# iassign mcasp_aclkr = mcasp_aclkx;' M( g- @ ?) q3 x- o, F
assign mcasp_ahclkr = mcasp_ahclkx;& @" v+ c1 L4 e
assign axr1 = axr0;
3 [1 O6 m1 ^/ K3 F8 x i/ I& p" E. U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; Q' [: c6 N$ B7 s5 z
static void McASPI2SConfigure(void)
! C1 Z8 ~" f; k+ Y" r{; A* u: n u' h! m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% z, b0 A: y( a, w( D @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. B8 W& O$ l; K5 y: w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* p0 F# u$ b8 e0 D& I, h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 w# g4 l( { c9 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 h, g! l. W& wMCASP_RX_MODE_DMA);; G8 X) ~/ f; H& J* D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 v( c1 r' ?5 r' f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 m7 U5 M! w, F# i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 \* G) W H/ K, }" f0 ?# \+ }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 H/ C1 F6 ?2 N1 p7 ]% P" G# i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : R' Q9 x; F2 d+ s" W! ?4 y3 y5 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! ]: j* B+ ` o8 D6 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ V, } f b* p4 Z, N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 y* S; E$ W. a/ C, k& @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, U! c+ c+ e# K5 Q3 ?
0x00, 0xFF); /* configure the clock for transmitter */1 i& u- T. m& a' F% B$ s( l+ p+ h, e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 B4 I0 G. O m* c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / D! f( |6 l; R7 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. X. f' Q- J0 \
0x00, 0xFF);4 I( H3 B6 A: t6 D% {
9 z4 v& p- T# y! ]2 u/* Enable synchronization of RX and TX sections */
+ F/ g0 O8 m2 g( ]6 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. G* N) { Z7 J; q# N. \4 E; d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 d% k' |2 W3 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, t6 q9 `. h5 M6 a) z4 w) j* J* ^
** Set the serializers, Currently only one serializer is set as
1 T/ t4 ?5 [! c8 l( V** transmitter and one serializer as receiver." T* p( _; Q( G4 [
*/- Y) G5 H) G1 O3 {; j$ N. k* h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ k1 D: M Q3 c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. j% x" f- B1 g; ^" g
** Configure the McASP pins
1 `( z2 `# A; a** Input - Frame Sync, Clock and Serializer Rx" K3 e \1 O" x6 P7 D' o
** Output - Serializer Tx is connected to the input of the codec
; H) L @1 t0 C*/
% m- h) ^/ m9 |) O. n! G6 D& TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 K6 ]: O2 m3 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, v/ h* q" F: t3 S! m5 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) z" |1 x/ n& ~/ V& S| MCASP_PIN_ACLKX, R( h3 ^" ]( |7 G/ n9 o {, o3 W6 Y$ V
| MCASP_PIN_AHCLKX) Y! G# m1 v; Y; p' ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ N' \0 z/ K& Z" m, M. zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 E1 I* N X5 ?3 j
| MCASP_TX_CLKFAIL : Q% o/ |1 g" ?1 ]! z. h
| MCASP_TX_SYNCERROR/ ]; q- M# j0 c, Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 @. m: Y4 ?- Q) q& J0 ~| MCASP_RX_CLKFAIL
0 R% B4 A0 `) i3 E2 u$ g| MCASP_RX_SYNCERROR / x( k, T5 f. V7 i3 y4 S
| MCASP_RX_OVERRUN);8 l: j4 o, e/ f/ j' s6 M; |& e+ i
} static void I2SDataTxRxActivate(void)
4 V" y. H" D( M* V{
7 a! Z% m2 k: q( x# `2 x- o0 Q/* Start the clocks */! t/ [/ e3 [! h7 _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! a& N$ U: l0 @* F9 `- @: @2 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, O/ _, }+ h( d( `' f& u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 f( W( J" w6 w, g' L2 AEDMA3_TRIG_MODE_EVENT);1 W; L, H; I. e9 c* R5 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* b/ F: ]0 h; A) bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 G8 e7 X; E3 D! H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( E0 |: X q X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" |, N* h4 w: _0 A/ T% w, ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 p+ K2 J$ `# \$ p1 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* s1 Y4 t, P9 |8 _4 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- y+ }( [% a! |) ^' W$ e' ?
} 3 S( `: w. e- k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 g) h# O: s1 ?2 J
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