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我的McASP配置分别如下:
; x7 S5 e1 b( J; H管脚的复用设置是:
: k! v" G9 b2 J9 x/ R6 |& u6 ivoid McASPPinMuxSetup(void)) S* Z: `8 K7 e) K1 r" l& c# |3 Y
{
1 U! J) @. |- a- e, `8 s0 F1 E unsigned int savePinMux = 0;
! C y- B7 g7 a, S" g savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
4 c/ @: v. T* P5 ]3 p$ v7 t' z ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
5 ]+ h7 |% }* o8 \, ? SYSCFG_PINMUX0_PINMUX0_23_20 | \
" d4 r \5 i! X& }% E# M SYSCFG_PINMUX0_PINMUX0_19_16 | \
7 `9 b q. d% w5 ^4 D+ S SYSCFG_PINMUX0_PINMUX0_15_12 | \
V$ b M- V2 p. J) W7 v SYSCFG_PINMUX0_PINMUX0_11_8 | \9 D. z1 f/ @5 A( r _
SYSCFG_PINMUX0_PINMUX0_7_4 | \4 }. _" D7 N/ T6 r
SYSCFG_PINMUX0_PINMUX0_3_0);2 }# e6 M* s$ F/ Y- V ?
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \3 Y/ ]% u, C: v
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \2 k% ~$ A% ?, `3 ]. w; i
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
- }+ S. ^1 s& @, n" t PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \" l1 I& K& D2 B; c0 I
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
* A& l+ H# ]/ |2 ^ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \: W v$ o- _" c0 [: p
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \5 b1 }6 E( |/ |* H
SYSCFG_PINMUX1_PINMUX1_15_12 | \
7 l; K1 d2 X8 i# v% h SYSCFG_PINMUX1_PINMUX1_11_8 | \
" v) b/ E6 A% w" _6 j$ q SYSCFG_PINMUX1_PINMUX1_7_4 | \
6 E) S6 }' P, C! A3 V9 U SYSCFG_PINMUX1_PINMUX1_23_20 | \, ~# }( \6 a5 l
SYSCFG_PINMUX1_PINMUX1_27_24 | \
0 t( o1 {6 r; _: y* f1 p SYSCFG_PINMUX1_PINMUX1_31_28& D& ^& q, t4 h
);
9 L* I! A8 d8 W: w. c5 Q4 f! l HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
+ e! o n% Q! N' Z (PINMUX1_MCASP0_AXR11_ENABLE | \
1 \) H- J- m0 u PINMUX1_MCASP0_AXR12_ENABLE | \
7 C# y: h0 |/ B4 ?9 P, a2 h, ] ^ PINMUX1_MCASP0_AXR13_ENABLE | \
8 A8 R, c, f, }. b D" W. s: ` PINMUX1_MCASP0_AXR14_ENABLE | \ V, J# e$ u( ~
PINMUX1_MCASP0_AXR8_ENABLE | \
3 y6 o* I8 G1 ]$ i* O PINMUX1_MCASP0_AXR9_ENABLE | \5 x# c1 E$ P& p q/ m4 D& t1 y
PINMUX1_MCASP0_AXR10_ENABLE | \
* U* R( B* P% A% ^9 A2 N savePinMux);: W8 t. H1 u8 B4 _
} b" Q2 o0 i7 n# g) H' a
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1.McASPI2SConfigure(); McASP的配置程序如下:8 E1 Z" G' o$ V' h
static void McASPI2SConfigure(void)
5 M7 |9 [ E! U- t' M/ |{5 y$ j3 J. h- y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( A2 f: v* p, ? i5 s: v) H3 T! a4 l- H McASPTxReset(SOC_MCASP_0_CTRL_REGS);/ o K4 N! E: ~9 w3 H. x2 B/ {, N
, z+ ?8 S n. p, o8 D# Q
/* Enable the FIFOs for DMA transfer */
' Q q$ Y6 z) `$ [* J// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);- [5 M. o/ @! r0 F
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, ]& C* e9 j( x0 x& r c/ w! j% N' H1 ]
/* Set I2S format in the transmitter/receiver format units */. F! w5 h; b- M5 L! p: J3 a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 Q, r; o+ R4 s1 q MCASP_RX_MODE_NON_DMA);' \* S" l; \/ L2 \& ]3 b4 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) e; s6 v% ~; z9 G" F a# R MCASP_TX_MODE_NON_DMA);
1 _2 g0 y* \' O! f4 P/ |
, W5 \2 I0 S/ G% @ /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 B$ I' R4 n8 u4 e% } McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; f) c8 }: U! q; w, {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 ^+ \1 ?6 X/ d. q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, f; x; I+ c4 p, Y2 B
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
8 ]; m- L8 z4 M- g* y- G% O6 D8 J
& A/ r# H9 V9 k /* configure the clock for receiver */
" F; _, X/ j1 M/ l7 y- L5 E; u% W// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
1 T: v9 H. U y! Q* T6 m+ C: p McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 m& U, a$ n+ S* x McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' w% k! F. C# _( @! [( o McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 x0 `4 W0 L" u/ S
0x00, 0xFF);
* @8 h: i5 G' g4 r) \* F9 @7 S4 F1 B+ P1 D; i! B+ a& w5 K
/* configure the clock for transmitter */+ d% d; v) Z6 F9 y$ w
// HWREG(0x01D000A0) = (0x00001F00);
" G' g; E# Y. e* G% o/ X// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
: P0 t" m7 {; K, f+ F) O McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
- c) l$ v9 Q4 I7 ^% B McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* h( z0 ^) z; \8 I+ ] McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 F5 J9 k) \7 G2 Z9 ^( q3 t
0x00, 0xFF);6 d4 ^! |. R3 l9 w
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/* Enable synchronization of RX and TX sections */ # C% Z( R4 c! [% L2 I5 V& j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);1 O' \: v% z) Z, f
' f( V$ G' G0 k* Y& t3 J
/* Enable the transmitter/receiver slots. I2S uses 2 slots */# G3 Q) h7 J+ U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: y, D4 `" r- b$ t0 C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ z. A$ U5 }/ ]5 U% a- ^3 n3 f/ N& ~- Z8 c
/*" N z6 T S) ^( t3 P
** Set the serializers, Currently only one serializer is set as
+ `. v8 O7 C8 g: q2 J |$ n ** transmitter and one serializer as receiver.* E+ G$ N8 L" A* O+ V
*/; }0 i' h$ S+ c4 J \' w- Y: |* l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* Z+ O9 l! A9 r McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);/ i& s; [% Z7 l* J' h3 {6 i9 b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
5 y" _( e) y6 G, S+ `6 O1 R McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
: g Y' P) |( t0 y1 {& M% j McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);* R. q( A) f$ `/ h2 f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
5 _* i* j( ?/ U! d Y
" c' N+ N! r* |. U/ h0 C McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
+ F; I) G# n; k7 D: Y" m+ _& _" |* d8 h9 n! r8 l4 _
/*3 ~% h$ |7 P+ y( j1 m
** Configure the McASP pins 7 L- | @. N. |/ a/ A4 K# p P1 s
** Input - Frame Sync, Clock and Serializer Rx
7 ] y$ K A4 ` ** Output - Serializer Tx is connected to the input of the codec
2 s" U1 j+ G7 O- G8 W/ _ */8 V* T1 y0 `+ F' b1 J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, G8 n) m2 e/ r4 a McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,2 ]+ ?1 u2 d" W. U
MCASP_PIN_AXR(MCASP_XSER_TX)* X- h+ P5 B, b; a6 I5 f
| MCASP_PIN_AMUTE1 |" i3 o$ t' [. M, m- r1 B5 j" @; V
);
) Z% W% g( d8 w7 ~9 j( B4 ]8 ^ McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,: h" m. w; c& O0 y/ f. A `1 k3 }
MCASP_PIN_AFSX
; ?& W4 q1 M) k$ o* ^1 q3 \ | MCASP_PIN_AFSR
4 @4 `8 R0 `6 Y$ O1 X* ~: R | MCASP_PIN_AHCLKX
; W! C! s& |# }& k | MCASP_PIN_AHCLKR2 N" S6 d" X3 c
| MCASP_PIN_ACLKX
+ W5 l2 I" S7 A+ k | MCASP_PIN_ACLKR) c8 G+ |! O! ?' l7 Z8 X1 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)% }* b: ^; q7 H% q
| MCASP_PIN_AXR(1u<<(13u))' c5 B' M( }) e* P( x" J
| MCASP_PIN_AXR(1u<<(14u)). l# |, a ~5 y0 c: d; X1 x
| MCASP_PIN_AXR(1u<<(8u))
8 v1 ~: N9 v. s( d& q1 M | MCASP_PIN_AXR(1u<<(10u))+ p6 `& M; C/ ^, X2 \
| MCASP_PIN_AXR(1u<<(11u))+ Q3 y# \+ u9 g- N' T% v2 p
);
; g, d5 L/ h7 n% S. o: z& A# N+ L- j9 g0 [: `8 I
/* Enable error interrupts for McASP */
% `8 q# t- g& i$ W McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
5 u: n: m0 O. q MCASP_TX_DATAREADY
. }/ L G8 S& X- O% G. u' H) U; S | MCASP_TX_CLKFAIL # O+ D# }" A2 s! Y. b: C! W
| MCASP_TX_SYNCERROR2 g, h; `" w( i0 E# c1 f
| MCASP_TX_UNDERRUN);
) B" O6 v$ X* H& D/ T
5 O9 @. P# T& @! _3 D McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,1 y; m- z$ ]3 }6 q7 X) ]9 d$ T
MCASP_RX_DATAREADY1 ]9 B& m% H# k/ E3 M8 R
| MCASP_RX_CLKFAIL) g6 p9 ? I# ~( j. v+ B, y
| MCASP_RX_SYNCERROR
+ G# E/ U7 V+ N; ^. I4 \' } | MCASP_RX_OVERRUN);/ j0 P2 Y( K2 t6 S) `+ h, a! F
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR. V$ C0 L3 n# _1 Z R) H
( g# \' P. e" }3 ?$ ~3 {# I- F}
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2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
' K) G* R$ S0 `- P" ~2 P! m; x, Bstatic void I2SDataTxRxActivate(void)
, ] V9 D' m" C{
: p. L- C1 ?2 L. S* y S* _' [ /* Start the clocks */7 ?( `7 D, M6 n% \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 Y& I+ ~4 X/ d& j McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
$ X B! |( s/ s: b
+ ^1 P, O( V: L! X /* Enable EDMA for the transfer */
D. A$ L9 O1 E8 ^. Y8 Y// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 U5 Z. p# f7 D, E1 a% Q- f
// EDMA3_TRIG_MODE_EVENT);+ J q+ V5 B4 g" z8 X* F
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, K; l- ?( Y' d0 O1 v! o& R
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);9 Y; y, r& f3 A
/* Activate the serializers */
, R+ W! D! X. _7 ]+ h McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ a* |% W( A# s! H" j McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);) B" d" F; V; m5 f. {* [+ h
/* make sure that the XDATA bit is cleared to zero */
& t- z# F5 Q* s: B while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);8 s& E- {3 H8 H2 B4 v A+ V
/* Activate the state machines */
- @) q. Y" k4 z$ K( L McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, Y& d: X" q1 a1 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& t* Z+ y2 `# A& \ McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);7 K. _8 M* Y3 @3 g5 k8 n
}
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