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我的McASP配置分别如下:
- B- X5 T7 f: K) C管脚的复用设置是:
# Q5 c) T! e5 E, nvoid McASPPinMuxSetup(void)" t2 d/ m, J/ [# L% v! w2 U8 \" e
{
7 Z3 `5 z1 R8 P& N unsigned int savePinMux = 0;5 B# s' v& _3 Q( Z5 d
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \9 g% d$ Z! `7 F' U/ ?3 T3 P5 d
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \% b+ n1 s9 [3 n" w1 y* h0 Q
SYSCFG_PINMUX0_PINMUX0_23_20 | \
1 E; y5 x# U, W6 K7 r* [4 [8 W" C0 ~ SYSCFG_PINMUX0_PINMUX0_19_16 | \
4 W7 c- T+ }+ k: {3 e SYSCFG_PINMUX0_PINMUX0_15_12 | \
4 E) ~" ?! U% w U! [% i$ j- o SYSCFG_PINMUX0_PINMUX0_11_8 | \- W6 b+ t# n, e# q
SYSCFG_PINMUX0_PINMUX0_7_4 | \
& b" @3 a; U2 u9 s" w( c' [) \3 x9 n SYSCFG_PINMUX0_PINMUX0_3_0);& w. \* \! j+ V1 \
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \# |2 W, i6 v- N! v; ~
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \# r; S. G9 j. [: R) N% f% D7 M
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \' g a2 \1 X A# I5 n( E: }- ]. R; g5 `
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
) j: ]0 a, v' j' V PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
" _/ Y; E' X! |3 V# ? savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \+ e$ Z6 q) r% o! l
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \, m; q1 w0 T% ^# T
SYSCFG_PINMUX1_PINMUX1_15_12 | \
) _$ ?! K, w* C: r: o* j SYSCFG_PINMUX1_PINMUX1_11_8 | \
( E. r- l) F0 f1 E+ \1 |) B; F SYSCFG_PINMUX1_PINMUX1_7_4 | \& A5 ^# c7 O' D @( \
SYSCFG_PINMUX1_PINMUX1_23_20 | \( k/ z7 H+ C' h/ S
SYSCFG_PINMUX1_PINMUX1_27_24 | \
( D- c: N; X) _& C% u( \& t SYSCFG_PINMUX1_PINMUX1_31_284 W f7 |$ R5 `+ `# ^! m- f
);
& F! S3 M% J0 K1 u& N0 \2 E% [ HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \5 Y) ?" D. `3 h7 V+ s( g o- G
(PINMUX1_MCASP0_AXR11_ENABLE | \+ I8 T8 \3 ]* c5 t5 j
PINMUX1_MCASP0_AXR12_ENABLE | \
$ A" N; h+ h/ s7 W PINMUX1_MCASP0_AXR13_ENABLE | \- Q: `7 r5 n, R/ b2 s
PINMUX1_MCASP0_AXR14_ENABLE | \" ?% A7 d) E, M) f0 f
PINMUX1_MCASP0_AXR8_ENABLE | \
6 h1 z ?9 y+ s, H PINMUX1_MCASP0_AXR9_ENABLE | \4 o+ p n( G6 ^, @7 L6 F5 T+ b
PINMUX1_MCASP0_AXR10_ENABLE | \
1 h6 d& g3 }- g1 w2 |6 K savePinMux);' }2 q- n5 U7 K+ I& p U! ^' E
}2 v" W3 T- |8 r
( d: z7 k1 u7 o6 w! U3 b! f
1.McASPI2SConfigure(); McASP的配置程序如下:
. H& Z4 ]+ K4 o2 v9 u9 wstatic void McASPI2SConfigure(void)
) N% @. V2 v& F T{. T0 h! Z) f; r& x% I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 d a( W4 x, V6 i McASPTxReset(SOC_MCASP_0_CTRL_REGS);
3 l$ H2 G# f2 _1 T9 n5 h- y; B% A- i* S4 a
/* Enable the FIFOs for DMA transfer */. u( J) E; p- c4 C- O5 R$ o7 ^
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);' Y2 C) f# V2 M/ t! J
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 d+ P6 B k0 s) w4 J( Z
0 z: p9 ]7 a% W% B /* Set I2S format in the transmitter/receiver format units */, @; z: O9 ?+ P) d/ P. D% O: x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' F6 V9 P) `7 m' l* ^8 s
MCASP_RX_MODE_NON_DMA);8 Q4 d+ Y; B! n U: V& e: G( l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: \ P- I8 `! V0 w* {
MCASP_TX_MODE_NON_DMA);
. B3 Z1 u7 |( M. w6 l
: H- @) M+ O' y" |- A1 R+ i /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 t! G, U9 J1 Z6 ^: E2 v McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) Z2 G2 N3 y! u- V) y7 b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" k/ k- R! J: H! ^' J2 S6 Q McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- Y! V7 [5 s. g# l+ ]( v0 d MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
5 F2 E2 Z/ K/ H y9 W" ?) C; l6 u& Q, o7 ^6 h( @5 p
/* configure the clock for receiver */+ A1 Y0 d" ^. r$ \ ^- J* D$ g, w1 q2 p+ E
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);3 i( P+ J: S+ \8 v7 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 ~3 C1 r7 z* x+ i5 {5 S McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);0 }4 i' |5 `) ~2 ]) i0 o6 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ z# ~# \& I2 u1 ^ 0x00, 0xFF);
+ V8 w% \# W( K- k. O
! P* V) J5 S9 C* a0 I2 u2 g /* configure the clock for transmitter */
" f' l. i% P( M0 [7 |2 `// HWREG(0x01D000A0) = (0x00001F00);& ~; @; S/ C" M. x; {$ d
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
% \0 P W7 n2 S/ J" J0 d$ G" D McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0); d' ]' X( y7 N9 L1 A; N; A/ I% n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);3 I# P7 W1 g+ c2 @1 ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) z3 E2 H8 x% N1 \4 d" D 0x00, 0xFF);
/ N9 `/ N5 G! K0 Q) t 7 e1 s( n# ]/ |; @ L6 P: U5 j
/* Enable synchronization of RX and TX sections */ # R+ `; l; l5 g& i# ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);; D9 c- _% {5 f7 U4 }
; `; W: x0 y- A! P0 j9 N# R /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ]1 d; ?. F7 z9 @9 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 `# F: X9 U4 G/ S/ {3 _; J+ T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* W% k ~3 d' |, c* ~% X( Q/ C
3 d3 g8 i7 { q* }: \; t /*
% T9 |. R" G3 Y7 [5 k ** Set the serializers, Currently only one serializer is set as( v7 W3 n1 N. i ~& K% n
** transmitter and one serializer as receiver.; i) u+ k3 x, k5 S; L
*/7 g: i' b7 z- B% d8 @- T# F- y& T: O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% |" r B4 \. ?7 u# Q o" l% r- R9 G McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);, l5 j% d: R: {& N( u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
3 c( v! @' X! D% |! ? McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u); Q( z) Y5 A$ j+ ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);" E* E: O& u1 k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
2 h( I0 N8 |$ g3 J- [8 @) R
& c! {3 V \0 G1 [" ` McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
1 S! Y/ V2 `3 d P1 V7 N3 D2 N1 T$ ], X9 z7 P& _$ |
/*- ?! W6 i( b% A5 K
** Configure the McASP pins ' H+ q Q+ W+ r6 s
** Input - Frame Sync, Clock and Serializer Rx
5 p, f) ^- }- i ** Output - Serializer Tx is connected to the input of the codec 7 f4 E' { [) U1 D: \$ h C
*/
' j3 r- y" f; B" F0 \ McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! c" N+ |5 J6 c( ~; { McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
* u% \+ i8 _) Z9 A. X( V MCASP_PIN_AXR(MCASP_XSER_TX)
8 N1 Y* Z* P* r. D4 J4 p, h | MCASP_PIN_AMUTE
. @' D3 H" N0 e" Y/ D# X );' o) P/ |& w1 p8 ]( Z' p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,& y# j$ v7 k- r0 J1 ?8 z
MCASP_PIN_AFSX
2 G6 N. x$ x8 z" \ | MCASP_PIN_AFSR! j" _$ Y1 o ]7 p% z
| MCASP_PIN_AHCLKX
1 d6 {( M$ z% I | MCASP_PIN_AHCLKR7 e! b0 K0 B+ Y
| MCASP_PIN_ACLKX6 q4 K3 q* P, d$ L0 n
| MCASP_PIN_ACLKR$ Z* |2 \. i: L$ `. U) v/ R
| MCASP_PIN_AXR(MCASP_XSER_RX)+ S1 \9 n9 A5 T y2 E* [- O
| MCASP_PIN_AXR(1u<<(13u))5 r6 O- r3 c$ B3 G; H8 K5 ~% V
| MCASP_PIN_AXR(1u<<(14u))
1 y# w9 H" D; b4 v8 H3 x4 u# C | MCASP_PIN_AXR(1u<<(8u))4 M* m" \/ M/ L
| MCASP_PIN_AXR(1u<<(10u))9 i) _- l7 _/ _; M$ `& K
| MCASP_PIN_AXR(1u<<(11u)): z( f1 l- S+ O) w% z
);
7 r6 J% X: c! i7 a3 l+ v* y
- I9 S5 ^1 x9 o/ A! w; w' ] /* Enable error interrupts for McASP */, U$ j* K! v4 e- w& V8 P& F. L) a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
! K1 W* v: Q! t MCASP_TX_DATAREADY
4 O8 Y U8 O: v) e _: s9 i | MCASP_TX_CLKFAIL : K0 r( u. @ Z% o* ?. g# }
| MCASP_TX_SYNCERROR, H7 g- q5 i, t) j3 x9 y. b5 w, s4 g
| MCASP_TX_UNDERRUN);, |0 [" b5 h; r
0 h: n9 h* _$ f# p5 q) F* f/ V McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
, }: U2 n* J7 `/ j/ F0 M) I MCASP_RX_DATAREADY% k7 V( U! F* W
| MCASP_RX_CLKFAIL
: g: [# s1 _1 ~6 ? | MCASP_RX_SYNCERROR
& Q+ @( B1 Q7 F* m: l | MCASP_RX_OVERRUN);8 d9 I y6 b3 m1 o/ s
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR, Z f2 }4 P0 p6 y) u
+ W8 E. k. L3 o5 x" K/ _ H
}
! m& X* `1 u* [0 E! P5 }& T# o. G* d+ q
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
/ n9 W. X% |0 b3 kstatic void I2SDataTxRxActivate(void)# w* {$ J+ b; z
{( v8 k' F* Z1 G# e8 c
/* Start the clocks */- O( z$ C7 t$ j4 d4 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 O6 E- C5 c+ j @ McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
' Z, `0 G7 I' K
: i2 d; `) {' ~9 D1 I6 `7 Y1 m /* Enable EDMA for the transfer */
3 n* @! e% Q# }4 J5 j7 ~! i# E// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- R2 @$ L" H0 |- ?
// EDMA3_TRIG_MODE_EVENT);4 o O8 b Q7 F) j2 K6 @) F' r
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 w. h \ A* I: h8 `4 T9 w9 ]6 ~0 @( x// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
( I6 S7 N; X- |% A- f. H. F /* Activate the serializers */
; m9 l* }: S! D. F+ t1 E; j! G2 s McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 V: f, o; ^8 Y; ?' t/ [ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);' q3 f$ W$ H$ g# L* c
/* make sure that the XDATA bit is cleared to zero */' O# N3 L' l; d# F+ x, F& _ K; j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
. \7 C; B+ E! D* m /* Activate the state machines */4 ]% m7 X/ u" j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% O3 I' y6 S4 g; D( x9 t* g6 u6 L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 y; J6 z" N. y" [- d- T
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
2 z9 y3 z: V8 |* }7 @& X: i) O}8 k/ a+ e& ~( ^% l1 u7 @+ E
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