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我的McASP配置分别如下:
7 Y* h0 u0 M% y1 h! p) S) s管脚的复用设置是:- P' s9 e- B6 m$ R
void McASPPinMuxSetup(void)
9 i" W( j. G2 N5 H, Y& y2 G{$ w) @! q0 q* }+ I& v: J
unsigned int savePinMux = 0;1 Z3 e Z |2 M5 m% v+ I9 E8 y6 K
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
8 C* g+ e/ m! j" z3 P ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
5 f' b% V/ p& g" v SYSCFG_PINMUX0_PINMUX0_23_20 | \( N0 t3 w% ]6 T/ [
SYSCFG_PINMUX0_PINMUX0_19_16 | \
8 G7 z/ M* `" s SYSCFG_PINMUX0_PINMUX0_15_12 | \7 D. R6 l+ @) o; f0 W7 P" ?( D
SYSCFG_PINMUX0_PINMUX0_11_8 | \
5 U9 H0 N- [# X. N SYSCFG_PINMUX0_PINMUX0_7_4 | \
& \3 }& q$ z; |7 k& e SYSCFG_PINMUX0_PINMUX0_3_0);
; D' r3 q& g8 I7 _. I V HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
7 W6 G0 s& T. }/ C3 a (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
/ K$ Q4 V$ N. a/ s PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
& L+ l* ~3 F7 {2 f7 N PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
# z! ]+ F3 a L3 F PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
$ S( k, i. c2 _% M9 x savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
$ r) {; i# U' B8 y* B2 l. M ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
4 l8 E. x L, v) T SYSCFG_PINMUX1_PINMUX1_15_12 | \
' W3 j8 G; U" Y- d SYSCFG_PINMUX1_PINMUX1_11_8 | \8 ?" k, y; z5 ]$ Y+ p9 V+ S6 l+ E6 [
SYSCFG_PINMUX1_PINMUX1_7_4 | \
6 I! @$ D9 \8 q n7 k+ Z SYSCFG_PINMUX1_PINMUX1_23_20 | \
5 L/ E* x) q1 X* [, s SYSCFG_PINMUX1_PINMUX1_27_24 | \
1 R8 Q1 s6 P' C SYSCFG_PINMUX1_PINMUX1_31_28+ |" A# l2 o* ~
);* ]0 ]% [' e1 e3 O0 {
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \6 C- o" M+ E' h" V
(PINMUX1_MCASP0_AXR11_ENABLE | \4 ?( U( ?, r0 W$ F+ D; {
PINMUX1_MCASP0_AXR12_ENABLE | \
+ F. o' g3 D( |% t5 A PINMUX1_MCASP0_AXR13_ENABLE | \
) P$ {+ Q* j Q- G J4 ]* a3 H PINMUX1_MCASP0_AXR14_ENABLE | \
* w% j d# w4 a3 D# J PINMUX1_MCASP0_AXR8_ENABLE | \: l9 c! n% Q) n6 V i7 J
PINMUX1_MCASP0_AXR9_ENABLE | \
* v m+ ]% z. W PINMUX1_MCASP0_AXR10_ENABLE | \
* o2 ^' f. R6 D$ c2 \/ r0 H savePinMux);
! i; p% J n# l) s( K0 ~}
8 g: N' q$ y. X; V) E' G
5 R0 [4 \, r3 W3 ~8 p9 U* O, w1.McASPI2SConfigure(); McASP的配置程序如下:
5 t! t- c% b9 z2 ?' c% a0 istatic void McASPI2SConfigure(void)5 E' W' [9 I( g( h) t3 }1 V
{2 L. A3 {7 N( S: K) X( u b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# w0 s7 [- O- s4 j McASPTxReset(SOC_MCASP_0_CTRL_REGS);' _# \$ B& K7 v1 B# |
! t* |% T# _/ }# v. ?) p& R; S" k2 T /* Enable the FIFOs for DMA transfer */2 Z: w, H- b" C: h' {
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
+ n0 D1 K. W1 L// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- S2 t1 ^' @' e
" e+ S$ a; |8 x. }& e/ e3 J /* Set I2S format in the transmitter/receiver format units */$ I' [3 M: _& z. Z% @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* F, J: A2 }: J) g* e. l1 p. J MCASP_RX_MODE_NON_DMA);
# h" N U u1 \, v McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! b0 y: {/ X1 F6 L& H
MCASP_TX_MODE_NON_DMA);
1 b& j* {: \2 g
5 g2 j \9 [ [. V9 v3 W+ V& c; T /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ~) ]9 m! ~- e, `# k6 H McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 ^4 P# X9 e6 ?5 Y9 {/ g1 Y; O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, d( n' v9 Y2 i- o3 l) L; g McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 N: l2 R) ~4 Z4 i8 C4 [ MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
7 I6 R9 i# {- G+ E- W5 [
' g& p# E. d8 j4 ?" B/ O /* configure the clock for receiver */
2 J8 x0 I. _" d1 _6 i// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);* ]( X' \: ~# I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: x2 |* o: o2 x1 t G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);' K/ m L: s- Q5 d% d [( A; U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 O3 V/ G& P& H 0x00, 0xFF);
4 Z( {5 D+ {! r8 T& k! }7 Z: l$ e
+ b O: _1 m+ M& t# B, c' l /* configure the clock for transmitter */, B5 r h4 C0 p' Q- Q }0 [8 h' y
// HWREG(0x01D000A0) = (0x00001F00);
% J7 f$ Y9 i" Y7 W1 r// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
o( p! p0 ^3 I- L1 e McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);. J x1 y" s8 u& _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 H; i( ?1 u% d/ I/ O2 l, Z# k McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 b4 H' |: L0 X2 x+ q 0x00, 0xFF);3 o2 \$ U5 ~7 O1 q6 S4 `3 K. \' V
% Z0 }2 w1 ?( ~! Z /* Enable synchronization of RX and TX sections */
/ b) G3 w* E6 T8 \+ E McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); a6 q- d3 S* e6 F. {
( E( s' d# v6 a/ B+ U0 w7 u /* Enable the transmitter/receiver slots. I2S uses 2 slots */! n- G- s& X- y* O6 r; m8 |% v* b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# ~$ ^. N" c a% i* I& n C8 {5 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; ]% y0 P8 `6 e
3 Y4 c4 x+ q' ~ W, _) m! H! S /*
* R, E) C* ]- K" T- t9 h ** Set the serializers, Currently only one serializer is set as
1 Y' E: ^" `' ]0 l ** transmitter and one serializer as receiver.7 @! q P% O' s$ ?
*/4 X, u1 N; a0 x' B" G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* N) |6 ^* ? W McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);' T- h* d, r+ R( L# \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);$ e1 B/ D& E6 s5 k, E. H; h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);7 G* p+ B N; Y5 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
) q& p" B) O" v$ G' G6 H% u& p E McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
, A! R2 {" H" x# Z" n2 c9 v+ ]+ @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
* Q5 a% [$ c" X) [1 R& e) Z: r
/*
) S$ |. o0 r6 u( Z6 y ** Configure the McASP pins
4 Q+ N5 W4 e( r* A' v ** Input - Frame Sync, Clock and Serializer Rx
8 E' z! b& [* h7 d ** Output - Serializer Tx is connected to the input of the codec
* a2 V0 {0 U1 c/ L( Y4 I Y */8 K: j$ {9 v( D4 ~' {5 B& H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ J& i L0 ~% O4 N McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
& v' I3 z+ p- U l5 q& E4 G MCASP_PIN_AXR(MCASP_XSER_TX), U5 F7 k2 t; B/ W6 }
| MCASP_PIN_AMUTE
& b7 ^* w. x* X4 Z; T$ i% g );0 A) e7 @) F7 ^& H4 }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,. X5 U1 H' v- r: }, m& a% f, h
MCASP_PIN_AFSX* Z2 L( f0 ?& u& p: g5 |# d+ z
| MCASP_PIN_AFSR; m( d8 u7 o H
| MCASP_PIN_AHCLKX
+ p v) o% `8 @: D7 ?! i | MCASP_PIN_AHCLKR$ X8 i' e* Q2 q1 G8 J; A: R; z
| MCASP_PIN_ACLKX
( i9 c. D" a/ w+ S | MCASP_PIN_ACLKR6 ], W: r6 x' Y& Q+ V. o
| MCASP_PIN_AXR(MCASP_XSER_RX)6 ~, r; R6 p+ K' @0 e* M9 t
| MCASP_PIN_AXR(1u<<(13u))
' Y) y: B3 l. U | MCASP_PIN_AXR(1u<<(14u))
; x$ \/ j" o# c' H, n6 S9 i | MCASP_PIN_AXR(1u<<(8u))
2 E% E: _2 O# k+ u$ _/ D. a | MCASP_PIN_AXR(1u<<(10u))
; w4 L' }; K8 a | MCASP_PIN_AXR(1u<<(11u))
8 ], s) U% c1 Q: }. S: i( B );2 ~8 E) M: n' {9 l5 j6 g
+ \' W) [/ l6 U: @. G) O /* Enable error interrupts for McASP */9 v4 `& K; Y& R5 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,8 D* F8 X4 _0 `3 {5 n
MCASP_TX_DATAREADY
% N5 ]$ J, U3 P* F4 z" [ | MCASP_TX_CLKFAIL
! F, w% y8 K8 X5 @; z- H, | | MCASP_TX_SYNCERROR
6 } L! k2 M. P( [ | MCASP_TX_UNDERRUN);
/ i+ d! f7 z: N8 T0 }8 c/ I
! Y' v9 @( Y6 s; e McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
% H6 e; Z. V$ P0 G/ W: b MCASP_RX_DATAREADY
$ t: T; O* q# \% R+ M; |- X& j) C8 k | MCASP_RX_CLKFAIL
+ o! O, `& R, x; L& |* s | MCASP_RX_SYNCERROR ) i: N' R- f1 a" G8 n
| MCASP_RX_OVERRUN);& n2 [9 R2 ]) W; p9 Y8 A4 [. f) l
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
$ Q( v+ \! @) d; S- _" Z) L, M8 [" b3 q# I
}
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5 G+ X4 _# L7 t8 b. y2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
* h' I" z, m' u; h7 b' _static void I2SDataTxRxActivate(void)
- R3 v9 r5 f. i! O# a4 j{% b9 h1 K) \' l; p* Q
/* Start the clocks */
+ R i. e* l+ f4 T2 f McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ r2 ^2 @2 C+ m) k0 B* b" e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
5 p* p( \ J5 b
4 T9 d/ d& H) g z8 { @) H /* Enable EDMA for the transfer */- k# K9 K3 t$ x+ Y4 c/ M5 F- W
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" O) g" E+ [* b- D5 r// EDMA3_TRIG_MODE_EVENT);
% `5 r. E" y, o% [// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" x! v( P4 p1 m6 T6 `// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
! @: \2 X$ d6 C% l: t T* s /* Activate the serializers */
+ o A( B) U3 m+ |! A5 M( ] McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ r- y* `5 p% ]+ V/ n- T6 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);7 y6 {7 R0 Q8 q
/* make sure that the XDATA bit is cleared to zero */# }. N _! @: U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);* }# N$ {, h8 ~( b5 K0 e: l
/* Activate the state machines */% ?; Q* z* W" M ]0 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: }4 M x% [' d McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 n, y7 J. a5 G
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
$ H0 `) t0 c+ u" Z8 z D6 ]& [5 O}
+ H/ m" k- B/ }+ h/ L0 l. f0 K3 v8 x1 p8 u2 ^ P3 k6 N; L* [
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