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我的McASP配置分别如下:1 \6 \! @' @5 v. G
管脚的复用设置是:5 V6 w) X) l' J7 s8 G5 i6 J% Q( S9 n
void McASPPinMuxSetup(void)2 v9 {/ `1 j0 B2 N
{: ?: X+ x6 F& q! P7 n! \9 k" C
unsigned int savePinMux = 0;
* T4 {5 k3 y. ~' }/ F savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
3 ?) E3 @; n) X% w ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
* \+ k3 b% w9 e SYSCFG_PINMUX0_PINMUX0_23_20 | \2 z5 f0 s' a& p3 \2 T0 [* A" `# S
SYSCFG_PINMUX0_PINMUX0_19_16 | \
" u" l- K! e( q SYSCFG_PINMUX0_PINMUX0_15_12 | \. B; u8 s# E6 _
SYSCFG_PINMUX0_PINMUX0_11_8 | \3 d- X9 C3 ~8 j' y# l! E z
SYSCFG_PINMUX0_PINMUX0_7_4 | \
7 o5 x; B% ^2 p* u; l0 _$ E4 z ? SYSCFG_PINMUX0_PINMUX0_3_0);% e: X; {- P" |
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \# v& F) W8 |! J+ C8 D) n. h3 A
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \" i# r* k5 n1 ]4 r
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \( G8 E) s' c, l
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \7 F. C9 E% P+ q% a
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
1 r0 e R2 {7 F% m, ] savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
7 G7 t# j* s0 S7 _* f, M; _ ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \5 x6 l: A% Y. f9 g/ ]) G
SYSCFG_PINMUX1_PINMUX1_15_12 | \9 n4 t' { p4 e8 }1 q) e
SYSCFG_PINMUX1_PINMUX1_11_8 | \
# y5 G' U6 _: l( z$ N+ _( X a SYSCFG_PINMUX1_PINMUX1_7_4 | \+ O, {; g; |4 P9 }" ^
SYSCFG_PINMUX1_PINMUX1_23_20 | \
$ ?0 ?5 x' O/ l1 p SYSCFG_PINMUX1_PINMUX1_27_24 | \# d8 p2 a9 \' c1 z2 i/ v! m B; |3 F
SYSCFG_PINMUX1_PINMUX1_31_289 r( @* h4 R6 K6 a0 F
); Y8 Q, F0 Q$ y; S
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \' Y, g8 C/ l4 E ~" N: [
(PINMUX1_MCASP0_AXR11_ENABLE | \
+ ?, e g" w- `5 e" _$ k- g PINMUX1_MCASP0_AXR12_ENABLE | \
* {* R( V. J$ m" p9 w PINMUX1_MCASP0_AXR13_ENABLE | \0 j! ?4 j; e: w$ Y& ~$ |
PINMUX1_MCASP0_AXR14_ENABLE | \. A# U, x. u5 ~
PINMUX1_MCASP0_AXR8_ENABLE | \. V4 U% W1 F& v o8 @5 [( b6 E0 U
PINMUX1_MCASP0_AXR9_ENABLE | \
. @& K/ W( [) e0 R" I; V$ X" \ PINMUX1_MCASP0_AXR10_ENABLE | \4 q2 ? w# a/ e7 x5 N' `1 H
savePinMux);' b4 d3 {3 f; y. N) r
}$ O8 q. N- V- X; B7 ~2 v* |: c9 F
; i1 Y% e2 I5 U, U
1.McASPI2SConfigure(); McASP的配置程序如下:8 k5 X$ p; G- }
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 u2 F0 N Y' i McASPTxReset(SOC_MCASP_0_CTRL_REGS);
! {, N) R {7 L: K! H4 `) V; R, j9 }4 r9 `2 w$ {. G+ y" I( X6 y
/* Enable the FIFOs for DMA transfer */# z2 Z5 t% G) ]+ S- A G
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);$ A2 u/ l9 t8 W" F' q
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
P" [6 q% z5 l; r6 y( L8 \+ }! W9 M) K/ g
/* Set I2S format in the transmitter/receiver format units */7 B& ~/ \; P# {% ~4 Z8 Z* e. P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" g' }) m# x) b1 d MCASP_RX_MODE_NON_DMA);1 _$ p- @% m& o9 T+ U# |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 r& e! R; K2 T$ m MCASP_TX_MODE_NON_DMA);# O ]- ~6 J8 Y+ d A2 N8 N
2 }/ O8 P5 i l# s+ P2 A( Q! r4 V
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' a9 d7 O- x1 f3 Q McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 ~6 [, Q5 X' ]/ `4 _: c7 T MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 C5 Q8 T$ U2 M, Z5 _7 v McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, W2 D' ?. t& y* h2 Q' H7 X
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
6 P& ^% G' {/ [+ \! Y0 T( v
9 t9 \/ l \; Z& o6 P+ w /* configure the clock for receiver */
1 O5 I2 a' J& g" y& @// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
+ y) l: D% z! i McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 Y% ?) A5 {( z# `6 c/ V McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& Z4 A. m% [( r( Z2 S: f0 m McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 h; w: M" `- q' ?8 G 0x00, 0xFF);
# [ A' R+ |; M4 S- ~ z9 }) F/ W+ z* l7 R# Q6 s
/* configure the clock for transmitter */1 @5 E" Y! }, A9 v y4 P1 H, |2 t
// HWREG(0x01D000A0) = (0x00001F00);
* F4 m/ I# I* X// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
! B% e$ j4 ]! R- f7 Q+ C0 U" R McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);8 G1 [7 `& X" r9 _6 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);3 I) F5 p- r; {- N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: @3 P* X9 P# d i9 e" v3 `
0x00, 0xFF);
' ~: u0 [, A& V7 Z; Z8 ?8 H
' [6 o! u, ^! l1 Y! ~4 e0 ^" X/ G /* Enable synchronization of RX and TX sections */
6 y% Y6 ~* o9 ^* d! l& i McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);: a$ e! f9 x/ j# l+ q3 v0 E
4 F, q+ b; Y& Y7 [
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- p: X/ T1 ~! g; p5 { McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( \: D8 ^* R9 I2 O( a. S6 c$ E9 w3 ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 j# U9 ^8 J) Q9 U/ W# L% z2 z0 E$ ?& T" M7 u
/*
0 f- `) i6 o; [: s ** Set the serializers, Currently only one serializer is set as% p$ S8 a# w B/ `+ ~6 D
** transmitter and one serializer as receiver.1 A- s3 N6 m) @2 g: Q
*/+ b' S- m9 m5 D1 u* B9 m- X& S% v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, O# W% h: W! a) [7 i' o# y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);$ y3 W! L# `/ a: \4 _0 B C# J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);, q8 D' q1 }- w( x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);8 _- {9 M. \- ^5 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
8 m: q( X' O% `$ j2 i5 X' m1 M% I McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);4 b) N* i! H% e, y7 T
) Z0 `# v2 W* x A) y$ }2 [' r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
W$ |! g% l5 \9 S7 f7 I# E/ v
+ S! z" U/ v! `1 c; @. _* ~ /*' G+ [: z% N Q. g5 q
** Configure the McASP pins
1 p5 [9 _% b( C+ |/ V) G l, y5 b2 K ** Input - Frame Sync, Clock and Serializer Rx8 o$ }" u$ @( \% \
** Output - Serializer Tx is connected to the input of the codec / N; Z* N6 Y1 E; J, F ^
*/
/ p' F7 t O' {* r2 Z7 d McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
?% }% f+ S. \ McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
0 i& o" \; U2 w% s MCASP_PIN_AXR(MCASP_XSER_TX)
3 W, H+ |. e5 E% a1 L3 w, r | MCASP_PIN_AMUTE
. z, C. Z2 K1 G# `$ \$ g" V! q* ] );
' m2 K/ r5 J Q* V' b4 ~) ?, ?- H McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,6 n) G# A1 a, |+ C* |: a
MCASP_PIN_AFSX5 K$ l+ q4 M; J. Y- u
| MCASP_PIN_AFSR8 J# I3 U. O d
| MCASP_PIN_AHCLKX4 K% v: i2 }& I/ L) s
| MCASP_PIN_AHCLKR
% ?' `; g) o, j: T, J | MCASP_PIN_ACLKX3 O# a: z$ W9 _6 l- ~
| MCASP_PIN_ACLKR
) E6 ]4 I: P% i- } | MCASP_PIN_AXR(MCASP_XSER_RX), n B- u4 |$ n+ a9 T- ^ O
| MCASP_PIN_AXR(1u<<(13u))
9 ?+ ~! B f W5 X, R3 a* k0 n% W | MCASP_PIN_AXR(1u<<(14u))
+ g8 m" ^9 A( d | MCASP_PIN_AXR(1u<<(8u))
4 ~6 k( F( Z/ H O7 z" M& e | MCASP_PIN_AXR(1u<<(10u))" E5 w( L! O. r, V
| MCASP_PIN_AXR(1u<<(11u))
$ P7 F% N2 s/ W: z4 K. k% B$ } );
! p* Z c' ]- j3 z2 {, y; ^
6 z# r/ w, F3 z5 d1 _2 s$ F /* Enable error interrupts for McASP */
" ^5 E8 W! ^/ o' s McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, N. J8 p5 r: @/ Q6 _
MCASP_TX_DATAREADY( C6 n3 Y3 K9 a2 R! [8 @, h
| MCASP_TX_CLKFAIL : P$ t) U" n( C" i( I9 r1 G# @
| MCASP_TX_SYNCERROR
5 H& B! J7 K% e0 r | MCASP_TX_UNDERRUN);
; L* l' z$ O9 D/ y* B) t( ~0 @
3 o! @/ k* k' B7 S! m' `. W McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
# j8 I8 c+ U# |4 A( s/ p MCASP_RX_DATAREADY+ C* O- H2 \' f" m K
| MCASP_RX_CLKFAIL
% i& x2 f% t8 X! D | MCASP_RX_SYNCERROR 0 B+ O2 J* q! ~' w1 h! w
| MCASP_RX_OVERRUN);
3 w! R. h% W% v& O6 D% d0 a" d//MCASP_RX_DMAERROR MCASP_TX_DMAERROR0 i2 H, A! z6 \2 }
6 A( u1 H2 k4 f) D" Z# Y6 ~}
" H& @8 Q! t' y X; O# c
N% \1 K4 b6 z! _2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
. q \9 _2 m* ~( Y. ?static void I2SDataTxRxActivate(void)* f1 U" Q* O" l: _- J
{/ V" R' T) @. ]% ?5 b
/* Start the clocks */
/ v; O% B9 p9 u( A, @ McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ U6 N: O/ D: @' y9 D0 J o' k' m& @+ `. b McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);- S8 }* G) M7 S8 {: P' Y# S% |
' \, ~2 f9 a1 T* ^8 r, v /* Enable EDMA for the transfer */
* ^7 D* _9 L; {2 o4 x% W2 u// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
U8 l4 P; m2 Q. R: K5 s// EDMA3_TRIG_MODE_EVENT);
7 w7 s+ o: G) i9 F+ I- O// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,7 S( h* f/ E6 q' M w. t
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
* [5 t6 H- R+ l$ H /* Activate the serializers */9 O+ a$ x" @, ]9 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ L, q/ S- p* D: ]2 b McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
" M ?$ j* N+ B; U @ /* make sure that the XDATA bit is cleared to zero */
; P( s3 g K. H while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);, @* Y. _, Q7 n6 a# @+ [
/* Activate the state machines */9 ?# Y/ H. n) ]1 x: ]7 ?# C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 Z' W+ I0 q! J% x1 f0 x+ ~- t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, F: m, p' Y2 d6 S) H; k$ k McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);4 h) e' ]% V$ }3 W+ {8 F
}
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