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我的McASP配置分别如下:% |3 \' O' `- Q5 }
管脚的复用设置是:
+ U3 A: l* \: ~ B5 w, tvoid McASPPinMuxSetup(void)
, {8 X) r. `9 T$ W$ ~' g{
& a8 f: s$ [/ ]5 T. a unsigned int savePinMux = 0;
. h; E. T! P/ X& U. f9 B. T2 X4 @ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
( y/ [" \8 u# G0 F% e- d ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
' o) _0 h# T/ Q9 w8 x SYSCFG_PINMUX0_PINMUX0_23_20 | \, H3 f( {* _( k |
SYSCFG_PINMUX0_PINMUX0_19_16 | \7 o8 T4 A, s6 \% q6 j/ j
SYSCFG_PINMUX0_PINMUX0_15_12 | \
6 q& J! ~3 _ R2 ] SYSCFG_PINMUX0_PINMUX0_11_8 | \3 q, ?, l; R1 { D# Z4 h/ `
SYSCFG_PINMUX0_PINMUX0_7_4 | \8 V7 P: z# v1 M# c/ | ?
SYSCFG_PINMUX0_PINMUX0_3_0);
* M7 Y; C C' M! P5 M1 e HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \ g# X5 m g: h }
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \6 {6 W2 ?/ p q( L1 A% ?6 `
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
, H9 t$ [. R& A( i+ W1 V1 R" a& ~ PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
, z+ @' [& }1 P, e# ` V PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);/ B# L8 D8 N6 r& R) w' f: h
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
; ?& U v$ M6 x- R* y: b ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \& _1 a' [* }- V+ j' N
SYSCFG_PINMUX1_PINMUX1_15_12 | \0 {/ L8 a- e7 Q( ^
SYSCFG_PINMUX1_PINMUX1_11_8 | \
* C4 o9 I- c) `5 ?4 h8 h6 D SYSCFG_PINMUX1_PINMUX1_7_4 | \
; W7 \- o ?# H- [1 Y* B SYSCFG_PINMUX1_PINMUX1_23_20 | \0 N; Y" Y$ U! Y) t0 U
SYSCFG_PINMUX1_PINMUX1_27_24 | \! o: p# A2 m1 D+ f4 m: d7 i* w) s
SYSCFG_PINMUX1_PINMUX1_31_28% e- K' H) b9 g. p( n
);0 _0 k+ O5 S# v8 _
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
6 ~; Y. [; J8 Q5 Q (PINMUX1_MCASP0_AXR11_ENABLE | \
5 v6 |1 E# t/ l5 K2 n6 p- C; _" y PINMUX1_MCASP0_AXR12_ENABLE | \2 \. M" s! W$ ~, ~( j' a
PINMUX1_MCASP0_AXR13_ENABLE | \! ~2 Y$ }( D! F8 j
PINMUX1_MCASP0_AXR14_ENABLE | \4 |- p# G: Z! H+ |+ w
PINMUX1_MCASP0_AXR8_ENABLE | \7 [& q- j6 a* n6 s4 E# {
PINMUX1_MCASP0_AXR9_ENABLE | \6 S" x* B$ h' p5 z$ N0 w
PINMUX1_MCASP0_AXR10_ENABLE | \
+ \" T0 C" |8 G8 l J- U savePinMux);
F* h5 `1 R7 z$ B* D- V& ?5 s$ u" |) s7 s}
H! H2 Y0 O0 d/ \7 {' ~: g& _% q, |! y4 K# q
1.McASPI2SConfigure(); McASP的配置程序如下:
! G1 G4 ]8 t2 Q$ T% W9 b R7 Zstatic void McASPI2SConfigure(void)( ?/ {" X3 J" t
{0 }/ f5 R* H6 U& o$ n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 ?, q9 l, n" g# o& h McASPTxReset(SOC_MCASP_0_CTRL_REGS);
5 k1 K% ]: { {! U8 e5 j. b( u0 m: P! V5 l; ]3 ^+ C
/* Enable the FIFOs for DMA transfer */
+ c3 c# [# x" |$ Z( w! r1 b5 B; m// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
9 }0 ~/ q* K: B. h% o2 u$ N// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ s( X! v4 i5 f# @& A5 p' U6 i" U( {( c
9 `' a( t5 J9 S2 q8 w$ F /* Set I2S format in the transmitter/receiver format units */
, f7 { P( I' B0 @, y McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% _. S1 h5 G1 B MCASP_RX_MODE_NON_DMA);
4 o6 M: ]% U% y/ n) r9 ]$ o McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- y) `0 W" q( |- ~ MCASP_TX_MODE_NON_DMA);7 ~! h1 e9 ^. g& K6 A/ {5 b
- o" g; d. d; M, V& O5 l
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */& D- R( H+ X7 O% n6 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 |' ~- j0 M, f6 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ E0 ]1 @9 D' [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: T% F- V7 Y0 g0 L4 e I. B MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
: f- A, _+ l) M+ ^7 @' ?8 H9 N6 O/ k8 C
/* configure the clock for receiver */6 ^( I( h3 q, k$ S
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
8 K/ [& T" C3 J$ s McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( w+ G7 Z& N: |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);* E$ N; n- u/ |, [5 T; V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ S0 ~: f- d3 I$ R5 ~ o4 K# X 0x00, 0xFF);3 X" B7 }' V0 o. R6 I
& V4 G! F' M* D7 m3 O /* configure the clock for transmitter */
& Y7 p0 Y! V6 h3 M- `; T0 Z// HWREG(0x01D000A0) = (0x00001F00);
1 {" ^) k, q4 u' h H// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);5 x8 c* O( ]% j( w9 _, c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);% Y' S- z$ V2 N, c" s& M. D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);+ y/ ?& Q) W' c3 `; S, x3 j! Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 z: }8 o4 h% S- u ] 0x00, 0xFF);4 S" C9 L& Y- Z$ w- p/ }$ e0 Q
0 t+ ^8 C+ @1 b1 R5 P2 ^
/* Enable synchronization of RX and TX sections */ # r3 f R$ S% ^( G1 @. {/ y4 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
& J4 z3 k& m4 z2 S* y% @9 ?* v4 g, K: B
/* Enable the transmitter/receiver slots. I2S uses 2 slots */$ O" m5 n8 L H v5 z2 ^1 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" V# a) k1 z3 x. t: @, z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ u1 }$ i3 b% v7 R0 Q
/ ]) r2 {2 ?6 z6 g/ R! H2 O4 _ /*
8 t6 v) \3 z) `& i ** Set the serializers, Currently only one serializer is set as
$ I" c6 o: o4 s ** transmitter and one serializer as receiver.
" y$ g- L) g0 k2 m+ a# l' h */; M+ X8 d! r: \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 C+ B, G: g4 e% I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);7 D1 r; N* Y% @" V7 c& e6 e o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);& a3 }5 a# q1 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
. z# B9 D# d, }' A; q McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
# _- @! K* M8 m6 N) k& X; Z- u* G' y3 a McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
( j' d# n% }+ d+ ^+ K( o. Q3 `& Y* P h; Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);" c: i: Q5 o; e$ ?3 l! _+ s! A4 d
% f6 h1 [$ ^% F
/*! B7 @3 x2 {. l* \2 U0 a
** Configure the McASP pins ) o/ y6 {& P5 l. q" X+ W
** Input - Frame Sync, Clock and Serializer Rx7 E; q4 O, `/ I& d( w
** Output - Serializer Tx is connected to the input of the codec . S: r. E' Q5 j4 R/ [" [
*/
" [5 i+ w" m$ d2 ^. F) N- n McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 R) ?# a4 V$ d9 u McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
% g) r9 V! P( f5 `5 n$ q MCASP_PIN_AXR(MCASP_XSER_TX)
. u/ T$ l4 o4 ]1 h& s2 i | MCASP_PIN_AMUTE
8 L! N9 y1 ?( _& t( c% s( U: Y; L. s );0 ^1 x& D3 j4 E8 X' L" P" B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,6 d t. l2 s$ [
MCASP_PIN_AFSX
2 c+ P: c5 J/ Z. a3 {4 ]2 m | MCASP_PIN_AFSR
6 u, @0 i3 Z2 v! x7 @! q. B. p | MCASP_PIN_AHCLKX
9 g- b. A4 C* g7 [, ~+ J3 e | MCASP_PIN_AHCLKR
% F9 ^5 P4 c! S- J. t | MCASP_PIN_ACLKX
2 p& }) U5 P; i | MCASP_PIN_ACLKR$ i) l+ |; F# t' M
| MCASP_PIN_AXR(MCASP_XSER_RX)
% d5 S; ]+ x7 X9 S# b- C! ? | MCASP_PIN_AXR(1u<<(13u))+ f1 w9 B, H+ G. N1 f
| MCASP_PIN_AXR(1u<<(14u))
$ a+ u6 K/ d5 n3 Y l, `5 e | MCASP_PIN_AXR(1u<<(8u))
^: w8 s1 M1 l, R | MCASP_PIN_AXR(1u<<(10u))' d0 z: O+ b! \8 R2 B7 M
| MCASP_PIN_AXR(1u<<(11u)): N0 f* b, |- Y# I
);8 O1 S% Z) Q/ g7 `7 y; ?9 W/ D
1 e3 A1 w$ T3 ^2 ~0 O /* Enable error interrupts for McASP */. |+ z/ S5 e" ?, {/ C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,; g& h- r) h% Y8 N! ^
MCASP_TX_DATAREADY/ [/ B( U) Z% V" |; ?& ]
| MCASP_TX_CLKFAIL 2 U2 s+ ~& z. t' ?5 ]; _
| MCASP_TX_SYNCERROR
( O; B2 b* _( A2 ~ c | MCASP_TX_UNDERRUN);
2 |% \) C# W: F& X/ {8 N7 ]9 i. a, c3 Y9 d1 k, p- D+ Q
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,0 E8 Y. g5 p) @7 s6 A
MCASP_RX_DATAREADY# M4 K" ^4 E U6 f! y
| MCASP_RX_CLKFAIL* b& r' p7 H4 R; F0 k, o. N
| MCASP_RX_SYNCERROR
* ~3 s/ S1 M9 B& k4 W1 Q | MCASP_RX_OVERRUN);) r/ r6 v) e0 R# g6 k3 g
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
& w4 t, U* x# x! K, e- E
) F- A6 p$ b) m* i9 X2 P}7 V! y$ T6 v; \( h7 T d
% O7 t1 m7 }3 U9 w0 v2 ?1 ~2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
3 i9 q0 B; u3 mstatic void I2SDataTxRxActivate(void)2 H# r5 T# Y2 Z5 U% [
{9 q0 a$ Z0 _$ B. K4 G- Q, g+ g
/* Start the clocks */2 Y/ S6 c. W) o% p' E! @1 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; j& E0 J$ v) A. b1 ] McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);! c9 W: H7 r9 w q6 h$ g9 Q" f3 j
2 j5 M( j. V8 x* q# p/ l /* Enable EDMA for the transfer */
: t1 r4 P! C: r// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& V, _# k1 l5 K) f/ H/ \' r
// EDMA3_TRIG_MODE_EVENT);* U: Z1 W9 [) V% ^0 V& e+ v
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% ]0 o1 O' r7 s1 F" Y3 L- p// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);) D+ r9 O6 y1 Q7 L3 y( b
/* Activate the serializers */
+ v+ w/ m+ P6 g7 q4 n( l9 q McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, ^+ t6 X. f8 g$ V+ G* }- u McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);% X0 ^ q) \6 z# ~$ @) C
/* make sure that the XDATA bit is cleared to zero */% k) n4 P# Z ~1 h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);; M m6 X7 s4 ?2 e* v) q& c
/* Activate the state machines */9 _2 u& ~* d0 J" j- [- m* c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. D, v, G! G/ M5 ~9 g# V1 E* f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) v0 d9 e8 a5 x) j W. P$ O McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
3 i5 x- W+ u/ h4 k, b* b# w3 x}
0 L8 |- F5 j$ U; n6 S
9 B# Z/ P# u- N$ J |
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