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我的McASP配置分别如下:) [0 Q9 ~, I3 H* s% L6 B3 ]
管脚的复用设置是:
; A- x/ L5 n, S# avoid McASPPinMuxSetup(void)
1 F0 K7 J; Y4 c7 i9 \0 b{
) [, f2 V8 e1 [/ O3 O8 G+ Q unsigned int savePinMux = 0;* v7 D! c9 O. P" K
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \ i+ f& m3 k( r9 B5 u
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
/ T0 h. X2 S5 F, `! n4 { SYSCFG_PINMUX0_PINMUX0_23_20 | \
$ F( W& h6 p9 A2 M SYSCFG_PINMUX0_PINMUX0_19_16 | \, `: y1 c; f: ?
SYSCFG_PINMUX0_PINMUX0_15_12 | \, V% u0 |9 [# P3 M
SYSCFG_PINMUX0_PINMUX0_11_8 | \
9 c5 ^# i( a e# J, i/ ? ~2 ]; f SYSCFG_PINMUX0_PINMUX0_7_4 | \
: p9 I# N/ P1 F2 m# S6 s SYSCFG_PINMUX0_PINMUX0_3_0);
! }4 J9 x: N M3 \( p; Z' e HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
; ]1 f# I7 f$ Q$ A, s4 c (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
7 K2 u, s$ u. B PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
4 e: n% m2 P- p5 x, J% f4 c, G# h8 g PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
/ v1 T* \2 W9 B3 j( A8 y PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);0 B, v8 H8 o9 J; h1 Q7 c$ f! k
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
+ @: [( q9 Y0 H- H ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \) V$ A* M( k: u: E1 T: V8 w
SYSCFG_PINMUX1_PINMUX1_15_12 | \
" E0 V; C2 _, L, |$ ^7 ] SYSCFG_PINMUX1_PINMUX1_11_8 | \5 D* {6 {& A/ {8 L2 X
SYSCFG_PINMUX1_PINMUX1_7_4 | \
# z$ \" J& U1 {% v) b A SYSCFG_PINMUX1_PINMUX1_23_20 | \
7 A/ _9 [2 }/ P. ~4 l2 V! l8 t& y SYSCFG_PINMUX1_PINMUX1_27_24 | \; v# F6 k- F0 J8 j+ }, C- n, p
SYSCFG_PINMUX1_PINMUX1_31_28
& I6 t) p1 L+ x, r );
- ]- K4 _3 @& p: n* a! G/ w8 D HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
! e( f) R# R9 U) s P/ i' u (PINMUX1_MCASP0_AXR11_ENABLE | \
' L+ l% T+ h5 y) V [+ ?5 c PINMUX1_MCASP0_AXR12_ENABLE | \
& H( L' C* X; v3 |' @ c6 W2 S PINMUX1_MCASP0_AXR13_ENABLE | \9 ^ f& I- t& N9 D# e
PINMUX1_MCASP0_AXR14_ENABLE | \; Z v3 R0 `& _6 w
PINMUX1_MCASP0_AXR8_ENABLE | \
9 s4 B9 N/ K9 l2 c! N7 ^ PINMUX1_MCASP0_AXR9_ENABLE | \$ k% i2 j' y8 B0 P/ R9 D: N2 \
PINMUX1_MCASP0_AXR10_ENABLE | \5 }; p4 a" M: A3 m6 Q. r
savePinMux);/ [: L2 A/ I! `
}" x3 m& ?' y, I
) n, ]$ _; L; V6 W2 [1.McASPI2SConfigure(); McASP的配置程序如下:
1 ~6 g5 Q+ N9 l; vstatic void McASPI2SConfigure(void)
- \+ P. d5 `/ J{
4 A- Z4 D6 j! N7 Y; H3 M" y McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& f! I9 m' J1 E9 l0 O McASPTxReset(SOC_MCASP_0_CTRL_REGS);
9 \% g9 ]3 b) e3 G; b: k9 g( N( v3 l7 H( D
/* Enable the FIFOs for DMA transfer */* W0 R5 S8 X( U9 L
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
1 h( W0 X5 ~. a# g( G/ c* d2 h// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( Z* Y, H. T$ T7 w U, m! b) v
' p8 j+ N. n: f( A
/* Set I2S format in the transmitter/receiver format units */
3 [2 Q) E+ H& L6 | McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( |- a% U4 {% W+ T1 t
MCASP_RX_MODE_NON_DMA);
/ U, k! U& D- `2 }& \; _- s McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, j- f/ H T Q' J* R5 T, M# M
MCASP_TX_MODE_NON_DMA);
' K4 ?% J" ?( V8 O% z" S6 R8 ~( O0 w7 L( E& @; Z0 V8 g% A
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 f" R& {7 K w, x( {* p, V; L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- G/ B$ \9 S5 R3 y. n MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 N) u9 J& E; \9 m* T0 e6 B McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * `. f4 M- J/ z1 ?* E
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);7 ^8 d4 j+ {( X( V x9 c
9 x; O: k0 C! ~! U- v /* configure the clock for receiver *// W, v2 `4 c! S; c" Z4 R
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
) f% x/ z, u' `" K3 e3 x9 I# t! x McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" s' h/ B* e0 ]0 m4 n0 L3 D McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);% J) [6 ~/ y; R) S9 n' r% Z7 c* t6 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: E* W: @1 E5 C! j: z 0x00, 0xFF);5 H7 W: F6 }) X- \9 f
3 A* O9 S& F! t6 \% ]5 ?1 S
/* configure the clock for transmitter */: A& u4 i7 v+ D
// HWREG(0x01D000A0) = (0x00001F00);/ r. S0 c1 Z) m. R* ]$ i& w
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
- [, M2 T& v5 q3 e, A1 i McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);) E/ U+ L/ \0 \6 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! i3 _# P9 T; j McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; \! ?+ v1 Q$ _" y- D! F 0x00, 0xFF);
# g8 s, M: Q! i( G |. v% q9 a
/ K5 ~9 \) l& M, v! a8 b /* Enable synchronization of RX and TX sections */
. j2 F, p$ g1 j8 o# c McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);, h# D* h8 b$ Q( A) ~' o3 ^: c; i
8 V. p1 K6 x" F w+ ]( u
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
* Q/ \& `: j* o' o8 p McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- T7 W7 E: J. }% G McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 g- S: C/ n+ M
0 h8 @2 n2 H: A2 b- l6 b. c' X /*% Y4 M( [! `% L1 Q( ]0 r
** Set the serializers, Currently only one serializer is set as) G2 q( n5 P* { I' U1 P
** transmitter and one serializer as receiver.
0 r% Y1 |& x9 F" s- H. b# I' R */; ^$ Z; @/ P) L: T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' v, u+ f. n) t f McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
8 Z4 ~5 j; _/ I6 n) H McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
" c8 ~- ?6 K$ I& \ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);- K% J8 ?8 ^' d5 I) m, [# F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);1 [1 r# a; r/ h; o. y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
" G) w2 m; J# Y- t+ Y) h$ q0 F0 h9 l( V' M8 f4 a- o8 }9 f) _! ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);9 Y& \& Q/ t7 A$ q$ {$ t/ a# |
- r! t5 N. b$ l- z
/*) G$ f7 k& n0 O0 w: W( P( ?9 }( o
** Configure the McASP pins 8 Y: S1 [* S* b8 `/ F, m3 Q* C
** Input - Frame Sync, Clock and Serializer Rx
0 z4 U* W$ }% `. @& r ** Output - Serializer Tx is connected to the input of the codec b# ]4 Y3 C+ I- Z+ C
*/
5 r0 n- H7 N R, w2 Y McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& e, w! J' o7 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
. x& l& o8 S, E2 M; q) q% P( J4 f; k MCASP_PIN_AXR(MCASP_XSER_TX)) ?0 Q9 Z2 f; g* g- [( ^
| MCASP_PIN_AMUTE
/ `* l: X, h: g# x! {. g$ @ );. u4 |8 }( c+ {! b0 |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,, j: [; ~% z- S
MCASP_PIN_AFSX1 ]$ _& J+ g# W6 \
| MCASP_PIN_AFSR( s* O( J& P9 [' x/ I6 a
| MCASP_PIN_AHCLKX0 s0 L' ?' S1 e* V
| MCASP_PIN_AHCLKR3 q1 n# D" F) s' f
| MCASP_PIN_ACLKX7 C5 g+ @0 P; k" w2 L8 G' w! ]9 C
| MCASP_PIN_ACLKR
! `4 u, O6 b, P( [( D | | MCASP_PIN_AXR(MCASP_XSER_RX)' L, H9 U9 i! u4 X: J* ^! s& ], l
| MCASP_PIN_AXR(1u<<(13u))
3 V1 o# }+ v5 w; u# X8 f | MCASP_PIN_AXR(1u<<(14u))
) S \. u8 \8 v | MCASP_PIN_AXR(1u<<(8u)): I0 R' i9 \9 B; ]7 X% J
| MCASP_PIN_AXR(1u<<(10u))7 [0 \) N& T; N' _" X/ y- f: `
| MCASP_PIN_AXR(1u<<(11u))
' `- y5 h# i$ c" B& G, k0 O; s );
7 _6 J6 |: K8 b7 g# @$ T) A1 H
& o4 O1 y* ], p8 { /* Enable error interrupts for McASP */
6 Z! n% a# M- f McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,4 ~, z, M; g9 F8 O- D
MCASP_TX_DATAREADY! L4 N# ~4 a2 u
| MCASP_TX_CLKFAIL
, m0 d2 X5 r7 w& P | MCASP_TX_SYNCERROR7 k2 X. B% u. [
| MCASP_TX_UNDERRUN);
- T4 y( r. b9 s4 L" s1 U
8 G& f3 m/ \6 B' A McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,( Q2 L1 l- `, _0 h: a/ P0 g
MCASP_RX_DATAREADY
# E) Z4 p& h5 z. M( g | MCASP_RX_CLKFAIL
% B3 s( j+ J E3 a | MCASP_RX_SYNCERROR
% m4 B. o! Q% C6 F) ]0 m# [" ` | MCASP_RX_OVERRUN);7 X7 A; q- J0 i* w8 |
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR# P4 J# g6 d" i: Q& j9 k R' w
' e; c! p. f" Q2 ?9 y$ A}
, H$ n. K# v% l) n7 d; H: l2 ?5 o0 ~* U
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句# @$ T; J) z% R* m
static void I2SDataTxRxActivate(void)- K0 s$ K# o r' H X ~
{
, f1 D( b! B. c: p; }) B+ A6 t /* Start the clocks */
5 v- q" I9 ~9 w1 H/ O7 {2 A McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); H. t. m0 q5 d0 u2 N5 z- d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);& \) c: o1 a3 a7 h+ A9 X, U
3 t' i; m- I$ U( k
/* Enable EDMA for the transfer */
2 j+ @- }1 u1 e4 l% j/ I' H// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% } e6 Q& ~# O( E/ U! c [2 H0 {0 Q// EDMA3_TRIG_MODE_EVENT);: E) ]7 B- s0 n9 D
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,; f) X# a6 t; V9 [- d6 b7 ?, ^9 o
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);. I) y; v" k& H: s |
/* Activate the serializers */ ?8 [4 N( b# M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 U5 @5 j6 P: o' U/ ^+ k6 D McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); a/ I u8 ~3 I' m; {
/* make sure that the XDATA bit is cleared to zero */
. x8 |; I7 K+ f% D8 n: T while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);2 u, N" L& g$ q$ l) o" H0 X
/* Activate the state machines */
/ C+ f0 _5 W( Z' k McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 b3 E1 H: r, N( u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- T* D1 j n' A# y/ x
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
: P" r, z' X* K# u! Q, m}$ [3 E& }$ [7 K v. I8 M
9 p) W& T( U+ x' [/ o |
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