|
EMIFANANDInit(NandInfo_t *nandInfo) { nandTimingInfo = (EMIFANANDTimingInfo_t *) nandInfo->hNandCtrlInfo->hNandTimingInfo; } 这句话怎么理解呢?谁能给小弟详细解释一下,谢谢 下面是对应的结构体 * Y$ ~4 Z: L2 t0 T
/ p8 b8 s& R4 p" t. x* P, s( U
( s( b; o- L" O; Y! Y
typedef struct _EMIFA_NAND_TIMING_INFO_ {unsigned int writeSetup; unsigned int writeStrobe; unsigned int writeHold; unsigned int readSetup; unsigned int readStrobe; unsigned int readHold; unsigned int turnAround; } EMIFANANDTimingInfo_t; typedef struct _NAND_INFO_ { unsigned int dataRegAddr; /* ADDR Register address */ unsigned int addrRegAddr; /* CMD Register address */ unsigned int cmdRegAddr; /* Pointer to Memory Controller Structure */ struct _NAND_CTRL_INFO_ *hNandCtrlInfo; /* Pointer to ECC Structure */ struct _NAND_ECC_INFO_ *hNandEccInfo; /* Pointer to DMA Structure */ struct _NAND_DMA_INFO_ *hNandDmaInfo; } NandInfo_t;
. x1 k; b7 j3 P
typedef struct _NAND_CTRL_INFO_ { unsigned int (*WaitPinStatusGet)(NandInfo_t *nandInfo); /* Timing info for the device and the controller */ void *hNandTimingInfo; /* Base address of the controller */ unsigned int baseAddr; /* ECC supported by the controller */ unsigned int eccSupported; /* Wait pin where NAND dev R/B pin is connected */ unsigned int chipSelectBaseAddr[NAND_MAX_CHIP_SELECTS]; m3 D- b7 k/ i; H
} NandCtrlInfo_t;
+ I0 z0 l4 Y1 }
+ D6 |0 b; k5 e! ~1 d |