EMIFANANDInit(NandInfo_t *nandInfo) { nandTimingInfo = (EMIFANANDTimingInfo_t *) nandInfo->hNandCtrlInfo->hNandTimingInfo; } 这句话怎么理解呢?谁能给小弟详细解释一下,谢谢 下面是对应的结构体 8 [ q8 ~& l$ P$ V# q7 V' y. k1 ~
2 M8 l3 B0 E' L) Y! N/ B1 R3 I R
7 O6 S$ X# \4 k/ W0 ~4 K6 J2 ~ X" m
typedef struct _EMIFA_NAND_TIMING_INFO_ {unsigned int writeSetup; unsigned int writeStrobe; unsigned int writeHold; unsigned int readSetup; unsigned int readStrobe; unsigned int readHold; unsigned int turnAround; } EMIFANANDTimingInfo_t; typedef struct _NAND_INFO_ { unsigned int dataRegAddr; /* ADDR Register address */ unsigned int addrRegAddr; /* CMD Register address */ unsigned int cmdRegAddr; /* Pointer to Memory Controller Structure */ struct _NAND_CTRL_INFO_ *hNandCtrlInfo; /* Pointer to ECC Structure */ struct _NAND_ECC_INFO_ *hNandEccInfo; /* Pointer to DMA Structure */ struct _NAND_DMA_INFO_ *hNandDmaInfo; } NandInfo_t; 7 b* v0 q7 I8 V9 f4 g& E
typedef struct _NAND_CTRL_INFO_ { unsigned int (*WaitPinStatusGet)(NandInfo_t *nandInfo); /* Timing info for the device and the controller */ void *hNandTimingInfo; /* Base address of the controller */ unsigned int baseAddr; /* ECC supported by the controller */ unsigned int eccSupported; /* Wait pin where NAND dev R/B pin is connected */ unsigned int chipSelectBaseAddr[NAND_MAX_CHIP_SELECTS];
1 ?5 E+ v/ m) G: W; l8 [0 o} NandCtrlInfo_t;
E- X w( J( z4 a. x$ J; \ * d4 k9 W& q6 i0 c
|