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我的McASP配置分别如下:
- z$ D8 y4 b( w4 n/ ^5 C! d& Q管脚的复用设置是:
" z7 `7 `8 z- @void McASPPinMuxSetup(void)! u9 t m+ {8 a; Q, u+ B
{
& A0 v' |( P4 ]( U } unsigned int savePinMux = 0;7 _/ s! C; o! U
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \% W- \( @" R1 e! H D% I
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
" i# M! n a: l5 c! n5 Y SYSCFG_PINMUX0_PINMUX0_23_20 | \
/ k# [7 r: y1 F SYSCFG_PINMUX0_PINMUX0_19_16 | \
$ Z2 x5 N' `1 B SYSCFG_PINMUX0_PINMUX0_15_12 | \
$ U7 D" x) X: F' ? SYSCFG_PINMUX0_PINMUX0_11_8 | \$ X& n1 O- B$ q, `; C
SYSCFG_PINMUX0_PINMUX0_7_4 | \
- G% p" Q8 \" ], P8 P/ l0 G& c SYSCFG_PINMUX0_PINMUX0_3_0);
' Q4 q+ V9 D, Z5 H0 E; c" d- | HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \8 Q! J' S. U A- r# G- R
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \' G2 F; n; S3 b1 i3 @* L4 ?: |; w* n. Y
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
1 C/ j7 s" }+ F# o PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
0 {, t. Z2 m; b, L* Z PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
1 T; M$ Q8 p6 P savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \- a$ K( r% ^& N3 J7 y. K
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \, p4 b# } V0 y5 T5 R
SYSCFG_PINMUX1_PINMUX1_15_12 | \7 t9 |" r4 X- t6 |, Z5 i
SYSCFG_PINMUX1_PINMUX1_11_8 | \
/ z+ c# g- Y1 R; J: v9 J SYSCFG_PINMUX1_PINMUX1_7_4 | \
2 L* h9 k# J; X9 n1 S# a1 ]( b6 { SYSCFG_PINMUX1_PINMUX1_23_20 | \7 u, |0 n9 z: W# Q
SYSCFG_PINMUX1_PINMUX1_27_24 | \
; A- Y3 i0 }$ l" O6 X0 v$ D SYSCFG_PINMUX1_PINMUX1_31_28
4 B# ^+ n y! y- d );7 X( X- L w" H7 U) n
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
, o; N3 L0 T2 ~0 d) P2 r& e& Z (PINMUX1_MCASP0_AXR11_ENABLE | \3 }: K$ o% e" C& z" m; ^/ k1 f9 C
PINMUX1_MCASP0_AXR12_ENABLE | \
6 z* `$ J+ _( y9 b& i5 {) \ PINMUX1_MCASP0_AXR13_ENABLE | \
1 f( V- L# ^ T8 F9 p2 d# N. B PINMUX1_MCASP0_AXR14_ENABLE | \( J2 D: V: M/ j3 R! ?6 e
PINMUX1_MCASP0_AXR8_ENABLE | \
9 J; b. h; ~9 n$ I3 | PINMUX1_MCASP0_AXR9_ENABLE | \
0 `2 O& J6 ~7 u PINMUX1_MCASP0_AXR10_ENABLE | \3 @% t& w& \8 E
savePinMux);
# F( M3 Y- _- p" R}' }, P" w) \" B' C# d, G
% X7 P0 }" ^( {2 W& u" N* a; g+ @
1.McASPI2SConfigure(); McASP的配置程序如下:' G. }' E* y. S+ d( j; c4 E
static void McASPI2SConfigure(void)
4 b; f% M3 v- \, u D6 n{+ y ?% w' f& L3 I9 j, \* h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 v9 l9 a) i3 R7 Z6 w1 s7 f: r
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
0 w* {/ u9 G* m, g5 x% U9 H
- w3 W7 O: i" R /* Enable the FIFOs for DMA transfer */
; a, i# Q2 n! D8 \4 M% q// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);" Y: `0 U$ a; ]/ ]8 n3 k1 _' ]* L0 O! a2 m
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 E8 y! X5 H7 Z$ ]$ y6 j! e, ?7 H" S$ P/ i/ y
/* Set I2S format in the transmitter/receiver format units */
; v4 {: s5 h! s2 \ McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# S# T! z0 ]5 E/ {* ^* w$ ~ MCASP_RX_MODE_NON_DMA);
" u* O4 h' J7 P {$ |! |3 i2 ] W McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) A) r+ `, M( L/ e: N MCASP_TX_MODE_NON_DMA);5 H( u2 e# i. i7 S+ h
" {) M( V4 [1 [! j+ E/ v' C% {) t3 M: {
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */' T) j% H: |9 r6 ~% G) O' W; V# [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! {& k! w o5 G1 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ b5 p$ ~1 N3 D, k/ ~! X- o McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 c1 _) J" l8 g6 ~7 }; o% a
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);! T$ |% ^# W' d. u8 _
1 G/ k0 x1 n0 @2 z /* configure the clock for receiver */
( ] `3 f% z, b! o// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);9 R0 Y! M. L2 ~- C( {% x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 O% }6 ]3 T) X z McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);2 f6 E/ ~! I% J. N! ?6 R3 q5 w3 M% @0 C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 e2 b3 p" y3 p% v8 V4 K1 v: }0 C7 l 0x00, 0xFF);4 |8 B* d' p5 v+ M( }, Q& a
& S2 }& I |$ c$ H! p" K
/* configure the clock for transmitter */
! K2 v, R7 h' L" J& E// HWREG(0x01D000A0) = (0x00001F00);' ?; }0 a: a3 L6 F+ T$ |
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);# w @/ L, m! q k$ j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);+ U! H; Y3 b6 @. D7 A' K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) W8 [- D4 f$ i* L! ?0 M4 R McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& z8 l& ~$ l" n. \. H
0x00, 0xFF);
+ i4 F' q; l" f1 z( B 5 h3 M- _+ d e+ K9 t
/* Enable synchronization of RX and TX sections */ . v" l) K. \# y; p1 i9 h, ?. G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
Z' @: s- d, q. C \, e
- `) M2 y8 z( q: j /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ R; t! Z7 c; V) H McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; ~! ?% ` S5 V5 ]8 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- ~5 v6 t: G, _' ` ?5 E2 J% k
$ _1 I3 ]) H3 j /*
: O9 G2 R' |2 X9 d+ V' h# c ** Set the serializers, Currently only one serializer is set as
6 Q2 k" V/ z# p ** transmitter and one serializer as receiver.
5 j3 M) [8 t1 G- y1 ]2 B1 P */
7 i ?3 m9 w5 } McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( `. [1 ?+ I( j9 k McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
1 `, [/ u! H4 A7 Y( h4 W! u( g McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);) m( g" l5 b, \$ V: A5 {- k8 k3 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);" ]/ ?% s" S8 w! A) m4 l( k6 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
1 ^! f! n! @4 N* k: n McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);* a3 G+ m- c0 Z5 z. I. F
, U+ k( l8 ?, a- t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);7 p* U9 ^7 ^, s. @
% ?! x; R0 i4 y) Y
/*
- l9 F# J3 ]7 {: t, {3 u ** Configure the McASP pins }& M* l* `5 Q" I0 B3 q
** Input - Frame Sync, Clock and Serializer Rx
- c1 z9 t3 l, w$ H. V ** Output - Serializer Tx is connected to the input of the codec
, g, M. y7 s! Y* g( s* n/ U */
9 v5 L- a. ]& k' L McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 B9 w2 J1 }1 d/ I" R McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
& ^6 k1 X% R& }0 c- r. { MCASP_PIN_AXR(MCASP_XSER_TX)
# Q- O% P# n( o8 M3 G+ s | MCASP_PIN_AMUTE
- ~ j* G: o6 t/ \9 e ); O. U( ~" a% @. w l$ M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
! r0 U5 `8 \2 M! Y MCASP_PIN_AFSX
. y& p3 W* b9 ^1 E0 V | MCASP_PIN_AFSR
5 Z3 c! K& g: l9 n | MCASP_PIN_AHCLKX8 t( {% g: {( m& E" F# k9 |# o
| MCASP_PIN_AHCLKR
& n0 e! \/ E7 ~. ] | MCASP_PIN_ACLKX
0 f2 H2 a- e3 `0 B/ {- r" | | MCASP_PIN_ACLKR" J& f4 }/ x; A
| MCASP_PIN_AXR(MCASP_XSER_RX)
) E# M" M f0 d. v& [0 F: z | MCASP_PIN_AXR(1u<<(13u))
& V Y( V9 L1 m" b4 l | MCASP_PIN_AXR(1u<<(14u))
! |1 W) w6 o6 C( M | MCASP_PIN_AXR(1u<<(8u))
% k2 g2 T* N0 J | MCASP_PIN_AXR(1u<<(10u))
4 z7 E+ ]$ D" F# S; i | MCASP_PIN_AXR(1u<<(11u))
P8 S4 u2 Q8 N );; g4 c+ X4 \% V8 g! a M4 O& A
6 q& m5 z" f! @1 m4 x& ] /* Enable error interrupts for McASP */
& _# h9 U Y" I McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
, `4 w6 @$ B% U7 H% }% r- c$ J MCASP_TX_DATAREADY9 H* }" L6 B. u( Z+ C+ s/ p9 ?! H p
| MCASP_TX_CLKFAIL " r) i7 ~2 e x, ^$ m4 F, G
| MCASP_TX_SYNCERROR
2 M* M$ j$ S3 B6 m | MCASP_TX_UNDERRUN);
$ O# K0 N; S: Z7 p
6 a. |1 T: E5 ^: i McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
" |5 x) p- A. w; E3 |$ T j( Y MCASP_RX_DATAREADY n0 j: r ~+ ]0 b
| MCASP_RX_CLKFAIL9 D+ Y8 |' E( g; W$ L3 b0 P- [5 C
| MCASP_RX_SYNCERROR
+ C" L. f0 b8 z$ O | MCASP_RX_OVERRUN);0 v# G& U8 ?- f( z. [: W2 ~1 \% G
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR/ {& y! _; w! W0 U, Q. Z
7 @. B$ z+ q0 f8 F, n" Z}3 r: k& ?- F; b* g1 ]
$ L: G( M( a! c# P' Q2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
+ C. I9 `. F" E+ xstatic void I2SDataTxRxActivate(void)% K: Q% q. P5 U- `
{
! s( z' K; H- } u% _ /* Start the clocks */
r8 p; [2 p& u McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 p+ r v- M: t" q McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
8 t* |. ^( x" L5 d2 N) V( q% v0 F. F/ ]
/* Enable EDMA for the transfer */: p: X2 ?2 F l3 y4 q8 A
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, I2 m) C2 d# i" _! G4 b- p
// EDMA3_TRIG_MODE_EVENT);# d# U- K7 c* [; j
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,& I4 R2 R8 m. G
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
+ ] c( b |$ H! y /* Activate the serializers */0 m' F3 }3 P& y* F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ M4 |8 J( v* _ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);% p- k& E0 E$ I9 h! h$ D' Q5 g
/* make sure that the XDATA bit is cleared to zero */
$ M8 e% m! k' x6 F' w while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
0 V; T% J2 N9 t* m /* Activate the state machines */7 I6 a0 k' J5 I% @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 Q' [5 _; x* w# _4 T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ H- V" v2 y+ ]/ |- t9 X
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
; H& f+ s5 e+ l/ a! `/ F}
- _7 F( H! Y8 [# C" B' h w/ a; ^; R! t
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