我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% E& d }0 i0 O% Pinput mcasp_ahclkx,/ I% a4 r) ?/ K" r0 N' ?
input mcasp_aclkx,4 o% p3 a! I5 E8 M# s! |
input axr0,2 T9 k, _! J: }& h
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output mcasp_afsr,
4 \% |4 V5 a6 C1 xoutput mcasp_ahclkr,
# ^3 }/ J: Y! q6 _output mcasp_aclkr,) x( v/ P0 m7 ]3 i% m w) k2 b# |
output axr1,9 _7 H" P" p8 y7 n
assign mcasp_afsr = mcasp_afsx;( X0 Z4 ~0 w# G" V5 x* S; F; ?
assign mcasp_aclkr = mcasp_aclkx;6 x( }$ V+ Q. K/ w; ?% U
assign mcasp_ahclkr = mcasp_ahclkx;
$ @7 Z1 l" `2 B$ l) i' oassign axr1 = axr0; & w: u5 w, O3 I( n v v
/ ^5 b4 L; A, m4 \9 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: l# D& Z* y0 tstatic void McASPI2SConfigure(void) |6 K* l8 N9 J/ e# v1 P/ E
{
2 }. `8 v: @; K9 _' dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# B E! [6 [9 [$ p0 j3 G; h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' ?, h2 l# s! g# n" Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 M1 u) T4 N/ ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" J; j) @4 Y' m g N! d# d- C$ G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" F' D, s' p; L8 N+ {( y: vMCASP_RX_MODE_DMA);
/ H% @5 ?! g! k# v1 K, V7 q( ?* sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
C, T5 o7 T5 N6 V2 W! q; s- m# T# ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, I" K. i7 _. |* l: `! IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ b) l5 J% H/ K; v# D/ O1 s6 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
l4 C5 p1 n8 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) U8 d! \( q% J; u' lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ E" q$ C- ]; g* a/ m) _" E. U8 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& ]: Z) Y. J b9 E* {2 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) o3 Q! M' e3 {; d3 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
I8 b' G! s5 S4 W% |2 x' N) d* I% E0x00, 0xFF); /* configure the clock for transmitter */6 m! ~6 y4 C3 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ b1 t' E/ A Q2 n; l: w, B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & L5 q" C8 }8 f3 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ q p+ _( u1 v# w/ S: ] E0x00, 0xFF);
5 N: v2 e; i0 ?4 l5 e; K/ O. x. i, {9 g* g a
/* Enable synchronization of RX and TX sections */
6 S7 h9 }3 W J ?; V6 E7 w, m6 W8 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ {9 u9 d: n" Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 T; g. R2 |. Y, M( yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** p6 R y/ z0 _5 U4 I6 b) U4 m4 V" f$ W
** Set the serializers, Currently only one serializer is set as, _& U6 {4 @& I8 y
** transmitter and one serializer as receiver., `* r2 J* R0 l4 k- ^# i
*/7 R" A4 a, O" \% q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; M: X- ~7 d o: \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 \' X* @/ Z# @** Configure the McASP pins 4 t. B9 k; M: D1 r2 g
** Input - Frame Sync, Clock and Serializer Rx+ y7 _& ~6 v) v$ m
** Output - Serializer Tx is connected to the input of the codec
h4 b' _ M. O6 d*/
j* A d& U( Y% m# KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: k. Q- d( V1 |0 d. \$ A# O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: n; v- ~' H& N' Z* {) y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& G7 {1 }$ i/ J" i
| MCASP_PIN_ACLKX4 g Q( R0 }7 ]- D: |
| MCASP_PIN_AHCLKX/ y4 L8 y+ E3 B1 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: y$ y$ W% K2 {) D8 v3 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 ?! y6 w' Y# x( J7 x) {. J
| MCASP_TX_CLKFAIL
& f7 n4 y/ Z) I F- L| MCASP_TX_SYNCERROR( _ ?, }. E l7 z* |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ q' A& r# D' ^6 B7 E5 _( k7 I| MCASP_RX_CLKFAIL
: r4 j& Y: C" ?! p+ ^4 J8 `! l; Z: X- n| MCASP_RX_SYNCERROR N$ X" c+ E k' p6 f" A2 S
| MCASP_RX_OVERRUN);
c9 C' V7 m# | U7 k} static void I2SDataTxRxActivate(void)3 D, ]) h1 m8 y: [" A) v' d! K
{; I+ G. A7 f! n
/* Start the clocks */0 m( l9 C) `+ H' x8 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* I( E) `- c/ M ? o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ I0 u+ P" p- k" IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 x% ^! k( K- q* o9 d% J/ _' k8 ^
EDMA3_TRIG_MODE_EVENT);
7 U$ L" t/ s2 o" e4 M: LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! }/ |1 b7 y. x$ g' z8 K# aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! j( w6 B. I' _' m3 U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 Y9 F I4 c5 g4 p* C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: ]$ x p2 S0 n* bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; Y k, K* c7 b& X1 I" ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; o e- A# f* n( m2 @; X5 N! s: {9 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. L$ d% @% O( p% {! F3 V( g$ e5 h
}
0 u& }' E8 x" D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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