我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ b# V$ J0 U) h7 V) ninput mcasp_ahclkx,- s- g* n9 D/ K6 {1 C9 ?
input mcasp_aclkx,
6 p( I% Z% @! W8 @input axr0,& w" ^3 p# u+ ^2 Z: q
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output mcasp_afsr,
4 i& a: r% S3 l. Q- `" `output mcasp_ahclkr,. k$ M! r, j+ Q4 y
output mcasp_aclkr,/ U# f4 J/ f2 A9 `# l* ^6 b9 N( s
output axr1,2 \* Q7 w- U* l! c/ l" w. A
assign mcasp_afsr = mcasp_afsx;: {9 k1 s( S* M! {
assign mcasp_aclkr = mcasp_aclkx;
6 c- k8 E& W7 H8 e1 R" Z8 Xassign mcasp_ahclkr = mcasp_ahclkx;
+ U0 \9 D9 E5 z1 L1 c& B" P- Passign axr1 = axr0; w6 e6 v8 `% N9 @6 t& m+ H. F
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + z9 Y* o2 g0 e
static void McASPI2SConfigure(void)' _9 g" L6 u" u K; d/ h& a
{, [2 d7 }( I( ~% Z% `5 u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& E& X% i2 ?# \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 D' |3 n* Q7 j! b. k( i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 ?( j/ I) Q# p/ \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) F( x0 }( n3 J1 M6 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 b1 I3 s$ a$ Q
MCASP_RX_MODE_DMA);
: j; z( _7 ]6 Q- FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, z% w9 x4 a, e( gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. d! {9 X$ u) j6 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( f/ G9 \7 E4 f! |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; L8 x& | s9 o" _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ K9 [$ b* |; oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; N# T$ g' ?! G( J8 U; cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. _- F/ h& U: I( N: EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 _7 ~. ~5 i; Z9 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 h. F- U- g8 N7 H: C
0x00, 0xFF); /* configure the clock for transmitter */: Q6 M/ u9 w; `- ~6 I5 f1 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& S+ s( {3 p) \' p8 S: R6 t1 r" C5 }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' }* @) h7 W$ e+ O# ^* P; o& YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. A- Q" ^: J# U4 U, q$ V" G7 ]
0x00, 0xFF);5 q# F9 ^! L0 r0 S. Q
# S$ d) Y0 ]' @% H4 E+ o3 N2 `/ o3 S
/* Enable synchronization of RX and TX sections */
& z2 `; G% i6 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' R4 X4 u. i! u9 s; QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 y7 Y |3 `) h; VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- E# O. l l. f1 C! }: Z' M* [3 W( ]
** Set the serializers, Currently only one serializer is set as
- I2 z$ _0 P5 m5 q" L4 \** transmitter and one serializer as receiver.
: j( Q5 i2 \9 _' Q7 [*/& T5 X* R& M# _/ S3 ]# ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 C0 L* O: |* U$ T, l, a# Q% e3 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- G6 H1 S4 g8 C8 ^& Y; w** Configure the McASP pins
# p: i, ~7 L* \. E5 I |** Input - Frame Sync, Clock and Serializer Rx
, n9 K5 s" J+ h* e5 l8 L** Output - Serializer Tx is connected to the input of the codec
: L8 S( J; p! ~*/5 [$ g2 ]3 X: ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& R/ L. y- x/ v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% M4 F9 O8 }: V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ k( a4 w; a8 L1 }( E7 J+ u1 S: l| MCASP_PIN_ACLKX- L7 n `. ?2 V! Y* @0 f3 |+ k7 L
| MCASP_PIN_AHCLKX5 P B( U. s* z+ n# x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- z/ e. F. K$ \% Y$ l; h/ b5 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 E# B+ q6 y; A2 Q3 Y9 L( M5 {| MCASP_TX_CLKFAIL
# [" A" G* l. [- h| MCASP_TX_SYNCERROR
0 k/ p# K1 R( O" `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 O: w3 m! W- ~) g| MCASP_RX_CLKFAIL K& ]% i0 q4 _+ N/ u' f b) G, @& M/ c
| MCASP_RX_SYNCERROR 8 \5 M8 \8 m& ~. O
| MCASP_RX_OVERRUN);
3 O2 Z8 U! C9 @: Q} static void I2SDataTxRxActivate(void): E5 z$ S+ R4 L8 E+ s
{6 E2 Y l2 v: u$ n1 L
/* Start the clocks */
: {" e. z8 f; oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); G3 f3 m/ t8 E% ~$ H' Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- n) \) [. m: s; X* _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ P: g% b+ K4 ~, ^+ O
EDMA3_TRIG_MODE_EVENT);7 L9 H/ R" k+ `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 p! F$ F% d/ g+ [$ p& D3 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 T) B) l# ]( _$ v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ ?- s' r& z+ p9 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 g% ^) m" _7 `+ z, ~, A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# t% @% f" k' |+ `' S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! }7 P" w. v- |0 K" Y' rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, ~9 ~5 H. x" N7 _# M5 e} 2 I# N; R9 A. h, T) i& ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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