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The timers support the following features:5 N6 m' _! k3 W- L
• Configurable as single 64-bit timer or two 32-bit timers
6 d k; N! Q: w9 u B4 |• Period timeouts generate interrupts, DMA events or external pin events
7 F5 u/ k/ T% Q2 O& ^' G! O" U• 8 32-bit compare registers
+ T, j/ v; g* i3 E% S8 z& M Y• Compare matches generate interrupt events0 |" V7 Z. O# N1 H! R0 J w
• Capture capability
3 Y% [+ w2 a/ V% @0 W• 64-bit Watchdog capability (Timer64P1 only)
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/*: ~9 z8 E8 Q5 q- H& r$ D, n. b
* T0_BOT: Timer 0, bottom : Used for clock_event& F+ w* z: S5 S, w0 t' {
* T0_TOP: Timer 0, top : Used for clocksource
+ H5 m' b1 {% r& F) | * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer! X6 x- i f/ }. `+ D2 a% z
*/ |
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