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The timers support the following features:
) [. s; f, ^; u• Configurable as single 64-bit timer or two 32-bit timers) R$ R, A3 X W& y; V+ R3 r
• Period timeouts generate interrupts, DMA events or external pin events# o3 r e r' C" a1 E3 \$ ]
• 8 32-bit compare registers* I2 @% p! w; t2 m9 [
• Compare matches generate interrupt events- w* F% R6 r! j. I" l: A* j
• Capture capability
/ z+ r F s: E( ?8 ~• 64-bit Watchdog capability (Timer64P1 only)
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* T0_BOT: Timer 0, bottom : Used for clock_event
- |2 k X( r8 W* t5 F * T0_TOP: Timer 0, top : Used for clocksource
# e' l' p. z) G * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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