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The timers support the following features:8 O9 r Q4 a8 r2 c7 v: K+ z
• Configurable as single 64-bit timer or two 32-bit timers# U" h: s( F' }' l z
• Period timeouts generate interrupts, DMA events or external pin events4 `' e8 y, ~) O' ^7 G
• 8 32-bit compare registers
! v0 Y& O' _4 a' A# Z1 |0 X• Compare matches generate interrupt events
1 v- o2 P7 K/ t3 A7 v) k- j• Capture capability
% z+ M2 m- _! M• 64-bit Watchdog capability (Timer64P1 only)
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* T0_BOT: Timer 0, bottom : Used for clock_event
* z- t3 l! n6 ?0 z0 ` * T0_TOP: Timer 0, top : Used for clocksource8 d1 t: c7 T M! r
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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