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The timers support the following features:) A9 i" g7 g9 a: G
• Configurable as single 64-bit timer or two 32-bit timers
& `: S" j- y' L* k• Period timeouts generate interrupts, DMA events or external pin events2 o, D' J9 n/ l: Q
• 8 32-bit compare registers
5 Y3 x, \, }; v( z4 Z6 E' G• Compare matches generate interrupt events
$ m: J5 D7 [# o* T8 E4 _• Capture capability3 B' U0 P( Y+ u9 @/ B
• 64-bit Watchdog capability (Timer64P1 only)0 o4 D" U7 {# @5 @: N
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* T0_BOT: Timer 0, bottom : Used for clock_event
' W& W# X0 Q9 X6 @ * T0_TOP: Timer 0, top : Used for clocksource
2 z3 o) |7 ]+ ]+ {& {$ K9 I * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer6 p( y( F: N; V H. b3 B
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