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The timers support the following features:0 p6 q' q/ T1 t5 l
• Configurable as single 64-bit timer or two 32-bit timers2 x9 n3 o1 `# n1 {$ M$ B9 X
• Period timeouts generate interrupts, DMA events or external pin events
9 o/ u% R0 W7 C: U• 8 32-bit compare registers
! N! z8 a0 i0 M• Compare matches generate interrupt events/ a$ D1 k% x1 J
• Capture capability
* ~, a3 A/ g8 f• 64-bit Watchdog capability (Timer64P1 only)
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* T0_BOT: Timer 0, bottom : Used for clock_event
% v% E4 q) b3 w7 n5 _: k$ ] * T0_TOP: Timer 0, top : Used for clocksource, P( H7 X! |4 N3 u. ]' R
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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