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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 r1 O$ J" D U4 n4 d* _6 n* V
input mcasp_ahclkx,
1 G# n X) d+ j4 X0 Finput mcasp_aclkx,. g& D! q6 C8 o1 @- o; [ ^2 V
input axr0,
, B. B$ g9 l4 N6 N u, v
. x: [ w+ o ~" O$ I9 @; O% {output mcasp_afsr,# c1 O( B4 j+ G& H
output mcasp_ahclkr,
& n. `5 L; f8 p5 M/ D2 [output mcasp_aclkr,9 j' d3 O/ Y+ s% k( e
output axr1,; w9 B/ ^4 r/ v& q, M/ X" c
assign mcasp_afsr = mcasp_afsx;
: Y7 v+ c+ }/ A, L/ aassign mcasp_aclkr = mcasp_aclkx;
3 X* N6 T- C1 C- Z2 w- F( passign mcasp_ahclkr = mcasp_ahclkx;5 A4 i/ u! z0 A8 I
assign axr1 = axr0; ( Q# }+ ^+ n5 C
/ b$ D {: @$ {/ {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 y7 N; Y6 _! ^: ]# s) J# L
static void McASPI2SConfigure(void)! E8 y+ f: L8 k5 k* h( B1 Q5 R" _4 f
{( z3 q" j/ C4 L8 T3 d0 g0 k: \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' o) Z# h1 F6 x" p$ h& z. B7 zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 L# f9 c4 d; }$ F5 @ rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. p' M4 s C4 _0 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' p- V' B: m, d5 M/ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ Q% H& t" e8 s9 C" F+ ~0 gMCASP_RX_MODE_DMA);, s1 c+ L3 ^+ [) l0 b7 m1 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; C- x5 ] J6 `% IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. b8 {4 O& N5 q7 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : a) m7 ~5 X5 h s B0 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 s [0 Y# u' K( _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 b6 L! G4 Z4 y; m+ k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" T5 Z" S/ c. ^* _. c. f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! N" Y$ c3 X% \ W( f5 d0 Y6 _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ j2 t* b9 n/ D) e$ ^' v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 L1 t* l9 K; R6 V6 Z" Q
0x00, 0xFF); /* configure the clock for transmitter */+ c9 A2 D3 h# X7 a v) d# ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ M' J$ Q$ [. l; F" X: l- {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 \6 H' P, {* a8 h- D$ ]$ z. `, v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# K9 X8 G2 j( R. d- t- L0x00, 0xFF);! ~8 n _* |# Q B2 ]4 O% R7 p
) j9 S0 u3 [9 e, L
/* Enable synchronization of RX and TX sections */
, B1 L. b' E0 a+ f1 |. JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 ? i) J4 o$ Y# i, m6 V5 i4 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. |" |: P8 ^% }3 K; Z% r# gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( {5 R' B9 f* Y+ G9 ?7 g; ?* p; v** Set the serializers, Currently only one serializer is set as9 s- ]) |/ Y) h2 }1 F: O
** transmitter and one serializer as receiver.
" p2 I: _- K( Z$ q+ z*/
4 S! Q# C! k- I4 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 A+ ]8 i# Z& r3 a: J" y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& W& K! n/ i. x" D5 d** Configure the McASP pins
% C. y/ _. W/ a. @& _& v** Input - Frame Sync, Clock and Serializer Rx* U3 l4 h( L7 }& d
** Output - Serializer Tx is connected to the input of the codec ( ?; Q6 w: m3 P% q
*/
! c* P$ |* Z- S! \/ UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! Z1 N3 K. G9 ^5 z, p1 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ y0 u8 S* A" {* H% H/ ~3 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 Y% u5 N0 m& || MCASP_PIN_ACLKX
[' G$ k$ Z/ \& w| MCASP_PIN_AHCLKX; b' y2 n" V/ I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' \$ q2 I/ u5 L: u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 R* H: c% X) ?" V& ^
| MCASP_TX_CLKFAIL
3 z) J, d0 S; w" j| MCASP_TX_SYNCERROR
& ^4 L" U% G1 d% V" s9 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& `- l" S7 c& Y% u- b| MCASP_RX_CLKFAIL0 ^$ ~% Q; [9 Q L- L
| MCASP_RX_SYNCERROR
5 T u9 J5 t$ _; N# A| MCASP_RX_OVERRUN);
! |( S0 A. p& X- H* n. m} static void I2SDataTxRxActivate(void)5 j% J6 P8 _: Y2 f) r
{
: R/ I$ V( k% A( D0 Q5 Q, j2 d/* Start the clocks */
3 R% Z3 @8 k% ~3 n0 vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. H; Z& }2 @! B4 h4 E! b8 X( ?8 N) ^, TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& L! g$ @5 p9 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 E b& C% S" y; {EDMA3_TRIG_MODE_EVENT);. N7 U/ h3 |4 H! f! V P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 [4 a' l+ F7 d8 {3 U) P0 QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" w- ?$ [9 J* e: L4 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 G8 i7 k! M/ j" M$ w0 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// f6 H$ c4 o$ H* N7 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% r0 A3 P! H0 A6 T/ T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 h. B8 Z: I6 Q5 M, V$ c2 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) c8 S' i1 _( V! G}
. S+ s$ _3 U, G5 d% A2 Z% `6 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / ?! o C1 L5 G/ r4 H. ]7 @2 o( ^3 ~! M
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