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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" C. U ]2 S, `. g4 m' `4 Finput mcasp_ahclkx,
' o) i1 b( S/ a: Hinput mcasp_aclkx,
$ g) g9 K& z5 w. Finput axr0,# V: E6 e; v5 ?- { H
% ]4 q0 R; T2 ?- d. m" U* s2 o
output mcasp_afsr,/ z& ^5 b, @* m' m) H" G& W
output mcasp_ahclkr,1 M: u" ^/ b+ @! r
output mcasp_aclkr,' _5 A5 f2 i% g, p" r* m
output axr1,- s! x$ C a+ p* x5 ?+ V
assign mcasp_afsr = mcasp_afsx;
3 }. f, H& C1 k, hassign mcasp_aclkr = mcasp_aclkx;
. @ H# c+ |7 N/ w5 q2 Cassign mcasp_ahclkr = mcasp_ahclkx;0 R7 f* B0 u4 x: R! z: \8 ~
assign axr1 = axr0;
1 w) M8 w/ o& A) C8 V# m- R& R+ [2 u* f: i( L! _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 _+ M* t" z) O+ I) v
static void McASPI2SConfigure(void)) s1 P7 {0 e: N {& c
{
( I$ e/ ^% ~( D R8 I. S: UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& _0 M1 x! ~/ B$ J# D' [6 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, W* f' {, g# ~1 a4 l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. c/ u1 |5 i# h" a# J: Y9 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 o3 V( S6 L2 q! {2 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, w5 e5 w, C0 E7 M$ k
MCASP_RX_MODE_DMA);8 Y' ]- m2 y" B7 T" w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# Y! A7 e ^6 Q6 D+ f' ?$ R, zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: H" ?$ r8 c& X1 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : @0 M5 K! t# B" r: A. o, X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 i- j C- b# r/ E& u/ G7 C0 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 M/ v1 t! ^2 @- U1 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 {4 w+ J" ]# ?# J8 B( _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 {% v b* l& o% P; Z7 ~9 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 [; V/ C% ?# R. O; J3 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 p0 h; z7 J$ [4 D4 A: J! d0x00, 0xFF); /* configure the clock for transmitter */; P/ x5 l" o1 t" a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- U+ ]7 m U: t' ~: _9 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 y9 |' Y3 P' u8 S; r' rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 M) |, ~# E [2 X6 I6 Q4 n
0x00, 0xFF);
7 m: V' X! [. X* V: u5 q8 e2 e9 m4 \- x3 h' R7 E
/* Enable synchronization of RX and TX sections */
m; I0 @1 ^5 s4 h- A* M& o2 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 F3 r' I) I3 fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ ]: l5 i7 F7 z' E& [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! |9 `6 g, O* a** Set the serializers, Currently only one serializer is set as! ?- b4 v. {. W# @
** transmitter and one serializer as receiver.% |& Q( I3 Z5 ?2 ?' H
*/
! U7 ~4 g4 m; P$ B6 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 t+ u5 V1 Y; n3 m9 s" ?8 \6 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% [+ L! d6 @ }2 I ]** Configure the McASP pins . O1 ^6 x6 H4 u+ A: _9 ~4 N) M
** Input - Frame Sync, Clock and Serializer Rx
2 j. A: `# c) w9 `* E5 \- L** Output - Serializer Tx is connected to the input of the codec 0 ^7 _4 `6 i7 b: H) B
*/8 \8 ~' g" `9 m+ K* j( K. j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 y3 j' w5 r6 S+ R5 kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 M& R! n6 k+ h. y7 N/ O* @1 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 \6 y( Z+ {& L* P, i
| MCASP_PIN_ACLKX
! j9 r4 o8 J; E* b| MCASP_PIN_AHCLKX% w/ f W+ s1 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% P( q- j4 ?5 k _ H( P# zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 b! B* B4 R0 I/ \" j# R| MCASP_TX_CLKFAIL / B4 F9 l/ g2 Y- C# m- e
| MCASP_TX_SYNCERROR1 I* s' k$ S e4 M% B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& d0 x/ @: E3 P/ t- u- x% T| MCASP_RX_CLKFAIL
9 m/ P* i+ ^" B S| MCASP_RX_SYNCERROR
8 {( @6 ]4 P: p' U$ b6 N& W| MCASP_RX_OVERRUN);
6 g, J3 \# @1 n/ M& N1 \} static void I2SDataTxRxActivate(void)# {' T1 r9 ?7 s6 v
{
/ k: |* N0 w. J; e& H7 ?/ f9 K/* Start the clocks */3 x7 o3 q$ ?" v8 \: v i" |6 l9 _+ }; M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, T" h* Q" _3 z2 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 o+ ?: Q% e+ I' gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 `6 Q5 R: x2 u" C, zEDMA3_TRIG_MODE_EVENT);7 _7 a% o: s' O7 ^- J6 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , h; ]. z# S: \4 k( ` t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% i: E* P% a1 Y1 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ i- T" Q( {4 q; \: j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* g/ h: d: b1 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 j9 V0 ~ e" P+ K* ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* r; D4 n) e9 e( y' }' l9 Y7 i8 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) G* Z$ v/ X4 D/ i% f* A+ ~
} : G' ~7 i9 h: M. P7 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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