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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ s9 S5 ^; n8 j9 `+ \) Jinput mcasp_ahclkx,) g' o$ v$ t9 b( w' a. Z
input mcasp_aclkx,2 V+ y" f# N+ |/ f1 E
input axr0,) R# k, K# r2 b. c
- ]' M+ n" }! q# c- m/ O/ a8 A
output mcasp_afsr,
: \' t# L" _5 k7 q* F/ N1 w( Youtput mcasp_ahclkr,% s5 x( L# Z3 a% ]* w
output mcasp_aclkr,4 J6 N" Q" g; ~& ]% _2 V
output axr1,
" ]' L. A2 |, r, C assign mcasp_afsr = mcasp_afsx;" t% \3 `+ w4 j' ~1 `- f
assign mcasp_aclkr = mcasp_aclkx;
4 X0 s" F- I+ K, w) X+ L- ?# ]assign mcasp_ahclkr = mcasp_ahclkx;8 L' n; }6 H' x6 d& m+ Z1 `5 x
assign axr1 = axr0;
! a/ ~& }4 H1 F5 F; o
2 Q! @+ R. O: B% {6 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" v: @3 N8 C& y/ w9 kstatic void McASPI2SConfigure(void): S: [5 l( C+ a1 V1 |, C B
{) E6 c" d# O; ~& C6 a) e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, U3 d. t+ e0 y% I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" Q4 R3 r! F6 \$ I: C' _. b' IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- R0 s- c) a3 r! e! X* ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( ^* o7 u7 ^, F! j( F$ J- M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," O, a$ h3 i, Y' o. [
MCASP_RX_MODE_DMA);
* R3 D. h! f% L! FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 O. Y' G- S9 K/ X o; jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 M/ H% c; T0 J* v* MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / q: y7 g( K. n( {% p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; M! ^+ e' k# E3 a. [4 F8 K8 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% k; y u- n! u: a. ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. i; E: z' g. g( v$ [4 Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 B- ]: L% a+ f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! n4 G; ^. G6 }8 X$ W! ^; [# g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% G$ [/ E X# _% i; w$ h, w, ^" o0x00, 0xFF); /* configure the clock for transmitter */
3 c2 y0 ^8 L$ E- C, k; b7 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 ?$ l8 l( F) ]$ c, A/ E8 J9 qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- Q7 ^% d0 t* o8 }7 w/ }6 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' j+ \. e. W! ?/ _0x00, 0xFF);2 B; |- I R& K% [7 ]: Z
/ @* Y. V- L& E" D D3 O' i& q
/* Enable synchronization of RX and TX sections */ ; j5 x( ]# D6 J1 ~( }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 U. _, b. L0 X$ J) A$ l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- ~1 d; c; Y' J, z( s8 ^. H# T' e0 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# c1 W$ ?: |' v2 N6 T {9 n** Set the serializers, Currently only one serializer is set as
; B. x) U6 b n9 v2 u** transmitter and one serializer as receiver.
! B; l8 R' a$ N+ p; k*/
' w: } G! R! {2 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 U! I- x9 [+ B5 h; H+ W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 G3 Z; p1 G2 M" A& J% R+ n** Configure the McASP pins
M4 o7 x9 L$ d0 A L6 K- f& ?** Input - Frame Sync, Clock and Serializer Rx
0 _4 l# p: T0 A1 E& b0 P4 G0 w1 `9 d** Output - Serializer Tx is connected to the input of the codec 4 f8 V5 _5 j* @, F- H% _9 F) D% H
*/
8 E i0 l; d, U [5 C* {+ |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 {& {/ j8 _, H _$ U& [+ xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* f! P) C9 K: f3 I- m, RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 k, u+ v# _% _: L6 Y G4 l| MCASP_PIN_ACLKX6 f3 |6 f( e$ S) y- H
| MCASP_PIN_AHCLKX3 g( f( y, T- c v1 t6 Q! u' _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) O/ J; B" v) O6 D! F/ t/ IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 ~$ i- J$ J$ [| MCASP_TX_CLKFAIL
/ i8 Z0 X+ c+ i# o6 r| MCASP_TX_SYNCERROR7 B5 U( m- f' B7 X% f; y) g/ _1 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 c; q0 R: u2 @5 X2 E5 t: n* z
| MCASP_RX_CLKFAIL, L+ }7 U w* v# N; [. [4 Z( ^
| MCASP_RX_SYNCERROR % @, ?& ^, z" S1 i% \3 d
| MCASP_RX_OVERRUN);1 P7 n. e$ s$ ^5 d8 B% ~/ f
} static void I2SDataTxRxActivate(void)3 R8 F! x. z' p, J
{
: \5 {( d" p; ?2 w9 Q5 A9 d/* Start the clocks */4 i8 W3 i: U) j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! g( L. x* L1 n3 B8 Z4 v) Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 ~6 P9 ~, W0 G' |, {6 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& U* x1 P0 _. f8 ^, _
EDMA3_TRIG_MODE_EVENT);! j6 r& z) P- t, I! B* |3 B. Y: E. j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( w- k7 m9 @ H" T% M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 e) e P& D0 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# a+ ^+ | ?0 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 C- s7 u" N2 M3 s. g9 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 S' d4 ~+ z9 U4 l1 X3 I( _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' M9 z. I9 T& l. ]; _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 O' k& U% Z2 d( z) C5 }
} " p& J+ x/ O3 `3 M' p% a- W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " t! R1 z- N9 G
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