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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 _+ Y, M, o$ ?, m8 e
input mcasp_ahclkx,2 q" V# q; M$ {& |2 E7 g! m1 n
input mcasp_aclkx,
+ T/ |; I% }+ j" J1 J' G; b/ ~# binput axr0,, c4 C4 j' B% O: {. z8 e0 O! f4 l3 r
# Z& e( S# Y$ u, A
output mcasp_afsr,+ h) F) d# b3 H7 B/ H' q4 @! L
output mcasp_ahclkr, I5 w! g9 L) g
output mcasp_aclkr,
3 B$ Y: G6 L4 p5 t/ O! }output axr1,7 P6 z+ U0 f B( b# R4 F2 y
assign mcasp_afsr = mcasp_afsx;
3 V# s9 g% @# Oassign mcasp_aclkr = mcasp_aclkx;" r! p9 P; _+ h/ ^, q4 e
assign mcasp_ahclkr = mcasp_ahclkx;
$ l* p5 V# {2 {) [8 lassign axr1 = axr0; . g* E; n' A9 K) l4 I6 b
. o) B! [# |& j# _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. w& K5 n) I' T' [static void McASPI2SConfigure(void)
3 u; R. `3 y& @0 X5 I* w' W3 ]{5 k/ T6 }! P! }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( V! H" n& H6 p( |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( F- n9 X' J4 C/ P! a- s4 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" y# c7 v) j' A! F, H: x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; N; @" [ r' `: W/ P" E& [- w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: F; E" o+ Q; f8 r9 u( e5 VMCASP_RX_MODE_DMA);
% u3 Q1 R8 [# w8 v. HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 A/ G3 H/ P- S- F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ \- M2 a7 q8 b: v' Z( xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % ?; S4 m- U: i @5 C* j0 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ z9 |& L* M U+ x, E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& i! l; S5 L# P ?0 S/ A# p( MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. G$ b# @$ d7 n$ P' BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* ?# @: u( y# }# x; u- T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 e0 p8 t2 N3 c8 U& J; ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 W& n4 e7 u) Y! y# R1 N0x00, 0xFF); /* configure the clock for transmitter */; F c9 d; N( w4 R1 M: r+ D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; R o6 h7 O7 H" l7 S' \8 \" B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& q' n: P8 ^* C7 t, |' CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ s' R0 A% M- w# a. \, e: e# L5 Z
0x00, 0xFF);
7 U" y) ^# H! K. T/ G! R% q. m4 v H2 E6 _" _+ O Y
/* Enable synchronization of RX and TX sections */ 9 X* Q* a& |7 D, t( }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! @6 g5 M; ~' N. B& L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# r) f7 Z$ Z. M6 C4 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 N! q: x' o7 o* S
** Set the serializers, Currently only one serializer is set as
( ?# J5 ?: m/ x; @( B( e2 U/ v** transmitter and one serializer as receiver.' `. _4 v9 v9 k' y1 {4 r2 n
*/
6 }( D# g4 i. x1 u. S+ ?* c4 S, }4 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ O( A! Q- w4 z7 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 o/ Q0 D$ x& c+ Z% r7 w1 `8 R** Configure the McASP pins
/ e' a g2 D0 k6 z% d, _** Input - Frame Sync, Clock and Serializer Rx
4 o# R5 O2 ?8 \7 ~. K** Output - Serializer Tx is connected to the input of the codec + m" j$ y& g5 G7 O
*/
( k6 N$ h% O; D2 I% k# L1 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! J( f+ y$ Y/ Z/ _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# P% p2 T/ l+ L. l+ E" a+ ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( _1 K: w, C0 T! e( r' r9 S: h
| MCASP_PIN_ACLKX
7 D+ @2 C1 X. B5 z8 z) Q U| MCASP_PIN_AHCLKX9 ? E- R B: W+ W" |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 t* p# w3 R: K$ I: E. w& ]- }4 T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 l- Y6 g# I: X2 o" `! M
| MCASP_TX_CLKFAIL
7 X' ~9 V8 k/ j| MCASP_TX_SYNCERROR
" P2 q; c1 r# |; S5 ]& G: `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 t- \0 @ N2 F
| MCASP_RX_CLKFAIL
( [' n: [- p9 o) g- B& K2 }9 R g$ ^| MCASP_RX_SYNCERROR
- }; ` A0 }+ H| MCASP_RX_OVERRUN);
3 G* H7 _. x e& p& D8 g, y5 q& W} static void I2SDataTxRxActivate(void)5 `9 r5 K4 B2 B5 H6 a* e
{7 l4 Z. s7 ]1 C: [
/* Start the clocks */
" ^2 s# c) @- r* x! y9 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" ]2 A4 n! ]' I' U2 z* c, nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 k3 w0 |5 _5 i- |% y) ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 P+ N% S! Q) B0 I5 R, p) \/ ]EDMA3_TRIG_MODE_EVENT);6 w/ Z2 V Y) K, r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . ]: A: s2 z" f3 b" ~! o- Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% [: E2 e6 H" b- v8 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ o4 k. `3 q" [0 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 p j7 S D: ]* v( r- k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 h4 k( X0 T# z' Q% z* yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 O" p! b) m3 CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 O$ G# u+ j: G} ! k9 f h+ ~4 C$ f2 u, _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! C2 G+ v3 A6 P$ J
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