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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, \( z$ `' g" i) e' w
input mcasp_ahclkx,7 P. _1 X/ {+ l2 u8 y
input mcasp_aclkx,% V+ b1 h8 N, ^, o
input axr0,. k2 |" u& r4 `5 w
8 N: J- t. K! U" q- P" Y+ T
output mcasp_afsr,( D; Y7 M2 H5 l; M
output mcasp_ahclkr,
1 F7 S6 I# _ ]2 d3 Z \+ W/ Loutput mcasp_aclkr,* M8 {1 r: U6 u8 \
output axr1,
) _# [) R: ]; l) l4 r' [8 V assign mcasp_afsr = mcasp_afsx;
& ]* U, `( O. J' Bassign mcasp_aclkr = mcasp_aclkx;& A4 O, E* Y; {* [
assign mcasp_ahclkr = mcasp_ahclkx;
: S$ v: O! ^+ z# b- z$ x* yassign axr1 = axr0;
& X+ I9 m+ \& h% \" @5 i
0 ?$ f0 Z1 Y7 r% C# C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ k5 w' P8 t4 E1 h
static void McASPI2SConfigure(void)
. G! Z& F2 F/ n7 X1 Y0 _{3 a; |4 p; G9 @# t7 x$ d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" W+ f( a, m3 n m) _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, g, o$ ]$ M3 s" Z: F7 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 d( D3 j) ~+ `9 O* w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 Q$ n1 `8 a) S/ N5 |& FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& r& @- m! u3 h
MCASP_RX_MODE_DMA);+ P& T5 d1 G$ }5 x0 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 s. X* m8 h0 p7 v' |! aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' z% E; k$ B& }) U- A( @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 T6 {9 d5 u8 B8 ]+ @* zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& A: O; D" D% M. b1 {; a+ w3 D% L% i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
D, Q. Z( X1 m7 q+ P n+ EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 I8 `3 N3 \! ^1 e2 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 B6 a( c' d7 h! mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) V+ n% F: d( D& |% `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 u1 Z, u z& G/ J9 u! U# g- K0x00, 0xFF); /* configure the clock for transmitter */
* V# b8 @ ^+ ^4 o1 d9 ]3 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- O4 n+ K: s7 M" a" j5 i3 O7 }' Q$ m+ \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 o+ U1 Y& j" _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& e' c8 R" E! k$ U
0x00, 0xFF);
/ P* K/ a l" u2 m$ U+ b- Y0 D* [+ Y' O5 d) o3 _
/* Enable synchronization of RX and TX sections */
1 {# M" Y9 J5 l0 M2 X1 C9 h. |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
P8 H$ C% V. h- wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 _$ V: v0 R" T5 lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! i. ~/ i& ^3 X/ ?, C6 \& q** Set the serializers, Currently only one serializer is set as
- W( E9 E6 ?0 w* |3 r8 o* r** transmitter and one serializer as receiver.
2 J4 D# e }! s/ l0 F7 F; g S X5 `*/
6 [! w3 `4 U. h/ m5 S( w" KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 W+ Q. R. X% [# O Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 z$ U8 F8 z3 c0 b** Configure the McASP pins 5 c W( _( n0 O' X
** Input - Frame Sync, Clock and Serializer Rx
7 W/ J+ {9 m( W( s! K1 h( ~* d& B** Output - Serializer Tx is connected to the input of the codec
1 x0 ?* {; t8 f+ U+ V7 K7 |- J*/
$ W( @* {/ E6 Z1 e# F# H! eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! D/ W' x2 j4 z( a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ l4 }4 j# Z$ f2 q/ ?2 UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" d+ Q$ e+ p8 M* F| MCASP_PIN_ACLKX" b5 i* m# O, K j( ]
| MCASP_PIN_AHCLKX
$ `& _0 w3 {0 M6 I3 f% O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% e2 M" \( ~6 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 q! u; L% F0 `% @; p
| MCASP_TX_CLKFAIL
7 L* ?0 ?6 w9 e+ I' `# A| MCASP_TX_SYNCERROR. h- U4 Q1 k/ q0 d; [! K2 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% W! y; i! p- B! O| MCASP_RX_CLKFAIL* h3 ?3 [8 S2 h4 X, V
| MCASP_RX_SYNCERROR : U4 z: u! b/ x8 {1 }
| MCASP_RX_OVERRUN);" N9 G, r7 H4 |' ~9 Q$ y
} static void I2SDataTxRxActivate(void)! n( G0 ?& A: k, C9 k2 W
{# w: d* Y$ z! a/ y2 R3 l: a
/* Start the clocks */
& F6 @- ~ y7 B4 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ O. `" y0 \% n8 z6 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 d4 ~$ ]6 B" T" _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 z4 }5 T% n/ g5 a- U9 v7 d( N
EDMA3_TRIG_MODE_EVENT);/ r1 U; Q8 B" U, t+ w$ Q! b- A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 {$ z: c" x0 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 j- H* ?& z/ X$ X- s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 J0 O/ u. C# ]7 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 u3 |; X! R, Z/ B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- e- Y( Z, U/ a0 Q& u5 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); a5 q/ i$ W) O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: c. p1 ~% N% h. |
} 2 |7 }0 Y- x! p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( D. p E1 H" j4 m' \, J+ {# P
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