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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 i' C; F! O4 E5 T2 }: q
input mcasp_ahclkx,% P$ t$ X. J1 _+ Z8 ?) ?) [
input mcasp_aclkx,
& `2 l/ t6 r. a+ [; i) Xinput axr0,5 i5 X2 S% }! `% C/ s; d
" _' |, N0 I: coutput mcasp_afsr,6 B) `3 [6 Q) r. a$ P2 K+ K
output mcasp_ahclkr,7 s# a7 s# I F4 \3 [+ s
output mcasp_aclkr,1 {2 ?- \# \. p& \& s G
output axr1,$ `" a+ B' w& o4 z
assign mcasp_afsr = mcasp_afsx;
+ p5 H* O: l \& vassign mcasp_aclkr = mcasp_aclkx;: G2 Y7 V$ L; x, Y
assign mcasp_ahclkr = mcasp_ahclkx;# \; W& F7 r2 }# M
assign axr1 = axr0; ( V% q4 z/ Q, i; G% J* k
+ s9 @$ u/ I: K. ? t) C- t1 j& C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 m/ v5 v/ n- v( p/ u
static void McASPI2SConfigure(void)) Q9 F) f/ U3 D7 m* H+ `1 N& _
{
1 X/ i7 R0 x1 Z( M2 m* MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 a1 a! W$ `4 w R- x1 m: a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. D: w+ y! D6 Y5 d& ^( L: E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: E( r- I7 V& V, J7 E. dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 B! J, y' P0 T$ ^2 U$ R# I5 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 s. ~' C) W6 k) bMCASP_RX_MODE_DMA);$ V6 ?$ [6 w; Z8 }! C r/ }/ q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- w3 A- g) r9 G8 c# j% l& Q$ uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 L8 Y- D0 h' A2 U' M% C- j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& d% H9 {! i8 n0 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" g8 x3 Q; l) w& k Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : H& D* ^0 n4 V& q+ O# Y9 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' [ h" q5 `( p& x* _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: C$ U2 s# I( H0 f& r3 p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % C3 U5 Y, K Y1 m; i3 ^. \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 M& ~- Y0 _+ Y d% x4 s- q
0x00, 0xFF); /* configure the clock for transmitter */
2 k, r. x0 S$ t# R1 }$ E( tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 Q; k5 w8 \& P- o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- @6 f9 L& v/ V' l. a9 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 x- e7 Q7 R; y3 {5 w1 E& a1 k3 g
0x00, 0xFF);
" B( h0 V6 ?1 r0 G1 B/ E9 {$ N# f, Z1 P/ a0 ~) X m5 a/ S
/* Enable synchronization of RX and TX sections */ ( T3 }. {8 n) s$ t# N# [5 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* S. \6 m' L+ r: g9 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% t5 H) ]5 |: B/ L0 c8 e2 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ Q# q' H H f( v+ I7 a# H** Set the serializers, Currently only one serializer is set as
7 V" s" M& [& o9 s: Q$ ]** transmitter and one serializer as receiver.
6 I' {6 a) J1 W$ i! ~' D8 [*/
: @5 L; W7 z% ^; W7 ~/ c4 ^6 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 k( n+ _* W2 F& R/ t( B+ FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# P4 K8 Z9 L2 v% L6 M# R3 S3 {
** Configure the McASP pins 2 j( Z, I% O+ s
** Input - Frame Sync, Clock and Serializer Rx% V! w4 Q e' @2 S& W7 S9 H8 y
** Output - Serializer Tx is connected to the input of the codec
1 V. F3 _1 e6 K% ~% j# Y*/
- K6 c, \+ G0 d7 Y- }) pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ G: z$ J% S4 B* g9 W+ zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( ^$ D: s' U) gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 X3 V9 T+ X2 k3 X3 N| MCASP_PIN_ACLKX
& ~. |" }1 `3 B: g7 s' @4 Q6 x) d. l| MCASP_PIN_AHCLKX
/ N; _" y" I% k! H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 D! M6 ^6 L* eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
H3 G+ s R$ d| MCASP_TX_CLKFAIL % V+ B, |8 p+ |# H X
| MCASP_TX_SYNCERROR& i* c% ?2 a' g3 g0 E% V$ C7 e4 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# R( N* a8 j4 ^' f" `8 m| MCASP_RX_CLKFAIL! }( Z4 B* w% o/ U) D& H' P
| MCASP_RX_SYNCERROR + ?/ l& H2 t8 w; i
| MCASP_RX_OVERRUN);; F5 B' R8 q* d# r" ^4 z- ?5 h( @
} static void I2SDataTxRxActivate(void)
# S4 H( T' S1 z2 V' ]4 z{
$ M# E0 w3 S2 K3 q% ~/* Start the clocks */) l: l9 a6 N B5 r9 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: o, f8 \8 A3 J, H5 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ V4 V+ W3 A4 E% ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) ?) V+ N4 `0 U+ s7 V; g" [4 l
EDMA3_TRIG_MODE_EVENT);
a/ H1 m% E- H, h2 E3 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
R* g2 @; h1 j/ u( i1 J1 G8 S4 S# wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 p {1 @1 Y$ z: z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* k% b5 c9 z" Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
H( |' ~' f% t; x4 m- Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* w# t9 f" |, ^5 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. }2 b8 N; b& k/ e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); u- \; }9 y9 s0 A
}
9 t( j% u" ~' F" T& w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . c" O3 g" ~# z) {; f
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