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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, Q3 B2 D9 S, q: X3 ]" zinput mcasp_ahclkx,
* c+ P( J' V$ X3 [input mcasp_aclkx,% z( k* O8 h( \" R5 p, y
input axr0,
2 i6 w+ x3 d" r4 l8 ]. N8 ^
9 r2 N9 v& f: U: u: w) O7 ?( |" L3 ooutput mcasp_afsr,6 F, J9 X$ E) o
output mcasp_ahclkr,8 P1 @7 R8 Y$ g# z7 O$ A! I D. D
output mcasp_aclkr,! u' H, o3 [1 w$ \5 x. X" p7 s4 @( k
output axr1,
% c W) M) d- M k; a5 ] assign mcasp_afsr = mcasp_afsx;
6 \8 T3 ?7 x4 E% F; {' g+ p6 Yassign mcasp_aclkr = mcasp_aclkx;
. x' i- L; z6 ^, k( Tassign mcasp_ahclkr = mcasp_ahclkx;
$ g+ G" c/ \! u, P0 ^8 bassign axr1 = axr0; 2 j6 K( `+ x0 Z0 ?$ X5 u
, _' P2 L9 `) K+ R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) ^5 I( a4 c1 g- R. ]$ p: i& K
static void McASPI2SConfigure(void)
/ t! L3 h4 }2 b; n, m{- H0 O- V2 \) o6 O0 K, z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% o0 Y2 S- X( { W. ?4 a' a, r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( c% p4 G: w |! k5 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 U. T/ D+ t4 u/ U `* w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% D+ q, _: y5 C( K* M$ b9 h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, G2 f' G, L% n9 S1 `( G
MCASP_RX_MODE_DMA);
0 P" c" o: {' o: {! N0 F* [" qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) {* O& g/ ^2 ] L) M4 ~/ YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: X9 n! W$ V% P7 X p+ WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 a R* b7 Q9 _% R* c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ k% B! _6 v. a1 Z: P" {- `0 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, o) H( h, W5 x: dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: @$ {9 J$ u( R/ R; {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; ^9 G5 {5 o( x& NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 R8 {! |+ u, F; } R- k6 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' e! Y3 G2 S4 \: n& G7 s4 O4 c
0x00, 0xFF); /* configure the clock for transmitter */
7 R3 R0 q! w8 bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ I5 l- d4 w4 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! u( |7 z: S" f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 L4 G: ^( Z+ Q& x4 b0 A1 f9 ]% g0x00, 0xFF);
3 L1 }' t9 r5 g: [% W2 t
7 c9 N; I& U+ f% c$ M/* Enable synchronization of RX and TX sections */
# g5 U0 [; {8 K2 F. P- Z" ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 z2 L0 l$ M7 U2 V1 v3 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ l" V# S; A1 Q2 ]1 e, P6 J6 UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 Q7 I# z+ a( \1 R) ~** Set the serializers, Currently only one serializer is set as: ?# e# u; u( V- y" | a
** transmitter and one serializer as receiver.! B5 ~- b( G( {, U
*/: I V1 G/ B, o* B+ g2 A5 D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" M' s; F) _" Q- x. bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' F+ [) b0 } R/ M- U+ N& E0 @: x** Configure the McASP pins 5 e# j+ ]! p4 t2 D2 u- l( E
** Input - Frame Sync, Clock and Serializer Rx: Y7 n- u) p0 Y$ ]0 p8 Z1 p
** Output - Serializer Tx is connected to the input of the codec
! \' L& y+ o' c# h; ?*/
6 S0 @ C# J n* VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. S$ n5 O+ _4 z$ s1 c! l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. w5 M% b- i( Z7 m( N0 x' f P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 Z4 l# n0 u* n6 v$ @| MCASP_PIN_ACLKX
& a+ Y S( J% k1 y$ j| MCASP_PIN_AHCLKX$ Q, F* U2 P5 |* b- R5 }! t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 u" z8 d$ p7 [9 J7 U9 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * |2 D/ c9 g7 d5 i
| MCASP_TX_CLKFAIL e3 [, v, g, M' [) }6 L9 p+ x
| MCASP_TX_SYNCERROR4 |. J# G; F* _9 |, t! A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 J4 r, V5 G6 |
| MCASP_RX_CLKFAIL
/ w! n& q* v& J& C. c1 h| MCASP_RX_SYNCERROR
- N, F2 r3 B+ H" @% h" o- ]- B4 x| MCASP_RX_OVERRUN);
0 V7 \4 H7 ?" T. N' V" s' f/ N# d4 [} static void I2SDataTxRxActivate(void)
- [1 y( b5 {! I) k{
5 z) L, @ r, i) ~' J8 j& k4 c/* Start the clocks */2 N7 E1 h* s# g2 g: t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 ~; M! d' G9 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 r, i8 P+ w7 L3 H+ I9 R# lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, b) P4 ~7 {( W1 j
EDMA3_TRIG_MODE_EVENT);
+ O( H. M0 f1 o4 R% P8 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' I4 @" m4 v* K3 M9 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 C- E+ B. @% i, zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ e/ T, C. w. @* V! k9 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 A/ u- [4 H. D1 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ ~. Y7 h) d2 I0 a% QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" v2 B/ R8 U, iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 X: P+ i2 C! {& q# X5 m+ b
}
+ P6 W9 D# u' }( q3 R/ K% z& i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * }) S- y3 }) l
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