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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; f" |* W+ u% A5 v a/ Z. |" Oinput mcasp_ahclkx,5 d0 P" G3 I9 t. E g$ V
input mcasp_aclkx,0 Q8 {& Y9 V Z% Y% W
input axr0,- v# N0 i& O7 D
8 _5 b8 Q0 r2 }( ]2 K8 Goutput mcasp_afsr,
! v1 N. ]( h& C# D' ^& _output mcasp_ahclkr,
, J" O+ f$ P4 K+ E+ A9 J9 Youtput mcasp_aclkr,1 p5 J$ t5 n* q$ r. y8 G% O
output axr1,* L: |2 g; E0 N9 M) b m/ e
assign mcasp_afsr = mcasp_afsx;6 o6 J* W+ X* h( p$ O M% z1 d
assign mcasp_aclkr = mcasp_aclkx;6 f/ J- V& V& V: N4 M! L% S
assign mcasp_ahclkr = mcasp_ahclkx; [- V. _% f! S" D6 u/ y
assign axr1 = axr0;
T' W" X& B) Q- T0 P& K- J/ s7 l& Q1 t% i' t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- y. H0 I: X1 kstatic void McASPI2SConfigure(void). t0 D5 R. o1 E
{
1 h4 @7 g; [, `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 H. M% w- ~: H1 \0 q3 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! k$ s ^5 m7 G3 y% |, @8 G+ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 f2 D2 s; c& _# L7 g I; XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 {6 E# `3 u7 Z' e1 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- S6 k; C2 j- \
MCASP_RX_MODE_DMA);; r/ r6 Z8 |+ x# S- k) U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! e4 ?) z( X4 e) d0 H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 B% z" _2 ^% {1 [8 A- y5 ]; ?5 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) h5 D. t2 R7 N. A; O: `% KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: z6 i- d' C2 ^3 }; _3 t' J) k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
X8 ~; j4 J* p4 J% D' t1 ?, ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: f3 k7 d% P" J# M8 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' ]# b; y. k* ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 Z* c; ]: S* {( a% R, J5 q1 z* b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ z+ S) b* _( R% Z
0x00, 0xFF); /* configure the clock for transmitter */, j! N5 R: |/ x% b/ z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 S' s3 B* v9 b: f' R1 D& Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 t- d% ]' Q2 ^. X/ L2 X* d6 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ t8 ^9 N& g7 i4 X3 L
0x00, 0xFF);
/ k5 ?; t- N5 i* o+ f# ?. \$ U0 u5 F: e$ g- x6 ?
/* Enable synchronization of RX and TX sections */ 7 D& @7 F" T- _# c( ]: {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ W4 H9 |' j ]9 y3 R" E8 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; \9 D0 V8 d9 t, ~5 Z/ M3 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 z4 Q0 A) G) Y8 R) Z( u# { x** Set the serializers, Currently only one serializer is set as: V' m3 a0 B. F- W0 J: f# h
** transmitter and one serializer as receiver.
) }* W* x3 B$ E, |( I*/; J5 L' C( P# E1 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- g( N4 B) o7 z+ |- X! T% \7 i+ g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ _' J7 f6 ?) a4 l d0 T2 X
** Configure the McASP pins , @ M- Y% b8 {2 c; j3 U
** Input - Frame Sync, Clock and Serializer Rx
. z9 B; J8 o4 |7 j8 ^) H# d4 E** Output - Serializer Tx is connected to the input of the codec ' m: |) a! G6 D& r3 B
*/
# [, Q0 S7 H/ F! W9 r! T& n: MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! l& w6 [: t# x8 c: PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 \" @7 a1 |5 }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! L0 i# z% k7 ~6 W# Y1 i8 N| MCASP_PIN_ACLKX0 G/ X# n. d3 \9 f: G7 @3 h
| MCASP_PIN_AHCLKX/ k3 s2 R1 \: ^3 A8 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; U4 b7 N) k0 g' @0 x! ^$ aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " A+ a& d2 J8 n
| MCASP_TX_CLKFAIL
- R7 W; t' z$ d| MCASP_TX_SYNCERROR5 ~! d. ?0 S; d ?& L5 K" \* y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : M' Z5 u6 d7 N6 P
| MCASP_RX_CLKFAIL' N" j/ W {' S
| MCASP_RX_SYNCERROR
7 \5 W& @8 ^7 g* ]) ?; @| MCASP_RX_OVERRUN);: P& m5 w' T. u8 b/ a8 \
} static void I2SDataTxRxActivate(void)
~0 I. \) B+ z9 A2 ~7 u H6 l7 K{& t+ G) F& ?& s5 m0 @4 w# @+ [! }7 J8 G( M
/* Start the clocks */
1 I) ~% S( p9 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' t9 Y! {! W7 N& r' {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ k* x/ H9 Q6 a5 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 L' n4 x0 t# @6 F, T' y
EDMA3_TRIG_MODE_EVENT);# W& q2 p9 d* G# O4 n) E4 b/ ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 N, Y0 v) R/ X! u- i) h7 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' }8 D6 ^: _" c+ JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 q! u% Y- d D" o( D; @4 | g; Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( Q7 @9 W; U+ R: k8 u K P) P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; ?, \+ i( S- L) ^( ?7 q: dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" O- ]" A4 @0 ?. ]# FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ P) o, [5 w0 c4 t4 @% ~8 R
} : @0 V( i0 |- s! |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , R* q7 B0 ~4 w
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