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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 z. J6 i: O' O7 {9 tinput mcasp_ahclkx,6 A7 K! V1 t/ B) i" h) r$ Q6 T
input mcasp_aclkx,
+ o& r6 q: L6 ]5 ?1 K, Kinput axr0,# \5 b3 x8 R! u' H
9 r0 E) q1 \- Q, M! G0 E- K: y
output mcasp_afsr,: i/ Q5 x% w0 j4 _0 R
output mcasp_ahclkr,
, O* V: S+ C& n, p9 t) voutput mcasp_aclkr,
- H' a, s3 r' C- X, E6 moutput axr1,( T7 q+ e1 n5 w
assign mcasp_afsr = mcasp_afsx;: N) d$ C2 E2 a4 d- \7 B# p* C
assign mcasp_aclkr = mcasp_aclkx;
" g7 S/ c- l: T8 Iassign mcasp_ahclkr = mcasp_ahclkx; x, d$ C, A0 t. q
assign axr1 = axr0; # V* k) B# g( N0 e% k& i0 R
' c9 S" p3 t9 s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
A5 N! E# a& G( ]static void McASPI2SConfigure(void)9 {8 }* A" S3 S/ k/ X* W
{
/ O; Q- v$ i. S7 }, Q* B9 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 }- B# z! K. o+ u* xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 q- p, y# l& [+ b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 D" s0 c* @' Y4 d) }7 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ X( ~: O) M- z( W6 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! u& i+ v" U: K7 m) P9 F7 k/ RMCASP_RX_MODE_DMA);" Q$ J- @$ K' C9 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( i" e! M0 V o; Y5 V) `- e3 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ?8 M0 o8 ^; F3 y" ]& r1 S; q. F) kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 F8 X8 u1 ^- b+ l& N4 ]5 a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ ?+ C+ |$ j. Y4 g: Q) h% L8 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
_) t2 z4 S& F) S- |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' \' [8 ^6 F7 x! I3 l/ Z6 J4 o. c+ hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* X- B f9 B; @5 P9 N X+ zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : h* j& A# q8 y0 C. e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, A2 k8 j/ |" Y+ U' K6 T
0x00, 0xFF); /* configure the clock for transmitter */
. {9 c/ {) {1 t- J# k% ^! o! u0 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% _& v) r1 {5 ^6 Q4 d2 `" jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # m4 g6 u, m8 v% ^ C6 Z% J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: s1 x( |* U% @/ _) C/ J
0x00, 0xFF);
5 a( o7 W' @; E3 s U) {7 P9 i& ?
# y* I+ N$ n4 e: b' s9 @5 U/* Enable synchronization of RX and TX sections */
4 y3 Z# c H8 }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 o# Q: K5 o6 s$ A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ N- Q- K r" ~! h W( Q' g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 @3 [* X; @9 J( f8 e- h
** Set the serializers, Currently only one serializer is set as- H. O/ y' {5 O! L4 F3 ~5 k
** transmitter and one serializer as receiver.
; a1 r# L# [9 B1 D, ^6 O*/" x4 Z. c0 `4 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ k6 o+ V6 e$ O" ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* M+ z: w2 X6 J. B# ?
** Configure the McASP pins ' _2 a6 n t% t8 D! |7 m( _* H
** Input - Frame Sync, Clock and Serializer Rx) s, n( C% u' s n0 e7 O
** Output - Serializer Tx is connected to the input of the codec
& g2 C- o: _8 r3 s*/! G: q& ]) K8 m% U# w, V( N" C* ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# C% \4 I, z8 U& \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ P5 ~0 e @6 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 o' Y& Z7 z+ Q| MCASP_PIN_ACLKX
$ d9 U. I7 |4 D' o0 ?5 {6 x: @( b| MCASP_PIN_AHCLKX
8 ]2 V: i$ P& T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& Q* C; S: a/ K2 F$ B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- C7 m1 j+ j8 x- \4 z6 B4 f4 d| MCASP_TX_CLKFAIL
: _& s; T+ u# \; c! M7 D6 u6 p| MCASP_TX_SYNCERROR
4 [& R: u, ], m1 }9 J* A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" @6 X! Y/ L- o- @" ]| MCASP_RX_CLKFAIL$ }$ }4 f4 ?! Q0 _, f' ~( n7 v
| MCASP_RX_SYNCERROR , m, G; A5 f5 O2 @
| MCASP_RX_OVERRUN);
0 x0 m) o+ d# D. _; B) B} static void I2SDataTxRxActivate(void)
8 F5 S- Q; q3 ?! T5 _+ h! O: w{/ p9 J* x+ S% [2 C9 }: s& k7 J
/* Start the clocks */
$ I# K5 I; s4 y2 p6 ]+ cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 Z& Y) I% ?6 \- v% }7 x: j5 ]: EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( Y7 N( a4 x3 ~: I5 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) [% |, \# t% n' o+ P- l T, q' F3 qEDMA3_TRIG_MODE_EVENT);
9 `2 O4 Y5 r5 W' U1 q( l8 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! `4 Y: S1 J! _1 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! J8 S. j3 V' q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ Q! w; q3 L- n' L+ I3 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& u6 N1 ]- {* `8 O$ F* z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ u6 E0 h) U: ?7 x$ w* m, M2 F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 Y! O/ x- o3 r, X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: w+ c0 f. J6 Q# O; Z) @
} 0 V O1 ^& {/ d& _3 u. ]1 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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