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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 `% A. s$ n* G9 r: p9 L- s/ E1 ginput mcasp_ahclkx,
2 m/ M: g( ^* j- e4 ginput mcasp_aclkx,
E, _6 H- P+ J' O3 vinput axr0,( b3 G( j. Z! i3 N2 ~/ f
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output mcasp_afsr,1 F8 b' u% l2 s6 N5 I; C; U! \$ n) a
output mcasp_ahclkr,2 H' g/ h' t" p$ {2 ]
output mcasp_aclkr,# |! F+ V. ~# k" Z9 l4 x) l
output axr1,
: o. }# z4 M& a! I. U" \ assign mcasp_afsr = mcasp_afsx;9 E) b% G3 I7 k2 s' i- @% r
assign mcasp_aclkr = mcasp_aclkx;" Z4 K4 b0 l5 c4 |
assign mcasp_ahclkr = mcasp_ahclkx;. |- h N: |8 \4 N
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 m* X3 d8 b1 {1 {, o
static void McASPI2SConfigure(void)5 a& k; h, |# c; N% {/ }. G; Z- |
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ p E! v7 S" P0 t2 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, f" I4 D* P. x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 U$ d2 v, Y7 S3 x; c' b& G7 QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# m# i& C6 r3 T' C2 t6 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
j$ o# C' g/ q6 w! [8 DMCASP_RX_MODE_DMA);
6 H2 ~5 H7 j- M9 Y4 n/ CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% G& ^* p0 m+ \ R9 R# dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ }) t- K' @3 {3 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( o+ d8 f; C) ]: y8 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 @- w; `% @% [, s0 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! d( Q9 u9 \, Q% o0 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* q: A2 X. Q u- X$ H6 N; bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* R. ~+ o- g: EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 Z' a0 P1 X8 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ T% |1 ?' }; O' h$ q0 l
0x00, 0xFF); /* configure the clock for transmitter */: J# \5 y( l4 [8 F1 n5 M; `& _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* }! P' g" c* p7 E: R9 q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! E9 ^: N4 z6 [' U1 T8 Q" n5 G+ W8 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# O; U$ e- O ~
0x00, 0xFF);
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, D6 s5 {) ]$ c; x9 W! z. |/* Enable synchronization of RX and TX sections */
8 X, M- S" m) q% Q' A/ sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( f- C+ Q5 G& D5 z6 X& ?- SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 S$ g Q, Y% h+ T2 ^0 y) s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 q! d6 @2 O& ~) p/ E
** Set the serializers, Currently only one serializer is set as H+ B% v7 b! X
** transmitter and one serializer as receiver., w( ?- X, a4 J# s4 K
*/+ A, N' _* M5 q2 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& P" G; Z1 R, v0 R- Q6 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) h; W) [/ c v( c5 K! t8 y( u8 y** Configure the McASP pins
$ B/ u8 T y S0 U' P** Input - Frame Sync, Clock and Serializer Rx; \: `; n) R: R. ?* a$ q
** Output - Serializer Tx is connected to the input of the codec
( \' G& [9 x5 z. ]; m6 h" n*/
3 m, L1 E4 B% F, cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
p9 [0 y* V3 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 Q2 B% C; w0 j/ V' [& KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( v# m. r6 o5 U- I# i" }6 D
| MCASP_PIN_ACLKX
0 K' p0 Z/ T* f3 L7 H9 j* f' j| MCASP_PIN_AHCLKX
6 m! x7 b( @. F$ M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ w, D8 [ [/ Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* `6 ^% w: p8 L6 _% A| MCASP_TX_CLKFAIL ' m G! a2 ]5 I! R( c4 G* h
| MCASP_TX_SYNCERROR
! b3 `& C' V7 N8 h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 s, N$ B+ A- f, G7 ]% G| MCASP_RX_CLKFAIL
# k: j$ h" s; L$ F/ A| MCASP_RX_SYNCERROR
( d U) f3 |+ C' D4 r| MCASP_RX_OVERRUN);9 P( T2 S: P3 O# Y7 k
} static void I2SDataTxRxActivate(void)
% R2 w1 x5 M/ ]$ W2 p9 [3 Q( p4 `# ~{# u2 t& `8 I! K$ s" V
/* Start the clocks */. G) j7 w* G, j1 I3 b! ^ O% m5 R) v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ ]% A7 O5 z7 O2 }% _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* t. N# C8 J4 C3 n; {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* ^2 ?/ ~0 P3 d7 ~EDMA3_TRIG_MODE_EVENT);" j2 x$ j% L6 z/ {3 m% S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) h8 B! P% z* n/ U$ zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 H+ O% H" t5 D$ U( F" lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ R5 k& G$ t; }& n6 g) u3 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% x9 } R. H8 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 j& u/ N6 [2 e5 s3 J0 u$ _! V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- e5 x" j: w6 n. q2 c: v6 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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