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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ [2 R- [1 X3 _6 o+ n0 Jinput mcasp_ahclkx,
. E9 U n( I5 Ninput mcasp_aclkx,
- K/ y- B1 ^% `+ p: Minput axr0,
, D8 Q) s& h# \0 G
" c; z- A' M j- b, Boutput mcasp_afsr,; p! ?% J: m0 h$ k+ @
output mcasp_ahclkr,
, _) _% C, @9 v) e9 Y5 Ooutput mcasp_aclkr,
: x `. q4 E- [. @% |, B! ^+ uoutput axr1,. l+ n6 h2 L4 o) X/ a. N
assign mcasp_afsr = mcasp_afsx;" b o5 I( O! Q8 v+ N
assign mcasp_aclkr = mcasp_aclkx;# s1 F) z3 w8 |# [0 ?: C7 q- ?5 f
assign mcasp_ahclkr = mcasp_ahclkx;, g! @% f3 R5 |/ |
assign axr1 = axr0; : I+ W- S# t' u. x, h
% a# u* \3 w( k5 k- s( ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 s* c! a1 M, ^6 M5 u8 E/ Kstatic void McASPI2SConfigure(void)
) ]* B/ A5 E3 J' a2 K4 e5 j" X{8 @0 `6 f. F. t. v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 m* N5 }- w5 o1 p( u3 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. p# q# C* c7 u& g2 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 H0 M, h% K6 P' l8 g+ B# p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ g# c* H& f3 T: i- Q* `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 O, u/ D& I/ X9 x- E; I* r
MCASP_RX_MODE_DMA);
$ \: ?! K: t( y% r5 Z+ `- XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, K$ C( ]' I) s7 u5 l! UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 E6 P/ o$ L" _& Z8 U0 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" y8 a( C$ O$ r+ F# j+ ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* e) L5 R6 E# {4 O. cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% H8 ~1 h& {2 r; E' @4 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" l; d( x0 z3 [/ iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) Q4 h! V" ^. d- R; ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* m+ c: Q- q2 L7 x# c, u4 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' r* T% V* f+ F* V0 `, v; W0x00, 0xFF); /* configure the clock for transmitter */
% V& A) a' T" SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" k8 I$ C" x" l5 R9 W0 F' ]) m* a3 _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 X: g5 M4 A/ p% b, R! }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' P' F% `! X; U9 U
0x00, 0xFF);
, u5 n) A& S7 X( d. b2 D" } i# l8 l2 m+ T2 u6 W" r, Y% [
/* Enable synchronization of RX and TX sections */
5 o/ z5 n4 n7 |2 c* y/ kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! ~+ Y: H, h% R3 }3 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 M. z. @6 {/ ^4 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** \$ g- ^/ W7 @
** Set the serializers, Currently only one serializer is set as) J3 {8 c) Y' y2 m) G
** transmitter and one serializer as receiver.
: S5 Q. `( J( y5 F3 z7 f*/2 W; K R) n, b% Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- C( W1 Z$ f" H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* { ~# x6 M/ L
** Configure the McASP pins * X( A+ h. B! Q; V7 \7 T
** Input - Frame Sync, Clock and Serializer Rx* s; N- O" _4 c+ I( C" ~
** Output - Serializer Tx is connected to the input of the codec
- X+ Z; h" Q0 ~3 w*/
! ^4 ]1 ~1 j* M2 k8 S8 x7 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, L! X0 a' p$ w: x6 v% P: K: ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( ]( E3 A8 q! ?, @, m% JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ A w3 Z* z; a) o3 @6 p| MCASP_PIN_ACLKX
3 Y* z5 L. e1 F) O9 X; O( A| MCASP_PIN_AHCLKX, V+ i# _8 j6 @- x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ _: q6 Z1 a+ s O9 A% f9 R% E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 v r+ n* N5 j| MCASP_TX_CLKFAIL - ~2 f: t' `: A! p: t
| MCASP_TX_SYNCERROR$ k! r0 G! |8 Z" [9 h1 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 D4 w$ E% r& S
| MCASP_RX_CLKFAIL
1 t# U+ `/ D5 j| MCASP_RX_SYNCERROR
% }. d4 d6 u# P: d: ~| MCASP_RX_OVERRUN);) d& M+ \. S* Z8 ]+ J0 ]
} static void I2SDataTxRxActivate(void)
9 F2 X( N# L/ [4 U{/ P# ^* A7 P+ a' {( u5 t$ N5 Y( _
/* Start the clocks */7 \& U+ V C0 w4 ]6 `" X# p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 x+ c$ E( |6 l( f6 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* e/ ]$ P5 @" t' nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," t: h* f2 Q7 }7 F/ M
EDMA3_TRIG_MODE_EVENT);# u# v: ~2 A1 @ {% O. d9 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 P% E% ?2 q4 P2 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 d5 E4 \% P. p% a6 u( d9 d( q% [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( @7 M1 Z i% r1 N! R2 F3 oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 O3 M9 A2 r6 |) E' S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 ]: u p @) n6 [% i+ I; X5 g+ J! yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( V$ V' ~6 |6 V/ a2 {! k1 J1 q& c* x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 @$ t0 o+ ^. l0 U. @" G( p4 o}
5 J/ Q% O ^" g; M5 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 q3 F+ y( _! J5 F f) g8 j; S% j
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