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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ D' Q5 Y- O d0 xinput mcasp_ahclkx,
& w; f5 R/ Q% w% }8 L W/ D: X ~input mcasp_aclkx,
' ?1 |9 s: E! v6 q0 K# v8 ninput axr0,
4 @) S5 H# w! K# `- I- ^
9 W; I6 m2 q3 o) w! q+ K8 D. D! Coutput mcasp_afsr,8 a( W" L) J! u& Y; N$ r. M. M9 M
output mcasp_ahclkr,% R9 w9 i4 b0 m6 l# t( k3 B2 N
output mcasp_aclkr,9 g7 ]* ~5 ]4 g( k) B, t! Y
output axr1,
4 ~# i) |/ O+ R assign mcasp_afsr = mcasp_afsx; p* \+ {( X2 L' K9 M! Q! K+ i
assign mcasp_aclkr = mcasp_aclkx;
* ~ {8 V8 T; h* c0 Aassign mcasp_ahclkr = mcasp_ahclkx;) U7 Z- C" C `: f4 A. {* h5 u
assign axr1 = axr0; # k: I/ P1 l! T( R# ^
; V4 E4 U2 H; _2 Q0 v, [$ {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) L! l5 ?& T% bstatic void McASPI2SConfigure(void)
8 V( \& Q; R' Q* f/ ?/ t1 X{, h4 x; o/ z( H+ B: Q0 g* z2 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 q0 L" F$ R* o) z( R0 I3 Z% i# vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. Q9 |+ p. j0 g) Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, \$ D, M' ^0 H/ TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 E( Y P: h3 |7 v+ ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, h3 {1 E. @( w. T" H
MCASP_RX_MODE_DMA);! U: E7 w U, F y; h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" f, u) r' P' R- zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ u/ i8 y/ ~* w% zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * }/ n% d1 E, @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 ^! a3 {: h/ f* J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 }& t. j1 O9 @* ~8 v8 z8 T' SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 @1 z( Z1 K. q: y' l, h0 w; \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 E A( D8 I/ ~: f" L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& h( q) z, L: D0 ~9 v/ D2 ?- |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) }5 S6 \- k+ g+ F- w
0x00, 0xFF); /* configure the clock for transmitter */' E' D [! `8 f+ Q& C" O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 n/ P+ u0 @5 `4 `+ M- D. M' BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 Z9 e% {$ s5 H4 E. V- K8 Q' y% H3 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- a* v! P/ }) g" ^3 M* Q0x00, 0xFF);
5 L/ j7 A9 d. z ~8 J5 \+ ]! x7 M& O& k3 I3 g+ R7 }0 U5 m0 s: ^
/* Enable synchronization of RX and TX sections */ / q6 W- H, R1 |4 ]0 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ z: a6 k8 q+ ]4 S; T @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* y: z N4 y9 R0 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 Z4 L& J4 Y$ l! v. l7 c0 D
** Set the serializers, Currently only one serializer is set as! x: k8 G) G; d& P) Q( e
** transmitter and one serializer as receiver.
8 D5 x4 I! X$ q*/2 @6 G6 S# K+ J. T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 S) [; `& c. Z% n! B) c: W5 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 R8 H9 b2 c5 d" h0 e/ X
** Configure the McASP pins 3 J) g7 g4 z1 C: a3 N0 r
** Input - Frame Sync, Clock and Serializer Rx! z% s" D1 e# `3 O* r, _7 r" P
** Output - Serializer Tx is connected to the input of the codec
! c( l8 a( D+ d*// c4 d( N7 K3 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 m, N8 y( y; Z+ g" K" {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( ?7 k$ N2 ?, Y2 G( [& ?+ G# p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. h& I$ E/ _+ R$ L) @| MCASP_PIN_ACLKX
( c M6 m' Y1 H! y! |- b| MCASP_PIN_AHCLKX0 N: U0 u$ {# M7 T% K. }( D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 C6 N# o) T- p) ^* c2 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! v$ X6 D! q! h- ]+ w# K| MCASP_TX_CLKFAIL
2 Z0 Q. S: f9 {1 ?7 z! x| MCASP_TX_SYNCERROR1 @# G; x4 o4 u/ c) i: q" m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # o; |4 M7 K2 D# L
| MCASP_RX_CLKFAIL
6 I- l, K |& g| MCASP_RX_SYNCERROR & }5 W, _; ]4 C# h3 w' h- z, M7 C
| MCASP_RX_OVERRUN);
9 z; c. ^/ O8 w$ k( {} static void I2SDataTxRxActivate(void)+ g% y, [7 n3 u, @) O9 f5 h
{7 L/ }7 @# W. {' Y2 @" F
/* Start the clocks */" x+ ]% T1 T: K- X. O2 g: [- |0 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ~( D& Z! y7 N5 N" l* k: M3 r8 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 Y7 z+ `& r' k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! V) Q6 E3 [3 u* D
EDMA3_TRIG_MODE_EVENT);
- w% V% E" k9 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % i, k; O: ^, O9 o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( }, P: L' B2 w0 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 m/ o; P# _7 [& J# p" O/ e8 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# T/ ]1 W! \" U7 P: pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ Y% a8 E& b- ]+ L6 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ ?/ h$ \6 u! H: u) G6 _( g7 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); |6 U6 F& Y4 W6 w1 G$ X. e
}
6 O8 ?* N$ h7 i- S. q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , v9 R) Y- I9 d
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