|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# h3 b9 z$ e9 r5 [* V9 [input mcasp_ahclkx,
: m& \6 ~& A% G3 C2 T- @9 Ginput mcasp_aclkx,
* \1 V! H, n/ X: f! i- Winput axr0,
& J% I$ ~; i/ o8 d- C) p$ J- o! [# r T
output mcasp_afsr,
7 @, E" e0 y- ?8 ~; R- Toutput mcasp_ahclkr,' E5 C0 f0 _& n3 w8 W! Q. R3 f
output mcasp_aclkr,5 z$ u; j/ A n7 W
output axr1," ^5 g/ I& S5 T# K
assign mcasp_afsr = mcasp_afsx;, ?6 @" g `: `" ^! \2 q; l
assign mcasp_aclkr = mcasp_aclkx;7 [# v- l* ^# c! Z6 \5 q. d. P" x/ `( R
assign mcasp_ahclkr = mcasp_ahclkx;
* w& h1 p& p- X' `) u7 Tassign axr1 = axr0; " U; y0 u3 T5 V8 F5 L
1 [) P5 G* \0 t2 ^6 ?; X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 ]. T3 t: @( A% Pstatic void McASPI2SConfigure(void)
/ K- j! D9 ?9 V, k9 }- J* `{- w* @3 N$ ?. c. c: y9 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 t8 g. z* C3 L% ?! K6 R, D5 d6 @4 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* g/ @$ [2 O: b5 V! V6 |* g( |. Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) a4 _( T; S. w, bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) F, O: U8 n% d# NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 T) O5 W% ~( ~! Q' v
MCASP_RX_MODE_DMA);
4 `0 H7 A5 R2 ~# C% dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. a3 Z. Y x( m# o) ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, b. O0 j' I v6 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( V2 F, o4 L- r0 j; j" g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' M& K" s. F/ j% z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: f3 |/ Q' s( RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; z' }4 N# N- m4 ^; gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! l1 C3 `$ Z: [( C. vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 P1 h4 v& R' ]# H7 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' f- d2 M8 [: t! k' ~3 A2 \
0x00, 0xFF); /* configure the clock for transmitter */
6 v2 S/ V6 M, r6 U% M! V* [) rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 R; |' u. k# I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
p+ V) m& b3 w! S; J. C' F( D# lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) w+ r$ W# c D
0x00, 0xFF);
+ f( w; u2 t4 I4 t6 n& l! N3 Q7 Z0 H' u2 C& n9 U/ K
/* Enable synchronization of RX and TX sections */
. G9 G+ m8 s% h$ h* [( s% D" RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% p$ G8 B* w$ e( m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ S4 ` f3 u. L' N/ A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# y3 g) U8 ]+ i1 p' N+ w** Set the serializers, Currently only one serializer is set as
0 t' b- P5 q& L$ E- X$ |; ^( T** transmitter and one serializer as receiver.
7 z) L/ m% W8 u8 A*/
, z4 @8 g D. [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" e) i$ R, ]" z2 k- F* T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, S( i5 y, |& {2 \** Configure the McASP pins
9 E5 _5 T4 z' l0 p** Input - Frame Sync, Clock and Serializer Rx
, k) O& |: g Y# z( V6 b% {. W/ @2 v** Output - Serializer Tx is connected to the input of the codec
8 o) `( G1 d h2 s*/0 m/ W2 o) R. U" I: E4 x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 Y$ q# b' Y. q; I7 n; sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ^9 t5 N# {3 z. TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. u4 L2 v. o6 _2 T3 h) G
| MCASP_PIN_ACLKX
7 g$ P- | c0 j9 X) W. b% `/ D. l| MCASP_PIN_AHCLKX9 U3 }) d! W1 z# Q2 ^% H1 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 Q0 ^+ t, T) P' oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / h; b$ t& m+ `" q$ F
| MCASP_TX_CLKFAIL
, _5 ]+ ~* K& W$ ], C! _| MCASP_TX_SYNCERROR
! o) a# U; O# b) c7 F2 e' D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , ~. Q* ?" O, l+ @
| MCASP_RX_CLKFAIL' i' w6 b) S9 [# L( p1 p
| MCASP_RX_SYNCERROR
" x# x! N9 N1 A8 v- \| MCASP_RX_OVERRUN);
9 P" p: U8 @& }( X! O: Y7 \) R% a} static void I2SDataTxRxActivate(void)
+ e9 U* s0 ?! [! ]3 G: x{! p6 R ~. T/ X' r0 M2 M
/* Start the clocks */* D; y" t1 X6 u2 F: b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& @- G* z' p! E! E8 W/ i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# \/ q0 X- _, X! {9 @ PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* c- r2 k" I# Y
EDMA3_TRIG_MODE_EVENT);9 _3 N- p I1 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 N- @3 @! P9 s% k, g: z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) k8 `& k) R; ?. c" _/ {: A, |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
L0 D6 L! ~( k( ?! H" TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ {0 D1 u" V% K) r( Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( y1 A* R) R+ B# p3 |) A. n# C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' x7 e; ~0 ], C, [/ ?1 B( m o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, l; F2 i- _2 O# U} ) A/ u: [# s# f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 O3 U5 S3 \7 o K. G$ p |