|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 A) O5 \* I2 ]) N7 w1 b
input mcasp_ahclkx,# D$ L1 A. g/ K' N8 W
input mcasp_aclkx,' J) q9 T6 a+ W# p9 q# `$ b3 j
input axr0,
8 a5 Z6 q3 x5 j& B4 Z# k, G: `, k, Y
output mcasp_afsr,2 a$ E: b( b" r( G
output mcasp_ahclkr,4 }" `" v6 U7 f0 q
output mcasp_aclkr,
/ {) W6 x z3 K1 n poutput axr1,$ a6 n1 l+ Y+ M5 W/ v& Z
assign mcasp_afsr = mcasp_afsx;
( F4 w+ U0 T, L& l. u& [; r1 eassign mcasp_aclkr = mcasp_aclkx;
+ O, B1 P, F1 _$ ?: qassign mcasp_ahclkr = mcasp_ahclkx;( K) O. Y6 u: O$ M8 `# t1 b# N7 w
assign axr1 = axr0;
+ Q* u# z5 e2 A! `6 b: H* S6 d5 Q' a( \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 a! D' P" I' r0 l7 Zstatic void McASPI2SConfigure(void)
! @2 R. Z& l) L6 Z5 n{5 r- {; e( y! p7 H& O5 J8 S" @0 [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 M" l5 w# g4 w( m& N' Q0 o. A" Q- oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 G: ]& y/ @7 j: qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& p# H) g' N8 E/ P" `- HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 j$ o8 i' P8 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 b+ m( g( O! Z _0 l! M& \/ _; v# S* I
MCASP_RX_MODE_DMA);2 t( \. m5 S( e4 u9 K$ F" N( g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ^% R" K: } j, c# Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- V9 J$ T; q5 o/ z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 M# C6 c& V" Z6 vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- p% G/ J* Z" J6 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 H$ l6 I, i! N& \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 p. }" n4 ]: O8 ?* A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ c1 ]% x# h& s8 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 ^' C" k+ T! L$ k8 Q6 v5 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 Z6 H! P7 F# z- Y; o0x00, 0xFF); /* configure the clock for transmitter */
: ~3 g' L2 N$ G# J8 i/ ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 i* K6 A6 k9 K; F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - j: k. q; I* m: [* P3 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 W/ `4 V8 h$ A0 Z* n. n0x00, 0xFF);
; ?* X7 z! A- ~ d5 c) I2 B% W
5 f+ L$ E1 i8 W" c7 a* m/* Enable synchronization of RX and TX sections */ 8 x; a" C, f9 H& a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. `) w" a& v- D) a% I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 H) e+ X# S3 e) N) CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! w: @8 E& k4 j" R& ~2 }! v1 a
** Set the serializers, Currently only one serializer is set as
/ [: C& A& W) h q** transmitter and one serializer as receiver.* n' l7 S% b9 r2 F/ X
*/+ F) V" x6 }1 O8 p) ] b4 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* H% W' K6 Q2 I' d* z% p9 p1 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 I, E- M% H, ^& K, g; b** Configure the McASP pins 4 I8 `4 {. s g* Z# ]
** Input - Frame Sync, Clock and Serializer Rx
: U1 f" E7 J. d6 q" L& P/ M** Output - Serializer Tx is connected to the input of the codec + ^. n0 Y* X9 I6 @+ T* e
*/) |1 R% k, Z9 o) q) z4 U( T# M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ a1 @' k$ ] s7 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 i* P0 A& \! d7 n0 Y+ J5 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) @; a& U+ I4 N# y5 G- }| MCASP_PIN_ACLKX, b7 }, z* l. K% A5 X4 b" t
| MCASP_PIN_AHCLKX7 J. d! _( N Z) ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% c! i- o: a6 e* c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: q7 R1 a5 j0 N! L/ L| MCASP_TX_CLKFAIL ; I+ H/ ~( b, K0 E, I
| MCASP_TX_SYNCERROR
0 }. _7 g; k; G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 w' B& G3 F2 M: }
| MCASP_RX_CLKFAIL; l; Q l3 ]* V2 c, W0 w9 N
| MCASP_RX_SYNCERROR " S4 y5 E! c- e% H
| MCASP_RX_OVERRUN);5 |+ d& p% I' v$ c
} static void I2SDataTxRxActivate(void)2 u [ } L h8 @4 w2 A
{
/ s! r# B5 P6 P! e, {/* Start the clocks */
" p# I6 O* d' \3 _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. A: _/ O5 W; [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ s5 O0 C8 n# I3 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' I* @) u$ P3 p. D: _9 M2 @EDMA3_TRIG_MODE_EVENT);8 t2 l' v8 S" o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 f2 p4 F0 n& N* g5 k' l# {+ UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 A" R* ^+ ^ ] iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ?8 p1 z C/ Z. e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 ~5 J1 n% K, H* |0 h" O1 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, h& w9 R+ P( W8 X: i$ PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ R6 q0 ]4 V! k1 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( m1 U. P3 ~$ t8 c! T7 Q% `5 \
}
4 i {# b/ m+ f9 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; c. l, {5 s5 I9 X2 W' k |