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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) k3 B% |; {6 c$ Qinput mcasp_ahclkx," N) v: U- R4 `9 G
input mcasp_aclkx,
3 S7 y( A6 E8 n" ainput axr0,' V+ U* \" J n7 l
4 L% C5 T% Z: a# c7 K4 doutput mcasp_afsr,
" h$ \8 w8 q) E; u. I! ?output mcasp_ahclkr,! d0 s. g$ o7 i7 T# ?
output mcasp_aclkr,5 i Q' W4 s2 V
output axr1,
' D) o) {1 `8 {0 L# a assign mcasp_afsr = mcasp_afsx;5 F. h+ ?5 J5 O. h; K
assign mcasp_aclkr = mcasp_aclkx;! p+ R, M2 @; m3 N8 ~
assign mcasp_ahclkr = mcasp_ahclkx;9 a! W' c5 B+ m) U, ?' E) P! D
assign axr1 = axr0; " n) W1 t) c5 n# m0 ~) m
' K \; a4 h7 e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' B, n# C3 a2 \% p8 Q; kstatic void McASPI2SConfigure(void)4 R) Z* z1 L0 p) E; m7 v
{
$ `# g! }- {6 a; W6 f' wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 r) V f; @" _ F$ @ K: a$ EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ Q% V3 ^# [! Y- x! pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ s7 F2 l. O4 t2 d, R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 L& _/ Z2 t: M0 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 F* Y+ B0 y. Y# }6 n j
MCASP_RX_MODE_DMA);
Y! b+ n* C3 |/ l# X2 u* y, w. EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 ?7 E9 ?5 X- } L0 p- v0 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ X: K }1 {( Z2 T& Y* {4 ^; |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ J9 V) H/ D2 R4 T" E1 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' N# \8 f1 N# L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( {4 A7 C/ `. v( r" }5 j. |! O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 @& ]; q: r3 g3 e6 m3 n; x0 l$ Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& O8 r- {! D5 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # `0 u' [6 j" y% y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ H: G, B, R1 L# _+ x7 f7 {0x00, 0xFF); /* configure the clock for transmitter */
% \7 B$ a$ V% E) i: cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 H4 E9 i' P8 n* I ~. ]5 a( ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" G1 M$ }$ y( j" b% z5 o6 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 l9 d1 B9 A0 h! e# o/ B; L# A
0x00, 0xFF);
* L* t2 m Q3 a, K& ~ G" Z, e# \" P y% l
/* Enable synchronization of RX and TX sections */
" ]; t5 Z# B& }, T1 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' L; j# I/ o, y @! M8 y/ VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: h& C/ r. Q! P& [ f% ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# [' V7 X/ a9 F1 D2 V, u+ d9 G
** Set the serializers, Currently only one serializer is set as8 u' X* j4 [4 J8 \; m+ e7 j8 L
** transmitter and one serializer as receiver.* c9 s6 ~) A2 m- E: i. k
*/
+ v2 {. n: x+ ?% M WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
a( W( }: e) y! O! V- rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 |6 s' B/ @) Q) T# {** Configure the McASP pins
; m; E% K( m4 j; @% e! K# S** Input - Frame Sync, Clock and Serializer Rx
- {# r4 n+ I4 ^3 Y0 H7 h** Output - Serializer Tx is connected to the input of the codec
. ]: A: W. J* q: y' ?5 |*/
4 d( c+ A* d& `! D" ^2 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- [; k5 ]. a" T) _) T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ f/ V& T8 {) H% `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
N6 L' _. u# Q. A+ N" |$ r5 R| MCASP_PIN_ACLKX2 J, v0 g( }, N) H. R6 N: G
| MCASP_PIN_AHCLKX
8 }" y! Z- k; F* t: @# F& J7 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# k6 Q. l9 d, ]- P: MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 A M2 F$ h8 Y3 {" E- o
| MCASP_TX_CLKFAIL 1 c* _4 z2 Y( B: t& F2 I
| MCASP_TX_SYNCERROR
- I0 y' ? K. ^0 H K: c* d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / Z+ r1 e0 ^; @( m3 C9 P9 W# B
| MCASP_RX_CLKFAIL" B# a. x3 J/ }1 \0 v* h S# z* Q6 r
| MCASP_RX_SYNCERROR 7 r1 X! S. `* u0 m7 [# m5 B) A, C
| MCASP_RX_OVERRUN);
- ~: ?+ M0 @; O/ m} static void I2SDataTxRxActivate(void)
% ?) ~0 E: h7 M{7 O4 H) |! n" W: R$ x
/* Start the clocks */( y; Y% g \; y9 v/ R7 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% T* I9 ~; r: }4 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 z6 g1 f4 s0 e8 P9 T6 K* qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, p1 O2 D7 B5 ?" T. L7 K
EDMA3_TRIG_MODE_EVENT);. ?% V5 T, {' a* l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 G5 Y7 ~0 R, m' e5 f6 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
K. s. ^) v; q# NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% {0 v: ` m; c' J4 w" VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; Z5 S9 R1 y$ {4 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 h# ^( [9 Q+ Z# s: |, s; T0 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) `" F4 b# |0 Q5 Z' G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! B% ?, p3 M# ]" F0 ]4 A
}
3 [+ g* h$ O) H* f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) F+ v/ d) n0 x
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