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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- Y# e# N3 r0 L. oinput mcasp_ahclkx,
4 _0 ]; Z$ F: ^# y" Rinput mcasp_aclkx,
: @0 g# W; F6 H; g6 I7 t, finput axr0,
% [6 {9 L! [( w1 F
2 S. @; z% x. i; D9 Eoutput mcasp_afsr,
{8 p" |0 s: `- U* C# Joutput mcasp_ahclkr,
* r& B h7 \: x+ q/ W5 Toutput mcasp_aclkr,' ?3 ~) F! r5 B7 c
output axr1,. x5 m( ]6 [; b
assign mcasp_afsr = mcasp_afsx;; ]& r) P `& q" Q
assign mcasp_aclkr = mcasp_aclkx;
+ X# y' p1 e. z: u( M& Qassign mcasp_ahclkr = mcasp_ahclkx;
/ w* b6 ^4 v7 M5 Q4 G' a# Rassign axr1 = axr0;
9 D5 m. ?3 u, O" Z( D' `1 q& l, P9 ~7 {1 E2 [* x% `) ?5 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % l1 Y/ j/ o* w3 \$ @4 I9 g
static void McASPI2SConfigure(void)* V) N6 A# q- [5 x; Y
{
. m" o$ F! x3 N+ ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 _, X) Z) r9 g A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; z+ e# C5 y' Z. H6 \$ Y [1 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' v! }' n$ L$ I, I! \( }* w( I9 o% QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! O6 V' d5 M/ ?4 c9 I: _( f; X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# Z+ Y* x) @) S$ c& N$ nMCASP_RX_MODE_DMA); J4 h$ ?3 ^; N9 Q/ w) A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ [0 }( w% {6 K# ?+ z, q# U$ Y1 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 e5 G- F5 ^+ t" @+ m4 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 e- j5 e) ]+ a7 [. w. e6 P' c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 a! p+ ~0 q' o3 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 _4 \( f5 L" P I0 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: y( U' k) |9 v1 S V) A9 c: G6 x. _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 e2 M2 ~( u5 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& n. W: g: N; mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. g9 l% u- e) q; l8 h0x00, 0xFF); /* configure the clock for transmitter */( @* ^- Y0 h9 V' y4 x8 ~! o r- A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# S. I6 V9 H0 Z( _9 R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 T' H7 U: l2 y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; k3 q2 X( b. h2 J' H9 ? S0x00, 0xFF);
8 z2 y, r; q; q$ a- @" i( m1 V- C ~
/* Enable synchronization of RX and TX sections */
0 ^: n! I: H" K* Z$ k2 I4 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 n4 h) C7 \$ J ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ {& T6 g6 Y1 Q2 L* S' u6 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 ~4 b0 r( ~6 C) E
** Set the serializers, Currently only one serializer is set as
# g1 ]" F/ Z/ ?6 q. p9 }** transmitter and one serializer as receiver.
, v9 A# v$ U/ o! K4 H*/
1 {, T/ r$ u# c; `3 y1 yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 T3 I' C# G& B) n. ~; v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
M' Y: h' t& e# Q+ L# ^** Configure the McASP pins . L. U/ }2 P7 w f8 z# \6 E
** Input - Frame Sync, Clock and Serializer Rx$ _& H6 p7 d1 N q' j" O; w: ]
** Output - Serializer Tx is connected to the input of the codec
" U) q0 G; y# s4 F7 B5 Q' w*/
6 z3 n. q H* i7 _5 y! }" h: n% iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! B# Z8 m6 t* E7 \, S0 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" Z) \* L9 g2 Y* J# m3 Q4 f+ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: K% v( Y7 a3 v5 [, ~+ g8 t) w0 W6 U% X
| MCASP_PIN_ACLKX
5 G. Z5 @) d0 l2 @+ t) p3 W! A+ j| MCASP_PIN_AHCLKX2 i, ^; {- K' j# c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% y: C; _' _4 K& G. u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( N( m ^/ w& x6 U, B' S: m| MCASP_TX_CLKFAIL
: }4 g+ p, Q* y( y1 L8 B$ L8 I J| MCASP_TX_SYNCERROR: m+ F. P2 N; G& h9 Q& K( O) F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 H2 I3 }+ F4 t+ O2 H6 v' e/ }| MCASP_RX_CLKFAIL% b1 u1 Y6 y$ `8 E) X/ l& P$ z
| MCASP_RX_SYNCERROR 7 e: Y0 X. {" Y; X5 V, Q c
| MCASP_RX_OVERRUN);
' l6 U- C& |: C' V} static void I2SDataTxRxActivate(void)
, f0 e- z& v! o7 \) ^{
& i$ u7 ~, y$ L! I, L: r/* Start the clocks */
' m/ p8 c. h# r: uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
Y& z/ c9 N7 P6 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 o" ^& c7 P4 ?. w5 e: K6 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: Y% L# j9 {2 n- {+ J2 [3 _% oEDMA3_TRIG_MODE_EVENT);
' H* S8 I( p" [/ Y' eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 d/ N4 D( x* W! b6 U( u- ?' s- N v, ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' D5 L# O6 n8 g7 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 V& s4 y0 Q1 X d( M9 C4 g6 t! F- `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ e3 h3 ~/ M) `$ B2 F' ]/ {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. ?9 U% k0 h( y0 Z, @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 b* }9 t3 P3 m# k" C7 { mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 O% q( B: Z" f; W! _3 K* f}
6 u r7 w2 J3 E; a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 i5 N1 i2 |: O& i) u2 K
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