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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ w5 O/ c: A4 l
input mcasp_ahclkx,
; V5 z1 ~. y3 a6 Y K2 F; O8 z, O0 n' uinput mcasp_aclkx,0 b- i' k' I. K6 ^0 f1 h& s
input axr0,
$ [5 Z* J6 R& g0 g Q) u
5 o+ C7 B- ^! T1 ^! G' M: @output mcasp_afsr,
0 Y3 b9 ?& M$ P$ Joutput mcasp_ahclkr,
: [' Q7 z; e9 @+ r2 S% m, B* O2 [% Loutput mcasp_aclkr,) w8 U! s7 n0 m D* A8 Q! Q" q
output axr1,
& @) V2 j: V% Y assign mcasp_afsr = mcasp_afsx;
% ]9 A6 J+ ?5 tassign mcasp_aclkr = mcasp_aclkx;
" @( Y. y. F: Q2 S" wassign mcasp_ahclkr = mcasp_ahclkx;
* t' [- M2 |. U% _ S. Qassign axr1 = axr0;
0 G4 ~, n5 A6 c: e; i$ n8 E( j7 g# H. L. A& {( f7 b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. @ W- ^# J( v* c2 [9 C; ?6 ustatic void McASPI2SConfigure(void)5 B; M1 e! s' O4 c' r
{
2 P) R3 J2 P e4 I0 O# DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# p+ R5 }: R: ?* C# [ K$ r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. s' b- X3 Z" e/ ^. ~- J* O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* J! [8 ~3 N5 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! O# n5 G1 }: z/ e: zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ T6 p, Y) H, |3 E5 Q$ ^
MCASP_RX_MODE_DMA);1 d2 M0 h4 J w! d. z' |! y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 x5 `9 t3 m& XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 l% W: |" J# s/ p: FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * m$ S4 H1 \( o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! I3 S* X5 f; A6 T& b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# N2 ?* S+ z* ~& vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 i/ l$ V5 M( e+ m& _; l0 ^+ {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ |1 V6 E. [9 t: m& | bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : c* y/ g# Q+ b( ^/ n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 H: R) A2 I( Q& E3 U9 M [
0x00, 0xFF); /* configure the clock for transmitter */' A4 F- Y( q a( n2 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 B1 |% s- c) S* Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( o) P/ { }2 {- Z u" u3 t+ W1 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, B3 L3 p/ N0 y. L8 \3 }0 v( G0x00, 0xFF);/ w0 X4 G% q) K$ q9 z
& n$ v* R" x' T% ^: L" }$ A, Q/* Enable synchronization of RX and TX sections */
# t1 j7 o( w, F. H, _/ EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, E3 s/ d) D0 C& e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 \3 a& y) G0 v9 ^; |/ \# a" }' Z6 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 W) p* V9 p) l8 \: S** Set the serializers, Currently only one serializer is set as9 K' x- X* F; o S2 L# \( c
** transmitter and one serializer as receiver.
. Q2 c( _3 C( T$ N( L! w, {*/
5 Q% I S$ W# [8 F9 R6 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 K% ^2 {5 K0 X/ J7 X3 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ j. A% U' Q# R# y1 ~9 B; z/ u
** Configure the McASP pins $ e: H1 V) j* n# j, u0 X
** Input - Frame Sync, Clock and Serializer Rx
5 k; y( h0 n( O$ h5 e** Output - Serializer Tx is connected to the input of the codec ; R2 ?6 z, O, \
*/
; ?) G) V, y# r1 aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ B/ ]- ~0 W }: k& n' y/ L# G5 |) `- D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- a8 |) F/ D7 G6 E8 p% [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# E" S- b" b) g/ H' s% H1 ]5 l
| MCASP_PIN_ACLKX
7 Z9 Q8 z4 a2 t7 h| MCASP_PIN_AHCLKX
4 J @- e* R$ j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- c' ^+ M8 a2 d' u! W8 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , Q5 O8 [6 d2 Z* E9 e3 f9 ]2 M
| MCASP_TX_CLKFAIL ; e, W& n+ n: Z1 W
| MCASP_TX_SYNCERROR
( y* w& ^; f$ r$ ~5 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . [, l$ W4 s% k) w, m" u; \3 P
| MCASP_RX_CLKFAIL
$ {; D4 q! N: A! n% r3 _| MCASP_RX_SYNCERROR
- V. c9 r4 C2 D) V| MCASP_RX_OVERRUN);
- D5 n. a( ?$ @' j) C4 u6 u5 l} static void I2SDataTxRxActivate(void)/ F" g( G6 W9 c7 m- c% `) ^" m$ x1 `
{' K: a" Q: w7 `# S6 R1 l. w
/* Start the clocks */0 y# l0 b* V/ f5 g) h5 z6 |) x/ }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% ?/ {9 K& }2 C, b: w9 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, V& u3 u1 F2 N) a) k) O* x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 m/ A, ^4 I ]- _2 o& sEDMA3_TRIG_MODE_EVENT);5 j* H/ m/ e1 _ l. {) o: J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" s) K2 T$ c( m k UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 B! T3 n. \" {1 e, b& w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' H) k$ H, |7 {2 m8 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( P! D/ g7 |0 i) b( B7 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 y8 @- r0 l! e- H# k3 J1 tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& y& ^1 @; N3 MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 a1 ~- }( ^* [# J
}
0 M5 L9 c6 O2 I7 f/ u% y7 V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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