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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. k" c6 G( G6 i3 ^1 e7 G$ S
input mcasp_ahclkx,
% d, [: e' T$ r- z$ hinput mcasp_aclkx,- {- k4 e7 q- N4 b+ w' q, C
input axr0,* k* u1 a% D- [
8 i( Z6 g; `8 ^output mcasp_afsr,
+ I" x* z+ f) h9 J# t1 i7 B& Poutput mcasp_ahclkr,
; {9 [" a: c5 N/ Ooutput mcasp_aclkr,
( P8 s6 |& y+ a5 ?- V6 Voutput axr1,
" _* s# L9 M, s8 x! \# y& j* q' i assign mcasp_afsr = mcasp_afsx;+ u, R- \2 ~ X0 v: C- I
assign mcasp_aclkr = mcasp_aclkx;) p" [- G- T; T$ _5 t: e! U4 a
assign mcasp_ahclkr = mcasp_ahclkx;& [$ j3 ]& ?4 x" q
assign axr1 = axr0;
5 Y" i6 {0 U3 g# ]% R0 Z D" E- l/ Y; w; z( O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 L v0 a+ u: {4 @$ n
static void McASPI2SConfigure(void). ~# G g" m- \- y' F
{- I; {% s* {, k# D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* h8 i# C+ `6 \" }5 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 T# _+ Z" S0 F5 T; Y' c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: a+ q7 I4 ?4 B7 Y9 e3 z8 q7 ^: Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* d4 e# C8 `6 r. M8 K+ _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 D- ?8 j+ i# c+ C# E7 t
MCASP_RX_MODE_DMA);) o4 G G* I' A! q- ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 d( z1 G1 z7 F. mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: l1 g0 G' i# X7 d* ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % c q7 A: l% e& U" c; I, V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ ~1 ^+ A x3 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ u+ T$ \* W: R: m; K/ W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, u! O! j* A. m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- _- i' D! g0 s) v- c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) g U7 i; P$ ?4 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* \* ? X3 y( z0 {! h( a+ b
0x00, 0xFF); /* configure the clock for transmitter */
# y8 ~& f: f; _* ?; YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- G1 I8 X( l5 q# S; y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! N; ]7 r6 V% L( u" M. ]! {" y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% t9 O( b* r: j& ?0x00, 0xFF);
/ f7 [/ W9 y' I- x {4 v% @
' ? s, i- F5 M* V* Q1 W/* Enable synchronization of RX and TX sections */ ' K P: a5 a. [6 V: F2 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" L* ~2 K( z7 |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) X8 Y3 a3 h: s' h0 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 S- q" w5 x; V7 ~' i; ^
** Set the serializers, Currently only one serializer is set as
# T, v9 n, @7 _8 X' W** transmitter and one serializer as receiver.
) T! [* V$ M4 i7 Y! D1 s% y*/
: M$ z m1 ~# L* K& fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" m+ u5 t, J* y- ?$ h& y& t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, n5 d4 ]# s, h! @, o# ~# x. C5 b** Configure the McASP pins
) J/ y& |% V: l( P0 f$ { H** Input - Frame Sync, Clock and Serializer Rx
2 \5 K$ _2 A. Y9 U/ Y1 j3 x** Output - Serializer Tx is connected to the input of the codec 3 {4 q2 V: f% u$ U0 T
*/1 s! {2 @4 j' E6 v! [" s/ e! f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); s% |9 I% V& S/ T! V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 L7 |" X( a8 S& ?/ C, FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, F8 @" Q0 b4 T/ r. G M
| MCASP_PIN_ACLKX
3 a- \( u5 I$ B( `. X# S| MCASP_PIN_AHCLKX1 S( X( m" e% ?0 K" g( O9 m2 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' m% M* @7 o9 @7 [( r& U3 t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR j2 M8 q& Y# u5 S8 c' E; F
| MCASP_TX_CLKFAIL ! c G; |. k, |5 `% {
| MCASP_TX_SYNCERROR* R9 V+ T+ L4 Q& S% D/ z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " E* H5 Y1 N) e u' O/ f
| MCASP_RX_CLKFAIL' Q; O2 D+ V, C5 z: S# R) A% b
| MCASP_RX_SYNCERROR 9 |+ g1 e1 a6 l* W
| MCASP_RX_OVERRUN);
- D) D3 K+ x& }} static void I2SDataTxRxActivate(void)5 u$ z3 I2 |5 h2 J4 y9 {3 [" r
{
4 h. w: z* L" U& x% M# j% h/* Start the clocks */. P% s' g0 f* `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 P6 R+ m" ^0 y* D0 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) n/ N8 b2 j6 S- {) v0 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& {/ S/ x7 t0 k5 b* \% o3 \( ^EDMA3_TRIG_MODE_EVENT);
. t) \/ l& w/ P& EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 e4 Q' l( M2 T9 S2 E) I! E2 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 V9 T9 m; `) q( V, rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 l& `/ |! ^; o V3 K DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% l! {/ L0 g+ Q9 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 o! `" o/ K2 @5 y A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' s) m3 L- \# e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 {' R8 C, |1 J; k5 n8 _}
) v" J/ W4 z. A: F/ ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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