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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- {% q2 V0 L( {1 K6 ]input mcasp_ahclkx,
* b9 E/ \' e/ n" Q, `$ qinput mcasp_aclkx,
2 b! G0 A) B: ]% Winput axr0,
6 z' N0 T9 ]' A" N+ J
0 D$ ~1 N6 W& P2 G, `7 @output mcasp_afsr,
6 B8 b$ S7 v4 ]( P4 noutput mcasp_ahclkr,
6 i- ?8 y/ L3 y2 xoutput mcasp_aclkr,) S. b4 Q1 p* O
output axr1,- z- M1 J) K3 \- C- Z& w
assign mcasp_afsr = mcasp_afsx;4 k+ w5 X5 H% V+ W0 F. l
assign mcasp_aclkr = mcasp_aclkx;( \$ V3 c. m$ W& U2 O
assign mcasp_ahclkr = mcasp_ahclkx;
0 `, i/ P! D6 H ^, L! ~assign axr1 = axr0; " j6 O8 X1 t! K
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : s3 I- a) D' T! h n q
static void McASPI2SConfigure(void)" c t+ s8 L% {
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ ]; V) ~) N. \) _4 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& B9 O: r Z2 _5 l! w Y; X* M" W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 i3 p& {; n) ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 k6 t& ~. H( VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, r* r# D3 c/ r1 m% y W* B5 W
MCASP_RX_MODE_DMA);
) L0 K2 q* h8 m. h0 r8 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," t2 M# [6 V# @; h. _4 a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* i9 u, o7 N3 a' v& I% ]& l6 WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + z( \& e' z; }0 ]) a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
K$ E* j, M, N5 R& \( tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 O7 l U& @* U' D" D5 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
O( s" R1 o/ H" k2 d k4 n2 FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; F. e" @& Q* ~" N3 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! U% o# p& ~2 k) P8 Z6 \2 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ P5 H' H+ x* c; ]# G
0x00, 0xFF); /* configure the clock for transmitter */
R2 }6 [0 `1 K- rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) P+ w2 B1 l+ C7 X1 }) K- y! J! ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) s" k1 S5 T" I* d3 t$ |4 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# ^ T9 T: u5 s: t8 g
0x00, 0xFF);8 ~6 N+ M6 X2 j1 o, P6 p f8 e. [' j) J
' U5 x3 ?9 Y0 z# v
/* Enable synchronization of RX and TX sections */
* `7 v6 [3 k: |9 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( t! k1 N2 U8 F! y" z& t0 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ r3 L/ U+ O' A" U W* Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 b8 Q. \' I2 H" m6 Q* |0 a% T0 n
** Set the serializers, Currently only one serializer is set as
7 T4 v! ^. k6 w2 Q' |** transmitter and one serializer as receiver.. `, N* P6 u5 Y% R' o- n
*/
" Q4 |5 y, p( I+ u6 n9 v, oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 A. o$ ?5 ]7 X8 k% H' O6 \4 t4 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) f \0 P. N2 [1 j* S$ U" k** Configure the McASP pins
0 {3 p9 O: A9 W** Input - Frame Sync, Clock and Serializer Rx% |! ^# X( U) G
** Output - Serializer Tx is connected to the input of the codec
/ n: s/ U5 B+ h" m. ?) V4 [*/
, S! r/ B- e: [" Z3 b, s9 A: y4 ~# VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); A1 F& B6 k# C" {9 X5 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" u- N- f- e4 |; Z! u% _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 s4 w+ a3 g5 E* E C' Y| MCASP_PIN_ACLKX
$ y" r8 n0 B' q) X6 E9 E5 e| MCASP_PIN_AHCLKX
" G6 J' A/ L& S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ {# J5 v8 \/ u5 _7 C0 d/ u9 j p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! W7 _/ k7 F& W) X$ I0 m% o7 }- C| MCASP_TX_CLKFAIL
4 P a" q8 n$ q| MCASP_TX_SYNCERROR, V {: |* w9 E# J8 K; x# P& P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % e2 G' O, M1 y) y# w
| MCASP_RX_CLKFAIL( K: p& N1 E# M# z& V3 j' P
| MCASP_RX_SYNCERROR
. @3 b) U, B' ~! p, u| MCASP_RX_OVERRUN);4 M! [0 s5 O( @$ P# [
} static void I2SDataTxRxActivate(void)( e/ x7 s( o) }7 q* d9 K6 f* k
{
9 M. i2 v- D5 E$ Q/* Start the clocks */
( P. _0 d: M* ]) r! VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* ?" g6 ~$ H" K( `/ T) I- F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# |6 w! {; {' U9 `+ ^. e7 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' i5 W1 j* ]* ` V& d. l3 P, Y0 U
EDMA3_TRIG_MODE_EVENT);
$ {: t* h5 J, G0 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 C3 S4 W/ N/ X3 @$ y; p" F# R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; ] e0 O9 @+ o5 z2 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 x1 i% m, l7 A3 t3 o: d: C* I; rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* P0 E: @) I- z) |- ]* q# A/ wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 | h2 `6 ^" @7 L, V+ {1 s a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); R0 G& X5 X: l8 O6 x( _: P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ v# A' l9 Y+ |) p+ s F
}
) T7 s3 z+ k8 U6 d, K. M/ P( k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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