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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) i+ t8 l! ~! N! sinput mcasp_ahclkx,
! w! ^/ R2 p+ T$ Sinput mcasp_aclkx,% F" Q( |* y+ C# i2 X% ~2 }7 H7 X
input axr0, h& k; i @. X" ?& L, c. T
6 n2 M/ u1 T0 E8 s$ toutput mcasp_afsr,$ N4 e. {/ ? i5 m
output mcasp_ahclkr,
+ L( O6 j. v+ W9 Q) }output mcasp_aclkr,* S7 i/ E! K+ v' _
output axr1,
+ l; I) l4 v# R. X9 P ` assign mcasp_afsr = mcasp_afsx;
4 Z9 c9 G8 {% q6 |8 G: I. d$ p9 g/ Zassign mcasp_aclkr = mcasp_aclkx;; b- h& R; Y+ C% q1 y
assign mcasp_ahclkr = mcasp_ahclkx;, U) v L. i& b$ H
assign axr1 = axr0; ( c& j, c- ^4 l# ^: e. _
& o$ D& o$ I0 r) m' k" D* [& |" A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 Z' q0 b! h. i4 v) Hstatic void McASPI2SConfigure(void)
3 _7 ]7 \3 t/ b; r S{
( @! G% O7 q4 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* C1 o+ z. v4 f- oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: M# n& F, }0 C) |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: c. J6 u3 K- t) S$ z% u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ a$ H" j6 J5 {. Q+ B7 J9 p+ \1 @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% o% Z, M3 |% g: GMCASP_RX_MODE_DMA);/ G: c" @0 T8 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ w) g7 j* G3 {2 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* ~; D/ E. e9 [- O: QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% [( {+ n0 S- k* J$ qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! C% l- b; f# z9 }- Q8 R Q# m+ T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; a- k& u1 f: PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. k' x8 {* M+ L$ Y' LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 B- z/ A. g7 R) E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! P/ Q7 ?# S' P4 M0 c8 O9 v6 ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
@7 U" M o# J( ?$ m5 X1 }0x00, 0xFF); /* configure the clock for transmitter */' i5 n5 w [* r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ t% J4 G6 {6 w2 x. k7 K# e6 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / _/ p$ q& `' `6 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ T+ Q* M7 A5 j( @7 \6 s
0x00, 0xFF);
6 \. C2 b3 J. S9 ?+ C
$ y8 w3 u" s4 j7 M1 V/* Enable synchronization of RX and TX sections */
8 X2 N' H; Z( R$ ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) G1 ^) \9 j1 ]: QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ Q/ k& O4 z+ I$ p7 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ |/ Q. k& k. p$ U6 A, s" @. V) ?
** Set the serializers, Currently only one serializer is set as
" `/ [ w8 i* j5 D** transmitter and one serializer as receiver.3 b+ H+ @# s4 S0 M
*/
0 S7 R) ^6 p( [6 [1 a. `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* |: P1 m1 f" `1 P3 VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# @3 M" X6 S) H6 j9 V$ B) V5 o# K6 Y' }
** Configure the McASP pins
; d) j2 z' o" E1 j1 S9 w** Input - Frame Sync, Clock and Serializer Rx
- F+ u& B/ ~* C( q# a" L& T** Output - Serializer Tx is connected to the input of the codec
0 f: m1 q' N) q$ ?2 R*/
* W: `- y* o1 z( W3 a- T# Y7 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& ~+ `# c n t3 X# u2 a& U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; W$ ^" S8 J$ l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 N' H4 }' @% s1 C+ _# K4 Y| MCASP_PIN_ACLKX
& |% r5 d/ G; G( L9 x g| MCASP_PIN_AHCLKX# K* ~0 }* T: Q: R. A, f2 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: t" `' g" y9 w9 T1 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / R" x" ^+ q9 t. y
| MCASP_TX_CLKFAIL
# O7 s' ], y) W6 J3 Y% b| MCASP_TX_SYNCERROR
- T `' i7 N8 o0 @: W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # {. _) r* L- g4 b9 I7 p
| MCASP_RX_CLKFAIL* a+ n( y# A: R. L
| MCASP_RX_SYNCERROR
" x$ K- j" J' v& }. s$ o| MCASP_RX_OVERRUN);9 T/ L: S x, s }
} static void I2SDataTxRxActivate(void)0 ^$ a2 L; a* p# t4 @
{2 j2 e/ D0 `7 c2 k
/* Start the clocks */0 i, O/ M5 U& t! Y# y! K C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ U" p. J5 q$ s* A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% r, P4 p8 @% ^3 x0 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 j A; \5 p6 K# R3 D
EDMA3_TRIG_MODE_EVENT);
3 v. @" p/ K8 ]3 j! n" ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 i7 ^. ?- \! [/ |7 o5 `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 H. Y, W% {6 m( gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 `6 c# ]) I# kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 J% J9 A% e lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 A# f0 `# Q9 Y. B% V- sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 j+ }6 W% K4 V3 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- ^) I! @& T3 {, _+ O. C
} : S- V( ^) E2 X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( }# ^3 n% j6 b% s
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