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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# N' L( \, _; n0 ^input mcasp_ahclkx,' J$ ^/ _- ~$ z5 z8 _
input mcasp_aclkx,
0 Y, K" p- k' z$ E" k! @input axr0,2 O6 y) m8 v1 p4 N6 l2 P
; }) k P6 {9 O- A6 v' i/ ?7 Toutput mcasp_afsr,
9 \& f ^- K- {5 R9 j6 j, K6 T, M2 x5 zoutput mcasp_ahclkr,
~/ H- ?& x) }3 j! l) X9 p( P5 u, loutput mcasp_aclkr,7 `% k2 W$ B4 g5 o q# s L
output axr1,* R! e! z9 N: [8 ~9 A) d8 Q
assign mcasp_afsr = mcasp_afsx;: u3 F+ \' T3 W; [
assign mcasp_aclkr = mcasp_aclkx;
8 k+ K b" l0 Hassign mcasp_ahclkr = mcasp_ahclkx;
% o6 V/ R8 ^0 U$ Z6 y7 M3 passign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( S. Z% }. Y) l" c: n' T
static void McASPI2SConfigure(void)
( J7 h: B5 k/ P; [4 z6 Q{$ @: S) y& O/ K1 F! `5 C6 u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 V& ?1 o- y0 X2 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 @# U6 `( h" w FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# s3 b' M" B4 r+ L6 TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! g: }( L& j/ f+ p- d4 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- {" r; r' O: ^* g- n3 N/ Y9 M" }
MCASP_RX_MODE_DMA);
9 k5 X; A7 ^. ^2 O lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ f7 @; ~6 T: n& HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 F. O. L& ?; Z+ w& ~! e1 ?; b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( } F0 I8 J( N$ w$ ] {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 p! _: b+ h7 x" }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, B! s8 Y! ~3 m- B, M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 L& e% \( O# X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( |6 n: T6 e, n6 bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : q2 x( ^! ~/ f% B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 Q3 S5 G5 r* a) ^$ q- A
0x00, 0xFF); /* configure the clock for transmitter */9 P5 I! w7 ?8 d, N8 _6 a& Q z H. [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( s3 Z9 K! f6 q* i5 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 ?! d2 m, d% d# |( w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) q: ?4 x7 x9 S; ?# ~: z7 ~0x00, 0xFF);( N! i1 p3 A) {6 G8 D
* x6 l C/ u4 ~* X& B6 D/* Enable synchronization of RX and TX sections */ ; d$ J$ R& S$ e3 x- v( w9 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# L' E! T7 L p& w. t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 a1 N+ N, }6 X# D! ]! e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 C+ F3 f8 H2 y+ K4 [7 }1 S** Set the serializers, Currently only one serializer is set as( I# _9 G8 @" Q! }2 T2 }# k; q! s* V
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ k* P1 s) Y( e' ^& X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! u. e R% r9 x/ ]** Configure the McASP pins 2 Q$ d: P/ a2 w) e1 H
** Input - Frame Sync, Clock and Serializer Rx
; r, ?0 t' `& y0 o** Output - Serializer Tx is connected to the input of the codec
4 G% Y; i$ B/ c3 j8 y4 S*/. i4 r& x' V# j1 g9 h6 Y8 x9 E, Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) ?# k" {2 S2 o3 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 T+ X( A0 ^9 P; J7 g/ G- o; HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* }$ J. [+ f& z% O# G| MCASP_PIN_ACLKX
, Z. @ s: W, x+ X9 K" ]0 ]| MCASP_PIN_AHCLKX
6 _, Z0 H( {* d2 j) W2 p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! g* r( I3 n9 Y& @5 T' l+ D! WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 s0 |, S6 Q$ U' G, k| MCASP_TX_CLKFAIL
6 r; D* u( j* e4 ^5 ?| MCASP_TX_SYNCERROR( o% g h* R, R/ \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& A% R' W5 Z( o4 H2 L. C8 S- U| MCASP_RX_CLKFAIL; s6 @+ U5 L' J4 J, s# p) B
| MCASP_RX_SYNCERROR
4 c: g7 A1 G+ _" E| MCASP_RX_OVERRUN);0 d8 o5 {+ O. `+ L0 d& P( q
} static void I2SDataTxRxActivate(void)
" V5 N9 q' q* D2 s{* {9 ?) }) r3 }; p# O8 ^( M' K8 J
/* Start the clocks */
1 x- q$ k$ s4 U3 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" S/ p1 Z2 [1 i1 b+ `- b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# v8 j2 P; Q8 o9 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. }8 D- B$ K, d% ]
EDMA3_TRIG_MODE_EVENT);: h) t Q6 g! l* i+ h$ I7 g! M) T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 n$ K4 f! @7 @* q" `, [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 x+ _1 U: v& G2 f3 H& o" ^; l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 [# {% q- V+ f2 X% A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 n- t2 H$ ^) f5 k* R, G; ~; |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// Y% L3 e! S1 R. Q, L+ g! T- j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 Q/ c$ E( Q' T2 ]' tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% T9 e- j4 f1 v' j& o# ~/ h" \
}
: D n) j& g9 W8 v+ k2 Y, K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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