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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ Z! o7 o" b+ G1 O9 f' w! l
input mcasp_ahclkx,
, H: h( M6 Y, a4 s0 t, U0 rinput mcasp_aclkx,
& B( S7 [' ~ Dinput axr0,
* t1 |0 G& b( P& _3 [* A& v: r
( ]4 C {* I7 p/ Loutput mcasp_afsr,
( f- t7 J' {/ [7 v/ n+ xoutput mcasp_ahclkr,
6 f8 B. _7 T9 ^4 |6 H! _output mcasp_aclkr,/ \6 m G6 I, |$ p: S
output axr1, X- h% f6 C+ N/ a* Q
assign mcasp_afsr = mcasp_afsx;8 U/ R* p" _& d
assign mcasp_aclkr = mcasp_aclkx;
" A. o- z+ B. N. e+ l5 hassign mcasp_ahclkr = mcasp_ahclkx;
8 M! o+ J# j: }/ R( ^+ Lassign axr1 = axr0; 2 F1 d% T2 C2 I, x; s0 t
7 q3 v9 _; e" m: h# t/ n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 x+ I) U- D, y! A+ N: W1 w* j7 Pstatic void McASPI2SConfigure(void)
. N( y: [" Z3 C9 ~' u) Y{: @. F! v1 Y6 G+ z8 `# C7 }; ^( R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& Q" q2 ], E3 L1 Q' v7 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( s% A% @7 K% }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ |, u5 U2 H- q) JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: L2 Q% V3 ~2 W4 `) DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ E: ^: }; N% o9 P# V/ `1 {MCASP_RX_MODE_DMA);
4 u( v# e% ~% U+ Z: _3 E! bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- @8 Q2 G |; _6 W2 R: p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 T5 G p0 M, |9 y' v* Y- m' E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 `1 Z3 c6 v _5 m8 v/ ]0 a) T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 |1 E* B9 J6 y3 W, a5 ~3 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- }8 O/ b4 K9 Z- ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" L' N2 \. |5 G% o' R% s i0 l' JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. r9 s! o- U6 q9 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 r5 ~& @6 N- H' X9 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 V5 H1 G; s/ `) z/ o) x
0x00, 0xFF); /* configure the clock for transmitter */+ k* G: b) r. v* D) g8 B; c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' c/ e. X: ?: w" d! o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 G1 ~* r F4 l! k' T! P" A9 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" l2 f6 i J. h% f1 |9 ? o0x00, 0xFF);
- H' Q1 o. r, w* ~$ f) c) @- j q# h8 y' m
/* Enable synchronization of RX and TX sections */
4 W$ f5 s% T6 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( \- c" u8 C5 \3 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 }+ }$ y1 c8 ^2 C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ o& a R# h, U. t7 ]** Set the serializers, Currently only one serializer is set as
9 J7 Z P3 y( T" |- G** transmitter and one serializer as receiver.
+ b9 ]3 h9 \) ~) g* }: q*/
8 r4 V. u# d1 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
J8 J; s0 c. qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 a% ~& W, @3 @1 e, _( k
** Configure the McASP pins
, A( u% D G- }; v** Input - Frame Sync, Clock and Serializer Rx
2 }7 U2 X/ u% T- o3 N& k** Output - Serializer Tx is connected to the input of the codec
- J3 q( O2 o- |*/
9 o% P( A9 ^9 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" ] M( m4 k/ \1 p' n3 c; TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# ~( z$ i1 A$ H2 G" TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ R) J7 O3 J$ F- i# e
| MCASP_PIN_ACLKX
$ A2 H' E+ ~3 K& w Z; i( S| MCASP_PIN_AHCLKX/ h' M& D6 h0 w+ I+ Z: Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 E' S, r( }+ l: f7 j! v0 \3 v6 S& |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % B" ` Z# ?0 c" {# X# p
| MCASP_TX_CLKFAIL
- r, r4 A2 M" |# E$ u2 a% t| MCASP_TX_SYNCERROR) T- Q5 W. e* I* a0 w) D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 g+ U; [7 _ F8 D( ^$ P/ H
| MCASP_RX_CLKFAIL M4 X z% C8 Q( x
| MCASP_RX_SYNCERROR 6 u9 X5 b4 p& ~8 A1 f( [
| MCASP_RX_OVERRUN);1 m/ H6 a. G6 c4 d8 O, h X
} static void I2SDataTxRxActivate(void)% Q' Z" y% O g9 d. P- E: ]
{% x. O0 F4 @. z1 H. ]
/* Start the clocks */! E0 d- s* m. h; x8 X! d: }% H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# x8 [8 J( D, P* L# \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ y$ N0 e7 G0 h0 |/ t' B7 F7 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% C* B# f, x" d7 N% S9 q
EDMA3_TRIG_MODE_EVENT);
" U. b1 r, x+ C! L) Q% jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& y& s3 F) b. K; b I6 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& _4 h e! _5 j' ^3 x7 a9 a8 u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ W0 V" X' L& X& q# A5 Z. N1 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 `5 j, L, k' r" P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: B+ e+ n2 z7 h: M% Q& g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' o1 q# G0 O2 G* _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* \& y; L- G$ H" ]) T
} 3 h$ o) o8 K1 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / v' X! R' H2 t5 `
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