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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 [. B9 [* r8 V- c: X% Y
input mcasp_ahclkx,
0 r3 v+ V: y$ i' V+ ~+ ginput mcasp_aclkx,9 d" S! V# i+ I. t T. E
input axr0,
% ?# ?* p2 O; j7 |' |
2 Y" E3 ?; V) ^6 E- V! Coutput mcasp_afsr,, w- f+ C: d) u# R
output mcasp_ahclkr,6 _4 `9 p2 e2 ^6 \& v0 [2 n' G
output mcasp_aclkr,
j8 H/ t, V! ^: youtput axr1,; _* L- B4 r: P
assign mcasp_afsr = mcasp_afsx;
8 x3 u# N; P7 j) D ~5 A$ C2 gassign mcasp_aclkr = mcasp_aclkx;
: A+ j! H3 R% L O* V: u8 n. rassign mcasp_ahclkr = mcasp_ahclkx;
$ z; X/ Q# u0 N9 ]assign axr1 = axr0; . U, [. d) i( J+ }1 w* |0 n
+ h P. M; h5 y+ U* i/ C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 f y/ X5 F' R' e. J( e* Q
static void McASPI2SConfigure(void)
0 S+ X1 a1 v$ d' s. J/ z' [ a7 P{" F: K6 B/ R: K3 H) G5 s- i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 u8 {( w' d' Y( r5 g& ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 _# w9 A8 u# k& ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 u! M5 I1 p% m7 F4 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ {7 A# i9 N/ B/ i( d2 L9 H" T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ~1 ~: a. S* kMCASP_RX_MODE_DMA);+ @+ ^- J9 S/ C! r* t$ `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 P O4 z8 }& d$ u* p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- _1 y( n) ~3 }2 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + r8 u! {- i- T9 l2 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 Z: d. U4 l! }, U+ z# O. NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 i) ]) p) C. J7 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* T z" C0 y# L5 M. C$ ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 m8 R9 s1 o7 w* |6 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( Y7 k8 b2 V/ l2 ^, b0 oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# w$ M! S2 W7 L0x00, 0xFF); /* configure the clock for transmitter */
( I. t5 i3 ~9 h7 l4 ~( U3 ` g7 a/ pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 Q( m+ g! t) s1 f! R$ t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 k7 \3 s5 l) k# g9 @- P w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, [) n8 d/ [5 p$ `# {# o
0x00, 0xFF);
. x- @6 {/ F+ `( t' O9 t6 k
& l( M2 [0 v4 ]/ w4 r6 Z/* Enable synchronization of RX and TX sections */ ' U( s* Y% \# U x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 X$ P- Q! k; m# U6 H N, vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 L& j. c, I6 A* A U1 B( hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, ~$ S; A y9 n. c V4 Z- c, t** Set the serializers, Currently only one serializer is set as
, U% g2 Q# |# U) F2 m: b* c% Y7 Y** transmitter and one serializer as receiver.
' n' l8 {0 m2 `, I* `/ g! ^*// D( @9 w/ ^0 E6 a+ \. l* a0 \1 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- J9 W$ x5 x, M( y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 u) _! ]) Q+ P0 Q S: s' B7 `+ v; O
** Configure the McASP pins ; m: E8 v! o6 ?2 D4 h2 [
** Input - Frame Sync, Clock and Serializer Rx9 \* P+ F0 \* M) {# b" _
** Output - Serializer Tx is connected to the input of the codec & Z0 I& S M, y* q: d
*/
. x$ f7 ^5 ?- r( ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 v- Z6 z: o4 `7 y% r6 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 h$ |" F/ t |+ e0 \7 QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* n, Q' d+ G" y# k. e# D ?. z! U| MCASP_PIN_ACLKX. I1 z: F) P5 I+ j2 P: B
| MCASP_PIN_AHCLKX
0 O1 w6 E% S- |& c2 ^# m' I( h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" T- o5 p- O) V, p; c6 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 _* c& M* ~- E/ `
| MCASP_TX_CLKFAIL # ]: H) m. m3 _! i4 O
| MCASP_TX_SYNCERROR" Q4 B+ N* `" Q% d! Y0 l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 i o* Q" y* [# ]( h1 X
| MCASP_RX_CLKFAIL
0 g9 b6 J8 P5 M4 u8 H/ L- h| MCASP_RX_SYNCERROR
, T/ r: C/ A4 ?' q' @; O| MCASP_RX_OVERRUN);1 J1 \ r9 o- i) C; p: \* o4 J
} static void I2SDataTxRxActivate(void)2 P; u) y: L( T+ c/ ~
{7 U; Q' _4 A" H( h5 I
/* Start the clocks */1 O' Y: M& s6 ?' \. w- S& S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) |8 |: y" Z2 O3 `8 ^5 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 ~' q, g5 c2 [9 U" U5 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' m; B& ]8 d# Z# ` M
EDMA3_TRIG_MODE_EVENT);
4 j' q; A# g' J6 O% l0 S1 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' J0 z2 `, r8 p9 K8 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ Z. O n3 u2 b; K/ [7 ?. b: K. @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 G% ?$ b# a1 o" j1 \/ g5 P3 K/ QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" H. N+ T" G& O. P. V" j) wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 F' l' I) p+ }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! } J$ M3 y5 r, q1 Y! _- |% Y% Z6 i7 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& \, u7 T5 e# ?* L* z5 t" _}
) k: R6 |8 T6 d; ^; p* ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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