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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ f, a, O2 d9 X3 J' r9 O \# z) Yinput mcasp_ahclkx,
( Q- ~2 _4 U E, f3 Kinput mcasp_aclkx,
5 t% E( |& T0 R- d6 einput axr0,; V8 D/ L% E4 o3 |" Z" b) X
7 u* T R3 L* D* @, Coutput mcasp_afsr,
" q/ e& z" s, _# routput mcasp_ahclkr,* g5 z; f1 Z+ S# B/ M
output mcasp_aclkr,! N3 u' t$ n: U
output axr1,' q K0 ?. }* ~5 H1 h/ C
assign mcasp_afsr = mcasp_afsx;
8 h1 e4 g: C4 dassign mcasp_aclkr = mcasp_aclkx;' y* H& P6 I+ }- }8 i$ A3 \- M
assign mcasp_ahclkr = mcasp_ahclkx;
* M* e' v3 G5 s# M2 R/ b! oassign axr1 = axr0;
5 d: S7 k/ A: b$ k1 G& ^5 j' P- ?* e% e" ~/ ~$ N3 `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' v3 L" V/ h* C) o4 ^! G. _/ [static void McASPI2SConfigure(void) d: B& ~% Q; e
{
+ u/ E6 M# t3 ?2 Y0 zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 H1 f6 F$ `5 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 U* Q& l9 }0 Y- r! hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 _! p+ @: }# nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- f Q5 ~" n5 U3 P( K. |- v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% U* i' d; g$ M# X$ ~6 {MCASP_RX_MODE_DMA);! z6 M1 m) f& A* K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 W N2 j) u3 L$ YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 C2 o+ D; C: F8 S% G& ?" [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" b* N* m/ j! |- X8 L2 p) M1 M0 \3 g- \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 O: }( X: n' X2 f& c8 P! b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : i3 T2 M7 [+ H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 U" L8 p8 _. K) O [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' |. F% J! _3 F. Z) x& Y& OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& p- T" |1 U" d" ?! a) L2 U8 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 O# p4 F; H* v9 Q+ \
0x00, 0xFF); /* configure the clock for transmitter */
' b6 @# `% O% B5 \0 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& b! `+ R8 u- x/ {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, H8 d8 l j# r) B2 tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- p6 t6 x0 a' L, |4 d% w; \" W
0x00, 0xFF);
6 e5 v7 |- J7 L: q1 U# Q9 O. |8 R9 @$ I# k2 a/ q4 l& X
/* Enable synchronization of RX and TX sections */
$ k/ m( h- R/ l* \3 Q% OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ Q2 t! B; p* C( o( I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 z8 W2 p0 l8 @) W0 ^' `( a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 k9 M2 b9 A; ]* O1 @
** Set the serializers, Currently only one serializer is set as
5 @) d8 u' d, M0 z** transmitter and one serializer as receiver.
. k2 Y) k v& M9 X$ S& ~7 O* w*/
& W4 q8 O" K; S0 u, PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 j, M; F o% p# O" S- {2 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 `; p! X& |5 L9 ^- t/ |5 R
** Configure the McASP pins $ k+ c1 ?! c: u
** Input - Frame Sync, Clock and Serializer Rx
8 h3 w4 x O6 E( Q# v( w" \** Output - Serializer Tx is connected to the input of the codec
/ ?3 l. |! M4 W4 G*/( G' @/ ^& I( {8 a2 j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, t* {9 y: d; l! ~ e. EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' T" a( j h9 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ @( D1 \8 f, V| MCASP_PIN_ACLKX
; _- l& U+ N/ Z" f$ {| MCASP_PIN_AHCLKX9 t6 G6 q! x. b3 w' T3 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 `- l( d0 D8 X6 ~) ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : G0 M2 ]+ @7 S$ G, H& E
| MCASP_TX_CLKFAIL
$ E* \* M7 P1 M3 f1 T$ r| MCASP_TX_SYNCERROR
: h: t4 ]# f. ^8 r2 T4 Y+ y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " Z9 L6 C" i5 \. T3 i
| MCASP_RX_CLKFAIL3 m: L! k; E0 }" k e4 |
| MCASP_RX_SYNCERROR
# U' [+ X( p6 R- p! o; m- W/ M| MCASP_RX_OVERRUN);- e" j6 A: j: G: ~9 o8 _% G. |" O
} static void I2SDataTxRxActivate(void)6 W( L3 \8 v% v7 t3 l
{2 `! I0 e z5 _& ?% c4 }
/* Start the clocks */
: a- D' G5 @- A. ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Z5 R+ P9 z& N/ aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& M* }: s! c. ?, c/ e9 ]( O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% t- b* t. C w: G; N j3 EEDMA3_TRIG_MODE_EVENT);% M3 J$ T# K$ z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' N) P5 u0 J0 [1 k* R# yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& k3 w8 J' }5 H" M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ B3 e/ p7 V- [' D) t5 }& P* `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( S% E+ P0 \5 K, V% @& q6 U! {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& R {1 G) w1 ]6 [1 C8 q% X7 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" d: y! \/ E6 a$ z# _7 j: X* s% uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# p" ~/ Z: J9 @- G
}
- U, U( U/ o/ {6 J$ v6 `" n y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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