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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, ?7 n9 l; q3 ninput mcasp_ahclkx,
' J9 M& d8 h1 j- Iinput mcasp_aclkx,
" l6 D. v: g1 q9 A7 j) sinput axr0,
n! H1 k+ J! p1 e4 \' O4 w' z) n/ k7 T6 C' U
output mcasp_afsr,. g g% k7 ?5 |4 m0 Q9 S
output mcasp_ahclkr,
6 p; ]/ \4 N6 K0 @8 n' moutput mcasp_aclkr,8 N/ W# e( ^/ B1 W2 N" E( W6 j
output axr1,
+ l& z: d S/ b8 B0 ^) x$ l9 n assign mcasp_afsr = mcasp_afsx;
/ Q2 M- e4 x& Z! q+ Uassign mcasp_aclkr = mcasp_aclkx;+ y7 F/ q( j$ Q
assign mcasp_ahclkr = mcasp_ahclkx;( ~' }% d _& X, k o
assign axr1 = axr0;
, r: `& z5 p8 `: i7 I! n. D; Q" v9 e; u( w" x% L& Y1 l5 q% h% ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 P$ v) E* c/ l" ], |8 Q) i" w/ u, s6 A+ Ystatic void McASPI2SConfigure(void)+ b7 k/ g. f) H. O0 S3 Y! w
{
3 w" v) s! s$ S6 I9 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ]+ y: i/ g: j, u% YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, ~3 F2 U" S* C5 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) o! ^5 D6 A& q2 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. e6 C' C0 x2 G. Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ T. G' a; X5 w# b5 sMCASP_RX_MODE_DMA);
8 n% g% s/ v9 X% PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 d, p9 S- G8 ?$ K0 P& q3 w* aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& a. h3 o8 g8 b) d9 g4 J/ _+ ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. @. j4 }: U. x, C7 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# H/ B* A* U' G1 GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 ^ l" k- ]6 b0 J* Z' v+ j, bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" m" }* O7 K0 J! s3 Q1 N! dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) }, e, u& F4 @9 Z* o( }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ q0 W1 z7 m; P I5 U" J! \; L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: a9 x" P6 ]" j4 c! B
0x00, 0xFF); /* configure the clock for transmitter */$ |/ N- ]( @# x) }0 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* m: ^* [- s* I1 W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 A4 o' g# k. g4 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; W# W( d! S! A( u9 L/ t) h* j& F
0x00, 0xFF);
% {, U+ U$ B8 m; A$ s0 @4 q+ d; ~0 T9 y/ z, l
/* Enable synchronization of RX and TX sections */ 4 W, {3 o9 ]' Y& a9 p. q+ p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 \7 ]- @ Z$ W+ ] s5 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 j9 p, i" x6 n! G& JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. f( x( g! ^4 i4 B7 z** Set the serializers, Currently only one serializer is set as* {9 I& `6 @+ b& a( ` R5 u
** transmitter and one serializer as receiver.
8 t) j5 W B' ?3 U4 j*/6 [7 j/ A) L# K% e& i: i" T$ h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( `# O* l) S* A$ e8 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 a, u# }# `" M- W: l: f, f
** Configure the McASP pins
" [ v# M& v: {7 C& v+ ^6 a) g+ F** Input - Frame Sync, Clock and Serializer Rx
! J6 ~& y) |' G) F7 @! q' p* a** Output - Serializer Tx is connected to the input of the codec
& @2 |% b) I8 N* P*/9 i0 L; c2 ^0 x2 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ ~3 i% T3 V% y! s% d+ l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); K$ R5 T4 a) ~# u. G* T/ p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 K5 `: q% `& g+ r" k| MCASP_PIN_ACLKX
. ~( q3 Z9 E0 B' S| MCASP_PIN_AHCLKX" H: Z8 a E5 ?" C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# ]3 ~( i' \3 i5 C6 BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' T4 M* s- e( {/ k& g
| MCASP_TX_CLKFAIL ! j; _5 U( b. O0 d
| MCASP_TX_SYNCERROR) Q; A# Y! D |" O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 ^& F, Q# E! ?2 h, ]| MCASP_RX_CLKFAIL
3 ]0 w( H7 i5 m$ M$ k- a| MCASP_RX_SYNCERROR h7 e$ j9 G, @3 {# b
| MCASP_RX_OVERRUN);# c6 S# |, s8 n0 n- v
} static void I2SDataTxRxActivate(void)1 S, m( K$ p" ^$ B7 d6 H; [0 v' Q
{: z) K5 h5 Z3 ]3 l5 C* J
/* Start the clocks */2 D! U4 p; u) O4 L0 ~4 \6 }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, Z9 ?9 A, o+ I' v4 K! n- _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, } @; @' _) g" X5 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 W+ T# _$ B w" T, MEDMA3_TRIG_MODE_EVENT);
$ v4 }9 U- r/ M+ V: d4 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' P, v v$ u; A# i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) u0 X# ^1 e, j d: p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 w+ t* Q' z ~- U1 ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 P. E7 y7 z% vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 \" W0 g9 R& u+ W3 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; u4 M, q8 v! z$ v5 g `% L1 F( cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 @2 \+ _, i' ~/ X} , H8 G* M* {' `, Y( U" o4 h0 G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 [8 o, j& R% s2 e5 E" w
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