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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' I6 ~' t% G3 `input mcasp_ahclkx,7 f5 E6 d. C4 b; n: ?: Q4 C# r
input mcasp_aclkx,
% S: R- D8 z0 y$ _input axr0,8 C! d9 J, Z2 S* l9 t. m
7 F. L p: S+ M1 Q
output mcasp_afsr,
# }6 }! h$ r+ t4 N8 o+ `% v, Goutput mcasp_ahclkr,
% g' Y0 P7 l0 U3 Koutput mcasp_aclkr,
+ n* X7 i& V+ d$ S/ P4 ]: eoutput axr1,
. Y3 X; d8 L# t+ A+ d Q assign mcasp_afsr = mcasp_afsx;0 W+ k/ [2 ^, G \" i
assign mcasp_aclkr = mcasp_aclkx;
) x8 o; g) A" S6 Uassign mcasp_ahclkr = mcasp_ahclkx;2 z; C9 \* X& U( [
assign axr1 = axr0; ( c; [+ O# f8 a) A1 o
]5 l) n3 l- f2 w6 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; a4 \% ^5 s( tstatic void McASPI2SConfigure(void)
9 G3 Z/ N' j2 y3 z{) C) W, \, d- ]; Z, a Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 Q5 y* y3 I/ r( S) ]7 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& q: k3 l& s: V. }+ A1 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ f( \# A: i1 U' t* M; g/ N# K1 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ k( L1 b! O& F' u6 b0 _3 _4 x- e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 K- e) m( u7 X$ n0 e; R
MCASP_RX_MODE_DMA);9 U5 `& j; g. @" D& A+ J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- S) H6 |+ O6 a& yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' g7 e+ g. t3 A+ w" U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 w! I* W& j, v* U5 g+ j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) {' ]/ X- }$ P- o- X/ P4 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! y0 z2 C) R) C9 ?3 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: x3 f1 _3 {, u+ Y# n+ V0 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ R! ?" Y+ k, C& L: N# @0 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& p& {. }7 y! H. j d! `+ {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 g4 |+ q9 _- B# ^$ H0x00, 0xFF); /* configure the clock for transmitter */
% T& p5 l& H5 W, jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) Z0 X L8 L' Z$ j9 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 _! g' c" {4 |: W I& wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 w _1 H3 v H; h, a/ L0 \0x00, 0xFF);
3 U/ u- o! D1 Y
* M8 J* A$ @8 j/* Enable synchronization of RX and TX sections */
, o3 ]0 ^5 O/ |; f, eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! z7 A2 |$ R. g( |! ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 L3 b$ A! w8 v. nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& Y" v: G6 `/ w1 [7 u- m; z& O** Set the serializers, Currently only one serializer is set as
' s1 [! A3 O; u0 M** transmitter and one serializer as receiver., h0 }: E, ?, x* p/ e, @
*/
( h8 B. s" k9 j4 \" gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: c: o6 q& j$ h- @) w) Z) iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& D- f7 c4 t3 z7 U* z6 z4 _( l4 O
** Configure the McASP pins . R" t H |1 B+ Z9 q
** Input - Frame Sync, Clock and Serializer Rx
( a8 U* U: H: ^* g. o5 W- J** Output - Serializer Tx is connected to the input of the codec
% t1 E* D) z3 B9 a*/
7 [$ G5 x2 S, C3 E% u4 z C! dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: M/ F' p6 H( @! | G J6 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% g/ \6 W. _+ W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 f' q. | I; v5 i1 D7 N| MCASP_PIN_ACLKX
% C! c; {8 x h| MCASP_PIN_AHCLKX! m' G7 f% g, Q- C; m" \7 l2 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. q$ [! B6 M8 g- `5 L" W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, b4 p" Y$ U& A3 L| MCASP_TX_CLKFAIL ; K8 ]6 p/ g' J
| MCASP_TX_SYNCERROR, V' q* o, l1 q8 E4 e9 ?0 ?* X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' `0 `: @9 \# p; ?2 |, j| MCASP_RX_CLKFAIL, Q0 d* Z0 a% H, f. a1 I6 k* p
| MCASP_RX_SYNCERROR
`; J2 E2 M1 @4 r- E+ Y( g| MCASP_RX_OVERRUN);
3 d6 x- I, U# M9 `$ |} static void I2SDataTxRxActivate(void)
( w9 [: M* ^( E+ S{9 }1 o7 t) m* p3 J; [6 y& Z2 F
/* Start the clocks */# l, S) ]: y8 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ X7 C) V; k$ _; {9 v; vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 G: J8 H7 l: v- [. T1 A7 r3 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
t, ]& r& `* S3 X8 N/ M$ w% o. rEDMA3_TRIG_MODE_EVENT);, O3 s! T7 p) s: i9 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 q' x# D* K, r% s. E7 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ e" z* F. F! |8 s l5 G1 U1 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; ~' f J( t1 S- }" |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& `0 @/ ]7 Y) b. L5 b8 r8 c6 a' ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. {$ Y3 p% I; f; \+ L. s1 f0 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! d: Z: e, J8 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' q/ F2 ]3 V( H r Q) A
} a5 y1 v/ A1 R! Y* `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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