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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' z. j. `" V# ]2 R" h! n6 s
input mcasp_ahclkx,
# r7 u6 M" m- W6 g& Y8 Q Vinput mcasp_aclkx,
2 ]" A% V" T+ c' zinput axr0,' T7 ~0 B+ o( F; Z
" H' L$ [ [2 Q( {
output mcasp_afsr,: ?3 Y" y Z8 `8 Z8 Y' F) i
output mcasp_ahclkr,9 X4 x( [8 Q1 p0 l3 [
output mcasp_aclkr,8 G" I/ L5 R e' o
output axr1,
: W# N3 b. L/ ^. b* ~ assign mcasp_afsr = mcasp_afsx;* K# l" p; |% v5 z Y9 |" A
assign mcasp_aclkr = mcasp_aclkx;: S# A# [* z1 Z* \
assign mcasp_ahclkr = mcasp_ahclkx;
% F \' |5 W6 E$ U& Eassign axr1 = axr0; - c/ H0 T- y2 L, o- h+ ~
# v& E% X9 R" _0 R! S: O% E; l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 g F) d3 n O. c4 u
static void McASPI2SConfigure(void)
3 \+ \/ ~* T3 z* J{
1 O, z; O5 _7 U3 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' B# N/ S) m$ N: }( K% M5 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' P; G1 T6 Z. C, \+ V3 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
g; R/ A0 s" n ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! O' F q: r% t2 v3 j" ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 f" @6 }4 f; g/ Z; LMCASP_RX_MODE_DMA);
0 R2 Z& M5 e2 d+ mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! G7 E0 A8 F1 h2 F, N2 M# WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 g# _# T6 v; p1 Y2 b D! QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# C, I5 M" I+ E p0 U; s6 o) OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; ]% v/ J# |" l% \ U5 ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 w; E: C: i$ hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ }) y z0 p# m& Z" {* v7 kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- F4 D' k- D2 G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! v* ^' O* v* S6 o' W$ jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 m; l' P4 B5 c0 b; w) W0x00, 0xFF); /* configure the clock for transmitter */0 ]: }: b8 o+ j6 W% H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 V3 v+ y' s' |! y7 I/ lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 D$ |% T5 v: R3 X$ I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. q; }% ]6 A8 r j8 S3 a5 T
0x00, 0xFF);
. y. g# j$ ?1 I z; r& _/ s9 m( l- P1 c
/* Enable synchronization of RX and TX sections */
% G$ J1 A" w% T4 s. @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! V3 }! t$ W9 n% r6 g4 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 y5 v4 G! ?" OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 T2 f# q l- |9 e; N, r/ \5 X, Z** Set the serializers, Currently only one serializer is set as
5 G& O6 [# ]+ {6 R' Z* f2 Q** transmitter and one serializer as receiver.
' x8 l! c: m y z0 |6 S*/' D/ K% d5 i1 p0 }* y. U4 P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ C) X! N3 q6 W# E2 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' Y$ r4 k4 [% k, R. H** Configure the McASP pins / k; }7 t6 K+ S) k, N* q1 e
** Input - Frame Sync, Clock and Serializer Rx
' X9 Z' c C3 [5 r6 m, ?** Output - Serializer Tx is connected to the input of the codec
9 R/ I( F) I% S" K*/% ~8 o m H% A6 _- \4 a% S, G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. j* \5 U- `- F9 w/ t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 B1 x4 m- h* C5 P* L9 M" D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 X6 w+ y6 } p w" R; _# e$ f| MCASP_PIN_ACLKX
' k: q1 d/ A; y/ C+ n* k| MCASP_PIN_AHCLKX
, r- t, ~5 X! \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ E3 _0 F( t* O" GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; p ^( Z. J& t6 m9 r! |. u
| MCASP_TX_CLKFAIL : l9 o/ b' l& V; J$ f
| MCASP_TX_SYNCERROR
0 M" a5 M) B- ^* y4 M' {8 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 C: b' A' E' g/ K
| MCASP_RX_CLKFAIL* B$ {0 H2 [7 z. ~
| MCASP_RX_SYNCERROR
" _ w* Q' H5 a( z: e5 S| MCASP_RX_OVERRUN);
- G, t5 }0 \; K6 x3 G: z9 q} static void I2SDataTxRxActivate(void)0 ?) o8 g2 `, g4 ^
{
' `% G+ X. x* y4 i/* Start the clocks */- _ N) \1 E& r x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. h5 m/ s" j7 i3 m, MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: k9 Y# w, P& i3 i. x# \* U0 ^) j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: t6 I8 R; f) [! G8 zEDMA3_TRIG_MODE_EVENT);) h$ S0 d1 {# }. r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! T5 {4 C0 Q5 Z' {* f. C: x( h8 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& t4 }. f1 G+ q( f& wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# z2 O m9 c/ H# I& ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" e E4 ?9 F8 R2 j+ V' m, \, ^8 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% m( Z: R# O" u d" ^# I4 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- h0 B# g' m: u5 Z0 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 p6 X5 }8 Y! z) j S! L
} # M, e1 W5 B5 f7 l% P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : Z; t) l6 o0 s# x- Z
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