我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 T' x& J% E& f* ^: z% A& r
input mcasp_ahclkx,3 i# V; R, r' A
input mcasp_aclkx,! i. _% C) ~, r
input axr0,4 D" ] s$ o! D2 ]
& O3 p% {+ |' n( u2 }) a6 T" ?output mcasp_afsr,5 i5 C4 _0 G: G1 e* X/ [& x
output mcasp_ahclkr," c0 c, ^ z- N ~3 ~
output mcasp_aclkr,
7 [, Y( W/ p' c' x) l6 youtput axr1,) N/ @+ F" S; L/ c2 f
assign mcasp_afsr = mcasp_afsx;& J2 f% \1 b! [- ~0 U2 w
assign mcasp_aclkr = mcasp_aclkx;
5 [" u! G1 ]1 _$ Y6 Gassign mcasp_ahclkr = mcasp_ahclkx;" |+ a4 T2 ~+ U( U
assign axr1 = axr0;
7 A& i6 ^! I% E
' E) {9 ?7 ~$ K( F8 f+ Z/ X" X" K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ ]: ]! A& L* v: Rstatic void McASPI2SConfigure(void)
' u! f) [ B% D5 W4 l* x{
0 x7 [3 q2 M4 g+ l9 I0 c1 }McASPRxReset(SOC_MCASP_0_CTRL_REGS);( o, O, k" N0 O- R" I6 \ R. l( D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( d2 `- G# E$ M5 P/ Y# ~* q% ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 Q ]3 S0 E0 C- I4 h2 V+ [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ S3 g0 Q! E7 z# R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ O O' l& i3 ^MCASP_RX_MODE_DMA);+ D. |) T' I/ }1 I. K- T' W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) {$ r5 G& Y8 m* bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" u, k* Q7 I4 ^( ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: F& x4 t6 k$ N4 ]! b4 G/ N- wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ G1 K. M5 g* j- x9 W$ ?' e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 T2 r a" p' B3 N) c4 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 ]( O! U8 O q5 z/ pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 ~6 [* ^7 [4 r9 o( s$ RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 k; S2 n9 @* E6 j9 }+ ^; `# m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: s# C) _$ d8 P ^" @2 y
0x00, 0xFF); /* configure the clock for transmitter */
, I' I5 m) ^; r' k% GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 S( _2 v4 J# Z! p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 n9 f% {2 z; C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," h1 _- A1 v) Z7 X( X1 S
0x00, 0xFF);
0 j P4 S1 x) H: @1 O1 M! F( v
0 P& {0 t0 d3 C& m( _% c/* Enable synchronization of RX and TX sections */ ( V4 ^- ?( L" e8 ]2 e" \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ a6 t6 u# c2 t* C6 nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ I [& l" P4 z; ?. j7 ^6 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 k4 F, v' a0 @" g& s
** Set the serializers, Currently only one serializer is set as
2 b- K- w/ w& |: J0 K1 Q+ n** transmitter and one serializer as receiver.
% s6 ]) B# ^ L7 Q9 F3 N* \*/: @0 |6 D" @4 [: D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 g, A( I" g5 u- }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# j% t$ _# V$ a9 I
** Configure the McASP pins
2 k) B' L" Q" `+ d** Input - Frame Sync, Clock and Serializer Rx$ Z9 J+ d/ o8 n# w0 g$ A, v
** Output - Serializer Tx is connected to the input of the codec , l" m- L: S. ^! |4 |3 d5 n4 R
*/
1 _/ m" A9 d! F* V8 _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* Y" v: S' D' [6 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 q+ ?$ w9 ~) \( F, `: I! }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) w, g* E9 W. j4 }& `. y| MCASP_PIN_ACLKX! u; \$ y" G: C4 i
| MCASP_PIN_AHCLKX+ Q- d4 N( K7 Q0 }3 W7 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' P; Q, F/ q- `, B$ Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 @8 A8 n! i" O0 J& T, K: C4 Q
| MCASP_TX_CLKFAIL ! V' }# o& X" f3 A; X$ W
| MCASP_TX_SYNCERROR7 l* r, g; J2 L4 W7 g: u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / P' l9 T5 m+ f/ }$ O/ k# H7 R+ d5 B7 q
| MCASP_RX_CLKFAIL/ l) o! Y( u7 n' w" ?: r
| MCASP_RX_SYNCERROR
# C8 @8 w5 G) `& [# d d" q5 || MCASP_RX_OVERRUN);; X- d' a+ d$ j2 d; Z( H2 U+ ?+ g! G
} static void I2SDataTxRxActivate(void)
4 _* W V$ }, o" L p1 ]{! s- J4 |: x* }1 J- k7 B0 _; V
/* Start the clocks */
' R+ k6 R7 c( s- C; G4 |& K( v' I8 YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( B8 U- { @# P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 O: @4 u; ?& d3 d( uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* a9 ~, X; Z* Z+ q! Q0 _
EDMA3_TRIG_MODE_EVENT);" s S& w ?5 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; ?7 ]2 k. [! W: pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# m7 }# \* f3 F4 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( d) B- i' |3 _0 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) h) X/ p3 K% k# W( ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, e W) A6 d9 C+ }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) P t& c. x) l' s8 d/ k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 a* Q7 W. S1 n' H
} ! K6 o9 ]1 V. Y* ?. f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. a: B3 |# A/ w8 J |