MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
, s( r# y2 c+ E2 }3 X) qinput mcasp_aclkx,
+ Y2 U) s4 b' P# Hinput axr0,
& m' o, p. s5 J1 v" n
1 n1 j5 U3 ^; Ioutput mcasp_afsr,
6 ]0 e, _" W! noutput mcasp_ahclkr,
; P; u% g' R) S% ^" y) o3 z- @output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
/ G; Y$ t  I6 fassign axr1 = axr0;

3 q- O$ K7 y" ]5 q, K
0 K: ]( V( M& t) \4 w4 j. W/ F

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

" j1 E5 M" k' U; O  c

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 c: |* E4 V5 K* DMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
% u  u2 {0 h/ d+ B# c) PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 }7 b: U9 Q$ o3 K8 `, }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
1 M) [/ E$ p8 E% KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
! i0 r2 x* l1 J+ P# q) D3 I2 V1 N2 D7 C/ tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% N$ M4 _1 s; N! `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ i* U+ p) z- A* `: |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# c4 Z2 ]7 N1 D: S0 `0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% t! v) |$ j5 Z9 W, c0 x- B: R. K' |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& U- D4 [5 Q3 a8 w, F8 O/ rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
/ j! m& X+ V& W* K$ }1 g7 `$ s
/* Enable synchronization of RX and TX sections */
* R6 N" j, n; }! [: |1 EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
  R6 J( z* K: X% W$ O& o3 _/ kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) p9 g0 J6 _! J# h; s- f6 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
! s2 C; G4 W# r3 `  }& J0 }*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
% E5 V! W' F+ E' Y' V- X** Input - Frame Sync, Clock and Serializer Rx
! }2 y* E0 c: Z** Output - Serializer Tx is connected to the input of the codec
& ~" v# s+ Y# S6 ?*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
& {4 Q7 Q3 Z2 f  ^' P# G, _' P4 [| MCASP_PIN_AHCLKX
6 ~+ M1 j. P0 W; H5 u$ h$ B| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
! a- M/ b) O) A! dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
  ]) V+ x! b- S4 U% ~! z* V| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
' [' ~5 Z6 O8 {% Z, g: Q| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/ c2 R- M2 L/ V/* Start the clocks */
0 {: d# o: X; V- B8 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ ]! b; S, I, z/ X7 XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
, l4 \  @, `; N3 L+ DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# i, a1 k1 \0 ~1 N4 Z% I; qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
* l5 M1 M" @9 ^8 v6 \. bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 h6 P" |* L9 {/ L% z3 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
; q% `& R2 y6 q, X9 t% O4 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

  ]4 @* Q  L$ X: e  f: v8 b