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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. W/ r' R) v( x: g3 g: ~. z1 ]
input mcasp_ahclkx,: I: s9 }$ ^+ V! [ k
input mcasp_aclkx,
5 m, r* \# X; v- t+ jinput axr0,
. {' I1 K% {) `$ O8 L. a; x' F/ ~; ^
output mcasp_afsr,
1 O- |6 v3 W9 }- U4 F8 z7 H ?3 ~output mcasp_ahclkr,: ^/ z" s+ q+ \8 M; V
output mcasp_aclkr,/ U2 g3 r) ~: b ^
output axr1,
1 b, j! N: M( e. t. f/ ^3 ~/ W" U assign mcasp_afsr = mcasp_afsx;
- B, B- F3 {* q# aassign mcasp_aclkr = mcasp_aclkx;
. U1 R9 i8 c( ^- r& `. passign mcasp_ahclkr = mcasp_ahclkx;
* h/ n6 R8 H: }% U: l' j! Massign axr1 = axr0;
$ q% O3 m. K8 `" j6 o3 \" B0 B- X7 j. P/ c! c3 A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# u+ C) I) M( c! U2 ]8 N. Q& astatic void McASPI2SConfigure(void)
+ J" {* z- k* o% ~( C S4 q{
7 D% i7 C; Q8 V# R; _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* k8 I- \8 O" ], N( \. F* ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// ^. b% }# D$ M2 f* n* Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 u! }( f2 W6 ~8 d0 _" z: L9 C1 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 Q4 y5 z5 b# B4 [; S3 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 E* X, H, l" {( ]; d% A% N7 pMCASP_RX_MODE_DMA);
# | b3 q! s% V$ @0 ~- ?& u- ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! Y4 T0 S5 O7 x0 KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 Z# Y1 ~5 z' MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + `1 \# P$ B4 J5 J2 f: s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- \: N3 Q1 n' p# W, i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 o! d m5 w# p5 Y5 s) EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) O0 y2 q/ i) c$ X8 k8 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 l5 o4 l3 H6 _0 w' C& c, sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " H) N% r5 n% \4 J3 q) ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! z, x1 c2 _) \' z y1 |3 z
0x00, 0xFF); /* configure the clock for transmitter */
6 W( t0 K; m0 v" [! ]8 { s9 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 P0 O5 i* \* {! n/ bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( q- r2 C, I# y3 D* d- {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ a1 t+ g) S. f) B9 e
0x00, 0xFF);8 D) f. Y- r- w/ z( Z' b$ H- P" o
6 o1 v1 ^ w3 T& }, X/* Enable synchronization of RX and TX sections */
) ~4 D) ]& G. r9 P4 J; jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 [+ R- T4 y" C. s4 }' Z9 R$ i. y/ ?1 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ k$ x& i, y: K( Y' {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% w! V/ B8 H. ?; g1 y6 K
** Set the serializers, Currently only one serializer is set as
+ E8 q. i4 f- j0 P1 o** transmitter and one serializer as receiver.+ ^9 `$ Q% s- I2 y) p
*/! R+ M& W% K- a" \. Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ A4 T3 Q- B7 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& }: k) d F! ?( F/ p* w1 N
** Configure the McASP pins 3 N8 e8 h. S4 P3 {$ H1 [+ F
** Input - Frame Sync, Clock and Serializer Rx
# M& ~: v; Q, A" B** Output - Serializer Tx is connected to the input of the codec % ?4 U% U4 P O
*/' l6 e3 z; H, U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- o4 x4 W" C3 n5 Z& C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 |# h: a3 u- x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ x; t" i( w& R4 Z6 t7 n/ Z| MCASP_PIN_ACLKX* n; |0 k3 f5 u; R; k
| MCASP_PIN_AHCLKX5 i, U( r4 r) m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ t5 W' }( d' G$ n4 \( O C+ LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 f; m2 s& U* ~& N/ ~| MCASP_TX_CLKFAIL 2 T3 M1 s, r1 v; [! P
| MCASP_TX_SYNCERROR
" a: Z, X; \" L/ E! a5 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. d0 V: q* E; |9 i* m) f$ p, j| MCASP_RX_CLKFAIL
9 J$ x2 f- S5 Z8 V# ^| MCASP_RX_SYNCERROR
8 s. R* W9 Y! m! R6 g6 X| MCASP_RX_OVERRUN);
: d9 _6 x: Q0 _9 B& g} static void I2SDataTxRxActivate(void)
/ i2 @2 ^ L: E b{- K8 v) L: h) A; e1 t# n
/* Start the clocks */
8 ], |! k" P+ P2 a, h+ WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, H3 z; o' }! f0 O- M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. m/ O: O( u1 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 S/ [. _, Z; G% H: \
EDMA3_TRIG_MODE_EVENT);0 N4 w7 l5 T \) M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" G+ [- V: n8 A3 X% q3 AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: x, m- C! `+ ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% n& p4 W' `& O/ h/ P1 M3 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ ~/ O% ?' ~; O; S& W: K2 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. E7 m/ W' h4 r% E' u' m, z/ x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: z4 }5 i, W C1 J) wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" a" ]0 R2 F P}
+ o0 j! F- f. C2 i4 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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