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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: {- N3 ?! s) }4 e S0 Qinput mcasp_ahclkx,
$ F# O+ W0 [: T, binput mcasp_aclkx,
$ y; }, @ }. n( [# t/ w/ j# uinput axr0,8 x* W( o" a6 Z) s/ D
) U1 s9 S- L; g z
output mcasp_afsr,
# L4 t$ k. }* r5 w3 q5 t8 w( noutput mcasp_ahclkr,$ L* I& Y1 L; Y' x# N u
output mcasp_aclkr,% R. R, K+ X. g! ]1 d; U
output axr1,
% k9 E( w+ C5 L. t4 e0 \ assign mcasp_afsr = mcasp_afsx;
+ R- i; } R# z4 ]. lassign mcasp_aclkr = mcasp_aclkx;9 I; E: ?, L0 v" _
assign mcasp_ahclkr = mcasp_ahclkx;
6 E& X* }6 b/ }+ q( [$ e7 r' V1 `assign axr1 = axr0; 7 X/ Z( D# U( Y" ]2 X+ i$ c9 z
! Z* V% X; w8 `2 m) k* F, L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ K1 M+ q' {& {5 g# o* Cstatic void McASPI2SConfigure(void)
m/ r; t' B! b! F3 j& Z; S{
$ Q0 |4 e4 m) h$ Z( k9 _, u( _; k2 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ Z6 e: Y8 C8 ]2 x j9 a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( K0 ~1 p* n5 R/ |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); {# D! ^6 L+ U0 R, x3 |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: `' n. L( i) v5 A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; v& j: V7 ]* O& k1 ?" w0 iMCASP_RX_MODE_DMA);* K9 s/ }' m, G' X7 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 S' H4 x7 Z, B: U! AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 A: u3 t* J8 {8 N' R" eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 b' h) q, A& `& WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
I1 E) W" p1 p8 ?8 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 D, s0 `4 W r. Z$ z% v" X! NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 B$ u( ^: j* e- \ C# QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ C: p; D( b7 F* ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) c0 n4 y% T d+ XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ Q0 r. D" P" x& L& g0x00, 0xFF); /* configure the clock for transmitter */( g% Q5 \ \9 q) k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' n* n, f. B* K5 {) d! g6 X2 p3 x8 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; Z4 U9 Q; y$ O6 y8 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 b* |) a8 Q/ v* M$ X. @
0x00, 0xFF);, X" L+ \! N' g% [, V# u
, H, v$ Y- [% ]; B1 D/* Enable synchronization of RX and TX sections */
! B' @# Y, @3 z$ h9 K- ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 N5 Z2 v: C3 R1 w8 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* J, H8 l" L! f' aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 V5 F- y8 F; L" F2 K** Set the serializers, Currently only one serializer is set as* C( Q6 P- H7 C
** transmitter and one serializer as receiver.. |8 v: x* W% w5 ~1 a8 L
*/
2 [: g* `4 K, \6 r9 ~0 }+ X# |( d# xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. c% H% p- j2 Q: i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 S8 u! H( P% }4 V** Configure the McASP pins
& ~9 k2 f2 s \/ X9 f" H0 k# S** Input - Frame Sync, Clock and Serializer Rx$ ]: B: W. `- L# L
** Output - Serializer Tx is connected to the input of the codec + ~1 _& L) b" W" X
*/* E9 S/ `( G% ~2 c9 e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 a g! Y( c l \! _5 b& ^% e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" `8 Q# k1 R* w9 B$ J0 }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 z; k, M$ Q) O+ C& n3 t" p1 G| MCASP_PIN_ACLKX5 P) A6 I9 ~; ]7 B. X$ n
| MCASP_PIN_AHCLKX
( ^, \" n" s! r1 s( r! @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. Z0 E% Y% g. I0 ?) D6 n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( G) M$ [. [( D3 H
| MCASP_TX_CLKFAIL ; d% V% O9 K# O+ h/ W
| MCASP_TX_SYNCERROR4 M) j0 Z9 R7 }( q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- |. W y/ r# G6 o% |& v9 v+ \| MCASP_RX_CLKFAIL: _3 E3 \) d5 s/ L
| MCASP_RX_SYNCERROR
3 A8 v$ i' L6 S+ J# U| MCASP_RX_OVERRUN);
& J1 T8 }6 S9 F1 z+ D} static void I2SDataTxRxActivate(void)
+ Y, S9 u- H) ?3 o! t{! A2 i( `% }) C: y' s$ k
/* Start the clocks */! i! O2 ~! K, }6 ]6 n; h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ L! D* s- Z; w. f4 |5 Y T9 o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, B* T2 j, P7 ^* C+ j+ ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* m: k7 I0 ]' B. e$ H6 B# |1 s$ g
EDMA3_TRIG_MODE_EVENT); x) c4 |) R Z" c" e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # [1 Q2 P5 k* `) V* N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# d; t3 m6 ~# Y ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( |) o0 H; }9 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 n4 T; j( f, a& H& [3 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( e7 b; k9 A3 H/ L; B' oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" N; c8 y% w v/ r; ?' @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- O! X9 o# a$ W! a, W}
, j, ?/ v8 u4 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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