MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
$ O5 k+ x1 F  X# J; ^2 e' W& ^input mcasp_ahclkx,
# R2 ]) i! x1 b- n9 q) @0 Ainput mcasp_aclkx,
& p# q! A) _' t4 {; B# Binput axr0,
1 k# I! g* U$ a2 m0 e; t6 W
$ K4 d/ j7 S/ k, q) P: Qoutput mcasp_afsr,
output mcasp_ahclkr,
/ y+ ?# O* D+ a/ O0 o0 P! H" Woutput mcasp_aclkr,
1 z- T9 ^8 v# Foutput axr1,
3 }% }) X" e& A$ j

assign mcasp_afsr = mcasp_afsx;
- Z- l7 k4 N% k1 n2 K- x6 u  \assign mcasp_aclkr = mcasp_aclkx;
! H5 V: M. y, J9 ]9 [9 n' V/ sassign mcasp_ahclkr = mcasp_ahclkx;
  ^8 b4 h% H# ^2 ^4 }assign axr1 = axr0;

5 T* s; Q; |: m) r* F, Y

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
0 T8 k8 _' q9 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
; x$ V+ T4 C! ]6 W. H$ SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 I3 C0 o. ?' _" U: q" FMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, r8 \4 q. e5 O0 `. [7 K9 R5 }MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 b2 y" ^+ f: E- k, }; TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 ?3 @% h: p! m! _7 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
9 F3 z) |+ i5 `( L- g9 x5 K) _& GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( e( n! W  F  L' C! V! r: QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 z, w, A! |9 R; U4 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 d5 f. M4 c/ ]) J+ _, H7 P# jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 ^! i$ u2 ~& `* j! I0x00, 0xFF);
8 P# D% i" y+ b9 G( Q
3 K) J$ J& m# T) ~/* Enable synchronization of RX and TX sections */
; }( X: O: g9 m9 ~! y! lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 j# M2 h9 j9 ?* jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
$ ^. ^& y3 T( ]& b# Q$ Z2 [** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
, w, h! B- x2 K1 c*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
: B. w; O0 f# [** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
8 X+ Z6 J, [7 M/ H** Output - Serializer Tx is connected to the input of the codec
3 C! k( N9 h" P! q+ j*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ y* {; ?% d! p: k' jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ Q: M& t* S* y' d| MCASP_PIN_ACLKX
5 p0 G; b" c- ]| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; w% S) d3 R1 G/ `| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
/ n2 Y# Q/ |" W3 y& q- N| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
1 }- J9 T5 g: y+ B2 z{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
8 u8 U: H( C, @. i8 I  lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; c7 F! a7 H* }' g. X5 YEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 e6 O$ n6 y. N( V, eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Z2 I. M8 W% @; p$ l4 r2 b/ `- eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 c7 E7 E  Q2 W! tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) o  U, ~5 F; I" ^}

+ X& V1 O1 _4 S3 O

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

# \0 u. S6 P6 ~  j( j9 F  }3 ?$ |