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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# t/ z3 R: U) N; ]$ Q% \input mcasp_ahclkx,
* T$ M) s# D+ oinput mcasp_aclkx,9 Z: t2 E) e5 d9 d+ M
input axr0,
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output mcasp_afsr,) |6 _: G! Y2 x" ]
output mcasp_ahclkr,5 X& k8 t P1 l: | N" y1 v
output mcasp_aclkr,# ?" w0 J, |1 I" S; u. m/ U
output axr1, H1 }" J9 S4 I5 P
assign mcasp_afsr = mcasp_afsx;* l4 z! d' z! c+ f
assign mcasp_aclkr = mcasp_aclkx;: w" T9 `8 u% m. y
assign mcasp_ahclkr = mcasp_ahclkx;
: C5 J+ F% w# r# b/ a& rassign axr1 = axr0;
6 G6 u4 g1 ~7 b
8 m, u0 N7 |% l0 _) m2 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 _6 d! B3 X+ S6 ^& }: o5 ~4 m" s& O! D
static void McASPI2SConfigure(void)
) K+ N6 _0 `% \8 f2 S F8 u{
. R: x1 G. `. p% HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ [# X5 T& D) B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ {5 F @) ]6 H! h, qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ \5 H9 p' m6 e0 j+ AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 H1 @, A5 Z- Q- O1 F0 {' |; k' N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% V/ U% _% e' w0 v* _MCASP_RX_MODE_DMA);( i5 _5 G+ |1 w! C0 a0 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ v* [* D3 i* D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) Q! D/ D* R. Q% N9 U( @ y; }5 L- R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; a( E, l v7 l* D9 X: z1 m& f; {% z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 }8 [8 |: u7 h4 Z! N2 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * ?1 W. K C# {8 U+ A& m% |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- D3 q3 }# Q/ `( @9 T: Q6 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: L) e: _2 S, m9 q0 ?. h0 w& ^7 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* c/ s z [3 n* ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ _- n V6 r6 D; z0x00, 0xFF); /* configure the clock for transmitter */
0 m) F: `% _/ d* I) _, U, [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! o7 A9 G& L) P+ P4 a" I* U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % b; q8 M% q. R0 z+ ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 {! l& G9 U" ]
0x00, 0xFF);
5 a1 W3 q$ X5 ~% `& P9 Q" L* Q' w+ I2 i- J% x+ |8 l D2 W( J
/* Enable synchronization of RX and TX sections */ 9 a) ~9 h; z' _0 } u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; G0 V3 I( h* }. }1 U# dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 A6 g9 \0 m: H2 b& p) U4 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 J8 b" [8 u* P( a1 r5 ^/ D** Set the serializers, Currently only one serializer is set as
8 k9 ?8 h; O/ }) b7 L** transmitter and one serializer as receiver.
6 A1 F" X- p" O6 Z/ ]*/
2 l5 Z* w$ X$ H0 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ ?) o+ U* K3 p# w3 i/ [) V" eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 z: n) A! \8 j3 m) u2 R; F8 ~** Configure the McASP pins
% o8 j$ X# x. D2 Q/ m** Input - Frame Sync, Clock and Serializer Rx
2 H5 S) Z( V0 g% n** Output - Serializer Tx is connected to the input of the codec
& z- B) E+ U9 h T v*/- i2 C5 ^' H3 G4 w0 e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' ?# h# X8 _6 }$ x2 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# {, O& H, {2 a6 Y) e e# I7 `' }5 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ h- I- g" A# j( [8 F4 ]. e9 n
| MCASP_PIN_ACLKX
+ W$ W* h8 j) B* Y% U, q) ~| MCASP_PIN_AHCLKX: }, a' D3 }5 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% t: M' P$ y; N# w" k5 V. f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, N2 U" i# ~1 l| MCASP_TX_CLKFAIL
) j9 z Z" O6 e2 j9 || MCASP_TX_SYNCERROR2 I4 I7 L9 V5 |4 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 j5 W+ N1 d1 I5 r. r v| MCASP_RX_CLKFAIL2 P# E/ X3 j/ n' ~" x( T
| MCASP_RX_SYNCERROR , `7 W" ` [5 a- }
| MCASP_RX_OVERRUN);
% P! j0 \. _9 Y* G! s$ J% \} static void I2SDataTxRxActivate(void)
, E' v, M$ O% I' L, Z G, r{
0 v$ E5 w7 l2 B; W4 w/* Start the clocks */4 q* e) J# l8 q1 Z" Z. F% {* q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. v0 v- s! V; y/ [7 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 B* {9 b. `: i- _, ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. |8 L. ]' ~# O9 O, k- tEDMA3_TRIG_MODE_EVENT);0 e( d7 s7 m% }) {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 G# } r5 W* N* g3 Q8 m/ s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 T' h4 k$ |7 o5 ^& o3 W7 ?, C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; ?- e5 S2 m& k0 Z( ^, j7 p4 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ l% {* h- k: X7 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# W1 E2 } m" z' `- K8 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 s0 e$ |$ s' w5 Q* |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% L3 w3 V, Q6 N" ]9 p
} ) M' @4 A m6 U) h, S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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