我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 _" w1 ]0 v2 R# o5 Iinput mcasp_ahclkx,
* h; c* U' {+ \: winput mcasp_aclkx,
; l; k9 X4 |6 y4 [3 v5 V, [7 u5 qinput axr0,
7 M) X7 m2 y; ?+ o: P, C7 N2 L, B9 i6 S8 N
output mcasp_afsr,6 n3 d3 l* K) \, z6 G/ q6 a; Z
output mcasp_ahclkr," V+ Y+ f6 g1 D0 u/ J+ E8 z, A1 _' Z
output mcasp_aclkr,
+ c0 ~! m5 H8 i5 _$ L: o9 x; [output axr1,
- r% A& p4 {7 H# L) [ assign mcasp_afsr = mcasp_afsx;
' F. M; p- Z/ F8 Jassign mcasp_aclkr = mcasp_aclkx;
- F3 G2 D7 C Z" |& ]# L: zassign mcasp_ahclkr = mcasp_ahclkx;! A+ W$ F" ^5 R- g y" Z
assign axr1 = axr0;
. E8 O) p1 @0 c' t& V4 Z7 G8 i. i$ K: m$ S. ]- L2 ?% e. P" s& V0 O2 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' r' q% \7 Q, P$ W
static void McASPI2SConfigure(void)
6 j' @# Q$ q, | ~1 Z6 T3 v0 M6 x1 n{
2 S* D5 }( \' [6 p5 k0 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 ?6 t( E* T4 a o( N- E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 y N0 k$ f g+ A/ f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ ?8 [$ {7 l/ N. w- v4 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 ?9 d! h3 s# |$ n- f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* D5 f3 f; N' l2 E, c* g& E6 _, N
MCASP_RX_MODE_DMA);
' ?/ F6 W; j$ A0 F, O; O7 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Z4 d6 k9 L( ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 q$ I E& v& r% x* b( eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 \" ?8 t0 S; R6 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( S3 o- u$ n* N2 G" j# pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % p' r: m" ~" s1 b( U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 G) e' m n! t, ?$ lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) {$ I. ]# ~* `" ^% H+ b1 j2 ?' ]) J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! p0 E3 u( q$ N6 c& D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 @! r$ f& l8 I' P0x00, 0xFF); /* configure the clock for transmitter */
, E9 }) C5 |" K# Y @; Q. }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% z' _/ |6 w; q4 ^5 B. [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 g% n# S7 ]* G: d9 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, s2 A7 z# N* P+ R$ g7 u& s
0x00, 0xFF);" C8 ^4 w: J9 y# A' p/ @2 t
- N* y$ t- u0 w" O. u( q4 V( \/* Enable synchronization of RX and TX sections */
- f- c+ g; ]' g$ G' T8 F, W. `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ h7 w( v: ~) S5 I& L; F4 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; j- P2 V. T) H$ D0 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. Y$ `1 Q1 D$ C** Set the serializers, Currently only one serializer is set as
0 ~1 e% o; G i** transmitter and one serializer as receiver.4 W4 }- [7 u. F9 N$ {% j; C
*/! P3 L5 L& S7 P1 g5 T# _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ r {0 I+ c+ vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% r; O2 b$ U& |$ S7 e. T/ m0 x
** Configure the McASP pins % @- w" n: [! i* D" i( K; a
** Input - Frame Sync, Clock and Serializer Rx
5 E4 h5 Z, \9 T2 E Y4 A** Output - Serializer Tx is connected to the input of the codec
8 V6 ?, Z* }7 p- q5 e' @( [! z; ?*/
) p6 g, r A$ }2 U+ @: oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" y- r5 F `' W& `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ?5 Z0 ^4 E& F) YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 C/ R& O1 s) R6 b0 C. r4 R0 l
| MCASP_PIN_ACLKX# L- r& L( }0 C8 L
| MCASP_PIN_AHCLKX
4 c k0 N: Z( S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* c; n- ~8 C4 q4 O" [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , E1 |* p& _7 s% L3 I( _- n2 y6 ^
| MCASP_TX_CLKFAIL $ m/ @% y" c4 T! z7 u: g
| MCASP_TX_SYNCERROR* f5 \7 ?1 Z) p+ d+ o9 }) L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. H( O ^$ f9 y2 x| MCASP_RX_CLKFAIL9 T+ u V8 y# Y1 b X
| MCASP_RX_SYNCERROR , C7 ~' x4 M* G
| MCASP_RX_OVERRUN);+ |$ I* {( o! l$ H" A: K
} static void I2SDataTxRxActivate(void)
4 \0 _- C* u0 ~- L1 @ `5 n5 D6 U8 y{
# x% u7 y% _" x) t$ z; ?/* Start the clocks */' q9 \" Y- t2 I ^) U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; k9 y" y7 P* y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ n) ^! j6 Y/ B, a" {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ C( ^! m3 ]7 Q! M: o% S# p6 eEDMA3_TRIG_MODE_EVENT);/ z& z& V4 m5 ?& v |; F8 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # w5 b- V$ u- a$ t, o+ G3 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% d+ ?! y6 U8 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 j' O0 N6 K+ B4 z4 N/ C- B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// F3 d8 X L0 b' j; [! b( u; Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; _$ [& Z' `# U1 {: EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ _$ E7 I! A5 s. @# }5 ~& j( UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; T9 E6 M/ X8 Y7 @6 ^9 u+ \! D}
% a2 m) p% h% n# P; Y7 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) J, V5 ^1 a# b5 }
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