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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& L7 f/ y) M; m' O9 M" z: Dinput mcasp_ahclkx,
6 Y* ^, m9 I( [( [7 T. |' winput mcasp_aclkx,
' w4 k; c3 Q* c) H6 v) I j+ ^input axr0,
" P. w$ u. @; r z! R/ s' L9 e* Y. N4 o
output mcasp_afsr,
0 }* v! [0 V7 g, koutput mcasp_ahclkr,
2 J& x: }+ n4 s) H8 Woutput mcasp_aclkr,
5 u8 q! ?' P# E9 z- i0 Uoutput axr1,
7 ]% U% H% @1 P l1 }) E! U8 ^ assign mcasp_afsr = mcasp_afsx;) q- q8 P8 p# S' H
assign mcasp_aclkr = mcasp_aclkx;" w! O Q$ ?/ L, b
assign mcasp_ahclkr = mcasp_ahclkx;
( J! v/ z2 b8 _; o0 B7 X3 l' sassign axr1 = axr0;
3 d) Q' k d3 i# V# P! A x8 z
" {1 D n, u, H. o' l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. k" q5 k, o& g( h4 _4 V+ ystatic void McASPI2SConfigure(void)
( Q) F" F" h0 k/ x: C3 o{
/ q1 f0 w% q) j( tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 a# s) P5 d, Z- \" i1 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# W: @3 {9 X" xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) }, Q/ B/ m- v% v8 m) h9 r8 _2 Y& c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& N6 I6 `' G0 T' [; z( d& [$ F/ l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# @* E) t+ h1 Q( g
MCASP_RX_MODE_DMA);
2 W* g/ I* F9 ?+ IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ R- l# N4 w3 [% T3 n6 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; z, }7 y' ]0 z) @0 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + O& s+ @( z2 x. e6 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! ^$ G7 y* C9 wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; Y/ p$ L# G, w4 h0 S7 a) A! TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* C0 B: F3 v" F/ h: L2 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' j2 b- D) Y1 w4 X9 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & N* y" p" `# @8 [$ o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( y! m1 T+ E5 c2 a5 n5 r- ~$ x
0x00, 0xFF); /* configure the clock for transmitter */
$ c" e. Q2 b9 f: JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. H/ z3 x( a- p/ x+ N% P4 S: ]" ~8 r- f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # I% `' F# Z6 I) D. a* z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& L3 k$ Z: ]) i
0x00, 0xFF);4 x' c2 G n* x2 d5 q( ^7 \
: z2 T9 P- a/ V* H5 Y+ u$ D) q/* Enable synchronization of RX and TX sections */
+ O2 U; v! D; ]6 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- z8 Q# b' `& X hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 u. \9 O+ l$ ]9 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ h! v$ _* y0 L
** Set the serializers, Currently only one serializer is set as+ k% o# j& p& T* k
** transmitter and one serializer as receiver.
0 {$ ~$ V" b+ b7 o$ ]*/
2 I9 G& ^7 Q/ r3 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# B7 e2 a" i! b; y) j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: ]0 N. V8 H$ r
** Configure the McASP pins , Z+ X7 s: q. z+ |
** Input - Frame Sync, Clock and Serializer Rx: l! |8 n( D4 T8 h. C
** Output - Serializer Tx is connected to the input of the codec
+ m8 ]$ `8 G T" W3 c) _4 K1 \*/: u! K) n& z6 o' B, J# _' p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, f! |0 U; |2 ~6 u2 a0 f; ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: X$ L* ^& c3 s* k5 o. B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 |9 S7 d3 g3 ?+ y& z B: R& @. b2 N; P| MCASP_PIN_ACLKX
9 w' D8 Y2 w4 _" n9 || MCASP_PIN_AHCLKX, U+ N7 |& i. W8 j9 E4 V- O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 x4 i/ j5 f9 o1 f8 E* n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR r% r, V" ~0 ~! g" Q
| MCASP_TX_CLKFAIL 5 k! M6 [4 X4 N
| MCASP_TX_SYNCERROR
9 |; g- u" q) N. q- ]% b- F( q) l* s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 M8 }8 G: ]" s ]! v
| MCASP_RX_CLKFAIL# s8 A6 f t8 n+ q5 |/ T
| MCASP_RX_SYNCERROR # t0 V" A* L j* ]2 f+ M
| MCASP_RX_OVERRUN);2 l" l+ o3 q7 ]) \" \7 {: n6 U
} static void I2SDataTxRxActivate(void)
* K' ^% b A4 u7 C3 q: R7 j4 [{
/ T2 A; a% E4 S. q/* Start the clocks */, @5 v: Y! j8 c5 C$ N/ \" f- i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ J0 y, ?$ E2 c# T8 o- QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: W8 t8 m) a# @- l% |+ \9 C; tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ v1 }; Z. i7 Q: F' }
EDMA3_TRIG_MODE_EVENT);2 U3 U4 Y9 Y% r) \8 S( O5 Q& a& s9 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . l7 y' F* t, V$ E, B" u! m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# U' X! B& H; \) K0 Z1 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 e, e% p/ h9 c7 P6 l( h) lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* j# g9 z0 u3 e# O7 G0 F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) J* g- A" i3 ?) i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 e3 G, a3 |9 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. [" n4 \) [ W V" e# r9 I9 p
}
: }4 d$ U. Q0 N: i2 F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 ~6 i: C) j( h7 D+ @ |