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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% s: a) y: N: G1 k* uinput mcasp_ahclkx,
2 U M- n* {9 Y: H$ V4 Binput mcasp_aclkx,( N& a' U& o0 |4 b. c5 d
input axr0,. y0 l* \4 F$ X" }! X% b3 v
- Z( g) t, u% B$ s
output mcasp_afsr,
8 N( W; j7 S0 i1 ^# L- moutput mcasp_ahclkr,
4 h- D8 R3 Y! N$ @output mcasp_aclkr,. n, `" r% O! Y5 z% D
output axr1,1 I7 e5 a* U) T& _. I' ~ B
assign mcasp_afsr = mcasp_afsx;6 Q- G" T2 c2 Q2 {$ p
assign mcasp_aclkr = mcasp_aclkx;
& @" z: }/ O2 e: A0 W( u$ Qassign mcasp_ahclkr = mcasp_ahclkx;
# O) U, d4 W/ sassign axr1 = axr0;
% ?; T/ l5 S# _) M+ t
: D- h% A6 `4 F0 `! V2 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & n9 c, _, q1 F( @0 S
static void McASPI2SConfigure(void)7 h3 \* k- k2 ~# c h# ]% @6 ^
{! k- T+ J B* w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 T* o% {! l9 {1 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; e2 d6 Q! V9 |6 @* {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 H8 H R2 U7 d f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 C) e# W) e$ I0 H0 a3 p- o& f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- Z4 Q% E4 U- T" Q
MCASP_RX_MODE_DMA);
* L5 D+ e# b5 b2 r3 l) \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 z) a s) A& f, q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& A( S8 v$ o7 \: A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 V3 c9 t8 s% u$ m" R- ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 A) ^2 b: k; ^1 P* |/ ?) OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / f! u3 k* C. S2 ~1 s5 p9 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! C, C0 n3 ~8 q4 V2 f, t! o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. [7 y! k3 X4 F1 q4 e( C, O: S) n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 _5 C1 Y! {( {3 S+ dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' N/ z- ?# M* s; L0x00, 0xFF); /* configure the clock for transmitter */+ j( {6 M+ ]* N% }/ }/ q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 M" m( E9 R3 [, O4 [% AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 _7 W4 W8 a. I% U5 m3 ?1 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 o+ e( G+ O; X$ ~* y- o, C) _
0x00, 0xFF);
4 r3 J, S/ b; H' v
4 H# H2 z) @* T/ M- {/* Enable synchronization of RX and TX sections */
" u8 s3 W$ _1 i* |! T3 eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 a2 u X' x% E0 [" n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- G T8 H( |2 p, W3 {# z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: T# u" M# |1 k o
** Set the serializers, Currently only one serializer is set as1 Q J; L( q# y) k" b* t
** transmitter and one serializer as receiver./ t- [+ _$ t c9 r2 k* A9 `; s6 r
*/% p1 K8 m+ V: G. s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# b7 d+ o3 {& u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. U% H( d! q4 K** Configure the McASP pins . s! A) V& u" h- P+ Z. K
** Input - Frame Sync, Clock and Serializer Rx- ]. B$ `- A" y1 g4 _: B
** Output - Serializer Tx is connected to the input of the codec
6 B! k; D4 d) d6 \! K5 l*/
" _; N, P4 S6 u; W! _0 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- A: k: k$ @- T* O+ v ?9 m0 l. AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ c# A0 W' N: o' d/ G9 o& F9 A7 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, r% i. y/ r- o+ q
| MCASP_PIN_ACLKX2 `# @9 L" E2 T. J6 w/ g
| MCASP_PIN_AHCLKX/ H* p0 v/ {8 E& G8 R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* M; ]% a0 O1 f1 q# q% o ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 J3 O5 k p O+ C
| MCASP_TX_CLKFAIL
* w4 ~, E3 ~; h| MCASP_TX_SYNCERROR. \) T) m# w" Z0 r0 C, o) X. e" M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 ]7 s$ \0 K8 V0 L, t3 A& w
| MCASP_RX_CLKFAIL0 c( D: z V2 E7 _% m8 F
| MCASP_RX_SYNCERROR
: e8 d1 u/ o' O- |2 l| MCASP_RX_OVERRUN);
$ c5 F+ D" M+ A' n7 p* d; m N2 ^" J} static void I2SDataTxRxActivate(void)
9 _, h" k0 s* y* R/ y! Y( O! Q6 P{
) |# y7 u4 {7 q6 w/ \/* Start the clocks */# W; P6 L' M% \, ?* Y0 s& ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 G5 B% q/ O# p% a7 n0 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 F L6 y0 G9 ?1 G$ r& _4 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ R6 g/ ]% o( F( i' U; ^EDMA3_TRIG_MODE_EVENT);
1 d2 O6 [: W3 M1 d* @) o$ UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ w% ^8 N4 ]* S% kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. [( [5 s! p( E$ M9 | Z! r$ `/ x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); ^0 F5 L+ _# c7 H* }/ J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ S- Y! F' m% m; G8 t( e+ j6 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 k) B8 w7 X% F5 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ {5 C+ M- h2 t& ^5 ]; ^1 }0 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 d6 [8 X" K1 s! Z! n0 Y: a5 v
} ! g" F* h0 l4 Y: o6 @- e" ^* m& P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " }3 l, q3 |. P2 x4 u% M
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