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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 M# ?& C; h0 X( K$ m# |2 L
input mcasp_ahclkx,
: g1 R u$ S+ f5 Q; Winput mcasp_aclkx,7 h, Z4 [$ H6 P# l( ]3 c. E) t
input axr0,
( b2 X$ ^, Y. l+ [6 O7 f/ O8 i. R- d/ S
output mcasp_afsr,% ?+ v; E8 @4 e6 b% O
output mcasp_ahclkr,
2 m: r) w! c" \/ @+ V4 `4 Uoutput mcasp_aclkr,5 Z* `7 a- Y3 p
output axr1,% ]; @5 [; Q4 ~, C/ k
assign mcasp_afsr = mcasp_afsx;! h3 ^+ _8 O: p2 q! P6 ^9 ^2 Y
assign mcasp_aclkr = mcasp_aclkx;* |( i/ D7 i V! M
assign mcasp_ahclkr = mcasp_ahclkx;+ @1 S' i3 H& d
assign axr1 = axr0; * |. D9 u U8 d3 a- d* o
7 v, v4 w9 O" ]9 n, B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ z; M6 O$ Y: y6 H9 _- rstatic void McASPI2SConfigure(void)/ L7 F' V0 ^1 `$ O/ h# a
{
8 g( I7 M( w2 E1 ?" ?( AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' S) h+ y7 _7 ~' lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( } K/ n# E; j" {: R; e0 j$ wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: Q) @$ Q" J8 O B8 m5 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 Z& a! U n& c; ^- ?. ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 e4 s! d9 M4 Z' N8 D E& t/ HMCASP_RX_MODE_DMA);8 }, O5 p2 y2 f$ {3 h5 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 z: V4 x% y) a3 D8 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* {" s. o" P y- w" k# b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, b* W+ G0 S/ [: V1 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# e3 E* P' g3 A. t8 a4 S Y6 f$ uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; Y k6 R0 w: D! B9 e( X* ], B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 P5 J6 }" A$ y" K* o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 J1 ~5 H3 h: c# ?1 x7 M0 \. m: B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); Y% V! A0 ~+ N! n( m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 l, |& W) f8 P
0x00, 0xFF); /* configure the clock for transmitter */# ~. E( ]& B# D9 ^, `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ O( p- D; Q2 z3 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 D" a$ F! j1 X# t+ h, a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ F1 T; c! d3 b
0x00, 0xFF);
; v; o8 i, C9 F+ l: `! p6 o0 }( R: ]9 ], @- `0 r$ E1 x
/* Enable synchronization of RX and TX sections */ : j6 @5 C+ z! } T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" ~, i! U8 D9 S7 J. M/ A. J3 M1 I; c; eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 r' ]/ m* G$ j/ v3 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' z2 }1 B' t; h& u9 q- H$ p! N: s* @. \% j
** Set the serializers, Currently only one serializer is set as
3 }* S8 M5 R0 I' P$ h) @) ~** transmitter and one serializer as receiver.) I- v( C6 E# A
*/
1 [/ w0 H$ b# n5 K% IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& p6 z" e8 Q: d: j" o4 I8 u( [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ d: P0 g8 i% V4 L- i/ n0 G [+ p' I% L** Configure the McASP pins
2 O* e# f) }5 V' {5 e4 h** Input - Frame Sync, Clock and Serializer Rx7 h' u/ m3 f* B4 Z7 B
** Output - Serializer Tx is connected to the input of the codec
: S3 I0 v$ i( r9 B! [*/3 s& F5 g6 y* h. d q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ X9 }4 X! `! ^) @4 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 |1 o( i. } e9 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 l- q# P" y, C, h, G
| MCASP_PIN_ACLKX1 t* i% J# G3 @3 G3 C& t
| MCASP_PIN_AHCLKX' o; t$ X: _9 T& d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; e& q. l( x( P0 B- ^5 t. MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & M8 `- w6 O& C& e" D. j+ [* V
| MCASP_TX_CLKFAIL 3 Y1 X4 P4 \( [! v6 L5 i6 o) M& a
| MCASP_TX_SYNCERROR
. |6 c ^0 C7 k: Q- k+ t8 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 E7 g+ r6 Q5 B. k7 g5 D+ n| MCASP_RX_CLKFAIL& }) x3 L/ Z9 b
| MCASP_RX_SYNCERROR ; X3 O/ v5 i! D: e+ m
| MCASP_RX_OVERRUN);
) v- o( G' ^: i, d} static void I2SDataTxRxActivate(void)
3 t6 P0 I4 w% g4 q& a3 H{" y+ L# N* W& G( F2 ^- v( ~" `: Y, O
/* Start the clocks */
; U( ^: O0 v' J ^: IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 q2 x5 P7 d: U& u: R1 g5 yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( `: s6 y) M( d( k, V" P3 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 S+ |( a# L$ CEDMA3_TRIG_MODE_EVENT);! n1 t- V( w( W" k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 I5 S6 w3 R* w! Y0 L& J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: h2 e2 ~8 X/ b: R$ U& x1 ]; y" Z; F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* f" O( r( C; R1 ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 h+ f3 i' Y3 F) bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' I( B7 d2 t3 M% DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
z$ W1 h- {: v6 b) a+ U7 _! vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! J; y* v' P ]
} ) D& I( j% k/ P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * M# \# R+ Z- ~1 R
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