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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, K. B+ p. ?/ W. x9 [
input mcasp_ahclkx,
" N" A9 {% b/ w9 \+ Qinput mcasp_aclkx,
2 R) J& d; X' [) vinput axr0,
" C6 `) r7 N7 \4 f9 X) ]3 T! H7 _$ h+ q1 @+ \
output mcasp_afsr,
& T0 ]3 M+ e( W) q5 x9 t% uoutput mcasp_ahclkr,5 t' N2 W0 X) l s8 y4 c+ X3 c% ^: l2 |
output mcasp_aclkr,
1 Z2 J& A; X( s1 H+ G$ J( J5 Ioutput axr1,3 V0 C$ |; ]" E" M( L5 S% L$ a
assign mcasp_afsr = mcasp_afsx;
7 N& [# g3 S6 Z* m2 uassign mcasp_aclkr = mcasp_aclkx;
) S+ G7 f$ P' q; A4 Massign mcasp_ahclkr = mcasp_ahclkx;9 t8 w. G) q4 u% z- Q
assign axr1 = axr0;
$ r8 q: h1 A! z$ l6 v9 y) Q1 H( {# A, f. @! I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + H; Q& g7 B6 k
static void McASPI2SConfigure(void)
5 F6 G, Q% a# g3 n{, j4 s& P" Y' k; h- O& Y' ], `+ V5 S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 N: [4 c ^' l) z" }, w0 [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 N4 L5 I+ w# n6 P2 p* v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& \$ v$ q- W6 \" ^9 N8 a4 H4 r5 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 Q7 L$ q6 \! O% K* V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 e" J% ?1 I) y; B' \
MCASP_RX_MODE_DMA);
/ ]4 }- o2 c0 |. s# C( VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* C/ [; R& l" Z) j. c0 j$ n% |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 o9 s8 U. R' k7 u" RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , q* \$ V& H0 r8 J+ T% ^7 G7 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) K- v0 @9 c; f# d3 m2 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , j2 Z0 u0 Q2 l0 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" Y' n1 w9 d3 ]6 u! i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& D4 b$ t$ i# }+ SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: V1 i6 k" \( r) fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 L o1 R8 N8 x$ K9 f
0x00, 0xFF); /* configure the clock for transmitter */- Z. ?5 v6 A$ I$ f1 l6 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( I" ?( b3 s% f `6 D& {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 V; S- `# q7 l0 H( ^1 H) G8 `* K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" R( q9 u) l4 G( O5 `% y% [- V0x00, 0xFF);% Y: v5 {6 O4 z: W/ s
7 Q5 _! C Y6 Z' R, K" m. I) v @! F
/* Enable synchronization of RX and TX sections */
4 w4 ? k4 f9 ?! ~% U" o$ O1 n3 a' VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
J) O+ _+ F& g# ]4 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 }- {5 z) S0 g% H0 ?6 M5 x" |6 PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; U% R6 T$ F* L) T& {) L5 f$ m2 m
** Set the serializers, Currently only one serializer is set as
\4 o9 _! g4 }3 C f; v# U** transmitter and one serializer as receiver.
& n# s4 i% E Q- w, Q*/
$ v3 {# [( G( S8 C8 ` \4 U* cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 }* F- t, n& B+ V* a* X% C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ |, M5 ~( w8 \1 R, Z4 R: X/ R! B) j** Configure the McASP pins
9 P+ \, I1 d$ _, i* `** Input - Frame Sync, Clock and Serializer Rx
% s& [# h: _ ^" e( m4 G** Output - Serializer Tx is connected to the input of the codec ; `, b. P! Q$ W% S9 B! x( k4 \0 ^
*/
+ E! L0 I8 Q1 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# m. }8 T4 D- X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( p* c0 Z* B( C. yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. W( C4 j7 r9 S2 V- k% Q- b| MCASP_PIN_ACLKX
4 `! v! |/ L) W' x| MCASP_PIN_AHCLKX! _! T- ^, _3 K7 o5 Q# B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 B% J+ c0 t, ], X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 C5 e# K: r4 |$ u
| MCASP_TX_CLKFAIL
, m% i' z1 ~" Z7 L| MCASP_TX_SYNCERROR% A9 U0 G5 I, E( C, Z# X1 V, w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 e2 l+ w8 }" i6 |+ t e" r
| MCASP_RX_CLKFAIL
! {/ k" ? b3 F+ ^ [| MCASP_RX_SYNCERROR & j) w7 E: \5 M: C6 U; H1 l: |( B
| MCASP_RX_OVERRUN);
& b' u* g4 q0 d} static void I2SDataTxRxActivate(void)& o7 p2 `1 `9 O0 p4 ~. v* R! K- n
{( j5 J) U! m, f; J* ], S
/* Start the clocks *// Q0 }* R: k ?( U; x! ]0 f' o6 \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ k* F" k z* z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: q) P( D2 P m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; ?- |3 @4 M( k" CEDMA3_TRIG_MODE_EVENT);' g/ ]: z' c1 H! x5 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - T# K. C- z' [5 m- Z0 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" b! w" G; @ ]" a" ~5 l% |2 t3 |+ G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 S& z9 n1 \6 ~. H5 \% ]( e* {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( C( V# p% g, f, L+ |+ B/ R8 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& s6 y" J( O$ ^7 L( g" n0 v# e F( jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) K4 d9 e0 {1 M9 E, HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 ]- S+ S3 d+ U' M}
* y) `( n3 \# @5 U. C: {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 a* j5 Q4 L0 Z1 r
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