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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! [3 p) O/ P4 M# G7 ^8 O
input mcasp_ahclkx,) l5 e! N( c6 W+ N
input mcasp_aclkx,
& l+ O2 j+ B+ xinput axr0,# ~5 j& p7 C Q9 I
4 h" y8 l: d. T4 U& S, {output mcasp_afsr,6 q$ T" A5 n/ Z9 H0 Q0 h
output mcasp_ahclkr,$ P. n/ T/ f) Z' J4 _4 N
output mcasp_aclkr,
) {8 T! l4 |' \output axr1,
) h/ K$ c3 u4 ^$ b O( _ assign mcasp_afsr = mcasp_afsx;
4 R! m* \- h$ b# j6 [$ `) V- v6 m" X( z5 Yassign mcasp_aclkr = mcasp_aclkx;
/ w" H! ]+ j: ]" L$ s4 t2 o8 k+ Wassign mcasp_ahclkr = mcasp_ahclkx;' _% L6 b. E* T* }' N$ D3 f
assign axr1 = axr0; 3 K" t l7 b+ l1 p5 t
0 B$ n2 g- f) ]( n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) F0 T7 U* f4 _$ }5 L% D) Lstatic void McASPI2SConfigure(void)
6 u P! {8 W+ Z$ F% d{- b e m4 i( w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: w* |2 s) Q" A5 w4 @5 E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 {0 @( ]% B5 X0 P# C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 m' J, s% c+ d6 |2 o b$ V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// `% S6 u' ]) V0 P- G6 A% W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* z: r: a# v* S6 b6 @2 q' nMCASP_RX_MODE_DMA);. D. Q) e& H% Z& G' u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 _) a. x; I6 ^8 ~3 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- f; S8 H4 [$ b; Z* }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) _' e( k* A' f8 u9 u3 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" Z$ d' V6 V& Z" N6 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( m* z0 ?. { t3 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* @6 l5 H' c+ i( SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 j* I! l% E+ d9 k9 h7 H+ DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" ~% ~. \7 I- K' W- A c; AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," Q* p8 e4 s/ L2 Z
0x00, 0xFF); /* configure the clock for transmitter */
! a3 y, u# f! O- j& @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- [: J: V% Z1 V7 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . j) ]" B9 w& D6 N# o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 @$ D7 R( K; c0 j0x00, 0xFF);
$ i! b$ Y. w8 s
! v1 N; p: S8 q7 `, i9 \& |; D& b' \/* Enable synchronization of RX and TX sections */ ' h9 L* G" n. k. I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# q% b' p% X- C! Y2 A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) S; x, x4 Q, z) U) ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ^7 F# D P4 B" v# X0 a& D9 Q
** Set the serializers, Currently only one serializer is set as
( ]. E4 W9 W4 g8 b( J** transmitter and one serializer as receiver.' o2 I; v# m6 C5 e
*/
# |, H% i* L8 E* q/ K& Q1 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% a- P7 S7 K7 H4 A/ a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& N- n# u9 V) ?" _5 H( {( k a
** Configure the McASP pins
- B" k6 Y+ _$ B b) j& Q** Input - Frame Sync, Clock and Serializer Rx2 j' U$ H& C5 r+ @) A* H, M. `
** Output - Serializer Tx is connected to the input of the codec
) V! v, F% q7 F- O7 k*/
0 q- @5 Z& N. j2 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% p9 ~' y8 n# z: s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% q S5 v8 P, a& X7 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* O0 x; n4 v/ r9 K4 P H# }: b |
| MCASP_PIN_ACLKX
" P% o$ F. q1 A( z- w| MCASP_PIN_AHCLKX
3 V$ W. J- _. M* k0 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: x1 b, p: d$ HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* j/ P- f' H6 P' c$ L| MCASP_TX_CLKFAIL
$ a. j- v+ x1 ]" `' A: Y* m( p| MCASP_TX_SYNCERROR8 c/ Y7 I4 `0 ~: {: T- e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; F: a' _ e% R0 a) B) ^: k
| MCASP_RX_CLKFAIL1 }3 B* r! c5 m; ]7 t
| MCASP_RX_SYNCERROR
6 k! [) Q! Z9 ^9 z. g/ b/ z| MCASP_RX_OVERRUN);8 b, K0 z9 ` e5 N. K8 S$ |* c
} static void I2SDataTxRxActivate(void)& A; K; D: O$ H5 \. P' t& v! \
{
7 j e5 q4 w" v' ~/* Start the clocks */, y( x# D7 }) {4 h0 D( Y; k' F2 o+ |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 g. l" r' q6 i( J( H8 S: hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* g/ ]4 o- E, l( A& K) }0 _2 O3 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 }: c- d& e( }: z
EDMA3_TRIG_MODE_EVENT);
. O$ `9 @* x5 S5 {$ z0 K$ i8 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * |; b; B, g. b9 A) P5 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% o4 `; o" x2 V9 M& pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ L1 R: ?) v! X: F. kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# P8 ^# }* Y6 w/ owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' `& Q a* f5 Z+ @3 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% h" e! W8 |% b; [1 a' H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 {; ?7 m! v$ [1 f. w7 h6 J
}
2 Y ^+ F' [1 }$ I. Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; i) M, b( v X: l* U! W% C
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