|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ p/ n2 s5 d1 G5 K( o# finput mcasp_ahclkx,, k, a$ O' b" b3 Y y# D
input mcasp_aclkx,
% H+ R1 c- e8 b7 P* H. Xinput axr0,
8 \) ?* s L {0 f; l% r3 G9 X2 p( N: k
output mcasp_afsr,
) r+ X7 ~ ~& Y# }& x" xoutput mcasp_ahclkr,
- o# F( g9 Z6 z( Youtput mcasp_aclkr,; r) v! o( Y: D) [' X7 D/ e! z
output axr1,8 J% E6 t) w! U4 B) h
assign mcasp_afsr = mcasp_afsx;6 w! ]/ g- C5 I
assign mcasp_aclkr = mcasp_aclkx;9 }! a" G, r/ W8 C% y6 a$ c
assign mcasp_ahclkr = mcasp_ahclkx;( o# p9 @8 Y8 ^" g( G2 ?: s( g
assign axr1 = axr0; " C/ q( W( M2 a
0 X8 y' g; M7 t! m& v' b- u& Y1 r+ Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 S/ P# j/ y" }( W2 |' S% @+ D$ ^
static void McASPI2SConfigure(void)# }! D i! N2 `$ s
{
1 ^+ t& j9 n8 R& R. ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ K% k5 D8 Q5 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 |( A5 j8 d! ^8 N4 m" GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& j9 Z1 G6 \4 [5 N9 f2 P, ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 m2 I+ k, O1 w3 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( j0 U1 a9 N/ ^: R1 s4 F
MCASP_RX_MODE_DMA);
3 F F3 r. D1 g( ~- DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 m( ^' |$ Z7 a6 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 A/ I- h9 D; EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , f+ M: d8 g4 ^$ `( l+ ?5 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( e: ^1 W& l2 V! J7 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; Z- o8 Y' |* p- rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. o" e: y, W/ D9 [: \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 n' ?7 }3 V) p) v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( w. i1 H) e( m/ S5 s$ a7 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 \1 G" k: @+ y6 [# D& J# Q
0x00, 0xFF); /* configure the clock for transmitter */; [: q- q5 z6 _- M* L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ S3 f8 E1 J4 J" r9 R1 U p6 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , q( v6 r% u* u' I/ I/ Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) `$ m$ N7 Q4 Y' a" m
0x00, 0xFF);
9 @1 F: E7 z9 _# S+ l$ u, A/ `
% e5 q- E4 q$ R3 Q/ t/ y/* Enable synchronization of RX and TX sections */ & x4 i( C# n0 S# ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; E! Z1 M |7 W6 d& U* ]( c e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 M7 u- U$ w& N4 o, s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 V2 A" @- a1 |2 \6 U- @** Set the serializers, Currently only one serializer is set as Q8 {/ P; j7 e
** transmitter and one serializer as receiver./ e. g) ?# W8 l7 s% h
*/2 ?6 f2 K8 T2 d* C" r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 {. m" {' D* Z& A% }1 V0 N0 G: ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* p i6 w! P! |/ `& B** Configure the McASP pins 9 J/ _! M: L2 U# {
** Input - Frame Sync, Clock and Serializer Rx4 n7 E! N( f% b( m
** Output - Serializer Tx is connected to the input of the codec
. a/ G& } i6 u- `, \( L L: W*/
\0 O3 ?* p S$ d/ g) \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
n0 q+ V4 A+ ` E' IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, [$ t0 V3 @3 U, ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 P( Q4 T) k" q( y O; O* c| MCASP_PIN_ACLKX8 [ ~- S7 @6 }$ x% f/ P- ^+ U" ?
| MCASP_PIN_AHCLKX9 j5 S7 {; ~+ N& N b- M K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 o* W: V. g6 Y" u- t' C' R9 k! c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ u, T! L! E0 ~. p& V! v
| MCASP_TX_CLKFAIL + M* |5 f: s! j0 u
| MCASP_TX_SYNCERROR
$ Y# R% N% e( X0 U4 z8 f9 k7 @7 P/ U ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & Z7 |( L0 U) i
| MCASP_RX_CLKFAIL
* L6 B. ]& t; c" C( F5 e| MCASP_RX_SYNCERROR
0 [ s4 m8 [, r1 d- G. @| MCASP_RX_OVERRUN);
: K3 l5 i9 l( |% q% O9 D; T) u} static void I2SDataTxRxActivate(void)1 t5 C: L j3 R# U8 q9 }* L
{
" O3 T( M+ O; F3 p. e7 z! d/* Start the clocks */
2 t1 U9 g" t8 A' Y l5 Q- K( bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ M, z) s5 m0 Y% g" V. CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* G7 l- P8 t a! {. N4 e) H- DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 e) x1 y. F$ V
EDMA3_TRIG_MODE_EVENT);
6 \/ X- z, W, fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 J9 y) j% M* l( ]$ d$ VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ S8 @: s7 d5 A1 t- x$ P) b' MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" X4 h0 h0 P* ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# f! M w: Z ?. ~ m6 { B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ V" |( V( Z+ T4 R0 W/ {% C9 EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 ]* k t! b1 m* v( ]: pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. P3 N1 }7 s# [, V1 x& ~
} : ]% Y2 r5 h/ A* F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) O0 V! c) i5 O: U& T, M7 e# Q |