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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 `# L9 k D3 g; g3 \input mcasp_ahclkx,( w1 s, ~. f# G& Z( s9 G
input mcasp_aclkx,
) ~' ]& }+ T: d$ Q# ainput axr0,
5 B; d' w6 y8 H( ^" h
9 W* ^$ c9 ]( j; ]$ ]2 k1 Q* x* S% Xoutput mcasp_afsr,9 t1 K" {1 l) H5 V# J
output mcasp_ahclkr,
. S/ d, J6 X6 g) I" f4 Noutput mcasp_aclkr,3 z8 ` n+ B+ R g" ^
output axr1,
* N7 a* s. j+ B assign mcasp_afsr = mcasp_afsx;
! M& |; [# c. R/ d, ]8 Nassign mcasp_aclkr = mcasp_aclkx;
3 }* w- u( F/ q4 `8 a$ dassign mcasp_ahclkr = mcasp_ahclkx;9 o7 Y: {# W" @! t, _. K: d) \0 L
assign axr1 = axr0;
8 q( ]! R0 {) e b* ^5 g5 W @4 u2 J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 {0 m6 j) w8 Tstatic void McASPI2SConfigure(void)
* n& |0 t+ J* N9 I; v" T2 `{
0 A5 K: [: u: R, Y! h& JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, e d2 R- o1 m8 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ Y: f! b0 V4 [- w1 `/ |" i) H5 ?, ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& Q' h: }+ q% y& W2 e* E: ~" o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. X' d9 C7 Y5 v# u& hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," G1 @2 r4 k' Y2 |
MCASP_RX_MODE_DMA);" x0 Z$ y" Z1 v" N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 c3 n1 @9 }& J4 V/ o5 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# w) z" S2 \6 N8 l8 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. p' d9 f- v) _2 |9 B# `4 q6 }; SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 s' N1 Z& K$ U8 N# X) n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # ~6 s# E1 e M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' E7 n9 W- f1 t* h; m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 X; A% Z4 ~" b( {' RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 a0 M1 b& Q, q: i2 v, r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ y# Z1 A: x7 e& H# \1 [5 U0x00, 0xFF); /* configure the clock for transmitter */" H# D) r3 L' I' b5 f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* ^4 f. L, _% k- u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; g0 L2 f3 R& y5 Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 }" z5 ], E1 V1 \0x00, 0xFF);, z; I, a) b9 G1 M5 ~5 y1 w6 t0 }+ R h
* M2 L! Y U. }. ?# `8 ~
/* Enable synchronization of RX and TX sections */
: D4 z8 ]: U- x- {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) e" r: D: [" b! ^" t- `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ k: t' D1 o) _% A0 ~8 O6 hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- L0 E; ~" z# `+ r3 b** Set the serializers, Currently only one serializer is set as
. [/ q; ~& s8 v0 p** transmitter and one serializer as receiver.
1 U' O* j. H1 f# y# H" l9 A7 g: P*/
$ @" e7 M7 K7 N- UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- G* P8 J! G+ W0 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 I% ~ h9 G! Q- l9 ?- L
** Configure the McASP pins
- k2 E3 n: A: L7 V5 v2 v0 I** Input - Frame Sync, Clock and Serializer Rx
# W c# S& ?, m: w* V* B9 X** Output - Serializer Tx is connected to the input of the codec
# E/ C/ ]2 U9 Z% g5 a0 q*/
5 e: K1 e! f) s4 U; ~! E; ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 W. f! O5 o8 m7 r% q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! b0 f, `* n2 @+ Y& ~8 \8 F$ ?, [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 C' b0 Y: h, ?! ?" K3 j$ L
| MCASP_PIN_ACLKX! @& E) E, x$ \' X; [ Z
| MCASP_PIN_AHCLKX5 C0 V, s( U3 F6 L# P1 Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 E7 |* d t- H" F) O+ ]; f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 X) U6 ^9 j3 s% h4 P! W- b
| MCASP_TX_CLKFAIL * v& T6 O0 Z9 F3 U6 I
| MCASP_TX_SYNCERROR
7 D1 w. d& [7 O4 k6 I. f5 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% R# @# ^3 j4 w8 k2 h0 [ ?) ?| MCASP_RX_CLKFAIL
+ U2 G1 p, K8 n7 z% Y0 c| MCASP_RX_SYNCERROR 6 h; J0 H s t6 ~! D
| MCASP_RX_OVERRUN);
2 y3 d$ V; _; w+ v: B' l4 w} static void I2SDataTxRxActivate(void)
* g1 H/ d2 p% q* j4 F{. Z- n! H2 ~. y" q
/* Start the clocks */' }8 E, \2 W5 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& }/ H3 O; v, `9 C* }+ CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 v. r4 i; A3 T: R/ PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 o% d3 f" w- O$ @
EDMA3_TRIG_MODE_EVENT);2 l2 y k/ f1 c+ X3 c a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, C* e O: N! c. h1 U8 x2 ^* U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ W5 [6 j& {$ T: ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 c/ m$ v% U' U2 x8 m) e. P9 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" f; O# `) [" L% w6 p k4 ?& `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. u8 N# ]( Z, O& I$ bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 y ` v' g0 Q, A& CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 z# ~8 `6 L1 b} " M3 f( }6 R/ p7 `( W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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