MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
" B7 j! t7 P  D+ P0 N- U' p6 vinput axr0,

  A6 O& A5 W6 T1 I) D' L( K% qoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
% P) W0 |( @! R. V( \' X, |% O8 routput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
* Y% `! ?5 p( v: j' g0 uassign mcasp_ahclkr = mcasp_ahclkx;
. ^# O& J& A. Y% ?) V" jassign axr1 = axr0;

! ~. a/ X4 ~8 f+ g+ _

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( s- c$ i, n' J' f7 G

static void McASPI2SConfigure(void)
{
' h0 g% q# T( H, V' ?4 e% g/ yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
6 l0 l# b3 d7 N8 H, O% k* n( t" mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, K3 [% P" B' M0 c( T9 k" f5 l: GMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. s4 l1 [, q( n5 Y! PMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 ^  W- ]. k; ?: j( \' CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, k( ]6 W% L% W' b5 {2 Y' S2 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" Q- e" \; f. a% @6 @4 ~0 N  R# e+ {! aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 Q" K# ?' [4 \4 Q% [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! Y" Y, h0 e( O& Q7 A) x5 r% `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 G! O9 W. K( i& O  z0x00, 0xFF);

/* configure the clock for transmitter */
$ u; C( ?2 w2 a8 k3 OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, f% d+ V* J- i9 e* Q7 Z1 d2 U9 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ x2 x. {3 y. M1 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ d+ s* p, d$ }5 G4 r6 q8 t/ I0x00, 0xFF);

# l5 N; e  R' J. e) E/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ t; q6 @0 n  ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
! s: X+ s- v7 P: C; X  x** Set the serializers, Currently only one serializer is set as
2 t* N( s# @& Q# [7 S- U2 n% S3 N: O: a** transmitter and one serializer as receiver.
*/
1 e4 M" D, V2 t5 `. M2 W8 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 _; S, h: ^' d: J0 z** Configure the McASP pins
, d' |% a  ?& ]3 L, |& I** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
: F) _0 R! c; z& ], W/ ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ~, n+ B1 ~& p8 Z# ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
. R. r8 b) @7 o' L+ c8 R| MCASP_PIN_AHCLKX
: F/ H+ a8 j: w! {8 ]' X- v| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
2 \+ B" k+ Y. d4 W# ]. n: h| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) V4 ~# p+ b$ O6 l/ N$ d* z6 v8 e! Y7 z| MCASP_RX_CLKFAIL
5 h. d* \3 ^4 P6 Y; f) V  z/ a$ H0 ?| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
  {, ^* d5 l$ h  H( S1 T" V2 W}

static void I2SDataTxRxActivate(void)
! D! B, O* H4 [' p6 u9 f# {* }5 K{
4 B* k6 J! [- w9 H0 E/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) b. e- x) s% f8 J5 X1 SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: X& u; f9 b; T5 [2 Y, sEDMA3_TRIG_MODE_EVENT);
. q0 O( j% l% C2 {- ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
) d7 s, V9 P. V9 rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
4 L) E' j9 G  `, LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

# M. G! Q  t3 S: x: V4 F