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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ l: x% V- V0 \2 l Iinput mcasp_ahclkx,
9 Y/ W$ x% u, {! y' f( O. zinput mcasp_aclkx,0 V1 R, n2 l* [7 N- S) E! o E' j
input axr0,4 s' f; y3 ?; c7 b' o- Y
7 y' v- E; X+ u8 S/ s, \2 F
output mcasp_afsr,
, i! Y) G4 W# s- b A0 |output mcasp_ahclkr,
: Z7 C9 A6 [5 Noutput mcasp_aclkr,
$ e; j3 H9 P) E" a1 ?3 @4 Joutput axr1,% o: q' a7 U" B& p# A
assign mcasp_afsr = mcasp_afsx;+ N" L7 o# T2 Y* ^. ^6 x
assign mcasp_aclkr = mcasp_aclkx;
5 W2 A( W2 ^0 D2 _9 Jassign mcasp_ahclkr = mcasp_ahclkx;( M0 c$ b& @5 k( V& i6 V$ b5 \7 T- s
assign axr1 = axr0; * z0 F3 Z4 V$ ?+ Z7 e% _1 k, V! ^5 h
t: h5 Z/ ]: W( X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . D% M: d* P8 z _% @: Y
static void McASPI2SConfigure(void)
|& g# V8 @9 }9 @; P{
Z$ n$ \1 P: x$ @& t* i/ e% JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, p5 r( J" e7 u, Z1 j/ a% T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; G$ c: R1 l4 r8 a$ HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& z$ \* v5 M: f$ n9 |: kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& N6 I3 ~4 ? z0 f. ?- ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ Q5 I7 Z- E% `4 V: n/ r7 nMCASP_RX_MODE_DMA);
' s" g0 s- n' F! B% m* _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 S. y" X5 Q3 ?$ l! z: ~2 uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ K' l- k5 z' G4 m5 p4 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* Z+ w& O- |+ Z7 @: Q8 a$ \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 [2 d7 K* L) G6 t9 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# ?, b9 o2 `! g/ K: H# D: NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- Q, H& r7 j3 x0 |* Y8 p$ \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% |5 V- Q- X P: I: X5 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ \, ~) y% w6 N8 u! f, }+ pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% s1 ^% q7 w6 E7 Q1 \9 g' K# p% k
0x00, 0xFF); /* configure the clock for transmitter */* R, X: d& j4 I2 ]! D0 R, T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 r. S. A% g0 a e0 {+ E- ]6 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 ~1 t) k. n( eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; u7 @- X% h& r2 b+ k0x00, 0xFF);3 G8 o5 }+ M# L
& h& \. K8 }3 {6 b4 N! M4 a, C3 ?
/* Enable synchronization of RX and TX sections */ ' J* |/ p, b8 t* c- q; o; I' k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" D1 C: u, W7 b+ h, ~$ m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 j' K' y3 Z/ A/ ]2 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** s. B' g, C" V6 C
** Set the serializers, Currently only one serializer is set as* i: y! n B, V- c" {* n1 _/ L
** transmitter and one serializer as receiver.
$ I! f# J+ U% v9 k: A2 R*/
& A {' E2 _( [+ MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 I6 Y, n" t2 }, `, F( }! l! g; t: ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 I7 U' Y* R2 x, P2 r, l$ P
** Configure the McASP pins 9 p- S' \! x" x# s9 T* ~8 L
** Input - Frame Sync, Clock and Serializer Rx
2 |" e; r# p5 t** Output - Serializer Tx is connected to the input of the codec
: N) @' ?, v7 M/ ^: o5 ^( T2 @*/, C2 ^2 A4 d) Z+ P( R& b. N) x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
w/ S" d7 L$ }+ p0 YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 V0 x3 a- q/ C3 n8 o: j2 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 {, |" X6 A, T1 W| MCASP_PIN_ACLKX ~$ f) }; _/ a+ R8 j
| MCASP_PIN_AHCLKX
% A. u+ x/ G6 ^& T% T2 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 b2 T1 Q% G' X- M* Y/ r+ HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & B% t8 z8 r9 Q7 K$ c
| MCASP_TX_CLKFAIL
) k0 _# ?$ v$ v8 I1 y! C| MCASP_TX_SYNCERROR
2 }# q3 |7 w# `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 v6 c1 {/ D. a- @5 E1 }8 U7 p
| MCASP_RX_CLKFAIL
7 x% }3 q% N+ H' ]6 ~; h| MCASP_RX_SYNCERROR
+ B @0 c( ^' c| MCASP_RX_OVERRUN);; t c( I! G; \9 Y/ u6 x1 _7 o
} static void I2SDataTxRxActivate(void)5 v. m6 E3 e' r
{
i" T$ o, z5 l" C8 n! V/* Start the clocks */+ s8 k. r6 [0 C: V7 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ {+ z& P- m$ ~, o$ A6 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. o* _2 A6 b7 G( Y* c$ H8 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* I5 i! }. O- yEDMA3_TRIG_MODE_EVENT);
+ w+ H6 m" K0 {$ iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! L5 W/ f7 M, d8 h C3 KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( c) E% N3 Z$ F1 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; a: m! l& Y m! R* c! l' VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 e' }2 `2 J3 m/ }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. L7 d" q8 x3 j1 j( ~3 i$ F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 }% W9 z" y3 n: a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 D8 Y; O7 Z& N! j: \3 }( o}
! q) ~* k C3 e0 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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