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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! s; e& b3 }' Q, j, l5 U/ ~input mcasp_ahclkx,
/ K4 s. h) n; \input mcasp_aclkx,
; w2 \$ Q% ^) i& Yinput axr0,
' b8 ]7 [2 g( Y# w' W! Y+ e$ a( P$ V5 ~8 a
- |% _) b0 @- ^' |. loutput mcasp_afsr,
* }0 u/ F8 r* G0 l( w0 xoutput mcasp_ahclkr,: D! Y; y( g# ]/ i% V
output mcasp_aclkr,
& S) w* E" w/ w/ d* S* @+ Moutput axr1,
7 Q8 h( Z/ r* r! x; K3 u7 X assign mcasp_afsr = mcasp_afsx;
4 c. Q' d# n- |$ gassign mcasp_aclkr = mcasp_aclkx;( q8 A5 `# ?$ [# Q( L- E
assign mcasp_ahclkr = mcasp_ahclkx;( r6 p' x/ S8 h% x5 W
assign axr1 = axr0; 2 y" h, I( {: e, y8 z, v$ Q
/ u. g4 g* }! I, W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : F6 V& }' o/ A! b- x* p: r9 Y3 |
static void McASPI2SConfigure(void)
5 K' Y3 v% _) z' k{
# `5 l) a8 h7 v0 v& U1 Z* QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ~4 C$ X# M0 f @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, ^$ X0 S, _# z, p# |) oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" D- e. U3 \" ^) o4 b/ BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 V! H* F* K) cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 {; K, D( ^ }: I
MCASP_RX_MODE_DMA);
1 l3 P# y6 @& VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z8 k, J% _- X2 L4 j k, GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 O V2 I" b: [, y, V0 NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' ?3 O1 H- {2 g: q; T3 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 R) [# ^& h1 t7 O7 E$ H, pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( u1 N. ^7 ]7 t. C2 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 g) W5 z5 ?5 G4 aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& D4 ]8 D6 w+ z6 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " |1 M1 W* {9 g0 k! N5 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ M9 t, d$ g1 g, H
0x00, 0xFF); /* configure the clock for transmitter */
) G) _" Q4 H+ p% ~5 W( J, sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
M1 g9 y! u: f5 T' \# \& iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ Z n: j3 J# Y1 _' ~: _1 @ f# NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 M6 S3 l& y0 K: z$ p$ Z
0x00, 0xFF);8 N4 o/ I6 n( c8 u$ m7 i* u
% G9 T4 o2 b8 j! f
/* Enable synchronization of RX and TX sections */
1 `& X$ l, `4 e6 U$ V& dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. }, K# M8 [/ n; EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' Y1 k: N# R6 j) }: v: u8 D$ z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, }1 J6 [3 f& D1 \3 j9 y- |" `
** Set the serializers, Currently only one serializer is set as
5 P5 w# j6 D* l; J1 W6 a** transmitter and one serializer as receiver.
5 h; j1 R$ ?! A" @# X: e*/+ ?7 r: R" o$ R; l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, g: T2 K) P! V0 M2 ], y$ n# m/ y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 H7 e9 ]- |1 k. m
** Configure the McASP pins
; |, I. X+ [* |0 Z" i$ Z* }# b** Input - Frame Sync, Clock and Serializer Rx
4 t* z* R; X# L** Output - Serializer Tx is connected to the input of the codec - t" J( r6 Q a! H
*/
& S) I8 q4 {6 T9 @' F$ Y% tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 Q6 ^, s2 m$ B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ m0 r1 \3 O3 v/ P4 i2 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: |0 [7 P$ |5 S: ^9 z| MCASP_PIN_ACLKX
+ x) n$ h+ W5 Y7 j/ O7 J| MCASP_PIN_AHCLKX
! v; P% k5 F) X( \; p R E! w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 d) J- v s) I1 g" \ {- RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) N1 z8 ^7 @) l. Z" C5 X- V' k| MCASP_TX_CLKFAIL
' r' k1 P& W3 W& G; h| MCASP_TX_SYNCERROR7 R, y6 S M. S7 Z$ A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# ~8 Y4 O: s) t* V+ ?- V& O| MCASP_RX_CLKFAIL
, X {3 J, h( v" X; a| MCASP_RX_SYNCERROR ; d! ~5 b8 Q; s
| MCASP_RX_OVERRUN);$ K5 v) L2 N4 Y2 S
} static void I2SDataTxRxActivate(void)
! T" H e9 s6 P. P{
$ ~& K! Z' l$ u* @) I5 y" m, ~, |/* Start the clocks */
- r! C9 J+ p. b3 d, d1 r, iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. Q- F3 P2 ~8 f: N$ a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- b1 W3 A v* U, v/ XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 R# I* V Y5 ]# g7 H$ I1 K QEDMA3_TRIG_MODE_EVENT);
0 n% j Q$ D( s; O- d, nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ i( @# z2 N& W, _+ ^) a' \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& S- m! d$ t4 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ n4 U( d8 z# j8 @. T& Y3 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// |* Q1 f) _ d$ }/ G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" ^0 p9 t! N3 |% h; c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) h1 S+ x1 g& `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 {0 i7 Z/ H9 q0 p4 v1 v
}
3 P$ o' F3 E/ ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' ^6 ^( P' i$ n" `" E( W! m/ ~9 b6 ~
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