MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
6 }$ m; N1 f0 A7 K
3 C* }( z5 M6 z4 Loutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
5 I  a1 V$ `# s% P4 i% poutput axr1,
/ [" H) H  b( X% p4 `% l8 |7 D

assign mcasp_afsr = mcasp_afsx;
9 c- _7 c4 [3 c# T8 wassign mcasp_aclkr = mcasp_aclkx;
6 Q: a) o4 Q) h* m6 J3 o/ W9 Y! Qassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

3 O; k  I; {& J: ?
+ r5 E! D! M/ q

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
9 i# F3 p% d" TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. A" ^% C# y# S: j) VMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
: p, o' [- L* f# w$ x) |: T, Z  k/ QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ g; n5 r# F9 J. E% rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
2 k' |' V3 z6 @# b3 E, y" w0 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
( v8 N' [2 N  t4 W6 K. F0 c  u+ ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) n. {+ V8 r  X& b& G4 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ n, o% S" N4 B2 w7 _# U7 \/ wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" m& L4 i1 S$ Q/ JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ |3 _& H6 F2 f0x00, 0xFF);
1 ~. X0 I# V$ v& T2 b
8 T" n* }( Y# d6 Z3 v9 T6 [* O6 u/* Enable synchronization of RX and TX sections */
& z2 E( o* u% M% S, TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
3 p- R* p- H  ]9 ^/ L** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
5 J; W( }! q7 V3 H% N1 ~6 r  J2 Y*/
$ i. W/ f( d% S, H, I( L' ?: ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
: a7 B: `2 ?3 l2 ?7 W6 K** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
+ z1 u* b- ?. L, r* mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 H: N2 z  o8 T6 A+ NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ ]$ i: p2 f% ^) p# a! ~4 ~9 w( B3 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
( o7 w  a; z2 j' f! @$ Z6 U| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# B2 `# b; E/ m4 m6 p* TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 @$ h, r# k* y3 P2 ~7 j( d; D| MCASP_TX_CLKFAIL
7 U) ^0 c& o, r' M5 [' i| MCASP_TX_SYNCERROR
+ Y7 X( F/ J* g$ f. q, h' a| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 @4 K1 a7 q8 _| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
# d  I/ K6 T) a/ O) H}

static void I2SDataTxRxActivate(void)
{
; @9 ]% _2 o" n0 O6 i4 }/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! R7 Y4 q' U! O' |EDMA3_TRIG_MODE_EVENT);
0 D5 Z: O% [: tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 G, x! t) ?6 `" z3 T' lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
8 i/ m: O% t: }. Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
: N  H2 q( t7 g& cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) m2 ?: P# x, j6 Q; \; kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

9 [' d9 v. i2 N, q

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

& U7 C4 k7 c1 ]