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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; b+ a; e6 W( q2 W( u$ N: I
input mcasp_ahclkx,6 g" Z% K4 b9 }4 Q. J$ k- }5 z! |
input mcasp_aclkx,
' I4 u @1 n; a1 {1 Qinput axr0,. H2 L2 v: y0 C: L$ U( h ] b
, q* F2 ?5 `8 ~" I: O3 u" J. G7 Voutput mcasp_afsr,
# Z8 E% f: u1 d, aoutput mcasp_ahclkr,
) U6 }. D; _: L& l5 v7 A; @output mcasp_aclkr,. S+ }, D" {$ t" Q
output axr1,( ^3 M& ~: y, q" {6 e$ V
assign mcasp_afsr = mcasp_afsx;) L2 `4 W* f' S, [" H( n( {6 a9 @$ T, O
assign mcasp_aclkr = mcasp_aclkx;
: e& b+ g. w- V6 j/ k, [, I! Uassign mcasp_ahclkr = mcasp_ahclkx;
( c# g8 J- o7 ?assign axr1 = axr0;
3 s# o0 R9 m1 }1 A% F) l! ?5 t! ]: V+ E+ Q2 [1 Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % v8 t0 V8 r! }: X
static void McASPI2SConfigure(void)
4 k7 ~8 W' V$ w- `# |; k{
5 H8 _3 `7 E, s1 \" oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& c' q- @* q, E+ _- d5 JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 C, j& q1 M( u* x1 Z) d; A$ C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" \+ ] \: }8 J. A' m- I4 B1 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; c6 A3 ~' m$ B" n0 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& P* ~ s: W3 |
MCASP_RX_MODE_DMA);
* i& K$ J- L. K9 [2 j4 Q: [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 W) m; U7 A7 T: X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- E% p2 e+ v0 J( ~: { u, I' V1 o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 Q3 p" b* k% C, G _; wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& Q" G" K X; K. I* SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' h5 V8 T# @. U7 K* r) i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 r# J7 a4 Y. E; H T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 w: M2 B3 t6 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , o. o1 w Z+ v) r9 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 C8 w# d( | A" ]% { F
0x00, 0xFF); /* configure the clock for transmitter */: {' L6 w+ v, `3 ^1 S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- Q: d. Q, J8 j, \: |: S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 C. s- |# j9 V3 V2 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. Z% ?/ ` ~) I+ }& X3 m
0x00, 0xFF);# y. j5 W: E, c! k) _) D8 m
# J$ r" W4 Q c/ U0 Y- L7 V/* Enable synchronization of RX and TX sections */
/ x- }* S0 [: U, a) RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 U( T2 r+ z! \. {/ b9 Y. FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 J9 h4 D- ]6 B$ m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 w* T: x; C! x. k. }8 V
** Set the serializers, Currently only one serializer is set as, |% i: O. N1 h+ R% y- ^
** transmitter and one serializer as receiver.* Q) j* o. i4 S: \
*/
B1 V- P0 R, BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' u3 L" ~- g! Z$ TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 X N5 u2 e- J! H* g
** Configure the McASP pins
/ E( i; B4 ~& z5 Z% S+ Z** Input - Frame Sync, Clock and Serializer Rx
M* h" g* b; `( D3 Y** Output - Serializer Tx is connected to the input of the codec . r3 @$ s k Q D+ e1 ~
*/
/ W( f" p1 v2 f' O+ C' r- E v# cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# {$ [" r7 u* T" C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; B. m1 t5 n7 @0 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: n9 w% `" _! Y* D1 I/ ^4 @
| MCASP_PIN_ACLKX7 D0 H [, p( I- B
| MCASP_PIN_AHCLKX# B5 d: ?) l! R+ n' O" X- Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 W& z1 p4 g2 d& o" x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* K) B$ T7 O" H! d| MCASP_TX_CLKFAIL ' I0 C# g7 [- u, r: R$ e
| MCASP_TX_SYNCERROR7 \$ O0 u& Y; ~: G. M4 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: [- Y, i; P9 t7 ~8 B| MCASP_RX_CLKFAIL
0 O8 n0 `. M$ E& d2 E9 i8 M6 d8 B| MCASP_RX_SYNCERROR
5 H4 P7 \! X9 Y3 P- M/ C5 _| MCASP_RX_OVERRUN);3 F* g& ]" x1 W- [9 q6 Z
} static void I2SDataTxRxActivate(void)- {7 U2 Q) y" b# s7 c
{3 u7 X p9 c# v' J) d, [7 U) ^
/* Start the clocks */% c2 h* _, K! N8 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 W1 R# X0 O' a, xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 g6 ^( q5 {( B0 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 c2 B6 K! G, ~8 c
EDMA3_TRIG_MODE_EVENT);
$ A7 S6 p# N4 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
`+ ~6 N; l3 v& z( v+ D& ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ a/ n" o# X/ V. j! C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' ~ Q8 z, X& ~+ F4 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; B+ R# _/ H. E2 X& ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 M9 n& Z, z* W) j+ gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ o. ?* }! a: R3 k) X' U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; u$ Z8 L; j" K; h) e" v
} 8 S9 W) l6 n9 a5 }6 l5 k0 U$ f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; U" ~+ Z5 h }8 B6 ~& |3 w
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