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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ ` O! i7 o6 J( o% X
input mcasp_ahclkx,
5 i5 |+ u# l& u( Yinput mcasp_aclkx,
" Y! a b4 j, W# Z3 E# Ainput axr0,9 A& Z9 H. a2 n8 H8 g
# X/ k: \% _. e) O9 B! y- _1 A
output mcasp_afsr,2 M3 w. ~* f9 a3 i1 b: f M
output mcasp_ahclkr,! E3 W3 e' H* L( o1 A
output mcasp_aclkr,
3 N1 w1 I' ?* c% zoutput axr1,( T2 k: ` R" r& h( Y
assign mcasp_afsr = mcasp_afsx;
6 B& [# c2 C8 Z* q1 fassign mcasp_aclkr = mcasp_aclkx;
, q4 L a" b: `# xassign mcasp_ahclkr = mcasp_ahclkx;: C: V j7 s p
assign axr1 = axr0; 8 k4 y' C9 O. h f# |; `' v( O; B
5 e" _. }7 _' l" V9 u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' i9 w8 I4 l' W$ r6 C
static void McASPI2SConfigure(void)& n/ n2 P$ a/ g+ O1 E4 Z3 ]
{& G0 k# }* @2 n5 V: c! _& I
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ y7 K, k7 y& x7 w2 U6 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: o. y0 I* u* u: c" NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( ~1 G# K Z. F- S" B" O* P: j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* O! K" ?3 x1 A" {3 i" Q; P" k6 w- fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- \9 P1 q1 ]" ~; y7 i1 b
MCASP_RX_MODE_DMA);
% w: @3 R! k5 `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( L g6 T3 i- A8 J2 ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 I! \8 S/ v' p8 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; j _' z; H4 |& uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 K4 s4 z6 k! }: G1 D. A# JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 J) |: W; f" P0 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ }- e! y( S R, q% rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& s7 D3 ^ S/ W8 j$ WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# |9 s$ B5 b! f O# Z! vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 B4 d- K j8 S" f- r6 _, R0x00, 0xFF); /* configure the clock for transmitter */
( o! T i" N1 U3 m1 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 ^+ r0 s" A [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% v4 m' P, r9 N5 n. ?# UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ p: U& {1 d( d5 s8 m# z A
0x00, 0xFF);. V/ I. h) T4 S
, k* k$ M) ` Z* ~5 Y, g# C
/* Enable synchronization of RX and TX sections */
- w: _2 {0 m& T9 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" Q' T5 p( Z: `9 g1 t" z* \7 q2 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% o1 _* M7 [5 D( @' uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ v! p. Y- T' r @$ V1 R" b& R; ^** Set the serializers, Currently only one serializer is set as
- n# {( X. B% R" {! u** transmitter and one serializer as receiver." b* K, ?/ ^% m E* p4 U
*/' F. ]$ m' ?3 [1 `6 a2 a) o( y% I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 h) ?0 ?# W1 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ J$ l2 A7 T# h, i/ n& }** Configure the McASP pins ) r7 d; x2 ?. w# y- A. I
** Input - Frame Sync, Clock and Serializer Rx: S: K v- X# w% d5 B, p' o
** Output - Serializer Tx is connected to the input of the codec , Q( g1 U- @7 L
*// K0 Y' _' J$ x; p# @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 E& h/ L! \% M1 h/ w3 n' g$ K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 C- q; C, m! w. E( C' GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 a& Y+ C/ y3 P* f; x1 B, b% J| MCASP_PIN_ACLKX% ~- L9 {1 z1 \
| MCASP_PIN_AHCLKX
% W+ t; u- @# g+ {: @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ ?. ?6 Q. q* G0 a0 |2 X- xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ?' y8 N: j6 M% h/ N
| MCASP_TX_CLKFAIL
7 M/ L7 Q) y b$ Z; {6 h) `| MCASP_TX_SYNCERROR$ }8 a. n% b* M- j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ T4 P% v; t8 `' J+ X- u X2 r- r2 W
| MCASP_RX_CLKFAIL2 E8 N; m- I8 |% o- j# E* F5 {# m5 |. Y" u# Z
| MCASP_RX_SYNCERROR
6 A$ v/ I6 D# J7 r0 P9 [% A" I| MCASP_RX_OVERRUN);
6 ?8 b+ Y3 Z( w& _* n} static void I2SDataTxRxActivate(void)
3 ~8 b0 y9 M- \) l{
9 j9 G% C2 a+ [* n" d/* Start the clocks */! ]" T3 [: S# f# p5 w- n- {' `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ j! ~! d `0 X5 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* L; }/ E7 U5 ^/ l: U; V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- D+ `; q5 ~1 B9 J% x
EDMA3_TRIG_MODE_EVENT);
( m+ |* j& x7 _- t) YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - i. w6 l' _: j, x# U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
W/ O5 G4 ^% d: D9 v1 `8 YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); q+ g8 r4 _' `" S+ t4 A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# r: s I- }+ }5 A" z' [( H! X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- S, F( ~; P' j1 aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% G, [- m# w4 Q2 i- L/ Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ ?9 ^6 T$ s4 s% Y# U
}
4 l- S; {/ Z" f# I3 ^( p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # g% o6 A" W% w! W! `
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