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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: H7 |2 ^1 e% oinput mcasp_ahclkx,. M$ E2 c$ \3 w: O4 m) z# V4 K
input mcasp_aclkx,* I% e$ F- X. H2 R
input axr0,8 F' G8 M- D7 ?4 p% U- {
% l6 N; y0 Y/ m: Woutput mcasp_afsr,/ r D7 y# h/ f) E
output mcasp_ahclkr,
2 M- b0 }, L, p8 Q3 e% \4 Poutput mcasp_aclkr,1 V9 Y/ z) W/ i2 B& z
output axr1,
4 g% Y: \/ V; M t8 [" v assign mcasp_afsr = mcasp_afsx;
& y1 W7 V# q4 Passign mcasp_aclkr = mcasp_aclkx;$ E# Y( Y0 W! \( `3 C- A# j- N
assign mcasp_ahclkr = mcasp_ahclkx;
% p) B4 U* g# _& l6 s/ R$ W {) tassign axr1 = axr0; 9 a1 n8 ?! M* r8 G' k( Y
# m! k) ?1 ~5 I. F# X1 t* B- j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 F3 A) c$ F; P" C
static void McASPI2SConfigure(void)
& u* k7 t( N" A$ Q% x& _{
0 K; B- G- s: _4 l4 s O& BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ f6 T+ P' h) p( |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 M0 h0 }( N3 |8 U- s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 b% ~" u4 C5 c! XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& R2 [; d- f" ^- MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 p0 s" V* c% J' Z. LMCASP_RX_MODE_DMA);
: d( U8 i- k# I6 n6 P2 O; nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 ]# n- x9 q. e% U" j1 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 z% _/ [! x& N- D* E" yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ ~7 G% H# N$ |* ?9 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 d# @4 O9 r! j$ O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 {' t) }$ u3 H. ?; }+ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ B8 B& g* b; C7 ^" ~. ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ G5 k5 ~' y0 |( F, l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ P" N4 T+ a: u3 k; |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, ]% x* e/ A5 r* k/ K- d
0x00, 0xFF); /* configure the clock for transmitter */5 B' P6 F+ y. Y( M9 _* {. E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 d% @9 d+ Y9 w o! _: \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; D9 `6 f( J& C0 X4 m4 h$ |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, C# r/ |! O% S% D+ s, M% b
0x00, 0xFF);
/ h Y) S% j) A& b" R t2 L! b1 a" V( W9 @4 v
/* Enable synchronization of RX and TX sections */
7 S/ D% b p x$ b" U' bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 ~! {6 E: B- {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 D$ k, c+ m: G0 J% d; jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' j* x2 g' L* G% Y9 b
** Set the serializers, Currently only one serializer is set as0 |7 z, D1 l% Q% n, X1 z5 a
** transmitter and one serializer as receiver.6 i/ } z- g4 k: T
*/
, C) d; U* ^9 ]' Y' SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 }5 k7 H0 F' P) T+ b EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 p' s* q; d/ r$ e3 ]
** Configure the McASP pins
6 |: O5 b2 Q7 }) I# @6 u** Input - Frame Sync, Clock and Serializer Rx' y- B3 j$ Q: i+ g O
** Output - Serializer Tx is connected to the input of the codec
9 F+ L/ M7 n& ?" B5 ], u3 e*/7 }: X* N a; [% t* @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: _! L3 _5 @: @8 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; ]2 T% _# A# M M* f1 O# u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 A; O3 L/ x t4 z8 k0 p
| MCASP_PIN_ACLKX
& I3 X8 S4 F2 X/ \. X| MCASP_PIN_AHCLKX
1 a7 P1 M A2 l+ c, |. N- P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ Q% E% C# k/ w7 N: o$ n- DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 W/ A4 ^0 Z2 _6 {' W| MCASP_TX_CLKFAIL
: v3 V4 a% {9 d) Q$ s| MCASP_TX_SYNCERROR
# a3 t/ U3 Q/ E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ g' J0 H8 V& |0 y| MCASP_RX_CLKFAIL
' Z; b7 H1 b5 @& N| MCASP_RX_SYNCERROR
9 E6 s& u9 A5 ^, \/ V! s% [& X| MCASP_RX_OVERRUN);4 E5 O* S1 g* @% k) r$ K1 F+ y
} static void I2SDataTxRxActivate(void)
) |, R; G( [; K3 v7 B6 U{
2 c* x7 U" j1 M' o/* Start the clocks */
$ v0 E: f) D% `% a; d2 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 y. R' Z3 F0 F/ D1 J: eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 F, U" Y1 _9 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 L9 D! O6 g/ ?$ x. mEDMA3_TRIG_MODE_EVENT);6 X. ?; @9 o$ m$ @5 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 ?+ S+ N. e: H7 v9 ^+ ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 P; ?2 T' F8 h! ~# v5 |! |5 N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ |+ |. E0 g; s1 @/ ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! O9 x& s1 D% [+ K, w' ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" s/ r& U0 R7 L& M% l+ N6 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 l. u. b5 Q( e# M# d2 u9 x( GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( p$ w; j/ T" h6 o9 `4 H* W. Z* i
} 3 }9 i, _+ a$ w! d& F6 S2 {8 b2 Y- j6 a5 Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 X: m( o" |8 B. H
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