|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 A( _( P: F/ o& ]6 |
input mcasp_ahclkx,& L& o4 M% J7 d# E. o* _
input mcasp_aclkx,3 F2 W" P/ L; U7 E8 i, @
input axr0,# L0 W v- t* X0 g" \
: Q" n9 q8 V9 o, p& G
output mcasp_afsr,+ K2 ]; b/ D* {) U1 {* \% f1 {
output mcasp_ahclkr, E( B* ?2 q4 K8 R, q; S
output mcasp_aclkr,
, l% [+ \7 l+ Y, A# Soutput axr1,. N8 S8 T# J$ n5 ~8 m* n( R
assign mcasp_afsr = mcasp_afsx;( N" l/ i+ U7 v4 w+ R
assign mcasp_aclkr = mcasp_aclkx;
) s T- m% q z9 M! Eassign mcasp_ahclkr = mcasp_ahclkx;
# s' f; {6 `; I: [assign axr1 = axr0;
) `7 s4 O& V' W! D3 t! [+ N ]$ `
, D8 y# s. o+ c3 K$ f r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 c2 y+ N9 e# l! B$ [2 b
static void McASPI2SConfigure(void)6 G- ?0 x' G, A. P; j
{
9 a7 L6 b n+ Y2 f0 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# l$ ^* q6 o& v' z( K* A3 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. ~, g2 ^( i) G* o' I! B. q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. F: m" C- x6 q, s+ q3 L4 o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 d$ V; v- H! ~* U V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 }( U# C/ A1 c9 S) J8 L
MCASP_RX_MODE_DMA);
0 `! _ J# H1 L9 m& r" iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 x* _7 F/ h$ v" R+ x" UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ K5 F7 w1 {7 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. n8 O3 i( P' n+ V0 n0 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ E1 f4 F- C. f( R8 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( B7 Y- E, n$ A% n3 |# yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 u9 q7 H/ y6 N/ ]: h$ K1 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% x0 v* }! ?; u% \8 L O" R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . Z3 A8 J8 i. z6 X- u, S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 i2 q" |' Q; ], J3 S
0x00, 0xFF); /* configure the clock for transmitter */
( ~4 H% @& {# U9 h. X! m& C3 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. O" A J* H9 Y2 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* `. K2 I) A4 t% V" iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ^: w/ ?$ l" C, x* r
0x00, 0xFF);
; r( f X+ y/ _- W; S0 ^7 @. r* E2 h
/* Enable synchronization of RX and TX sections */
! }6 E" O+ `3 w+ z/ s+ K* Q* DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 t# s9 R, G EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 G% T1 Q) L3 \. \8 @5 F! c6 y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 l' b V* d# A+ N* ?& v N
** Set the serializers, Currently only one serializer is set as
8 D5 h6 A; @9 [7 L1 E) ]6 M( X** transmitter and one serializer as receiver.
6 j5 C$ K2 h5 X2 p- j& t7 T6 @*/
; y) w) |+ N6 `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ s1 u& p" T" s5 a: rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 m( F0 }" R, P- v) ~* o6 }2 Z* ]
** Configure the McASP pins ' j3 N: r/ f6 V; U! c
** Input - Frame Sync, Clock and Serializer Rx
; D# ` @0 L2 u4 [# H' d# ^" q** Output - Serializer Tx is connected to the input of the codec ' X- G$ _4 Y+ {7 K( O5 F
*/! d; v* G1 ~/ u5 {! d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" |" G. U2 s6 a% K# D3 s# n1 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
u; |2 e3 Z1 S& ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 p- K+ \, X7 _$ u+ M" S$ v
| MCASP_PIN_ACLKX
3 o: H7 B q( j( V" ], V1 i| MCASP_PIN_AHCLKX/ {. n+ v4 n) T! L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- t# K$ n9 R7 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. p) s4 G0 z# a+ a7 b+ D: R& a| MCASP_TX_CLKFAIL
" c6 Z' L* @: o4 L! {' {. j* R) g| MCASP_TX_SYNCERROR
+ p0 r8 i) k. z, K/ }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 R5 [# l1 }; Z3 Z! I" D3 ~| MCASP_RX_CLKFAIL
s- H) Q2 w" P- s/ l| MCASP_RX_SYNCERROR
" u$ k2 H& n5 N" ^- [| MCASP_RX_OVERRUN);; \( p/ Z9 H5 Y- A
} static void I2SDataTxRxActivate(void)
6 O8 R l1 `2 w6 f1 v0 Q{
( E. S# c( B2 D4 S" F! b: n/* Start the clocks */7 |- T# Z/ {( u* e0 a4 c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- v- S* ?4 v" M* N9 B2 L. P; oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( x" s/ e/ E" ^( _( k& \- W. f" V- EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. o1 H) V/ j( i6 v# y9 V% oEDMA3_TRIG_MODE_EVENT);5 O) r* s3 v0 p. h. F- j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* h Y* D, C+ u* _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* }( W" \6 b# rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" z- v/ |" q* h; y& `) xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: e/ Y; }6 {: X6 W/ dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ _4 F# M! n8 x; B5 z8 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 \8 y# F7 E7 g' o, P6 W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
Y' x3 k1 i; N- U/ E" V0 b, m} 5 U0 s) s8 C& N1 J4 l: t, f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) b9 A/ f7 i" f# u; R
|