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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) d }1 l) [5 J) m$ q5 Q
input mcasp_ahclkx,
i1 C, w8 n; Q" p% o! n8 Tinput mcasp_aclkx,' M2 y- g) U. x9 K9 M6 |! r2 x: o
input axr0,
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& b) u6 r; H+ K- E* c$ q Goutput mcasp_afsr,1 f6 J. L- L) `' @
output mcasp_ahclkr,3 G0 h! p0 j! w, V, b$ ~( h4 e
output mcasp_aclkr,' y/ \, |* d4 ^2 x7 o ]8 F
output axr1,
' u0 ^$ p( ^/ E! O assign mcasp_afsr = mcasp_afsx;
- h: ~; O# a3 _( xassign mcasp_aclkr = mcasp_aclkx;, @6 l" w8 K5 X* r! t9 }5 K
assign mcasp_ahclkr = mcasp_ahclkx;; s: X# K n7 O0 b# s) c; E
assign axr1 = axr0; ' O- z: A4 }3 A e* \" K' T+ y
& V3 ~0 l* Y" w; w( h4 V6 L; Q# P. I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 s) u) H' k, g: z% u0 H- w9 _static void McASPI2SConfigure(void)
0 _. @8 R( w" z6 ^$ h{
- S# ^4 q/ S' @6 D& w/ [4 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ \/ F& P+ i4 Q4 k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ G, Q) x& U, I0 y) w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; ~* b3 i* n, A( Z1 |* s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( o% S7 U2 j' s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, L1 @8 R' o. c# h# u& E# p5 @MCASP_RX_MODE_DMA);
$ L- g* ]5 ]% S4 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Y) e. z/ i8 m8 Q. I$ SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, _# d D6 K: e8 E! A) MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' c4 x$ y! y, _" o( Z6 S/ S+ n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) V6 d1 ` C9 O5 l. u- X+ P$ X/ V; C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 p T4 O$ B- ~9 ~0 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ o8 e4 G; d3 U; VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 y" `; F3 z2 D# z3 ]/ C+ @$ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& c5 ~) V9 Y! U. W- [1 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, s2 _3 V8 c( Q4 e2 [* q0x00, 0xFF); /* configure the clock for transmitter */& Y/ c6 F. u, `0 X- b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ L: ^4 x# g9 H- j3 @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& l: W1 ^1 M$ r1 i! w9 G8 Y1 S) P9 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; ?" G& a5 N+ {( w2 s0x00, 0xFF);
, y4 T! x, Q+ z9 v# Q0 w
4 r; A( m. b5 R9 Q! H/* Enable synchronization of RX and TX sections */
) ^' w! a, r. N# w: tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* Q+ |" I8 D5 t C' t0 U ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% v" Y) G; F" @; r7 ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# R7 B' Y0 ~' k T** Set the serializers, Currently only one serializer is set as/ J3 O- e0 c9 ]& _
** transmitter and one serializer as receiver.
9 m6 T5 F4 J# f/ H; H% O2 a- e*/: f& p7 w- f0 ^0 i% p5 l( l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 X) j* F: z* p; @3 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 H/ b. a, q9 Q& g
** Configure the McASP pins 6 ~' L A9 `8 M0 X8 P! V- _
** Input - Frame Sync, Clock and Serializer Rx
" F- V+ P$ ?) U( \9 a# A** Output - Serializer Tx is connected to the input of the codec
! p% R. x7 N3 W7 ?% e. U3 V+ {* u*/" E2 x" k3 C0 L6 M4 }' P, [7 J& q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: w' T" @2 ~; q1 ]8 z7 _4 B8 L' ^) }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; F/ \$ r' _6 X# hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: {% Q$ Y+ X- D" y# t8 G4 k
| MCASP_PIN_ACLKX: `4 L4 t" M+ f! ^
| MCASP_PIN_AHCLKX" N6 ~' X1 M8 {+ `6 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 T: f% g# N3 S, H0 M- R0 `6 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ [, H) f( ^% r6 N5 ]| MCASP_TX_CLKFAIL
5 y- }7 y! B! |4 ?6 H" H5 \| MCASP_TX_SYNCERROR
% x9 |& f) f# w- l4 R" f3 \. [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- y- B* I7 ]1 K( O| MCASP_RX_CLKFAIL
6 }- Q, T4 m" ]* |7 T| MCASP_RX_SYNCERROR
+ Y* f( f4 Y9 a* x1 a| MCASP_RX_OVERRUN);
. g0 ~8 D2 p1 C. J$ W} static void I2SDataTxRxActivate(void)
" _. g1 C+ X" ]8 b. \; H{
) x0 v0 t+ C" H/ k# x: ~8 {/* Start the clocks */
) |# b2 l" N! a- J9 Q* _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 s$ E' u( l: {1 U7 ^. f% v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 q0 z- z4 e* j$ a. uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 ~7 ^; u7 P6 h S: v' ^* C) _- @/ a$ j% t
EDMA3_TRIG_MODE_EVENT);
, q- b/ ]& x7 @8 \! YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ T3 m2 g7 l+ I9 V; uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; a9 t& T( j" {& m H* b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ \2 W9 q$ N# v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ `; ~0 L! r2 K f0 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& h# a9 a( }( \4 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 i+ s. H4 `4 W- y) P" eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& f! p7 W' d4 Z Z
} & ~( l( }+ v; G, P f6 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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