MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
6 `/ |& s) E  Linput mcasp_ahclkx,
, q) f# z' w5 M/ V: vinput mcasp_aclkx,
. N# M* Z4 {% U; Cinput axr0,
# f6 @3 U2 B4 _& A5 c: K
output mcasp_afsr,
( M& o6 u8 m! aoutput mcasp_ahclkr,
. }3 g/ D- h; C5 @3 m! coutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
* S2 b' L$ k2 q, Q1 Nassign mcasp_ahclkr = mcasp_ahclkx;
  e; ]% q- B6 I6 Y9 t5 gassign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
0 A% b: A$ R7 `$ l2 `{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. ]3 t7 Y, U2 F1 Y3 _McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
- {/ W5 G* E! ^$ `! S' jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 Z* a$ w. R0 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
( h9 I; z5 {( X7 W) GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ M! z# ?& X0 O9 H& VMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, ?) f+ _) C9 @/ c. ]1 tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
5 E8 s6 w/ m9 m% z  dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 c0 ~6 t. u# c) wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ?! k' \$ W# R9 N0 q5 @* JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
7 ]6 K- F8 X' T1 Q, S8 H4 n* i, FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% Y. ~# Y- p# T2 F" w, q* ?) yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. C- K" }; e2 q0x00, 0xFF);

3 R' a) J5 C) w% U$ [: g/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* {/ G+ i- `* A3 B# E  Q* |) |, KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
* [2 {) Q5 x, `+ Z7 G  `** Set the serializers, Currently only one serializer is set as
7 m) j: A/ I9 K** transmitter and one serializer as receiver.
1 j: h- T4 t, U( r# @) v*/
6 y+ L$ u% T+ b; jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# V/ b' S7 h1 J6 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
6 g0 k: _4 v3 Q: _** Output - Serializer Tx is connected to the input of the codec
( @! c" S# D6 Z2 k* y% O3 L*/
- p- {# E: F! L* QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ u# b# S; S* c: \+ \# PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, S( Z/ H4 i7 x; _  lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
6 M1 S- N, K. E/ _2 l8 A2 {/ d| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
0 b5 h: |1 A4 L2 y! T! r| MCASP_TX_SYNCERROR
5 e: X" Z" _% _$ E4 J| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 q) ?3 y* t" A7 K& k| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
! f+ g6 d/ u4 ~8 F8 E, [/* Start the clocks */
( R2 u( v# z) G) G0 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  k! t5 \8 j$ i; n1 s) S/ jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
! [8 x( S2 b! g( e9 a, e* OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
# d: i/ S+ f6 E4 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 s: ^0 ~1 c0 g" EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* ?1 i4 Y& `# d, WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

- v1 \7 }! m/ n  W3 V3 D

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.