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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 b0 U' I; ~) R0 qinput mcasp_ahclkx,
! [! P, R5 Z1 M; |- Dinput mcasp_aclkx,: v$ u0 h- ~' C& u
input axr0,
" x3 c2 T' r7 V% k# u- x0 E% G( H" x# V4 {, g/ D. d
output mcasp_afsr,, K: M1 Q: G+ h" U1 }$ c; M3 J
output mcasp_ahclkr, a7 ^& F6 ^' W8 ~8 K0 r5 s9 J
output mcasp_aclkr,
0 M0 a% G, Z' N+ M: poutput axr1,
( k4 ~" q; H; r5 Z assign mcasp_afsr = mcasp_afsx;
7 r% t) E2 L- t' @- V% T" Fassign mcasp_aclkr = mcasp_aclkx;
- x3 J% X0 N' ]' J2 i% t* Tassign mcasp_ahclkr = mcasp_ahclkx;
9 O4 R+ Q9 D" m0 p" uassign axr1 = axr0;
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/ j* ]7 q. K! P& P0 j4 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 {2 M' L% `1 @
static void McASPI2SConfigure(void)
+ a6 Q- ]+ j9 I% n{ c8 `; H1 c% y8 o9 y* _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% d4 _$ E0 y/ r) ]( M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. v' f, y' r3 U. ^% HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 J. R8 }# S3 e( H }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" `0 f# F- e7 y% t$ E. w2 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( v `2 I7 u& q4 O) h! E
MCASP_RX_MODE_DMA);- B% s6 I" Z6 e% g
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ B' l( z/ C6 P& \+ QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' e; C! q2 _( q/ {4 [+ x" UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" O1 Z( ?9 Q7 b2 |! f! q# HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 ]: d) [+ T# b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % t+ u& m! ^5 d1 b/ V+ r; h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- A g3 P) B9 r& [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* K. s4 {( w H8 g5 x' p. l1 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 F, [3 C0 d* z; H; H/ {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 q% z4 E/ v/ h$ \; N5 d# B0x00, 0xFF); /* configure the clock for transmitter */1 H( T1 T4 h: s- u( ?3 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- V1 _; B) K; B) S8 {4 a e$ Y1 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: z5 j/ @7 Y+ ]# v3 ]- A" v! ]( ^* bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 j% M9 F& C7 S' K$ M' g
0x00, 0xFF);
* K0 r: h: c' y b- R5 g3 ]* I' q E# ^
/* Enable synchronization of RX and TX sections */ " b% D+ Q0 m" B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* Z2 Z# I- z" s$ ?8 c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* n2 T- G- ]8 p" D/ E- F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; M7 x3 Q' C/ {9 n4 x' X: G! b
** Set the serializers, Currently only one serializer is set as
v( w3 d7 E" [** transmitter and one serializer as receiver.* Z' I7 S% U; t
*/& g( @% L) S- `; j2 r; _& Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) r2 v8 P c, I yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% W. q% i. \1 a# s1 ^
** Configure the McASP pins
9 d# V' { R+ y1 K** Input - Frame Sync, Clock and Serializer Rx& s9 R# L/ j# `4 Y" T% u
** Output - Serializer Tx is connected to the input of the codec
, @/ x& N7 r7 [% a*/8 f4 w# n3 Z1 Y, y, p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" u1 ]3 ^. M' i' L4 F4 {9 A+ aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, `9 |. c6 Z+ S# P/ Y# G+ a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
K! v8 g- Y% D. M6 I/ Q2 c| MCASP_PIN_ACLKX7 I H7 u+ ]/ i1 O/ B2 \3 R
| MCASP_PIN_AHCLKX% d. t2 n$ e3 v5 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' [% s# `; ]; J5 F. K, C+ W% jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # y' p& S; w+ T- \
| MCASP_TX_CLKFAIL
) Y# G: H; Z5 B# E$ _% ] N# A8 ^| MCASP_TX_SYNCERROR8 R, i+ n- W+ S3 ^2 G* z5 W/ q7 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' e0 ^; Q, i4 A
| MCASP_RX_CLKFAIL
; |" L* d3 {4 B4 G| MCASP_RX_SYNCERROR
+ p4 @7 t3 Y% b| MCASP_RX_OVERRUN);9 s" V! o0 Q$ ~' \2 S3 {
} static void I2SDataTxRxActivate(void): K5 v. T' o8 T' @) W
{
2 a s* G H( L& f* j/* Start the clocks */" A+ J" n0 I; _+ B( J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 \4 q9 }. q6 v' E- Z3 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 f! x$ j2 J+ I, U% O. n. _" GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
E" \; P* [) k* B2 P+ CEDMA3_TRIG_MODE_EVENT);
" G( C; ?% m C+ Q ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 ]4 j- F* v# h) m3 v$ BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" ]3 q( Z/ D- S7 v/ q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 D; ?. I' `3 ~9 d" f' T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 |/ a1 i/ k) h) J7 B6 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) l6 Q: M% v- Q$ d& V) A. ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 y5 g' e4 k/ W# U3 P; `" S0 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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