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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 M0 z8 g% I1 D* d0 d2 m4 }input mcasp_ahclkx,
0 j) J6 \# E& |: Y; rinput mcasp_aclkx,
" I( d' o4 r! \' i2 Q4 Sinput axr0,
- [. Z% E0 Q) k% z
( I. Y* o* ?7 P1 {7 |# L Koutput mcasp_afsr,
: A" s5 [8 e6 M/ L9 P Voutput mcasp_ahclkr,
% T) ]# M8 Q/ i* [% voutput mcasp_aclkr,3 H" G6 b! B/ l1 e- x. B4 V
output axr1,
6 K: |/ M3 g+ n2 `2 ]$ { assign mcasp_afsr = mcasp_afsx;
6 X4 W+ @/ T& B0 N8 h9 iassign mcasp_aclkr = mcasp_aclkx;
' Y7 q8 `, V- W" massign mcasp_ahclkr = mcasp_ahclkx;4 m7 G5 | R* M
assign axr1 = axr0;
! B3 B: H+ Y0 A+ x* z: @ n' O
5 \* j1 M0 h( }/ h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! [6 ~* ^4 s# d: k$ T5 ~$ R
static void McASPI2SConfigure(void)
6 `4 T+ W$ y- `{; g: r: P( ]& u5 s0 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: k1 ~1 ?1 _* U7 {5 \: PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, q! ~: W7 `+ S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ u+ M2 i L3 s6 `& U5 j) K: J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 t" y# F( l) b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 r, Y1 c9 z% l' t2 x% L4 [; tMCASP_RX_MODE_DMA);
$ T& `7 z9 |* F( a1 `0 M L, c4 w. QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; T2 `$ U* ?! RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ~4 h) W' Y, AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * k: D( ]8 N8 b- K+ q* {) I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 G% \- p2 w5 T0 K0 u( N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 i" f8 _$ X. f; P- U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. Y1 p1 Z x, T+ m, j) ^7 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- a4 O/ y3 L$ C( m8 g4 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Q' g) G: ^: \+ h1 R5 E IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 [6 i& Z* z" \% w
0x00, 0xFF); /* configure the clock for transmitter */
- i2 G. x( s( A r% T# ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" K3 a4 ?6 v( m, [* H( k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - q [8 z5 D: W0 U. _- X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* ^3 Z2 R8 S. g# m0x00, 0xFF);
/ K. B- \9 l& e/ i% j
8 ^4 W& n' T) Q/* Enable synchronization of RX and TX sections */
1 I+ r9 J5 T* S6 L" qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ x% l1 F: l+ {, ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; u6 `/ {0 l5 A, B* \* {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 a. w% ^7 S% E** Set the serializers, Currently only one serializer is set as7 @6 h0 M& o. T( M/ A- ~
** transmitter and one serializer as receiver.) j t; r2 H9 w1 j* o
*/
- s; B. [# }3 {( F$ ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 T$ l$ N; y" g v( g% Z! iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' o% k) F$ E; D# E' a) H* H) q& V" e** Configure the McASP pins
" _2 v/ }* D2 \# f0 t( A** Input - Frame Sync, Clock and Serializer Rx) ^4 z6 Y% c, }) }- b9 N
** Output - Serializer Tx is connected to the input of the codec
( @ u9 t$ O( ]7 \; d*/: [$ q7 f; h% T2 `8 y X7 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, O7 H9 O m, y$ u1 X) j% SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 s' e3 E1 G% I# DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( e9 M" a' _6 O/ k| MCASP_PIN_ACLKX# Q5 G( I9 K' b; h; B6 W9 I
| MCASP_PIN_AHCLKX/ J+ K1 |" {1 O8 c( A& l \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; f% B9 q& P0 t8 G. N: r! MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& V% l* c9 Z9 _0 q& o" b| MCASP_TX_CLKFAIL
$ k9 ]/ v* i }- u* Q0 ]/ k, T( G, || MCASP_TX_SYNCERROR! l+ X" y9 @0 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " o* p3 B0 z6 Z$ ?
| MCASP_RX_CLKFAIL
( ?# Y5 E8 ]' _. M Q* C| MCASP_RX_SYNCERROR
4 w. H7 d, S X$ y' p( X| MCASP_RX_OVERRUN);
, e5 C/ I% h3 X2 b9 U6 ]; \0 s} static void I2SDataTxRxActivate(void)
" Y, h# E8 x0 I! a{; X: Z ?1 k* `
/* Start the clocks */0 {: l4 J: R( q- W* w+ h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& e% c+ c. X0 `% Z, j; j- [9 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 L k# x4 a- ^' E% ^( q5 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 y- Q6 |6 I' a" _8 _# A( s x
EDMA3_TRIG_MODE_EVENT);+ @& y5 y$ d% b0 i2 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; a) p5 A, y q# w. x; xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ d1 V) k1 B1 E V3 P# ?4 ]" |: Z" B yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 O* m; \8 d8 N. \. F; @* ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 k( _! J4 {* M+ V+ e( a4 |$ M) ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 n8 T3 I) s( N% ~$ @1 f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' }$ I( r' T. T9 K& b" Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 B( h9 I: r5 M( `4 v
}
5 I2 L& |& j! ~0 t. ]6 P- n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * E, p; X+ h8 S3 f
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