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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 e- [1 ?: X5 y5 x# f0 L
input mcasp_ahclkx,% @& x' X" M' B/ X+ S, q
input mcasp_aclkx,5 l- G, i. C( y9 g1 D
input axr0,: ]3 Y" t) Y) x% J( _
7 @. K2 s4 j! \$ x7 foutput mcasp_afsr,
( k- i; @4 _) ]% Loutput mcasp_ahclkr,
- _5 b7 Y. j1 Q) k. q) z# Noutput mcasp_aclkr,
2 E" g# u) h$ p; K: F& poutput axr1,; _, H. g( ], u( E
assign mcasp_afsr = mcasp_afsx;
; P. m* o: B2 n. V3 ~( vassign mcasp_aclkr = mcasp_aclkx;
6 E5 O+ E- Z) t2 O8 v3 Passign mcasp_ahclkr = mcasp_ahclkx;; H2 {/ u& ?1 Y) v
assign axr1 = axr0;
3 M: I% l" y! s4 H2 t
4 W' J% u3 \3 g7 U) S; _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / G# a! ^# _8 r. X4 M
static void McASPI2SConfigure(void)
' T& a! \# S c; ?{3 r& ~. c, y* g! Y. P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! t/ x! ^! q( n; y' j0 _7 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 J3 B; J) z P, ^2 P' S1 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; K7 |5 \& U$ C* a+ f3 u; J9 D! {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: W" S2 H; Q2 \1 q5 c. b# }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 \7 D8 i# z q1 n% p$ [- c, ^
MCASP_RX_MODE_DMA);/ m% x7 R- H' D6 k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Y0 n/ j' Z s( FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: M" k$ e& I$ @* u3 j3 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ a7 x7 R/ Q* n# ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 Z# n! Z$ o$ z& s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' X; w G( x# v, EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ K0 Z! p' F$ F% O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* t" E4 q& Z# h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: @2 a; G# i& J- v, _- [" NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 a- T: x% X1 I+ s+ B* ?
0x00, 0xFF); /* configure the clock for transmitter */
0 M% P3 H' K9 V% K; EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! O" D! x) }* |+ O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& K" Q d# P9 u4 _* t' hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 p- M; B7 ^$ g" `6 I- i3 ~
0x00, 0xFF);
; ]0 D' n% a- P6 V( j! j) T8 @& @
/* Enable synchronization of RX and TX sections */
, b& B# j d z1 wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" |3 C; k# V9 g) A1 u5 ^: R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& d8 s0 r+ \9 D" _ G2 _: |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ `* P4 l$ k( P( P** Set the serializers, Currently only one serializer is set as
7 r( E, ?7 w: p2 r" r2 ~** transmitter and one serializer as receiver.
/ f& w7 i* I' Y/ W/ G*/! @# c4 m0 B2 B; ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) v6 [+ V! t( ?- W J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 Z2 ^- u5 [9 q( [8 D: o9 e
** Configure the McASP pins 1 z8 y/ |+ @* D
** Input - Frame Sync, Clock and Serializer Rx
$ N; [% m* Q) n** Output - Serializer Tx is connected to the input of the codec 1 e9 G* O& [/ d' ], G, x: B
*/
; w- M8 j0 o0 k9 [7 N* }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ a4 q! W5 c8 j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 C. p, C- c+ _7 S- f5 H, z# FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& o# t1 }+ `5 A( [9 r; n| MCASP_PIN_ACLKX8 _" z; I8 L2 h7 e* _0 m0 `; ~
| MCASP_PIN_AHCLKX. ~6 b& l( I/ i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ R7 C4 f: q' {: j% mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . I3 l/ @: ?/ _6 V
| MCASP_TX_CLKFAIL
) V: P5 P2 Y4 N+ S* z9 Z| MCASP_TX_SYNCERROR
) L2 k! E! @# I0 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" V; `9 ]. B+ J2 V! ~% T| MCASP_RX_CLKFAIL
! D1 E" h9 L9 q |) C+ ~* _( B| MCASP_RX_SYNCERROR
; b- W- @0 @5 j% ]4 O, r| MCASP_RX_OVERRUN);. N: d) s' E! J7 T+ g. n
} static void I2SDataTxRxActivate(void)
4 q% t: z( ^/ s l" r* I, I% t% T# t{2 o$ v) T5 ?* d* m3 w, T. x
/* Start the clocks */6 C. w' K9 a* r' u( Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 ?$ C+ x/ C4 X) R1 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 ~. F! T$ V/ O, v |% ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 F% I% d7 v, T, q6 @EDMA3_TRIG_MODE_EVENT);
- }% l) O1 J q9 O1 I( U0 H! |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 e5 h& w; ^* r7 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& z) f$ b- e# e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# B' {' L0 E+ z) i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 b' R% G5 P: L; j$ | e ?; c3 Q; R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' v0 d. R+ q2 I5 e6 e2 r! }: d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ W( \" x* ^5 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* A$ L- C4 Q6 b/ l- E3 ~& v} 5 E9 ^$ F7 _/ m X; y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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