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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. ?* H! G/ ^9 e3 ?# Y7 U$ \; Ninput mcasp_ahclkx,
6 O4 f3 Q# [8 }% Q$ @& Winput mcasp_aclkx,
; W4 a$ K3 e, J3 X: A( J5 Cinput axr0,
* f; B9 ]" A T5 }& _2 W
: |) D: h% D3 m1 Koutput mcasp_afsr,3 f# d8 g2 `" i% Y, _/ g
output mcasp_ahclkr,) k& k7 ^3 T$ L% c% |9 g. m
output mcasp_aclkr,4 ?9 s2 A9 `: ?
output axr1,
! i7 f5 o& T/ ^& E6 V2 G) o assign mcasp_afsr = mcasp_afsx;0 E% s! C1 a) Q- k3 B. E
assign mcasp_aclkr = mcasp_aclkx;
4 @; N6 G$ o& A+ u" ]& \- F3 ^8 Fassign mcasp_ahclkr = mcasp_ahclkx;
5 }6 O/ \" o' g6 M0 Bassign axr1 = axr0; 9 z/ h0 o/ R5 A. `$ M4 a( X, o" |1 `
6 ]1 i5 V) d( O7 }) s& {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * H' n, B) Z9 B
static void McASPI2SConfigure(void)3 B Y+ V' Q- {
{
% X1 X4 I- A2 Z& T. L1 b* F$ GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( y& ~1 Y- O/ y9 QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! R0 Y) v t- j3 n9 Q; t( bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( Q) f1 l* K( h8 f: s: @, g; nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# U3 P/ ?3 C _' R. v z `+ HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 G- d0 A$ G. v7 i( o/ _; uMCASP_RX_MODE_DMA);# {# T$ D7 V/ y; w' k1 U6 ~: O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' t; H0 ]' k! t4 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ u" ~- B7 D4 A. Q& i: vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 v' R; L0 z( @- p0 EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" X" |* s% w/ ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " V. a* g% N' N" h( V5 v9 t( N9 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 v6 ?. B) Z5 {3 `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 L1 l8 J& L; n7 K8 x& {% w, e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" o' A) b- W' i* T" k! hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) z5 w# D4 _/ a2 j9 m2 @5 {0x00, 0xFF); /* configure the clock for transmitter *// ]& n W5 P3 M5 x: i+ @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 p# n0 E6 s$ O8 G( ~ _# K' h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( p1 N5 Y. |* w) a7 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) c( e' q& `1 _8 P3 h, v8 s
0x00, 0xFF);
} J+ y/ A+ r! v6 c; B! L. c8 v! J' ^7 N
/* Enable synchronization of RX and TX sections */
3 Z1 h3 m4 j% v0 w2 n; y. K8 `% YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) v4 @% R# h" N, Z8 t+ s. r- X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ u( t" P ~! Z' x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ p7 \+ _) D9 ~% ~# J** Set the serializers, Currently only one serializer is set as% B: {) o" ]9 X7 l
** transmitter and one serializer as receiver.# G; n U! \3 s$ D( F- l
*/
* G; T% ?. v' VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) G* ?, t) U6 J" p( E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- H; n" x- {" `. Y( i** Configure the McASP pins : W( y% G, `1 ` {5 H
** Input - Frame Sync, Clock and Serializer Rx. F* B. o- J& u& O. Y0 m, e
** Output - Serializer Tx is connected to the input of the codec 3 i# z; I4 `+ G3 e3 G7 R8 {& A8 U
*/
; a& ^8 D5 u1 _! A( b: d6 b: NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; H3 h4 q+ Q1 z$ |' j, T* p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 T# e0 L1 K! j2 }- JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 W/ W* z- Y+ I* j' W' I6 u) O| MCASP_PIN_ACLKX
, R4 B$ ?' P& g4 V| MCASP_PIN_AHCLKX
/ f% I4 M: c! T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; J! W1 Z9 z ~$ kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& R( ~# T# g- L8 h( H% R| MCASP_TX_CLKFAIL # K; m8 g$ ~3 k9 p4 I/ B* W
| MCASP_TX_SYNCERROR5 w4 _/ u' Q5 W% @* o3 Y+ y! V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 F1 G2 R$ T8 `; U* L7 ~( }$ _| MCASP_RX_CLKFAIL
@: r: |2 G" W4 e( P) c| MCASP_RX_SYNCERROR
; s6 g* x+ |8 o1 {5 g5 h; Y| MCASP_RX_OVERRUN);
; S1 W3 O! S& {} static void I2SDataTxRxActivate(void)2 z7 V1 J/ W; e. i4 ` S3 K
{
' y p4 e/ y$ Z, d+ G& p0 x8 E/* Start the clocks */
8 [: ~, X2 @( H0 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- G. |9 ?6 c" oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 l& E2 A% @/ K/ i3 J m% [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( J! C1 v. l( V- q
EDMA3_TRIG_MODE_EVENT);
0 x1 a% ?/ M" L; M0 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # M$ F0 d$ q" \+ b. y# E' j B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 i- Q1 U1 r! T% |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) F2 d/ `! A0 q BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 a! [' V% D. y, u( @4 k" \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 d3 K0 R$ u& }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, C3 W6 Q1 ?5 `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- V. |! B# d- m9 {$ W& ]" {3 c* V}
* s* W! m4 N$ m D% n9 r: B9 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
k' k B' T! N- K* `* C' Y |