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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; J; Y" B' T/ a0 C
input mcasp_ahclkx,
3 `& c$ J% i$ Ninput mcasp_aclkx,
8 v9 g+ p7 \ O: uinput axr0,
, N; m9 Q9 @" V9 u0 c( M0 S- z" ]
output mcasp_afsr,0 ] M' A7 U0 M: N' Y u
output mcasp_ahclkr,; z' U: |( I7 ^/ O! V9 L- J! W9 F
output mcasp_aclkr,* g/ S- L+ y# o0 v2 g; v6 G
output axr1,
5 k7 D0 j$ S6 P7 s9 b- O assign mcasp_afsr = mcasp_afsx;8 v+ d9 z+ X, p0 n
assign mcasp_aclkr = mcasp_aclkx; `( ^, c5 z: u9 Z
assign mcasp_ahclkr = mcasp_ahclkx;
/ g; V( W( {* ]# N, R6 v# cassign axr1 = axr0; ' s! i# t/ Y- E5 O/ u8 R' k$ J7 K- i0 V
! o7 s6 ^- Y. i- f3 i' L; O* {9 ?+ `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 y* r, _7 L+ B [: c4 E. [5 W) S6 l
static void McASPI2SConfigure(void)
7 T# E, f# q5 X% \* j{
3 _% `) \/ [4 r& F/ UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* O# |/ F1 I4 c+ Y: PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( a* A6 r2 q: L( X. vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ |- S$ s" W- M% S& C. U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 o$ L+ n7 i. B! ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 h6 Q, ?9 A2 d6 R. J
MCASP_RX_MODE_DMA);# x( h, C! H. T' i$ E0 M) S! B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' P: h! r7 f9 x3 B4 G; [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ Z0 a& l$ z/ r9 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* p4 E( q( d2 S; V1 J- j7 P" JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 \5 N+ v, F2 V } f% |+ X! bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 ~2 @ @2 S4 Q" }9 W( gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 c; U2 W N* ?7 I5 J4 Z- K1 R( \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ ?! q$ _7 R+ D9 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ F7 Z" U P8 k. e! D, u0 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, \5 k( s; l: {2 o2 p! B
0x00, 0xFF); /* configure the clock for transmitter */
. ]' g( v; T1 a" n. G; S/ v5 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 \" Z; I, e( N; G4 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 o9 l" \4 w+ l" J, lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 C' ?4 w2 h2 B, K7 U1 f( x
0x00, 0xFF);5 l6 s3 E. j& a2 W
8 k% X) c1 Y! s$ x- U
/* Enable synchronization of RX and TX sections */
& r: f( e6 U4 M$ K/ s8 {( Q! w3 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# c2 G; W$ `* ~0 D2 [. SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. |2 ?& z# o( OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** ?& D; L7 {. X1 i* f6 h/ Y
** Set the serializers, Currently only one serializer is set as
+ _) ?3 }# ~ F F) d! q* u' o4 M** transmitter and one serializer as receiver.
/ j6 }5 m" k, G*// v* h1 z- B' N# d( g% V7 o; _0 t4 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! w! _; Y- j3 H0 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ Y j$ r3 E# ]( D5 b1 j
** Configure the McASP pins " z3 u, \: q- R. C
** Input - Frame Sync, Clock and Serializer Rx
* k) p4 _* v4 o- H8 u** Output - Serializer Tx is connected to the input of the codec * z4 }0 V$ \& f/ S
*/
6 \$ Y. M2 k7 ~ _5 ~! D. @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% G8 X: s7 F4 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& z0 c9 R* J: g, U( y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 ]7 T N. s$ l% m! ]
| MCASP_PIN_ACLKX `4 k- J' k- J T# P) n
| MCASP_PIN_AHCLKX7 R4 v3 o. y% M% O' h% [' Z/ N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( p+ I, l5 X8 V$ x9 W/ d& Z; c, yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + W ?9 q$ T4 i1 a- G1 }8 ?
| MCASP_TX_CLKFAIL
?% t, v/ W/ V9 S6 k E* p! S| MCASP_TX_SYNCERROR
% P2 _% ?% R1 s5 m& G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 j. B8 P7 x# a: c7 Y- v8 W
| MCASP_RX_CLKFAIL% T0 r; q! q8 [" S" L4 x
| MCASP_RX_SYNCERROR
' q; i, C+ g. ^$ ~. j| MCASP_RX_OVERRUN);' X5 F; W* x; ]: P: Y8 e' k5 P
} static void I2SDataTxRxActivate(void)* f, W, I2 A* I: K/ d6 A# \+ T
{
, \: d% L, i o/* Start the clocks */2 M4 M( t6 s' C7 J' W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( `# U( g- p: x, @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 W8 b- z& U; ]: [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 W, i2 ]2 f# T5 W" T5 NEDMA3_TRIG_MODE_EVENT);% [8 ]+ e7 m* C* O3 T$ M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- ?3 l0 @/ |% y1 M& z5 C! PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 }7 j$ H2 V/ M1 N& LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' E6 Q: a0 }* m6 d8 X" E+ E' n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 j3 y m# j P ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( P$ \5 s8 {* l5 |6 L% |0 W2 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 e% }! @5 P! |( RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% }$ j* \4 P4 W H- X8 {3 ^
} / ~' m) p6 O2 N( R- o. A7 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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