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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ r. v3 @. a) A9 o+ v8 G# B
input mcasp_ahclkx,3 r1 L8 y4 E9 s' u
input mcasp_aclkx,3 e* t$ ^$ O8 Q* G8 l: `3 V9 Z
input axr0,$ u0 |* X! { \
1 I( t! |/ S0 _, B' C! q( woutput mcasp_afsr,
! p7 Z/ o+ Q7 uoutput mcasp_ahclkr,
% c) v* i' V' f$ b0 T2 Q* Woutput mcasp_aclkr,
7 X) }/ A9 u9 E% w$ K9 coutput axr1,
- n4 g( X: v/ a0 N6 } assign mcasp_afsr = mcasp_afsx;
9 x* R$ ]& Z# @5 l7 l% P" |assign mcasp_aclkr = mcasp_aclkx;
- J. C( F1 o$ ]assign mcasp_ahclkr = mcasp_ahclkx;; @" e8 i9 G% r! h! ?% n
assign axr1 = axr0;
8 r. R/ a! J+ p% Z Z; H4 a- R. L1 N5 Q1 L5 {- p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 d& c& G- Z- L
static void McASPI2SConfigure(void)6 P: F+ O1 p6 V6 x& w
{
& o3 c0 q7 U: IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 y; q! V7 `- S3 T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; f1 E% q6 b4 X; i5 u$ H; ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ I; W% X- O+ m/ E" Z7 b! Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ I, P, t+ r0 B2 `& {! J& eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" M* W2 Z7 `6 h* MMCASP_RX_MODE_DMA);6 L% v% U X: J: Y/ ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; K, p5 B; X7 _9 c. E- W pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! b) k3 a: T0 y! g0 v: {9 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 j/ m3 S: y: i' n6 t$ c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- |- L1 G, r P4 L, ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! e! }+ D5 P" k; z; [0 |6 Z2 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 {3 ~9 k* A1 z+ V1 D6 rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 ] l8 R% t8 qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. S1 I% f& g8 o$ d8 sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 I1 E5 e6 H/ t% N0x00, 0xFF); /* configure the clock for transmitter */
2 b0 `: s* b2 J# E9 j& G. y# r7 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ g, |- ]8 j) n* L# WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 K' n/ s# |) _& R& U# IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; L- Y, v' X ?0x00, 0xFF);
N, O2 a- t" _4 V: p9 [9 g5 Z( q0 Z) q
/* Enable synchronization of RX and TX sections */ : Y0 l3 r4 F6 X2 D( Q( L! |" N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! T) l1 j2 D ?7 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
m4 @' g# B: W% V5 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 _ b" k' S( @0 |7 F4 T7 h% g** Set the serializers, Currently only one serializer is set as4 J+ @. j7 d- N; P& r- j& v
** transmitter and one serializer as receiver.
, Y( H+ l6 Q$ {*/5 P- i" f9 [. ]! m) P% H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* @2 ]+ h# Z0 `8 v9 b$ V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 j! l$ e, L8 z) q5 N** Configure the McASP pins 1 F% X% I' m! M7 O
** Input - Frame Sync, Clock and Serializer Rx# @6 ^7 q2 B4 c* k" x
** Output - Serializer Tx is connected to the input of the codec
$ d) x! d% ^2 u9 d$ o*/
. ?- M: ?$ }# ~$ X! vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ `+ j: Z( k R' N5 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 ~# T* A. i R8 YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, \, Y' Z: W, q2 N
| MCASP_PIN_ACLKX8 E$ D) T3 f4 C! L+ i
| MCASP_PIN_AHCLKX% z' {/ N- A! h% s' V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, o1 I4 b5 e+ j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& V/ D9 S6 W, d4 Q& c| MCASP_TX_CLKFAIL
* G* ^$ a6 r$ w& F/ J| MCASP_TX_SYNCERROR
# @9 k) P- S0 S2 R Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
O- Y0 a# _8 k( _: \| MCASP_RX_CLKFAIL" L, a( @. N" q! u3 }) N
| MCASP_RX_SYNCERROR
& ?, k F& w1 R( M) Q| MCASP_RX_OVERRUN);
@: u/ D6 g! B$ l' ~} static void I2SDataTxRxActivate(void)
' l3 S2 V. M1 |& y$ ?7 W: j{* T3 y: N# @3 b3 b6 {7 v0 c
/* Start the clocks */: U! b- V2 |1 j( T- M: D, t2 [ X g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 K' t. x/ a- o% _6 b2 {: z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 e( W! u9 k1 j( k) m+ G: S, L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," {$ x* D. f1 R6 J; t) u K. @
EDMA3_TRIG_MODE_EVENT);
' Z2 \& Z' R4 V2 _$ Q; Z- MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : g1 b/ }, _2 q, w: y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ d/ v, h' i1 ?# x5 _8 B* Z/ SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 X6 r% @1 v; ]( U, u% |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" Q% Y! Z. i% @# bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ n$ V! `2 x( E7 U& h; M' ], @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' x. S. z* q2 v" R2 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, Z0 V! F2 h5 `2 O
}
* Q! X6 y$ K: B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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