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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! E4 s" B' c- l) R2 [. d
input mcasp_ahclkx,
u! |5 j. O, ^5 u: oinput mcasp_aclkx,2 v' \7 y b d4 |9 D, e
input axr0,
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8 S8 B* T9 M, V+ S! V, ?output mcasp_afsr,6 J, N; L' X4 {0 K+ _' W
output mcasp_ahclkr,! W2 z4 c \# Q- J8 s. x: ~
output mcasp_aclkr,
' Z/ [- o2 m; a Joutput axr1,8 e- p1 w, I- h; |+ r" m
assign mcasp_afsr = mcasp_afsx;4 i8 z$ F1 ^. D# V5 x6 f9 x a
assign mcasp_aclkr = mcasp_aclkx;3 E) \6 v/ l$ C. B8 F4 Q
assign mcasp_ahclkr = mcasp_ahclkx;
1 L' M! o2 T m$ Q: @% z! aassign axr1 = axr0;
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* N5 |6 `# h% X2 J4 C5 j. t0 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) @( A# R: U7 g5 ~8 xstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( `0 D7 Z4 a" c" U' |6 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 C8 I* o* h0 r! ^3 t8 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" U5 o1 `, P8 y4 I0 z( yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) c& H; p" ]( ~0 E& Z# i$ R3 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 X7 R- y1 R6 T+ Q6 G
MCASP_RX_MODE_DMA);4 }4 |8 `5 N! q+ e6 ~, ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ \+ S5 _5 o4 @$ x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& d$ P& F9 W0 j2 R7 k& k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( j0 c% V# h @7 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 \# y; E: z9 ~, f2 S1 Y1 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 K, e( B9 U, iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 t1 x+ V3 a- E2 s& X" h; L4 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ B" i! w, x; d+ b% u* W) w+ A, D+ ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; p& A4 t% S6 F- f, o4 e5 y$ xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: q% i2 O" m! S* O+ E0 L$ @- A
0x00, 0xFF); /* configure the clock for transmitter */( _* w, r9 Z7 A9 h5 q3 m3 u% D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 }! `" r9 g9 _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 |- U8 A# F* C8 W& yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," U$ f. L4 o3 V' \
0x00, 0xFF);
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' J6 E0 M. Z0 P5 K, o0 L* Z/* Enable synchronization of RX and TX sections */ & |' P+ @) E' Z1 Y, n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 X; L: H7 Z: [, Z4 p4 H. VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 S8 v, J Z) B3 `6 g' L" M- wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ m4 {- j+ ~" ]3 L, v& [6 z$ e** Set the serializers, Currently only one serializer is set as- U7 k7 K% Y- J) {
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 ?6 S4 w7 F: C* w6 e, K; s: } kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! b ?- i/ m% `" j+ W** Configure the McASP pins + \' j1 U R* H. s0 r
** Input - Frame Sync, Clock and Serializer Rx
; J1 ] K# q5 }" o** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 E3 h* e/ J/ _6 ]& g; |0 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 p) a4 Z! O# d4 J/ A2 v8 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 w$ r# _. W' R6 B" J
| MCASP_PIN_ACLKX
' e. ]- E+ |2 h ^$ ]| MCASP_PIN_AHCLKX( P7 r4 O; J/ v6 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 U s' X* w) s8 O% r3 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' N% H4 X" j8 Z( h( |" v$ a| MCASP_TX_CLKFAIL
" h' J! |" a* W, F/ z ?7 Y| MCASP_TX_SYNCERROR
0 c. H. C7 m+ {; P& P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . Q0 w3 h/ G" P9 T, u
| MCASP_RX_CLKFAIL# U5 _2 {2 |" e1 o# q
| MCASP_RX_SYNCERROR
/ F3 l/ d* v8 {* M4 l| MCASP_RX_OVERRUN);, B7 M$ m0 U* z3 t
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
6 H g# c. V1 W0 j9 |* q: ?( c% N4 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' c7 H# O- T ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 K* U3 w- |7 X* U+ E3 F# @. REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; O- m" M8 V, V1 W1 S7 \2 _
EDMA3_TRIG_MODE_EVENT);2 M/ b( @9 q; e0 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 T$ Z+ Z/ }, ^1 n8 q2 O2 @6 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 U7 i2 B6 ?$ J8 |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# E. [ `- E( u1 p8 ?/ O% j3 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; ]3 T* E/ h& w$ ]9 E9 g$ z( P5 c1 h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 {" n$ U) D t& H5 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 I: V1 Q. ^. X2 E# g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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