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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* G: j* [. @+ N# J) d0 N& P2 sinput mcasp_ahclkx,
0 L4 i1 g' |* j; K& Uinput mcasp_aclkx,
! j4 z# z, y3 y; l+ h1 V* }input axr0,6 G1 L$ u/ k8 \5 I; A, r4 d; {
. ~* R; ~+ x7 ^4 e
output mcasp_afsr,
* F- Q2 ~- {; F1 |output mcasp_ahclkr,
% L* x5 j3 w0 M- W' N' Voutput mcasp_aclkr,& M- S; {# U- R3 K2 b
output axr1,; p! ?4 z9 V/ v! |5 S' y4 d
assign mcasp_afsr = mcasp_afsx;7 s k: W9 X! E# @
assign mcasp_aclkr = mcasp_aclkx;' i/ I0 {0 \1 F, ]- Z
assign mcasp_ahclkr = mcasp_ahclkx;7 ]. ?+ z. Y7 {0 h% R! S( m
assign axr1 = axr0;
+ v( c% m5 e+ t$ C! V& {2 q! v" `, u0 r6 A* \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , g, G5 P/ s; u4 T! R5 P! q6 z
static void McASPI2SConfigure(void)! L Q5 K7 J) _
{
) l7 ~* g5 A. P" d) h5 W% x. GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 \! @5 r- V/ t) _9 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# R- r/ f& [9 _2 G* K( \: v3 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 ]5 |% L$ b, s4 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 B7 ~5 y! q8 r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. g" q8 t- U0 {' Y
MCASP_RX_MODE_DMA);
, ~- r- _ v9 n# c2 T2 \1 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* n& L8 y0 p8 `% z% r4 Y& g2 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- L; |4 R$ @( e( D+ e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( f0 W4 \9 k5 x9 X7 z, UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 G# u- x8 V) ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 t" K+ i" q) ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
q6 q$ |0 ` J! ~9 t+ RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 _. O& B0 I% t% v0 W9 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 \) ~* V. g9 X# z- D& L9 ~' BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 S$ s) M: y+ K6 Z! E8 c" T0x00, 0xFF); /* configure the clock for transmitter */
/ a" T% Z/ c1 l1 [ a! ]; n% J; SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ x1 X: z6 R" F6 f+ q" t7 I/ U! [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ ?8 A$ X" X" O' O5 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 V, ?1 Y; i. H' }1 F0x00, 0xFF);3 w8 ?4 K- H- J+ \ ^$ i( C% ~
5 E8 F; |! G1 ]" n: N3 L
/* Enable synchronization of RX and TX sections */ s) ]% U9 T. F) S" P a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& b# l1 G X, [" _- h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! u' d. Y9 Z9 E& n& k2 s7 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, U) X4 E, T3 i- C( I+ @$ _# P
** Set the serializers, Currently only one serializer is set as
: k- `, u' A7 b4 k, w, |8 c9 l** transmitter and one serializer as receiver.; f+ N# L% Q1 \: k
*/
7 i A* H1 D f. XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( v; ~ A" [/ l' ~$ p, q+ U; _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! z/ K4 o+ Y. E* m9 S X" E3 h* u** Configure the McASP pins
. x' w" J! ~8 v1 T; p** Input - Frame Sync, Clock and Serializer Rx0 t+ w6 | e- u, b' @( C: X- k
** Output - Serializer Tx is connected to the input of the codec
$ i, T, j) B B*// C: M) o! j7 g7 \5 C6 ~8 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& x7 r6 H( }0 i7 k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" O# ~ i# u; Z0 s) e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 u) i2 G" Q) _% d( U$ U+ g0 T# X
| MCASP_PIN_ACLKX8 z3 b* {. S4 L8 f- {1 \; [9 n
| MCASP_PIN_AHCLKX! x+ C$ F' m* {7 a9 b+ @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
s2 h9 h* F3 Y, E1 n3 |2 T; [0 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 `8 a$ R: K ~: h; `| MCASP_TX_CLKFAIL ! a9 b/ K+ q3 G" ?, l' Y
| MCASP_TX_SYNCERROR
$ ~5 v! b1 k) d1 E) y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' B/ w w6 N( p3 B$ _! ]% E$ Q7 W
| MCASP_RX_CLKFAIL% v" r( C! l: [- {% f2 o
| MCASP_RX_SYNCERROR - ^/ }/ U; V3 V$ }6 z8 j
| MCASP_RX_OVERRUN);2 ?$ X# ?; C9 X) I1 W+ \
} static void I2SDataTxRxActivate(void): @4 |1 d$ a- Y9 r; R5 G. A
{- O3 Q* G8 L3 @9 r# T
/* Start the clocks */
6 s. l) p0 [" y, Q' }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ L5 ]4 s0 j l. \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* N% G/ {4 S: B: c' K) x0 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' u" {. v$ p! P x1 U7 M" `& h$ I
EDMA3_TRIG_MODE_EVENT);0 L$ W, J" l2 p5 I& n" U$ Y: h9 ?5 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% C* k# D( f% G5 A, Z0 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& G+ d% [+ |6 m0 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- z) G2 m- M8 p# nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& K5 l; o6 h" N, S- x9 `" _6 M! fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 W7 i8 `$ X% n. z: } c/ o% G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 l3 g- u+ d O' L$ ]6 \' D% D, r$ @9 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 o. s' V, v9 k `. f} ! d. i' C( S; c# C" s3 n0 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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