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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: r1 E9 \1 h2 I7 winput mcasp_ahclkx,
0 ]& z! Z( O( \! D3 z5 dinput mcasp_aclkx,
* V# A& Z) F3 g- Linput axr0,) |6 O7 r1 J& ]# v0 f
" O+ j f3 i% l% R8 r
output mcasp_afsr,
2 ^6 _1 ^9 c3 {2 h+ B: @% @output mcasp_ahclkr,
0 \% F; p" h' W2 Zoutput mcasp_aclkr,
" U3 q M9 l2 I3 Moutput axr1,
6 B! d d- @3 j assign mcasp_afsr = mcasp_afsx;
+ D! ]) T& o, b4 S1 }* x! b1 Passign mcasp_aclkr = mcasp_aclkx;9 Q: ~' H3 J R: o Z. N* i2 f
assign mcasp_ahclkr = mcasp_ahclkx;2 Z; W& m5 c5 M; m8 u, f3 y
assign axr1 = axr0;
$ f" O" h# e$ M. _( W$ ^( P
6 z" l, s: t1 V6 c* h6 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 `* g6 R) {$ X$ `5 N/ R* b# h8 y5 I- v( Fstatic void McASPI2SConfigure(void)* _, | P% {+ V) l6 J6 _
{6 L# [4 C: Z* y3 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 |' j0 w0 J; i/ K |, j3 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* k4 S* E0 I5 m1 x' e' W& C) M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! r6 o9 d$ Y; R1 [$ o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' |( I6 n2 X+ S( \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ U' m9 ^- l" q' p6 i# A
MCASP_RX_MODE_DMA);
, ]# t2 {2 t; yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( m2 A$ M8 H4 Y H5 ]8 \9 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% I/ y. |/ O( I6 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # k( o4 e% }! m4 h% Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 d: J: v: x/ {. U3 f7 u5 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* }( i- a, o. Y8 p! _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 x* o3 y+ N0 P/ h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 y0 p- n. U z d( ^7 L+ @4 v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 M( F# ^7 L. u8 O8 J& Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. _8 ~: P5 L5 k f0x00, 0xFF); /* configure the clock for transmitter */
! Q, D' \" y. J! \+ E7 h. HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( j. `3 h9 ?$ G4 b% `4 S: T6 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) D }0 x; W, y6 f. E' t/ K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( A* k9 ^$ B# [. ]9 H
0x00, 0xFF);& w5 @' {. \# \: }6 M+ A1 W
( R. Y9 S. {/ G, s7 S8 o/* Enable synchronization of RX and TX sections */ " r- ^$ l1 i8 V* _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% T0 ]2 e/ ^; ^- y8 {8 h; ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 i3 L. E+ I( m) Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) d b3 r. \7 u @
** Set the serializers, Currently only one serializer is set as
2 U/ a! M A7 @3 d* N( ?- L0 M** transmitter and one serializer as receiver.
4 U$ ^1 {+ n5 L# f4 ]& {6 a5 Q8 H*/. I+ z4 j# V0 @# w: k _- G% |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ e3 H' g+ @$ K. L8 c: B% \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) L; s3 B+ V5 r5 r( Z; H, F
** Configure the McASP pins
1 d2 E/ w g, n: X0 S8 u** Input - Frame Sync, Clock and Serializer Rx9 F' a/ a/ q: r0 _& k
** Output - Serializer Tx is connected to the input of the codec
7 K6 \+ k- x! F1 \*/
" V" n. X9 Z. a: M) r( uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) [( ]5 g) j5 U/ w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" h" z1 }3 R8 X7 p8 ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 ]: ~; ^/ g* G" T' s$ i* @. w| MCASP_PIN_ACLKX
" n9 H' Y' L" S& i' v" p0 ~| MCASP_PIN_AHCLKX
6 r2 [- F3 p0 H( o3 K5 r: G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 u0 T0 [! Z1 ^3 m j) o7 F0 `- \7 t4 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; D. u: |. W. q- b
| MCASP_TX_CLKFAIL
, o1 d5 {0 @4 [| MCASP_TX_SYNCERROR& i a/ f( K' e! l" Y6 H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' i3 d1 t+ ^( o
| MCASP_RX_CLKFAIL
; R: B% R/ r5 n% F3 z1 T1 @| MCASP_RX_SYNCERROR
! F+ t; V' Q# K& d9 d: H9 p| MCASP_RX_OVERRUN);7 B' M. W; W- G! h% d ^4 [7 C- {
} static void I2SDataTxRxActivate(void)
. I8 P5 {7 I+ }( f0 r{
% W0 E$ C& n9 }# c/* Start the clocks */$ K! m, m5 z( y$ t2 J7 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ E8 C3 z8 U4 w' O; l0 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# M; G* b: S& f9 d& t& ^/ k; z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
y' J) v- X1 R u+ o/ P/ k# pEDMA3_TRIG_MODE_EVENT);. F) H9 s0 Y& Z+ y9 A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; F( r- r, k; i2 x5 q0 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 R7 u' f3 Z- d+ L. f& m# mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: Y% X/ j F2 L7 Q8 {+ g; W6 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* l+ E! ^" j, \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* b+ N! u F' s6 M" iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ W& Y0 o% {6 q( ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 j9 M7 P+ `3 p( j7 t& C
} 9 ` Q% C5 U" d, h( o8 `% {; `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 e' Z F( z5 {9 t, \
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