|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
t1 ?8 K7 v0 N, P: l! Ainput mcasp_ahclkx,
. v$ H$ u( i1 oinput mcasp_aclkx,; M3 s, x \, w i( y2 G E
input axr0,
, T5 q" ~' r0 U. k/ y) r1 w2 C" z$ T5 i8 O4 y7 _* m) I; r$ t
output mcasp_afsr,
. [7 J3 {; q2 X- n! l) B- Houtput mcasp_ahclkr,0 V9 X- s! U+ d, o# q
output mcasp_aclkr,7 z x, I2 e/ v- i, q/ S; F9 K! ]
output axr1,
B7 K3 a& Q- `) z; s$ c1 X5 L assign mcasp_afsr = mcasp_afsx;2 o8 r2 u6 T, ^7 N; C
assign mcasp_aclkr = mcasp_aclkx;
% O _% K" k4 {* D4 |. } b3 _, w- zassign mcasp_ahclkr = mcasp_ahclkx;& V, d* M6 n2 |3 L+ v2 ?$ b1 G4 Z# [
assign axr1 = axr0; 8 \2 |% i( P, \2 N9 v" ^ B r
/ K5 ?0 t: L9 n/ o( d5 c8 \" T! n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; F. O) d) [( u2 z, estatic void McASPI2SConfigure(void)& Z4 a) U0 q; D' `( W
{
; q( a9 U# |2 f1 y8 O$ FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 S0 D$ d8 f; ?* d, v5 \* X7 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" y/ i: P) k4 w o. @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ W7 I' C7 I4 YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ k. r n: [1 E# Q3 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 w+ H y+ _% f. d8 T4 S2 zMCASP_RX_MODE_DMA);) B4 w9 q9 l# {( l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: }, P# i. o! L' b8 t4 D& g- r! kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 g" R7 ~( t) O5 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( P& H, F9 ?$ h: ?0 d5 V6 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( N9 y- f3 ` }# n9 z4 J* r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 r1 k) M; N! v8 N' D3 O, rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 W: W/ R5 w! \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); T9 n& R7 L" E( ]$ K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 k% Y4 N- a" ]5 X! [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: A# b% u1 _9 j1 X& M0x00, 0xFF); /* configure the clock for transmitter */
8 u& W% I4 d# _, }* f2 J6 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' h ~1 E# C! s7 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# N6 [# f4 X0 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! S2 m0 ^8 V. P- J, {7 b
0x00, 0xFF);+ K) S$ V. l2 B. i" r3 y% D
5 d6 E- {0 W2 T7 L1 e
/* Enable synchronization of RX and TX sections */
; i" D9 U8 G' `! {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, e2 m& @0 s; _! C( E; s" O0 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ b) c) y7 l/ x- I2 F0 J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ i& J1 Q7 Y0 l( r, g** Set the serializers, Currently only one serializer is set as
7 j# c5 S! G7 \. @: V4 C) G; K& Q) w** transmitter and one serializer as receiver.$ o4 h' i5 h6 S; u+ w- X& m t, T( g
*/8 s g% D# U, G# g3 {$ |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) ]% M9 Z+ [2 j2 ]; ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; H* y6 F3 `- u
** Configure the McASP pins 7 D$ I @9 @, _% [& P: I- a" _2 n
** Input - Frame Sync, Clock and Serializer Rx3 t1 v+ j _% y2 o& X
** Output - Serializer Tx is connected to the input of the codec
4 t: @% f1 g* U1 i4 m7 c*/7 y/ O4 R& C, `* N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 M/ k7 t# m. A2 j# i& T0 e# i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: i) `; W# C+ M) W' W4 a' t1 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ t& k% w- g( V- m7 @| MCASP_PIN_ACLKX
2 F$ Y) n) W: V, @ f) v. ]| MCASP_PIN_AHCLKX' g: N; Z% a* G4 c. u" i' W' a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// j0 `" w2 T; b) H" t: v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- v0 a4 `% j, J" s4 V1 J| MCASP_TX_CLKFAIL 3 s0 r% E( x. Z. {3 F! F7 P4 D
| MCASP_TX_SYNCERROR8 j& @$ ^" \2 t; m) @3 I: o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 n5 I0 Q+ p6 U" u% V- l
| MCASP_RX_CLKFAIL
6 ?' W7 l1 }8 N& E8 l+ A| MCASP_RX_SYNCERROR 3 D& W, j5 _ g. u
| MCASP_RX_OVERRUN);
+ q! y' `5 r$ }. d1 K# Z} static void I2SDataTxRxActivate(void)
1 h L- i! `7 p9 S{
! x5 J- u1 D; _/* Start the clocks */2 Y, A; Y. y; {0 |" A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: U: i4 R6 Q+ H: F; x A! I5 c) e, MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 d( F- j) L' N" _0 t' N- P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! ?- O' K, Q3 p" T% |& w$ C$ J8 q
EDMA3_TRIG_MODE_EVENT);
0 x+ t7 N) l, P f: d+ O6 I8 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 N9 T! o- T: M7 _# a9 x" XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 G+ ?$ q' [4 ]% V0 K# BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ f9 \+ a9 U# P7 m2 T EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% s- O: m& T8 \4 U$ j0 qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% l8 C* v+ Q6 Y/ p7 u3 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; c( L% X6 Q! e" @ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* s1 V; D) E- L
} - f0 H! O* ^7 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 ?) b/ G+ g- X$ |$ u
|