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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ I+ d2 @' E9 F' U1 l& z. q
input mcasp_ahclkx,
( S* |9 a' h: |2 B7 `8 [input mcasp_aclkx,) N- g4 a* k5 f
input axr0,
9 W' w# ]) n! t# N& Z7 j# N9 i* w
7 ]; {+ v# t% g; F1 L* d/ F. doutput mcasp_afsr,1 J4 Y! k' m6 [1 k& ~) K7 ~* x
output mcasp_ahclkr,
" T! ?# s+ J5 a1 z7 z* loutput mcasp_aclkr,
& x v+ ]( ?3 e0 Q! j, noutput axr1,
: S9 Q0 k8 N( l G+ E% H \9 ~( z assign mcasp_afsr = mcasp_afsx;5 N/ q8 i& [) `7 n9 D& l( K
assign mcasp_aclkr = mcasp_aclkx;
% E7 x! _5 \0 yassign mcasp_ahclkr = mcasp_ahclkx;- O" N. Y! Z- w0 J5 [
assign axr1 = axr0; 1 u, ~2 @% i( `
0 `" l) S- g: |( A6 V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 C0 H. i3 U$ ^) R7 zstatic void McASPI2SConfigure(void)
) {* @) R) A2 f( G{
6 R+ x9 E1 m* _% m. o+ m: \McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 m. U. _& J" t+ m4 c/ c# g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 L( r- n8 Q6 Y, b$ E4 ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( x2 O* t: P* e) d& Y! u& m! `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) a1 x u+ ^4 d# P8 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& g+ @5 ?# h3 E5 \8 g) IMCASP_RX_MODE_DMA);
4 u- B$ t5 e" i* q! E h" ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 d. f) S# Z8 e3 v! x( J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) o% v5 \' b9 ]6 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & @* Y% [ l" b! U5 ]$ X, H6 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* a5 B+ P( s6 p- v/ p9 V# L9 p. v b4 HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) o3 D+ r' n3 N7 O$ D% b" ^3 R* O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 j9 V" R" q; U2 W2 Q1 A9 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; U6 y$ D7 U7 C% T3 `$ c; E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 [( j' p# Z B7 o4 Q4 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ o a! C ~' R0x00, 0xFF); /* configure the clock for transmitter */
7 ?' _% v3 k5 ?& AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& J; A# ^ i! U ?# U5 v, AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- {# s, A) ~6 E+ n$ _% c( l. GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 n5 h( S" w# E5 ^' p' Y0x00, 0xFF);
5 i3 v _6 S8 K- J+ c3 B& v# M3 i2 `' k
s2 h Q# z* s0 g7 ~/* Enable synchronization of RX and TX sections */
: d h' C2 ]6 u# IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- S9 ]4 v1 r9 B/ V5 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 Y; o3 l! S4 C" A& y2 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 q$ a9 X' V+ X/ m
** Set the serializers, Currently only one serializer is set as+ {2 X0 _# ]1 K& X0 c2 f
** transmitter and one serializer as receiver.4 k5 W# I* _0 a1 I9 y% o
*/
) B% o. I9 {" Z( R- iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 y& W( q6 L$ J& I" j8 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 d! [6 r) Y4 Q/ a8 c
** Configure the McASP pins 9 u9 ?' ]' \0 z% k) ^- m+ B
** Input - Frame Sync, Clock and Serializer Rx
+ @/ k. [* K v) b: O9 C** Output - Serializer Tx is connected to the input of the codec
) y+ h9 G% t, s*/6 _6 P& K/ o" b# }# T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 q% @6 w; X& d. {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 ]# }8 q8 `7 Q, [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, M X1 X& [6 x4 e1 q9 t+ W/ y| MCASP_PIN_ACLKX2 z7 b8 |- {" |& F3 ?, T
| MCASP_PIN_AHCLKX/ z1 l# i1 [+ h& n( C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* ?% s2 x' o# r+ {5 PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - K. ^1 |$ z- e: H' s" U. s
| MCASP_TX_CLKFAIL / k w# t2 H8 H, m" A
| MCASP_TX_SYNCERROR l* U+ k5 Y- W! a+ C. [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 \( D& q6 s5 d' W6 h. y
| MCASP_RX_CLKFAIL0 f+ L1 D# `! | I7 t
| MCASP_RX_SYNCERROR
: b( }" K2 `* H/ @| MCASP_RX_OVERRUN);- h' x2 U+ B& K t' p
} static void I2SDataTxRxActivate(void)
# x! O7 B# r0 W{
0 S3 j& ]% {# L9 P m; v" z+ I# L% l/* Start the clocks */
/ [" e! k) c, ?) C# F9 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% J6 G/ } Q* H; p B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% w5 C6 j7 i! A5 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 [3 t* ^1 V7 C' A
EDMA3_TRIG_MODE_EVENT); t4 e/ D+ l1 ]3 s8 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " O( i. m- ]" ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 q' e' d2 k7 n4 z% r0 J8 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 Z" d; |* n' {! o' `6 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- r4 I: l% x8 ?" _% kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# P: @, n: S4 d9 G- NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' G; ~& a5 w$ C6 m1 n9 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 V2 b% q8 y, B' S- S
} ) Y7 ?1 W5 `- p: m8 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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