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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% ~9 e q5 c, B* K: ?7 j4 Finput mcasp_ahclkx,
6 o1 G+ c) K2 k/ Z% ]2 G) N+ Qinput mcasp_aclkx,
+ {' I# o7 @( s0 Ninput axr0,
4 E) x* s! h+ ~, i3 ]0 j' v# U
( ^7 Q4 ~7 N. D' p+ doutput mcasp_afsr,
3 ~ n* f8 r& ^# ^$ u/ ] Aoutput mcasp_ahclkr,
5 t/ N! ] a+ Y5 Ioutput mcasp_aclkr,
- y0 Y) c% e( D/ v6 E/ Xoutput axr1,
$ t! K$ U2 v. l( s8 k assign mcasp_afsr = mcasp_afsx;
2 x' z, w% U# q# eassign mcasp_aclkr = mcasp_aclkx;
( y) v/ I6 k8 K. a7 v3 s$ C' j& Zassign mcasp_ahclkr = mcasp_ahclkx;) w1 r+ o/ L0 _0 }
assign axr1 = axr0;
' C! A: T6 c& u7 P% K7 U8 l i) l5 H9 ~6 x( }& }3 c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - Z. R5 k6 s0 [8 V1 f& i9 C
static void McASPI2SConfigure(void)
3 K* M: j( U% Y- i$ _' I0 N{
2 }+ P! j6 S! Q: E5 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' r3 w1 Q) }9 E2 Q" g7 e% n# T3 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 o' a6 v* \: i3 t0 IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 C5 g" K! B( v) m+ |/ v, e7 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ P/ e' m( w! w! U) N# E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 r6 m0 g; f6 F3 s w4 o( d$ \MCASP_RX_MODE_DMA);" C9 i* D% A4 n* T3 t, ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: v6 w( Z7 t; m2 O% e* A; v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* g3 n4 Z3 y. Y0 u( ?, ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / ?' o7 v0 j, F# O# U) D0 F) q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- p" I( d9 P) l- RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( R1 w7 v/ ?2 b% YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 \# m- b, j5 O% P# J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! K" D' J G* Y( d* S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # ?7 U) d+ C. p, J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. X: A3 H" g- S0x00, 0xFF); /* configure the clock for transmitter */
) `! Q3 ^0 l ?. ?2 H yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) ]+ y. z9 r% L, k$ q, ~4 Z3 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( {6 f n" y( d; k3 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* ~% U+ V P2 ~/ K& A. v7 w* v( ^3 F
0x00, 0xFF);
3 C, g3 k0 m S" t
8 U" B* P1 B/ I' `% d/* Enable synchronization of RX and TX sections */ : H7 G8 F* Z+ \! I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 k! z6 u# D. N- B0 C6 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 F+ O8 s$ @& H, o, k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: m# Z/ H; A* x- \: e** Set the serializers, Currently only one serializer is set as
! c4 ^8 j# k8 ~ z6 i& r/ n** transmitter and one serializer as receiver.8 [ r( \: c& X1 i0 e0 ^+ i* f
*/5 o5 ]# l5 A- ~- i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: L6 S$ z; [, F3 i3 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, F8 ?$ f) J5 V* _# o
** Configure the McASP pins $ n8 w# e" t% \+ a- f
** Input - Frame Sync, Clock and Serializer Rx9 w3 T+ y, l( c. ^+ s
** Output - Serializer Tx is connected to the input of the codec ; g6 n1 @* r# _, c
*/
0 a3 H5 `/ U x: dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 u4 h( @: n0 r+ H2 ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' l) s* |2 J- @3 C& Q) ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) i1 X. A/ P# \& i
| MCASP_PIN_ACLKX& c4 N! i& f O) _
| MCASP_PIN_AHCLKX
3 I- ?0 s% c: a6 Q6 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 f# P6 W8 E2 B" ]# z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 q, w7 V3 d7 ~9 Z7 ^$ w2 n
| MCASP_TX_CLKFAIL
9 q/ W- _3 C8 X4 H& i; ~| MCASP_TX_SYNCERROR5 |" E4 N" l. t" w+ O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 c# A9 d0 d+ ?; r+ B| MCASP_RX_CLKFAIL/ B# I- Y c7 n4 [7 Z! x1 k
| MCASP_RX_SYNCERROR
& M0 {6 m3 U1 l1 B| MCASP_RX_OVERRUN);& C ?% o8 }. o
} static void I2SDataTxRxActivate(void)+ U2 D3 h9 H6 c' J" z
{4 k9 r# Q0 [3 X8 n, x
/* Start the clocks */
7 `. t0 S, `5 i1 [) t" w+ C9 h6 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 _2 x0 v0 A% M* s6 r @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 x8 ?$ ^3 `, Q" j% `9 F6 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 K/ g$ x- C# FEDMA3_TRIG_MODE_EVENT);- X! s) r' g+ D$ I- n& W. r( X, X3 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 ]( K! m1 P' `1 y7 Z7 ~' r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ r2 T& l9 ?; ?6 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. E% F5 G! z. k( r" z+ [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% A. i- s+ I8 U; `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# w" O6 Q) y: S* v( ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 X- m: r9 q' ?+ s9 j) `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; ^: b( @; @2 r% r6 M
} + y+ k% {* e+ S) n/ v" n4 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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