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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) R: i, ]5 d( w# N0 V8 N+ Linput mcasp_ahclkx,4 Y. d5 J7 r4 |
input mcasp_aclkx,
+ _# H7 ~4 c% t* ainput axr0,5 c+ D( Y. T$ G9 m4 V3 o* h
, f( B/ G0 c, z% o. L# c" u0 Soutput mcasp_afsr,
% I1 E4 x% U) e7 u/ T; \% s) ?output mcasp_ahclkr, e9 ~/ l# J3 z$ h, D6 {* S
output mcasp_aclkr,
* s J7 @6 C' S* ~output axr1,- [3 C1 L; N; }& q
assign mcasp_afsr = mcasp_afsx;( H) e$ }2 n1 @6 I2 [
assign mcasp_aclkr = mcasp_aclkx;
1 f$ B" r- i0 \; Uassign mcasp_ahclkr = mcasp_ahclkx;
+ t6 @) M b$ u+ Y% O: h- Cassign axr1 = axr0; 0 Y1 x5 V1 _5 f5 l. i# \
1 }4 m! o7 M" T$ y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 {- F& K# O I8 A( i' s$ v1 \" Dstatic void McASPI2SConfigure(void)
" o, H; Y) F0 O2 k8 i{
4 U! h1 h1 M" c, A; u5 J" q# KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# E! ^2 W1 K5 ~& p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ b, ~; i, l7 k" P% iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" M7 P9 Y8 f( V6 k6 c/ Q% H, S$ S' k- WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// W% p% |5 r' L7 }$ P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 y; T. ~1 `: _# K i: xMCASP_RX_MODE_DMA);
% J* ]* j7 i+ W! j7 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 d0 M5 I" P7 s# \! G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) W. {( e+ ~% ~. m3 l/ e* ?' rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, |! @: S5 m/ Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% J4 x, g' _8 M% ?6 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 c7 _+ W1 R) v1 ~* C8 C3 `1 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ X6 t; G2 H6 e6 s6 g5 b- `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( |8 p6 \7 V7 K, C& {! B! g/ JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 g) ?5 c- M/ z: |8 |7 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ?4 d5 B4 h5 a% g1 J1 u( E0x00, 0xFF); /* configure the clock for transmitter */3 \! e" S+ m3 W; @4 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! V3 s' V$ Q; c5 N6 ~+ N" f* O7 ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. W* \& _& D" X4 [1 y' vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 c. d4 y" J9 u1 l& w
0x00, 0xFF);) R( z4 R- _4 P7 h' u6 W, e
- g3 `, Y& W! i: P# |; C2 ]/* Enable synchronization of RX and TX sections */ 3 [) P* v: Z# W8 J4 V6 o h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" W) L) @# U2 |: R2 w4 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 a. C; r6 _6 I! W/ B- C: U! C v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) P5 Q C* |. a- W4 i# x' t0 Q** Set the serializers, Currently only one serializer is set as
: y; E; P. q+ {: c& T** transmitter and one serializer as receiver.
( q W. i4 A4 e, y*/9 B7 H8 l9 _- A+ ]% }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ L9 O( x1 z6 ?( pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ d, d) f1 w1 W% H
** Configure the McASP pins
% G4 ^8 H6 B1 l/ _! \- c! R** Input - Frame Sync, Clock and Serializer Rx
- l0 h' v6 Z4 S** Output - Serializer Tx is connected to the input of the codec
, @& f* x& w8 e; _& W*/9 p& S' |. q, ^4 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 r5 a+ F8 j: ^$ L( N2 L4 Y! QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 _2 w. f; ^5 M1 } [6 c( z5 r2 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* k4 \( L. y& c5 C
| MCASP_PIN_ACLKX
) ^3 s$ \6 R7 ?. v| MCASP_PIN_AHCLKX
8 N9 ^* ]: ]- Z. i: z/ ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& u' l9 D: X; L* o0 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; `1 E& F: f/ S6 T7 q; n$ |; s
| MCASP_TX_CLKFAIL 3 m C9 D0 r2 Y0 s$ N
| MCASP_TX_SYNCERROR) @0 C( Q7 l0 ?7 g4 T4 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . H4 C( r1 J# n# ]1 x
| MCASP_RX_CLKFAIL) G6 b' S. m% P2 l6 J$ d
| MCASP_RX_SYNCERROR
. ^8 ]7 z* o0 j. r/ j( Z4 x| MCASP_RX_OVERRUN);
0 U, E& ~% H6 \3 R, T) C, C} static void I2SDataTxRxActivate(void)
- W# f# k% C t3 B( W& I* Y5 }{
% K( z y" X, F7 D- K% E) j7 h/* Start the clocks */9 c. ~+ g' h, a# n/ Q& M. b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' b% Q4 Z( E9 a% U4 o/ sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# J. N3 w& q$ z- ~! N3 d4 m/ Y j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* E- Q) t; [" D# R+ sEDMA3_TRIG_MODE_EVENT);( b" j" _5 D# n. R5 m+ E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 q9 Q2 m5 I- \/ U: ~6 f( lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" R4 b. M" ^" L# I/ O3 m& t, o4 DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' A* x8 B e2 t* L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* n: S- }/ q' Y9 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 [( n% w: w, N) O! H' jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: d# z( a, w: d. n! c1 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ v/ z' U- Y( I& q" C
} 0 i8 Z7 e, n6 Y; v& G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 p/ V! X) x4 u* R5 j5 q! H+ ?2 M" T |