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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; c' W, A5 F% L3 q N
input mcasp_ahclkx,
H* O% e1 d' Y; Ginput mcasp_aclkx,
4 Z# X4 H7 U4 `' finput axr0,' ?2 q; ]4 @3 b/ P
5 H' v. t/ o/ D9 n: Y+ B) Woutput mcasp_afsr,
^% q' p" d0 ooutput mcasp_ahclkr,1 x1 J9 U1 q6 H# f% ~# L
output mcasp_aclkr,
R" J& h- Y5 ^# ?' l# X2 b" |output axr1,2 y( B8 q. q: A' [7 d
assign mcasp_afsr = mcasp_afsx;
% L! b. B$ a8 i+ y- e3 H* tassign mcasp_aclkr = mcasp_aclkx;
# G, z' M ]" qassign mcasp_ahclkr = mcasp_ahclkx;
0 n* k1 [& l0 x# W/ W( ^assign axr1 = axr0; 0 Y. l: d3 X5 u' j, s7 d* [* s- X' w
, F2 G# @9 Z; N/ V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' z1 z: }) l) p
static void McASPI2SConfigure(void)
4 G3 K5 Y! F3 {{
1 v1 F U: d% m& }) R0 G: i O0 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);" Z; _2 x' F7 A, V& E& L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 J7 b4 T9 x, F! D+ H2 `1 O7 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 H' x1 M ~# i# t I3 ^5 e9 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; w* g5 L. S# e* T, S) u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 I" \9 @% `3 b {8 g) d3 TMCASP_RX_MODE_DMA);3 q: Z5 e1 H3 R3 T6 F8 ?2 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( [& @! J! k" y! a+ c! X. TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ k* e5 m( N' N6 c# f" r7 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 d2 i& _0 @) C% Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! M) D- |+ s; D& b& W1 W! h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: M* i; Y0 e* A" aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 _) }5 z5 B/ \/ l: s9 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ r# I' ]* b% l t! XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , T* }- G; y# z6 U1 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& |: L2 {$ x8 Y4 e
0x00, 0xFF); /* configure the clock for transmitter */! a+ `, ^; L3 U4 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 u# Q. e" ?" ^! }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 ~- d5 T0 ^( O; N' J4 W6 u, HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 b1 @* }* L/ R) ?2 H
0x00, 0xFF);
2 }+ L, ^, s X
9 ]. U: I( t# o& v/* Enable synchronization of RX and TX sections */ ) { C( K- f* v9 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, V( e) F& }& l7 L4 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# B4 o# s0 K0 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 _0 A: f" ^. U9 N, P** Set the serializers, Currently only one serializer is set as+ }$ S4 S$ b7 k: T2 j
** transmitter and one serializer as receiver.# L) f) ^8 M+ H9 T( U6 L! `
*/$ A% w' {6 O: u/ ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 I$ P% N( I. W# H9 o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 \4 t& y) e/ q0 e: H
** Configure the McASP pins
* H `- c. e6 ^- y" R) J7 S** Input - Frame Sync, Clock and Serializer Rx7 Q4 b; z H G" [5 m
** Output - Serializer Tx is connected to the input of the codec : y4 m* t6 O( A/ g$ C% I i
*/9 @. W* A( e. r2 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 }' ]; N9 h+ G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( Q- J6 j4 N' g7 e0 l2 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 S: R a# U) X
| MCASP_PIN_ACLKX" O6 C/ q' s# B# e- o4 A
| MCASP_PIN_AHCLKX2 {# J# J( X% I2 h! P. t5 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// X" _5 w( v8 m2 ^% ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. U0 E4 B9 }7 E* Z8 i" w| MCASP_TX_CLKFAIL " O+ l: D! }+ e( G X
| MCASP_TX_SYNCERROR
1 n+ H) q; j' f! N: ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 r; \( j( W: p$ u7 A5 Q| MCASP_RX_CLKFAIL7 _1 e3 Z- ?# _3 o' D _7 @* D0 s
| MCASP_RX_SYNCERROR # Q7 n- \. R3 x2 k. u
| MCASP_RX_OVERRUN);* V" D9 j( _' h5 g
} static void I2SDataTxRxActivate(void)& s5 }* V( N B. r* j& h/ {
{1 E, ]: q( K6 |
/* Start the clocks */
7 J) O/ w ?+ U+ c8 ]' G! @1 v) zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' c! v% J4 j# X1 K1 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 ~0 P$ e. ~9 B8 S" ~4 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- S) V, x7 M- K: p, i
EDMA3_TRIG_MODE_EVENT);
1 B9 u' n6 f: ~8 r6 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, i3 M! Q. m+ V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ ?& [0 K, j3 P/ dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 @. C* I/ s3 B( k' R4 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 V) _7 E6 `8 O" twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* s X B6 r* q1 d# \0 Z& A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 V7 X$ T, g1 F/ u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 l! B9 B1 v4 f9 U _8 _} : K- ]/ D1 o* g0 m1 |2 i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 u, a% u r) C2 M7 R
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