MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
- w) }" s7 j9 O$ G8 h  k  dinput axr0,
) Q& H7 ~7 L, J& Y
0 E) h$ F8 L" toutput mcasp_afsr,
output mcasp_ahclkr,
- r0 E, Y9 M' doutput mcasp_aclkr,
output axr1,
* {+ d* x3 e$ k# e% K; u

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
9 T$ T9 t9 s& W9 E9 Z+ Qassign mcasp_ahclkr = mcasp_ahclkx;
* o; f3 F7 J8 w. }- N4 g( bassign axr1 = axr0;

; l, Y/ T* y8 L( U3 [% B; b

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

* v7 |  |$ Y( x# _# `8 c+ Z

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 q& r  R3 y% n: F3 O  x1 ]6 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! A% b% f. Z! q  ]. o3 d0 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! l7 W6 p% Q, l$ Q7 D3 i9 OMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 U5 ?- s# J6 V8 o9 |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
9 ~. }2 k4 F" f, b4 IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# J% R+ {* e6 ^* TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
' W8 `& w( f3 ~; c5 l" a1 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& [+ M9 }* t; a' s2 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# O( |2 K$ w- q+ g% _3 a/ r0x00, 0xFF);
/ A3 ^9 [9 v6 _
/* Enable synchronization of RX and TX sections */
* S0 Q4 a( H9 ]1 I5 t! I* UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- D  b' {: E! l, T7 Z; p$ w2 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
: {+ G0 c* R6 n** transmitter and one serializer as receiver.
" a, }  W! F( E  I( w5 ^  E*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 z5 Z- m' g/ w" AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
; `* c1 U# |4 j/ \* e** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
+ G1 Z! C  J/ n  s5 z* f% w** Output - Serializer Tx is connected to the input of the codec
*/
& R0 H+ x- Q! }0 @2 M+ cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
& W; ^/ [5 n" p2 y2 H8 E2 U6 L. W| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
8 p. b2 Q$ [, `. XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 G. i) Q8 o% `! W- y( j| MCASP_TX_CLKFAIL
" v: Q7 X9 |3 F. a8 K. X# Z| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
6 Y, z2 k4 @$ [% i4 L| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
( j. b8 s$ x3 w, |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, `: w' Q8 m/ H" k) m" TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 |8 `; a5 \) V. j6 |1 g# t+ ]EDMA3_TRIG_MODE_EVENT);
, z& M+ F  H6 q8 C8 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
* c) Q% s: Y1 M  ?6 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* S5 ~. Y3 R# J# fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ P1 M* B( [6 g}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

7 s1 z' \* }" j8 W( |- g. _