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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 b" D& T7 e3 V5 a3 `1 \- l9 linput mcasp_ahclkx,) z2 O/ e- N2 _% k9 C$ e# n# Y
input mcasp_aclkx,
0 R; U2 O+ l- x. w; [ R8 H4 Vinput axr0,
- Q0 e3 B9 y, |- j
2 t2 P: o5 n( }* m l1 @output mcasp_afsr,
- C% c" G% D4 Moutput mcasp_ahclkr,
- \* G0 \4 f& s. @1 p! R9 Joutput mcasp_aclkr," K4 G; S' H. M. P
output axr1,
! C% W% m( K& J9 V3 c3 L4 U assign mcasp_afsr = mcasp_afsx;
3 [5 S* I1 J+ i2 o& I8 F/ j" I+ ?6 U4 Iassign mcasp_aclkr = mcasp_aclkx;% \& O5 p' X# B5 j2 f$ w! |
assign mcasp_ahclkr = mcasp_ahclkx;
6 ?. G# j: P" Z% R- t' o d3 ^5 dassign axr1 = axr0; / S l2 ?3 l) C: t. i# P5 `" y
' M" I, T3 k* n. ^' w: [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& I3 i4 p% ?5 ~& ^6 i( r8 u5 ~2 kstatic void McASPI2SConfigure(void)( x$ H" E2 G; J( g1 s' [
{3 ~/ W( _; B. @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 @% L) T! I: R' i8 t [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* p$ N* o' E4 s* v( F; RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' r8 E) L1 ?) z5 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
c% h. q8 F4 g2 K3 s2 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( y; Z: ~+ {/ O; a5 S# c# w$ @MCASP_RX_MODE_DMA);
+ A! [0 r( Y, GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 X! z u1 q# A" v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- _2 V: T% G( k7 F- b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) h$ V6 _! a- _) D B& Q q$ Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, d( w' _" ?: ] X8 x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 r( P5 X( O( h( y/ eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. A0 [# O! \- s. }+ F) v1 V1 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ H' ~5 K6 o) ]& I! [, W" y& h6 Z d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : C, A* d: X0 V' L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% i8 D2 A- @5 T1 Z; Z! c# b6 x7 w: @0x00, 0xFF); /* configure the clock for transmitter */
, z2 ?( B, r3 i6 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 Q7 G5 L& t* ` Z9 u' [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # M: _& O8 o9 {7 V9 ?! J7 f0 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 u, J( `( k# y& a# X1 H& e
0x00, 0xFF);: Z- V' M/ |/ ?/ u/ h# a
7 z! p; @7 O. C7 K6 i( P/* Enable synchronization of RX and TX sections */
/ X2 p# D1 m% j( dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 r4 @& h4 m% ^, d. ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 W; Y f. H: C# x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# ^# Q4 @4 T5 M! Y1 t# d3 U& \8 Y** Set the serializers, Currently only one serializer is set as
5 U, _6 @" v. _) K0 i** transmitter and one serializer as receiver.
( D; x0 r) ^0 l. v) \*/ o6 W: V4 M3 h9 c+ H4 V2 W; E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) b. M& i" d9 _" R+ y0 T2 p/ o z( v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 E R$ h: J. `% o4 G6 t+ U3 c
** Configure the McASP pins
8 U9 h* F3 Z3 q# R+ J** Input - Frame Sync, Clock and Serializer Rx3 ^6 k. ~% @, Y2 _1 a9 i0 E9 {: ~
** Output - Serializer Tx is connected to the input of the codec 5 {: L( u5 a/ ?" l
*/
4 k4 g1 r6 H8 T A5 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ m9 Y9 r3 p% u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% Q; Z1 v) Z0 p4 q5 z4 y% Y8 p; a% R n3 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- W8 i( I# P, h* L1 K3 u* ^5 a
| MCASP_PIN_ACLKX6 u# m+ \6 ^0 ^$ e
| MCASP_PIN_AHCLKX7 `2 k! g1 M8 F3 g$ j% g6 X( D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! a. ~9 J8 y* t+ w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ]8 w* X' a7 g
| MCASP_TX_CLKFAIL
+ a) Q8 a* q. z6 ?; [6 `| MCASP_TX_SYNCERROR. i/ }/ r6 V2 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR U: x! h7 I0 d/ r4 t5 v
| MCASP_RX_CLKFAIL* o; \2 v$ _9 N2 C
| MCASP_RX_SYNCERROR
5 m. n& I( b- d+ x% j| MCASP_RX_OVERRUN);
" M3 @- ~8 d9 m, u} static void I2SDataTxRxActivate(void)
) t( b5 f* K d{ p2 P: S- C8 J" u0 S
/* Start the clocks */
$ v0 X: A; b4 R% V v1 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* h% [$ x1 ~0 S- o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" h/ X3 X8 W" e4 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' y" i6 ~' D( _% S8 h" V0 _- l! v4 u
EDMA3_TRIG_MODE_EVENT);- w$ L0 j! v# h) K x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 `' X' A/ J" {1 k3 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 G# }+ @5 h7 b3 n2 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; w1 V6 D" e5 F* lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 P! `* h$ M, \7 R* |1 x0 q% v5 ^, Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ P. d7 f+ \$ w+ c: Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 V/ z) ?) \0 F$ O$ d- g: S1 P0 b* EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! P; U& S) ^! j- P
}
9 A" B8 Y# t' D7 ^! {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / Q' H- u6 _$ M' ]: W
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