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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ W2 x# h- Q& k) V' Linput mcasp_ahclkx,0 ^1 [9 [3 h5 i2 @" U
input mcasp_aclkx,
9 e' X3 J/ m* S% W$ v& w1 q, `input axr0,5 d8 G9 K5 z. C2 S
# d8 J6 @+ Z8 T+ E
output mcasp_afsr,) a" N( h! {* V& N( V4 N
output mcasp_ahclkr,
6 Q% w, K! E2 Eoutput mcasp_aclkr,
5 [- A- \* @9 r- [7 ^0 Woutput axr1,
9 x2 r: `8 L$ C6 [1 b$ ?' U assign mcasp_afsr = mcasp_afsx;8 f, |5 Y4 k$ u) L, Z# R
assign mcasp_aclkr = mcasp_aclkx;+ q" y: o: ~6 h( a8 B& F) P; s
assign mcasp_ahclkr = mcasp_ahclkx;* Y" [6 p( X* E" ~4 X' r# g/ Y6 C9 C
assign axr1 = axr0;
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/ i% {# O, r( ^6 ^4 e3 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! ]! a4 ~# n* }" v! O a; Fstatic void McASPI2SConfigure(void)7 b2 X, V& p/ I2 ?3 r) z
{* y% v! b: r. H- x- P. L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' m( E& }5 U$ y" ~9 X, |, R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// O0 Z, g% S+ c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ v: P: B# ~# \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" o% c. O# X7 n5 Q2 n9 Y, U" u9 RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, S) |, }( G4 O. \8 B+ v" \' ]) K( f
MCASP_RX_MODE_DMA);3 F5 g% N+ {3 w: {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 L4 v) M t) M! HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 C; D. G3 q3 u7 ^# d: k3 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 Y. z9 C p8 k' j( h" ~4 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ ~8 B! \, @* D7 i" ?! F W5 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" c* n' H5 [2 M# M/ c$ T* qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; H: u% U1 T* e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ a) S+ V9 ~6 v6 U, y( a8 v' w* U, yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* b) g' T* X1 o( r x- bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ i0 |2 \: j& E% Q5 x% d+ X9 v
0x00, 0xFF); /* configure the clock for transmitter */6 T/ a$ ^( ^" o' v- i8 N J$ `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 F: e6 [, ^$ F3 Z {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 N }* i2 z& x! y Q! I. G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ u4 K6 \: w3 R" r2 T) c" [' m
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ . ]/ B+ e& _8 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# X( |3 F2 l+ [% z2 C" hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: p+ J' N8 h) ~1 }& ~9 c8 XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 M8 y, c( m8 o& z) \$ \+ G* \) [
** Set the serializers, Currently only one serializer is set as; [2 S) D* T, _6 R/ w# U( l
** transmitter and one serializer as receiver.$ e" J: ?: x( C$ {
*/" r) B( G8 c! Y' Y6 ?2 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- T4 B8 j+ H7 R/ e# P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ P; j6 l& a( P$ o! U+ ~** Configure the McASP pins / V2 v, D! ~9 r' L7 a
** Input - Frame Sync, Clock and Serializer Rx' ~9 ]5 R9 U+ L( X5 J2 d
** Output - Serializer Tx is connected to the input of the codec 7 [" g. @. r: v* d
*// g8 ?% H8 S) E& z4 O# _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 f* U' t _1 _5 s2 M0 A1 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ J( d) K; j# v5 {" I1 J \- T8 g, s3 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 O5 T' G l+ Z8 f
| MCASP_PIN_ACLKX/ C6 s1 o7 X$ }" B! v
| MCASP_PIN_AHCLKX
5 c: s* n/ f9 v" j! k/ H; h8 c* R& I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ _$ S& ^8 J z; ]3 G( K# |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 g* E% f4 G- X& N- |- l| MCASP_TX_CLKFAIL
7 v) j% m* R! T- A; s% G4 O: w5 m f| MCASP_TX_SYNCERROR& ^; K# Q- J+ Z# V: l4 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * d! u: g' ~( @# L8 }% I9 i
| MCASP_RX_CLKFAIL
7 M% Z! x7 X$ ?( Q! e# N1 Z! X- J| MCASP_RX_SYNCERROR + }) S+ u* }# I. O) M
| MCASP_RX_OVERRUN);- ?/ `0 K. B- ^3 i: _+ Y
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
- B2 b* t% J! m; u* {4 u2 Q7 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ q( J6 ~/ O- ^& t) b1 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 ^4 A( g! n* e% C; J( u) ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ J6 Q* I4 C1 d' xEDMA3_TRIG_MODE_EVENT);
1 }7 P3 g1 N+ Y( HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( t$ }- P: B, y5 d% D3 C! i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 q7 D! n" M. Y0 N, uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) L+ _0 p* I: O$ W: W: p! IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ n: u! Q$ T& b% j" ^2 V5 R! c) `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' m% {4 N, K* R7 @+ b$ h' U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& n) m7 z- c2 U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ o. j8 g% K% s- U5 [/ _& T
} 3 L0 k7 N" j. n0 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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