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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 P- v' h$ L" B" z, h _
input mcasp_ahclkx,
. v' _0 l1 q* [9 ]1 G" binput mcasp_aclkx,7 T" Z# X" }: I/ U+ @
input axr0,- n- p9 v0 h! P
( t8 l/ V" g/ c2 M* toutput mcasp_afsr,
& E" f% I$ {4 @5 |output mcasp_ahclkr,/ ~: J: ]2 V& v: @
output mcasp_aclkr,; U- T' c6 }3 G" I+ n5 {
output axr1,. T+ L) x( a% ^( b9 r
assign mcasp_afsr = mcasp_afsx;
; `4 B" d! j) w# H: V2 passign mcasp_aclkr = mcasp_aclkx;
3 A& A1 a5 u( Y0 z3 N _( j jassign mcasp_ahclkr = mcasp_ahclkx;# X4 F0 x, t8 y& ^( Y3 d% k
assign axr1 = axr0; " z& W% A% F, c9 E
/ E* G5 ?& j M6 R# b' y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 }( N# |& T$ r$ zstatic void McASPI2SConfigure(void)
* k; Y3 A' H, V/ E{1 S0 K! k# {" @3 ]8 [; {% d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" S, O5 E+ U W- n* ~3 m$ eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 p" h4 |0 o( s& `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( |* C8 z1 n' @! m; q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( g% C# _ y0 f" A3 b- d- b3 B1 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" j( Z, x1 A) ^" CMCASP_RX_MODE_DMA);* L& X. `8 v4 T& h& _$ H4 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% k1 t+ C: ^! O& Z' D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 p/ J p; E# s( F0 ]9 ]! p9 n( uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 @. c( C" d7 L! I2 [; W: [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. m/ J" K: p0 X! f3 p; y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 u4 C% y. j8 {7 X3 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" w7 P5 x* b/ z) e j( e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 `. c ?% y1 U6 H6 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Y3 R+ j4 Q' L+ _0 C0 ^# I/ F M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% Y( r" ?9 W/ y9 J1 K
0x00, 0xFF); /* configure the clock for transmitter */: Y; T/ @4 k; u; g! q0 _. w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 z+ E0 o( G+ t3 u- ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 R2 A7 s. P5 [3 P9 r" L, M8 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( Z8 Z/ { e- S6 ]5 {% S0x00, 0xFF);, n' w+ U3 G7 J5 N X3 c( a* I* [8 }
8 R+ V# x6 f& T0 q& v; J+ V/* Enable synchronization of RX and TX sections */
f$ m3 P8 b! s$ AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' r" T- r0 s; q; ^9 h/ v- i/ p# X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ w% T7 d7 ]* S& |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, q5 ~( X* K! D8 d
** Set the serializers, Currently only one serializer is set as# H x6 W3 `3 {1 B
** transmitter and one serializer as receiver.$ C9 C( Y9 a5 r/ ^* [) u
*/
6 x1 Y) f7 D' d& VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 U; u* [5 `% v" iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 o. S4 x$ S8 W! G' ]5 N* t** Configure the McASP pins
& B: u( m: F' ?+ |** Input - Frame Sync, Clock and Serializer Rx$ Y: [$ S1 a3 L, G, N" K
** Output - Serializer Tx is connected to the input of the codec 0 k: r, B1 K1 w. Q; o* N) u7 f, a
*/
5 i9 k/ q s. V( `, jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' m! k, @! j+ S: y+ P1 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ d6 S% S( R& n" |1 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
T$ ~; _/ H" D7 @' ]| MCASP_PIN_ACLKX
# _. V% Y; b0 {2 [) q0 M| MCASP_PIN_AHCLKX' Y8 d& r" R; b4 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: t: K* ^, Y; {8 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 e. y5 |& @2 E* ]3 {2 K6 F7 e
| MCASP_TX_CLKFAIL ) ?; J' X0 N- l0 o& m
| MCASP_TX_SYNCERROR
; ~5 H( [! v, v1 G0 Z+ u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 N% B2 T3 G5 U Z$ {' x
| MCASP_RX_CLKFAIL: t, c1 w+ H" p/ I; p
| MCASP_RX_SYNCERROR
* H5 H) ~- S2 C7 z3 r4 q; H0 c| MCASP_RX_OVERRUN);0 f& P6 p0 G: u- P! u! I! ~
} static void I2SDataTxRxActivate(void)
, d5 a/ A- {) J) O/ U1 }{' L1 t" {5 `, M+ K
/* Start the clocks */
2 x6 ]7 o- Y# }: eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. w& I5 ?: j7 Q$ `+ B* V$ jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 M( Q1 u' N4 v. S9 _2 k8 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# x6 Y' p3 I% v/ e0 x& L) `EDMA3_TRIG_MODE_EVENT);
& o$ r# a5 R1 I) ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 ]& B# o: m }8 J, Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 a- k. X1 O6 }& FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& T4 E5 c& L# L( _: \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& O% Q8 ~' t$ f$ r8 _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 P$ ?: A2 M5 H: s# N5 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* L Z% [! \3 W& P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 n" \, I( [ i( B0 g}
1 i6 e* M/ u1 w0 s& N: l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' {$ g2 F4 I/ Q2 |
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