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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 a& O9 c+ Y6 G# oinput mcasp_ahclkx,
- X, q0 `( ~. ]$ _" {3 k7 Tinput mcasp_aclkx,
' @8 ?$ v: ]3 {9 g' }$ tinput axr0,
* X8 B k/ [. F' W( _8 I7 Z+ T! @; D5 e
output mcasp_afsr,
m$ v" I0 ]1 E5 i6 d6 g8 l2 ~* C6 woutput mcasp_ahclkr,9 L [! e( N6 \ @) X5 H+ ~8 ?6 p
output mcasp_aclkr,% i! F# ~3 h. u
output axr1,
- l; t" U* X+ I" i assign mcasp_afsr = mcasp_afsx;
; a# @; v+ }- s: W8 o4 ]6 gassign mcasp_aclkr = mcasp_aclkx;
+ D' \# O3 l2 D$ K+ g, v" jassign mcasp_ahclkr = mcasp_ahclkx;+ |, _% _- {: G. R
assign axr1 = axr0;
7 G7 X, J J$ W8 M1 v2 `6 {- t1 t- O5 p( m+ Q& C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% L- V. u4 U8 a2 e3 Lstatic void McASPI2SConfigure(void)8 B% D! L" ~* L @. D
{0 P6 U1 I) k* U( Q; z: _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- @ ]8 Y' i% V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ x8 |+ o3 z$ Q' @3 X* ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, m0 t( T, p+ t5 l. ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 L0 f5 k) f+ ?3 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" e7 Y/ @) j: D: RMCASP_RX_MODE_DMA);, B3 r; U- e- K x/ E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* o/ D) R2 U6 ]% t, Q$ x; l; _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 i9 A( _+ J0 U w# P0 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 |0 p9 Q4 h# [$ N) c# I& aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: b( G0 I. [5 p, U7 c6 Q2 mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * f% ?& X" |7 `" C" L n8 S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ q1 t1 ^- `( f+ c! p, w xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' v' @, ~0 l4 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! _& H' J1 e0 O- jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- V2 t$ f, d: V8 b4 N& q0x00, 0xFF); /* configure the clock for transmitter */
, C* P/ m6 r! yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 g+ Y$ O) p t4 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 i* a$ E5 i) E: P! l8 _1 n. d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 T" w: {8 u& M* B% S0x00, 0xFF);7 @6 }7 v1 s6 n% V" q
, m/ X# E7 U( d; G/* Enable synchronization of RX and TX sections */
. g p9 ^/ z" [/ h. uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: k# Q5 j9 g% `/ q* @+ M2 e, KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 D' x# ]1 j+ o! L$ B) U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 P9 h/ B6 X# S& T2 p" J; r
** Set the serializers, Currently only one serializer is set as
: B) z6 _: M [) {** transmitter and one serializer as receiver.1 O5 [2 Q! ] S$ b; f- ^- A
*/( c/ n- m/ v8 t2 w1 u; {* m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; i; Y$ c- ]: T' b6 o- H+ g4 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 |$ m0 I Q9 w1 @) k
** Configure the McASP pins 0 J4 `4 U9 W5 E/ e* x( m6 p
** Input - Frame Sync, Clock and Serializer Rx
5 L6 X% @: D# ?1 x0 X0 U+ A" X** Output - Serializer Tx is connected to the input of the codec
+ m1 D1 \% i7 a, w$ h" t*/
. S; c# t! x* q; \7 N& UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: ]6 Z9 R1 X! ~) j1 k1 W' y9 j+ L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% |! M' N( ]2 v9 ], r6 |! x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% X, [8 s0 N" b+ k, G6 L' ]' ~
| MCASP_PIN_ACLKX
: P( h! D! O# |4 Y' @; ~% A| MCASP_PIN_AHCLKX5 k7 h3 Z! i3 p: h! {; o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) \% R1 g: A6 B/ l" [ M5 k. t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 Z+ I0 J# G' Q' T S
| MCASP_TX_CLKFAIL
- Q- O) R0 X: y( k" i3 `7 w| MCASP_TX_SYNCERROR
9 k' a, o& L# _% P+ X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 J8 j4 p; h1 p' H
| MCASP_RX_CLKFAIL
7 R% _8 N1 L& b0 p| MCASP_RX_SYNCERROR ! u! Y! ^# o: E/ ]0 Z
| MCASP_RX_OVERRUN);4 s% Y ?9 g" a( f% e7 d
} static void I2SDataTxRxActivate(void)% ]% |; Y( m4 R- Q6 A4 V
{
2 c0 V" U2 p5 i2 k# T/* Start the clocks *// }+ `! D# g, k- l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: ?- m$ ^1 a5 V9 V; M( W2 e8 Q" ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# ]& i( T- L$ T- e& W7 t# [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ v6 ^0 t4 d+ z8 QEDMA3_TRIG_MODE_EVENT);) _( I0 V d0 m% C, j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; E5 ^9 W& L) ~+ aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( {$ O0 ]& m* q8 a1 p7 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( w( [$ j7 F$ kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 u9 q) r" ~$ e B# m9 l( J9 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# `/ M# n5 }0 | p8 U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- \( j1 C: Z. B9 I7 }. W, Z3 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; [; m2 g( o0 v0 n+ ^0 W% G
} # R- k G! `0 c+ L/ u( L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - d) A* z7 S7 y& U
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