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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) o1 l/ }- s9 i- H# ^
input mcasp_ahclkx,, x1 }5 `2 d) q: P
input mcasp_aclkx,* T2 t# |4 ~& ], A2 V
input axr0,! Z a3 a0 M8 i- l: }
0 o! k' `$ V3 B% r! q
output mcasp_afsr,
, z/ r+ M, f1 Foutput mcasp_ahclkr,% a9 M. ^- ?5 [5 X, e7 F3 w& u) G
output mcasp_aclkr," g8 J" Z1 A( W& Q# p- C
output axr1,
' r0 [4 U, e7 Z; {9 q* \ assign mcasp_afsr = mcasp_afsx;+ _( i( f3 |- O( j/ U" `# `1 x
assign mcasp_aclkr = mcasp_aclkx;
7 `5 G' ]" ^/ U4 Rassign mcasp_ahclkr = mcasp_ahclkx;
" M0 Q7 j% b6 A! Q& U+ eassign axr1 = axr0;
' D; P3 D( `9 _9 ~% N' ^) R n% I: W/ T: @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( f% B7 B" ]2 Z4 K$ l" ostatic void McASPI2SConfigure(void)+ `& b' e& _4 l
{
2 z, Y1 n3 {+ w" Y: ~/ |3 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ n% T' `2 r6 ]- w8 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 v) {6 X3 q" x! j4 v7 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 ]# O0 \* r" Z4 _) EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: k1 X/ i# I- h+ M0 ^+ qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ H6 [. I$ i8 f4 O- q7 X. L6 V
MCASP_RX_MODE_DMA);/ \ C0 `) i2 |0 w$ R2 X& w2 g& N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ` _$ M. {; _9 w1 r0 A2 bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) W" b) n f f- C7 YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! o/ Y# l. k9 K: D) I- XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, R5 U# }. F- ~) p) O3 M5 V! bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 y; G- N2 D. o9 P! N+ s1 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- ]+ i9 n# l4 e! q, g1 g2 y# ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 x4 l1 Y6 s3 \) b8 y3 ^+ F$ H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + |9 ?! O/ ?1 {) q5 |% a! Y& V+ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 }4 Z7 \0 |' `2 F0 S4 Y6 J) P0x00, 0xFF); /* configure the clock for transmitter */
2 y4 v' p5 y) f& `) VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* `8 X( m8 T: J* iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ }$ @9 Y/ e, k3 B# F) RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 E1 S3 y* F: j1 b5 g0 [; w
0x00, 0xFF);+ V1 O1 e0 }; O" l# e9 C
: x- J9 b$ X- s4 I c y/* Enable synchronization of RX and TX sections */ % e8 M! L# d) h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 ^8 A4 j( T+ w% QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% `6 Z) `$ O4 M$ g% y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 E/ r% S% o* T2 N& h
** Set the serializers, Currently only one serializer is set as
+ N% E4 {8 S0 _- L' u6 T8 \; l; w** transmitter and one serializer as receiver.
. T7 n3 X+ b/ j* ] X*/
0 N3 ]* b& G/ mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( B4 L0 q4 Z. ]9 y! x4 @( a5 k3 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 J0 x, M( U) R2 H5 v( l o0 E** Configure the McASP pins
' c( ?0 n T j6 Z4 y' F** Input - Frame Sync, Clock and Serializer Rx
/ N% o; g1 E$ Y** Output - Serializer Tx is connected to the input of the codec ; n4 v$ B: K, b1 F5 w
*/
( S, N2 G% h& s+ q) kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ @5 Q: ]& q s! X+ t) i, f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 S$ k8 O# z, A6 H- B8 Z k( cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 ^# m( ]6 j8 e6 S
| MCASP_PIN_ACLKX' L' ^ M4 J5 I. p! l: K
| MCASP_PIN_AHCLKX8 y. ^0 T) w" z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# J/ j- y" L# h( |( k4 _! y- F6 R5 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 @1 R5 b q) L4 d# ~1 y
| MCASP_TX_CLKFAIL 4 R0 ?" L9 X2 m* v( t- [
| MCASP_TX_SYNCERROR
* P/ Q' ?6 c2 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. T4 r: X8 e2 O# j- S| MCASP_RX_CLKFAIL- i' `2 e1 F0 ?* N/ Z' A: E
| MCASP_RX_SYNCERROR
/ e# C5 o' H/ Q. E; y1 x| MCASP_RX_OVERRUN);8 f9 b1 U; T4 j S+ D
} static void I2SDataTxRxActivate(void), o. }- k J# I( X; D; U" O( Z9 C
{: O: b! S0 j. W6 B1 g. K. g" [' d
/* Start the clocks */; |0 c, J ]( F( Q% h7 w3 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, F- T7 P- \8 b2 C2 W/ hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# x6 s7 Q$ f) t0 I! a" X- y3 O% wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 J' O4 i* R( y" E7 u0 S- P
EDMA3_TRIG_MODE_EVENT);
* H) K7 m! E: w7 ?: O$ s- UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . V% |0 ?( B) w( b" ]; C* R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ E& I2 x1 `* t+ G/ |" r8 d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: e9 k" x& Z% V. k' {. S& p1 }" `9 [! nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# Z0 x% w f' J' K% }1 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* |& S2 {+ G5 P/ O* Z; @" N2 i j0 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 c) ]$ W2 O! {3 `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- m* |; A# V1 y3 p% N
}
) S% K! k/ l4 W" m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , j2 D7 @5 y1 }8 Z H
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