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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," f0 X. E: @/ H( ^
input mcasp_ahclkx,
7 ^# c3 O+ M* ]3 C! s7 Qinput mcasp_aclkx,% y, i7 g1 ~2 q2 U" _8 h
input axr0,% `) U3 \9 s, B2 j/ o
' S/ L9 J" E! C* n2 Z
output mcasp_afsr,
7 v* M. ]+ \; H) M2 C% T6 Moutput mcasp_ahclkr,
: B( c2 t6 S/ ?7 {# S) woutput mcasp_aclkr,7 {$ J' Q0 o) v
output axr1,& G! i( K0 T) x. N* q X
assign mcasp_afsr = mcasp_afsx;/ o% H. Y. q+ ]* `( ^' A
assign mcasp_aclkr = mcasp_aclkx;
. T9 _3 S- E* x' g2 Iassign mcasp_ahclkr = mcasp_ahclkx;, l9 {; L! `4 }7 a9 A g3 r. u
assign axr1 = axr0;
) Y# ~1 a+ s7 a" d1 V( @/ j# w* ?1 K( z+ p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 A$ F/ m p2 Q) [! ]static void McASPI2SConfigure(void)
8 `0 T2 D4 D7 C{) u' W9 ]! j, i+ x: D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' s5 d# R) f y: z# U7 R! S$ L: v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, |& y) G |" h( p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- i$ ?# Q2 K6 F Z3 W* F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 T; ^) }1 n3 \: l( mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," ^9 N8 j" u8 i! p8 z
MCASP_RX_MODE_DMA);
6 I6 y4 d+ S, F+ t9 S0 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& W" y5 T: W# X: r; T$ h/ w! q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ T% {1 z4 k1 T2 L0 O7 l* d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 Z( B& I [* L2 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 h& L4 o, Y" D2 f* w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 S& ~3 e# ]% ~8 D( @9 |, |- UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 q5 i) u! B" y) N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 u n- n" A3 }* I: X% d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Y# Q# q. ~* Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: i0 I4 x5 C5 U# e: z# Q0x00, 0xFF); /* configure the clock for transmitter */. d8 C' ~( x! S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 o5 u4 p0 A* o/ W5 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' i. L# E* T. u- V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( C, J7 k4 v! m+ z Y
0x00, 0xFF);
2 X/ U( _$ M) M1 e! m8 ^: d$ }7 y4 }
/* Enable synchronization of RX and TX sections */ v" i. A! h. T0 c4 v8 p. F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. I) k- _9 i) F* M+ k3 M( O9 b; OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ \, {+ }0 ]; l- v# xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* g7 \7 s, G' n, ^& D- x** Set the serializers, Currently only one serializer is set as" c9 B9 u$ q5 U A
** transmitter and one serializer as receiver.; H n3 y, P, `) P
*/' [ G5 Z" }6 j& |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 A/ X |4 j) `$ Z* H/ \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# o2 f' f- M' K# R4 N% f
** Configure the McASP pins 3 }5 C G& O0 m( K$ |% D# W3 S9 \
** Input - Frame Sync, Clock and Serializer Rx" N: N+ V( j* l( W( D, F
** Output - Serializer Tx is connected to the input of the codec
% X2 m8 S7 Q1 g8 |/ ^- S*/7 }3 r8 S T7 U5 N; z9 P. w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' A0 K. G. R. v9 r3 U' [$ P" zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 | K/ ~0 S( e. G' S+ u: y. T# }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! b5 [, R0 `3 }! g7 r
| MCASP_PIN_ACLKX
. b5 p! v5 b9 J% O8 q| MCASP_PIN_AHCLKX/ U& j1 B' P3 q! @4 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* M8 T+ p, Y. i* \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # i# h5 Y: ]% K- q+ {
| MCASP_TX_CLKFAIL 2 C7 {( S# C# R) R
| MCASP_TX_SYNCERROR$ F: }/ F+ m. E+ P- y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / x7 c0 ]+ z0 r
| MCASP_RX_CLKFAIL
9 @( ]* e$ j2 @+ J( N3 t| MCASP_RX_SYNCERROR ' R4 O5 X7 `% {& B9 w
| MCASP_RX_OVERRUN);% x$ G! w1 R. ]# j1 z' i n1 N( m
} static void I2SDataTxRxActivate(void). r, k4 |; W1 H7 e' e' y, M
{, y, W9 G+ y1 Z& o
/* Start the clocks */, e& V8 E! m( a: m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" f. K- z1 [; H+ S& kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 F2 l; q- c" t% P4 j8 } E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 D! U- n3 m! u! Z/ k6 nEDMA3_TRIG_MODE_EVENT);# F- H( r- j# @: @+ i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 B- m' B7 [$ dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' _# ~& D" D3 ` P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; ?& `; w6 A) S3 a6 i, E. SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* H' |. G% |; M/ d$ @0 p1 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ g4 U% f! ]4 e2 O$ F1 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 Z ?0 [0 a' K3 P6 c$ NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 t: \$ P: z4 Z7 ]& ]
}
$ ]5 C3 u! F8 m( h k* p K0 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
3 G( G9 @3 W3 {$ t- d% { |