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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 M7 u- p6 x+ T- J& A' ?; Xinput mcasp_ahclkx,
2 E- o3 D8 Z. P8 S8 E) }$ Ainput mcasp_aclkx,
" D* Y. w! G1 _7 r$ P- L8 c* c0 ginput axr0,
) W! b. q7 q8 @! z l. Y4 c- O1 n$ a2 ?* K2 `1 S
output mcasp_afsr,
2 z w* e" q0 y- o! f" A3 ?9 Ioutput mcasp_ahclkr,
! i5 X% k* A4 U4 p4 w& b; joutput mcasp_aclkr,
! p: b- x2 ~, o' Houtput axr1,7 f: t3 E* h. j7 A2 I
assign mcasp_afsr = mcasp_afsx;
9 }: l* b7 p; H' Z$ U1 B) o/ tassign mcasp_aclkr = mcasp_aclkx;
8 K. f X7 r& Z6 F4 P. S+ Gassign mcasp_ahclkr = mcasp_ahclkx;( N! @* u$ M9 s7 c5 B, l( N/ Q9 m
assign axr1 = axr0; 3 W. e/ z3 ?2 z! U+ D2 o
5 U, J( X, ]. m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 Z( y5 q5 T @
static void McASPI2SConfigure(void)- x5 x$ m a, }$ `9 A
{
* g- d; k& }7 Y6 d: e7 {7 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; y3 _( t) D7 e% f% s# `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" d3 _2 L8 u! b) W& \" \) G" Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* Y. f' r" f) F$ X. YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// x7 H1 o" x- g/ b" h* C! r3 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. E: K1 a. k; G. {+ T/ f8 ^, d% }
MCASP_RX_MODE_DMA);7 z' G# T/ C* v. N. B, W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! C. A. o0 @: w( q. O9 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" u) p) G; U' m5 g& e z- _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * t+ }+ o+ M* t8 X% w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% ^: z! \" J9 w5 c$ x5 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 r" e$ Z3 V8 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 b1 n7 U, C3 z# P$ T' aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; |; \/ W; m/ m z/ d' {. x) n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); u4 f' Q3 z) \, y2 {; Q+ Z6 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
^( ~$ y! X1 ~$ s: H0x00, 0xFF); /* configure the clock for transmitter */7 f! J1 t! x( I9 Q# M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* D" @9 }# |: D8 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ ]7 F5 ?4 P" q3 h9 f; P3 gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ i+ q+ t( [$ a7 _0 p) ^( Q9 [
0x00, 0xFF);
( F+ n$ D, H: e9 h) C# X: B! |
; k8 t( _7 l& t8 x) ~# ~ b& ]/* Enable synchronization of RX and TX sections */
- o. s, J2 i0 Z8 n0 Z( XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ S' p1 p" X5 a; } y( l Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 q! v% W3 t& J. Z6 P, y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 y3 m# U" ^- R+ O; l
** Set the serializers, Currently only one serializer is set as
j. b2 @- @8 r7 z- f** transmitter and one serializer as receiver.
4 ^: {# F# h& o" W" o*/
( B) k9 }: ?- ?8 N" G& tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 M% U) L! l7 o; {) ^5 Y2 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 [/ `5 {9 a) |, B** Configure the McASP pins
0 M$ y/ u7 n* I+ m** Input - Frame Sync, Clock and Serializer Rx
& ~5 \; E. _5 e" S** Output - Serializer Tx is connected to the input of the codec
' D& @# c& z2 w$ d2 h*/
. v* r6 f* d B0 e9 J ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ L+ D6 g! o4 n4 U# q( cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# D! s2 ^8 X1 N" M H# l! fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; w% N( `7 M6 J/ ]| MCASP_PIN_ACLKX
( }: V" p% b x; Z( h| MCASP_PIN_AHCLKX: x; j4 h1 P' c: I4 u! ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 e( r0 h, } r' V( l+ _( SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 t! f3 {, v i" e" Q
| MCASP_TX_CLKFAIL
6 \. o! B, |6 M) ]8 A7 i9 c( }| MCASP_TX_SYNCERROR+ Y& N9 t) t4 @% q/ i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * k4 l( A7 p1 p' z7 t3 Y0 L& q& z
| MCASP_RX_CLKFAIL
2 C2 x' L' J; r# }| MCASP_RX_SYNCERROR " h! j7 V# h+ Z; V7 j
| MCASP_RX_OVERRUN);
. [! H3 B8 m$ j K% L} static void I2SDataTxRxActivate(void)2 E7 m. ?6 e9 H- S& O
{. B; }' u D/ t; b
/* Start the clocks */+ p/ s5 k) V* S- z1 T. m3 y! W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- M1 R% X1 [3 I8 ]( a+ }$ sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& [/ Z7 [7 t/ \) ~! _% I5 D" VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- t$ m7 @1 M1 C, {; s, D! v- lEDMA3_TRIG_MODE_EVENT);
. p* S( `& c" }6 M0 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 y8 @) ~* U! P& Z7 k/ U$ a( N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. A! W# P5 @& f5 Y5 I# ~% L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* ?; Y2 ?# [$ e' G, Z, SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' o1 l( c' b3 e6 p G' Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- q# U2 q) j9 v+ z4 J% U: ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) [. F% n# W3 r- W. Z# V3 i( LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. |9 F" @$ Q/ ?+ v+ l} + k* u* T- o! s) I& Q; U( e' t5 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) ~1 a- A1 n" d e& z M
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