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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# F$ A3 e8 t& G! ~( x$ p$ [- _
input mcasp_ahclkx,# _1 w8 V0 w8 v% [, [
input mcasp_aclkx,
+ H; d/ E3 s+ N/ `7 ^ _input axr0,
7 i z9 `5 ~3 x& l7 B0 `
$ a/ S( |, d$ Z1 doutput mcasp_afsr,
# Q/ @ C9 E7 W0 K) Poutput mcasp_ahclkr,% I& p# x/ j# g2 ?# N
output mcasp_aclkr,+ B3 S: Q) ^4 Q
output axr1,
2 z3 ~* ?' _2 A; y* c assign mcasp_afsr = mcasp_afsx;
) ]$ b) B6 e! q: _9 Yassign mcasp_aclkr = mcasp_aclkx;
3 O2 R: t7 J; xassign mcasp_ahclkr = mcasp_ahclkx;
$ n/ [" m' X' E' F' d" nassign axr1 = axr0; * Q) o$ N9 }# T# q
) u _0 d% x6 {! v* D: m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % S7 _; f0 m) c0 r3 g5 t* k# v
static void McASPI2SConfigure(void)
. z! d( S: \/ W/ _" T+ G{
+ ]# u& k/ M$ X OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& z' `" \ l( r% i7 q) xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- R7 h3 q" Z8 k6 K9 S( ~( @5 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 ?" B7 S& q. G pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 L8 f. p$ y# q6 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- n& B3 l3 L7 p9 Q* U" x( FMCASP_RX_MODE_DMA);4 @2 Y# z& Y! k7 ^ d7 i" F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- }2 O% h; H" \! {+ |6 n7 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 H, O" ?' X! D- ]/ RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 `4 e& i; ]- R5 H. h1 `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; m8 S* W |6 n+ y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% G8 r8 x3 T1 X0 X( A# zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, Z8 r1 X' t# mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 m `. H8 Y0 I" ?) XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: `# u% f! a& b6 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' @* Y7 d+ v" j( A# q. A$ r
0x00, 0xFF); /* configure the clock for transmitter */6 q7 k+ S: P0 f% G' V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" x& b6 X" d& C X5 C" P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! y0 J. K* K. z& F8 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, p, N6 @* n; T# @8 N" ]% T/ a& e" V
0x00, 0xFF);! n& _3 {7 \' S. l$ ]0 X" ?& i0 c
- y4 R. s, R. r4 U) ~
/* Enable synchronization of RX and TX sections */
5 T! f9 k5 l3 U O8 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* T! ]% d: O) c. k# c& o4 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ _. l. X" Z) }+ o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! u! h; r% p. Y6 U
** Set the serializers, Currently only one serializer is set as: A1 z) Z0 ^/ M( l, U1 W5 G
** transmitter and one serializer as receiver.
) v8 x) D: p7 a B*/
8 d& C8 o$ g. T2 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% q3 s5 `: Y' l8 s7 e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- {, l o6 ?7 k# _: p! d** Configure the McASP pins
: E& G- x1 |6 p/ W; k, C5 [7 k& E** Input - Frame Sync, Clock and Serializer Rx$ ~( Q; U4 E; _ e: E
** Output - Serializer Tx is connected to the input of the codec
6 X# m7 I: S9 D0 m*/+ }: V! r: n9 P( ~+ i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 @* F4 @6 H% E: g/ T* T( C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 @ R. e( ]4 O! P, h2 I2 tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) M9 w& u4 S( p; x| MCASP_PIN_ACLKX7 y3 v+ o$ _( A& u: U4 F
| MCASP_PIN_AHCLKX5 O8 k1 l; s8 \& V, B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ L5 Q: ?) @1 n0 h& s4 Q Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. F9 Z# Y% Y# w| MCASP_TX_CLKFAIL & o3 J# |( G( L6 y: f6 j
| MCASP_TX_SYNCERROR5 x% {3 C! ~0 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % w8 M; c7 p% x
| MCASP_RX_CLKFAIL2 J, R7 U9 y. z
| MCASP_RX_SYNCERROR + `' \& s% c0 j, y9 k) e
| MCASP_RX_OVERRUN);
3 ~$ E( O$ ~$ | ^$ m# \$ `" v4 F} static void I2SDataTxRxActivate(void)
# ^6 g D3 _; f! n! F7 O* d{
, e$ v7 G( K& }9 D2 i* o7 E" k/* Start the clocks */3 u' P+ D) R9 K e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 v6 @3 n) R# Y6 e" y3 v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ~) @ _: h1 z' D. ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 Q$ k& j4 b( u! u( V4 z/ bEDMA3_TRIG_MODE_EVENT);9 Y x" v9 h5 S _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 N) u$ m( c/ ]3 s9 s* M/ zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 }0 p- u1 G& i3 b5 ?1 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 Z0 p1 a2 N) Q& u+ H1 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* z" F& R" F [; k- \/ pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 u" w, D e4 B/ a X4 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) N" | }( K0 P. h& ~# v. f" v( P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( z2 L$ M4 n. L7 Y+ _} p, |2 Y6 T- Y9 `( L" L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ d% p% `9 u ^$ v' U
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