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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. D/ O7 _8 d* q" F
input mcasp_ahclkx," x( r: y' O9 L/ n& y
input mcasp_aclkx,7 m/ F3 A7 m- v$ { j2 J
input axr0,
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output mcasp_afsr,4 t3 A) W( d% ^9 I+ i: [
output mcasp_ahclkr,# V# N0 t1 E# D$ [! h7 t/ L
output mcasp_aclkr,0 s# `! ]0 a( b& J) w; B( X
output axr1,7 w" b$ R8 P. u( }" j) p0 W
assign mcasp_afsr = mcasp_afsx;
% R$ s) s8 r9 {assign mcasp_aclkr = mcasp_aclkx;
) k: C V8 R- y. {3 Lassign mcasp_ahclkr = mcasp_ahclkx;
o1 [! E/ c. w5 [3 f. j, Gassign axr1 = axr0;
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. e! C) ]5 }; E& r7 `: C. X& \* z0 t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 U/ Q6 M/ Y9 F2 l' r* Q$ G9 F x
static void McASPI2SConfigure(void)7 N0 G5 h3 ^4 F# B# W7 g
{$ U9 U7 Z* j( G+ |9 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" `- y: }6 `, S5 |( \8 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 w0 ^: u2 f( ]* AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 K; q( l. G* M Y9 K- ?/ }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& O! Y9 `$ a( EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 |, @6 r& y3 s% jMCASP_RX_MODE_DMA);
$ J. ~0 L" H! e3 s( o2 B. XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 a& s5 E6 w; e# a% a2 c4 w( PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& U) O* g9 M- ?) U( y, j% {, AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# U- I) y% p0 J) UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 C' k6 w7 F4 N j$ P5 ]1 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; e6 z/ M8 e+ D+ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% O0 K; N+ w* lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! i: y1 W( b% x- d0 H/ {2 z% _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ Y& E; C, s# m8 ^1 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, D- p* a, f) ?2 d" p' J
0x00, 0xFF); /* configure the clock for transmitter */: V8 p3 B1 C2 R# L5 L5 P( [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 [0 Y- v7 A( C. o% ^ gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ g* T. Z6 H2 P+ y6 k' _' J/ {8 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% B5 m4 I2 c( Z
0x00, 0xFF);9 ~+ C/ W1 h! _0 Y& Y
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/* Enable synchronization of RX and TX sections */
3 Z7 X9 n0 R* K/ Z6 C+ Q& h7 qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! V( v# c! } n4 q0 t7 ^8 @6 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 Z; T; O9 Q- q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% O0 l& Y( @) G* G( U! r1 x3 F
** Set the serializers, Currently only one serializer is set as4 e$ k0 a" ~9 E" j4 _4 U
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 r( }- c( J Y$ a' V% oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( ]) V) \* D0 k** Configure the McASP pins
$ g7 {2 E( o( d. t6 B** Input - Frame Sync, Clock and Serializer Rx
! l+ s; X) m6 e: k+ S% L4 S** Output - Serializer Tx is connected to the input of the codec
/ l3 F- l! C* |*/7 u) ?, Z. N. Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 j$ T, p* @" `7 E" T6 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 [8 w9 p* {3 p; V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' n! z# r- ~2 E! b/ v$ V# ~0 X
| MCASP_PIN_ACLKX
0 I2 ]$ l8 W' k. U; {7 J5 k8 M' M. A| MCASP_PIN_AHCLKX+ J; C t4 d$ c b4 b& L9 I. k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, l2 L5 d/ x$ l6 g9 e( iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 `( G Z! l6 J. U& V| MCASP_TX_CLKFAIL
- F% Q0 B! z4 ~2 Z# s: y! q4 z| MCASP_TX_SYNCERROR% S" p% j% W5 l- q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 n) ]2 W I4 p. Q1 H9 N: H9 o
| MCASP_RX_CLKFAIL+ _ F) N7 O0 d' Q+ E; f9 p! Q
| MCASP_RX_SYNCERROR 7 g7 F& j5 s3 T% ^$ }
| MCASP_RX_OVERRUN);, U" c$ c+ ], z3 H7 t4 D1 D2 U+ Y2 m
} static void I2SDataTxRxActivate(void); j, T; @! k/ y
{7 v( U8 ?- @( Z$ _3 M3 w
/* Start the clocks */
1 U2 i" Z5 x* R4 n! @: C$ `! b9 s+ FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 |( q7 ]8 s$ _& F/ l5 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# ?0 m0 r. f. X, T3 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% c4 i. I5 W8 T9 a: D# A6 M3 N
EDMA3_TRIG_MODE_EVENT);6 V8 f6 V7 a5 z$ `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 e; Q* M1 R k: g& O5 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 u1 v2 ~5 E1 M/ ]. ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 a4 b/ ~, C. @8 {% y' KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ x4 s3 u$ x: v; z, ]+ z: ~3 ~7 S& u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, z2 N$ G/ ~3 a4 l1 H& L) ^1 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 A0 | L4 T/ B% i+ k) N8 l6 ?* T7 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( a9 P4 ^, O+ J! Z
} ; N, g. c2 o: h- s# @& [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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