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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) [9 F3 l" J! x) l* w4 v; f
input mcasp_ahclkx,! b$ n7 T1 P- v. b+ l
input mcasp_aclkx,
, E9 B' ?0 ^- r3 q/ sinput axr0,/ { a+ k4 {+ Q5 Z' m( z
- F# i( {1 I9 Z. Q) G4 X( noutput mcasp_afsr,
+ ~3 X5 r4 u( R7 A0 Q0 h$ foutput mcasp_ahclkr,, _! e' Z8 e6 S5 r R$ j7 D; D
output mcasp_aclkr,7 y( v6 Z/ c: k/ F% h. q5 e( ]" B
output axr1,: }6 L/ e) X* K& Y# a
assign mcasp_afsr = mcasp_afsx;
! c/ S9 G/ F: A* e3 uassign mcasp_aclkr = mcasp_aclkx;
9 f8 @$ M- ?8 s' q8 {4 e9 Uassign mcasp_ahclkr = mcasp_ahclkx;
6 t/ c- u1 [- c) @assign axr1 = axr0; " `, t9 r4 g; [7 j+ L
# p# Q' s$ Z( }( [# L7 _. z& E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% [, o4 Q# Z: M, h8 Tstatic void McASPI2SConfigure(void)9 }& {8 Q% J! A0 o* y! F0 `
{5 B) r6 S g, J; w0 M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* a8 E0 z# T# U6 I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. `5 F- {2 f/ O; [5 oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); s- a" W. q5 y- W H2 h/ E- G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// c* w" D- P2 ~+ }2 d( r3 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 v5 A( ]) _+ X7 a- a# h3 H$ `MCASP_RX_MODE_DMA);# x" N G* v1 F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( S( g/ I+ \+ g2 K# p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 Y: r l4 D4 I4 h5 }3 ]% {1 E" o+ A5 G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 a b0 }) M7 X6 B9 o( q; uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 E5 ~3 z3 B9 F9 S; J' H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 l6 R6 q/ V$ IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 [) W: t" d- ]1 d% ~9 I" M( u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ h$ o0 M d$ S1 P/ N% F! OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( w2 ^$ y2 w& Y/ p' ?/ P0 \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 V( M0 @# @* {8 B$ N4 r' v) c
0x00, 0xFF); /* configure the clock for transmitter */
; E( M0 W5 ?& e" LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# ^- D1 d1 {' K3 m0 d( c; n4 qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / A5 C; ~ ~$ L) ~1 W( F. j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 e. j ~* P; w, h O R+ n; V0x00, 0xFF);2 l& V/ o# G" D
5 L) Z+ E. g/ f) {2 K# M/* Enable synchronization of RX and TX sections */ * u) Q( K7 C7 N) Y. f0 R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 W3 ]+ ]% B" l( wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 Y G- \, m7 y1 _% i# c% W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** U/ I! W' J$ h; w# \1 q- o
** Set the serializers, Currently only one serializer is set as) Q9 b4 C2 ?* k4 Z6 U% l
** transmitter and one serializer as receiver.( l# o# k& `' K5 S, `( G" `
*/
' p2 Y" h+ k: ^ d9 L8 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 c7 W, o0 M5 e( ]; o+ r' cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% E& t# s0 g3 ~' o, t9 [* z7 K
** Configure the McASP pins ; ?& ]) e/ _* F) `7 b- c( ?, P
** Input - Frame Sync, Clock and Serializer Rx- f) M3 a1 ~) P# T F0 b! M' @
** Output - Serializer Tx is connected to the input of the codec
+ N" R) q' g# q*// s# ?; B, f3 A, u, F! e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: ^. N- p* v, T$ y# Y9 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 I& o& G& L# x7 F( t. u; ?: h C$ qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ p- d, D, t! K4 m* u4 a| MCASP_PIN_ACLKX
! F3 y% H8 P: p5 Z7 \| MCASP_PIN_AHCLKX
0 t' K! G2 n$ Q9 U% W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ i! A3 A6 w7 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & ~# G2 p$ p1 a: h. Q* T, `
| MCASP_TX_CLKFAIL % F" b1 o8 z, G* p$ T) A: u& d. Q
| MCASP_TX_SYNCERROR
0 v+ h' a4 Y7 P1 Z/ l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. Y% O/ m9 Z$ T| MCASP_RX_CLKFAIL8 J' V2 c' d+ t7 D
| MCASP_RX_SYNCERROR 8 s% X" D# C/ ~/ O9 L
| MCASP_RX_OVERRUN);' e, `; R1 B/ J; l, i
} static void I2SDataTxRxActivate(void)
! F4 \" z. ^" Z! Z9 f+ q! Q{
/ m5 j$ o8 \/ x6 P+ N/* Start the clocks */
3 W O) ]5 k% e! l/ ]: [/ UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' e3 s0 W5 v( F3 b) ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& G+ {) ^+ F5 Z# A7 {0 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* H3 @5 U) M7 @: n; V$ d
EDMA3_TRIG_MODE_EVENT);0 [3 \% x4 ]2 L5 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; C( r% q% T% P- r: P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 d% C$ M2 M! cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 x1 [5 Y# E, L4 T& v! CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* g7 `: R5 z {/ _8 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 j+ `) K" ~8 F. BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ]3 u& w1 D" J# Z+ R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 X; ~: i) ?/ j1 D) H
} 0 _- V V1 ^1 g# {, D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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