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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% m Z: o9 ?$ k, ?4 `" M1 Cinput mcasp_ahclkx,1 R' w) X7 r$ b' A
input mcasp_aclkx,
6 r: {% v. R% m$ k' p2 \5 d7 I; p2 p" S. dinput axr0,/ s$ p8 }4 ?3 o! h! v8 ?
$ G: t l! }$ Z& m' X1 F, p+ m l- ~output mcasp_afsr,3 ?. P; e, X$ K3 F' P) l; Q
output mcasp_ahclkr,
% }" \- N ]4 W0 |( Goutput mcasp_aclkr,
+ i1 q3 c7 ~, X, K" ^7 G+ U3 ooutput axr1,, ?0 x- b X$ @( o0 l% l0 ]4 j
assign mcasp_afsr = mcasp_afsx;
. f B' c4 u6 h, U0 V% y# uassign mcasp_aclkr = mcasp_aclkx;# g6 s2 l( s7 r
assign mcasp_ahclkr = mcasp_ahclkx;
: j: `3 m; c& G6 h/ e) Q$ |assign axr1 = axr0; : O* Y* V" d, k0 s. X0 ^
}# r9 O3 Y; V' d# h+ q$ A5 y* D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. |8 }) R8 q7 {: {2 S! q- e% x2 o. ~$ R4 ~static void McASPI2SConfigure(void)# `7 R5 H& N. w1 t' {9 b
{' b g0 C+ j( j0 V- b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ `% }: _; Y0 N% B) m; S; hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// X; W& k6 ^- l4 F2 Q: z2 ?! A) c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ x- E9 b+ V/ ^2 y9 Y7 ^- A) dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. k* w6 Y8 X: `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 \" M4 m; z, G% q: W. h( s
MCASP_RX_MODE_DMA);
9 v$ H" d" u, R' l cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 f- T$ }1 j! E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 Q, ?6 ~+ Y+ ~9 E; B) V4 G B0 ~# p! k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( |5 d' _, O4 r" C5 I: s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); q+ ]! _1 `/ [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) M' `: ?6 k, B+ B7 V, U. J+ W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% l- B( V/ s0 u( q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) v1 d/ w: i0 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 @% c' S& y; c- m5 a1 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* u. l. F1 [- f) Y! v9 J/ k
0x00, 0xFF); /* configure the clock for transmitter */2 F0 P: }0 a, F5 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 Q: v; @+ w% [; YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . ~+ }7 \8 `: [ `/ `5 z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, Q$ u& Q) I' v: B! v1 {" I0x00, 0xFF);' L1 O3 Q; \$ F
8 }% ]& E- l: A/ f& s/* Enable synchronization of RX and TX sections */ ; A& L$ \' ^( R2 D2 y, Y8 E& X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: h. @3 q- u& J7 i$ g. e7 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 Y ]/ C: C' u+ |4 n4 N# J4 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 k$ p& A7 w( ?8 W
** Set the serializers, Currently only one serializer is set as9 c& P( p" g" w4 Q; ~8 z* y
** transmitter and one serializer as receiver.
% v; w* B* V6 e5 }4 K# {*/
( t( O) y M+ V; o) uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 |6 O2 J' v' H$ hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, v7 K" N" j+ O1 \6 Z# M0 v** Configure the McASP pins
9 U0 m4 ^7 L1 C. ~# k8 J** Input - Frame Sync, Clock and Serializer Rx/ R: n2 [ g7 _; J2 \) L
** Output - Serializer Tx is connected to the input of the codec 2 } Q4 z3 y; y9 @4 A) b, W" Y
*/$ U" ~7 d6 l6 |7 ?; H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ u1 w8 l0 G, L- V1 {3 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- L4 R* q& f) A2 d" J: J+ Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 m. B% b* E( h
| MCASP_PIN_ACLKX6 j+ ? y% b6 Q% {
| MCASP_PIN_AHCLKX
- {& ]" B5 f) s0 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: G5 `) n \8 a4 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 b* Z7 r# V7 [9 S: m
| MCASP_TX_CLKFAIL
) V5 S, R+ u! s8 e( P| MCASP_TX_SYNCERROR
$ v- ^% O8 ?8 X0 ~9 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# w. ~& y: {7 I8 H' F9 j| MCASP_RX_CLKFAIL# Y0 r9 z! s$ d$ n! K# ~. b
| MCASP_RX_SYNCERROR * X, y1 h Y% r, u ]3 f7 G
| MCASP_RX_OVERRUN);
1 _2 |8 {- j9 y6 ]# |! T} static void I2SDataTxRxActivate(void)$ j7 ^# ~6 R3 b
{
7 z: C* i7 }, b& v t2 y' o+ d# Z4 f/* Start the clocks */
6 P' o# p! f. s) t0 C+ VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 p$ c, P: x/ l0 K8 F, F4 T9 U; jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: J9 I' i2 ~$ q2 s) I% H3 L) q' hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ~. |: ]/ s8 U7 t0 C# V" xEDMA3_TRIG_MODE_EVENT);2 x7 k$ W+ X) ]$ [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. ]7 ?$ W# U" B+ y. U% cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# D J- ^: c: r& [: d N0 _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 x5 g! X# @. s/ s4 O' FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* S' b% o( R4 i7 h: g0 V# ^; Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# b2 ~+ [7 T$ [* X( b: }" n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ l6 x3 }7 i: I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ ], M/ }5 Z) p L# [4 T
}
+ X+ S/ p9 g$ }& U, N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ e/ J7 k5 d' W- x5 g! d8 o9 S
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