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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 d/ n m N$ c$ R3 \- G E1 b
input mcasp_ahclkx,) ^# e& M: h1 O( s$ ^. J' {
input mcasp_aclkx,
/ [% O% U. f4 Y2 p) M+ I! Zinput axr0,& f8 s% B2 R+ y0 k1 ?( N
]: P k' y* l2 e. n" Noutput mcasp_afsr,
9 a: O+ b/ C& M: ^& r( s' Xoutput mcasp_ahclkr,
9 O! z8 Y- J7 i8 l* {output mcasp_aclkr,4 G3 ?0 v8 j9 N' M$ e" D
output axr1,% G9 q2 l/ n# i! T( {* c4 g) X/ i
assign mcasp_afsr = mcasp_afsx;
* _( j( h3 B0 Y+ Yassign mcasp_aclkr = mcasp_aclkx;4 e6 `7 j% v# V: S
assign mcasp_ahclkr = mcasp_ahclkx;
s4 h0 \2 [( m' vassign axr1 = axr0; & y* m, S. h5 ~
; Q% C) k- Y; P) }3 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ r& j- O/ K% i6 C' n* \" }static void McASPI2SConfigure(void)
/ m' f! K1 W3 Y2 {* |& D{
: \8 b e0 F; uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- R9 F0 g# W4 [) xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ E$ H9 a7 h. ]. J/ ~8 t/ W9 P7 W; C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 t3 _0 O; ~, K* V! B+ M ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; B/ O% `3 `/ S* m$ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! `. _5 z5 Y/ p- q8 ~MCASP_RX_MODE_DMA);) z/ |8 S; |) |# u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 w6 c8 ^& ]2 I/ ]6 kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ ?. j& I9 k% T6 i5 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 a R, `* y8 a9 Y0 `6 ~+ [: o( f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& [9 E, {: ^( g9 G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( o8 {, e. {7 _/ R" O8 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 Z p# @; T3 d6 E' H4 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 h& k0 ~, c4 C: h% pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 s9 D: K2 ]9 n- UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, h8 w) l/ t! b j# ?4 H! X% e4 [0x00, 0xFF); /* configure the clock for transmitter */3 W2 Q' z: i8 P5 F3 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 r9 ~9 t( S& M+ D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; L. L8 L4 |$ mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; j/ I& w/ N7 r, f0x00, 0xFF);$ u8 A$ j1 U6 `+ j- L: e0 {
- d) X" y( @, l2 u& I5 A/ M+ c# @/* Enable synchronization of RX and TX sections */
5 M( A3 L. z7 Z0 d8 e1 Q" {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ y/ N9 l, y3 d# s! b% a9 Q/ T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 T6 {1 {, ~7 h3 g5 R( ?! nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& M+ \1 X4 a0 ^6 t; h* q** Set the serializers, Currently only one serializer is set as
" }- G6 u* q% F. V' R0 f4 s, m** transmitter and one serializer as receiver.7 V0 T5 s( P1 I4 V5 ?) } A) s6 I
*/
! d( d+ S- \, I& x% x* ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 N7 h5 X+ f: o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* D0 w+ H0 M$ p/ A; F `
** Configure the McASP pins k# g8 ]1 b" L+ U0 z. N, H: L
** Input - Frame Sync, Clock and Serializer Rx7 x) a* r( O+ p9 u+ j
** Output - Serializer Tx is connected to the input of the codec ) _1 q% @$ ^1 d q
*/
+ D2 _2 D) A! L, S5 T( @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 l, X8 M9 N: Z( n; wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; M1 G. n* v2 t+ t1 ^9 |5 QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ |: @ Q9 ^9 w/ n% v+ N# z
| MCASP_PIN_ACLKX; M' Y/ ?7 p( O" A. N
| MCASP_PIN_AHCLKX
6 n$ F2 z! N9 C0 @9 || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" U/ Z- V! |1 {6 z) O7 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& N2 G6 X6 W3 D/ I| MCASP_TX_CLKFAIL ' u) E2 f+ V9 b- K; n. M6 N
| MCASP_TX_SYNCERROR, r* m! q" L0 o: f( {: [- p& \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% @" ~: t ]5 g. Q3 i| MCASP_RX_CLKFAIL
9 b- u( N- l$ T| MCASP_RX_SYNCERROR 0 `$ i3 j7 e+ |- ^
| MCASP_RX_OVERRUN);9 |6 I4 p) m& x
} static void I2SDataTxRxActivate(void)8 E% e; y- w9 l) K2 B, \
{' S* ]+ d- L, ^( S
/* Start the clocks */
* ^4 \) @ ]: D/ y8 g2 f" {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 _4 k2 X% |1 g3 J" }8 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 W: G: T E7 Y8 j/ dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# u) _5 _2 J% K+ l- e
EDMA3_TRIG_MODE_EVENT);
7 H& J8 |+ {: x& O) i5 O1 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 V4 Y& g0 L' C" B- uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 I w7 m" n' V" r' R( E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; g; x9 e1 P7 l9 q" r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ G% x6 h& \) J: k8 _2 {( l; F% e( O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, [3 P) w3 }9 y9 IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- @# j) K5 N9 Y; Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 h) z+ {) d5 {) n} % x% a1 h; J, V8 H4 C' }" B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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