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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( A" R* O! g# N: p" minput mcasp_ahclkx,
& C5 y- o1 S" A. \ Pinput mcasp_aclkx,
# B& R8 J$ ?; rinput axr0,8 o+ \! M/ t' n* ]! |
* G& ?! `1 B* voutput mcasp_afsr,
& ^% N R% w' Qoutput mcasp_ahclkr,
# S5 l" L6 {* |output mcasp_aclkr,1 f# n2 ^ x9 G) Z2 k/ G# G
output axr1," h9 o% l5 J* b. }, p& y2 N
assign mcasp_afsr = mcasp_afsx;/ R1 O. C7 G# _, g
assign mcasp_aclkr = mcasp_aclkx;6 Z- K, E- D1 @2 t+ U0 x
assign mcasp_ahclkr = mcasp_ahclkx;- a2 w" S# {2 ?
assign axr1 = axr0;
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0 ~9 i" m8 U: h5 F3 T% T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# f0 d/ {& V, m T. J) Fstatic void McASPI2SConfigure(void)6 P% ~* |5 g3 e+ L
{6 W# X0 e j* d- c& H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 S; Q A6 a# n1 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! o) X- o: n& l# D7 D0 O+ X5 q* zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); S/ r5 o! M& @+ i6 N y8 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
I, S9 G9 a: r+ {% |. v' TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" [% H& D0 @* @" f: kMCASP_RX_MODE_DMA);& e* P+ s6 b" k1 f* p1 X3 F7 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, W2 I6 }& ~ ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& I/ ] f8 O5 _% O: Z0 L6 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; n- a( W2 t; ]" @: T; v/ }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' Z' z5 B0 B4 T4 E" H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( ]6 a& t! }2 Q! }' {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 X# f9 }! s" u" F7 Y4 l/ |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 P" x9 s' t) G8 |! M5 ^3 b, y; @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" Z" ?( Q; `$ d. S% X% ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
^8 e) n" g1 {% n" c5 n- r0 B. y3 D0x00, 0xFF); /* configure the clock for transmitter *// o* C+ Q5 w, E: k' @8 M4 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ Z' |; K. n3 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + G! N) D a A/ N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," x) }) I* d; Z! Y$ I1 X
0x00, 0xFF);
( `( W# ]0 P+ I8 U- @1 x7 j- K$ O" j; X7 u
/* Enable synchronization of RX and TX sections */
; o* _$ u9 ?% z' O0 x" lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& |/ K, D9 J, jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. u6 k5 H2 F! N& b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 T* [; P: @: M4 G$ R: i: r. [+ U
** Set the serializers, Currently only one serializer is set as
3 M: c6 P+ d9 O( g** transmitter and one serializer as receiver.
7 f- a3 j$ H7 z/ @) g*/8 a9 [% u* x, H- K* H7 ~: \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* Y7 A/ a8 q9 B; W z2 e. {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 n, _0 T; p! T
** Configure the McASP pins
! W' \& S ?* y( T** Input - Frame Sync, Clock and Serializer Rx
' }. v w* r2 K* Q: J: E" b! ]** Output - Serializer Tx is connected to the input of the codec
V% \ e: Z; ?' N& K" ^*/
/ f/ W" h2 A6 D7 l5 \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ q3 x# K" N2 `& O; s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 C, h/ H) W7 Z6 M: q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 B/ P% g. o2 \+ O" W* V' k| MCASP_PIN_ACLKX
0 E+ O3 `4 R! s| MCASP_PIN_AHCLKX
9 z) ^$ p6 v! z# G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) T% d' J/ s7 S m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* [; n' K& P. c. a! T| MCASP_TX_CLKFAIL O# b7 a( n6 s
| MCASP_TX_SYNCERROR
! z/ ^( @8 i) @( @ }& c. [' b& O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 C* k+ `3 D( T7 U5 T| MCASP_RX_CLKFAIL
& v" S1 |7 F- h| MCASP_RX_SYNCERROR
7 c; E$ ]: X7 M* _+ X: Z% }| MCASP_RX_OVERRUN);
4 I! Q+ t+ U3 C$ J% Y6 C0 l} static void I2SDataTxRxActivate(void)0 M* E, z" R5 u8 M( R2 P
{+ ]* p2 m/ C1 P9 I
/* Start the clocks */! I) h. {+ f( A) q$ b" d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); M" ~ I% U8 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 S8 B y' Y( x3 s/ D D% g& ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 k2 ~- G$ P5 r9 x0 h- T0 Y
EDMA3_TRIG_MODE_EVENT);
' C1 L/ a7 E; F0 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 S6 L7 A. \/ g; Y& g% M: u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
y! E% Y: i. l3 s! [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* }. O7 ~8 O3 [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 ^* e' r. t& z0 \, s: z+ t: J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 s. t8 g: y3 T) L8 ~! NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; @9 p: w" @9 U Y8 M1 \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 N4 H4 _2 @; j: h
} 7 R; L# j9 f% d* Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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