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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 \ e- s8 G9 V0 n! W+ ]input mcasp_ahclkx,& w! ?# ?# Y0 J
input mcasp_aclkx,
0 b5 S1 \ {# d- rinput axr0,+ L7 W( l1 \( }; W0 ]% R; e& F1 k
) f" y) X* R+ z9 h
output mcasp_afsr,
* S3 p$ `0 Y2 T# L" _ routput mcasp_ahclkr,# g3 l* G& d3 O+ I
output mcasp_aclkr,6 I5 Q3 O% a, f- ~6 E
output axr1,+ B5 A3 b* F7 N A5 U5 T
assign mcasp_afsr = mcasp_afsx;
+ S. ^3 R1 _( [& e- Hassign mcasp_aclkr = mcasp_aclkx;
, E+ G* `- E. d" }5 S: lassign mcasp_ahclkr = mcasp_ahclkx;
, B& f9 w8 Q$ I+ @5 M+ r& }assign axr1 = axr0; # ~$ B, d/ J f
3 @/ c, z, i' d" g C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 m) M0 n1 t7 V6 B& K9 u# u
static void McASPI2SConfigure(void)
7 r- B+ Q* ?. O: e, S4 }9 w{
( ?# }! a8 V9 T! i6 UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 [( [6 k' J) V& }1 ], x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' @- n: J4 |+ v# x- J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' d/ T0 W9 I7 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) U$ o1 O' Z2 X5 D' W \7 \) lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 b! U# `% E2 L
MCASP_RX_MODE_DMA);
o- T e4 P( x" s' c; D/ d/ O2 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ @- E5 F" w$ L4 A( wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// p3 F, O0 S* N0 I# d7 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 B9 l- w, q. [6 V8 W1 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ G6 t8 x$ w& U# K( jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' B) [9 s9 T! H; g# ]1 J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// a) f, J. |' m) B- d$ c; h6 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 [" J% f+ b( _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 O' ^$ T! C) Y0 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, Y) ^$ ~1 Q* y# d% o q4 y; h
0x00, 0xFF); /* configure the clock for transmitter */0 K9 u% }, X) @ G$ x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 H* l& f) O2 H [) _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; v4 ?+ [# \& h# W( ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; m: [# Y) Q9 T$ f W- Y7 }0x00, 0xFF);
2 `; g) d9 A# I
; i3 t0 @, `; {) ^2 R5 r/* Enable synchronization of RX and TX sections */
- }) s6 w( t" q' u! qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 X, }' z& C0 ]! ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ w0 `7 ]* V! b) `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& T. R, _# E2 e' w$ F/ O |
** Set the serializers, Currently only one serializer is set as
9 b: F7 i- s0 t) |1 S6 z0 M4 u& m** transmitter and one serializer as receiver.- o6 m% U4 V, R
*/
4 H" i# J- W" x$ vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 u' B. G2 _% y7 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 v% C' o7 ?( ?! [9 K N) x% {** Configure the McASP pins 6 v6 c, t! L- D
** Input - Frame Sync, Clock and Serializer Rx
+ `1 V* L' J* o [! |! t& d** Output - Serializer Tx is connected to the input of the codec
/ @8 V* G/ ?, @: m*/) L6 f6 _' \. Q3 n, L+ _. n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ S" q- A4 _% s0 k, R& W2 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* l: n1 o C2 y2 Q$ L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# Z' _% ~6 }+ \$ a2 o
| MCASP_PIN_ACLKX
2 i2 M2 N( s) U| MCASP_PIN_AHCLKX
* V2 i8 J$ D6 o6 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' @ F0 D# O& a6 x9 m( AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, G5 `" A# @1 a7 \| MCASP_TX_CLKFAIL
' r: ^% e. l' w! R0 V| MCASP_TX_SYNCERROR6 \1 ]* N: ^& I/ ]* w7 H; J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) m) Y8 X0 u! u- a5 q: j
| MCASP_RX_CLKFAIL. |: K1 r# ?) U6 D6 ^+ Y4 E2 e
| MCASP_RX_SYNCERROR 1 Q0 d Z8 |3 T
| MCASP_RX_OVERRUN);, N, L' s, J' j2 {5 ~
} static void I2SDataTxRxActivate(void)
; x% f- I( L( E0 d{
0 A1 o6 }1 j' v, T1 e/* Start the clocks */& T0 x: l( o6 a% `7 K% }# k8 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 x6 i8 ^& w/ H2 D4 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 r( N) u5 W* w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" ?1 M3 j7 q: e) dEDMA3_TRIG_MODE_EVENT);
& S% s* }" r& ?, O7 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ S2 k$ z$ O2 _+ v2 x( z- z) QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, m0 [1 Q# ~3 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! _3 \( v: ]' A7 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, f/ i) i4 o, x- t/ U5 _4 t Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 W. h: U* l$ m( j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' p* e x$ h: F+ I, S9 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; {6 h& U5 k6 T l( `% P) r; R
} " b, |! k( m5 P( A( U" d: J% ]% {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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