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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 T# a, \* W! e5 H% [# a4 Minput mcasp_ahclkx,0 a' u& O# G8 ^6 F$ C
input mcasp_aclkx,
2 v2 w& Q" f9 V# linput axr0,
- M9 o; t( y- S( O
& y$ ]; e+ M8 routput mcasp_afsr,
% W& a/ r1 s5 G3 n/ } S, E5 koutput mcasp_ahclkr,$ S; R) c4 Q. v
output mcasp_aclkr,
% s# |$ | b. y! F& routput axr1,
0 g2 q5 ?$ y4 j( V3 { assign mcasp_afsr = mcasp_afsx;2 U7 d; |- l) l) t2 ~* A8 b4 M
assign mcasp_aclkr = mcasp_aclkx;
c5 a/ b0 S/ V7 {9 [1 p; rassign mcasp_ahclkr = mcasp_ahclkx;/ N/ P& I# i6 A B# h
assign axr1 = axr0; $ w2 E4 V" _; F: I
n/ [5 z2 ~: r" [4 _% s- @! R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' @! P$ ^, z9 [' Gstatic void McASPI2SConfigure(void)
& ^6 J( M4 }1 @0 K{6 F5 }: m, a+ n2 `9 A1 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 q F. g: B1 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ f/ t0 \; E2 s( zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! a6 y$ C- F3 D0 u: k. K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 \5 l/ G5 Y. M! }+ X8 B& ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# R8 b3 b; @# y3 u9 b4 B% p) m$ e
MCASP_RX_MODE_DMA);& z5 y, K' W6 c' a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. D/ G& Y5 B# C4 E4 K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ m9 K' w- ^! g, |. {" X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 U8 ?2 y1 ]: b0 B0 n( GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ B& F6 L) D& u2 V. _- n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 S8 t- A$ B" nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( Q) R9 N( g3 B! G0 E3 k, cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 S8 E' y" b7 s0 S7 jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' X8 o) a) M; S1 ?% T* F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( x& y) M, J4 K8 y! v% o0x00, 0xFF); /* configure the clock for transmitter */
2 u. Q& C$ U2 `9 p9 `" i) uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 y( d5 J9 p0 J+ fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * k& g% N5 Z, P7 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 N+ c% T3 t3 S" ~, Z9 p
0x00, 0xFF);
6 |, d& j6 R% p* j C4 e7 Q# B8 {! M4 C, a
/* Enable synchronization of RX and TX sections */ 0 H* U" e9 c- X" h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 ? A) A9 T% `% E8 s5 B; U }2 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% x8 l$ r: L5 |* v1 U6 y/ i" @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! X2 |* ]; W/ O3 p6 U4 C" y6 x** Set the serializers, Currently only one serializer is set as
' @/ Q! X B4 N2 @% A7 O0 j- d# s** transmitter and one serializer as receiver.
3 K, [( N* }- I: m*/2 s6 r& ~, X4 R( e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 h0 L" b, |* q$ j" GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) l# J$ ~ d& }/ o8 _$ T" Q {2 ]** Configure the McASP pins
: S6 Y+ A* o3 |! ~+ d** Input - Frame Sync, Clock and Serializer Rx& `. G! v/ ~; u
** Output - Serializer Tx is connected to the input of the codec + H- S6 Z% E( A% T
*/
8 p4 X2 Z L+ _! WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); n6 A d" p2 l' _6 r9 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" k/ r3 P! N wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
?' q$ |) b7 t1 U" m1 h| MCASP_PIN_ACLKX
, ]3 B6 _8 P. s| MCASP_PIN_AHCLKX
, m' w0 p$ z' g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 M7 [: ]* h' M, r0 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 _( R: Q, U" o& f& t' o8 y8 X
| MCASP_TX_CLKFAIL
& V4 k) a- @8 |/ } P5 j# ?| MCASP_TX_SYNCERROR
, R S1 r% ^8 p' S" y% R5 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ _4 d8 i; e5 l: x; C+ [* k0 v| MCASP_RX_CLKFAIL
- ?/ y5 |+ Z! Y b" b. t2 J| MCASP_RX_SYNCERROR
2 c# t+ m5 H+ k| MCASP_RX_OVERRUN);% p5 m3 e7 N. U- i
} static void I2SDataTxRxActivate(void), w. m& s: g0 N0 g: m z: |
{
6 ~9 t& H8 V' G; V& F% r/* Start the clocks */& F" J! e" G( y* {5 W$ e5 ?$ e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- h: }; S2 T% O6 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 a" g! d+ v4 ?, A6 F: I8 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- b. H# Z8 J; G8 Y) a- i% T
EDMA3_TRIG_MODE_EVENT);
+ Q4 ^, V/ c9 [4 e- oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 H8 ], P# [: B* Q& B2 O& dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. h5 g' q% m @, u, v3 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- Z3 e, l' {! R: L4 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# f5 l6 t x+ v: r. }8 [' K& ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- K, K' {* z2 m) l) @: l- z) mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) T( m5 n# J2 [' T# o+ S3 y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( ], M: q' l! u {& X8 I/ }' x}
+ S" _. `7 v) f2 L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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