|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, u! N4 ]' V& V( t2 P. u8 Ainput mcasp_ahclkx,) n+ V7 W) f9 ]" o5 Z
input mcasp_aclkx,
, }+ Z; G- d/ Q9 S, Binput axr0,
/ P! ~# \" H4 B6 `, b5 ~; W! p. o% S, | |
output mcasp_afsr,
& ?: f* P5 r2 ]2 t3 q. D$ ]! Eoutput mcasp_ahclkr,
- I4 Y% M$ U+ H* H' R, \output mcasp_aclkr,
+ b% w* z6 }5 O. a F( [output axr1,
/ R0 s' D5 t0 I) {4 Q3 M! P/ w assign mcasp_afsr = mcasp_afsx;1 u* R% R$ h; a
assign mcasp_aclkr = mcasp_aclkx;
' G3 o' l: q0 o6 A: Zassign mcasp_ahclkr = mcasp_ahclkx;
, G* G0 ~7 V- k/ A0 j( i: sassign axr1 = axr0; 3 r: j3 l( E! k
0 j: P6 Y5 w A/ p4 d- E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 ^5 L# Q) O! N( Y7 Jstatic void McASPI2SConfigure(void)
9 \5 k$ C4 O4 e2 Y0 D4 ]{
( F. w# t* q3 P: x- c& fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 ~8 Q+ A1 d. w+ \+ u0 g6 F7 [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# h& \1 H' o- K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
N: g$ X+ `8 J! k) P* OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) Y6 n3 ]- Q3 W+ ^7 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- n& G: J( L* ?% WMCASP_RX_MODE_DMA);7 Z- w8 Y0 p F; c; m7 w1 {5 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 Z5 g( H- ?$ S8 g9 `8 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) C1 p+ Y$ K" e% ^0 ^4 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ d6 ]5 g* _: M! O- v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" M- U% z+ \ a$ z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - H3 Q# @$ s% y4 y/ e) m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% a$ L& l6 U( W* n) B; U6 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) j1 t# o! a; Q9 l0 a9 u8 ?, u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & b d. r0 [- @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* v/ n4 x& J9 O) i
0x00, 0xFF); /* configure the clock for transmitter */
- `: g2 w4 O8 ?+ p/ y% U( sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
I! o' W1 k7 R4 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 n) V7 p7 J% P4 u) J" H) ^) R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: n# k g+ x0 L1 V4 N4 F0x00, 0xFF);
0 y6 X5 o) }/ ^: X: u! y! B$ \5 D* W0 L% A. m% t3 ~3 {
/* Enable synchronization of RX and TX sections */
' U) c8 W( i( D C8 W: t' NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 @4 H# f6 `9 Q6 B t2 v6 [. }7 |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# A- |2 b2 j) F! c" c; EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 ~1 A$ w+ G% [: t** Set the serializers, Currently only one serializer is set as3 W3 p% @" A& O' e2 i! p
** transmitter and one serializer as receiver.
* `5 }1 o2 ^) Y4 n4 h. Y8 z" S*/% b& \5 \: ~ g4 w! Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 a4 {: d) Y* D5 X& _! S8 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 U7 h! g# N4 ~4 t9 {: l
** Configure the McASP pins
; b* s) E3 U6 R+ C) J** Input - Frame Sync, Clock and Serializer Rx+ t( w% t; E: [* g" i0 n$ {* U
** Output - Serializer Tx is connected to the input of the codec / Z$ z' @! R# ] F9 d
*/. l6 A* J5 t3 R& I1 `) B$ m" A# \! R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. B3 t1 ~! `+ C: K; g- ]2 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& j7 E0 ], C! gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* c: E8 R, O' h$ ?| MCASP_PIN_ACLKX; b0 K2 K( t: u
| MCASP_PIN_AHCLKX
$ i* b e; _( L/ v; P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 r& ^& M: [% [. H# [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, M) V: u8 O" u# z9 a q/ y* V/ ?| MCASP_TX_CLKFAIL , J7 r1 W7 w1 Y9 S5 f
| MCASP_TX_SYNCERROR
. n9 L& x) y2 X8 @2 a0 T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: n$ e( M- K- N6 ^| MCASP_RX_CLKFAIL
# v9 r0 J1 `- A- o) L' V+ j| MCASP_RX_SYNCERROR
. l/ F" l2 d7 ^0 P' d. B: D- Q| MCASP_RX_OVERRUN);1 W) I: {/ B9 X4 S$ r& T
} static void I2SDataTxRxActivate(void)
R) _1 q7 r7 ~{) Y: ]# r9 a5 o* U" P; b6 k
/* Start the clocks */( g6 v. |( i% [' O+ V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 b; o7 X7 e9 Z6 t0 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) L3 C' l0 O3 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% L3 Z% |5 A2 d8 }8 [
EDMA3_TRIG_MODE_EVENT);
$ }! ?2 J" |6 h2 m9 ` i @. MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 Z& e" k+ ^" O2 I. z. z) V% _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) e9 ]/ x% z4 h" X6 S: c/ T. e# O2 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& r! a$ y; }, t8 y) kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" g- V7 }. _; J5 ?1 l+ S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) Q6 x1 c6 k% MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, B+ k9 o: s8 Z, @0 L1 \9 R5 {! Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' b- F o1 { X
} ' l* b+ i5 g" D+ d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& p& Z+ s; F U |