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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 H! x- M: W3 U( h& O- s. q/ r4 F6 _input mcasp_ahclkx,1 ?4 L0 [1 v# l) Y+ Y& a3 A
input mcasp_aclkx,
+ Q5 u+ m' U' z! s! r! Qinput axr0,( J5 l1 P+ ~% j8 g# `
) v3 V' v' y" b) O9 |4 joutput mcasp_afsr,% ]; R- O0 b) F3 m3 V
output mcasp_ahclkr,
2 T2 q5 ^6 v" ~" Z- d0 Boutput mcasp_aclkr,. l2 }% d, [- v- C( I' Z
output axr1,
9 A7 r% Z8 G: ~, E1 Y assign mcasp_afsr = mcasp_afsx;$ @3 r/ o2 O# F! X! _! I9 \
assign mcasp_aclkr = mcasp_aclkx;* K# b( Z+ b- a% A1 t; C+ L
assign mcasp_ahclkr = mcasp_ahclkx;
0 y' n& O5 u) ]8 T# N+ k7 wassign axr1 = axr0; 8 |9 h, C! L; z. o
9 j6 x0 L1 R+ q7 W# j/ [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 {6 S& h$ k; ]8 p
static void McASPI2SConfigure(void)$ C* Q. i6 R% b6 J
{/ h y( i+ B B" Q3 x/ g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: ]) v& |$ [8 F$ v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 ~; _% E0 V. ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ t) n1 n5 C, ~9 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 L3 ?# A% ^) ^' ~1 O/ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ x* @ \* B7 d5 S0 u) y
MCASP_RX_MODE_DMA);
3 F: o0 b% @% N( SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 F' u4 \ x% l3 p0 M' v* e. C. J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* }+ c+ c+ l5 F+ U6 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! v" F. _0 l! u; CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ w* Y8 r$ ?0 |( f' u( m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + r! d6 K) O8 L( t6 L7 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' l0 D. i' q O0 n! E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" J l! ?3 U7 }* x1 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 p& O9 Q) B7 {4 X9 ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: t( ?: ?, b; i/ z6 I
0x00, 0xFF); /* configure the clock for transmitter *// @7 T3 s( d" n& u8 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 e+ X5 C0 `1 V4 v3 s0 _3 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, p$ o* j4 G) x" ]! W. P& QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, F, R" y) |' v4 B0x00, 0xFF);5 F o- F, Z# K7 s3 I/ V
. M# R: ~2 u I, j N3 n- u/ @/* Enable synchronization of RX and TX sections */
' F. e8 X/ a3 W$ ?/ Z& S1 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 V4 |+ y. I# PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 J3 J4 r1 l0 D. @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ }3 [, a: {3 l! |9 j** Set the serializers, Currently only one serializer is set as
5 c6 c _) e' ]8 r** transmitter and one serializer as receiver.. X; v) n3 V* V. y9 o$ f
*/* r7 A$ E" T8 {) ^' i! {% ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( c, G3 @1 @% K0 F6 E5 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: Z+ S. Z- L. a! G5 ]/ K( b
** Configure the McASP pins ! R9 y2 b6 O' O
** Input - Frame Sync, Clock and Serializer Rx
: M5 D) a1 X) l3 p** Output - Serializer Tx is connected to the input of the codec 7 e0 @ { e$ l* d$ k" A
*/6 w/ W) w# k9 A; o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
z- K" r$ i7 X; k+ C$ bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 Z @/ p8 f, _* y1 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# I' N% G( V% o# t
| MCASP_PIN_ACLKX4 x$ S/ E: p6 D
| MCASP_PIN_AHCLKX6 T4 q% _; B2 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 M) N% s# o) ^' z4 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : w( M; D2 [( Q" {7 Q! X
| MCASP_TX_CLKFAIL
; t- D' i! I: {" S| MCASP_TX_SYNCERROR
_2 V" t' n& ?. r( v6 _8 [. p5 w7 _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " A2 h. K6 E4 }# R. G. |! L
| MCASP_RX_CLKFAIL
- q, Z, G" u4 @2 V" \3 L# U* t$ L| MCASP_RX_SYNCERROR
5 H7 _4 W* I" T/ C4 B& K& c| MCASP_RX_OVERRUN);7 N' k( s5 o5 ]
} static void I2SDataTxRxActivate(void)
$ `- N K/ G/ Z7 p. w6 J z0 u; ?{
" z, `% q+ {1 O7 E+ b/* Start the clocks */
0 n1 c2 h! J- P$ |* K! BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 P5 ^# W. P- m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 Q2 Z- ]% `4 J& c- tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, R8 x' Q& H& gEDMA3_TRIG_MODE_EVENT);: T; p$ K5 Y% b% c7 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. e! G, o7 x% d! @; S% g8 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% D6 L; b/ H- f+ YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 }; V8 {8 l( q, MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: N P) L1 D& G) J* |8 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 Z/ ~$ b$ u: K. b( U0 g% K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' ]0 y5 c* C# e# b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! s" R B$ ~- \4 `3 A2 k f
}
l0 B9 Y5 d$ s. A& }" T/ _5 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
1 @3 ], M9 Q I6 m3 l" L+ q6 a2 T0 [0 J |