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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( @" c4 p5 _0 o- w# F
input mcasp_ahclkx,
6 O8 c4 A0 q8 J) r6 X8 Linput mcasp_aclkx,1 \- g, U1 E% u$ y D3 Z. O1 L
input axr0,+ @% S/ S% h3 R- `& D
8 W' _6 T/ h1 `3 |& [5 Z8 ?0 p% @& J1 Q
output mcasp_afsr,
) u0 O! B, l! J; ]( { a! k J6 Loutput mcasp_ahclkr,8 Q: G6 B2 u) Z1 u
output mcasp_aclkr,
& p5 I- y! \9 Y3 voutput axr1,
7 h# C1 [; c- J# G% a! W assign mcasp_afsr = mcasp_afsx;
+ U# w; D( {, m% Z% Q' passign mcasp_aclkr = mcasp_aclkx;: L; X0 i9 V9 Q; H
assign mcasp_ahclkr = mcasp_ahclkx;
0 X) l: m0 N* }1 oassign axr1 = axr0; 3 J, X" y# H5 b0 Q: A3 i
# J: p r, A- P* \/ @1 Z4 Z0 h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( [# R) k) t" z9 |( U9 Rstatic void McASPI2SConfigure(void). D; o- c( E0 N: @9 P
{
0 r' C, m& O+ cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* i0 k$ Y* j" k, X, T# n! o: }* B! G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- X: W# f$ c7 S) W& J5 `2 c7 u; |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' G& Z1 d1 C0 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 X1 K9 @( S& j5 C3 N( F, JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 P: N3 r0 r# R
MCASP_RX_MODE_DMA);3 M6 t6 C2 @1 B: x# x7 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: U' p' I- p% K( P5 p0 N$ P% oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; u9 j- U2 ^5 M% ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 f/ ^2 V1 @, T: H$ _' cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- F6 C0 z+ v. x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 ?3 o* r- }, G- W6 i' IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
g& c1 L e3 v- _7 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- `3 R @4 [4 k; H, E7 A; C3 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: Q3 i) T& {2 Q& V9 A3 J/ HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) N# _, L: @/ T# J! H0x00, 0xFF); /* configure the clock for transmitter */6 w1 t% ~& p; e5 O- Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! d4 `2 o' [2 z/ h- S1 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. _! N3 M" }3 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ n, G( ?- z4 m2 ` {
0x00, 0xFF);$ b. x% D3 I0 ?" L" o$ p
; x) _+ A0 ?4 G3 f" d8 {! [
/* Enable synchronization of RX and TX sections */ K# ^" X2 [6 U) j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ b. G+ B8 k/ C: w1 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! C g( q8 x4 M5 I4 V' kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& \' ^% L" Z, u2 z
** Set the serializers, Currently only one serializer is set as
( e1 I% B* S) |+ M2 j7 H5 F- ?** transmitter and one serializer as receiver.5 ?6 M% x! p5 M }( j
*/
5 Q K: T( V4 s% H8 h- b; RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 e# e( s# r4 w: j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! Y7 G! o6 L. R* d2 ?" @
** Configure the McASP pins * O4 m) L. U6 s7 N
** Input - Frame Sync, Clock and Serializer Rx
7 A' ~9 B+ p# E0 D" J% h5 E9 K** Output - Serializer Tx is connected to the input of the codec , l. n2 L, E) `
*// J1 b t# O/ `# e G: S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); |8 w3 L* Q' y2 O- j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- e6 B. u+ v' t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: @, [7 b7 M0 x* C6 B2 I| MCASP_PIN_ACLKX
7 |& ?4 a0 }: L# U* [| MCASP_PIN_AHCLKX( _1 {8 i6 W$ V$ T. j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& K8 C, k+ x/ {" UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 E6 W) H. y! c$ K6 K
| MCASP_TX_CLKFAIL
# u- Z& j( j& U6 R+ s/ o- C1 g! W| MCASP_TX_SYNCERROR
2 K, v) ^* A6 i) G* s# B( j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( h; F4 C8 z/ B& ` b# V# F
| MCASP_RX_CLKFAIL
& _, d5 {+ l& k& U2 d( W3 r| MCASP_RX_SYNCERROR
7 }* }" x0 H2 p| MCASP_RX_OVERRUN);
) t8 A7 h: W1 T9 v; u$ ^} static void I2SDataTxRxActivate(void)4 j5 P7 H, u7 G/ E7 X
{
+ a) Y* A2 d9 N) l( y5 q* Q/* Start the clocks */
2 G7 s1 M0 k0 T* }5 i9 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 z% y6 c8 M6 _) k* E4 u' N9 b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# Q6 ?6 U; A( B& ]8 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& f8 U* p5 ^) t' L. D2 V7 o: f
EDMA3_TRIG_MODE_EVENT);
# v. W: l7 c9 ~5 \$ v( XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + Y9 B8 z. P) R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# P8 H0 w q0 G& g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
}6 Z1 F7 A4 T3 W% c3 X6 V- h5 ^: rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, w9 _: W8 U3 ]! a; E; r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- J' f# g9 B9 A" ~* W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 F" k5 g* n5 j. n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ B- U2 ?! s8 I3 m- a3 ~
}
3 s# T$ I0 a( ]% P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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