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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 b0 X$ X+ ]3 ?- ?, V2 W
input mcasp_ahclkx,0 L' Y3 N( [5 J5 l* a
input mcasp_aclkx,
' \. N0 L' p/ ^0 i( Iinput axr0,+ W& u/ |- o u- z& j5 D
5 B9 o2 p! U. e4 i0 Ooutput mcasp_afsr,8 t- \: V7 d( w& c# u2 { g. h
output mcasp_ahclkr,5 [( R7 M" k- h0 Y( i) t0 Z; Z
output mcasp_aclkr,
, G6 g* f8 T# ]* D% y5 Houtput axr1,$ }# ^$ \- o. Z) k5 L8 [% h: F. A
assign mcasp_afsr = mcasp_afsx;
: @5 x( ]7 R# cassign mcasp_aclkr = mcasp_aclkx;$ j# J4 d. i: x
assign mcasp_ahclkr = mcasp_ahclkx;$ w! x Y ]6 V$ u
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) X8 \+ A9 g1 u% w& Y9 ^ }3 i
static void McASPI2SConfigure(void)7 P7 a { h8 ^# S
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 W' w, P" C$ @0 r! i BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( B! F' {9 F% M/ o* _% nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 S9 X5 k& }$ S$ R3 a; ]# z$ _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ ]( F2 `- ^* D# ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ _0 j f- _3 ?, `% D- `+ i. n
MCASP_RX_MODE_DMA);7 g2 G' p- R; H3 b& [6 r( _, C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ e- Z. }7 h# Z( Z, ]4 I* EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; q# K2 R, B2 m1 z" O1 }( R8 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
D4 Z* V Q: E, s% c( X UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 r. g. k* N2 o2 V) d4 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! x- K; M. i3 P- `8 U" |- Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* { h1 Y+ \ Y- qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; V$ ? |1 |5 Y* TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 I3 K8 Q0 y2 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( @% l2 n/ ~: n& D( @8 ?% }0x00, 0xFF); /* configure the clock for transmitter */
5 N8 r! ^4 z. Z3 g2 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% |% b9 g! Z: o4 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 o1 z3 q+ `( q" H1 J0 N) D( e; O- BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! ?, s( O9 V$ [4 h0x00, 0xFF);5 {' [# @" l- w, u6 R( P
* i+ [' R% X( s# F+ Y0 C) T, }) w
/* Enable synchronization of RX and TX sections */
$ {' B8 z( M$ `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ Q7 ~6 G$ Z X& Z. H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, g6 V, Z( r: z: J& q0 o- ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 q! l; m. P" L- m5 ?- a* b: v. k7 Q9 J4 c** Set the serializers, Currently only one serializer is set as
y3 L- I1 v7 C1 v1 H** transmitter and one serializer as receiver.1 S5 I5 w6 C5 b' ]
*/2 b: W7 ~& y3 t/ u0 W/ q4 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); }* a( n! @2 n/ r/ X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# t# }, l& D \/ M9 N** Configure the McASP pins
- P) b) z/ _# s7 t; u/ @+ r I/ |( Y, z** Input - Frame Sync, Clock and Serializer Rx
% ]8 b( N1 b) S b$ r5 w: ]** Output - Serializer Tx is connected to the input of the codec
4 Q/ F0 R. d) ~& `*/! Q4 o9 F& X0 Z- ]2 Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- H; P N7 K' v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ t6 Z7 `/ A6 L1 ^( RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ N+ g' r6 B7 L$ \7 d) r. Q* P
| MCASP_PIN_ACLKX& J5 Z4 `$ ?8 {$ i: @6 n9 L4 P7 z" d, G
| MCASP_PIN_AHCLKX7 P+ \" m* b% a5 }, H: \8 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 ^9 z; \& s6 x. RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ K; {0 c, |; _8 @| MCASP_TX_CLKFAIL 3 h9 y; X- p5 N' c3 L
| MCASP_TX_SYNCERROR
: K# l/ S2 T. E+ { r5 ]* a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( X0 F$ _& ?1 p& c
| MCASP_RX_CLKFAIL
2 e" V# ]* @: [- r1 @7 X/ S3 m. f" D| MCASP_RX_SYNCERROR
1 H" E p( E8 x# ]2 W n' F| MCASP_RX_OVERRUN); Q7 `: G% t0 B3 e4 J- J$ @! L
} static void I2SDataTxRxActivate(void)
/ B/ w" h8 [, ]3 Y/ t O, W' Z% [{
* g6 s% c# Y% b: b! y/* Start the clocks */
# u6 Y% [0 m CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ V% w" f1 [3 y. W( t, d0 j' l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 R# P9 J k9 Z' F6 _% }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," }1 r4 f9 v# Z9 i" \9 W- t$ g; N
EDMA3_TRIG_MODE_EVENT);
0 b3 S, G' K d. z5 G" n- uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 `1 H) r9 D/ R$ j; X# I! V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 y" a* S" O' o9 m8 P4 X' ]8 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 A+ }6 n% A1 q! U: ~* VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 m/ z g" M3 ^7 V1 [$ qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( L0 Z( d9 |+ e+ j! D( o4 j# Q# a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 O& t, ~: u: H4 K3 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* o3 a5 B! z4 w" G, c# t
}
. D5 k6 J- n4 Y' g/ P6 f8 w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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