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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 p; D6 j4 w0 {
input mcasp_ahclkx,
0 y4 s( [( D. q( W2 H5 L$ G/ Minput mcasp_aclkx,& J3 E1 K i9 J6 ?
input axr0,+ \ Q ]* H0 D& r9 y9 v4 u
0 U. e0 \" G4 d
output mcasp_afsr,* d' |9 I0 G6 D" s. a7 W6 R3 s
output mcasp_ahclkr,
0 X* w5 X9 I! Doutput mcasp_aclkr,# ?% \- [6 R$ d H0 F( a3 {
output axr1,
9 O3 T: ]. W% V4 H0 {- f9 i assign mcasp_afsr = mcasp_afsx;2 J( y x1 M. J1 b+ n* b) m% m
assign mcasp_aclkr = mcasp_aclkx;* k# C) _3 n7 d# Y
assign mcasp_ahclkr = mcasp_ahclkx;
4 {! W; p3 Z7 t, tassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( b5 F8 x5 N2 ]0 x0 k; D- Z+ D
static void McASPI2SConfigure(void)
2 M8 _) k% q8 ~6 R! K: ]{# ^7 }2 X* O# N* U6 H( K) D0 d3 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. q j/ Q# _' Q6 U9 I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 v8 t6 z; e7 K$ V4 e1 f; `- L FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ U. r: M2 ~, y! q5 I+ dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% k8 ?$ y) Z/ W; k$ cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
k6 }# V8 q5 G! r% _* G( {MCASP_RX_MODE_DMA);0 ?; a; I0 j( {" O& A3 I G. Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 @4 S0 n% d; G; \8 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ k7 n! L! e+ ?) SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, j' }, s: x' E4 M; ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& p3 c2 e& W6 T! p6 @ N3 I6 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- p' L2 |$ T$ i/ _, s( iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* F6 {; T2 ^" jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" Q" o7 t* `, `8 e1 F; tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 Y8 g2 ~6 A8 B5 m H4 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: Q2 O( w$ q( a, M; l7 S
0x00, 0xFF); /* configure the clock for transmitter */+ C! l1 E, F h$ V' ~' m L" Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 m$ j. \' m L0 d) _$ E- S, @1 x+ n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / s, r) K; D2 E. s$ \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( P3 O+ W. n F
0x00, 0xFF);
) D/ ]# b2 I" u/ {; F3 A
3 g& t: y) c; Y- D0 {! U2 [/* Enable synchronization of RX and TX sections */
1 u- F# S9 x7 O2 T: jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* D1 r7 W4 e3 C+ K' J( g# uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); t' l& h( y/ D3 ]5 W( l" P, ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- [+ o# n: v3 e0 d+ C2 _** Set the serializers, Currently only one serializer is set as
/ b0 t- @- N/ o( ]1 a- q3 N' ^** transmitter and one serializer as receiver.
) G5 p* K' y& w; @* f1 ^6 `5 F*/
2 E8 t. r1 X% J8 e3 [, GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. x% p! A# C4 ?6 {9 z1 P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% p- Y8 i9 W# z" T; w0 m0 D2 E' l** Configure the McASP pins / w9 B- z' f# s) B
** Input - Frame Sync, Clock and Serializer Rx6 p# }2 J2 F6 X: c) j
** Output - Serializer Tx is connected to the input of the codec " m' {! k. S" O
*/& S1 `# z1 \3 d5 z% O2 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( s$ ~, x" M: D$ i( O h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ ?) D8 H' L1 O% o, ~, a7 l6 PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% H5 t. B8 o- F. q' A| MCASP_PIN_ACLKX
3 W7 ]7 B4 h0 U6 f: L Q$ U| MCASP_PIN_AHCLKX( q: \6 d* C) W( c! \4 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 Y( E4 ]0 |: D( aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 p6 [& W9 `& ^( D8 d1 E/ z7 B( D2 {
| MCASP_TX_CLKFAIL # Y! f; ], @$ }1 Q
| MCASP_TX_SYNCERROR
4 T; ]' F n6 K/ d: y* W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( B( _ n( X) _/ J+ B( ^
| MCASP_RX_CLKFAIL2 {6 l1 y, Z0 B3 p
| MCASP_RX_SYNCERROR
- F8 I3 C% N1 d2 t8 m| MCASP_RX_OVERRUN); _" ^0 j7 A( B8 J$ i- N
} static void I2SDataTxRxActivate(void)
6 P6 G0 \% Y( n. `{
8 @( j/ ?9 n7 p0 ]) R7 q( w/* Start the clocks */
0 E; V. {! _) |8 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* ^1 g. E& l5 l' q0 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 C+ O. b2 ^; R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; Y, F2 A) g @" F
EDMA3_TRIG_MODE_EVENT);% ]/ H! E0 V& i; Q) ~) p3 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& {7 R0 `2 L) s3 h5 y6 k/ TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& z+ C8 t* J7 p7 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, h1 y1 ?5 I4 n M( F! U: b5 C T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 D! r+ |+ W. \9 k$ u, m0 W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, T8 \5 W; Y3 g2 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. w: X% z/ D1 \/ Q' tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& l$ ^" ^$ p V& V" D} 7 B4 Q' ^1 J; [4 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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