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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ f$ @$ H: ] x# o7 einput mcasp_ahclkx,+ [1 d: J, y5 {8 e1 A
input mcasp_aclkx,: o9 E2 C; V* a7 g2 k
input axr0,. o1 h; B2 Y" h* w. |, D. W
: }! W \* A: w3 N0 a8 Coutput mcasp_afsr,3 G! K3 i3 ~& k
output mcasp_ahclkr,
6 z4 J; t7 e; k2 goutput mcasp_aclkr,+ G+ B' Z; e+ x# {
output axr1,
) @* ~% a7 Z% F- {) h& y assign mcasp_afsr = mcasp_afsx;8 g+ V3 T7 _9 [+ o" V
assign mcasp_aclkr = mcasp_aclkx;. b0 T5 q5 w+ ]3 [0 @
assign mcasp_ahclkr = mcasp_ahclkx;
6 N) Q% h$ K" Rassign axr1 = axr0;
5 G$ m7 h$ X" ?2 E+ f, Z
9 z$ d( F; m- o u2 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" d( G# }% o& T3 kstatic void McASPI2SConfigure(void)5 p- l0 n2 d0 ] G1 ?8 S/ h
{- I8 [- x1 F, I z- ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 T4 p, [' u9 ]4 QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* c3 p k5 N% y, x0 m9 F& b' q8 tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; x# X1 N6 C$ W9 V1 d% k# I% dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ n E0 M% ]4 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 c+ N1 S& `8 l7 ^6 ?" i/ w, X
MCASP_RX_MODE_DMA);
$ i/ ~8 `' l4 Y" |$ t: G* V9 o3 M) ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ?( N0 \" s j" |- i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 N2 X" Q5 l2 }8 M/ a+ m4 dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) `- E* m4 x( {! I) G! pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- q" o" Z* s$ E$ g6 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " u% Z6 S2 Y. x/ |* f: ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( J* R9 u7 ?5 n! y b, |% b6 DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- x8 J- A$ s) Z' Q6 \6 e# j" J5 V$ z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 G9 }, P( B" w+ IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 _* J: J/ f' D
0x00, 0xFF); /* configure the clock for transmitter */
5 y8 @ s8 W0 h* lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% h8 S! O3 K9 u8 C2 a2 c5 e9 T9 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 u% D X0 z8 s8 y1 `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; c0 i! V3 z# W: s+ m# {( `2 {- S
0x00, 0xFF);
/ [* R; J2 T# F2 M
' g% I( A; |. F! T/* Enable synchronization of RX and TX sections */ / u4 w. t# r N9 T% q; y: [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 b' U" S9 L& ^5 u: P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& G) Q( a3 d p0 i+ k/ MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 r4 S; J) a; H! F, B
** Set the serializers, Currently only one serializer is set as- t+ @$ Q9 E& ?1 a) M7 ?4 \
** transmitter and one serializer as receiver.4 |: q( k' i" \: U) t% J
*/- X- b: q4 \* p2 g) T$ s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 {) E8 [, K% nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 x& x3 M' b$ M' K B$ V- s** Configure the McASP pins
- E d& k+ Z& H) H: h% j, B** Input - Frame Sync, Clock and Serializer Rx7 l! B4 D+ ]( P0 a3 Y
** Output - Serializer Tx is connected to the input of the codec
f; O0 P4 T3 v+ w' S$ X$ B" H*/
6 W1 }; b$ k# _& R- ~8 @' t7 t9 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# ^4 n v/ i* n& h- P& n) G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% W1 i8 \) i/ _# pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 X8 u! j5 j( u0 r2 ]| MCASP_PIN_ACLKX
- x4 c* ]' O! g$ ^, p& k| MCASP_PIN_AHCLKX @. }- |8 H6 `) w% E' H6 X0 ^9 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 e T" w/ G& r Q& O' j! P$ V# h3 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : C; ?' }" J, ~( V- B8 B
| MCASP_TX_CLKFAIL
5 f9 L' T* Q. ?% D6 v| MCASP_TX_SYNCERROR
4 I; R5 Z) w& ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 B0 u% c7 K4 F7 ^, S3 t& f: G* B
| MCASP_RX_CLKFAIL$ K! @- ]' `3 {( g5 m- @" r
| MCASP_RX_SYNCERROR
$ R3 H7 M3 `/ t8 Q$ ~$ P: o% U0 u| MCASP_RX_OVERRUN);
& M! V( J2 y2 o1 ]} static void I2SDataTxRxActivate(void)
) w6 {" `- h/ |% v) m9 }{1 a3 @4 x; Y' I5 ~3 C1 ^* P
/* Start the clocks */" E6 J1 X w6 F" f! m, S5 f. }: c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 }0 ]4 w6 B2 v7 r/ J6 ]" p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ M& i1 X0 B: K+ z( _6 N, n; U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 x8 ?4 q1 R: y& d+ |EDMA3_TRIG_MODE_EVENT);5 _0 E' L$ ^* T7 U2 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 |, U( e4 R( ^- }5 e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 g$ K6 D m* ?: t: ^) t m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ A6 `3 `' y" B3 y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( H# K( w: e8 |3 d U1 j; A& A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. V8 p: A( }& @: K, }& D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 W1 {6 g+ d( u: o2 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ [& g3 f1 \" z. l- t4 ^2 ?: ]
}
0 t, O e- i3 J8 L: `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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