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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! _2 X8 a- W. R5 Minput mcasp_ahclkx,- I# M! V, r ]) `
input mcasp_aclkx,$ R9 u" _& K9 ^2 l
input axr0,
+ k F+ |* F* U% ]0 n; }
6 N, O* o/ ]" J- o, v0 h5 Routput mcasp_afsr,
1 q9 Z/ K5 A3 youtput mcasp_ahclkr,
( p/ B- V$ p0 g* h4 N% m! v* koutput mcasp_aclkr,
- w2 T0 u' |, B8 Y p' ioutput axr1,8 n4 Z" S: r0 f$ B
assign mcasp_afsr = mcasp_afsx;
1 Z8 P4 ]7 w0 y jassign mcasp_aclkr = mcasp_aclkx;
' C: I9 t# j: L, q0 v% Gassign mcasp_ahclkr = mcasp_ahclkx;
0 y `9 H7 n2 v$ g) \" Kassign axr1 = axr0; " }8 J( I6 J+ a0 @4 y4 X+ M
- {9 ?# w+ l* _: Z- G7 J% R$ K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 F- Z/ o, _) W3 v Nstatic void McASPI2SConfigure(void)
% z2 t! x4 A% I! _) d, J{
) y9 ?* H1 ? r) e! T2 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. [& p- D* f& j3 u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 \, E' _9 H/ c4 ^8 s$ sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; q& Z r" V' U6 E# B0 Q# V8 r$ bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' [4 z& A l: G6 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 M8 f" x. |: Q7 h1 [MCASP_RX_MODE_DMA);8 i5 v2 e$ m8 T1 D1 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* M: k/ X3 N" s, t1 P1 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' S$ L* h3 V& aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + C8 g( Z) u# b* E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. ?1 _7 @) ~. X5 c$ B! \" v8 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
@' N( l+ e5 x, U& ~0 B& {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' n1 R3 g) }3 h, V3 R' Q& i- L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' D0 E9 n! z- A6 r- X& LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
G9 y+ [% r2 k7 g+ ]( yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. u6 l' E# I' R0 O1 \, N
0x00, 0xFF); /* configure the clock for transmitter */
# t0 K) R# A4 b- ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" ?" R u! V* f% Z+ ?- t7 i9 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- K: [& w% ]) \. {" u( LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 y/ @$ |! x% r' O6 l: I" Q2 `0x00, 0xFF);
6 {& R- t! Z4 r# d) G \8 f |* S$ M% j+ M( {- y- @ P# g
/* Enable synchronization of RX and TX sections */
2 {5 Z4 E0 [/ L' h' B1 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
\5 A; ^* K' dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& }+ a; T2 d! c+ p j& A. Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# ^; {2 @ z- m" Q** Set the serializers, Currently only one serializer is set as
, a% `8 y% O1 w** transmitter and one serializer as receiver.
4 r4 Z6 g, A9 P: ~*/
) ]: t+ b: O/ o( d! C. {5 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 u5 P/ j0 @ h" H, M( X2 b2 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# P+ _$ Q5 t- l. w" h' X* F** Configure the McASP pins $ x/ A3 G Q# {# X( x) _
** Input - Frame Sync, Clock and Serializer Rx
& M# \. l' F% g& G. t8 S5 m** Output - Serializer Tx is connected to the input of the codec
; o5 f( t0 _( X# t0 L* ~8 ]*/: ]- I8 z) p( J& H) l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 V) O! G( f+ ], `2 c; E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ |6 e6 ]0 p, s# J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 |8 }! U9 n, W3 |
| MCASP_PIN_ACLKX
5 r0 [# V# \0 c* o2 A# q' e| MCASP_PIN_AHCLKX
1 L; G6 S( i/ C* n% a1 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! R& s& ~4 Q, g4 b4 LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 s& m6 K9 H% s" T( W. i% ]) P5 O| MCASP_TX_CLKFAIL % ^- Y; d2 W( G% E7 `( L
| MCASP_TX_SYNCERROR T$ n5 v- N- |# C- J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ F7 i- P$ Q7 O. J# B6 `| MCASP_RX_CLKFAIL1 v" \5 {; J d
| MCASP_RX_SYNCERROR ( A M6 N! Y% M5 T1 M) t5 }
| MCASP_RX_OVERRUN);$ \5 s ]6 s+ L( F1 K; {, _" S
} static void I2SDataTxRxActivate(void)/ c1 w# v# G- Y* p* Z( ?
{
3 _& }2 `3 u, h1 ]8 }; J: o/* Start the clocks */
9 j2 Q* b* W5 w& u. I) n( AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* q: d7 c& P: y) s4 F. o. _. ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. D3 |' c% _7 t1 G$ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, [* c. q/ k5 S( D! v/ a
EDMA3_TRIG_MODE_EVENT);
4 @* T6 A- x9 U, J0 E- T# YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# h1 \7 A f: G/ C+ ~ D! CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 M/ a. H E: |" r/ `; o0 X) r9 t, F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 I1 A' v. X' r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 [5 {) j2 B( c( q3 Q y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* S. b( I, D. N( c3 d3 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) ?" n0 i) C: X! T7 u# @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 B, i2 {7 v9 V. d+ g% A* x} s( ?* ^3 E1 i p. r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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