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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 v, y) S' s+ xinput mcasp_ahclkx,
$ i6 P& G: _; z$ [) A" W2 einput mcasp_aclkx,
0 s; L- o; \' Y- Q2 _input axr0,
6 ^3 x" o1 E7 Q2 |0 f# X: z( F/ l$ N. e
output mcasp_afsr,: j# b! B3 _+ I; c$ a7 H' T
output mcasp_ahclkr,1 {; V5 L, b+ |9 z! p
output mcasp_aclkr,: K ^* T4 W; q0 z8 R6 b" c
output axr1,
; @2 O0 L: K: v8 s assign mcasp_afsr = mcasp_afsx;
' v6 B6 C( Z* Xassign mcasp_aclkr = mcasp_aclkx;
* j% m) {. ]/ g% @, d D6 W5 Eassign mcasp_ahclkr = mcasp_ahclkx;: v* T- p6 ^( v0 |0 B3 J
assign axr1 = axr0;
! O0 z& b% h8 Z/ v. f
/ `3 L* P6 {, g0 J# S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 L$ `: k- X5 v1 a/ o) D$ Xstatic void McASPI2SConfigure(void)
- d* F Q6 y$ A0 |: l* c1 [- ]5 t{; L! d6 f( k% c+ \. M6 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; A% n$ b, U# F# ~& v9 @( cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ l! s3 e# G M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, O. M: {; J/ ^$ VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ h+ Z' ]# ]$ k# q) P4 d2 }# U2 f; ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 }" `- x5 L# ~# i. t
MCASP_RX_MODE_DMA);. }* p4 f8 }4 j) Y! ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 |5 s6 Z5 F& _) t, C. J6 ]3 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# H @) r; b' i! L; O( _6 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* I8 A$ x" v2 W5 G1 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 W9 r4 t) f! TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! x& K# b2 g8 O$ h: S$ G3 L+ ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 I, e/ z1 T# w* O- ~ ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; O' e: T1 D* [5 r! _2 u7 ~/ j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 x4 A0 a: c; M1 M+ H! ?- Y" Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 ?+ h6 ]- C! y- E. { O0x00, 0xFF); /* configure the clock for transmitter */2 @0 l: ?* C% w: l1 U0 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% Z6 j9 E; o8 T9 {6 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 {3 E8 L# T1 w% i' dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 u* v6 |/ g* ~& f' y0 ]
0x00, 0xFF);
' \' W: s6 }% {2 _0 `/ Y) Z0 `% O' }/ ?3 ]! Z5 W( Z6 C M
/* Enable synchronization of RX and TX sections */ . M$ D+ i) j, p1 [7 D& z1 v5 _! k5 ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- a7 |4 G' W H: n7 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! }8 i. S3 x9 i. z' G! U3 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 C. O0 K* n! v! l6 t3 i
** Set the serializers, Currently only one serializer is set as
1 o5 c: S1 U2 @ B2 L** transmitter and one serializer as receiver.
5 K l! Y% g" I" V& }9 ^*/2 Z! Q1 @) x% @0 p& d" N& N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) }) \7 j/ W1 s) ?: x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' G, {' B0 q$ P+ r" G; _3 y
** Configure the McASP pins
" \# `: z* f) k** Input - Frame Sync, Clock and Serializer Rx3 }" J$ S1 O% P( y( J$ A+ y
** Output - Serializer Tx is connected to the input of the codec $ z0 f/ w! G' G+ G' `' j# F) ^
*/
0 A' O& H( z" u8 o0 g2 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- S; q8 \- T V0 S% D% MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 m0 G, d; Z- j( p6 X) z: c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 Y' J) z7 b% W6 y% i| MCASP_PIN_ACLKX+ M/ i6 } b: a1 b
| MCASP_PIN_AHCLKX5 A- R- w/ q* `: X2 [0 c2 t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- W/ [# v9 F8 j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 f8 f" i. j4 K6 }- m| MCASP_TX_CLKFAIL
+ R8 q# K2 Z( s/ g| MCASP_TX_SYNCERROR, o0 P( M1 ]4 x3 f$ v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 Q0 I9 q) w) Q; }
| MCASP_RX_CLKFAIL
2 |' R- \% L' j M| MCASP_RX_SYNCERROR + o3 [; R2 m9 ?& n+ f& o, q/ U
| MCASP_RX_OVERRUN);, J4 d% y8 ~' @5 y! T
} static void I2SDataTxRxActivate(void)$ ^4 A8 J. q9 G% r. I: j& _
{
: q3 q/ ^* n$ k/* Start the clocks */
7 a+ D6 Y3 V8 B" A2 {( i/ W- xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 f6 A; a" C q- K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 w @3 v. @9 X# }! q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# Z' f# t1 b4 z$ A) O
EDMA3_TRIG_MODE_EVENT);
4 h' X' i$ y5 ^ Z$ h ~( l% @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 g$ Q8 p; V2 F* M# x0 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 y3 d p1 J- I+ L( z* n7 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ n& I& F0 M7 k7 r; j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ Y G3 a) z) |. s' a- J% jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, K7 y0 ^. ^2 ]8 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ `; [4 }" e% R) u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 g# W6 o* _$ F$ O) X( y
} . V: H& h/ J E$ t0 j+ l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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