MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
7 R2 o: m' v- r* @: Cinput mcasp_aclkx,
$ J- v. M2 d' m5 a3 Iinput axr0,
3 x- W) r2 y! ]+ T1 v* P: O% w  f/ ]
output mcasp_afsr,
$ j' g1 b, F. Q. Y  |output mcasp_ahclkr,
output mcasp_aclkr,
& Z! e3 C5 v% C/ ^  Poutput axr1,
2 O8 W4 @4 U; c

assign mcasp_afsr = mcasp_afsx;
3 D$ y8 u; q9 Z* Kassign mcasp_aclkr = mcasp_aclkx;
# F8 k% z$ p, Y& eassign mcasp_ahclkr = mcasp_ahclkx;
, p. a3 O# W( I. L, ~- m) a2 wassign axr1 = axr0;

2 U% A1 e# P9 E' u) Z  Y2 _# C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
$ m, }# v" [/ Z* W{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
% b' ~- ^2 }/ z& P' H1 Q, [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
  S+ }" x1 m$ Q5 JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
: n2 I' q/ |$ mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 C# A$ E8 a$ X$ bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 e0 X3 {4 \4 @  D% GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
9 D. S' g8 p# bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 a  G) n* o  FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 {5 s, z! t* B, s) z9 e0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 U7 G0 \) T+ ~0 A* ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, v! V) m8 r& s, T6 E; i* G0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ @0 v* R1 j9 U& }/ A" jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
- w% r) h6 G- E  u** Set the serializers, Currently only one serializer is set as
  O. i' J" ^* I5 j- c" U+ g** transmitter and one serializer as receiver.
1 o2 d& c: r+ ]1 J6 X*/
/ w* Q  d+ A/ O; j/ w" r  dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
1 d( C6 ?* P1 E' q** Configure the McASP pins
1 R3 k' N5 P, ~/ w) v' b** Input - Frame Sync, Clock and Serializer Rx
/ _1 U, E; \; `** Output - Serializer Tx is connected to the input of the codec
*/
1 q# W! b* f0 M# d. s& bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
0 h  Z3 R! R0 G3 `+ h  R| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
' _* C( K, r& h5 ^| MCASP_TX_SYNCERROR
$ a$ g4 @& S4 }% j| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; k9 L& ^3 w8 T| MCASP_RX_CLKFAIL
1 k% }! a3 a/ s1 t9 G2 p| MCASP_RX_SYNCERROR
% x  K- |* i0 {& d% j| MCASP_RX_OVERRUN);
. J3 w- W* X) _) g" K! a}

static void I2SDataTxRxActivate(void)
3 x; o0 d! n1 c/ O{
/* Start the clocks */
* T7 C6 r6 V3 u8 @) N8 B' jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! M7 @) S# j# t) X6 DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
" A$ G# g9 z0 ^1 [5 V5 Y: {. UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
. ]- l1 K0 ^0 E) z5 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
  C- L& y7 K* I( SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' S) p1 K$ x' G4 M$ U7 U+ N7 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 C# V8 w* g) T2 F2 J. _}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.