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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: t. ~; @& N$ W2 l1 a. ^2 z: |) binput mcasp_ahclkx,
% \/ a+ Q+ ]3 V- c. o. H" |+ w2 Z# qinput mcasp_aclkx,
; C* Q* x! p* Z$ x! n* ainput axr0,# ?0 H5 a; o; Z7 Y$ s5 E$ I. j5 j# f
$ m) h3 D( \2 P q3 z
output mcasp_afsr,
/ g* ~' S9 y% j" Moutput mcasp_ahclkr,
3 d" r, }- G" ~2 u+ }output mcasp_aclkr,( h4 |: {7 V0 V+ E7 B( ` c/ l) Z3 a
output axr1,
/ ~- ^, K0 S; m. ^0 ` assign mcasp_afsr = mcasp_afsx;
8 a6 ^ E' x& U t7 x. W* v1 Nassign mcasp_aclkr = mcasp_aclkx;
$ j, W9 h5 w4 p- oassign mcasp_ahclkr = mcasp_ahclkx;, e5 W+ a* O0 W
assign axr1 = axr0;
! m' V2 Y) w2 s& J& i( u
S9 W8 h5 K! L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' G: V5 z* g) d2 f u/ Bstatic void McASPI2SConfigure(void)
$ @/ a6 L' a+ r{- g3 @) H. H ~- F4 M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 ], D" A6 m6 {4 d( Z$ f, f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 y% D- n4 o4 z. U0 VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ?2 ?( E5 E6 w7 A9 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 J) _* R3 l% L( d$ V& pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ w8 m/ @, Q" D9 r7 y" G `) HMCASP_RX_MODE_DMA);& T$ S$ n( D3 X) Z" t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, J4 n8 S6 j. H0 o9 v; ^$ a* K2 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 M1 Q; [2 m; E. x) x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 y' n# Y4 y6 `- `, h% p: dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 h% D" \; `" w4 f5 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) B4 C j5 F6 `. R9 V0 tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# {- n( r$ H8 f, [8 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" d# [" ^8 h( H E3 M5 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; x! _) P6 F8 E8 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ |1 r' L1 T" k
0x00, 0xFF); /* configure the clock for transmitter */& ~7 N6 W+ O9 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& s4 F$ T) f$ w1 X. XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( c0 b" r+ `, e9 J g2 N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! [) A7 w6 }4 ^# l2 d. X
0x00, 0xFF);
; A7 j$ s: k* Y4 j0 R$ l3 u3 c' R3 O1 ^, M L, R# ^: d
/* Enable synchronization of RX and TX sections */ 1 b/ s7 O2 k% W) j5 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: S) B& S# ~6 I r! x. ~$ wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# H/ ^0 A" W" K6 N+ }, u, [. oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ h6 F/ Q4 `% q" e2 I& p' i
** Set the serializers, Currently only one serializer is set as) ? i) p" x. g
** transmitter and one serializer as receiver.4 b+ ] D1 w. s+ n
*/
) w0 U" \# L6 O5 S& g# @: u- P. S4 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 ?1 v0 H9 R v" G$ x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% B: g/ D" c J, c
** Configure the McASP pins
' Y# U9 n) L1 p! T# ]* q** Input - Frame Sync, Clock and Serializer Rx# u: [0 m e: W& _
** Output - Serializer Tx is connected to the input of the codec 6 r, I7 a6 I7 U1 y
*/9 g, E# b" D p8 U1 n5 t- o- x6 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& j/ j. P$ \5 a( s9 q3 G; MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) A7 \* m% @6 \. D' C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 ~2 c7 G! u" g& ^# A| MCASP_PIN_ACLKX
" h3 M! D6 ^7 F% `( ^$ K: {| MCASP_PIN_AHCLKX J* [ P( \0 a2 L( o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 _8 p7 F. p7 i$ f( ~3 |( X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) w( q2 [ O/ e' p6 w
| MCASP_TX_CLKFAIL
0 I9 `: R, t% p. k| MCASP_TX_SYNCERROR! N6 i! G% ]6 K$ T& n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 ]0 m. g Z9 I6 V" `% m# q5 b
| MCASP_RX_CLKFAIL1 ^+ l, w4 V0 h- i
| MCASP_RX_SYNCERROR
, }) a: A8 ^/ V. N( Q, j+ P| MCASP_RX_OVERRUN);0 X, D! {: p, k4 f' }/ U7 D4 ?2 P
} static void I2SDataTxRxActivate(void)9 g0 g$ c1 ]$ @
{
8 Z1 n' { _! }. d. Z/* Start the clocks */' Y3 ^% l( t' C" \* u5 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: }% t# l4 ^8 X8 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! g; A7 o) r+ p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 v9 o* `# ~' ^4 b: i! u& d3 v7 m
EDMA3_TRIG_MODE_EVENT);
% }0 c6 C; Y9 ? z- ^7 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 {7 w2 ~1 t2 v( z$ P9 e, wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: x2 c/ J6 Z9 z4 j( O: T! ^" S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 Q* U" d; L5 _+ w1 _! c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 d! x+ }- H; ]" F, O" f! T8 x! Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 ^# ]- t' _4 A2 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; t5 D& Z! o; b* x6 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 z; u4 V( Z2 f: R5 B
} - r5 v V" b$ ~3 t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 d& |9 u0 { B9 l
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