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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' Y5 X2 d! l0 vinput mcasp_ahclkx,
9 q0 F7 _/ ^' @1 N, a0 Jinput mcasp_aclkx,4 g: S5 z; f5 }: U. {% t1 @
input axr0,
2 s/ N1 Q" K( y3 `, q1 L# E0 \+ y# O
. m0 J# x% n; W' K! poutput mcasp_afsr,
1 j; `) p1 u+ ]$ U' Youtput mcasp_ahclkr,! Q! X. S1 J/ x) y9 i% O
output mcasp_aclkr,) K8 B1 N, ^- S/ ]" Q
output axr1,: z6 |# _* R9 ~, _8 l
assign mcasp_afsr = mcasp_afsx;
. Y% a6 K2 k% R; Y. N( E- zassign mcasp_aclkr = mcasp_aclkx;2 l0 W6 z9 _7 q/ |. \3 q
assign mcasp_ahclkr = mcasp_ahclkx;. F1 i$ g! ~+ i% } J- L
assign axr1 = axr0;
, r. [- F4 @6 B' ?) R8 p; h) G. {1 L: l9 |1 y! Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( R7 b9 q* ~: n4 J; z! ^- k# O; Q
static void McASPI2SConfigure(void). |- O$ N3 H7 b
{' z! b7 M( J7 @* V; t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 J3 U( Q# f: Y9 ?; G2 {' @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ P0 N5 x# \/ d& M( P2 y9 ^/ D' t1 nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 d0 }( z' z/ _; z: v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: d1 K' }6 I* q! g' v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 o; B! X( k/ `+ v, d' I
MCASP_RX_MODE_DMA); h) C' R. v2 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ c! m( u1 b' `) H: H7 ]+ T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, K' T1 T2 e3 Y6 C. KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' |& q' ]/ J' t% T. rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 @% a) R/ Q. E) n& ?+ y oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % J( z2 t# @& `) _3 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ A( Z+ c+ p$ Z- w/ @8 R0 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); [/ A% G0 L) I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" o* c1 s" X8 N1 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 Z+ w1 B, z, ?. Q& f3 w# w
0x00, 0xFF); /* configure the clock for transmitter */
" _/ M% j& o/ o/ Y9 h# b& q+ fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 c; t% x3 p0 A/ t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. ~& Z. X1 |. J8 Z: I- B" u2 n. JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ m4 ^/ {2 S% Q
0x00, 0xFF);9 U4 v a+ I. R
4 G, J2 `1 d+ l+ v" _+ q/ @
/* Enable synchronization of RX and TX sections */ - h& h2 b& N5 h/ | l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( g% c( X5 {, X! o }# }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' S/ L% F8 N2 l E. Y9 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 c9 X6 J4 m& g7 f, o2 b** Set the serializers, Currently only one serializer is set as
3 Q9 i2 h3 P0 c# t1 k- l. Q** transmitter and one serializer as receiver.
, ^) D+ T9 v" \& `, a*/; P9 {' R; M M3 [- _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ }0 q2 M& P4 t& j" K- R" x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 u9 _$ A7 L' K( H+ k T** Configure the McASP pins
% t2 u- L2 Q. r( P# U/ F( K** Input - Frame Sync, Clock and Serializer Rx3 Z( a# T C/ @+ c/ p0 q
** Output - Serializer Tx is connected to the input of the codec
7 \9 l$ t1 j: F5 U4 ?*/6 k/ K) ^( g1 y, ?* K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 z9 g. b3 e1 S: d* q$ r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 \( l9 `9 ^3 { E! ~5 b7 |# \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 _& L, T% T" ]1 T
| MCASP_PIN_ACLKX
: E: d" X1 c; K| MCASP_PIN_AHCLKX
, _9 F9 |4 ^2 J; I6 H4 S2 _, v. }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 h& q1 R% Q, lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; j1 D" @! f8 T- C| MCASP_TX_CLKFAIL 7 ~$ w- t" |* ~ x4 b" y& ~
| MCASP_TX_SYNCERROR: Q1 f$ h& C+ u( f) m$ f5 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR g1 m7 l' D" F5 s" k4 _* d
| MCASP_RX_CLKFAIL( R3 k5 w0 ]* E; s: A
| MCASP_RX_SYNCERROR + D+ n; F& \9 `& K
| MCASP_RX_OVERRUN);
0 [0 U# N1 W1 T! H' Q P& M& ~} static void I2SDataTxRxActivate(void)
, M. E8 C, B; c{
; R/ x+ ~9 ]2 R" E; E. G* l9 ~* v/* Start the clocks */
$ B5 N. b9 Y( H: F* `# jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: F$ R3 G' T' E- s7 O9 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; F2 F- z. S9 \8 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 r: N# ` d& [+ r, c7 o+ PEDMA3_TRIG_MODE_EVENT);% B# ] P0 O% f z, `; K4 h O# B8 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 `. |7 ?1 c$ O) x" o& F A3 B" M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; q- t# E( f, Q0 Y8 ?: B1 S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" D% E) \5 \8 k- l) a! w' [1 m4 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" ~, L0 B- X# [ P: V6 @5 I% O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ `0 W5 l3 m" J, e5 @ b/ N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 O; g( x' I4 o1 kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% _: [" y ?" O& w- l X}
. ^7 W c5 J) W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * Q" x7 H, I% u ~1 Y
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