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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) G: I0 j6 [9 }* Kinput mcasp_ahclkx,
/ @( J/ ^4 K/ f$ s& Linput mcasp_aclkx,
0 T: I& N* U! B" Q, m2 Iinput axr0,& p3 V: Q1 A: m2 x7 n3 Y
2 d/ c& j- c; l& e/ ooutput mcasp_afsr,/ U5 w; V7 w# Y6 K
output mcasp_ahclkr,; B) j( U+ Y4 ` |5 c. g/ f4 l
output mcasp_aclkr,
7 B3 ? e. ?) W" o/ qoutput axr1,! e W1 h: C+ t5 Z% t. O
assign mcasp_afsr = mcasp_afsx;% h3 J5 g e" [! @8 I
assign mcasp_aclkr = mcasp_aclkx;
( X. g& H8 W1 b! n. cassign mcasp_ahclkr = mcasp_ahclkx;
. r* r& ~( I3 l5 D+ Qassign axr1 = axr0; 5 ]1 N+ e: W- |( v9 R
2 g F+ ?- J: z7 v; r# B k5 _- ?6 w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 |7 |/ b5 a# g' n4 g
static void McASPI2SConfigure(void)
) k( b4 g; Q; q5 i! `{
4 E8 I/ v" m! o4 @3 E0 t# CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 {# G9 u/ J. Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 l4 a) Y' h; O+ h9 }9 C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: m. p2 n4 x3 z+ f4 a" u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 T0 F! u' w* ~! v. U" {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% j T9 T5 v; z+ ]% s6 A1 U: g: uMCASP_RX_MODE_DMA);' v+ ~5 G( u5 S! n4 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 r; W, p' s# A8 @; l$ ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, \4 X4 D3 k8 S7 [1 y$ @0 h. c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" q! a, u+ X& KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ L8 }/ X, n m; x) T; |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 Q+ Z) N" ^* e: U rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" A9 o: D/ ~# X" I0 g/ T' d) z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 ?7 C1 G. _& [; G* {% z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' Y- x3 P3 f4 K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 |8 m% c1 a- _2 U# Q3 {7 v$ A
0x00, 0xFF); /* configure the clock for transmitter */
& x2 c; e* q/ o) I. lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 B! X7 @# {: E' n9 B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ k: V% U$ P* Z+ `( Q% ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; B- t& ~1 p& R) b0x00, 0xFF);# D, s$ G6 z9 b
1 I7 L! O5 C: D" A# Y8 J$ c5 s M0 X
/* Enable synchronization of RX and TX sections */ 0 z) _3 L! f. g1 U3 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* q9 o2 h9 R/ j5 p4 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 Q) R6 F- f% R- j) J1 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- B4 V% b6 e, Y ]! d% ~; z6 R* _** Set the serializers, Currently only one serializer is set as2 f$ M ]6 u& V) T+ l
** transmitter and one serializer as receiver.
: b3 p% v, f$ U5 \+ h9 ]* g5 _*/
& A- Q2 J+ K: w6 x+ s f- P4 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 R5 o+ D$ S; M% j; d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" H1 O+ V0 h' z& v; o** Configure the McASP pins ! [5 R6 t% n( ^" D
** Input - Frame Sync, Clock and Serializer Rx+ h. F/ o: H' ?
** Output - Serializer Tx is connected to the input of the codec ) A3 X4 E0 h8 a5 K
*/
- _* } s) S9 F4 U ?/ O3 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: K" y# ~- M/ W) |$ G" HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; g, c" Y! h6 s2 K5 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, Z$ F: G- f5 C* P3 T7 U; A
| MCASP_PIN_ACLKX
- Q1 Q& l3 _4 v# L| MCASP_PIN_AHCLKX
! ^" z' s; Y# F) `5 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ S' i, i/ _- c- X; \7 [/ v i. e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , b& d4 G% A! \1 o3 [3 O
| MCASP_TX_CLKFAIL
. M3 ]5 s" P5 ^| MCASP_TX_SYNCERROR
7 H; @2 H( z( A2 E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; F% k; n; L' L& E- U5 ~7 ?| MCASP_RX_CLKFAIL% F0 _ P" ?) H( `: p1 X8 Z- A
| MCASP_RX_SYNCERROR " B! T2 D+ o2 A, s4 k; ?
| MCASP_RX_OVERRUN);
' i4 Q6 o/ ]7 J9 }3 L, L} static void I2SDataTxRxActivate(void)
9 ` N4 ?* O3 E{
, C) |0 d, @3 J5 k/* Start the clocks */, K* p9 }. P- P) I) N1 M* Z$ ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ ?4 o+ a% n q4 r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# ]3 L# R3 C2 [3 a- L* J1 Y3 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& h$ E2 y' G/ \, N' C* _4 L
EDMA3_TRIG_MODE_EVENT);
' M" U2 K+ ]8 Z7 l, ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' v6 u6 R& F+ i, e8 v( xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 Z5 ~% b' v% s& [% w5 H4 HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& ^3 @# H; ~$ l) GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( D9 @/ I* B$ I8 V0 I" q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ^1 u) L$ Z* v' g% v. v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
O. O, p7 D( UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 N2 P- N& i0 j; ~! j
} 3 s! w& K3 ?' P* k& h" T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & r. L6 _7 H1 j; U) `- D
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