MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
0 `$ \; H& N( X/ V5 q) yinput mcasp_aclkx,
: U) }: T1 c0 t4 S0 f: I9 a  S7 dinput axr0,

8 q3 U3 b) `/ [4 @5 M/ s$ I3 f% D# xoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
+ `; N5 V: x' `8 toutput axr1,
% P3 K0 ~) f' n' R' d

assign mcasp_afsr = mcasp_afsx;
! g9 p* X  Z+ F+ L& x1 o, t3 wassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

, ]! j7 n; l8 V3 w
& T/ W& K- u7 D

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
  U. }5 [3 z, d, y0 Z) UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
5 U% k4 F8 h4 ?* NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 v1 }, I5 a1 Y& gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) k' O% y1 i0 G& S$ E" j7 n, GMCASP_RX_MODE_DMA);
( N6 M) P( H% E/ e* M* z# _- HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ ]" w6 ]4 g4 `8 iMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. e) V+ L, D. R7 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
& ^2 I' H" g$ k1 e) r0 `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. S. X4 S2 @2 R* b& VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ {' F) p1 J# z9 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
$ M3 o% k2 a7 B3 c5 C+ X
% a; t9 ~% W3 u$ w* O$ v9 o9 _/* Enable synchronization of RX and TX sections */
7 w% S, z, V+ }- N% UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
) l6 i! t. ~, t0 e8 W$ n2 _  gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
9 ?1 R4 t4 S4 a! T' H+ j** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
% C1 j9 B6 \" |** Configure the McASP pins
" y) b, V+ ?9 }** Input - Frame Sync, Clock and Serializer Rx
! m. f4 B. K0 u4 @' }** Output - Serializer Tx is connected to the input of the codec
4 z" }# t8 Z0 O( C: G*/
" D* m0 J$ L8 E" b7 {* u, OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ T8 V) t' W1 @9 Z$ ?3 JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' Q. S: @8 L. E: z6 \, O) @| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 j" `6 p( J2 t| MCASP_TX_CLKFAIL
5 M- D9 e4 G6 W" ]| MCASP_TX_SYNCERROR
" \6 y5 y+ z& A& w* S3 B| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
, x1 `" q& \! @| MCASP_RX_SYNCERROR
6 f( L6 a+ q) H* Y. r| MCASP_RX_OVERRUN);
* H" t! s: k/ G9 E2 O}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. j- S% N0 v, `! k4 l) IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
  [7 ?$ D; Y8 u4 {; V* G- ]4 l9 x8 I$ UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 b+ ]- W! m) y% e" Q. [! E+ cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
6 n7 E1 l& T9 j1 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ }( h4 C* |2 i, U4 |" nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
& X+ ~" @5 W  I( |( R2 n7 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. X# N$ ~, e) \- V. zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

9 t# _& C) v2 O1 m& V$ q

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.