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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- {# ~, s7 A: }2 ~3 Q+ x% Minput mcasp_ahclkx,
5 M8 C. q, O, b% z- winput mcasp_aclkx,% T7 L, i5 i; ?& G* ?1 Z
input axr0,
0 H! S, r/ e6 A1 Z% e+ @: |0 W0 j
, ]8 A- a8 U; E; `3 s! Boutput mcasp_afsr,
' x X+ w! ]1 l9 Routput mcasp_ahclkr,- j) j* \' \3 p7 _% C* P
output mcasp_aclkr,
. E( _0 z. ~3 a# E' B koutput axr1,2 I9 Z4 Z; g' P- @: h" ?
assign mcasp_afsr = mcasp_afsx;
/ e x$ H) n9 F$ Lassign mcasp_aclkr = mcasp_aclkx;! l8 b* Q# S- C& \
assign mcasp_ahclkr = mcasp_ahclkx;5 v8 u! l% f; v# N9 W* X5 b* u
assign axr1 = axr0; 2 G% L2 w1 _9 A4 p& x r4 V
$ m) {/ a* h& O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 ^6 q, n4 u& N% d0 A
static void McASPI2SConfigure(void)' q# O' D. S- |$ S% s' A
{
3 J( {8 M" p" m( G: x/ E8 l$ f" }McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 P6 v8 o2 o2 u& C& [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 j5 i) q" N7 q6 V, UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 i. @2 F; X7 o2 j: MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& j5 X% b, I1 X$ P. t# G, aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 Z, z5 M5 T" r) w% d7 l
MCASP_RX_MODE_DMA);
% u6 ?* n2 R. M9 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ E, k1 ~5 k& I9 [) fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' _* ]* V1 A* k& ]! N) _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# a m; D; e9 Q% c0 {. B9 U7 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; K* S |) M2 D& p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 @- }0 n1 L% @$ s; ^. l: ?1 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, G- v+ O/ U: N" i/ m6 G7 V7 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ ^0 C" J6 B8 K( h, G" c; P- E# u* k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 q' b! }% u$ ^1 W7 \ `/ DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, H1 m% h5 f: j; z' d7 R" N0x00, 0xFF); /* configure the clock for transmitter */$ I7 H$ ?2 _8 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 n& p; v% N1 n4 Z# a6 b& jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); d M4 A+ ]0 d: v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 y- Y. j0 I2 m8 P
0x00, 0xFF);* B% p0 I7 l# L+ H
% [# I7 A2 h8 P$ c+ j1 _
/* Enable synchronization of RX and TX sections */ . J# m- k5 f" w0 z* h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 y, z' K. N- C' IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- F9 L. N# [" ` r/ `& L4 P# zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ f0 f( w% F9 c3 y+ d$ L% Q) m** Set the serializers, Currently only one serializer is set as: k8 }3 O6 m" d- O# y% I7 w. n
** transmitter and one serializer as receiver.
- h( r' ^$ [( | ^*/
" A+ n3 M j8 y+ q- f5 ?4 `# KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 b: i, K6 Z2 L. t" ^3 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" w4 q8 d) I1 x2 Y
** Configure the McASP pins 2 t1 i, @( d1 k
** Input - Frame Sync, Clock and Serializer Rx
7 r2 O4 `' ?6 L; W" ?; p! ~$ _** Output - Serializer Tx is connected to the input of the codec
4 z2 @, C* u) z* y*// n; b S" K) K G5 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ l9 B: `1 s6 [0 _* Q% _$ A3 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, m* W7 U+ s1 b! CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- [8 V5 f; O5 f2 v6 N4 B
| MCASP_PIN_ACLKX
; B. ^% T( X1 Y0 g| MCASP_PIN_AHCLKX
- r; q/ W) |& {* b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# T4 k) \0 [" Q& G! J1 G3 b1 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' p8 |. M5 U8 U# Q: N| MCASP_TX_CLKFAIL * L' I3 p# ?7 Y2 u6 p7 }1 f
| MCASP_TX_SYNCERROR
7 d! p5 y8 ^( s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 A- z6 _/ M( d
| MCASP_RX_CLKFAIL9 g! r u( d5 S& `% C( C8 I' j
| MCASP_RX_SYNCERROR : o' h1 M7 Y0 G% {7 f
| MCASP_RX_OVERRUN);. \$ E4 z5 B3 j* h" j& Q" k" b) u
} static void I2SDataTxRxActivate(void)4 e0 ]. `7 B. A c/ d. ]" o% g4 t; }4 i
{1 o. s4 ]% f% t* F+ s5 _; \
/* Start the clocks */& B; X L C6 q \! D+ U" v+ p: x Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 f* K' }' {7 ~% f; cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 F/ S h$ b8 j! E) b }/ c uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 j+ T* z- j' u; h+ ^
EDMA3_TRIG_MODE_EVENT); q9 I; E3 w# u" z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - f! Z8 T# T( m, }6 e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* M: X6 y/ ~5 [8 d/ i: x6 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' O, ?( c" f2 j* B, M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) r1 _( Q, Y: I1 I' ^9 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" r2 J4 s( f1 V% `# r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& n& v7 z3 i6 |! ^" |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 Z" B8 l4 u$ N- b, k- @2 D}
" w) h) \" I, i* h) S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; V6 I2 L: a7 C7 u( M
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