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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' z- `: i0 A* t+ J' w0 {8 Uinput mcasp_ahclkx,
: N$ d3 d( h0 j3 V4 W$ Hinput mcasp_aclkx,
' _& n( ^9 ~3 J8 R* D# p3 zinput axr0,
! C p! F/ S* L3 Y, P, U
% {/ x. L9 ?( zoutput mcasp_afsr,2 a. u1 A7 x" g
output mcasp_ahclkr,, {% p, Q' k7 X, ]' @
output mcasp_aclkr, t! L3 W6 h9 ~
output axr1,* T% C/ |; v4 n6 V( i
assign mcasp_afsr = mcasp_afsx;
& P2 d/ j) |. I; |- z$ Gassign mcasp_aclkr = mcasp_aclkx;
( p' C1 j1 E f- i( ` @assign mcasp_ahclkr = mcasp_ahclkx;0 B: X" o) F3 {) i
assign axr1 = axr0; 5 ~: B- ]" |" L
5 ], Q& \9 k* }- N% w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & x, b) E$ I2 h5 h! h
static void McASPI2SConfigure(void)" [$ G6 S( M8 U+ O' v8 V
{
5 }. m g% j) A7 Q% I! x! `% Y/ XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 _; q) u" @9 g' S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% b6 }; C1 X- b" {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ `# V: G* o6 n( F/ H3 B2 d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 l1 R1 W; D6 A+ q4 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 A; B& f$ T% W8 m$ f7 N, jMCASP_RX_MODE_DMA);
; r, q" r$ p0 s @9 k5 Q" P/ t' J7 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 u& Z' Y5 E7 U1 n# I2 r+ z; |+ a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! O& v' `1 P$ H" M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ f2 v; Y! `$ X5 J7 K3 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( O" G- F* x- N9 X" _1 O4 c. C; \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" @) K j) O! ~9 h0 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 \7 j4 _( m- i3 xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 {) E5 E$ \' e: F( u7 e. ^+ F1 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 M1 u6 H3 \) v9 s7 J6 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 m @3 D4 C, B4 K7 V0x00, 0xFF); /* configure the clock for transmitter */( A, H! p2 R% s$ Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* c: _/ n+ b* ?# [+ w4 Q: @* v% T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. Z; w* N2 Z0 d, X9 tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, h* n% S' I7 ^0 ~; N
0x00, 0xFF);; l2 T7 G8 w+ o2 o ` j# s
/ w: G1 }/ m2 M T/* Enable synchronization of RX and TX sections */
9 ~ J8 V' o1 g1 z: `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 f, T* J6 F% v3 r1 LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 e' ~! T4 y! Q; r( Q2 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: O- @2 K* H5 F* O9 h" ~0 I
** Set the serializers, Currently only one serializer is set as
* [8 _0 g1 o% a** transmitter and one serializer as receiver.
, \# O u7 i$ V u( U; i+ G1 |1 |/ }*/0 \/ q. ~& ?5 @7 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( Z, W- N3 `2 N9 ]6 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ y; G& y5 `. W5 ]6 M z1 A6 \1 D% _** Configure the McASP pins
- Z; Z# M* @, u J** Input - Frame Sync, Clock and Serializer Rx7 E6 g. R$ Z# _
** Output - Serializer Tx is connected to the input of the codec + ]" f( u7 m: A, Q1 O: \
*/
0 G" d+ j$ Z6 B) z5 p! ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); S$ g W; y7 K0 h7 s3 b# _1 j% L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ p/ u% {2 ]' A) F' T. y; w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 O4 O" z5 v5 q; a3 ]/ k| MCASP_PIN_ACLKX+ Q, C) p+ q7 ]) N; C- X/ t
| MCASP_PIN_AHCLKX; T* U, }* D+ r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 x9 G5 O% P6 u2 E% RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 G7 o( U" K& M
| MCASP_TX_CLKFAIL ' [$ s( b# b- b3 W C6 ?
| MCASP_TX_SYNCERROR/ k9 \* c9 v3 |8 P; V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 |- S) n, C9 u4 w% {| MCASP_RX_CLKFAIL
" ]/ I; b3 {, L& s| MCASP_RX_SYNCERROR - K0 F7 n' f( m, u- \, y; a0 T6 G) H
| MCASP_RX_OVERRUN);
+ o; E! M6 o6 l+ {} static void I2SDataTxRxActivate(void)' U' k1 [/ v0 l; K6 @
{
9 b6 j3 L3 H. V& Y* p- o5 \7 S! h8 k" b; r/* Start the clocks */8 N9 R# s4 E9 X: L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, f) e% i1 |6 Q( v. m- _, ~1 C* uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 k3 y$ {# d+ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 F1 s* X2 c- d* s6 K7 KEDMA3_TRIG_MODE_EVENT);: Z. |2 y& o' V0 }* x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ b5 t0 g2 O; F. a8 t+ ~6 J& z- M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' C8 @& r, G- N$ h7 d! nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); L1 {6 ~/ r! b) z' T: H! s. H! \. \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& S, s' V2 A8 d+ T" g" Z4 P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 m% `# ]+ h+ e% FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ g+ M: }& v: c W: aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) @; p2 j9 t- i5 m( j
} 6 l8 y* ^' g% S9 J+ ^( f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 x. p/ Y% u; o( I7 Q( p% L+ ~
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