|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: v1 ?5 R4 ?7 J8 \
input mcasp_ahclkx,
; E; K; F4 v' y ainput mcasp_aclkx,$ ]- T! {+ j& V
input axr0,2 P. }( @/ ^ n1 [% Y# A5 |1 V8 Y
2 S3 E" ?+ u& s. R7 A% _
output mcasp_afsr,
4 B r5 t6 ?7 n4 y2 U( l& Aoutput mcasp_ahclkr,
/ L3 v9 S0 N& |* g9 coutput mcasp_aclkr,5 S) `' L- y2 w+ m( x
output axr1,
3 n' p- q; i1 r8 d6 u assign mcasp_afsr = mcasp_afsx;! [4 ^ J( y3 P" b
assign mcasp_aclkr = mcasp_aclkx;
# L1 T8 x. k4 M8 \. W4 a' l! O8 Wassign mcasp_ahclkr = mcasp_ahclkx;
9 Q5 A; Z! ?' _9 L+ R' _; bassign axr1 = axr0;
0 g8 G% ~/ t6 l% R, M9 {% D. v, z5 O1 s0 T# H) f8 |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & U k5 A9 u: I ^
static void McASPI2SConfigure(void)9 y, f; a+ p/ o5 n
{
S- Y1 Q2 W( x. c0 e* S5 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! a6 L; C5 ]% R8 @; N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 y. C* K$ B: q* D& T# E1 jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. g; `# ^: M8 W; L( L0 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. W9 v! [# Q9 @) c% `3 t8 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 x& U! Y! \0 N% u3 r
MCASP_RX_MODE_DMA);
$ c. i: R& R: m! h2 YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ t: @8 o4 y% m6 L4 pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% k6 ^: P" F% b- C) `5 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , [) t$ d" K0 |- N+ O( `4 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 A2 l v8 `/ @8 d2 J3 r" i( W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 h" u- c1 I& {( X7 Y1 M" L8 q* l C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 i% b+ d/ N |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 R9 ~; i2 ]/ F0 F; S ~, S, e" L, }' }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) @/ y( J- B0 R, @ L% y8 z6 o( u9 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
z+ a. G+ j( S$ `: K0x00, 0xFF); /* configure the clock for transmitter */! X* e- S/ M: _1 N& ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ l- q' y5 c; P) a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& b. O0 c0 M' XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 D; k( _7 @9 ~7 ?
0x00, 0xFF);
3 h' V; ^5 k0 l: x4 B: _! b; S( A; Q1 `6 `8 t! T) W: ?9 H
/* Enable synchronization of RX and TX sections */
# C; ]- d! q- HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 b( L0 n. R" F1 A, ^6 V; l- r5 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. I4 b& \& g N$ O3 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 E) G& T, {' D; J- S** Set the serializers, Currently only one serializer is set as
, H% x9 w3 D y, ~0 A** transmitter and one serializer as receiver.
) Y( ~2 C1 n0 x. x$ r*/
9 K* P, p+ Y7 J5 F& ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; ~- D- E- k6 _% x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" n$ T9 z7 ]9 H1 u** Configure the McASP pins 6 Q" L' U6 K# U% l* ~ ^2 F$ J
** Input - Frame Sync, Clock and Serializer Rx
# g ]% R; S6 Y7 C** Output - Serializer Tx is connected to the input of the codec
9 } a5 P5 k# j0 f* D3 h+ ?8 |*/5 D7 ^! K" H# h" y) N) a# i5 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- L! F8 Y: J3 C) u# z" C% Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 Y {' V+ e1 P0 P4 b3 A n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! G5 T1 w+ o1 j r. {
| MCASP_PIN_ACLKX
G6 a6 V; i% B, A- \% ^4 z( o| MCASP_PIN_AHCLKX% c; _4 J3 a1 J) W. _) f$ M, \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 B& p& L5 L1 F5 H0 h' w% o5 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, B2 Z4 w' _) _! E7 P| MCASP_TX_CLKFAIL
/ |9 m& W' v$ e2 v- E. y| MCASP_TX_SYNCERROR- v0 \, w9 [6 r$ B q' U, I9 l2 J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 V. U+ H& X& Z5 H, n# @" G d| MCASP_RX_CLKFAIL' m* [0 Y; E6 j8 }/ x" D
| MCASP_RX_SYNCERROR
, H- x2 n, L7 a% ], H/ @. i& b| MCASP_RX_OVERRUN);
6 V l# ~" q+ r9 h f} static void I2SDataTxRxActivate(void)' A1 U/ e; i6 Y
{
5 t* `& b% [ T: h; Y; b6 ^- n& a/* Start the clocks */
" \3 w G/ u/ WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 ~4 N- z5 h& B+ G5 [/ G; b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 w; B7 J% l, f3 z/ A R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- n' B# W t! V" h4 X9 T- SEDMA3_TRIG_MODE_EVENT);( j; r8 V, d( E+ l& s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 Q6 W* \2 ^9 e, ? g$ J4 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ~8 x& y. X- B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( o) t+ _1 }4 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# L7 d. h% |1 l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ L) {, o" |* z1 X$ g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; A6 j/ G0 N0 s$ {McASPTxEnable(SOC_MCASP_0_CTRL_REGS); [" F2 U: T7 o- b+ ?4 g$ e8 j
}
, o+ N& M0 D. N. r# f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 \# i! I3 R0 P* o. c- R |