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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( K2 T% A! u5 S0 n d/ Z3 _ \
input mcasp_ahclkx,! A: y o6 m6 o" H8 h
input mcasp_aclkx,
2 R( r2 m' E% E- K* h) b: qinput axr0,
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output mcasp_afsr,4 g, I* w7 j! q( R
output mcasp_ahclkr,! ?$ u) D* d2 j4 {, n$ }' u
output mcasp_aclkr,
6 ]: w. P7 v2 }* ?4 |2 E4 W4 v( |output axr1,1 S8 p* X& S( E; @7 m) `- N: m
assign mcasp_afsr = mcasp_afsx;6 W3 |1 Z2 e! ]- G- @! w
assign mcasp_aclkr = mcasp_aclkx;( u1 `$ k. `+ A5 H6 X- }# r
assign mcasp_ahclkr = mcasp_ahclkx;, z, w7 B9 z- V9 k$ N: {
assign axr1 = axr0; 4 T: B, ~$ L4 y# x7 W: K
9 F3 o# t/ T. ?, r" Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . ^# s2 t) a9 C' P. H
static void McASPI2SConfigure(void)
- Q' B2 @" |1 b! A {{
& f, J0 m6 {! W+ K' G5 A6 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% ~) D8 t! @: x, N% `4 S2 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* `( g" L% [6 h, B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- x9 B! h) G9 Z! v' W7 ~& \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 n& A9 P3 n7 m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! i4 V; s3 R8 G2 j" j( Q9 Y- yMCASP_RX_MODE_DMA);7 M% h+ v4 T+ [3 _: v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, n/ S+ G6 }; j( {5 W9 W& sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; \0 C5 r( Y8 A4 Y) I8 M: b3 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, W* D1 K3 X' \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 {' X) W) [. ]5 e TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ v0 C: F6 E3 c5 g' y* P6 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 K& P. B. m3 n# b' r5 SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. J/ B: Y0 g" L" YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # z ]. F8 H, i/ H0 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 m6 ?$ J4 D7 d/ P# `0x00, 0xFF); /* configure the clock for transmitter */
# Y/ a% {* Q; D6 Q: \: J" HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 D, H. {& N- vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 W6 E' g- _% v8 W. e" v1 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 S3 Z! t3 `6 X" i* L! R/ L0x00, 0xFF);
! T/ O) p4 [1 l k% y
* I% f: g# d* [/* Enable synchronization of RX and TX sections */
- m" P9 Q# Q [0 l8 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 s! x$ t) p; g) M6 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' t* q6 S! G( G# h& Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# B, v4 V+ `( m0 }- M4 P/ \* B8 @** Set the serializers, Currently only one serializer is set as% ?2 O! h5 ^+ F" p& ]2 V
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 B; V! l. a _% [6 `8 N/ x# I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 u$ E% o) E. n$ Y- p" y9 g7 b# |
** Configure the McASP pins
4 y! y0 Z0 _& P( r** Input - Frame Sync, Clock and Serializer Rx
6 F) b4 X; ^- E( {* e* w2 p! n& `, [7 z** Output - Serializer Tx is connected to the input of the codec ; C, f! V1 u( Q' h
*/
+ t: I. [8 S9 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 w! E: A/ Q& S! I' q. oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! P; N4 w' ]% J1 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: O- [& L, Q$ y. x6 c5 I
| MCASP_PIN_ACLKX
+ o3 u3 i* x7 s| MCASP_PIN_AHCLKX
$ n/ O. M- d( A8 d; T* Y* q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) q: I& P: }. U! U( D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % S( @8 Y+ f& E1 R% J0 d! f0 L
| MCASP_TX_CLKFAIL 8 a: ^/ o% @5 N" _# H+ j+ c' M
| MCASP_TX_SYNCERROR3 ~$ G' y: d+ ^$ l3 P& H0 ~7 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 }/ x2 a; t4 x" V, P* i+ C| MCASP_RX_CLKFAIL
" Y5 c& Q6 ]) ?6 C' F4 E| MCASP_RX_SYNCERROR
% x4 ^$ h0 v; Z| MCASP_RX_OVERRUN);$ Q& V8 I5 l+ A! t0 y0 W
} static void I2SDataTxRxActivate(void). H. d7 S& w1 G7 E3 d3 k$ F
{
# V+ U, b' w! G* Y/* Start the clocks */
, M5 b# ~* Z9 y. M* y2 o% \2 uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. P# x) l; t* r& L* s) G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; j$ v6 V! X$ Y1 ?* X& C, K2 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 X: P2 S' q) e
EDMA3_TRIG_MODE_EVENT);( k; S8 |; i7 |0 j5 {0 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 L7 e( Q* l6 A" U1 f: A4 EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// E% d" `+ l+ m' R J: \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- \. j7 u; w; T* r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; x( Q, ?0 I( D( s" N# }' b5 twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ ^, D, }3 z' S# m; V: hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 ]5 r$ F: o) E; \: i3 M0 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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