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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' w3 g3 M5 R w* `( z( X
input mcasp_ahclkx,
. c: e% A+ o! Tinput mcasp_aclkx,
: T0 I- q$ j" ^4 R0 J# O- g+ F. ~( `, _input axr0,
$ Q: A, k Y8 ^ k% N3 a; l* f% }
output mcasp_afsr,2 A) U+ F# ]" }( a% Z
output mcasp_ahclkr,0 e+ [3 `" R+ T0 V% X5 a9 g2 v' S
output mcasp_aclkr,6 h: g/ r4 Y: H( |
output axr1,; M0 x9 [* {/ u4 u" X1 A
assign mcasp_afsr = mcasp_afsx;: y/ P9 A7 w, ~( Z8 r' l
assign mcasp_aclkr = mcasp_aclkx;6 p2 w. C$ j1 \- z% [2 l9 e
assign mcasp_ahclkr = mcasp_ahclkx;
) E# l$ M: d8 q" t9 _assign axr1 = axr0; " S& k, T+ f) `- z. g+ [! r! w$ _
9 T; y% ^9 f4 t! N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & l1 P3 |, T) W+ Y7 y4 U5 d$ U
static void McASPI2SConfigure(void)
8 R1 V( T/ ?% M0 I{
2 Z+ s; {) S9 w( zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- C0 h4 A7 k' Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 h3 Z( [; m/ ^7 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; K8 y/ l: M- S9 k3 K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 r! ~$ K; W+ a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! O j4 j* x Z) s& U( r7 ^MCASP_RX_MODE_DMA);
6 M$ {) I# W/ Y5 r# K4 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& p3 D0 f7 m; A! i$ V" Z- Q8 L2 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% U, Y, Y% X p+ C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 f. s% R' Z, C) XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, N) k2 z( y% m9 m' XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 q( d4 I& \1 Z0 L' `% ]' NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 t u/ ~0 a* Z5 s+ yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 f5 v# W. `; V( \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 U3 p B& b9 O5 A! mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
U8 e5 \+ N# H/ ?* |7 l* i0x00, 0xFF); /* configure the clock for transmitter */
& b5 `1 x' n: TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% [% Q! Q* B0 L& i9 K) C c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' x3 F8 g( p8 P2 ]# k0 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" Y. l0 X4 d4 X Q0x00, 0xFF);
' g: a" J3 m/ ^! U# {; X% d
- }2 {2 T9 [- L$ G6 a/* Enable synchronization of RX and TX sections */
9 j0 y. I) B3 q* n+ D; DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: q5 C! ?* _0 z. S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 u2 H& ^) C5 a( ?# W; L6 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! }/ }, q) u) Z0 ?3 K: s+ j8 t** Set the serializers, Currently only one serializer is set as* i4 ^5 u* D, x* q3 s5 i
** transmitter and one serializer as receiver.
6 e5 Z) J: Q. {/ D9 d% M9 |5 ~*/, y$ F9 U6 Q2 h% G- A% T. L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 S3 e9 F* a5 d, _2 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; V4 i' ]1 X( A# Q5 n; p7 m: p/ v** Configure the McASP pins ! v; Y5 s% N4 Y# y( a& J
** Input - Frame Sync, Clock and Serializer Rx6 x/ T# Z$ ?$ P$ p4 [) M4 z
** Output - Serializer Tx is connected to the input of the codec
5 F9 H L- Z% Y$ }*/
1 R+ Y2 v6 c$ A! y) R$ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# Y- \" l, D8 F! U9 V" f! T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 ^! ]: J @: F+ k7 g, U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( B' A+ m- ?, U3 }| MCASP_PIN_ACLKX7 x' t* a3 |0 z, S* J
| MCASP_PIN_AHCLKX
+ K2 `+ j1 h& P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 A3 Z9 M+ \4 I! {% eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 W9 Z+ K, w5 ?# l1 g+ m* I9 |$ J* G8 R4 x
| MCASP_TX_CLKFAIL 6 U9 Z& ^' `- O+ F9 R
| MCASP_TX_SYNCERROR# E' M* Z. z% `" E& _" \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) { b W$ q& F* B8 D| MCASP_RX_CLKFAIL a8 i! l9 B% t( x+ f }
| MCASP_RX_SYNCERROR
5 T" g2 m9 u9 Y z| MCASP_RX_OVERRUN);. g. v$ w. }" `$ v) W; N( s8 Q
} static void I2SDataTxRxActivate(void)
! x/ Q/ b8 w( x# {8 i6 a& p{& m) n7 Z7 Q" ^; D2 n" A0 c0 h8 C
/* Start the clocks */
8 f4 a/ c/ {/ U, X4 t) IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* W. G( I' W! C2 O7 ?0 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, |" k9 @( P- Q& C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- e* e1 v* T6 Q$ K! k- H2 F9 u
EDMA3_TRIG_MODE_EVENT);4 B! O9 w! Y. H. {6 c7 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* W* a2 K- j- _( e+ o, w7 ?& d# iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" e" k, e* t3 f# }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: g! }7 }& Q+ `- [7 ? ~7 f9 |. eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 k# y1 o! H5 o9 cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% k$ p# {9 {, P7 A! ?0 y: |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ m/ ^. D& F P7 D/ p' N. lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' C; `- x9 J5 v
}
$ v, X4 |6 A$ L" E4 U3 w: _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) u- s k) Z% u) g' h0 Y
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