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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 Y% m9 Q( _% Q' \( U, R; U7 Q
input mcasp_ahclkx,
$ B5 T1 K" v' R( f# ?3 Winput mcasp_aclkx,* b0 L6 |. \7 x& |; Y2 q) d3 ?
input axr0,
; A& X. g( v& W# F ^5 P
9 e0 O1 J* [3 p youtput mcasp_afsr,
8 ?5 N6 R) z: @# joutput mcasp_ahclkr,4 ]) s) p/ w' R9 x/ C2 J$ `3 d* f
output mcasp_aclkr,
5 V, B5 k# }( a( L# Soutput axr1,9 y& x6 ]0 K) N3 `
assign mcasp_afsr = mcasp_afsx;$ v6 G7 S8 _ o, Q$ K2 T
assign mcasp_aclkr = mcasp_aclkx;
; `' x; T9 e# I5 B$ j; P6 z0 b( dassign mcasp_ahclkr = mcasp_ahclkx;3 G) A3 z& ?, x3 Y3 `- I! L
assign axr1 = axr0;
3 c3 B D8 V2 R1 ^/ n3 i) g3 \0 W7 g* _ }# |0 W' B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & [* h3 }& H/ c8 L) ]1 Y
static void McASPI2SConfigure(void) @9 W/ ~; L4 k% f+ _0 A+ e
{# d6 _* T8 p; s& ?) G8 m! ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 o$ a' h0 H$ V, |; }- uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- L; m: g ?% E, B# \7 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. m1 w! U( X* E( t7 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 t( ^) Q7 J9 E/ [0 K& u4 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, K' z' B X2 u. C1 n
MCASP_RX_MODE_DMA);
% t0 q# V% H! Z+ O4 AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. ~6 c E8 x! l$ ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" K. a! M! D3 a8 {0 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) c* w/ C! K, e" A* \! VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 j6 z7 o) a3 C4 R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * c5 R$ B6 H+ X9 V3 c, i$ O5 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# n0 t( Y. J; w* C1 e) yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ Q2 [* i/ p, e7 V' u8 i0 yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 d! m8 D$ p( z- @1 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; u w% f1 w; o& m$ l! w0x00, 0xFF); /* configure the clock for transmitter */& s1 C- f0 Z* f6 s# i' r: |+ G3 y J# h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% e8 ]6 @) N, @! u% }1 j' g7 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 t+ ?* t( y( v2 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 ~4 d8 E4 E5 y" y/ F) i2 R0x00, 0xFF);
" [( W2 c, ?7 Z7 G% h& u/ F# X# A- y2 t; b$ @5 ` s* |
/* Enable synchronization of RX and TX sections */
0 q+ Y! _0 s# @9 R KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 ?/ T$ B' c7 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 p1 [4 ^$ M0 v( J: W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 S3 n! P% G# O& E9 u( B7 ]% W
** Set the serializers, Currently only one serializer is set as
, c& g. x/ N( N** transmitter and one serializer as receiver.
^, G) b# Z3 O% }*/
2 |; e* ` b; S0 Z; SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, R( ^5 S, P* a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
M" i9 X S, A+ i: L2 o+ F** Configure the McASP pins . u, y9 v0 p; D( w- r4 ?7 b
** Input - Frame Sync, Clock and Serializer Rx
0 I$ g+ E: g; u7 m) [! J9 \$ z** Output - Serializer Tx is connected to the input of the codec
# G6 ~) V: d. I- `0 }$ q*/3 s6 S5 u- z7 I& K/ W# o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 h4 `0 l3 T u0 |# [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 V P; ^5 H' E3 }8 _+ SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' N1 q, E8 S) D1 o
| MCASP_PIN_ACLKX
+ J" i: m9 U9 p! y( D. y| MCASP_PIN_AHCLKX2 I! g" `% J* w, |3 x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 h. W8 R4 T9 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 C) W8 K! A2 r9 Z3 W# G1 I5 M# R7 D| MCASP_TX_CLKFAIL
' q+ Z; b+ G/ W* @1 ]| MCASP_TX_SYNCERROR8 a) s2 R, V2 |( x" }- n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 n# l {0 v! _$ t
| MCASP_RX_CLKFAIL
: z9 J5 o! |7 q' [| MCASP_RX_SYNCERROR W' D% n- C# N( |6 J3 b8 g3 o$ @, N$ b
| MCASP_RX_OVERRUN);
3 B$ I. w$ A; m: p/ ?& T} static void I2SDataTxRxActivate(void)
/ E" r; w3 `; }+ u# b3 L{: ^$ f. {4 l& [% d* k; ^
/* Start the clocks */2 ]! @! v7 _% c+ ~: t* v) F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- w/ x& D$ { {4 J1 Z! s7 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- N( ]. X5 x( A% q/ A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* t1 h1 T q& [: y, V+ F4 ^
EDMA3_TRIG_MODE_EVENT);
3 P l( P4 `! OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 G% k% L$ v* x* U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ L! `- S" H* Z* N) d6 q# H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% p. w0 ~8 p* tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& ~) u7 D* d2 e' }' f4 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- E) z5 P5 m8 d y9 e; ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 L, [; U. \- G7 Q$ L8 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# T" Z, r3 E7 g4 h- a! O
} 0 k) J/ _1 ^9 ^7 s( E/ s4 ]. z2 G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " X/ }; M0 N: c
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