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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, ^5 v' ]. u0 ^( Iinput mcasp_ahclkx,; c& g6 }. F) `- ?" M6 M b
input mcasp_aclkx,0 V# K$ ]# O7 F, T2 m, J
input axr0,
' ]" A4 Q# K; ~( l$ U3 V. ]0 s/ C- D
1 W$ n' U2 M+ C2 [* Q! Joutput mcasp_afsr,
0 G8 q9 ?6 t7 m( d3 q6 m2 doutput mcasp_ahclkr,
8 g' P# @. [3 W/ }. o% J/ _% Youtput mcasp_aclkr,% o% P+ m h) p: k2 M H4 W' L
output axr1,/ D, D h. H1 ^* }6 G. c
assign mcasp_afsr = mcasp_afsx;
- \: \8 M R, p+ e/ zassign mcasp_aclkr = mcasp_aclkx;- D" M- ^% n" @" s# Y$ R: \
assign mcasp_ahclkr = mcasp_ahclkx;6 V; ~0 V U% E% v# S
assign axr1 = axr0; ! L- U/ p# ~" }% f
1 ?: w( w$ Y/ x2 O) |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" r7 j/ H, w5 istatic void McASPI2SConfigure(void)8 a3 [+ A* M, [# ]7 ` r
{* p. C6 x. L. J" U' v( k# { T0 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) i6 N; k& i! X7 j% B8 s% w* |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// q3 p- s* ^" ~% g1 z9 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 b. @7 {# g7 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 \1 E. j2 A: }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 P2 R3 M- F# y. p/ I6 [1 ~MCASP_RX_MODE_DMA);' e& s" a) n! ^/ }+ q: u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ ^# i" J. @+ l2 P& M! E" W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# n$ @0 ~( k8 H& B1 Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( Q& y* t% b T4 `6 v! W: T2 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& J: K. a9 z3 Y2 S. ]. s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; e- x/ n1 `+ k5 B5 Y6 ^+ M% l( [* [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 V0 w h1 J( D7 d8 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: T2 |6 e0 G( T, x6 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 I9 w/ k' }! G% o" C/ C6 TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, e4 H7 y8 r% b; R
0x00, 0xFF); /* configure the clock for transmitter */- K1 k9 }1 f/ ?2 ~8 {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# a* F- s) B, L( w1 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 Z5 |7 T3 F$ t4 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. \9 y2 C; b: }: d7 w; A
0x00, 0xFF);; W3 r7 H" D3 d* r, t% A
$ K6 h1 z l+ u& k7 n6 i/* Enable synchronization of RX and TX sections */ # m$ P3 \7 S2 l( Z6 P! V. O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" U# L1 a2 q) n# E# w4 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- r6 }# h0 w, y1 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& r9 H& o9 L+ s4 P$ X; t
** Set the serializers, Currently only one serializer is set as
9 g5 w8 H* d5 g5 s3 t. h( A; L** transmitter and one serializer as receiver.
! Z" J0 N3 j1 r2 D*/1 }* @, D5 T& z1 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 @, w3 m6 W' } W' a) x& ^1 ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" Q# u& x( L8 J
** Configure the McASP pins
) d1 K) ]3 S& N9 F** Input - Frame Sync, Clock and Serializer Rx2 B# N9 r9 X v; G- A" [
** Output - Serializer Tx is connected to the input of the codec
/ R |% O+ g! B! U' _$ U*/( p. K# w& C: \+ N& Q3 h4 ]2 v) T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- W) A; s7 M$ s% q8 B4 x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 r$ }4 G9 N: PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) j; t2 }# N/ g( r5 ?" a| MCASP_PIN_ACLKX
1 U4 U+ y0 [7 [ T4 Z" }, _) J| MCASP_PIN_AHCLKX
' ]0 @* ]3 l4 T9 w3 ]0 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ k& J% q% Z2 s8 I7 e s" H1 @. H" {, N9 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! F8 D% J+ U* A5 T- g
| MCASP_TX_CLKFAIL 4 y" D( s4 @1 h
| MCASP_TX_SYNCERROR/ A h7 i/ `: i0 p( P, m( E5 `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 l: L& H- E, l) U; H| MCASP_RX_CLKFAIL0 R- ^2 O6 d6 N1 V9 j$ m5 s c, b5 g
| MCASP_RX_SYNCERROR 2 p+ ?! X7 k [) J# ~/ h% D2 m$ Y3 |, m
| MCASP_RX_OVERRUN);- I9 n$ V% l( E `+ J# z4 p
} static void I2SDataTxRxActivate(void)
) W9 X6 i6 a0 s. i3 [$ g9 f{" ~& }3 t/ s" q, F4 d; A
/* Start the clocks */% B2 n! K7 g9 K0 h$ }) V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' W" J* h6 D! HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 S7 Y8 s) {$ R5 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( c4 p: ~6 i0 s6 ]% m. P6 c
EDMA3_TRIG_MODE_EVENT);" B2 l. w5 z) k, t0 |5 s$ Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! u: M' N2 o; e# k6 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 n- ~1 z& U% OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 B' W# P. K- i. Y; i1 B& oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 _3 N( E/ Z# m, p7 E r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
w" o+ e0 v0 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# ]/ O" t6 R% Q9 S/ e% }& i* HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; b1 i( z; A0 }& b
}
$ S% w- {( J9 E0 R9 s7 O/ j, n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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