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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," ]7 x8 j) W0 G6 _' Z
input mcasp_ahclkx,1 v" D2 n) ? u& N0 s$ R
input mcasp_aclkx,
6 d# ]- a( n) M" Hinput axr0,& O0 }$ a. C, W) a
3 }, d( h6 }7 q0 e. aoutput mcasp_afsr,
2 K) l; p2 t) c# L) B* ]output mcasp_ahclkr,
" N' m6 `) C" j) w# d6 ?& youtput mcasp_aclkr,$ g/ H% @% J& z$ L
output axr1,( Z+ h- Q$ k I; P0 a$ V8 ~
assign mcasp_afsr = mcasp_afsx;
" T1 @* T1 Z3 P( N/ Gassign mcasp_aclkr = mcasp_aclkx;( H8 j: m3 q2 P* |; S; p
assign mcasp_ahclkr = mcasp_ahclkx;" m" n! _+ R& j' F. ~/ y6 N5 v6 v
assign axr1 = axr0;
) F @- h$ P r# ]# d/ V3 p4 o9 r% Q- l- ^. \* x1 M2 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 j) E& h' H& Z$ U& d+ Lstatic void McASPI2SConfigure(void)( S% A, j1 B1 L
{
' \1 e" J6 r# r; _7 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);* a. n+ s* V. U. z7 i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* w8 V; _. L- y7 Z8 i8 W2 K1 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
_; n) s" L# P! H+ lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 `1 F8 Y- o2 ^3 t8 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ~/ R. s6 |- y; U8 J
MCASP_RX_MODE_DMA);
% p0 `+ P& J7 o! g$ [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- b+ _. u) }# m% {& @* ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! W6 p+ v/ ~4 g5 }7 W# d7 {+ u+ eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) J. F# }( {- @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; a W& t/ x+ P9 r: W* I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 [3 h$ ^! m, M9 l AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. N* l- I* h+ h" d0 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, q, s9 b7 Q/ e+ p" S4 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 {2 ~: v# |# T) m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; z# A% C1 W0 g! D# p, L0x00, 0xFF); /* configure the clock for transmitter */
2 b z! p* C3 H8 I; s+ H) J5 BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 h. i8 v4 E5 ^5 i3 _" c, ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % w; X: a9 C8 g9 |& H4 O/ `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( |$ |' W, l+ v e6 ]1 h
0x00, 0xFF);$ P, O5 |! T d# z3 \4 K
" B0 ]% P% A r: f3 Y$ T1 x3 I1 o
/* Enable synchronization of RX and TX sections */ 3 o1 q' D) A% l, W8 ]$ Q# a6 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) p; }; p- z3 x6 B+ I% B! d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ R4 v3 v" [/ r( f1 ?4 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 z1 Z+ P# V5 o** Set the serializers, Currently only one serializer is set as1 O: {& q `5 O. B
** transmitter and one serializer as receiver.
! W+ c, p3 x* [2 h: r7 v*/; [2 }6 ]7 {& q- t! P r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 m9 }& A1 Q, w& `, a1 D5 Q* PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 L" F V% h3 z4 z" `
** Configure the McASP pins 3 I8 Y; v& F* C. x9 h% w
** Input - Frame Sync, Clock and Serializer Rx
f% @% Z0 t5 X** Output - Serializer Tx is connected to the input of the codec
' t& c7 t0 l2 m, A( @*/
5 U3 u6 B3 R* D( Z1 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* s4 Z) f5 F1 G- ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 i; c9 c ^! z6 K' B: h. Z$ k5 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX k U; u' j- C& U3 [$ w
| MCASP_PIN_ACLKX
7 v: B7 t0 K2 a+ T& I9 ~5 n) B, g* G| MCASP_PIN_AHCLKX
3 ]0 f" F% u% \9 Y* w) u6 S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 \# G5 d( j2 B* W0 h8 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 ?* U* e) a8 [: H
| MCASP_TX_CLKFAIL
; E' j+ h( m# x! x, H/ ?| MCASP_TX_SYNCERROR
# y1 t5 {) N1 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 L7 c$ `! H0 J+ ?
| MCASP_RX_CLKFAIL
4 P/ x$ l( I$ A6 I& k| MCASP_RX_SYNCERROR
0 e/ j" [( Y O0 ~/ v| MCASP_RX_OVERRUN);
; }0 ? j( F" u z" s} static void I2SDataTxRxActivate(void). v. i3 d$ K* V) `
{6 c5 l5 d4 A6 P D5 w3 P9 C1 z. K
/* Start the clocks */! c5 p4 j5 q8 ?3 u( [: Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* B2 |" T: B: O0 W+ X1 X: F2 i+ P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: [ A$ B) Q8 [7 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 u: m2 S5 I8 L4 f3 @EDMA3_TRIG_MODE_EVENT);, T6 g( p; ?& J, X, F: M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' Q( l/ E4 r. |! `: c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" |2 w( L1 ?8 h# U; E, D9 oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 C' w% I( K/ a5 _$ yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' E+ B7 @- G g7 j; p: A" n% n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! U, c- S5 O4 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; v3 }, z2 Q7 O6 @( K: HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! g# f5 M& @, R& i* m* y& Y! ~0 \
}
9 ?: {8 R% ?/ u. T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % N2 _/ e/ q9 j7 s8 S8 S* W) w, t
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