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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 Y6 {: g: {; C! l8 V8 ?input mcasp_ahclkx,
' O9 p) W% k) u2 j8 J3 b" _& V% vinput mcasp_aclkx,
E9 z* d f% U U! b1 Sinput axr0,; N: }( a- V9 c' O |& X3 o( j+ T
5 p/ F$ a1 F Q; x8 h! j7 D1 Loutput mcasp_afsr,* E; Q0 ]7 b* U- R, N, g+ ^
output mcasp_ahclkr,* X" a! q4 r3 o' |
output mcasp_aclkr,
9 C" {2 ^# f" f9 Q( @& soutput axr1,
" Y" }' d7 v$ T2 d" @# n! p( [" D! M1 D assign mcasp_afsr = mcasp_afsx;
% v9 c- M) y$ g$ p+ Uassign mcasp_aclkr = mcasp_aclkx;
" t/ o9 x/ C. w) b) r. p' hassign mcasp_ahclkr = mcasp_ahclkx;( |+ Y5 j5 x: H0 B; ?& [8 j; B, O
assign axr1 = axr0; 7 N8 K' H- X5 V* r. z- ?; M! M4 @
! \4 _ z' d/ l* f7 `6 G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 K) c, ~5 G" a& Z6 c; t3 ~
static void McASPI2SConfigure(void)
0 o' L! b# M9 H( \8 ~ k# e9 }{+ P& ^% D3 a; Z) r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 U: O; E0 l* H: _$ Y+ Q* N% O+ c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( M- @- d1 ?4 l5 h# q" ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" i& C* j- l& R. s% V+ E3 A& fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- {3 ?: T4 Z0 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
r2 c# f2 m$ R, GMCASP_RX_MODE_DMA);. z( X. W ^. I" \4 X/ n$ d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ c! P4 @% ?6 @0 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ N5 J/ N9 ~0 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + |1 Y% b8 F6 J7 i4 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 r# g' O5 n, w6 a, oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- _0 e; I/ N) C. F$ FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 U/ a( R" A0 p/ R( U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 m$ |1 c+ K) k8 W$ p: Z! Y$ R/ UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; N4 c; j5 A0 W) a- q- j1 B+ T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 v" w& N3 i: L9 R5 V4 T/ j0x00, 0xFF); /* configure the clock for transmitter */( D9 m B3 O2 i* r/ _: |6 \' G8 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 ^' l6 E. z `* lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# I; E5 X. f4 S2 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 y( U1 l. v" c; r' \
0x00, 0xFF);/ x! S4 g/ t7 b; K! c% ~
9 K' @# Y$ g2 n, [
/* Enable synchronization of RX and TX sections */ 7 |0 N, s- ]8 E) P5 e" X0 `" E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 n; [, Y1 s! T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. i2 G: W) m% C9 o0 [* g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! u$ M8 l9 d: ~1 F9 r& Q. e8 v# {** Set the serializers, Currently only one serializer is set as
3 K- b- b3 q6 ~' s** transmitter and one serializer as receiver.
; U; y9 t! y& h8 o*/3 z$ n7 n: W' L) c5 M5 h+ ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! N8 o9 U: `1 ^0 P+ e6 M1 l/ Y. WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ {9 J% H' M3 p: M6 }** Configure the McASP pins
6 l2 m2 P5 H& ?7 O d8 i9 W** Input - Frame Sync, Clock and Serializer Rx
. ?9 I% U2 G, J7 q! g** Output - Serializer Tx is connected to the input of the codec
% Z! ]: R' ]8 Z9 b1 k9 e1 L5 L$ P*/
- E9 }" ?- Q) r7 T. OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& \$ k" y1 p/ d L4 _ q5 j- u: M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 C' O/ H4 S, |) [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ^. t% n! w: w7 U# m$ B* p+ I$ L& \
| MCASP_PIN_ACLKX
0 ~3 X3 M6 @/ l3 D8 i- v" K0 c1 A| MCASP_PIN_AHCLKX* ~' {& }& ^; ~) V t9 b' ^' N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ M, m {- ~5 ?3 p* A, xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 H1 a% [" o t( P/ {
| MCASP_TX_CLKFAIL . N* W6 y% f4 `
| MCASP_TX_SYNCERROR
5 c4 s/ @9 J3 F/ M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / Z1 g8 L: k, f' S" _0 k0 U
| MCASP_RX_CLKFAIL
' p/ }" L. q" o- Z! D( I3 t| MCASP_RX_SYNCERROR 7 Y$ k8 a# h8 b6 o" y
| MCASP_RX_OVERRUN);
* b7 X! ?- `3 y} static void I2SDataTxRxActivate(void)0 P5 r5 J$ P0 m) s e) ~
{8 y3 S8 M5 A1 ]+ I3 y- E
/* Start the clocks */
/ k8 Z6 s+ I* T. @$ Y7 F) CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 E& z4 K! S2 X. w* JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 [- N. L. n/ u+ h1 n; `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: i _1 J4 @5 ^+ D; JEDMA3_TRIG_MODE_EVENT);7 g# X) |3 a$ t1 S; [ P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ K, L: }8 _0 M% uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% ~% z0 G. ]# UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 A# F# \$ N0 n ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! G2 J3 ~0 a) D# p6 X: t& g* [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' A' R5 r( M$ K: a( e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* t6 [4 }5 C) p' K: z8 K2 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. [9 y6 H6 {! ~8 O
}
( G, [) n+ Y; y" ?0 L5 n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 g! f; t2 d( W0 u \, x& R: M
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