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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 C9 L2 R F) t) d; t6 I3 T8 f
input mcasp_ahclkx,2 Z/ F4 u: k. A$ J4 `/ F; R3 v
input mcasp_aclkx,
3 x6 r$ S0 b" X; i0 c: Sinput axr0,
. e* p: v1 u- c; ?8 h! H0 K
0 ]# o( x6 U+ l" y; |4 `output mcasp_afsr,5 H, V: m8 q8 D0 u
output mcasp_ahclkr,
* J( w. S7 `, A0 K5 o Noutput mcasp_aclkr,' |% X8 M! }4 h& W+ O+ q9 P; W5 j
output axr1,- O# F. ~# P8 U
assign mcasp_afsr = mcasp_afsx;! v9 d2 C$ b/ W! t
assign mcasp_aclkr = mcasp_aclkx;
6 E: o. l$ g3 F7 t/ Zassign mcasp_ahclkr = mcasp_ahclkx;
, M- Y5 A! ~, @* K- s" ?assign axr1 = axr0;
9 I4 s1 q* l1 ]% T- Z3 @* ]7 ~* M8 N2 O. L% f; R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
c f1 T+ ~3 g( T5 w2 z3 V+ ]static void McASPI2SConfigure(void)* i* i! {) Z* A; B# n
{
6 ~7 n9 l ~" O+ BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- V; F; F$ z: |+ O- g( _2 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 [$ M7 y; Y. o% W' _) |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, \- R2 e$ Z0 Y* i( [, c, t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! k# O0 o4 @( D, D* l9 VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 X2 c h) Q$ h& b" zMCASP_RX_MODE_DMA);/ o# K" U7 R- u- x1 m/ k( k# K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ I( o2 ?, l5 G" O3 V& \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 p% L+ D2 o5 k& n: g; u& vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# m8 T: i& x$ |, {+ b! b' bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& g2 s1 x( U4 i% S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ P& N& I% A* }: n- g% c* iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
R) T$ }! h3 Z$ bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
g9 E. t; K; Y J; C vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 ^) E. [7 i9 N6 T3 }# _4 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 q5 H& p' r# M9 H2 d0x00, 0xFF); /* configure the clock for transmitter */
+ o% S) ?1 \: c: x8 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: n$ o3 K) x7 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 K( @0 H3 I# W% Z+ XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) s& D3 H0 o& q6 o$ }0x00, 0xFF);: z8 ]9 ]" d2 s( k" N# W
& n2 @0 ^* J2 Y
/* Enable synchronization of RX and TX sections */ . P6 ~1 o# M' }& F( M$ u# K9 [5 J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ X- U' ^6 s2 D# m. a9 W0 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! ]6 W# @* \7 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ d: Q* U: R" M% P6 \0 |7 x. j** Set the serializers, Currently only one serializer is set as6 T3 H* v. l$ h( k# n# f
** transmitter and one serializer as receiver.
5 _& }( d# r' ~: k2 \( X% O*/
% i, V$ M- `0 A, I/ p' _- wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ b- e: p' v1 F5 f3 q& e& \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" a+ `! s. N9 R) j
** Configure the McASP pins
: J% }1 \/ g" D** Input - Frame Sync, Clock and Serializer Rx! f9 e t8 h5 \9 g
** Output - Serializer Tx is connected to the input of the codec 9 U% j( M0 m1 v5 X$ n
*/# ^' s+ d4 I4 n4 b8 H3 u+ Q, s+ ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 Y$ A7 J! `# z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ I1 S& p0 o8 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* Z( J" E r! P1 g
| MCASP_PIN_ACLKX
* D1 M' q1 v J5 ~5 V3 Q7 ?# e| MCASP_PIN_AHCLKX
! U0 h" i8 m$ U% Y5 k7 m0 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( d! T- ~' X8 q. {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : N. J/ [' v0 o. j' v& l) }9 N$ ?0 K& N
| MCASP_TX_CLKFAIL % B# m% r+ y7 `$ @6 X: K. h( q
| MCASP_TX_SYNCERROR9 V; C% O5 v1 g- [7 F: O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: _* c% \- w/ l; b- |1 G! X| MCASP_RX_CLKFAIL
7 ~% c8 y& D+ o3 n: i| MCASP_RX_SYNCERROR
! Q" X$ ?2 `2 w: w: N| MCASP_RX_OVERRUN);+ z- L3 t3 m! M! Q
} static void I2SDataTxRxActivate(void): E) i& E. s. z/ s; [+ u
{0 Y! W/ ~$ |1 B w* W2 M, J
/* Start the clocks */5 E: V) {' R6 h6 j3 w" [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, [& m/ e8 ?- p7 X/ ]% z5 ]- P8 V I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# ]4 {# I) t2 ^) v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* L7 ^7 }% K7 `/ R: \
EDMA3_TRIG_MODE_EVENT);
% H1 H- z, \ Y% N2 T2 j% r6 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, |6 E! T* p, F6 p0 P2 g( NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' x! M7 j- P; ?4 `2 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 {1 a' h; @6 v; D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- E* n/ [% q6 D$ `$ B$ {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- L7 X1 \8 D4 k: N9 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! }$ x5 c. z' d! u7 m1 S- c: Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 g5 v, L; Y: g1 g
} 3 M% {# a/ u+ q1 _2 V! T; m3 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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