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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ P, |5 M" O: r, finput mcasp_ahclkx,* u" I( M4 v' Y+ v. {( Q) t
input mcasp_aclkx,
5 z% H# l) j5 s( o' cinput axr0,
7 g7 n3 m1 F& f7 Q) _1 ]9 A
$ N2 m) i# ?! w) o; q: x' Ioutput mcasp_afsr,
8 z" n: s1 g9 @, z, x) g9 D2 Boutput mcasp_ahclkr,! r3 ?- l/ m/ V3 M$ @+ P3 F0 A( n1 W
output mcasp_aclkr,0 N* Y" F* s; `4 J1 n9 {
output axr1,
- t! P: ?! {& m7 s% t M* B" G assign mcasp_afsr = mcasp_afsx;. P- D8 \* }- n. Y
assign mcasp_aclkr = mcasp_aclkx;
$ S; h N8 ^' b' r- V. iassign mcasp_ahclkr = mcasp_ahclkx;) w: n, q% d% j
assign axr1 = axr0; : A" m* @: Q4 y6 H
) q. V0 @2 @0 Y8 w- v' O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . k3 ?0 C; m( h
static void McASPI2SConfigure(void)
2 u5 t1 Q. h8 w9 C5 f+ g{
* c/ e, j& d1 R) ~; }7 m oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 E' @" [0 p! T: U( o& f a& K x1 r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 P( W/ i/ `3 G1 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, ` b) b( s* N9 m& {) bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 w3 c& l% t/ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 w P! e- k' _, a2 k @MCASP_RX_MODE_DMA);
( ~9 `4 r8 z* j1 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, g+ ^( u2 V' q( g* s" x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 [7 {0 L$ l( F' ~+ u4 u% C1 f% R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 Y( C z* \6 F. O: _; wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% K$ u6 \* Q, c2 i1 R6 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ [" O- p% o7 t( R! V$ }9 mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' J! x' m# S0 c& m! t3 DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: L$ i0 p- a5 f! }9 D' G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: I }" T# @9 H5 \- _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( w; Z! X1 ]; c% y$ _0 G0 k
0x00, 0xFF); /* configure the clock for transmitter */
* {: a" ?9 x! d& m5 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( [" Z% j: ?+ i" `& \" |& VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' g3 I: q3 M- }+ g5 o& R" p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( e- `# ]- ~8 s* [% i+ A
0x00, 0xFF);
5 D0 l* n, d8 @ E5 x& A
( s# A7 Z) r7 a/* Enable synchronization of RX and TX sections */ 4 Y2 R# D3 s Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 r. j6 V# |6 s4 J& c0 L7 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
m. g0 u5 i/ m/ YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 a8 O0 A% v* s** Set the serializers, Currently only one serializer is set as" B. p5 s9 b& f" [" _/ V! {1 x
** transmitter and one serializer as receiver.7 z) r+ v. M0 t+ S5 ^6 K: q+ S
*/
: t0 |* K% X! gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, E, n- c: q. P) F, IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 z3 X$ O! S! L/ n* B9 g** Configure the McASP pins r" z7 C; t. C! j7 i
** Input - Frame Sync, Clock and Serializer Rx
6 h- o$ o$ c' l: l$ b8 q: v** Output - Serializer Tx is connected to the input of the codec
( r. }/ d( z- `+ C, }$ g/ F*/
3 R+ M: B) c$ e) q, y, OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& h7 S# ]7 z `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% p5 w2 h, X4 X q [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX q: C$ p& o3 x$ \5 Q4 z7 h
| MCASP_PIN_ACLKX$ G6 i4 r( g8 B8 K
| MCASP_PIN_AHCLKX
- W$ X- }! c" m. L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ T9 x7 Z8 [7 i% P1 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) h- _& Z% t; |- R) G9 L
| MCASP_TX_CLKFAIL
( D. ^1 z9 g$ f1 W' W2 j1 w) c| MCASP_TX_SYNCERROR
* s/ ~+ }6 l# {# M: S" T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 T7 A- s( a/ @* [1 s" L
| MCASP_RX_CLKFAIL
, m$ [ c+ L3 Z. [| MCASP_RX_SYNCERROR 5 G% e) _* t5 M9 A+ w* E" E4 Z
| MCASP_RX_OVERRUN);) [) x- z8 \: n- \$ v( K! f
} static void I2SDataTxRxActivate(void)
| @( @5 f! {( j: r{
5 G- Z' z3 X$ D" H6 B: g3 G' [+ S/* Start the clocks */. j( w3 X) @9 F+ ^& c7 M" x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 h1 g. S/ g7 j% {; J6 M+ T% X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 _3 j0 ?4 ]4 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% Q% r; e: L" W" |EDMA3_TRIG_MODE_EVENT);
3 o' N+ H- m9 A+ W2 h d2 O5 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' h8 o3 l- i; ?) V/ wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 R& u' D7 X4 v3 z8 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 j% B- ~5 @) Y0 E" q M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) P, `/ C1 Y4 N7 w( d! X/ ^7 f O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ b! Q" _3 r' @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; Q! I1 c, I4 k- M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ g% ^0 P2 M6 B7 v
}
9 y7 P4 F( Y7 b4 [8 s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 k" e8 S) w$ X; S5 M9 w( t
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