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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 U) m+ n. U4 }3 @; W: i. l: m
input mcasp_ahclkx,
6 m7 G! l( o3 f0 u c! p8 s* p5 L) Pinput mcasp_aclkx,
4 D9 R. Z6 Z/ T( M; l! winput axr0,
/ W" [, ]3 F7 C2 K: o5 |! a
4 v- L$ i( o" ?; @output mcasp_afsr,
- ~: R! l, ~$ n* h# [2 U o9 E9 houtput mcasp_ahclkr,
. E0 b( L+ O' K) @) I% r5 W# Qoutput mcasp_aclkr, L/ N6 ]2 E# N9 G, L
output axr1,2 a" g/ N: E8 \( _1 S W4 V" Y
assign mcasp_afsr = mcasp_afsx;
! \% a+ x- \4 |4 r. u* {( O" Gassign mcasp_aclkr = mcasp_aclkx;
. u0 O# a9 F2 ?/ ?assign mcasp_ahclkr = mcasp_ahclkx;
6 x! p+ X# H- \ G2 T4 C% qassign axr1 = axr0;
& `! H9 k- ], G. J' T+ } [& C5 W! Y( G+ L: v) K: i; C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! ~0 C& \$ Z: N- J4 Z
static void McASPI2SConfigure(void)
# E' q' {" {7 r7 }/ i* r( x{6 {- M* w2 L9 G3 Z( L0 z% l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 p4 F$ Y1 X/ A, g7 a0 ~- UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 M5 v7 B* W* G; [$ ~; \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) `! v B) n5 O: R4 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; k! C ?0 O, i$ O/ tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 _6 o# X: {( T1 AMCASP_RX_MODE_DMA);1 \6 z8 `- L! t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# b! z2 h7 q FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" i) U. I* Y5 v: \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 A- R: w, j7 H, b r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& E, Z6 x1 `: X3 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* F; F! Q7 `3 UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 Q/ \* r. f% _' X+ g {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
i" J4 B2 D, S+ cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * W$ W' x6 @/ Z0 t8 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 C2 r ?6 N6 P; j
0x00, 0xFF); /* configure the clock for transmitter */
) j2 e6 S- n# [5 p6 S8 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: ]6 P/ b! g/ r* v0 J& ^9 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ G G' X h8 e0 j6 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! d3 o+ J6 J6 W+ q# P% H, g
0x00, 0xFF);
' c( s) K/ H' c6 l: [+ T
- s" o9 ?5 z- p( A, m5 h1 |/* Enable synchronization of RX and TX sections */ - H# v: w" I% Q) F0 F+ V) f: j% _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
b# s, v4 O% D! T Y( bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& |4 P) ^; T9 J) u) }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! a" ]. F( F& _: F; `
** Set the serializers, Currently only one serializer is set as2 O& z) F1 m) u, f6 ]9 u
** transmitter and one serializer as receiver.
6 r6 @" W2 ~6 j*/
& \4 b8 n' s/ A! k6 [- q* KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 D% X1 g' g7 H. w& N7 p/ qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
u) R+ W* C- O1 }8 O** Configure the McASP pins 8 N) ]" J( N& t7 u2 b7 N+ _9 O
** Input - Frame Sync, Clock and Serializer Rx1 D4 w" u( K# r9 k& R: G
** Output - Serializer Tx is connected to the input of the codec * ?, u/ {# w; _; h
*/
7 Q8 T/ r+ X+ `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 z: _8 P) G7 h7 R! s: _7 `0 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' h9 k7 \9 p/ |2 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ D- Z* G& M+ _0 e2 \| MCASP_PIN_ACLKX
( _+ o0 O: ]+ l6 E+ Q! I* P% \| MCASP_PIN_AHCLKX& c) n4 p/ b) t# H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' D9 \# Z2 b9 S$ j$ E1 F* u+ bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- H7 X+ `2 a# _ e| MCASP_TX_CLKFAIL ?* v$ M; r, J
| MCASP_TX_SYNCERROR
; Y" O/ b/ @5 B3 k9 s/ Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, h) A0 \- o* h| MCASP_RX_CLKFAIL
" C. p. C9 X/ ^% M/ I. x# E) }| MCASP_RX_SYNCERROR . `# j2 P6 x2 D9 U
| MCASP_RX_OVERRUN);
8 A0 L; V+ S/ T+ R" ~1 T# `+ F. J} static void I2SDataTxRxActivate(void)
$ N: `+ W; U( H{
: X2 Q' O( e x4 p% j% Q1 F; w/* Start the clocks */
# u: X# | E5 G0 }4 V, {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 A; C C- F! G% C, e5 e" g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ \1 @" D$ o1 i: w0 }- j' Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% _" J1 s9 d% Z, d1 K# yEDMA3_TRIG_MODE_EVENT);$ n4 n l# D, a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: s# K7 z/ ?) |/ lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& ` y+ i+ ]! G# v% @8 N0 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 J3 W5 e8 R+ p& e) I1 K( G4 I( j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 A& s' t( c- [2 f7 lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! P# [# G# b% I9 h7 K. T/ p) Y5 ^ ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) o8 d6 i5 O8 Z- f4 k7 u7 m* y/ F6 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# e+ ]$ e, J* C2 u( Z; _
} 7 F0 `7 @6 |* w" ^0 B6 Q6 W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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