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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: P$ B9 e! ]& Q. |input mcasp_ahclkx,& |$ G2 g) l* J
input mcasp_aclkx,. e: A8 O' s: f5 X! {2 J+ b
input axr0,
/ m: F( M( s' I% m
& t" `! g; R }" V/ \+ P# Coutput mcasp_afsr,
- W' j9 d- y$ F0 g9 S G0 moutput mcasp_ahclkr,
. v" {7 x. @5 boutput mcasp_aclkr,
1 L5 F2 m- `1 ?6 _( Uoutput axr1,; Z9 z( p6 v6 t" S
assign mcasp_afsr = mcasp_afsx;
! T- r' r0 ]. z0 qassign mcasp_aclkr = mcasp_aclkx;& w# S" P2 K4 ?( G1 q. y! x( L
assign mcasp_ahclkr = mcasp_ahclkx;1 x, N6 I2 l0 c* a
assign axr1 = axr0; 5 R- {- `5 q3 |3 S, \1 e7 w- Y- }
7 [1 [5 n! v, C. ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 |2 S, ~) N, C F0 H/ V2 g1 q* `0 g
static void McASPI2SConfigure(void)" |! ]/ \7 ^; w, A! R
{
% d- b" {" E1 z2 N2 @! pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, n7 g5 o2 `9 g, c2 K$ q: ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ P; n0 a+ E5 O6 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 y$ i/ J% y7 h7 w+ @0 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' D6 ^- ~, ]& b1 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 H$ O7 J! y0 L9 E
MCASP_RX_MODE_DMA);1 |' P6 _; E; R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 a7 a& B" W# P. B- i" @" A, sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 B0 b" J/ I+ ~0 q' x" J# L* tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' E0 C: V: F# a. K8 U5 O5 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- l4 U' d6 k% q. g, a2 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' |9 w0 l4 ]% ^2 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ m$ W! u; E- E* P/ I: Y8 z- Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) h$ H& t) Y; S& H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ A- ]% \' `+ gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- {% T0 ^9 ~. E, v0x00, 0xFF); /* configure the clock for transmitter */& M% t+ b2 ?! Z2 X8 O' t1 f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
w9 {* z$ |( Y+ m8 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 s# q- _: R2 F2 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" B* u' x/ ?! H# w. c4 W0x00, 0xFF);
/ d& e) S7 h$ b5 ^
: N) \0 Z. w% N% z; X/* Enable synchronization of RX and TX sections */ # f& }! u8 S& g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" i" Q9 A9 S- K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 F, I% z5 H9 j1 X: T/ s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) |. L! x: F) a/ B0 G. a** Set the serializers, Currently only one serializer is set as0 `% t6 }, ]$ u, x
** transmitter and one serializer as receiver.4 G1 n/ u9 z8 X' V# v3 a, h6 }: H
*/
/ i: M" l3 |% c7 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 @( k) W p% C( mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) D% x8 P* A# g4 h4 L) \** Configure the McASP pins
' M; h9 X) l& M3 Z, d4 w** Input - Frame Sync, Clock and Serializer Rx0 p0 R" E0 N5 c' q8 y' ?7 s
** Output - Serializer Tx is connected to the input of the codec ( K T z [/ y) [$ z0 `
*/9 ]$ u% L- S {' b6 K f {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ U( q: \! B @; j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: m" O8 H6 r) y7 r! cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. Z7 V9 y* T8 {6 K, r: @* n: c2 {
| MCASP_PIN_ACLKX
- J' M( N) {5 k& l5 @( _; ^0 q| MCASP_PIN_AHCLKX
8 D* N4 M( z2 Z" I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 [6 E g, z O; U* |+ i9 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 {0 r3 }0 U1 `8 I) ]( i9 _
| MCASP_TX_CLKFAIL
: i8 g; ]6 N! x& @0 n| MCASP_TX_SYNCERROR( o7 y# n/ K6 b: V. o4 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ |5 f+ P6 U4 K9 U& @| MCASP_RX_CLKFAIL/ g1 t# I, j9 E7 ~
| MCASP_RX_SYNCERROR
1 _7 p- T* `% u" t( ]| MCASP_RX_OVERRUN);% `6 F' X5 I8 ~0 [$ A0 H( `4 @
} static void I2SDataTxRxActivate(void)' T4 z- L! L Z3 z# S
{& x3 U& P% t0 k& T7 k
/* Start the clocks */8 c% e% u7 v/ n2 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 v" @4 L1 _5 Z* c8 w/ N6 }! CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ ?: t9 a0 f* }" U( x$ y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& l: w1 U0 S0 q: H+ \
EDMA3_TRIG_MODE_EVENT);
' C( f% P% ~0 E6 M/ vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - l- g8 A3 w/ R! ~9 p, `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# O* y* _. ?7 _3 G9 L; K/ ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 [' U4 {+ _+ Z' X0 r! gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ N# v9 t+ B, H; V6 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' \) j) v# B% G) r* f1 G! Z5 H' SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! ^0 }/ `4 @8 y4 O! U3 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 }. _- t3 p S. m
} 1 ?1 O) q* H: H9 r [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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