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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) X( D* y3 X5 V2 Binput mcasp_ahclkx,, D. o* r1 A+ j1 q+ c
input mcasp_aclkx,! O3 h/ j$ _* U: }
input axr0,7 K5 H% ]1 [! c6 C& l" R5 c4 {$ \
- \9 ]- Y1 j; q! T7 youtput mcasp_afsr,7 I) W- s0 Z1 u! q+ C0 v" C# F% G+ f
output mcasp_ahclkr,7 k9 H& V' U& b
output mcasp_aclkr,# Y; I4 X$ t% _: U8 n; r' c& d
output axr1,
7 w, Z: y$ ]# m/ U( \) I0 I; ~ assign mcasp_afsr = mcasp_afsx;
* `" k, Z7 d9 tassign mcasp_aclkr = mcasp_aclkx;
3 _1 `! Z5 \( i; Y4 Kassign mcasp_ahclkr = mcasp_ahclkx;; v p& e7 r& s; \$ W. A5 O
assign axr1 = axr0;
* z# {& \1 a5 c- r0 V7 n. P d
9 Y# e8 B, H9 P' K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- S# N/ k" g/ Q1 j7 ]7 x R9 Ystatic void McASPI2SConfigure(void)3 Y5 |8 [$ ?- k1 y0 ?0 h
{
9 x" L; m% A! ^4 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ K, @+ v$ {6 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, M4 Z% n4 N# I0 {6 S5 j4 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); q3 S$ J0 E, Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 f3 [# Q2 `$ i' Z% T, x0 ?5 R$ n0 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 T. N6 B& y% L9 i; P( O: _
MCASP_RX_MODE_DMA);7 d7 P% v+ j' M) `$ f7 e2 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% D5 e" @9 }; P; e7 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 c2 a6 G) H9 [/ }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ @' \9 Z9 ^& A. PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 y; Y/ M# X1 R/ S$ ?' `# U0 X& ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , T. l% h( V, J. B+ v: V( b1 Y# m0 E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ l3 x- V* c! K; Q% b) e) L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& e& `; T2 S5 b: f3 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* ^0 d" m+ u4 S% MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: B! M8 |$ K& n7 ?6 B, V p
0x00, 0xFF); /* configure the clock for transmitter */9 z* V9 N/ D& f- q- n# I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 @- l8 @$ w' @: t2 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 L1 W& Z5 O4 p$ K, T9 ?& @1 q1 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: L% }0 [5 U' D0x00, 0xFF);! e6 ~( [# d+ ~/ l3 P( d
3 {7 Z5 d$ q; O2 g/* Enable synchronization of RX and TX sections */ 4 [% Y1 ^& I, n; `, Y2 T; i: F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ P+ n5 {2 u: Q' lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& ^7 ]5 y O8 C, R; [5 C9 o7 B: Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! k6 g0 J8 W( J3 D** Set the serializers, Currently only one serializer is set as
+ F. o/ r( s# K3 N** transmitter and one serializer as receiver.& _1 B; a$ F- M* b& B4 G" _
*/
4 z/ t, O2 u4 F! ~2 R4 G% kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); _0 D' Z5 v, o6 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 y6 |- Y5 I7 |: H( X** Configure the McASP pins & i3 F" q2 L9 c0 ?( {
** Input - Frame Sync, Clock and Serializer Rx) a& q3 ], S0 B/ s- y
** Output - Serializer Tx is connected to the input of the codec
; L+ j+ O: O6 U0 n# l a$ @" S*/
: J; W7 u/ d2 Z# y, P" xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# x3 W+ {9 s: P7 K! l( J+ d) Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 B- |; Y2 s2 T, I+ aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 [) s5 D' c# d$ i
| MCASP_PIN_ACLKX
$ r6 J" R" y2 o, a6 ^| MCASP_PIN_AHCLKX
6 D4 ]1 t. v$ t6 ?& h, s" a8 S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 |2 X: G5 T) MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 ?9 R6 R6 ^+ K$ h! v
| MCASP_TX_CLKFAIL
5 r3 k/ i% f4 x. `| MCASP_TX_SYNCERROR
7 o0 H1 G. _! t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 \6 p: \! q+ O v9 D| MCASP_RX_CLKFAIL6 ~/ l3 k; F6 E- u' f/ S) ?' S7 w% B
| MCASP_RX_SYNCERROR 3 \/ f4 i8 y& h# ~3 \* R: e7 E4 h
| MCASP_RX_OVERRUN);( W) D: [$ U' r( i
} static void I2SDataTxRxActivate(void)
+ l2 D1 Z* L# H5 L* m{
5 M1 n7 S, V7 A5 j! _* p5 s/* Start the clocks */
, j4 B6 Z! J, M4 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# c7 j, _+ `: i6 ]8 w9 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; K0 E) I5 q: Y) W- T0 ?+ U) {3 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- g5 R" z. P/ ~2 h
EDMA3_TRIG_MODE_EVENT);# h- f1 \9 _$ T: W8 ~/ ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - u* f3 D9 d( g1 p) r) |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 s- @! \& i; A2 V' G& `& q* _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 A5 ]4 U! w0 IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 u1 O/ @, V, j( u! v3 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 o+ ~2 q3 h' k: c0 Q4 ~- j$ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- j2 O- |# h. q! h3 |& W E3 J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 l2 l' ]9 \* F4 c* S: K' }} N9 k! m1 _# b2 U4 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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