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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 \1 S* V% E4 @& }$ c& Q
input mcasp_ahclkx,
7 m8 `5 |7 c: S5 E- _input mcasp_aclkx, z4 H6 B9 ~ N. s. e
input axr0,
. }2 W& t, {2 v! q5 D
, n, A2 l1 }5 T) O5 w9 {output mcasp_afsr,; q, }0 g+ K2 K9 {: p
output mcasp_ahclkr,# w8 r3 C; G( {9 _% \0 a
output mcasp_aclkr,
+ V7 @$ x4 D0 b$ R' ooutput axr1,
8 N6 ^9 b' {2 b. K! V# N assign mcasp_afsr = mcasp_afsx;
) F+ ]; r1 H' Z( T; A7 c$ Jassign mcasp_aclkr = mcasp_aclkx;
* r5 {8 b3 ~) R1 |assign mcasp_ahclkr = mcasp_ahclkx;
( B: d( f+ X/ Q$ d7 J6 C) @' j4 L8 eassign axr1 = axr0; $ C A1 c! q+ K3 I4 @: V+ w# h
) G8 _6 c9 h$ }" i1 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 N/ j" G0 p( }( x& e5 r
static void McASPI2SConfigure(void)
7 I8 ~" \- U. ^( s{
1 S5 K# {9 B' BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 S; O* m# N: h) ^% [ d/ L7 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& \3 F/ K# T6 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& x) h/ e5 g' ^) ~6 \9 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& B8 Z( i5 E2 H2 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# T/ P6 U4 ~: `6 q7 ^- QMCASP_RX_MODE_DMA);
/ w& x1 L, x( T6 }) JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 e: c* a0 v+ p" e* i# mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: c! I- b5 t ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; ]* I8 a2 D% g* t3 y& |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ B0 K2 u. Q6 ^6 R+ g- L6 z3 e/ {; }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% N! R; C2 Z1 I2 a6 f: u kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 {4 Q R# L9 U7 x' VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
P) d9 L1 ~2 d& ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & O; K6 t# ^, D. | ?* H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* a2 K6 `* C4 k: v9 @9 H
0x00, 0xFF); /* configure the clock for transmitter */
V' Z* B# k. T& ]0 Y+ xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 w, V7 b' I; `% w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & u) h9 O5 U1 P% \7 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( C$ S: l. K9 u/ o7 w0x00, 0xFF);% ~9 A, L, C3 Y0 z4 f
. K6 T# Y i$ @
/* Enable synchronization of RX and TX sections */
+ R( {( Q+ ^9 R, _) bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: l# a# {/ Y r- W, A, {8 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 S Y" g# D; R* S5 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 m X0 P3 H7 F9 m8 ` i+ U& D** Set the serializers, Currently only one serializer is set as
8 z) ?: B& S& C ~** transmitter and one serializer as receiver.6 e! M: Z7 q" x( p( H- z+ o& X! x* S0 n
*/+ q0 U6 E0 E' z _2 H. F0 x( x; M; C. E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& C( {7 K5 |0 b5 h3 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% s) ?8 u! n% G N1 \** Configure the McASP pins
% }4 k6 G @& G2 N2 x6 Y# O** Input - Frame Sync, Clock and Serializer Rx
+ g) Z( O& R' k+ L** Output - Serializer Tx is connected to the input of the codec 3 [3 E9 \: k( F; T% x$ a
*/
1 ] k$ V/ L5 v- qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 ^( H& J3 ` t; [& p5 R- pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& S2 j$ s1 v% [8 l5 X6 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 @9 {* M' ]3 k, @" h
| MCASP_PIN_ACLKX
! e v/ Z9 l% p9 p5 v( P: R| MCASP_PIN_AHCLKX& }0 y3 S/ L# B% j, o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; b% q/ v+ }3 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - e/ b! o+ O, e; C3 p
| MCASP_TX_CLKFAIL
9 H' }& N1 Q! g3 I6 K: n6 m| MCASP_TX_SYNCERROR
* I1 X8 a u2 ^0 N9 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. k5 U" _: H6 i3 s| MCASP_RX_CLKFAIL
0 k4 D/ Z6 P9 {| MCASP_RX_SYNCERROR ( L' E9 @% N' O) r! P
| MCASP_RX_OVERRUN);0 v8 @% j8 Q! u0 I) Y5 J
} static void I2SDataTxRxActivate(void)
$ E! ^1 [$ m w3 |9 t- ^{
! l' M9 T" t" ~2 R1 d. b; G j/* Start the clocks */
9 x7 f6 C2 @3 [9 M: z; ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) S! J- n% V" Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" M8 D& i! s5 j) Z5 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 R! }" S6 N) V5 d8 z2 Z8 iEDMA3_TRIG_MODE_EVENT);
& h$ Y) W( k3 _6 i" E, O; c" j/ VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ y- w! Q! C. u/ t/ KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 ~8 r, K6 y* B1 W$ ], h8 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 X9 v( `# v0 X' p" u7 ~$ k, jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) U& z' q$ s' r9 P' F v4 Y' gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# v+ V% L+ `9 M0 ]. E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: V6 c% Q' s8 xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 P! T" \! z# E: j; n6 s7 r; B+ l% m
} , u0 i4 k0 x* G4 J3 R! e2 r3 p! H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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