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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ k3 W/ g% N" a# ^; i
input mcasp_ahclkx,
6 v, L4 C9 i5 R' t! s& Tinput mcasp_aclkx,
# e2 |: {8 i b/ X' S8 uinput axr0,
1 H& P7 |1 c5 a0 Y$ p+ Z
8 R9 {' V! ]" |output mcasp_afsr,% k# {& M9 [ r0 w2 h
output mcasp_ahclkr,4 J) I9 K* q9 Z* Z Y8 ]" {8 n
output mcasp_aclkr," l% e& d" w% ?4 n1 Q# w
output axr1,. z+ w7 c0 p0 C7 O1 x. T
assign mcasp_afsr = mcasp_afsx;
, X( O0 {. M# S) M7 u$ u; i- lassign mcasp_aclkr = mcasp_aclkx;
: F0 u1 e7 E3 @: ?( x( xassign mcasp_ahclkr = mcasp_ahclkx;9 o! p! `( S" E7 g
assign axr1 = axr0; 1 Z' F" s+ O8 {; B1 [: E+ Q7 m
0 v! \% O; ^3 I% M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 t4 ` N9 U9 K8 I3 g9 }5 G
static void McASPI2SConfigure(void)
* Y' b+ h9 R* P$ ^- t1 p) n{
) c8 C9 V; x+ K k3 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) K8 s" m3 l/ T; l" Q0 O6 a! aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- D* R6 ?" H* b% I ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" ~- y; y/ @) w* d' `+ W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
u1 s# |8 F: f' |+ b( \9 z9 G* m5 W9 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, t8 ^+ ^% L: ^+ `
MCASP_RX_MODE_DMA);4 n5 {" ?+ E, q- K# N; V' E7 q( ^# h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 _* X& {" ?! M/ ` t. l$ A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 [. |2 M, @6 H* T4 x3 D) T* p/ ?( ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 o& o4 |1 ^2 {/ k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 S" T4 M! ?, I4 I3 \# _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( ~4 l) X1 y7 T( C/ Z4 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 L( S" J x9 _# b: K6 a1 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# l" S, b& [0 U- ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' ^+ ^# ]4 ]. s6 h- D) }+ j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% U: A; n0 s& r- C! u a
0x00, 0xFF); /* configure the clock for transmitter */
) L8 F% y+ N [) y8 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 d: I3 i2 y3 E3 _; B0 `4 uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" {1 k, u1 Z8 v7 H5 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- ~; |; H1 ~7 d; P/ A3 m+ G
0x00, 0xFF);
2 G: ~: m1 Q4 e) h: W6 P7 r" ] @, F- ]
/* Enable synchronization of RX and TX sections */
+ H' w5 i& |7 o( H G) ?# xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# K( l/ `/ f$ A3 T1 V: zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 `! I: m7 h- e2 |- Z* \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) Q7 }; n) a- A+ Z" p
** Set the serializers, Currently only one serializer is set as
8 B" I& x* n$ F3 T** transmitter and one serializer as receiver.
v7 Z" l6 u% Z# L" E*/
L* L# g. }: S7 s: s, ^( JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ N) [+ S/ k, Q+ ^% e0 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! u8 u- ~4 I' b+ H# B* I; O** Configure the McASP pins
( B7 |- S7 J8 b$ v s# d6 e** Input - Frame Sync, Clock and Serializer Rx3 A5 A: J$ s* R% X6 E
** Output - Serializer Tx is connected to the input of the codec
6 p) [; t6 ~5 J, p) {# f8 v*/
- F( q8 y4 T6 W5 z9 _: G- oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, c0 s, U: s$ F, pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 ?; K: l- }- B4 L4 x* P+ T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 w' G: t# [/ t# }5 E8 F. _7 k| MCASP_PIN_ACLKX9 D% z* D) x! Z$ B
| MCASP_PIN_AHCLKX
; l: @! l P% {2 I5 g$ K7 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- ^1 Z/ ]: z3 V. e7 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR a0 V; ^3 k( Y+ b/ k9 P' U5 a# C
| MCASP_TX_CLKFAIL [; p2 h6 e X7 J- g, j
| MCASP_TX_SYNCERROR
9 n6 |/ Q6 w$ v/ a1 U7 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 G7 x8 U5 n. N" A* z- K. ?# S
| MCASP_RX_CLKFAIL
6 S( X* z8 z: U: c| MCASP_RX_SYNCERROR
" t5 a, Z0 H- l7 [7 ]| MCASP_RX_OVERRUN);
\1 |$ s, ^ D} static void I2SDataTxRxActivate(void)
$ i& t/ S6 K5 a$ m4 m{
/ T: @" [3 F9 T6 g2 {; H- U/* Start the clocks */+ J; ?$ M/ X E' i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 J6 V, @) n |8 C/ O# j0 _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ U7 W" r" s3 |1 ~$ M9 K R7 G6 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ O5 E$ w; l1 K" S% Y: CEDMA3_TRIG_MODE_EVENT);
. |' a F6 S n: l/ W0 T: QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 w6 B; G3 p/ x: ]* k! ~" @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ O, T4 w3 e% L) W: g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 D. c% Z7 d+ z6 E+ A1 a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ K% l6 W& X& }8 h9 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ h4 R/ ?7 F7 a7 ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 F' M' ~4 O' z6 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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