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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 S5 M# w( o" h. G0 e- L) C' Q5 U( i
input mcasp_ahclkx,
$ o! [+ k. p; i# @/ _' sinput mcasp_aclkx,
7 l) c$ ^3 X: M# J# y- r- H! {5 {input axr0,! c! L$ d: ?; C: Z9 w
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output mcasp_afsr,; L/ q0 Y" L* j* K) y; y
output mcasp_ahclkr,5 w# Z% L2 n5 i' g
output mcasp_aclkr,! O9 V$ t# D9 `# P
output axr1,
; L/ r U% u' N; | assign mcasp_afsr = mcasp_afsx;% {( p0 O" r* Q; P' Z8 e3 B# ^* ?
assign mcasp_aclkr = mcasp_aclkx;
! K! ]* d1 |6 I4 xassign mcasp_ahclkr = mcasp_ahclkx;
$ B# Q) a g$ Sassign axr1 = axr0;
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6 }0 S+ L$ X$ A3 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, E5 t7 {2 g4 g4 p, Tstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Q& z$ }5 a+ IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ]1 A& I& c1 |, }/ d* q2 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, J, N" H% z6 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
i4 h j* D% @! HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ ?4 i( _ ~8 b! |6 \MCASP_RX_MODE_DMA);
# f S) p1 X- C; u; C- @# [# LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 e7 f( ~8 {. `+ y AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( K) X$ c" l1 N: s( p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " Q* R* @* i( O. V& s5 U1 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: l" V& D6 G! Q- g8 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 A1 j7 |8 `' P; H5 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 l% r( z2 E9 A, @5 K9 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
V* c1 L" a5 U4 _! }- h" fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; b$ `! `" l% Y7 h. E3 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& d1 c4 m% K t1 O4 Q) G$ ]0x00, 0xFF); /* configure the clock for transmitter */
g) P5 H3 _. a0 w8 X0 d/ ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 ~# q% Q7 T6 R: w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 ]6 s7 b/ q$ n* J) N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 ~* N9 f* `3 c9 W' }0x00, 0xFF);
0 B6 y; i" b' d- e+ o$ d$ U
1 g1 h/ k% {! r' K/* Enable synchronization of RX and TX sections */ + G1 ~. E; t( I) L: T& y& M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. _4 g# v- y5 E, s; lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! S/ w' Z5 a+ D& Z! LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 L/ g3 z5 V1 X- ]** Set the serializers, Currently only one serializer is set as
# r6 v2 D# H9 i6 o9 R' A1 U5 G( E** transmitter and one serializer as receiver.
+ e( w. D. [' f. P; X: Z" L; k- h*/8 A" x/ p2 C# Q( C0 D, o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 G+ U: X$ B8 m4 d/ m& x+ V3 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
M$ W% z2 w, j, J; F3 Y** Configure the McASP pins
( C6 U' R1 p6 c+ t** Input - Frame Sync, Clock and Serializer Rx
& o1 P; ^1 c" X** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- c8 M6 U) E2 d7 H. V) U) yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( m$ X7 ~- X# R3 H: G, c; I i8 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX Y" O1 E) g' q% D- `8 X& u% `9 f
| MCASP_PIN_ACLKX
. p( l! m2 b: x1 R| MCASP_PIN_AHCLKX
. B8 k) o) T4 m- W+ F j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
h% s: o* f0 k0 {4 `, @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: g. J) V8 p& M& f| MCASP_TX_CLKFAIL
$ Z$ b' @1 `- X- L# ^| MCASP_TX_SYNCERROR6 b" K) k4 o y9 I. D6 Z) c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " j. E% i2 h9 R u: o# B$ L
| MCASP_RX_CLKFAIL
# T: k% V: B; ^; o J. T2 E| MCASP_RX_SYNCERROR . |" f, \. F/ G* j6 u
| MCASP_RX_OVERRUN);) W8 _4 J3 H, ~
} static void I2SDataTxRxActivate(void)9 _3 H; E) W+ X! f6 ?1 r
{0 {2 a8 U( N4 \) m9 Z0 q$ _0 w
/* Start the clocks */9 R! G3 P: t% ]! w) W0 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; d m! N' B9 BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( ~0 E; o7 k h4 i6 @, cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& k% o0 C: U* J9 oEDMA3_TRIG_MODE_EVENT);! u- n' o2 n; b9 S6 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 c8 g# x; r& p2 |# S- ]0 m# fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( k$ ~ Z t) b, }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 c' F) R& u9 D0 I( k1 T& [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# I) H) q3 \9 O* C+ t0 {6 Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% X! D& d1 ?) ` d- q2 \6 V6 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. ]/ M6 ~# q9 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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