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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 A$ x2 R2 a. @) O4 q& dinput mcasp_ahclkx,& T, H8 G6 b1 f7 F
input mcasp_aclkx,0 l1 ]% l5 p* I
input axr0,; [4 j: H: Y; L9 m. \
6 ^1 L. R; L8 y2 {output mcasp_afsr,, L$ M3 z9 u& I& A+ u' o
output mcasp_ahclkr,2 k" D3 U5 i8 V3 c. X$ S/ r
output mcasp_aclkr, W* L/ A Q$ k+ g' [, K2 U
output axr1,
( _" S2 K, ?3 p3 t8 X1 `& m# l q) R4 L3 s assign mcasp_afsr = mcasp_afsx;
5 q. ]# _3 H3 ?( a3 fassign mcasp_aclkr = mcasp_aclkx;+ I* g' L9 i0 i: j0 g5 A: K" n8 j+ D
assign mcasp_ahclkr = mcasp_ahclkx;8 e' Y e9 v) x C5 p: T
assign axr1 = axr0; % e5 u( p, y2 [
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 k# O& o, d9 |9 w- Q" _$ s
static void McASPI2SConfigure(void)! ]9 l- [, \1 l2 W" E- d3 R
{. {& c$ T$ T" ]1 q6 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; h: R& j8 ~% t# R% GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 g/ D$ E' i7 w7 u3 |; [# JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ h5 x% ?3 N4 w) bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 L/ D" [, D# G2 Y7 S' AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," M4 ~4 x: B5 ~& H
MCASP_RX_MODE_DMA);
' @! y, p) @, S7 }+ Y/ V$ M+ oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( E7 J# m3 \% X% A6 d3 j: a# J3 mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
u1 ]: I; L& [: MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, \4 p+ y$ k& c2 ^) _2 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 X0 t) g! c% {0 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- ]5 S4 Z# Q8 b/ d& JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! t4 F9 |# [% a" s; U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& a! u( _4 n7 S# U$ TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - ^+ T% F v* d) c& L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, G7 ?$ U( }3 l0 T4 B0x00, 0xFF); /* configure the clock for transmitter */
, e+ c4 ?1 V6 B3 f+ z' U+ @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. Y. x- y, ?; }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 H: f2 E1 G/ \# E4 f& ]3 UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" G" Q. c" U/ ~1 ~# {# g9 ]0x00, 0xFF);
9 ]. _- J- r# [3 P1 o8 A
- @% i$ Q2 ?; E0 z/* Enable synchronization of RX and TX sections */ 4 g+ M% ?4 l- r0 K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ c" V0 v) A. a9 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: }+ T& O h+ c5 T7 m HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 ^: g, u2 }: u0 b1 A** Set the serializers, Currently only one serializer is set as( j7 J0 ]6 W n- O( |
** transmitter and one serializer as receiver.( N1 m4 }. ^( d
*/
1 o* p6 [! n: I# I8 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' |: M# r3 @0 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, E; u* \% q. x: v# r* L
** Configure the McASP pins ' A% m9 p% v% a& z
** Input - Frame Sync, Clock and Serializer Rx
" V A) ~5 L2 @2 ^6 l** Output - Serializer Tx is connected to the input of the codec ! c( m/ R5 A' o4 Q0 v$ d
*/
, [: H% q& `3 y4 F! UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ `* }: X/ _7 |+ q: Z4 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 V" a8 ]1 u. W: c# Q9 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! n0 ^- h' d5 T2 j, i: b| MCASP_PIN_ACLKX5 V" K- t5 ?9 S& U8 Q7 }
| MCASP_PIN_AHCLKX' z# |2 D v+ o* p- Z: l; ~( `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 u7 p p2 f g! ]: R$ d. f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! H$ U6 q4 K% s' ?
| MCASP_TX_CLKFAIL b8 S" N: _( s0 B3 v
| MCASP_TX_SYNCERROR
" l7 ~+ h0 ^$ E0 n( E) k' V" }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 C' D& T0 i, s8 v| MCASP_RX_CLKFAIL
( S8 Z J. a2 n ]5 k, A+ c" T, _| MCASP_RX_SYNCERROR
8 L5 k% o, G+ E2 |: u| MCASP_RX_OVERRUN);" f4 N4 Q# X- s
} static void I2SDataTxRxActivate(void)
3 }9 ], Z7 [0 f, {* \' O2 m$ \! P4 i{
3 ?& i( a) j* R/* Start the clocks */
7 O5 R/ g+ O+ l8 OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) D4 o$ V' y% }$ l5 h' i* q2 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 e- B0 h O1 A$ F$ H& ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 m$ u6 L6 A6 ~7 t! f0 c$ nEDMA3_TRIG_MODE_EVENT);
8 a% t# P$ o9 c6 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + h4 D4 H0 }2 Y+ b h& G6 T* Z8 t$ z4 \/ K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" d! t9 u: E8 ^8 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 h4 K' L- r3 h1 ^. g; ^& |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 t+ Y; T3 @, \ w3 A9 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" e d7 \# S5 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 M* L& `) c! CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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