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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. D' S4 \- H& s. D- Kinput mcasp_ahclkx,
3 j' E/ a; M0 }- ]* Ainput mcasp_aclkx, I% c5 e) v4 G
input axr0,% X5 U3 `- D& g T+ z0 I* B& z
/ p# I! r& H- k* L- [: h9 Y$ Q7 x1 Aoutput mcasp_afsr,4 Q7 ?7 N" j3 t
output mcasp_ahclkr,1 Q, I/ z% _5 T
output mcasp_aclkr,% Q" _7 g$ H1 r/ M; K
output axr1,
) e. ^, z7 u/ X1 {1 k( I1 v assign mcasp_afsr = mcasp_afsx;! A9 [6 }0 R/ ~" x+ x) r
assign mcasp_aclkr = mcasp_aclkx;8 z6 _1 y/ L. b: L
assign mcasp_ahclkr = mcasp_ahclkx;# z' p( m: @4 U: X4 L1 t
assign axr1 = axr0;
% c" p; M2 Q( D' v* |
! q9 i) `8 C( @( w1 B8 y( o- m+ i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ P; q8 u, ?8 l6 e0 A5 istatic void McASPI2SConfigure(void)
/ J' e7 v' H* k+ l9 ?{1 _; F. y6 U7 |* u. \5 t/ E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* i g4 x3 ~; g# gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 h$ G' a2 z4 a+ \0 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, S$ w' M! ^) B: `, k3 P! N" \7 Q% ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) ^) u; W/ F- ~4 x& r6 z3 f. dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, C: R- S9 C8 ^$ D
MCASP_RX_MODE_DMA);- W, T9 j1 `" a, F- w8 v( W/ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: K9 ?! X8 g9 i* h' z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 s5 R: y1 W# u$ o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 W' m+ \2 D+ ]5 ?) d3 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! y0 W1 h3 }9 I% [& z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" e" [9 u2 r( t4 X/ f- uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 W$ p: M+ s0 j) k6 Q" F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ x' v$ e$ v* z" x. e/ I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; w2 K f5 _ ?! SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% {, p6 @, q, S5 |0x00, 0xFF); /* configure the clock for transmitter */- Q9 M4 `& O( T( G# A/ Q2 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) B/ Q$ `. A8 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* L1 f+ t4 b- T; H) hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 x# i1 W! ~, \4 V! z+ j- b% n
0x00, 0xFF);* o+ P9 A$ H e: X# x6 V
# o u; R( x5 P% ]/* Enable synchronization of RX and TX sections */ 0 U7 X3 V) s0 E0 ~& o; e/ F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ L& }% ?3 z8 x b& G1 B, L( K; u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 H6 u8 T" _; m ^+ E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. h6 n7 O8 W7 t6 ?6 O: w8 Y
** Set the serializers, Currently only one serializer is set as
" O4 k- n, ^# D Q$ ~! G' P. p** transmitter and one serializer as receiver.* r) j; Y1 c1 v4 z1 |
*/- u8 R2 V7 Y% R" b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- X/ `2 M( `' k, V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" F1 D: Z* U" P: y
** Configure the McASP pins / q& U8 V R, \( L6 r1 @. h
** Input - Frame Sync, Clock and Serializer Rx
, e" e' w6 a8 b- z** Output - Serializer Tx is connected to the input of the codec ; _ Q, L9 S. `( a- |! L2 j
*/% B! e* u! I7 V' s% |) |2 N# e7 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 S4 g. |, M2 N: r5 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 o" o# F: A1 {$ O1 M4 n/ v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 v' U+ R) i1 W| MCASP_PIN_ACLKX
4 M; L& U# L& w% q Y$ E| MCASP_PIN_AHCLKX
W) @& G, S( E. C& Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& u- U) z% j( {( gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % j1 |5 d4 e' r4 c
| MCASP_TX_CLKFAIL ' M/ }& D8 q% g
| MCASP_TX_SYNCERROR( T2 L8 e5 o: d+ P! j7 Y! j$ Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR k/ m, N, N7 Q; E1 t
| MCASP_RX_CLKFAIL
% i' @' A" @& t \* N3 {0 J| MCASP_RX_SYNCERROR
6 E4 P& Y3 y! ?| MCASP_RX_OVERRUN);! H" Z' L) v% W% T
} static void I2SDataTxRxActivate(void)& q/ T# ]% m: n2 d8 M; K1 Q
{; d1 A6 K3 x, E9 c4 ?2 a
/* Start the clocks */$ y, V& O5 i, S& r7 v% Q3 e' u; H G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 ~( t$ ]& l$ y6 \. L: Y& KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) b$ N- p" s2 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ O( o8 Q: J9 J7 r0 Y6 ~6 XEDMA3_TRIG_MODE_EVENT);
# E2 L" E: A8 e8 j4 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; @/ ?& h \ s/ D) G# V" kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 A+ x6 S7 A3 h6 t2 c0 _6 z1 oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' [& h7 G* Z1 k' _( e% X: i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# a& }/ x [. z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 R1 D( V1 l2 n% N) k4 Y* y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ q4 v" [' q$ F% H) K5 g2 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" H7 j+ T, {6 q4 M ^( m8 ~6 v4 _} - z# a- y9 i. Y u. ?' G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! M. s, z, K0 B) E
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