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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 |( d+ t# M0 b0 X5 J( z; ?, }
input mcasp_ahclkx,1 c' l2 H( O* U$ n7 ?8 R1 k) l8 c
input mcasp_aclkx,
" z1 X% z; b( d7 m# n: [! ]# Uinput axr0,0 P( x. U+ v) y( T2 S0 `' n
- ^0 ?, ?2 t: n" Q
output mcasp_afsr,* S% W* v& N6 ], H3 \% u. j% J
output mcasp_ahclkr,( q+ z3 t, h" y6 j5 R* o
output mcasp_aclkr,! Q% K. m5 s: U2 n
output axr1,
# d- f0 p# U/ z5 D7 O assign mcasp_afsr = mcasp_afsx;
4 U+ y5 t% l; L( r* d# oassign mcasp_aclkr = mcasp_aclkx;
) _( R3 D2 q+ r; f% [: b+ fassign mcasp_ahclkr = mcasp_ahclkx;
5 a$ H5 B/ u: Y8 ^& lassign axr1 = axr0; 4 [5 Q" v/ Z" ?; G
4 K" E u* y" o6 q" ~: C- i3 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 W$ D. ]: E) V6 a" I5 N& b( istatic void McASPI2SConfigure(void)
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1 P4 c; C e2 ^3 I2 R0 C D4 G* yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 n! _( ^6 m4 q" E% \. _5 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. j5 ~) A; ?9 h6 m! T- L' m) U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; u, G& }: r: f/ d9 |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 }# s2 h9 J7 b3 l j) V& O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ]3 D) n7 y9 n* K
MCASP_RX_MODE_DMA);# N# Q8 U% X1 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% m5 D1 S! G* P7 a+ D# p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 J1 g1 o' C: l, e# Z, n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & i- F' U4 D' ]% |# r7 f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, \- r* _ g+ t6 H& f1 l( [, B( I7 {/ u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % w5 @- d+ M3 ?# Z: Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 T! A4 K5 z) T7 S3 ]% h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. B% p( ]6 a/ r, o% X# c1 G z. ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 y( `9 r, d( w# r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% m9 w# j8 c, Y( j0 `: @# L$ y+ k0x00, 0xFF); /* configure the clock for transmitter */8 l3 l8 }8 ]1 e' D4 c' S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 @4 t- K+ s- ^5 U2 U/ e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: [/ ]- x8 Y0 ~! u( E) q% M) @9 WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 T/ q( `" f7 I% x9 Z& B0x00, 0xFF);
. c* g$ \' v# N9 S6 t; X/ z: x
5 ~+ U# L* o! Z1 g. y/* Enable synchronization of RX and TX sections */ / p& n% [3 t1 c( }& Z1 E. g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; k# F" g1 g# ~5 S) PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# }% k- F8 H/ o: V, E& |0 oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. ? S/ R! N* e3 g2 T
** Set the serializers, Currently only one serializer is set as
4 |% B: K' M$ c6 D! i/ a% _" j& p8 C** transmitter and one serializer as receiver.2 [; ]5 G& l: _$ U9 g
*/
5 r2 n7 R2 `% q$ N; lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: O$ n8 d6 ~6 LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( e3 F8 I3 p6 s
** Configure the McASP pins 3 f& k7 d+ t* _1 J' a a7 t
** Input - Frame Sync, Clock and Serializer Rx) ?" E1 a0 |2 M" ?' I3 P- Z
** Output - Serializer Tx is connected to the input of the codec
' e6 Y) X: \4 j*/
V0 W0 f% }3 ` R: C( VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% K8 K/ K1 D' i6 [0 H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" Q( F! E4 B m& C* ^; Z5 Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! g0 q* m3 m* q+ E; e, I; \
| MCASP_PIN_ACLKX; t: K- ]# T: R: |6 Q# B
| MCASP_PIN_AHCLKX
! q) E8 P0 d9 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 t) h# d8 G$ m, Y+ ^' n+ ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# B+ d4 L) T8 b- P q. @) A| MCASP_TX_CLKFAIL
8 R: M, q5 }; @9 z) c| MCASP_TX_SYNCERROR9 b$ X2 G; U! l6 q4 w3 R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % R; n6 M- j) C' Y! N4 C9 e
| MCASP_RX_CLKFAIL$ k& |/ ~0 s, {/ A& H, g6 ~8 _
| MCASP_RX_SYNCERROR & V9 Q a7 D6 A8 z, M, S4 a( H
| MCASP_RX_OVERRUN);! x: D, Q& ~" n
} static void I2SDataTxRxActivate(void)
* z6 u5 h @. v+ U{
% r$ `8 t' @) _4 k/ {$ r. |( q/* Start the clocks */' v, C! z/ r8 R$ G( A' H3 `/ P" O5 g* C) F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 b' X/ B! Q) x% W1 S; h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% Q; C+ ?) l" v0 A- `9 p& @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# X, A u9 _; ~" rEDMA3_TRIG_MODE_EVENT);- z$ K' K# [) y7 x: |9 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / Y! l6 s! [2 @, e% K2 q, V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% j; X$ a7 P9 t* DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( S% h! N3 X3 y q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) ~$ l0 _; D' c. Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: l& K- O: r( ~% y+ ^7 |: q) s) N0 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' H/ R X' X9 R* V; `9 b
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 f: R |( y9 N/ O F}
7 T( `, a5 T; V% [8 n+ c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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