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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# ^& D* m% [8 K6 ~
input mcasp_ahclkx," y P5 J% Y$ i; c/ h, s3 J
input mcasp_aclkx,$ F- K6 B0 P' u0 c5 w/ q
input axr0,
) `& _7 u' F+ u( `' |
" @! l; F5 p7 D8 Aoutput mcasp_afsr,8 S$ @3 w6 g0 T; ]0 `4 C
output mcasp_ahclkr,7 k+ [. i1 D% }8 V' m
output mcasp_aclkr,
' I1 |; b" x: @6 {- Xoutput axr1,( C2 W" a% v4 j8 k" E
assign mcasp_afsr = mcasp_afsx;0 _2 b3 E7 d( u9 d& `
assign mcasp_aclkr = mcasp_aclkx;
: s* Y2 H! P- Y8 O2 j# n6 I+ P/ Nassign mcasp_ahclkr = mcasp_ahclkx;7 y; I$ ?+ {& b
assign axr1 = axr0;
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. C% J5 J" N, N3 J2 I. z* x- g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% e1 a8 T7 o+ x( n9 tstatic void McASPI2SConfigure(void)
) @( \; u- s; |- z{6 ?% S) u# [& e4 P( }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% ]! s7 T5 D* k* l) G- Y6 Y a3 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 u2 l5 z' b: I) j* }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% n0 @. u( I3 s( S6 f/ TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 X5 f! p( n$ ~/ `% x5 ~: |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. w% W4 G4 T" g, l, L jMCASP_RX_MODE_DMA);1 h0 Q1 e) t8 I+ @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ Y1 f9 x9 `" _4 C4 v, g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! z. {! z' `" K; x) T: NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + d. w) l+ F- v4 b: x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); c' L/ i' U6 }; y/ C& ]- {, o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % v. w" i1 z5 Y( R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 l; K- A- P& a' Y" l. SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 ?4 Z6 i8 @ H# g! L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * }( d& M2 ]( K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( e6 m& J; d5 N4 K l+ O7 t5 a
0x00, 0xFF); /* configure the clock for transmitter */
; y& O7 U" S/ {/ VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; n6 v! W& _ T4 H9 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 e0 G4 i3 r( [" [+ S, T. _+ FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 F, r' l( [" C5 Q( _# a
0x00, 0xFF);$ R& l& s3 n, Z; K
* y) H3 q' y0 p9 U/* Enable synchronization of RX and TX sections */ " x$ c9 A# ~7 P/ G( J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& n7 H9 n# X( }/ c# M* L+ \, V' cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( k7 R& M) a+ a7 D5 E$ B: dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. [7 f# e+ _( ]# L) s1 s
** Set the serializers, Currently only one serializer is set as
e3 W6 T4 I6 g/ z% Y. ?** transmitter and one serializer as receiver.) w- C6 n1 N/ r- S, @! e5 b- o8 s
*/5 J; F" R/ F7 c8 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ \8 e. z. V. i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 A, x" h* f4 g. V- v** Configure the McASP pins
5 Y( w5 O1 p4 [** Input - Frame Sync, Clock and Serializer Rx4 S7 e+ b# p ?. Y/ E, n! s! |
** Output - Serializer Tx is connected to the input of the codec " o( H/ `# C7 E1 Z
*/
_( j- j( x" ?- E0 ]; |! sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 l8 r1 n9 x2 s) c) B- ? Q1 h2 T9 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* C$ P4 S" w+ {8 k' lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# m; r0 f9 ~( U, [( i
| MCASP_PIN_ACLKX
& @% Q# c" i9 e0 M- f/ {$ F. J| MCASP_PIN_AHCLKX
3 i) W+ B8 J9 {* Z! P' d* f. I+ a1 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 \' G: W% d2 k8 y1 [% }. n U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, g5 m$ T' G& _3 x1 h0 L| MCASP_TX_CLKFAIL ' }- d: }* P7 T
| MCASP_TX_SYNCERROR% a: g9 Z4 r$ g& G& H0 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* s# f. ~' h6 ~1 R' N| MCASP_RX_CLKFAIL8 E, X* N' ~* a0 t: B+ ?! H
| MCASP_RX_SYNCERROR
1 S G# r+ f& z) J( p- c* Z| MCASP_RX_OVERRUN);
, R0 d( S/ O- g8 `! d} static void I2SDataTxRxActivate(void). i; |+ v8 k; W0 b
{
, L2 Y' I9 Y7 [9 A3 Z* l/* Start the clocks */
- ?# J( x6 M; \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ R, t1 V( v a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 k) k/ p! ^. I; J% `3 gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. ^2 p Q' ]. UEDMA3_TRIG_MODE_EVENT);; ?/ d' G' I* w: a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 X, T3 {1 ^( J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, _1 h( c4 `) VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% |7 f R) Y9 O Z5 b* U, p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// C, R7 C0 `1 W; y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 i) b: v; ^$ {/ x6 Y) B H' r z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* `# A( H6 j# ^! c7 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( t+ K6 x5 i* T9 g
}
" v3 {9 A7 e e- M0 ?) g: C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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