MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
; o: e1 q$ a1 ainput mcasp_ahclkx,
: n: L. N. X$ W; linput mcasp_aclkx,
input axr0,

) E- K* g4 s. t) C! {$ B6 Koutput mcasp_afsr,
2 i% ?! Q4 H7 youtput mcasp_ahclkr,
6 c( W: ^& ^* }( e8 goutput mcasp_aclkr,
output axr1,
3 Q6 W* F+ q" T7 v7 T7 b* O

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
* J2 r5 x+ {6 P7 M# v# U) z/ B$ ]assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% s* f7 \" G. P! N. N$ k9 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
# H! s- F$ K; o/ v4 V# I: b: GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
9 k$ }) `; w( D5 C' ?8 W9 f8 n: gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( V7 I( C: g: K3 y. LMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' F: t4 f+ N! |9 R7 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 H9 o6 _" ?" U5 X% A7 }% IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
1 m/ Y5 ]& }" {) nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 y) _3 D. c" o, C" J# D. Y8 O- YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) [8 w$ L* E( ^! K* _1 N0x00, 0xFF);

; D: c  e5 c* l. P% p) X, a+ p& X/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
* W" x& t7 I; Q7 _) @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
* C" I. k# k7 F7 A) I8 Y** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
7 ]) @# p- M# C" i* ^' G; bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
4 R" @2 R, W3 h0 s; B** Configure the McASP pins
/ t9 z/ w) k+ B: P9 s* u, V1 L** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
$ |5 c$ x/ ]) k4 p! [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( R- I$ z$ x0 Z1 G5 o& B8 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' I( a1 M9 r; Q9 U# Q: f* O  S) J| MCASP_PIN_ACLKX
3 g! _" J" U; I: M7 _+ H" s3 K| MCASP_PIN_AHCLKX
9 ?" h3 u9 l, X) m. L% c| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
6 Z: V) B7 X: S$ }, [9 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
( t1 r2 l7 c8 Q& H| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. L% }1 O8 N& L| MCASP_RX_CLKFAIL
# m+ G1 z4 ~+ @# {+ `0 V$ ^| MCASP_RX_SYNCERROR
& s( ?) p( V0 ~| MCASP_RX_OVERRUN);
! Q  U" s/ g! [# y* S}

static void I2SDataTxRxActivate(void)
{
7 i. @5 v) |$ b( p/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# G2 J2 o) ~! l( n% o+ rEDMA3_TRIG_MODE_EVENT);
; `; q% ]' t2 o  ?$ R# `- dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
9 {: }, `4 i0 ?& z( i/ DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, N7 ]0 I2 b% E; ^6 a) k- f9 o5 MMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 l0 R' W3 H7 |5 M) B0 _! _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

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