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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: l* s, p$ R$ K. y* C( binput mcasp_ahclkx,
: n7 y+ Q+ s# O" j7 F$ E; u8 [input mcasp_aclkx, P( p8 k8 R/ z- p1 Z+ t" M' Q
input axr0,
6 P8 j3 O3 {! _' L |$ J$ y! @; j/ G, c' R; B5 b y
output mcasp_afsr,0 h2 V I1 z# ]& l1 R* x) D' [
output mcasp_ahclkr,
# T; }5 m9 J- loutput mcasp_aclkr,
& Q. { _4 c/ r' zoutput axr1,
7 M; M4 h) @. I0 x$ F; F assign mcasp_afsr = mcasp_afsx;
* Q, s% [3 Y7 i' V. Vassign mcasp_aclkr = mcasp_aclkx;
" y) [, F6 h S9 v, ^assign mcasp_ahclkr = mcasp_ahclkx;
8 N- S9 `, G$ T2 w5 F" Iassign axr1 = axr0; 6 j9 J' u$ \- X$ g) }
" ^+ z5 h& s, k8 f P# i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 S) K8 S5 J0 Istatic void McASPI2SConfigure(void)
9 l' y ~( c9 C' p) V{
- n' R7 ]( e! I- zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
]7 \) V0 \2 |. ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 q) }! i$ q& i2 O$ [5 k, O, `' |. J& Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. A' g( m/ R$ B- B! fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ A( }8 L5 h7 N5 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ c4 k$ m: n# b0 G( m* lMCASP_RX_MODE_DMA);
% D6 z9 o) n- h6 q8 q$ z8 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' s: L6 x0 b6 P& x9 G; B5 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 Z+ s/ w: T$ c( F' [5 s+ _, J1 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( b* L( P9 I$ {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( M: S& c. u9 C1 l; lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / {8 Z- n4 e; \/ ]/ W# d' h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ g" Q: J- G! G% R) g- G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) ^9 E; ^. ^0 A, X8 W! [, ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% `: n! ?) S" H0 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# O$ z ~9 H/ c" h* C% `0x00, 0xFF); /* configure the clock for transmitter */0 a. U9 {0 r0 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); Q; u+ Z& W* ]$ l6 Z7 c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( k0 l& g# S$ Z! d6 c/ r: p" r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 V' p' G, U9 A+ q- L- C' r$ {0x00, 0xFF);
& h- ?& e; `4 U% D; a$ ?9 O' k& o2 }2 D4 [
/* Enable synchronization of RX and TX sections */
* E& j/ I, w% hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* Z0 ~7 V) J6 W. W: T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- B/ D: y" _( S) b; l Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 ?) E$ J1 o) }0 I- t7 S9 I' M** Set the serializers, Currently only one serializer is set as
9 r& w; I5 D2 N# m8 |# t** transmitter and one serializer as receiver.% Z; U4 O I. y! i1 m; i# ^
*/
" j5 s" O0 j9 q' ]9 d. p: n% J8 q& ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 G' |+ k4 J: {: S/ c* l; M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 d% P; V1 E: R
** Configure the McASP pins 8 E- N% z$ T" A
** Input - Frame Sync, Clock and Serializer Rx
* [3 a/ O8 q/ t9 {( p0 f; o** Output - Serializer Tx is connected to the input of the codec
' X. Q; E Q; Q5 k! r3 O*/
( b. ~3 _) y% O# @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' g n3 F. \- I' Q0 G+ h8 r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& L9 B0 {0 P! X, n( @1 [' eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 i4 r* S" f6 s4 q' J
| MCASP_PIN_ACLKX' z- F4 Y- t9 T! X
| MCASP_PIN_AHCLKX
6 ]2 A+ E9 g9 S$ t' A/ `: Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* W: {: r4 j! A2 y3 L% |& MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ H( s8 {& x4 B% H
| MCASP_TX_CLKFAIL 0 a. r0 k3 D+ D# z7 e( [
| MCASP_TX_SYNCERROR6 y9 [& _( i+ P8 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 d2 }" L/ ?3 o2 Q. h8 e' \| MCASP_RX_CLKFAIL
5 ~4 `- ]3 N* B/ h| MCASP_RX_SYNCERROR % x/ q% N! k& o) L) e$ s
| MCASP_RX_OVERRUN);
$ O7 h) q6 \/ R, Z} static void I2SDataTxRxActivate(void)$ ` o4 X: ]( q7 @9 t( U1 v
{9 f5 ?1 q7 Q* ~. ?. c% w# e% e
/* Start the clocks */# m; s; `7 {7 o x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 ^6 d# a+ J3 G6 F O8 `7 ?5 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 ?! f* r F! {% y S6 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; h! g. ~* Q: n3 _EDMA3_TRIG_MODE_EVENT);! n ?" N5 @8 \) L+ B6 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 }) U1 X% h% t# p% ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, ^2 l' |$ u N P' c" u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& _; _& S' E; h2 A8 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 S+ b7 u6 B: Y5 O: i/ L8 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 ~0 \; t+ }* b7 h, o0 k8 c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 k' Z. ~- ?6 n. d4 d' f8 J/ ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* |+ s3 r# i3 C. ?
} 4 L: R$ Q) |; n: }7 _9 y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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