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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ S( w4 r/ y' u2 Z* g* ninput mcasp_ahclkx,6 H8 t( ?# u6 _; Q% X
input mcasp_aclkx,
4 J2 U2 [) ?- _. Qinput axr0,2 w5 B+ l6 ^2 ]- }1 x& E
& Y# Q. A9 L, F1 `8 Q+ _- o+ b. n+ s
output mcasp_afsr,* b7 ~7 b$ p1 H) ?1 m2 V, Q& J4 C
output mcasp_ahclkr,' w u( @0 @- b% M- O
output mcasp_aclkr,; J3 v& K8 f0 o+ v! K9 B& C$ U
output axr1,1 d% b6 y r- n3 u
assign mcasp_afsr = mcasp_afsx;( r" F, h0 ]! n! {) I$ g
assign mcasp_aclkr = mcasp_aclkx;! w: w- J, D- V9 r
assign mcasp_ahclkr = mcasp_ahclkx;* j! q- r7 n* \4 |# [8 f: G
assign axr1 = axr0; 7 l1 W9 m4 p1 b0 G6 `: z( ~
" ]# u' L: J& x% U$ s; D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 p( z; i7 f% \* l+ X- B. q
static void McASPI2SConfigure(void)
8 }- v6 @5 p5 @- `" s$ J z{
" U1 h' [& J, Z, W( u2 k6 J' Q/ ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 T# b8 c3 u9 z p5 }4 o* ^* ^/ XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" r( n1 ?3 o8 H3 {3 s4 f4 \8 Z! \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( w7 L$ R6 c2 i9 d/ wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 D8 F. x1 `" S4 P8 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: P% t3 _# \) {' d' r
MCASP_RX_MODE_DMA);2 A5 d3 g k/ [) X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 v+ V8 n0 k1 t! f" S1 b6 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 I9 T) b' N- M" l( _7 X. _8 s/ b' @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, Y F; R: D" z% {! lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ G! @% K- @6 ]% RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 G: }! z* Q: z8 v0 J& lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 v+ p2 j$ o) r" |/ a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 R' D. | U H& f4 E+ v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 h+ x \! Y9 P. r7 m# t0 A6 [+ b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% e8 I$ T; m$ J- X5 a0x00, 0xFF); /* configure the clock for transmitter */
" T) x+ z7 J% U2 [& ]# |- S MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); ` f+ f4 V/ b& a6 `9 M) w* \/ }* o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! \: V. _# O2 }7 E3 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! m: e& S& c6 K; [! g- i/ J1 }
0x00, 0xFF);
6 d) X: f* D+ X+ ]7 p0 { z" w
8 d8 k3 Y4 _# A; W/* Enable synchronization of RX and TX sections */
( l4 {" r' v- _' `1 c6 m& D( NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% {7 ~- i8 b, t1 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: Z7 L! i+ N) X1 M) w- ~0 N* l2 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" ^6 n# | r+ {- c- L* ^! j$ R( L** Set the serializers, Currently only one serializer is set as
# @1 n7 P: `$ Z# [3 s1 E- X** transmitter and one serializer as receiver.
# p* s! k2 q0 q* V% a4 P6 M7 P7 l*/
" M& L" X; r& u! Y2 \. _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" S. z! [& |9 `/ wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
j, t' N- w( S# s+ k; z- B) V' ~' o** Configure the McASP pins - [( s( H& v" v' s" S% ]
** Input - Frame Sync, Clock and Serializer Rx! u9 G. N+ d4 A, K( l) M) f5 I
** Output - Serializer Tx is connected to the input of the codec $ ~8 j/ g* L& t
*/
+ P k' d: |( o& C7 F; L+ G/ ?, H. ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ [5 m2 b3 o' M" Z! W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; p2 K( K l' ]1 x* X2 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& M) O7 ^. C9 X( w' u9 U2 z| MCASP_PIN_ACLKX. p6 W- q( d: {
| MCASP_PIN_AHCLKX- v1 L! ?& z4 f8 B) Z' R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& M5 }/ g& |/ v7 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ M+ e- @+ J2 K- G0 ? P+ Y6 F| MCASP_TX_CLKFAIL
# P3 X" n- \' e| MCASP_TX_SYNCERROR% j) c2 j O4 ~% N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + ?3 ~) l+ _) P( Q
| MCASP_RX_CLKFAIL; z" W: }3 S% Q: t# c# z
| MCASP_RX_SYNCERROR 7 |. E- Q+ v9 ?- `
| MCASP_RX_OVERRUN);
) U6 B( X+ Q4 ~1 W1 k7 {} static void I2SDataTxRxActivate(void)
# s) W; r+ o( n" B# ^{! Z0 O8 A1 e# b6 m5 t3 S! e
/* Start the clocks */
2 P! O X0 z' ]5 u l; i rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; ^0 W0 |, x. O) ~& Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 N- ?) ^. U( uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 f4 l1 e, D& p; O7 }, `EDMA3_TRIG_MODE_EVENT);
. e8 ~; K% L3 M* p/ J' REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / y! ~! e# W6 H! r* {# n/ |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// N$ G5 X7 b/ ^1 u, R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% i& r" \; O5 M7 a0 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" p" `% {7 m$ a1 V9 L5 q6 h; i( Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( r y9 Z' i7 P0 b' wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) I. e+ u- l: x- w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 J" R0 ~9 m0 O' m( v; @
} " I' u+ s8 ]. ?$ F4 `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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