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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( |) _8 V# i4 i6 M' J# ]+ `input mcasp_ahclkx,
' L4 X0 u+ {7 ninput mcasp_aclkx,
, p* n$ E9 H1 s4 D" o1 Rinput axr0," O' n" [6 c2 ]3 r. k! F
, W; {4 Y+ N1 D% K) _
output mcasp_afsr,: a- t" a' w; u5 h i6 g
output mcasp_ahclkr,
& P0 T. ?; O$ ~) W% \1 ~output mcasp_aclkr,
! X Q# z! L' doutput axr1,* t3 q" y0 S2 a9 T* b
assign mcasp_afsr = mcasp_afsx;
2 r1 F" m- h" O3 L. K+ iassign mcasp_aclkr = mcasp_aclkx;
2 n! f; Q/ f0 v4 x8 D0 e) Jassign mcasp_ahclkr = mcasp_ahclkx;* L$ ]. a |* I
assign axr1 = axr0; - {. E7 ^5 n- G
- r3 K) q4 `7 R7 n. f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# {. S! {/ f# Z$ v- i. _6 |static void McASPI2SConfigure(void)
# \9 d: Y) Z( y" q/ L{# E* q6 @8 z" a/ L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, W0 n. c ~7 m! M }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 q; Z/ I/ {2 c& q3 ?8 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 S7 `$ J! F5 J8 S C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ J% C" [; P0 i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! S* B6 ?/ D- E9 L" f; XMCASP_RX_MODE_DMA);
5 t1 M9 X5 w# u! N% v- F L7 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) A2 Z/ n# H! J4 b; I# w' QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 I1 p3 K6 }7 X+ r9 `6 B: V1 p' E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 }* p, a4 ^# |( C, {4 F" j6 S# X5 H+ QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 G" m7 N( l r& O- |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 i5 |, V& A/ D K* `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 Z, c6 ]0 N( d# d& t' Q) ~. A/ g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. P1 v( e5 t1 ]$ w% l; UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- j+ E j$ ^* j/ Y8 cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" p* D* M& {% ?2 ^$ C5 ?8 n0x00, 0xFF); /* configure the clock for transmitter */
3 K+ B b; I4 I8 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ k5 \- s: t/ {" w, g+ p5 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 c/ n- G3 u% Y4 \0 z8 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ r7 b3 [! x8 J' \' b
0x00, 0xFF);2 Z# {1 w* B/ Q8 J# a% p& m9 a
" R8 b0 s! Z5 q: F0 P/* Enable synchronization of RX and TX sections */
+ Q8 X& u6 V' TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 a0 l. G+ l& m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! Z1 i! c1 r& J7 H% c0 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" | @% J. C7 a: H
** Set the serializers, Currently only one serializer is set as! [* g3 a" a' q! y
** transmitter and one serializer as receiver.
1 T! K+ ]& I8 j! m/ ~; P; F2 z*/& P8 H; Z, ^4 v3 D5 q( h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; J7 S2 ?9 C& b7 u1 K9 X2 S8 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 E% N5 Y) t, l7 h$ `% I
** Configure the McASP pins
1 J1 L: P7 r# _** Input - Frame Sync, Clock and Serializer Rx
- ?# ^$ }/ x( \1 U5 o( W** Output - Serializer Tx is connected to the input of the codec 2 \* \' S L6 k1 K
*/: n% t1 a& J) a! Y. E3 r2 J j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 Q& r, W: k$ a1 w W7 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); I- F/ e9 Y& @+ Z+ Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( ]' s! q! u6 e! l$ ]7 Z: O| MCASP_PIN_ACLKX
, `" G2 E; q: T- e* y% m5 b| MCASP_PIN_AHCLKX
/ p7 [9 @8 G7 z# \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 u! E# k/ \7 O' `6 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- |& J$ f% k7 E* F9 X| MCASP_TX_CLKFAIL 9 e, P- R- q- p* k. o3 V0 K
| MCASP_TX_SYNCERROR | R t1 T/ o7 I4 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 a9 F# a4 l+ X7 Y, G' _| MCASP_RX_CLKFAIL+ z, \7 Y) q* E. k/ S @
| MCASP_RX_SYNCERROR
) f$ ^0 @ j3 J| MCASP_RX_OVERRUN);4 E! t# i8 ]0 H, z A" J0 M
} static void I2SDataTxRxActivate(void)
! p' m. a) ~4 z- s! P# a) ^{9 q2 E0 C p/ R7 w! M5 T8 x
/* Start the clocks */
' X0 }' b: o: C( G, p& `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! |) Y% p/ V# t9 `& Z2 I4 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. r+ Q [3 M4 C4 L3 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- y9 D+ V; F6 j$ M
EDMA3_TRIG_MODE_EVENT);5 ~4 X% I; _0 y. }3 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 }9 d6 M2 g. v2 ?% c) ]6 L- x$ lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 @9 z" d3 _. p" ]& ?- O: OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); [8 F$ h1 H3 R& \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; }, L* p4 d, k3 S6 Y/ q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) ?, H8 n$ T6 r7 ?" r# Q" V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 t. I6 }. T( {; n( a- o- y/ K. m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( E! y" E# A6 a8 N; Y! v [+ e
}
3 G7 k! c9 g) R$ O& K9 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) g5 {) O# x8 |" E( M
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