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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 c% \# Z2 ~/ r! Iinput mcasp_ahclkx,6 D3 Z3 J: [; B. E$ v
input mcasp_aclkx,
* x! N: Z& Q3 W' q% a+ R6 \ q% \% Sinput axr0,; l9 L. }/ u2 s
+ V9 r; h- ^4 R: M4 J% \! H( `/ Y& N
output mcasp_afsr,
, T2 ~* c, h8 G# S9 voutput mcasp_ahclkr,$ [7 e$ a, |/ N6 {
output mcasp_aclkr,+ F8 ` g( u2 o) W5 V
output axr1,
1 f) M c2 d1 ]3 c: ~ S) w7 y assign mcasp_afsr = mcasp_afsx;# ~& R2 ?. ~; u) ~) X, K
assign mcasp_aclkr = mcasp_aclkx;9 a h$ t# M) _; p- j" D' `& g* w7 p
assign mcasp_ahclkr = mcasp_ahclkx;
9 a/ k( X' g2 Q7 Lassign axr1 = axr0; " ^/ Q$ I" h. G4 w8 ?3 G) K
) M- G" e/ m. s7 {: P ?' z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 q( ?4 K- ^- q/ Z* a
static void McASPI2SConfigure(void)* a1 D4 c+ I F
{
% q4 Z/ a9 \6 o" O9 W) rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 d/ a9 N0 n' _. {$ `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: i: T% z: H; I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 u$ q1 M- J9 f- uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 h0 M) X: A3 N( uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ w+ F7 f) m! Q- O9 e- \& U% s
MCASP_RX_MODE_DMA);1 F7 ^ _6 B& @# H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 X: R9 d+ V& ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 |) u' w5 r9 Q/ e) Z4 ?' l! c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + S: r9 w& Z7 s* v9 ~! C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 L1 N9 \/ a5 ?; ^3 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / z/ p& d! U- R. y$ W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. o6 x# P, h% N3 O+ r3 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% H4 @9 Y1 w; Q @3 G9 @4 o0 j. xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 a1 Y, s; U, L$ xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) M9 [0 j% ?7 O/ x( u7 f( `. C
0x00, 0xFF); /* configure the clock for transmitter */7 I0 m) d" b% S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' e t% x1 o- k, g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 A' H0 {8 n( ]2 RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ `1 e- z9 C5 j) X a1 H0x00, 0xFF);/ p5 |3 O6 ~, i" H' a% V
0 E. h1 L: Q% `
/* Enable synchronization of RX and TX sections */ ' p# V4 H9 `0 @! w0 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, A3 n: Y F* ~: c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 U- |4 [. J2 ]8 l4 L9 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** J8 U8 T* R8 `" l# p/ v6 ^
** Set the serializers, Currently only one serializer is set as% r6 _- u+ c4 d7 W( x( X
** transmitter and one serializer as receiver.
& E. F& C5 M7 K6 E5 y5 D*/# Y$ W' s6 a& y; X% ?+ o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ G8 j7 A' [% L7 V7 i/ N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 R' N* C' p3 ^; f }3 w
** Configure the McASP pins ! x5 s* \1 l: f9 [: R3 S6 y
** Input - Frame Sync, Clock and Serializer Rx
0 _: v: y( I. W9 n' I** Output - Serializer Tx is connected to the input of the codec # g1 j2 K7 [" W6 L, W
*/0 J4 e$ c) a/ i5 K, |, z+ a8 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ p' @* ]: }/ w, `: p: q+ N7 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' e6 C% V. N2 v( PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 K" q/ L8 ?# ]7 b0 _2 A
| MCASP_PIN_ACLKX
% c9 c" O: @$ k| MCASP_PIN_AHCLKX$ y" r* r, c: d* D3 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 \ z9 O7 }; I1 X$ E5 g6 k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 ~9 r( t: r/ @$ O2 v* }+ a| MCASP_TX_CLKFAIL 1 Z3 B3 b+ b; |# J6 H6 E
| MCASP_TX_SYNCERROR
% m# H# ^0 A- P" i& P1 `) e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 D4 r+ ]. v3 h( S' M
| MCASP_RX_CLKFAIL
, b, ?+ l: r4 X6 x* k8 S| MCASP_RX_SYNCERROR + T5 s" ?- W* ?/ r) s
| MCASP_RX_OVERRUN);
7 L, B Y9 K$ k) p6 U. B! I" m i8 k} static void I2SDataTxRxActivate(void)1 c- M/ e. m: P# |3 i
{/ [5 C- Q' {! e+ l: R
/* Start the clocks */8 N5 `9 g* S) Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; v, i4 P; K, ^( _' M! b* hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' r4 |+ B. \$ X$ G1 x" ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, x2 C! o6 M# AEDMA3_TRIG_MODE_EVENT);
, j& s; a- [" T' k' {6 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 _" _& v/ ~+ ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: R' i$ I/ n" l, w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, O; B& G$ ~9 q2 [2 ~- n# L" ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# u- j5 o' x9 z" { W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ W. _- M' w7 v3 {6 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 o5 l6 e- b+ o5 N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 D( n! \! M& h/ p
} 3 d/ ^5 s2 r: k# @$ `* x) b: f% p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 q3 ?4 q `$ S( g- D
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