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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," `# L7 ]' M: V+ r
input mcasp_ahclkx,4 a+ h& ~! ?; {+ Z- e* E
input mcasp_aclkx,; N# m% z I4 i6 r
input axr0,
/ r4 P! C2 L+ O, Z @* ]$ c3 b' V. g2 a: d( Y# p+ {- d7 P% p
output mcasp_afsr,
+ S* w/ R, M8 ]8 l" w+ H1 C2 n1 V& Woutput mcasp_ahclkr,; n7 }5 G8 P& h
output mcasp_aclkr,
# }- j; Z, Z0 f2 ]3 ?8 T. Z: poutput axr1,
6 k/ ?5 V3 X# Z3 }' I) M assign mcasp_afsr = mcasp_afsx;
K8 d% b, D% E& I! s9 d0 J d: Aassign mcasp_aclkr = mcasp_aclkx;. F+ o7 Q0 v+ g6 F/ S8 I
assign mcasp_ahclkr = mcasp_ahclkx;
! S T% X" X& H& o: A8 R" massign axr1 = axr0;
0 z, Z- t# w+ H4 r. }; b. \" l) U( }) ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . C4 s5 o3 A) v. `/ n- ]8 U
static void McASPI2SConfigure(void)
: K4 B5 s. I% D% |{
4 @& W& P5 X: e3 D1 W$ CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; `# A0 f/ M! p1 W( M) c' i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// B; F' y, {9 c/ L4 X3 T9 d3 c. L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" e4 t$ U% X9 U9 \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 S5 ]4 A/ J, e6 b! K# J' y& z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* x7 u. w1 H8 `: R0 V; A/ l8 kMCASP_RX_MODE_DMA);
( j" S3 H9 o- ]1 v7 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 s& G( m) z# F! M; T! f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& r" R- }0 z$ FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 s& f! C5 ~* eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ j3 T: o# ?6 p3 o6 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . }- k+ L, a" a1 R+ Z8 ~6 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- R4 }( {: v/ Y: d( SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 }9 G$ E4 Y3 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % f8 v) O N3 W- s& x; d3 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, n4 V8 m! z9 N( s# z5 C! K
0x00, 0xFF); /* configure the clock for transmitter */
7 [8 R! W; } M; ]( M9 Y5 M3 b$ E/ eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" a% u. s! P$ x# b; S7 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) C' R. J0 N+ G3 ]" j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; @, f K+ n7 z
0x00, 0xFF);8 T M4 s9 X4 Y' ?$ y
# L9 z1 a; F7 X
/* Enable synchronization of RX and TX sections */ ! T2 E' ~5 Y1 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- j5 Q; r$ t& p4 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 ?8 `# h O" G' k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ c0 w5 o) j- S( }$ k& r I** Set the serializers, Currently only one serializer is set as
5 n, K/ `/ p# ]: I% V. k3 M9 K** transmitter and one serializer as receiver., q& Y$ U5 m2 z
*/
. m- D- m) W# E0 S/ r. zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ T# T( ]( f! U) e3 R: [# |/ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) |7 r. o2 J9 r( _' t# ]
** Configure the McASP pins 8 y% ^! L5 C( J4 L; b }: Y
** Input - Frame Sync, Clock and Serializer Rx
* t. F! z0 I7 q5 g/ \! ]** Output - Serializer Tx is connected to the input of the codec 0 L9 j) K+ B2 z5 N, h# X5 S* e
*/
# m1 T4 U( K+ Q+ N" O" PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 A F( `- g b+ ^1 M, e$ U6 J2 v/ u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% I9 D1 T: z5 M: V/ a8 v. }: q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! t+ G6 Q# P; L2 ]9 M; Z) z| MCASP_PIN_ACLKX
, k4 n' N2 f3 N" U. B- h| MCASP_PIN_AHCLKX
; {" y" G4 X+ u2 r8 k" A4 z3 @' t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 {/ _7 x5 ]; H9 u/ j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # S5 \2 b- }" A' }0 D. R4 j! I; S
| MCASP_TX_CLKFAIL 5 F( N1 O/ f; a9 e
| MCASP_TX_SYNCERROR
. L/ p s- R5 t) [; B: L0 K3 E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
K1 V6 o5 a8 m; D| MCASP_RX_CLKFAIL5 k5 |+ j7 u& D5 z2 S
| MCASP_RX_SYNCERROR ; O) Y0 r2 s& S& n6 A
| MCASP_RX_OVERRUN);2 e$ @3 p2 w, B% b) ^* f
} static void I2SDataTxRxActivate(void)/ K! x! `2 Q/ t3 T. \; Z s
{
4 r! g& z) q7 I3 o- v/* Start the clocks */2 Y) Y+ S& `5 M- e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, k" `# r# V6 A" X3 g% A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 Z* s4 I2 ?# f- r6 h/ c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) }8 T* ~7 I* P! D' Z2 }+ TEDMA3_TRIG_MODE_EVENT);* Z6 f$ |6 S; X4 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . F2 a# |9 g# J9 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 n9 z) D( }, p# k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 x' g! ~4 g" V* |, M6 {6 Z$ c0 y5 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- M' r4 F6 \& T, u# J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ^# c* w# f% B& I# hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ]+ L+ Z( g5 O9 K! v: w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 _0 t+ |( I1 F
} : J2 F8 d6 R Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 \/ J" a0 I5 s) k* |) |7 T
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