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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 R$ d. O& u2 D" m" `( F1 a! ?input mcasp_ahclkx,$ L* g6 t1 e! s
input mcasp_aclkx,! I( Y) A' C3 Q. c, w
input axr0,& Q6 ?4 X+ H7 ^5 {% s* c5 d1 @" k8 m
% S/ b3 X+ P$ ^& P: ^; B+ Y' E3 Q! @output mcasp_afsr,
: r1 w) e9 t/ x" T- [# t, Houtput mcasp_ahclkr,
1 Z: Y# Z) D! F9 F% Zoutput mcasp_aclkr,
. F: ?- O& Z- toutput axr1,
9 e9 u- | h' G: x assign mcasp_afsr = mcasp_afsx;1 T/ U) i y5 w# x
assign mcasp_aclkr = mcasp_aclkx;2 ~: d5 A# R( s
assign mcasp_ahclkr = mcasp_ahclkx;* d0 N! s- Z ~$ \' e* p/ @
assign axr1 = axr0;
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* l: Y: y; N- |. A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 p; L$ A8 L# D. o% Ostatic void McASPI2SConfigure(void)
3 k0 R. e0 z; q* W( J/ X1 z/ z{$ S2 s" H% Q* l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ T! b3 o: G3 J5 R$ r5 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ d) v: Q) M; y( j" K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& h7 {9 w4 @0 u; L2 ]1 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ l9 Z V1 H, {4 v9 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 K7 y' }: k* s! M6 c. e# kMCASP_RX_MODE_DMA);
: e3 V$ X) U" }2 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( t) S1 d: x/ P' i0 ?: V& z! tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ a; q4 L4 s% M8 h2 k) `- e' G1 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 v, A f" i5 i8 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* j5 d) @* @* X7 w% B- v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- Q' g B) _ \1 G( IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% d. R6 Z0 f5 Q$ b% tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 C* @, k* L( m3 `7 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" b) y+ a1 }& [1 N; wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; y! B! p- @( h2 _6 C7 g+ o0x00, 0xFF); /* configure the clock for transmitter */ f, W' {0 d+ @- d. h0 f+ W i2 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( I, O% o' Y0 _9 I7 z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , W) n8 `0 i7 ]! i7 `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' a, e) i! P, M6 L6 n+ |% `2 ]
0x00, 0xFF);( T$ M/ A5 N: Z5 J
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/* Enable synchronization of RX and TX sections */
7 x Z) M+ `# x) Z: e5 K0 GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, i: X5 o( g+ \. t# l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ U) Z0 n4 A8 i# J; M5 S1 q; X* AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ \& t! x8 k2 K** Set the serializers, Currently only one serializer is set as
! [9 C$ f! m7 }; X* g) c; A** transmitter and one serializer as receiver.8 z: i, L i7 _3 }) _3 z
*/! E0 B) k% y, g6 ]" ~% F# w/ q& u* K" [$ I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 U! t4 \. O+ a, F: DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 ?& g+ i! W, D( s1 S** Configure the McASP pins 8 q6 G. {# A5 C9 x& |2 o. P* V
** Input - Frame Sync, Clock and Serializer Rx% P; a0 R' i' }) `+ W4 e
** Output - Serializer Tx is connected to the input of the codec
- t& \3 a# ^& r" n/ p# ~1 R/ ~*/
* c6 K$ e- b6 B0 {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& F9 G* B) k* m) U& @# t# n: rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% B: @6 U! E- m1 {* OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX x Z( F& t% `; |
| MCASP_PIN_ACLKX
$ s6 z0 b1 L* f( I- v, J; _. `| MCASP_PIN_AHCLKX- u, I4 }& ^5 D$ b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. {4 ~# |' g! j) Q$ d/ o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 p4 f1 G: O% \: b# ]; ]
| MCASP_TX_CLKFAIL ( l7 [6 f" C" s2 {8 T4 O
| MCASP_TX_SYNCERROR% B' @2 T* I9 |- n0 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 m+ q7 R& N/ c0 O| MCASP_RX_CLKFAIL
( E$ B$ ?- j* V5 e| MCASP_RX_SYNCERROR ( R5 U% N; q' R5 P0 T
| MCASP_RX_OVERRUN);. _) v. x/ @7 q% n
} static void I2SDataTxRxActivate(void)
' u, g" H1 R3 H& i+ S$ D. c{
6 [. p1 q2 q; R1 i/* Start the clocks */
; u Y7 ?1 {* O( k X4 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 Z Z8 ~( W! X4 S1 g7 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# j. m5 C2 k7 w O0 y% sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: T6 ], V/ G' Y# H/ lEDMA3_TRIG_MODE_EVENT);! `+ t4 ]' K7 ~, h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; q8 }. E% F- \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 T1 o( a( G$ }, t4 R& D+ vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 }0 b8 {" u( h4 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; Y, W3 L7 m) n; h8 O3 I1 D; q" C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: U- G2 Q& u* a( V* L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' K9 _: n! l2 c2 J: fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- ^/ f3 o5 q9 i( z8 Z+ w# H}
6 U' g" X U% x9 |' L* u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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