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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. c' e4 c/ g7 C9 \: ?( W
input mcasp_ahclkx,
) R; J. n2 |( K% b7 b2 w6 minput mcasp_aclkx,
% H) z, z( ~2 j" w I7 X, ?, f8 |" qinput axr0,
2 `# G1 [9 L, X( o. V
4 R8 I1 q& T7 G2 ooutput mcasp_afsr,
5 Q1 F# b9 I( j6 q4 p; q( Boutput mcasp_ahclkr,, R) _: N) O. w6 q# v, A
output mcasp_aclkr,
# v( r! a( k9 v2 P/ youtput axr1,
0 x/ Y: }& ~! h5 k) { assign mcasp_afsr = mcasp_afsx;% U4 m% M/ D, K
assign mcasp_aclkr = mcasp_aclkx;- x7 N, b3 C7 y1 j( X5 u) W$ E- g* u
assign mcasp_ahclkr = mcasp_ahclkx;) j3 I2 b# U# v
assign axr1 = axr0; 3 {7 u W7 L+ O7 o: v
1 H' r( ~! P' i8 D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 n4 x4 C# [2 T2 H
static void McASPI2SConfigure(void)' j! W. p& H- b) X3 P9 v5 ^
{/ ?0 J- v3 b: I" Q6 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ k3 r. Y4 F, N! k' X1 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! K! W, n7 k! lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 S" x( D; s: Z$ K( @9 c& lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ S0 ~; |! i) k: b- Z; j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" ^2 F3 g6 }" p8 g+ W; {8 qMCASP_RX_MODE_DMA);6 C, L/ v' t2 \" _; `: m# n( Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 q# U% v. J9 ^ ~( H$ wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 X3 O2 I0 i3 d/ S: x; {% PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( D% B6 w# Q' I! h# ~% y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 p! `3 b C ~7 g( [, I. {! MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ x; j0 y5 d, R$ i- V9 v9 y% b1 b+ ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& p! k& Q+ `, ^( X- M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ B+ r9 T4 l1 N+ F+ Z: Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! I/ ^0 k$ l3 r) K8 t/ C# n: uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
?# Q( \6 j/ ?' N- M0 K' J0x00, 0xFF); /* configure the clock for transmitter */. D) H7 N( F, K' z9 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 B8 C' e k/ f( ?" T9 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: \4 z; Z7 Z. `. @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 `5 P3 n ~. q- o ^& }" h+ W% |% l% W2 g
0x00, 0xFF);
* {) f3 l5 Z+ {: z8 N5 J" j k
0 B% @) }; C0 ?) V6 ~4 N, M/* Enable synchronization of RX and TX sections */
+ L4 [- u$ w2 A$ n5 \1 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 ?7 e `* L; c8 S ?0 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; A+ j* K, O! D7 m7 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 W4 o- r' r1 w9 ~
** Set the serializers, Currently only one serializer is set as
M/ I6 z1 \ y( ^** transmitter and one serializer as receiver.( t, N6 p% r, X$ C5 G1 S/ ~: N2 }0 _
*/. y+ Q; y5 }/ ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ E3 `& e1 w. v, V* @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 X; b U2 j& h* Y
** Configure the McASP pins
1 B+ _" Z5 M/ q1 H7 A( [8 x" F** Input - Frame Sync, Clock and Serializer Rx
/ p0 t+ n! N# ^8 ? h) @7 {: q** Output - Serializer Tx is connected to the input of the codec
3 b0 L8 z. [+ l# \ z2 w*/, J& Z/ d( w: W; F) m3 e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% A @. m7 n8 w+ b# b# i# M" |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" T% N: @) r+ o1 o% V1 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 J" F3 o4 x/ D( O, H k
| MCASP_PIN_ACLKX
* e4 A' O/ w/ S: G| MCASP_PIN_AHCLKX
/ v1 O; u# z; ?/ n$ {2 s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* v1 D. q/ G* @9 s* x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. s3 q/ K" E# w8 g- b5 p" b. {+ Z| MCASP_TX_CLKFAIL
$ O$ b$ D, N6 U4 e# y| MCASP_TX_SYNCERROR% R% _" S, O* j2 u' Q9 ~" g3 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 N$ v! _* v" ]2 V& i
| MCASP_RX_CLKFAIL7 ^+ U' X' [8 F S3 Z
| MCASP_RX_SYNCERROR
5 g6 p; r- G4 b8 p) d( y" y| MCASP_RX_OVERRUN);1 m& ?/ @' ]9 B) k, p
} static void I2SDataTxRxActivate(void)/ j9 T) `6 ?* z# c- L) |
{
0 Y% m6 S8 K, i' Q4 A2 L1 V% C/* Start the clocks */
( b1 v/ L. x( ~, T; nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 [- @; i" W0 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ D8 D C7 [& C5 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; F* d0 O, S" A5 l) X4 H
EDMA3_TRIG_MODE_EVENT);
4 E6 W! Q; h" m g0 o) ^; YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) k* B% d$ @, g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 I- L: ?" D2 J1 y a, W$ v. S0 @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 s8 _9 y' ]8 W/ |. N9 r5 I1 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( f5 |4 ^. z3 G+ L( T/ _+ O5 U- cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( c) z/ p* M$ Q* d7 y5 F8 Q u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 g- X @: w3 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; v9 |! C5 j8 `0 ]4 A
} 5 o6 K. U* d" t! Q5 K" O% ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : S' |8 }" }& H0 d4 w& Y
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