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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* [, _- p4 N: t+ U+ P7 J! X
input mcasp_ahclkx,
# K% o: ~0 a" `3 y3 C; ?, z, ninput mcasp_aclkx,3 j1 v2 S7 x2 p
input axr0,
) `. C) z$ i: b( _4 z3 b
+ f; [7 m3 P1 q, uoutput mcasp_afsr,
/ W, ^% L. j+ x# @output mcasp_ahclkr,/ T* g( t/ F0 G% z/ X" q
output mcasp_aclkr,
' L! w" h! a6 o& Moutput axr1,7 |' d/ A4 g1 L f! x" F5 f! x( X% @
assign mcasp_afsr = mcasp_afsx;& N9 R Q# t7 e) ~& J! q
assign mcasp_aclkr = mcasp_aclkx;
# p6 v3 s, m& [" S- ^- X5 W5 Fassign mcasp_ahclkr = mcasp_ahclkx;
* f4 [& { F: V: z3 r( e/ n: b- Y' @assign axr1 = axr0;
* } Y# }$ _% o f. g* v2 ?& C+ f) ~/ [5 M3 M$ \7 x8 h- d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! i% B$ C2 y# I5 }
static void McASPI2SConfigure(void)
* J! }8 K* t1 N{1 |8 x3 f/ _" Z; e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 A" s w; O; \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
k* o5 X3 i+ m2 I/ fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! |, v- E* s& _' \0 W& V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 Y5 L+ m# ` yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ B; D( L+ b6 U3 C% s' j
MCASP_RX_MODE_DMA);
" y/ ?! c! m' Q ], jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; F! X9 w9 |6 t0 X( a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 }7 L2 E1 c- M4 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / M/ J% T1 l3 S, S* K5 }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 E6 j2 k5 M6 O: J2 Q0 W2 G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / D+ Z- O% G% D7 F, k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. j) u$ U7 u# M5 B$ A, Z' d9 v3 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 p* _$ g2 }; ?' u( P R! `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
z! C, [6 n" i2 W' X9 _4 |8 X9 _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: l9 ?- i+ K8 D% K+ v6 R5 S0x00, 0xFF); /* configure the clock for transmitter */
e2 U" o% y2 T- ^6 y7 U" r0 m, lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! d5 i5 @4 p4 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' G3 w# D. O0 r4 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- S9 M5 d3 y# m/ O# h0x00, 0xFF);
3 y" X& d5 \; Y/ [! ^' T ^ ~/ u' H/ k
/* Enable synchronization of RX and TX sections */
+ v8 w8 ]& X/ SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# W' c/ e3 H" h& F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 X% l \- Z u7 d: F4 T' g. }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% I0 `% \6 b* s' [. _# l- R; Q% y
** Set the serializers, Currently only one serializer is set as
$ H. g T5 K5 S1 O. h g9 j- G** transmitter and one serializer as receiver.$ \; T* Q3 s t5 H$ m; i. l% u r
*/
/ ~6 i. ~4 r* q, TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 ]) `3 f$ A; p5 [- SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% O5 y; a2 V3 e+ ]& G1 b** Configure the McASP pins 3 z' z! t3 M" ~$ V* k
** Input - Frame Sync, Clock and Serializer Rx
0 z' f* y& h6 W. f' z4 O** Output - Serializer Tx is connected to the input of the codec
n+ u: `( h, ~% `) @! W d*/# b! I% m9 Z. L5 e, y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) F$ A" t! P8 O/ | w; M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* D V; X( k9 T3 ?) Z3 z2 `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( B5 @9 j4 T3 o2 {$ K
| MCASP_PIN_ACLKX0 W2 p0 H& v7 d: W5 G( |9 P ~" ~' R
| MCASP_PIN_AHCLKX) s: ?) d2 ~! f, b* x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 S8 X7 B X8 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; N8 p! Z4 i8 T: X* _, [
| MCASP_TX_CLKFAIL . f, ~6 P; c7 Y3 W% t' Y# ?; o
| MCASP_TX_SYNCERROR
; M/ f' I. K, X2 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( ~4 P6 Y, O' H8 i C| MCASP_RX_CLKFAIL. ~; e3 e2 ]5 D+ m. q. l
| MCASP_RX_SYNCERROR ( M- d+ p$ U5 ^
| MCASP_RX_OVERRUN);1 o$ h! ]; s% k3 z
} static void I2SDataTxRxActivate(void)
& R& `, B. S+ r3 |{
1 q$ A, m* O7 B% f% a4 j e/* Start the clocks */
" L: _1 \" x) g; \/ |* I8 ?: tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 @8 X$ n( Z9 f$ ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ o1 l8 J$ `, y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, W8 `: w, L; u* J1 i, T
EDMA3_TRIG_MODE_EVENT);* L3 B/ Q3 |8 K7 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . z; a1 o l0 r& I, e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 L6 k+ r7 C0 `' u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) |) {8 o6 Q, r# C- v& {) s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# K% W! i ]9 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ Y# {. T5 \/ ]2 H, n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) |1 f' W& L: n4 K1 A' i& G$ s, N* C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. ]- c0 x( e5 w% L0 g1 V7 Q6 S
}
- q/ w# o, W. z$ [- k- C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - B$ s( L6 I2 G) R
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