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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 ?& d. B$ ~ Q, C( m6 {& L- [/ Rinput mcasp_ahclkx,1 w) P3 _: r" m8 B* H# b
input mcasp_aclkx,
; m+ C9 }% r4 M6 w$ Tinput axr0,
' Z5 f; j! o H7 N# t1 b% Z$ J0 s2 ]4 a+ C9 j/ n; {& B; Y8 a
output mcasp_afsr,, {; M9 d; U- d- n
output mcasp_ahclkr,/ C8 {: h, d8 U2 n' Y7 y
output mcasp_aclkr,
) A7 B( n. Z+ o( a) n4 e" D1 Woutput axr1,. ]4 F# g8 I8 U. U/ Y/ n: Z
assign mcasp_afsr = mcasp_afsx;. Y! t) _' M7 K' j& Q
assign mcasp_aclkr = mcasp_aclkx;' N9 r% z9 O2 o, a/ ~
assign mcasp_ahclkr = mcasp_ahclkx;
5 Y9 r; Y* P, Sassign axr1 = axr0; & A- d$ b9 A: e; Q
2 s" m {. l. B! d% X& P v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( K: c6 W" d, M2 w2 |7 R* i4 `& r
static void McASPI2SConfigure(void)5 e5 _) W( M* A
{
9 r5 l" S m% e1 _McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 G: l/ X9 m& r) j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 ~( y: {/ Z% u0 A5 A$ @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. y2 A5 ~5 F( k! L+ B* |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! W3 z% N& W4 |9 E' `% JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# o2 R) I* R; D4 `* y
MCASP_RX_MODE_DMA);
1 J, t9 ?, y' N5 D) R kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 ~4 X% k7 K! M3 ]( C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, O- q6 E, x7 f# W5 _3 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' W. l8 D+ u2 M! n8 P" n5 X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% d3 q: J5 L) n( n* d* f& Q u' q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% k$ b7 e# M+ c6 L% I& @* O9 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# |2 ?4 x7 _9 a8 d% Q" A4 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. q0 y3 L/ k) |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) |; C% q8 }2 h- T2 F. s! S; fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) R3 y9 p+ w+ P: v- v
0x00, 0xFF); /* configure the clock for transmitter */) k3 K" M t7 u6 J1 x% D" k. V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; J# B' }3 d3 n$ n) I, Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , H& l k' U3 z; y3 J& V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: A3 Y: N9 b* j: f
0x00, 0xFF);
1 z) T, w1 p5 w. {) F
; x% b, u" K3 t4 a/* Enable synchronization of RX and TX sections */
3 ^+ I5 ^* [. O9 G, c# U; G2 O4 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 v7 H1 k/ ]* J3 V) i0 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, w3 g" \( _8 |7 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 @, w! V7 Y- N) V8 ^
** Set the serializers, Currently only one serializer is set as. |; c# A, t- ]( Z
** transmitter and one serializer as receiver.
# Q2 {( E8 p9 |*/# B$ P' \& K$ P4 n. p4 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- J2 D) M$ k- O, T2 Z2 i1 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# ?2 g! V( A6 m0 X6 `% M** Configure the McASP pins 1 m; n" }: n1 M3 T7 M
** Input - Frame Sync, Clock and Serializer Rx+ E0 m/ S6 y8 }# T7 ^ d5 R
** Output - Serializer Tx is connected to the input of the codec
( k2 Z+ Y1 S9 \0 D( V8 b*/' q# C% E5 \6 O2 k9 u p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& T! k9 n% q) `3 a7 F& ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# i% w2 d, l0 wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* Q( i+ x/ I1 Z \ \: Y+ b* k- ~| MCASP_PIN_ACLKX
! g, T6 y7 Z z( f5 z/ V9 X| MCASP_PIN_AHCLKX
2 \" ~( g# b& P) N! M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// k9 } g8 K3 y& D- b: S. ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 @! J, a# H. Q3 R# g| MCASP_TX_CLKFAIL
/ R5 Y) Z5 Z7 [9 b9 n' y& `| MCASP_TX_SYNCERROR/ m5 d- A9 U8 l$ D0 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % _- a( p7 g1 K( i' x
| MCASP_RX_CLKFAIL
8 @: ^* W* }6 `$ o| MCASP_RX_SYNCERROR
- G, t, v' O, ]- Y. u8 C' D| MCASP_RX_OVERRUN);
3 @9 d4 R1 {6 P} static void I2SDataTxRxActivate(void)
' k |/ ^: \; Z% `! N* X+ j& u{
# q9 M5 r) Z3 O3 v8 f+ s/* Start the clocks */
5 l( d" I+ u) u# C7 c. k% XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) K; A8 B6 c+ c8 VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; n% d( X% o PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& r0 i V7 Q) h8 P9 R4 BEDMA3_TRIG_MODE_EVENT);+ U# v! }4 R. J6 A; k2 r; i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 F& s- W& ?- g1 q1 dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, g$ H! O7 I, x+ {/ _, w, Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 m+ Q' K/ } X: {+ m" K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ U- h3 g K. b1 K" W6 \# g. owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 H7 z3 C2 ^4 s. ?# j$ NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 \0 h/ {, n/ V! a! ]$ [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ c$ z, P& m6 `) }' k' c}
: Y( Q# S5 d* E3 T& v5 D. O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 {: b2 A: A% ]+ A
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