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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 i0 S; G7 Y$ j5 u" Zinput mcasp_ahclkx,
- x; F4 }" K- p8 L9 A. Hinput mcasp_aclkx,: b) g2 c& \$ A# V
input axr0,
7 E1 `) G6 ^! S9 ^9 l3 [
5 @! g; ]+ [5 a9 uoutput mcasp_afsr,
% Y7 g! ~$ F! p2 e2 \9 moutput mcasp_ahclkr,
# H) g, Q% T' ?3 [2 Y8 e9 h- N! D# Poutput mcasp_aclkr,3 |& o x2 @9 y5 T+ b
output axr1,
' `- U" `) v8 W( [* @$ }$ a assign mcasp_afsr = mcasp_afsx;4 I+ k; n+ P2 V3 H2 f
assign mcasp_aclkr = mcasp_aclkx;# L) `7 Y9 @ b: X3 `1 y( m4 X
assign mcasp_ahclkr = mcasp_ahclkx;! q: y4 [: `2 J. [2 x: Y; L
assign axr1 = axr0;
+ A6 f3 O7 r" Q- _* R! ^
8 Z: _3 d# @/ ?; D/ ?# @. O* d( H- W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # |; p3 q" `0 J( k \
static void McASPI2SConfigure(void)5 E+ `) z# f/ _
{
6 Q# H, L$ B" `) @ _& FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! w# i+ `- @# C# uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ ?) E( U) A; e& v$ Q4 _: k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 W2 Q5 B& I' V- ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 Z. r) q$ l5 z5 t, J/ b4 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 A1 H( B# |% u7 o* f2 a
MCASP_RX_MODE_DMA);
; @! w+ P, n& `% x% b! CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ Y" R9 k" F2 c0 e8 t# m+ {2 A1 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# y# V" W/ V$ E: j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % c; v# `8 e4 }2 |: [4 K5 s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. g$ f" F k3 O R4 G# D( B! u ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 h2 i4 ]! ^$ n' K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 j( X$ Y7 R9 x9 E" X+ FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. E7 k. g1 j+ g: A2 D. h$ d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ }2 p0 w" i# D; z7 ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: \2 d5 f. l6 S' p9 v% V9 i0x00, 0xFF); /* configure the clock for transmitter */
& V H9 r+ {# x2 h2 sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- H9 d0 F2 r0 H: `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . o2 m- t" r( q0 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ K" Y! Q! n: M1 [0x00, 0xFF);" {( e- B U( C; k, I' Q
# l3 E# w$ P: ?/* Enable synchronization of RX and TX sections */
/ R" n" A: W6 i$ X) FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- s3 N6 X* O) |) v8 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 g% l4 n4 m' ^- M2 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: s/ a- D/ G: Z( M
** Set the serializers, Currently only one serializer is set as
d! I" c( p, T! ]- k+ O; X% d** transmitter and one serializer as receiver.- X4 B- I3 O. M7 g! |" t/ G
*/0 ~6 J% G/ l6 U7 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 V( e8 X* W# C5 bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 l7 c, i5 L) v$ _8 e9 g** Configure the McASP pins 5 V! o( n2 f- b$ y; L7 e* p
** Input - Frame Sync, Clock and Serializer Rx( r6 m; U: e8 A# @0 F, \
** Output - Serializer Tx is connected to the input of the codec
, X0 @4 z) y$ n) R, E, U5 v*/
( v2 H0 o& ^( y0 F7 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 h4 Q/ ?8 q+ j' p) C/ [- m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# d6 _) B/ A+ O! r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. t7 X7 }0 g8 g/ n
| MCASP_PIN_ACLKX
. F( |1 t5 `3 b6 A S0 b| MCASP_PIN_AHCLKX
5 A% F/ B% _' j4 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: w. z# [! ^5 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) C% m" R9 W% \0 P% z7 r1 f2 K
| MCASP_TX_CLKFAIL
! E2 r% ]$ a1 ~! \( K H2 z| MCASP_TX_SYNCERROR
/ e/ A w# j) [, V+ ~: H9 o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . C9 X2 n( p# N
| MCASP_RX_CLKFAIL
" l' M8 u9 G8 T| MCASP_RX_SYNCERROR
; [4 X( j( B; J3 l! ]3 x8 J8 L3 ~| MCASP_RX_OVERRUN);+ M7 o2 g" z/ R1 n
} static void I2SDataTxRxActivate(void). {# w) S2 g( d% ~
{
) }5 [9 z/ [4 b5 \# J; o4 W/* Start the clocks */8 t6 x6 S2 i! J8 N8 I" g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' Q) A k" M* QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 z. v1 H4 F: J9 t+ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# E0 [. d+ _$ L/ z0 Z/ L, k
EDMA3_TRIG_MODE_EVENT);
" ^3 F: c0 `: O; QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " t) ^: `# K6 H/ ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: H* P) C0 [% Z3 ~0 j% PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 N' P7 b/ {+ \% G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// g: T5 y! y8 n" D- P! ~& G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 u4 U' v9 b% I: t% O# k6 I% W! KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ ?; L4 g" k2 O$ P9 Y+ QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 o* o3 ?3 @6 X6 l% [' ^* v1 T}
' E" j6 e6 S" I; S8 }% Q8 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 ^6 d) E7 o+ |! q% r; Z0 Z6 e
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