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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 y. ~! L7 k! r6 R
input mcasp_ahclkx,
7 q, \. b7 Y( o9 [input mcasp_aclkx,
; n( n8 Z/ t" i: x4 N- A, L( einput axr0,
) u% a/ k' h' K5 S* V: V4 }
. B- `! i9 D, joutput mcasp_afsr,
D* t9 P8 I6 O7 z- t5 J& ooutput mcasp_ahclkr,8 e/ G9 g. T U7 C
output mcasp_aclkr,
, K3 F# n+ k3 y0 f7 P( Coutput axr1,! X7 g. ~3 f( b
assign mcasp_afsr = mcasp_afsx;! s, H" W, X$ E2 T, B+ G( B
assign mcasp_aclkr = mcasp_aclkx;
6 l" V5 f! N, @0 z. Q: `' w) \assign mcasp_ahclkr = mcasp_ahclkx;( Q2 g0 n4 J0 m1 u( n
assign axr1 = axr0; & o/ g4 H0 b- L8 S
* @) |0 p: r6 e$ D) H5 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' c6 g# \ c# j8 Y* y
static void McASPI2SConfigure(void)
% |- `7 D3 Q! I- [1 w{9 [9 H6 w$ v7 j( t* M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 D+ j2 z3 Y( a N A0 v# wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" \- `) D& u d$ F4 H3 D' t* z1 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ D$ S9 v N% n j$ o3 QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 B. Q% x) a; Y8 S+ X' Y) R3 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
B! J) w* e0 G0 M- U% WMCASP_RX_MODE_DMA);- V- X' m7 h! m9 ]( q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ b: x2 Q. i( z0 {; ?9 }8 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 ~, T2 b5 c+ bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" T; R" A4 E. F* ~5 h; N3 c# iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( H3 B7 Y* L( y% J4 V$ H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* P; d: s: e2 ]& SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: W8 Y/ ~5 I* q, [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); v- U# n) o( k, v/ S& e3 b. G0 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 p1 i; O. s8 J% k Q; wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ `# g' w( S5 U# X' s0x00, 0xFF); /* configure the clock for transmitter */
! b: n5 }; z$ E+ [/ j- P5 a/ kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ D+ R- R! `5 D0 T2 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % o0 d" U0 Z. Y( ^( P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 Y& j% _' L* b+ K& Y
0x00, 0xFF);. c. k3 i c% b# M5 G
1 @9 i5 f6 ]$ v$ a/ P
/* Enable synchronization of RX and TX sections */
$ z- W/ i# x% r$ m! J# Y, T6 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; o P5 d8 B" L$ N7 Q8 yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 I2 z# Q+ J# E" H1 i( d' g0 u [7 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% D! D& P' @- }! Q' e$ J% ]** Set the serializers, Currently only one serializer is set as8 J) G7 S; b+ Y; c6 q- W
** transmitter and one serializer as receiver.
. Y, \. @+ \3 S# w. J*/
8 R9 p" f0 H) H7 ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; E* c/ G+ M; s% bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 I( |0 g8 ?5 }, `+ D U- A** Configure the McASP pins 4 B& K- H6 F7 V5 d
** Input - Frame Sync, Clock and Serializer Rx/ L* I+ u3 ~- U# ]& c7 v
** Output - Serializer Tx is connected to the input of the codec
6 w" E- Y" V1 {( H. `" B+ R*/
9 v& ]0 h3 D' VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# W) o+ ]3 p" a) A5 u( q, _3 g, SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' ~8 }1 d t8 _. Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, K& B6 M$ ]6 e% O
| MCASP_PIN_ACLKX6 }; d& C3 m/ n, l Z0 ?; `
| MCASP_PIN_AHCLKX
* y3 a- |' y0 P C' i' d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# n1 D% {4 O; B& I$ F. ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" K; s# p' X8 z" P| MCASP_TX_CLKFAIL : |' A# M6 l! c- ?* B( w; y' x
| MCASP_TX_SYNCERROR
; o- U9 m: `8 G* \6 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 ^4 a/ P# x( S" g! F0 x
| MCASP_RX_CLKFAIL3 _, B# Y6 U, ]. Z# a1 r- J" o9 `
| MCASP_RX_SYNCERROR ; Y" Q: {5 }5 Y; ]4 h U
| MCASP_RX_OVERRUN);
) t; T4 l7 e' ~1 x2 a# X' ^$ C} static void I2SDataTxRxActivate(void)& p+ U1 d5 o; q/ D6 N9 U
{
. \; _: V' W- O- \9 W9 m/* Start the clocks */
! m+ W* M# o& C/ ~+ B% s- a; vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* ]! o& r3 v2 O8 Y, a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, [6 a, i0 X, H j& P( h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 H' Z2 _- H f8 J% t2 F
EDMA3_TRIG_MODE_EVENT);) f4 T7 ~5 r+ d$ }0 d( d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ V: _6 d/ \& z/ r# U* x# pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# ]8 ]7 f4 ^% _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( ~. ?3 S$ [& ]: }3 R& n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ L) g( u, n- I( o6 H2 t) h, |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 M$ n" p$ Y+ ] a0 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 }8 C( m& N# q0 @# y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- H+ x. K4 {( w; s# w; Q3 H+ @# r}
9 O0 D0 x! B0 m8 `# Q" R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' }- W! p* y, l6 S6 a
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