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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 M. I& l0 g& H6 h) c$ W/ n) K2 zinput mcasp_ahclkx,
1 w; n* F) k0 ^6 [; ]6 { |input mcasp_aclkx,
5 m ~6 z- x$ R1 F! Jinput axr0,
% s: {+ f5 N2 R% |& B U4 g4 [5 n& j) x2 @3 @
output mcasp_afsr,2 a, r) \$ E: j2 b/ E9 m5 a
output mcasp_ahclkr,
/ w0 L$ r- @0 h8 U6 ~& `) i8 C0 d+ l _output mcasp_aclkr,
4 _5 q( Q3 o! X4 G# moutput axr1,# m: ?" a) O7 Y: y6 b& U
assign mcasp_afsr = mcasp_afsx;
' ^+ B- B+ X7 O1 Jassign mcasp_aclkr = mcasp_aclkx;
" u6 V1 s3 S/ c# n ?assign mcasp_ahclkr = mcasp_ahclkx;
8 p5 D: B% V0 r5 \% b+ ]$ Wassign axr1 = axr0; 9 z- N/ S3 n2 P A
+ A4 D6 R. R% u( m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 q) k1 p- d/ ?5 _1 L+ |
static void McASPI2SConfigure(void)
- x; ?' S9 p, _5 z{4 h; b( m8 T2 _% Y& u: R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* M: m* @) x: I/ vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) |8 h# | g$ ?- x+ ~$ wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ h9 {# ^# r2 }2 Z# wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 y: }5 I: U0 RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, U2 O6 U3 p2 ?MCASP_RX_MODE_DMA);
" Y+ p& G$ v* }8 G& Z! n/ p& DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
Q& c4 U7 z8 `/ ?* SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
A; ~" J8 P6 O, X; V8 O. @& ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( b% q5 _& B1 z" H) p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. M' Q8 g, [( A* F9 l$ [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : I; j, }4 y4 c; _( t6 q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 H1 I, q' P j0 QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' j, f$ e# h8 ~1 T; d0 T3 TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) c5 U6 K6 Y) @1 b4 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: }4 L8 b' L/ G
0x00, 0xFF); /* configure the clock for transmitter */, X5 M% t9 l3 L2 x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 ? e3 ~- R1 P$ z9 z0 t) N+ U) K) bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % Y# I: Y% M5 L+ H% b/ M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 ~& v; P' p1 n& C7 c6 A
0x00, 0xFF);
" K$ J8 R" @+ J6 {5 J. Z
0 v+ q" l3 `* X5 [. x0 m, ~/* Enable synchronization of RX and TX sections */ " A A& Q, E- h2 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& e. b$ B, H. G4 r; g$ r4 |# _; W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); L7 F9 }1 q! \2 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! y8 g6 C) u. [* q** Set the serializers, Currently only one serializer is set as
- j9 B) K6 M0 n6 ?2 U" H) g** transmitter and one serializer as receiver.- k$ E. q" b3 `; ~
*/
% P7 c4 ~/ p& D1 ^/ `: z3 k! }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ r( ]7 u0 C9 X5 P$ h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* F/ Q$ `6 P$ t. S1 q% U6 [** Configure the McASP pins
8 B- b) I0 ]( a) D# w3 v** Input - Frame Sync, Clock and Serializer Rx0 H0 ]' |% R% l8 y
** Output - Serializer Tx is connected to the input of the codec ' i3 ~, l2 l0 N; l) k9 n' v$ D
*/0 \! N0 O" R9 A& j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& \. a+ q) [& k. g6 L. U. HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; O9 {5 P- c4 a. z" X$ ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ e: E, K, k$ G) b. [
| MCASP_PIN_ACLKX& @7 |. g3 D; X0 x! _/ a
| MCASP_PIN_AHCLKX4 e$ P% X6 ^2 x' h' i ]9 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% j' e# \. W8 Y1 |& p+ QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ O9 Y* `1 p" n5 h, H9 G% d& H
| MCASP_TX_CLKFAIL # k+ G8 `. r2 A7 _8 m8 ]5 j
| MCASP_TX_SYNCERROR
. W4 W- B3 o3 j+ F8 z* a6 K3 t* s6 z# B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
P; e. J* C5 z* Q1 N# }/ S| MCASP_RX_CLKFAIL ^; Z5 [- \. w- [9 b
| MCASP_RX_SYNCERROR ; c! F' {, k0 t" u
| MCASP_RX_OVERRUN);8 A, O5 ~9 n( ^. v8 ~3 b
} static void I2SDataTxRxActivate(void)! \2 c/ h( H$ }$ [( i
{, i& @" a4 R* b* h, D
/* Start the clocks */5 J% [) u& R3 J0 U' k+ ?9 r/ B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 Z `& i, c8 X/ R: c: MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% ~( M3 B" k" r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ T2 i5 W- E2 P$ {" c1 |/ [EDMA3_TRIG_MODE_EVENT);
% w3 n( |- @7 O7 A7 t4 b$ E pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % p' W* u0 J2 k2 e# L( ]. c+ m" x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, a. p+ e$ c, N, k, u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" t) B" F/ t8 H4 F& T' kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: Y. E8 o9 Y% B! u/ ^8 Q' s4 ^; b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 Q: i5 f' E* e3 V# O" t. `8 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 t, {, E. f, RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 [4 ~1 |0 N+ |; F; m}
. L7 ` K& [& d1 ?- j' b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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