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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 A7 |- C; p+ g4 j$ m1 f0 n
input mcasp_ahclkx,' }7 V# J) P/ f' Y0 x# y$ @
input mcasp_aclkx,
1 m e5 T. q( q4 h; t- k+ B% dinput axr0,4 N) b* X3 U% X* T4 F5 L& I! v8 x
: `+ o( t) e) E7 c4 Boutput mcasp_afsr,
& x ]7 H3 l1 D/ j0 o0 F! F2 Q' b: coutput mcasp_ahclkr,& r: ?9 `) Z) I$ D& I6 d
output mcasp_aclkr,; v8 w- x- S# f7 _
output axr1,
6 E" q6 t9 \/ Q) W& R assign mcasp_afsr = mcasp_afsx;
& M* ]0 ]2 v4 a1 p. \3 e* Sassign mcasp_aclkr = mcasp_aclkx;
8 }8 X' ^3 @, g" W8 L9 m( hassign mcasp_ahclkr = mcasp_ahclkx;
+ [6 C% {% {4 dassign axr1 = axr0; + l @+ `1 C4 {9 ]. [
+ A6 z8 ?- @' u7 x- G; v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: A: B! M/ t6 M s# X: astatic void McASPI2SConfigure(void)7 J7 k0 ^1 v0 \ `9 i, W
{
2 u( z+ Y I0 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# Z* ?8 i) S$ k* W! uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ x; V8 ?4 R X' n8 M" p2 C' Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 b0 z5 N( b' _9 \! X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! a" |' C$ H/ x' \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, {! L9 v! w3 ^1 t) U4 p w
MCASP_RX_MODE_DMA);
# g* D) W2 b0 c* H2 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 r% m3 h' w2 C' M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 q$ U+ P3 {/ [8 w: |' v7 }& W; PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # ? `1 X: H6 h# d$ m/ s7 _) Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ j0 p, L2 p6 y1 A9 \7 G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: }- I8 F7 E! |# E9 Q$ L$ k$ x! vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# T: E7 L+ |9 L" `$ C1 q) U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: R+ h; \. s. T, S9 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + q- d H, Z3 f7 q2 W' A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! S5 b% b8 i0 H5 n0x00, 0xFF); /* configure the clock for transmitter */# t2 ~) x% T9 i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 _# w/ H5 Y( x" D8 N" Y' e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 I7 m1 ?: n F9 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: @% N; ]) ]( g" l0x00, 0xFF);
( j8 D+ x% E# ~# F% Z3 k H% Z {. i B: t" {
/* Enable synchronization of RX and TX sections */
& f& F& ~# g) i3 Q SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 t \3 R: `0 Y% C) ^8 k0 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. t [; q' Q6 d1 R; @4 ]) F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( R8 t7 M( b8 i** Set the serializers, Currently only one serializer is set as* \! m3 N# t- u2 p; W
** transmitter and one serializer as receiver.
3 i. M4 {* F. A$ N z*/) Z' T% U" y+ P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* b9 H% S5 g+ }& a/ _9 M6 m1 }9 T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 R7 ]: W F: t# B) }4 E* j** Configure the McASP pins & w$ u p7 m. ^; U0 l- m
** Input - Frame Sync, Clock and Serializer Rx& u! v: F! x* p7 [8 H! H
** Output - Serializer Tx is connected to the input of the codec 0 h4 C w( P! m$ U
*/
) F& A/ v) v+ e- O9 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ c' t8 p% |% M7 f7 F( d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% M9 m$ F3 @: G6 @* H8 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 j8 k* _- q# Z% K9 \& L| MCASP_PIN_ACLKX
6 e1 c( f' n M/ n" P, @, d0 o2 E& N| MCASP_PIN_AHCLKX) Y7 g8 z4 S; Y, Q; L! _; x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ p8 q0 t N4 C) U. l; aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- @1 l; _" @5 n& @| MCASP_TX_CLKFAIL
* \( J( C5 ^; s( R' Z| MCASP_TX_SYNCERROR% f' S9 G( V$ b6 h' ?' Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 y3 @3 e7 M0 f4 C
| MCASP_RX_CLKFAIL7 C4 E! w5 F7 f9 R
| MCASP_RX_SYNCERROR + x: ~, m0 @& ]/ H i( q
| MCASP_RX_OVERRUN);: @* @" ^ z1 V4 a) W. K
} static void I2SDataTxRxActivate(void)
6 U- K! h5 _( C& ?" G{
! @9 T' x* r, [: B7 t/* Start the clocks */+ S1 f n# z; Z. l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 }+ Z) W- i4 ?+ m6 C* n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( @0 C. \ R" v# U( d* o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 U! L6 Q1 }2 O9 L ~4 [5 jEDMA3_TRIG_MODE_EVENT);
# y! V7 H/ I% u: n, R2 M% h7 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( F$ e0 b7 F7 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- m& E! U: j1 P3 {' A4 T% TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 b% U6 d4 E* N$ hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 _* [9 Y1 i9 i& w* {$ ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 g5 ^! G7 _& n z3 ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 K. u& v/ r( |! PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& n3 y$ k' Q- l, e9 l0 h+ n} ; `! ^% J9 o( \1 ^# A# b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . g% @. u6 J2 X. v4 o) g
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