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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' P3 N! k: w/ s( H
input mcasp_ahclkx,: _7 G8 H% x& ?. T* x/ |- [
input mcasp_aclkx,
( o( e5 X, u+ B, I; dinput axr0,( D3 A% u ^; R
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output mcasp_afsr,
; E' f# G) j! C* f0 A+ y$ }output mcasp_ahclkr,6 P4 ~% {, O; x* u, B
output mcasp_aclkr,
6 r' s: U) u& L- houtput axr1,; \# ?; M# m, a/ Z
assign mcasp_afsr = mcasp_afsx;# ^" p: S0 t% j( g$ v m
assign mcasp_aclkr = mcasp_aclkx;
. f/ H1 D6 r- Yassign mcasp_ahclkr = mcasp_ahclkx;( _0 f" m* ~+ j* H# u4 C
assign axr1 = axr0;
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9 r$ C: l t+ s6 C$ w' a( V: e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ]9 s5 m8 C$ K) M6 ?0 ]( \
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);; A8 P: X! }2 X3 l$ K; I; o" z, \4 \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 X( \9 B' R: ^2 Q: A; p$ uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 V. Q3 ]+ y5 f5 ~0 K5 p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& v# n) V7 j1 ~, ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) w! U4 y" X0 l# B I. @) d
MCASP_RX_MODE_DMA);/ Y' s( n( c ]9 S+ y6 s, N: i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 h$ m3 G# V$ Q; Q: q$ @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: ~4 z3 |* z6 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' \3 B# b( q/ r8 w, A! pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! W' o% c+ D, y/ ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" Y7 o+ A& O: W# wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! R& ?1 B& a7 X) @, G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) V& ]# I4 G7 _: R. `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( I! u7 _/ J$ s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ m# u2 m' [) Y. n( c0x00, 0xFF); /* configure the clock for transmitter */
5 `+ `9 e+ B# N/ J' y e0 F" P0 ?" LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ ^9 Z, m' [+ T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & J) X- O0 E; i6 M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, g G8 W A0 e) E2 g
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ 1 h$ B5 b9 z9 x( d) `# _9 B5 \3 p" ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) ?; u' e; {/ M2 V( c: ^; g n& l/ eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) W$ E- w) x d" Y- F1 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! \7 |' |: U9 f( v% g6 u3 I' Q
** Set the serializers, Currently only one serializer is set as" g% w2 ?2 J" O2 _8 I2 D6 s
** transmitter and one serializer as receiver.4 x4 A& \9 i; w. T' w
*/
3 r* I2 _. Q$ ]( m) R# z1 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 _2 x7 Z% l5 d e4 Z \! Q$ ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# x2 K- h6 i. v& \7 R; _3 _
** Configure the McASP pins
: K2 S; F$ [! v0 W- C** Input - Frame Sync, Clock and Serializer Rx5 \! M& Z1 S4 x0 ~; ?7 i2 i
** Output - Serializer Tx is connected to the input of the codec u: i! a" p3 `, ^: u# ?
*/* ~8 L5 c8 b- Z* j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% W' F+ ?. p. j8 V- U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- D3 U$ x0 J( ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) F& H& d4 ~% [) U, P| MCASP_PIN_ACLKX$ t8 D# N, u/ b
| MCASP_PIN_AHCLKX
- d5 d- E" C& P& L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 s$ F- b% ~, t2 z( s2 `+ N) O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ [* D; A* k2 z* g- i| MCASP_TX_CLKFAIL
: q3 y3 i1 p* N1 D7 D| MCASP_TX_SYNCERROR
* a1 ?5 B% {+ \( L9 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ r: O0 u5 K/ D! V8 o| MCASP_RX_CLKFAIL
7 _& t! I/ n1 G$ \% {6 Q. @| MCASP_RX_SYNCERROR
5 ]1 S3 h% E( b$ i9 u| MCASP_RX_OVERRUN);2 e$ P) x% I6 m9 M& j# M* K
} static void I2SDataTxRxActivate(void)
% [4 a! j6 Z) P+ {4 m; @# Z{) s" }- j% I# b5 i+ b2 x
/* Start the clocks */, ]. L1 Z) C1 f0 \' H( y( H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" ` n3 E: I9 J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( `9 U1 l9 A. b/ mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- b, [9 ?- ~- T E9 z
EDMA3_TRIG_MODE_EVENT);
6 r, W* s* N$ |& t5 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ A- w. D! x$ @/ h" C9 jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 D. g, ?3 v ~$ TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 B* w, L1 ?0 B; C2 f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- c9 m9 F) W5 G: u8 {* ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' u' G/ H' U' ]. c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. o, G6 N! B3 D" ~+ u( u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 k! x$ x$ [( x, \
}
! x: K& D0 }" r. [) f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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