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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 R5 v; Z' o, u# [
input mcasp_ahclkx,4 f+ X! U/ `" P, m- X
input mcasp_aclkx,0 T; ~. K, W- R* z
input axr0,
* C$ d5 J V* F( I2 k+ E2 r. a/ y+ ?8 w( b# \* {
output mcasp_afsr,: P: N! N$ ^/ Y+ f3 J8 R
output mcasp_ahclkr,
7 f I; |0 k# Y, s8 f5 H# Uoutput mcasp_aclkr,
0 ], y; `4 u( W& [( Loutput axr1,
1 J; g; S- X) f/ { assign mcasp_afsr = mcasp_afsx;
# e' d! ]/ x, g" N3 ~8 Xassign mcasp_aclkr = mcasp_aclkx;2 E; o1 k( ?0 Q" J6 h4 y% b
assign mcasp_ahclkr = mcasp_ahclkx;' R- c" T% \: E7 M* R: t
assign axr1 = axr0;
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% T2 v# { X6 y: e2 A6 a$ `: b3 ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : O6 P' }: ~2 V
static void McASPI2SConfigure(void)
& B$ i f; y/ J9 L: J4 Z{0 O3 b, `# E$ k7 M q$ D- w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 [1 Q }% f6 \& X" h$ `- @+ ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ A+ S0 Q$ N% N- P, p% U- ]1 x* D3 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 h* O$ r4 j7 y/ a3 J- ~7 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! o" j O# x9 N- t# qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 V% G0 r$ g' A" _+ B$ c: b& a
MCASP_RX_MODE_DMA);( V' I, D$ P5 S* y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 F' S, r# O3 c$ J( \$ _+ h! [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// {7 C3 n- J7 @: F0 t' S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: _1 M' Q0 ?" i% P- @7 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 s. P* ^ G' B' N, k. RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' [8 o0 M7 p8 [# d2 C# {! A- t8 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' g; ~ o! [/ K% ]# ~3 }( _( N3 X5 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. F9 K; Y0 W6 o+ N, Q# l' iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* H4 t& ^( l8 x5 l" |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- P. }4 F w7 J+ E
0x00, 0xFF); /* configure the clock for transmitter */
1 |1 I/ F. c6 q- j3 T7 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; p$ z: b4 j. {$ `' P& @: r' O2 ~1 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 @6 k j$ `, V- F# V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: ~1 \% D8 e( m- y% e' p0x00, 0xFF);7 k N: J' ?) `6 z. z- w
1 K% q4 g i2 N/ s$ k
/* Enable synchronization of RX and TX sections */ I6 Z& x3 r& r9 u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- `3 s4 |8 H/ M) W0 j' a1 F% H" T6 U9 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
u! O! {" o6 E/ m3 U MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, u. v6 Z% c& m+ Z0 Y+ @
** Set the serializers, Currently only one serializer is set as3 k$ @5 C. W9 U6 O+ ]
** transmitter and one serializer as receiver.
% ?: s- m; S T9 e( i7 r! ~2 J*/
& a- Y# W. }3 J3 ?3 C+ F. z) @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 e$ l( B+ u( M7 n# l" M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- J0 O' f- f, K4 l9 y4 ]. C" Q& d2 N
** Configure the McASP pins
( l0 w0 H {3 ^** Input - Frame Sync, Clock and Serializer Rx
7 U3 E, n6 t) H** Output - Serializer Tx is connected to the input of the codec
; P4 K5 b* \+ t1 N6 R* ?*/5 ^7 i9 j, b' v# e4 W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. u8 Q/ o) ?/ M7 s7 rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 K/ N5 s" h5 a- x6 r, i8 o: M: p/ m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. B8 a0 Y: i) k4 S6 |1 \
| MCASP_PIN_ACLKX/ `$ K; u. O0 x
| MCASP_PIN_AHCLKX+ ^- U$ Y5 p ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 G1 q0 ?( O- N2 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! q8 m- c4 Y; d z8 N( W4 P9 g$ g
| MCASP_TX_CLKFAIL * i# l) y b* ?* r+ @
| MCASP_TX_SYNCERROR% k7 @* D* J A* a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( s. h( i& @1 c* p! O1 x9 o* H# b& K
| MCASP_RX_CLKFAIL$ l7 O- ]8 t, j1 n! i
| MCASP_RX_SYNCERROR ( i; ?$ o* s, n) d2 S {
| MCASP_RX_OVERRUN);
7 g5 \- ~( L7 j& _3 @6 ?} static void I2SDataTxRxActivate(void)6 M; ~! |! H9 a* e# I! k: `
{
5 Q) S/ q* R. z) ~/* Start the clocks */$ s, ?& G* {# `$ J& e2 V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); F0 o- N' s8 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 C) D" i( z8 a) O6 t" Z+ {: x: x* ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: o7 h+ K; t: Y7 u1 o
EDMA3_TRIG_MODE_EVENT);
# T" H9 T7 ?! A+ G" PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 @' o/ g6 j- K1 S# K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" |6 D6 F# G$ ? z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 X! ^* Y- C& B) f# NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- O' K7 Y/ y0 U. p) f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 v6 d* ~" k3 F$ H$ P5 M: RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ^ K7 L9 u- e. G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 R; l/ _3 Z6 c- L3 M( I0 _5 y# x} 2 E! v8 n: }& U T. g J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) C& j- U- `$ @7 b
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