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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% ]' r. L7 ^. z" pinput mcasp_ahclkx," @9 s% e4 b/ U( J, Y
input mcasp_aclkx,
" p: f+ E! i& P* @input axr0,) P2 M# H5 X% c6 p9 y
8 d9 A d' \: s
output mcasp_afsr,' {9 ?( S6 S. p# S3 B
output mcasp_ahclkr,8 h, z9 A/ C- y# t$ e
output mcasp_aclkr,
9 r5 j5 i) Q: q- @5 @ s; {( youtput axr1,
% K, w' @* ^) q$ C assign mcasp_afsr = mcasp_afsx;
Z6 S& x. h9 o Fassign mcasp_aclkr = mcasp_aclkx;
% {2 I( ~) y$ t- J" F6 ]* |$ Cassign mcasp_ahclkr = mcasp_ahclkx;( n+ e+ P% \; F" \, u# r+ y
assign axr1 = axr0; ! J. A6 a' L7 t" r
) `* e$ z% E( O# E0 J m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 b) t) U4 a% r: x2 Sstatic void McASPI2SConfigure(void)1 U* C2 R' p$ R g2 W( {
{' g* o3 x' b+ e7 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. C5 V5 @0 b+ |5 |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) ?: Q9 a( e5 u9 `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; Q. c& X( Q! \* p8 a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' M; [" k* d; M- W, f9 J3 PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 k j! `" R' P; ^5 _& ~) A) C( XMCASP_RX_MODE_DMA);- m3 Z8 t, `6 B* j; V0 o9 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 y/ f' x+ v. L( R. K8 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 b- z( Q& M" X. f/ h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . j5 |$ a! e6 w7 c: W& Z6 B% `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, {( t- Z+ s% y7 k. X" Z, LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ^ n; I, }& uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ p+ K* T) U+ R5 @. B8 i$ lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# I1 G- i# J' y* N. d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' l( i( ~1 g& pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 k5 x3 r1 N" d9 P8 P. K5 f
0x00, 0xFF); /* configure the clock for transmitter */
k6 h( a! S( H1 M/ _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% X& z$ i1 i. F6 W) z3 C' kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( @& y' N* m( b' [) g* d0 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& Y5 L! i* \$ H2 {: Z0x00, 0xFF);4 j) J2 n# s4 s0 u2 t
S' j Y6 _6 c7 ~# r) i
/* Enable synchronization of RX and TX sections */ / p# u7 \) c. |- B! x& B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* H8 J3 B8 _% u* u D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. g' f c& o3 F$ Z! B$ i; `" x [0 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) _" ]( l4 c+ T** Set the serializers, Currently only one serializer is set as
3 b+ a* L# Z& t1 X1 ?** transmitter and one serializer as receiver.( y# C" x! G( e. y S: c
*/
2 a+ N+ z1 W* o" L J/ @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ l9 o; a A! T( ~: DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( h/ m& l. v2 R; t+ w
** Configure the McASP pins + m. U5 Q1 Y" C
** Input - Frame Sync, Clock and Serializer Rx; p. f: g6 u; a5 m! b" }
** Output - Serializer Tx is connected to the input of the codec
2 E0 g! W7 ?1 [/ R) Q" [*/
% n. q/ R5 R$ j h3 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
P, w& n0 s( n3 T1 E/ V8 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: P! c7 `" B* b2 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* h3 H( O% `" E1 ]% B
| MCASP_PIN_ACLKX5 g' Q3 I0 o0 k1 e/ B+ L
| MCASP_PIN_AHCLKX6 N- o. ^$ M$ |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 D3 w) ?1 M d: K5 h4 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ f) L) I1 X7 O3 |8 ~4 ?| MCASP_TX_CLKFAIL # {; u9 b i+ S" g& s& c& b) W' Z
| MCASP_TX_SYNCERROR" t9 \2 D5 j k4 z# Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: i6 ] d/ h% x+ n( G* l* V| MCASP_RX_CLKFAIL
# Z2 r# r* K" R5 r0 }( k' [6 _; M* f| MCASP_RX_SYNCERROR
6 v* o, ~: z& F- d- K. x| MCASP_RX_OVERRUN);
3 ]; L+ J$ z2 P2 T* {} static void I2SDataTxRxActivate(void): Y: D" Y) G4 f }2 Z7 _1 _
{6 n3 V B8 H4 z! k; s
/* Start the clocks */6 G) D. l: [. C8 [* I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. x1 Y9 Z' ]- j D3 i3 ~3 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 g* P- t1 A% W3 b0 A" p' {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; v$ y+ P9 f$ h4 D9 Z; @( e0 M
EDMA3_TRIG_MODE_EVENT);
$ F3 J& l5 Y2 [* h& Q. @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 y5 A7 Y1 t$ P0 C/ _& A/ oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' E+ z( v G8 k; q0 p+ }, i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; G. |& _# l5 d2 ^. J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) w1 x0 V' B: h% }, K! vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" x$ p- Z% M0 J. \* y2 g/ E; \7 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( x$ A4 }5 D& @% \4 }6 o) ^9 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 g3 |' X G. |( d& L" h8 ^9 u( G
} 1 C- ~! ~# I: \) s3 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 `& i/ o5 D3 c" V
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