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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! V2 P+ \" \9 R& binput mcasp_ahclkx,8 I3 l; v$ ~0 S$ Y) O8 ^ y# l! T
input mcasp_aclkx,
4 o/ f, _* V( p! T3 Binput axr0,
6 @% ]$ D7 @6 _ _" U, q1 U) \0 j2 S5 n+ n6 r
output mcasp_afsr,
1 a4 A, H1 O- u5 @+ xoutput mcasp_ahclkr,6 A6 r, u( |$ z1 u2 r7 x, d
output mcasp_aclkr,9 ~' E; H. c/ Q$ x' z% x. P _
output axr1,2 ~# m, i; o$ O5 h, C( Y0 ]8 l$ N
assign mcasp_afsr = mcasp_afsx;
t a! l9 |) {assign mcasp_aclkr = mcasp_aclkx; Z0 Z Q z3 g3 M
assign mcasp_ahclkr = mcasp_ahclkx;
/ d- U( s$ @* f$ y% B7 sassign axr1 = axr0; 0 \. B" n6 v! g, {" R8 {4 `
" J3 _6 e# {$ T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) o0 z! q T1 i, p& t
static void McASPI2SConfigure(void)% r9 ^9 X: i+ q+ f; `
{ p; k; {3 U1 A/ z* ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
m R1 G# |$ V. ], jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* d+ M E- F) TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- l3 M* F5 j. g- B7 l2 w7 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% j$ W+ o: p. r- _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& t1 R' B+ G( @' y
MCASP_RX_MODE_DMA);
; O& R8 p' X; o8 Z: D4 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& N8 i& C$ E3 R3 K8 HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; F/ @9 W& @2 o( J9 a- c% H" j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 `+ W N0 U( {. c( yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" v0 D. V6 `* h/ ]; FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , }4 T( s9 C5 H8 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ f% M2 h1 F# u2 p# L' ~- DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: z+ ]* [, D6 a* b1 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: z% [& G' i. i* r; u9 ^! bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 ?0 T, Y; y: l T. I+ X2 k0x00, 0xFF); /* configure the clock for transmitter */% o3 B- I7 x6 V4 [! L. { D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 L! U" I! u3 ^: {. U+ \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * |; ]% Y) n% N0 q2 C3 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* Z0 R3 K; T3 G( _+ m9 x5 ?* {
0x00, 0xFF);" v ?3 U) I: J$ Q8 Y
) x* @4 o% l X' L/* Enable synchronization of RX and TX sections */ % W( p8 D0 V) c6 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 g7 ~$ s% X4 Q4 m1 f3 Y9 ^* I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, x9 S: A* u* q; [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- t8 L; E3 u8 t }: D! O4 N
** Set the serializers, Currently only one serializer is set as
+ w. q1 @" e0 S* f$ Z/ w/ C5 h** transmitter and one serializer as receiver.
1 g- G7 @/ _/ }*/% A5 N% h9 D3 p% `0 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ j! P. _, U1 k" c. j6 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* F. L. s; l4 P+ c: i3 z
** Configure the McASP pins 4 B7 ^0 ~+ T% z1 R- {
** Input - Frame Sync, Clock and Serializer Rx
6 m% l! _% D0 {6 ], v** Output - Serializer Tx is connected to the input of the codec 3 X* _ q; b% c" G0 Z: g7 v
*/
1 t+ V0 x+ o, P7 N7 U- A; dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
F4 j' x% R) z# hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ u$ A) X* Q9 s% ?. S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 C; W" Y" v4 h0 N3 C& X| MCASP_PIN_ACLKX i3 `% g9 [( d( s& q* }# I" G
| MCASP_PIN_AHCLKX: _5 ^ |4 x: l1 X' s! g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' j5 Z# E9 H7 ~2 G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 C& L2 P7 h/ z8 A0 O1 i| MCASP_TX_CLKFAIL z9 q, m+ a2 O) c+ ~5 a
| MCASP_TX_SYNCERROR. m' q M% i) {) O/ I" x/ g8 G* k- I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 d7 K$ B8 M5 D, ]7 I2 B
| MCASP_RX_CLKFAIL2 x V) H- L. j2 J/ U% ?& M5 }
| MCASP_RX_SYNCERROR
6 c" c. h0 _0 z| MCASP_RX_OVERRUN);7 t( E2 {9 H+ s# V# j' {4 X
} static void I2SDataTxRxActivate(void)* D' P6 Q( T& C h4 E. ?+ k& X
{
! r5 j) p, f. R& ~8 K6 }/* Start the clocks */% T+ x& s3 k, i) e0 c; h3 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& O0 T# x' e) n, g6 {, r, |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 h6 h% J! `5 C1 X# z7 n8 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# n* K: A, x7 r* K
EDMA3_TRIG_MODE_EVENT);1 ~ k8 B( U7 q: |. b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 \+ H( e4 t( I& ]# _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 U2 R9 H$ N2 ?8 a$ T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 o: R% E# r+ x V/ {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 U: g1 W* e& a& f$ {' b$ X' x) ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! y, \% z( x" I1 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 E+ q# _1 B1 ^+ H5 E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ O5 J, D1 Q) O% I. d} i6 x5 ?3 B) B) S' S1 b! z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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