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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& }$ X' @" M0 Y
input mcasp_ahclkx,
7 m9 H% I X' i9 f8 K/ finput mcasp_aclkx,5 [ @0 u" \' O7 I1 N# B' b
input axr0,* m; x& Z: p" ~
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output mcasp_afsr,
$ r; [# Q) I/ n1 y) Uoutput mcasp_ahclkr,0 o% P" W% R: R7 {- o4 T5 T$ k: S
output mcasp_aclkr,- d3 W0 N5 L- k
output axr1,+ q# m4 g# {3 X8 v. {' [& s) C
assign mcasp_afsr = mcasp_afsx;
0 ~! O0 v) q0 d K' W% kassign mcasp_aclkr = mcasp_aclkx;- e1 r8 g2 R# ]
assign mcasp_ahclkr = mcasp_ahclkx;
x8 L: r! ^+ x" g+ Qassign axr1 = axr0;
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6 l" t2 @1 R& y/ p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" ~( p8 E8 v# D# h# b8 y/ s/ m- T2 t zstatic void McASPI2SConfigure(void) V7 K- y. x4 U9 Y+ G+ W
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. R2 R9 D4 S6 J5 [' CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- z) z; J4 O* c. w$ @" a5 _" ~( F7 U8 q% AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 _$ ]* |6 i9 L3 N# N, c# q, b7 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' u; r% a! P: S* m& G0 J% PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) Z3 d! I: t# Y7 e5 j2 nMCASP_RX_MODE_DMA);; x3 v" D3 P- T9 L+ w/ w0 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 x& X6 s+ @3 h- V/ V) L: P9 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! [0 ], v1 y( y, k5 T6 |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; a, `' i+ O2 c! w+ d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: x+ @* S; c) m. l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, Z) w& b) r3 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 l, ^! X8 H/ N8 ]1 M# S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; ^6 \6 d- i# z* Y2 @, BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' r( |9 A* y& _) I9 r; h# iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) o0 {) }2 F% ]0x00, 0xFF); /* configure the clock for transmitter */
1 V* {1 d J! G3 d/ o0 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- K4 t. [. D1 C# s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 k4 I7 L- T5 c; J8 `7 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 s8 A# I. N: o, r, D; y' X0 M
0x00, 0xFF);
s$ u3 h% h- R; e1 h7 a1 e$ }' P( o# G. J+ N) K4 d4 b
/* Enable synchronization of RX and TX sections */
: E' X. a! z8 G lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, M% g' G, W8 h) W& s. `- wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ R) C- t& j L- j. T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% T& Y R4 p# G
** Set the serializers, Currently only one serializer is set as
7 B( G% P9 j1 W W0 O** transmitter and one serializer as receiver.2 ^+ g" U; p1 E0 O
*/2 ~" v' m$ x8 I X) G3 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ G7 h$ U* F( r# V. S* U* ~9 o4 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 U& M) O3 R* X- m1 y8 H** Configure the McASP pins * u4 L8 j0 t- m$ w
** Input - Frame Sync, Clock and Serializer Rx& T+ M' |: _5 A; H) u5 T4 C6 k
** Output - Serializer Tx is connected to the input of the codec
- @7 U& g/ ?# i+ g*/6 w7 g3 |' h: Z' J1 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 q, L' M5 r6 s& [0 X T+ WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: F' K5 d3 o/ g& F6 x T% B3 P( d$ o. A. rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' q) D8 g9 Q* g" w+ I0 X
| MCASP_PIN_ACLKX8 q, n; I+ }$ g+ B
| MCASP_PIN_AHCLKX3 w1 f8 m$ X9 D( Q- z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' J) S/ q# ^/ QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& |0 b6 r* L' t' V| MCASP_TX_CLKFAIL
, y3 P( Z# ]; \* ~$ Z5 \| MCASP_TX_SYNCERROR/ X+ F2 k4 u; ]: D T5 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / s) H# J& T8 Y$ Q# U& `0 s
| MCASP_RX_CLKFAIL
' ^6 f6 k5 l: h/ A| MCASP_RX_SYNCERROR
4 a _0 B+ w6 J/ N| MCASP_RX_OVERRUN);6 b6 _( ]8 H2 P5 l
} static void I2SDataTxRxActivate(void)- f9 Q1 ~( k+ u2 D. W+ _! j8 }# b4 ~
{
/ u9 z" O+ F0 R, ?! O0 ^. u& P1 e* T/* Start the clocks */
7 h! d! J- H* V, [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 q* ]/ }3 C( N6 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) v1 w$ X/ X; m! J6 M2 W6 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% [% H1 J+ I8 a1 e! U# Z4 }EDMA3_TRIG_MODE_EVENT);
% j' j" Z n& s0 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / X* q: s& R4 x4 u0 ^$ B& r6 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* X. k: y$ q5 F/ N* aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ^# {2 _7 b0 ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. f. q1 J: E# J' O; ?, |( l& p9 f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ E. g9 u* f+ n; X3 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 g7 M% C% l$ ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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