|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 e2 N* z6 C: M& f2 S
input mcasp_ahclkx,
9 [" a/ w: _; x* T8 j" [* Zinput mcasp_aclkx,
9 O/ {' n# T- G' s& a p' {/ jinput axr0,% ~' Z8 H2 F) u- U
' n8 T& K. L& E" [" Ioutput mcasp_afsr,
8 \8 [: |- V* D2 joutput mcasp_ahclkr,( }" z/ O; b5 g% V4 |; w! V
output mcasp_aclkr,
. } f$ ~8 h& R4 woutput axr1,
( Z8 }( D+ _: \/ `, m, h assign mcasp_afsr = mcasp_afsx;" T9 i2 P. u2 l; d; P. C
assign mcasp_aclkr = mcasp_aclkx;: m0 l" T2 r: E0 F
assign mcasp_ahclkr = mcasp_ahclkx;& g9 i- g7 Y: g: n! S/ B
assign axr1 = axr0;
5 `' M( {! i% g- G
) B: h1 N* h. G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ h6 U& R( C, R# v, o
static void McASPI2SConfigure(void) m) c; K. ]' j9 N6 l
{
7 i$ j. k# M) a: c& z7 } OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ k9 K# I) L1 M, T9 Q. @6 ~. K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 o! W2 |$ Q+ ^. t: m* N/ Y/ ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ^+ h+ O- z' \, h' kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) F5 m0 ~4 B! i1 F1 V7 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 K/ e: U ]% m3 h9 f. x& z* ~. s
MCASP_RX_MODE_DMA);1 a) {8 Q% Z! N8 ?2 ?6 E. e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. o' r% U) `4 M0 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ E) T/ n9 X; g; T7 a, Y8 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 R( P# {2 f. p+ M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 M: u( [; d% \* Q& Y9 [9 \% TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 l. B* r) _. h$ \- z& B; dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- {: n4 q1 H/ S% V" N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; t( T' M/ P1 x0 {9 O0 Y" o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 X( D% {% t' `( t9 z, ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. I5 x) S6 g, k; @# _
0x00, 0xFF); /* configure the clock for transmitter */
* i3 _3 P, f' D8 x* yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
i7 f0 S' p2 ?$ y" bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 g. S6 p5 F5 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ @* C; T7 X; c% j0x00, 0xFF);
' O, G. {9 e+ Q q5 Y. }/ x! d0 K
% j+ Y8 L2 W$ f/* Enable synchronization of RX and TX sections */ - B6 B1 @; r: \. B) `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- T) Q6 x+ n, ~* tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% U+ `6 F$ y; Z. y1 f$ A: O0 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% m7 w; {% L W; C
** Set the serializers, Currently only one serializer is set as) R; ~: d+ V4 x% F/ Z
** transmitter and one serializer as receiver.# ?2 H5 v. D& e' _ o* {2 X
*/' U* g! Z4 D& x7 S4 D0 L9 s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, @4 t! u1 ~) n# Q" W& x) i5 w9 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* u- d3 N) S% P0 E% b** Configure the McASP pins
8 f# F7 d" Q+ \0 p% k5 v** Input - Frame Sync, Clock and Serializer Rx
i& @ P+ J: f4 F** Output - Serializer Tx is connected to the input of the codec & s) x$ F l# U
*/, w5 i* x: m7 m! X1 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" X. W" u1 D, t3 z- w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ A! ]7 t+ H, S) A' X, ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ I7 s. v! _$ S- x
| MCASP_PIN_ACLKX
: ? v1 s' _1 g+ p: ^| MCASP_PIN_AHCLKX
3 [* P/ y6 s; L6 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 [0 |* N/ h1 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 X, e5 w2 _. m/ X| MCASP_TX_CLKFAIL
& {( L4 L# |/ l: |) v| MCASP_TX_SYNCERROR
! n' V$ J; N% A9 @# E6 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 B7 w$ d5 ?; \+ l1 [
| MCASP_RX_CLKFAIL n" N- L; k# f+ Y
| MCASP_RX_SYNCERROR / N' t& h( g4 t% L% l* {
| MCASP_RX_OVERRUN);
2 k4 r5 z0 `5 O* _$ ]} static void I2SDataTxRxActivate(void), W# @) i1 _# o5 p
{
2 ~# s! i: F6 Z1 Y% v1 o/* Start the clocks */( C4 _! U) [; }* ] d7 p k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 t2 }! T. i6 w+ nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ S& {7 ^6 p6 L; Q! R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) `/ W6 h, U7 a) {9 WEDMA3_TRIG_MODE_EVENT);
8 P2 l/ o5 p. r# b2 u/ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; G/ F; c0 c& J3 d( a& y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 h5 u( U8 K3 s9 j# b# n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- B$ v" F! g6 f, W/ V1 ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- {* K" p5 P* E+ c6 e- i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( I; \) Q0 x- |# V1 u; hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: L: K# K2 `2 l, j3 Z, XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 V* Y R9 }5 `! E1 f: o
} # p+ I( w5 B- Q7 w5 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 a" h. e2 v- N9 \
|