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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 c; K% M+ n4 sinput mcasp_ahclkx,0 W [8 I3 x7 P. l8 h# @% j
input mcasp_aclkx,. k* w5 p* T, @0 {( p r; a
input axr0,
7 O3 N$ K# o; I4 V7 C
- ?, {& _4 i3 m8 moutput mcasp_afsr,$ j6 K* z: m2 X
output mcasp_ahclkr,
1 b( T( h& r3 o/ ]3 g; ?output mcasp_aclkr,% D1 ~6 |7 X1 A b" a- w
output axr1,2 y& }$ y4 s* L- t' P5 l4 s
assign mcasp_afsr = mcasp_afsx;; n( T7 @( B* L. E E+ b7 d
assign mcasp_aclkr = mcasp_aclkx;
" A |) J* A* z3 z: X, p2 P1 c6 kassign mcasp_ahclkr = mcasp_ahclkx;
+ B R" `* t' B2 {( B- d( Fassign axr1 = axr0; + e/ B% |: [* \- B
* ? o; I8 k8 x# j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- s7 h1 G4 o- w" k5 d& P1 ]. vstatic void McASPI2SConfigure(void)- F% G7 C# H$ q: `( H; I0 E
{
" T ]# L' c7 e, g8 K+ N( ?9 P- X9 }McASPRxReset(SOC_MCASP_0_CTRL_REGS);' @5 q6 x* n4 _! W/ T/ |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ R) p' g) P% J3 x: V @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 d% \' M$ G3 _; C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 B; Y0 a1 P; S- B7 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 l. b* D; o7 { Z( HMCASP_RX_MODE_DMA);
4 ]( n/ N8 A) \4 h& CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' j0 I( Z8 W# JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, Z' n) \2 X6 X- z% ^8 d( ? E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # }- G( z: j' P6 }4 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* d$ r; ?$ q, [# p1 V6 l* i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # P+ j$ C4 Z4 ?% u, |5 O5 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: j8 I6 d) d9 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 T7 g; T) t- O# ^* [! I7 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 ?+ y( c) h& R8 T7 L* K% v! r5 o: h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! f, `( Z1 t4 M: p4 A
0x00, 0xFF); /* configure the clock for transmitter */
9 r9 t. v8 M0 d+ NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ J7 v, M8 ^$ |& D2 D( s+ IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & w' k# A% |7 k6 I& t9 ?) e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ R' ~% i3 e: }8 Y$ E/ @: z0 N- R
0x00, 0xFF);
! G" [* B( P3 N, q
: E2 g& Q6 m( x& `4 [8 V" @/* Enable synchronization of RX and TX sections */
4 B4 x+ g' a: x6 |: @& l* iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- ?0 m& Y; m3 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% d. Z2 U" y2 m, Y2 H- @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 L8 H l; y, i! V: f- J: e( C6 j** Set the serializers, Currently only one serializer is set as2 _( e: B& g. Q/ L
** transmitter and one serializer as receiver.
. J; K2 }1 ]5 ]% J0 ^7 B0 p*/
3 P9 T e P2 G; u1 E, v2 F7 B+ kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; B2 o; _+ X) r" s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% h+ F8 k, g) x
** Configure the McASP pins
# {" `* a; a) o! A% n** Input - Frame Sync, Clock and Serializer Rx+ }% }9 I; X3 `9 s: ]
** Output - Serializer Tx is connected to the input of the codec
9 g9 ^0 r! u @; h*/. `5 ]: A5 e" b9 M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# s; S( h9 n/ |' PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; }, u Q3 L9 a1 O" j4 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ T& U- E9 ?; P5 Q
| MCASP_PIN_ACLKX+ x3 k9 j5 A, o3 N& U) }/ _
| MCASP_PIN_AHCLKX2 l# ?1 ?* A) i9 ~( c8 \4 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 i2 D) I% |/ [6 L$ M5 s$ F RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 X1 u/ b4 d( T |
| MCASP_TX_CLKFAIL
% p3 r. `& y9 C7 @4 e( Z" L! p| MCASP_TX_SYNCERROR
/ p/ l) V& \, L4 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 {7 T8 q J+ j9 i: h2 W| MCASP_RX_CLKFAIL u" S9 D) q& e
| MCASP_RX_SYNCERROR
9 d6 |: k; q# ] E| MCASP_RX_OVERRUN);
1 a9 w+ }0 l0 G% D} static void I2SDataTxRxActivate(void)
# R& Z- g# R4 S{8 }, |- M) G8 ^+ k
/* Start the clocks */5 C+ ~9 s: z. D. G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 b+ |- M4 ^% C" vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- s3 V1 I7 ^% s' x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, Q/ w5 M. D4 K* g% ~4 l6 tEDMA3_TRIG_MODE_EVENT);9 O$ _$ m$ ]) x6 U1 U% Y7 k- ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) k0 Y4 u: \/ ?- p2 ~0 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 T9 V3 K: m+ N3 N, I& k, j! J. x, n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. M* O" z% H3 g( e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! _1 o; b% ~ w# {* G _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' F% F8 C$ _7 T- h) `5 N2 H/ q/ PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( S$ Q( }1 c3 q+ Z. u; G8 ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; B) I ~9 J, O+ p1 T4 h}
& F4 u$ f" r& a0 v+ X! }* _; b8 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 [8 G) Z4 \2 T; Y
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