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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ Q7 E$ m; Y: _* \; n. M
input mcasp_ahclkx,
: f z/ E+ u+ b8 K" l$ Oinput mcasp_aclkx,
) n3 p" o- a) P0 N* J- ^# g) _input axr0,
. }/ {/ N. L" X( h
' }6 N! N% ^' @% y6 b1 T8 toutput mcasp_afsr,
+ a0 Y" S7 [- ?+ |6 eoutput mcasp_ahclkr,; I8 d1 L% b& L* r& P5 Q. X7 G/ o6 D
output mcasp_aclkr,
" N0 Y( m% m& @3 E4 [output axr1,, l6 G2 o- T9 W) z0 r/ l
assign mcasp_afsr = mcasp_afsx;) v4 P! o- D" i. r4 I3 Y2 ^5 }
assign mcasp_aclkr = mcasp_aclkx;" ~" y' V/ {; B) K3 D
assign mcasp_ahclkr = mcasp_ahclkx;
' ]" Q' c: L) {1 d7 {assign axr1 = axr0; 7 u$ T6 D4 x! o1 D' h7 H" V' a
- N$ C5 V" T2 j3 Y# t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( H4 Y3 f9 d+ R8 Estatic void McASPI2SConfigure(void)8 O+ w/ u9 s! k( }6 j
{
$ f: J s1 T7 w- N) }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ B. ^, n9 {0 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' C/ N# J9 e5 p. S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 S/ w2 ^0 j* j! `, M; g" p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 ], E' e$ x3 y0 f$ b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 |1 Y3 j' k+ K; E1 X$ O1 q
MCASP_RX_MODE_DMA);4 V. Q, E3 s6 ^( {) N8 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 i1 Z. ?+ a" o, `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 M" s" a- P% c4 }8 {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( n; c, j) M$ `2 h1 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 G+ |+ B8 j# z0 sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . t' i, M4 P+ D+ w: B$ ]9 r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 K4 T- S' j l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 f# _) W0 A- @0 O5 E* ]& L. V: g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / N! }0 d* A* n, \% [. x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( D5 F- [- Y& Y4 T$ b3 z7 Z: v9 z5 p
0x00, 0xFF); /* configure the clock for transmitter */
t/ e/ {4 C/ _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ { Z+ K/ a% R2 [) d$ ?) bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); R5 r3 \3 k1 s0 i8 N; ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% n2 A. _' k, h0x00, 0xFF);
; o0 l8 F4 x0 `( Q# x# w7 _6 y6 b: V6 u0 T+ t% K$ \' y: T
/* Enable synchronization of RX and TX sections */ 2 F9 t1 V: B; I8 a- W$ r1 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. o& h" h. P" w. i$ D0 j# W' G- O* W# E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- y2 L' G( q5 a7 O: {# zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. K' P8 @1 ?) [3 S** Set the serializers, Currently only one serializer is set as' N9 h( W& m' w$ T: V3 e# X& i7 ~
** transmitter and one serializer as receiver.- g* M( h" _; \; ?- o7 e- x
*/
/ e; K' v' E" h: u% i- YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 m1 S8 L% X( f3 t4 j1 B* V) @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" L/ K$ i0 F) Y% n$ w** Configure the McASP pins - w! c, o& O$ u3 V: p$ }
** Input - Frame Sync, Clock and Serializer Rx
$ j+ g5 H. }7 Y- Z4 N6 V** Output - Serializer Tx is connected to the input of the codec
( B O- t6 ?# j5 p) w. o! ^2 F*/$ M( a" v, ]7 Q' f' }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& n& Y8 Z; |6 ~5 L/ @$ |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; x* ?2 n5 K0 u' t; q) L4 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% x2 s' ^0 Z1 W3 {" L- g! P
| MCASP_PIN_ACLKX- k, R( j" G0 T' x
| MCASP_PIN_AHCLKX6 W/ d, u9 }# N* B2 Y+ r& I- `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 Y* _$ O+ d+ w LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 Y) v7 w1 Z# L; [. j| MCASP_TX_CLKFAIL 4 i3 k3 U- Q$ u. x/ Z# Z' g
| MCASP_TX_SYNCERROR [% G0 \; w4 e6 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( c1 r: h! T& V1 C8 Z# m| MCASP_RX_CLKFAIL
4 \' [( x2 O" O$ y$ x7 ?8 L( ?| MCASP_RX_SYNCERROR # B# y. P7 K5 K. X" e/ U$ Z
| MCASP_RX_OVERRUN);; H- C) w0 ]- t' ~1 s8 S6 @+ {
} static void I2SDataTxRxActivate(void)
( m/ B5 ]. N# O8 z# Y" {{+ S9 a# Y6 Y. @) R# Z' s
/* Start the clocks */
8 p9 V2 `! N: E% D0 |2 S+ f/ SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 R; ]' u4 D1 ^# k8 U* O9 aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 G) l" D3 P8 g. b3 V5 M/ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," s6 u6 m2 m7 m+ e: ?% k, O1 {+ r
EDMA3_TRIG_MODE_EVENT);- g) B) B3 L Y! f& C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ X) f! J; |& R8 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: u8 v6 D7 t) }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" N, D1 x6 `8 u7 I- J/ z4 t8 B& c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 M* e' k7 Y/ t9 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# C7 v- J& n: r p/ U$ w( b+ v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 j, K; w4 ^+ B+ V2 c% o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% G, o9 H$ l6 b# u& ^) i
} / J/ N# ^. @& D" s- V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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