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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; u' f* M0 M( q l8 v
input mcasp_ahclkx,
. s) J4 G# n Q+ w. q' ]: hinput mcasp_aclkx,$ @% J9 J9 W+ N; Q" z
input axr0,
- A) a0 M& Q6 S# s! G3 T" d b
( T9 x* x+ u4 p; S8 u: w" U! q1 I4 qoutput mcasp_afsr,
2 T# m. L! j1 Y, y% `* M6 ?output mcasp_ahclkr,* }$ ~. Q' ^- F( W3 C. R& I
output mcasp_aclkr,- E7 G' ]# E1 h4 F; {: `5 z2 l1 _
output axr1,
+ @: u5 H, A3 d# o assign mcasp_afsr = mcasp_afsx;8 l! f3 T& w- Y6 @# w" m$ G. T3 t2 Z
assign mcasp_aclkr = mcasp_aclkx;
9 [; P% [4 q: M$ iassign mcasp_ahclkr = mcasp_ahclkx;
! O" V/ \9 \( T6 O! Y. _5 v1 @& v+ ^assign axr1 = axr0;
* X! S: v8 x- d) f( t) Y' I4 m$ _7 n0 ^6 u8 @$ ]3 I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ v; j I# p+ M9 v( K: Ustatic void McASPI2SConfigure(void)
' a# b/ M7 M5 S6 @{$ Z: W' W$ u8 ~3 v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& d/ G; N7 h) h/ R1 {# Y: L* ~+ XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 r4 Z h h) [, A/ P$ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, ~/ X; o9 ~0 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' k6 g# E; z- R- [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; H( ?/ V1 y. {) r1 K7 ?; z$ p$ y- rMCASP_RX_MODE_DMA);4 g' v* r4 X: \/ `% S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ ~& P; Q0 G+ A& XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( H4 }" W5 t/ R3 O6 g9 [% F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 `% f! N, }9 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- ~- S' k: H% b0 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. P7 m R0 Z( {( mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' G) z$ ?8 X9 _! p" P- P; x0 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( C" Z( L) a1 X, J+ j% {3 a0 q1 \$ UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ [: F" C. |. ]3 x1 @% x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ Z# X3 x1 T' p( K, N+ q3 b0x00, 0xFF); /* configure the clock for transmitter */2 N: O' A: W: c1 w8 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 u* |7 I' D- L. M, w& ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' I5 P; e1 u" E7 kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) H3 D- U: S& i3 Q( P" P& K) S2 Q0x00, 0xFF);# ?/ B( j a% e1 u* ]+ |/ O9 F3 d
+ W! L* l8 ]. y3 e
/* Enable synchronization of RX and TX sections */ 8 L+ g5 V1 I5 l2 J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 y) b9 E5 n: E9 W- H) e& ~) ^3 C! CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: a) q0 p2 o, ^) F9 f, W1 A. F/ g$ aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: @$ L( {6 D6 p& t$ k( T** Set the serializers, Currently only one serializer is set as* U9 [% H. v9 K
** transmitter and one serializer as receiver.
q/ @: X/ B# ~' d' H4 Y3 h4 S, W*/7 D+ v* d7 n/ d3 E! Z6 k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 p( V. G" I7 p! \" T, C- ^$ KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 {; l, j- T1 [" Q; j# U/ m** Configure the McASP pins
1 m4 C3 p } c" q2 c** Input - Frame Sync, Clock and Serializer Rx
* Q* \+ u- S" C) L5 o** Output - Serializer Tx is connected to the input of the codec |1 }) ^+ m/ q2 W9 a# U
*/
' ]% n, v( ^, i( |1 Y; @. ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ H8 q3 ]- v- }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, Z7 ~0 ?8 I" N8 f# e8 b1 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 K- x8 w9 G+ I6 S. U% x- b
| MCASP_PIN_ACLKX
5 ^0 I( p; n3 }7 D| MCASP_PIN_AHCLKX" \+ p+ z$ z$ J& ~4 ~# o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, D. F% r3 {3 s% H, y3 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 l9 g1 J3 \( S7 y7 b$ K| MCASP_TX_CLKFAIL 1 Y: c6 P6 Q; G. I2 {
| MCASP_TX_SYNCERROR/ y+ ~1 I: {. g2 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . Y1 _+ u3 @; c6 d) f- j$ v( k, S# x& v
| MCASP_RX_CLKFAIL
" v& ^9 R6 [" v| MCASP_RX_SYNCERROR 9 |, ~( _$ ?0 C# K
| MCASP_RX_OVERRUN);
# Z6 }# f( I& D; k} static void I2SDataTxRxActivate(void)
_7 T9 k2 a" Z4 t- }* z$ O{
5 N3 O0 U3 Y% \( Y1 E: A: G5 Y) l/* Start the clocks */. ]0 p- K+ e: l7 M) H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' g7 ~; D8 F+ g# m, A( p+ UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& i( {" x6 g( E3 n; C; o7 Z" gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* k$ q( x7 z: O
EDMA3_TRIG_MODE_EVENT); V4 T: ?5 |% _$ M8 W3 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - X1 E- @& {: V! z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 V1 P8 Q9 `2 g# m) l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 ]; Z( I% O8 ]3 l6 k s" z: jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" X( L2 X7 L+ `+ ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 v9 Q# }) V' D# c2 j* U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 a( l- w3 T; R& s/ rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* ?* L( w! T* {5 p) l
}
4 H5 g# e+ G" Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 B; {5 Z. N G3 Q6 k* Y! W1 [: [
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