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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! {. w. r1 f! y& h/ R% h# J$ K
input mcasp_ahclkx,
' z- ?( @; P/ w1 P+ K0 }% Zinput mcasp_aclkx,$ B2 M2 N4 ~' h: _2 C
input axr0,# d3 c" { v# e2 W
9 a' Z m. L" e. X( w) D6 }, C
output mcasp_afsr,
2 N; v6 k1 V. @* aoutput mcasp_ahclkr,* b6 v. z+ ^. G: X3 }2 A
output mcasp_aclkr,
- E( k# \/ K" t) z* [7 @output axr1,# s/ K3 ^% {9 D& L
assign mcasp_afsr = mcasp_afsx;! _) ?* z( L; I) _9 M
assign mcasp_aclkr = mcasp_aclkx;, G* R* k: n$ p1 M' h& k. H l
assign mcasp_ahclkr = mcasp_ahclkx;& \& m* o3 \$ f2 z! {/ h- I
assign axr1 = axr0;
4 K, j8 D9 v( G
5 A! H% G9 o- j3 s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 q$ [% u( G% dstatic void McASPI2SConfigure(void)* i- W9 j) T4 D7 @2 h3 v: Q
{
( I6 G8 j z* z2 Q% S. pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' i# B5 p/ q$ l) }$ j% e4 \" O8 _% M8 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ y! I( O% {3 [$ w/ f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& Q3 r8 S" F- Z1 g- ]( J1 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( Q: n5 d I+ P+ k A: G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, r4 @, T/ K& v4 R
MCASP_RX_MODE_DMA);. K8 A5 V, Z. d: E& K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 V6 h2 ?3 @2 K/ H# }1 q- JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 e8 G7 _8 d- p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ?4 c9 D# Q/ X$ zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& ~# M' ?! }5 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 s5 f% S' B' y, t' w" [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) l Y$ i3 i: u; c0 W6 G8 o9 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. C! f# b* t Y7 R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( n+ D* W0 c1 l+ _/ d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. k, U" n I' X Q2 f$ u7 x- ^0x00, 0xFF); /* configure the clock for transmitter */; x' m8 P5 c' D/ p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 a+ v3 H# k" {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ m0 [: m" V# e+ ]" Z x% \8 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 @! |+ I3 N( D8 i. `
0x00, 0xFF);% ]$ U0 i: V; M8 h% @3 q
% `& s5 x" ?: \/ x( i# L
/* Enable synchronization of RX and TX sections */
" O, i# ~* W/ W6 E% j" U* GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* J- N6 S) G/ ?8 d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 Z% z8 u+ L# ^ @* N! b3 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ U* ], ]8 T; y; o& ~+ q6 z4 v
** Set the serializers, Currently only one serializer is set as, A. [; Y( B/ `* ?2 \9 j4 a' G
** transmitter and one serializer as receiver.
* P- Y7 [+ `9 P+ h*/
: b$ z) _6 A' w0 N/ \8 K* XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ \9 T2 }$ d$ {% `! C; x* m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) b R: p, I* x** Configure the McASP pins
8 ?& K( j; ^; { {1 U' j) V, F) p** Input - Frame Sync, Clock and Serializer Rx
' Y/ D* ?" g1 R2 V, u** Output - Serializer Tx is connected to the input of the codec - e( r; b$ m8 c" Z/ d
*/
% A1 P2 a+ h' q$ UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 g1 k- g) x9 z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 w0 s! S* r4 o* SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( g9 \$ D9 a0 ^; a S6 I4 b
| MCASP_PIN_ACLKX" [- p& k* N! L! J9 Q
| MCASP_PIN_AHCLKX
7 W7 J5 l7 R# \+ f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; E7 P: g2 Q$ M# a: \: v* G% v8 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& c% ?/ h8 T% B+ u% Q) x, e| MCASP_TX_CLKFAIL # m9 e9 K: {' d0 M# m8 a
| MCASP_TX_SYNCERROR
1 {) S* ?2 g9 ~) `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR j, r( \4 `/ m; U6 n( U7 z) W
| MCASP_RX_CLKFAIL
- N1 M- m, r& a9 \( w* n# O8 g4 i| MCASP_RX_SYNCERROR
: C2 i% N# C: t# I; ^1 |6 U& ?| MCASP_RX_OVERRUN); Y& u* G- {/ y# o( ~
} static void I2SDataTxRxActivate(void)
. P% [, H0 s/ s1 Z3 v! ?{" d6 F/ q+ _9 F! O) Q! Z, a: E9 [
/* Start the clocks */ `% G! {" M7 l, R2 A& {: ^3 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) K" P, \. G' D2 G1 b+ L! {& J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- N: ]5 |4 {. J. \2 D! ]% Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, d7 v/ [% L- y4 }8 `' Q8 k) ~: k
EDMA3_TRIG_MODE_EVENT);
, r7 }! B S! [) [+ l( bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 B% K" F$ N; R6 ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& N6 h; m5 v' }$ Z9 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 o* H1 J# Y q) j5 v7 Y% NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. H$ w# b+ L; e O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 M- J/ a9 w& }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) \0 f5 W$ S5 t9 p: r! o4 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 _) `* `0 r, D
}
0 N" m" g0 F: c! n3 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / z$ ?7 R+ n+ W8 O, z- ?3 ?# {
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