|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( e# h. p$ I0 b4 a' @; Ainput mcasp_ahclkx,
% m+ S; M9 C; _- Binput mcasp_aclkx,
- z& W1 e7 U8 W3 oinput axr0,
" C0 D' A# y; Z% ]; f, X, V% d9 N6 x. u* N \
output mcasp_afsr,: }+ E/ |/ {- D# o/ ]
output mcasp_ahclkr,
5 ^6 w9 ~8 C& |& K4 s+ H( {) Noutput mcasp_aclkr,- z" G7 s6 J6 G+ _6 H' Y/ C
output axr1,, w, w5 s6 |& z0 m
assign mcasp_afsr = mcasp_afsx;
0 e8 c9 r/ z1 s7 @4 V% u- rassign mcasp_aclkr = mcasp_aclkx;/ [; y, ~; ~% e. e" f
assign mcasp_ahclkr = mcasp_ahclkx;, V7 [/ N* c0 j9 _
assign axr1 = axr0; % `+ N/ n3 r9 Y& F% n8 F3 y7 H
* \6 c4 F8 I% y% u% J. C: `9 d2 \3 n7 Y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 k. p( z& ?3 j* y6 G0 b! X- estatic void McASPI2SConfigure(void)7 J& g2 C2 z3 k1 U5 f# T9 e/ l
{
5 a. C, T+ P0 R$ Z' yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 @# v* U* o) r$ d9 [9 I( nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) u( ~; N( m* b2 E. M3 Q' h6 s' o9 ?6 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( }/ \: y% a+ C; _# x5 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# {/ k% @. k) {& xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# k+ ]; q5 V8 J- C3 W! g; y, V
MCASP_RX_MODE_DMA);
( [6 y7 j* j) M- TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 E) y! S& D% \- X6 _) |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ L. y" t/ }: C9 q# K$ {7 N! w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! H+ e! Q5 ^; J# \' E) `4 j2 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: c" X) O& I6 d1 ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 V `0 O( }& g7 i" a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ c9 |8 _# X2 Z# A7 {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 \4 z4 f4 w$ [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; M* ?4 ?' Z* \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* O- a* `$ |# {& e8 z
0x00, 0xFF); /* configure the clock for transmitter */: z# C6 f- u2 a, n7 T) }6 {( x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 z. w9 s7 s" Y: Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. J3 `" Z9 Z ^- e' C& l' P+ bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ g j5 i8 ^" S% G: ]
0x00, 0xFF);; k6 g$ c$ W1 r7 t' K3 [/ S* s
. f" a8 U9 @9 S
/* Enable synchronization of RX and TX sections */
1 S* D* p6 {* XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" y( X: k y) n* `' a5 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Q4 R" ?4 d% oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% y* S- \$ w' r4 q( O/ [- w
** Set the serializers, Currently only one serializer is set as
( Y, {) i2 \0 s** transmitter and one serializer as receiver./ z, P# S/ _7 P% g8 U: n ?
*/
3 I8 C% s5 c! ]; P: P) _4 l/ _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: j4 Q1 @8 n/ x( C+ [/ c- W- A5 i# Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 O$ L+ O7 m6 b( {2 R
** Configure the McASP pins # o& h+ R5 R5 M7 B. l# j( x
** Input - Frame Sync, Clock and Serializer Rx
( |$ z4 D1 i/ |" k* [** Output - Serializer Tx is connected to the input of the codec
, o- k; w' q1 h- A. v4 v*/
( R" }" g6 ]6 H, m, q: l NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- [" Y& `6 T5 Z- m0 u* V' YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- R" G& a I8 s0 q2 n+ \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 M& ]3 v- T; ]9 x/ a0 O. j# n| MCASP_PIN_ACLKX) k. `7 O9 V8 J6 p3 C8 L9 y
| MCASP_PIN_AHCLKX
& n% B8 F! E) a: W/ O- o/ H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. x! q# E3 n0 y0 f5 m$ n* E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % P7 |* H3 Q! _! s% J" Y0 u
| MCASP_TX_CLKFAIL
! F. |9 A* x' {| MCASP_TX_SYNCERROR, t6 d8 R( q. W5 p1 Z, ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 X3 L( \# _& j* V| MCASP_RX_CLKFAIL; p( Q7 k4 E( H; q
| MCASP_RX_SYNCERROR ! f0 r) I' X/ q& h* ]0 E) E
| MCASP_RX_OVERRUN);' {' w- m1 g' ?* a- E: k
} static void I2SDataTxRxActivate(void)
' r+ J1 V5 |* \2 p7 S{
; \3 W6 F" g4 h* o& p" q/* Start the clocks */% k+ Y/ Y; J: U* r0 ]! `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: A9 B3 b- V6 H% F: p5 R) nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) D5 z: k9 T4 u. y) ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 l5 ~$ j1 t3 F- T- y0 ~/ z! [
EDMA3_TRIG_MODE_EVENT);
+ e. P/ F) E1 u0 l( y/ nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + @4 x, {4 v- I; [! P" e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 U8 _; m8 z2 } x' X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 A6 {4 K# W/ r" Y; vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ }5 o/ y7 l6 ^# C) e9 A! }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 W2 B: z! Y" A% `& s5 ?! O2 B, tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) w0 j7 h G \& R6 I1 K! R2 OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 b) S" g; \, M4 J9 j% m. ?
} 9 A' n" b6 e' T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 t5 S/ k) `8 d
|