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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( C8 [& f. D; v, e9 linput mcasp_ahclkx,' Q- c% `; r: K# c3 q k0 z
input mcasp_aclkx,2 D' D$ J+ A! P$ l7 a4 E4 D1 |: v2 \
input axr0,
4 q4 s/ c( R1 E/ N' c# S
0 P0 ~/ h6 L/ Goutput mcasp_afsr,
$ Y2 J+ h: l& ], M0 b- uoutput mcasp_ahclkr," E# }- U& Q* v0 C
output mcasp_aclkr,
" s/ R8 M0 [ f* ^; Routput axr1,
) h0 g6 i$ A& S7 d# a# g assign mcasp_afsr = mcasp_afsx;
$ T# Y( k9 H+ Y) j1 J& U. rassign mcasp_aclkr = mcasp_aclkx;
9 i, m; f( |: L o' Q6 c1 xassign mcasp_ahclkr = mcasp_ahclkx; q8 i8 Z5 s+ L8 ^% z
assign axr1 = axr0;
; ?( q" e, E3 x3 o% y
" ~# l0 j; f( V7 ] U( \' d! t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, U% M$ p) d% s) t; B; ~static void McASPI2SConfigure(void)) d( M* b- r/ j, g! u$ n- J c
{* c9 X. ]$ n& g, P: r' ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: _, Q8 E. m7 Q+ _* Q3 G8 G+ fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. A5 V8 l3 Q6 @" G4 v: h' S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 {) {* H# R1 T0 k4 n9 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" R# {' q* k) O; L5 l) P+ D% lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 r4 b( k# v, T$ ]8 B
MCASP_RX_MODE_DMA);9 Z+ A1 j: k/ P1 B: P6 F8 C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' f7 f% p4 n; R: R/ S/ x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& P" b/ N1 h- |; E( E/ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 W; i, _5 B" N; \" P7 I! ~( _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; t' `1 G* Z/ l; |2 k& _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 s4 t% `" M0 B5 y$ x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ y. \5 h; ^ g3 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 n: u) c; \7 v* H- r J- [) s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 d" t4 T5 u7 T2 o# |0 n0 TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; b4 U) G/ ^( I
0x00, 0xFF); /* configure the clock for transmitter */! ?; l/ W2 |/ |# a9 u9 l; a0 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ F% ^) |8 C+ [4 @9 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 A- E$ H L. }: Z! Y/ K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# ]; w1 F9 \7 f0x00, 0xFF);
" V' b! j x2 _# |0 d& M( m& X. Y8 H q* C' y. t, M/ y' l* v
/* Enable synchronization of RX and TX sections */
; S" x. @$ O) H; N# v3 X' YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- G' T9 r6 M! W6 c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* g) W; _1 y2 }( E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ @! D0 o6 W% W- a. M6 T2 I** Set the serializers, Currently only one serializer is set as/ p7 Q4 X/ o5 V6 R3 ~8 D
** transmitter and one serializer as receiver.
) A- L2 ~. @. x" l. b*/
G1 @6 o% x4 j4 {. hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 q% ]6 B& J. q. @4 p/ X% w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 H# c2 b7 W1 t t- A0 O8 t$ J** Configure the McASP pins
, \/ Q7 ?; P4 n& V** Input - Frame Sync, Clock and Serializer Rx
, K2 D' t6 _) d( u j** Output - Serializer Tx is connected to the input of the codec 0 V; f& l* b& F2 E0 ?8 X
*/
6 v( n0 D3 W/ V$ mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( y6 a* E, o/ m- |0 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" l; X4 m; u N$ `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 x% e ]5 C4 W- n1 q3 m0 p
| MCASP_PIN_ACLKX, S/ M- ?: _; G, c+ p
| MCASP_PIN_AHCLKX
1 B0 p9 G5 C7 B; Q! d. R6 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& y1 D% g& ]! j9 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + b1 c1 p" V T# m# M' D. p
| MCASP_TX_CLKFAIL " o) {" F6 w( `% D: p) Q
| MCASP_TX_SYNCERROR( Z' Z% g& ~" ?" J3 U6 N6 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ n4 d. _' _3 Q5 Z| MCASP_RX_CLKFAIL5 t, G( L, n3 R2 s3 W3 O e
| MCASP_RX_SYNCERROR
$ }/ _; S5 V% S6 j# p| MCASP_RX_OVERRUN);# r H& U Y& T6 {2 H
} static void I2SDataTxRxActivate(void)
; t# @/ y: T4 V) p6 v{
! v' u$ N0 S7 T7 X/* Start the clocks */
4 R- m# Q/ s9 ~4 L) r( gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: j- [7 [. k! e" q! jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. W# `' i. ?% b/ a& Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ t( c. j" D4 g6 O/ b' UEDMA3_TRIG_MODE_EVENT);' G7 u, [" K+ w' s# }5 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 h( G3 [) e& Z8 O6 l; b+ H! z8 C( H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: U g2 E$ N- W' B: E* ]: k! H* p5 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; A @' [$ q3 ?5 J. eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 t0 c5 m8 ]+ F( U( H% Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ P8 d5 V- i) U7 }( v4 n( `; _7 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ c. s1 T, U; T1 _3 \ j0 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 Z# ^( u+ b" t
}
4 S j q* w6 Q; {$ w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) _1 O: b# |5 Z$ i
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