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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# h' W9 T! L; s5 J. B8 o. a7 a: u1 o
input mcasp_ahclkx,) Q, g, K- `' R9 `! o7 A
input mcasp_aclkx,, ?& d7 O2 t2 U$ v: ^7 q
input axr0,0 z6 d2 \- ^9 p6 v6 R- @4 n
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output mcasp_afsr,) r6 i/ K9 C( R& j5 E% `: U- d
output mcasp_ahclkr,' ^6 D) h2 B5 X; X
output mcasp_aclkr,
; L! R: w6 s' houtput axr1,8 l+ J3 b0 m: C* ], U, L
assign mcasp_afsr = mcasp_afsx;. Z2 Z5 G. B1 m
assign mcasp_aclkr = mcasp_aclkx;3 b1 d0 W( o& h& A9 u9 }' B$ F- g
assign mcasp_ahclkr = mcasp_ahclkx;, \" _0 @/ Y3 Z& | }) A
assign axr1 = axr0;
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, N L9 h2 N; k2 w0 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / _% y* T4 l" ?7 ^% X. a/ ~# M" d
static void McASPI2SConfigure(void)5 p* n1 b0 G& H# U; D9 f2 F1 a
{9 d, m r9 _+ A3 K0 `! O; t' T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 H2 t7 ?3 \2 j$ P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: }9 j+ a+ h. l& p5 X6 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 {8 y! U# @4 \+ u* d5 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. e- g/ ^7 Y) V/ H1 P2 T4 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. g! T3 ?5 n: G
MCASP_RX_MODE_DMA);
$ e3 k6 x/ W* u" B- {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 U3 Z1 N. z Q3 g ^& o: qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- L% a$ Q2 Q b, G' e9 C* c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* B4 r. ]1 @' B3 c! DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# g. P0 M* e: u7 }) U: x/ Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# j; A4 V4 _# e+ y- p& W# U- E! ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. v% {2 J8 z+ u4 n+ Y4 E7 ?" F7 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" s/ d2 _8 G6 }0 A1 z0 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ }9 w% _0 `0 h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 K7 a* ?2 y6 K0x00, 0xFF); /* configure the clock for transmitter */
& x' I# B2 I1 ^, D FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 x6 W- n( U5 J+ S" }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& c O6 g# M/ U9 b- UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 C1 k( ^( X9 F% o' ~
0x00, 0xFF);8 K7 S) {$ V8 P" M% m+ T
4 T: a$ d; W% n, q5 U* T
/* Enable synchronization of RX and TX sections */ / e* n c: y2 m6 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ T" m/ w4 S$ K, z! yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' } a- b& j9 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 x$ o7 ]. D+ z% @; ?0 F. B! w: R** Set the serializers, Currently only one serializer is set as
+ P- q/ g, g, U3 Q** transmitter and one serializer as receiver.# U; p" Z/ h) q
*/; ]: H3 `) m' i+ L" V4 f( ]. W ~: \# e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* M+ ]; N0 g+ ~: I7 EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 p1 }' g9 K3 x& {
** Configure the McASP pins
* K/ e. d3 \( b4 h; M s** Input - Frame Sync, Clock and Serializer Rx
4 c' _% S- h; o- i; N** Output - Serializer Tx is connected to the input of the codec ! P+ F) \5 e) \3 v1 K! Q
*/
9 |! z( e$ H! a2 CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" }$ R6 S, o& C; c9 @" {0 b0 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ \% [( f9 e5 ~ X" I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ A& n0 ~, }3 Q4 V6 _
| MCASP_PIN_ACLKX
. c {* X8 ]- ?- j( ?5 {; p/ M' q| MCASP_PIN_AHCLKX! h' Q% k3 g' b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 p- U* v; n- V/ n. R9 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 ]% k/ ^* W0 j5 ~| MCASP_TX_CLKFAIL
0 X) V4 ^" J9 C- `8 p3 E2 @| MCASP_TX_SYNCERROR" c) L' G& \! W. K. \, r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( p. f+ X+ x# f
| MCASP_RX_CLKFAIL" {3 J9 \; f4 J6 W4 A, g
| MCASP_RX_SYNCERROR
, A. y0 Q% w$ ^- [# j| MCASP_RX_OVERRUN);
( X% U4 V8 _2 s+ w} static void I2SDataTxRxActivate(void)+ S5 n j' j! F
{' i9 h1 m: w- z* _2 R% g" |1 S
/* Start the clocks */( ], N/ q3 ?2 L; q8 Z5 }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& w" z$ B3 s9 P7 p) P0 g3 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# e! P7 I" u% p4 F2 Z- f8 s& W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
j# c) T" p* m4 oEDMA3_TRIG_MODE_EVENT);# E. r) q/ t8 I& Q1 b3 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) S: H% I" N* }# O xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 @! |1 R: b7 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 l ?& |# ^6 X: @$ }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, ~) w: i' X r) W! u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- C" W2 s2 |4 G5 w2 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 K V) \; n, v" |, I4 G8 z, OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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