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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ |) A9 u0 i$ T: e2 Qinput mcasp_ahclkx," n& Q$ M5 f8 |4 C6 |
input mcasp_aclkx, `2 K, g+ Q- Z1 H/ N
input axr0,2 j/ O7 [. k/ t3 O3 p: N: \
. ~: w! r9 j: X3 Joutput mcasp_afsr,
/ d+ c. I* d) N; O5 Y9 N& \output mcasp_ahclkr,
9 a6 H- k: m5 _. F+ a- S" O S) ]- houtput mcasp_aclkr,
! T3 B" g J7 f* M H) coutput axr1,0 B- w5 y+ X- D7 ~8 w
assign mcasp_afsr = mcasp_afsx;
# f9 E' N7 j3 c1 Z# Dassign mcasp_aclkr = mcasp_aclkx;% u1 w0 w9 q4 f+ O* B7 j0 u
assign mcasp_ahclkr = mcasp_ahclkx;
* S- ?, ?2 y( z- u) g5 \assign axr1 = axr0;
2 Y! I% u8 F3 J3 G* B7 {7 f, |6 t/ b# L' Z6 q; N3 E+ @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 |$ ^( Q# `( J6 u& D
static void McASPI2SConfigure(void)
0 v" {# U: ?' x# u* Z{5 n7 `# H. c% N R0 @( o9 l# O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 q4 Z( _! ` E9 E2 u' ~; x1 M1 [" S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 a, g, X# D0 U. ^6 v3 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" S; G: r( ?& _% W4 q# j5 r2 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, E; H( T2 f' o/ Q3 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 i& \4 Y" `* U) Q
MCASP_RX_MODE_DMA);! M* N$ x: Q A; L3 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 v/ H$ u' V5 B% t4 {8 n$ |' ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 W* }2 n8 B: F4 E$ _: O8 k, `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / L! J% D1 O2 l* I; W6 c4 j8 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) x+ G, B% h. @* o! c6 J! lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 r0 u+ m/ H4 T0 {: ?0 g3 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& i7 U) w; C L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 x( g3 d/ p4 I' Q1 n; R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' R9 q4 ?2 s, i8 T6 m# w1 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ R5 K' n* B/ [' @
0x00, 0xFF); /* configure the clock for transmitter */
' R7 D0 z. }1 A: y, k4 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 e2 S- M$ Q! `6 q+ D' fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 i% l. M$ p9 R/ h& b. j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, j% a' L5 `& }2 r) ^
0x00, 0xFF);
! T8 N9 r* I8 S+ q& v4 P2 {: o
y6 C& x6 g9 \% V( Q0 Y$ _/ q' _/* Enable synchronization of RX and TX sections */ _* K0 s c7 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& t% s# A) E$ [+ f3 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 S9 Z: v; G$ M* E; W; F- UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" s3 p( M! h0 B( B$ [: ]** Set the serializers, Currently only one serializer is set as
4 O3 ^/ G/ m8 R- b& p% ]& v** transmitter and one serializer as receiver.3 I. J; N2 h9 i# _; E0 w
*/
+ r: G2 r }5 ?( H4 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* r3 S% z6 p4 v) b- h# K Q0 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! u5 h* _! B3 j+ Y** Configure the McASP pins ( {0 \1 y; S1 P3 M, B
** Input - Frame Sync, Clock and Serializer Rx$ z; }; L# Y% j& F0 p
** Output - Serializer Tx is connected to the input of the codec ' `9 l: p* M0 ~$ _
*/( C- y, I; O/ |- \- G# N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& O! R' \5 Q8 j4 e6 ^* {4 ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: d' e" c( Y) a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- d# h' u# i$ J$ ~- X, M| MCASP_PIN_ACLKX% U$ A. d3 l+ U& f _5 ?9 O3 e
| MCASP_PIN_AHCLKX
% h. E! W, j. m8 e% _% H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! o. v7 I) t/ @" w% {: y5 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " q- a' `& O( K
| MCASP_TX_CLKFAIL
~' u8 s6 M+ B- e6 A' y| MCASP_TX_SYNCERROR: f/ M) H" Y3 I: [. E9 C" A! i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) o% j. R- c% m; _3 k5 M5 c| MCASP_RX_CLKFAIL
) v2 p+ k8 c7 \& ]0 G| MCASP_RX_SYNCERROR - I, I- L8 ~2 W- Q9 F* h5 ~$ a
| MCASP_RX_OVERRUN);
0 X" G/ S2 h% K) K3 u) b m} static void I2SDataTxRxActivate(void); U: l9 o8 G' ^2 j2 m8 }3 X3 k
{, W! d6 {; W _( Z. W
/* Start the clocks */0 d! f3 ?# A- D0 p Q Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 L8 T% W F% A* o) Z; u& [+ ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% y' F- `/ z3 m5 y6 `/ s X- R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 Q( k: r* m% ]* g* V6 S8 F G, R0 i
EDMA3_TRIG_MODE_EVENT);
* G. C# b8 D/ r1 c: ^; \ I' F+ b$ wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 v! s3 {' V. x# [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 c6 v, N& `, s- l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. Y1 O' z0 I1 X0 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 w) a4 ]& |% ~7 ], h" v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// N: a4 F2 t/ A1 z. [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 L4 O" w: d4 n" FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ B! K* a9 F" y$ T} % c; j( V" b" u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 f N) p4 a' \9 u" [8 h9 u' E
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