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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% k+ p9 z7 H9 _# \input mcasp_ahclkx,) j' x% z6 }4 N
input mcasp_aclkx,% Q; G. F& I6 Y4 a# n r
input axr0,* k, _' I5 k3 W7 A3 X
+ D! F9 d1 H# i$ |7 xoutput mcasp_afsr,
* }. ]$ J3 c2 R% w# d) {( S4 Routput mcasp_ahclkr,
, R3 E3 t0 M7 A) qoutput mcasp_aclkr,
6 m8 O4 e' E' }* j- Ooutput axr1,
\ G, O) E1 a" I5 m# V* k assign mcasp_afsr = mcasp_afsx; p* K+ }6 F/ @6 h4 I4 G' Z
assign mcasp_aclkr = mcasp_aclkx;
8 ?9 R4 [& F, Y9 o8 c1 q3 \; Tassign mcasp_ahclkr = mcasp_ahclkx;+ k) W1 v6 F; y/ I$ F. ]; h9 w3 j8 G
assign axr1 = axr0; 0 Q, }) I* s2 h
! f6 }* o- a/ P) X S/ B! f7 L) o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' W/ O H- i0 @, X
static void McASPI2SConfigure(void)& y5 d8 T; a; V
{
. Z* W u9 x; s+ |5 o: |9 M# C) W/ ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);; e5 L- ?5 P- @$ k4 E. ]8 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% ^, f+ t& t) R: {9 e$ A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' Q3 G( z# N, @2 _" rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ N+ W& R2 ?) ?9 t! I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! y- S& p: I6 h& kMCASP_RX_MODE_DMA);
& s0 ^. ` [9 o8 G- yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 C- M8 V4 F; N+ O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ h3 f3 ]; {/ B8 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' h: Y4 D5 b$ e0 g5 T, M/ j. \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 s d2 H! g& Z9 F0 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % S# V2 n& ]& J. ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# p0 i1 y# }+ d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ v; B) s8 V( G M$ IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , h( J2 `% k. K5 O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: U, T [7 t; k/ _) }# j
0x00, 0xFF); /* configure the clock for transmitter */5 |! `! q$ q* y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 N2 ?% o, G4 S' i% S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" |8 g2 Q; |( A% y) {8 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- @1 U, H4 K& ?; I. I: z( H5 T
0x00, 0xFF);3 i* d7 A& A! F9 t- N
! x4 S# e) P4 v/ v3 Q- W! m
/* Enable synchronization of RX and TX sections */
" k7 U7 {0 R1 _% f' iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
p' m y& m8 v; RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 P T$ g3 T8 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 K1 b- c: D8 g* Z/ b** Set the serializers, Currently only one serializer is set as
( {" ], C4 f! G( b: d** transmitter and one serializer as receiver.# M- B- x: F. o7 x; h/ V) T
*/
# F: [$ G2 `9 n7 G' XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! ` g. m7 } w, F$ yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; Q9 u- O( r2 O5 o/ E4 Y, g** Configure the McASP pins # c7 E4 B& B, s. q6 \; e9 \
** Input - Frame Sync, Clock and Serializer Rx
9 @0 w. D# J2 d" ~** Output - Serializer Tx is connected to the input of the codec 0 [3 V5 U3 m4 v' C5 |
*/8 _8 d% M" N9 K( W6 J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 [: F% P7 W2 U8 g1 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 @& T( _; k- Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 N8 e( K/ V; H- {/ k* Z| MCASP_PIN_ACLKX2 Y2 ~* k& O1 M
| MCASP_PIN_AHCLKX
0 W6 v }, j; V" @8 U; }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; ~ [# w3 |7 ~; l) d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " V. q% g3 W( M/ W( u, p) i
| MCASP_TX_CLKFAIL
1 F' h8 B2 e+ g8 T/ N3 X/ Z" L| MCASP_TX_SYNCERROR
7 P* a3 p5 c: ]0 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 {- w6 U( k" r' L| MCASP_RX_CLKFAIL
9 \- K. P% v& I| MCASP_RX_SYNCERROR * g7 C( Y7 ^4 b0 _0 @+ j6 N% E5 W
| MCASP_RX_OVERRUN);
% _- d0 c5 D4 o+ ?3 z} static void I2SDataTxRxActivate(void)4 P/ }& @9 t8 M6 N+ ?" q
{
l; a4 K" E6 F. I/* Start the clocks */
6 ]& n* `! M n- nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; Q9 C" C' c! X4 @4 r% o' u" Z8 @0 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 S1 e" [' X, I) w- G9 K9 G4 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! r. e8 [% Y0 ^
EDMA3_TRIG_MODE_EVENT);
! m* t6 x& N/ Z: a( fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) Y4 e J0 R) e [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 x2 U+ O9 w0 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, {! n& | d1 G) wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: y) |$ D" G$ R0 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. y) B; p3 C+ ]+ OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" d1 t$ {! y4 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 W n* q. ]/ h2 |& w$ h}
( f! D; P- j' b# N$ `8 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / ?. s" q0 a+ U# N& y8 v% L3 T
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