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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 d+ Z8 o9 Q3 |5 C* X5 R6 h; @
input mcasp_ahclkx,1 ?( L( R2 U% \
input mcasp_aclkx,
% ~; |% h: p H y+ Y, Yinput axr0,% R* t* D8 W; d3 _0 A
+ Q- r/ w9 g* ^/ u8 R# K8 _' T
output mcasp_afsr,
" `; j3 W4 x! noutput mcasp_ahclkr,
- R# P4 Z& w$ A6 Z' P1 poutput mcasp_aclkr,
+ P | J/ z* T6 S, t Y4 \output axr1,
. t- B4 q! k& s9 @( }. H% p" Y3 Q% } H assign mcasp_afsr = mcasp_afsx;' d, n V3 G$ {+ \) S2 R- S
assign mcasp_aclkr = mcasp_aclkx;
/ v* ~' F! `) V9 d% uassign mcasp_ahclkr = mcasp_ahclkx;" v3 b# P: p2 x, Y5 v
assign axr1 = axr0; 7 v) N1 b2 A" n' s0 X$ I" J
3 y& [) `. j/ L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: [8 n. A' w' X0 cstatic void McASPI2SConfigure(void)
6 c3 |) {. u3 l. L! D{- {+ l! {' T C3 s9 V& L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- Z7 `6 L( W% E% oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: W. e7 X$ k- x* d% v% n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' z. V# w; q& P6 U+ L+ {9 O* [- d* qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. `; l. G6 o; kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 y/ R8 m% B0 B" `* Z5 k5 r( f
MCASP_RX_MODE_DMA);* g, G* j+ s4 \' p$ w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ]# s5 m) x' D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* Z' _8 W6 G9 U+ T( w9 P3 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 O* x2 @& j) v& m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( n4 P; d* v6 J9 {1 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ F; S' K( W t$ {0 m mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' g" ]% s3 ]' N" pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: K( a9 y& y2 c) r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 c# [: g$ [! T8 H* ~% d0 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! U' h4 c+ P I' S( Y5 _ v/ J+ i
0x00, 0xFF); /* configure the clock for transmitter */
, d: x" P$ E8 q9 v) s! wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 S# Q7 [) C2 G6 [, Z% R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : h( m: o- Z/ J( ]) \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 p) a4 `/ `5 H, F- ^0x00, 0xFF);6 q& g- u! I2 P0 g2 s9 q. n8 S
/ i) I7 D3 `6 Z6 S( Q* K' M
/* Enable synchronization of RX and TX sections */
7 L+ S+ v' W* V2 i) mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' J5 N; S- r: y' R% Z/ Z& XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" _( L7 q f/ zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, w& `7 |5 l2 l# ?** Set the serializers, Currently only one serializer is set as$ t, l+ G9 J4 g! U5 D8 _0 _1 }
** transmitter and one serializer as receiver.
1 E7 ]9 j% e# c# B2 E*/
& l3 E! L' n7 ~7 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ n8 A! J2 T4 r% ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 ^- S: y0 S$ A4 x3 {** Configure the McASP pins
6 D5 B- ?$ y5 N** Input - Frame Sync, Clock and Serializer Rx
0 P8 Y) k0 |% t, |( Q& B/ @, i** Output - Serializer Tx is connected to the input of the codec 4 y4 p+ N: p+ V3 `9 ]
*/
9 Y8 g6 u4 `2 h/ v8 @9 y( x4 z' [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ o" V9 ~0 V7 T$ s, z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ H" W. z5 O/ q) GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 G A8 A4 h: g5 C( _
| MCASP_PIN_ACLKX
) y6 H3 P( {9 W; e6 u Y0 { j| MCASP_PIN_AHCLKX9 _) r% B4 U$ `3 K3 I3 {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 ^ v6 E, h. R2 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & i8 X8 m' @! a, I
| MCASP_TX_CLKFAIL
$ _* o' i1 v& J0 J& e0 ]| MCASP_TX_SYNCERROR7 [! ~0 s( I3 k7 S% c6 x# t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 P% M% [8 l* G+ }( q- T. d| MCASP_RX_CLKFAIL
) n# z+ e! o* _. U( D| MCASP_RX_SYNCERROR * ]9 W$ K) F& v; Q3 |
| MCASP_RX_OVERRUN);& X3 o* I/ J7 |4 F8 _9 `6 _
} static void I2SDataTxRxActivate(void)
1 W) z% q9 f5 q1 m' b& A{
. X: B0 W5 v/ C6 E& |/* Start the clocks */+ {' @& W- X, ?2 d+ j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: s1 y6 V( B) W* g. iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- U1 ~" ?( z, B/ P8 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ W, v" d4 b9 r: |' n+ A' [
EDMA3_TRIG_MODE_EVENT);# r0 m: ~- i1 \. [; T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ y1 |# F, e* s: T9 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 n8 K& s/ N2 k" H/ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 Q4 O ~* ^" ?4 N4 u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 t$ k' p9 K$ R' u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 c1 q' e# Q* k# \1 j4 y9 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 ?/ ?4 z4 ~ g yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 ?' C3 m6 Q! D1 o
} 1 q$ \* `/ Q/ p. N6 y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + U. I2 ^$ r( @2 x# L
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