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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; W: z; N% z! `
input mcasp_ahclkx,
. e: O, L$ i( D$ ?input mcasp_aclkx,
/ x* P' r) J. x+ P/ Rinput axr0,
9 T2 l" z+ m+ ^5 Z0 ]6 J! {! {6 x9 e" X% m6 f& b: V/ ?
output mcasp_afsr,. ~% g% p$ z! H& A
output mcasp_ahclkr,/ K9 i0 q F# d. m
output mcasp_aclkr,
+ u+ x p0 c; i+ A4 s; W6 }( @output axr1,
/ ~( {% [* P' m1 W1 v. K& | assign mcasp_afsr = mcasp_afsx;+ J, D. V1 w# S9 p3 m+ [
assign mcasp_aclkr = mcasp_aclkx;# c5 {, N6 \! h/ j! ?
assign mcasp_ahclkr = mcasp_ahclkx;9 Z% Q* I" F, u; ^( O, O
assign axr1 = axr0; , |4 ?0 B' E3 ^5 d
5 K+ b, _5 S X$ M8 v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
j# n7 a6 L. _5 G4 Pstatic void McASPI2SConfigure(void)* K7 s' R/ p( t- p- c
{8 _+ z0 f3 \6 L" s9 Q/ M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' _; G0 z0 D5 a1 |4 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. |; n( w6 j6 K. {# O+ }4 w$ BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 z4 W- {8 p0 [& \: v( N9 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 @6 e! i7 x) E' h/ x" ?- S, Z3 n; _1 MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ t) A: x6 L# n6 H
MCASP_RX_MODE_DMA);( g7 p2 y2 P6 [0 `" Q* `4 v4 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! b* B) v" |" E, C0 g! @8 R$ IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 P, P$ f5 e7 C" e; o$ {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / e5 `# U) C' D% P& F% R- B* k4 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' T4 Z- ~; l wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 ?4 ]1 M0 N6 X/ F. s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 E! ?9 Q( ?& q' [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 v: U' }6 T1 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, u" l; |/ I+ M# IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 H' W7 E; ?# i: k! z$ Q. s
0x00, 0xFF); /* configure the clock for transmitter */
e' J# h0 [+ SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& v; L9 X1 |4 S S6 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' Q& l+ U5 }0 b0 W/ g$ H) Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 t( j0 s& {2 _8 O" L4 Z- u' i0x00, 0xFF);. x! p( Y4 L/ k# d
* b+ d0 b/ b9 |0 \4 t0 N% z7 ~/* Enable synchronization of RX and TX sections */
/ K5 D( _5 s" [9 }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 w; E i) \: s l* _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% H6 Y( v$ U1 LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# r6 X6 q V+ H/ M; D: q5 g8 }9 z8 Y** Set the serializers, Currently only one serializer is set as
/ N) V( W" r0 e+ s+ M: u** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 ?$ k( _$ |+ s: u1 nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 x. v+ G; _5 t! i
** Configure the McASP pins
& l4 h. Z |$ P V/ s( g0 R** Input - Frame Sync, Clock and Serializer Rx
( s b/ ^4 M3 d& W6 m** Output - Serializer Tx is connected to the input of the codec
, P4 f( P# {" P7 u- g0 R3 I9 {*/
7 J" f# Z7 Y9 v" Y/ o b; d+ `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" ~* l" D; h% b- FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 v, o+ K% `* F4 NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 L( J: c- R( P. v5 E" T9 b| MCASP_PIN_ACLKX
, y7 ?2 M/ P4 V m) s: A| MCASP_PIN_AHCLKX- b& J: F, N; L0 N) n2 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 y6 f/ T- k- R; i& ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 c2 ^$ A; Z" H. j- ]7 q2 W
| MCASP_TX_CLKFAIL
; B% I6 x( X* t& V' s) Q6 ~: S| MCASP_TX_SYNCERROR/ J; H6 N3 G$ M* _- F. g1 e8 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( S8 _. Z, P* l
| MCASP_RX_CLKFAIL/ f ?3 J5 d& z; [- H/ J
| MCASP_RX_SYNCERROR
8 S$ m0 {( }* n4 t9 Y0 ^ i) F| MCASP_RX_OVERRUN);' p: ]* }2 @4 _ g! N
} static void I2SDataTxRxActivate(void)
/ ?5 V3 y* k+ C0 e8 m* @0 `9 C{# P: u% `4 t, v5 H4 Y5 f
/* Start the clocks */
5 C0 g- D6 c5 y3 d, h$ |/ nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, J, N+ _5 a% aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; r3 \& y9 n* d3 @" y: a0 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 U, M4 v# z4 B" L7 z \. I( {
EDMA3_TRIG_MODE_EVENT);
. ]* \( w I- |2 n6 {8 W( HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" }7 T$ R/ ?6 [; O) }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- e, n; b$ D; i, I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# X3 T% H& O; ]/ V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" s9 y% m& ]: x0 G! X+ u5 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% R1 s* y$ z2 S# l8 IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( _5 [, g- T' \; {. lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; J1 A5 T( w7 `/ E/ O}
0 {1 g$ l4 i+ l9 g5 a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 {& T& w3 p# C0 ~# C7 |: H
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