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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! p- R8 E9 } g0 V' d$ W1 p) K3 Ninput mcasp_ahclkx,
5 N6 D" P: k6 B! _3 O ?5 ginput mcasp_aclkx,7 L; z# i1 M, K" [8 ?7 Y
input axr0,4 X& G2 }, w9 U {. S9 Q# N& j
" x; H- w m: u& G( routput mcasp_afsr,/ e% M2 ? I+ Y3 b8 ~6 I( r
output mcasp_ahclkr,1 a7 Z" \) B+ Z9 v3 o
output mcasp_aclkr,
4 I( M- _) Q) aoutput axr1,; V, {4 {$ K# a7 S+ V& E% J
assign mcasp_afsr = mcasp_afsx;$ ~9 b8 H+ {* f5 U7 z3 w0 L2 p
assign mcasp_aclkr = mcasp_aclkx;) f# D8 F6 `4 A" s
assign mcasp_ahclkr = mcasp_ahclkx;
) ?! _4 X: ]$ e2 [$ J S5 l( Vassign axr1 = axr0; , X; s' K- w7 M2 M; Q; k2 T
+ Z3 p" h, G7 l0 [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 |4 N) y; \. D
static void McASPI2SConfigure(void)' X B. x, @ i0 u6 Q6 m: r
{
+ S# B6 `0 L) P6 E. Y( SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 ]) @8 p4 E9 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. B' v1 }9 s+ l' ?. _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% _+ T( J# Z; |! O5 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ k- b2 n4 O+ y# H6 K, W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- o$ v- ~$ F! K8 l( T
MCASP_RX_MODE_DMA);( u" D$ r5 z( a" H# @( N6 s" Q6 h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. _ y( C6 `5 s) O, p J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- O! |9 ~# A, ?% O& X9 R+ v4 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# y* U' }# _0 ~# MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
}1 {/ x/ {+ c2 S% L9 L' mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + {/ ~! W- Y$ E: e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" B5 D q6 Z1 D! j# z2 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 C- ~3 `6 W3 ^4 |- e R* n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 Q5 N; ^9 y" K$ [8 D2 d8 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( L# a3 w0 `( i
0x00, 0xFF); /* configure the clock for transmitter */
5 Z2 G9 }3 Z5 z5 N* qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% H( ^! r) G) K/ q/ r3 U( m! ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : T0 i: G" }* Z8 t4 {3 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ C, Z( w! t+ I$ D, |0 f9 R0x00, 0xFF);, T3 C5 b' |: w& v" G. l
% S" y, X! @7 c
/* Enable synchronization of RX and TX sections */ 8 y0 A/ }9 e3 h4 x" ^, G/ }2 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ h: _, N+ w4 c7 p4 w2 }3 V1 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: y8 y% i! `/ s2 G' I. AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# A- o9 {8 w5 d! Q5 q** Set the serializers, Currently only one serializer is set as
! m. S4 |, Q6 a8 _** transmitter and one serializer as receiver.1 g; M2 S! [9 y* l
*/+ w9 ]' _# X. n8 O k# C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- w2 i. U5 t9 O* |3 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* x8 h/ i8 H4 I
** Configure the McASP pins / P- w: M$ R# H. Z6 R
** Input - Frame Sync, Clock and Serializer Rx
$ k* F/ u; h. o* |+ E** Output - Serializer Tx is connected to the input of the codec
1 [" v" D; X, c1 R* X, e( ]*/2 Z& ~3 }: Z) U7 ], V/ B0 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 b5 u: L- ~, @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) s. _, l% M* E& G9 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 t" z! t, D. ~0 ?/ u' M4 y( L& r| MCASP_PIN_ACLKX( Q9 k: o0 _+ S5 r% K
| MCASP_PIN_AHCLKX
& P5 [4 e- Q- W+ o8 {9 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 O. S3 v& X6 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' P7 h( n. r1 }+ d| MCASP_TX_CLKFAIL
( e+ e f0 H0 K3 R' }0 d| MCASP_TX_SYNCERROR
9 J5 m2 @+ ~3 F4 s; _7 Y: M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . _* L9 w' D- z; ^/ X* m
| MCASP_RX_CLKFAIL1 o7 O+ U2 I* b4 C; y& C1 P! i
| MCASP_RX_SYNCERROR 6 [* h) ~# D# V5 J& ^% L' ^6 C
| MCASP_RX_OVERRUN);
, T9 c6 F' ~' L0 p" f} static void I2SDataTxRxActivate(void)# z; w. K. G" e7 l* I
{
5 r D5 `! k2 {7 `- h1 s- ^ Q/* Start the clocks */
8 Y( p- O( \' _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# g2 r7 C M; p/ E3 C$ o ~+ }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 U# {2 Z3 ?# i8 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% S3 L2 {$ K0 _+ j7 x4 @
EDMA3_TRIG_MODE_EVENT);, W- y$ F9 I) O1 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 K! z! ?# N. x, B5 K. t6 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 P) O0 Z9 \) _5 L- G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 L# f% s/ E; J! [: {9 bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- u f4 F: t0 O. Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 x) B4 J8 K5 I5 i/ C3 }3 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# g: K" H& n2 d) [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( _! J! W v: E. _} / r. x1 u- u$ ~0 H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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