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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 C) i9 h4 d- S) v' Q+ _
input mcasp_ahclkx,: k4 t: i: _+ a- c
input mcasp_aclkx,
- P" i6 l0 Y% {, |7 q% T1 w5 winput axr0,: f% T" X p4 \, s1 X
6 q+ Q0 U; ]1 M. t: ?) [( U1 ]' ?
output mcasp_afsr,
4 I3 K4 F& A' K+ W/ U* @4 soutput mcasp_ahclkr,
Z; o& j- X. t: N/ Q/ Koutput mcasp_aclkr,( |1 h; e; p: k4 n- h* p& W! G
output axr1,) y) L# U# W6 u
assign mcasp_afsr = mcasp_afsx;
" g' P& d# q5 i" O' E. r e6 Xassign mcasp_aclkr = mcasp_aclkx; _6 W9 G: }3 Y' e8 x" K
assign mcasp_ahclkr = mcasp_ahclkx;) Y7 ~* C" Y% @7 P/ r) Z+ A' h, _/ \9 r
assign axr1 = axr0;
9 \( c. p. u* _, B$ H5 S2 D2 ]6 s9 c9 [, T, t- o# j, I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 M7 Z" E% Y! y$ @( l8 M8 V
static void McASPI2SConfigure(void); ?* z" H% Y/ r7 @" c. n
{
0 ~# X. d) x- a: q6 @3 q# pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% J2 U$ _& J* Y# ]; i* a( y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 S# @2 U' z) i3 k4 J+ ^; `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! f0 ^) a2 I( \% [1 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
~1 q8 E& k z0 X7 R0 o& |+ ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 S9 f( c5 ^, h: J5 m- bMCASP_RX_MODE_DMA);7 f8 B" ~9 g$ s! h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' O3 |9 z. R; b/ \ K5 Z3 R+ sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% v/ p4 m! [7 Y4 ~, @/ l4 j+ ^, ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, ^- @& z+ [4 f1 N3 N$ aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- b; U4 [4 i3 x3 {: C" vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 ?0 @% x! m6 u9 A1 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. f9 a6 S/ i4 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( l( L+ q5 S# q3 Q9 M8 u d8 N$ XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, S5 v* N7 Y% X9 M5 E( MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- C) X, I: ?4 a- e
0x00, 0xFF); /* configure the clock for transmitter */2 J* d9 r; O# ~: {2 p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 U5 H( j9 e! X" P7 ?) }" G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& D- q* c+ {( c' B# f8 X0 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," N7 [8 K! ] O5 n1 y
0x00, 0xFF);
5 d! \0 y4 X5 k3 W/ C) `' u) V/ l9 j
/* Enable synchronization of RX and TX sections */
* r2 |9 I4 @2 L. B/ g+ D& B8 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- \7 e6 j1 w: }8 b' Z+ m* B0 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 T* I# @+ p" G9 N; L" I7 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 K+ Z1 ]; g' W& p
** Set the serializers, Currently only one serializer is set as
+ k3 ?# h: Y7 }9 G" t. \2 K** transmitter and one serializer as receiver.
) k8 F. `0 S. d" i1 N*/
7 U, C) q- v$ n# {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ e+ O8 D1 c( f2 y- N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ Q# e/ y5 r: m; e2 n2 B E2 p4 V** Configure the McASP pins * |0 `' K, L# Q8 r) Q
** Input - Frame Sync, Clock and Serializer Rx
4 D2 x4 f s$ V) a** Output - Serializer Tx is connected to the input of the codec
" _8 l+ R8 G& e*/
# M5 C( ^& l3 jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 m6 F; _1 v' b8 p" RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 h2 o7 L1 i P4 k, p- d7 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; T! `/ b. ~# S0 g
| MCASP_PIN_ACLKX r/ x s* t( W
| MCASP_PIN_AHCLKX
$ [% R( X/ m, J" x; @9 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. ?4 c/ Z6 n& m; z/ e9 p: aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( c. G2 ]1 v( Q+ @| MCASP_TX_CLKFAIL
0 H: `4 M! v1 c2 a| MCASP_TX_SYNCERROR
) K6 \" r; l) E2 F/ T) F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, N# L+ V# P: k6 x: }| MCASP_RX_CLKFAIL( s4 E, J5 y& a( N& D7 X
| MCASP_RX_SYNCERROR
+ V1 ~; @# v0 Q6 ]9 {| MCASP_RX_OVERRUN);0 d% t" z& G8 S# U( n! ?6 w! H
} static void I2SDataTxRxActivate(void)9 F& N- @" Z( V
{; P( i5 e4 [: P9 r5 D
/* Start the clocks */( b- E8 f. }. t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. i# S- |% x; c! [1 F3 j- S+ oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 A- Z* h0 i; C/ g% I) z8 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ Q# H E; b2 L" EEDMA3_TRIG_MODE_EVENT);
S! c% l% F4 z# @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# a4 J# z1 ^& ^3 k( s5 C' y. |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% {# w* F5 `5 v" q+ p* n5 K& T$ mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' u+ T1 n. I" \; R8 X* pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 ~9 U& v5 S1 ]2 v0 H2 M( [* y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 |) W8 N2 V" ?5 x# S. vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 R% n! x0 j ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) \3 J3 G3 {4 s
}
3 ]* Z7 V8 T+ D7 ^, V4 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. h5 o+ x* j4 P# d- S( _
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