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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ X! D2 G3 P4 R! yinput mcasp_ahclkx,
3 L a5 r4 ^' h1 Q9 e2 o5 B$ U) Sinput mcasp_aclkx,) W0 Z' B/ S: j) u9 u8 Y# D, i/ L4 }
input axr0,
* D& n* }8 ?; r: V! m1 {" @
. T2 b& C! L/ I- q9 Q0 `4 h0 loutput mcasp_afsr,
+ U$ ]' f1 k- _: z. {# Goutput mcasp_ahclkr,
# y; q4 i- f& |output mcasp_aclkr,6 J+ N7 N9 s Q8 y
output axr1,; a% k: k% y' k0 y4 j
assign mcasp_afsr = mcasp_afsx;' Q8 p7 T, M! b
assign mcasp_aclkr = mcasp_aclkx;
, p8 w9 q5 p; I. m( Oassign mcasp_ahclkr = mcasp_ahclkx;) S" z) c; @% r: `
assign axr1 = axr0; # x9 W1 `& E* L/ k- F
: @) o( ^# W3 j! l$ d$ w& M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: I( p" S; p3 T5 ~4 I( Ustatic void McASPI2SConfigure(void)5 H; k* p Y. U& Y
{
2 A- u# G5 N, L1 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 T! Y+ o( ?5 E- pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& j* g7 D4 k2 M/ ^1 ^- ^: |9 l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ z7 t/ X. P3 @( d4 b" F" ^* o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 y6 d1 u7 s# H% S4 }2 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 u* x: d( ]9 UMCASP_RX_MODE_DMA);+ b8 O D* [( r1 D ~! l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. n3 |2 Z2 E2 c) z5 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, W% j6 ]: m# c8 M6 n! m& |, U7 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - B. j" c6 ?' a9 s2 R* `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ M3 M! D& R& @/ [8 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) `1 R( t! H% x1 F8 A7 d, V3 I' KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* ^$ M: |) c9 ~ b; P9 J4 v, iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 B* s( m. N2 h# @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 I1 k/ p6 O& B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ }8 ?. U8 Y* u# i0x00, 0xFF); /* configure the clock for transmitter *// O: e3 C' [3 _' D/ g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; m2 C0 d+ H* K oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * ]( @: }/ `* ^) v8 u2 @" ]0 ~/ L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
]! _7 D% h8 |0x00, 0xFF);
6 t0 k T* g, _$ }
* e5 N' m! c& X+ ^: L2 Q/* Enable synchronization of RX and TX sections */
# Y! t' [( n' m; ~+ AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, A6 t* Y8 M$ J$ \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& P' f* }. B9 X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. @. |: N }5 h `
** Set the serializers, Currently only one serializer is set as
. e/ w# I2 U' H0 d) o {** transmitter and one serializer as receiver.; v1 v' K5 h% _) o" {( J
*/
0 l% Q' }/ h) V: A9 u) c1 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. Y% P2 H2 V# O6 B9 J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- w9 s; ?/ p5 {* D** Configure the McASP pins - F/ u/ T0 `# M$ U* r) }7 E
** Input - Frame Sync, Clock and Serializer Rx& i a# K6 I5 H1 k- Z$ h
** Output - Serializer Tx is connected to the input of the codec
8 c, F6 h0 h& ^( F*/4 a. ]3 L6 ~" Y* H7 K% c3 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 G1 n* z; v: `8 j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) ^3 F6 J) k+ }2 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ a9 ~0 m$ a6 s. W& q9 V0 A
| MCASP_PIN_ACLKX
$ c' _. R3 j1 f| MCASP_PIN_AHCLKX" X. I$ O: L. O( _0 b* _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" o1 m# X, K' c) |0 z7 B: W' _% ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& s6 y! c- S+ t! W0 q| MCASP_TX_CLKFAIL ' c7 y, C$ w7 D7 y
| MCASP_TX_SYNCERROR
$ z" B) x+ L$ ?2 Q2 {' m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 P2 T: g2 Y2 Z, {$ I b| MCASP_RX_CLKFAIL( r" y" G# D' w, J1 H' N1 V( q
| MCASP_RX_SYNCERROR
* x: s/ C6 S+ D! D0 Y| MCASP_RX_OVERRUN);: }7 c: F1 f! F* I/ Z/ C3 U
} static void I2SDataTxRxActivate(void)5 @3 |, j9 }7 U. l$ Y( ?4 o
{
3 x' t& _; o9 s1 G- L/* Start the clocks */. M8 ~3 E6 C1 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 W" T( @! _0 ~" ^! ^) d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 H9 L% t2 r+ c6 H" c1 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
y) D6 W( E( m7 t7 G) NEDMA3_TRIG_MODE_EVENT);
; l+ P1 q# n# @6 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ I- L, i# B3 x3 vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: I- ?% g/ m, X" E# zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; l& i9 F+ R9 M, q6 S; ^2 y) H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. x+ j- T/ c3 p6 C+ i: }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ F6 {$ Y4 h1 c0 C& d9 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( z( z6 p/ s2 `; I8 e) CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" f W& I: t$ B f' V+ y}
7 l: |( ]6 l. _& D1 d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % n4 J: Y9 U6 e* g7 Q: w7 U# G
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