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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! k# n9 z- ]! L) D. @4 Z- m
input mcasp_ahclkx,
( m; T% e2 r1 R* J" oinput mcasp_aclkx,
; W1 ~$ p' X1 _input axr0,
- C7 d7 ^/ W* X$ h- l( ^3 T, ?. m1 }2 l! b6 x, z- L. q
output mcasp_afsr,$ j! H* I( W+ ]4 O- l- J2 f
output mcasp_ahclkr,
. D1 Y+ S9 ^# h4 A& routput mcasp_aclkr,
9 q( F$ U1 d/ M% `" soutput axr1,7 d5 e2 Q' U7 L# D
assign mcasp_afsr = mcasp_afsx;! h! L6 e: z1 l2 h, E6 e) o
assign mcasp_aclkr = mcasp_aclkx;/ }& J7 e4 M/ u& E. g
assign mcasp_ahclkr = mcasp_ahclkx;
! Q' K. e9 M1 a7 i: s1 r: _) Massign axr1 = axr0;
) `! r. ~& L) I' e+ r7 D9 D8 Y2 s3 {* @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 `7 d: B6 h+ f" `" c: E6 wstatic void McASPI2SConfigure(void)/ Q2 W0 x/ Z: u% X8 d
{
, ?& m0 t- K0 C8 V' W' p, VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( c. H" K2 p) Y Z1 Q: J6 E$ i) v9 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: d5 G. l3 U7 B W" b6 E7 g& f" @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* a+ U7 W1 p5 ^ e \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: g6 O: N5 M/ g! }$ c7 _# O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- [6 c' Z6 J% z$ u! M& U
MCASP_RX_MODE_DMA);+ g3 d" k: O, t- C" y( c# n( X u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: j( H0 H" K+ S( O/ ?6 u2 b5 J- K# W5 o8 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% h4 {" U+ @6 {6 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , c- U& b3 k! \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ^: e1 X- v+ o) R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! `! T6 H( a/ P5 Y# R6 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% L9 x0 r+ j8 ~: T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); U5 I0 G3 U% g% a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ [( \3 _" r1 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 T: T" s0 G! D* T0x00, 0xFF); /* configure the clock for transmitter */5 N' K' X& I' v- r1 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! _) E1 O- W+ P& G8 ^- |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 b( |) i# s+ k' O; {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 t. x& `1 Q% b9 ^4 ?7 o" c0 R0x00, 0xFF);7 ~ }( y+ p! Q. l& I$ F
* y. Y6 r' i0 I6 G2 q6 [! x/ D! n/* Enable synchronization of RX and TX sections */ ) Y+ U% L' X( v" n P% _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 O, J( z) \+ h0 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" L; K& G0 d7 D+ o# z( ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" o0 g# B9 X/ ?, G+ p- `# I
** Set the serializers, Currently only one serializer is set as& w4 Q' u8 ?" c
** transmitter and one serializer as receiver.* C7 H+ N( y, A. q- r7 p
*/
: s# o# m0 l7 m0 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# V8 z" M5 m& T. U3 S2 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 j* }2 L2 d3 o1 W j l' U% Z$ {** Configure the McASP pins : E( y7 A q6 T1 E
** Input - Frame Sync, Clock and Serializer Rx
( [- u$ b K2 J E; {** Output - Serializer Tx is connected to the input of the codec 9 u, B6 H8 ?6 h. p# O
*/
0 p7 M- M3 J, AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ Y D( B3 p, e7 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ R& a! H+ U& Z" h, H3 y& hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX L, w4 y/ B+ V* a
| MCASP_PIN_ACLKX
9 _/ t3 V( F0 }" G| MCASP_PIN_AHCLKX! \) h7 i6 y1 l0 R1 \4 u7 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 `8 O Q5 i" ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 z4 c( I" u7 {# Z `: o
| MCASP_TX_CLKFAIL
$ K+ c8 v9 E4 b9 C| MCASP_TX_SYNCERROR
, G$ @4 f( r8 V3 w% F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 ^7 w* g: N# p7 |4 A| MCASP_RX_CLKFAIL
! b# [ [' C) p/ W" n| MCASP_RX_SYNCERROR
* t; K" u- z/ B5 \| MCASP_RX_OVERRUN);, u' ]8 K3 Y$ W& F) Y( Q. d
} static void I2SDataTxRxActivate(void)) g" I6 _: t: U: \& q/ b
{
. [: o5 w, s0 ~. x3 g) t, w. F/* Start the clocks */3 m" ~% r! x5 M! e' f: Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% Y% G1 z8 ^7 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! q9 h3 {2 |( U' m: k. IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- T" q% b/ d3 Q" K5 e! hEDMA3_TRIG_MODE_EVENT);
/ V# F" ]5 ]. K& N" wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 O$ u- d1 a& a/ x. N a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! a9 P6 Y2 ^! |$ ]3 mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% U0 \) r2 f5 X# g& N, RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 L3 D) }. S. H8 S. Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: g. [) [. b% [, v |" a- `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 O( G, ^1 @8 l# vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( K3 ?3 `* ^" L0 S7 B% f' W} 6 w' ~8 H V2 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; H, ~; O7 m u5 d
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