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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 }, S; |, E: V( g; R9 b$ C
input mcasp_ahclkx,0 R2 X' T w) q: U9 G" Q$ ^( u
input mcasp_aclkx,
, h( V& W! q* s* c& Sinput axr0,9 ^, `1 }, q/ s2 B: x
* X. q# b0 N9 i& B1 |% Routput mcasp_afsr,
: ^* o( w. m8 D, | ~- `output mcasp_ahclkr,
7 _6 A! }' u- o9 C7 loutput mcasp_aclkr,& s2 K) W: r/ D
output axr1,
7 c5 ^, U7 S0 a/ y, u4 f% ^ assign mcasp_afsr = mcasp_afsx;
! k( H: f+ ^# W) o4 U4 B! E3 tassign mcasp_aclkr = mcasp_aclkx;* _6 ]+ j& B- l5 U+ r# |
assign mcasp_ahclkr = mcasp_ahclkx;
8 a5 f% ~* F7 S3 ]; D( J" aassign axr1 = axr0; 3 \# y" x6 U! a
. A) ~. X3 L6 _) l9 D0 U* [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) i; W# v/ v( o4 S+ E7 N/ ~* nstatic void McASPI2SConfigure(void)
1 g* N$ L5 [3 e7 d9 _5 J{
e8 y3 ?: w% K; R9 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* E; q" K# F2 }9 F2 T, E" l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) J8 y* ?1 R0 v6 } ]/ lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. {( q* G7 t* u; S# h8 l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 d8 B9 z+ Y" @8 q8 e5 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' l0 L' w6 v& J' L
MCASP_RX_MODE_DMA);
1 ~2 X# Q. h. u+ D, A, Q$ ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% \6 f" C# u4 `# \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% ?0 U1 y( E) [/ y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 t. A7 T9 w+ l) S, U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# S0 N: n% o; ^9 T2 gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 U: z7 ?* F' w6 B8 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; D' u# A4 u8 C$ UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 n7 t5 t2 P2 M3 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 b2 v5 M8 ~% H& |; g, |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) C7 e5 d; a$ q
0x00, 0xFF); /* configure the clock for transmitter */+ U3 \; H2 J& [! H5 H l4 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ w$ l0 K+ H f! ~9 F1 m: r" N$ I% P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); y+ }( |$ u) a. j8 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 u1 V" X- T% u1 G1 U7 T0x00, 0xFF);
1 _2 }" T3 w# r& @* Z) ]' x* g' ?& i" y/ E- d
/* Enable synchronization of RX and TX sections */
6 I& w8 H; W0 _, MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. W& }3 G8 G3 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 G8 B2 N, r: M: o* Z2 O) Z, g$ xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, [' x5 {9 ~7 {" D/ Q** Set the serializers, Currently only one serializer is set as4 X. x5 z4 s# b6 r. y$ w/ Z$ Z
** transmitter and one serializer as receiver.
" W* }. x& m1 P0 i5 p; M5 ?2 u) [*/
- [5 z& q2 ~0 @5 f3 y0 |; ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# k# k; }6 u3 b; @. V0 p) E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) a; G2 ?. d* Q; y/ f5 E( ?** Configure the McASP pins
7 i, B* p. ]) A; V- k0 X: j** Input - Frame Sync, Clock and Serializer Rx2 j% J8 M7 W/ W, ^( K1 @5 d$ R
** Output - Serializer Tx is connected to the input of the codec
. V/ @# u+ _% j' K! L+ S*/
* l0 W% {2 s. a* K6 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' K$ y! I# M% ]9 O1 V i+ G/ Q0 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. O' t/ T0 p* M* uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" O4 o$ l7 R9 F- ~7 ^5 H| MCASP_PIN_ACLKX
& i$ I4 ^5 ~) [2 @1 d% S( i1 g| MCASP_PIN_AHCLKX$ H7 n5 ^5 {8 I: Z- n# h/ T2 Y1 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( ^; k% }* A% Q. P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: A; i E5 N1 T: G l| MCASP_TX_CLKFAIL . o3 ~# N: N0 e% k# R
| MCASP_TX_SYNCERROR4 a% s( |- b- l( L, V$ E3 j: E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - U1 f7 G/ e$ W
| MCASP_RX_CLKFAIL
9 X; }: v( C% a| MCASP_RX_SYNCERROR / M* p+ w! _' W2 g
| MCASP_RX_OVERRUN);3 p: _" K+ C0 e" ]
} static void I2SDataTxRxActivate(void). _7 O7 [# ^% {/ V
{4 s. Q3 U) Z7 T5 ] c# I
/* Start the clocks */
! n, h" Y. K( YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 v0 o: S8 V6 U6 E9 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. P# x ^8 V/ t4 l1 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 {3 X0 f2 K( B# T
EDMA3_TRIG_MODE_EVENT);# F8 l3 F/ s3 h: Z0 \' l6 k2 q( [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" Z0 t3 T* R# z, k* _& g/ x" dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 O2 q& h+ p# x( d$ q8 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 B/ v$ a Q6 V4 l6 }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, d# u$ E8 i/ M. u y/ w0 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' R3 p. @9 K) p2 d' r) V B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) X) g+ K/ P% s2 h! C4 HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ X. x# j- ]2 ?
} - |$ ?7 L. |' [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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