|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 I# e& N y3 rinput mcasp_ahclkx,, Y& Z4 t8 |4 S6 G: _' i
input mcasp_aclkx,: Y4 G X3 t! f# x" T
input axr0,
1 O/ h4 F* Q5 n5 h: p* z7 w5 P$ O
- M' H3 v* I3 c n* soutput mcasp_afsr,9 }4 O o1 T; L% L
output mcasp_ahclkr,
" u: U7 k5 @8 a0 K( ~output mcasp_aclkr,' d' `1 _+ S+ C+ x5 G# v" w7 }
output axr1,
# h) V) X# Q4 C' a1 N assign mcasp_afsr = mcasp_afsx;# `2 e# ]' w/ M6 K' ~5 J Y
assign mcasp_aclkr = mcasp_aclkx;6 z$ a* @ e2 {4 u% K6 c
assign mcasp_ahclkr = mcasp_ahclkx;: z+ \' ?3 G: O" I( w
assign axr1 = axr0;
! b- {& n0 T" }- p4 D
# g u$ g" J0 x9 {4 M# T- D9 z: e1 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 U. d4 C, g! s. P9 k
static void McASPI2SConfigure(void)
1 e! f. u( Y( @: A" C& `/ n{
0 d8 ^+ n5 r0 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 [% e* T* H$ h' N0 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 ]* b. ]1 _$ E; ?/ m$ I5 @1 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" k" t/ b% _, A; ~4 {: yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* M1 D) g1 r! E; {( dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 l. o/ j5 ]5 z: b' AMCASP_RX_MODE_DMA);# x# I/ y8 h* ^* V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% F. {0 m5 z2 ^5 }9 p9 ]1 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( a& s5 i; j7 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 A( i4 M* P0 T3 { QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 N$ L+ l- c( H# _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 |7 ?' X+ I9 M/ `* s. f, b5 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 z! ]1 G- _; a0 E) U5 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ o. g E+ v' R& bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 v! w' h+ J: z1 O2 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. P6 V9 ]( B& w$ F
0x00, 0xFF); /* configure the clock for transmitter */
& J3 k8 N- V. l# t+ dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; s8 E# z. a N* d pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( I+ O: I& [+ J+ k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 L: I0 _" F5 \+ O, ]5 A
0x00, 0xFF);
7 y4 ~* j: d' L, R; `
: D' s$ c8 R! M/* Enable synchronization of RX and TX sections */
7 H3 g0 X8 S% ?! D iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! f" Z5 }% B0 L# ]/ n+ ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. s; U3 |+ |) C9 T6 o1 sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! }& f: F# l8 s% F** Set the serializers, Currently only one serializer is set as- `( f+ e' ~1 |; a
** transmitter and one serializer as receiver.' W B( [1 i0 ~# z ~% c
*/
2 L: N7 L: T2 h) LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 D: i) C/ ?3 m3 U, s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 }; a3 \% O v. [5 x** Configure the McASP pins . x. r8 U9 i9 G/ b- m. v
** Input - Frame Sync, Clock and Serializer Rx
% }* i2 r( H7 V( Y- I- w** Output - Serializer Tx is connected to the input of the codec 6 v5 l$ y9 {9 a% b
*/
! |6 C7 ~! {; o& x4 ^' ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ ]2 T( w6 N9 c5 X5 P8 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- N5 |; d& U& b: H& R4 ?: w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX {, u! v' \/ ~ F \, z
| MCASP_PIN_ACLKX
/ F& i2 ?% D) u3 F: r0 t: k| MCASP_PIN_AHCLKX
3 ^' F! z8 j8 @9 B2 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 Z$ M! @- I2 t* ~- |; i. BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : y' v9 s( G5 [- e
| MCASP_TX_CLKFAIL
4 o% I3 ]8 s2 o/ e5 R| MCASP_TX_SYNCERROR
4 ]# S; `) V& `( B/ L! X: [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 R6 O$ \. P: h# D* V% S) o
| MCASP_RX_CLKFAIL: H8 D, L* B$ q/ \/ a4 t
| MCASP_RX_SYNCERROR l0 J: L0 q" G B8 i% q# V
| MCASP_RX_OVERRUN);- j# o1 U) ]; A/ U( f: o O4 H' ~
} static void I2SDataTxRxActivate(void)
5 Y8 ]) i! O/ p5 c% y, f0 b{
8 V6 Q) I. C' m3 G0 I, Y/* Start the clocks */
- ^- P2 V1 r& U+ t" w/ D$ _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ F2 [: d5 K! H6 A6 {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 L3 d/ ?: b; X5 {( qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# ?5 a E) h3 [3 S$ ~ B7 U
EDMA3_TRIG_MODE_EVENT);
! v% \% L/ v! N0 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- u5 v" @, Z( \& r% xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 v* {8 L) h% \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) l& y! _2 F1 ?% d; |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ L. ?% J( R3 H+ z" ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 C) k; Q# q4 j3 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 [3 ?" g8 {8 f7 I: p) y: cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% A" v2 _3 \1 W* |9 B9 X$ b# ?! n
}
9 t8 Z+ T U7 a* S% B1 O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ c6 v' z; d# N: S3 f7 S1 B |