MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
, d2 U8 \: F+ E8 z& h! kinput mcasp_ahclkx,
  l* @5 W. }. z! A1 j% x$ a; H" ?input mcasp_aclkx,
+ ^7 u) A: ^2 B( x7 \input axr0,
% h  ]0 ]- Z. k3 {
0 R8 R% k5 t! x5 p9 s4 xoutput mcasp_afsr,
output mcasp_ahclkr,
9 x6 R/ e' Y- l8 f: x* Eoutput mcasp_aclkr,
8 W( [" i5 M: Y9 @! [output axr1,
/ R0 Y8 L; X2 S9 [4 B8 j

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
; U, p3 s' i, q3 d& d; Qassign mcasp_ahclkr = mcasp_ahclkx;
" G4 Z1 c- X. H' M3 N. u, vassign axr1 = axr0;

; r5 n5 B8 \6 n/ Q- ]: }

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

3 d. S% x" \& S( ^) n

static void McASPI2SConfigure(void)
{
2 D3 i% ^6 A2 V# Y( FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ o: t6 c% S3 @  a6 u( H$ j1 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" M" r2 n6 [: CMCASP_RX_MODE_DMA);
# `  E+ }3 v+ _, q5 y3 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ `" a9 l& k7 a: G" b1 YMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 |3 E, F& E0 k$ l- y; @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
3 p5 ~+ B2 R. B; n, L9 _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, z! D# ]5 u, C' O- {: a2 PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) Y- ^8 `9 s" NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
% y# p9 ?# L/ @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- I+ g- X- k$ y$ W# IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% o3 ~" M7 {6 E" u. b+ t6 b/ d** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
7 W3 o  I9 b' n5 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
- C; q( p/ |0 _% D- A; E: ]& \** Configure the McASP pins
# G# m0 A* x1 d/ |: x* @** Input - Frame Sync, Clock and Serializer Rx
/ D. v. ]( @, C** Output - Serializer Tx is connected to the input of the codec
*/
* q! A  e  o, k! BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- w& h. T5 t& k6 E+ l0 N& K- qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& J, u. ?6 Y6 w. \9 J  d| MCASP_TX_CLKFAIL
. l0 u, U$ w( Y1 a+ k" V6 e| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 a1 G- n2 n( K1 P3 I( O8 G| MCASP_RX_CLKFAIL
9 s5 y+ P/ b- A: E2 Q# H) L| MCASP_RX_SYNCERROR
8 }2 r& I; v. F| MCASP_RX_OVERRUN);
; n! C5 F1 j0 K, |+ R( B" ~}

static void I2SDataTxRxActivate(void)
" Q# W: w& x2 x. [3 U# P{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  B! m& s: a) z2 b) n5 C0 C6 v" FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
1 K. ~1 Z- s) U" m4 c5 y9 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# U0 X: ?% _6 P0 N0 B5 P' {/ N2 ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
* ^6 ]7 M  ]) MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 b1 Z+ {" S$ K( e! I* {: VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
1 N0 \% K" _, p( ~/ iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" X: q8 ]: N* U. E1 pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 I4 A! i) d3 a. d( S}

. P: u: ]3 S4 W9 {" z: @

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

! n- L% V/ q2 B- X8 f% x