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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' e$ O/ X$ F% h: F5 c0 m5 Linput mcasp_ahclkx,0 n3 R8 g+ W, y$ ^' k& m
input mcasp_aclkx,
' l0 [# X, ]1 e& u$ J5 Ninput axr0,. H2 D0 L: x8 }% f6 i+ E5 y Y
; q7 u' D& A) w$ K2 k3 |& _/ _3 s Z
output mcasp_afsr,
; H9 N; Z% e, t& b" eoutput mcasp_ahclkr,
/ o1 q/ u# i: S4 w% U: j$ \output mcasp_aclkr,' l+ G- G! D- z6 T$ ]
output axr1,
, h8 O8 f, B4 i+ e: ?3 b assign mcasp_afsr = mcasp_afsx;) y) ]& H3 l* e; Q! }) f
assign mcasp_aclkr = mcasp_aclkx;
5 I7 n7 Z# K9 Y Uassign mcasp_ahclkr = mcasp_ahclkx;5 ^6 u' C( P% z: j8 ^. w3 ^/ A
assign axr1 = axr0; 6 r' j& |1 C; M' H% l
/ P4 _) N! u, P6 l9 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 o6 ?) P8 h! H2 z$ j1 }4 jstatic void McASPI2SConfigure(void)$ x* F) ]$ p/ e; P
{
7 Z0 y3 h! m i1 {; b7 T$ x2 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);* ^7 H# N/ }/ y1 \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 [$ X0 Q6 b9 ^) Q/ y$ u" tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 E# E. f0 M* p# M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 A1 a" l5 J5 C0 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 o% r7 c) Z1 g" YMCASP_RX_MODE_DMA);
" l- b$ o# ?7 Z1 H% jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% n% ]$ ?+ }& j P# D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ H {9 _; R; o& n% dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 { V6 `* T* `8 m& T3 o, Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ U8 g4 g. D! m+ s* L2 `( _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; r [4 j, B2 G( `5 V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ E3 F; D0 Q- o& f! K/ c! ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ Q! F* G3 d- \% ^5 s2 x: n1 z; @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: H3 ~* P; N/ n/ {0 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' n3 d4 z# Q; ]; h: x, `5 q/ z7 O! W( a0x00, 0xFF); /* configure the clock for transmitter */
/ d/ X3 Z% j+ WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 D# }8 N( m3 M5 _ [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 ], F) s4 j0 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. e- n" x) G* d
0x00, 0xFF);5 k4 W! S& t+ {& Q
7 S! i N S( ^. p9 Q0 ^
/* Enable synchronization of RX and TX sections */
. R8 E2 P; D2 IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, ^# \, w0 T2 V) V( E3 q* {- VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 |; V* |5 D$ z9 r" X/ d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' L4 g6 U. m/ @; k2 e
** Set the serializers, Currently only one serializer is set as2 q7 V. ^- _. F; E. b2 z Q2 x2 ]
** transmitter and one serializer as receiver., m0 g8 d/ A% P
*/! @9 p2 a) k! w2 [. P. K8 J8 v7 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
T0 ]! m; T& \" \; C6 a' xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ Y; Z0 N* }; Y5 Q, J5 Y3 ^** Configure the McASP pins
, c0 c5 S! z% z/ p) h% M+ @0 J, `** Input - Frame Sync, Clock and Serializer Rx
; ^3 Z/ j' F3 |" d+ p** Output - Serializer Tx is connected to the input of the codec ' v3 M" o: e2 i
*/* D( x7 O! {* Y% C* Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: L/ D9 y2 h' y% j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ h% j; G& i- {5 f6 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 Y/ ~( c, E5 l; y6 ^- e z# G. _
| MCASP_PIN_ACLKX
7 R- C7 y2 v- U/ W( p$ i| MCASP_PIN_AHCLKX
# w, h3 Y, a$ s$ || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; @/ r9 ?; C d. g$ K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 b0 m( x% o" |, `| MCASP_TX_CLKFAIL 6 J; g# O: v5 x
| MCASP_TX_SYNCERROR% z" [, u* D+ p# _; J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' X* n5 O' [; `8 [| MCASP_RX_CLKFAIL/ j/ N" \% H' H
| MCASP_RX_SYNCERROR 8 n$ Z. S" H L v- d
| MCASP_RX_OVERRUN);
4 \ J$ Y; c R% V} static void I2SDataTxRxActivate(void)
w2 A) X9 w+ Z{+ d0 ^, L! U+ Z$ W# F
/* Start the clocks */- Q4 k: G ^- z: e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' N+ e$ q% \& RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 h4 U/ @! W1 u! |& W- y4 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) b5 D( Q& ?: g) O0 p- O2 ?$ G
EDMA3_TRIG_MODE_EVENT);+ n4 l; X8 Z M) q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 C5 F$ v: r7 ]) X8 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 G( h4 D" j7 ?3 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* L3 P5 n; D# b4 A) b' g# hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! {. Z, j V) j! l9 _$ }4 iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 _2 H$ ]9 q3 g1 ^0 t$ z* tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) ]3 ?7 T& D& b" q' KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
R* l! ^1 t; G% ~9 I" q8 J} 6 ^- j, T4 n# U1 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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