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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; M0 \1 S# m- S7 E: pinput mcasp_ahclkx, S; e* r6 J7 _( b% @6 s5 H3 o* C
input mcasp_aclkx,
$ E$ H5 m z# F, p% R$ Binput axr0,
0 l; |# U( n. n0 T j3 n; o/ K9 ?& H" H7 r! g% V v7 y i
output mcasp_afsr,
7 c, [& j9 T0 Z+ Q' T, X: foutput mcasp_ahclkr,9 |+ V, h9 F( q1 u
output mcasp_aclkr,
9 M" M/ }. x! D, Q U: eoutput axr1,
4 m' x2 U; r+ R$ J) P/ T" z assign mcasp_afsr = mcasp_afsx;' y4 e9 J$ w/ N8 c# p- i5 R
assign mcasp_aclkr = mcasp_aclkx;
$ }& l& }3 |1 ]; u( h. F9 Iassign mcasp_ahclkr = mcasp_ahclkx;
, [! g6 x9 l& z" u& v5 hassign axr1 = axr0;
- d; x5 T. j2 r2 } { F. W( ^1 _/ `/ S6 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& U2 _4 F) W+ k: T2 h- k( [* sstatic void McASPI2SConfigure(void)
" z) \; G ]- V% }8 p+ C6 i{
% s% Z9 Q! |, b& ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ ^1 w6 w1 F6 h" X2 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' W: q; m5 U7 D, r1 t% x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: ?6 K1 Z" X$ W& J1 ]! o$ t$ p( [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ R: w5 z: C0 N6 q7 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, a: D+ F& k3 i$ T3 E' ^MCASP_RX_MODE_DMA);2 c7 \) C+ e, ^* T8 `. p4 {5 \; M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# u! @* W& E: l0 A4 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// d8 \7 M# o% |; U4 }2 W& a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, q1 w, k' B3 i# X* aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* E- x5 S, O% BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / k7 m9 [ P1 _# I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, O' C8 o$ E, z/ dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# o c! J \9 {5 r7 |8 x2 O, h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + o8 n) S/ e3 \& q8 v: q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
L+ A! L2 Y% C" k* W0x00, 0xFF); /* configure the clock for transmitter */
; g: t) I; I% k" x- ?/ H* n4 I, ]9 J0 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 M, m: Q4 B/ ^6 `: MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 _! L* s J4 \6 Z8 G7 h- P3 `. o5 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 ^) b1 A9 Z3 `' e
0x00, 0xFF);8 q$ Y$ V$ a8 {( j1 G8 n, W U
; U! f$ o' [2 p0 O7 I
/* Enable synchronization of RX and TX sections */
t0 @; }: b9 y% W, wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 n+ F- o! ~0 L1 F3 h( z) P5 p9 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( u1 N5 P1 b9 W3 c( f! C( ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 o- s* P7 d+ f# b/ Z4 L** Set the serializers, Currently only one serializer is set as
! S* x4 V$ t) p. O1 B$ b. p** transmitter and one serializer as receiver.4 q9 _1 P1 v- o7 R6 @
*/$ t; S2 @6 a, G# z1 V5 G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& w v" D1 j1 f2 \/ c+ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ?% ~' m& [" e$ S. n7 {1 b** Configure the McASP pins
3 @" j+ x9 m6 x2 {' a** Input - Frame Sync, Clock and Serializer Rx
: v/ x9 U2 g, F5 h# X; J* V** Output - Serializer Tx is connected to the input of the codec 9 ^7 t. T, J% G* l( O) \
*/& F% o Q; H6 j2 V# Y3 m$ Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 R6 W& T5 z( w. P1 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 b, e& w c# Y; k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 ]* l% K( ?, [! \4 e
| MCASP_PIN_ACLKX9 \" U- o0 A8 w2 i4 F% S
| MCASP_PIN_AHCLKX
) U1 {$ `: z2 Z+ |2 E& w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 t# i( G% o" K; X7 ?- g( y. OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 [" u. a) c! S/ Y
| MCASP_TX_CLKFAIL ! T% |. S( H. }
| MCASP_TX_SYNCERROR
2 ?, ?! l6 m- | S+ V7 c0 ^" j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + P0 D8 X& j1 |9 ^; g- j, u0 j
| MCASP_RX_CLKFAIL
7 g' \$ z# B& w/ x& p! ~! c& |: B| MCASP_RX_SYNCERROR : @+ ~- B$ r7 f# t
| MCASP_RX_OVERRUN);; n3 \0 F% W+ [' o0 E. U& U0 |) Z
} static void I2SDataTxRxActivate(void)4 }2 ]3 f0 h& l$ A8 g4 I
{1 v* M% _: O6 C0 i4 T0 y5 \
/* Start the clocks */
+ I" e, q# s0 O- R( O+ J3 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% W U7 c% `3 f* S7 S9 ^" L# o+ u" l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) `6 K; n5 m9 s/ @# N9 B) N0 z' tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 j8 L2 V2 e6 `; G, L' x4 P
EDMA3_TRIG_MODE_EVENT);
a* D6 \1 s3 A" nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, Q4 {. r; g- }( e8 W9 K0 E) SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, m4 [+ b& q" s3 kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 U3 n! s3 z7 n& Y3 E" ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ O" w& p5 M$ i0 y# z; M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; \. W5 D/ j6 y- M; ]3 F, OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* S* C i9 M/ h/ I2 x7 F; k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 ^3 l" ~/ A9 v! o' s: ?
}
3 \; @5 n! C( D* q4 S0 w0 U2 W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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