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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ L% Y& J. ?8 |! |input mcasp_ahclkx," j6 z' O- s- B4 v3 \4 u2 _! Q" J
input mcasp_aclkx,
% h/ z% e1 s; L; d( Hinput axr0,3 I6 @/ U2 e. c E9 x& P
% F: A* G4 j- b+ h" O1 x. D9 V4 L8 aoutput mcasp_afsr,
! s X" ^) u1 h" J: }& s8 C/ Woutput mcasp_ahclkr," m+ k, ?( A" s4 I4 {+ E
output mcasp_aclkr,
/ P% G9 c% Z' ioutput axr1,6 G M. I5 W% [' m3 O% L
assign mcasp_afsr = mcasp_afsx;
9 ^& i# j8 }( C2 y& h9 v% oassign mcasp_aclkr = mcasp_aclkx;
0 H7 T" b/ k' Y0 F: y2 h# Nassign mcasp_ahclkr = mcasp_ahclkx;
& V- t; t7 Y; a8 r2 k1 @, Y. R7 tassign axr1 = axr0;
0 \/ ~4 P& f! A: m& }% u: P9 g7 n, E, C1 g- Z* ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& Y4 K% K7 E q+ Z3 Wstatic void McASPI2SConfigure(void)
$ B0 T1 F' A T2 E* a! G; \; A{" \" t3 _+ _ S# o( {; Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 R3 |. N" A8 F8 j# a. h9 X! IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& j$ M) D$ Y2 J: o V7 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: d1 Z) x! D ^9 D4 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! Z/ R7 i4 F$ B# C7 I, L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; U. U! v2 c4 L1 J6 ?
MCASP_RX_MODE_DMA);
; h! Z% H" g, {1 N+ VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: u& P; `! }7 b8 @- n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" W. W' ]# x( n4 V: a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + ]. F% x+ G$ X7 N2 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% `8 L( e+ j* f8 n. @* `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, y: z* a, B9 K2 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ k, Y7 I2 m3 u- M' x4 F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- [- p8 w2 Y9 x4 y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # _' W }; w4 e/ T) ?9 i G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ w* j3 }1 s, Y4 U2 N4 L
0x00, 0xFF); /* configure the clock for transmitter */
. ]9 D' s' u6 U1 E& }/ OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 b @2 V0 r, y, ?0 D) l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 L; L% t' B, Q& t* R* \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& j. O* {( g7 ?, W3 ~* D# ~
0x00, 0xFF);, z. y! b& l% j1 T" @$ |+ k o
2 _, a+ |* y+ b: H/* Enable synchronization of RX and TX sections */
% X7 c/ i" _9 w" M6 B- B" P$ DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
[, p# g A- \. {8 p/ JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 e9 o: W: u6 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ ^8 w: @$ E; g! ]) f7 g
** Set the serializers, Currently only one serializer is set as
' S) V5 K j# Q& Y" V# }+ k* }4 b** transmitter and one serializer as receiver.2 \0 h! |7 O3 j" k
*/1 z+ f) T, ^2 w4 n5 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 f+ g. j* C) A5 \$ Y; W" cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: R, _9 \- J. ?! A** Configure the McASP pins ; a5 T! r Z) q, p' @: S
** Input - Frame Sync, Clock and Serializer Rx
! }6 ?- a. j, y% e5 g** Output - Serializer Tx is connected to the input of the codec / K5 l9 k2 O; Y% y% B
*/
; ^+ j9 z# L9 F6 }% ]2 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! q" z& b0 Y: d4 g' {7 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 f, b+ A2 g+ S5 m( y' g) W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% Z! W, ?, k M7 B g" k( W; `
| MCASP_PIN_ACLKX" f6 G, f6 @; Z* [) R6 J9 h Z7 x
| MCASP_PIN_AHCLKX
' E# S4 k- w! ~/ x0 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 O) i3 j% M3 Y3 b" K! nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 Z1 G0 j( ]5 {1 c" u& F
| MCASP_TX_CLKFAIL ) q$ U6 y9 K4 C; A2 d3 J1 ~9 x
| MCASP_TX_SYNCERROR, ]+ ?; ]3 D6 s/ @' I! Z( A7 J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 x4 R' g; i* w |
| MCASP_RX_CLKFAIL
( W( o! A6 a P9 P| MCASP_RX_SYNCERROR
$ g7 L; V2 R9 h1 U3 V* |& r0 N2 w' G( @" _| MCASP_RX_OVERRUN);3 t( r% \; D9 |' F* [7 q
} static void I2SDataTxRxActivate(void)
7 B" f h: P3 ]$ s- f{4 A6 _2 w* x4 g
/* Start the clocks */
/ O5 A3 a6 n5 s: O" N2 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 y1 y& @2 } C B, }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- c2 ~: |3 m9 L2 W$ }, eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 u( |6 c1 b: s* ?: @) I" AEDMA3_TRIG_MODE_EVENT);- N) I. o* j" i+ k; P: m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # @' F. h( R- s: t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, s6 {. B5 U( t: _# z6 X6 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; g) W' ^+ J6 W" s' }9 j5 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" r! d1 X5 {) r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) L7 G! S2 G d" S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 E0 M- {$ u1 c; Y7 H, WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" ?- W' w7 T) K$ Z/ Y} ' ?) a r0 P) ^* _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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