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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 a# z- Q5 Y# ]2 e
input mcasp_ahclkx,
( _ f( u7 n# K; Y6 Z( zinput mcasp_aclkx,7 I9 G# H- q8 }7 K8 A
input axr0,
; }5 U- f) p( ?/ g
) c0 G7 _% i5 y7 r( joutput mcasp_afsr,2 a- |% E9 r" i- ~! \* H, y
output mcasp_ahclkr,: V/ ?! I& Y8 F4 x
output mcasp_aclkr,6 R0 K( c/ h: T8 Z! C
output axr1,1 v8 Q# _; y* H' V! H
assign mcasp_afsr = mcasp_afsx;
. ]/ r+ |3 t L- Iassign mcasp_aclkr = mcasp_aclkx;4 j1 [, Z5 k U* ^ `! Z
assign mcasp_ahclkr = mcasp_ahclkx;( O# I# [" \: V$ u6 p7 j5 m7 q
assign axr1 = axr0;
2 K' g. t% O z7 u* I7 u% T6 {( [, d( P3 b- s4 r' L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( }! z9 ~! k0 S& G- Q
static void McASPI2SConfigure(void): C* J* J/ K* l9 V/ i7 e, a* B
{8 T* H- A. {7 \7 ^ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, u8 n" M0 m5 O* |5 o2 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 `* m! U5 V% @+ |* x, jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! p) {/ z/ R3 R- d# C8 j" hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 z0 C% ~4 p. q. a8 P3 W% R$ y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' Q5 u C6 b" O) P9 h: w6 A5 u0 rMCASP_RX_MODE_DMA);
0 c- g& Z/ n% |1 d/ {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 a: @* y- b& ]! _) ?6 e0 L! DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 _+ C' \3 x7 M/ W# TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
S/ j" s B5 t, g( U0 kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 D3 ]+ y3 T& d U+ W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# z# B* t. B: v$ y# t0 E( A; sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& a0 J$ i6 T! c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 `, ~% t) k" k8 z1 Q5 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 a. F+ C* [5 q' l% {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- i/ E8 j/ K( w, g; a! P4 t d" M
0x00, 0xFF); /* configure the clock for transmitter */) [, u1 S5 p7 ~7 C1 @# O2 K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 {+ t* D# x% z, ?+ x1 Y/ Y7 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , E& y( _" F7 e# C+ F" p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* L2 o5 P) v3 o0x00, 0xFF);
6 E$ L& a8 n' q# {, w1 z3 o$ Q; b# |, G5 r3 v5 I' q- u
/* Enable synchronization of RX and TX sections */ k# c* j9 G0 O8 P7 W7 f6 u% H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" @ Z( r' `6 W2 k+ R7 L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ B r+ ]1 T* _( NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' ~. [6 B( b5 D) O
** Set the serializers, Currently only one serializer is set as3 M5 I: H5 D; z* u6 r) Q
** transmitter and one serializer as receiver.
# m4 h( x1 [. H) l*/3 U( Z, l$ J! O' t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( N6 l2 W* M! C: d5 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ i, _! }# j3 R** Configure the McASP pins . V% T- ^* i1 J; l
** Input - Frame Sync, Clock and Serializer Rx- e% B+ e% ?$ I0 P9 N1 r* I
** Output - Serializer Tx is connected to the input of the codec / f; K( G# d5 d" e, S0 J
*/& K7 [7 F9 L) E9 n9 t& K0 G3 Y: R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- }1 X1 s5 o+ q7 h: CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 i* q- Z$ U& l9 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- Q4 Y6 v+ X8 t( q' e: `4 I| MCASP_PIN_ACLKX$ a7 p8 Y1 L( i' \) Z( u" ~
| MCASP_PIN_AHCLKX" e7 g6 p# u0 K( x! e, e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 n# `/ s9 f% E0 ~/ w5 [" j) b5 k+ yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 H+ ]7 J: e0 r# l| MCASP_TX_CLKFAIL ( ^. q# {; N5 t1 z! k% _9 f' X
| MCASP_TX_SYNCERROR7 u. k" i( y" F+ A ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : X' z0 \; P7 _8 ]6 d! F4 [1 K. u
| MCASP_RX_CLKFAIL
* n& b* s3 w6 m4 G| MCASP_RX_SYNCERROR # V9 ^# S( t8 R- B/ n/ {
| MCASP_RX_OVERRUN);
& | K! \+ Q& E6 `+ ]' f} static void I2SDataTxRxActivate(void), h9 p2 l% z; G, v. D& [
{
! t, \3 u$ W3 e/* Start the clocks */; j6 F2 d" g1 m4 y7 v7 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% T# x! [4 |0 A) }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 I2 y+ X# h& p, T+ e/ \" E# v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 S% F+ r" d# h; e4 ^$ O; u5 @
EDMA3_TRIG_MODE_EVENT);+ T& x8 B- U. n( z, x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . |. e3 L' _- h2 _* i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 e$ K1 [( I$ Y, _& A* |, Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' n' I+ p; j/ F3 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% I2 v1 O) E) j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! {) i& Z4 b# [7 e: t$ {6 ^) p( mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ y( g; j' Z2 Y, o N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! M0 j$ e2 p" S' {# e0 k
} a# L$ H# C" B. ^8 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + e2 }: g+ \0 P: C9 z. d
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