|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& f$ g* X2 ]9 n! j0 c
input mcasp_ahclkx,
% @9 e) |: v0 Einput mcasp_aclkx,+ I0 X; u# R- E X. \
input axr0,6 p: `" j2 H5 w j# }- p
9 ]! H& Q8 ]; f |% Goutput mcasp_afsr,
$ e$ Z) X# ~3 _0 x9 K1 s' e1 ioutput mcasp_ahclkr,5 T0 o; p0 m5 M$ E& E1 Y1 Z* W
output mcasp_aclkr,
2 I: r, R% h9 ^- n# a! G6 z; e1 Foutput axr1,/ g7 ?9 K7 ?1 B
assign mcasp_afsr = mcasp_afsx;
: J. L" v! w- x' V" \assign mcasp_aclkr = mcasp_aclkx;# D& t1 b b6 Y# q/ m( \6 M" I
assign mcasp_ahclkr = mcasp_ahclkx;
. K+ U* i& {4 T" gassign axr1 = axr0; * p! q8 h h( ]9 q$ e
j5 ?: C/ z+ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, X, g: F8 k. |5 Wstatic void McASPI2SConfigure(void)
- }) x* O9 L0 e- N* P{/ W; G+ C& w! b8 R( {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: J9 a4 z/ ~# j* B# z* M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% w; t& C) h) ? T) ?# z& J, a/ ]- X) CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, q, f8 D6 o9 @$ C3 m C2 |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* O4 [" ^( i* AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ J6 T# Z5 q) L% H' {3 x& f% SMCASP_RX_MODE_DMA);2 `# T3 o' ?+ v, K7 [! h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% n j& Y! u* |( ~; r& c( j* }, yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( [+ Q: \8 z5 \( J; @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& p U& j1 f, MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 `0 }8 n# W# q% ^/ K- \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 O+ O' j% J4 a$ K0 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' P w- q- G8 r1 k" R+ M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% q+ M" `+ |# ^6 R" GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 \) d% V) b) L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ r% J! | w/ b0x00, 0xFF); /* configure the clock for transmitter */- o+ N5 A' o' Z# q* H) _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) L9 _8 _9 D4 r5 e+ `9 M% T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
P$ }) I$ G' nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 M; ?0 |( ^9 D: Z D: I0x00, 0xFF);% I1 F, b5 O, r8 n( w- U
( M; {5 Y4 X F' }6 \, N
/* Enable synchronization of RX and TX sections */
+ C) I4 `/ }2 e' f8 X# k* ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- W4 Y- j) i( l1 Z/ C2 fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 A" m7 x3 w2 x* @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# K' `8 Y4 R$ H6 f/ Z( G
** Set the serializers, Currently only one serializer is set as
( v1 a0 I; o% w** transmitter and one serializer as receiver.7 }. x) Y' y( M* w/ _7 a
*/% R; m7 X. J, Q: E- y2 Y: ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 I: y- t `+ g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- V: {3 h' M; K7 u0 f2 D+ P** Configure the McASP pins
9 D) X$ U0 h9 J7 [6 Q+ ~* v** Input - Frame Sync, Clock and Serializer Rx
/ F2 Q% }6 S; g0 @4 ~1 l** Output - Serializer Tx is connected to the input of the codec * ?* f: m5 m7 I; w
*/' Q% N3 H+ i9 p) l9 F3 V& h" j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" ?/ A6 z: O$ \7 L4 x% ]4 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 a0 G- ?& U/ W4 ^% YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
c6 H4 j" Z* A: U# v0 g, h% m0 S* S| MCASP_PIN_ACLKX
9 i( A# A% c1 h) h/ w- N| MCASP_PIN_AHCLKX
) R. M, @" S+ w/ |- ]. \# p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( _( P1 I% M# }1 o5 e" _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ k/ N2 x$ [& J/ K, r
| MCASP_TX_CLKFAIL
' E$ p& Q1 t7 V; V/ ]. T* w1 R| MCASP_TX_SYNCERROR
2 n$ R( Q+ n5 `! a4 Q- C8 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' F+ y# |: M: z: ]| MCASP_RX_CLKFAIL
. j7 M) \# c L' Y7 c5 K; }| MCASP_RX_SYNCERROR 3 F$ j, T8 d2 R9 a$ @
| MCASP_RX_OVERRUN);: S+ U1 v" S ?1 M8 r
} static void I2SDataTxRxActivate(void)4 Q- {+ N* v' `
{5 [# Q. `8 x$ K9 l' D
/* Start the clocks */
% M% z/ t$ }+ V7 u2 j+ RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! c; E7 d: u o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 b4 y9 ?/ d) r4 _2 f" U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, [+ M8 U& }# ]- R
EDMA3_TRIG_MODE_EVENT);
7 f* }8 T/ O; v1 L; e/ y) `8 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ V$ ~# H. o5 G$ d% f% _" d; r1 C& [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! I0 B" p5 v: }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 ]) b8 I5 q0 [' y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' g9 R; _! d" O5 O( A$ N: u; @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ l' j# m3 [! @8 j* [. j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 F# t+ T" U" T3 B2 T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. G! D6 S, x' Z S+ g} ; h6 D1 ?4 m! Z- L+ j3 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. H3 p2 K1 e v* { |