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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 u; ~8 f0 O2 X5 t& D: [& G
input mcasp_ahclkx,5 u' q6 `3 {/ h. u
input mcasp_aclkx,
& y0 L5 q5 L3 kinput axr0,1 Q" Z( o3 e# y6 l6 l
& w4 l5 p. C h, B2 V. \3 T$ h
output mcasp_afsr,
7 I, j: o7 p; w; _. n$ ^# {3 coutput mcasp_ahclkr,1 S" A8 I4 V1 H/ K8 c* e1 l J/ m
output mcasp_aclkr,5 O9 j/ Q6 d! X, F
output axr1,( @& S! k9 P5 s; }! D8 h
assign mcasp_afsr = mcasp_afsx;
4 H7 V( l) V+ d, L. r( e6 Uassign mcasp_aclkr = mcasp_aclkx;$ s d% p j/ X- X& D. r
assign mcasp_ahclkr = mcasp_ahclkx;/ L/ R" U, w3 B* J
assign axr1 = axr0; M/ y* F# p, S
6 b" R& }$ Y: d$ e) `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : B; _: _4 k! u0 _
static void McASPI2SConfigure(void)
& @6 R5 G; b4 [" x$ C. R' j{! M8 Z0 ]* c& Y5 D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 A+ O% U* {- HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ _; A- t6 `$ S3 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 L- J+ N+ \* t: }, J3 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 i1 a h% r! m% o z( DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 C5 [5 R0 L) ]6 WMCASP_RX_MODE_DMA);! R9 _; S0 X% A" u7 |+ Q; U; G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ a: Z. p/ F+ e7 vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% p: ]- D! f( Z' I4 B. a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , z! w2 a+ \. u) j' x& `0 w x1 r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); |& m; z9 X5 W" {: _- Y1 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 ]" E8 t/ y3 m% m; o7 i0 s8 \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, q8 S7 _5 P2 R5 c! w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! Q/ B- S' A& r4 K) Z! Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 W# [% L( R5 [* ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 Q7 J' z( {6 y
0x00, 0xFF); /* configure the clock for transmitter */
% i2 `, n5 e6 c8 f- E& OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) p. h& B& z ^# \! h. Z% L' c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" |, q) G, `+ U0 |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! P& ^) J! Z4 c R; a/ K* r
0x00, 0xFF);
% h9 R z2 R2 B$ c7 s( L- F$ _* ~1 D; A% S" ?% _2 Q7 x/ Q1 r. v% P
/* Enable synchronization of RX and TX sections */ 3 g% z3 _3 F& o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' ?2 E+ Q9 N( z. yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 ]1 B0 Q" x: m! v* `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 ?" _/ x; w1 L4 ]8 S** Set the serializers, Currently only one serializer is set as
: r8 X6 G) k5 q+ W+ `: {** transmitter and one serializer as receiver.3 x' K2 ] d$ r5 p. x
*/6 h; k; B4 x2 D7 u9 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ c" n% F9 f- q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! f# r& p {" i. | J9 W: ]
** Configure the McASP pins 9 y6 A v" j% W( G t
** Input - Frame Sync, Clock and Serializer Rx" C4 K% e# w+ S
** Output - Serializer Tx is connected to the input of the codec ; n! }! \/ _# ?1 @2 s
*/. \) K; p3 ~# K( E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* e+ V6 t& L# S1 [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 |% I% y* M2 E; Y) `( `, f" X# d' y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% o N3 P/ z4 _' B6 N% F% x" L
| MCASP_PIN_ACLKX
+ B( S0 h$ z! ]* U3 c& d7 I. ]| MCASP_PIN_AHCLKX& V: Y/ `0 I- V. ?+ }5 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" m3 s( v' h) W3 B$ ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. J% N% W4 D% j: L) D7 I& ^| MCASP_TX_CLKFAIL
' I; _8 L2 U. h| MCASP_TX_SYNCERROR0 H$ v0 u+ _& d7 X- x% |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 F2 t. t; L5 s: @; v
| MCASP_RX_CLKFAIL
7 P" C4 J# Q, p| MCASP_RX_SYNCERROR 4 S2 X# ]5 W7 y5 ~# N
| MCASP_RX_OVERRUN);7 n* m4 G6 I$ I0 ? {
} static void I2SDataTxRxActivate(void)% Q- R8 k6 C5 P0 q, c. R! k/ J% I N# u
{
* h4 Y2 z6 j" ?3 N% F4 m+ L/* Start the clocks *// J: Q9 A6 o _& @7 |! I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( H$ n/ c' Q) w7 E/ t9 U( t3 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, N0 ~8 z* I& Q% I% i2 l* H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ ]9 C( W2 f9 l8 V
EDMA3_TRIG_MODE_EVENT);
7 B+ E! @1 ?4 C" L/ o$ n; JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 G# V# J5 k; v" m m' j! L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% g: ]) M0 ~$ S) G. _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& H2 `- ~# n( Q, V/ X% v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% F, H/ Z+ s5 V" [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ D$ g% c( v- g- t0 R7 o, X. }, IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ \/ Q) T1 ]# y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) f. l) R# A& v4 s9 i. s; Y' ~
}
! s H- a( A- Z: m1 D# I/ W/ v9 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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