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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; L: a# Y' {: vinput mcasp_ahclkx,( Q" I$ y' M5 Y
input mcasp_aclkx,) j+ ~) N! U* a; H% v! Z9 H0 c# p2 x9 T
input axr0,
: i) x4 a1 {# N' U; X9 h5 J! \3 `, S2 t5 z+ v
output mcasp_afsr,
2 e3 |0 w$ I2 n0 K2 N" s$ \9 voutput mcasp_ahclkr,7 Y) H, G9 v. Y0 U
output mcasp_aclkr,7 c, F. K1 a8 q5 Z5 M
output axr1,
, u6 D5 ~$ d4 l" C9 {) ~2 e, S assign mcasp_afsr = mcasp_afsx;+ [9 h2 Q6 u1 r
assign mcasp_aclkr = mcasp_aclkx;& M' H! ^4 ?3 c" T) A
assign mcasp_ahclkr = mcasp_ahclkx; ?- G! t* s1 V3 E: W
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! D; d1 ?3 ~/ m9 d* s4 L, t
static void McASPI2SConfigure(void)% F2 b! N9 Q7 x- F8 D4 I/ J
{" e( b) i* S" S O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ r$ L0 Z& x- @; D% z k' e/ kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 V9 X8 r, ~% I' z, ~# p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 ?# @9 |( J; H2 I k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
T/ ]3 v# S _+ \" N+ k. OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ q: W( G2 c& V1 g" D+ u) ]- Y, _. h
MCASP_RX_MODE_DMA);8 f8 g* F( h& j/ q6 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 N( e e# S- W0 B/ Z7 q' G* P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 _8 S/ w2 O1 G& WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * c3 _4 P; o( @0 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 l2 X, B! N, ?# }* x2 m2 \ B* j9 Q; |; pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# |; K; W) [/ N7 c( QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' {# V& {1 k8 n; |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 L2 J$ d; Z% \5 B. L' UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ]4 S/ ]2 Q. h( H3 f5 W. f/ _( V& u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 B6 l7 `: O" x( }. f A9 e0x00, 0xFF); /* configure the clock for transmitter */
9 @3 b3 f# f& }, R, DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ \# ~# U; g% y/ K* s+ n) N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 U3 O: h% j# ~2 S. g) S. z7 L" X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" @$ F5 w# M6 o* ^9 e# F0x00, 0xFF);
& P- o! P5 g8 A f8 s& y
1 [7 f3 x5 k0 W! I: f! b8 V* ~5 j, L/* Enable synchronization of RX and TX sections */ % S$ n# W! }$ \2 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 p0 A# {" S6 Y. ?' sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 _5 L) F* [( w& j3 t" x; q* m$ [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 f& z5 e% a7 _3 u( L: J) `** Set the serializers, Currently only one serializer is set as# o7 V3 E2 D( u$ C+ ]
** transmitter and one serializer as receiver.1 w. h$ E7 n, s- w5 n/ O: R
*/" u! L5 i! q; F( ^- M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 n8 R; C5 g8 }; B: {2 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 i2 }; Q) s+ K6 o& I: `' |** Configure the McASP pins $ F8 H7 ]# t: R4 v/ V7 p7 N1 w3 b
** Input - Frame Sync, Clock and Serializer Rx
6 M2 g- f3 Z! W+ I3 s$ P. m** Output - Serializer Tx is connected to the input of the codec
: {& ?( O# u8 ]- y/ E*/5 F: I3 m/ @+ e4 `2 O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( B' D" i0 ^. [' Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 e! M, d: h2 d# M, ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 {6 j9 i" D# f8 [| MCASP_PIN_ACLKX: A/ S" ~1 }1 ?, b- |1 e
| MCASP_PIN_AHCLKX5 j3 Z+ j1 r+ f3 c# C4 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' c% f' V, o5 O8 a$ aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 j4 [+ S( t5 }2 X! @8 T| MCASP_TX_CLKFAIL
, b' P: W! z+ h( {2 s5 @| MCASP_TX_SYNCERROR2 ]0 ~/ O& G7 N& H" r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& V9 |3 [: v" m| MCASP_RX_CLKFAIL6 M! s4 N+ x' ~: h* H- n" D3 I
| MCASP_RX_SYNCERROR # b& c) X9 F* P- c; l7 s% v- r' J7 U
| MCASP_RX_OVERRUN);3 d+ D& K$ d8 l+ A
} static void I2SDataTxRxActivate(void)
; X( i7 K2 Z$ @& q/ V% n- b{) H4 O) v/ w8 h7 H) A4 R+ v8 k
/* Start the clocks */% }* t; _& K. s3 z8 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! _2 F$ q/ N% w0 I) E& j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" ?) T% _2 ^, I: T! B! A7 B& w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 L, p# S7 R% ~. `& C4 ^4 y9 ]EDMA3_TRIG_MODE_EVENT);
_: s/ S1 N9 w+ a5 n2 l7 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, e4 r% L# w3 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 o ]! V% D; g {6 JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- n) \- z; m2 g S2 E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. f6 C! K+ L) V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. t2 I% x8 h$ O! _9 W8 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! B" z' I. l B1 n7 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 [& G9 L( w& b
} . S/ }8 K* r" g% j% E0 ^$ d3 y* H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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