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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ V a( E7 `- |1 p/ I5 i% S
input mcasp_ahclkx,
2 K1 u4 N) V5 n* ^4 q9 ~3 @input mcasp_aclkx,4 {" R" u4 T- F: [
input axr0,
6 |2 [' @0 P- S8 C" a6 t
/ \7 r% E! _$ C6 a# }! p5 soutput mcasp_afsr,0 y! n$ [& F3 y5 C! ]
output mcasp_ahclkr,) Q" \$ o0 i! t
output mcasp_aclkr,! }5 \6 v* }- f! n4 \
output axr1,5 W1 Z0 C7 Q. L9 X7 U+ H C
assign mcasp_afsr = mcasp_afsx;5 c5 O! ? Z0 z- x
assign mcasp_aclkr = mcasp_aclkx;
( K; \- J6 R7 T1 _! P7 I' i0 ^assign mcasp_ahclkr = mcasp_ahclkx;
+ d& j, n; Q; x% \( kassign axr1 = axr0;
0 W0 P1 i$ w& \/ C! o# h# E/ O" C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& q9 ~$ ~7 m) z4 ~* M: xstatic void McASPI2SConfigure(void)6 W5 G" p! a+ o
{7 n1 e \" O* }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% M: N) ]2 F9 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 g' I; a0 c `4 r6 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 H5 y) F; w C n- y6 F% y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) X* G$ k; u- {/ J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 e7 ]$ \; H& o. S& d* l) u zMCASP_RX_MODE_DMA);
$ h% l7 t* H1 S3 S0 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, n# C: a# a% }+ \ s! D0 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; [; B9 [- z' J- ?, F. mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
A; d/ U: v Z Y' B [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# k* G" I; E; d. d$ z$ I L0 O- ]! k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' A* m& D' f" P5 ]( ]% v$ S- b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; y6 W* y+ a( p( R8 L' HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ T- E6 `, w. \/ @" h! uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' g; H) T: k9 K/ C0 W- B* _# vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ~% c9 j) K; j9 v0 @" ?
0x00, 0xFF); /* configure the clock for transmitter */
$ ]6 b9 q! \! P6 j# y" H$ A- A0 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, {& X% m$ m$ a" C& kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ C$ d, C) z) hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ U/ u9 n! |# G! P0x00, 0xFF);
: c0 y8 H' v4 n0 I4 W$ c& B' E7 S
2 c* z3 ]$ B$ M: Q# t/* Enable synchronization of RX and TX sections */
% y' G8 [" _4 \, N: a! v bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 d( N) V* F% V9 D0 u$ r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- |( M* n9 c+ W) G# y- @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 E5 ^ Q- o/ w5 O7 Y; A
** Set the serializers, Currently only one serializer is set as
9 q& {8 i2 F8 O" u: G** transmitter and one serializer as receiver.
" P2 H& e" H' d5 Q0 F6 ~*/
# d! ?. b/ Q0 H9 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 D a, G( s) c5 U% ~0 o Z0 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 l) L) l, C9 P( i c
** Configure the McASP pins & b$ [# e$ T5 O# v1 n
** Input - Frame Sync, Clock and Serializer Rx
2 E$ F' o( }" T$ x, y** Output - Serializer Tx is connected to the input of the codec 6 C+ C" A8 y2 q3 J4 O" e1 l
*/8 o& U9 t! Q0 D; U9 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; W' m5 S) u+ J& A ]' x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; W. Y7 A" x9 ]1 W5 D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ B6 l4 Q$ w" Q$ d7 @* l; P/ |0 M| MCASP_PIN_ACLKX
o Y6 B% Y/ C a8 O| MCASP_PIN_AHCLKX
! v! W- n' d! A _: Z, K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- z" @5 Y( A) p" X1 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% k. d9 J+ J& W; A4 t| MCASP_TX_CLKFAIL
" n: i/ H/ Q. T6 Z2 L; G| MCASP_TX_SYNCERROR* Y, a/ w( i! P8 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 t) |9 P8 d+ p' }; m
| MCASP_RX_CLKFAIL: y, ~/ {: C" `1 y) g* a4 k
| MCASP_RX_SYNCERROR 7 k, H: u# c8 D# o
| MCASP_RX_OVERRUN);9 g& N* {; L' D7 Z$ x
} static void I2SDataTxRxActivate(void)1 @( j( c, [$ o- D* J+ d- }0 |
{" D" G3 k9 [9 A0 p. B6 X- P* D
/* Start the clocks */
7 Y+ k* I, E9 e7 L! q% }/ o7 m! @. nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* K- n* t' m+ t! b* iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ K/ W# X7 `$ i" N% f$ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, O: ~; j. k& u' [5 F# B
EDMA3_TRIG_MODE_EVENT);
: s+ u$ z/ i3 H6 X9 T; [0 I% a0 c Z9 o6 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 G/ A, X2 x2 C9 s2 ?) f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 }( U- P2 c5 I. u- b9 v' f9 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, c+ O [. W& x! U3 K* o6 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; f! S5 ^! Z M7 u, Z5 C4 h0 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 F5 Y+ J. `( p+ I0 `1 K9 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! b3 `1 D/ Q6 L- Z' e5 P+ h* e& D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( C8 ^7 G: R/ I8 t
} + x0 A0 M; E/ F2 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; b) N/ P% Z" S, w
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