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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 N8 ~- {+ ~. f- L; M& P% K; uinput mcasp_ahclkx,
! W \, y# q# s7 hinput mcasp_aclkx,
9 V, d- d* Q3 w' ninput axr0,
+ z5 L% Y. n! j( C- }
3 \4 x( i9 z5 Doutput mcasp_afsr,
! N/ V3 l/ W D* P+ q- Loutput mcasp_ahclkr,* A8 W# o5 I/ _4 _1 u; E1 t
output mcasp_aclkr,! ~* |! K Y) V h! N. a8 r/ X$ D
output axr1,
m: _4 Y# y& C9 y9 j assign mcasp_afsr = mcasp_afsx;
7 [- j2 F! }' }' _: w1 Kassign mcasp_aclkr = mcasp_aclkx;
. T0 f: F9 b9 d- V; f! y. U; Y7 I- aassign mcasp_ahclkr = mcasp_ahclkx;
0 g1 p) e* j0 Wassign axr1 = axr0; ( r2 E; J# s$ [2 Q4 ^6 u
/ T5 m: G' g4 C( P+ R( Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 g3 l( H7 ^( c
static void McASPI2SConfigure(void)* w8 B9 P7 K& E6 ~
{0 C1 s% l2 H/ K7 u5 Y& k* f& A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# v2 v/ n2 N2 ~: N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, z! j; l3 C: v0 `" _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ `8 N; R! n) }0 \2 y; AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ?( d; Z' S9 q3 x7 @- T r' w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 A$ ~- \6 M* j3 V3 g7 f9 ]5 jMCASP_RX_MODE_DMA); b( J' v, I, U/ e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 r7 u' j/ J" a O* ` WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' D/ C) ]4 b _1 o% |0 Y! x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& N* s5 L1 _2 M2 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ W0 @" \4 R6 U- X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* t* U& t9 @: W4 l WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% i5 u7 \# J2 S/ ^8 m$ M$ e/ aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 x! ~( v# j3 l! g# S {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 E1 B5 M* u. W' o& A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 u+ g* g3 j3 X' b- x3 q; V
0x00, 0xFF); /* configure the clock for transmitter */
4 W8 E2 a: W+ _8 W, h# `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- K$ s h" n9 n I0 ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# @ l i! A/ yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," D, a" T1 c5 Q; H& w: l( L
0x00, 0xFF);+ D0 y' n% y3 V9 d8 N' Z( I: u/ B
$ U( C, {7 e% y" y( x( b2 O* P
/* Enable synchronization of RX and TX sections */
, C3 k1 \' E* C2 X3 `1 N$ W t( T, TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" @( f4 u$ D; I- EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 y8 h% q# c3 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 S5 T1 l4 ?- M( T3 B4 k- F Q
** Set the serializers, Currently only one serializer is set as; C! `1 M( I9 O8 q* b% d
** transmitter and one serializer as receiver.4 M. ^* [7 v {! F- V5 n
*/8 [, }- S/ d2 T8 i" w+ u$ [5 ]/ i9 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* [! B* z; K; M0 n- w. D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 f% J- @ _$ T$ U
** Configure the McASP pins
2 z/ S2 z4 j" {. }* G3 w** Input - Frame Sync, Clock and Serializer Rx! `2 w3 J2 o/ d* T/ R
** Output - Serializer Tx is connected to the input of the codec
( I z1 E5 ]9 V, ?, {*/; m5 s$ _7 s1 {2 W' ?) ?! m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: g5 [/ G S) `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 [1 W% J% P8 i5 YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* _7 S( P' s9 D( l! G1 f m* A
| MCASP_PIN_ACLKX' C" B- c6 n: k( G; L" }: B; h8 ^
| MCASP_PIN_AHCLKX+ l v) N3 o5 ?8 j& B: E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 @3 w9 o" \; c- j GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; r6 C; H" m: ?# s) I, n2 ^3 v) V| MCASP_TX_CLKFAIL 2 C7 \8 G; z# c" \$ M
| MCASP_TX_SYNCERROR0 X7 B. p3 H! ~" y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ X5 d- g* a- f/ \: \, k$ o! @| MCASP_RX_CLKFAIL
+ T5 x, Z! W5 C' B# || MCASP_RX_SYNCERROR 0 r1 O, O+ b) K" N! k
| MCASP_RX_OVERRUN);0 R3 Z7 D9 i5 \2 E
} static void I2SDataTxRxActivate(void)) e, \7 `; X' u4 j+ l( U
{+ T; B5 P Z5 j W! S6 d
/* Start the clocks */! d* I: w. `/ p$ t! o. F! {! }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 Q$ j; P" Z9 Y+ B- h. s. {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' C& T4 K; A/ v: ~2 I$ E, ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, `# \" v q" b, d: |5 \- OEDMA3_TRIG_MODE_EVENT);; b G' S* b @* d- P# s7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , @) `, \+ b" q: G# q" F _+ {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. q. A0 h6 X: f- K3 G& [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 a K% \+ u# _% A- o; c# h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* N8 W: e2 \5 B6 X- bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ y; b+ v& X5 M( e6 A. d- z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 m! t" ]. k$ y \" M0 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 P1 \+ T& r. L}
; o; Q0 C4 i# U0 A5 J- p& l( x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; \4 h( {4 P p- w0 M/ {6 Q8 {
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