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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 \- b5 F1 q# o
input mcasp_ahclkx,; |' ]# J' O+ H V7 g0 F# c0 R
input mcasp_aclkx,+ }+ j/ e! L4 c {
input axr0,. N. X2 o; @* Q/ F7 n
4 Q9 E, R8 q! y) @output mcasp_afsr,
. C. H9 t+ R0 soutput mcasp_ahclkr,
; M( I3 `* C4 F# toutput mcasp_aclkr,
% ` {6 R5 V3 p4 P( soutput axr1,
I! w( b# I/ e3 Y* u assign mcasp_afsr = mcasp_afsx;
# h# \3 n, m( _# J. Nassign mcasp_aclkr = mcasp_aclkx;8 t& J9 W" O Q& ]/ j% Q/ Z
assign mcasp_ahclkr = mcasp_ahclkx;
) J8 |, m9 G$ c4 v/ kassign axr1 = axr0; % p* W% U0 _% t. M* J! E
B! |) q7 M* G6 r: ?0 ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 R {- D h4 |; g/ n" ? ^
static void McASPI2SConfigure(void)1 Y* d. G; E6 N0 [+ k
{* Q! }1 \6 ]* j0 e7 |9 M g0 C2 o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 g. M2 w. G3 Q) C# V* xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! \5 e5 D0 K- s9 ^" x* w$ _: h% Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 E1 h8 c5 b. Z& n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; Y: N, Z1 x/ o8 `( ~1 y* ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 W9 k% y6 o( R& s/ k kMCASP_RX_MODE_DMA);/ S& E3 x+ P6 i7 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( Q) \% L1 ~* w1 [, N) F3 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 ?* \1 n W# d1 ^" Q" d9 t. yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 X* S% M, x8 S+ [2 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 J0 }% Q, c- K5 ?) \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ]9 C1 V, T+ CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ y+ D! p0 j p, |' g4 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 M- }& f/ x8 k- [0 m' R2 H, _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 m2 f. E: |; X% {2 _" ]2 b) T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 \- |1 n. _5 [+ P: G- z$ S
0x00, 0xFF); /* configure the clock for transmitter */; |0 M3 W o5 P! I& @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 i& X2 M7 l! _- }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, q( d- s& B( t+ KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. }! I% u3 R. d: c
0x00, 0xFF);* S+ }! O5 \2 f$ v& t: }+ [
R5 E/ D% `6 J' i E u5 [/ Q/* Enable synchronization of RX and TX sections */
. J6 w+ C8 N# [ n( c$ OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% r+ C$ o! ]9 t4 F bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 t# _% s( z6 ~/ J. k) H% U+ PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% ?1 |0 s3 n5 T6 x& p** Set the serializers, Currently only one serializer is set as
1 f/ o$ ^! z2 }** transmitter and one serializer as receiver.
- J) X5 e* _( `$ f*/
: `1 _$ p' y* N# P, e8 h& q4 V- iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ M) ?: f) l3 J; S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; @! B' U5 }1 {- o# a2 q( Q" H** Configure the McASP pins
, v& L; i% x3 u Z+ ^1 M# o8 a** Input - Frame Sync, Clock and Serializer Rx
+ y- p5 e# k8 @0 I X5 v4 l** Output - Serializer Tx is connected to the input of the codec ! k% N+ ^, r3 C* E/ |, P0 U
*/; V* X+ E, E1 X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) @7 g# K' ?! `1 ]' {; b* VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) W3 x- W& K4 m1 M3 W( @% o& }$ ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: Y9 w1 i- r$ K5 r. W% T9 `# o" r
| MCASP_PIN_ACLKX
9 m5 t/ o4 g$ M7 _6 w0 w| MCASP_PIN_AHCLKX0 U! x l* o9 p: {" P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 `4 I" \' @. I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - f/ l3 N; G7 W6 X& C: U
| MCASP_TX_CLKFAIL
Z2 Z2 \) e. G7 v5 [' M6 b| MCASP_TX_SYNCERROR
* [+ y1 i) l0 m9 K+ r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; k' q" @5 c' z: p| MCASP_RX_CLKFAIL
$ _* h/ T9 z- f3 N| MCASP_RX_SYNCERROR
* w4 h9 Y2 s+ @| MCASP_RX_OVERRUN);7 _0 `: K% V' ?
} static void I2SDataTxRxActivate(void)- S8 V2 `6 j7 s: i( r
{! [; f! p4 M& ?3 k4 L/ z1 S
/* Start the clocks */
5 A% h/ c% ?/ F9 pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 o1 ^# n& r9 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& T* I& e3 q2 V' z! q" c8 b; n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; X1 L/ E2 O H* X% L6 M8 n; v& F6 sEDMA3_TRIG_MODE_EVENT);
6 S6 }+ G, l& S$ Y9 E1 X# T4 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* V& U& I; B% D8 n$ ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" N5 e% N) p# o$ X- J% C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 R. d. I% c1 A" |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% \+ t8 q& z# F n# o/ uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# K) t8 w3 N, N. P+ m! a/ n R* ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 e, T; B; E7 R0 ^" Q" F# o1 ~, q; fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! n) f+ L$ D( c9 B
} ; U3 ^- t: N" u4 o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & X5 G1 B4 C# I$ Z1 _; i3 p6 K1 w) C
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