|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 H7 U0 T8 ^( C% S
input mcasp_ahclkx,6 w) i2 `, h$ J) t5 R9 C4 I
input mcasp_aclkx,
. N0 w- L- \4 j9 _7 _& ]input axr0,% D" n2 ~3 w1 r0 D4 y
8 \8 r0 K8 K' w; j
output mcasp_afsr,
& ~( C% ~, W7 ? h! foutput mcasp_ahclkr,
; X, i& `3 h$ o' ~9 Loutput mcasp_aclkr,
; J6 \& v5 W$ l: Eoutput axr1,
+ f+ o: f3 q! t) B2 X assign mcasp_afsr = mcasp_afsx;
- m6 e1 L. E3 b5 P0 w: I8 i; T3 ]! ]8 R! Cassign mcasp_aclkr = mcasp_aclkx;; e5 R: E' K, s0 V' H2 Q+ H
assign mcasp_ahclkr = mcasp_ahclkx;
: R) D6 Q1 w2 Bassign axr1 = axr0; ' [* o- [4 d' w
- x9 y8 O9 o+ c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ^( n$ |; o$ ~+ U" u+ }( z& a9 r
static void McASPI2SConfigure(void)- q- r! k& H- b% o2 C
{; S8 |$ j9 [$ U) Z0 E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Z7 A6 }4 u1 LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ h$ N6 W/ i! S# V3 ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 z+ _. [6 P) O" F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 p/ |2 g, y) t/ p! lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ w5 b, V6 s. B, w0 u
MCASP_RX_MODE_DMA);. ]. R/ F3 z/ Q0 y; t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 p$ B8 M* w; }( C( }! T: }, Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 [1 T; s7 J% r) Q6 Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: e' X7 i' z5 |. t! c. P1 M8 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 x, n z: @3 l3 K! |( M ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 Z9 @. X1 H' B( b% {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& Q; B5 e/ u, r( w+ q; A; D3 `) U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 m: U7 A9 x, P* i) F! N. \" B/ N8 |/ rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 P. s- f- A9 w. u4 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 k& _- b9 N. ^* R0x00, 0xFF); /* configure the clock for transmitter */
; p- q1 e7 M& S( ?+ v7 D3 K! f& QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ S- ?4 V8 r/ D$ R: t3 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 } j& F# O5 p, O% v" jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 N0 h8 h1 E0 l0 }* U% b o* a
0x00, 0xFF);
" D' Y) k2 ^) i6 u
+ i: u" g+ Z: D+ o8 ^: s/* Enable synchronization of RX and TX sections */
) l! B) I5 e3 f" c) K" i' fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 l( c1 o) F, w9 _' T: XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! U7 \2 [* E6 [# T& }0 _% oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! X) t; b" x% ?2 ]
** Set the serializers, Currently only one serializer is set as4 Z7 Q+ u: [- k" s
** transmitter and one serializer as receiver.
4 }. P) k) L% y \! H*/
' b! b3 W/ o1 j; LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( ^7 `5 ]) p0 S' H4 i4 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 U5 c3 T) T8 ^3 h$ X- n# k+ I1 b; _
** Configure the McASP pins 4 R7 a! c* M8 |8 E `5 U5 b& P
** Input - Frame Sync, Clock and Serializer Rx# V W6 k5 y" M) j) c0 D
** Output - Serializer Tx is connected to the input of the codec 4 O7 V6 A+ \3 y: u' }
*/
! |6 B3 c" |' N& b7 Z( H7 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ^' s( E% J) gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: N+ w" w* F" Z3 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) y3 h* Z1 M3 D8 k/ C| MCASP_PIN_ACLKX
- Q% F% E; `+ Q* ~ F% ^5 x. C| MCASP_PIN_AHCLKX
. |6 K. i1 [! x5 O" r/ B* P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( B( Q4 J8 n! b4 h" Q' K$ l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! A& t1 C5 p4 D" Y
| MCASP_TX_CLKFAIL
% t9 Y0 ?5 X" ~6 e. a7 r) G8 @| MCASP_TX_SYNCERROR
8 w b1 s; h1 ~8 M4 ]) J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 a: l* V% z- p6 \+ {9 }7 f/ e1 Q* I| MCASP_RX_CLKFAIL
+ |( T$ L5 Q+ b, }+ Y0 U| MCASP_RX_SYNCERROR
. ?# t t8 m$ i2 d4 o| MCASP_RX_OVERRUN);. h8 |3 y. |6 c- y7 d
} static void I2SDataTxRxActivate(void)- q* l( Q$ `" M6 M( ]" _& f( w& r+ ^
{
+ {! [' z9 m9 K/ m/* Start the clocks */
9 i9 I6 q4 |: R9 l. _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& u+ x! M- @3 x7 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, P: b" E) V; F# v0 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- Y. M4 l4 T7 A3 |: f$ x- r
EDMA3_TRIG_MODE_EVENT);
0 o( j8 g' E( A) R! ]+ @( o" AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 @& d! W; F5 d9 k9 h) B/ OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. ?6 {+ L, Z( S- qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# z/ T7 b$ r% x# q" j! U% n" V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ ]2 r K' C$ ~9 m' g/ f5 V. i9 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 v8 p5 u: M( |" u- i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& h% ]+ D; |5 i3 i! ]. d7 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, r; j& I x1 }# z
} " |! _& R) T9 `/ D1 p3 P1 @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* J# s5 V5 K1 Q2 ?" M! S |