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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* s( W8 P4 ?5 y) T2 i! q
input mcasp_ahclkx,1 x& p/ R! t2 E% v
input mcasp_aclkx,
- U! E3 R# J/ D& v8 o8 Q: G- Linput axr0,$ P2 Y( ~$ o5 H
5 @: |3 Q9 g& I4 ?: a- i
output mcasp_afsr,- C, E" `, T8 {2 ]6 X
output mcasp_ahclkr,& k$ _5 c' O; c1 W
output mcasp_aclkr,
# v$ j' E6 F8 E2 i* p) ]output axr1,
* @2 O: M ^. o3 b$ K" o' d assign mcasp_afsr = mcasp_afsx;" D1 A% U0 L5 @4 ~, j+ |9 z
assign mcasp_aclkr = mcasp_aclkx;
4 ~+ Y4 S) B1 U9 S0 `0 Eassign mcasp_ahclkr = mcasp_ahclkx;% x9 |- [& _# n0 F
assign axr1 = axr0; 1 d9 Y" A) p4 R3 k+ q7 }
I& ?" I" x" j" L P+ \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 p3 I6 ? s, L. c- z
static void McASPI2SConfigure(void)
, Q/ ^0 T6 s& ^/ C{; S6 a! C* l# E8 Q- u) M2 m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" o1 d$ X" M6 {" c0 _3 ]/ FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* j5 j/ m. \: @' ]+ ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 ` [- v4 Y# T8 G, i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: V! C: P, I; k+ ~( e8 X# ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! w d8 R8 p5 t3 b C: hMCASP_RX_MODE_DMA);& M# y8 K1 s2 p& J w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# r* h6 E7 s9 F9 n# W; G' |) l% PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 u% z8 U9 t/ s! |3 B# N. f" A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 w0 [) x8 |$ B" [ L$ zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" P2 }6 Z z' G B% A2 GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 s% q8 c- {/ v6 f" c# g c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 z& |( O9 S1 `) a! c( Q" _9 dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 P( c5 w, Z% N1 }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: M( @- P* ^7 H' l5 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
H. F- \8 w* P0x00, 0xFF); /* configure the clock for transmitter */
6 K+ G& X6 @4 d. J! C3 XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ s1 M# C7 M9 C6 SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! ~) ?9 p4 T) jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* T8 }' _) }2 s! J9 k0x00, 0xFF);" [1 L7 |" I3 V: C9 I
6 e+ ~- E7 d" s
/* Enable synchronization of RX and TX sections */
6 q% C; r4 [' p9 S OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
o, b7 ? ^) R- }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. G/ h! \ f& H6 f3 W" }9 N! [/ QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 M: [8 g d- I** Set the serializers, Currently only one serializer is set as
# {4 P U' p7 n0 ]** transmitter and one serializer as receiver.( W/ p s' [4 W r1 p
*/
& J7 W N2 o3 {7 j% Y9 G" zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- d$ u7 r' N/ R; JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- K0 i3 F% ^ R! o7 k. N** Configure the McASP pins
& F) g, a, a [: ~* i1 `' b** Input - Frame Sync, Clock and Serializer Rx
, R B7 Z2 p; @8 N( k! j# S** Output - Serializer Tx is connected to the input of the codec
, `/ _$ K2 ~' x, Y7 k8 [*/
7 ^& c/ J& K7 b$ H1 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& J |3 L9 [, W$ i, X! m9 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); j0 h' a1 y9 D+ P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. b0 p5 C+ c# h9 i" X/ W* r, E* z
| MCASP_PIN_ACLKX' E0 d/ ]+ ?9 D3 A; n
| MCASP_PIN_AHCLKX7 `; |$ x& I" X0 T' a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ X' x4 {: i% X- o4 i1 Q; S$ nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! T' E: a, v) h2 d; X| MCASP_TX_CLKFAIL
5 W/ s% P5 P0 J8 U| MCASP_TX_SYNCERROR6 J* H6 d$ x7 T8 R7 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 b- p, @6 j* t3 V
| MCASP_RX_CLKFAIL
/ B* B9 i- G3 X5 F| MCASP_RX_SYNCERROR
* p# b' s8 q- n$ [+ S4 K8 q| MCASP_RX_OVERRUN);% m& g. K- x( _$ Y& G4 o( Q+ O a
} static void I2SDataTxRxActivate(void)1 H8 W" C$ d# e7 ^) Q7 e' G
{
7 w# w, y8 C, ]/* Start the clocks */* ] q( Y, W: |. p% ^5 P& a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. D5 w/ W. `/ O; oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( ?2 a4 ~% Q- @" N3 n' u% O. G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ i' d# P& v% ]1 o% V4 ?
EDMA3_TRIG_MODE_EVENT);
( J4 M7 `$ F- o! D; o- XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# T: u. w: J1 A# E8 C3 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 ]3 A- D4 a; Q3 T+ g1 T& H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( A# v+ Y! z: @( @/ o0 R+ IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- f# j2 |8 ~! K9 _$ m( p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% s5 N" n! {, g& b5 W- R6 CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 x7 O6 G: _" z; E. r4 ~) ~2 X7 K8 T& k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: r" ^+ u7 q3 W}
( N" a6 C* k! L/ O/ o( l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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