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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," X/ z% C: h; z" e' M2 C( Q
input mcasp_ahclkx,
; Y" V/ D# e8 s$ k6 Hinput mcasp_aclkx,
% `4 l/ ^8 |/ L: o* d& ^$ O/ sinput axr0,
, s' C: } _ f" \2 w$ g; `$ C3 H5 n1 }! A! g: j( c( l
output mcasp_afsr,
4 q0 f' D* t0 G; P9 s8 l% H. `& ~output mcasp_ahclkr,4 `+ {3 F& ^! @, Q% B$ l# y
output mcasp_aclkr,
. M5 a. ?7 e! [, A s( Aoutput axr1,
- `' \9 K7 `8 {7 z3 W$ q3 k assign mcasp_afsr = mcasp_afsx;
5 ^& H7 z9 t" S% c( G1 n1 V6 gassign mcasp_aclkr = mcasp_aclkx;9 |' F) q, f: O0 r) H1 ?& x! X+ v
assign mcasp_ahclkr = mcasp_ahclkx;) w! \- P' M* O4 \
assign axr1 = axr0; : v( a, p* _+ l& U; g$ o6 N3 r
! j: `$ c8 x: n) e3 I' ]8 l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 K! ~& A: M: c7 d& k
static void McASPI2SConfigure(void)
1 `! R3 M- k( f{
- b$ P& \& X: BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, n: g- i7 c: P- @$ v! N3 J3 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- H) r2 Q# P8 H) e, ?7 m0 ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, }1 B) u+ q/ {& ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 R2 K! [. `6 v6 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; @) ^+ T, R/ Y$ I+ i9 [9 }5 D
MCASP_RX_MODE_DMA);
7 @6 z. X3 \8 {, c! J a( }: RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) J f( G& t1 ?$ d+ ^2 v' zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 N) |' G6 k- g, Y" W) D1 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
l( b7 {5 Q/ U( bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. D8 w" B2 b' l& U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - u) ^6 }$ ?! Q6 z7 A8 s7 {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! |4 k: d, K2 O# Z t2 F/ qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 D* B1 R0 A: OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: r6 w1 v8 ^. OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. o' g$ C7 Z4 b% v- l' }
0x00, 0xFF); /* configure the clock for transmitter */
9 ]) K* _# d0 p3 wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% r& e9 J. S$ R9 I' W% ~/ H# l' tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ _$ D1 ?+ i: x n# kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 m2 q* b) }% N; a3 ]0x00, 0xFF);5 ]# H% E* r/ H% r
: |- l- S% c h6 @3 o$ L: i1 x- C
/* Enable synchronization of RX and TX sections */
7 R' X$ U5 l( ~8 p4 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; p+ m! Z: k$ A `$ `+ T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Y# e+ a7 j1 x* _* `. A2 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, U; S6 D7 a6 A4 A3 w** Set the serializers, Currently only one serializer is set as
: _0 A& q9 P3 I6 `3 [** transmitter and one serializer as receiver.5 P+ Q2 {: u" S# G& S
*/; S2 \, `" g2 ]# f% |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& B. h& V# c: q8 W n! ]$ b) RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% i |4 Z' W- X5 _- h
** Configure the McASP pins , x" p7 H' t( b* W. U* u
** Input - Frame Sync, Clock and Serializer Rx) E1 K& R/ Z9 p) B
** Output - Serializer Tx is connected to the input of the codec ) O" p! `+ z2 a7 F2 u
*/
6 \& k( t3 R; ]. F$ F6 r* hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 c7 N: I; g2 P: o( V& F C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! V: |$ t2 P. k9 }$ QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# W; s$ G! c; g7 O" O
| MCASP_PIN_ACLKX
% r' F0 N2 [! `7 l9 L| MCASP_PIN_AHCLKX9 p' y% d4 m6 \, D" w* g) r/ D( w* n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* Z2 u' v- {6 ^# l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! H* |2 Y1 s* k [* z/ x
| MCASP_TX_CLKFAIL
: c/ |9 n( Q0 j( u) b6 M| MCASP_TX_SYNCERROR
- a) ~: L3 R) W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 z2 M2 a9 F: _( e6 |1 U% n9 V| MCASP_RX_CLKFAIL
9 j9 }# l9 [* P% I/ f! w6 |( d3 G/ ]| MCASP_RX_SYNCERROR
! K2 R. |2 ?6 S: C0 O9 h| MCASP_RX_OVERRUN);
$ D3 ], O8 @1 M/ X} static void I2SDataTxRxActivate(void)8 i: M+ a* H, z# l
{
- Z$ N7 N s3 e E' _2 J, _/* Start the clocks */. R% q8 b5 ]# k3 @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( Z# B; |1 x1 j( jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( a6 k2 y M. P3 j+ n3 V) D/ M3 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ i$ C( w9 D2 a8 e, @
EDMA3_TRIG_MODE_EVENT);
5 S1 T3 R* D q' J( G' FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) Q7 q/ T0 ^; y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, p9 w% v: y8 D/ @) L, B. k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); Y9 l4 E+ r0 z: V' v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) C; |. m6 P) u2 P* m7 S0 W% e: @0 Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ H& N) H) x: X6 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( f% F J* z5 J8 @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% M6 n. y) M/ ?' Y) W7 G
}
8 t% Y0 V) g7 h" |( }; Q0 q/ a! Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ g0 X$ ]7 n5 c; ~1 Y |