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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 A+ x' u/ f8 ~* I
input mcasp_ahclkx,
" Q5 q2 Z6 K& n I5 A$ ^& s o cinput mcasp_aclkx,4 D& b, t9 q% f2 s: ~1 I
input axr0,3 B2 K. a1 i7 x6 \! L$ w
+ d1 F* b# _2 r' X( t4 [! B- r {
output mcasp_afsr,$ }* X/ ?. ~2 i- ?
output mcasp_ahclkr,: M! H5 w2 z+ Q1 \3 q, W, t; k
output mcasp_aclkr,5 f& A0 E; t/ W) J: _: F* |5 j' S6 n
output axr1,
1 O! `$ e8 G% `0 d9 @' y, ]7 ~( D assign mcasp_afsr = mcasp_afsx;
1 R* p2 f5 x7 o# `assign mcasp_aclkr = mcasp_aclkx;
% E& p7 t3 ?; V2 g) E) ]& `" S( ?assign mcasp_ahclkr = mcasp_ahclkx;
, O; }; ?2 b) z" r! ^7 }. uassign axr1 = axr0;
% P% w+ g# A3 \' i5 H
' e# k+ M4 Z/ B1 ]( w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 }2 n4 x3 W9 e4 \) X$ ?static void McASPI2SConfigure(void)8 o% W- I- `( F- H3 Q, |: i5 R4 `
{0 R( h1 X# ?' F; g6 X( s C5 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; `- v1 V. ^8 i( [1 f% cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" d6 ^ G: Y$ n( ]8 i! ^) {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& }& h# e; p3 d# G; ], A7 F3 }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 _5 J, N8 q9 ~/ w1 j* @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ L& ]# I% E$ f9 `MCASP_RX_MODE_DMA);/ b+ \+ E `/ E/ U' G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ m" c# j$ _6 p+ N0 z& B( L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( ]5 p) p3 V/ QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' D! `5 ?( J% V; G! H; X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ T! Q) ?/ R' q& L7 d# C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / S ` a3 h6 G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 _( c5 ?, o0 l' a& A1 e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" Z0 R! A- ^4 x1 [4 P6 I9 G: i; {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " m2 p. w+ z/ f/ ~9 Q( g& ?( `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 _! V K/ C5 z. L! M
0x00, 0xFF); /* configure the clock for transmitter */: C$ b0 s- `# o% n1 s0 b& A; A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% c/ |! R; r$ z& C; \ p- R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 V' k3 c' y! Q H' FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. R. ?" T5 M$ J( V. B' r
0x00, 0xFF);" `& e& a; I9 S1 C
, C/ c# ]7 ~2 c. t/ K) v, E. \9 l; k
/* Enable synchronization of RX and TX sections */
4 X5 }9 M- w( [4 O0 X3 s) F/ wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 y4 Q7 S, x$ l; b4 Q; G( g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: I" M: S) s6 F H' `7 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 w+ H) w6 A7 u9 y
** Set the serializers, Currently only one serializer is set as& D( x% K+ R' N9 t- K* T" V `7 H
** transmitter and one serializer as receiver.! ^! E8 w* _# x# Q; x
*/
& Q- K1 E. @) L1 Y/ w7 t8 I6 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- a4 l- ~1 C5 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" f$ V2 j/ |1 K% D) l1 I** Configure the McASP pins e f9 e/ R% @ e* B0 O
** Input - Frame Sync, Clock and Serializer Rx T2 [$ {4 K+ y, d9 |
** Output - Serializer Tx is connected to the input of the codec
& o% U) ]0 x$ w5 a, j*/6 B4 H" ]* m' a" p \- Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) }4 @% h& K0 P+ O) T) [* i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 _, j( f3 c- Y6 Y. I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; ?' |8 S" I2 Z2 i' C| MCASP_PIN_ACLKX
& E& p+ J# d3 Y! w X! |/ X/ z| MCASP_PIN_AHCLKX/ e" Z+ i5 n b5 H/ S E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% |7 \4 ^ T9 `4 r R! ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - r* E/ }! ^! y: K- B
| MCASP_TX_CLKFAIL
& x" E; S1 o6 h( x+ m' h| MCASP_TX_SYNCERROR+ W* H2 j/ T5 ~. r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# m. L* p9 G) ^, i" |. @| MCASP_RX_CLKFAIL
% @! I. i `1 _- S* o2 O- s7 ~% T% g3 T; J| MCASP_RX_SYNCERROR 6 E* l4 F2 A+ B/ U" s; _- `1 u2 \
| MCASP_RX_OVERRUN);
# h, W3 C/ S: O9 I: q& p& r} static void I2SDataTxRxActivate(void)
( [8 _4 f6 @" p: ?' I, r{% Y2 f1 n' M! g/ b4 A. F4 o
/* Start the clocks */' k; K5 k0 K" f4 _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! q" ?2 E9 p6 {! J8 J# K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 t: \8 g7 A* C; u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& @ s/ N, A$ P- ?1 x3 B" P4 ^) v
EDMA3_TRIG_MODE_EVENT);
) |9 C/ a3 ^+ tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + q- K; G3 V* W, W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ Q$ a( \: y; W! |/ P' B6 c' i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ H3 u3 [+ k4 U4 V2 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 R# B9 ~* v; _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 G1 f& {5 m% k6 z8 p$ HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 V2 o) D5 q# wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ L, V+ s# l8 b' P$ ^
} $ Z( `9 u; C9 D* e$ u' m6 N- H# ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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