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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% B& T( ] r, F- v. hinput mcasp_ahclkx,, p" J, O* _* X+ D& \2 E* R
input mcasp_aclkx,- A7 t7 Z2 i4 P
input axr0," T$ j- I; |" K: X s+ D1 S8 b
/ }/ O5 A4 g! d' `& [% W6 g
output mcasp_afsr,
9 `( ]! R: w3 @8 X' Noutput mcasp_ahclkr,
! ^6 K7 {7 M! b- Woutput mcasp_aclkr,' ?/ G# ^, b" b! @8 O
output axr1,
0 A" G* D1 {( s+ b, x, u assign mcasp_afsr = mcasp_afsx;
6 x4 ^4 K7 [1 ]7 C5 \assign mcasp_aclkr = mcasp_aclkx;
|8 ?2 L5 `! Z5 ?/ O, s+ Lassign mcasp_ahclkr = mcasp_ahclkx;
- |5 F5 X0 z8 a2 A" }# W7 Wassign axr1 = axr0;
# m" W. b& \9 D
: h6 n& K# }. V! x! \7 I; b7 p+ @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 ]; m& N3 M9 B0 B
static void McASPI2SConfigure(void)
9 k& e# d6 b$ | D{0 R0 H' W& H5 d1 f- }( I; h7 M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 n& Z8 Z. E% C4 R: }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 i( H& x% [2 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( {: m. Y6 j6 y. \5 p7 n9 B$ wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. h* l$ x8 n" F: V' x! @; k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ c% e j5 C" |" m" FMCASP_RX_MODE_DMA);! i: u" q1 e, F( y. e& p* L+ D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ H8 G- L) N! Y) r. J- _: G2 x7 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" l/ e. e) {2 T5 Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, [ R$ s7 o! E# E5 G; Z; I$ K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 ]0 e- ^" I. H6 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 q, ~0 i$ S' g D4 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, a; c& r _8 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 I# j$ X. b. M W1 i" L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, [( m6 R: v! t# U A ^# jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 Q3 w. W, u5 O+ ^, c
0x00, 0xFF); /* configure the clock for transmitter */
3 s4 T) o* o% D4 l2 p6 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ n7 y. ^% J; Q$ ^ P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . `- j0 s# ]- ~) p: D D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 x4 b' ~) o% _& X0x00, 0xFF);
% _( Z/ m7 e) f- s3 e, x4 T+ r6 r) C$ @; s9 j1 ~5 ~" [4 f
/* Enable synchronization of RX and TX sections */
1 @$ Y7 i4 T* `3 A+ D9 p% y mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 J! C2 w3 v1 G; E4 ~4 z0 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! y! X* t# _7 k# j1 {; z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* X) ]' ?# P: e. E4 h** Set the serializers, Currently only one serializer is set as
4 u' D" r, d6 k! E3 v6 e* Y8 v** transmitter and one serializer as receiver.
# A1 a, l% N7 K" U; ]! I*/
/ p' j6 F9 l6 L5 z$ ~) @5 ~ }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
u; Z* Z& Y/ k: R; MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 A: X' H' b/ Z* p/ s** Configure the McASP pins 8 q+ `4 |* d" a' a; n
** Input - Frame Sync, Clock and Serializer Rx
4 g; a7 Y' g X. A! u** Output - Serializer Tx is connected to the input of the codec ) A# h; s* g6 m9 u
*/
0 ]/ Z1 O z8 h% _1 M& wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 g3 b2 t: o0 O5 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! d& T8 o1 y4 }8 z) dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 O r# q. e. Z3 E5 N# |% m
| MCASP_PIN_ACLKX) L4 F" Z7 D8 ^
| MCASP_PIN_AHCLKX
. h( ~; D8 G' a) ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 c* L4 r3 V1 J1 [) G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, T; ]8 U) ~2 M+ `3 z9 K# h' _/ `| MCASP_TX_CLKFAIL 3 {7 ^: ~5 Z* y% v6 b; o/ c
| MCASP_TX_SYNCERROR
6 A" @. [1 u$ `' i, ^. ]& s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 Y% z( \. M. H0 s
| MCASP_RX_CLKFAIL Q# ?+ B- S1 Q6 Y' |* Z
| MCASP_RX_SYNCERROR - V- H5 V7 x5 \9 B/ U! _0 a4 }
| MCASP_RX_OVERRUN);$ {5 v8 z6 `# U& f. Y
} static void I2SDataTxRxActivate(void)6 A+ L4 ]! L2 E& s' {' |( s
{2 `. N: i% b w2 l
/* Start the clocks */
" ?: I! A, ?" z. g. R' i( S+ Z* `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 |# a( b( A$ i5 y6 c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 F' T0 F; V& P5 R4 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* `; f* f- j) l; N' y. k
EDMA3_TRIG_MODE_EVENT);
" @: l4 [; u- W9 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% A- E9 ?9 M, [3 i* k+ n4 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ m& B# ?, i5 l- a* `0 q1 o/ w2 C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) O( Q6 T+ A+ D8 o$ U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# I4 h5 T+ F0 H) \6 ?. A6 R* ~) w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' w0 ]( c7 j c4 O) }/ g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' t4 d' j4 d, K/ K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& x$ b3 G* Y1 H4 t" N: [
} ( J7 r: z* |5 D* x. s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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