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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 q( P1 r) T8 H S: u. @# y
input mcasp_ahclkx,
( V/ z' ~( |; I8 L; ?; J; Cinput mcasp_aclkx,; I5 h+ E5 t) n# C
input axr0,
6 R! [' U& x, k! |8 O$ k
6 }( [% }- w/ H/ Houtput mcasp_afsr,
: V/ B& V" x# P9 |3 houtput mcasp_ahclkr,
+ F/ W- h) C6 O6 _output mcasp_aclkr," ]! C% E) t& v; o% n
output axr1,
, [ r" Z3 [! M" ?! d) g" z6 K5 l assign mcasp_afsr = mcasp_afsx;
& I( T$ y0 c! k5 n E$ y- l# b4 ~assign mcasp_aclkr = mcasp_aclkx;% E) O9 I+ X9 K3 M5 `+ C' |6 n% C
assign mcasp_ahclkr = mcasp_ahclkx;
1 F5 l9 ~9 F$ _( rassign axr1 = axr0;
0 ?6 ]3 k4 T- z# {7 y
4 G# W+ W/ \( a6 G }/ Y5 ]) A S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " Z6 t. r# J8 ^8 O" }; \4 m
static void McASPI2SConfigure(void)
2 B4 G, I" i* f$ u{& S( B- m! d- {" E! V! I+ V/ c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! d0 N, `& r9 e" z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' ]: }# {- K$ A9 I+ x/ vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# j# U" q- C7 I. ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. q3 K; h* O3 R% Q& }/ B* u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ q2 z t6 v! H; f, O/ t8 i
MCASP_RX_MODE_DMA);
- w3 I9 X6 ~. k$ C$ FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 R& u4 S; \" H/ `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 T- I$ J$ b) o) m+ q2 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 D* ^+ D8 s: b' h( {( Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: J* K4 W7 `# P* ~" b$ Y" F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ H, ]; h/ N1 N$ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% E) l9 i/ K) P" H& oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ X4 y( b& h% [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % C+ g# W) a- {# ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! x- d5 F1 b/ h0 U5 F* C/ d
0x00, 0xFF); /* configure the clock for transmitter */3 P- a+ J9 b: Y- P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! L. x* F% K1 o8 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 i2 @3 `& _1 `" L6 o% P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; E W$ K; B6 S" d2 V& o/ k0x00, 0xFF);
' J, d- m6 m. i/ h4 W
) e7 c& b$ f- @+ ~6 m/* Enable synchronization of RX and TX sections */ # m6 e- F4 W& G! `' \4 X- |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ c0 P, L8 G9 U, VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, k9 O+ j! f* ^: w. S& TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' l; o) ], _" ^
** Set the serializers, Currently only one serializer is set as
3 Y$ q/ p% }5 p0 C S$ g** transmitter and one serializer as receiver.
0 F7 y: ^" Y% p4 A: c1 B*/
1 p' m. S" S3 ?8 p* c1 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 x) p1 F9 L7 l9 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ a( D* z% I# ?0 i** Configure the McASP pins ) O! s. d; b& ^8 k; q3 t% R
** Input - Frame Sync, Clock and Serializer Rx5 H3 j! R0 l* U' p
** Output - Serializer Tx is connected to the input of the codec + N& L. s! p1 P8 L4 D. q7 I" H& g
*/: q; P) i' n& q4 e8 G) x* w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 V, r7 \9 y7 y1 W9 M7 G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! S4 Z# ~. g* Z* _9 J* t$ ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ g& n0 ?1 X, V. L5 t* [
| MCASP_PIN_ACLKX1 I) R& m/ K" D& J: r! }9 d, ?% y- l P
| MCASP_PIN_AHCLKX
9 F1 U! J7 B0 c" V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 j9 U. Q( N x0 v7 ]' Q1 h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( `5 ^# Y0 |) h, @$ x2 Y# G
| MCASP_TX_CLKFAIL
, }' T% L1 v6 ^' U8 ~8 ~4 O| MCASP_TX_SYNCERROR7 v' F2 `6 c% J8 v v6 g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + f( A" ? _5 I9 P/ N7 Z4 P
| MCASP_RX_CLKFAIL
8 v( q2 o p# v" a| MCASP_RX_SYNCERROR + {, h4 P+ Z* S" m, W L
| MCASP_RX_OVERRUN);( Y' K" Z8 m0 g
} static void I2SDataTxRxActivate(void). ~5 R/ J! T3 d& b
{# [* x: q# ~6 U. X2 p
/* Start the clocks */
. C; T' ?7 Z1 D- A iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 y) v* _- T C; D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 ]+ I1 l: R8 M! L% v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( M7 ?/ q* @! ?( w+ v" VEDMA3_TRIG_MODE_EVENT);: r. R7 i$ m' H; G7 C) ?2 T7 J3 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 K0 [) R# `; V; M1 a6 L1 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( o& i& b4 h+ O: m1 w- K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 v: v: i: C/ M/ V) G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 p2 \% n- ?7 ], g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 P6 v; b- R* C7 f+ Z0 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 b7 Q' j( A' N+ _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ A1 @1 s/ f; M/ ^# F8 }3 _/ X, _
} 3 E' l" v# x& P2 B. d0 u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " V2 ^* f# P$ C: e K& M; L
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