|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," x) }* m/ x/ z z( b; {
input mcasp_ahclkx,
3 I6 K' ~5 e: K! ?- winput mcasp_aclkx,
8 L8 D# g% X/ T' C& U! minput axr0,5 X5 M' e4 q+ D. l# C3 S+ G
4 }5 I. N3 b/ I% m; N+ I3 U" q f
output mcasp_afsr,) @) V/ J9 Q' r5 T$ a% l
output mcasp_ahclkr,$ o3 k' O3 s' M+ X; p' Y4 m
output mcasp_aclkr,. d, t' y i9 T! ]' R
output axr1,- S4 K" M* x8 C. C
assign mcasp_afsr = mcasp_afsx;; U! Y. N' J: E3 {" Q/ p
assign mcasp_aclkr = mcasp_aclkx;
2 r& F( U1 a1 h' w" fassign mcasp_ahclkr = mcasp_ahclkx;
5 T. e0 X/ f/ b9 n0 Wassign axr1 = axr0; ( ~' D& c; G/ {# [
$ R6 u+ m- u2 U- V. l# H# w% k4 }, }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " k* X3 H9 S# u2 g
static void McASPI2SConfigure(void)/ s9 F g* J( l" _1 i+ [1 r. U
{3 X+ }5 X; N$ J1 N6 v3 l/ O5 G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 X" o- E {) k- U+ sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 ?' r! i- [' o( T, h" pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 R+ `! V: B, |' X1 {, |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 @, P @& g7 }5 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" h; n/ x2 `+ QMCASP_RX_MODE_DMA);
0 ^4 m9 p' N8 }! v8 q* [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. U; Y) l( {4 l$ ]9 s9 e4 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- ]0 v. X; b" a: C2 t# \9 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * x0 y) z9 |: z: V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" {9 q2 N- v) x6 q* C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 \6 v O* { i+ J( ?/ d# Y4 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 L* l& k. k' y. C% iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. U8 o" x1 F% ~ u5 p& nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # B+ p5 q4 f8 y5 ^9 {' v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: D, S6 V( C5 n+ i
0x00, 0xFF); /* configure the clock for transmitter */, R' i4 l" k4 G0 B% m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# C6 G# C! K# _$ P9 z. f; CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) f8 T0 P/ A7 I7 z8 V5 yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 s( L. H7 |5 s" @! E
0x00, 0xFF);
! a# u. B! t2 S% [. n: b8 _) \0 H# i8 s: c+ U
/* Enable synchronization of RX and TX sections */ , f/ z1 D$ V# m% J& r. x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ e$ X; F7 x5 U2 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. u) d! Q! l& U, L7 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; Y) m! f2 n8 A0 g$ H: X** Set the serializers, Currently only one serializer is set as4 I, U. w" T' Z/ O3 j4 N) d
** transmitter and one serializer as receiver." q" I$ j; G' K' K
*/
* D$ g" J$ |+ l) cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 ^! e2 o- h( l3 R0 o/ R0 sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, i' O o% N, o( i K; o" L5 U/ x
** Configure the McASP pins ( ^* \$ L3 o% K# N9 V6 w
** Input - Frame Sync, Clock and Serializer Rx
`4 x6 X) D5 c( z** Output - Serializer Tx is connected to the input of the codec 9 c1 X4 A4 F+ D- v
*/5 ^* r/ y8 b; l) ]( B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 ]/ V/ f( V5 g; z3 P: dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ N. _" A3 z5 u, k' N4 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; Y2 _2 ]' F7 A$ B7 C& _6 `# b| MCASP_PIN_ACLKX/ H/ m% ]2 N- y# R, S0 [6 r6 g
| MCASP_PIN_AHCLKX2 V) u) B3 P9 A" Q8 g/ _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 H, I( E8 |7 c! Y) nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 z5 s; @3 f# K# Z# w/ |0 j
| MCASP_TX_CLKFAIL 2 q) r6 x1 M& N, s4 a6 P! h7 |
| MCASP_TX_SYNCERROR
( ^5 E. t: ^3 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 j5 Z* V% Z5 `) [" t' P6 T- J3 t| MCASP_RX_CLKFAIL
4 t d2 @7 Z2 B H2 ?7 A* O c| MCASP_RX_SYNCERROR ' {/ F. E0 L& P" j; q
| MCASP_RX_OVERRUN);5 g; B% E) z, X' d, I6 {* Y
} static void I2SDataTxRxActivate(void)
* ]+ e6 k1 o; W0 g. w{! {2 I* W, a, s' a9 G5 N7 \
/* Start the clocks */' g5 Z) {( v! c' D9 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& s; T3 ?# Q' h; S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ m& r; _; K% C# k% WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, z& C# V6 }+ R* a2 T: d4 x7 ~
EDMA3_TRIG_MODE_EVENT);
+ u4 u* Z% b+ ^2 |- WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 Y) h' E- D8 f: ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ Y; \0 }7 s* s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ I0 a' g+ k v. {0 D/ M3 \' m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 x6 N9 s3 B% p: N( l bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 J$ X) P% b7 [8 q% Q/ u+ y! B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 S# n; D( F* tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- a/ O T4 I5 {}
& C- n$ b" v0 D. K! i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) J6 D7 N; q6 H7 S6 s! R
|