MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

) u$ m; T! v! T/ U7 moutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
6 {7 S2 z, m: c  u0 {+ s1 }

assign mcasp_afsr = mcasp_afsx;
" X& V$ l' C, ~# ~9 ^: w. w. Xassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
) g( q/ F8 j/ q- u1 d" Eassign axr1 = axr0;

* j2 M6 I( _. E4 |/ ]" B2 Y

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
& I; x& j, I* ]: N; z. \3 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
, J+ M8 }0 j; E/ Z; e% SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
- S1 }/ Q6 w% b5 D% f2 V+ gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 V4 Z4 S- ?# m4 y. q6 a1 e" d% wMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
! W) l7 a% N0 f& w/ V# c7 `, a# i) OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' o7 _7 m% k- \% u# @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! \2 `9 z* p6 ?3 B) T5 E- JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
+ u+ \) g/ q. ^+ N% SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 R8 V/ d; j4 O, H0 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; Z7 R/ \! w2 r6 s7 B6 v0x00, 0xFF);

- v2 ]* x, b& z6 Y/* Enable synchronization of RX and TX sections */
( `, T1 h5 d" Z3 L# k2 _8 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
7 k& v* A. ^- t# I4 B/ c$ Y# g( HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
3 {  \# e$ A0 {8 i** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 J$ P  q& j% |8 ]5 J- v- y, ]4 kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& j( |+ a7 l; O+ E# R, B( F! p1 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! c) J( ], E  y1 S| MCASP_PIN_ACLKX
  i3 W# p' h4 M  @9 D/ b| MCASP_PIN_AHCLKX
% A/ x0 u) c- [2 G# L$ I| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
1 F, K! I+ F0 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 x) f4 B$ Y* t3 @| MCASP_RX_CLKFAIL
8 U3 y0 ]- F5 e. N. A( d| MCASP_RX_SYNCERROR
) g6 s  s7 I5 U( J/ T% }| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
& u) o; m. D  B8 `3 c9 `/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
" |' I% S; q; H0 v: jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ t8 o! S# q( H" |) o7 h2 AEDMA3_TRIG_MODE_EVENT);
  x- ]3 G( r) Y7 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 w) ~0 M  V- [4 [' |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
& Q7 m  u7 N0 @/ W# nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- a8 t* ^$ w9 p, R4 }( C- O# FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) }2 }, ]+ R- w; t. ^3 e& a}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

# y" ]* P- k) z# s* w2 p