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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! s3 r. ~" C5 G- E5 ~+ f
input mcasp_ahclkx,; t3 z7 {4 _, N* f" ^3 M' x# W! I
input mcasp_aclkx,
. U4 L& V$ I% m# ?/ D) @) m% Pinput axr0,
* M1 H- ~1 o" ]5 W# C
; O' C5 U+ Q" @1 r8 L( I' P* soutput mcasp_afsr,
7 U3 Z' u" l: t! v& z) z( N; uoutput mcasp_ahclkr,2 h& ]; J1 [) r* `5 ~& a. _
output mcasp_aclkr,
8 ]* }6 O/ F" A# Voutput axr1,6 u* ?! t# b% B: Y% T
assign mcasp_afsr = mcasp_afsx;+ k7 W$ N. X; W4 ~7 P% S, T
assign mcasp_aclkr = mcasp_aclkx;
, _/ l8 g( R, B! bassign mcasp_ahclkr = mcasp_ahclkx;+ A% B8 P5 Q1 d6 v4 N# M5 s2 R( Z! L
assign axr1 = axr0;
2 s# `1 l; k& b: Z
2 e6 U- S0 P' X. }/ r" j% A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ t& F1 j/ x& P0 _" z3 i
static void McASPI2SConfigure(void)
, h6 t/ N6 H6 h" T- o5 M" ~0 X{
# R) b% Z7 y/ U0 K# B zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& p- J" N q0 O6 ^4 T0 e7 m4 x; aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, p5 G8 k; L, [: L5 C2 ]( G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 |1 H5 t$ Z" K6 M( |, HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( ^9 A1 B' i0 D3 _& l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* M1 e0 M5 Q3 n5 ?; n$ AMCASP_RX_MODE_DMA);9 E& M, C: k3 ^, O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: e% Z' v+ u6 _# n4 uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- s& S1 E5 a B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ x" g3 D) I+ ^" q% h) M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; U; ~ I! @5 i. L0 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , [4 ^3 i. ?8 _2 G6 w. ]5 T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ t% G7 _+ C2 i2 {+ J( q( [2 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) q! ?7 N1 l8 y# hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ]- p v$ S! |* }7 A! {3 e D: CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 l7 h& K2 w1 _( B: C1 [. c
0x00, 0xFF); /* configure the clock for transmitter */
6 c, s) m0 c, W$ p" w1 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 s' q6 L+ c2 n# I; A! v `$ r2 v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 r# w8 _) i2 Z4 D. G2 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 b2 Q, v J! B0x00, 0xFF);
& O2 \- e3 T' v; s$ d; }6 M; ~
8 m" _ F" m. g9 t/ ]2 g/* Enable synchronization of RX and TX sections */
4 f% U4 I! D+ _1 ]6 [1 S E( YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( r' a I* c' X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 [8 `( n' Z8 q7 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' x" S; P2 p' `0 I* u1 ]* J0 S0 h** Set the serializers, Currently only one serializer is set as4 b. j, W& w' a; T
** transmitter and one serializer as receiver.) p7 U% Q1 q, x
*// y! v# X( q; c0 Y; j7 g, `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ n( W! e. m- P ^! b$ jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' @! z# w+ K5 t. ], ~+ D
** Configure the McASP pins
8 M# O& v+ w& ?# }/ u. J/ U** Input - Frame Sync, Clock and Serializer Rx3 i% X8 {2 L, ]% J( I2 P
** Output - Serializer Tx is connected to the input of the codec 6 G+ f* l: @/ Q% p/ u. o' D
*/; }# Q9 f- L; q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# T6 w. C7 S8 f% A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ]9 E: t) Y9 P1 m+ [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 _" I3 }# @2 @& s7 D; _| MCASP_PIN_ACLKX6 H8 g$ c6 S' I. C$ @/ @
| MCASP_PIN_AHCLKX
% v( M3 v% ?4 ^7 T. H- X/ w& @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% H R: b N% ~4 s6 x# P; UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + q7 `% d' ^& Q& O0 L4 t- J
| MCASP_TX_CLKFAIL | P) {! K& F& `% j+ Q
| MCASP_TX_SYNCERROR8 m0 A- O) r/ _0 X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 d: O, d. P$ |! a7 f
| MCASP_RX_CLKFAIL4 h0 Z' v3 z5 s( }, h/ C" _6 X
| MCASP_RX_SYNCERROR
- b, }$ A6 Q6 @& O$ R! r1 g| MCASP_RX_OVERRUN);
* Y& W6 x- |6 M! I9 u} static void I2SDataTxRxActivate(void)
+ ^0 t2 X; D* Q' K2 e# ?- n{
/ l* ~% M0 Y( B$ r/* Start the clocks */) @" s F$ c$ z) q/ ]4 h' @; ^# t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ W: a( R9 U) \9 |2 B8 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 Y7 [- C/ a: B. w4 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 _+ J* I( ~3 `, W3 D/ a! ~EDMA3_TRIG_MODE_EVENT); X8 |7 C: K! c) `: p' A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; z6 m8 n2 Q1 Z: z" l5 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 l' V" X( l9 D4 j3 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 \0 X4 O0 ]; _ Z6 NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 ^; `6 u0 _' h) s4 z3 Z9 b' W3 C# M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* n, u! c' }/ p3 B6 S: R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 g7 Q1 q( h4 ^' H7 ?- FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
z* @. M- Y1 ?# X}
% H; G4 Q4 ?) N3 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # W) u$ A1 ?: H7 o- H. D$ ]
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