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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* \* d- ], [' E" k7 Z5 Rinput mcasp_ahclkx,
; j+ y# v5 k5 h8 X8 A, vinput mcasp_aclkx,
0 s. |* ^# s$ N, r3 ~8 _" ~- R0 X& _input axr0,
' i% V- ^/ Q& e( ? ]" S* o E+ @
2 q" ~# I" ^& q1 C6 }6 F1 eoutput mcasp_afsr,
& Q$ c2 N' {4 N; R$ z, n/ \& Foutput mcasp_ahclkr,. g- K0 q X8 D- O# F0 W
output mcasp_aclkr,
5 s9 {5 e% O9 @output axr1,2 s" M c5 O7 f7 Z8 C# a$ k( W' t; s
assign mcasp_afsr = mcasp_afsx;
8 u4 S& H7 a! F) L: eassign mcasp_aclkr = mcasp_aclkx; z6 j; A4 a$ Z1 y
assign mcasp_ahclkr = mcasp_ahclkx;& Q$ L; q, M4 I- r' e
assign axr1 = axr0;
6 ^6 k, ^4 c: b% {4 u5 v% w' W' t$ M, g$ |
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) ~! y7 U. _$ L0 q- `5 F6 m2 i- i' k7 N7 ?static void McASPI2SConfigure(void)& C: j% e8 U, m& C
{
( X s* T" S- [- vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" J+ I: i, U" U9 k. w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 ^1 O- [- z/ d* i" l8 P. \8 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 P* n4 L4 D5 N# _, m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- N8 r8 T6 D7 @' Z! y7 D; x* B& PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 U/ r6 \, \( B" _
MCASP_RX_MODE_DMA);# g" @) f W: o% n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. \8 w+ O, u( I9 A, g: hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! m3 v' k' y- D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
[+ A4 x: u' f- uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- H8 J, B6 }. j) G& s2 l& bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 w4 g! n0 |# e2 A7 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 t% [5 @; {$ ^4 O& K+ ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# x, l- W3 D gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ n2 z: F" _+ I; n. o% n) lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ F. J Z' J( F! V: Q. r7 {) d3 R
0x00, 0xFF); /* configure the clock for transmitter */
% j0 R! B C2 i. ~( YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 ^, O- K/ p8 `% O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ]. p) k% V" iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 O* h, X3 b9 E! l
0x00, 0xFF);9 Q1 y( \4 o8 `3 s2 Y
! X/ Q& y' z. J
/* Enable synchronization of RX and TX sections */
9 l4 q; [7 P/ n2 R) }- {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 f* j! m; i- a9 `" MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- t1 ?/ Y1 l0 f/ \' l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** s) j4 h" a: W
** Set the serializers, Currently only one serializer is set as
4 M% X* j( H4 }9 R& w$ z** transmitter and one serializer as receiver.7 ^8 a" [! d, Z3 d# ^
*/: ?$ _' K9 L& J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 c2 k2 T% U8 v: S9 ~$ }3 F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 [1 H8 @* C" I, A3 x** Configure the McASP pins
C* m" ?8 M( S; T% E** Input - Frame Sync, Clock and Serializer Rx
. w) S( r% _: b( b) b** Output - Serializer Tx is connected to the input of the codec T) t1 E: T: }) w# E
*/
& g5 v1 e1 @6 b7 G/ u& r4 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- x2 h% d- J* K3 `8 e+ V a' o6 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); P J$ ^9 W. b7 E1 J# q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 N1 Q) x6 u$ [6 L
| MCASP_PIN_ACLKX- _6 t2 F0 T, {/ `- x% b5 @. k
| MCASP_PIN_AHCLKX, A' X% }; [* \8 M+ J* o- F: n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: k5 r1 x4 S% |3 C+ DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 z# n" g: x( P3 g; ~: h2 Z0 `| MCASP_TX_CLKFAIL
( ] B4 `/ d' a| MCASP_TX_SYNCERROR
4 r$ _1 _4 _9 x* R. ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ ^" c3 v F" c) {| MCASP_RX_CLKFAIL
& w" Q% w5 C, i. n. S; o1 ~| MCASP_RX_SYNCERROR 4 m5 f+ V% i5 b* M
| MCASP_RX_OVERRUN);( d6 y& k& S7 w$ s; j# W0 G
} static void I2SDataTxRxActivate(void)
. F7 b7 e' P* I% v+ p{
- [9 F0 \. A* L; z; h8 O& l1 F$ x/* Start the clocks */. l5 n h% ]- y e4 ]1 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. {- |9 e- x+ z; X ?6 j* jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// i0 e$ o+ n# [7 j" y" _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," p" ~9 L! B, k- R e; @# R+ Y
EDMA3_TRIG_MODE_EVENT);9 I/ L# {5 p# @# V- c( B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 K7 J4 i* }- |; f- a' k WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 S, Y1 ]1 ~% z" L2 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) S( m+ n. U1 I: @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- C2 s; Z& w; \ F& jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 c8 h& U3 w5 p1 P( @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& q: D. H& G W0 [2 g, s) f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); T" g& c Z" D+ S" b7 A! |, l1 u
}
# s2 ]2 u `6 _0 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , u' _6 j4 L3 N: g
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