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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; h& a' O) o2 m* O" w
input mcasp_ahclkx,# `& c" R4 r- S
input mcasp_aclkx,/ w8 ]& Y( ^5 \& j2 `, N
input axr0," u0 t- S: n! U E
5 t' h0 Q( S T5 joutput mcasp_afsr,
p9 F+ |) z+ }output mcasp_ahclkr,
0 G* F4 _& U7 }( F3 J" f# {! ^" U8 zoutput mcasp_aclkr,
0 L- c/ R J3 qoutput axr1,
" x0 u/ E7 p; q/ p+ p assign mcasp_afsr = mcasp_afsx;- `& m3 T" ]& [. U
assign mcasp_aclkr = mcasp_aclkx;
& _+ n" j. d# d& T; W+ Vassign mcasp_ahclkr = mcasp_ahclkx;$ Y# r% @3 q2 k
assign axr1 = axr0; 8 Y' E* T, C* d x3 i5 [
5 Q+ v! }4 {9 c/ c) Z3 j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 I5 C# y/ ~2 r1 L9 h8 ~static void McASPI2SConfigure(void)
8 d# G9 N! A4 D* E1 m! f/ a{
: l2 W' i3 f1 I; ?1 E! `5 T8 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 {* b y9 o D: g) H! E% d! w( {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 z7 l8 M' |1 b( ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 L# A1 [: s9 _* s* i1 r' a# B( }5 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 o; w3 x( Q/ K0 |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- G6 i$ B H: g x" A$ r) w& QMCASP_RX_MODE_DMA);
. E0 L( I# e7 }" A9 V: d4 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Z) i! G4 M4 p v* Q% R7 X. w8 m* \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ O' z. K' U6 {( U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : U- ?9 l' c) B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ N6 H* I7 q8 Y. F0 x {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " o* I! K4 i4 B# t) C& ]) }/ L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 t) Q* [ ?% _3 {- ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' I$ c, i8 ]# w# y* U- L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 Q. e2 f: T' y/ m- z$ S. [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 p2 F+ S/ w" [0 B& Z# N
0x00, 0xFF); /* configure the clock for transmitter */
6 N8 r1 Y: G* B7 e0 y' N- B$ |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! E6 Y [. W$ h0 [1 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( y& l7 L) @9 P, Z, BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," {, N: \* H$ r7 v5 s- t9 q
0x00, 0xFF);
$ V! T) s$ J" S, T8 L9 V: O% R& F/ S5 N0 e2 _8 J- p7 V0 e: _
/* Enable synchronization of RX and TX sections */
u) L$ s& m. }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 S' y( n9 \1 g$ M% x3 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' A$ J7 o& q+ T* L$ {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 L7 z7 h' D! c, D9 y8 u
** Set the serializers, Currently only one serializer is set as
8 w1 W: ]1 S! V N. t9 `** transmitter and one serializer as receiver.4 j0 r. _9 I# w: ~
*/2 [4 ~/ n/ b7 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 l9 s5 h% K/ y3 z, ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 }# Q9 G( M. }% [** Configure the McASP pins
4 W' I% _$ R& C% j- s** Input - Frame Sync, Clock and Serializer Rx
' |0 A" P! u+ T4 J. j+ [** Output - Serializer Tx is connected to the input of the codec % p4 @" T) }( `" `* x
*/
; { m( n! y+ dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
J3 w5 t1 ?; ]/ ?" d8 y5 @# U& gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( o7 o$ S/ k3 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( i3 D8 ~% t2 H$ C, d
| MCASP_PIN_ACLKX! N' T! ^; i. E% C8 x
| MCASP_PIN_AHCLKX1 L7 J. L% ^ k- b% L% W5 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 L1 S3 W. u/ e& v$ K/ R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) z& q# c* O3 D& g+ W3 C4 N
| MCASP_TX_CLKFAIL 9 V/ @9 y5 q/ ]# C8 M4 |! w, |
| MCASP_TX_SYNCERROR0 J' a! V, L8 J9 ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 Y: W" a1 q' @/ Q* j# i& t% K| MCASP_RX_CLKFAIL
8 Y: H: v5 C- I, k| MCASP_RX_SYNCERROR
* P1 ^& y# e5 A3 k% s0 [' c: x6 }| MCASP_RX_OVERRUN);
* a' k( I# p& K} static void I2SDataTxRxActivate(void)7 I# K; G6 F* U, c& x: g
{
# I l# z3 q5 m, g1 G% F% V/* Start the clocks */
P$ G. u; ?7 L4 K" g' ]: A9 PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 d% [9 ? y' I& n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' C7 r; X5 o E7 T5 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 Z9 [( M8 {: b7 ZEDMA3_TRIG_MODE_EVENT);: Z( R- G) p Q$ }9 u% x6 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) f0 k* p) S' I* A5 a" R8 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 f& y; b. e! e! V( O6 x7 `, _9 E% P' _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( X0 S+ v* h: _* d& i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* G& {/ Z+ w) B, q! z, C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: ^, a/ ^) G N3 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 ] i4 T J' ?; VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& t/ `- S r1 q! B9 }) w
} 6 F* |4 h) z0 C- \+ X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 s: |! Z R- B6 n
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