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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, e9 E6 H& \& i+ f
input mcasp_ahclkx,
0 W- Y3 l; I+ ^4 Z) Dinput mcasp_aclkx,
0 \, f* Q* m4 f W/ T2 r9 q" ^input axr0,- Y# u* v+ p, q' \
: W; @. t" {7 s, Y
output mcasp_afsr,2 t5 }8 V% E h2 A5 B# c7 B: b* B* U5 [$ j
output mcasp_ahclkr,
6 A; }" o7 u! x& _; m: }( S) Moutput mcasp_aclkr,
) w$ k0 l* ?& e* L( S" d* loutput axr1,( J8 ]& v5 Q1 \8 U M
assign mcasp_afsr = mcasp_afsx;4 y; E7 C$ p ~, ^/ b
assign mcasp_aclkr = mcasp_aclkx;% A) |1 r! f8 m
assign mcasp_ahclkr = mcasp_ahclkx;
3 L; `& Z! {) O$ u( Sassign axr1 = axr0; + L0 {4 p. l- ~ K
1 J7 v% j: b) ~* f1 @; J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% ~" p$ Q- d, A" Y; Gstatic void McASPI2SConfigure(void)9 o/ s/ \& w w- o* {0 M6 w
{
" k, n4 V/ Q2 |, L, ]9 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 Z. p8 G! D; j3 }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# T5 I& R1 k2 J4 p( _) qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ]) R4 j# h& n- {3 g1 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 B, r- K4 a G4 ^8 ^5 t( T! y, |- MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( u7 `! h- B1 t2 G! }MCASP_RX_MODE_DMA);
, ]7 _7 N, L3 o# B ]5 y( O$ C* |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
T' X) w& \4 d& E$ m9 H/ }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: _8 Z' i3 V& Q# v5 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) ? G; R! D+ |3 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 {! w O' T, [0 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 M4 i+ C$ D9 g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 }9 t' X. p- ^# x2 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 H% I( F- a4 T: b( J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - D3 Z6 R$ l7 |& v8 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' ^* d, J9 i. H+ {' X
0x00, 0xFF); /* configure the clock for transmitter */
3 R" c+ b4 W3 x6 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" N: W+ A5 @( L# w: s. ?; T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( w4 G: r) [ G6 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, ~0 q' r$ d. M6 E$ `
0x00, 0xFF);/ ]9 Y/ @/ V; v5 K- I
% G, ~7 E# R; J, j
/* Enable synchronization of RX and TX sections */ : L5 b! o: P5 t8 y) g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" p* A1 a; d+ ?7 H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 M) f5 ]3 i8 }/ ^0 d% | _( r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& H6 k! @7 i; \$ ]/ d. R
** Set the serializers, Currently only one serializer is set as+ r2 c4 Z# V, i" X. K; L
** transmitter and one serializer as receiver.
; B1 B4 Q6 u% J, E9 ~2 A& V$ h*/6 x- N" A G0 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( U( X+ @8 m: e3 b5 u q9 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** w0 p) K$ D2 L8 k4 Y7 L
** Configure the McASP pins
+ g4 C- M* E3 d% K( O5 U3 Z" v** Input - Frame Sync, Clock and Serializer Rx
+ I! h5 R% N { e+ Z** Output - Serializer Tx is connected to the input of the codec : K" U& f4 ]5 H i. s+ [* U7 ~$ p6 m
*/- u% j9 [, G6 i5 r8 v* c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 C( v" f9 F8 e4 F: c0 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 s j7 {% [/ k4 e" ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ A) M" U: q) `8 b: P% Z% y| MCASP_PIN_ACLKX
: w3 q5 v' z, B$ u; `4 j| MCASP_PIN_AHCLKX0 B2 J) A, N1 D2 w# ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" E* v: m' F) I+ d, _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 Q7 X$ u1 K: D! F ^, ]% f' O/ O$ f) P| MCASP_TX_CLKFAIL
) ]9 X z" `0 ^, y. C- v7 X3 U| MCASP_TX_SYNCERROR
/ H4 P+ i8 T/ j0 N* G2 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - l9 A8 t: t$ s* } e2 {* `* e
| MCASP_RX_CLKFAIL
6 \. O: ~# D% L* \- M: n6 u$ q| MCASP_RX_SYNCERROR
. [0 s4 u# ?; I| MCASP_RX_OVERRUN);! O" K" X5 S) [2 ?# n1 n; r
} static void I2SDataTxRxActivate(void)
4 R$ N* y: p1 \- Q* ]* w% d{
! o$ c4 u+ S; A* [5 w4 Q: z4 A/* Start the clocks */
" e2 l5 p% f9 M4 {/ B5 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 G1 l d+ B& y9 O5 m% OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; S4 [, `+ t# h: @3 v" v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& z2 p% j! }: V( v/ {# V; l8 uEDMA3_TRIG_MODE_EVENT);
6 ^8 Z+ f3 x- F/ @' Z- v4 a& ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 f ^$ d" O9 f7 ?, mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: D: u+ @3 S& `. C1 D# nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! G0 x- F8 T" r/ u/ C9 [: PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
q( C, w; m6 @* Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: D; t5 H6 }8 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 k* L4 f( h, C$ E! YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. ]4 U* h9 F- P" q# F% O}
' V$ T7 G7 | R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) J( f6 s' Q% {) }8 Z5 E0 S
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