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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, r/ H, f$ e4 n( p H5 Dinput mcasp_ahclkx,$ e8 t; Y! \ j: v
input mcasp_aclkx,' b4 W6 z: E; h* D! S) V. E+ H" O
input axr0,
" R( t! [; U) r6 ~2 z5 t3 d5 u1 @$ M1 T' `% W) n
output mcasp_afsr,
4 v% m8 A8 X p/ O( ioutput mcasp_ahclkr,+ s8 f" K9 r3 n
output mcasp_aclkr,
6 [& B: b- {( `output axr1,2 i6 n# }, B5 \5 M
assign mcasp_afsr = mcasp_afsx;
p" O) V% p8 D2 W! ?8 B4 I7 kassign mcasp_aclkr = mcasp_aclkx;
. d4 ]) g4 D8 ^assign mcasp_ahclkr = mcasp_ahclkx;
1 m" j# g1 j6 @$ L/ x5 E o/ c3 Jassign axr1 = axr0;
4 |3 a0 v9 Z5 p2 j( a5 | p1 {
/ ]$ K4 [ G2 R9 \) o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 S+ N7 w( G' Y" K. D. bstatic void McASPI2SConfigure(void)' E# o5 W2 b$ E* u3 T
{
3 R; D7 }% r; ]/ \; GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* @" U3 ]$ O; m& P$ G. N3 j) u( j( tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) J5 _* j0 J1 b) FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; ]. ^! g; J9 D0 rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" t- l2 ?6 X+ W0 p- t, N* S; v) ~, }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; p' c& p& C' U9 {' H$ XMCASP_RX_MODE_DMA);) a6 W/ s- [. m& V% }0 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 Q0 k3 L. `+ T! N& TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ o) h2 L4 W% D7 N0 E( a' ]" a% Z7 }4 @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ h* ^& O) ]" e' xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ b2 L2 _# \: RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; g6 |3 e, l+ sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# U; ]+ r0 X. Q7 y. G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, D5 N& i6 e$ X# c" |1 q- v' S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * d3 \, M( O3 ?( P' N% ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! Y) x- k, _1 J4 {) c: }0x00, 0xFF); /* configure the clock for transmitter */1 K1 @. y/ \6 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 s9 ]5 ]* v5 Q- j$ D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- G8 x' V- j( s& F8 f( vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& y7 d; }# ]7 d, u2 S) {
0x00, 0xFF);
8 x' f8 o: `; v4 s9 `! P9 R( b
/* Enable synchronization of RX and TX sections */ + [, R% n) x1 z4 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 D( |- ]9 l$ o; ^& v$ DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, l) f Z F5 e3 A) VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. H- f8 q9 U% i4 ^4 w. J6 }** Set the serializers, Currently only one serializer is set as7 S7 f( [6 b2 n$ P
** transmitter and one serializer as receiver.- F2 s9 p3 }5 G( ~( Z
*/
& m* J: l2 p5 d4 I9 F1 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
j8 \1 l6 }7 y6 C+ E6 o' sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 {3 R$ l7 _$ T1 C: b
** Configure the McASP pins
) l0 F/ f8 {: f) j+ }+ o1 f$ n** Input - Frame Sync, Clock and Serializer Rx
# k- ^$ G! v% }7 K' ^9 }( f9 i** Output - Serializer Tx is connected to the input of the codec 0 s! Q' a" A+ K j
*/
( O& x; i, e( |" t9 n9 O, c# l3 M( GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
_8 }4 a1 ^. @3 K# w( ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, [7 R% K$ }2 v1 t Y# G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, h& D( e; E. w6 @( E$ c| MCASP_PIN_ACLKX
' L. f9 `) y* u5 f| MCASP_PIN_AHCLKX* S6 n' R# e x/ S* D$ v4 r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! |/ d! z4 z2 ~$ ]$ }/ Z3 i( V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / c2 W' o6 r8 z( N
| MCASP_TX_CLKFAIL
! S k6 q' J4 U9 c0 R# t| MCASP_TX_SYNCERROR
8 K1 }) }1 F4 r6 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' G) ?( z0 M z3 [( Q
| MCASP_RX_CLKFAIL) t& e# L) b- {
| MCASP_RX_SYNCERROR
3 ?: r, s2 m8 u# a9 l8 e2 d0 G| MCASP_RX_OVERRUN);
% [; O* B% j" ~} static void I2SDataTxRxActivate(void)
! H! ]; G4 r1 W- R3 K* A' Q& `{
- J' O5 s7 M& V) G3 H7 W- i/* Start the clocks */8 U" H5 g5 k. H9 {1 e, h1 i% S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); g1 J) y3 H" v6 E9 C: b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- E( e1 t7 [, O* }, {: FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" u+ y/ k8 P% K5 xEDMA3_TRIG_MODE_EVENT);
# V X: L) k; c& xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 ^( Y3 N, r7 G! k3 w( F. rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 b) z7 w7 H6 U! \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ B: B) H! }, n! j6 z# w1 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 H) B! B+ w! ^) G5 ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" l6 d, N9 x& X, F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( e! T6 e* U+ Q9 ]2 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 f6 j+ W( P3 a}
: Q4 a' f" q, ^) p$ }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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