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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' a" ^" _2 L" I# b) q9 K$ Minput mcasp_ahclkx,
! S6 L( l7 h m: Pinput mcasp_aclkx,
3 ]9 ?: M0 O! Qinput axr0,
, N: }: t% i4 V6 X3 p. i
( w+ x5 U/ S, p( O7 ?" Q$ \$ poutput mcasp_afsr,
) u: Y9 K+ ]* H4 `output mcasp_ahclkr,
* J6 r2 ]6 e3 k$ y! @4 K1 coutput mcasp_aclkr,
/ R0 `9 m$ _ q0 x( A; H$ voutput axr1,
; F0 O6 ?' ]& v! D) K, F6 t' v assign mcasp_afsr = mcasp_afsx;
T, U0 D; z8 N/ j2 P5 I, n. lassign mcasp_aclkr = mcasp_aclkx;* p- \( \3 N9 B
assign mcasp_ahclkr = mcasp_ahclkx;
2 V4 J. Z7 e+ v2 L& V0 qassign axr1 = axr0; % [1 k( v2 p1 [' C- {3 a' F t2 L
) z0 }/ k6 A& t( [" j4 [/ |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ y5 s0 \3 ]4 E; B
static void McASPI2SConfigure(void)
& R! s+ a0 m+ Y" `$ E$ J{$ w V4 P) v+ r, J, g! Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( n; F- p+ M4 T( M( l$ S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 ^5 s* @' n2 T; d& \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: c5 L0 x4 r8 ^- t1 w! KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. B7 |" h: N6 ~: X5 z8 ?/ \" CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," }2 y1 g% }7 b& B6 w1 f/ m* Z
MCASP_RX_MODE_DMA);
. B, [+ d5 w( ^+ I2 D/ pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! W' V* L* k! G& W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! x, M& o: X: G7 i. Q0 r) a( W* v. wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : L/ o' F) c/ v9 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; e4 o6 y( c% r4 j) G$ K3 ~6 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, X' m- Z: ]* L1 j) D& w$ W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 f/ t8 d, Q% n9 E( Z9 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' c" C8 n5 Y! n% k" O2 o" qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; p; u4 h* }: {0 s+ l8 @" P2 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% w& J1 w: i# o/ h; t- }
0x00, 0xFF); /* configure the clock for transmitter */2 E- K# U, P; H0 B0 e# J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# z4 f6 h3 k wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 ~$ o% u8 W6 W" n1 t" u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* Z0 f9 j7 W+ e& ^& n
0x00, 0xFF);7 J6 _, S$ s* G$ M% p6 Z# N
. y8 Z' ?% t2 ]1 k: S* r: y1 K$ g$ G
/* Enable synchronization of RX and TX sections */ $ \& m" G, m# ? I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& z1 ~4 ~2 I% e3 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, d& ~3 t6 A3 f! o+ C+ k. g* ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; e. O \" i7 L C% y( Y( z2 f
** Set the serializers, Currently only one serializer is set as$ s8 K3 F3 b" n( L8 ~
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; {2 V- `1 h) ^2 j1 }! W# dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, v3 ~9 ]. h: E
** Configure the McASP pins & x0 J$ @+ ^0 _5 v5 r
** Input - Frame Sync, Clock and Serializer Rx- i( N) P$ ?- S$ }7 [6 r0 B7 y. ]
** Output - Serializer Tx is connected to the input of the codec ! _) M' E# Q7 V/ u# v
*/7 u ~5 R$ | r& {. @% l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, p6 D% Z/ F- `3 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
N$ P4 t* Q8 p' p H4 X8 h( VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- y* R/ A3 P) Y, z, D0 z
| MCASP_PIN_ACLKX
8 [* g9 I8 o# _0 E1 l| MCASP_PIN_AHCLKX
1 S7 P8 U5 E u0 ~# X# D8 o; l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 U% b+ c% V& l3 n2 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. q' x/ f- z) ~. C% m, n% o1 j| MCASP_TX_CLKFAIL
9 |1 \% l% h& N: E0 c| MCASP_TX_SYNCERROR2 N% A8 W+ m1 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / V9 [+ q6 O7 p: }+ R6 c
| MCASP_RX_CLKFAIL
r' c3 E" q) G; I( j( v. o| MCASP_RX_SYNCERROR
1 y1 C0 ~7 N" d8 [. d: ?1 x| MCASP_RX_OVERRUN);+ F3 `: T9 b( @, v
} static void I2SDataTxRxActivate(void)# q4 Y) `& W4 Q/ C5 I# B2 F
{
$ X( z p0 c0 O/* Start the clocks */# j- G6 m; c( f, Z, w0 G* c+ _+ [& M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 V8 b+ j; f4 j- Z% D7 B' h" B/ v. ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 i3 i: A+ W* e; q/ ]& R% o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 X' [! Z# U |2 c, m5 KEDMA3_TRIG_MODE_EVENT);
9 ^9 j u( u- z) q! o! g( `, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& I/ p! f1 Z3 oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ ~7 [5 l3 x- X! `) m' XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: v" g% U) {7 H4 O M) L6 `% ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, d0 h) c+ `% ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( G* F' {( z, S* f; e+ N0 m6 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- k: M. u8 u% W+ {- B8 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- n( |4 d; ]# K7 Q0 ~/ j} . Y$ i) E! }! H- f1 M5 ~7 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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