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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ w* v, Y( T- t
input mcasp_ahclkx,
5 Z4 z4 f/ H. L% B u, iinput mcasp_aclkx,* o5 h3 L% P P9 T$ \. C* l) T
input axr0,3 u$ W3 ~; c, @$ U/ [2 E2 N# u
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output mcasp_afsr,
# D/ j9 s6 I5 h6 F" |5 l" Noutput mcasp_ahclkr,! u# z' a9 [6 t/ J& E0 f M
output mcasp_aclkr,! R. O1 t8 s( n
output axr1,
, b1 Z& \7 S" _$ e3 d3 L" G& n R' r# [# F assign mcasp_afsr = mcasp_afsx;4 Z m# X" ]; [5 E+ t4 j
assign mcasp_aclkr = mcasp_aclkx;
7 W+ ~- V+ }" T8 k4 ~5 bassign mcasp_ahclkr = mcasp_ahclkx;
+ T1 X/ D. _# y8 ?" v) ~assign axr1 = axr0; . |0 [: {+ O# k( q" x8 b7 e
. Z: f/ R, o9 F; H: {* M& }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 k" z9 O4 w2 x- o* |
static void McASPI2SConfigure(void)% ~5 M" w, [: H/ k6 D" `
{
! j5 _: p- Z2 x, nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' \" V. g- S/ n. s! ]3 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
h4 E! h% |8 P) ?9 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 m+ J% r( q/ N9 m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; P5 B2 n6 a3 n/ P0 _1 D" |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 h4 B3 p0 w4 p3 I. f
MCASP_RX_MODE_DMA);
, e* e+ l* u3 F |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ M" Q& s! c) B. t( u- TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// d! X1 F# _8 Z" J s) q# T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 V# {, V% @3 x7 h& A: `4 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 Y- x) d8 v. xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 ]0 e/ N* k; I' ?% c; K: NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 K- x9 Z( c. I2 I5 ^" D5 f% aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. O0 j8 I7 [5 J8 a) a7 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 A+ Q* e" P0 ] A8 B! K! eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, E/ t0 m* k* k8 o. L6 s
0x00, 0xFF); /* configure the clock for transmitter */# H7 b# i6 w! E X5 z$ g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ ~) F6 f; B0 z( ]8 }$ ?$ Q0 r' w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * p; x* k( d/ ?5 T& B& t8 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( |: b- h5 @0 O# ?4 t
0x00, 0xFF);
- s& q- k& U1 W5 x9 \5 B+ m( J) P" V! L: g
/* Enable synchronization of RX and TX sections */ / B$ u# q4 B, O2 d* G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 r8 p0 g$ M# i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- o- W! Q% v# e# DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! Q. m& U, [6 y l/ s! J** Set the serializers, Currently only one serializer is set as
+ p+ f- }* B" o) B8 p0 l7 \* i** transmitter and one serializer as receiver.5 O8 R0 ]6 y2 c# p/ [+ t" @- l
*/9 P7 I# x! M9 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 v+ d3 P- t! X: X3 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- S/ s$ B- T) O& l# o! l
** Configure the McASP pins
/ `: s7 I- a( B/ W T** Input - Frame Sync, Clock and Serializer Rx
# L/ W7 @% J* [: e+ [! Z" A** Output - Serializer Tx is connected to the input of the codec
3 R0 _, S9 Z* K5 b7 t3 i' U*/
. m/ B/ g" X. s- SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" d, O: Y$ P, U$ |) u9 o& g" uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ u0 V5 w5 F2 @9 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" u ]! H! q2 H0 R7 k| MCASP_PIN_ACLKX
" k! d0 k) i8 d" q+ e8 D* a- a9 c| MCASP_PIN_AHCLKX& T5 X1 X- X# F! ?, U5 B i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: b/ C: V5 n; S" |* e3 wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, D# U# y) n8 I: ?. C| MCASP_TX_CLKFAIL 8 h4 l8 x% I; x, Q/ O
| MCASP_TX_SYNCERROR
/ }" D, o$ B3 M5 i* Z; S2 c$ O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- K0 v1 o6 L# G, Q| MCASP_RX_CLKFAIL
3 p+ w ?1 x" o; a, @- o| MCASP_RX_SYNCERROR
$ @$ U8 P7 m+ F) t9 }1 S| MCASP_RX_OVERRUN);' `" @3 ^8 O, C/ @+ [
} static void I2SDataTxRxActivate(void)
. B( r/ I* P2 P* E& G( r{
2 U: K8 E" K. F& U7 F/* Start the clocks */0 [% a' v `0 }! N6 _8 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 j1 |+ R( z9 w. Y( Z6 DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& }6 i7 S; ^8 y1 X$ J' VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ] w9 r$ Q/ m2 m4 S) K5 W
EDMA3_TRIG_MODE_EVENT);2 q" l' d* I7 N7 y0 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 |, w: |) T; I2 `0 ]! F9 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* r7 @ A7 z5 s* A; f9 q% N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& u4 ?6 c w: k# K( Q/ }# C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 N, T9 k* t3 B! d9 n8 Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ u2 K6 n5 Q4 j4 ^! t. ?' j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# b0 A2 ~- a. y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 o- G( o( q/ D- D; Q; ?, ]} V7 T2 d% [+ M) r9 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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