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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ d* M& f4 L8 Dinput mcasp_ahclkx,2 a8 b1 [& \# U6 z4 T! ^; e. p
input mcasp_aclkx,% ^9 D; l2 O0 Z7 Z3 K( H
input axr0,
) @, {9 w, F* F8 E
' s% g/ b7 F$ coutput mcasp_afsr,% A/ k* e* G! X* D8 q2 y
output mcasp_ahclkr,& }3 Y* v T% d ]; S
output mcasp_aclkr,
. Q; Y1 T, V. t( s4 Qoutput axr1,
$ g, G: H1 l/ U assign mcasp_afsr = mcasp_afsx;
- q. m4 J. ^4 d+ v7 a9 N3 qassign mcasp_aclkr = mcasp_aclkx;
& |2 }/ t4 r* E/ h. wassign mcasp_ahclkr = mcasp_ahclkx;
, F+ A8 R# q: i! e- X2 ~assign axr1 = axr0;
( m$ _/ V( X% w" |& e5 h9 `! L# @
# D$ Q& ^: I. X y6 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - r+ Y% K8 ] F1 A4 g% X
static void McASPI2SConfigure(void)
6 T' G1 M4 T4 }3 h' @{
6 [3 o' l _+ V ]. kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; ~7 i" r& M) Z) b) @2 f) p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ ~3 j0 \. a0 l( l: A+ fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 w, P) O9 Z( o; R% G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, F# v' T, \. |) {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ s$ L; a( V7 UMCASP_RX_MODE_DMA);; [) U4 F' T) h0 S3 k* Y" x% r5 C e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ |3 M2 @, {3 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 Z0 r7 o/ f2 A7 S ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# o) O O3 Z7 f5 R, y3 V) NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# E4 |& r; O5 L$ ^: KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 Y" m1 O) @2 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; c' X' l- X9 B" VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ O8 ?- `( D7 Z' m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( D/ T# o W) G) n3 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 Z# r( d* S5 c, F4 l9 F( Z( X9 M
0x00, 0xFF); /* configure the clock for transmitter */5 s" v+ J& m! J4 M4 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ~9 b& j- _! [! G; @) v6 D% vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; w: s: @& D) I! s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 ?9 D' R2 ~$ G9 m1 W! {4 L& ^- \0x00, 0xFF);1 b* q" f w4 W
- |1 u" L& l, V G# J' F
/* Enable synchronization of RX and TX sections */ 4 m' u0 |- v: p7 t) Q5 h5 q3 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( j c4 y9 w- D% T; d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 y( i. f: C3 u* I/ d1 ?* u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( e6 {! o* n' R) s) Q. `0 { [
** Set the serializers, Currently only one serializer is set as
8 D [7 z9 r: H4 V** transmitter and one serializer as receiver.
# R- T8 n* f6 u*/
; o4 H8 o3 j: s- ^8 W6 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) L2 m) s2 Q2 D- B" b5 n# L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 s# h- x; Z' v v1 x+ q( ]2 k** Configure the McASP pins - l* ]* y" C2 Y; S* V, h
** Input - Frame Sync, Clock and Serializer Rx
l. V& s: b7 N! s9 G* [- A** Output - Serializer Tx is connected to the input of the codec 1 B; r6 i F0 ~) [' X. g
*/
+ A2 T3 ~6 e9 aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* Z: N8 b; _+ b4 E2 \* s5 Z( M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 L" j6 ?+ w1 p/ M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 c" }0 c- |$ z% o% z
| MCASP_PIN_ACLKX
- _2 N/ ?' q6 r! b3 i| MCASP_PIN_AHCLKX
1 i% D9 E+ n. `: N4 h8 o/ ]+ f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; ^( w7 I2 q* }6 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 E- [. h: U8 m- c! E
| MCASP_TX_CLKFAIL 1 Q3 K) n; V/ H, S6 ~' r% M+ X2 M# F, X
| MCASP_TX_SYNCERROR2 @% z) @' r1 \1 A3 R2 J* o. q9 `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: M7 P" b& y" B6 T0 C1 P: }| MCASP_RX_CLKFAIL) c7 F6 A6 P- m( A$ W( r
| MCASP_RX_SYNCERROR * |; T: a; c1 f
| MCASP_RX_OVERRUN);
* T0 }5 ^1 u+ Q" b} static void I2SDataTxRxActivate(void)
' j8 r( {# C7 _ `, p% y2 B) j{
/ ^" A3 {9 p+ @4 o/ X/* Start the clocks */
m9 G! f6 ~/ P) j2 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 x- ^6 J& n- C5 j5 X5 V5 x9 G* g: L' ]0 XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, d6 z0 E' f1 j# b3 b/ D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 ?. [2 V9 F- n6 G
EDMA3_TRIG_MODE_EVENT);
, N% O( e0 a' V. k pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 H( N0 `; _6 dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) @2 \& ^; W, M- T( ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
a, Y( W' A( W9 e' l0 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. n8 f2 K* a5 W+ @( Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. A6 g1 `6 r: ~2 W2 U/ E( w( \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 y5 T8 s1 B1 [: [; j6 X7 X3 `5 \0 K, h4 LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 D2 U. [/ k& U* A9 X$ r7 ]* a}
% `$ p% ^& J+ j( T2 p1 P+ I# M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , S1 ^) t2 w5 {
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