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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, p3 e5 e! i0 }& S E6 P9 w
input mcasp_ahclkx,
" O8 K8 q w1 Z8 V/ f* A+ winput mcasp_aclkx,
" o( @- O; G3 y& B* ?0 \input axr0,2 r! a3 Z- E/ {$ k3 g
& ?9 A# @5 [/ D- Y4 E) I+ E- _
output mcasp_afsr,) ^5 `' w% q7 K/ h0 \
output mcasp_ahclkr,8 n s, i) }2 F$ V
output mcasp_aclkr,
8 f3 [# [; q8 G4 d) s; J# aoutput axr1,
8 d$ ~0 K7 \, x: o; Z* M" u assign mcasp_afsr = mcasp_afsx;
( t) k D7 w- ]$ Bassign mcasp_aclkr = mcasp_aclkx;& X$ U8 e* ~6 M9 S( Y
assign mcasp_ahclkr = mcasp_ahclkx;) J3 ?0 ?6 e6 i0 |1 v
assign axr1 = axr0;
M) {* ?/ ]/ L0 K1 D! a6 z" Q- [ R ^: r" \0 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# X8 _2 j8 o `, P8 @$ sstatic void McASPI2SConfigure(void)6 y( ?/ S6 r) B; r( v
{9 g2 d! J* n, _0 _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 R/ A: b7 b T& I3 s" y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 Z C. a6 D. } w4 ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! O# ?/ x% {. a( ]$ k. ?2 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) }1 \% S) Q' s+ YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 m9 B, {+ b' _8 s. |" Y
MCASP_RX_MODE_DMA);
% L. D4 h8 X6 q8 c' C- u9 m! _; LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 Z' L; F1 p m6 k. Q" r! LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. u3 \ i3 j3 w3 t H! cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; H* W! i# ?+ y1 Y& r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( j. D. ]/ e8 O; `: s F* p% XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: e$ v. M' q" t. ~" t- x$ `( q/ F- c: NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- z% F6 m8 Q- o/ x, g% N8 G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& H M/ A% r: r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 L4 T4 r& N1 V9 r' P S/ u( I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& i) D6 [4 _0 ~0x00, 0xFF); /* configure the clock for transmitter */1 I' m* _& d: ]9 ]: D" B2 V' c; l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! _0 I3 P, p4 }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 Q0 C5 W* ~& [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! z' Z9 }6 W3 R6 F# c0x00, 0xFF);/ |: V% @/ Y3 _& o
: s o* v* v5 g% ]/ F$ b/ m: ~6 @$ P/* Enable synchronization of RX and TX sections */ ( j5 k9 [5 C' g7 E1 P4 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 D7 K$ W' k) d: y$ LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! X# @3 G# ~9 I% ~" Q) ~5 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 ^8 G+ M3 T) t; }/ k0 B
** Set the serializers, Currently only one serializer is set as; A) j% J" f% ^2 I5 B& V" U
** transmitter and one serializer as receiver.
& T" R5 {7 Y9 Q/ s1 m*/
2 M( N6 J4 ?; L# ^* O2 _ h3 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ I/ A* X4 a( U, W9 VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 m7 K, x; v- u* u+ C7 v
** Configure the McASP pins 0 D* t. S6 Y, ~" |) x3 \' i
** Input - Frame Sync, Clock and Serializer Rx
3 I! u5 d6 E, Y- G6 [: t4 U** Output - Serializer Tx is connected to the input of the codec
6 _( G2 K$ {/ k% j*/' |+ W* c% V" y7 s0 J9 B3 ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% D g0 R' B: fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# B) z6 J' E: c- j+ K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% x8 L+ R- m4 e; A1 [3 A. u5 M& X; E| MCASP_PIN_ACLKX z1 V: K, X( i; T$ b. K6 C: Y
| MCASP_PIN_AHCLKX
) B/ |# H' |9 I+ J1 o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ @! p8 K" G+ B M, L/ SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' {9 z$ w# x8 j% |: O| MCASP_TX_CLKFAIL + E5 f+ `9 z. G, o! S8 t
| MCASP_TX_SYNCERROR( Q& U% }4 G3 y2 H1 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. V2 j& A0 L* l: ^; B8 Q| MCASP_RX_CLKFAIL
9 m) S/ v2 q4 z| MCASP_RX_SYNCERROR
8 D$ D2 d5 }6 v6 y| MCASP_RX_OVERRUN);0 H& e2 q, }0 ^7 j* X
} static void I2SDataTxRxActivate(void)
& m/ u. P/ W1 v4 [! w{( g" R+ r! w! ]) ^: e
/* Start the clocks */
- n8 F( d- B: d+ Q$ {, `: z5 u8 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 |. P& _5 x) ~8 @9 u! uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 ~9 @1 U$ z' e2 f' c* m" H! IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# G! a# @# A8 ^5 U
EDMA3_TRIG_MODE_EVENT);) n- L) v1 Z7 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ o' J7 c0 }5 h. U! U! J0 o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ r. C+ S) e1 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% }8 F4 V" ~- s OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 r+ A1 C3 {8 N- G) Y+ o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, _& _1 G+ q! X4 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& x5 I9 |4 a) X$ b% m ~9 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& j+ e3 e# H; l O6 r3 f- r
} 3 H9 ~1 Y9 M8 C& o6 n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) c$ B- [& z" ~# G. A- Z
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