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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ u3 {) Z5 z/ O" sinput mcasp_ahclkx,
: m3 m, J5 O8 o$ M7 g, B5 Xinput mcasp_aclkx,; ~7 {5 r: x8 K1 N# o& Z
input axr0,1 h& l3 ], _) u8 @
0 u0 w0 a- a1 U1 x+ L6 I6 k# \. c5 e
output mcasp_afsr,% F4 ]- D9 M3 b& V" b+ l
output mcasp_ahclkr,; e' \" A+ |2 l
output mcasp_aclkr,7 I3 G! R+ U2 ^. L8 @9 ^! i4 N
output axr1,
0 r3 l z- N$ j& x/ S assign mcasp_afsr = mcasp_afsx;/ U' z7 a6 p/ Q' ?" G$ ~
assign mcasp_aclkr = mcasp_aclkx;
8 P, ?+ W7 u$ t- l3 r" v" ~assign mcasp_ahclkr = mcasp_ahclkx;! `* G) J3 A2 ?% `/ M
assign axr1 = axr0; 3 v# W# }8 T) \/ b6 m( | ?
: B P1 f5 k+ _# h, I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : {7 Y3 c- S5 Z6 }/ p( Z
static void McASPI2SConfigure(void)1 p$ R8 }$ j, g3 Y# ~6 u
{9 |/ y4 n) b4 L1 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 s- k1 ^7 S; v- V" vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* { k. W( H+ F+ B1 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, a& ]3 @4 K% G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 r" @* L9 G* w2 l7 s" L- _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 u" }8 Z. T0 G. l0 KMCASP_RX_MODE_DMA);
2 Y: v1 D: G2 {: A# q2 NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 r7 N% }' R- W6 U* P1 f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. j$ w( u. I' g ?5 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ d: ?8 R; u9 T( [" m" }/ D- w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( a- U7 B& f( I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # N* p2 z4 }, R2 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. N& A; H6 Y0 u5 VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 j Q) m) \1 s+ r1 C$ HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ L7 @8 j% f3 ~5 f, @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! ], B1 I: i; ^! {8 g, B9 i0x00, 0xFF); /* configure the clock for transmitter */
8 R6 _5 @$ }" U' q; E8 d- R8 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 `4 Z- @5 Z9 s3 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 E% t; z7 t& YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, @# `' O m _. C0 y
0x00, 0xFF);3 x& c& Q% B% A% D4 Y* b7 ]5 R
& @0 d/ c( v1 H) |/* Enable synchronization of RX and TX sections */ 6 m* H0 C0 O3 X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. q1 i) `; O6 `1 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* f6 d j, J) u2 h5 D! WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, W0 B5 R$ j8 i+ o* f** Set the serializers, Currently only one serializer is set as
9 ]7 ^+ _: N- ]+ P, W$ W** transmitter and one serializer as receiver.
7 v7 j$ K% Z* M3 c/ S( B*/% ?1 P7 v% ?3 P2 D/ e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, f: i8 ^2 v. h$ E3 i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 H8 H% g* J6 X" T! a/ k** Configure the McASP pins
; E# F( d" }( e# r7 R4 ]** Input - Frame Sync, Clock and Serializer Rx
7 ^( b: G% u7 _( W5 s5 t c. @/ S! O** Output - Serializer Tx is connected to the input of the codec
. y6 c+ s# |6 R# V, Z4 x6 [*/2 a" r* m- B" ~8 Q8 B- P9 I4 m4 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" a5 I/ P( f- E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 _( J8 A7 ?; L! |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX u2 a4 x4 e4 ?, C7 J+ d
| MCASP_PIN_ACLKX
6 @5 |5 n3 q9 T9 A7 Z$ m; N* X| MCASP_PIN_AHCLKX
* Y% N% A& g. Z2 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// H( a. r3 M# V" e+ m s) t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 k) o! s0 d4 ?| MCASP_TX_CLKFAIL 7 C. X. ~: ~* o* p! n
| MCASP_TX_SYNCERROR2 V2 R& F4 j* \/ t2 J3 v4 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% R; l8 X' _6 l( } r| MCASP_RX_CLKFAIL( ^; {; U8 b8 C G( a9 C( J
| MCASP_RX_SYNCERROR
, P& Z( o5 S7 t( I, U7 D% _* x| MCASP_RX_OVERRUN);- M: Q5 T. Q. ]& N) G" }& n
} static void I2SDataTxRxActivate(void)
. L2 ]; p' D( l' S2 k! Z: k2 X2 e{
`5 z4 ]* m9 w p+ ?& Y- U" S% ~/* Start the clocks */, i, q1 |8 O+ ^/ y3 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 T- W3 \; m# n9 ? {6 F3 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ Q6 @( }7 Z3 t0 K* i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. K! x$ q! G% C& n8 wEDMA3_TRIG_MODE_EVENT);
- h2 K9 ]3 Q7 k1 F: ~7 f4 A6 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 E5 @: L: D! z( Z/ R, [) JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; _6 c$ A! V/ T# x: o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% n: @! k) R! HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% N \% i5 V- v4 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% ~# w: A# G) b) IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% W. O* S5 U( w p: m; A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( S, `* N: z0 o; m+ F
} $ i q3 I" d" P* g: s: M2 j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) U d* [! q B6 v/ G
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