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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 T5 L( b7 f* _
input mcasp_ahclkx,, a; k/ G ^. l% z" w
input mcasp_aclkx,3 c) ], l' O6 l
input axr0,% J, R/ a7 N7 F% X9 Y
, K2 G9 C( V* y( j7 `4 Coutput mcasp_afsr,
! }! g0 F" u% o( c7 n3 q9 Q0 ioutput mcasp_ahclkr,
- P. S0 J7 R7 `output mcasp_aclkr,
8 a# w' ?5 ?% F4 @0 ] uoutput axr1,
2 X$ `" D1 E% a0 \' ]' ^* I assign mcasp_afsr = mcasp_afsx;
+ Y- N: a# q- T. \/ bassign mcasp_aclkr = mcasp_aclkx;
5 D8 j+ s0 K/ p. a" d$ f- O8 Qassign mcasp_ahclkr = mcasp_ahclkx;+ k! f( q4 X- C$ `! j& ]) x
assign axr1 = axr0; 7 [& h- F9 l/ X. Y) A, ^. E% m2 \
/ x# V; t" D; m9 Q1 B# G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) `8 | ]" {+ x: ]- z+ P6 Qstatic void McASPI2SConfigure(void)+ v3 p/ l" u- W: _+ G3 J E2 e
{
) @9 M" j7 J0 s( _" ^4 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- H' o {" k5 a. q3 ]2 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; [7 C6 k* h% a4 h2 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: Z& T. N" U* S% K. D) vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 {8 Z$ @$ X* J, W( \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 M4 f9 p$ \: p* D4 Q0 F
MCASP_RX_MODE_DMA);
; P: ?7 t6 o0 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& P" C7 h, @9 K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' Y/ h! y8 G9 y2 ?: u5 l/ g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 B$ |' f! H& Q5 B1 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* S6 m) `. z+ C% c& p, l1 o% d; G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! W, z: ^1 d7 t, d3 J, O* J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. I1 d; o) M( m# aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( n' [" c8 c' p7 P- b6 E5 `) N" O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : D8 V/ g" S$ l# f6 w4 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% n Y: O0 M; ?# y2 Q9 _; T0x00, 0xFF); /* configure the clock for transmitter */
; l+ z* }" J( F! S5 p* I/ QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 P4 f6 Q8 [2 U0 Z' r9 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) o( z4 l# ~; K3 N8 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 W! s$ ^8 G3 o( C9 G0x00, 0xFF);8 K) {* `1 V$ s: ~3 B
) l1 j. W4 G+ y* o
/* Enable synchronization of RX and TX sections */ * V. z, y' _ p* o& Z% e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( V- o( b N0 d' v7 N% }) |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' b' o) J6 O* Y1 C# N$ GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# P d% S2 A0 T H6 U% [
** Set the serializers, Currently only one serializer is set as/ c: V6 Y* B5 _; k
** transmitter and one serializer as receiver.
4 g( L5 ~2 m: {% E) w0 l*/# i0 S; n* K/ \/ ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 ]* G. v N" h+ U2 ^: k9 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' M0 Y/ o) p9 K1 z" e% E
** Configure the McASP pins + i- G3 {6 }' q
** Input - Frame Sync, Clock and Serializer Rx
+ k6 J9 O7 ]& b* x- G9 o4 h** Output - Serializer Tx is connected to the input of the codec 6 N1 h9 h3 ]4 [- o
*/ c+ k# Y. @' ]/ `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: Q5 _" R8 ^$ z: I* hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ e; b1 J3 e9 E7 O5 J3 t4 f" t8 AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, D1 w& o8 ]% `3 ~
| MCASP_PIN_ACLKX3 v1 I/ E J- w2 }" t) P
| MCASP_PIN_AHCLKX
- ~' I% S* g7 `& z/ Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) u: X; r1 r- z" z0 ~7 R R$ M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 r) H; B9 I$ L! O! h1 [| MCASP_TX_CLKFAIL . _6 ~! S: O+ M3 H3 W Q% k
| MCASP_TX_SYNCERROR
k8 C* H6 U7 j9 h G( l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' _/ i! j) _; I6 j: F9 i
| MCASP_RX_CLKFAIL
7 Q3 s; D) I& i$ Q| MCASP_RX_SYNCERROR
* `! o5 j `) z* j0 O' G5 ?% b; {| MCASP_RX_OVERRUN);5 c3 ?4 t( w' k2 o, k
} static void I2SDataTxRxActivate(void)
! i* I4 b. m: M- C3 I4 t$ D B{
( |, I& V: c8 z. N/* Start the clocks */, a5 x, t) v B [) p: ]+ I6 g G. ^' z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: U. U; k# P8 v" LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! D/ X- w" M; @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, d) k; W' k3 ?* _1 W8 PEDMA3_TRIG_MODE_EVENT);1 E1 [. h. H1 |# i( O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - _% c# P5 I" g+ T+ G& d3 \: K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 m: I! `8 S/ ~& {# a8 C _& zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ k/ e0 ]/ w* YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 j5 C! m1 h; B5 B& O" ^3 H, Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ Q. _1 _ E% c) x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 |4 \ B# s0 T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 d. Y9 y6 n5 y1 I' s8 }! h! j
}
, G+ _/ x& g1 B3 R/ w) k$ O3 B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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