|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 X' o' d2 V4 O5 _input mcasp_ahclkx,& Q% \' o6 h: q2 V
input mcasp_aclkx,
7 F3 t- h+ m9 {8 ]( Vinput axr0,# T' G2 @) C& ?1 f* i, h# U# h
" r4 ?* x2 E$ l4 J: j
output mcasp_afsr,; \1 ?( h1 A/ R7 e; t5 W
output mcasp_ahclkr,2 V# c! z1 x$ m. D p
output mcasp_aclkr,5 [; _7 c( `" J
output axr1,3 ^9 S+ _: f; t+ A* ]+ x8 y
assign mcasp_afsr = mcasp_afsx;
0 B9 l, c- `* X9 @" Lassign mcasp_aclkr = mcasp_aclkx;. x& _) I; c! X- h3 [7 A
assign mcasp_ahclkr = mcasp_ahclkx;- n& a& ^. B! P% m: m
assign axr1 = axr0;
1 U. F. r" t0 I" f0 H" n( S( w' @9 H& e" @: n4 F4 b$ m& N; ?6 @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 Z( g: f4 C7 z
static void McASPI2SConfigure(void)3 n% h* N1 p; g
{" ]# y# a6 h$ ^! x& R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 k4 ]3 _. z A! eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 @/ u! Q8 T2 t# {# R1 u6 o- ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ @6 T) U. F5 d; C0 g2 E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* x5 e- `& D6 |$ a `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* \- j& E$ I# h, rMCASP_RX_MODE_DMA);
) ]* P' e" L% c( J3 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 q, F% \# K) Y. Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 w$ B+ }- x2 j1 @* o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; L# l$ }, x- g! Q; e, ? v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 B% V, b+ ^3 K: t8 k7 S( EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; T+ B5 U8 J" h: rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, s$ a7 y# R* J2 T) KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 @. Y( S5 e2 u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& a8 k$ u0 {( e8 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& L1 r0 O: Y- F, [2 N* V
0x00, 0xFF); /* configure the clock for transmitter */
! E1 }9 t0 j5 F; xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 A4 q- d8 Q2 p1 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - k& I4 F2 K( A/ U7 H( t j$ }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# e& ?5 ^) J- `# e
0x00, 0xFF);! {7 i2 I8 o0 f$ G( x3 {1 y
" Y+ R- w" ^( R4 P( j/* Enable synchronization of RX and TX sections */ + R1 Y& \/ Y; S0 }, L$ N# @9 s p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* k% p$ Y' ]; S2 n$ b' n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& ~, [+ q) G% m q4 \* f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) ~5 S0 G) \. D+ z; p1 n4 r
** Set the serializers, Currently only one serializer is set as
! x$ k3 j* U/ y/ o$ Q& p2 z** transmitter and one serializer as receiver.
# `& e6 ^+ k+ t5 e# l*/
- G/ a! H/ H! a0 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* }( [* D5 {2 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& f N3 h2 a4 E/ [
** Configure the McASP pins
' N( E6 I9 u. J- i' {5 ]** Input - Frame Sync, Clock and Serializer Rx6 i4 g' z: l4 w0 q) s) N# O
** Output - Serializer Tx is connected to the input of the codec
" n o" e2 U/ l4 m- ]/ L*/
) b, o/ ?! M' [1 r. X( D: tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% b% d' s+ S. `) j N( M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, K4 k- d( I# X5 G0 f1 |6 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 F4 M% @' F3 ]6 t: U8 g
| MCASP_PIN_ACLKX
" y0 M% P$ b% E0 S3 Q* J| MCASP_PIN_AHCLKX6 x6 P3 ]6 R; d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 ~2 o6 W6 O0 ~0 X0 c. K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 I; \4 ?* r' [| MCASP_TX_CLKFAIL
# \ p, A' W. Q* |3 H D; m( R| MCASP_TX_SYNCERROR S: f) D8 K# v3 }9 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, Y+ Z0 u- D% g% m( U% \! s5 K| MCASP_RX_CLKFAIL
6 @) r2 m& _: g) R" s, R| MCASP_RX_SYNCERROR 0 a/ x; p% W8 x% ^% A; C
| MCASP_RX_OVERRUN);+ ]" Z' J" M$ C1 ^; m# d
} static void I2SDataTxRxActivate(void)# [; K4 M! K. L s6 C( }
{. Y6 ~7 H/ K( l+ l* }+ B2 {
/* Start the clocks */. f% I' G2 |! }, }/ j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 U. j' m# O# J; h: t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( [3 F. Y8 f# W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* y1 `- p* @$ a- f, `EDMA3_TRIG_MODE_EVENT);; j9 A, o l9 W1 Y# P; J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, k' r( U9 O# R* l- TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' }$ @, N7 c9 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 g; P V( `. C' i7 ~& a: k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 l7 @8 b! R6 I" O7 s4 W# Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* ]; U- }! f. j b. \+ e/ q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' n8 p' a* B. M9 @) @( h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 g% ]3 n5 Z( i6 j+ {}
# h j$ s4 U" |% M1 F- S+ C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 f( R) m$ c! |* ]7 |$ Q |