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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 w% v. H& y% y/ k* i5 P0 f
input mcasp_ahclkx,
% u9 W+ M) J" j& I! Vinput mcasp_aclkx,0 I, e: {. F, e9 F$ e' y* D
input axr0,
0 t2 x# A! [6 C* I5 R2 v
' G* c1 r- z9 Xoutput mcasp_afsr,
( Z5 N( L: B* c6 e2 F, `output mcasp_ahclkr,
; k+ ~( S+ o W6 M; eoutput mcasp_aclkr,( k p1 g' V3 B9 ^" N; |
output axr1,
4 ?$ y" a* [, C2 h% O4 d assign mcasp_afsr = mcasp_afsx;3 l, S- |$ \/ ^' s$ A
assign mcasp_aclkr = mcasp_aclkx;% J0 _) m: ~+ A
assign mcasp_ahclkr = mcasp_ahclkx;7 y3 Y. N3 [/ N
assign axr1 = axr0;
) D% o2 ~1 L b3 _! P" r8 k9 \! i4 g5 j: P7 Z* U) g% }6 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" t+ q5 m" h' C7 m4 k" vstatic void McASPI2SConfigure(void), d' {1 _+ L7 V0 s: }' E7 H, c
{
' ]- Y1 D! L0 V# D' pMcASPRxReset(SOC_MCASP_0_CTRL_REGS); W( [5 i) {. h; p: d6 V4 R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- i" C: n4 M# c; ~. y7 p. A3 {2 J+ H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 O# F" Z# m. K# v& z8 ]5 ?: }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 o4 H; X3 k5 N* I, P+ t) h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* p1 A0 U( I3 S# I3 \ T. y
MCASP_RX_MODE_DMA);0 _- O+ z! T% J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 N3 D. A0 M7 _' `+ {7 L0 i1 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 c+ p+ k' _9 ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 c7 l, r9 h5 f. F4 P f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ F6 i u5 D3 c) AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 V$ }, |9 v fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 }) b% Z% D# v6 n- A* @% r G- ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 Q. m( C; C! W/ O5 Y4 L/ v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / T2 O1 N5 p1 h7 G; V9 b7 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ~$ A( w/ e3 H: P, y
0x00, 0xFF); /* configure the clock for transmitter */
* L- J0 z4 |% Z9 Y9 D5 OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! D5 K; q( w! s) g) jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ a) G- i) Z7 p8 w* ]. N8 TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' ]4 l- p8 t) M7 o% d
0x00, 0xFF);& P, Y8 O0 [& L8 V5 M7 U
* n$ C% c7 ~' g; W/* Enable synchronization of RX and TX sections */ * r/ D0 m, \8 M3 `5 k% [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 ]3 M& `/ T# P: z0 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 S% g4 z+ s" J0 H3 r a: j rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** o$ n+ a1 a/ E
** Set the serializers, Currently only one serializer is set as
/ t/ B; z8 I5 ]* |& e** transmitter and one serializer as receiver.( b, g, l( x% w5 z
*/% n1 H/ h- C2 B7 S. F! F' a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) E' _) T6 Z# p$ _/ LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' U- s( `# b6 D** Configure the McASP pins
# t- R0 a# Z3 q9 `6 E; r2 G7 |** Input - Frame Sync, Clock and Serializer Rx
3 j& R: y7 p" c1 k; Y3 K, e+ ~** Output - Serializer Tx is connected to the input of the codec
$ @3 i3 K3 {1 x7 \*/: V" z) z0 n, x2 U0 v6 I/ s' |% G! C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! P4 |/ @9 X' y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 }8 v6 p3 n8 ]# @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# n# I" s9 g( m6 x| MCASP_PIN_ACLKX) e! H- h# G( Y9 O$ O1 d7 F$ R
| MCASP_PIN_AHCLKX3 S/ M- V+ F$ Z( [% ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 ?5 Y/ T0 Z- D0 Z. P* L/ L2 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# ]4 T: s. J2 i# s+ U/ o| MCASP_TX_CLKFAIL
: Z3 r e! h3 w, z" o0 C9 Y| MCASP_TX_SYNCERROR
5 F& g1 A) \/ o% H- y! Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 {+ x; @7 Q7 |- N- p/ Y, W| MCASP_RX_CLKFAIL
# c2 i4 t: Z/ H( G1 m2 |: a| MCASP_RX_SYNCERROR ! E0 M2 J! r5 Q+ w) ^
| MCASP_RX_OVERRUN);
, n+ P6 h/ X- n2 }" j} static void I2SDataTxRxActivate(void)9 o% D- h" `( B& F, @/ Y F
{
. r2 I0 B2 a% g+ p" D# b2 V/ z/* Start the clocks */
p) u# d! e7 K3 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 j" W. @# S- _ p9 [* I4 t7 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ~8 e9 }; f+ C; hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 M5 G. n0 b% f- h
EDMA3_TRIG_MODE_EVENT);
0 E- U4 h. T$ R% M2 I' g$ QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 D0 p" _5 B' E$ Q- q( b0 {! eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' T# m5 S& v. O$ a. z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, u4 g, g8 Z3 P8 r7 P' y9 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' ~1 Q/ H: t4 T4 g2 q* f! Y- }- D3 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) y* A4 l2 e4 U2 W; k9 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, K$ x- v, ~+ U* f, P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: c7 E7 L; ^3 X) B} 3 X4 S' S# C& Y: f4 V7 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / I' z- A8 [1 p5 y5 m" {: K
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