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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ B: n( ]# V, M. Z9 n9 F
input mcasp_ahclkx,
8 n- D8 d1 x# y/ M% M/ A. a% Linput mcasp_aclkx,, M2 T0 u. L s# Y2 t4 p$ o: M* ?
input axr0," I; _: ]$ V8 K1 c5 _, K5 n/ E) `
' P# O* Q. x: W! X, w+ M
output mcasp_afsr,
0 e% R( f/ {1 S: J" {output mcasp_ahclkr,
( Q! W: |2 P X! Joutput mcasp_aclkr,4 z. t/ p. r7 L2 l
output axr1,
7 b Y, M/ M: u assign mcasp_afsr = mcasp_afsx;
. I* ~/ T# n j- a- M) F8 C8 L% Oassign mcasp_aclkr = mcasp_aclkx;
6 [- D5 K! d& d z0 P: iassign mcasp_ahclkr = mcasp_ahclkx;
. C0 q9 E, a4 Y( fassign axr1 = axr0; . y+ `3 l, F& ?/ o7 [
* k+ {9 j' L, u$ D% w8 L2 ^* y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 M6 P5 j7 {" }9 @3 Wstatic void McASPI2SConfigure(void)
" {, q+ ], [, w j* o{/ k+ P' f1 t; m$ C4 y" _! h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 a0 c: o5 t0 G0 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) z+ G6 K9 n7 D- _- @8 LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 m# S6 d; h p; x$ W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; X. R* c- T' S. r! G j# m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ~* I$ Y5 B0 s1 X; U
MCASP_RX_MODE_DMA);$ ]# K, o! G# N& ]; o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 s; D- h. m' N$ \# S( xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, p& L( D: Z7 O" eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, d' i: i' j; P) FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% e' D+ [, i1 n( [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 F8 |! P3 b; N5 _7 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ u4 u* z6 \4 v& ~! T4 a/ a$ J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ N" t. E! a" O l( q( _' |7 [# }2 aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 N, Z4 N! y9 \1 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: y; n# v. V8 ?) R; ?0x00, 0xFF); /* configure the clock for transmitter */
: V, p4 i5 F4 q& [9 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: Q; w5 X) T! m! q- `( R2 ^7 ^2 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( |/ } A* ^4 G8 y" ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 h7 D$ Q F- M$ O5 K0x00, 0xFF);+ c3 F: R' b [ Y- w& ^. h1 Z' j& t
' `* W" L; g% b) R4 o0 F/* Enable synchronization of RX and TX sections */ % f: D a; U0 H( q! T. |) ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ \+ h( l1 z9 \5 e1 K& A- s& R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* y1 _& m& |5 ^" U" O: nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 [: R; Q H3 \: l! S2 h( f** Set the serializers, Currently only one serializer is set as
, J" T& E5 `& }* Y0 T! p** transmitter and one serializer as receiver.2 E( P I+ }$ v0 a4 m
*/2 z. O2 a) J9 h. L+ R- n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" t* H5 n7 R( e# i( {: B% H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; M$ ]: F7 A/ }- V, }! T: O
** Configure the McASP pins ! ^0 X) t" v5 @6 I
** Input - Frame Sync, Clock and Serializer Rx
& y- I, _' e* |, R% T& ?' w** Output - Serializer Tx is connected to the input of the codec
' _) ~% M$ Z8 f8 x6 e- G*/+ f* ?9 g0 f+ m! M/ u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. @: K p6 V1 ]% A6 j j9 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 o' l' _$ e# k) R. j; ^1 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: o1 H1 E( ~* d8 T2 Q! X| MCASP_PIN_ACLKX
( }& X* k! r6 j& V/ l7 l- J# A| MCASP_PIN_AHCLKX3 i' K6 L$ o3 m$ G2 Y6 H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ z" Y/ v+ h3 E; HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. g1 y5 r& d6 G) z7 [' [; \8 a| MCASP_TX_CLKFAIL
# y/ j# |0 D; X h) b: a$ N| MCASP_TX_SYNCERROR3 _$ R% l6 Y E; ?1 {. |9 P o5 s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . J4 L2 C: B- b
| MCASP_RX_CLKFAIL0 M+ J& N4 I2 I) j& J1 g0 n7 P
| MCASP_RX_SYNCERROR 1 g- r9 N t) q
| MCASP_RX_OVERRUN);; A" Q& S V, t( b2 v' v
} static void I2SDataTxRxActivate(void)( v8 F' k# E5 j# T1 ^
{# U3 z* u, _" g4 P
/* Start the clocks */
3 i8 {4 H; U7 G; e. o, n: FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) M, j$ h% X; k' Z# r N! R7 a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 R5 ]9 U% C( ?& Z/ V( o3 u$ J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ o; y w: e7 [% I4 h
EDMA3_TRIG_MODE_EVENT);- f" O, _& ^9 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 b; n6 d0 c( ^; @+ o1 g. k- uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) H- f% y) p- {6 j/ tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, i; ]) _/ ^* p1 P! a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 E; L+ e) t( N- Q( S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 }/ V, l' w& ^' s/ G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- f! P. g+ w8 P3 {7 S, C" j% J2 ]3 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 v$ ~7 i7 o% ?6 h, \4 A0 T
}
- n' j/ J. E( n1 E/ a/ U3 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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