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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% Y: c2 c1 u" }input mcasp_ahclkx,
* C3 z3 y# ^. Q6 ~ |3 E: G% einput mcasp_aclkx,
$ r( E# W+ ]% l# @0 ]input axr0,
S7 N% c& Z( W* T5 _, F* G/ ?$ o% v+ J' `" A
output mcasp_afsr,4 ^4 S& Q+ f$ F! |
output mcasp_ahclkr,
! u1 h6 P, ~) Eoutput mcasp_aclkr,0 z, H$ o2 q- {; ?
output axr1,
) a( y+ j, L& m assign mcasp_afsr = mcasp_afsx;
4 T& z: `2 \. ?assign mcasp_aclkr = mcasp_aclkx;! G: W) c: H2 {
assign mcasp_ahclkr = mcasp_ahclkx;
+ g) Q) c5 P2 ~7 y! g- a( R5 Bassign axr1 = axr0;
% _ s0 [" |. r8 b0 C* r3 {+ n& K# D; L- N) S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " k& O( z% l# J4 l/ F3 n# x. ^
static void McASPI2SConfigure(void)
7 ]0 K. l- g9 S- F/ H$ |+ G{
* g! E9 e3 i/ EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% t/ t; } ]$ \! AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. w# K0 H. b rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ p* `- q% Q2 L( T& W' ?( L5 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 Q/ H4 C& p& ?0 ]# f" q1 w9 K1 T4 XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- r0 C) G& `. S( I( J/ e! I' BMCASP_RX_MODE_DMA);" y: e& j# G! X1 ~" W: z- j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ k+ a, [4 N, {4 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 R. L6 m& n# |% H% t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, d+ Q- D6 i, ~ E {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: S5 {( I: d) @5 Z. MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ W( g7 O9 X) Q$ ~; I( GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ D$ y; M4 g5 w% W8 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ K" |, b, f9 L. i8 }& @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); C2 m% D5 R; X/ P- _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ J% F" q) e1 _6 i4 H0 D1 y. U0x00, 0xFF); /* configure the clock for transmitter */
! F5 w, C" H7 {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 H: r: S( X' O8 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 ~+ d) P7 f @! m" f+ \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 a2 o" S( w# G" }( A0x00, 0xFF);1 t0 U }$ p6 }( |4 Y
: j. | W, ^- X |- G& m/ v/ @
/* Enable synchronization of RX and TX sections */ 5 C! v7 A0 S Q+ r; E, A' X4 D8 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 b# l% f# p. K. }* G8 ^+ jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 S- g: J0 Y# @. v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* c4 L1 J$ D+ V. G9 j9 O** Set the serializers, Currently only one serializer is set as
" T. Y5 [% }- s; [$ |& x& g) W** transmitter and one serializer as receiver.
( k% V- D5 F! L7 x" }4 m3 m*/
2 z4 S) D& y& D/ h6 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, n: ^% x6 \3 W n- \& N# nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( g' ^; b- L( K% A( g, T** Configure the McASP pins K: l! z1 E! d4 `9 F+ J
** Input - Frame Sync, Clock and Serializer Rx
% N4 q. g0 I; @' v* ?3 c7 g** Output - Serializer Tx is connected to the input of the codec K4 E" z% A( {, `0 b; `8 J* E/ ^
*/
2 Q+ ?, ~; h4 {6 h$ Q9 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 x- B) i; N% \# T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ f) y R; ~5 g% d3 R5 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! G% Q0 K! V3 I( Q| MCASP_PIN_ACLKX, |- T& b) P; h8 D; L0 E
| MCASP_PIN_AHCLKX4 {& z" m K) ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ s% c7 K* l4 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % |$ {; F7 x' h
| MCASP_TX_CLKFAIL
. i* p& L8 ~0 Z# b7 R| MCASP_TX_SYNCERROR
, y3 j: X9 Q* z* ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . h' m# F5 `# N; d; w# N
| MCASP_RX_CLKFAIL* ]) [% h d0 p9 @$ @0 e4 l/ f" A
| MCASP_RX_SYNCERROR 8 F% L( \5 f- z+ J% T$ @
| MCASP_RX_OVERRUN);; {' @3 B) `' c, [/ B0 X
} static void I2SDataTxRxActivate(void)
0 m+ Q- P9 o& r: y/ `{; j W" d3 V1 Q/ i+ ~
/* Start the clocks */
& ^1 q, N5 B/ [& Y6 [! @8 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& G- c9 V0 R6 |. J# p$ _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& Y0 N& C# R* b+ d9 G( s& C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
W" n# {) U! Y2 X/ jEDMA3_TRIG_MODE_EVENT);
7 G5 N. i7 C% r3 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, k; R" F2 A' M2 T, T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# O# s, z8 W- I7 b. U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* i! Y* w' ~' B2 @: j# jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% D% Q2 [% U! }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# r, v5 x1 ^2 ?9 e+ p$ c3 ~ V4 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 `! G1 v+ L& z) y" ] e6 OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: U, A5 [* g* o% o3 R}
. ^/ z+ A2 X- t9 m: S1 B r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 b: N. X' _2 L( i& }& ^
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