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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! N& E e' k7 ?2 B3 m4 Tinput mcasp_ahclkx,
' n9 N( K R2 {6 P, g3 W+ kinput mcasp_aclkx,: G( y% s0 _6 D
input axr0,/ T/ |* O2 s* C
8 E2 r% }4 e x7 z4 }0 K; a6 Boutput mcasp_afsr,* }9 u' l8 O0 l6 c! D4 I* F
output mcasp_ahclkr,
0 _0 C8 P/ p- q( E- z: toutput mcasp_aclkr,
0 D+ v V: R, y* n" i. h1 ^output axr1,
5 H5 @2 F* ~( D/ C, c assign mcasp_afsr = mcasp_afsx;: n5 G8 Y, B- G! `# y) \. h
assign mcasp_aclkr = mcasp_aclkx;
9 d* ?& V2 u- ]7 I8 W- Q! p2 Passign mcasp_ahclkr = mcasp_ahclkx;
9 o/ ~4 T4 s) nassign axr1 = axr0;
' L& e ]5 W& K/ F* p8 c4 V
4 @$ m; g% J! M" s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# G( P0 V2 n- d t# Fstatic void McASPI2SConfigure(void): P5 G* K( x8 Z
{
1 [8 f( p% K1 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. {- e! H' j$ x w, R0 b( |4 k! P) fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: ^ W5 o h: U. {/ `; n1 K. KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 Q" y- a" L. ~0 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! @1 w2 e- f; d, e% `. f5 k9 T3 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 u: L4 K) ?- o9 V* ?1 u; k( d2 N- dMCASP_RX_MODE_DMA);! G+ t( I7 N) x* \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ]1 p% b7 E3 ^" W( q+ S9 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 B/ K( `) `7 U" HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! D' @+ n7 M) c* f( ~+ ?1 y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: C ^1 G0 A0 a3 d3 j* U& f* wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + N* O7 ?' \9 \. b% }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, b3 ]% q" m4 {) F! w9 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 ^- m' D4 F" u3 I' F) R- W: w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 ~9 y, z/ b8 b* H1 r3 h0 `. ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# d1 M( w' T0 d; L$ {- ^0x00, 0xFF); /* configure the clock for transmitter */& Y8 S1 @2 v. w) v1 m% ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 ]( ~: S+ g2 p- p1 ~5 @ j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " D. v0 v8 }4 b! ]* z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) N# e7 H; w J p7 b! R3 f8 R0x00, 0xFF);
a/ {" M, O3 S' u+ X7 V# \ q" m7 G" M
/* Enable synchronization of RX and TX sections */
1 A/ @ T) m5 d! ]$ k* |9 WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. j% I- |( n0 [! L8 |5 R% }5 S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) ]" R; K0 l; x; k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 d# v' Y/ G; ?0 T5 ]4 e** Set the serializers, Currently only one serializer is set as9 K& S( r6 O' j7 z! d1 P4 j' T% C, u
** transmitter and one serializer as receiver.5 I3 z3 z" R+ O/ ^/ d
*/2 j, C4 \ A& O& j& ~- g, P4 m7 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 x0 [! l! W5 I$ H6 l0 C; @% }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& D4 N: K% @' \1 l% h6 y% X
** Configure the McASP pins & j3 x; h% ?1 X
** Input - Frame Sync, Clock and Serializer Rx' q! K4 o+ H) R& n# H+ Z
** Output - Serializer Tx is connected to the input of the codec & T/ N" r4 N; ]4 ~7 T; Y
*/6 K1 C1 f3 x% Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: A1 ^+ {& s; p& }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' c1 u% m" I( t. bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* y! F- U/ L" o/ Q, {3 r c| MCASP_PIN_ACLKX
! @' f& o$ n# v0 F/ d| MCASP_PIN_AHCLKX3 h2 X- F1 u- e+ A: }/ Z2 H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" K( T0 s8 m4 s% J7 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 G. \5 c+ C7 ^9 b
| MCASP_TX_CLKFAIL
* k, E! W$ i1 r- \' d| MCASP_TX_SYNCERROR$ r' u' I- O8 h6 B3 T: \9 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. A$ X. K0 B& I0 || MCASP_RX_CLKFAIL
5 U8 v) k7 m6 h6 J| MCASP_RX_SYNCERROR - `% p; q2 w8 v/ ^: f: K
| MCASP_RX_OVERRUN);# l# X' V Y E8 D, {3 f# v
} static void I2SDataTxRxActivate(void)
$ A) i+ a1 l: \{
* I+ {4 A$ I, }- l9 @4 n4 W9 d/* Start the clocks */+ A, J$ N p2 ?6 e9 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ { N+ ?$ D, F! u) h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% \+ c8 J3 W& P0 |* T$ v7 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 v( s8 I4 E2 f
EDMA3_TRIG_MODE_EVENT);4 V/ A0 k, Z8 O) ~/ N" F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. X! p1 O: Y" s" Y9 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 a6 h e" J: E- a- ^! pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, C8 b! p4 s( _* {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 K2 J& B8 `# o+ L; ]/ g" s4 n# Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 _" Y1 E1 u9 e/ @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% D, V! z$ `, V* [* iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: S5 L5 Y. b4 t* x/ ?
}
7 K3 a3 ?; W6 h# Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 o2 i( u! p! y
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