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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, T- w( P9 r6 h. j0 pinput mcasp_ahclkx,
/ x+ [& C) e9 W/ z- A1 H0 finput mcasp_aclkx,
7 V9 V* w7 Y# |% n" d! y$ ?input axr0,( ^/ ^' g$ `3 G3 m, i/ }: v
* c; [1 a: r- z3 K Toutput mcasp_afsr,
- P$ [4 C( L5 t: Koutput mcasp_ahclkr,
5 L+ x0 l! Q. x$ Q1 B; houtput mcasp_aclkr,
" m1 g3 z( p( C- T$ K1 poutput axr1,! c8 d& d& `0 d8 \6 n1 R
assign mcasp_afsr = mcasp_afsx;
8 x3 |% d# u$ Y0 Z7 E4 E: l6 ~assign mcasp_aclkr = mcasp_aclkx;
; y2 f, v, a) Y h" n; Q, x& Cassign mcasp_ahclkr = mcasp_ahclkx;' N' {% w! h" K
assign axr1 = axr0; : _3 w: h0 D1 u/ i- e
) O8 f* ~) B+ ~" d, T- [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! J+ D/ e8 A7 e- n1 R" }8 B
static void McASPI2SConfigure(void)
8 i* C; ~" P$ @3 \ a{
! f! Q) c) b1 c9 ], a( yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 P; O( y/ ~, K3 ~* L* C3 u, ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 X \7 Y# l6 e; o. Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 b A8 @/ P* L+ \6 A# {3 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, r6 i3 T7 C) @2 J( |* r7 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 @1 e, k+ l9 ?' S1 \6 S
MCASP_RX_MODE_DMA);7 X `# C+ D( \6 }- X. G- Z b( L$ D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ r/ K7 @$ D! A3 h3 q$ [- T# _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ J! a, b' {0 D \% c+ K) o: ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 L( h7 Y! N7 s) C7 T; i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 _6 i. J+ e, W R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, S! {5 P8 U, w5 M9 k/ u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ i! }: e, r3 E- M; x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' p+ M- o" m: S' j, K/ B6 Z C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; L, U% |. _1 @: z% K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ }4 l/ z9 n& K$ H/ {1 P8 o/ y0x00, 0xFF); /* configure the clock for transmitter */
# J$ r X$ E O7 `* {0 y4 W; A( y+ sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; H5 \- D) n+ k; u5 o! b! P k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) z4 |" {& ^! u, x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 ^4 K1 y* o# O4 B: U% c0x00, 0xFF);
# S8 D( t+ x6 `3 s2 k, M. e4 ~( h) Z3 I! _% b
/* Enable synchronization of RX and TX sections */ / g1 c! Y) U: c: a* b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ e* P1 V4 q' C+ W1 n# P4 c, l, |5 Q8 vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( I' y% L2 p8 {4 F/ k6 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* T1 t+ h7 \$ B4 K& |7 J- _ |** Set the serializers, Currently only one serializer is set as
% Q) ?4 u: ]; [5 I: w) @% Y9 @** transmitter and one serializer as receiver.
" k. L1 n. J# f3 z& n3 C9 Q, l- ^*/" d/ k( `% g3 b) R6 ]% I' {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ x8 e' T5 M- Z+ I) x4 X$ z8 {/ S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) X& r! u$ i w. x
** Configure the McASP pins " L% o7 P1 i$ [& V% v" ?- n z
** Input - Frame Sync, Clock and Serializer Rx
, Y9 y B# u3 v/ w** Output - Serializer Tx is connected to the input of the codec
, b' j8 W. G3 J! K4 v*/; i/ t5 `+ @4 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) E8 M, w) v0 FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* s9 i) C! f* ]7 V* B9 z* _ v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, S2 L6 q$ k0 J( q; v6 h6 |) x| MCASP_PIN_ACLKX
0 w0 |( w9 y1 g8 @# p. d5 r; v* V| MCASP_PIN_AHCLKX2 c7 ~$ w5 T7 n. l9 K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" H; f( I3 d. ^0 K8 H# R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& K9 ~: P& ]4 ?& P| MCASP_TX_CLKFAIL - I+ }2 k3 E1 a$ C8 W1 i- G
| MCASP_TX_SYNCERROR
( }9 N; M+ A0 D( z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 ^8 h; p( g4 U3 p
| MCASP_RX_CLKFAIL
5 l! s w+ t$ l! a| MCASP_RX_SYNCERROR
, b5 v! ?3 G2 \/ D4 k& }| MCASP_RX_OVERRUN);
# R. v2 O5 k) v} static void I2SDataTxRxActivate(void); ^8 b: w. {: z' A
{
7 A$ h3 w+ t% B& t8 Q/* Start the clocks */( G2 @! R. s# z( e/ G# y! \7 O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 @! N- J. R" Q) S& ^: K# V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ f7 M% Z2 I/ Y: |+ _+ n; Y7 n# ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ j$ o& v# D" LEDMA3_TRIG_MODE_EVENT);
( g0 r v* G* E- E) BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% t: T# ^& U' X+ }$ z, AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: J$ T1 e8 k8 U3 L, n) h# s% dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 b" _ v4 m2 N: C! {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- E1 r1 `/ c% }- K$ _. @& ]" dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: D/ [$ c/ N8 b; h# S2 ?1 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, F/ x" ]! l# }% m' X4 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: W/ q" w9 X, h) N% y. F( N
} 1 A" d: n! p: \4 |- D, F" H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ Z/ { v+ J. F/ n
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