|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 B. G( o, j" X# finput mcasp_ahclkx,0 X# ~6 K/ F+ s$ d; i. s+ u1 z6 p
input mcasp_aclkx,
2 B& j5 b5 q. Y2 J% i7 einput axr0,2 F, m% X+ n U8 X4 q
! a$ ~7 U& K6 K6 Z( Aoutput mcasp_afsr,
3 l/ r# \. i! J! x# m- ]output mcasp_ahclkr,
7 Y0 G2 x9 d/ D* h2 ^output mcasp_aclkr,
7 D: _5 A4 _! H& {8 E8 r7 youtput axr1,6 X7 m0 w: D. m; H& T- T
assign mcasp_afsr = mcasp_afsx;! S% r$ N# p& \* b
assign mcasp_aclkr = mcasp_aclkx;0 ~4 k* f" |2 ~2 `6 N5 M
assign mcasp_ahclkr = mcasp_ahclkx;) q7 I, s! i7 M) z& O7 a9 o
assign axr1 = axr0;
' {9 a# }$ D. [1 ~) B
- u% T1 q, `& A$ U; v; O+ a; f6 M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - {9 f; M6 y% [" Z
static void McASPI2SConfigure(void)
% d* \: [0 H, q* {$ M0 P; ? b& G8 x{
! x$ E' {! @) i R1 B/ f6 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 b* F: G$ b4 Q" ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' v& D$ q$ l3 e! L) d: q1 ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 F' E3 @1 b' c* I; H3 X, e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 U2 H9 o1 u4 Y) E. M. G$ v' \0 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 J) q- |9 r; Y$ ]. Y- I
MCASP_RX_MODE_DMA);" ^8 J5 }& h/ m% O+ m, ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& ^4 F1 f( `! |, O$ h' V$ b- I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 ~6 f" H3 N& h; OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 }1 {/ v/ J! S; H9 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 a; H4 e, K. `: W4 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 ?" X. T, ~9 D4 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 L& ~3 ?' p1 w7 }" z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ c. k8 s5 x2 h* d! ]1 YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , S. M, M/ @5 w4 S2 A9 e# }, e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 A# h( n5 B7 i4 J# C
0x00, 0xFF); /* configure the clock for transmitter */
" u) N" v& B d9 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ t* W0 S6 k$ c' a( a" Y. HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 `# n! R3 c' wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ Y0 |0 J4 ` \8 Y+ z8 J. f" v9 G2 W0x00, 0xFF);
, i3 x7 M5 ~- L/ k
6 v8 K/ m' K) w9 y/* Enable synchronization of RX and TX sections */
. c% Y. e8 r5 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; _: U: _- L6 _: nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! a. x0 G% E3 | {$ K4 G! [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 n7 c4 u* N; E G9 q! y
** Set the serializers, Currently only one serializer is set as
* V4 y1 s8 N: m8 v4 x. Q2 Q** transmitter and one serializer as receiver.9 T& C6 U) a0 X; w f7 O# h
*/1 N7 U, O8 E. {6 b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 Q7 i M$ q/ p% d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( e3 [% V& p6 [8 ]
** Configure the McASP pins
% n0 G1 P# D5 M7 |. T+ I( ~4 p; R- V** Input - Frame Sync, Clock and Serializer Rx
9 C1 R& |1 m9 d: |' ^** Output - Serializer Tx is connected to the input of the codec
" s% c) n7 R2 G*/
& t% Y$ h; y2 X4 {* YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) a ~, o8 A8 F$ u" AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( a/ `/ U( m; \2 N8 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 f7 o8 }0 k O I l
| MCASP_PIN_ACLKX
H& g2 R Q% f| MCASP_PIN_AHCLKX; J& C& r( }7 Z7 r6 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. V& A1 @3 p* H/ gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* U' U' |7 f% e; B1 b| MCASP_TX_CLKFAIL
& u+ X3 _3 J$ K6 K| MCASP_TX_SYNCERROR9 p: b! g- l) }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, o/ F5 ]; N1 C: m| MCASP_RX_CLKFAIL+ u: @! i7 q0 n/ p0 M3 m$ {
| MCASP_RX_SYNCERROR
8 {9 Q# W( ~! t2 s| MCASP_RX_OVERRUN);
$ z5 o/ f7 b: D- K. z# n& Z$ c} static void I2SDataTxRxActivate(void)& f0 n. J- u* C& z
{
8 x+ m) _9 d8 F1 z5 W8 u( |! I/* Start the clocks */3 l% P9 o# U4 D* O5 @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 C4 u. `' a+ O. x: e$ L3 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- |+ ]( e9 S; v: B( u: q7 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- G& j) ^9 \* M! \' m' jEDMA3_TRIG_MODE_EVENT);0 }" I0 Y3 z. L3 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' H/ X( f) a3 O6 g% ]2 [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ {4 Z. i% }" g3 V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 w. W& E" l# `% \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# @2 _* t$ n, h. K$ j% M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 K" C( y- Z: ?. B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* x& u) N; T# t8 n x7 J" w- |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' B* }* ~8 c2 Y7 e& {. G0 p0 Q} 5 f5 L* a9 @- z# ^' a+ Z: S; x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 S. i8 @) `2 o* i: i3 E- u5 u
|