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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
f0 v+ t3 P4 ^input mcasp_ahclkx,. Y* b6 q) F- U9 ~1 I
input mcasp_aclkx,
) f |# w8 M. }. [input axr0,8 G, E3 k0 G& Y7 ^8 q- E9 \
# N9 i7 \( l3 f8 D& ^$ ~
output mcasp_afsr, ~" g" s: @0 m i1 R
output mcasp_ahclkr,
5 a3 J, \% r3 B o! ~" Foutput mcasp_aclkr,
4 w Q4 p0 S# K/ Zoutput axr1,0 r7 @! u& s0 u% A. b$ {* A S3 c2 {
assign mcasp_afsr = mcasp_afsx;
" {' {9 i" x, I, b3 X" t, tassign mcasp_aclkr = mcasp_aclkx;! K( F" t) o$ y) f
assign mcasp_ahclkr = mcasp_ahclkx;
. j0 y5 K5 X7 f6 @- _assign axr1 = axr0; ! ]$ l9 n n! T- K
2 m- p2 d, |0 F" w9 J" |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( [$ B9 C$ g7 k( j8 E; O( v5 Ystatic void McASPI2SConfigure(void)7 K& q& {) u, \
{
# [! W- g' q: b- M s5 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 H- X: O& n9 R* A& DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& O* Y# V2 e2 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" ^. {3 L* `# }; r" ~8 h, |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// Q0 v0 Z$ E! ~8 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, f1 y# ?. Y- R' E6 |. u- UMCASP_RX_MODE_DMA);6 m* |3 [5 ]; n) f9 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; [: g" u& B: P( V/ @ q- e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 k- Q& h& _5 n/ q" G y. h) V* H+ H: X7 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ @: b( y, q' f4 I; S% W& ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- K) E$ g$ E, I* x" e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - H: X% ^# y/ {( H8 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- K: ]$ i+ v4 d AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% g3 y9 z0 @+ J; f' t9 V8 P; v0 u7 L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 M. l5 S3 C- R: e: R: h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 V) `. A/ T9 o. U4 t& k0x00, 0xFF); /* configure the clock for transmitter */5 N' o$ t1 s0 _! S# a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ k. C8 G+ O" q: { L1 M$ T8 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 k$ Z2 `! y, [- q' h! C, d8 {9 _ gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 q% J& d7 B1 L
0x00, 0xFF);
2 A- D4 {! T; W) E; x2 `
) ~, [% l5 P Q/* Enable synchronization of RX and TX sections */ 9 [9 c1 M" |) O+ {% ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 w6 K. `- f3 Q; g6 x0 O; lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& s" g2 O$ F9 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 ]0 N5 e3 E5 C** Set the serializers, Currently only one serializer is set as1 R8 W7 C! U2 V( m! c- o
** transmitter and one serializer as receiver.: u1 Q: F; A9 u# K1 G1 E6 v
*/
& E8 [" p3 ]$ W2 I' yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 O9 V& d3 }; {! |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 A1 w+ i* Q& [6 X9 F. ^** Configure the McASP pins
2 _/ V! v5 G. A, X; B0 |** Input - Frame Sync, Clock and Serializer Rx
" |4 p {! h- U: \ A; Z** Output - Serializer Tx is connected to the input of the codec
& `& S7 l1 r3 Q0 B8 W2 Z*/$ l1 H- h% s1 A$ G- Y. P' L; Q4 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! y: n3 k0 Q" b, F! o! L5 Y! n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% k1 \( e1 [, s" K9 T* LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" t8 q& z3 j) Y9 [+ t8 p
| MCASP_PIN_ACLKX- L7 m2 R! a4 U& P5 c
| MCASP_PIN_AHCLKX
1 |4 f. I" ~, F" U; o: R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: Y( Y0 Z m# I& R: p' E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 U" K5 I+ c7 g( v& F# B v| MCASP_TX_CLKFAIL ' T$ y$ T# M7 {! K+ j
| MCASP_TX_SYNCERROR
$ Y( W5 {+ p* u. q, o% \2 V0 Y$ i4 R# \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 g& e/ f* R# M
| MCASP_RX_CLKFAIL; k9 I& q' a5 c. i5 Y/ }
| MCASP_RX_SYNCERROR
: c3 O3 b# W- D; e4 Z% E| MCASP_RX_OVERRUN);; m' k& i% X8 T7 X7 b1 w
} static void I2SDataTxRxActivate(void). Y' |! O9 Q( {8 C I
{- m1 ]) a& Z8 k
/* Start the clocks */
5 |6 b( l( u3 {9 T7 J& m; IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 z( H5 R& }2 f1 d. U, x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 s4 B6 Y- P4 x" q8 Q# J+ V* zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ I- l# @! `* A0 V
EDMA3_TRIG_MODE_EVENT);
% u. E8 ]1 J. PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / C$ }, {/ V& c+ ^5 @" S4 R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 i% \$ m! H) Q9 o, S6 l% L3 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! V# }9 U2 g0 P: DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& d7 i _8 b' g+ U) F* S1 R( M: d. Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* A1 Y5 h/ U/ B( NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 G0 H8 h9 Z, Y3 p+ {; N2 k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; H! R, H. W$ @! S. s( t) h m% b- l
} 9 ^# ] L0 ]0 C& v, S J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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