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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 w+ e4 e# \; f9 L [# w; k0 h
input mcasp_ahclkx,
8 x; z. s( _4 e- {5 F8 l# Ninput mcasp_aclkx,0 Y/ u( B- T: Q$ b( l
input axr0,
( I* y! s2 A# p3 }, ]- ~ q" s! n2 @% F. {8 t
output mcasp_afsr,; S. j2 I' @+ ^& @7 y2 l
output mcasp_ahclkr,
8 ]5 W/ [" k3 Y7 ?9 D# E- V, ?' uoutput mcasp_aclkr,0 `. ?3 R! _. E( a* F9 t( x
output axr1,- @. e9 P( @# M1 Z( }
assign mcasp_afsr = mcasp_afsx;
) v6 z" q6 F4 H0 @' x0 vassign mcasp_aclkr = mcasp_aclkx;$ H( B' _" a! o$ x& B
assign mcasp_ahclkr = mcasp_ahclkx;
5 D- @) Y( I3 A7 y! _assign axr1 = axr0; $ f5 b( z9 A r* Y4 c& J& q+ S
: @$ u8 O! D0 T6 s9 c0 V" [% L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; @0 D2 @/ r4 W: W9 J# p6 Zstatic void McASPI2SConfigure(void)+ y2 y3 N2 u6 V+ P7 i
{
2 A" x% r/ d! `1 Z. R" U* h7 gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ G* S4 P; `) d. WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 C# g* N: K; \, K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 N, y! f; q3 z: a$ L9 N+ oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 P! D( E$ ^* L% e2 ^. n! L6 o' ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! G! s; ^% p! O. A8 x# j
MCASP_RX_MODE_DMA);
% e% M5 p1 P) P j3 B8 |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 M. b1 \0 E9 R; ?9 O SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 G; d3 N+ [ s, _) E) ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) c" W. s0 b/ |7 _- C lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- o) z4 G( W9 O2 ^$ DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 O u% V4 ?7 S, d$ B7 O$ c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; }" e* [7 v; QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 @- a7 Y6 g) N0 _, IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! }! `6 n8 e( {# t, Q8 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ A$ P' s" X, v0x00, 0xFF); /* configure the clock for transmitter */
9 x4 r% \% K/ X( o; ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ I& c, i; `7 v0 Y( TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 d- s1 @, c7 i. I% E4 m. Q) x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 d3 i7 {& G6 A0x00, 0xFF);) U7 K. u1 L; d7 N2 M
. k8 G5 F* x j+ ]/ |3 W d+ M
/* Enable synchronization of RX and TX sections */ 5 {6 K! T9 O, p7 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( Z: ~8 P7 g0 |7 v, ], QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 r& {# [# `* t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% q$ m( a* U2 K6 f, S, p; w** Set the serializers, Currently only one serializer is set as
. a4 M5 H& w C2 y& h3 T** transmitter and one serializer as receiver.
# {" Y6 E6 T# G( ^+ S! Y6 t$ O" U* P*/
% l+ v% c k5 @; K1 N( `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- E" d5 B q: f; N$ g' D0 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: {5 N9 {% P/ V** Configure the McASP pins
# d& q* z6 L5 X8 R& r. u5 M; v** Input - Frame Sync, Clock and Serializer Rx: d s- @" G0 b* ~, T/ G
** Output - Serializer Tx is connected to the input of the codec
& @# h3 V& G- Q9 r6 X/ w*/
/ a$ {% I, b' j4 a& r* BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 F& X: L7 v2 a+ \2 C0 i$ i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. q' p% R8 `* Q: N8 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: _4 d3 j) s b) J6 S| MCASP_PIN_ACLKX+ K- m" s, c0 b ^- Z
| MCASP_PIN_AHCLKX
# y) w: N! A/ w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 E" {5 G# J3 U. \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % ^1 R4 F* m" b# B
| MCASP_TX_CLKFAIL
$ F Q4 z: Q2 v& e| MCASP_TX_SYNCERROR
; H* f( Q" f# U+ S& d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 X% v+ {; E$ [) t; g| MCASP_RX_CLKFAIL
# g4 e; ^% x0 J1 n; `+ D+ d& G7 _| MCASP_RX_SYNCERROR
) r/ O& h0 K5 A3 v5 ?! Q| MCASP_RX_OVERRUN);2 S! l, \3 ?1 s1 L: ~: D
} static void I2SDataTxRxActivate(void)
5 p5 q% o) F& y& U* z{9 Y: D' |1 `8 g1 K( Y( E* V r
/* Start the clocks */
6 C* l) @1 X# o J6 r8 U2 [7 AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 C. G7 D$ S! p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. i) f: [7 R% G2 R GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 [' B. E# w$ bEDMA3_TRIG_MODE_EVENT);; P8 e7 q8 Y& O+ D- L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * |" }- C/ i+ [( k. ~( i9 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 `/ C& Q% G; g( l$ c4 l$ f0 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. {9 j8 v* K1 U6 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: c/ s% S& @0 j. S5 Q0 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 C' e$ g+ {$ s0 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ l( G5 C. ^' lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 B9 N6 H# |# Q/ T
} # ?6 v% s' s ~2 K, D# w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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