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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: z( _0 T+ \4 D+ x1 k4 j6 v |1 Kinput mcasp_ahclkx,
: S8 t4 S1 b" T b$ V6 r# N; Xinput mcasp_aclkx,! A3 F7 J! l) F. }6 A, d
input axr0,
0 p! l, L9 ^% L7 l: z$ u& D1 C0 d
output mcasp_afsr,, F% ]8 P# t5 N. m' q" N' B
output mcasp_ahclkr,) n' D' Q |) E3 I7 }$ C
output mcasp_aclkr,
0 u/ I; B( p( Y* c k: f4 poutput axr1,
& j6 I' d( h2 b assign mcasp_afsr = mcasp_afsx;
1 ?; r- o3 a: i" C( Z8 Sassign mcasp_aclkr = mcasp_aclkx;, B% O ^0 P: i* q$ A
assign mcasp_ahclkr = mcasp_ahclkx;
, K& E- a; Y- l+ J; j Bassign axr1 = axr0;
2 `& t T! a; e/ m& C+ H3 _; n6 r. V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# f. ^% [0 ]( |! R2 d9 Tstatic void McASPI2SConfigure(void)7 A: m5 Y, H% a, \' `/ g( x
{! K( U1 W% P1 Z# C( ~* v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 {( M0 S$ N& x3 t. Y6 p$ `. cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 X; f% Y. K, M8 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) T! P$ \) _9 g( v' [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// F8 ?. O! k0 L) s$ p; E8 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 \" Y: [# {9 d
MCASP_RX_MODE_DMA);/ O9 {2 R( F# v) W" T/ z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- a1 m& f* j: w* h: D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& v# c3 e5 d& wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 e4 b& ]; M) y# y- S5 g& U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 `; S& `$ B" O& x0 Y+ y+ M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ H2 }& s- S4 Y0 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 A' ^7 | f0 U9 [7 H# KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; Z% p+ v) F2 Z$ R: CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & s c, M F% ^. w1 ~( f0 K. F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 s/ w$ Q2 o$ w O0 v7 D( g: r0x00, 0xFF); /* configure the clock for transmitter */
4 I% N P+ D) L/ y. a: o, ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# i3 Y8 k0 Y& b m; X* j2 Q; O2 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 b" q0 ~ @# r7 a* ^' d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 ~; ~& B& _5 B# J& O8 \; ^0x00, 0xFF);# j$ j* |) |; v1 F: o' v# T
$ g: f1 F- _% a! p
/* Enable synchronization of RX and TX sections */
, E. a( P9 o: yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: o8 t# U8 h- n2 S6 a1 H$ G: ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 a2 ^& P$ r, FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ c/ j7 g2 w! @0 g2 k- m: v6 g" k** Set the serializers, Currently only one serializer is set as) I0 d, {" U: L. Y: e8 v
** transmitter and one serializer as receiver.7 u8 R; O6 X* b8 }0 ]
*/
% O8 v% D- N: A- a1 iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ M& ]% \6 J! R+ x3 h+ J" k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 t' a+ j! q, H3 h9 d
** Configure the McASP pins , Q u3 g/ m2 |, k
** Input - Frame Sync, Clock and Serializer Rx& N9 P8 `! b5 B. ]
** Output - Serializer Tx is connected to the input of the codec
2 o. _4 k) U( |2 [*/0 M5 p6 T$ {# y. }) v. k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( U7 D( A$ ?* ?9 N5 I7 ]% d! KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ E& q# w1 j8 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 t9 Y c& A- G
| MCASP_PIN_ACLKX
" o. G0 X& @/ e! v; l| MCASP_PIN_AHCLKX; V3 E" w7 I1 W$ h. f; n" B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) ?) a7 q6 X7 @6 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
`5 [) r+ P7 `/ {| MCASP_TX_CLKFAIL * S. s% X/ R- ] Z/ W) ]' r) X
| MCASP_TX_SYNCERROR2 I: \2 c0 _, I9 x: l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( N9 ]) Y) y) R; r
| MCASP_RX_CLKFAIL* ]% K5 h" Z2 B5 `7 ?
| MCASP_RX_SYNCERROR
3 T& f& _* k% {7 `. e/ H| MCASP_RX_OVERRUN);4 V8 l; v' [1 D2 o
} static void I2SDataTxRxActivate(void)& @! _5 {* O4 |+ ?
{+ ?- [* I- f1 Y7 a- G
/* Start the clocks */. d) m* U3 A" o' M4 S; z7 n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ ^: j% @, V; X. ^4 W8 ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' A; l y; U) E" q1 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 D" E9 r: w/ d; }( LEDMA3_TRIG_MODE_EVENT);
8 Z( i6 I$ ]& y- p9 y6 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, q9 M. J [# B+ b9 Q lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& {" h3 G% M7 @/ B9 i0 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ Q' ~$ F% F% k; a/ r& w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" k1 p. R8 a$ e4 J( B) ?8 D$ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" G, K ]# P* N: E( c t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 D5 ~( |; N0 Y8 y/ O: xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 u0 }( T2 f, K$ K, v
}
F" L- A& t/ ]( M k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , t: s# m7 y; i: m$ p
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