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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! Q4 L2 Y0 c6 G5 Q
input mcasp_ahclkx,6 {2 c5 G8 O5 y# J* @. v
input mcasp_aclkx,
8 O/ Y( l% P# z6 E' S i: uinput axr0,
7 q1 D; K0 K9 _) b5 _
" ^& Y a) F5 R' @- b' j# M" K% Routput mcasp_afsr,7 G# t: y$ w1 W$ l5 `
output mcasp_ahclkr,8 w- m; W1 D* j) y! Q9 F: p
output mcasp_aclkr,% c- @; M7 ^% D2 s* l" a
output axr1,
0 h6 ?$ H" {# r; a* b+ Y assign mcasp_afsr = mcasp_afsx;
, S4 h5 x6 b7 N1 O: ]assign mcasp_aclkr = mcasp_aclkx;
7 j3 X. h# e0 Jassign mcasp_ahclkr = mcasp_ahclkx;
' _, \0 p* C* b1 b) Massign axr1 = axr0;
; K, i* e* z7 Z) |: h1 e. b+ ^. C% L) B5 m% r" E! H7 P( q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. y8 I. ~! F; _. `( bstatic void McASPI2SConfigure(void)2 I& v' P1 j2 K2 X& X v
{% _# t2 k5 C j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* |3 M9 Y* t, j9 u, zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! ^* W, Z' _3 R j8 L8 G# zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& u. F# D# l4 h {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 B e0 M+ S* g' Y( Z- T' jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 F' }3 H% |, B4 R' z/ c) j
MCASP_RX_MODE_DMA);2 w/ b e8 M8 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) ?; V O( n( Z; Q) b/ R7 I8 X8 DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: ?$ |6 Q) m3 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - T' z, y! \9 v1 e) F. U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ M' V1 h& }! a+ N3 ]% a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 o! p. `- u1 ~, z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 P; T2 |1 @1 FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- p* ]6 `7 N2 Y* g. ~ \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 p0 b. h# y" }( I" c4 ~7 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 j8 D' E8 o, n! K2 @) F$ \
0x00, 0xFF); /* configure the clock for transmitter */
7 d; g1 B) J5 z& N+ T, TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 J2 o$ j+ o& z) Q1 I P, XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; J: e5 u, h3 A [: B! \2 K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& `; _7 B Q+ e; U, g" P4 ^
0x00, 0xFF);9 }. O* O$ n. ~5 k5 s- N
2 S. |9 a6 P/ N8 L+ k. j/* Enable synchronization of RX and TX sections */ 9 X! h/ a( A w, J/ d) s/ X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; v: S8 G/ V! N# [ r6 [( lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 b( c P" X) q d X% o8 \9 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ H2 r; k' l* d: x. F M [; F" p** Set the serializers, Currently only one serializer is set as
1 u) ?0 H" R. K( U** transmitter and one serializer as receiver.( U4 v9 |2 u4 W: h0 c3 S1 f
*/1 F- g# Q4 {6 S; G4 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 u5 w2 I' R7 ~+ y- I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& j9 z! T% X6 H% ?/ N( v
** Configure the McASP pins 4 r" H @8 q: D6 H7 q
** Input - Frame Sync, Clock and Serializer Rx
1 J9 \5 ^. ?/ u** Output - Serializer Tx is connected to the input of the codec
$ Q8 p" H4 v& Y*/1 g# @( ^* h$ g2 w6 A. k! P: e9 W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" N9 _- m! J: q3 C) yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; N. I. M* d. }5 L3 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ g4 O8 h8 V p# S/ X
| MCASP_PIN_ACLKX$ G' H' S0 X0 i) w
| MCASP_PIN_AHCLKX! s1 B% ]8 |; ^8 u" a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 K1 p0 V9 E3 z5 g9 f( y" Y4 n7 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + H% {6 e6 f3 e: e0 S
| MCASP_TX_CLKFAIL 5 p2 a' A2 w% _; y0 b, Y
| MCASP_TX_SYNCERROR, h) R$ P) O1 Z% V9 u; N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) ^! P9 |6 F- o9 y
| MCASP_RX_CLKFAIL: w: H) ^( Y! }' a: k. b7 n1 S& F
| MCASP_RX_SYNCERROR 0 ~3 i0 v% ]8 y' {, ]# k* t
| MCASP_RX_OVERRUN);
- p' o- d6 a$ Q( G} static void I2SDataTxRxActivate(void)0 q" [% V: S2 q" n5 U- F
{
- v1 p3 b) C1 o( @3 }7 P, L/* Start the clocks */
+ T3 K! b' M6 ^" q( A1 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ [9 O% {, y$ S6 z! ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 ? N0 H+ p0 h5 A1 |. d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 T- ^1 t7 w- h0 \% @! lEDMA3_TRIG_MODE_EVENT);
X( M8 d1 f/ a" JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 j$ s, Y+ R7 H% l Q L- h, WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ H' `5 P9 A$ Y4 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; T7 ^7 @. G- ?- W2 s4 {0 k: R! QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 U9 c' T1 D7 e" n9 T9 C' lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& J1 K4 y$ J% T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" X; U3 J/ y* H) R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! y* b7 H% ~* t
}
* h* g5 G" T- _9 W0 D% K0 l1 t+ Q2 {' V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . B" o2 v0 N) `0 Z3 x
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