我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 S: K3 i9 H$ t# P
input mcasp_ahclkx,
# P) P- d: Z' kinput mcasp_aclkx,( Y% ~7 Z# m, r# s9 K3 z
input axr0,1 m' n1 {& T t6 `4 }! Z
, M/ A7 b1 x; E# Z, q
output mcasp_afsr,# W7 z# z2 D {4 d4 ?# M
output mcasp_ahclkr,% u0 p% ~- F# O, d; z
output mcasp_aclkr,8 a- p3 j E D- E& c& ^: d
output axr1,2 q J1 [, I" B$ v
assign mcasp_afsr = mcasp_afsx;, p/ e) _) V, R7 V9 |
assign mcasp_aclkr = mcasp_aclkx;
0 T7 q' \$ ^1 i2 I0 @& X: @3 A( Tassign mcasp_ahclkr = mcasp_ahclkx;
+ U6 i: k) i- W% t& dassign axr1 = axr0; 9 N* }3 L- } d V
- e, I9 E2 T; K0 @! o) E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ v! T$ u9 Y# k& N
static void McASPI2SConfigure(void)
- T* f1 f' O5 G- g1 U{
$ O4 y8 S+ W9 K8 k8 B. |. rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
J) H- I8 g3 c/ Y) L1 N4 k+ X( YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 D- k5 y0 f1 a2 x9 X4 [9 E$ [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- T* ]( @1 H) k" W, L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 ]3 z# s* b! u. l2 v1 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# u" S$ S: f( ?! {MCASP_RX_MODE_DMA);
& k, q w4 P* w: X: yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( I k$ H8 P4 @: _0 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( J$ b3 h& s! b1 G+ z: ]& S! C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & X! [, q6 V; `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ n. m8 [2 F; `4 j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ ?* D4 V# O! y& k4 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! C4 Q2 S* w! q! C M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# e, p3 x6 M8 q2 Z6 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - i4 `0 [" T0 ?; R- l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 \5 ?) c7 M! J5 m' J6 |0x00, 0xFF); /* configure the clock for transmitter */- }' d* Y. ?. P: W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' d" L0 L2 {/ V& W0 ^/ {% R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); Z K+ o5 E( u! L# z1 V \! h, Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; x$ R9 t/ i( F& ^0x00, 0xFF);
6 u* b# N' {6 a- o, o4 d7 i1 g' ~; }# m) K7 K8 b Y
/* Enable synchronization of RX and TX sections */ 5 A1 I# [5 P8 [# y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ t, ]+ s7 m0 T3 U+ l6 P% PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' j9 B5 f5 B, c) Z( J8 Z+ I4 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 j9 p/ s* @0 ?2 m. U
** Set the serializers, Currently only one serializer is set as
2 [ J4 I* e0 z2 ~** transmitter and one serializer as receiver.
' Y! i$ @5 s( t% h# M5 Z*/7 d$ D3 [' e% _4 n0 O( v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ d8 w/ n! T& lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& K# ~: J/ \7 Y& D' f0 ]4 |2 B. Q** Configure the McASP pins
; l3 X, f) h1 m- ]( U** Input - Frame Sync, Clock and Serializer Rx
. J# S3 ]' I' a9 n** Output - Serializer Tx is connected to the input of the codec
' l6 k3 a& A0 o9 M* o' a! _* t5 y*/
$ r# I* N& V7 D6 W' o% qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! } s5 D( L- k8 dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 K# b6 s/ u# U" \( z* D' P5 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
c8 t. S" l% r; f' n| MCASP_PIN_ACLKX0 v9 p+ w2 L6 U* g" p& `5 a
| MCASP_PIN_AHCLKX
u1 Q) O7 @/ u3 J6 {7 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: a5 g8 q) q: D- ]' QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! h. p3 T6 n" ? Y7 `) \. ^
| MCASP_TX_CLKFAIL 0 g( D/ U1 ^3 s q/ _
| MCASP_TX_SYNCERROR
& _1 ~) r Q4 ]9 \& `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. [, a* H- t8 A( Y| MCASP_RX_CLKFAIL, b5 ~) W9 V* [8 |- w% e7 J
| MCASP_RX_SYNCERROR
! m. Y+ s/ X% a' q! } u| MCASP_RX_OVERRUN);% F# z! P: F% A6 H5 ?2 ?
} static void I2SDataTxRxActivate(void)# g R# G3 l5 J* ]3 K' N# ^) e
{) B* j2 `3 R0 k8 W5 i/ r2 v7 [
/* Start the clocks */
' W& p2 H( u% r& C3 I2 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 f6 Z' J% }$ |, D; }0 O# y# bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 \& v9 g0 r, u% C7 G; QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 a) Q5 k4 ^# T: KEDMA3_TRIG_MODE_EVENT);
$ H2 s4 r7 L6 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 u) y) c: W( F/ t5 U/ {8 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: I2 D1 q2 ^! X0 f4 d# F: LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' y& h) G- `% S& Y; E9 LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 ]6 e9 A- O$ F, c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" P$ J) y" q; m# t. KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 j) N3 @7 T+ H, q M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 r9 s8 B- y7 K- F
}
. Y" P9 l/ G! m! ?) ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 j s/ z" y0 w9 T( @7 j E+ i, R |