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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 U$ N; G1 e; Y4 W3 n. x" D( }) j& R
input mcasp_ahclkx,# C8 c: m. L/ z. y- E8 _
input mcasp_aclkx,0 M" Q5 R+ Q$ a5 L
input axr0,+ W( E9 u# H; J% s0 P
2 a: l1 ]! i9 n: v/ y7 G' ?
output mcasp_afsr,% P# z: V, Y( q( N7 p1 i; T
output mcasp_ahclkr,
. l1 h# n3 N6 t3 I9 Y4 f+ routput mcasp_aclkr,
8 {5 x4 ^5 f1 g# K$ S$ Noutput axr1,
. x3 Z9 @9 K) E# p assign mcasp_afsr = mcasp_afsx;
! o O. G, d& K8 R5 g" oassign mcasp_aclkr = mcasp_aclkx;% ~% B4 A ?( q/ U! k& R9 Z
assign mcasp_ahclkr = mcasp_ahclkx;
c4 g$ h2 Z0 U0 o0 Q: U, Aassign axr1 = axr0; 5 \3 {/ W+ R& P" V( ]8 `7 B; O
D1 a. V! i0 X& @) ^! I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! v7 N. M2 }9 l( p4 I5 w# g
static void McASPI2SConfigure(void)3 g3 h1 z$ K" Q
{
- |* K8 e0 n9 @4 O8 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 H. \9 J+ m6 n& |) {# q: v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' |* o% w" [6 D! }% zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) p4 `) B2 V* C5 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* C6 p B( v. w8 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 K( a8 S3 G/ K: `. A2 m
MCASP_RX_MODE_DMA);
4 \6 |$ {5 x- oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 n v0 o5 L: b+ g2 ^' ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 K2 y$ ~8 x1 E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* I2 k% M! P9 }6 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. d4 l) o; {# G! b- s WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 y( V1 z( P2 f3 F. ?* k. M2 }; ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: b% r0 c g! ]2 @5 o l: x7 n5 e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 z1 p5 ^; M/ y8 W" r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 F9 l0 [5 w. N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 o* r; y$ R0 |' d& @
0x00, 0xFF); /* configure the clock for transmitter */
3 u5 p0 ^+ ~6 |, o9 H! k8 i; uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ _3 V, n! i' z; q& |: G/ ~" d* V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 N& [8 x6 v* S, l. t1 v' N$ [4 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 |# l( M( |' `$ K5 `$ @! d/ H& M$ k8 N! \
0x00, 0xFF);
) l& u( F: k V6 M) q& x5 b* P6 t2 h
/* Enable synchronization of RX and TX sections */
! b3 M) R7 V. M& `" \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" W8 C4 f9 n: U8 e! L. ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% G, P) F L( I7 i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) U! _# s. S. c* `6 R+ h** Set the serializers, Currently only one serializer is set as
, g$ i$ Z0 W, [& t1 k** transmitter and one serializer as receiver.9 W- w: p( _* r8 n) X; K9 O3 y
*// j" D; m" Z o( ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 \9 D& t) U8 |/ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 e1 Y% ]" X& l: ?7 V
** Configure the McASP pins 8 `4 w4 M* w: Y: @% ^8 _
** Input - Frame Sync, Clock and Serializer Rx
; P1 M; F: Y9 I1 [1 m1 }** Output - Serializer Tx is connected to the input of the codec ! n$ F% C- H% ^. c
*/9 `/ n) C7 W5 Q3 W/ Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& Z; m! {4 v8 b# f. P" C- N0 I9 q! HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. z6 K( ]. H7 C1 B, z' JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& T1 P! q X( t3 y( N* l
| MCASP_PIN_ACLKX O/ ] ?. ~( {! V% G h
| MCASP_PIN_AHCLKX4 G/ P0 m2 v& z9 Y( H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- _/ D) ~4 |9 q( T0 f' D" CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( h9 p* z8 H- b1 p$ k0 L- v& n
| MCASP_TX_CLKFAIL 4 e( f9 c; d: f$ j6 f7 d
| MCASP_TX_SYNCERROR
8 L0 j" [+ T8 K, k0 T- A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 v( l1 ~% G% W7 l| MCASP_RX_CLKFAIL6 j& Y6 t! d+ n
| MCASP_RX_SYNCERROR
- i2 J Z9 ]* P( q| MCASP_RX_OVERRUN);) J2 T& Q' Z; [) @
} static void I2SDataTxRxActivate(void)+ h6 y& H8 @3 o' k2 W5 t4 q
{
- Y, p0 e% w% q. R/* Start the clocks */
0 @8 }; {( T5 I5 qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# d; [8 ]( t" d# F/ g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 C8 ~, M4 ]2 h# y, R* gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# o7 T a% R9 o' O$ d
EDMA3_TRIG_MODE_EVENT);/ n9 y, \" `( T7 R _4 M0 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 u5 v6 d- O" W6 V6 B+ {; E {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' Z. o& K4 X( v# ?5 r* Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& r# \3 Z& a! z% J+ P7 t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 F, j% m4 S8 F" J2 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 z/ H7 R% p# c3 L% [7 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 Q0 s% D1 C; r. @" UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 _2 d* u3 f% {8 \}
3 g1 f. i3 [. w6 \2 E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. Z: y7 `, R) L- s5 y6 C# Y2 b: I0 I
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