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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 t- s% }# ]3 `; v5 sinput mcasp_ahclkx,8 ^4 g8 R+ X$ r9 H: w( M- b
input mcasp_aclkx,
; ]4 B' u3 E# o c; iinput axr0,# R, }" S. J C" V4 U. K% c; q. ^
, n* K6 A$ v/ \
output mcasp_afsr,* H# o) _/ t8 n5 e9 N/ f
output mcasp_ahclkr,$ @3 `4 u- r0 E v7 U. `. Z
output mcasp_aclkr,; o5 E8 i" ]; x: ]/ G
output axr1,
" x+ q+ |& }0 Y% X& l3 \3 W assign mcasp_afsr = mcasp_afsx;4 R Y7 B4 W3 E
assign mcasp_aclkr = mcasp_aclkx;0 U- ~. S: H+ o& Q, Y
assign mcasp_ahclkr = mcasp_ahclkx;+ j; }" u( @- s! p8 k0 H$ f
assign axr1 = axr0; + I' V- I: h, b( X1 p+ W
5 c% y& w0 c, `" a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; m% {2 x9 S% F; R
static void McASPI2SConfigure(void)4 j# H7 a4 O+ @6 [. U
{" |$ q3 i3 _$ H5 L0 n3 J. X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
x8 u2 |* T8 C w+ u- _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 M) y4 k w" e. B% Z9 p8 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 _& a! Q2 h( O0 I7 `+ |" z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# k* B7 J& s+ d0 q. ]; ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( @+ W" a# `6 l6 iMCASP_RX_MODE_DMA);- @0 b1 M( k# x w0 d, p9 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. o1 t& v5 L7 t- VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 A0 T( U/ ^7 q9 L0 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- Y" g* l( K b! O- q' ~2 kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. D8 |. p+ b7 P6 _% o z4 wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 ^+ M) v( I, f5 T$ R! }( y; Z" z# U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, V1 X0 D- v- {$ A0 M/ R+ _: s' dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 h8 j& @/ r( x$ p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! r/ U; A9 o$ d" P% D: m$ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 ?+ s' E2 R& x+ K
0x00, 0xFF); /* configure the clock for transmitter */9 X+ J% T4 ^& E$ L$ l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' K, N Z. I0 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 Z, L: n7 ]/ ~" L+ E+ m9 J- I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
X7 I2 D5 l, F( v1 v; }3 u0x00, 0xFF); _# ]- Q+ h" F4 }5 Q2 L0 K- d
! Q+ d7 v. [5 c+ N: U6 t+ u
/* Enable synchronization of RX and TX sections */
$ Y+ H+ @, I) T5 N6 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 k9 \- T5 o/ r6 c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 w4 \5 c% ]$ Z* G# E( ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( ^7 j" J. B4 r** Set the serializers, Currently only one serializer is set as- P5 `" L& @# l, W" \2 g
** transmitter and one serializer as receiver.* R5 [& u) }" ^- W' h k. ^
*/, `; K/ K. H. i$ y* [0 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 |4 V0 s. v" u. I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 b! Y# D" Q& [8 i7 {0 X, R** Configure the McASP pins & ]) g- g6 M* a! Y; p
** Input - Frame Sync, Clock and Serializer Rx( _5 v ]/ R! @, v4 W
** Output - Serializer Tx is connected to the input of the codec
/ n: }1 O) |8 E7 }*/
9 v- T* Y$ M4 X5 g) }0 MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- H, ]3 ~# _0 n8 Y* @: T J$ x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. B+ _8 z; b8 e) d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- B* o; d- T6 [
| MCASP_PIN_ACLKX
3 P1 P( y" g1 z" \+ v| MCASP_PIN_AHCLKX
3 O5 O# _, R, B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% L0 X1 m+ \3 c) W+ lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % k: z8 k. d% w b/ W2 C1 t1 g" R
| MCASP_TX_CLKFAIL
: P% y# Y) D) w. a0 M| MCASP_TX_SYNCERROR
9 E1 T4 _2 f) |8 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 u9 t' Y, h0 e. Q' u# J
| MCASP_RX_CLKFAIL( }% Y9 W! Z; A L
| MCASP_RX_SYNCERROR
a) ~5 i7 W4 o| MCASP_RX_OVERRUN);
1 M1 c, Q% s9 b) k, S} static void I2SDataTxRxActivate(void)) m( }: T b) z! F( @" [2 ?
{
- f; A, M* U7 L a: Z7 \! n/* Start the clocks */
( o# q) T/ _9 H0 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 U3 s+ `, }3 Y5 \, ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 J: m0 H7 T, K2 {1 P9 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 p( z1 i9 y$ P& x: f$ Q, sEDMA3_TRIG_MODE_EVENT);0 s; w+ ^# e, u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! J9 {. J* o2 k0 }/ b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 P, \4 b) u: ? }# v+ l8 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. ]* p! b8 {6 L$ @ X0 x0 l/ W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) n! ] ?8 o' S8 M0 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 \4 i. Z) Q2 g% gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 O4 ^* e3 e- p& ]8 r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 k& N' @5 x" o7 E8 g}
- h9 y9 ^2 w, g+ q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * g1 Z0 O$ o% H% c7 m
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