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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! Y- O4 V$ g T& Z ~0 ?9 }input mcasp_ahclkx,
* O3 L8 {3 C- C$ C- ginput mcasp_aclkx,
x# R6 y \# P L K5 b( qinput axr0,4 q, i( d6 W8 X+ I/ v" i4 F
. [: l; M) {7 _$ g0 H* K: i
output mcasp_afsr,, V Z5 X( |5 [; P8 f9 }
output mcasp_ahclkr,
" ]- d; w, E$ Z- a% ioutput mcasp_aclkr,
+ n$ I- L5 f! \0 Z, J) }output axr1,
- [5 T/ s) n |0 C assign mcasp_afsr = mcasp_afsx;
1 F+ U8 `* x& |3 r Passign mcasp_aclkr = mcasp_aclkx;5 f* d2 {( a6 I: i+ t* y
assign mcasp_ahclkr = mcasp_ahclkx;
0 A, @$ F6 L% P9 R+ dassign axr1 = axr0; & Q" j; J9 _6 S. f% t- c; M- V& o
2 r8 G8 p/ N% k1 m- a* S7 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 U: y$ V' [; s& c* Ostatic void McASPI2SConfigure(void)
$ p% K. [. d9 M- E( `{. i& z2 s+ O" l+ }& ^6 w! {% O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 X3 I) a) B/ x/ I5 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 g+ b+ n. z. E4 n9 Q0 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 h+ G: @/ z2 |6 ~% Z( Y0 O( u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. X. h* f$ |- w. gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 z/ e) E W. d: L0 ]2 w
MCASP_RX_MODE_DMA);
( k G- w1 ^7 G; z2 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 p3 D+ | Q7 V$ \8 f: \7 N' pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 h! j C3 q7 r- Q. @9 t" tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) r3 M1 [: _9 S8 N, \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ @, t3 }3 v& ]* v, X% ^. q0 L. `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , q W4 [& `, Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 @% E9 W# m- b9 m i3 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 {- ]! N b7 y) H* O% IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & S) n1 t0 { F# B2 X3 z9 e$ R6 Z5 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ ]6 X; f: L0 m
0x00, 0xFF); /* configure the clock for transmitter */
6 [5 c. `# @9 d: }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# l# ^+ y& G q: i; M" p% j( N- l f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% Q# x% S+ J" F; PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( k5 L7 m4 W3 C# u
0x00, 0xFF);
[0 q6 R7 W/ K( \0 v- K% M/ O/ y$ F0 ]- G; R" a X! T5 q( x; K
/* Enable synchronization of RX and TX sections */
$ U' V! M6 j; m5 Z+ r$ hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 Y7 _/ R! F6 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); z& u( ^" l5 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 |$ z& ?: y# ]0 ^
** Set the serializers, Currently only one serializer is set as
$ v) m; B& Z( N** transmitter and one serializer as receiver.2 D! a5 Z( {' X' ]: u
*/
* Q7 W( x" o, k/ R, EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! k1 v w3 Y$ F& nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ r3 \/ U) b; k$ n; o** Configure the McASP pins 3 d, \) m2 B' S0 x# ?( E" N
** Input - Frame Sync, Clock and Serializer Rx. s7 Q# v/ G; Y# v% N( R" `
** Output - Serializer Tx is connected to the input of the codec
2 S3 m" @8 o& `3 b3 n' m$ r x7 y3 o* h*/( A# c: S: Q5 ~# d7 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 B; \0 H1 V5 N2 r+ ]! B9 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* v1 F2 n& k( ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: M! J9 C: G# J( W9 q" A$ w2 ?
| MCASP_PIN_ACLKX
" Y$ @' @ x' \+ R9 d, j$ v' n| MCASP_PIN_AHCLKX$ |, p. v1 {+ D: K$ x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
G( P, @( t7 m* @# E( u/ wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 z$ P8 `0 Q3 f) @8 F* {$ j1 p
| MCASP_TX_CLKFAIL ( J5 D H3 e/ C6 k0 L
| MCASP_TX_SYNCERROR
; H, C4 R: F( n& x: P4 ~( Y8 ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % S% j9 W* B, \
| MCASP_RX_CLKFAIL
- a I' `7 `+ D3 e, P, t| MCASP_RX_SYNCERROR " n: O6 m3 L# o% i
| MCASP_RX_OVERRUN);9 R0 Y- B M8 N, i$ \. M5 R
} static void I2SDataTxRxActivate(void)
! l0 Q% c k! L7 Y+ A{) a( y7 L9 d, D3 I$ O i/ D R, Q
/* Start the clocks */3 Q% y7 ^3 |& ~. u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 [- f/ i' F2 |1 T# y# b* o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: K* D0 f$ y' j# H% M2 U6 b7 X1 h/ m' HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 q- ^1 ^8 ^/ x6 REDMA3_TRIG_MODE_EVENT);2 W9 Z4 b, B& Q1 V2 u3 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% K8 ]* {5 ^/ q" vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 i% l0 s8 P' a* y: P8 D3 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. T# W& `) x1 K9 K' p! D6 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 B+ o% ^1 @% P6 j5 N6 i# @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 h. }2 O: {+ i% x. q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. P4 @4 q" ?# V( E. @
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: h% o8 a- [: L9 s} 0 n1 Z" \% f$ `% q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 H" L, D4 A$ ]+ X
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