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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' _( y0 M+ \& `( T0 c
input mcasp_ahclkx,
6 u' l+ `. ^* t+ K( D/ g. z5 w1 hinput mcasp_aclkx,
; k) Q8 v# I1 G+ w9 q( _& e ?( finput axr0,
) y' k' f! ?3 c' p$ ?) N8 A! {: Z1 o* T7 \1 p" }4 A
output mcasp_afsr,
7 o' @1 r p- Q0 H1 e7 w8 Xoutput mcasp_ahclkr,; b$ P& T2 R1 l0 |$ ?# _
output mcasp_aclkr,7 i- q+ R6 S* }7 w V- X
output axr1,' l; U7 Y5 ]. n! a6 D' H
assign mcasp_afsr = mcasp_afsx;
% @- C0 o! l: P2 I: J7 ]+ xassign mcasp_aclkr = mcasp_aclkx;: I/ w: C3 _+ U. u5 Y% V# w
assign mcasp_ahclkr = mcasp_ahclkx;# k: u, O3 e1 b O! a3 W) z3 E
assign axr1 = axr0; 6 I( ]7 M" s+ n& u, T
" ?5 K7 q- s6 I4 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 A" ]/ t+ e0 Ystatic void McASPI2SConfigure(void) h" Q6 z: N2 J4 f4 S/ p. Y
{2 e( p. t! {8 `, d. z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 x/ l5 e" R1 p4 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 U0 r$ s" k5 x5 ?5 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); g/ ^4 e2 \0 m( ~- K, w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 P4 U [; ]" I& E( g7 R- D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 z7 \0 k0 ^ X, X& W" n/ U8 oMCASP_RX_MODE_DMA);$ v2 G& |( R& x- P7 _ w# ]! L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 B$ ^8 p2 ?9 q P; wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( g4 }; y F. f8 |) V( ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 \$ [. X* \5 [+ |% G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* v% `! |7 `1 H! B; yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ k+ @2 |8 M, a! \8 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' o) P2 z J' F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ D* e+ n) m. j. B6 [6 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) A, R) I7 }, L% v/ y8 v7 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ M `2 o3 V& y Y
0x00, 0xFF); /* configure the clock for transmitter */) V: M! Q! J. }9 X) a& W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# D6 W9 j' E h! T/ L& wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 U* }! l$ F: _. i& d. AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* r' Q9 g6 D2 y; a
0x00, 0xFF);! j8 X* {% W8 i* Q+ ?8 A
, H% u3 i( [# k; O5 ]5 `/* Enable synchronization of RX and TX sections */
: U9 l: A" J# \' T; ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; q# |. |7 ]5 V3 ?& N; x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& s: g4 A. ]2 o' F, n( Y; ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; K; u8 ]1 r+ _$ ]2 f** Set the serializers, Currently only one serializer is set as
1 m8 G* c k7 d6 s" s ^: S) M** transmitter and one serializer as receiver.
$ N5 O, a* {* Q) p. c: W*/
* Y. h: P3 s1 w2 {' gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Z( K1 \, C# Z: Q0 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 {, g) m$ p3 M
** Configure the McASP pins - S2 X% G( O4 p6 F& f6 x
** Input - Frame Sync, Clock and Serializer Rx% u R- ]; |+ C; u2 v
** Output - Serializer Tx is connected to the input of the codec ) ^9 R3 M) |% I) X+ }8 t5 ?
*/( P6 r5 R, W, c5 m1 P' m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ^* [- w6 W2 [( W* i. t8 [) e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 a0 q ?8 N# Y& ~/ @) h3 NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; x4 ]: Q* t, p; }+ n| MCASP_PIN_ACLKX
0 b# L8 u* a7 [9 \4 p| MCASP_PIN_AHCLKX
}- v0 e" l1 W2 x: y& o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 I% w# m7 ~' @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 v3 P6 u0 |# B, M2 l* {* \( M$ H: Q
| MCASP_TX_CLKFAIL 0 `' V8 G7 S! Z( e& V( X
| MCASP_TX_SYNCERROR( U. y2 P$ r+ z5 p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 ~5 X8 G. O5 @* Q& B- W| MCASP_RX_CLKFAIL& f" K4 g0 s- G# U6 N
| MCASP_RX_SYNCERROR
$ n6 e7 P- C4 y+ k4 \6 k| MCASP_RX_OVERRUN);. h& J4 d/ R3 R
} static void I2SDataTxRxActivate(void)
x( }! x! E- Z$ E* M{( l; b' W" I E! C$ R% @
/* Start the clocks */
8 `. |# j% O& L- R/ N( Y4 PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* \% p# I0 t+ W6 K) k3 F5 d$ Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 W1 M1 X8 K& s9 t# I( h5 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! }. {* { E) S- v( qEDMA3_TRIG_MODE_EVENT);
, n* y) m+ M. C {+ S8 {4 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 q7 Y# ?4 I; o* U( f: B" c* s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) N: d% ]7 b* m& q2 ?, Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 ~9 A4 x5 u9 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 p" S! O, K. X, h k$ }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% [1 ~5 v4 q9 K$ U d& ~* [: F5 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& z! ^0 J' j0 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 U! @ x. _: C; e} 8 W" K% p7 {5 V- y7 z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 `5 u. F3 v$ I4 H
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