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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& ?, d5 y+ z5 g2 F" C" p; pinput mcasp_ahclkx,! _' k: C0 K/ M6 O
input mcasp_aclkx,' ^6 T! z& ]8 B$ E6 f/ D
input axr0,
& i* a, r: [( z# T; r& i/ }
C8 u! V$ f, Y' E' B; o' E# p$ J' \: Joutput mcasp_afsr,. l: j; A j: R8 n) f0 Y) |
output mcasp_ahclkr,
( X3 w; q7 `+ V% r/ U3 Koutput mcasp_aclkr,3 {" a6 f" j/ K v6 K: P) v- M* s; W j
output axr1,
0 n5 ]; o+ [3 e' Y$ ` assign mcasp_afsr = mcasp_afsx;. Z9 ^, a' _8 \+ j$ D
assign mcasp_aclkr = mcasp_aclkx;
; R1 G- l$ I; Yassign mcasp_ahclkr = mcasp_ahclkx;% u) a& u. y o3 ?
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 S: Y7 e6 F' l, `, q s
static void McASPI2SConfigure(void)
; h. w' U- [1 u" Y# {8 K+ i, I; i{
0 r9 u Q1 C, GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 e; j& ]8 |5 X1 k* Z* @& m8 z, q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 g+ v6 j6 b+ ~- `6 k% z% o+ N, Y5 e, R, g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); F) y* r F3 s. D& h$ V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( t, |6 ~, p) m+ y- GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 r0 E" T5 Z; _/ \! k2 i: q$ r+ |7 W) [MCASP_RX_MODE_DMA);
1 g, P5 [$ W6 l6 ]# ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ]9 i% `7 ?8 R6 m! B) GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 c% q" w9 D, K4 aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " P. w5 X0 R- m, ?: G0 c2 N+ T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- x3 S0 X# j" E6 g( P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 O) A" x' j( T. BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 O" d$ B9 b& K( E) d" AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
B" _! y: T. A+ ], nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; e+ H$ X3 w2 p1 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 v6 W q% F( Z% P6 l8 h
0x00, 0xFF); /* configure the clock for transmitter */
8 }/ Q( L+ N: j: T+ W7 F7 H% v: P/ HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 @( x& o! i, j G4 U2 I) KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 t; x! s! ?6 \* }8 @; x6 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 h$ ]( g" f! l$ ]
0x00, 0xFF);+ q' W9 P* R7 N
( `2 Z% F* M: j1 G5 I/* Enable synchronization of RX and TX sections */ 0 I( Z* G w" C: f% X3 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 G) |; N9 _# ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) p, n! q: _# l+ v" P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
f# d9 c, P- f2 [** Set the serializers, Currently only one serializer is set as
# e$ d0 t! ~4 Y7 s** transmitter and one serializer as receiver.
% Y( ~7 K+ a2 j*/
( W% C6 \% K; s) ^. v& ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ Y9 L$ H# s1 u& `; ~" Y# u2 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 j) ?0 K4 b# j6 a9 A
** Configure the McASP pins : F4 Q, y- a2 G/ }
** Input - Frame Sync, Clock and Serializer Rx8 j) @' ]7 D0 B% F! W8 `" m7 X @# j
** Output - Serializer Tx is connected to the input of the codec
1 b: H4 \& z: k*/
- G4 ?/ B% s. QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% g" V- t2 u" G5 U/ R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 ?. M1 E6 l% V9 r8 g# G: r* G% @# _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 ?7 _* r8 y' z8 [
| MCASP_PIN_ACLKX
7 F4 f5 ]" }# _( n| MCASP_PIN_AHCLKX& K' E1 E0 i( p/ J0 y- u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' p# L* \ `& }5 B4 b" i+ `" u/ qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 ~% D! z/ ]3 q5 P3 s1 S| MCASP_TX_CLKFAIL % ]6 c' t% I9 B5 H* I
| MCASP_TX_SYNCERROR2 [1 c! f2 z- N. ~+ y F- w& I- w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & O h# ]1 I6 B* z; l; |
| MCASP_RX_CLKFAIL! I8 Y4 G9 G9 ^& s: L
| MCASP_RX_SYNCERROR
" g G5 {4 ~* W/ d* D' p o| MCASP_RX_OVERRUN);" T5 K) H5 a4 e3 n! W, D0 h7 @7 T
} static void I2SDataTxRxActivate(void)$ |2 k! L8 q" e2 i. @: D5 q( {
{
3 Y4 B1 G/ a5 O6 P9 I/* Start the clocks */
1 i0 n: V! h( a: uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ B0 c; f7 M3 G% y- B2 [: IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 L J! |8 A" u8 S6 x& b( [; aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, @+ h. \+ C8 D
EDMA3_TRIG_MODE_EVENT);
$ o; \" W0 Y$ X& h U YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; W6 g3 c% t( S, c% K0 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 l4 |1 A, c" I" XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! f+ c9 F% }" P7 @* \) [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 o! K6 r7 y$ d& owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: p' g, q- b, ?& I1 f4 v$ B M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- X& s G& L7 Y- { w5 m8 a7 G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% U7 Q+ `- E6 Q} 4 _; ?8 A+ w) @6 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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