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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 y! Q3 O/ L% D# ]. cinput mcasp_ahclkx,8 j( l' \# I/ K5 h/ O l* o" [1 y
input mcasp_aclkx,* v" [9 R0 H/ e" l! e! _
input axr0,
3 ~5 E7 }3 i& G9 y6 {- X+ u8 V$ a7 {+ b
output mcasp_afsr,9 w, L5 O- ~1 m2 ?. J8 D
output mcasp_ahclkr,
( N' a7 u8 ?# J6 \output mcasp_aclkr, u9 X& W B8 p9 m$ o4 x+ M; ~& E
output axr1,
' Q+ T3 C' G% e1 K1 x- b assign mcasp_afsr = mcasp_afsx;
3 B: E/ u6 Q8 U& |; i- V8 Dassign mcasp_aclkr = mcasp_aclkx;2 ]( z7 ^ Z1 \- K
assign mcasp_ahclkr = mcasp_ahclkx;( x4 ^5 t! q" y& y6 s6 a9 |0 E; r+ ?
assign axr1 = axr0; & s, |5 u# k: P1 ]" j4 c! y3 i3 Y
! w* F6 t, w6 q/ W6 N# [( j; `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 x* e# h( o: L: [$ L* C4 v
static void McASPI2SConfigure(void)4 a$ l& x: y; P; _) w
{% G) I; ^- S% M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 F+ n f2 T5 D3 k; a) |% }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) [2 i! [" P' A! O7 {: NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: G& a) ]% C5 w6 o& H% JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' Z4 l3 x3 a" U+ l" d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' }- B; F& P$ n/ @5 G$ KMCASP_RX_MODE_DMA);
+ ?7 Y( ^2 D* @+ M$ f: _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 N' L$ O' ~6 e/ Q* l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. I! S& A- U$ X0 Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # \& v2 A- U, Q9 S, ?/ p& r" C; ^7 O' ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% n' n/ d3 |. z. L9 x" UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( L0 Y* k, G* ?8 A& l: j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 l% a8 o6 T& q4 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
@2 x7 h! ^7 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , @7 @) p( T; T3 _2 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ V2 J( Q. \9 o" U6 N" {+ L% N
0x00, 0xFF); /* configure the clock for transmitter */
5 B& S4 \( T! K: U- n* zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 {* F1 D6 X9 |2 o$ tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& U. t2 g9 s' g* {9 }8 ^& i( gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' D2 }4 [+ s% a- y: ~: X7 ^
0x00, 0xFF);
- t% `; B# w6 [3 X. G; J* o3 j9 Q7 h5 Z) i
/* Enable synchronization of RX and TX sections */ ' m, M \4 s# [! m; T! \" x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, Y4 o+ x5 N. H$ a9 { l" a/ j. D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 X8 V* K- L2 x; F7 K+ q) PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 x3 v+ e; `, Q+ P+ G
** Set the serializers, Currently only one serializer is set as0 ?. k: ^! ~* j1 N! `
** transmitter and one serializer as receiver.
0 {1 x% U( D% T5 g*/
+ D( @! y C- J$ J0 T$ l; [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 A# f9 \ a& e: [7 J+ x/ r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 K5 @- g6 W' Z e2 q2 J: `2 _, k** Configure the McASP pins
) P E7 s0 g u7 o** Input - Frame Sync, Clock and Serializer Rx8 I1 O/ Y( T" G2 Z( c4 c; o
** Output - Serializer Tx is connected to the input of the codec 7 b3 E& W4 X ?$ H0 V) ?- N
*/! v( u+ ]/ b1 E& R9 S, Q7 I/ z) A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( {. {) s3 C& n, XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- J4 o& {3 E" _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ s- g2 x* Y3 J$ U% H \( e5 I| MCASP_PIN_ACLKX% r* d0 P& S! M$ @8 M2 }7 j) e/ ~
| MCASP_PIN_AHCLKX* D8 D9 S# n; d5 q. A( h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 _; G( ?, c8 }1 m8 K+ w, X! q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) K9 m! @! Y2 s$ Y
| MCASP_TX_CLKFAIL 0 b9 {) U8 l/ r; Q7 {
| MCASP_TX_SYNCERROR, s, c# i' g& M$ w5 P; h/ I% m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : e* u1 ~) g: r* j a
| MCASP_RX_CLKFAIL \ s p8 |) q/ g4 j
| MCASP_RX_SYNCERROR
/ y; [+ w; y$ g| MCASP_RX_OVERRUN);, i3 I4 s$ j# A) }6 T4 Q; l6 F7 C
} static void I2SDataTxRxActivate(void)3 F/ o- s% h9 G
{
8 x" i+ U/ D# a; j3 _" y2 T- z/* Start the clocks */. o1 M: E g1 s$ N2 [9 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 B3 Y, p9 t/ ` I9 G0 ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" h9 v1 d' `9 `9 E& {; |. lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 u" u* G% s# G2 m; p/ Z
EDMA3_TRIG_MODE_EVENT);7 f! O$ n( o7 J; h1 l/ v$ ~ P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : o3 t' U! Y# G) {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! @; U7 W Q$ x* ?# @4 gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# ~9 n; M5 m7 i9 O5 S* k" C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ O: {9 ^: _+ c# H) \2 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 ?+ I4 V6 N% ?, }/ m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" J% q% t) ~% l3 a1 d4 A2 mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ P7 x( s9 W, d T- O2 p
} ; x8 \2 q# N! ]0 X% v0 m/ z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + l+ k8 d5 g0 D; [1 U0 M" M
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