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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 a5 N8 C; b# z' m1 g T) n" Minput mcasp_ahclkx,
+ p: k( v+ B$ f# q* [input mcasp_aclkx,( _- Z$ f- T/ r' b) N t7 H6 W
input axr0,+ U, b8 m5 f8 K, ^
* Q7 ~+ U% t6 `) W/ t/ a
output mcasp_afsr,
7 o' F: Q3 M! ^3 B7 o, I/ moutput mcasp_ahclkr,
* ?2 K7 Z3 O V/ {9 @output mcasp_aclkr,: y- {7 B# ~5 `2 _) y) f, n% p; q
output axr1,4 `2 T8 P7 Z; R1 K7 q
assign mcasp_afsr = mcasp_afsx;
% f7 t' K# C qassign mcasp_aclkr = mcasp_aclkx;
9 m, w- {% d6 O1 y/ fassign mcasp_ahclkr = mcasp_ahclkx;
4 U7 c. F9 _' bassign axr1 = axr0;
2 z: X k( O% _1 n- ^3 _ E+ k+ \1 m! {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- h' ?3 z8 j# O! L: B Z- ostatic void McASPI2SConfigure(void)' F. G3 Q7 R- c0 }5 z
{
; M6 w( }3 j& b& [3 [. [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. K7 p( D3 }8 a c M5 ^% kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 N- x. a8 M$ [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 M7 b5 F i" WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; |! x- |/ G0 z" K1 |% CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 [% X- F% ~. }1 d. AMCASP_RX_MODE_DMA);# p* Z7 g8 S0 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 {3 [. J: I0 `$ b b1 W1 P" M+ _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 }- k3 T; c- h& z- g+ C' ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, d' E/ K1 N. J, J1 m, V4 m. d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. h- y( O# n# L' g/ g2 d1 B1 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " D4 o; W8 _# V! U6 i- t+ U" u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
p r9 u* l! @& e: g2 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( i8 ~& c' f) e" c. {/ {9 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 C0 k2 W3 z! cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ T9 F0 c3 o0 g0x00, 0xFF); /* configure the clock for transmitter */
, S/ A+ ~+ o% g* A3 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. J( w2 d, I# CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 P4 ^4 B7 |2 R! } c6 G8 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( x: O" _" L9 z S5 |' L- D) _0x00, 0xFF);
8 e, d; ^. [3 b3 \2 b5 Y, y
& \5 x, M d: [5 ]9 e" G/* Enable synchronization of RX and TX sections */ 3 o: b) c, d) D O. j- Z6 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) ~/ [+ s2 G* L. cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& ]) M) f9 C5 P3 [9 @% {) nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; g8 b( Z9 `4 J/ E9 V
** Set the serializers, Currently only one serializer is set as6 [' G) T* Z4 r7 h+ U( o
** transmitter and one serializer as receiver.- G4 `6 D- C2 a
*/) F0 _" s! p# V' f% a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 k, O5 A: Q7 | _$ G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% k" Q% W" X' p: Z** Configure the McASP pins / f+ ] J# }4 B; {" X6 k/ d" m% Y
** Input - Frame Sync, Clock and Serializer Rx$ ?; h* T# z2 M& u- I ]5 a
** Output - Serializer Tx is connected to the input of the codec
( I4 q6 G% ?( q# O*/! R! f4 w* k, w# p" B4 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 h- E* @* j' u# f8 E* _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 c# Q( R F# I4 F: x) A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ @3 @- |- d. D L k+ X
| MCASP_PIN_ACLKX- p2 B' Y, G& A$ c( j9 Y5 s
| MCASP_PIN_AHCLKX
`+ [+ z p0 K C; \' A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( y4 _+ s3 j- K$ \) x! L& GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 j% u; M2 {0 j( L Q* w| MCASP_TX_CLKFAIL % C: W* K1 L* C: o( p" k3 g5 y* P
| MCASP_TX_SYNCERROR) g* }( S, I) D& R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 R: ~5 U5 ^7 j# ^2 P' h; y
| MCASP_RX_CLKFAIL
) g; p$ v5 z1 q2 \2 i z% s| MCASP_RX_SYNCERROR . O+ r5 s! T; C. d2 Q' f
| MCASP_RX_OVERRUN);+ H# S1 Y0 A7 W
} static void I2SDataTxRxActivate(void)' I8 p! d" K& C" e& v
{$ h* T3 m' J7 \' C
/* Start the clocks */
: _! M7 ?) }' P$ @$ h- o5 A! LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 y7 a/ {7 g9 P/ RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& S( S9 `5 C6 ?2 e3 T& G# UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, i8 ^8 Y, t. e7 h S2 P( c% ~) KEDMA3_TRIG_MODE_EVENT);9 c$ I r9 f% t4 `. d8 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # Q+ u7 ^# L- _, U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- J8 v# R& M6 J- M: \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! p5 I ]3 K# J; [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# `: E: K) _0 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. e1 B2 S5 s' Y. b! iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 s; s6 u; L9 ^ u1 L' RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# |6 X) a5 w) g* D/ q5 v
} * p0 |$ e/ O8 N( ]7 |' C h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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