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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% |7 _( l; ]4 D8 d( I8 |7 w6 minput mcasp_ahclkx,
7 k _/ O' M! A6 ^& ?input mcasp_aclkx,! F+ j3 K! z" |1 Z4 w9 N
input axr0,
u. ?/ J4 r' |8 v; }6 i; Y- w% R7 k! @' z! R+ s- J0 |, b0 E8 z8 P
output mcasp_afsr,8 z" I% ]) ^* p( z
output mcasp_ahclkr,! ~2 Y" d$ l* E: s# B+ m" k
output mcasp_aclkr,% h4 D: ]- X/ r6 {- z
output axr1,; `" {! i5 J8 D3 g$ b1 l
assign mcasp_afsr = mcasp_afsx;
2 b) ]9 N7 a) P: Uassign mcasp_aclkr = mcasp_aclkx;
- e) r- ?% `1 o4 G1 f) T$ ~assign mcasp_ahclkr = mcasp_ahclkx;
k, m* B3 E2 _+ D& C, x, o# s: j3 vassign axr1 = axr0;
# Y5 h+ n# o ~3 Y
2 _, N/ z* d/ \& W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % U- {- @. f/ o' D8 i# w( \
static void McASPI2SConfigure(void); z3 X! t, K: k/ t/ z% `
{$ M( F8 w3 [7 c# p' b2 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" w+ k, ^9 v# _( l3 \5 p9 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ v" V7 d# u+ A: hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 O6 H6 p' }+ y+ G9 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 f$ a7 z6 b% Z( A8 d0 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," T: Q8 P/ w# e6 `0 X
MCASP_RX_MODE_DMA);
d8 v/ E1 e- s2 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ^! L$ r/ N$ [2 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 f+ m* g' ^& O9 h6 P( C2 C+ t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 F% |* S) y, [( WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 |8 C0 a) g! {/ v5 H: ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # S# w( H6 L+ Y/ {4 B9 j, x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 O& v1 n" }! Q3 iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 c/ T/ J. B: g0 S; [1 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: m1 V* Y# D" R- F8 j2 _& {+ JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 C. ^ c7 _7 L8 i7 r5 ~6 k0 s
0x00, 0xFF); /* configure the clock for transmitter */
. { N1 ^7 p. l+ X( m5 ^) r8 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); [; Y6 w% H5 I; {6 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 _% E* n5 z1 k% ~, a9 `4 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* n) ^+ f5 C, S4 Z0x00, 0xFF);: c3 s' [7 l& m: [
5 B5 @# k3 j; x6 e) f/ U1 Q% A/* Enable synchronization of RX and TX sections */
4 Z7 G& I8 _8 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) G7 C" s/ @8 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 F2 c- A+ z' `1 U# D5 `- [# S$ |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' L5 i% p h- T# p6 f+ \$ z2 P
** Set the serializers, Currently only one serializer is set as( ]/ z+ A" \# X4 C. C# N0 t6 w! L: r
** transmitter and one serializer as receiver.
7 w" u! F n1 x3 C% x*/) M; M( J& Q8 Q+ H+ V4 ^8 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 E: `8 M& \9 F. i; OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' }- e( \- h _5 H# C8 E4 Q7 D5 C# u** Configure the McASP pins
4 k' b+ p& w& J. N- Y4 A** Input - Frame Sync, Clock and Serializer Rx( l r5 U7 z% u3 C4 d7 S
** Output - Serializer Tx is connected to the input of the codec - W1 k8 O( m6 v/ q/ H
*/
9 i7 W% |" \5 K6 d8 G" uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& O0 [- G1 s3 Y3 [0 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& e; z6 F2 z" Q5 k c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 z& x; }0 H8 r) \' v H' b- m| MCASP_PIN_ACLKX
* V4 y: X; O, T m0 v| MCASP_PIN_AHCLKX
) n1 R, K# U9 \0 m4 _8 s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* ]/ x6 z. R" _$ {/ g9 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 e8 T' }3 k, ?8 l3 x& f
| MCASP_TX_CLKFAIL
7 m2 t+ }$ S0 s+ M0 y| MCASP_TX_SYNCERROR
L# A- \" P/ z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ z( f" D7 |' H8 u j$ [7 n| MCASP_RX_CLKFAIL& o1 x! M1 r( e8 n, i& f5 B* y
| MCASP_RX_SYNCERROR , @) W2 }) F) X4 |# b
| MCASP_RX_OVERRUN);+ B; i2 I; p/ s- {
} static void I2SDataTxRxActivate(void)
, P/ j3 {( T. g+ g, R$ W4 x" r{" `/ h2 }! Q4 I+ `* r, }6 i( P
/* Start the clocks */
! M/ d5 s8 H( G3 H( Y8 n2 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, U/ ?6 @$ t- C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% o b2 R* C; O; @4 Z7 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 x- q6 o" s1 u0 h1 {6 s; F- {5 k1 |EDMA3_TRIG_MODE_EVENT);6 \% i% A8 p) |3 n/ K2 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 A4 Y; A i% w3 r, v1 |; y9 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# G' G0 Q0 h2 [8 F5 y3 I( `' `) X8 P, t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' a# h2 F* \9 A9 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 c( V& {) S6 i% T, pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 m( T) @; n3 \- v, K1 T$ JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 Y" Y4 U: ?& W, A- F+ ?4 P! WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 K; k$ y% |0 F) h* `- s} 5 r. e$ ~4 `0 ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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