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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ T0 P- Z3 h) w, T+ E- ~0 ]
input mcasp_ahclkx,
2 v) G1 U/ e, r; winput mcasp_aclkx,& o$ E' p' ~9 e# ~$ ]9 E+ g( s( B
input axr0,: X, {7 [) J. E
, h Z0 j& v9 y8 O7 `, Woutput mcasp_afsr,
9 a) L, o$ F8 m$ X9 J3 L$ k& e2 q4 i% ~- Noutput mcasp_ahclkr,6 d- @" ?9 b" {+ b" n
output mcasp_aclkr,5 [# Y; q) A: m) V) w: a
output axr1,* m6 n, F% N" K& V9 V1 _; Y
assign mcasp_afsr = mcasp_afsx;
& J/ x7 A- e. `& ]) o2 @assign mcasp_aclkr = mcasp_aclkx;+ P( a* {9 v( n( F' S* Y
assign mcasp_ahclkr = mcasp_ahclkx;
. d- e( R! [0 \assign axr1 = axr0; 8 o) @8 N' [0 D0 u
* C* V. j) I/ U5 A0 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 y5 P5 c8 a* O& I7 astatic void McASPI2SConfigure(void)
7 f4 C& g4 t' X! }& |, Z; N{
7 F; g; `5 Z& t: nMcASPRxReset(SOC_MCASP_0_CTRL_REGS); L1 y; C% H- z) m$ k8 R- q' s! b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- ]" c' w, _2 r3 T8 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- Q8 z* w- ]1 m/ u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 J. U' {- Q' ^6 d8 S2 }" o4 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 s0 E2 [! p. D( M
MCASP_RX_MODE_DMA);
# Y# ?* J3 h% y& u0 ^3 S& _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; q8 {* V4 i: H- d6 z+ t* ^. ~- m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 f& o8 E, c' p+ G/ b2 | Z( sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- c) @* i! `$ H2 t/ lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: \" j5 |9 o. k8 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & v# @7 T% f9 ]/ b' N) @$ |& N! d; p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, h- c% u7 |$ b9 a5 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 B1 V: G0 l8 O# X$ CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 D2 b' t9 t4 S* zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: D& r( m0 K- Y a# L7 }) g
0x00, 0xFF); /* configure the clock for transmitter */
) _& h- ^$ \, V7 F/ z/ y* q7 X, kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% V1 a0 G- n, C6 K/ @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 F6 T3 Q7 j0 z6 m9 o1 {! M9 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 y8 M9 R, h- ?+ r; F0 J0x00, 0xFF);
/ E! a. U! \) A8 A! |, k" Q8 y* x4 p; u9 d+ p
/* Enable synchronization of RX and TX sections */
1 K; b% c- @) K1 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 r: ?. e6 b1 S1 |1 S/ r7 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! c Y5 y% S* _! ]! V/ X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 @+ e5 e% g: k7 R* l9 n
** Set the serializers, Currently only one serializer is set as
# I4 x# @; N& Z3 }& E4 `# _** transmitter and one serializer as receiver.
+ N4 V- G, G0 E*/# A2 p4 B/ }. N: t$ S( k3 R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, s$ }, z% V! Z* @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 P- C1 c. U3 W! @; d, M** Configure the McASP pins * R" d6 }1 `. J8 V/ A J x
** Input - Frame Sync, Clock and Serializer Rx
7 S: e7 C$ H$ Y' q** Output - Serializer Tx is connected to the input of the codec
2 z, S& `2 {8 I( ]9 R4 F5 V*/
! l7 k' W- g% Z- O2 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 ~6 F, v, |8 L8 K! F+ R. i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- N; b! R6 Q$ w" k4 m( e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& w1 f# o) c" M8 z1 M6 d! A| MCASP_PIN_ACLKX
# h$ O" U. U5 D4 w! u9 W| MCASP_PIN_AHCLKX
& ^. F# T, Y( f( Y, L( ~- v: q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' w; {/ r$ ~- M- _# ~ a$ a" t1 m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
?9 b0 D7 m. j. m+ L1 ?' U| MCASP_TX_CLKFAIL $ G b. B% B) K2 J: I, T
| MCASP_TX_SYNCERROR
$ [( B# |1 D% i9 \7 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % L$ s/ @8 Q; U/ K
| MCASP_RX_CLKFAIL
8 y" h2 m1 {% M4 C| MCASP_RX_SYNCERROR
, w* V1 s" C& Q6 s) u| MCASP_RX_OVERRUN);% Y. H+ H, W2 I" c9 }
} static void I2SDataTxRxActivate(void)2 Y% C4 q- D, I' z' V' q
{8 B3 ]& n) A# Y! a! J) m
/* Start the clocks */9 ^- D/ v0 P/ f3 c6 d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Y. K/ ^5 n w' WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 o: A( D; [& t% L- @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 v- G3 b% R6 h
EDMA3_TRIG_MODE_EVENT);
5 `7 K: {; K$ O2 n4 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 F# V) V/ Q8 i$ {: REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// q, {( q, l5 p* D9 u% W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 w. H; ^$ l1 Q$ Q. a" ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* O: U/ R5 }/ `* @; bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# @; s, {. j4 G# A5 k2 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 M% A& \ H1 H l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* \6 x' q8 ]: |# }0 u+ N}
2 u! \2 }: G+ G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : H1 [! K" W1 X' y
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