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我的McASP配置分别如下:
- f! s! X) I+ ^: m" L N" o ^管脚的复用设置是:
1 N% h) E& h. e0 N4 K: m0 evoid McASPPinMuxSetup(void)0 g9 c) m5 z, n) q& ~6 k7 V! O$ U
{( N7 P& V- E/ i. i/ l
unsigned int savePinMux = 0;
, V' W8 m) R1 I; S: g* n. ?, t! A savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \8 G; [" ^ \! N/ u( l' t
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \, e9 Q7 ? x4 u0 g
SYSCFG_PINMUX0_PINMUX0_23_20 | \4 W/ H. q7 K6 h+ Z- G L7 D
SYSCFG_PINMUX0_PINMUX0_19_16 | \( b+ g6 S& X* m$ S
SYSCFG_PINMUX0_PINMUX0_15_12 | \
! R+ l. H* m+ j8 `9 E J SYSCFG_PINMUX0_PINMUX0_11_8 | \4 W( S9 I8 R% t* Y1 t
SYSCFG_PINMUX0_PINMUX0_7_4 | \: A1 U8 q4 j. e3 g& S; s
SYSCFG_PINMUX0_PINMUX0_3_0);& K: i. ~+ B* Z
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \( k8 t$ J) U9 `5 V* g
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
- r4 \/ l: S; x+ h( g1 o8 I5 | PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
. Q) W6 r \6 B( e) | PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \4 G; ~4 o) ]3 l/ j) B- Z
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
5 { C; \# V7 e$ \! C savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \2 o/ e0 N( X( r9 ?. Y
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
& d, G% v5 o2 w' x8 Q SYSCFG_PINMUX1_PINMUX1_15_12 | \7 z- c+ G6 m$ R0 y9 C
SYSCFG_PINMUX1_PINMUX1_11_8 | \
5 `! Y, d8 I8 T/ @/ k SYSCFG_PINMUX1_PINMUX1_7_4 | \6 _: m* m. P! T9 I) `- G& h F
SYSCFG_PINMUX1_PINMUX1_23_20 | \: r! D, ^" T" {+ W& B$ T: s
SYSCFG_PINMUX1_PINMUX1_27_24 | \
; D1 H0 c7 b3 }' L6 f2 F SYSCFG_PINMUX1_PINMUX1_31_28
; i5 }( g8 f8 B* H! { );4 N" ~% N) M9 G) U3 g }
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \. j8 Y5 P' f7 W& l5 f& S6 h% ^
(PINMUX1_MCASP0_AXR11_ENABLE | \# k& ~+ a" z, Y' _7 E
PINMUX1_MCASP0_AXR12_ENABLE | \
7 t9 v! B# x8 I- I( ~ PINMUX1_MCASP0_AXR13_ENABLE | \
) @8 I. H% G8 Z' U4 Z PINMUX1_MCASP0_AXR14_ENABLE | \
3 r3 n- }: b' g3 \$ A( u& Y ] A; f PINMUX1_MCASP0_AXR8_ENABLE | \
) Q* t0 |/ k$ ?7 P PINMUX1_MCASP0_AXR9_ENABLE | \% ?+ N6 c: f* m
PINMUX1_MCASP0_AXR10_ENABLE | \
q' K4 [8 ^" ]9 K+ Y3 Y4 x9 u5 n savePinMux);
5 V5 X2 s/ o7 @* v9 |}2 w M! @) F8 r- W r4 o/ z
3 s: Z( ~ O. R: s1.McASPI2SConfigure(); McASP的配置程序如下:
o6 [: i( b8 J0 D; N. E6 ^/ ]static void McASPI2SConfigure(void)( y4 Y9 B5 j% n4 m. j. h
{
# D1 R- y# w" Y& W McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 d. Q/ i' w. ]; r' _8 w% U
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
) B% h) ?! d5 R9 X( j. }. u! ?( P
/* Enable the FIFOs for DMA transfer */% k# `( \! g) i. y
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
3 K+ X f: ], Y. D3 i- ^// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 c4 K. w& N( B4 ]
5 T/ y8 B+ A9 X& n ^ /* Set I2S format in the transmitter/receiver format units */: ]9 s; z% R4 k6 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 S( l; U7 u. V4 B( R* y& j3 C. F
MCASP_RX_MODE_NON_DMA);
, q% z' |$ F( ?% V6 _ McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 n3 N8 e2 W4 J0 c
MCASP_TX_MODE_NON_DMA);2 @1 J+ {1 q7 t2 A! o; d/ u
8 \4 T0 F/ F7 z# r( s
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */' c- b' O$ ^& ^) X& J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 q" O. t2 H- n4 d+ r% k6 F* ? MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 \0 ?6 z8 \- }. h& N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , ^4 w% g3 B, U
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
V/ |, u8 @# h. r+ s
! N% {# ]' b n; G6 _ /* configure the clock for receiver */
4 u/ r+ \* i+ q5 ^5 b* n% `+ ^// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
9 g& f4 b$ \4 r; J# T3 d: g1 P McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 T: y' ?4 {7 N- ~/ ?& m McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. z, w; _' C- l& u4 V! l' M McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, R/ [! g* X+ M2 I) j
0x00, 0xFF);, [4 L0 G$ L4 k& }$ L- B+ A: A# V
" V) M# k+ ?/ Y( D9 ~
/* configure the clock for transmitter */
: p5 h4 F, \) K+ V8 a; J// HWREG(0x01D000A0) = (0x00001F00);( ]3 S o/ p" D/ J6 c
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
7 f. s( x2 j1 o* P McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);0 e5 L3 o- W, I8 i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! t5 R/ L Y, X) k7 a8 c6 S McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 v% Z/ f/ ?9 j( @: X& p 0x00, 0xFF);
. B3 O- |) _( k3 ?; e! y ! s! D6 y3 ^5 ~- b! n0 D# k
/* Enable synchronization of RX and TX sections */ * \: z* v( v; J+ C, p$ J+ J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
' V( ~" o% d! V8 Y% V+ g; X, B9 p1 j
/* Enable the transmitter/receiver slots. I2S uses 2 slots */. k9 l4 @* d, K) W; W6 M2 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 k& h: O: ~* D6 d! k; y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ L2 x6 h ]1 r' p* H* P& a" q
# R! c, k' H; F
/*
5 k' h* u: i1 \0 g ** Set the serializers, Currently only one serializer is set as. l h" A8 {7 O9 C7 u
** transmitter and one serializer as receiver.- a& E7 t$ P7 C+ |. _& J
*/
, R; W, U* a: o3 d" M' @0 P2 {: ? McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 ]+ H P" S5 `' B, }: G8 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
; l s% {' t5 k McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
( l2 |, p/ l* W! v" ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);& n; F9 b9 F7 }: A1 R& ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
& Q0 B9 f/ n7 s) p+ h* [ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
; |. l: s( T7 R: X1 B
* S9 |" z7 B9 M9 i! n! |: C McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
. ]- h' c2 \3 p# B% a* q, O1 l1 V$ n9 p! |% `( ?& t7 Z$ ^
/*
# K/ B$ Y# k8 f6 p ** Configure the McASP pins
$ K% B' I" ~, B4 _% J" p8 f. r/ I ** Input - Frame Sync, Clock and Serializer Rx
& K# i! {' P. m5 ]- `2 \ ** Output - Serializer Tx is connected to the input of the codec + ?' H! R5 z" m
*/
$ }$ ^; i, Y' |2 Q& Q McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' j& T6 ?( K; w8 Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,; t; W0 N; O+ c: M$ }# K
MCASP_PIN_AXR(MCASP_XSER_TX)" S# R9 |" U- H) `6 M7 k
| MCASP_PIN_AMUTE" F$ }, k$ p! {' ~( h
); \8 V# y; V+ S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
4 H- r/ ~" u1 i0 J- m Q- s A MCASP_PIN_AFSX
5 K- Q. e5 @( c2 b6 p X& v | MCASP_PIN_AFSR- F- z" ^# C" E0 \) w
| MCASP_PIN_AHCLKX
, o3 G& r$ j/ B1 Y+ a) p# |. S* l | MCASP_PIN_AHCLKR
0 V7 h& Q5 g7 |; i* _9 C | MCASP_PIN_ACLKX
: a: ~, q1 g4 Z! o, F5 T | MCASP_PIN_ACLKR! P+ y1 W: g: X
| MCASP_PIN_AXR(MCASP_XSER_RX) \4 K- }% l P8 \' Q* n
| MCASP_PIN_AXR(1u<<(13u))
! V1 y3 o3 U# f | MCASP_PIN_AXR(1u<<(14u))4 m2 d, [- F% [/ Y2 l
| MCASP_PIN_AXR(1u<<(8u))$ @0 @( Q' W1 |5 S: y1 [" [" t
| MCASP_PIN_AXR(1u<<(10u))
! E3 U. v' s v2 S8 ^ | MCASP_PIN_AXR(1u<<(11u))
# v V& x0 t" K/ ?0 }, r! Y );
9 k$ d) z0 N% a1 ]$ r8 x
. Z+ s( _5 \+ v2 e2 P /* Enable error interrupts for McASP */" i: C' n# K1 W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,' ]+ {. Q/ N$ H# ~- c% D6 ^3 y
MCASP_TX_DATAREADY
0 C8 v# b9 }: k! |$ { | MCASP_TX_CLKFAIL
& t' i5 N" l5 |( J: F) T# g | MCASP_TX_SYNCERROR! ^4 ]% h/ q/ |3 V" l
| MCASP_TX_UNDERRUN);
) H6 |2 k4 k- _$ Q O) k6 Z. B" b0 y8 ^8 I
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
0 p" F9 a& Z5 S6 z$ v$ o, I7 j- ? MCASP_RX_DATAREADY: S4 g9 Z: o' K- t
| MCASP_RX_CLKFAIL
) x! J6 T* g- W( ?' X" l | MCASP_RX_SYNCERROR
# w3 ^8 G- \1 g/ P' O g4 F | MCASP_RX_OVERRUN);
7 w6 E3 C1 s1 h0 x8 g. n/ v" u//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
5 n+ A& `! v- y$ ]) v# D
: A1 E7 c& C! r6 t$ s0 Q$ \5 E8 t}, I9 \! _" I& g$ d2 M; [
. j Z& T# W9 u7 _* v. C7 O2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
9 o9 O5 s: @- J+ k+ [5 n8 Y+ g7 ^% ustatic void I2SDataTxRxActivate(void)
0 V, \" E: c/ |{8 p p+ W$ Y. e4 [! @8 K. R9 }5 g
/* Start the clocks */; F1 w+ m2 _. Q* B) t7 T! I2 e; g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' P) ^. ~. U, b- v McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
2 _5 O" I1 y$ c/ b2 s! p }
% P$ M2 P7 x i) b6 O4 S3 K" p! L /* Enable EDMA for the transfer */* d T2 O7 ]# v( b, T
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- k6 N6 t$ k% i4 d// EDMA3_TRIG_MODE_EVENT); B% X; d1 W7 W* Z; }) e6 Z
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,) v h# D p% E6 T P$ M+ E' o
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
; f5 m6 U+ h- x! s# s! n5 p /* Activate the serializers */
% T+ ^9 e2 }2 _5 F McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% f T: |) ]" F R9 ~- T" \ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);. Y: [+ f! E% S
/* make sure that the XDATA bit is cleared to zero */4 [3 ~, m K6 N$ ^+ Y0 b( Z9 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
Y! i' o Q G, Z" \3 i /* Activate the state machines */- j d O4 Z1 K% L. J( Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; e# P% j& ~$ `; [" @ McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) Q4 p; g, J5 e& c6 o, T7 }& @ McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
; W$ ~8 x1 [0 l b}
0 f9 C- m0 |" C8 @1 n& Z
6 q% a# Z4 W4 f2 b0 }. Q" I7 { |
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