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我的McASP配置分别如下:8 h3 J' }. V2 I& S
管脚的复用设置是:, g" P: T m0 K- b4 c
void McASPPinMuxSetup(void)$ ?1 d7 d1 d9 V O+ J& G& ^
{- l" c, G: B9 D
unsigned int savePinMux = 0;
, g+ u# j. p- g7 ~" D savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \# r; N: }* S3 u: D1 m
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
, Q0 a3 V0 z+ a& R SYSCFG_PINMUX0_PINMUX0_23_20 | \# a; Y2 j; Y* v' n+ H/ Z
SYSCFG_PINMUX0_PINMUX0_19_16 | \8 @: T5 v% l# y# k" H! ^ u9 P; m1 C
SYSCFG_PINMUX0_PINMUX0_15_12 | \
0 _4 ]& H9 j& i! f% |! R! G/ W. O' K8 ] SYSCFG_PINMUX0_PINMUX0_11_8 | \, y G" X. |- v& k' z/ s" [
SYSCFG_PINMUX0_PINMUX0_7_4 | \
. Y+ x& K9 ~: a/ E7 ? SYSCFG_PINMUX0_PINMUX0_3_0);
- D/ K( |; A8 x+ V' C/ I HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
" q8 D% i' f4 t# h6 M (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \( W. X6 a* e8 @. t! V/ s! o
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \! y7 o" W4 d. ^8 R) @9 a- W
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
5 G; r9 `% G; F) \/ [8 Q PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
# ]7 o; ~3 _: i+ `! P& m savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
3 W# X8 t$ E8 \2 h7 ? ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \, e2 [" ?6 A# \" g$ [. y- t
SYSCFG_PINMUX1_PINMUX1_15_12 | \
; ~) c/ Y6 m+ g/ c3 M4 r( H SYSCFG_PINMUX1_PINMUX1_11_8 | \; h! o& q. n1 \* j" u2 w" Q% E6 f# Q
SYSCFG_PINMUX1_PINMUX1_7_4 | \
2 A7 n" c! b: i! j9 b; B1 C SYSCFG_PINMUX1_PINMUX1_23_20 | \
8 B% K4 }8 R) A: M3 o8 r3 ^# m2 p SYSCFG_PINMUX1_PINMUX1_27_24 | \8 l* g3 c1 ~# B3 e$ \, n, A
SYSCFG_PINMUX1_PINMUX1_31_28. e$ }! p$ i9 V2 K
);6 n2 W/ V8 L2 E& L; ]
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \$ A+ S- I/ i+ k$ _# y
(PINMUX1_MCASP0_AXR11_ENABLE | \! g- Z' A) x/ T/ }8 G
PINMUX1_MCASP0_AXR12_ENABLE | \* s. C' c' E, i
PINMUX1_MCASP0_AXR13_ENABLE | \
% t6 x# m5 b6 F1 ?& ~. n PINMUX1_MCASP0_AXR14_ENABLE | \ _7 p6 Y# ~7 E
PINMUX1_MCASP0_AXR8_ENABLE | \$ m# @; i/ ^- }- T4 u7 ?
PINMUX1_MCASP0_AXR9_ENABLE | \
+ c F% A" h# r0 y; @% f5 c( a; R4 p PINMUX1_MCASP0_AXR10_ENABLE | \
3 B! x3 Y h# o% T savePinMux);9 C; J, J7 @* s) d/ J! }- ^+ P* ]
}% D$ [. b) \/ r L
1 d" ?$ t! ^* r( l4 G) X3 Z) m
1.McASPI2SConfigure(); McASP的配置程序如下:
D1 o7 r# c- W2 s$ X' dstatic void McASPI2SConfigure(void)
' |, n( I; w) F4 M8 X! L5 r{) _5 b# U; T0 g4 T2 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ u( n+ a, D( T! g# h: j8 Y1 { McASPTxReset(SOC_MCASP_0_CTRL_REGS);2 g5 L& X# K, Y# `' ~% q# n$ G0 N
% z) P1 H# ^ T/ P
/* Enable the FIFOs for DMA transfer */
8 O3 o% v% v3 T; `& Z// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);6 y y) L& H6 M4 r' J; H$ o
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 M. I. \5 L, P$ p* Z9 B
% e, @# M1 g+ v; d# z /* Set I2S format in the transmitter/receiver format units */
& U' q* e& e. _( V McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ~2 B$ {( I, x. `- X$ R$ U$ V4 G( T1 v- }
MCASP_RX_MODE_NON_DMA);
- T: d1 B- D" V McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# m, @2 O; z H Z
MCASP_TX_MODE_NON_DMA);6 S% m+ i8 ]) r5 F9 ?- g" ?
: o8 s# Q: \* l7 _7 V" \6 \+ W. i v
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */" n$ z. H: U1 B4 N0 Y L# u; d( m. c$ C- j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # A% h, @) o5 ^* x) f) t6 k3 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! B0 k! z: L% f: b7 o' {) e McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 @) K$ H# f+ r MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);, h, P, l- R. q$ _
7 `& ?9 ~% C4 w z; Z
/* configure the clock for receiver */
+ |' T6 K# ?) C4 E2 \- b// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);, ^" O3 I3 A$ N7 V" r# O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. \9 d, `" W8 V5 K- N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 k1 ?3 n0 A5 j McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 _) e$ `: o( V
0x00, 0xFF);
, }# s/ M7 x6 N+ K8 D, N& v
% H& a6 _% c% F9 {! W# x /* configure the clock for transmitter */, y( n2 }; {9 _$ N/ V0 R9 z
// HWREG(0x01D000A0) = (0x00001F00);/ N6 e2 ^7 J' s2 I: K2 O
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
3 [0 q8 X/ Q4 E* g( |( y4 x McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
+ [, F3 ?/ t+ H# ^7 u. R$ a McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% r/ d& y7 B/ h McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 D6 N# R2 }1 g; `1 g/ r. ~
0x00, 0xFF);3 w, l; Z/ a% V# ]$ T8 U
+ n& ~6 F( j& ?# o7 a3 k
/* Enable synchronization of RX and TX sections */ * P3 A0 u# m4 J, }7 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);" k% G* J3 a% Y* x! R
# T) C* D P, ? /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 u5 Z* N3 a R$ ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ v. G0 u: f. t+ S, W8 w% V9 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' S" U6 Z. U" F! e, M5 l1 ^5 u ?! V0 d
/*) E& _7 @8 A, X, R' I8 R/ C% f
** Set the serializers, Currently only one serializer is set as
6 U7 j+ C4 R4 e' h# N) D ** transmitter and one serializer as receiver.( P$ X& D5 v" t7 l2 T
*/
0 V( ]0 j% C6 j0 K z) J$ `/ ?$ W McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); c, i4 y1 e& X& s7 O! w( F2 ~; k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);# V, T; N$ @- h' Y, T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
" L0 w8 U2 B4 z2 Z1 X# ~6 s McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
1 u! B0 |0 T/ O7 r McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
* G9 T) o( W- T5 g; z McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);' t) u# L: j+ `) x* e/ a7 u
4 t. C0 r6 N' N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
: ~& I1 |0 e& X8 G4 R: [( ^) y# `5 c8 ?6 s7 I! k
/*& B6 k2 y9 e" `: H
** Configure the McASP pins
& o2 r% T- m2 p% ]! L ** Input - Frame Sync, Clock and Serializer Rx
' e$ g* w8 ^7 Z v, N4 ?7 i: } ** Output - Serializer Tx is connected to the input of the codec
" o1 X# ?$ R: V& u* X *// X" P [5 E& l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* G, f! J" x2 m+ d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,% R5 u6 X! `$ U6 w# a% N/ H
MCASP_PIN_AXR(MCASP_XSER_TX)/ I" j- Q3 l% Q9 B4 e/ |1 r! o# m
| MCASP_PIN_AMUTE
: a: [# N0 h9 S; Z/ R );
+ K. w/ K' {0 r0 P/ R McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,. \$ j6 v3 s3 \' ?
MCASP_PIN_AFSX# H# @, i# B: C m M. h
| MCASP_PIN_AFSR& z( o$ f9 j8 J- ]: u0 z( L5 V
| MCASP_PIN_AHCLKX( k4 y7 r: `; @2 @" Y0 g1 U
| MCASP_PIN_AHCLKR# z4 i' B% \7 D
| MCASP_PIN_ACLKX( @5 X1 _1 \9 v2 i# I
| MCASP_PIN_ACLKR: Z# f/ R; V8 m4 S+ q- w6 r
| MCASP_PIN_AXR(MCASP_XSER_RX)
$ p( Y) n$ b$ S8 f. a | MCASP_PIN_AXR(1u<<(13u))2 j2 f/ t$ i q5 A
| MCASP_PIN_AXR(1u<<(14u))
9 _5 U- I' _; b, b \$ `3 M | MCASP_PIN_AXR(1u<<(8u))
# ]) a, h, U! }: O8 O. A3 e | MCASP_PIN_AXR(1u<<(10u))* d* ^" u& K) |( ^6 G: P) |
| MCASP_PIN_AXR(1u<<(11u)). N G+ f) X0 d _" f; _
);
2 a6 F7 b3 q, }7 U5 H9 A* \/ `. u
/* Enable error interrupts for McASP */- r) d1 ~$ [- ^ a: l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,7 [- X; i1 L' ]+ T% }' |; h, f
MCASP_TX_DATAREADY
! v8 G7 Z) I( s) ~+ Y& e% U4 p | MCASP_TX_CLKFAIL ! Z/ b2 ?* I; w' e
| MCASP_TX_SYNCERROR5 \) \$ J; J0 T' S1 ~* N: E
| MCASP_TX_UNDERRUN);
/ Z4 M9 d5 v9 V; D" _2 q3 Q3 M0 C W9 a# S7 s
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
9 A1 a6 V# v/ E' C& r MCASP_RX_DATAREADY5 f! `# y+ N/ q/ U. X
| MCASP_RX_CLKFAIL
5 A" a7 f/ y# p+ I% ~" ~ | MCASP_RX_SYNCERROR
2 g& M- |" L: v, X | MCASP_RX_OVERRUN);) @* k# Q& G3 ^, A% K8 [2 c! ]* u
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR( ~% S3 D& i# Z5 p3 Z6 x
( Z0 X _( B6 O: \}- l0 H( }" d5 Q: d% m
) m# m; [& @; @2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句; P( T5 j% a6 q% Q4 J
static void I2SDataTxRxActivate(void)
2 d9 ]6 K8 F C4 S# X{9 Q* |8 b+ o" E4 W. J
/* Start the clocks */% u8 B& v( \5 \: b& Z9 t' Y( C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' ?! D, `6 C* `5 v, s; z5 P, p McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);, o# R, H/ x' ^7 ?! `4 m- g$ L2 W
f6 D2 E5 `1 O3 A) v /* Enable EDMA for the transfer */
- E, D' o* g- y2 n) Q// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 N4 ~0 H7 a- D5 ^8 g8 V: h
// EDMA3_TRIG_MODE_EVENT);
8 y5 i4 y0 ^- ]0 A+ A$ j8 [// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
[% ~, Z0 ?5 k8 w) I+ I& e- c/ X// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
+ g3 s0 R! h6 E* s0 V /* Activate the serializers */
0 y! W( m6 L; p- y0 x0 o0 ^ McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 O7 R6 w; u9 ?3 ~6 a9 a2 o* \7 O McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);0 m0 x# m5 `, d
/* make sure that the XDATA bit is cleared to zero */8 [8 Q! N& |+ e9 r4 R7 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);' P- \4 t1 \9 S, E# ]( {
/* Activate the state machines */2 i" E9 L1 I3 B+ m& r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- n/ @! b6 k' |; n/ ~ McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 `5 \7 i! J4 n* Z( o& N
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
% `2 T, L! a ^" w% Z# l: O}
3 m0 h6 }% m6 X' O# m$ E: G( j6 t3 \, D h" S o v
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