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我的McASP配置分别如下:
6 m: E' |( T) E/ o+ {% h; J管脚的复用设置是:% X( ^ p1 E U2 l. M
void McASPPinMuxSetup(void)( v6 m# `& Z" S: g, a* V( K# q
{! M5 t. z- w" _& c; a
unsigned int savePinMux = 0;; U9 [& f& c. q/ d. Z
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \9 T0 a i: |5 I
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
* ?8 A, t7 z/ Q, s- |# |9 X( r SYSCFG_PINMUX0_PINMUX0_23_20 | \
# k& R0 \- `! o3 A" Y, z SYSCFG_PINMUX0_PINMUX0_19_16 | \
% q( s8 f/ d$ D SYSCFG_PINMUX0_PINMUX0_15_12 | \4 n# e1 k& ~* @/ g- U' a
SYSCFG_PINMUX0_PINMUX0_11_8 | \% m2 f. q) u. [9 R2 x$ c. N" Z t
SYSCFG_PINMUX0_PINMUX0_7_4 | \
- @$ J# D- [9 v. l' m; Y SYSCFG_PINMUX0_PINMUX0_3_0);3 U. q/ Y" U# q; U% c
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \; ]6 g$ P3 X* z8 s
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
- } m) T3 c: D PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \, ?* a, j. f$ d; _
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
4 B* @* ]$ P6 M* P# f# Z PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux); F' s6 v# }( P' x# `7 E+ F) `1 |2 @
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
, V6 O* j. S7 T; S k9 Z ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
; d# T$ x- h4 J0 a- g3 B SYSCFG_PINMUX1_PINMUX1_15_12 | \
# J8 G4 j# l5 g" v SYSCFG_PINMUX1_PINMUX1_11_8 | \, }* w, O6 J7 F
SYSCFG_PINMUX1_PINMUX1_7_4 | \
9 z* K1 x5 A1 K g2 Z SYSCFG_PINMUX1_PINMUX1_23_20 | \3 I7 Z7 X! o% C: P/ Q
SYSCFG_PINMUX1_PINMUX1_27_24 | \! H& D$ A) p" Z l9 \% \
SYSCFG_PINMUX1_PINMUX1_31_28! _7 w- M4 P* R, S
);
1 Y) O4 m; C) X8 F8 B. N HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
/ M/ u7 ~8 T5 {/ L (PINMUX1_MCASP0_AXR11_ENABLE | \
, n% r2 U: G" O+ | PINMUX1_MCASP0_AXR12_ENABLE | \
- N& ?; R, `$ A- } PINMUX1_MCASP0_AXR13_ENABLE | \
8 ~1 m5 \" g3 f. ^ {$ g PINMUX1_MCASP0_AXR14_ENABLE | \
. ^: d2 s& H0 z: D; g PINMUX1_MCASP0_AXR8_ENABLE | \) B; A( a: c$ G+ q/ s
PINMUX1_MCASP0_AXR9_ENABLE | \; z. l5 p4 m( K2 W! Y. H- _: P
PINMUX1_MCASP0_AXR10_ENABLE | \
- J$ R1 {+ g9 {( B5 ^8 l" z savePinMux);
: G$ S6 p9 O3 @- P6 i5 w}
- r1 n* { w9 w1 C
7 K t# {' n/ I- r5 G9 ^1.McASPI2SConfigure(); McASP的配置程序如下:5 S$ \8 ^/ b: t2 N0 R ~7 E- b
static void McASPI2SConfigure(void)
. t* Y/ U) Q# @ E4 r3 h{
1 h5 I6 K7 ?! l0 Z' O8 K McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 ?. b+ x# ?: q. C McASPTxReset(SOC_MCASP_0_CTRL_REGS);
e& Y; l& F4 V" I) s9 J& ~
! u& U# o/ m9 ^1 b; [4 j5 A* ^ /* Enable the FIFOs for DMA transfer */- O+ Q5 j: S5 X; ^$ R
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);, W1 f& ~& n6 M: ~1 {
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 J7 ^+ r+ R* c2 G8 R0 z& Q
& a, V6 p1 R% o# k# F
/* Set I2S format in the transmitter/receiver format units */1 W6 Q; F& g5 N, J9 F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, ~. \7 X, c( P1 b, R4 b: Y
MCASP_RX_MODE_NON_DMA);# x; c8 Y- I/ b( ]9 f9 u4 p/ R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% B5 Z5 n: b, W0 D2 R MCASP_TX_MODE_NON_DMA);" _% D$ W5 G6 K% a& I5 {
4 r, K. W; R0 t0 ]2 } /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! j/ r% ~7 ~* V% f* G* z' h McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 ?# u0 Z- ~, R+ V& q& z7 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* F5 b% a) v; F McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: ^7 P/ l6 X1 A5 \5 D) ?: Z0 X: | MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
8 f6 @$ r1 U" M5 {- {1 D4 Y
- r7 V2 g/ y8 F* g, x0 M /* configure the clock for receiver */
9 X! q( G% o$ I/ B// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);- Z+ D6 r# w7 b; x0 b2 r, A' I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) T% S0 b# O: K9 h5 P7 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) S! V- L. L5 E% O: p3 v# S McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 C7 h+ `% ^. C; C9 U' e+ c
0x00, 0xFF);
+ c) r# O# i6 }# [- w
- X2 A; J6 S6 R4 ~* N /* configure the clock for transmitter */
) E% n$ o. |! m! @ l// HWREG(0x01D000A0) = (0x00001F00);
6 c% E8 `) b3 U) t2 n// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
& k+ i: e' t( Z( k McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
# f' g2 s/ J, ^ McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# A3 I {0 X5 _$ l4 R9 t8 ^$ R) d McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( f d; x/ f( x5 d7 l! b0 T. y
0x00, 0xFF);
- }: p1 ~# I! O! z# i. @8 | D! Y , p* b' B( ^! f9 O: R0 D
/* Enable synchronization of RX and TX sections */ + s$ A; |$ C7 I0 z$ @3 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
# i& s; a) Q# V0 L w l
9 o; c; Z6 z0 e: L /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ ?, e* t5 x7 \- i8 G! k McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 F0 p* i& j& Z/ R/ O" ]4 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. v* A( {' I I$ m4 a
' y7 x5 z7 ^4 s/ g8 t /*( V3 ~; P2 V( M# n( L
** Set the serializers, Currently only one serializer is set as
' v O$ b: i* U ** transmitter and one serializer as receiver.2 h4 N( b& A* x: y% t, f4 o) V
*/
5 {' @, P# x+ l+ Z: s McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ S/ n, C. R5 ~, ?. |; h McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
4 u$ x" \4 b% n) ` `4 ~( A& w McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
2 ~! O- K3 z& X7 Q. M4 W McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);; C5 u$ G3 G( g, e. |- I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
) P& _2 v; }! c L6 }) B+ Y1 z; U) g McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);7 e5 x$ L; l6 [. ?- o. A
# d: E. F/ p/ P. D7 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
# j8 T) `2 O. T
8 V& q4 \5 e/ _- \& J3 R% D /*
; h- M" w8 ^+ _ ** Configure the McASP pins
9 S$ l5 j" b0 ^! L$ g: l: a ** Input - Frame Sync, Clock and Serializer Rx
: n6 @# g/ U* z8 \3 u1 H: { ** Output - Serializer Tx is connected to the input of the codec
\) P) o/ q) B/ U2 P) l */
1 {' a2 E! L1 a6 l7 m7 B McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; W% q P4 b5 d9 d2 i: t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,& r4 v/ v# h T U0 h, j
MCASP_PIN_AXR(MCASP_XSER_TX)# ?5 f9 }! w$ G7 h0 b- k
| MCASP_PIN_AMUTE
7 K$ |- m# j( @4 k( q7 [ );/ Z( s1 M. G# I- D+ R6 e0 B+ |/ ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
: q6 v5 a# C2 `3 @ MCASP_PIN_AFSX
b1 x# d! h! j, L$ |6 L5 r4 u- e | MCASP_PIN_AFSR6 ^9 Z; o, a: M
| MCASP_PIN_AHCLKX9 f; Y: _8 E s+ j' Q% k3 z( W% @8 s
| MCASP_PIN_AHCLKR
6 {* M' N" m6 \4 M& N | MCASP_PIN_ACLKX
4 T4 ?9 U5 b$ e3 ` | MCASP_PIN_ACLKR
8 h1 {3 {# M+ b6 Y# h( I7 I | MCASP_PIN_AXR(MCASP_XSER_RX)
X0 M, P+ ]8 E( j1 m/ W1 O | MCASP_PIN_AXR(1u<<(13u))
3 j9 c1 v0 d$ i, E | MCASP_PIN_AXR(1u<<(14u))
n0 o, d7 P- {+ F6 w; W | MCASP_PIN_AXR(1u<<(8u))
5 {: k" n; w0 Y& Q | MCASP_PIN_AXR(1u<<(10u))
5 u9 `' [. Q2 `2 Z4 X1 { | MCASP_PIN_AXR(1u<<(11u))0 Z" g& v9 P& z
);
, k c2 v& O0 v. H$ J# _: K+ @/ b$ W4 Y# E
/* Enable error interrupts for McASP */% i+ W: K( y# I* R8 N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,( b2 }3 ?9 d# ]7 `" U
MCASP_TX_DATAREADY
$ X8 y( a' B4 o( Q. E/ m0 N | MCASP_TX_CLKFAIL . {/ W3 D0 Q# C' b& k6 w
| MCASP_TX_SYNCERROR
1 N- r8 L+ R, i( ]# e6 \* o* m9 n | MCASP_TX_UNDERRUN);2 v- _' _; k. m
5 t5 Z' a8 i# Y% J( _% S McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
4 a9 \) K, \. T) z MCASP_RX_DATAREADY
8 x8 [- O' e) a7 T$ t | MCASP_RX_CLKFAIL
2 B+ |" d6 l% d- i" U7 |" m6 l | MCASP_RX_SYNCERROR 8 I2 q8 \( Z, e: i
| MCASP_RX_OVERRUN);' S5 b J" T% x
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
6 p1 `3 V' b# w8 y# h$ G6 P; Z; |/ j5 c& E- l* N0 P9 Z
}
5 T4 o& E. {& S2 |3 J" F- H- `* q. A
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句1 s! `0 h& b+ {! ~
static void I2SDataTxRxActivate(void)7 x' l& t% `4 c" a1 i$ I5 `; G
{: P& k$ S- k$ P0 s" m) \
/* Start the clocks */
/ c6 W+ G% `0 N4 I2 u4 ?2 s& I4 d McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 b, q) [! @' b5 u McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);- H: W7 f# v7 y3 B" Q5 Q
1 P1 [4 ^ |# q9 F v& W, h! C5 N
/* Enable EDMA for the transfer */
1 e4 q9 t( v8 G0 F. I// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," l0 v/ e( q, y" `, i/ P# E: |, K
// EDMA3_TRIG_MODE_EVENT);
+ q0 x/ m- ^! b; C// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,/ j9 a+ o% V( i: V6 Q# H) z% \* b
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);+ [: ^- Q$ j- s" y* {4 O! h
/* Activate the serializers */
* j b. H4 N- V/ \2 q1 o0 I McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 A+ l* Z! k. e$ @; h. u McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
% _9 L$ w" A/ m /* make sure that the XDATA bit is cleared to zero *// r' ]- S4 I2 V4 L! v, [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);7 r% e$ D1 k; D2 `+ v3 T
/* Activate the state machines */* E2 R. V% x% T5 [2 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 D3 [) {4 f y# r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 r, B7 h: I$ C McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
- f0 M% F+ S* E3 T}
7 ?! g( F; d# V& j; ]. H$ n! s+ c/ y, c8 Y% E) Z9 H) R
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