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我的McASP配置分别如下:3 n. H1 n% m2 h
管脚的复用设置是:) r( x4 u8 ^& p$ Z, n! \
void McASPPinMuxSetup(void)
2 D, X8 A9 ^6 k) a& h{
! J0 \$ G+ M$ ] unsigned int savePinMux = 0;9 ^" n' w+ Y/ R& A2 X
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \; K2 y! X$ w% u& H7 f! b
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
% c. k+ _6 D7 O8 P; A1 I SYSCFG_PINMUX0_PINMUX0_23_20 | \& E6 R9 }% W: ^. R7 u
SYSCFG_PINMUX0_PINMUX0_19_16 | \
4 |( W( _: u m! N# f6 m- ^4 y SYSCFG_PINMUX0_PINMUX0_15_12 | \; w" g, a, k# F; f! C
SYSCFG_PINMUX0_PINMUX0_11_8 | \
' }# M3 L; ^% F0 R SYSCFG_PINMUX0_PINMUX0_7_4 | \
9 w7 U( t6 ?; F* a5 W3 F SYSCFG_PINMUX0_PINMUX0_3_0);
' Y0 r. ]# ~ S1 y6 q HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \; k& i% U6 B( C- D) b' i3 r
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \+ C" t. ]; {) p. f+ ~, R# m ?% o# G; C
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \+ B, n, C8 ?7 `! d& N% _% m
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
4 c5 p5 I, ^( M# w. M. d PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
% k. C6 I+ j4 b+ f, S+ W savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \% r% ~% c; P- Y3 X7 J) }3 X
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
. R! c4 V5 [: x Q" K% u1 G' t SYSCFG_PINMUX1_PINMUX1_15_12 | \
( l1 ]! K9 {1 I+ T SYSCFG_PINMUX1_PINMUX1_11_8 | \
" B2 B; p! i$ @/ G3 ? SYSCFG_PINMUX1_PINMUX1_7_4 | \
- L* p* X: `* J. j6 C. F SYSCFG_PINMUX1_PINMUX1_23_20 | \8 ~/ t3 a9 n4 z9 U8 ? I5 g
SYSCFG_PINMUX1_PINMUX1_27_24 | \! |6 E; z5 I W- G
SYSCFG_PINMUX1_PINMUX1_31_28. b5 b: y1 `+ B" a- T" N
);
' P a; E- r0 J& y+ i8 D$ W" K HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \3 M* B% e7 L/ u4 `9 D# M
(PINMUX1_MCASP0_AXR11_ENABLE | \, Q! e! v: B+ l
PINMUX1_MCASP0_AXR12_ENABLE | \1 u/ ]7 a& \) _7 I% `' R
PINMUX1_MCASP0_AXR13_ENABLE | \
4 z7 j5 W# V# T; h PINMUX1_MCASP0_AXR14_ENABLE | \) b6 M7 p; R3 `; l5 _) K
PINMUX1_MCASP0_AXR8_ENABLE | \
. c v- _. I; W) v4 Z7 g PINMUX1_MCASP0_AXR9_ENABLE | \# X5 ?" M' D# A) x$ I& x
PINMUX1_MCASP0_AXR10_ENABLE | \
" ?, P% Q8 t& R* n2 P savePinMux);1 N9 k4 ?2 o* f7 T4 z
}
9 g( r8 x% j4 G
! H( W- t( f0 a1.McASPI2SConfigure(); McASP的配置程序如下:
1 {7 O: T3 D& k$ e. y% Fstatic void McASPI2SConfigure(void)
7 J8 g4 P- w. c3 {$ k3 s8 [8 ?{7 d8 O8 }; P O% g: Z6 n |( v, o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 n* T: z; v; A McASPTxReset(SOC_MCASP_0_CTRL_REGS);+ i# q- A, V! @+ r5 a) T+ t
# D8 g- ] s- J' t0 a3 \ /* Enable the FIFOs for DMA transfer */
% }) O6 I! ~) ^- k. D3 n5 [// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);' {- }) }+ d$ X
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 v, `9 _- s% m$ w
0 Z2 C# y9 U! l$ w, C* @: c4 I /* Set I2S format in the transmitter/receiver format units */
9 s2 D4 X" v5 h) ^( a" A, X McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- a- ?, O! V: n! Y, g: A; w MCASP_RX_MODE_NON_DMA);& b( I$ y8 E% W6 h5 K8 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' C* b3 v. T+ B7 ~9 L MCASP_TX_MODE_NON_DMA);! f! t* q: ~% V7 W
# k( _, k0 y" q( C! W' g- h! t; ? /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) N; d. d0 ^5 p6 p/ _$ V6 v* j& h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : X g- a2 }, Y, w8 T$ K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( h& J# u* X# j: T! C- a9 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & l# X' P) l/ }# n1 |6 [
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
' [$ ~# p2 g" b/ a! l
6 w! p2 n/ E/ }8 ~- C# `0 [* q /* configure the clock for receiver */
" }) r. s# w2 Q6 m: f! E) X# I// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);: r) Z. f0 } ~1 j+ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" i& [0 \3 |- a; k) f9 E McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);/ n. R/ O% J0 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 \4 s- G/ w U- ~5 a 0x00, 0xFF);$ D7 @: K6 m. l/ h1 n# T
' |- ]. o; t# J. z, M /* configure the clock for transmitter */
& m1 l/ y& L# I( _1 D8 U- @// HWREG(0x01D000A0) = (0x00001F00);& X! A1 v& t3 i9 C1 o9 u
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
+ j$ {8 h& `$ \3 W& T" A2 V+ ?% Q McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);5 ^+ l- g0 ?4 }( f# M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);1 h4 ^0 y. X: A5 F* ~" N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) j& b1 b1 e7 f" y: T
0x00, 0xFF);
. M! b% q F) q$ }9 d: f% B ' p. v0 M; f! \ W5 s
/* Enable synchronization of RX and TX sections */ , |( O8 x2 k& {% l; g1 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);% E. |2 ~) E1 m
# w! k- u- B1 N e# K
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: p6 |7 L$ A {' X McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 b) E3 E( s( g2 L b& i; F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 E R; R/ `! P9 }& ~, N2 l
- d8 z8 p, O( _+ y9 L* z /** P2 d. h4 i' ~8 W; c* x
** Set the serializers, Currently only one serializer is set as5 m3 J/ t6 }( `# h8 f" a
** transmitter and one serializer as receiver.6 \5 ~! n( g# Q* Q& ]
*/! ~. E; c k* m! ]4 Z) j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ H+ P8 j/ Q# J6 G. F1 o* u- f McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
8 A* T) k5 }8 Q# d8 `3 \, d- Y" ^+ p McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
+ ^* v. k7 b1 T' \ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
% d( [# ], _9 {3 @% O6 a McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
/ U5 p0 ]+ |) }( Y3 C McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
: z0 E8 q' ?- ]( D5 d9 m. c
# V/ O* J) A, R- h8 q' G' K+ m McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);6 e1 q9 C$ a, O8 n. Q# b1 Z
: f8 F7 b: H' Q+ T( F, D
/*
; C/ b3 B$ l0 k$ X ** Configure the McASP pins
+ g; k% a. l' M* O ** Input - Frame Sync, Clock and Serializer Rx
8 J0 x4 f/ Z; j, j8 S* R ** Output - Serializer Tx is connected to the input of the codec 7 ^% N6 `& Y& \6 g
*/
* k L2 R& X4 @3 h McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& |' s2 h0 z: c+ }6 @( m) I6 }- g7 u McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,2 x8 o. u$ g1 V' H9 F
MCASP_PIN_AXR(MCASP_XSER_TX)
/ t2 a/ w- U( }+ v | MCASP_PIN_AMUTE
1 {$ v# t! A) S: [" Z- W );- M: ^( U: G F1 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
( c+ Q5 k1 y$ z7 `. j7 O- | MCASP_PIN_AFSX0 A( A/ A+ x( k. o& x/ z( q3 z- ?
| MCASP_PIN_AFSR* s+ N0 V4 t i4 q% Q5 ?5 p
| MCASP_PIN_AHCLKX- o7 g) c: ^9 d2 v
| MCASP_PIN_AHCLKR% U- _- `2 B$ H( T. x0 @
| MCASP_PIN_ACLKX
M. e+ [( D/ l+ f/ F | MCASP_PIN_ACLKR( Z1 M0 ?1 F1 q+ J/ k/ C! @
| MCASP_PIN_AXR(MCASP_XSER_RX)0 Z. T! N- [7 K s5 ~( ]; S/ y
| MCASP_PIN_AXR(1u<<(13u))( w: D5 z+ s' C/ n3 |) r9 j. l C4 c4 ~+ p
| MCASP_PIN_AXR(1u<<(14u))
* b$ l/ n! _' Z8 Q6 j5 k$ V- E" X Y | MCASP_PIN_AXR(1u<<(8u))
! [' E3 f+ G' Q! G6 G' W! S | MCASP_PIN_AXR(1u<<(10u))" ?8 y, P" N6 D+ ?9 l
| MCASP_PIN_AXR(1u<<(11u))7 T4 X( _" l: B; ]; Z1 _& r
);
0 o+ E. N3 o( X* x1 k) v1 |1 x. C2 l! F, [' ~# W/ j
/* Enable error interrupts for McASP */& O% D* V9 V1 E! O: _5 g# v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,: q; b3 Q5 n6 g4 L6 ]
MCASP_TX_DATAREADY
# s1 v4 Y& a7 I | MCASP_TX_CLKFAIL & H: G7 N; j/ Y7 j& }# d
| MCASP_TX_SYNCERROR
5 X" O4 y4 D+ t, J | MCASP_TX_UNDERRUN);
' I" h5 y6 M P, L, [% v3 S7 O+ t/ \8 a% o/ q/ I& p
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,: P7 |. r D3 `0 b7 e, P( A
MCASP_RX_DATAREADY
2 J, `! S4 B% w; z' o | MCASP_RX_CLKFAIL2 J+ O( e. D4 h: g! o3 @2 o, O1 O. {
| MCASP_RX_SYNCERROR
0 r4 K2 \6 F/ A. `- k, w( I | MCASP_RX_OVERRUN);+ p3 U- N0 n6 G) J; a
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR1 n2 Z; K y+ ~+ U/ r& \! I
" H1 ?1 \0 ~3 `" N
}
* O+ ^- T2 l* a; t# ^+ ]3 l: Z/ a% ~# i2 I8 n! w6 F# C
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
+ p5 o6 _! g4 _( c% Z, j& H Vstatic void I2SDataTxRxActivate(void)
+ |$ Z% Z+ {0 N1 q0 j: n: K{
' V' z1 C% l& C+ }! ? /* Start the clocks */; ?3 N s7 N' ~0 I4 h0 ?$ j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# {# k8 I3 f6 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);: s; S7 b0 v" A- V5 H. D' |
' h5 k0 r- b. v /* Enable EDMA for the transfer */
* C& }5 @) h7 _& {& d6 S" T6 W// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& i$ ]5 X0 Q# N, e2 ?+ Q$ E// EDMA3_TRIG_MODE_EVENT);
- k8 t3 G! _5 G$ x/ | B3 y// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,* b* {1 g2 r" }% O1 u
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
2 c" R% C& a7 m1 H4 _. u! u- p /* Activate the serializers */
4 m3 Q9 L7 ?9 L8 Z' P1 d McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 m2 G( S# I, o- `8 f7 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);, c; @! r: ]$ _2 h7 O% d
/* make sure that the XDATA bit is cleared to zero */. B+ i9 j! K4 r, E- [# [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
7 M" }# h) e1 W/ E# { /* Activate the state machines */
+ }. ~5 E6 B& m+ d2 L McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, }' X- {# R7 D; w! A8 Q McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( E S3 S6 y3 [) A9 n
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
( w, |1 ^$ h" n: u}$ |1 x2 t( o) S p! d
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