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我的McASP配置分别如下:
1 c/ K" x4 Z1 P管脚的复用设置是:
7 A/ \5 `4 q Q1 C+ l8 ivoid McASPPinMuxSetup(void)
- {/ j q% {! u' y4 [) n* ?{$ h( s9 y# J9 t
unsigned int savePinMux = 0;$ S: k1 A! q& i3 Z4 R( S% S
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \- r# X' ^0 Z" N! ~6 P
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \3 ^" c2 l6 I3 q/ J- @- T
SYSCFG_PINMUX0_PINMUX0_23_20 | \* Y8 b. c6 E7 R1 n* L4 f
SYSCFG_PINMUX0_PINMUX0_19_16 | \
! `+ y/ g7 G% E, y9 G SYSCFG_PINMUX0_PINMUX0_15_12 | \
/ ~; L- X2 X: c SYSCFG_PINMUX0_PINMUX0_11_8 | \
# {, b% ]7 |4 t+ Q SYSCFG_PINMUX0_PINMUX0_7_4 | \7 k: Q4 R, F7 y |# \2 U
SYSCFG_PINMUX0_PINMUX0_3_0);
: z) V5 [! W& |$ @8 g3 n5 U HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \: \5 g9 x1 x! e1 S: U
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
& J/ G: w; O! f7 k5 g PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \0 ]8 \/ ~. L% n9 K+ m
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
1 T$ e( v0 m9 s3 K# }1 I9 q5 ]9 J PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);, r0 B( r- a4 ^* Q; |! \
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \3 C* H* ~4 {8 v2 m
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
0 g" Q' @7 I$ l; e; t+ Q. z3 { SYSCFG_PINMUX1_PINMUX1_15_12 | \5 o$ ~' B$ e" j- x* V7 | W
SYSCFG_PINMUX1_PINMUX1_11_8 | \* \5 Y" H5 ^3 M+ n$ y
SYSCFG_PINMUX1_PINMUX1_7_4 | \
/ G. L+ ~3 l* ~$ d SYSCFG_PINMUX1_PINMUX1_23_20 | \
- `$ `+ E. }* X' O5 _ SYSCFG_PINMUX1_PINMUX1_27_24 | \0 q& K1 v I9 ?
SYSCFG_PINMUX1_PINMUX1_31_28! ^% T0 b6 t4 H) Q" [8 f
);
, X# A% B- r- U8 o* T4 a HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
) R' k7 R, C" e, K$ \8 p (PINMUX1_MCASP0_AXR11_ENABLE | \$ k/ N* q6 r/ @
PINMUX1_MCASP0_AXR12_ENABLE | \
5 I, Q: m! }2 u* G6 T PINMUX1_MCASP0_AXR13_ENABLE | \
, T& n* j8 A+ ^3 a/ h PINMUX1_MCASP0_AXR14_ENABLE | \4 h1 K+ T/ W0 b$ C: B$ g
PINMUX1_MCASP0_AXR8_ENABLE | \: e2 y) e4 M/ q6 Z- @/ J i# t
PINMUX1_MCASP0_AXR9_ENABLE | \* X; i% x/ B; l; q
PINMUX1_MCASP0_AXR10_ENABLE | \4 J: F, J8 ?! a% }# a& w+ v
savePinMux);
B1 i2 \( t8 X0 h! O: g}
4 _# p% Y8 }* m' g% B U& `+ I7 H8 M/ | J6 j
1.McASPI2SConfigure(); McASP的配置程序如下: i$ q7 r# c c' e9 p
static void McASPI2SConfigure(void)4 Z/ q& P0 y/ o, I m
{" }: D9 l1 x( _9 |+ A/ C( q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ }6 h, G, ]2 \) X& N& Z McASPTxReset(SOC_MCASP_0_CTRL_REGS);$ h' h8 X, z' N4 {% k. B0 U
2 u6 h# c! R- {; }
/* Enable the FIFOs for DMA transfer */# D( i) l/ w7 {$ m
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
+ x3 a- f* n# q# _// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* W3 D% t$ g6 e+ u
" q+ J. l0 X3 j7 l! h) A8 F /* Set I2S format in the transmitter/receiver format units */) X+ t7 g; O0 m3 f2 z4 b, Q0 j+ T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 J1 u2 @8 n( H" P; E MCASP_RX_MODE_NON_DMA);' v2 B* X6 s9 _" a2 n9 ]* i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 R- \$ d' H7 c2 S. _ MCASP_TX_MODE_NON_DMA);
- p7 ^4 g! A9 _' w, ]0 b ?4 P1 |' ]0 G( N- y+ a
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */' E5 r- X: [: C7 `0 E4 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - N) z9 m5 _! \: _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 B$ Z' G4 \- q! g7 e McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 a# \* c! B8 u: v3 z" I- g
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);! F; o4 [, _1 n( f: \ |
. h* g2 V6 V! T+ X! N
/* configure the clock for receiver */
, O& k/ e+ L. d4 `& j// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);3 t/ H0 l4 q( e3 R6 a- p- A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* U3 U# d! Z: @3 b5 r6 N6 s/ f McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 U6 y: N7 b9 o( ^+ }% M McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ P4 Q5 V4 ~4 T6 d
0x00, 0xFF);
% N+ J# K" ~: h% |8 y3 `* }, K0 @1 k" Y2 c
/* configure the clock for transmitter */
4 {2 e E6 W% s# v- B" t9 ]) z/ G// HWREG(0x01D000A0) = (0x00001F00);, g+ S* ~, u0 U. [: {) O
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
2 T, A5 _6 Z1 \: s2 M# W$ ^& n, g McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
% q9 j8 S6 O: e# S McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: N4 ?# j* J4 E9 o McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 a+ B) d! D2 v) O
0x00, 0xFF);) j7 K$ h5 R- G- u( D
o% J, |& v5 t; m2 j% ^" Z, p /* Enable synchronization of RX and TX sections */ + |. V1 o' |5 H# ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
& r ~8 w9 k) w' |- G5 |3 [
* j* v1 |+ I, f! Z, U /* Enable the transmitter/receiver slots. I2S uses 2 slots */& [2 B: e8 Y: C- c; G0 }! N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 q8 a" ~; P" ^( q" N5 V McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* J# q+ I3 A& G. l) I( X
* g5 ]( ^& N2 c7 V /*/ R, }: X+ b5 p% x4 j1 W; w
** Set the serializers, Currently only one serializer is set as
, g* |2 G C! \+ R( D; C ** transmitter and one serializer as receiver.
0 O# r' Z& Q/ z3 Q' M9 X+ D */- t- t" }$ ]2 J: p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 H0 P" \. \* Z& T2 \8 i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);6 q/ r, v% g/ R* m5 g; T7 ?" ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);5 _: U1 N, S6 S. |0 j8 G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
! l8 i1 G# c9 Y; D McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
9 c2 X$ G# A2 ? McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);. L+ j2 l' b& h4 j2 r8 ]( f) I
% R% }- `1 t2 G3 h& Y2 v% _ McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);7 A i* }! S6 [/ p5 q9 ~
; r% f2 i# Z, K9 H* M) a& b" t7 ? /*
1 f4 q% Q+ f2 M7 W9 h ** Configure the McASP pins
+ l; n( v/ N9 Y) M1 c ** Input - Frame Sync, Clock and Serializer Rx
2 V( q/ o! ~ n% [0 } ** Output - Serializer Tx is connected to the input of the codec
8 m0 c3 B2 T, g a! u C9 f2 m */1 J' Q3 o2 P7 }8 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
G. P9 Q1 E& L: T# v- } McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,% S- f2 u5 u- p; U( {% L! k
MCASP_PIN_AXR(MCASP_XSER_TX); h+ r$ w j; m3 _
| MCASP_PIN_AMUTE
0 d. ~) k7 F% o$ B2 o );% A# ?2 R& ]0 w$ e9 x% R3 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,7 O& h8 t! ?; j7 g* b: {2 U. k
MCASP_PIN_AFSX
9 V7 O g( N5 ?7 p7 U/ B | MCASP_PIN_AFSR
: v( D! V9 \# G4 g* c; ] | MCASP_PIN_AHCLKX) u6 Z1 f2 p' l
| MCASP_PIN_AHCLKR% a- u& y( K6 O8 c d) _4 G
| MCASP_PIN_ACLKX
+ m/ c5 A) m3 n! A | MCASP_PIN_ACLKR
/ j P4 o+ B9 T# W | MCASP_PIN_AXR(MCASP_XSER_RX)2 l2 S; e9 x1 E, O4 E t
| MCASP_PIN_AXR(1u<<(13u))
" c1 F8 S# c3 D& J4 I" e6 W | MCASP_PIN_AXR(1u<<(14u))
$ ]- b4 b6 j& I" k0 Y0 [ | MCASP_PIN_AXR(1u<<(8u))5 F+ J4 [7 O V) ~0 H5 K7 C/ c# _
| MCASP_PIN_AXR(1u<<(10u))
# U- A, G1 U0 a3 a3 ]2 l9 H3 s8 a2 [ | MCASP_PIN_AXR(1u<<(11u))
) C4 X: z* s2 ^, E- E) i. r );9 w* p# ?0 R. `; B
" z, [9 I0 Y2 e /* Enable error interrupts for McASP */
7 Q. ~4 m3 q: `+ N! C) z( \ McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
; l! X* m* M0 L" {7 X MCASP_TX_DATAREADY
* o: w3 w5 Q6 s8 o1 ~% ` | MCASP_TX_CLKFAIL
9 l8 g# X; ~4 b; t' J | MCASP_TX_SYNCERROR
2 X' }1 o3 c+ S/ E8 G& I( A | MCASP_TX_UNDERRUN);, q) O. }4 C% W
1 G) G6 @% Z) r! ~ McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
& @2 X: ^4 r- I) o5 o9 f" c MCASP_RX_DATAREADY
% v$ P A0 H. i* u* q( c" H8 D | MCASP_RX_CLKFAIL
6 T6 K7 C: }4 m | MCASP_RX_SYNCERROR
2 B8 N% A# T7 w O | MCASP_RX_OVERRUN);
! R! O; u2 C' ^//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
& i- U1 s! d1 C2 g- E: Q* j" n
: J' y/ S; g) `* p) B}4 b' _3 z" ?' P K+ P7 ?- h
9 [0 B3 I' z0 I2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句2 Y" b u+ R$ z: |9 B3 H
static void I2SDataTxRxActivate(void)! A6 R( P7 w' a" H6 F
{, {9 \* j* h+ Z- a+ m( I
/* Start the clocks */
# G' Z2 F9 N2 Q McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ q" |5 }, b8 I. @8 V0 O McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);, j% t5 ?4 G2 a5 K( _
. U% u u; U5 W7 n2 q0 L2 L1 I /* Enable EDMA for the transfer */
: \8 r% Z( h, r1 ~// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. o+ p' D7 D. {" o$ U" q, _3 p// EDMA3_TRIG_MODE_EVENT);; B; y! w( l7 M; h# [/ T( M
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 P1 O: C" Y8 f! w. w. K0 |" z// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);( L" J9 Y! u) Y# ]' m5 A
/* Activate the serializers */- t9 j5 {) A% b; n" m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( {2 \0 ^6 g& S+ N2 [( s McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 ^8 x. v( y0 e3 V% k5 \ /* make sure that the XDATA bit is cleared to zero */
6 u7 H! D# X8 [2 _4 b. o% c/ i: g while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);2 C) @( ? q! l
/* Activate the state machines */
/ s1 D: ?* W: p5 E/ u" _, l McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ Y% }, b. e9 K! s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ Z4 u6 c4 b2 E+ M McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
4 W {- R# d% b/ C; k5 S}4 C) C- v+ @/ m
# I/ D' v3 D/ p' B4 e$ _) o, t
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