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我的McASP配置分别如下:
3 t8 S+ @. z- r, [0 j c4 |8 X' R3 n管脚的复用设置是:
2 ~, O2 J3 d/ I# Q7 J5 B8 [void McASPPinMuxSetup(void)
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unsigned int savePinMux = 0;7 N7 x; o8 F. o9 s; b3 o' S
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \4 j- h4 i n% y! d
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
6 m" H$ W3 w! D4 I" _9 r. T SYSCFG_PINMUX0_PINMUX0_23_20 | \3 d' ?) i' V \ J& l
SYSCFG_PINMUX0_PINMUX0_19_16 | \5 I$ Y& a; h- F1 H
SYSCFG_PINMUX0_PINMUX0_15_12 | \
. N- |2 C ?9 f SYSCFG_PINMUX0_PINMUX0_11_8 | \
/ b: t# m8 R# J( _1 I SYSCFG_PINMUX0_PINMUX0_7_4 | \% c% k: [# E( p9 p7 j! y6 f7 n
SYSCFG_PINMUX0_PINMUX0_3_0);
0 u3 c- \9 N! ? B5 E) W0 ] HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
3 y2 i3 h! U, y1 |& M( ]2 i- r% B (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
/ k( k) I* k3 D4 e PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
( f, D' I& S" L4 T, j4 d PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \, O% d2 y2 Y" m7 {1 N, `; Z# x
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
+ D# \& S0 z+ V& e savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \% a. M: a* Q' a7 g0 o9 X! s: A
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \$ H5 a* B s, G7 e9 O% J+ N4 [
SYSCFG_PINMUX1_PINMUX1_15_12 | \
) @4 a4 _6 v( g( b) R SYSCFG_PINMUX1_PINMUX1_11_8 | \
; t6 d! H: i$ I9 v$ z SYSCFG_PINMUX1_PINMUX1_7_4 | \
9 s# H- B' x& M6 O% N* W( K4 ^ ^ SYSCFG_PINMUX1_PINMUX1_23_20 | \6 g1 A- f& y7 ~+ v
SYSCFG_PINMUX1_PINMUX1_27_24 | \1 M U) n/ r6 h. P
SYSCFG_PINMUX1_PINMUX1_31_28. o I0 S6 u3 ]: ^0 b$ \
);
( @( \# ?. e) k/ V; x HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \$ P1 Q2 V$ q1 c& W' m: {: f* R' n
(PINMUX1_MCASP0_AXR11_ENABLE | \& @- c4 v$ C2 @& e5 h. W" Y( p
PINMUX1_MCASP0_AXR12_ENABLE | \; G! j! G" g) h! k Q
PINMUX1_MCASP0_AXR13_ENABLE | \& X% Y1 v- f* Z. N- \5 T. i
PINMUX1_MCASP0_AXR14_ENABLE | \4 C9 Z* C3 s4 d& |, o' b
PINMUX1_MCASP0_AXR8_ENABLE | \
3 X2 G) h8 g; M; ? PINMUX1_MCASP0_AXR9_ENABLE | \/ u& _+ Q- P2 q9 A
PINMUX1_MCASP0_AXR10_ENABLE | \
3 K. Z+ k7 w4 d q savePinMux);
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8 ` Z/ u8 `8 q/ E' F* {5 Y1.McASPI2SConfigure(); McASP的配置程序如下:
- B% ^- C1 y7 F7 ~/ @; cstatic void McASPI2SConfigure(void)8 r9 e8 U. H* T1 f! w' g V0 P
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 r2 E% Z _. C, P1 S McASPTxReset(SOC_MCASP_0_CTRL_REGS);! z0 ^4 W1 y, r% \
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/* Enable the FIFOs for DMA transfer */
& t/ m, Z$ C% N, d& I' E) H// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
( p4 D, S- ^. L1 E- X, M' N4 g* l// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
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/* Set I2S format in the transmitter/receiver format units */
/ |. i/ s+ Y+ |2 S) }$ }- H McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 l) |( }& P ` MCASP_RX_MODE_NON_DMA);
# D8 J4 Z% E- B$ f McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& S2 Q4 p. D( D MCASP_TX_MODE_NON_DMA);$ }- n5 @: g B: c% s: l
+ W' H! i7 Q5 g; R2 J: F /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 s' p7 U& t6 A, C) G5 p% n3 a0 x# s McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 H9 n& U2 M4 v% O+ R! S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 v/ C; S) P- y2 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& |1 D, W4 \3 i2 ~/ D4 b( s" y5 F MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);1 o' M- Y% E4 X0 `/ [
9 w& A! M6 z( I" ^) s7 l; A
/* configure the clock for receiver */
$ m( a4 u5 g& N// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
0 \3 |( B* k" O McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 u" ]. T( P0 W8 n8 `) O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);- i" d7 ~! F M' N k. i2 l& t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: _# h- W: P+ A+ Y2 e2 H2 X7 ?1 A0 J
0x00, 0xFF);& w) k- K1 `0 s$ D1 [3 g; w$ _
& f) h6 x, K. z, O# n
/* configure the clock for transmitter */
" C( x L: p7 v7 J// HWREG(0x01D000A0) = (0x00001F00);
2 V; j% ?% y9 i" `/ n# M. ]3 Q// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);! V) N) o% r& I! a" x- w( E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);3 X1 u+ W- g2 P) W' l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);. m8 j7 }0 @9 y# Z1 x& i6 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ g3 C. c8 V M3 @; E 0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ ! B7 K+ C' A+ V x2 |5 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
5 D, m1 O- X |; f
0 Q6 d2 j# H3 F9 D/ g9 G /* Enable the transmitter/receiver slots. I2S uses 2 slots */* p4 O# ], m( m# T6 p' n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 U. ?) s: d& q+ x) @ o" d# j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 q$ |) ]. ~! _5 \& o- y# b) E; ~" l. O' _
/* j) B ]4 f4 s& ]3 X- ] G" ~
** Set the serializers, Currently only one serializer is set as
1 T: t: C% S8 E* ~ ** transmitter and one serializer as receiver.! B+ ^6 Z/ X3 ^5 w
*/
9 `& s( c4 }8 u7 R! l McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! R0 X3 |& j) m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);8 H% ]* S! r: m( M1 M7 q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);+ a* ]* g7 D i" T: @/ X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);7 O$ e1 l- ?/ f8 z- N9 w( |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);% K# \ t4 v3 o& x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
+ G& z# U7 Z8 C8 F3 Z; x$ W/ v# N
0 a O6 ?1 f" X& b* @) C! R/ j McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/ Q0 ~ S3 `; i6 E; L/ s( i
2 a {; D' V4 H3 ]( p5 f2 Z1 x /*
2 A( H( m; ?- ~8 Z( ^; Z8 _ ** Configure the McASP pins
5 d" }' T% u- Y. x2 t* A5 r2 _4 S ** Input - Frame Sync, Clock and Serializer Rx
- ~6 n p3 Z8 b# A9 z" T; \ ** Output - Serializer Tx is connected to the input of the codec - i$ C; P4 F- w Q. S0 B7 y
*/9 h9 F+ A/ Q) a& V$ S9 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; [, F/ G2 [+ U; u& a, z8 ~ McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,0 |. e, a# h- k3 m
MCASP_PIN_AXR(MCASP_XSER_TX)
H2 p# Z; V3 M) d1 n) u- d | MCASP_PIN_AMUTE" f5 r# I( [: v7 d h7 V! G+ u
);
6 s9 t: I& i% r4 R McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
, I$ ^7 ^- K H6 _7 }7 z MCASP_PIN_AFSX5 V# d" N+ w/ |' B, l- D
| MCASP_PIN_AFSR
0 `* ~8 C+ {$ q! v | MCASP_PIN_AHCLKX5 B* X; A( R3 H7 i) v
| MCASP_PIN_AHCLKR0 t0 N4 n O/ T+ o# J' |
| MCASP_PIN_ACLKX
* g2 f0 u- C: E! h$ s | MCASP_PIN_ACLKR
9 O8 m3 J! Q* t% ^3 K, K" c | MCASP_PIN_AXR(MCASP_XSER_RX)
" M4 u% ^: O% B0 V( j6 _/ L | MCASP_PIN_AXR(1u<<(13u))# ]: b: g: |0 x7 E5 o5 U3 v, A
| MCASP_PIN_AXR(1u<<(14u))
9 j$ D. k Z" R8 x5 b | MCASP_PIN_AXR(1u<<(8u))
2 I/ G) ~; {7 N1 o& B' I& f3 e | MCASP_PIN_AXR(1u<<(10u))3 }8 i& n3 ^, d, _; j5 Y$ t
| MCASP_PIN_AXR(1u<<(11u))
: q5 s, w6 i0 \1 g2 o; I );5 d* i. Y7 \. P5 d- U
" O+ s2 V, t6 Q /* Enable error interrupts for McASP */
7 m) R5 d7 _1 A: V! U1 B McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
% M! I9 G: h. G! w3 W MCASP_TX_DATAREADY: i: G; e2 Z7 H ]6 Y
| MCASP_TX_CLKFAIL
! v+ x: m2 }9 b; W2 k; C | MCASP_TX_SYNCERROR
* r# e# \5 i! [3 ]" N# V5 [ | MCASP_TX_UNDERRUN); A T$ _) k- K* a9 N
/ w3 s. T) e2 M* i+ D. P- m1 j McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
4 L% m+ ^& l8 \1 r. s. s( t3 j MCASP_RX_DATAREADY7 R5 N5 f6 Z5 m' {
| MCASP_RX_CLKFAIL# A, K: m0 ?& f. x5 m! g2 j( s
| MCASP_RX_SYNCERROR & v; G+ t$ P: y) n- z7 Q" ^
| MCASP_RX_OVERRUN);" Y+ E: ~. _2 X; i$ s$ T- I
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR {' a; n/ }5 q% s( V
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; Y) V& w" v( W( W1 [9 `2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句4 S2 ]! S% C: ?) r
static void I2SDataTxRxActivate(void)
: q4 |+ ]! g9 p9 M" L0 u" L{
4 v1 j2 v/ s. S4 _% Z2 b) @ /* Start the clocks */6 V+ W+ e: @/ X n; T+ `! R6 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 A3 V3 E& u8 n8 K3 Q McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
& \% Z8 s5 A( n7 x0 k2 W; w8 N( H! v+ m& o9 K) M+ m! ]
/* Enable EDMA for the transfer */
- n. W0 {- _7 w& Y5 M// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ R3 r" {0 d3 n6 h' J// EDMA3_TRIG_MODE_EVENT);
7 ]2 J. E% l% Y! X+ n, Q// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 D. g# d) L f% h# \! d// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);. ^% e( a/ c: S& s
/* Activate the serializers */. L: G# G: k5 D/ I! V8 j: W) I/ b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. y0 g+ G% a8 l2 {( o: m) R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);4 A2 B5 r# k# q
/* make sure that the XDATA bit is cleared to zero */7 y$ h3 I5 G) Q' C* {! B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);7 a1 B* G. P+ X
/* Activate the state machines */2 G" m$ I2 `8 ]! J3 k7 }% a) T5 a6 v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, { a. ?0 d8 m: O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ I3 z5 J: K3 Q) ~
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
8 E6 g" o, t4 b- L}
# K8 s8 L& R& b! n4 s2 H* u# \ x
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