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我的McASP配置分别如下:
: w4 s% p- ]8 h b3 |管脚的复用设置是:* M7 h* j( }; q/ |0 g2 S0 c$ L
void McASPPinMuxSetup(void)
% k# B- f- w0 J3 i; F{, J4 O: l& s w" c" J- n
unsigned int savePinMux = 0;1 V% c' _! ~/ z- W' q# l
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
- I& B% a' r0 u ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
4 G8 s, R/ [6 W* @7 x% g/ B: \ SYSCFG_PINMUX0_PINMUX0_23_20 | \0 @5 e9 S1 @( v. c; r7 U: D
SYSCFG_PINMUX0_PINMUX0_19_16 | \
& X+ g& ]9 Q3 h SYSCFG_PINMUX0_PINMUX0_15_12 | \
( \+ |# A: \" R. G SYSCFG_PINMUX0_PINMUX0_11_8 | \
, r" u7 m) e& z- k6 d SYSCFG_PINMUX0_PINMUX0_7_4 | \( }. J( c4 m- S! i' z
SYSCFG_PINMUX0_PINMUX0_3_0);
' S: B% w1 K2 d8 `0 i) z' T HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
- l1 }$ h. o3 j (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
& H- C, p7 k- P( S5 F' P0 K# w" Y PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \7 V# O. S- x, \+ q+ T. P" f" @$ I
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
/ K3 g) H- \( h0 t, \) Q5 T PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);, O/ x1 k; \( Y/ D
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
) o( R g8 n* g& k% b c3 t- |2 O ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \' U4 @+ m1 p8 f( O2 H, B
SYSCFG_PINMUX1_PINMUX1_15_12 | \# u! [# v0 _4 C
SYSCFG_PINMUX1_PINMUX1_11_8 | \
0 a; C6 Z! q1 W$ M SYSCFG_PINMUX1_PINMUX1_7_4 | \
# T9 U: e0 U9 { S2 B SYSCFG_PINMUX1_PINMUX1_23_20 | \
6 G+ V; ^- ^* q& o9 B6 q SYSCFG_PINMUX1_PINMUX1_27_24 | \/ r9 A0 I% @4 r$ o1 a: X u
SYSCFG_PINMUX1_PINMUX1_31_28
, P* X- J* U, u5 t2 _2 v );
, x* l: X1 ~, X HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \) F$ ?+ c) h. n6 \% L9 H4 X8 C
(PINMUX1_MCASP0_AXR11_ENABLE | \# T; t# n5 O: m* O' A
PINMUX1_MCASP0_AXR12_ENABLE | \
2 W* h- H B* ?6 y; F4 s PINMUX1_MCASP0_AXR13_ENABLE | \
1 J* m K/ S3 N PINMUX1_MCASP0_AXR14_ENABLE | \
, H% X7 R& I: x% A- C6 b _ @) B7 c PINMUX1_MCASP0_AXR8_ENABLE | \1 `9 W5 u/ }# `- ]* L* Q: q2 C+ z3 r
PINMUX1_MCASP0_AXR9_ENABLE | \
0 O8 X9 f& S" W, x PINMUX1_MCASP0_AXR10_ENABLE | \- m$ y) ]7 {5 }8 d# k: R: {
savePinMux);
4 h7 H$ e6 {3 _0 J}1 ^$ c$ p0 o& A; {# @# P
E' ^& I" y6 p" s( n1 D. a4 s3 z1.McASPI2SConfigure(); McASP的配置程序如下:
% i8 h8 h* f( ~% K1 a1 qstatic void McASPI2SConfigure(void)* T7 Z& v# Q T" a1 f" M
{ g* {9 E! ^8 n* C; D2 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 b: h- G6 r# R& X. Y McASPTxReset(SOC_MCASP_0_CTRL_REGS);( S, x& ~3 ~) R) l }4 R, a
4 G2 Z6 W* X6 @5 Y& m9 `% v /* Enable the FIFOs for DMA transfer */
# _, j( _9 v/ }. F' [# D// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
% a* Y# d- \9 O2 l# A" I( F8 t// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); h% B& ]9 x3 D- d7 e$ U
& J8 r# ^" h/ [7 t /* Set I2S format in the transmitter/receiver format units */
0 o) B0 R$ R" N. V McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
V9 X* y! w V! V MCASP_RX_MODE_NON_DMA);, P$ C! a9 p+ X3 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ U0 u8 K0 G* w) p
MCASP_TX_MODE_NON_DMA);# I- S7 L, t; m J: _ X
8 ~/ p( Q0 \9 k% o# D5 U; e
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */" G- d7 m: d/ K0 ?0 X" u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' s- c8 ~; _# V" v( K2 D3 J MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; C( Z( w* p# B1 {9 p) C McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! P5 z' M: a1 G: L! u6 u! J+ H2 o
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
4 V- y$ h# l" d' s+ c
- |5 n! M3 x3 W" n) {) c( l! l /* configure the clock for receiver */
3 l9 L" Q' R- L# B// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);8 I* t0 x) T6 G" f: P1 J! I( S0 L% v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ q; Y7 Z# B9 p' c7 ]9 q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);% j" F9 ~, {) @- ?% g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# ?1 D( e( D3 H% N2 X* c1 Q
0x00, 0xFF);' J& T; L5 I; w: {# R3 w
/ A3 F( ]/ F2 \: a
/* configure the clock for transmitter */1 ^1 I: K$ e( m" x: d: u
// HWREG(0x01D000A0) = (0x00001F00);
% Y3 }9 |1 L8 \7 m// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);; E2 t" D! u4 O/ t% x$ M+ x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
1 L D) T+ W: y% \6 S/ D McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);( F* I0 z2 Z4 m. W* `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 j. h: g" `5 W S p! T& e0 H( Q
0x00, 0xFF);
4 o/ g+ F+ A4 _! V6 i$ G8 g2 S 7 k/ V2 O! g2 Z2 w) o! Y0 a9 p( j- v
/* Enable synchronization of RX and TX sections */ 3 Q6 x- r) }' M' n5 q8 Y" M! N. F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);+ H: q2 T$ N7 @! j% i: r8 ]
0 y6 ]+ G- Y3 ~5 n& a, |- h" ? /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 ?5 V* t" i" m5 D McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- q: E( e8 L+ i/ {7 w6 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 u& _) i) {$ j! i _4 S
, c& G7 m% l9 Q# _+ k
/*
+ v' u3 G( @/ M- f+ v( w ** Set the serializers, Currently only one serializer is set as
g$ b2 D& r) N5 X ** transmitter and one serializer as receiver.! q! L" f) F- ?$ Z3 u4 ?
*/6 v+ x1 d% k) L) z% z, a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 h1 x8 v/ }/ n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
2 l& d, W7 J8 {9 \6 O( o McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);' ?0 e0 k8 H# X/ S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
7 E6 w' c8 I( }3 s" [/ D McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);7 b0 Q( B. Y0 _4 y% i1 n3 f. m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
, \3 `9 l1 J/ c* ^* `2 h n4 V9 \( d: L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
* ]5 {3 w# P m; }3 q
$ X! p& U8 H3 S/ s+ n /*
0 l$ M9 E* Z2 g3 f ** Configure the McASP pins
: T$ W7 h- k1 |/ Q% } ** Input - Frame Sync, Clock and Serializer Rx; q9 ^) _) c" x) e7 b( E
** Output - Serializer Tx is connected to the input of the codec
" E0 ~! R+ p1 z x- {6 K9 Q+ |+ |6 j */
" N( | Q L) \, V- c. ` McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) ?: W1 s4 [7 n. h! I. ~. p- \% J4 z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
8 R& W7 q9 O8 y8 q" u8 c MCASP_PIN_AXR(MCASP_XSER_TX)
1 W8 C% w) D: T& ^ | MCASP_PIN_AMUTE
9 P' h7 h; b+ m. Q/ u; [# G V );
6 C' d7 _/ ?2 @" i7 r9 N% n8 ] McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,- ], ? O7 m3 s8 x: w8 @
MCASP_PIN_AFSX
: e! i2 k7 c3 w& m7 W. ~9 N$ {5 ` | MCASP_PIN_AFSR
0 e" U/ P# Z# A | MCASP_PIN_AHCLKX
% q# t6 N+ p2 b: M& ~ | MCASP_PIN_AHCLKR
# }7 I' R' H( D | MCASP_PIN_ACLKX3 b; i' H/ F0 g( j& l$ F8 \
| MCASP_PIN_ACLKR8 ?; F O0 z* b. j% Z- u
| MCASP_PIN_AXR(MCASP_XSER_RX)
" p4 F) @; H7 B$ S/ s& b | MCASP_PIN_AXR(1u<<(13u))% l- S3 J7 B7 M2 E: W$ N& G! U3 E& a
| MCASP_PIN_AXR(1u<<(14u))
) B7 F# Y3 E; a% C6 w- N | MCASP_PIN_AXR(1u<<(8u))2 j( o7 s* w5 l& X6 k+ g. K
| MCASP_PIN_AXR(1u<<(10u))
( f! B4 Y: i$ f/ |3 J' u | MCASP_PIN_AXR(1u<<(11u))7 Z, z2 q r% ?, b0 o' G8 ~
);
, Q0 [3 g" T& |( t x: S0 Y' {
/* Enable error interrupts for McASP */
0 s. H+ z) r2 i2 V) k$ i McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,: B u! E7 L6 v# W6 h' l/ \, W
MCASP_TX_DATAREADY$ D2 N- x F0 T7 x1 v) d
| MCASP_TX_CLKFAIL
* Z( Z; d) l0 R | MCASP_TX_SYNCERROR: h# N4 F8 w2 V% h8 i& ]2 u9 y( Z
| MCASP_TX_UNDERRUN);
# X4 h% q4 F0 S/ z# y+ ~1 g3 h# @( p7 @ |/ m* E* K! c% ?7 [
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,6 {, G) j- v. u2 \* l* A
MCASP_RX_DATAREADY1 K j6 `. K$ M, V0 p0 i, n
| MCASP_RX_CLKFAIL" d! T) |; v- W' x+ J$ a
| MCASP_RX_SYNCERROR
( I6 v4 n, y+ L. { ?- X; W0 [0 | | MCASP_RX_OVERRUN);
8 q; J0 R/ h5 E) X# j* O//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
; ~* M3 f. z5 `+ k) ?0 S6 a% f& |/ F7 e; w3 |1 E
}
, X6 R% a% J1 E$ z! o( U+ \" n: j: B& _/ `. H1 s
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句9 P! l7 j. P9 C9 O
static void I2SDataTxRxActivate(void)
1 Y" F* @, l& q4 {; [! z6 q" ]$ J{
. u. o4 ^# I Y! [ /* Start the clocks */7 t; T5 y# O. Q5 P2 s) O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. n6 ?7 O0 ^8 U. P; B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);5 Z+ G7 C9 `, a& w) S
, \( \8 c; T# K
/* Enable EDMA for the transfer */
7 p5 D& t1 L- t/ U" M9 D' t2 D2 [// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! f7 B0 R. a$ h2 F1 }; u! W// EDMA3_TRIG_MODE_EVENT);
+ O- R% U! B5 A' x7 }" P* i" v. ~ t// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. H$ P) {4 u1 h// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);: ]. C/ ~5 ^6 ?& o3 G: }4 @6 N. M
/* Activate the serializers */
4 D/ r$ a& k! F: C9 n1 q! W McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 k0 }& `1 D! t, I: y+ u8 A$ \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
, S9 ^5 t8 z" j! z5 O /* make sure that the XDATA bit is cleared to zero */. }1 m: O/ ]" D. \/ S+ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);, \6 ]# \( U5 n5 T# h4 t" S- Q
/* Activate the state machines */
8 W* b* V7 H1 q& _ McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: p- Q0 C1 Y! |0 g3 Z6 n; u" ]" }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" v P/ ?+ u1 B! { McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);+ K ]# U! n' T5 i
}. X4 o5 t$ r& c; ?+ f
4 q; [. K* W5 c- u; A9 ^3 j |
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