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The timers support the following features:
) k+ u7 T$ I) }0 S4 p) Q• Configurable as single 64-bit timer or two 32-bit timers: b& C2 t9 ^) n/ C
• Period timeouts generate interrupts, DMA events or external pin events: n7 r) s9 }2 @/ y
• 8 32-bit compare registers
$ k ^8 W9 z. t% j1 w5 t• Compare matches generate interrupt events
6 J' p& O3 g6 J. }• Capture capability
0 ^; n2 K2 E( c3 u! L' u• 64-bit Watchdog capability (Timer64P1 only)
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/*+ n: j/ @, C D% X ?( o4 M( {
* T0_BOT: Timer 0, bottom : Used for clock_event
; ]( N) X6 K L: o% n * T0_TOP: Timer 0, top : Used for clocksource
; i; z0 A6 R) l1 G0 K6 `' d6 o * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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