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The timers support the following features:
; T. K$ U9 N! _/ j2 g• Configurable as single 64-bit timer or two 32-bit timers7 [5 ^9 k0 ?3 t! z
• Period timeouts generate interrupts, DMA events or external pin events6 m M! B! r" N" S# l9 d) |
• 8 32-bit compare registers6 [- }$ c( S+ O' d" \
• Compare matches generate interrupt events
$ A+ I; D- o8 J# p! B. I• Capture capability% D+ P5 n" r% K, l& U, b1 I3 u0 s
• 64-bit Watchdog capability (Timer64P1 only)& Q$ M0 Z2 ~: ]! b( P- p* ?
3 A3 l( r) e; ]5 h& G
/*0 X' C8 {9 J8 H, U
* T0_BOT: Timer 0, bottom : Used for clock_event# d; I6 J3 g4 Y/ ~
* T0_TOP: Timer 0, top : Used for clocksource5 A8 u- `0 ^! e- `
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer: ] o+ U- Q, T( s7 g; h
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