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The timers support the following features:
" D! Q- p. E& o- ~) L• Configurable as single 64-bit timer or two 32-bit timers# v! R) f& I; R0 I
• Period timeouts generate interrupts, DMA events or external pin events
6 u; g9 q. G& b' W# d6 U( S• 8 32-bit compare registers$ w T& B" C8 i' c) j
• Compare matches generate interrupt events9 {8 _6 k" E! ?5 r% ]5 ~3 T" `% O3 g0 u
• Capture capability
. e% v# U1 {0 w+ d- y1 U w• 64-bit Watchdog capability (Timer64P1 only)
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; ]9 L4 d- b3 u0 F" O p; ^& X8 h/*
4 V& b6 q, l$ r! I- o. r. y# L7 ^ * T0_BOT: Timer 0, bottom : Used for clock_event3 N, l. d4 O: X! \
* T0_TOP: Timer 0, top : Used for clocksource
( d& q+ D& {- F, S9 g5 X * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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