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The timers support the following features:
! k* P! T4 x0 T7 W- g( r1 W( V• Configurable as single 64-bit timer or two 32-bit timers
+ M" e9 C5 A+ s/ v, d. C• Period timeouts generate interrupts, DMA events or external pin events
0 W: v( R1 s l; ~" B+ m• 8 32-bit compare registers+ ]- V0 |4 D) h6 }: U* w( N4 Y
• Compare matches generate interrupt events
9 ]) u& u1 w N) M8 a5 y' i9 R4 A• Capture capability
& g4 N, \2 r3 |" ` {6 z' I• 64-bit Watchdog capability (Timer64P1 only)
7 P4 l) ^4 u1 n% V* ?/ c4 P- L5 {/ j1 E9 U* ^2 _3 p: X- \
/*
9 V8 ~; h8 D; ?' E3 w( l, r% k * T0_BOT: Timer 0, bottom : Used for clock_event
# H" }5 N6 B5 U0 C4 N2 f * T0_TOP: Timer 0, top : Used for clocksource
$ j, _6 P7 ~, D% P {1 P3 N8 G * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer3 n5 L! J/ K4 A( X
*/ |
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