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The timers support the following features:% S) E" ~% {5 e
• Configurable as single 64-bit timer or two 32-bit timers
7 q- n6 Q$ D- C1 x+ Y9 `• Period timeouts generate interrupts, DMA events or external pin events8 h3 V# G7 `( f" D' C8 P% X% b9 g
• 8 32-bit compare registers
0 }: Z" b9 n, q• Compare matches generate interrupt events
9 D) d' i" \9 K, v% M• Capture capability$ y8 j! u8 W6 v% o/ V" Z8 {8 F
• 64-bit Watchdog capability (Timer64P1 only)
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/*( {% `( K' \/ n" F" C7 ~
* T0_BOT: Timer 0, bottom : Used for clock_event! v2 G0 Q1 U* ]4 n+ {* F- f
* T0_TOP: Timer 0, top : Used for clocksource
6 B/ f: D% Z c7 V8 ^' Q# r+ } * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
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