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The timers support the following features:
( I# E. y9 {. i• Configurable as single 64-bit timer or two 32-bit timers
0 W' s* r/ G5 O5 P% Q• Period timeouts generate interrupts, DMA events or external pin events; O8 Y9 E. E3 o) p4 p U. d; \! z
• 8 32-bit compare registers' U3 u! m3 c/ h/ S2 F
• Compare matches generate interrupt events
" d# {9 e: x; k* u' I7 m• Capture capability9 Q- ^9 ~& v s1 E3 l/ O/ y5 Z
• 64-bit Watchdog capability (Timer64P1 only). v" P) | G' ^
& y5 ]0 a5 ^1 s; s# S/*
3 c; R6 B1 `3 x. W2 X+ ^ * T0_BOT: Timer 0, bottom : Used for clock_event1 [. y( J& c/ |( F) B
* T0_TOP: Timer 0, top : Used for clocksource4 T' R `" b( t; C( g" }: V
* T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
$ E4 s) q" }1 I/ y3 W5 q */ |
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