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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. h/ s) v+ t9 Z' s# n" X
input mcasp_ahclkx,7 f8 W& T( n5 e( k
input mcasp_aclkx,; x. c: I9 o4 [# _
input axr0,4 w0 j8 n+ J7 J5 O
6 K7 W: s4 Y' [
output mcasp_afsr,
& n! c& ~) d8 i6 c6 G0 houtput mcasp_ahclkr,# w& X/ s: n7 B m* ?- G
output mcasp_aclkr,
& l( f$ M, D" {8 @$ R6 aoutput axr1,+ \) f# A B5 w4 H" N" V3 H* K/ E w
assign mcasp_afsr = mcasp_afsx;( r& d) q* D& C( Y3 B0 b: [' q
assign mcasp_aclkr = mcasp_aclkx;( k, N8 p# r( C$ z' k! W
assign mcasp_ahclkr = mcasp_ahclkx;
) @& y; H+ q) y, ?% Uassign axr1 = axr0;
' w3 i- f/ P# D& {2 u v' P' I' n6 ~9 |& r/ O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 q% \- x- S% t: [* J: l- t! Y
static void McASPI2SConfigure(void)- \# T& P1 F6 c
{
! }$ D- I1 {- O( VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ]5 h4 P! i# ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 H8 f ]1 \+ p2 a. x+ \1 H dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 _8 z; a# M3 W: L# W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ l+ M% z0 {. N2 }" T8 k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' w1 d, \0 ~8 M2 ~4 D F4 E8 s2 e
MCASP_RX_MODE_DMA);) y Y3 r6 |! p5 H: X8 u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' f! W% ^$ X" J% }* V. }6 r' l f0 W5 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 |$ d2 v: z6 Y4 O, \7 l9 S0 v+ dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' j* r2 b$ e" x9 S/ ^ EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- V5 j, a; X6 ?3 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - v, A8 } c! |, o0 f) B [) `' p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 H% I% J1 f' N* i* m* i8 C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' L6 G- z2 j( q( s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 n. X& h5 u, i( ?* }4 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% Y% ^4 {6 H$ [0x00, 0xFF); /* configure the clock for transmitter *// V8 h1 O# j! [% k- a+ _/ Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 H# w# {! M+ H* ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & ^) K* w. K+ `9 P( N( O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! z- D: W6 Q o6 p0x00, 0xFF);
1 v" T# k" ~( Q. `' p/ H# n% y7 ?4 p L6 q" C0 K" t) K( x6 z
/* Enable synchronization of RX and TX sections */ 7 i2 I! u" d7 _6 a6 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% Q% B+ h6 Q# Z: o! d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; T. J/ d4 f/ ^0 O% G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 u8 z: M0 |; j9 K6 E** Set the serializers, Currently only one serializer is set as7 |9 r! J; s' ]0 F( v; _
** transmitter and one serializer as receiver./ w8 E* o7 b ~7 Q& O
*/ o( Z& x9 r% E9 G5 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, J8 B3 n/ V# Y. w9 m; KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: e8 T X- m9 s3 M3 ]6 I
** Configure the McASP pins
' f; X; r, j9 O, v# y( n, K* g9 h** Input - Frame Sync, Clock and Serializer Rx( j: X+ K0 a* ~
** Output - Serializer Tx is connected to the input of the codec
2 l# I, g! v7 b3 Q$ N! H i*/# Z+ F6 v% @6 w0 y* r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 G1 H8 c6 E6 n( B8 i8 n! Y2 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ g& \! L0 T+ ~9 u$ h7 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* ~+ f' v* I4 r' O2 k
| MCASP_PIN_ACLKX" ?# C# w. Q% P$ F8 h4 [
| MCASP_PIN_AHCLKX
2 o/ {5 ?% {9 G# d- c* D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. n% R$ ]. f& t1 o+ i. A$ YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 {) T' u/ \8 I, }( Z) i9 E| MCASP_TX_CLKFAIL
5 |9 ?; \, a G" X| MCASP_TX_SYNCERROR: ^1 r6 j2 q* w! v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ c! S# } K5 J/ e+ U| MCASP_RX_CLKFAIL
( H+ I' o0 u$ || MCASP_RX_SYNCERROR : G. N; Y z, K5 D+ ^
| MCASP_RX_OVERRUN);
6 L- u) y! b0 _} static void I2SDataTxRxActivate(void)
7 ?" {6 z, x2 H3 |{
4 G5 Q( j. M5 M$ H" h/* Start the clocks */
/ n: a, W* F s! }" t- OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# V! u+ T' c7 ?7 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! c* j) O d- o" B, q' REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, {1 X( T6 A+ ?' c1 D- r+ @$ @$ @
EDMA3_TRIG_MODE_EVENT);, _+ o6 P' A" O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 r2 f- D9 r$ {, D' }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' n' d- v" }0 \- x5 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 F9 T# K; Q" o- EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 p2 Z- u# A: E& g, B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" e# N N7 @2 Z9 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" _) s2 g* i9 a/ N6 z% _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% I7 |6 k' g, O- }' p
}
2 u4 Y% h) I9 Q5 _- K3 J' U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / R0 b6 ?: i1 i; ]9 C# @, |
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