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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 l) x1 z# d s6 U. ~input mcasp_ahclkx,. a5 N1 P+ z0 d5 |4 C% a7 N
input mcasp_aclkx,
6 Z! w, I7 t' f2 U% u+ {input axr0,7 t. V6 D) N- D6 Q# r
; Q7 A& S3 \2 o; g" u9 H& y
output mcasp_afsr,1 g a. e+ m8 w1 O) y
output mcasp_ahclkr,* V- y; b o# z! w: I
output mcasp_aclkr,! y3 i4 U4 _8 [- E
output axr1,3 y: x Q$ J# d8 I
assign mcasp_afsr = mcasp_afsx;! m, h+ T6 n: |( P7 P( U
assign mcasp_aclkr = mcasp_aclkx;
0 W# \5 v7 `! W/ \; {: aassign mcasp_ahclkr = mcasp_ahclkx;
% R& V: D, \+ C7 ^* {& \assign axr1 = axr0;
/ }& ^, z0 ^9 D! s1 @2 n
$ V" f& x, z4 q; Q( c1 d ?4 B& e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" o( Q6 C. o) E8 `8 W3 astatic void McASPI2SConfigure(void)8 I; Z; e- u; S6 b
{
" Y& k1 x d% Q Z3 J1 z9 }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 P- J$ e, u, y# d5 V$ c6 z; xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ q i5 s* p& kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ x6 h! E+ n7 R% |! |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* O* J0 n3 a1 o, ^, NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 ]$ q. z3 V1 `$ F# X
MCASP_RX_MODE_DMA);2 Z& O1 I- j" M7 k4 F
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- N# P1 S& a F0 d, V. z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 F/ _0 b% T( k% h! A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 m5 P, ^0 b: w1 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( y* ~+ }8 T" A' O% K. ^7 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* C0 ~/ H- C, q! c" o* C3 r& jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" W- Q0 [6 ?1 N8 m+ OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' `' C4 W# Y' e" `8 g" x6 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. H+ e" j" @2 x" g$ X7 ^& rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% h* Y& ]0 `$ \1 l6 |/ a: n' n0 u0x00, 0xFF); /* configure the clock for transmitter */7 {: F% P+ ]& K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. u- r% Y# z0 o& i$ EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, g. B; U# {" A2 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 {0 y) S9 `, a0 V( t5 [0x00, 0xFF);
! x4 Z) Q) X" U* `, ~1 w( I; ?6 H' j% _0 b: u& C
/* Enable synchronization of RX and TX sections */
1 D+ g3 q8 D+ F# \: B- e2 ^3 B/ UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 w, M( @' Z/ TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; I$ ?& f. X9 K1 W8 E4 Q& d; b' d2 S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% f p1 {: O+ Q# I& G** Set the serializers, Currently only one serializer is set as7 @. E- @7 I) ~# B8 O
** transmitter and one serializer as receiver.% k @5 a+ @+ U7 j+ M2 _
*/- f% ^2 y# Z% ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ t8 j! \+ g% f$ Z' d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" @1 h9 A+ v! o. ]0 T: d! ^5 G& T! O** Configure the McASP pins
) z- m- `- M7 h( N/ j** Input - Frame Sync, Clock and Serializer Rx4 a) Y4 |' G* b F
** Output - Serializer Tx is connected to the input of the codec ' ?' p, B" L- ]" d( O
*/
4 L. h6 n# A% z7 ?& j# i0 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' L" D. ^" R w. K4 ]. `3 ^9 h) g! ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' m G' e. ~# u$ }; {& C# aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 m* E7 q# J) j0 X+ C7 v! K8 [. Y0 e| MCASP_PIN_ACLKX6 i$ z( \& c" M9 E& Z. ~! J7 r
| MCASP_PIN_AHCLKX+ V! j$ f# D# a2 Z$ M' J. Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 ]* J) t8 a1 F% m! Y: R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 j. h4 S1 O2 G9 e7 ^| MCASP_TX_CLKFAIL ( D- I+ |+ y' V2 D3 V! A |+ e0 ^
| MCASP_TX_SYNCERROR
2 `3 R8 j. D Y( v, G' }8 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , B2 ]5 T. `; s6 m9 ^
| MCASP_RX_CLKFAIL$ U5 m9 P+ X! Z+ c% n( P: k: Y j
| MCASP_RX_SYNCERROR . f9 `& ^& ]' O* y. b4 H
| MCASP_RX_OVERRUN);3 F% I, M2 i" v, D2 q( R
} static void I2SDataTxRxActivate(void)
% a4 N0 q8 M) a8 }4 I0 a{6 I, Q( w1 G+ N0 ?, j
/* Start the clocks */
: V; w. m" o: H* M7 R% i! WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 `6 v M) y0 p( L( R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 c6 y6 \! ?& M8 V3 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 f7 e' P2 C% A) l2 }' h
EDMA3_TRIG_MODE_EVENT);
# ]. F+ H/ m( c, P0 G* C; vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 H! s0 R, y) G' u7 dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 x: ?0 e9 J5 \7 \2 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# f; f$ S$ w% i$ x7 C8 E6 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; [" {* ` T/ e( ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" i% x1 S, l7 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: p* H4 b. w; O) m: T1 l ?% u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" ^; r- D+ w2 q6 d" S5 G
}
/ Q( G- V) ~5 l1 \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' }, c* f$ k; {* I, ~) ~0 c& X" u
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