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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, z4 i% ]( p6 c5 b3 {- o# Xinput mcasp_ahclkx,1 Z' f8 v6 }; |( S$ s& ]
input mcasp_aclkx,
# c# b d5 |) m: G finput axr0,2 W: D% s! L, Y7 J# F6 t+ x7 n
# {/ `) \8 E$ Q! Q2 g
output mcasp_afsr,. b( ?5 P$ U8 p* L+ l* x- P8 U3 Z
output mcasp_ahclkr,
@. I2 K, K) a* z! Poutput mcasp_aclkr,- s( E, `7 D1 r$ E. ?; H" I
output axr1,
9 `1 i2 h+ v3 D$ W" F assign mcasp_afsr = mcasp_afsx;1 k# A3 V5 y, n# _
assign mcasp_aclkr = mcasp_aclkx;2 i8 J) V# p: o/ k- B6 }% p- l
assign mcasp_ahclkr = mcasp_ahclkx;
. \% h) D1 {# b& massign axr1 = axr0; 4 j" d( `6 T( U& E
: \0 U6 y8 I- W: H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' w# ]7 j3 A5 ?" }9 C$ @4 H9 T7 [, R
static void McASPI2SConfigure(void)
6 s( T. Y- b* E& V{6 ?! V/ u L) Q( w$ D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! r' d" z m1 F. \( u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; _3 {4 m+ v, ^9 e P' n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 W( c2 e3 K6 q! bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' D, R, n4 O+ Y9 z) IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( a/ l8 e7 a' `6 m# x
MCASP_RX_MODE_DMA);
/ b( b" t/ T# i, r$ b6 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ B0 T+ t* u& g4 b# e. |: p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 {/ N& D+ p* Y6 q! l& {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
h7 C0 v% \- K; g$ {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* ^4 ?- ^0 {, P: R1 h1 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. X" Y5 Q' T+ n/ xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! l" t& n9 M* S) F2 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. t" t1 E* j2 x3 GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 {$ K1 |7 B: W. D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" r: J. Q3 i4 P7 K6 W0x00, 0xFF); /* configure the clock for transmitter */- S5 g7 C# Q. k+ i* M0 ?/ o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
t( D8 y( O$ ~, O9 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' j! y+ A1 B* E& Q" @7 o. c! q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( T5 Z3 I7 j+ c0 P7 p f6 f0x00, 0xFF);2 U" E5 Z0 \( q3 `8 Q
: u, L# Q/ D+ ^; k9 I/* Enable synchronization of RX and TX sections */
! i: \) }$ b& @( q- F o& TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 h3 x5 B7 B8 k+ J6 ^) eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 d1 E5 R9 _% p! w1 ?8 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! y7 d! Y% M, g% {6 Q, @6 a) i2 V3 L
** Set the serializers, Currently only one serializer is set as7 Q5 a0 e, P# ]- b+ u7 N% R5 T X
** transmitter and one serializer as receiver.+ i% N$ c& `, p. t, Y
*/0 Z0 h4 h: }, I$ D& r3 W e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 m) [* k7 X5 ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# U5 w8 v; F* ]2 W2 Z
** Configure the McASP pins ' [; x6 P, T; C7 t% G
** Input - Frame Sync, Clock and Serializer Rx4 i7 [% l7 A( I$ A6 A
** Output - Serializer Tx is connected to the input of the codec
" _6 e/ v2 G8 ]% Z! a$ Y2 ^/ |*/
/ c! o% L, g/ A( r+ }! VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 a, g' E. a, m) t' G' s- LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 l8 h. w/ ~+ u/ }+ h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' Y( y' [* k2 h| MCASP_PIN_ACLKX
) @5 P/ k: z- E' v7 t4 G| MCASP_PIN_AHCLKX
: B1 Q5 I0 ~& Z/ Y @& [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ^, J' [1 e! _' }8 f0 q2 C2 X zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % n% u) {# U0 \) P( o! E* g1 ^( L
| MCASP_TX_CLKFAIL ' r' z$ ]3 u2 J. {7 e
| MCASP_TX_SYNCERROR- }$ m3 g. ~. l: A$ u! H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 A4 E% Z# F# p
| MCASP_RX_CLKFAIL% d" V9 G- n1 ~- D
| MCASP_RX_SYNCERROR # \) ~ ]* r G6 d1 K! v% ^
| MCASP_RX_OVERRUN);
& I& @% i# _+ M1 ^} static void I2SDataTxRxActivate(void)
- Y; O$ \% {( K& w* }{6 X8 c% c; x, H) `; X
/* Start the clocks */
( a N% H6 F9 v Q$ _$ T/ ]' Q) H. P( W% sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, D# f; @% `* e% @1 k; J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ X+ m# G9 l8 s8 y Z9 q/ j+ OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, P8 @6 r) T2 r2 Q, D; A/ P; N: OEDMA3_TRIG_MODE_EVENT);) X% t8 I' Z3 j; D9 Y3 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 ~( t( l/ y* X1 O, w. S) c; k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: p( _% v, k1 x' N7 I8 r0 P) q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" c9 r1 o( |4 o. |( U0 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! X# p1 j4 A# g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
S9 G/ K. p( \, L: J1 q3 l. OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 K4 N5 e9 i1 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" W7 ]4 y2 g. M) V1 s
} 9 Q) I. A" J2 ^" L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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