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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 Q% u& e) C, T. v- r1 xinput mcasp_ahclkx,$ u2 S1 l9 [1 \3 d* C3 f/ j
input mcasp_aclkx,
; e' j, i8 T, u/ m9 x: Y, I) Qinput axr0,
& \/ Y K+ K4 z3 t6 }) E9 j a+ R( g3 }' S
output mcasp_afsr,
/ T1 p+ P* R" o0 G# X1 z, i* w, [6 houtput mcasp_ahclkr,
* ~' z8 ^8 K8 z9 S! {& Y2 ?7 {output mcasp_aclkr,+ w1 G6 i3 G2 j5 s) {- g
output axr1,, G; Y4 _4 q X) D2 A+ \
assign mcasp_afsr = mcasp_afsx;
% ?; E4 Z( t0 q0 P/ t2 Tassign mcasp_aclkr = mcasp_aclkx;, _' M) m, E7 V$ H! I9 v+ B! N
assign mcasp_ahclkr = mcasp_ahclkx;
$ ]. e Z8 g3 \! v: ?assign axr1 = axr0; t3 n8 d9 l. B
$ s: B8 }" d6 ^# a% U% ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# @) p# _' V5 o. j# D" @, J2 Rstatic void McASPI2SConfigure(void)
9 N/ P0 t, M: L$ T* J; r& ?6 U{
m% Q" q+ c' P/ S0 pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ^! i5 o8 h! ]/ B" S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! n) K& r ~/ g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. z. g" [$ M4 a0 f' A" X- J$ RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 W8 U; o4 B e3 x7 u. b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 y- F' {# N9 l) q! {( B
MCASP_RX_MODE_DMA);
* s! U& F# h) `# x5 {0 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; i# G. M! V' C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) q U' B6 [. Z H# C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 c1 j9 g9 H2 ?) iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. ^& O8 F3 j1 BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . a' p- H5 x. P/ M& q0 A& A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 V7 ~7 i/ b' X& r8 ~3 G. vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 n( m% E$ B* Y% ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 ]# m; d0 v3 p, z0 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ a! r5 L0 p0 ~+ J5 |
0x00, 0xFF); /* configure the clock for transmitter */
2 {+ J* t- ~& e* J9 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 x: a& Y1 j; m# ~% F) {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; z6 J* _" d7 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 V7 ]! K% s5 B8 m
0x00, 0xFF);2 ?! H& \% H! S* j4 W
/ g) U2 b$ h1 h9 \: j/* Enable synchronization of RX and TX sections */
3 t5 t6 Q! ]0 }" g- B, \7 T/ |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 H; g; H2 b5 A9 U9 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* D& @$ _9 _/ h: f: X, eMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& R5 M8 A4 k' k F** Set the serializers, Currently only one serializer is set as
* _8 d5 I% j* d! H** transmitter and one serializer as receiver.
: F. d1 S% P* x" m. P' o3 [*/
% f. V' B, y+ |3 Z3 g7 P# wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 ]9 L; t. r( _1 x/ P: ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, @8 K! v: d. m& F2 W
** Configure the McASP pins
. _/ c# ^+ r+ {1 X5 a, g; Q$ ^# n. @* A0 ~** Input - Frame Sync, Clock and Serializer Rx) Z1 \6 b7 k" v
** Output - Serializer Tx is connected to the input of the codec
/ s: X: K( q0 a4 f*/+ k0 T* `/ h% l$ a ]7 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% O$ Z1 L3 ?1 L. x, H) NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 M3 B2 _, y* m6 Q' \4 s6 Y$ HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' h& ^) V5 t/ o% n8 r6 o! u. H| MCASP_PIN_ACLKX; r9 \5 M. k. L1 m' \
| MCASP_PIN_AHCLKX
& o) l, g# H* a# R) {% \( i0 z, G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 _- U7 P/ e1 h, D3 K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . W+ z) H) S+ q* m$ T; O
| MCASP_TX_CLKFAIL 8 [3 m: d& d9 D( @0 ^7 R
| MCASP_TX_SYNCERROR
7 c# f2 K' b* V0 Z. _% L* `7 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' Z+ i* N. C2 J# O' _$ V
| MCASP_RX_CLKFAIL+ I( t5 g; m* C% c+ e
| MCASP_RX_SYNCERROR
6 @% `* `. g. Z" d7 S# {9 `| MCASP_RX_OVERRUN);
) C% j/ B0 a, v6 V! P; p) Z6 M} static void I2SDataTxRxActivate(void)
/ d* g% S) [+ P. ?$ |9 Q0 G- @" _{9 ~# E6 _, f" K5 z
/* Start the clocks */4 J: [4 l" o* }! X# S( ^) a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. A- w; o' e* l6 s1 @/ cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! N8 Y. J7 V0 C2 `4 U% ?+ W* E8 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( Y; G$ V8 r% _, \EDMA3_TRIG_MODE_EVENT);' |8 @8 K! ]8 U) |7 {% k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. Y7 _1 Q) J( Z) x# m4 E( iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 a7 j- |1 ]5 K$ D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- w& i" T9 f5 N# ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 ~4 u, f2 t2 U' v7 Y$ T# O' [3 D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 |( i2 a, Y1 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! [2 y7 g0 p" b* XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# e5 x( S6 T( _3 q- K} ; `6 M" E5 G6 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % i: z/ h* o: i5 H% g
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