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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 _+ X N. S5 z, i/ a8 T, U8 ?/ D- y
input mcasp_ahclkx,
* B. S0 W+ r l% J" zinput mcasp_aclkx,
& c: h1 Q: I+ \input axr0,3 o _1 L# B- R* T
4 r# e2 \: a" u. t) J% _
output mcasp_afsr,
" v$ Y. j; r" t- Goutput mcasp_ahclkr,
5 F5 A( i6 N coutput mcasp_aclkr,& r2 p8 Q- E9 c. b# s
output axr1,, x& a7 v) W, g
assign mcasp_afsr = mcasp_afsx;$ [: ~% p4 {- P" H
assign mcasp_aclkr = mcasp_aclkx;% {1 ^6 @6 _6 B; `, j$ u
assign mcasp_ahclkr = mcasp_ahclkx;
6 e3 n( q% ^! r' w% I# kassign axr1 = axr0;
$ c/ K) ]6 Y" D5 n: P* I- _. i) y: U2 W4 D( M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, a( m, I h& Ustatic void McASPI2SConfigure(void)
/ @+ U W0 w4 }* ^; G{6 |. b# X3 T* \' f! t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 }9 y- }0 H: F! q5 B% pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ A0 C1 L- L. p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ~# D9 d6 \1 B$ r, O2 R$ L5 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" z. h) X; h( v$ P: D" jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 \3 K1 }' [6 U/ P ~! K3 H( `% z/ {MCASP_RX_MODE_DMA);9 Z* Z8 j3 a, A2 k9 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& q1 C, K$ @8 P6 s/ ]* b$ pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 N0 s' x0 F, Z0 ?1 H" Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 J! T( U/ A* kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% J8 g$ {% e2 u) x) B) Z/ e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 J! l* B. V) D0 c7 U, F$ F2 v! u) lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; ]+ V/ R) |1 l/ |- c2 Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 ^- ]* E3 J1 Q; ^( T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 r* `( _1 V% A" M% i9 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 Z$ k1 C: B) l0x00, 0xFF); /* configure the clock for transmitter */9 R1 l J1 g R' Q8 Z0 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 Q m" _4 `, ~9 H UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 d( u7 h+ j8 O8 ]+ X+ W2 P* S+ L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. g- \* }7 Z' ~- t0x00, 0xFF);7 F: q! K( \" X6 w
, g2 e1 e' L3 W0 A/* Enable synchronization of RX and TX sections */ - E6 J7 ?7 G. p" x1 ?* }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- }$ Z0 V6 O/ N$ M: p- N7 W& V6 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 C) V# \7 W J' T4 R; p( m4 J% T K& FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 z8 W, }1 {' f1 _: [
** Set the serializers, Currently only one serializer is set as
* x4 V% |5 v; w5 c2 r2 a+ B* E c- t** transmitter and one serializer as receiver.: }% N9 s& I" z5 e
*/" [) d( ?' h: O- @% O* Q# {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
z: _2 v0 F9 L4 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ x7 t/ V3 {) x5 a j** Configure the McASP pins
3 K- w6 M% l% T( d3 B' _** Input - Frame Sync, Clock and Serializer Rx$ Y" W6 U& r1 f2 B$ ^3 j
** Output - Serializer Tx is connected to the input of the codec
! Y0 q" a! V d*/
: ]+ o1 |5 |/ q: kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 H! p4 K5 S2 U! v% c, uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" n2 w, `0 {. dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- h9 L4 F& n" ^( K) t1 T3 i- T' l| MCASP_PIN_ACLKX
$ c8 y" c2 p3 w! P1 o) ?. x: S c| MCASP_PIN_AHCLKX
# S& t* a9 {3 M: _9 A* j0 ]( ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, x: A: ?2 v8 j- D4 X& OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' n" r& e9 p- n) r" O1 o
| MCASP_TX_CLKFAIL
# A1 s! U4 J/ @| MCASP_TX_SYNCERROR/ \% {/ l# S3 @, s/ p2 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( R2 C e' R4 t# }| MCASP_RX_CLKFAIL f. e+ d0 E# e+ }* t5 s- r7 d' s
| MCASP_RX_SYNCERROR # F& ]& l7 ?! J% C; v/ b4 P* J
| MCASP_RX_OVERRUN);7 s. e( Q7 A ?& h: A
} static void I2SDataTxRxActivate(void)! p. D4 X( m1 c) U1 T: g% O
{# ^$ ^* Q5 b5 y0 T$ |1 F
/* Start the clocks */
( w# |1 V0 Z) X! M; lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- ?6 E% V8 W0 {* p4 r* [) j$ GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 ?# w' Z a2 j1 e2 P4 l8 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% K! i9 E! Y. L- Z. z+ |" o6 U* M
EDMA3_TRIG_MODE_EVENT);4 M0 V. F0 `7 }/ k( z2 n+ b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 w8 K! b8 [8 ?) G2 bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) F7 M. k& b0 R+ zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' a& w. ?8 _- V2 F' K& N3 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. G1 g( T" _( p5 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ \5 {9 |' U/ [( r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* t) C1 l# j8 f& E `3 K/ N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& S/ M t0 t1 e5 V ]
} 4 j* A! l" r5 L7 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * T1 ~6 h9 `" @, A' Y$ H- @
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