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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 P/ s- N6 L( N! M0 ~. a! J. m( hinput mcasp_ahclkx,
1 c- \6 a0 Y8 ]) I( yinput mcasp_aclkx,( u' m, Q8 N; p/ J
input axr0,
7 r: {$ d1 r8 A- D6 i* ?" _$ H# p; E. x' x$ y1 H
output mcasp_afsr,
) F" I: O/ ^$ ]5 g1 j: z& W, U' doutput mcasp_ahclkr," Y) Z' r b8 Y) L
output mcasp_aclkr," `% ? J5 I9 u* `* X
output axr1,1 |5 F, B2 E# J( v5 e( K: A
assign mcasp_afsr = mcasp_afsx;
0 G: e' J" k# Iassign mcasp_aclkr = mcasp_aclkx;& H3 ^* o8 @7 m. [! s1 `
assign mcasp_ahclkr = mcasp_ahclkx;
& @) m- m6 S/ Z( ^) k6 _1 i# yassign axr1 = axr0; ; J, x) ~5 E& n$ F& Z
2 J: Q Z8 G% p) }8 U' \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 w& }0 R* d0 ^3 b/ L1 V: k5 Astatic void McASPI2SConfigure(void)$ Y: Y; w8 v$ r) C' X4 L8 @$ P
{' H9 P: v. {( I) {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 g0 @: s% b5 H% A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& X& r5 q- O" _7 H7 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& w; _( M$ H$ I8 n# b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 n4 c& u9 S! r& J3 w5 n4 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 e' y! [. i: P) s6 U
MCASP_RX_MODE_DMA);
6 N2 h# ^8 h" _" @/ A7 L3 cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, X9 }( B4 K/ Z# J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 |3 \. F3 k6 R* k5 j: rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 L$ N2 w. ^8 I/ j' z) A* O- L: G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; r- a3 \2 F4 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - v$ y5 t4 ^/ O6 A3 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" S6 V4 F. n- R+ X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" n5 I; J8 ?8 [. W; e2 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 q4 {# Z4 J) \4 y. L$ n. P* `; z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% @8 T, N; e4 n9 \; s
0x00, 0xFF); /* configure the clock for transmitter */! s& k& X! @3 w* N; _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( Z& ]4 { Z, j4 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* w2 n& b# f6 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 e- I6 N/ r4 `' U" ^, V0x00, 0xFF);3 B5 N$ i1 N( u# C3 W- V% w
8 c: \# \. ~( @2 \5 p) F [! E/* Enable synchronization of RX and TX sections */
! |+ u# [, L; N j5 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 {+ f$ R3 \0 q7 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, a* L, Y( ^( ]5 u# \% E2 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, x* r: g; i& i& I U: z** Set the serializers, Currently only one serializer is set as9 E8 v( `* G- F1 C& `* I2 J
** transmitter and one serializer as receiver.5 H+ d( W1 J; s* r) q( B
*/# D b0 K4 X' c+ m- l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' `) k" I7 G* B7 GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 Y- p7 {1 ^$ D& u& I4 Z
** Configure the McASP pins 9 [/ d t! B) x( |: [* w2 X! K
** Input - Frame Sync, Clock and Serializer Rx
6 V, k- Y0 ?. t/ x** Output - Serializer Tx is connected to the input of the codec
8 f+ H! w- {1 }& G- O*/' K2 C: V; F/ X/ H( X: Z* b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 p( F" e6 J. n/ y2 K1 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 d% U# A! d" N7 q/ a5 \8 U0 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) f( S" e( x* T* E8 @
| MCASP_PIN_ACLKX
- [0 w7 O" z: k" p6 F| MCASP_PIN_AHCLKX
5 t2 d/ P+ R2 Y$ D7 W ^2 J3 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
{. e( o' U. o9 h. B% |$ fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- g. N* h0 U3 w* A4 p4 O| MCASP_TX_CLKFAIL
7 O" ^6 [3 a) p. z| MCASP_TX_SYNCERROR
& ]: ?& `. X M; i( _/ {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : o2 y; N8 U4 k$ u: d( g }1 `3 u
| MCASP_RX_CLKFAIL- j k; `* W0 |/ e I
| MCASP_RX_SYNCERROR $ m" M3 Q1 l+ g0 G# Y5 c/ o8 t
| MCASP_RX_OVERRUN);% }3 q7 Z+ W" \, {; O
} static void I2SDataTxRxActivate(void)9 \. Q; R- Y+ j$ d' u7 ~9 `* { c
{9 F- B! f. A. {( J- K
/* Start the clocks */
% f4 N7 Y8 @9 s2 I7 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 X; V: h" ]6 ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 o" H. X6 r' D$ L' TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& ^$ m N( p& k* r) X2 X4 y& v TEDMA3_TRIG_MODE_EVENT);
- J) _5 `4 n o! w& P. ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # Y) S5 y+ ]0 m8 t, D+ {+ e7 }7 Y; ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 e6 u! O4 B1 L6 k- K9 |! o" v- v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 O0 f+ J* H ~% y4 A& w Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 M, M/ T8 ]' ]: w8 d/ q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; q2 u Z8 ~7 z2 y- |0 [5 ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ d+ u1 t" t0 p: l7 _' i1 j3 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! j9 I* L; H; ~
} # }( `. W* ]. q) I( b' u6 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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