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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! K/ B1 k* j2 l$ H2 S I4 t, x0 `- W
input mcasp_ahclkx,6 c. Y6 o, ~3 ^& k
input mcasp_aclkx,& [, B+ h) B6 _# D8 C- o1 N
input axr0,
) B( I- M6 G! x1 Y. w/ X7 T& n K7 F/ V4 y& B5 k4 q
output mcasp_afsr,
: j8 T0 m& Y* e' houtput mcasp_ahclkr,
' H: Q' d/ e# e. goutput mcasp_aclkr,
0 }; E4 D7 Q! y/ v2 P7 o6 B6 }output axr1,. G6 V2 W9 Q- u0 I+ r
assign mcasp_afsr = mcasp_afsx;! F0 L& t" `9 g3 m
assign mcasp_aclkr = mcasp_aclkx;5 }2 D5 Y) m, U2 a9 H7 T- P, J
assign mcasp_ahclkr = mcasp_ahclkx;% P' J5 F3 q$ B }. A4 t" p8 m& P2 O
assign axr1 = axr0; % O; J" @0 L; |- t
/ j% g, {8 R! @' K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 u8 m- t% [$ y9 n6 |& _static void McASPI2SConfigure(void)
1 `8 f6 a6 E* w9 \{
( b5 L) `. I/ q0 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 N/ T6 Q# A' cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" ^9 G: q2 O0 H: f2 V; x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 ~. K" {) V5 b& n- [) {3 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 x9 Z2 C- |# F3 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; A3 S6 u* J( ^9 XMCASP_RX_MODE_DMA);4 r+ O& l8 o3 R2 h$ _1 B. d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" U* O/ m( U- U1 e1 I3 p% fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 `# F, F3 o: w- P0 R7 v4 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" E; Z9 j' \2 u1 u9 D3 ~/ O, ~' pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 @9 |' V; m F1 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( \ j1 {, i! g( }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% L9 u8 f ^& I. Z' ~. |8 l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# \4 S. T" }* S, g$ h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& H8 m7 T, A+ e' fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ Z0 n) F' p. V( d5 y$ U
0x00, 0xFF); /* configure the clock for transmitter */
- V- H4 {9 k4 D7 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ]" g' L6 S2 p/ \/ ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" M% g- J% d8 x' q* y: h* ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 ~; f0 w) p5 b* c4 F2 v8 ~0x00, 0xFF);# h6 U# N) _2 ]& `" `' A9 [9 c" }
1 K% d( t/ w* |6 l, n0 C5 O G/* Enable synchronization of RX and TX sections */ - U3 A# h2 v* T) `& Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 Q0 x/ t3 H. }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 k6 O, W: i5 Z3 E f8 W4 [; }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 B2 s0 e5 z& b) I** Set the serializers, Currently only one serializer is set as( G7 U3 R6 u& C
** transmitter and one serializer as receiver.
$ K6 ^$ U8 P$ Y. k! b4 s+ D* V*/2 x5 n/ I% e$ u1 I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; H9 T( f& \2 V' d" r/ E; ?7 P) X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 W2 g ]8 U- h7 C b% `
** Configure the McASP pins ! w* u, n5 M& S5 D
** Input - Frame Sync, Clock and Serializer Rx% A# N' O" R6 N7 {! h2 S3 e
** Output - Serializer Tx is connected to the input of the codec
' n3 {" w5 H2 `*/
& C( m& P' S5 f3 t! E' y7 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# h A! H3 {5 k& Y) ^5 DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: Q8 Y# I9 A3 j) W9 X0 }7 YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 T, I. T1 o; k) j6 V- s1 H
| MCASP_PIN_ACLKX
6 M) w4 m% V8 s& T7 s* l* n| MCASP_PIN_AHCLKX$ ^) e8 T6 T6 f1 A, i L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 A2 }4 ~3 U1 y* J8 y0 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + i( K9 u5 v2 d7 F$ Y5 h: k
| MCASP_TX_CLKFAIL
L6 m6 y7 Y# G* p. t9 d| MCASP_TX_SYNCERROR3 p7 q! Y. _& L+ k) J- ]1 I8 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- `: a$ X! u, c% n! ?" K( V| MCASP_RX_CLKFAIL2 A$ o8 Y& K/ @5 Q- G
| MCASP_RX_SYNCERROR
0 H7 q; w) V# a6 O3 q| MCASP_RX_OVERRUN);
; h, }# u% Y+ j5 {: {/ [5 b2 |} static void I2SDataTxRxActivate(void)
2 @# ?2 R& h6 y3 D% c7 {" ?{. x* B* ]6 G) |
/* Start the clocks */
8 J) K3 O) q. ?7 X; p7 U ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 \1 n& Z5 a3 ]8 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 z* v/ Z5 v8 _) M9 s# s3 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 X6 |4 w; p9 C% z6 A
EDMA3_TRIG_MODE_EVENT);
$ J( d9 ^2 C2 v5 {6 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ I2 }1 W, p6 Z2 b+ ~% }& `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 W* {- z- W' v7 U( E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" O* B) L+ b8 f( l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 F5 A8 A, \4 h" n- D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ J. \$ R* M# b3 V7 T; ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ \3 S7 V' f5 m( Y" k$ I! _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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9 Z y3 W+ w, |; f- J- I! O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 u: u# S& e |
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