我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! F7 Y+ W: K& m7 d* q! [
input mcasp_ahclkx,
* x/ }9 f' }! D* i& Finput mcasp_aclkx,
- O# J2 G4 Z& n% d8 R0 H8 S3 Kinput axr0,
( ]6 q& C [" d# M1 r" X1 C F4 e! B/ F
output mcasp_afsr,0 t8 M: P, J1 F/ k3 A, i
output mcasp_ahclkr,) k) k1 `3 J2 A) a) m |* q* q
output mcasp_aclkr,& X+ S' F# l. h& Y9 S
output axr1,
! E4 _5 D7 `& K0 _' O, K) | assign mcasp_afsr = mcasp_afsx;
( F7 o- ]" e/ Kassign mcasp_aclkr = mcasp_aclkx;
* u% N% n- I+ D6 V$ R: Rassign mcasp_ahclkr = mcasp_ahclkx;
/ ~: s0 C& O: I. @3 i1 L2 b, [) Vassign axr1 = axr0;
3 k2 i. a; \/ \% U4 ` W- [2 t6 x% D8 d2 E7 {+ B$ N! Q& j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# p3 T; {' H1 h& g o9 f, C$ M. r, Dstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS); ]2 \, o1 M" k( c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, q3 ?, Y, ?8 f6 }: {- O) j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ i; R& v+ _6 e" ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 G9 J# y7 K7 h: R9 K9 E: FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- r$ i# f" l* e3 v
MCASP_RX_MODE_DMA); M- [; f- B# s) q& Y, C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
\1 _0 G" o% DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, t U8 W! J) V8 [4 ~7 t, L% k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 j6 r7 v I6 @$ s/ iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) H7 D- T. H' {( p( }9 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, |% `* G2 g) U, @* W; DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; f% [6 P G, @% O$ ^; ?" f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; t) A8 p% f' f3 k% ]2 ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 K8 S& N8 N0 |/ a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! k& Q) y3 E" c3 Z9 I. Y" i1 w" H
0x00, 0xFF); /* configure the clock for transmitter */& c6 p# a1 q& q) @+ ?. ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 N" x( ]# ~3 m# y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 ~: N3 [) k, v- w* xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, y4 }7 f* O5 @
0x00, 0xFF);0 G/ [, L6 e9 Q- h- M
) I$ P* I+ W+ E$ w/* Enable synchronization of RX and TX sections */ 7 m9 C7 y8 F& D9 n! \4 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ ]) o5 M3 s6 E( w. {$ ^/ p$ h9 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ T; E% _& d r2 z& \: Y! T, ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- L7 s, r2 W2 P$ S( D* o$ U* r** Set the serializers, Currently only one serializer is set as b' J1 m9 G* ]7 T' h
** transmitter and one serializer as receiver.
4 o' z6 d3 q6 |* B0 k*/
3 b8 Y1 Y9 T& Q/ ^9 ?' }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; f) [, L( \' l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; {+ Z2 E; M& ?4 p7 Z8 b! I, L
** Configure the McASP pins 0 x% V; `7 o6 S0 R9 u" ?7 }
** Input - Frame Sync, Clock and Serializer Rx
4 b x1 |: z' I3 j! v( n** Output - Serializer Tx is connected to the input of the codec
4 p* T+ o6 V! R*/
) o4 t* ?6 j J- N4 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: y: h4 J. }( I+ b( g: W; i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 y0 D( u7 Y% S0 ^ `$ H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; X) H+ t* ~# K; q
| MCASP_PIN_ACLKX f( O; j: W0 g3 U% u
| MCASP_PIN_AHCLKX) N1 b2 g1 m3 E# G, {, s" _$ K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 E6 ^7 _( T8 N1 Y3 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! r; I5 _8 F) \( [4 k/ g5 s| MCASP_TX_CLKFAIL
k/ b2 T, S( R# h| MCASP_TX_SYNCERROR4 X# N( [+ G- i1 w( u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ O* f: C# k, S* y) W& s| MCASP_RX_CLKFAIL9 U) g8 J- j1 c8 d5 F
| MCASP_RX_SYNCERROR : ` C& q+ E5 O8 p4 M s1 x2 L
| MCASP_RX_OVERRUN);
4 I- x' I4 F1 a r: d0 B} static void I2SDataTxRxActivate(void)
3 b7 i. B$ V" n# L{5 V1 @ H: l1 Q: n8 e
/* Start the clocks */: b9 j+ a7 E' s& q s0 b. r+ m+ Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 O2 v' Z" h- p5 P) HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
c% X3 C7 a$ Z6 J: _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& Y# p- H4 i3 e. J" n
EDMA3_TRIG_MODE_EVENT);0 ~1 L; f2 x: }4 A. J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 Q+ X, N$ u& f7 g5 W5 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 A6 w9 T6 v2 f' Q+ y0 C7 n6 {# S9 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 ` G8 r# C2 x; X% E0 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 o6 z% [) Y2 Z9 s P V! xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 A) y$ U5 }7 m# l& K. ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ~* D4 M" \0 X) m2 L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& `. a$ w8 W; J9 ]} . L* g4 h3 M/ M) F6 [7 i+ X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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