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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' H1 o; o$ w0 R- Y$ E9 h! m+ H$ ~
input mcasp_ahclkx,
) q# W3 A+ }4 J- jinput mcasp_aclkx,
; } [% N1 N/ @& m0 Y$ K4 cinput axr0,, u3 a$ X- h9 ^. \. I' H# F6 @
/ j! g2 v( e# b8 Y% ^5 I
output mcasp_afsr,. V' y D7 R' d, M
output mcasp_ahclkr,3 Y7 @) U2 R. p. }1 l! E
output mcasp_aclkr,5 N7 z- o* K; M1 m
output axr1,# _6 g- M( f$ y" }9 N
assign mcasp_afsr = mcasp_afsx;) |8 l. Q7 m. B
assign mcasp_aclkr = mcasp_aclkx;
% Z+ P' ~. ]- r/ u' dassign mcasp_ahclkr = mcasp_ahclkx;
3 W9 u7 n8 W+ F. p& t5 e+ oassign axr1 = axr0;
% O. x) a5 c7 ]' A+ i& U' \ X$ b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( r2 i& }( h+ r
static void McASPI2SConfigure(void)
: m6 J# E/ A- _4 _. T" k{
! J( \ T# ~( s- B+ UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# t9 m4 a4 s% z8 q3 N& H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! I; P0 t. ]9 H2 a4 l+ [1 E! S5 u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. N$ s0 P+ i9 `+ J) }5 z, [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
@# o& P4 U: O, iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, O* ]+ ~" M! ` s$ ^$ {7 {/ u8 ^
MCASP_RX_MODE_DMA);
5 F/ c" U, D* T" ?2 o4 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ @- W3 G6 k7 @1 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: w, ]8 s: U: ^3 D" ~3 b; @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 u; d! K: [" `6 n. mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* L8 Y3 j- J4 g- u+ S |! OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & J+ U) ^# U7 h- ~3 {/ x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% ~$ x2 m3 q7 G3 M t9 g" eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* B$ O% b$ p6 k8 x7 [8 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 D1 X' K; G+ ~1 J, e. fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! |( p- M5 R0 u7 u0 f* L0x00, 0xFF); /* configure the clock for transmitter */
' _6 a! Y. l2 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, D) j! i' K R' [0 @ j c, s$ J4 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) g6 E3 O; y" ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ j' z6 D& o# o, Z( D, a3 D$ d
0x00, 0xFF);4 z" R e5 [4 |5 _, y1 m
6 \9 k F8 s; H1 A/ Q3 i/* Enable synchronization of RX and TX sections */ / X9 m) B4 A8 ?$ E. y! p/ c$ {/ A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 C2 L( M7 n/ F1 ?. @; z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; G8 }5 P7 i9 b$ _" JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 l9 ] `! \7 B, o* X, \' _1 T. w
** Set the serializers, Currently only one serializer is set as: B" L( H2 K& P' A
** transmitter and one serializer as receiver.
- u6 D6 D7 ^& A2 A) w5 N*/; W g0 o; D! K5 ^$ b7 l# }1 @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' N( Y: e O) B( I2 U( CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 R1 S& l: J5 Y: Y, N** Configure the McASP pins 5 t3 M, \" z6 _. U* t8 P' z
** Input - Frame Sync, Clock and Serializer Rx
" Z, Y1 e# e! m/ z9 K** Output - Serializer Tx is connected to the input of the codec
% P) S- } B) ]4 H; }*/
, k& C- s" c% {! eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 B o- s3 L' a' j( S T8 A7 B6 K1 ?/ }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, U/ J( i* k* FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 _' ^$ I& L' W- V2 u
| MCASP_PIN_ACLKX+ `: x& ?# m' y, r8 |7 A
| MCASP_PIN_AHCLKX* [: Y* a1 _* Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* c- r8 D: n# P1 s% Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" K' o# x5 Z0 Z4 u- C, M| MCASP_TX_CLKFAIL : f- P& L$ D6 _* s( J
| MCASP_TX_SYNCERROR. A {0 Q. ^& Y6 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , D4 b( Q0 p; B) N, e
| MCASP_RX_CLKFAIL0 U) r- k3 N0 @8 u8 Y u
| MCASP_RX_SYNCERROR
2 P3 v7 P3 K! F( v9 E( y0 O| MCASP_RX_OVERRUN);
/ d: J2 ^: \( m. E% k E) j} static void I2SDataTxRxActivate(void)4 `/ C2 M; ?- e
{
0 M5 \9 Z% _3 |; Z8 q& U/* Start the clocks */
. P3 S% O7 ^" f( [, t- RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 t$ Q) o- B8 C! U% Y+ J7 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, c1 a& u) A& x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
P, {5 Y& X( @* C9 f f LEDMA3_TRIG_MODE_EVENT);% l/ ]+ h* o7 q$ U, x) ?: G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( P8 u/ a8 }( ^& P# T" O0 A. [' o( v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; V) s2 E5 j _# K8 ~3 N- B; w+ P/ M( ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 J2 ~' m6 f" \/ ?/ p# _2 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" J3 `5 W) \ M9 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 E) }3 X8 q; W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 O- }2 E! j" E1 M" y5 N- P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ G( J, q4 P# v1 P/ G8 v}
9 l$ A& C. ?- Y; V1 W, P1 ]: r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( i; o8 N# \ r) I6 E
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