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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 q! e6 U) U' D) Z9 _input mcasp_ahclkx,
3 n0 {5 H, r) {input mcasp_aclkx,
2 l/ r0 P& C4 \ t2 ~; c0 Dinput axr0,
4 ~2 \& e2 h$ B: E# ~/ a; P `6 y* m3 z" e% e
output mcasp_afsr,8 o0 h" K; M# Q# [! `2 m) S
output mcasp_ahclkr,4 F& Z0 o+ d, p( O& h, Y
output mcasp_aclkr,
# @) f5 P! B, Soutput axr1,/ Q- t/ E( |( S' m- h1 E. v
assign mcasp_afsr = mcasp_afsx;* L7 s8 \! }: `2 P
assign mcasp_aclkr = mcasp_aclkx;
& J# @2 b% c: D0 Dassign mcasp_ahclkr = mcasp_ahclkx;
0 R% j7 X- Q3 e, t; p4 eassign axr1 = axr0;
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" V1 y* E( ?2 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 ]5 V! D# E) \6 p
static void McASPI2SConfigure(void)
3 j) m/ q( s1 s; h{* `: @& F; O# q* h# G6 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 v+ h8 f; S% H- s% N9 f8 V; c# B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 x" a2 [0 h: D/ n4 t% R+ }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 X3 y0 j5 b7 I& i6 o5 R, J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% j" f8 p; M6 w- `. B5 N! BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 D( k) s8 }% D1 a/ K# |$ bMCASP_RX_MODE_DMA);) \$ J2 f4 k5 k) X* m2 z1 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! y0 X9 `' j# A1 @8 b9 FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# H* Y$ C: R# G0 f" y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( S/ v4 y7 _- Z- c8 T& ?2 w( f0 ]7 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ p0 f( p+ J$ A$ d( U9 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 c1 \) Z3 @7 A: Z& Y$ c* Z5 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: f2 @" p- a- W$ d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ s7 W" r" e6 _0 H7 O4 \+ @3 \$ ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 P, A7 e$ O5 X$ lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; ?7 e5 I) k9 f) `0x00, 0xFF); /* configure the clock for transmitter */$ V/ r4 r+ p. U! Q8 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); A! t' \0 f( d/ G5 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " M; F0 P4 p8 b, d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; @ l8 k% L4 f" I# z2 U. D
0x00, 0xFF);
: L7 a& X1 ?0 j2 w# l! g9 t/ Z
/ ]. e" f: k( `% b/* Enable synchronization of RX and TX sections */ 3 B6 P4 u, W9 _# L4 A0 G" P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* r4 _5 H$ E8 { Z5 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 c' M, t0 Y' @; |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 {% y' y4 { n
** Set the serializers, Currently only one serializer is set as
- [3 [3 D3 E2 |** transmitter and one serializer as receiver.* \% t h+ |: f _+ F
*/( e' V! b, q% ~' d$ w! H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 k2 X# r/ ] ^: A2 W5 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. f7 r9 }) X8 v8 w# L
** Configure the McASP pins
) X8 ?" d, [6 a( ~8 u- ~** Input - Frame Sync, Clock and Serializer Rx: |( ^. g/ w+ t* E9 \ N
** Output - Serializer Tx is connected to the input of the codec
# ?% ~! D6 ]2 b+ W' z7 d1 c9 C*/
! s% k3 V, f' _: {0 p' a& MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 }& f4 Z0 F) L" U3 V. A4 m$ @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' Q1 e F: }! R0 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& K. C8 }% f$ z) b! y+ O
| MCASP_PIN_ACLKX
3 O3 J- Q& i( i; c }7 j$ c$ l0 }| MCASP_PIN_AHCLKX# i1 ^9 `* F3 v9 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; G# l0 A2 _9 L# p5 ~# \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ g' o; y: v. a
| MCASP_TX_CLKFAIL / T- l$ d8 y9 |4 [8 G x2 T! ]
| MCASP_TX_SYNCERROR
; P" W& ~0 P( H9 @) N; i" q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 q' G+ h2 x8 S, d: D/ F. ?- ~; a
| MCASP_RX_CLKFAIL
6 E* x5 @' ]! Q' `; \| MCASP_RX_SYNCERROR & A# X" S! h* [3 O0 i( a- O9 N
| MCASP_RX_OVERRUN);
6 S/ X' G+ o- B; E) }} static void I2SDataTxRxActivate(void)
; r7 Z) G8 [7 P! Y{; ?7 I5 P4 C* n% G( o" w" Q( L
/* Start the clocks */* K$ u" V3 n' ^2 I4 P; h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- y+ {3 L; h6 R" I4 @8 \; }" K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, s9 v- B5 j" l) [. j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. |4 x" Q& g/ x' c. Y7 ?
EDMA3_TRIG_MODE_EVENT);/ B% u) e9 T) v# l4 Y x2 W. c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " T/ v1 L, D& R, X. B8 g5 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 T3 h J4 C* x% ?( [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ i) g2 E$ P, b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" u) q' T) ?7 _, G! [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 t: u* k+ M |2 P: {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# [/ |/ f: ~6 c: oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' v$ \; Q1 G' U; T0 ~% L. r+ {7 d} 4 ?6 _) U( X+ m. |& J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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