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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 f% {2 j3 {: z& G" Uinput mcasp_ahclkx," W8 m" J- R1 G- p% L% t, \
input mcasp_aclkx,$ e" p3 ?6 \2 t7 a* M ]
input axr0,
5 Q5 T& F8 J; v f* ^' ?3 H
" I# u3 s( S3 h8 ]output mcasp_afsr,
" N4 S$ A' V% ~- B" i0 G% d' routput mcasp_ahclkr,
2 y( f; U# [9 N% L6 P- moutput mcasp_aclkr,
6 | i; K7 a/ }7 W, joutput axr1,
/ g7 d N( h# |6 I8 V assign mcasp_afsr = mcasp_afsx;; s; f% {+ _: ]: _
assign mcasp_aclkr = mcasp_aclkx;( g! P' h: j5 Z
assign mcasp_ahclkr = mcasp_ahclkx;: m4 H* l. S. V! B/ G4 t
assign axr1 = axr0; 5 v3 a0 z; D; m
" [( v% t7 I, D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! P7 Q' F4 P2 A5 r# G* }! Qstatic void McASPI2SConfigure(void)
: b6 p: {# Z5 e$ e' F- }& j{5 z, r4 i; S. w1 B! T- @% H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 e( h( @) i6 [7 }: `$ ?# p) h# A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: K6 H/ T) c/ p9 S/ oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) S4 a7 [0 m9 C0 y% n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! D# n8 a, w/ D% t9 V4 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* i3 W+ ^) @1 f/ K3 N8 w* D" Y; N
MCASP_RX_MODE_DMA);
9 \. k1 Z+ I, v+ j+ @( q- R QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 x1 H! ?1 `4 S5 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ r: |3 U# X1 L9 H6 v6 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 Z: B$ V, F9 z7 C, uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 d4 `, q6 P) l6 t8 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( r3 ?; ^0 y3 ~' pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 m, I, G4 V3 L: k# z4 L! [$ YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: A d3 I: |. O; e/ e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 I+ G" K5 L9 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 p# s" p! r- U' W0 y& a
0x00, 0xFF); /* configure the clock for transmitter */
7 s% j' t5 S/ k! E1 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, g8 L: c3 }) q) K0 T7 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* y! {) Z! \* L4 X$ m9 V6 _+ fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% r) x- G2 d9 w
0x00, 0xFF);
; {$ r' v# `, g- h* ^$ {) E0 j; |6 f/ B3 Y; A; l; W$ Q
/* Enable synchronization of RX and TX sections */
" O2 R$ b' S1 M# n5 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 Q5 c! i w% ?4 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' K+ p$ |( Q) e- |* MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** U6 [/ C- V0 j2 w8 o
** Set the serializers, Currently only one serializer is set as
6 ?, f, u& Z8 I2 K& v2 Y** transmitter and one serializer as receiver.7 {4 [+ Y" L+ j! C3 n
*/
7 i m6 C s! |$ N" l) O# GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- p0 d& R; P" V3 X/ C6 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. z/ t' I+ K* B$ H% [/ Q** Configure the McASP pins $ h4 S+ M1 P1 P# g" r* {* G: {) ~
** Input - Frame Sync, Clock and Serializer Rx
. J1 J" G/ `9 M7 @$ y+ S+ e' W! R** Output - Serializer Tx is connected to the input of the codec ' U9 b U6 v, W- Y2 G+ K7 {. T9 o
*/# Q( C' b4 S u+ T) _1 A# m B6 e% g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( m' b) o9 n4 b @- ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ b1 z4 ` b( m6 T0 R$ R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. [! a. _; z; C$ `' c; p| MCASP_PIN_ACLKX
; t0 J8 q( d) m& ?6 L| MCASP_PIN_AHCLKX+ M9 X$ Q# S/ m; X& e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 q* z" q( Z- e4 ?! c$ R3 z) }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 K' d9 C, P2 @ v, k
| MCASP_TX_CLKFAIL # a. c! n% l2 W7 i6 {& k
| MCASP_TX_SYNCERROR
. O/ P$ W- a6 Q2 w9 H! g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) u8 e6 g0 w6 g& s| MCASP_RX_CLKFAIL
3 Y2 { ?- \. j- e5 p| MCASP_RX_SYNCERROR
" {9 |8 F2 n% T5 e, J3 h+ v| MCASP_RX_OVERRUN);
0 J8 m0 Z8 C3 w A( o8 b# P} static void I2SDataTxRxActivate(void)
! s8 S1 m$ g1 b# d4 \9 ]& \* M* X{
$ S( _3 Z7 T2 U+ a; a/* Start the clocks */: a: g6 i; z. Z$ O3 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
u) T$ W$ ^) T$ `& k( x3 yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 ?5 O! f( v1 S, w, K- N9 L4 O$ \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 n& |! Z/ S8 [6 g2 k2 o% Z. E
EDMA3_TRIG_MODE_EVENT);# W, R$ I! R4 j, i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 P9 H6 M- e3 h1 K# E: c: uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- d8 j8 ]& D% N) T# J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" ]% j9 G3 h" _+ @! q# \, Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ ~$ @. G& j8 H7 x- {$ [; q: Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, o2 u, C6 H& X3 F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
z3 w: A* g5 J8 P& E6 u. CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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