MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
& _9 c( H! u  s9 |- {input axr0,
0 z/ n; N, M' S4 U' ]0 R5 g, q5 f
) q" x! G; X+ joutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
4 u. W7 u* c! ^9 @output axr1,

assign mcasp_afsr = mcasp_afsx;
1 \3 T. _+ j1 L# `& P* B1 s7 Wassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
  }/ A8 E+ k/ ^1 ^: M4 D. S2 Xassign axr1 = axr0;

0 k8 ~3 a' |, b9 m( D

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
& F0 U' n* e% ?, x0 K{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 P6 Q" @1 q7 \0 W* PMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
" w5 N# ^8 z- q0 U. c. LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
, E3 H8 E! a3 ?# KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* p4 v0 v. N+ j5 Z! ?MCASP_RX_MODE_DMA);
, o0 W2 j+ {" Y' x6 @6 s% @8 b( r! VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# t+ ]1 `- Y1 P- q  V( HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 Y* {' A4 D& X0 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% W. [# ~. H  J, l$ o! \6 A/ D  eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
) Q2 |- i# t( cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, f* q2 l" n& t# K, m1 |! bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- O2 _' f2 I% e( H* E- m0x00, 0xFF);

/* configure the clock for transmitter */
) U! _* q$ R! {5 F+ EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 h( H/ I  [: S5 s; iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
% @7 \; F/ \0 Q; c! {  \0 x5 M! f
4 S. u/ l! k2 p, }, s/* Enable synchronization of RX and TX sections */
* c, s$ e& e5 w" EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ U6 [# [( I& {- Q# ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! N; \6 t2 i! s, ^! i. BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
" a7 N- R  u- n* {; y) {0 ~** transmitter and one serializer as receiver.
) z/ j- p- L: r; U" f*/
) q4 S! ~& k0 G* A- l( q; n4 {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
  @$ w. C6 `' O6 l7 I( u4 z; j** Input - Frame Sync, Clock and Serializer Rx
; J4 b, O/ i4 d' V' X1 R** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ _0 ]+ y% t1 M! p) E8 }+ l. ^2 `| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
+ B' K5 ~! R' e' ]: F; g$ a| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
* [+ \# w' F3 @. t  H# z4 ~| MCASP_RX_SYNCERROR
# o4 s" z) R" Y/ ^. l| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
5 K' ?0 A# m. }{
/* Start the clocks */
0 s; m) a+ `- u4 G$ ~; hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
; e) f* \; k- r$ Q% a; LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 v; e, v9 Q1 ]6 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

$ C$ @4 m; R, i0 o$ ]$ }' C- Q

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.