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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ V& d" A6 _% I4 b; i* finput mcasp_ahclkx,( |) a6 {5 G5 S
input mcasp_aclkx,
& y7 y7 `" K9 c# q8 l+ ?input axr0,
* X4 ]0 f5 N+ i# n; o1 X
) k9 B+ X! `0 @/ r5 b8 |# Foutput mcasp_afsr,* v7 t- m; H! W& V
output mcasp_ahclkr,) X2 F% @6 n0 `
output mcasp_aclkr,
; x* t" L* t4 uoutput axr1,
r, _1 A: R9 \' I, W/ B assign mcasp_afsr = mcasp_afsx;% u+ T6 B- a/ \$ z. ]6 N! q% H
assign mcasp_aclkr = mcasp_aclkx;6 }7 m3 z, c q4 W7 K7 U- n- E) e% X
assign mcasp_ahclkr = mcasp_ahclkx;; `5 g# ]+ R* c$ o7 r
assign axr1 = axr0; 7 T+ `, Q0 B' B
3 F- q% d. y( ^: ~+ m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: `! J- o/ F: ]' B6 z4 pstatic void McASPI2SConfigure(void)2 ~+ f. ^4 `. m3 ~% ~
{
/ L7 C1 [- E, E$ `0 l) ]* }0 s0 z/ WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ [% F2 `$ h- WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ ^! o- [5 Z4 o! i& ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, j. t1 N) C8 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 z# K8 o5 U& w: M/ n- C% a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 |& H) I- X' v' }& F
MCASP_RX_MODE_DMA);/ B4 }/ |$ `1 n; H( ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 U- W+ X+ ]5 W5 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' k* b, {/ ^; |5 p6 b oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& f) v. d( f: n* g) CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. p9 D" r- L3 ^* S- s S9 l6 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 ?9 _& A7 ]0 a7 \% q/ @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 y0 L" U# I; v6 N3 f/ c0 R& |2 R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ s9 B; T" W: N i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* k7 A; W4 t, V: VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; z3 F: D- o. I& z' z* |
0x00, 0xFF); /* configure the clock for transmitter */
0 Y. e @6 J& G/ d/ z% x4 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ _6 `9 q* ^- k/ j: j4 ]) w$ O. G8 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % \0 g7 U4 P/ n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" K# b& g* Q4 e/ j0x00, 0xFF);' k( V& O7 Y) F; \
5 M4 c+ d. A( a+ T3 ~' y% N4 A/* Enable synchronization of RX and TX sections */ 5 |9 h6 b6 F3 q" V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ j* X& p* c; f+ W6 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); i; C$ X! w2 C" m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 o4 m7 k8 }. P, ~2 q3 m! W** Set the serializers, Currently only one serializer is set as( U; F: T5 D" [) I' ]- Z, z7 V/ H
** transmitter and one serializer as receiver.
5 E, T* Q% @6 A% F7 e& e/ M*/
& C# I% w2 X+ a0 h. d% sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 e1 Y; R8 W1 T" S% j" J; E, HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: I6 i( D% }' [** Configure the McASP pins
/ @5 a( X8 ^) G** Input - Frame Sync, Clock and Serializer Rx8 h3 B9 F: c* g: N& v
** Output - Serializer Tx is connected to the input of the codec ; C- |# A; l: C/ J! ^6 S
*/
6 y' |/ R7 K. z4 D& s d- hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, \1 H; _& _* Y \% i# fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 S" @8 D1 D, PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; R; z( p0 l1 z. S* @# x
| MCASP_PIN_ACLKX' i1 C7 c3 W* J6 |( [% v/ _
| MCASP_PIN_AHCLKX2 c! p* V8 t3 k& T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ p( l5 d" D0 S+ l3 Q& X8 I3 X7 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 h) Z( ^, x/ A. T| MCASP_TX_CLKFAIL / ] \. Z- x) |
| MCASP_TX_SYNCERROR0 ?8 W8 X9 W, x1 c* W9 d) _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( w- {& H& V ^% N
| MCASP_RX_CLKFAIL6 v& E0 ^- S/ C/ _; p* H" E
| MCASP_RX_SYNCERROR
7 ?# {& g& ?) [3 l| MCASP_RX_OVERRUN);
, h1 H+ S; U7 h# o! v} static void I2SDataTxRxActivate(void)# G! W% `! M+ l4 l7 i
{
d/ M* q) y6 i# b/* Start the clocks */
3 L. \4 y) D/ ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, Z& h- D+ q+ w/ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* K; i. c! v6 O8 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ L3 v; U" T# i% hEDMA3_TRIG_MODE_EVENT);# b+ T9 }# B# A) o/ }; n4 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ z4 M5 y4 k/ l& wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 H9 w$ i p$ {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 A5 J+ `8 k1 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ ~7 d2 x5 R9 ^3 q7 q* c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 ]% R' O1 W$ c' h5 U) w% L2 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ B v: J7 c+ e4 j! hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 |) p+ y) k1 v3 e Q1 u4 C9 z$ B
} ! m8 ?7 u0 f9 F& r! X" z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 _* }0 _; Y' a1 p) ~# D, e x |