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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 ~5 b& m8 o, L. [- f1 s+ Y
input mcasp_ahclkx,- \! O& i- k0 m! o1 ~/ s
input mcasp_aclkx,; b; a$ i' ]+ j e) I/ N2 r) Z6 ^
input axr0,8 A9 l* m; B8 A4 Q' F% f
, W# G2 C' }) f8 p' d, [7 aoutput mcasp_afsr, {# S6 G3 ^7 D. u+ x2 ~
output mcasp_ahclkr,( b2 w% s& O1 e" e2 U+ h& p
output mcasp_aclkr,
( D. z+ k+ t- _6 t% C. W, @output axr1,8 p. y6 q/ t- E$ u+ }8 [
assign mcasp_afsr = mcasp_afsx;
3 p" Y" ^7 \9 Eassign mcasp_aclkr = mcasp_aclkx;
! m9 s" S# H" X2 massign mcasp_ahclkr = mcasp_ahclkx;7 f7 `$ N6 T6 ]" Q
assign axr1 = axr0;
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* ^0 A+ N. ]0 B6 @& @; v0 F8 }" j5 v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% F- G+ O$ m* _static void McASPI2SConfigure(void)
+ v4 U! n, `5 R! h' q- Z; r4 j$ A{7 {, g% \) l' h" u4 Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ _1 q* G# X. F( e$ T* m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( H e( e5 W6 T" uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 U& N. u5 L" ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, o# ]0 w% ^# [# P6 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 M# F9 I3 p7 ^7 hMCASP_RX_MODE_DMA);
5 T$ r ~5 W: O+ w% T7 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' P! O/ g1 J2 |2 o9 k2 ]* d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 ~% a2 n" C+ e, I* W, w6 E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 S' ?- m( L2 {7 [, B- G( k3 A9 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ b# V4 ~" Y5 f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; d( V0 y2 _: [0 B7 M kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 A" N S- Q. d3 P; A1 `4 |: Q# [9 i, P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# U7 h: O. v+ l$ ?9 _, s) ^$ T* E: i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , a3 Z( d: y1 n5 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ j2 u. \2 s* t! T
0x00, 0xFF); /* configure the clock for transmitter */
8 x$ {% F/ ~7 T, k. e+ c5 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 f+ T; \0 z! `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
f, C* B( E: b) z& Q- }! \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- g/ C% i1 E2 k5 z0 _; S" A% F, o0x00, 0xFF);
% y" e' z) n. M
' i2 z$ Z; z, J* e9 A% q! s8 i/ ?/* Enable synchronization of RX and TX sections */ - r% T: [7 G. G6 m6 k3 O4 y1 i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ ^# L( Q2 Z( J/ Z' M# M6 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 _$ V! Y2 J/ m9 g1 @" \0 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' q3 g7 _; Q5 T( X
** Set the serializers, Currently only one serializer is set as
7 E8 ?, b9 G i3 {% z8 ~/ M** transmitter and one serializer as receiver., h0 q5 Q5 J- `8 ]% r6 [6 D
*/
8 Q+ a7 N& R6 w. I9 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! A+ U7 S) }2 S' b8 f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# \( c: t7 B N8 w
** Configure the McASP pins 2 u" H6 i7 {" E7 M8 M
** Input - Frame Sync, Clock and Serializer Rx
+ d( h" B9 a* p$ H0 H+ W** Output - Serializer Tx is connected to the input of the codec ! g" ]# W7 k6 m5 |0 ]( A3 B
*/) K; g8 G( [; x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 j5 f. P+ Y' \6 m. u# SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ x9 s5 I' R) \; [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. @ K- u' c% \) a! I3 r3 `2 z| MCASP_PIN_ACLKX
" F1 q- m5 A* d6 t| MCASP_PIN_AHCLKX
3 z& O! m" ~7 H3 G, t. K0 g3 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ w1 ]9 n+ I1 r4 E. |5 e" m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 y5 z; x, T( S/ o$ a- P( @6 `
| MCASP_TX_CLKFAIL 4 G* ]* p/ b* m
| MCASP_TX_SYNCERROR
6 M5 j9 M g! Y; L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 y6 r6 z9 O4 Q( [/ Y+ i/ s6 _( @
| MCASP_RX_CLKFAIL" z$ O7 _* L, M1 P3 c6 Z( ?% r
| MCASP_RX_SYNCERROR ! Y* s- [. d, U2 E
| MCASP_RX_OVERRUN);6 h5 S+ I% R: u# ?& M% {
} static void I2SDataTxRxActivate(void)
5 a" o% T2 ^; L9 M* G{( q, P3 y( x2 T* }: R
/* Start the clocks */
8 Z; B$ ]* d4 C5 V7 f FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- N! I& ]: {1 p$ @8 M7 K( N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 k9 A% k5 i4 y3 A& g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% A' M, B9 s% B, M7 nEDMA3_TRIG_MODE_EVENT);
7 C1 _- P1 X, [: B, `" R2 J: f1 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 P' W; C+ H. A; f2 _+ w0 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 X, E7 \6 ?. T ~1 ^2 g/ `: zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ S2 [, M% o* y& z1 ?2 a w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 w- O0 l4 ?" f( D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, X7 J* \; X4 ]# | f/ N6 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( ~: \- b" O5 k- v7 ~- S! vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; t( \* T" W% e5 @6 c
} % s' n: m8 O/ z8 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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