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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 S* ^, _% y( R4 K
input mcasp_ahclkx,
2 w% V; ~9 l \/ f: ?. d1 jinput mcasp_aclkx,5 k* Y- v. ?; [
input axr0,. C. t5 |/ U6 B1 n/ P! c$ A" J+ O
% R6 v. w0 c" M2 u
output mcasp_afsr,! U0 M# A4 S q
output mcasp_ahclkr,; F9 H8 ]) k- Z1 i a* c& \$ [
output mcasp_aclkr,, Z8 X% b7 z: x6 p4 D, H" N
output axr1,
+ [3 K- K+ A) |3 p0 h( c+ b3 O' z assign mcasp_afsr = mcasp_afsx;
+ t, S$ j( H9 y# }" z" {* Tassign mcasp_aclkr = mcasp_aclkx;* P. E/ v$ x3 G
assign mcasp_ahclkr = mcasp_ahclkx;/ G4 P5 I/ w. Y D% c0 L
assign axr1 = axr0; ! @1 H1 u! h: ?5 v% E
2 c0 x4 Q' H6 `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - P8 F; |( K% S. [$ B( k- {! B4 b, }7 s6 s
static void McASPI2SConfigure(void)" @3 a, W. @* \% ~6 a2 P7 i, U
{
+ ^0 Z' i6 \+ g4 C# i& `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 o+ y& C; F$ b% U; w1 A3 S9 j1 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 n1 k s2 r7 t2 u9 q7 e4 Y& rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 F, i3 `7 F/ H5 T) `8 c$ y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( E% {2 r: R9 |% c: ]: ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ |( ?4 }3 c0 q8 }" F3 f) Q4 y
MCASP_RX_MODE_DMA);. O4 @9 f j5 F. m8 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ l; r" w' \- RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 W6 r3 U3 e8 g7 n6 i. H( W9 c4 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; |" J | ^ {& M* u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, Z$ G5 V0 b" Z4 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ h8 d; f* |; }5 G+ r, N7 G# OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 L; _( j L% m" e8 ?. v+ Z! H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! m/ ?+ P$ @* y k# k$ w o+ T2 n7 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 z" |2 w- k3 a; Z, o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! ^) C1 U- P/ }+ L8 N+ M: F" ~& w
0x00, 0xFF); /* configure the clock for transmitter *// M# Y B# G& [+ n; m p; X) N, z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ ~5 Q N3 b5 q: o5 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! S7 X8 }- `$ N I' y6 |5 h y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; I5 F/ x: Q$ u: l5 I0x00, 0xFF);, B4 |- x6 C; ]9 z+ Z$ x
+ U- d" j% U! U0 |, z/* Enable synchronization of RX and TX sections */ % v% ]$ G* q4 A8 m' X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- k# c/ R% D: u- _% X) xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: Z. k4 C% b7 W6 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( \( n8 q7 E S1 h7 u** Set the serializers, Currently only one serializer is set as
% y2 A9 h1 ]3 ~9 D* J% U0 I** transmitter and one serializer as receiver.
& Z% Y. g' A% S*/( {, _: `4 G" V& s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% t8 N$ e5 A# Q5 a# ^. c/ s' w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 Y& f3 s$ p" A( m** Configure the McASP pins & w2 E; P# ?. X
** Input - Frame Sync, Clock and Serializer Rx# q, ^ x \, A
** Output - Serializer Tx is connected to the input of the codec : K1 g8 s' C i* I+ J% Y
*/
* V) B7 B# k; q& g- _) y4 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ R+ e1 F8 Y/ H$ |' @) YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' a9 w& e% P( M. J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; A% P# i$ }# F v: p8 r% d
| MCASP_PIN_ACLKX: W4 _. ^" y: c- q2 m. e4 v2 L
| MCASP_PIN_AHCLKX
4 U) _6 n/ c/ W, t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 [/ o% R/ R RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! U* V) X: [. G* B| MCASP_TX_CLKFAIL 4 `7 o8 L/ K4 H% `$ P
| MCASP_TX_SYNCERROR m( C' @. O* q2 w6 c/ g! _" a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * S% v7 q5 ?; B) F8 E
| MCASP_RX_CLKFAIL
0 Q" |; k/ j/ h& k| MCASP_RX_SYNCERROR 4 S; [5 k7 k9 p
| MCASP_RX_OVERRUN);
. f& c- Y0 Y) C' C} static void I2SDataTxRxActivate(void)
- T0 |8 I: _2 i. h d/ n{
% L" u8 f- H O" t7 F/* Start the clocks */
; X# D) i; P: }! s2 G, G6 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! a# d- B& C: l* CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% p2 I' p# U9 k1 p4 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 e+ H, s* j. A& d& k# B' h R. kEDMA3_TRIG_MODE_EVENT);
) Q6 P8 a7 P# S9 V2 r$ Q* TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
S+ l- q9 C: G- ~) K# jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ r" I4 [4 O- b' U7 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% T5 ^9 p6 N: a* o7 d C4 s" r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 S5 P1 {0 h5 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; C& I7 E a4 N. ^' d4 h- ?( |8 R& IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 J7 x. w$ ~5 I$ R# z6 ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 N3 ?$ c% `7 n" D" B
} / v, r$ g! @) r8 i$ x8 b$ ?) e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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