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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 c4 x# t: r. B, |. v( M2 I4 L
input mcasp_ahclkx,
8 P1 c d; u- o; ~5 D5 cinput mcasp_aclkx,
5 q, j3 {, E, {' K I+ v# b% L3 Jinput axr0,' z, h3 i, O# X0 W) K- a" X7 C
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output mcasp_afsr,. r" c0 N# [5 ^- W, I* ~+ }
output mcasp_ahclkr,0 F8 O ^4 x/ P r
output mcasp_aclkr,) u" r, X* u1 n: c N
output axr1,
$ \/ o3 h1 h4 G! P0 E% {# T assign mcasp_afsr = mcasp_afsx;
) x$ c0 F% n H3 Cassign mcasp_aclkr = mcasp_aclkx;
! I1 l, `+ y Eassign mcasp_ahclkr = mcasp_ahclkx;
/ O9 h, Z( i: _4 Jassign axr1 = axr0;
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+ F! d4 g% Q9 {- \* S3 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, |: `+ {$ B& ^/ f* Estatic void McASPI2SConfigure(void)$ q: ~4 v) K2 l+ _' p4 K
{# D4 r- D" s1 j( u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 q" |0 E1 U t2 T4 d) K+ zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 f" B& G; A: n2 V5 x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 h( _1 j, K8 }, Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# J* e% z; r& ]) j, X: SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. a) Y, @% u0 v
MCASP_RX_MODE_DMA);: r0 n$ T, N6 z/ d; |, g6 j- e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ w" z4 t" n% Z0 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 Y4 [0 q' o2 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ O" X4 z, w2 y; [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) Z$ A$ { Q, q* C- k2 DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ y/ b+ }% H& R% vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% x0 o1 i$ }' }4 b5 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* P" O. C$ t# P* _# Q+ _; N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 K/ B& ~2 l% G2 \6 @2 {) p: W2 z, F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' ^1 h7 r5 @( }8 B
0x00, 0xFF); /* configure the clock for transmitter */6 m) }2 }$ x3 _6 ?* G+ x0 v8 x" P- V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# X! t) r/ o: L. x% zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ a- R3 c! r" _# U& v# @; f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ x9 d9 K6 G9 C, }: N0 U0x00, 0xFF);+ m" i6 ?3 S9 ^# G4 J
' I4 Q) u1 S3 q: o
/* Enable synchronization of RX and TX sections */ ! z' h! d$ b; c1 ^2 f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- a0 }4 `+ D+ c4 q. N& gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ x, x% w' |. ^3 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% L$ d( S6 ~3 {. {* a
** Set the serializers, Currently only one serializer is set as
5 Y: m* D: O/ }% c7 N** transmitter and one serializer as receiver.
3 e# I! B8 f, v2 j( T*/
/ S2 ?7 R, `: \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ e( M5 O' d y k3 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& A2 C2 j% e$ I8 \. B; B0 h0 v, b l
** Configure the McASP pins 4 K2 Z2 v9 H& {: f+ r
** Input - Frame Sync, Clock and Serializer Rx
$ Q+ H2 ^6 B; t6 e. y/ Q1 p6 t/ ]9 b4 A** Output - Serializer Tx is connected to the input of the codec
- Q$ v5 W! X& Q: _" Z8 e+ s*// ^4 k" a ~, c: r5 J, H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& D3 J+ t* c `- \' P% P- nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" \- n- @1 X+ j! }) k* W* |, \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& H2 ]1 ? L5 R| MCASP_PIN_ACLKX3 s3 p% g2 \6 l! N( d2 e
| MCASP_PIN_AHCLKX$ |: W( F" H, a: V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) k. P7 O7 I5 ?. q sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 Z$ R( I, V" h: b# `$ s1 { [
| MCASP_TX_CLKFAIL
' Y1 W/ Z5 Q3 J g9 `* o| MCASP_TX_SYNCERROR
# o* g$ Y$ o) b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) ^1 d" a3 }1 k6 E7 {
| MCASP_RX_CLKFAIL
8 k5 W6 e# `: e# m6 B| MCASP_RX_SYNCERROR
6 e ^8 O+ A; k/ z| MCASP_RX_OVERRUN);2 h& o" \% [2 I, T3 e& X
} static void I2SDataTxRxActivate(void)( c8 \( L) ?# C2 U: ]& |
{0 e) \6 K d& c6 ^+ w M: ~
/* Start the clocks */6 h6 E! Z2 b6 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* w! N' }/ W! i7 Q% h8 h/ R- cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; m; ~5 I( `5 N# K6 M0 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 B! G: l; A" U, N! }, x
EDMA3_TRIG_MODE_EVENT);) [) ^. k$ m |1 u7 k, F3 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * O* p: R; Z: \0 I$ }0 q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( |6 ^ V1 s5 y. \* m4 d2 ~$ ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 p: x8 s+ C6 G) T# ]7 u2 WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; P5 l& }; B. X; X. l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 C) a. K4 R$ tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 L3 O! v$ c& c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ G' @3 x2 M( s$ |, t6 G) q# a}
7 S3 S5 N, F H9 M8 u0 [ G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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