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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 U2 p- b9 `! @input mcasp_ahclkx,
- }9 |7 ~9 @( dinput mcasp_aclkx,
5 H5 A# h2 p2 |* v* {input axr0, E% _ K5 Q4 z2 s) C& l9 a
|$ a f1 x% D. d
output mcasp_afsr,
# r" X) ?' `- K- G9 ~2 Ioutput mcasp_ahclkr,6 v- H1 K7 [' O) w9 c
output mcasp_aclkr,1 t% D' M. b/ s: l% _: W% w# y' v
output axr1,7 p6 t1 H; G# x/ @. g G7 ]
assign mcasp_afsr = mcasp_afsx;% v/ v+ i" d: S4 g/ x1 \1 H# j, s
assign mcasp_aclkr = mcasp_aclkx;
' w9 B% M0 P. vassign mcasp_ahclkr = mcasp_ahclkx;
0 ?! ^; c/ B. v1 Xassign axr1 = axr0;
, D/ T1 V( r" z7 X- N! H; i0 I( b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # r- ?) R" X% P: a7 j
static void McASPI2SConfigure(void)
5 ~/ `2 w2 |+ l' O2 T& ^- y{
0 y; g0 U0 {7 Y! ~& WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* c/ i; N/ b& L& y5 T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 v5 o- f1 q5 t$ @$ d* XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; m8 y" [ s$ y! AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 p* o' R! g0 W: S7 v: E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 M1 v5 }/ D' R: s- x h3 HMCASP_RX_MODE_DMA);
# `5 v3 e* s7 A* a8 D* ~2 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* x6 E E: d8 @. r' R SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ Y0 ?* Z- ]$ }: D! L8 z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " Y' q7 R) v+ [- u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 a5 y3 ?, c7 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 I1 m0 c: f% SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 I# U3 O4 ~$ Z# B9 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: ~) P M% r" v3 ^! |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* C$ `& b) l$ h9 g& S2 l( XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! k$ v2 }8 P: f% J& ]+ U( |, j0x00, 0xFF); /* configure the clock for transmitter */
% s }3 h2 x: B' z) DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 \- p C9 C* n; \7 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 i0 M) m2 S( p; Y5 H! z& V5 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! a- ^$ f; {0 k1 h0x00, 0xFF);5 _) |7 e- q, l! x
1 S$ [9 N7 O, N& I2 p/* Enable synchronization of RX and TX sections */ ! d$ u) _: i9 Z: G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 F, N- ]6 a# |9 ?* O: i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( i& b2 l& X$ d, `7 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, K# ]1 ], X4 e" Z, v** Set the serializers, Currently only one serializer is set as3 y$ E( z" J6 P# j+ N5 T
** transmitter and one serializer as receiver.) F- ^, ~" A) D. q* }+ _7 X
*/
# X- k* ^0 m5 j5 I4 C- B% Q6 l0 q- bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* o8 c& G- j5 g9 C( ]. |3 f( R( xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 c0 e. C0 h5 w& V/ ^$ r# ]
** Configure the McASP pins
0 x( @& B3 B0 a6 G8 c** Input - Frame Sync, Clock and Serializer Rx
$ _9 _' e2 m% T** Output - Serializer Tx is connected to the input of the codec , w. h8 y5 t" \1 c1 u( J# R" T, O
*/
- [5 {* w! M4 l6 ^' A) UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 h& c1 R- D7 Q2 _- y6 j1 T0 [ ]' W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 p0 }& B4 N& C6 ]( g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 g4 x5 _( Y& B3 }* W- t
| MCASP_PIN_ACLKX
4 m1 V' |* D A5 s! C| MCASP_PIN_AHCLKX. ? B* }( T2 @1 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* c. r+ w1 n% g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 U4 t/ B1 W; m* u2 s( o& e
| MCASP_TX_CLKFAIL
' f8 X, P' g- n( n| MCASP_TX_SYNCERROR
$ [/ s; t- h8 ] l: e" C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 X: f: x% K( |& D! x! D| MCASP_RX_CLKFAIL
" s3 m- q3 e+ R| MCASP_RX_SYNCERROR
) a) N) w/ ~* ]| MCASP_RX_OVERRUN);
2 @- i% N9 j* D1 W0 K4 A& d- {} static void I2SDataTxRxActivate(void)) w, l; Q, Y7 `! _- ^8 X
{# n" h$ {9 n$ b
/* Start the clocks */; H9 {' f7 a# g% b" W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
K! |7 G( _* G( e |& {; JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! P6 |+ ]/ n2 L: i( G) x7 p! wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- U2 }! {2 \' ~; Y, }9 H. ]
EDMA3_TRIG_MODE_EVENT);
5 J. ^# I" s' k; M" }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 x( Y: I. e1 L: ]6 G# GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* P$ ~2 Y* w9 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 H' T: ~1 D1 w l5 H2 Z2 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 A: S7 r! M# ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& D4 s; f8 P3 k+ p. x3 H2 T; kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ `, E7 E! }& m& G: b/ J0 S8 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; s/ D9 w. n/ O. t/ g8 ~1 T' f
}
/ g ~% ?. ]5 m. P# Z1 E' l" l, e3 z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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