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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% R7 w; k0 H/ [5 g) s2 g; _. vinput mcasp_ahclkx,3 Q, ~, Y# N; s- j3 C( ~( K
input mcasp_aclkx,/ T1 W4 S8 w! `% K
input axr0,7 [# u' q9 M5 P/ ~
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output mcasp_afsr,: i! j1 J X. h; b( c
output mcasp_ahclkr,
/ S2 k& D9 r4 ]( r2 x+ joutput mcasp_aclkr,
! u5 O4 z( a5 h6 L% a9 o6 loutput axr1,8 g5 n. p2 I: @9 |
assign mcasp_afsr = mcasp_afsx;
0 v3 X2 ?5 ]7 c5 Y: o/ ?4 V+ B( uassign mcasp_aclkr = mcasp_aclkx;
& c$ b x- i& C$ a: `assign mcasp_ahclkr = mcasp_ahclkx;
; N2 T4 W2 O! ~& J( [6 Massign axr1 = axr0;
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. F3 e# s3 a& D6 A5 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
Z7 \( X9 s* o, astatic void McASPI2SConfigure(void)0 n$ J) h3 @* b/ C# X. M: E! J
{2 ]7 P& U$ Q+ |- ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" T# ?" ?, r3 v6 w# K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) y7 F) u7 h; O7 |* fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- p2 m1 _* l( ^8 d5 X6 d! d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 z) j! _$ Y6 k. X" YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Y6 N- q p$ u
MCASP_RX_MODE_DMA);
' t$ K# r, q- E) k) h+ s, e/ hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( Q# J1 \ C6 ^3 U, i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ z- M; z2 s8 tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' i0 n* m3 A" }* f8 p9 ~! z: j- Q/ y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) c9 m* g0 ^5 |: |: i- c! ~% ?9 p @2 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 t. M8 ~) R5 o" Y- S6 V- FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 |" u: |- H$ N# z: f& oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; {9 r( G& Q$ _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* c( U$ h: S( a; \% p6 D, ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. e. R0 H7 A+ Q0 Z0x00, 0xFF); /* configure the clock for transmitter */8 d2 `/ _6 }2 m7 P8 ?' g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. {' [) n' E* G+ D- h8 f! {- a, x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 c: |' Z% ^. q4 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ M$ B: J& x0 K! u& I7 c8 o0x00, 0xFF);0 W% p W* o, R: S
% W ^1 \; L- _' L
/* Enable synchronization of RX and TX sections */ % J- D* }, i+ R( \# z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 y/ l4 @0 i+ ]7 y2 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( r0 Y0 x O& wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 `6 g+ E' e8 i) }$ u/ b6 q5 |
** Set the serializers, Currently only one serializer is set as
7 k9 B) r2 D# \, l** transmitter and one serializer as receiver.* u9 D# u2 j; w- T
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: w8 O0 M1 Q# O" S% {4 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 _1 \( e* R; o( e, \3 F7 o
** Configure the McASP pins : r% u: E: a: [, |2 c# e7 K
** Input - Frame Sync, Clock and Serializer Rx
% E5 ]* |1 m7 \+ I) t2 r* J3 R8 b' X** Output - Serializer Tx is connected to the input of the codec 9 Y; w& ] Z, C( ]& _
*// q) h8 c. f! @3 \( t2 e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( n3 _/ e+ {+ g8 P$ R. B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 w0 _- v E- X8 V8 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% d4 O+ l/ w4 J. j, O, P( G
| MCASP_PIN_ACLKX( ^- b3 [! F# i5 ?8 m3 K1 H# Q
| MCASP_PIN_AHCLKX
8 m4 R, A7 Z$ p! m& x( O, O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. ~" ]! z3 r9 M0 t. N2 @ g8 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! n+ E t. q9 \# P- w6 W
| MCASP_TX_CLKFAIL ; J7 v4 q6 L: Y) z3 w
| MCASP_TX_SYNCERROR, P; b' V( W3 ^& t9 N/ `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : Z" @ I, P8 p/ q" C
| MCASP_RX_CLKFAIL5 o# U7 s6 P0 O( t5 ^# V* H* G
| MCASP_RX_SYNCERROR 7 h7 I D7 z+ r! A
| MCASP_RX_OVERRUN);$ |2 W% x, F! s+ c/ D) g: g
} static void I2SDataTxRxActivate(void)
/ `+ A5 G' e# G3 X{
# Z$ F2 K" N R' _% v7 ^/* Start the clocks */
; A$ |8 T" {, l; D& g% XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 F6 C1 j7 d: f2 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 o, N0 s+ _$ g" g9 z% A2 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ Y$ C7 ~6 J, f0 ?9 b
EDMA3_TRIG_MODE_EVENT);+ B! Y% A3 r7 C7 Q7 W5 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / u' A4 ]( |: K+ g# e g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. O2 q; h4 d1 ^, K4 e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* p1 S6 p7 {# ?6 Z0 f o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// a$ I% A! g6 w3 Y# f* P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ H) y& c6 H7 q0 W3 l3 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
O7 V# c/ l2 y' Z2 `% o5 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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a# ~7 ^# `3 T Q2 M) F- R- [! I& q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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