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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," r$ G7 j+ h9 a& n% V8 e- q2 [1 P* Y
input mcasp_ahclkx,( f% O# A2 t x+ Y9 ^
input mcasp_aclkx,
; t" H7 k; L& _2 S3 S- D6 `" Oinput axr0,* Y$ S( ?) h$ A% }+ ~
' Z4 b; [9 t; F. W d7 noutput mcasp_afsr,- `) H J- j( v' s9 _2 c& w
output mcasp_ahclkr,
; X/ A0 @# @' }1 koutput mcasp_aclkr,
: s6 e. f$ s& ]. u9 h7 u* ~/ z8 ^- A6 uoutput axr1,; T; h$ w+ @, J
assign mcasp_afsr = mcasp_afsx;" c" t1 w0 q. P$ s) H& Z( i4 f
assign mcasp_aclkr = mcasp_aclkx;8 t, U& ~9 o, V2 R& s
assign mcasp_ahclkr = mcasp_ahclkx;
) ]0 N+ A( D& j( e- y6 _) Jassign axr1 = axr0;
9 ?2 m9 `! H0 ]6 B
$ e- @. V O" ~- A, s/ y r/ k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* V& p% |2 B' P6 c6 Z- x+ D; Dstatic void McASPI2SConfigure(void)
g/ @% \ |: q2 \7 S! r{$ I: p' o6 ?( V: }& b. h. C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: P! F0 Y3 v" C; I6 I, i6 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ Y7 Y" W- h% D: @1 @( ^, aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 ]$ n4 i3 n/ [% p( X7 I% x. q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% r, y0 y8 ^( E V8 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ t6 n8 x! f2 xMCASP_RX_MODE_DMA);' d5 Y9 _9 C" ?, {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* [' j3 E% B* a. AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ z# N$ \( C, N4 P* F/ |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) f: {6 f1 o0 f& s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); m& t9 a& S% [+ R# g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( R3 \1 S- |4 V% s2 ?0 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) c" K0 p) d' {8 U6 Q; lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( B Z2 a! a; F( Y+ G0 ^) QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) ^4 K& Q6 R8 Q7 T& L" C/ a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ j" v: v0 Z" F0x00, 0xFF); /* configure the clock for transmitter */6 k( ?7 y& D h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" r0 X" I. m& S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , f4 }8 R+ w! c4 ~: u3 C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ U; p% P0 |1 t. M0 l
0x00, 0xFF);
! Y4 l7 Z( o+ H9 P
# ^4 G8 p$ t: v: F/* Enable synchronization of RX and TX sections */
2 d, k8 M1 |! O8 W' y3 y( [, R6 }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ w; H1 Q& X1 \) h% M HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# u& [; N/ U6 T/ h7 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" V0 m1 w- `' |7 d2 z9 X** Set the serializers, Currently only one serializer is set as; x7 O! p7 y, ^4 ]
** transmitter and one serializer as receiver. @& _- C& p8 b4 v* E' C- F, q7 H3 |
*/% x+ v) t- S# F3 G# e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 L/ Z) b/ z, [7 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& B4 e% G5 P& a# G4 i: b' E! v& [** Configure the McASP pins & l& C) H" O0 X" U8 Y
** Input - Frame Sync, Clock and Serializer Rx4 ~# F& F( Y9 X9 P7 E0 d
** Output - Serializer Tx is connected to the input of the codec . f( {$ m8 W7 ?& W
*/
1 l; `2 L8 a. H3 E6 G0 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 C% S; Z: K( E, @$ E' f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 `2 S' M N5 gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- J3 J+ B% Y$ r
| MCASP_PIN_ACLKX7 ^. d5 ] s# w+ R& B) \) ?
| MCASP_PIN_AHCLKX
3 d# } l4 w( ~- v, J0 A) T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* f1 x! S& S) ~. R# ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - s. Z9 t, ^6 q1 D6 \. d
| MCASP_TX_CLKFAIL
5 x' e/ }; H0 {* n) P# B| MCASP_TX_SYNCERROR/ ?4 i$ ^3 O* r' w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 k q% G" S' h' Z7 Q| MCASP_RX_CLKFAIL: v/ d" b4 _4 v! \! ^# H
| MCASP_RX_SYNCERROR
& E8 E1 e$ V" f| MCASP_RX_OVERRUN);
& k8 U+ O& m+ m. G; \ E* i# P8 ?3 ~} static void I2SDataTxRxActivate(void)
* X% S+ B1 B! _4 _! D- n{8 q5 R V0 C- ]* o' k$ G7 e
/* Start the clocks */4 ^' ]4 w1 I7 w7 A$ }% e0 I! }+ m8 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 y0 \& ?9 B5 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, Q$ S1 R! j, _! X" r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 V8 G5 J2 g0 |+ x8 i# h: y L
EDMA3_TRIG_MODE_EVENT);9 m+ e7 M8 g% J g3 ~/ l6 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 {# L& Z1 ^- r# t6 ^. {/ C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ G# |$ d& G0 i; Y# C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 |1 u5 j3 {7 }# |9 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 |/ o$ @. Q) T" h5 o4 ^ n/ Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 P" q7 O& g. i" [3 N L3 i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 [3 k; ]+ C- H j- d |, S/ M Q5 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; X" Z R+ y% K; k- M} # h2 ~5 j: U7 a9 K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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