|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ F' s2 Z B+ R1 Y4 G# {* Zinput mcasp_ahclkx,
% l' t3 Z/ D( g0 h7 Kinput mcasp_aclkx,
5 A; v1 w1 \, r) \input axr0,: d1 C3 F5 n& _/ J# ]
$ q- I3 J; `4 }
output mcasp_afsr,2 P3 p* B' Q0 p, a# g- V& |# j
output mcasp_ahclkr,' W2 n" }& E3 Q; k' S
output mcasp_aclkr,
$ x' c2 a. h+ X* Y% {# G& houtput axr1,
) Q5 _1 M: Z. ?% H8 Q9 n assign mcasp_afsr = mcasp_afsx;2 p# e4 D. M5 y2 P" r& s
assign mcasp_aclkr = mcasp_aclkx;
; r M+ P5 i" k$ o) w J* Sassign mcasp_ahclkr = mcasp_ahclkx;
8 E2 b5 h& `, h# X- M0 j0 massign axr1 = axr0; ! y) Y! N, I7 ?* I1 e1 K
- {$ P& P x6 N, o9 d. W, @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; S! e2 x( b8 A8 S4 Q$ [static void McASPI2SConfigure(void)
3 j$ R/ A: r) X( N* p! |3 d) _! V{) A. L+ i Z! g( s4 a( F. O4 D6 E5 a. g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; H+ c8 R: Q) t6 ?* N, xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" V1 `/ q( n& g& |4 W' g# U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! ~1 y% e6 c' `1 S. Z( N$ F2 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* I2 E7 j+ n0 g! ]% j8 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 g! R/ B3 {, Q1 w
MCASP_RX_MODE_DMA);0 x0 n3 F, q4 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# _# H, T2 D* V7 f' N( o X+ [/ x' K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ a$ Q5 v2 a# K# m; B, OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 N" d! A- }0 o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ V1 [" y2 `1 d+ t! Y8 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # A! d3 V8 f% K- N/ K$ j+ g# O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; S6 o& T3 z6 v [; z% B8 i9 Q4 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: B1 L6 s: I- G% x6 F" SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 h) w* B! B7 Z5 l; ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; D) C+ k/ j2 v8 [
0x00, 0xFF); /* configure the clock for transmitter */3 K) t) N5 d5 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% O4 M! w7 \0 _ W vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- D+ Z8 L, ~) J! @2 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 q9 K. \, f# _; D( l9 g- i, Y
0x00, 0xFF);
f' w7 X: L1 u5 L- z; @5 s, v) G' l$ e3 \" b
/* Enable synchronization of RX and TX sections */
0 m" w: w+ y6 Q; E# IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( x9 o0 Q- C& ?1 e0 m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 R! S0 l. Z' K6 sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( L5 v# \; _; y( f
** Set the serializers, Currently only one serializer is set as, j& K" E5 I ], x
** transmitter and one serializer as receiver.
: l D) A3 @0 i5 d. ^' g*/4 O* g2 v2 I* F1 M9 @* C2 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 B9 S3 O5 r8 `, o# {5 Y7 g) z0 D5 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) H3 r; c8 D7 a }0 l
** Configure the McASP pins
% i, n$ f9 F9 ^+ F** Input - Frame Sync, Clock and Serializer Rx
- G" \0 G( s) H' R; a** Output - Serializer Tx is connected to the input of the codec
, G1 R6 q+ x t4 Y*/' {! A, w ?' v1 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. f6 g$ u! f S* h# W# ?* _0 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 o. `7 a" p" ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% ?4 G& s& H% ^2 b# n# p( p) L
| MCASP_PIN_ACLKX
, C9 j$ F$ W0 Q2 L* L| MCASP_PIN_AHCLKX3 J; a: v( Q' j( a8 t; v2 z. ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 A* f2 m; C/ u0 B1 X: p+ iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 o# j$ t' t3 v, M9 X/ N) L2 U3 S
| MCASP_TX_CLKFAIL 4 i1 O& z# m9 w" k' e
| MCASP_TX_SYNCERROR# s2 m7 U# P* A6 G7 x) G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 m7 \9 l- m. j6 ]# h" `; Z| MCASP_RX_CLKFAIL
* @+ ]/ I9 o4 ?& X| MCASP_RX_SYNCERROR & N3 V+ F" W$ p: K! ?' n
| MCASP_RX_OVERRUN); Y3 m. E$ d2 ]0 M" M X) }- v$ Z
} static void I2SDataTxRxActivate(void)0 @/ X, `7 H$ T$ f# k
{
7 a4 M2 m0 l* z9 r3 M% V; s% z2 z/* Start the clocks */
) T* r4 m) c8 ^7 ` ]9 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, {! F( ^! T) SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) K4 K$ S' Y& H6 Q& oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 D5 w$ w" z; ]( i/ C5 t
EDMA3_TRIG_MODE_EVENT);
4 V$ l% ~# _# B. lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ Y& R% n2 d2 [1 U' b0 \ HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 M$ k9 @$ |1 U+ Q- V7 r9 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ t- d- A# e" g4 b# ?" v2 t0 @8 \$ \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 v/ s$ }$ R5 i7 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, x4 c- S5 p8 M4 ?5 ]0 x* u4 WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 U0 _( h& T+ AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 P; J5 T0 [. d& |% h
}
% v1 ^7 d- Z% d( Q* }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ b$ {- E5 ?' S: u' I! e& Z5 T |