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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% ?( i0 J* r- z& J
input mcasp_ahclkx,3 |' u v2 N8 h' a# O
input mcasp_aclkx,
1 h3 c q5 Z X0 Winput axr0,- [/ H9 ?8 c) v8 j- d
- A& c" ~2 V I8 r
output mcasp_afsr,+ v1 K: ^/ v8 j0 [* F4 ~6 g
output mcasp_ahclkr,7 }2 v# r- r& @" f& q
output mcasp_aclkr," Z1 R5 r/ J0 g9 J
output axr1,
% v A- J, _' X: S1 C2 d' h assign mcasp_afsr = mcasp_afsx;
. a. Q6 U/ {" i8 b1 a; dassign mcasp_aclkr = mcasp_aclkx;
+ B6 S* J& @. B' J# J) O& uassign mcasp_ahclkr = mcasp_ahclkx;
, J6 Y r) U$ e0 j! g# e0 xassign axr1 = axr0;
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) J' _% Z6 w& ^3 E; ]' `# h! d! @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * n( Y+ z% K# f
static void McASPI2SConfigure(void)' {# U% r4 p+ r; X4 a$ E
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* W0 Y6 I: R, y4 D8 f1 JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) ?2 J# K0 Z, r7 f/ M- LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 L2 h T1 K. N9 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; r/ A% g* Y- j( J; U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 U8 {" S6 y K
MCASP_RX_MODE_DMA);
6 U" T2 `' |4 x% E& ~$ A( tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 f. Q5 k. w( h! V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 c+ W6 u+ M: D( {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; y+ w4 w5 z. c; n) Q, G" hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 O4 X" u* F/ _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " p7 h! J# Q3 u/ F" R# U# t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; V: g/ r7 p$ R. N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 b7 w9 b4 G9 r7 M" B6 y3 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 U" ]7 J6 T! m$ ^- kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: H4 i' x' J/ n* y; D0x00, 0xFF); /* configure the clock for transmitter */
+ ]! d9 B: O6 P9 `( CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 I( U+ O3 K' A. ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 C) k$ M8 Z S0 V# F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; F2 N: v9 X2 }% D& v: f* N+ ~0x00, 0xFF);; n5 s: Q$ t) M. | a y" |* x1 K( G
( ^3 w9 ]4 b' A8 A1 O: c) c
/* Enable synchronization of RX and TX sections */ " V8 O3 |' s; Y' A3 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ m. w P' h+ r9 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) R I" ~) d2 T; O0 _1 ?3 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" ^ L- K' f7 A! y** Set the serializers, Currently only one serializer is set as) b# S( `! t, @9 \( l" s
** transmitter and one serializer as receiver.* O8 w) u( u4 E# H* {% q, O
*/
/ B& j M/ e1 z k8 |. XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ ]7 K: M; A+ w' hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 T5 x0 @4 r2 B: t! G6 T8 q$ j
** Configure the McASP pins / l4 U( Q! V7 K5 {
** Input - Frame Sync, Clock and Serializer Rx" X: g$ F& H- Q
** Output - Serializer Tx is connected to the input of the codec 8 B. j! W; O3 Y6 Y; E. ^$ C
*/
$ N( x5 n. @! \2 y* q: S9 s( fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ O; c9 _) f6 C4 P: m+ ~) oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 M% h' x. c r* W4 R" _6 b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% ~ ~) W( r: o+ O( D j/ r
| MCASP_PIN_ACLKX
& x1 F9 Y S0 l: a3 c| MCASP_PIN_AHCLKX i0 ?! m# C' _7 N. i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ A) Z* c% a3 A4 Y% C7 O D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 k" j3 \# v% K$ h; h
| MCASP_TX_CLKFAIL
) B& W7 U! Y2 A( V* d| MCASP_TX_SYNCERROR7 t; r# t0 C( _% M0 g7 i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 z& f" p" H4 t$ L. h4 S8 D
| MCASP_RX_CLKFAIL
6 S# l' `" b/ T| MCASP_RX_SYNCERROR
; Q. \8 ~; y! D| MCASP_RX_OVERRUN);
; J9 [+ C$ a8 f* X5 T3 B9 X! N} static void I2SDataTxRxActivate(void)
9 \7 s: a1 k/ p. x* T; w% v{
* }: w$ T: B; \1 a2 e/* Start the clocks */
# D" i; g2 t/ ^- J) sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 I8 V* g8 z0 o6 M3 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ [6 O9 s& H2 z$ d2 E" k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; m* L0 O2 x- @
EDMA3_TRIG_MODE_EVENT);3 @, y" B* U$ z* L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " G, U, Z4 } v( w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ m+ ?/ z: \0 P6 ]% BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 ^" w# V5 y5 n# Z$ h* F6 x: kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; z( D: {4 Q7 C4 F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 n9 z5 a% Z2 W7 ?! \0 Q2 l& nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% d* s0 ]; h- M( u* c; ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 T0 a( M1 f: s2 @9 N; |
}
8 V1 u; p* s6 Y9 S8 d% V4 A) d, W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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