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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 G+ h' i( E2 K0 Y
input mcasp_ahclkx,0 r. m6 x. A, f* W
input mcasp_aclkx,; U( F, \$ W! _- T4 M
input axr0," w' B9 u$ h, Y) [& n
" U$ L- t8 S9 x7 z& `9 Y3 D( ~output mcasp_afsr,
0 ]& e& {0 _2 Q1 xoutput mcasp_ahclkr,
4 K: p5 [1 J. Goutput mcasp_aclkr,7 k" f4 i5 ]/ Z: R! z* T+ x
output axr1,; O) U+ K4 S' r+ U1 k, F9 y
assign mcasp_afsr = mcasp_afsx;
. N) X8 M+ D8 Z" lassign mcasp_aclkr = mcasp_aclkx;+ g( p( s) W$ |+ n
assign mcasp_ahclkr = mcasp_ahclkx;$ t$ _) Q6 H; ?( e$ u
assign axr1 = axr0;
' _5 ]# [ T3 |& F* p7 O
4 a, T# t- f$ B. \* u: b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 _0 z0 V" ], Z" R7 I! [0 Gstatic void McASPI2SConfigure(void)& t: T- U7 x& v+ f
{# I2 S; E$ P# u- ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
T4 u& |" K% d) o& |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 U1 a8 K5 q. v: B1 ^/ i1 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 S3 Q& h% n5 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 T# D" Z0 |, ]' _. h6 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Q5 F5 u7 V5 T, V+ }MCASP_RX_MODE_DMA);) C1 W+ C% V+ i+ t+ P1 @+ }# ?7 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' H ?9 t0 w+ ~, Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ r+ s' I+ r# l* c0 N& B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 ^& }1 u1 A, F+ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 G/ ]/ B9 ?5 s. i" u9 J6 {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: t+ _+ T' Q# ` ?% aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ _8 c% o' }! P+ a- A& q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( X7 Q1 i+ F, {" s+ p2 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 W6 A+ n5 a* b' t5 h: W+ M. FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: Y, V) P2 ~' S: H* H
0x00, 0xFF); /* configure the clock for transmitter */
, f* j/ u$ h% m9 B1 _( g LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. ?5 v6 t! |5 w. L4 p, i7 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : Q3 {) R0 N5 J( i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 O- r0 Z' u3 P5 S
0x00, 0xFF);
! y3 Q* t" `! r+ s5 a1 V3 P( T
' H* [4 c- v1 g( G# k4 J/* Enable synchronization of RX and TX sections */
$ r( l1 @8 O- t! I, b6 {0 g# c5 g8 `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 d. X! o5 e) [* p$ u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' }/ u& I" Q; H; Q, l5 j2 E; \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) n4 |& k6 j9 O/ l
** Set the serializers, Currently only one serializer is set as( n/ T0 d# y" `+ {
** transmitter and one serializer as receiver.7 H! i& Q( I5 z3 t0 w; \
*/
0 t2 M/ d5 x4 T: ^0 u6 h. l- IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 U5 p) b' Z8 w, |% `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 x( i e, r8 S: [+ M8 `
** Configure the McASP pins
8 U5 R) i- ? G% M** Input - Frame Sync, Clock and Serializer Rx
6 a6 r% Z* b( W+ D& @) O# @** Output - Serializer Tx is connected to the input of the codec
% Q* G8 f' u2 x% w* ]- f. G*/- V9 Z7 }/ V( d+ l$ @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( ?3 E: h5 f6 {* ] z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 Q) N+ V k7 S$ a4 h) t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ _0 ?) m4 Z% H7 ~
| MCASP_PIN_ACLKX5 q7 A4 e5 R: A* J
| MCASP_PIN_AHCLKX r) I; O' ?* W' l% j2 d/ }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ y: d% Q9 |# K; ~) E# t. E/ j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 g- O9 l7 a, [ i- a
| MCASP_TX_CLKFAIL # N" ^8 d" u+ c( T0 |9 d
| MCASP_TX_SYNCERROR
- C8 w& F7 o# T L! N3 q9 h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' C/ \3 M, D& f9 r| MCASP_RX_CLKFAIL5 `. o' i( B5 R+ @7 s
| MCASP_RX_SYNCERROR + a# K' t9 R+ t Q2 t |) M8 k9 H" ?
| MCASP_RX_OVERRUN);
# V: d5 c3 x8 L- g. g} static void I2SDataTxRxActivate(void)1 M$ @2 @2 j8 a( f. I
{
/ @+ K9 V! F* E* v/* Start the clocks */( s p% f, f& j. e8 `8 X8 U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 O6 K$ J4 f; W, Q9 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 ~+ n5 m. W7 L0 p% ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% {3 \% e3 W4 R
EDMA3_TRIG_MODE_EVENT);7 C6 t$ S1 @$ i9 s4 m a' O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 d; l. i; f. E9 | K# b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 o- y; H0 y W8 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 {$ L7 Q% p$ j& N$ e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& F$ I- E {2 t: A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 T& B& B6 [7 E6 k* t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
c$ ^8 Q- f0 Q) {) b# d( AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% v! l0 K/ ]. G) _4 E} % L) G8 n. i. ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * C0 I0 [& Q* k' l- |6 M
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