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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. V# }& @0 o0 t
input mcasp_ahclkx,* B ]3 X$ Q$ p1 P
input mcasp_aclkx,+ M* v. T( W% f4 M z8 i& Z* z, k
input axr0,
a% ^+ T7 ?. K, \* P( N# w. U$ h* x6 \# ~ O
output mcasp_afsr,
$ s" @6 z1 }7 `output mcasp_ahclkr,
( P/ U/ ~5 O( woutput mcasp_aclkr,
% i1 v, q( S/ q- d$ Eoutput axr1,
! y) h! p! m- e- c) W' C assign mcasp_afsr = mcasp_afsx;" f1 `6 S$ f J) M* k
assign mcasp_aclkr = mcasp_aclkx;
/ l5 K7 k+ a1 r1 E8 Eassign mcasp_ahclkr = mcasp_ahclkx;
; Y9 X5 R! L1 y% E5 {( b% Gassign axr1 = axr0;
8 _% X0 E! Z0 ?) X$ Z% _3 X
) |- @$ q! @% W9 G: y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* M& Y4 {% j/ H4 d; Hstatic void McASPI2SConfigure(void), M$ [1 c- l3 q+ K. `( ~
{
4 I/ B0 w% }# B' F& a& M9 Y) IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 U9 Q6 ^# i% A" [. iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 u: p5 \ m) b: R& D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ O, Q/ ]8 L/ k7 v m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ O# r5 |7 R1 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 V* I* L4 U, g9 `( `
MCASP_RX_MODE_DMA);
( |3 Z6 E- r+ e: w) {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ^- @5 p9 E4 }: _0 F/ Q3 M$ WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 k( i4 h0 y0 A: NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 o- c2 f1 Q- {" D# P6 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ f, }! l; j6 ?7 G- z( m$ G- \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) s+ t* P2 D3 l8 ^! N0 h9 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% Q2 {1 I/ q9 M9 F B% {1 k9 D) n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 b9 X1 |8 a: j5 e6 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 P7 v! `' [4 m' h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- g; |1 V! W' `; w; O0x00, 0xFF); /* configure the clock for transmitter */+ {: h- P5 D7 r5 j+ N- \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 l- D1 A4 {" W9 g6 _" y! BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" q- x8 c3 ]# Y3 Y1 {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' k0 Q9 c. f. J4 W* W; U9 n& [
0x00, 0xFF);% x) Q" v$ X; Y* i. l' R
9 O3 u- e# B' d" x8 z- j3 d/* Enable synchronization of RX and TX sections */
3 B2 Y+ Q6 l2 m+ M* x- f& Z1 t6 q7 F- |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% v4 G6 d- q/ S" DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% i$ Q( T+ _9 N7 U( x; W0 F5 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 |+ C' }3 S5 j. J- F6 \# r** Set the serializers, Currently only one serializer is set as
1 V. B$ l" O* N( ?1 l8 T** transmitter and one serializer as receiver.
- m& R+ w$ M6 Z ?4 i*/
0 P8 F1 b" I! I5 ~& F! ~! y9 u oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( M4 P/ [6 H0 f( RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 J, u) h' _% K, D5 z, F* ~** Configure the McASP pins ; r' ?: M. S$ Y0 o& }
** Input - Frame Sync, Clock and Serializer Rx
- C7 G0 L5 i- }4 S- v** Output - Serializer Tx is connected to the input of the codec ; ^8 n/ O" g6 u; Y! i" R
*/$ F/ M5 i6 P0 |" [+ h: q' d. `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) i$ i, h/ H9 w1 {8 h3 M7 w: v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, C4 j# N' A8 W0 W; zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 y' \, q, @' V- W. h1 _) e; _
| MCASP_PIN_ACLKX0 y3 c3 h* o1 s& ?. \1 N5 C6 K; ?9 x
| MCASP_PIN_AHCLKX* ]& t5 c4 c! O% r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. I, \1 x! x1 J! s, y* Z5 o7 h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR j5 u' x- G) [) X4 W* P* O
| MCASP_TX_CLKFAIL : L2 l+ l) O$ O/ p- [5 J. E" k
| MCASP_TX_SYNCERROR |# B$ |1 z. N' n& ^2 f& j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " Z& d' ]8 S8 S9 R6 D
| MCASP_RX_CLKFAIL4 B0 B! P/ Z: r: u. P' q
| MCASP_RX_SYNCERROR
- c3 c# o9 C- n| MCASP_RX_OVERRUN);/ ~2 O; W+ w4 N9 l. T9 [3 ^
} static void I2SDataTxRxActivate(void)
K' T( A4 o+ V" h{, C. v4 R. M+ I6 [# n
/* Start the clocks */
* G6 u, N, F8 U1 L# zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# V. Q* {: n" @) W3 ?$ r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ w* F. Z, W2 _" Q: ~4 L5 ~6 G. LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: B5 i; ~3 N! m, z" @EDMA3_TRIG_MODE_EVENT);2 M, U ~! f8 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 \3 R8 e1 E1 Q8 W4 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. Y: u3 O' ]3 g4 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' }( U( d% @0 KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 }, Q# u5 G# hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, k8 n# u5 _' I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 j( @% r# l6 u6 ?9 I4 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; B8 t% q1 [6 u& j}
' M9 X( b- J- x( |2 Y% ^0 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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