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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# `# ]1 {* _. Q
input mcasp_ahclkx,& G) r/ h/ l, M
input mcasp_aclkx,+ {- L' f+ c. m; g; X; ~( V
input axr0,
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0 f T* F- ~' W9 Z8 \. ]output mcasp_afsr,
6 n* Z# ~; E$ X4 d" B: d. Voutput mcasp_ahclkr,! ?- W. u" Y( `" W v- f1 y, i
output mcasp_aclkr,
$ m7 c( P' W) ~, Q% Zoutput axr1,1 S7 X1 N/ f. P; i9 _3 ?
assign mcasp_afsr = mcasp_afsx;
$ E. x; ]" `+ V$ o+ n& qassign mcasp_aclkr = mcasp_aclkx;
$ R: a& Z* s& _8 x! m6 s# hassign mcasp_ahclkr = mcasp_ahclkx;
4 t6 q1 Y& {+ e& J) iassign axr1 = axr0;
4 b% ?7 K( A+ X" M5 B+ u$ Q7 a: P7 r) L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 d) c+ D: X3 R3 `) v- f" rstatic void McASPI2SConfigure(void). U0 A# D# [) ~9 e7 D+ h! ^
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( U) r% X, x$ \" ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, o' V# _. n v& p# m' x0 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& i9 V% m* \2 J. q7 ^0 ]* O" ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 |& i- r y' U' qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 [1 x9 B; ?; I3 C, w7 S/ M$ }MCASP_RX_MODE_DMA);
3 a& c$ h& I* e# A& v0 I# wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" T- |: }, s: Z. hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, r" B6 ~2 t1 k$ A5 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 [% m7 R/ s0 r* w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: b: M# |8 l; T2 g: @0 f/ r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- R# \6 e! J6 |8 f% ]+ C1 z. b: PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 X+ @! p2 s6 l4 V: o% P8 eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. D4 S) Y* A% s) A; I- I/ vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 G; I" E4 V# b! h1 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* G2 Y. c0 Y- \7 G$ }
0x00, 0xFF); /* configure the clock for transmitter */' t T1 O$ G, i$ m7 j+ C& D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) M4 r, Q; N) I7 r! O# }1 \8 D* }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 l, T1 h7 D- G" {2 w5 E$ n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: y4 S7 S* _( K+ \# h0 F1 {
0x00, 0xFF);
2 R# ^+ W* b6 x* ]& ?- u8 A K: i2 Z% [7 _* @4 G8 E
/* Enable synchronization of RX and TX sections */ 8 ^, b- [% C- U7 e6 u# J; z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 M* K8 P7 _' p- _5 n% gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" w6 w3 J% h: t d2 d8 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' U( k) a2 J: b& \9 F' v9 K** Set the serializers, Currently only one serializer is set as
! R/ o4 `7 c& q+ M* ~$ Y- T** transmitter and one serializer as receiver.
; v" I( T1 v& a) L. e/ L P- x*/) K: j8 e: t$ T# e5 ?( a! O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' f/ R: ?! U0 T( `4 X* y5 d# Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% X+ E1 h2 O& J |4 r# @7 W# j
** Configure the McASP pins
1 ^; {3 G1 e: ^/ U' P** Input - Frame Sync, Clock and Serializer Rx; Y/ w6 p6 h& @4 B
** Output - Serializer Tx is connected to the input of the codec
4 t, G! J, k! C! c {' V. s*/
, z" l; o( H, Q/ c! `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- ^$ E3 z* Z* ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& b. j& W/ M: b0 vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; L) h$ o3 j1 Z0 s9 A0 P/ x1 o| MCASP_PIN_ACLKX* b, F: |3 I. |' y P R
| MCASP_PIN_AHCLKX
4 R, E+ E$ b& G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. l) o0 B% @8 Z5 Y8 B6 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 y0 u/ }, c+ i2 O| MCASP_TX_CLKFAIL . a+ A3 f9 P; i7 G/ J
| MCASP_TX_SYNCERROR
: q( ~9 C' H8 |8 H1 L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; ?3 i+ s# C; S& n# j
| MCASP_RX_CLKFAIL {3 u2 C- a+ ^. C0 U
| MCASP_RX_SYNCERROR
, L% ~# a3 ~+ D6 i1 x4 I| MCASP_RX_OVERRUN);
5 B$ l7 ?* b: P) X" T4 l7 R) m} static void I2SDataTxRxActivate(void)( {& L! b6 W$ W+ ~" V5 a
{1 P. i5 n8 ]: }- q$ m: a5 u
/* Start the clocks */
) q- l/ i; p: T, |4 P9 m0 X! cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( s* `, D& |! w4 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. T4 A D" G3 g* g- V" R3 B3 n/ K3 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 r+ y: J& Y/ D. _$ D
EDMA3_TRIG_MODE_EVENT);
, s& j+ o( _1 |0 g: Q* ~& Q; A/ e: oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , }" \! E# y, p8 s$ C+ p: A6 P% O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- b; i2 g' R+ N" d4 T' }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; k& y% `' A( J1 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& U: S3 A% n+ E1 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 a1 g4 f' U3 }! FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: u7 b) N5 v9 m5 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. \) h, b. b- X8 ~5 y/ Y} 0 h2 a9 t& \& N# |5 A( r( }0 T0 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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