MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
5 T  o- a7 ~, o- Sinput mcasp_ahclkx,
- v* ]- L" m4 ~5 F/ F; K# T% u' N  hinput mcasp_aclkx,
input axr0,
! F' w) c! E! y; m/ ^( Z  x6 i
output mcasp_afsr,
output mcasp_ahclkr,
2 I) |' F9 u" K: o* aoutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
& o: w" D# j0 F6 A  p* iassign mcasp_aclkr = mcasp_aclkx;
9 j  z1 Z; |* b- ~assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

" l1 m7 O  q; `3 q

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

8 X- s4 m) S% u+ s* z  M( |  g# Z

static void McASPI2SConfigure(void)
: L. d1 X; D9 F0 g# J+ o7 c) O{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 E7 z2 G5 r! l% U/ y7 }' \' lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
. h* L1 Q9 f0 ]8 @" d! F: {) EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 h' t( B0 a- d- w0 f, N1 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, w* ~$ _6 A! e2 w1 a4 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
! W( p+ ^6 U2 r  o5 n: ^( yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% l1 t( `2 y7 j  q! G; aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) e8 D' ?/ K9 F: t2 j$ x0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ j3 M; e& m0 d  [6 G/ kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
) g8 i& s7 w" P: B4 m% `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 s* _7 W1 S* B3 X3 V1 i6 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
6 c, b0 D3 L( x6 n/ J# N** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
/ T  C+ v8 O+ a& d' s) V3 {0 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
& i% E: T9 S' `( z4 ?; _/ F** Input - Frame Sync, Clock and Serializer Rx
3 N% _) {- o* O: y, ]** Output - Serializer Tx is connected to the input of the codec
! |' W1 Q& ?. E4 O: f; t*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 D* s$ b/ P5 P& JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ E$ e3 O' b5 p4 O3 d| MCASP_PIN_ACLKX
, l: k/ }, y+ S| MCASP_PIN_AHCLKX
! z+ i9 C' w$ z8 r; S1 x| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
8 X1 N* K- ^2 o$ v- MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- R* t: K0 N* c| MCASP_TX_CLKFAIL
1 I5 y+ ^! r; W) i; P$ v| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
& J* o, m4 b7 I& C# C, \{
9 U# C; b; i: C/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
2 ]" {% n( M: M) cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* ]! u/ \% Z0 A+ z2 F! J" \! WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 k  ~0 B. d. k8 C: {. D8 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ a) B0 ]/ e4 z3 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.