|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; p# A& O& X$ }) L$ x6 C( h/ P6 ^
input mcasp_ahclkx,7 a( F) t: }3 \8 d/ q
input mcasp_aclkx,3 o @8 ^3 }% c' _) J) ]- C5 j" o
input axr0,
, c1 E2 Q* p0 \. R7 k
( e3 n0 U% F$ c3 Z! J3 ]3 Houtput mcasp_afsr,
1 `) O, [# n& e. y. W8 [# ]output mcasp_ahclkr,/ I: Q4 Y; r I x1 e! _1 v
output mcasp_aclkr,
3 R6 e2 a1 O& M5 g2 Y7 V9 A( Qoutput axr1,! O x* o+ h* T* j4 J6 V8 A
assign mcasp_afsr = mcasp_afsx;& P$ T: q T2 |5 V, X" T
assign mcasp_aclkr = mcasp_aclkx;; J6 ^! K4 H; j% b6 W
assign mcasp_ahclkr = mcasp_ahclkx;
; q1 J; y% i+ p& x$ Rassign axr1 = axr0;
0 N; p, x$ A7 }# O& Y9 s1 G3 z. h! }' A. B2 c9 |# ^2 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , ?+ d) m4 y3 m1 L7 T5 I1 }
static void McASPI2SConfigure(void)
- [! @' R" e" o{. Q/ l) Z* U) @- q0 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 O* |5 ?' S( Z# U, q2 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 X. l: _, z5 Q9 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. \1 f0 ?% J' E G7 a4 n" l* _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ }+ [* b* X, U5 G4 x& Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; D4 ~4 U ?2 S
MCASP_RX_MODE_DMA); K5 S9 x9 P$ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 G' l( z5 z4 m5 Y+ FMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ X% p. V8 l$ t" v( I5 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
q- j2 L9 q; E: ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ ]. k2 c" k) SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 Z/ o( A; t7 x8 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ D1 c) ~0 g( V& t8 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 @' d* f; N9 W3 {6 c$ J r4 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 V3 u9 K, K2 q- ?/ r$ QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 J, o4 y, w: i$ w
0x00, 0xFF); /* configure the clock for transmitter */
/ H7 H) ]. s/ S2 u I9 v: AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" y2 [+ \' l; r) cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ m4 A+ J+ H; L5 ]2 ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 C& _4 B8 N# X0 Y# F$ a# D
0x00, 0xFF);
4 G+ R; z; P# l( Z1 _
$ p5 v( j9 s4 L7 T* H. d2 V/* Enable synchronization of RX and TX sections */
7 S0 \+ k$ X$ z S! H. B: \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( g; r; Q" Q( ?6 G4 UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 e# {, d: L/ D; z+ A/ ?. P) a6 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 G7 A2 m1 R* g; G8 j
** Set the serializers, Currently only one serializer is set as7 E8 `0 j2 j; j# y- @
** transmitter and one serializer as receiver.* Y- Z9 S* a4 q3 w
*/" \8 p$ F$ Y5 I( [( Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) S y1 p- o& T5 V, m0 VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# E$ T% q* ^7 X X% \2 m1 Y
** Configure the McASP pins
2 D/ A/ k- k5 h3 J# X% t* }0 N** Input - Frame Sync, Clock and Serializer Rx8 V q3 o/ ~: `8 V& Z9 k- [
** Output - Serializer Tx is connected to the input of the codec $ W) w6 u* q+ ~$ [0 E, b6 _
*/
; r) D' P: \. c! L5 o$ A* C1 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* C7 x ?! N3 D/ H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); G" @! Y* V* M! R$ R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: M( ~, S$ M3 [, D/ }. p; u| MCASP_PIN_ACLKX- s8 @5 p9 H3 H# F4 }+ `% f" H3 ]; Y
| MCASP_PIN_AHCLKX
/ J6 ]( l4 E3 g$ _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# S! I' G& j5 G8 m# q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 M N7 }2 n; C
| MCASP_TX_CLKFAIL $ s9 @! q! H0 G5 U& B+ X4 k
| MCASP_TX_SYNCERROR) |% }& P3 _; t# d. w9 J5 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. F/ ^5 z9 Z- z* e| MCASP_RX_CLKFAIL6 r \4 |' C2 ^ H) r- D" C
| MCASP_RX_SYNCERROR 8 A/ T* S2 Z9 Q* m c+ W9 \
| MCASP_RX_OVERRUN);
( K" _5 \0 h, c6 z} static void I2SDataTxRxActivate(void)
8 L1 h3 y4 O J3 c{
; E: ?% [" t' ]8 q" P: K/* Start the clocks */+ D# N( s3 e+ t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 V: c; o- Y# b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 z. }5 I" ?% _/ d+ e3 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* i4 i" L7 }" q& b2 d9 @* ~
EDMA3_TRIG_MODE_EVENT);' ~3 m6 h8 J+ @2 w4 Z7 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. y3 M4 T5 @4 i- ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 m: p# p; w; e! V1 _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 d3 C5 T A8 W8 t5 a$ p. ^1 L, BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* w% o) m* T% Q$ l$ ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& G7 B$ o& j; r* O4 ~$ n. F
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( K% k) u. P* u3 c6 XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 q/ Z) S! l2 }/ I; ^8 K* r' b}
- {- ^# G/ U- H) Q% \9 N C# @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) N- g+ v7 ^# {! S% ]
|