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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* O* h# m3 B! Y4 F7 P9 h& I$ x+ K
input mcasp_ahclkx,
' o0 e$ k5 B; x& d m$ ]input mcasp_aclkx,1 ~ N l$ j" `# t
input axr0,
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; p8 m) j# K- t: O. T+ M+ Woutput mcasp_afsr," m1 e5 [, h2 x1 ]# ]
output mcasp_ahclkr,
9 }2 r6 b$ ]+ ^/ v6 ]# e& I5 Routput mcasp_aclkr,
/ n1 [0 V+ m5 [: l2 eoutput axr1,) l/ G1 ]3 X! F
assign mcasp_afsr = mcasp_afsx;- p. A' Y! z& V9 F3 {- {
assign mcasp_aclkr = mcasp_aclkx; \8 \2 p/ k' N# N- O0 }! B3 @
assign mcasp_ahclkr = mcasp_ahclkx;5 |" E1 O1 A6 c# c$ V! c
assign axr1 = axr0; . I2 e" ~6 r/ @$ `% ]
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' q: n: s* f' e- g6 \) ~static void McASPI2SConfigure(void)
; N/ e0 s9 O* c( ]% j2 J. B+ g{2 ], C! F) O: }4 k2 ` F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 R9 { e5 p" W( {9 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: j/ E+ y8 _ t* ?8 f, m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- X# P) T; ^" K+ k8 K h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& `4 ]1 M3 U5 P6 d. d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; W5 c5 K6 _* D! d0 Q6 i# l) R! Z: KMCASP_RX_MODE_DMA);
3 t* ?- W' b2 `# N" h- ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 _/ _. f/ a7 T( E7 @6 z5 l b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# _9 j, p& y$ t! X& ^8 wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
N3 e. M" T; lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. n6 U# p; c1 @$ o9 a: n( HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 {8 u- h# z* i& }5 c9 l' M$ NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: j3 ]6 u" @! H% y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 }0 l5 w7 s9 F: rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : u# }( e6 a9 w- P; c, |1 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- i: B/ V" W& [" e" m- {4 H0x00, 0xFF); /* configure the clock for transmitter */
0 Z; ^% z+ ~% D, r/ ?* g& ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ p( g! ^" o" N$ g# M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 ?+ w4 y# H/ H2 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' i: w/ y5 l: T' l/ t* L0x00, 0xFF);
; N' }( L3 z C t5 D0 u f e+ j
/* Enable synchronization of RX and TX sections */ + }" O o: }0 x- l3 v4 U2 g. a+ @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 z9 } y6 ]: m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- K% W3 R* m) `8 q: a$ F, \8 N( T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ ~7 e/ L" N7 e1 }/ f+ ?9 H/ T
** Set the serializers, Currently only one serializer is set as) U: U; W) R! Q# K( L4 U3 |
** transmitter and one serializer as receiver./ K& t" T. B. @! g
*/3 b% e$ `% _! y: _. s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* ^4 p+ \' ^3 Z4 I2 i IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; \7 w% ~' s" u7 i8 _' [9 [% ^& i** Configure the McASP pins
# X' p N$ q4 T' k** Input - Frame Sync, Clock and Serializer Rx
% M4 t( Y# W$ s W) v6 I6 D/ G** Output - Serializer Tx is connected to the input of the codec ! |+ x# ` I% ?6 F! D! B$ Y- ~
*/
2 U( a( |5 j( e6 ~) lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, \& n( v3 D8 M, w: E# |6 V, OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 U) n7 m. S$ }" V9 Q2 X4 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. t0 y' X5 |2 F5 m9 ~3 `
| MCASP_PIN_ACLKX
: R- z! M" ?: y4 p) u: I| MCASP_PIN_AHCLKX% e$ C# \: G8 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* A# d6 x5 L& p# B6 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % y J$ e+ I* G9 X+ ?$ {6 Q6 z
| MCASP_TX_CLKFAIL 6 c6 z! l& V9 ?) |# |7 P1 ~1 E4 o: }1 q
| MCASP_TX_SYNCERROR
4 m* F; D) M! K9 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 B5 K( v2 h: J* ]| MCASP_RX_CLKFAIL
/ f7 Z9 T; M: c| MCASP_RX_SYNCERROR # H& i, q3 [6 D7 u
| MCASP_RX_OVERRUN);
5 n _$ ~" X) p- g$ p# ~) L} static void I2SDataTxRxActivate(void). e* i. G" }+ r( x8 f6 K/ @3 y
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/* Start the clocks */
t' i% Z/ m$ x& ^) O+ a: mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 {+ ~/ b0 ~- c, I$ i2 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& c0 p8 W5 S8 Q; r8 b! ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% P3 V% K v+ Y% `* x
EDMA3_TRIG_MODE_EVENT);
" A' s( w$ m$ N: F, HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* x' V* J: j# ] Z6 p; V) l2 p/ ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 ] u; R" k: F6 {; @' i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! h& ?; ]2 g' t: i$ ?. T o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& g! e( O. D: |3 C, Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: z |: \# I, F/ r- z* g; b+ o: ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% T1 W- ~5 P' ~( @$ [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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