MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
7 {4 S4 a* e! `input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
5 S4 B! a: G! q- \output mcasp_aclkr,
& `) G" V1 L7 t9 t. {7 l5 Routput axr1,
: I4 ?/ Q! M$ F) Q" _

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
" A2 K: S1 P7 d- V/ a  r8 bassign mcasp_ahclkr = mcasp_ahclkx;
. b" c: p& ]. |9 Zassign axr1 = axr0;

' h) \2 ]* M6 n- I/ V& L) u& @7 H
9 H3 m; g; a9 J8 D9 P0 C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 {4 B+ a. n: i) J8 \3 I, G7 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
4 a& d' E: p0 z6 v0 K" QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* z0 |9 f0 c. ?& v0 L' J" fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
0 b2 @5 t  x# H: K; I/ lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# @$ W( O- k" \" j& h6 M. j" oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 X: j; @& s# J* }1 Z0 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 M; ]- Z( ~, J  w& ~+ `* t* iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( R' t2 A: w; yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
/ x% d1 \5 |; q4 ~. AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* u" Y1 J9 {' I" L, c2 bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" o) R0 K: B2 `0x00, 0xFF);
. D5 q; p# l1 h; j) X
8 T& G0 r$ G7 ~4 |6 M9 e7 f1 i/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
. m! H. u' Z# Y( K6 T1 y* jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) V# `4 H# |5 B5 m0 t. {; vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
9 t" R3 |7 d7 x** transmitter and one serializer as receiver.
*/
0 b6 O* t# p4 ~/ ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
" b+ m4 d! o% S3 T** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
) d! m+ }; M% A. d: O' }*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, U- L* a4 R* }3 \+ `, r6 t* c6 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. H) L2 v* K3 h: ^% Y; CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 j2 d6 R4 [! S) l( I: \| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
/ Q; S/ ~, t, ~1 z& l7 m9 L5 `| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. S% d% m% V- ~# b+ i& k| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
6 A3 `! J/ m4 z: u8 b9 ~| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) z+ Q4 Z& H+ @* A* l$ F| MCASP_RX_CLKFAIL
' [' b+ a* }; A( G2 G| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
" f; q- g" _+ Q6 B! g% _}

static void I2SDataTxRxActivate(void)
. C# r" k% b; @! w{
/* Start the clocks */
1 ^3 _, X# ^+ i! k4 W: |7 a$ ?  pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; W5 ^6 O7 x$ }. D. u% hEDMA3_TRIG_MODE_EVENT);
- v8 w" @* `, D& E9 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. N7 @  a. d- ?" wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. l) |- o  v4 W}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.