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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) S# E! X0 V0 q- A. xinput mcasp_ahclkx,
# t& x U0 ?7 ginput mcasp_aclkx,3 `+ z: H5 S' Q) |, _$ K, Q
input axr0,
+ D) {" @ c/ r( T7 N: Z9 e. i6 D" W8 U3 Y9 p* ~' p6 F- h
output mcasp_afsr,% L% x' u: P0 t( x2 q
output mcasp_ahclkr,
6 c* h; R. n; v" O, X+ h' }+ n7 Eoutput mcasp_aclkr,* V+ g; n6 {6 O0 f9 D& H, C0 y
output axr1,
$ \3 i- i; s! k) \3 C2 Y# O) K( K assign mcasp_afsr = mcasp_afsx;- A8 P4 P6 K1 `3 l" F, n0 n; _/ w/ ]
assign mcasp_aclkr = mcasp_aclkx; |3 C9 M8 d/ p" p: \
assign mcasp_ahclkr = mcasp_ahclkx;
4 s. R) S1 `( e2 z+ ]" Nassign axr1 = axr0; ) s1 w/ `- U% q) b! {2 n& _
2 l% S; v+ X# s+ Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 F$ _$ F$ l* n+ s: @3 y$ n
static void McASPI2SConfigure(void)' t1 ^( A( J) W! |: \- m" m: K6 {
{) L- ]) Z& e2 W/ v' I8 \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ L; B6 K7 r6 C5 ?4 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% T0 A. Y" K$ I; }2 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( @* n2 D; s* P/ ~( J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, m# }5 m' _8 u/ M- e1 ]# eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% v/ o4 m: z+ b4 A/ j+ f; Y8 F8 |
MCASP_RX_MODE_DMA);
1 |3 P) V% P7 J/ e9 o& c9 QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) r, I) d1 ~' z1 d5 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 @$ s" w9 ^$ f# }! r% X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- T5 [: Q2 U8 J& qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 p& F( m2 `' o) mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' z: E4 B: U2 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, H3 q. q* b+ z5 [) I5 |) o# TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ f( J5 r1 Q0 U$ q! j$ FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - l5 ~4 J& `: u y! P7 z6 X1 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) [- w: g! T' l% l# k0x00, 0xFF); /* configure the clock for transmitter */- i9 D% J2 n6 c$ x5 O6 E, A9 C2 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& G5 r) Y' d9 Z; j- E* ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 F' r, H, D9 Z0 m. eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) p9 ]" Z1 l& D0 Y6 I7 p" o! C0x00, 0xFF);' T( ^9 w, i' {. r/ s# o
9 b) L- b3 g$ k. i, P, e/* Enable synchronization of RX and TX sections */ ; N% g. N: P$ N) Q8 ^! J: K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% ?# R: H z' B! L3 K; Y9 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; J0 A: W7 V/ F" t- ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* S; F5 L1 Z* M4 r! g n* _: ~
** Set the serializers, Currently only one serializer is set as
0 |" n- G# u: n* w** transmitter and one serializer as receiver.
# {9 J" f& v4 b( x3 P& f' C*/1 K- k, h, [' ^. Q) M; {6 z0 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 n9 A2 q# a; Z# x) o5 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ H. w# p: ?7 s r4 X** Configure the McASP pins
3 f1 |- h3 q2 M) ^. W: f+ I( ^** Input - Frame Sync, Clock and Serializer Rx
. v, c% Q5 e+ `# X7 v* Q** Output - Serializer Tx is connected to the input of the codec
6 z9 Q: G9 [8 [8 V*/# q d& G/ a7 ^7 |! V( T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); P v4 F) P% x0 E7 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ F1 V% y# ~* T8 V" m$ C' iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. X: P- D% ]* ?0 e/ S1 j| MCASP_PIN_ACLKX8 h9 d) s! z8 Z$ {, y( s/ z& a
| MCASP_PIN_AHCLKX
8 C7 h* k) w) \* V2 g0 C$ L* e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) h, N6 d' v" _/ M ^7 e$ {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 t* W$ _' m; A0 M( i0 L% W
| MCASP_TX_CLKFAIL
, g2 l6 w2 G! Q; s `| MCASP_TX_SYNCERROR
% f" V7 F! G/ q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' p5 l& _0 t$ i# c ~
| MCASP_RX_CLKFAIL4 M# v% l) H- ?% K% z
| MCASP_RX_SYNCERROR $ k" f# \) d) P7 b- i5 y. I
| MCASP_RX_OVERRUN);
Y+ X F/ {: h7 |3 W( l: k} static void I2SDataTxRxActivate(void)8 v- ^/ U( `( J) Z& ?
{
6 i( X! Q& v# l7 k1 B/ Q% A/* Start the clocks */
2 _5 p0 x3 B2 C" vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ K, ` N" O8 @# Y5 Q0 }( PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 `! Q0 [5 U( e. ~4 K4 m: I, R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; e N9 M. _8 O
EDMA3_TRIG_MODE_EVENT);
# n0 M [6 o- [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 F! P+ ~0 M: a. t* @# A- ]( E1 uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 r, P( a8 a2 L: \2 Q, {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 B5 x d E' x4 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' \" ^6 A2 C+ j$ ]# S& D7 \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* A4 S0 N3 ~- J; s# \, R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! U5 E, f; a9 K( k+ _' h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 A7 w, E8 J7 T& x+ c
} 0 y# o$ T7 I3 P) ?9 g& n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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