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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, J8 [3 c/ r/ \
input mcasp_ahclkx,: L% }; v( b$ s% Z' W- H5 q' w1 ~
input mcasp_aclkx,
0 ?+ G& ] g$ M Y- Tinput axr0,+ }' s9 L7 H0 e" r! ]
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output mcasp_afsr,
- C$ i3 o0 L0 w, Q( Boutput mcasp_ahclkr,
6 Y, W5 y$ @5 x1 koutput mcasp_aclkr,* B- O8 B0 N( k( Y9 L
output axr1,6 V8 I( O+ `; s& C
assign mcasp_afsr = mcasp_afsx;& K$ Q0 e# q! U. J
assign mcasp_aclkr = mcasp_aclkx;
% l5 k% M- I. f3 X9 lassign mcasp_ahclkr = mcasp_ahclkx;- [; u9 D* y* _* m3 j8 S% Y
assign axr1 = axr0;
7 X% ^( c2 f- e' }& e- m6 v8 f6 D2 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 Q: Q, S/ M- c, J9 `, i. Jstatic void McASPI2SConfigure(void)
' ?7 o+ H7 I) K1 ?, A7 L$ B' c- ?' `. I{
: W9 u/ K9 | }! f" @; rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# Y) g5 ~9 ^; x8 o3 s& O. eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ t& l6 M" o. i- @& [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# M4 ` m8 \8 [+ x- F0 {3 LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' H8 e s9 W- l, u8 dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* C) r' B; o ~1 x! L9 O7 Q' g
MCASP_RX_MODE_DMA);
* H* ^9 |. A# U3 m) kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* E5 @: ]5 O% ~) v9 B2 o8 n0 O6 zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// s9 s' ~* R* N9 U4 X& @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' ]- T0 D1 f: r/ [: QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 g$ c" [9 s |, _- M& J9 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 c% M# I8 o5 M% V! }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 ?4 b1 G' `" {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 ^- r, w" O& `7 C1 n; O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 f* W5 w1 I4 S4 ]' g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 @8 ?( c4 t: g# U
0x00, 0xFF); /* configure the clock for transmitter */4 z2 d* j/ w T/ H4 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ ], j; z4 i: wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: ^7 U+ K6 M0 {; Q- [& _+ x1 Q* fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
]+ F0 ~1 U, r+ A& k0x00, 0xFF);
; h# K6 T3 D% D! ~; C7 \- m! k9 M2 r9 D% C# f$ q
/* Enable synchronization of RX and TX sections */ : l. N/ Z0 n9 ?& B- z4 v: P8 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" G5 d( b6 p5 X. p+ x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# h) ~7 C( D o, y1 m* S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- W8 [3 r+ e9 C; v( |) u# m
** Set the serializers, Currently only one serializer is set as
, Y6 o n8 Z T( u9 j1 R** transmitter and one serializer as receiver.
6 H( n( G8 q q2 o3 v*/' V2 D2 W* M( ^2 O) \! o! W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* m- w1 x* h# mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 P) a3 w1 L5 N** Configure the McASP pins
- A8 q/ N/ f* [) O* Q% W; A _; ^* }** Input - Frame Sync, Clock and Serializer Rx, M9 X( Z7 t# Q) M1 J4 I7 A
** Output - Serializer Tx is connected to the input of the codec 9 q9 p* ]$ M- M7 f
*/
" h. W7 t/ y8 D6 d6 s9 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* P; ]: x" U3 B/ j9 z8 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ C1 [ w0 H1 w- ]. ~ XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 Q, \6 b$ [7 B% ?
| MCASP_PIN_ACLKX
" ~- F3 f! w) j- b| MCASP_PIN_AHCLKX
( J; {8 C6 P4 U, T6 ]3 m- w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: z. e* g; q2 P( x/ YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( H6 U D$ _* s% I/ j| MCASP_TX_CLKFAIL 9 M K0 r- j# \$ X5 J
| MCASP_TX_SYNCERROR
i( L: l i9 \) Q7 T* f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' Z2 t/ d9 O t( u, M r0 r5 N
| MCASP_RX_CLKFAIL
4 @) y5 {4 ~4 Z# p/ I2 w) D3 y| MCASP_RX_SYNCERROR & J3 b: r4 {0 X; m4 i4 B" b" H
| MCASP_RX_OVERRUN);- J# ^) _( I" d q( w3 m; ^
} static void I2SDataTxRxActivate(void)
0 [/ i- K( U: m% j{
! b* J1 v( ~$ q8 F7 l$ y/* Start the clocks */
% N! b( |! D" W: @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" b6 U7 @8 m6 e5 l8 h: vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' d$ ]$ ?* r5 t7 ? C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 U8 A/ U9 s2 z; D. M# S# z: B
EDMA3_TRIG_MODE_EVENT);
' L/ S' Y& z/ W% iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + j2 I& Q% ]. h3 E/ S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ^ F6 Y, j: ~' a+ Y4 |" o S# f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 Q" o5 z+ X+ [! G" z+ w* B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 |2 K \. Y# `5 ~, w5 i6 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
q0 \ E {" H) K! fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' L: o0 y! d Y7 `" v$ i3 P/ z$ |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. k# D; t f5 b) `- V8 x# }
}
# w- |5 \* a% A8 o' e4 W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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