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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- b1 }2 r9 }4 U! o" O9 E9 r8 C* _
input mcasp_ahclkx,
! U4 t4 y1 z/ |. l Minput mcasp_aclkx,7 d) Z0 `6 D2 W2 [4 \
input axr0,
4 \ ^6 v! Q# R3 g: a2 U8 J: G9 y, j- D
output mcasp_afsr,
/ G0 e( ~, s1 T9 `+ ^5 X+ o# ^output mcasp_ahclkr,
/ W7 E6 \/ C* `% R* \0 H1 T" P/ @output mcasp_aclkr,
" E4 a: v% P2 M7 f" T4 foutput axr1,
: h$ H5 x8 k7 O) G% b; w( D# I assign mcasp_afsr = mcasp_afsx;: x" O: l% X3 f; N
assign mcasp_aclkr = mcasp_aclkx;
. c) p7 f3 F) n$ A' Wassign mcasp_ahclkr = mcasp_ahclkx;+ o. r8 T4 H7 j3 Z# t1 r$ q
assign axr1 = axr0; * f% D6 u* @8 p2 b r# W C$ m
7 ~ c' b4 _! q! l( q# \* H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 |. S# }* k% s- C8 Lstatic void McASPI2SConfigure(void). w8 Y) p% H0 p$ f: X. \7 H
{6 d& y2 ~0 e! N; o- u) e j5 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 v3 D- H2 Z/ G6 u% ~0 X" G+ ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# d! `8 {( Q, r; P4 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# F( u [) p! T0 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 b) [/ v' E* ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# {9 s0 ?7 C' B7 Q# ?
MCASP_RX_MODE_DMA);9 C3 R; G$ ?) @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# B5 R" c! P) e1 H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 V6 W( ]9 [7 U$ M& a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! C+ T2 `; C' J* pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 a; q& {- k2 L3 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' n q, F+ P! W- T4 y- DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ?: K& c- B! a* p1 e! F# dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 W9 C6 ?8 }" dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! ]8 x7 _; a/ h2 G5 ~* J1 v6 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, X- O4 z7 N3 X; v
0x00, 0xFF); /* configure the clock for transmitter */
2 R2 u6 U' ~/ b* b h+ f/ s7 uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* ~8 r$ d* z5 X+ t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 s! l2 I5 g3 ~, ~: q: j8 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; I5 p! L: x0 ~2 j' e/ F
0x00, 0xFF);
2 Z: b" m6 N* d7 D! ]* j) v% i& b* `$ U* w
& H! [9 w+ z' y% f9 g% g/* Enable synchronization of RX and TX sections */ " u4 ] i n; Q% d m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( ]7 {. T) x# z. o' ?8 b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) P- T5 v" ~2 k& S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& W/ T6 u/ N/ [8 ]' h' q** Set the serializers, Currently only one serializer is set as7 f& H& D( x/ z& {/ s
** transmitter and one serializer as receiver.4 \) I9 P2 t" O1 S
*/
9 J# K* P+ E( d* L, Q% sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& T [5 Y( U1 `, p, w) nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! m3 V, o( n5 e* J* \0 ^. D** Configure the McASP pins ; `" q* ?5 S C: H% ]9 j. s
** Input - Frame Sync, Clock and Serializer Rx
8 [7 L3 P+ z0 R* e$ M+ Y** Output - Serializer Tx is connected to the input of the codec
x1 }$ Z7 i C9 T3 H, _*/
% L% D9 Y6 e. j: eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& B6 G3 T* r. V; u6 N! F; ?1 O9 aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! z7 M6 d) q6 Z" u6 J- i. L4 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' f4 x4 t t2 ~2 L6 Q* B3 c| MCASP_PIN_ACLKX, t/ I5 U& x+ G% H B
| MCASP_PIN_AHCLKX
% X/ [' H$ {- [( e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- E6 F. c6 v4 w; K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : Q+ k3 ~8 L/ F. ?
| MCASP_TX_CLKFAIL
+ K; j& r' v0 N& j/ i# M( `9 t8 b| MCASP_TX_SYNCERROR
( e. X& k, E. V5 k2 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 B2 r/ P- }# F% }
| MCASP_RX_CLKFAIL
- l, j9 ~# [0 N| MCASP_RX_SYNCERROR
! Q( S' w' i! d) y| MCASP_RX_OVERRUN);
2 }& S7 j5 T. {8 G4 O} static void I2SDataTxRxActivate(void)+ [0 E* s. h" w' |0 {- Y
{0 X0 X+ u2 t( k# M) j% {& G
/* Start the clocks */3 s: i8 l- m% O6 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- e4 m K9 V$ @ e2 |! Y# G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ W$ e& b# x4 ~( X) g5 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% ?- d! j z. E' n! x, H \
EDMA3_TRIG_MODE_EVENT);( A9 _7 H% s- g) y& X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! [9 ]7 U8 b" a$ Y/ K i0 d1 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& f$ H4 s. B) c0 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 q; Q, o% N& D' a2 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& }/ X0 B! _1 R H' Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; @4 e6 A! i2 K1 e' \" G, b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 ^8 W* C% W3 y$ N% q) Y( TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! ~* h0 E0 r* A# K
} % b+ V5 ^# V" l/ M* ^9 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # k% A3 ?5 }, W
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