MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
' e* `) o+ V8 x; |# i$ f5 L7 O* P0 @4 ]input mcasp_ahclkx,
input mcasp_aclkx,
$ i, G2 ?2 ], `1 O. v6 `input axr0,
) w3 i" u0 N% s6 `4 h% N: L
8 j/ C9 R8 P% Boutput mcasp_afsr,
, ~( Z) b9 E: N: j% Poutput mcasp_ahclkr,
output mcasp_aclkr,
. K! a+ z, R8 @2 d3 J: Loutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
8 @7 k- Q! {6 l8 ]( qassign mcasp_ahclkr = mcasp_ahclkx;
! h- F, }$ l! t: h  Y+ ?assign axr1 = axr0;

, }0 G1 m- z  w3 k) z: F  c; }

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
! a, P" `4 P1 z/ B: XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) _6 Z: P1 b1 U# \McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
& K8 r2 y( E6 L/ `( WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 ]8 m& h6 c  fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
1 G( I$ W1 D' R7 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
: l  O0 ^" ?2 ]1 X& ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% k7 c! G* i+ ^1 O# }1 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
4 {. n* {4 E- t/ }6 K6 C. E* I: oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; t' W. p- W: T: q+ t# DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
9 i" @' C1 \& X- L7 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" c, _2 U6 p2 d( d- wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 C9 x3 P& M  ^1 r" z0x00, 0xFF);
- ~$ A; m7 ^2 a  h
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
( n7 g( d$ C+ f3 a" C' jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
7 \- v: ^7 Q3 t! q7 X8 w5 f1 r) N1 O7 g** Set the serializers, Currently only one serializer is set as
0 R* H# u7 |* P7 W" `: x** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% D3 W" k+ N; `1 G2 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
& s) m% Z. ~/ P5 I** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
9 P- m/ ^, i7 r4 M** Output - Serializer Tx is connected to the input of the codec
*/
1 {6 a- I7 i/ E* P; kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ g* s& ~4 R' s2 E: p+ sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
, J9 D5 q0 i' M4 _1 A* }| MCASP_PIN_AHCLKX
$ B8 e# s5 E( C( l' |0 z4 ^| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
8 a; i9 ~& f3 [, H$ s6 O8 _% w. X| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
1 ]7 j/ d, d4 l  N- v| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
7 [( L2 ~2 k( Q* q/ z}

static void I2SDataTxRxActivate(void)
{
" h+ }  W# M  o4 q+ \  A3 N/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: R4 N/ O- W& E+ e6 M9 G. lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ m* F. E8 q( r% n' B0 q* h  X, rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

/ I/ U) v4 H) ^3 h0 ^9 F7 V