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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 U/ N& O9 x+ [; i0 ?9 ]
input mcasp_ahclkx,0 c. @) }% r. P4 e9 W9 Y$ n6 J
input mcasp_aclkx,2 H5 m. u, @+ \# k5 M& \
input axr0,& R- S6 F* w2 {0 |
7 p. _. q% X) ^- ?& a9 w! `7 M2 Coutput mcasp_afsr,( R- h1 q- b0 A( f
output mcasp_ahclkr,
1 v" i1 p" B" Y5 @- D" i0 poutput mcasp_aclkr,- f5 s1 n I' w/ _+ y
output axr1,7 w/ r) [2 [6 T: m7 V
assign mcasp_afsr = mcasp_afsx;: b' C& N* H, Y; W- X
assign mcasp_aclkr = mcasp_aclkx;
" r& x- N2 O1 g! `; eassign mcasp_ahclkr = mcasp_ahclkx;
0 m1 j3 U3 m0 }/ U8 a8 C- ^6 e5 [assign axr1 = axr0; 4 G0 B ?2 X7 S x
7 P( D4 B6 ^" A9 `0 J) n
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 S6 R/ L) }$ I/ l$ v4 h
static void McASPI2SConfigure(void)
; S$ f7 L) |' m4 z: c, Q% f{, ^0 ]3 X# q, q: {2 t! d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 k9 I" y- W( n( m: `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 f. n4 [- n% @4 i% }: o# d: m% uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% e/ x! Y% t' c( k/ D7 d$ j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 F% }; j* q; M0 Z( x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 y! {, w$ @9 t/ n+ NMCASP_RX_MODE_DMA);
+ A0 e7 m* Z+ w: hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ x, E i* `+ I1 k3 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 B' c1 ?% ?( d6 b( [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ x& V) k) X S/ ~5 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 W+ t0 P x" p3 j. d3 E1 Y. Q* V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 ?6 W) T9 ?# y- a; U( LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: E1 t6 v' V; q# NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: n- m. c9 K3 X* hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( m/ {( s8 ?/ B) F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ G T+ z: u* L
0x00, 0xFF); /* configure the clock for transmitter */' Y, p5 [' B" ]$ C/ q( c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 d! w O6 Y2 N o& p2 { B8 d' P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; c! F8 t) R E* w+ I5 yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( g: G2 {/ B" V" h: n0x00, 0xFF);5 D4 U: E2 T T$ g/ W+ X
% r/ c! g7 {$ d0 _$ _' \3 N+ G2 x
/* Enable synchronization of RX and TX sections */
& w* h1 _" q$ n8 n0 ^; eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 p/ v; I& @' m( L4 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 v+ F/ r9 e" m& uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# ~3 q0 P; t! _ }* ]& T
** Set the serializers, Currently only one serializer is set as
7 o/ _! u% x* u% M. F9 a** transmitter and one serializer as receiver.* p) I$ y7 W6 }- n8 l' e
*/
5 [9 e' K& h1 I% I7 G; ]* ^+ mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( P1 n4 [5 c, [' [, j6 G- F* p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 O- i" s7 ?' N1 a# k7 t** Configure the McASP pins
" f/ L; _) f. \4 b, z2 B0 @; F( t) V** Input - Frame Sync, Clock and Serializer Rx, `5 y- @! X( \( ^- B
** Output - Serializer Tx is connected to the input of the codec ) c) x9 G0 ~1 B# \2 ^+ K) O! D1 Y
*/
- N" h7 M( W& S7 k1 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& Z- n4 e# l: U+ l. xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: s5 @2 p: V' I1 X: U& H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- d. d: ?) |5 Q
| MCASP_PIN_ACLKX
$ k# r4 k9 t7 [- ~| MCASP_PIN_AHCLKX( j: |+ L' G% k$ F1 u, E0 b# l; i, f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# y1 {2 X: I" [, m+ L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 ~6 ~6 S* C. T; I
| MCASP_TX_CLKFAIL " n8 f) ], X5 Y6 u% H
| MCASP_TX_SYNCERROR* @0 H: W$ t3 j3 |; m1 j) T9 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* T% u7 h: s( X+ u| MCASP_RX_CLKFAIL
- Z4 c$ x" {6 i| MCASP_RX_SYNCERROR " _; I; X/ @1 I/ @ ~- b
| MCASP_RX_OVERRUN);# ~. v. `* T4 @. H
} static void I2SDataTxRxActivate(void) h8 e4 N' Y# t( ?. J+ b% j0 n( y
{+ p+ K3 E: h" G* T; U$ d+ \ I
/* Start the clocks */
; |6 I3 D; H4 c( J/ F" Y2 _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 t5 R, q* H) s' B' J* ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( ~! m( z% h" O8 N4 _) A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% G% _4 s6 S7 S. Y3 b- \0 E8 mEDMA3_TRIG_MODE_EVENT);0 D* I, B$ r4 M6 V' m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- T; V. w+ M3 ~( {. ]' h ?: FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 e& q1 z1 Y/ a0 e6 v7 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" a9 B I/ |1 f' T* W$ l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 t4 s) m2 j/ F g3 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; Q& A6 T4 |7 t7 c+ Q( ZMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 e8 _: h6 l& i, {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 t3 R( [, l9 l$ v
}
( t2 w+ y' E) ?( B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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