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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 Y8 Z2 e& _) |( xinput mcasp_ahclkx,
# U# i+ V4 _& \input mcasp_aclkx,
. @( K9 V0 S. \input axr0,
. \4 Y$ T7 y0 f/ M! F) J6 [+ N3 y9 E$ Q, { m1 d
output mcasp_afsr,
J3 p' T3 _2 @7 ^0 A* h& uoutput mcasp_ahclkr,' S# N2 J5 R6 W1 R0 K
output mcasp_aclkr,
7 e& T% N: Z0 voutput axr1,1 ]0 i! D- r1 j7 t3 C) e+ p
assign mcasp_afsr = mcasp_afsx;8 f# Q2 [2 b: t& y
assign mcasp_aclkr = mcasp_aclkx;
d4 U( T( B- v* @7 k& Massign mcasp_ahclkr = mcasp_ahclkx;
% H) I/ ^; d9 n. `- y( Eassign axr1 = axr0;
5 V* q- b7 e3 V1 g2 q0 H2 y# b' H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 K' i+ p, ^) o. b' ystatic void McASPI2SConfigure(void)
" W& h$ u( A' D& s" h{' i- z" b; M# m" O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! g! z3 V7 q' V4 r5 Q& F: }: Z# B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- R3 P7 w0 i Y p( QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( D+ ~9 f8 `5 ]+ B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. n/ b% s9 P% `. p5 \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& G O0 z& q2 \( l( U" P, DMCASP_RX_MODE_DMA);5 |3 X5 G# a/ u% s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ J" z1 r9 L- }8 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 U3 X0 M( Y D7 k7 v9 W# e3 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 j( ~) t; x; g& J- P- a" @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# t& _& p4 \. X; F5 O0 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 `4 F1 p2 W7 A: q; Y* cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 p# P# K+ C: z0 Z8 y j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; C0 C7 O/ O* O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! u' c4 _7 _# x- Y2 K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. h8 @, j P6 j" T [* F0x00, 0xFF); /* configure the clock for transmitter */
6 u; z( t5 ]! d' e5 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* Z, r& [7 E: x) {. `: l$ GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" l) I, Z/ ?, iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
w [. A. u2 G. D3 c9 f1 l0x00, 0xFF);
. t5 I p1 C6 a; s
3 u8 T( Y# m% n: F/ E L/* Enable synchronization of RX and TX sections */
; R& E. ?; B; \- G8 }, J3 i* dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// H) E: m+ Y! q9 i; Q9 V& D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ k# }' m7 _: s& EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* H6 t, ]/ r7 |$ U% O8 F, H** Set the serializers, Currently only one serializer is set as8 B# f" F0 Z- Z n; Z0 q
** transmitter and one serializer as receiver.
3 _5 L5 V4 d3 Z% e*/, n% `" {+ t$ _- s2 N. i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 x' m1 {) D, iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" n$ v! [# H5 H8 e# h
** Configure the McASP pins ) S8 D+ }* V; @& v
** Input - Frame Sync, Clock and Serializer Rx N- z* v, W& B, W1 d; p4 K
** Output - Serializer Tx is connected to the input of the codec 9 z* _! P+ f3 j5 _
*/5 a# O7 z( [1 S% E2 S% f1 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 w8 n( b! m7 U1 X! X9 i$ IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# |# j, P$ M) B2 U9 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 `/ \! a' H ]: H. m- z3 m| MCASP_PIN_ACLKX2 ?" P7 B; g; O
| MCASP_PIN_AHCLKX
% I5 A% E' X6 |9 Z$ S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 T5 n. j) i `& Z: Y& O9 e: s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' A+ V% k+ J/ E* |' R' V3 _: j8 {
| MCASP_TX_CLKFAIL
/ ~( `+ \: d6 m0 N| MCASP_TX_SYNCERROR
7 {+ [- g' c( a3 |# }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 J; ]8 q: Z& A7 o- X" |: i| MCASP_RX_CLKFAIL
4 { @) A/ r9 L$ Z| MCASP_RX_SYNCERROR / s. y. v+ w4 F/ [; y) R" o
| MCASP_RX_OVERRUN);) l, s" {6 f) H+ h5 b
} static void I2SDataTxRxActivate(void)
' ~+ M" z$ [/ I( a9 K{
5 h8 O G8 h Z+ U/ r" M/* Start the clocks */% S9 c4 H8 X8 O2 M5 K0 v* V% E5 v" ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' j3 _# ]! E5 t% X P* m' QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 T2 G; K+ D1 y2 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 j) M' ~6 J0 F, ^4 M. x4 f
EDMA3_TRIG_MODE_EVENT);
, v, s5 I! e1 I. MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; d; X: n% W* p9 E; j! G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& r8 H+ M& i- A4 `# R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 o! h9 @, E" \$ w7 ?; L* QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 H* _7 j7 I& c! v( I6 \$ h9 g! K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. y& Q. `1 [. W- t3 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ z7 b6 W& d* W3 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& [5 F% Y* J* [8 n} % y5 q5 \1 i1 j( [/ W0 @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 e* X3 ~2 U9 {. M
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