|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: `. X) ~ K0 Q
input mcasp_ahclkx,4 \, ?/ y, A, l2 i8 e9 e
input mcasp_aclkx,
) ~0 i9 X8 I' f& i' [input axr0,6 v4 I, J$ p" T/ y% T5 j1 N6 b m- W
* n/ f8 R# ?& I4 ioutput mcasp_afsr,
" ~+ q+ ?/ i2 joutput mcasp_ahclkr,
4 C9 \9 m v) k Routput mcasp_aclkr, r. P" F# B- h8 }
output axr1,
4 ~% @5 V% S! \( g( N1 B! Z assign mcasp_afsr = mcasp_afsx;
: n/ M4 l) w" M; Iassign mcasp_aclkr = mcasp_aclkx;6 X: j# \, D& J( `$ z
assign mcasp_ahclkr = mcasp_ahclkx;9 ]' K8 q8 X7 O& ~8 x3 C s4 F
assign axr1 = axr0;
3 T7 J9 j; n- Q# w2 l) E
& _7 L X6 t( J- F# v+ Y# j/ r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 I, l V* j8 j) b; Vstatic void McASPI2SConfigure(void)
" g M& y5 Y+ R! y- t1 P6 L{
( f( p; z& K! O- qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 z: t# ^' J- L/ ^1 L8 m/ B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 I0 ~0 D( p" dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 j9 w& f: a6 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 m3 _/ u7 o8 {5 ]. N+ v5 x: jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: ?; ~6 u) q! m# {- f5 h2 c% IMCASP_RX_MODE_DMA);
7 a& M) J, B' Q$ MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 i4 ]7 b6 E! O$ Y; ]- TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ^& \/ j% J' b8 n3 g) H2 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 u- U6 S1 Y" {! Z# O9 m2 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- j2 s. P: j/ t1 l' \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 n+ R7 E8 N5 w6 V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: U% X- Y, o% z4 x: p- R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 z* D7 W6 \0 P- K7 c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" \; P4 G R s% h! ~# |% I+ d }& RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 q9 C- P' d* C( a% `; L* v
0x00, 0xFF); /* configure the clock for transmitter */& h) p5 [: e6 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! ?* l6 ~! G$ u. _# k2 f$ X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- W& a" V) Z5 z5 r N$ E9 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; W$ |' C) r' Q6 e2 C7 R0x00, 0xFF);( r# L* y$ B, A" F! |: G
; t9 q+ V9 F' t) q+ L4 A% w' c
/* Enable synchronization of RX and TX sections */
2 {1 p6 H* `& u! {% |0 tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ `4 A( D) t( _* n/ q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, K1 f" N# N" o4 R* a- GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 F0 k* a1 E+ m. @** Set the serializers, Currently only one serializer is set as
- v$ p5 k! a; l' }: B5 v9 ^** transmitter and one serializer as receiver.
8 f2 X: V! M! M1 |*/) {0 Z8 O! R, P9 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 a( ]9 r! g; u& b5 ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- n7 [( ]# r' q4 U7 u6 [/ K** Configure the McASP pins
$ w' c# G: C0 Z% w** Input - Frame Sync, Clock and Serializer Rx
7 u0 o4 T* N" ` W9 o8 Y$ W% c** Output - Serializer Tx is connected to the input of the codec
* I7 W5 J( Z5 n5 w*/' K% @/ i' l% @* C$ b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
k, z+ ]. C( O/ f" |7 P& CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ r* j+ k. d* X& I% |/ ?: ~2 D6 Q }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- [8 f" u4 s4 ^3 X
| MCASP_PIN_ACLKX. f5 _; \7 n& z" m! I9 s
| MCASP_PIN_AHCLKX
2 n# ]% N" P# y1 O6 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 x9 e* F4 g$ r# D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! l& N3 k6 \! s9 N! y7 ]
| MCASP_TX_CLKFAIL
) t5 q- ?6 p) Q6 t3 `' y1 n| MCASP_TX_SYNCERROR
" P' B( _/ u# m/ b {' q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : i9 o& z9 [. l" Z' ?3 L6 D" ^$ F
| MCASP_RX_CLKFAIL
0 [% z% i& D2 A! F9 N| MCASP_RX_SYNCERROR 9 c+ N* a" Y3 V. k9 t# A7 y) B
| MCASP_RX_OVERRUN);
+ [. L) [% J- S' g' @} static void I2SDataTxRxActivate(void)' d; V& k E/ A$ @+ g, }5 Q* |
{3 N# a O, c, g, T* y8 v7 W' v( w
/* Start the clocks */
7 p) |. I, e9 CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 n) k7 o2 l1 p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ ?9 m4 q+ U7 E' T4 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 C# b8 V2 J) W
EDMA3_TRIG_MODE_EVENT);& p; z1 D+ u# Z7 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 P, H9 F% t N$ ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 _1 Y' f; _6 y' U8 g' L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 }* s& u( L8 t+ z' ?# w/ I' C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( r J: c; {- Y! M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. ~4 d$ C6 T& ~0 q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( I m) Q3 B5 _, h2 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& ^3 _+ H' v; |) y
} , `* i4 }$ Y$ Z! E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) Y- k9 e/ V" z5 M$ t; e6 } |