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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 W6 [) D# A3 k6 w7 `input mcasp_ahclkx,4 E/ K( E# s0 y1 D. Y
input mcasp_aclkx,
4 S( x$ ]* Q) S b2 Vinput axr0,) |9 l$ e1 o% E+ {$ Z& i
0 D# D% V; Q; e/ r" |: o
output mcasp_afsr,
# @5 r* {# s2 z+ E, \: q; ^8 loutput mcasp_ahclkr,
) E5 |! b( g, D) J3 s$ houtput mcasp_aclkr,
4 E } S C& ?6 aoutput axr1,$ E+ B( r1 I8 v6 M0 V; F' S
assign mcasp_afsr = mcasp_afsx;
0 o5 K) T: W) Xassign mcasp_aclkr = mcasp_aclkx;
. j3 v& `& Y1 o* r! k0 uassign mcasp_ahclkr = mcasp_ahclkx;
# `( ?: V$ D {9 S9 kassign axr1 = axr0; ( P6 j5 L7 P }- d. f
: h6 D+ W8 j& V# B7 a, E0 J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ E+ q) e4 E6 @& C/ s! d2 `+ w2 h1 Vstatic void McASPI2SConfigure(void)
& |: v! E4 s% z% u2 d2 s{
' \: k' A5 l5 s# eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, }. g2 ^( c, T$ |, g; UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) k1 T* a# k6 N2 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& J. s6 ^$ K8 F% P: ?. [" oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: D$ O0 p6 x) v; Z7 X }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# E( M8 t* `7 ? l- {9 ZMCASP_RX_MODE_DMA);! r; O; n5 o6 U9 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 e' R" ~* V3 s4 k5 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 `( {5 n/ B6 A8 k% o+ ~; q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : b+ [' M7 `$ r% j0 {; O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# _2 J; [+ I% E: B# j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 v5 R8 A( F H8 s) {- E& \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# H) c/ g' ?0 M6 u! lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% \' s* t8 r$ ]6 u1 g- L3 L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 `* L S8 t5 ^. Q+ X, ~% j; a( |8 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' K" v0 v3 l( e" E. i0x00, 0xFF); /* configure the clock for transmitter */
* L; [& k, J. k o I, yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" F4 n, q0 Z }7 i9 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( r" [: s, W& X. k9 y; H3 AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 A& d# U& C3 t
0x00, 0xFF);1 n3 K# ^* O& K) y% U! j
3 g. f6 U$ d. B/* Enable synchronization of RX and TX sections */ 1 Q0 x$ c% [* t; m6 \( w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- n. M" t h* v. K$ c* i; c0 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 D! K6 Z* Z/ ]1 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 i2 H9 Z/ n+ _3 J/ ?7 M
** Set the serializers, Currently only one serializer is set as
5 u; C6 e8 i* V9 @# y- g% p& }7 j) ^** transmitter and one serializer as receiver.
( B: B- u& e9 |0 }9 F*/0 Q; K: N0 a, Z% ?- k+ N" p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 L! Z$ k9 r" f: q+ U7 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# u! o2 K# H1 D. Q3 E/ ]# ^3 o** Configure the McASP pins ; k, c; X+ ~ E3 }, @! C. D' b
** Input - Frame Sync, Clock and Serializer Rx4 ^' p* A2 y' o8 u4 E, D. ]1 R
** Output - Serializer Tx is connected to the input of the codec " S" A/ j) D# g6 [9 z. P
*/5 U) {. j. V( D2 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 y+ Y) f. t$ Q- x* o, K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 A7 N, |3 ?# q3 h5 ~ y8 M( `6 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) v2 t7 ~: D7 z2 g
| MCASP_PIN_ACLKX- [: E; e! h# q9 q! E' {3 S7 J
| MCASP_PIN_AHCLKX
8 F2 D% x8 S" B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! u" Y& c! C) Q; O# [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR O4 t8 {5 [$ {, z& L
| MCASP_TX_CLKFAIL
0 M# e7 k9 P' h/ G| MCASP_TX_SYNCERROR
$ m" C( K ^* ^& K- B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 c- z9 h4 `7 F" u
| MCASP_RX_CLKFAIL) w1 U" q" A( r
| MCASP_RX_SYNCERROR
+ H/ G- K( d8 l7 z9 u# y% z4 Q) m" L| MCASP_RX_OVERRUN);
/ n) t) r% B* m1 U5 K+ P} static void I2SDataTxRxActivate(void)
' `$ d$ U/ m6 W7 K: `( n9 X7 j{) I+ C# d3 C. ^" |% a: z5 T$ F9 t
/* Start the clocks */
" p+ i& r9 B- k/ q9 o. CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 f" T! F% G( j; e- A7 z) M* b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
i3 S4 v6 x4 s* T5 W' \$ [& tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* V! h" `0 c% F1 ~! L/ i* J
EDMA3_TRIG_MODE_EVENT);
# D: f9 b5 x4 M2 B' ~ |, CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + V8 G6 w3 |, z( A) | f' `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' z" H9 e& q4 L0 G SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. U) ?2 t8 I4 E/ s6 }# |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! J9 @9 V/ }+ W- x6 P* Z- C. _/ [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 N+ \+ S, M. Y, H7 F( d* J2 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 R+ I, i. w% x$ q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. W8 @$ u- r; j! ^- e# h}
* k: D& c7 P! E+ @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % h+ } I" I' L% o( \
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