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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! b% u0 S+ I9 J: R7 t
input mcasp_ahclkx," R! r: ~- L5 m6 i/ T6 R. E
input mcasp_aclkx,
: Q4 D0 W7 _9 P1 O( Y; N6 R/ B; ]) Finput axr0,
% k% w) H( b4 f {: O/ }
/ F; F( ?7 y& y3 t8 K( woutput mcasp_afsr,
1 Q0 R8 f% w1 }7 P6 L' houtput mcasp_ahclkr,4 }0 Q$ l; N2 P( v- a& i
output mcasp_aclkr,2 ?% S3 E7 u( }
output axr1,
5 y& d( k1 F. F( |" T2 B7 R- U assign mcasp_afsr = mcasp_afsx;
5 v: e+ g5 W3 ~ [assign mcasp_aclkr = mcasp_aclkx;; N/ B# m( |' y1 }
assign mcasp_ahclkr = mcasp_ahclkx;9 ^& Z! }* k* w" k
assign axr1 = axr0; ; C" E @. F8 z3 q4 P8 l/ b- z
6 l4 @+ d6 h) |& F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* n$ n0 u4 Z$ t+ Xstatic void McASPI2SConfigure(void)' [& h, z* N5 p9 Q
{
. Z3 P! `1 V( C6 {McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& J2 I6 |3 d1 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& ?0 K- c# b. f- ?( H% yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 C; \( Y$ l6 |/ ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) k, i: j6 k/ s. s# `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 J* `3 n! t% M9 L7 j' F, vMCASP_RX_MODE_DMA);
* ~& M% x* E. W: RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 C/ A9 a9 m5 e3 s0 j2 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% |+ L% U, }8 j) l' Y6 A# |# S0 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. D& n* y# C+ _. x: N/ s& o0 L% ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! i, M' |2 T! i. wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 y: o7 R# J% v' ~0 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% C9 m+ A2 y |6 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); I6 s1 A6 C# K, @% H4 s# {- _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% _& _ p/ w* k Y$ o# ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; t u8 T% X G4 Q% L
0x00, 0xFF); /* configure the clock for transmitter */
& Z# [8 h8 Z& C0 W. kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, E/ m6 n3 g1 t# [( I% J! a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! u) v% \/ h" j) Q. {' S7 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 M/ a- I- V" C- O4 q
0x00, 0xFF);! m% U* T' `! [; {7 {' W4 r7 `
1 _% D5 y) `& ?8 U+ z: }/* Enable synchronization of RX and TX sections */
3 j& ^# T) D+ l# SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; z% I+ N& R4 S- G- c* L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' ?7 w! l0 s% K9 e2 ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ Q, O4 F9 I/ S. b** Set the serializers, Currently only one serializer is set as1 i3 E* s- k! h2 w r7 G6 i
** transmitter and one serializer as receiver.
& Y! q6 ]9 }0 A' p0 `*/0 P; |! j1 s- {( u0 {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ A4 Y/ w7 n; C$ |3 V; b% hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 _; W0 f# h- R4 n2 _
** Configure the McASP pins
, {, q/ |# `' W2 U% Z** Input - Frame Sync, Clock and Serializer Rx. [. |7 A( Z# f7 W7 `# M
** Output - Serializer Tx is connected to the input of the codec
; x; f3 H: h% s. ~ x+ U*/3 o o+ s9 Z5 L9 ]2 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) U. W- W( k4 |3 g: {! AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ i4 |! y9 H6 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" d s, q0 ~+ z% j$ B7 N
| MCASP_PIN_ACLKX" K9 Z# t6 P4 o4 F
| MCASP_PIN_AHCLKX) x1 v* n- \9 @9 g# r# }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 h8 |% u1 |3 j; M% @5 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! w! [9 o3 h: k
| MCASP_TX_CLKFAIL 7 I" \* x5 z- \
| MCASP_TX_SYNCERROR
- E j- s1 `4 W% n& c4 N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 B! u8 l8 m# }9 _
| MCASP_RX_CLKFAIL
! h7 v1 i3 {2 H" i8 j| MCASP_RX_SYNCERROR
* i" n8 B4 u, ~+ P| MCASP_RX_OVERRUN);# j) b2 t% k0 ]6 R. C
} static void I2SDataTxRxActivate(void)
. t# |( S" S5 s$ E, C) Q{
+ L K7 x9 v8 b+ R/* Start the clocks */
% R! T6 T- L% F% Y' u9 W6 v! RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* t: N: O; J: D( `% N4 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& s ^4 ]1 W7 J0 x. BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ o0 c4 l! c; r& x. p% h% f& g! d# g5 W
EDMA3_TRIG_MODE_EVENT);' s P5 N3 |/ ~" f8 T& T- s6 F) r. s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ W# D1 z- t' g6 x" L: P5 }7 J7 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! l4 X6 I; }4 j4 q$ J5 l# X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 b+ K6 n7 G9 W$ J% ^4 x6 R" v4 D/ E! vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" f* ~" j4 G# s: m) Y- o& v3 y$ |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& j) j; c( R YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ t6 E" [ X6 z- w( g+ F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ r. v7 B* _9 P4 \7 }' j/ }9 [}
7 }+ p. t( _4 K* j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 z" u2 q6 p3 `8 c ^/ U) L
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