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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 |- R1 H0 j; t
input mcasp_ahclkx,
( j3 a3 R k u2 M5 D& r. ^3 N: n5 {input mcasp_aclkx,' I6 Q3 w4 V& c+ c: s1 s8 ]8 _
input axr0,
# P6 k& ~, l8 ~4 R7 Z2 E1 }4 V
output mcasp_afsr,
4 H- c) Q) [3 V1 _! d" t: youtput mcasp_ahclkr,8 v9 E9 A3 H5 e5 O0 a, o5 G
output mcasp_aclkr,
" ~) j. R0 X0 }2 U9 B! Youtput axr1,+ C Y6 A% M9 [ s# S2 N
assign mcasp_afsr = mcasp_afsx;
( p j$ |! h! f+ O# Jassign mcasp_aclkr = mcasp_aclkx;
7 w* x& j, E0 j" x8 \( qassign mcasp_ahclkr = mcasp_ahclkx;3 q; `0 F1 t( j/ Y, u5 p
assign axr1 = axr0; 4 B3 D5 s0 r; D, q
- s1 W" d( Y# h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
c/ G' P# Z. istatic void McASPI2SConfigure(void)
& }( g7 n4 ^4 C9 o2 X{- a& z7 c0 n, S2 I1 n5 s8 U) `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" g% f/ h5 L/ d- bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 i* `% |' Y* m9 L3 H8 d ?1 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 v' C- {1 m% h- t) W& p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 z. [ N4 g" w' ^; n5 m" l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& s" T0 h3 `( i3 B; C: X* PMCASP_RX_MODE_DMA);. R) ]( I$ j5 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 f1 N7 c' n$ \+ D+ D/ S# f2 BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 ?* P! P2 ]/ RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 Q3 N8 @# F+ l0 F" s7 e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! c2 V6 w, G, r9 V/ \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ l, R, O9 }, i7 k! t' }+ pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 i: u2 |% U' y. Q6 K/ a9 B+ m8 p1 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 y; x3 b" G9 N0 y: T3 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( d$ k" f& Q3 w6 SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ o; \4 K/ @) E
0x00, 0xFF); /* configure the clock for transmitter */
5 i* H3 j7 z. ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% t: G% Z, D8 R5 ^; r% Z- I. oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 F! ]- p9 c$ Z4 p+ \9 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 Y c6 l( k! d8 z! I0x00, 0xFF);
7 S' E* j* Q( O7 g# [0 j1 t0 m, ?0 [, C# M
/* Enable synchronization of RX and TX sections */ 2 f( o; K* a' M1 w, V" r5 }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 D4 ~. \$ r- w* T v2 Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 ?* s4 R) E& |9 j n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, G, e7 C" m9 w& ^' g$ v** Set the serializers, Currently only one serializer is set as1 R7 p. S2 ^' y4 p0 D" V# s
** transmitter and one serializer as receiver.' T/ M# `3 i* v8 m! ^
*/
2 S; n/ O+ V. M5 [" A9 i" JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. z* p* x+ a1 {. N4 ?: \. b# aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ t- W1 M( m5 W2 T3 R# E/ [
** Configure the McASP pins ; C. y4 S& G. y
** Input - Frame Sync, Clock and Serializer Rx
: u& X6 c, @* O% \6 n4 D9 l** Output - Serializer Tx is connected to the input of the codec
( b7 h6 F/ I, Q4 h*/3 F/ S% Q* G n8 e7 @2 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 j8 Y3 f0 Z4 S7 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* ?. G; Q+ U3 v5 c4 G/ v; \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ g- s- l& T+ i| MCASP_PIN_ACLKX8 J5 i* y. D& p- D, O8 P( U
| MCASP_PIN_AHCLKX+ _0 |5 L4 }3 ~! L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ p w4 J7 x. Z" p9 d" ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 [4 X. u# `. a4 a, v/ Z u! R| MCASP_TX_CLKFAIL / F9 N3 l5 q! U6 }6 |; k: u6 E4 x
| MCASP_TX_SYNCERROR
% R/ J7 f8 g N* V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " K* o3 ^$ y. w+ A
| MCASP_RX_CLKFAIL* t6 Q& |$ y" u% H
| MCASP_RX_SYNCERROR
5 T- t9 e; u s; R0 T7 o3 x7 @6 v| MCASP_RX_OVERRUN);* ~$ {5 D6 {2 A8 T5 _" b, L$ O4 s6 |5 {
} static void I2SDataTxRxActivate(void)/ c0 x! R' s" N. X! e, O" d% \9 V
{, X1 s+ j$ `! r# [6 p. G
/* Start the clocks */
g A3 z& D; ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. J( h4 C. K; L5 p( b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 p+ t9 t7 h1 U0 e, _& _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' V% F4 z e% d) o0 G' u1 jEDMA3_TRIG_MODE_EVENT);
1 z5 @" f5 g" B R2 o; E3 g8 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ l) t: q& o; g- Y+ H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% P8 h' U) J. f. t; B+ A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 H9 k6 c+ g4 _3 b+ R* I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ e; N! X" N3 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 d) d3 v7 F( h' PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. y0 A0 _* e1 ?) BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 K) e" l9 _" I3 n2 r0 H} 1 V8 X2 e* m0 K3 R" O+ p) o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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