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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 o t# o1 P9 N. ^6 ]
input mcasp_ahclkx,
( T2 V1 ^2 ^5 R4 i# t: binput mcasp_aclkx,
- W- U0 E% y' r- |) [- \: J. tinput axr0,
) [! M1 S# n2 N* y* R" _$ r+ o2 @; [* k$ `" c# z
output mcasp_afsr,2 V( s& M/ K3 p
output mcasp_ahclkr,
( s1 W" N4 X* F! O; I) Z, Q. Toutput mcasp_aclkr,
% G" s$ q6 J, s' O0 X" S s: eoutput axr1,
& D: K6 O- d& r3 T assign mcasp_afsr = mcasp_afsx;
) {# e" M4 C! \' X: v6 L) X6 F7 T6 Qassign mcasp_aclkr = mcasp_aclkx;
+ ^# E: m& V- Kassign mcasp_ahclkr = mcasp_ahclkx;2 \' i) W. `7 y2 C$ h% P) {- i
assign axr1 = axr0;
+ O' x: ` z4 s+ L" R/ }3 f7 R, s# P8 `8 \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! s4 m: a2 M$ q! Y0 [static void McASPI2SConfigure(void), b' [: D% B7 a1 S
{
" r1 Y& G8 I; X8 l* Q3 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( b1 O; b' q/ _. E. gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% `+ P/ I1 O; j3 I& l) H5 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 \5 s3 R g+ `8 }2 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 s7 g p2 I( s9 h+ G$ d, G HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( g0 H, a7 V; I' o$ m
MCASP_RX_MODE_DMA);
+ f: x5 T( V" j0 {3 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 l% R( N0 ^/ s6 }- }+ ]5 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ q/ l4 y6 H" g' g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 D" h' y6 I# S; H- R4 s3 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% {. m( L u! c; {- w/ |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 F$ |# l1 C6 R: e+ |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( B% k( h4 V$ F* g" [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 A' I8 a: I: Y4 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 f7 G3 R" e8 o. W4 E& h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" |$ E( C% o& }+ G ?+ q- e0x00, 0xFF); /* configure the clock for transmitter */
5 ]0 D0 [* Q: J+ R4 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 f/ O ]- D( ~( M8 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); |' J; w& `) y8 C+ p* C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( ]- {+ r3 x7 O- U: k5 d( @
0x00, 0xFF);
- Z+ p" s% w/ i5 q9 N! q" G% t/ F; u, t8 G
/* Enable synchronization of RX and TX sections */
2 N$ k7 E, Z( o1 q/ V( K6 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 p8 m+ Y, z0 u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' G% c8 m: o S( l- c- J# }$ `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- `0 F5 T$ m0 x9 Q& Z+ ]' f
** Set the serializers, Currently only one serializer is set as
1 f- ~' Z1 k' y0 c& e! o** transmitter and one serializer as receiver., W" }" K. {! v! e. I
*/
0 J% Z# _9 k& h/ X# `- hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. g6 H% i& \$ w, X5 Z0 m
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- q. c/ ^1 j. u% e$ Y$ _** Configure the McASP pins 0 A4 i$ P3 B- T# C$ `7 Z
** Input - Frame Sync, Clock and Serializer Rx
2 {) Z# z% \( ?" M {& }5 C6 W** Output - Serializer Tx is connected to the input of the codec . T7 h4 d* ]. k3 {" W1 u: v8 S* h
*/, b0 k: o& T. v, [. G2 h$ w H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* _3 M. a$ x! Z3 @! o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! P- R* r0 n% r$ d1 b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- e& W/ L6 K9 V$ [9 L6 |
| MCASP_PIN_ACLKX8 W; ^4 |# e4 h0 _1 C* K; p
| MCASP_PIN_AHCLKX
7 i! [0 y+ x. d& [0 I# ~ A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) L3 G- S, s) y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( N$ P6 A. ]8 B' x
| MCASP_TX_CLKFAIL ; U5 e; O5 n( q! V% z
| MCASP_TX_SYNCERROR
% f* O1 `; _# d+ o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; [6 p- ~ S4 ?3 x/ H0 m( P| MCASP_RX_CLKFAIL
4 K- m+ t4 X3 W. f7 \3 l| MCASP_RX_SYNCERROR ) J8 U) R. P* R7 `6 O- X! G
| MCASP_RX_OVERRUN);- F# ?' y/ \3 D. @" Q. t" n
} static void I2SDataTxRxActivate(void)
, X3 \/ w6 R) v1 `/ B{
8 ^, p7 b9 M# K- \( o% m. |" O/* Start the clocks */+ a- R; q! ?0 }1 K/ z) |$ o, I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# x' r; d9 v5 I. G z& Y" HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
Q0 _$ t: W b' [* h6 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' i- l. b4 o1 J _EDMA3_TRIG_MODE_EVENT);
, Q! @ E: Q& z# i- oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 U( y2 {: Z5 [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; V/ G' T) V7 ^3 Q: SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: L* z" |; z5 A4 |6 q: Y: Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; `; A( k7 w, |& Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& z# c4 w. |( F$ y# QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ v* u' n! s" D3 f. [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 r1 p+ G; b/ u) m. ]} 9 D/ G" r" d `$ i- Z i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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