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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& p; u0 P5 y( S8 ^$ _9 J
input mcasp_ahclkx,
: U$ e" E, F' [- m7 \. vinput mcasp_aclkx,
5 @- z. K" j% {input axr0,
: }# ]1 _8 Y1 O4 r v1 F- T0 ~" `. z9 I8 L- ^0 {+ p
output mcasp_afsr,* [$ f7 s5 m! }$ B! Z
output mcasp_ahclkr,
/ X% H2 k( k" coutput mcasp_aclkr,
/ j' ?- i8 ^% {$ X) ?output axr1,8 c: ~' f* | t4 H2 a
assign mcasp_afsr = mcasp_afsx;3 {8 k7 C; g4 m* i5 p* b
assign mcasp_aclkr = mcasp_aclkx;
1 p! D/ B4 n; dassign mcasp_ahclkr = mcasp_ahclkx;/ a: Y, t# M+ A4 \
assign axr1 = axr0;
- W! ~- M, O0 l1 r* S& c
& @% {% I$ J, I) A( c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! s/ T! J: j4 z- w0 t
static void McASPI2SConfigure(void)
$ r/ j" y+ v8 E" x- j, ]$ R3 }6 Y{: Z4 D& Y2 [# I- G& k" E. S
McASPRxReset(SOC_MCASP_0_CTRL_REGS); f$ s; k. [; O$ L! a# V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 p8 c) E. m% q: a0 ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* L3 Y* Q" t, \3 s% X" _! a* yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* k; L( U. ^- {7 p# M9 a' _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 O; o; Z/ K0 e
MCASP_RX_MODE_DMA);4 v3 o0 E5 V9 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 V0 ~% e9 d/ u1 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 O* m& J, a$ k7 v5 z7 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 ]" ~0 k8 D/ o Y: XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' D) j9 E; L/ b) Z6 d. uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + ` [8 P7 A6 a5 r3 n9 Q/ f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 U, S, S. ?5 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ C. g5 \5 J( W. ?, K+ E( l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; C. o! q* v w: A5 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% n' h$ {8 v) ^% j6 I0x00, 0xFF); /* configure the clock for transmitter */
& i; d i' T( t! l7 Z% H( mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 @, i7 I( @- ]& N6 T- i: Q- GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 Q/ F& i' F- i+ Z' @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. s2 M }" s" f) p/ z! {7 E0x00, 0xFF);0 u) Y& Y/ x; }5 b! ?( r
6 x* E" c; b, f! ~% z/* Enable synchronization of RX and TX sections */ ' n; w& u& A9 K+ o/ f7 p* ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 a1 O* }! N/ P- N# z- D9 }$ BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
S X, _7 D& N; _( l6 i6 M* i! kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, X0 J: m4 A- b# K** Set the serializers, Currently only one serializer is set as6 ^7 N) Y3 C8 o1 }% S9 C0 L
** transmitter and one serializer as receiver.
' O- A0 M: r* y2 G7 E7 K! a2 h*/
3 n5 s- S" u0 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 y" t, `6 B. Q) D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ `0 ^! L: o7 J0 t2 x. J, g1 q; j
** Configure the McASP pins
9 {( c9 d$ E" N# D** Input - Frame Sync, Clock and Serializer Rx& Y& y# x. f. X3 M+ Y/ w
** Output - Serializer Tx is connected to the input of the codec
1 E% z; J9 [. o*/
& L, ^) J0 q$ J7 R! bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 q! _% h) W# Q% f8 ~: Z% XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( C$ y9 Z2 ~2 h1 _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& V& E! H, m2 T- _| MCASP_PIN_ACLKX
. B) `: Q' d* c! Y2 c| MCASP_PIN_AHCLKX
8 K: b5 M% i& [- h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- L( B7 r( R( a+ y2 ?4 u+ O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' L4 f, ~8 s' t! K| MCASP_TX_CLKFAIL 8 c4 _0 p% D8 }# b7 @& `6 g
| MCASP_TX_SYNCERROR4 _" r: T5 B! c- w3 m1 `# _; D, J0 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * ~- {; Q) L" m+ |6 U4 {5 L
| MCASP_RX_CLKFAIL
) v# k& l. i* I, ^: J; X6 c| MCASP_RX_SYNCERROR $ l0 s$ Y5 r. N; X
| MCASP_RX_OVERRUN);
7 \2 P' h- Z+ n8 c$ [" ~( A} static void I2SDataTxRxActivate(void)
8 x$ g+ D. b+ `9 W' _{
1 o% {. [( j9 i& X* |$ }- l2 ^9 ^4 b/* Start the clocks */
* o& Y" b( T2 q3 ?7 \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; o+ x& j1 o: G; f5 ?4 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. d Q' v7 d# D4 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; n/ l* J ~) G8 u( ?! W
EDMA3_TRIG_MODE_EVENT);* r4 A+ Y1 Y6 a- E9 y* j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) d4 s: u: H$ Y" ~/ K, Z0 X. B TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 s6 g( ]- S$ P. S# HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 D( Z7 H) d- B3 e% y3 n) mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ N/ M$ {. i4 K! g9 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* y" A+ m( H1 N( z+ fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, w2 d2 F" U: ]" t9 D) W: P8 IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: Y- ~7 |; I) h2 D" j
} ( |) I4 u( S: r1 n0 U: y! M2 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 U3 ]* n* a& C2 l: Y# s
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