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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 T+ Q) b! P& j5 N5 V
input mcasp_ahclkx,
: X4 k" O* \5 }1 Pinput mcasp_aclkx,5 Y$ H3 Y7 K4 p! ]" M7 e3 \
input axr0,9 \& U" K7 E. T, ~. C/ J
) c* X L& a1 l- [output mcasp_afsr,
9 l. L, N4 G' [2 o* D5 o) Foutput mcasp_ahclkr,
% g7 w1 i0 L- |$ _2 x. _" poutput mcasp_aclkr,2 Q/ |. {# b5 q0 E
output axr1,# N% y% O/ h# t: f" S6 B
assign mcasp_afsr = mcasp_afsx;# y, j2 h, b4 L; u: n* M! X( }! ^/ C
assign mcasp_aclkr = mcasp_aclkx;
+ q' W! Y0 ]1 G: O0 k& p7 Passign mcasp_ahclkr = mcasp_ahclkx;
6 V" o& k6 X5 W* m/ c5 oassign axr1 = axr0; $ e0 N6 D, s3 f* z; C
, [5 H! o# O2 T: P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 S, }* z+ p$ ~( F- Z2 bstatic void McASPI2SConfigure(void)4 X! J6 b" p+ j: a. o
{
: @# N6 j1 R5 } W4 vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( m6 q; q, C! }( B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 s- R+ e) S4 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); Y/ f! Z. x! S C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 _4 p6 D- O1 {$ K/ v' }3 q p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: } j- G* x) G& _# Y$ s: s ^! X; f
MCASP_RX_MODE_DMA);0 t9 w F7 m6 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 X5 R4 z' H% xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! G. o) h, D( ]. f L/ c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 z2 Q# k& R! v4 b( Q/ W }# j# ^+ s' Q& M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: b0 e. [& o2 z+ C5 C7 z9 O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 V/ x A, d5 R# l- a. j3 V5 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ W5 h# O* R9 \/ k6 IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ ]1 o7 m( L WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 l; E/ k! Q# _2 b5 z: UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! j) d) q- n6 I) {* U2 e0x00, 0xFF); /* configure the clock for transmitter */2 o: V* n9 T6 @$ Q m; t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" q: @6 w p f; p+ x8 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* O4 {: J2 U* w! z+ sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* k0 x0 ?7 Q9 E8 g0x00, 0xFF);" p8 U- N( p0 B( j1 i
5 ^" W1 [( \ }0 O) z/ A1 d/* Enable synchronization of RX and TX sections */ 5 G$ w6 l/ c# Y1 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) t# \. K! O M4 B4 V* p" o3 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! [# q& S: U+ M5 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
m+ R& B: C$ {5 O0 K: L( l** Set the serializers, Currently only one serializer is set as
& u; A1 d4 _: s** transmitter and one serializer as receiver.
7 t2 \$ n- D6 U4 T. i& q9 Q; Z+ A*/! w& z6 b. f$ }' P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. T. P5 ^* | e9 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 h3 q4 n3 w( ?** Configure the McASP pins ; d: x M4 r; X& Z. `
** Input - Frame Sync, Clock and Serializer Rx
; a/ X! B# \- M; C3 ]; v5 z5 G** Output - Serializer Tx is connected to the input of the codec 4 S0 b' M8 Z! f& S4 S5 `& `7 u
*/# J8 M- d! b- c, P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- i2 X! O8 c" Y" {& O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 ]3 g4 k; K' I% U6 F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 a* ^) q" x: \& [| MCASP_PIN_ACLKX
5 X9 R1 O0 D$ t& t| MCASP_PIN_AHCLKX
; @$ e; y( y7 C || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 J5 u; D, A* PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # k( Y# i, ?6 b# l
| MCASP_TX_CLKFAIL
6 S) ?& w' R" w- M| MCASP_TX_SYNCERROR
$ k$ b3 F/ e; {: O0 D" z' i+ B1 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 t2 B" F( E5 Y& F| MCASP_RX_CLKFAIL' |5 P: G* _! T4 @6 O
| MCASP_RX_SYNCERROR . ^5 L) J4 @+ }. @$ X
| MCASP_RX_OVERRUN);
/ u) T8 I. ?0 r; f0 u. a6 B6 [5 ?) c} static void I2SDataTxRxActivate(void)( B. A" x1 |; m$ G+ m; l( R
{7 N7 ?8 y# `8 t$ q
/* Start the clocks */
3 k7 P* u" q2 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. k$ j; D+ }9 U6 F+ q! [9 d, p/ bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 v7 C4 [7 U t4 W8 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- G O1 j2 H$ v8 W% @+ nEDMA3_TRIG_MODE_EVENT);
; m8 D* m" [1 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 Z6 ~* V9 [! e' S8 V" g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 I* S, K2 Q, {( {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 f: e$ X K! r/ QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; k& \3 ^! R' j* `while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 C7 y, U0 o6 Z/ L" aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 x0 j, i; t1 q3 m' r; }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 c+ d: i$ \2 e0 S* o}
8 z6 c+ Q: t9 Q) @# @& L2 L! R- }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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