|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ N' B! l5 s; J" c4 @input mcasp_ahclkx,
) D4 p9 @0 @0 |) \" ?input mcasp_aclkx,6 { l6 Q4 y o3 M& C
input axr0,' v$ X) N" c, B' H6 v
- O/ v T% H. e C1 M. _
output mcasp_afsr,
: V m& m' b6 u0 c( _output mcasp_ahclkr,6 a: D5 ?& F' I/ X, h
output mcasp_aclkr,
$ A' `# S! d" v Q$ b# koutput axr1,( `+ Y3 m6 X. L% {6 ^: g2 I
assign mcasp_afsr = mcasp_afsx;
A, x/ g+ m' c* Sassign mcasp_aclkr = mcasp_aclkx;
5 x0 ?6 l* R( p# lassign mcasp_ahclkr = mcasp_ahclkx;
0 G; C$ g$ t6 f5 p( W+ b+ vassign axr1 = axr0; & X/ N& {8 J, C' M9 e
% ^4 H, b) ?( Z$ {. j: J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " `( @$ X+ @9 |1 _
static void McASPI2SConfigure(void)" ~8 @9 h3 J) A! W
{
+ U$ s K' B; i0 m* l, bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 F6 i3 |& i1 J( F0 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 a$ g# s2 f$ m) m. T( k: X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 V0 K- b0 Z9 m& rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* w7 e( G# @3 G+ g0 ?# XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 C. L$ D+ U* q" W/ l6 r' L, _
MCASP_RX_MODE_DMA);
" t8 S5 Y; X* J |6 p0 `/ g5 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; R3 Q9 T7 a- _( _3 E5 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 A& j$ b3 c1 h7 ~4 M1 \6 PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 H( C+ ]7 {& _0 z- y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: p) h- \: D3 N, v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & d: S: w3 Q) S l" k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 P5 U: B! n& `9 Q/ y% {& s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% K3 a, c( M5 z. ]! G6 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 B7 E5 P% T, f" E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ }, p+ I: c! [8 j: n0x00, 0xFF); /* configure the clock for transmitter */
x- Q% h/ I) r* r3 N! F: JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ x6 A2 s& f) FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 ?0 C# { x( I' j" v" y- v8 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 \ `# n8 x0 [3 d6 T; U" V0x00, 0xFF);1 n1 G: B6 }* @+ F) D+ `5 p
1 \' r, F, r& `) C4 R/ O2 k( X/* Enable synchronization of RX and TX sections */
/ b: N, Q. g1 }0 w2 wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 E4 ]3 Z; |3 Q; CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) a8 [, @; H# G7 z1 g1 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ j) M1 S: Z" w** Set the serializers, Currently only one serializer is set as
6 [! T2 j: k0 S9 x** transmitter and one serializer as receiver.
3 x. Z7 Y& |4 U$ R9 H; i*/6 I# z: V' V" V: h$ t# o8 q; K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# p, h1 L4 J9 |5 P; F" yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 g+ T, [' V; M0 G' |** Configure the McASP pins
/ \% p3 P4 ^: ~) X' L3 l** Input - Frame Sync, Clock and Serializer Rx& z2 K! @( H1 l, M3 C5 `
** Output - Serializer Tx is connected to the input of the codec 4 |' }8 E4 h& c: ?1 L' n
*/6 \4 t8 `6 V- I5 ?% ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) O! N5 Z& U8 Y6 J2 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 h% t3 p* s2 n: q$ ^& uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 S1 S( y6 b5 h5 G! m; P. g
| MCASP_PIN_ACLKX5 K6 G1 ~) P0 z1 J: [/ c* g
| MCASP_PIN_AHCLKX
( R; D: I/ z9 [& H1 R5 p' G1 w+ H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) a9 X! z( K- ?! C7 b/ ?3 s8 g$ a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * W1 E" p0 a' t- ~, c+ S4 g( N v
| MCASP_TX_CLKFAIL - i* r& Y3 T& m8 ^% Y6 {, [+ T
| MCASP_TX_SYNCERROR
' g! W6 R+ p# Z D9 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 S: n' ]& }& f" E$ }* y0 Y) q9 J
| MCASP_RX_CLKFAIL. o {$ L" {1 O3 o
| MCASP_RX_SYNCERROR
! y0 X \5 s1 b| MCASP_RX_OVERRUN);/ N( B6 j- U) E/ [( J
} static void I2SDataTxRxActivate(void)
% G. E; |3 K/ s{
* f1 A- }' U# ]" [: d5 _/* Start the clocks */. }! |6 S# q+ w8 q% u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% Z: I0 R# d4 A# W& k# T. A3 b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* E" E# _: p2 A5 `2 E" W, s( H$ X+ BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," ]" k; r: V& V" J% Z$ I+ d
EDMA3_TRIG_MODE_EVENT);& k. V8 h" q2 s" o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / Y _; y7 N4 K) ], E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 e I4 C/ R8 a0 F8 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) Z5 L9 P7 ^6 T5 s8 w- `0 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 p: z) M* F5 m! `2 e( Z9 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 F! y# a" J, u4 C! X0 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ g4 W( y3 z* [% x r7 \+ c* R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; I( {4 V5 V) j1 d" W" T} # O- }3 Q: T9 _6 C2 x, S4 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % n, E; U' r; |3 d. Y5 I4 m
|