MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% e0 f! J6 r5 |8 _( tinput mcasp_ahclkx,
input mcasp_aclkx,
- N7 G& d+ t& E& A7 N" B6 ginput axr0,
' ^, F) z8 r- U3 _' ^$ {: n
* L" @) u5 I, c7 b. ~0 H% voutput mcasp_afsr,
- R/ I# _7 w- z% goutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
! j: P5 b: M' {& L3 z" P* nassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

8 j0 H/ W1 D9 i2 y# J% ~# }
8 g6 Q( F9 \; X3 b: N- Z1 d

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
/ J7 K* ~  _0 N) S* E! OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# V2 J$ s( o% X4 F- J1 eMCASP_RX_MODE_DMA);
4 }) E/ X- z* RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ W. g$ ]: o, }/ t6 {  x( [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" k7 H/ v1 b2 _! X9 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
  \" ]/ O) d) b- _! k( _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 U0 P( `7 r+ w6 |0 `7 t* NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 \# {) L9 n2 v* s- _; s% @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
4 i0 W! P0 F6 A* [8 O, D5 d6 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) z1 L5 {6 a" N8 ]1 _0 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
* w9 q1 r2 W! n4 W, D3 K/ V
* ]8 b1 m6 q' N1 ]- Y/* Enable synchronization of RX and TX sections */
" Q: T6 Y9 Q! WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( ]; U& _5 P) s! z( y5 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
; U  Z& u( W- \** transmitter and one serializer as receiver.
' S; T, q7 x  M; G*/
$ r! ~$ e6 C0 `! iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. k4 e0 G. W8 o4 GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
+ z; k" `+ }; k3 a9 Q  B+ _** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
. Y& t/ Q0 _  R4 Z3 I: cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 Q  H/ ~0 w$ Q, xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
- U# t8 W$ _+ f2 f- d" b  m| MCASP_TX_SYNCERROR
! ?6 z4 \0 X( n4 f1 x5 h3 a| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 q( E5 |- @# M6 Q) \6 a7 A| MCASP_RX_CLKFAIL
  L6 B5 f2 A  Y/ K4 y% v% H| MCASP_RX_SYNCERROR
9 X- x, D* c( B, q| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
4 n, {* u$ a6 c. mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ W/ U1 b$ P0 H  o5 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
( o8 b# H4 L" w5 u  Q0 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% L8 s% g+ b/ G7 N' ~( PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 E$ E3 g: M" }5 ?# y$ Q" HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 u: l6 }# Z7 P* Q7 C; o8 T; A" y}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.