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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 W8 Z# o3 A2 t, n; L" g
input mcasp_ahclkx,$ \. B- A; n2 _. Z+ Z
input mcasp_aclkx,+ @' R* e( d g' N& }( C% u6 A
input axr0,
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output mcasp_afsr,
/ b. K- v5 [; J1 e0 t. ?output mcasp_ahclkr,& u7 X& D$ [; |) U
output mcasp_aclkr,
+ O8 J8 i2 v$ koutput axr1,
5 ~ ?* d$ m. R/ s4 q assign mcasp_afsr = mcasp_afsx;
9 P/ V2 c. u% l5 V+ Dassign mcasp_aclkr = mcasp_aclkx;
( D( |' K4 `. W0 ~$ {- e0 [assign mcasp_ahclkr = mcasp_ahclkx;$ D5 _2 X) U! E
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 t! W; w6 f0 a, C, @' S2 D$ ~static void McASPI2SConfigure(void)8 [3 P$ _) ?' t2 ~
{
1 s# ]0 g: i$ Z9 W$ sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, E( [: l v; K! l! eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% z7 D2 A4 E& ~& r, F( ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* K# z' r* L% e4 M; ?! |, H ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 ^" F+ r# D: p( W% o9 T" c- d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* v$ H" |& Z! ?4 a9 E3 C& EMCASP_RX_MODE_DMA);8 T5 @% b, j, J1 t- [, n, ?. u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ Y# o7 ^; a2 K* S7 s5 Y( TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. o5 P4 J% j$ ?7 u* f( t* Q @; qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 T& g) i0 S- E. w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 q. G, m2 E- W9 L4 v. C2 Y7 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( C# S; s6 n5 S7 U0 N( ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; \+ o* R j8 r( {3 X- S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) R9 H& o3 M2 D: z. |& z( SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 a1 k8 ?$ R9 P$ z* n' ?# x( hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 P- e& Y! L: S) u6 l& d' u# g0x00, 0xFF); /* configure the clock for transmitter */
7 N0 Z. ^! w+ g: `6 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 D; A [' M7 _! D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " C! h% S& M1 N! {/ |; _/ m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' U% F( Y* S: k0x00, 0xFF);
; S" p% u( H, a( S J$ O! P6 C5 C# B
5 n5 V5 t4 M" c8 Z6 S/* Enable synchronization of RX and TX sections */ " p* L# L# @0 d k. R2 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' q; R* O. {9 g* s4 {! fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 O1 W& \) U5 v% X5 o9 SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 l: S/ J# R5 R" D, s& I8 C$ X** Set the serializers, Currently only one serializer is set as
" a$ Q% C* i8 i" a# s- g** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 b8 n6 }* Y$ RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 z# _' ]7 J1 |3 I2 }) H) r
** Configure the McASP pins
# M9 e! H+ K! I- \' i* f/ [ s, h** Input - Frame Sync, Clock and Serializer Rx2 ?: L! G& c7 V4 F
** Output - Serializer Tx is connected to the input of the codec 1 t4 j f$ X8 f+ @/ B
*/
* w' r7 \8 F& @6 T0 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* h! A/ L' C7 w; X& C, B/ \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& A- C5 X9 ?% B U+ v" iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) ]" C6 v* ~7 z- X| MCASP_PIN_ACLKX
2 m9 I+ v2 K# f| MCASP_PIN_AHCLKX
+ K' S0 t5 X b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ?# S) V) a. b0 wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR U& Q3 O! P# O5 F
| MCASP_TX_CLKFAIL
4 ~$ `; v/ T {& g| MCASP_TX_SYNCERROR
v ]0 S5 }$ f1 p- h+ S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 r' C% q1 n, K% j4 ?* p, Q( w, [2 A
| MCASP_RX_CLKFAIL+ A, r8 [2 A& B$ r( L
| MCASP_RX_SYNCERROR ! M4 u: i& T* H# J8 K
| MCASP_RX_OVERRUN);
1 K4 T! }1 u5 E [8 W} static void I2SDataTxRxActivate(void)
( |& A/ k2 y' _* w: H{- k, G1 l1 F) `7 z. a5 _; s
/* Start the clocks */& ?% A4 R4 n: O, W, Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: e0 {6 o+ ]# N! |- n* b; N- gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- ~) g/ K# A2 i' J2 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 @3 \8 T" R \; c( u$ \, A
EDMA3_TRIG_MODE_EVENT);
! f: H- ] ]+ n; gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 `6 }& p ~' Q4 ~, a1 t" rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. E! m, p) Y; @- m+ B0 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* ?. n9 q% H- H8 f" A1 R, e9 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* r# m& r% ?# d% T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( h4 c8 @' a( j f- }4 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 z" |: }5 p3 R8 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! _1 u0 j6 R" Z$ j e. f2 N8 `3 E}
0 C3 Q7 `# G/ j* y, ~3 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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