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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 T' [) ^7 ]+ g o4 Q4 y Vinput mcasp_ahclkx,, K4 h' t- i( _
input mcasp_aclkx,7 y8 q2 m# b; [, L
input axr0," F0 h2 k( B+ f
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output mcasp_afsr,
9 F. i; \* y$ G7 d% D! [* M; poutput mcasp_ahclkr,3 J6 G# c& c4 I& W8 o" |" ~& i0 n- x* Q
output mcasp_aclkr,$ Q5 S v, d' I" ]9 q) k7 x4 f$ N; ]+ a
output axr1,8 G3 D2 W9 C- w6 w& U
assign mcasp_afsr = mcasp_afsx;
+ W. R. S% N3 Nassign mcasp_aclkr = mcasp_aclkx;5 ~( ?$ ~, b O! i1 b
assign mcasp_ahclkr = mcasp_ahclkx;/ Y. q4 l& q' O5 l/ `& {7 i
assign axr1 = axr0; 4 _+ |2 e i4 r' {
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + T& @( Q: O1 ]1 P+ G& C8 i
static void McASPI2SConfigure(void)& u7 Z) k) M& ^6 S' v9 L$ T4 x8 q! P
{
Z" V' s) K" i* z3 M3 e* VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 m/ L) j( _1 h# P* i; |' T6 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! R& O t2 [$ i$ c3 m' D) kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 O! ^6 S' V7 E/ y& d" i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. u; g8 x2 V8 w+ T0 t* eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# g% Y s J& A7 f# p8 K. |. M4 BMCASP_RX_MODE_DMA);
& Y& o( D& m4 p1 j) T& n! I- VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' @% v% N4 S, i9 b; A9 |0 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ k8 Q7 [! M9 D9 _9 d. l+ J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * j% f& ^, p6 f5 h" m2 v+ y0 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 t- |% ~& O# jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # Q% T# J0 r( K9 N$ h6 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 e' }7 z6 ?: q+ g7 m. K& l3 |6 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# h& w4 p2 b8 V( K3 L. q. ]5 _& BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% t' O8 d3 n2 y; F% J- xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," V1 W% s& p' q4 j1 {1 r, V
0x00, 0xFF); /* configure the clock for transmitter */2 y% b& H- V2 z4 }$ e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! p: Q0 O/ S& b% w K: g; g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / m& `8 F' c* }/ x4 j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. Q, ~& x1 {% ~- ]# Z0x00, 0xFF);9 @8 R& R" c% V0 |2 U* ~ ]
% k' a" D, {" B; b* ^. }/* Enable synchronization of RX and TX sections */ 0 @3 A' c) b* Z& p% K. p4 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( w- y1 B t2 E* o, Q2 y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ?7 K. a& d* K$ v: WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* P0 ]/ \1 ?4 Y$ H8 j' J& k
** Set the serializers, Currently only one serializer is set as$ r! ?1 p$ Q2 y A- M
** transmitter and one serializer as receiver.9 J6 x& }2 R, H$ t5 a
*/
5 J' \8 ]- ]4 h. H5 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 i$ U6 p: q$ d3 s# p1 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% q2 r7 z; A; a: @** Configure the McASP pins ! c% v0 U1 T, r: S& s: p
** Input - Frame Sync, Clock and Serializer Rx( u+ S$ i) Y I( }
** Output - Serializer Tx is connected to the input of the codec ! p4 K5 }' ]- D) r
*/
& V! C1 V% c, B) FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); l! h1 |7 F! D' X1 f* u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 y& D* \8 w. a( I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 b: N( m; p: z5 K8 n' o# Z| MCASP_PIN_ACLKX) s% P$ S4 h5 _6 j3 E$ ]
| MCASP_PIN_AHCLKX
" U$ u0 d4 o5 [* o0 K3 i6 {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 T1 i9 Z6 H0 ?, A0 ^4 j# P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 E& W4 a' c& X7 Y( Z- Y& |
| MCASP_TX_CLKFAIL . |+ A1 ~% V. }5 `5 D0 a
| MCASP_TX_SYNCERROR
+ G1 J y+ T& S/ q% j9 t0 W& w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * l( x1 B! S- `
| MCASP_RX_CLKFAIL3 r# u) y9 W4 S5 m, ]# x$ f. l
| MCASP_RX_SYNCERROR + k5 n$ B$ Z! V% y
| MCASP_RX_OVERRUN);
& D1 V& o! e+ j8 ]' a} static void I2SDataTxRxActivate(void)
% G! m0 w5 x, h$ }2 P+ k: \{
/ D! S$ f$ m% q6 |# K/* Start the clocks */
" }- Y0 i1 T9 o7 M- d% x) yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); m( l0 P8 g2 \9 p" S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 E) g0 b, }- L6 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ h( a" ~* Q& [EDMA3_TRIG_MODE_EVENT);
4 t! {$ P- N3 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- W# p% u5 S7 \# X' H( d, Q) aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) }" w2 E' T' e5 Y0 ^7 c$ d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ c0 F- i2 x" W4 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: t5 y- H: H4 D6 E* F! ~% J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- l& {) D$ P5 B- |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: o( u9 i% [- W+ p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' \+ A7 j' p6 r} # S, o, H5 ~" ?9 O; R- U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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