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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 p; r2 V7 G# ~/ F- T6 H
input mcasp_ahclkx,
$ Z4 a$ d W( ?input mcasp_aclkx,6 N" Z: p1 y7 ~( S
input axr0,# x8 |: o6 ~: X8 J! K
$ ~4 e9 x) C* [ F- W6 doutput mcasp_afsr,% m3 z. p4 c& H: ] }; t
output mcasp_ahclkr,
j8 ]) k+ z& Toutput mcasp_aclkr,5 m# y& t J. l( W. r' y# _6 z
output axr1,6 D7 A, j- K N/ a1 F
assign mcasp_afsr = mcasp_afsx;
* v7 E8 A" Z) f p- }9 e- Qassign mcasp_aclkr = mcasp_aclkx;, ^& Y- ^0 j5 | A! o* c) G7 d
assign mcasp_ahclkr = mcasp_ahclkx;8 `9 z2 S* v4 d+ I: N1 K
assign axr1 = axr0;
& |# k$ M5 K4 l9 f& h) K% r5 J# z
7 N7 `8 E# I; u3 @/ Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & a* X4 ?( J( D8 n- Z
static void McASPI2SConfigure(void)
/ U, W+ z" w5 O{
! E& l/ [" T! w1 ~! w2 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 |1 o* x5 t* cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 y% ]6 x7 x0 r& {0 H4 b5 j' E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( E, O* G- i, HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, s% z0 W7 s5 z7 H! kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ H+ J' d, A8 R
MCASP_RX_MODE_DMA);# J) x5 t3 ^: A& }5 ^( X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) Y! e8 a. P, q5 d0 f0 [7 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ c: h' V. q/ k' R" @) J5 tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 ^0 h0 b# I% D7 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( u: u+ `& e/ y; l3 v, GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' [' M, T/ u' SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" p: M# g O" h& N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- M' H3 {, ^7 F Q" {8 v! Y7 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, I$ l0 O5 j' N5 m `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 o5 V- F2 i8 Y# a7 a2 W0 p- x& \
0x00, 0xFF); /* configure the clock for transmitter */) }$ D" M* D; W V7 A# |3 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 p- L- z% t; L% Q& n4 L1 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 B( D( ]/ q4 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) f6 z& B* P z5 T$ F( e
0x00, 0xFF);/ h4 x8 g" g5 w9 r
- H- B9 ~: A8 ]' C- S; |
/* Enable synchronization of RX and TX sections */ & e' W* f- t) `* M% U$ i. x# r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" @5 g4 M% W+ W- F* `4 R9 I" c0 G2 n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- I0 ~ Q3 J0 B+ GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; V' e f0 q" p3 |9 T6 \. a0 `; P+ j- {8 W** Set the serializers, Currently only one serializer is set as
" |3 F# Z. S0 i** transmitter and one serializer as receiver.; C! }' e4 F. D: U; O$ \! @% b
*/4 v- H+ e. c9 q6 K& r6 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" z) ]0 W( l8 ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; [$ m- H6 T$ V2 X
** Configure the McASP pins
2 ?5 m6 W2 e+ s0 H6 r% n** Input - Frame Sync, Clock and Serializer Rx5 C% q9 u! A" R2 Y: o! a! H9 w+ f
** Output - Serializer Tx is connected to the input of the codec
4 M/ a9 H1 _' p6 r; z*/. Z' G- c6 q# M% p8 \- Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ m8 l p. A9 S0 ?7 c( x: W+ j+ mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 B1 _. P7 `6 Q! B# \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" V; ]- A: K8 `% M1 B| MCASP_PIN_ACLKX( \% v3 O P$ |) g# e
| MCASP_PIN_AHCLKX
% Z( T: O9 n& ?1 i$ f/ {& g( C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# Y. D9 Q. m/ wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: g. b" b0 ~; @4 e+ l0 \1 B| MCASP_TX_CLKFAIL # Z G3 h/ B* `5 s0 O; o
| MCASP_TX_SYNCERROR* k1 j) ?9 C+ `! ?9 w$ X6 L2 Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
\% g% g" V# |: [1 c| MCASP_RX_CLKFAIL
. N' l1 M" N, N. D/ H7 e| MCASP_RX_SYNCERROR
; B' w" A2 ~3 y* {+ A" O& |& w| MCASP_RX_OVERRUN);
( `7 V/ n2 j& g$ F( H0 ]3 _7 e6 C) L} static void I2SDataTxRxActivate(void)( U. F5 N0 e6 y+ u
{3 f, _; M! [6 x- | ~* h
/* Start the clocks */$ Z, V& v0 K* t6 i) G n& c, F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 O+ j, ~: F! C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' O, D5 V3 {8 o; AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, U$ i5 w5 \: d: K2 y/ t; w. ?: v b
EDMA3_TRIG_MODE_EVENT);
' ?# e& }4 s- }! K& ?! JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , i, w) k9 _* S* w; a/ ?. N7 r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* Z" |6 t# J/ Y! XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' b/ i2 w4 }5 Y& I: f m$ E" E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* R4 B6 |% \% N. n3 ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ e1 h* N& \, B. ~% U& {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 ?/ c% a5 H( pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 j# r9 U& L8 `! z+ z9 r! d}
3 E% F* l F* G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & l. p& F3 Z1 O
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