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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* m. M$ t: e/ x- y# {/ N1 i% Winput mcasp_ahclkx,9 [8 g- q* l, B9 _( h! W
input mcasp_aclkx,3 B8 I1 w ~" L+ B( T6 P# M
input axr0,% H4 r1 i" F, B# P2 S' n; I
. ?" |: J8 W+ f3 K
output mcasp_afsr,
5 T: v7 Q0 u4 a/ Coutput mcasp_ahclkr,, ~# @, r, }0 F7 c) G: r
output mcasp_aclkr,
+ G4 y, L6 ?3 p/ V$ boutput axr1,0 s7 K9 I! X3 {! k8 p6 L4 @
assign mcasp_afsr = mcasp_afsx;. U6 _4 s% o- n. P. n) f
assign mcasp_aclkr = mcasp_aclkx;
; b9 m, Z! i' `, Q; X, c0 Sassign mcasp_ahclkr = mcasp_ahclkx;
9 p/ C$ g2 ]& Iassign axr1 = axr0; - m4 {& [2 Q6 l6 B- M1 p: b
+ o# i( @# _2 C& j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) L- \9 _9 F, \) J' T+ g' O9 g
static void McASPI2SConfigure(void)
7 G. }7 f+ `. I6 b{
6 w/ ?/ l3 F9 B- ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( m3 r! l0 ]9 }2 r2 i' `" I2 a- fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 }- H; }7 T1 x" F }( |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 D V% ~$ [7 Z, v6 H9 M( T( dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* z5 y9 K+ o) \& n$ AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ p# L" K {& Z3 E9 H O
MCASP_RX_MODE_DMA);) D! Q. a, D7 Y, |* ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# N& P: W$ t ^$ g" E7 A, w# kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, O' }8 T' M3 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ?2 n3 H! H7 x$ JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); r1 E+ l1 ~* O& b" f* z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! o9 N5 q" _1 y, d4 L" J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 ~1 C# L5 j7 _7 H; L- \$ CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 \ z5 P2 j' T8 C0 I, T2 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' J, T- {( \9 QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( r- H$ P+ B: Y# W5 J9 Y0x00, 0xFF); /* configure the clock for transmitter */+ X+ o/ D; S3 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 Z$ `" z0 y: \; F( k! y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 X" q5 _# S p+ {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* }8 P7 \ l' g6 u: K0x00, 0xFF);4 I/ E8 X2 j8 ^% a8 @# q8 |
' r7 M) d( R Q' z: @( m
/* Enable synchronization of RX and TX sections */
& g( w d" W( x" hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! n( a3 B- Y$ \ q" Q3 }9 }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: q; Z; p5 \( H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 ~; W. q3 L Y9 S
** Set the serializers, Currently only one serializer is set as
0 n" ~& Z9 U1 L) N3 `** transmitter and one serializer as receiver.
2 \0 O: {. d7 X: j |9 \$ f*/( n3 R6 a0 ? Z \3 B: K3 e+ |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) V) _* y: R0 [4 v7 O: [* eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 J* g- U/ k5 U9 V
** Configure the McASP pins
7 Z+ {1 ^# W# L" N** Input - Frame Sync, Clock and Serializer Rx
9 a4 } b4 h9 i* D7 v) ~" c5 ]** Output - Serializer Tx is connected to the input of the codec
! q4 m: S5 ^% l S*/1 J% I% C( @9 I" a) S8 k, M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! Q: n+ G- Z* B3 M% YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! a. A* Z" q& q+ r8 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! G3 K/ B7 r0 ~% J* w7 r| MCASP_PIN_ACLKX: L6 E: t1 _0 z) h# E* x6 T# ~2 R
| MCASP_PIN_AHCLKX# Z: Q& c' g4 W4 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% N$ j" J8 d; A" N W! }/ sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 X( E T& [: P1 A, F6 S% ~| MCASP_TX_CLKFAIL
3 G; ]% `, r2 ?7 t5 F8 M| MCASP_TX_SYNCERROR+ Y& P8 A$ g1 G( G7 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " k; U1 s5 n$ |$ ?, G. c* n, {
| MCASP_RX_CLKFAIL) Q+ B% O2 b& v: q, y
| MCASP_RX_SYNCERROR 5 X- L% S# ? U" N
| MCASP_RX_OVERRUN);
7 m6 K' X0 h; H+ x) H' o} static void I2SDataTxRxActivate(void)
4 \; G/ i \- }; N7 _{% c" \$ i& X' B9 n z: f/ ~
/* Start the clocks */3 F3 K1 Y! {8 Q0 H! d# L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 u C8 e2 l8 c) W* IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; p z( G* u! k9 P3 B7 Z5 \3 Z( b9 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 `8 A. `; ~, R3 g, O: C0 tEDMA3_TRIG_MODE_EVENT);
$ q! y8 N, j' E; X: Q2 G, kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' @7 K( y% A {0 J9 T+ G" G! P* J, y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ l2 L5 P. A0 _2 f& y5 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! e* }: R1 `6 ~7 m3 @6 A) `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 L" |2 u0 |) n5 N; U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
A% ^! @! o: q* p. zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 Q. z! j" t1 Q# Y: q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 J" [2 b4 j7 e; a0 n9 C
} - P1 J. P# R. ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 G4 Q0 x3 [7 N+ V/ ]6 Z
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