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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 `) n2 G, {5 Y4 \- J8 Winput mcasp_ahclkx,1 u7 s, r9 C- A, ]" O( X2 H! g
input mcasp_aclkx,$ h2 v' L! W/ E
input axr0,
# D8 |0 L7 i/ `9 g, |' P4 c6 o$ x' X- n. W+ h+ G2 G
output mcasp_afsr,* j; E( l1 {# C: n3 R m7 e8 S5 [
output mcasp_ahclkr,
' V% F' G: `) toutput mcasp_aclkr,
+ j. ?9 X B' m @/ Coutput axr1,
* L {4 ]0 L, k9 H0 }' q( M1 w F assign mcasp_afsr = mcasp_afsx;
/ D- ^ w. O. T, t5 e5 @assign mcasp_aclkr = mcasp_aclkx;% K3 l; B, Y7 |: v
assign mcasp_ahclkr = mcasp_ahclkx;+ v/ [1 B" X2 X" i5 L$ S
assign axr1 = axr0; , N6 q' D+ F* H
3 D" j. E n" `5 w6 I( _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 X; ~3 U8 Y* |1 J+ {" g1 ~
static void McASPI2SConfigure(void)
$ R q# I/ w/ f8 o5 E8 N. s' L9 g{% T, T3 a9 E* F. y$ Q! u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 T6 R& h' g A% ?! b% t3 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 _- G! H! N( t: u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ G% i+ r: K; \" R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ B# p6 }7 p8 H! G; K; @" M8 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 q4 z) \) x) O- T$ J1 vMCASP_RX_MODE_DMA);" P1 V+ D! X2 _- Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ T! H) O; }- R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ m+ k0 ]+ q# }% q/ R- OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ C9 Y) j# _# a) h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% }3 E" z; O" J& m; dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, B. b& l, `$ Q) Q" M, a2 i% U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. K, ]: C* c0 B& N7 F K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; b/ o- ` Z+ W2 |" ^% N" X/ \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& g$ T9 ?8 ~! k! E0 b& QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 t- r5 H$ h. a/ I0x00, 0xFF); /* configure the clock for transmitter */
. y- [( u: P! B" [8 I' _9 M: HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 V( d/ L$ A- E' S. Z0 i+ r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: U6 L, a& `, O5 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% ]3 O4 |, f+ L# u$ ]8 Z6 i
0x00, 0xFF);8 ]" ?# O1 y2 u+ T
4 Y9 j& Y9 m, t; M8 f% L: w) b
/* Enable synchronization of RX and TX sections */ 2 c7 t3 `- N" n2 f4 R- |9 W- B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' @- y5 P- U/ Z' l' p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. Z1 w. V( v, U$ G6 H" w" W# ?6 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. b1 b' d* l F+ x** Set the serializers, Currently only one serializer is set as
$ l N, p: W4 E2 B$ e7 x** transmitter and one serializer as receiver.
# m4 R. e- o" J+ o; T& ~*/( J+ Q. {, G, b6 U1 B- R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( q8 ]& w9 J1 I AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 d- m8 P/ _, P7 A
** Configure the McASP pins 7 c+ T! i+ m2 r3 k2 I* v) a0 q4 C
** Input - Frame Sync, Clock and Serializer Rx
4 {3 t6 H* ?" W+ g0 }** Output - Serializer Tx is connected to the input of the codec
4 g2 C1 B7 H: [% D*/
% d9 U/ G5 v" M; t* LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 `8 E& F6 t! G1 V oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 x5 P. i) y* i$ Z+ _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ H5 Y/ l- i5 p% {& X' D| MCASP_PIN_ACLKX/ \0 [$ A+ b; h* y7 s, D) D
| MCASP_PIN_AHCLKX
5 k9 l6 Q; j; `: S' ~/ w5 j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 ]: s0 w0 \0 G% p) S5 R" e2 @( n. Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & Q4 z) A2 B* g: H4 [
| MCASP_TX_CLKFAIL 1 T# t+ U9 k3 D+ j- p" K
| MCASP_TX_SYNCERROR7 X2 C9 Z+ ~) m4 R) @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 x3 n! i& t G
| MCASP_RX_CLKFAIL! b3 ^& p+ |7 z9 k; J
| MCASP_RX_SYNCERROR
7 }) r1 |. \- @' [+ A| MCASP_RX_OVERRUN);5 E3 V0 Q8 {) y4 v" Z+ G7 V
} static void I2SDataTxRxActivate(void)
! B d, ^8 a1 e. a" @9 d& \{
2 O5 k2 O4 \8 n/* Start the clocks */
" C2 F% m/ Y4 s- h8 Z. ~% ^5 n) v' SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- e& U P$ ]( U7 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 M" \" m" k+ O& q7 }! XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% J; b* }! V& f( kEDMA3_TRIG_MODE_EVENT);
7 b7 `$ p6 \* V m! c* y0 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 h* `: Y% T6 H7 g- SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 r6 [# `; b# s' w% k: ?7 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 `, w' T V' f. CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ b6 Z, E9 o; P9 Z( {- wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- s% X: s4 T$ T+ eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ Q" _9 m5 H' X) f6 q; X" sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* a; N7 U% ~ `# \
}
/ A# K" S7 O" V7 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 o9 A3 |/ f7 e% b8 G1 m2 o
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