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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 Z+ y( w, O. l; }input mcasp_ahclkx,. u, o% H/ A; ?' }
input mcasp_aclkx,
4 j* N2 q7 o% d9 D% H5 n; Y/ Jinput axr0,, ?; U. m) \) J0 C0 f! X, S: r
, e# [% x0 J ^1 Boutput mcasp_afsr,
r% j* t! I' |, Voutput mcasp_ahclkr,5 U/ V( @4 M0 T& H& j, S! |
output mcasp_aclkr,0 X% q* X! {# O' `' }6 a8 Y
output axr1,
7 h% E$ f m, B `( o" j0 N; m! w assign mcasp_afsr = mcasp_afsx;
! h. Q; o; [( O- ~assign mcasp_aclkr = mcasp_aclkx;/ [# O8 k/ s# n! T- N/ A
assign mcasp_ahclkr = mcasp_ahclkx;9 _, f0 d9 Q5 Q- t7 j
assign axr1 = axr0; # ~+ @7 N C+ ]; N7 k
" o) q( D, p$ |0 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 t1 L/ A4 P& X' |+ j
static void McASPI2SConfigure(void)- _- p1 O `: u- I% n5 K$ L
{; ~+ j7 I; {$ }2 f* ]' G: Q& T9 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; ^# t M; Z3 ^ N2 O }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, E% f( [$ |1 T$ J6 U3 z; |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; T9 D; r7 ~: x X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ a: H. ^; c8 \' W% oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 p" ^2 k+ G3 c9 {MCASP_RX_MODE_DMA);. i) U8 F6 \7 X q: K3 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* I* z) f; y& M% y# xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 c4 r( n- Z: [* n4 T: W9 J$ ?$ \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + _! E( ` a* H- V/ u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 A8 t) f* Y7 x m8 L7 a. C$ t" k# VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : J6 l: ]& R7 y( {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 h1 y. v5 b- k) L) y. c1 I; }! v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& B% u6 J |# K* Y, B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# [+ a# W$ ^ ~! b/ cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& Z" d: O/ e$ F+ ]# E$ E _0x00, 0xFF); /* configure the clock for transmitter */
4 }% J% L1 w' tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* k$ S, U* k5 P" r) F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 U' f* A9 d0 [( I6 P F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 m' w5 {! F' { s
0x00, 0xFF);
# \: E8 p8 R% c5 f# G9 t
* r. q( T# `" h1 W/* Enable synchronization of RX and TX sections */
4 @6 {/ p3 b% t, A+ OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% Z ~- Z8 r5 N9 o5 x1 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" ?* H0 C* r: x9 X# A: HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: e2 g& p9 s! H; X) ~** Set the serializers, Currently only one serializer is set as" Y) E7 }# J. M! j, R
** transmitter and one serializer as receiver.: L% q2 f1 m' R% f* j
*/
& H8 i7 \9 V, x& ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ @- b( U5 l% P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 [9 J6 O ?" A' \** Configure the McASP pins
& u1 K6 i' X, ~ [0 e, Z# p0 B** Input - Frame Sync, Clock and Serializer Rx8 o; ~. q; F- D, `/ v n) s- T
** Output - Serializer Tx is connected to the input of the codec
) E X( A8 Q7 P ^+ E2 D) Y, d9 V/ E*/
* [0 O# a2 B5 d9 L0 x# \5 P7 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ {/ p; R8 [: K3 q9 Y% u& ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 K, M. p& V2 B1 ~& K5 N2 L% F$ PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 f/ T; v% _3 ^% V5 k' A1 _4 [
| MCASP_PIN_ACLKX
! [2 a2 g, L+ i# o| MCASP_PIN_AHCLKX+ q1 b5 v: q& K5 D8 E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 P' K$ K4 M* I; S2 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR V! |; O6 B; `
| MCASP_TX_CLKFAIL 6 Y2 P) f, G5 K4 t" h) f3 ~
| MCASP_TX_SYNCERROR8 S/ d$ z4 N/ A5 \& J, m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; B- o% r O: f: n( S W| MCASP_RX_CLKFAIL
8 Z# l7 J6 v! B7 V| MCASP_RX_SYNCERROR / N5 _" x. g. X1 @+ J% f; h8 h# @
| MCASP_RX_OVERRUN);+ Y8 _# r- ^) v# O I
} static void I2SDataTxRxActivate(void)
4 q+ c6 T+ L4 M- D+ @{
7 L2 _+ N- } ]6 r/* Start the clocks */* H# b3 a! W/ C. C9 c8 s' e [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( h, p T( I# p" I) D: W7 @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 G7 f" Y$ ^% ]$ W* e# e% O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. f: N8 w. P1 |5 E3 Z L5 \: G
EDMA3_TRIG_MODE_EVENT);5 s2 }: y4 d$ s$ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ e: J) H- d: N; o# bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 u* c( q) H1 t! S& k$ @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ h+ {( N/ F8 c: V6 H# Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# e& j. q1 ^ T Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
S3 `, F4 U) x& P% n& IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 I# j2 j- Z ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 s Z7 B1 x0 o+ v' [- F2 Z}
/ t! M: t' A6 w4 p- G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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