MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
, |* u! i# n" ?4 ]% H) _input mcasp_ahclkx,
input mcasp_aclkx,
$ ]9 U" L' Z! u. \input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
# j; S  E) C1 Q' Doutput mcasp_aclkr,
, z( E' W! A, V. D6 j8 y/ \8 houtput axr1,
! d- t# @2 m: s* L

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
8 a3 i6 t0 b5 s" w5 Passign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

) d1 n  u) I9 r1 m4 F% @/ G2 c2 E

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

/ ]3 t- G7 p+ d4 J

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 c2 M) c5 f( uMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
$ }( g* I! s" L% [3 r  vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; o' E% `  n! K7 Z: `# ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% z) D) B9 i) ?( }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
0 o/ `* f/ u* J5 `" r" H6 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 e# x- E& ?! E; w1 m/ s9 hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 X1 j1 Y  j  V' V0 W: z) _+ @0x00, 0xFF);

/* configure the clock for transmitter */
9 [0 u0 ?& _; O* k  H' e: ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. W, @- p, i4 z& MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) A- X' ]" S6 p# ^' ~8 {+ T- vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 e' H8 \; y! @7 o0 I$ m; e4 i0x00, 0xFF);
8 y! g# a5 w( ?: _
/* Enable synchronization of RX and TX sections */
( i! s7 I/ a4 l! |1 XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; J4 i0 S' d. F3 oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' l. z6 D" r# g3 ?5 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
$ U" L, g* y9 W*/
3 d# y, I3 L% z0 ~4 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
& M2 {+ w  e# l. M  Y& e** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
3 ?1 i. q# E4 F4 g$ J: b*/
, {" L# V5 k7 g. y, K6 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ ?; K- h* J2 e# V! h; a9 U" JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ Y8 @1 D# P+ J$ n' i: m| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
- G! m9 M) E4 V| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
- l& ^3 p$ K( T7 X( L( ]% _5 NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 V. ^) p  G; ^" p| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
) P0 n/ x$ m( _0 B' O| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
) @4 g7 ]. Q  l$ ~% I| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
+ @9 P' _" j, c: r{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
7 r/ w* n# g& h- eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
  A3 l+ k8 i& s# aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
, T! C  f5 S; V9 U, O* }9 \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( q5 ]7 G, b5 CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) _0 Y& S8 R+ E; |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

" m% e/ t- o# u7 j

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.