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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" \: {, L3 Z' y9 z1 tinput mcasp_ahclkx,
) h% C; s6 M- Y! F8 _1 }0 k4 ginput mcasp_aclkx,( h1 E; R2 z4 C4 l+ {1 k
input axr0,) w2 S @, ^) k) G) h; i w
( L( F4 _: c: T* X7 Boutput mcasp_afsr,/ i9 N$ l1 U3 d0 z2 K
output mcasp_ahclkr,
( L$ ]8 y& \& q% ?$ m F- ?output mcasp_aclkr,
, P( G/ w: x( f8 d0 j2 Foutput axr1,1 K0 B6 s; J7 f, u/ h* \
assign mcasp_afsr = mcasp_afsx;* @" U2 F% `. e1 f( A J! c1 l' w
assign mcasp_aclkr = mcasp_aclkx;7 g- C, B' I' ~! @
assign mcasp_ahclkr = mcasp_ahclkx;+ R0 u& \ F+ Y$ Z' k6 c
assign axr1 = axr0;
4 S+ K; p ^' t$ Y
, y& S o( r% u6 e6 B) b% R& K* R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- G' y" \# |- Q# _$ S$ E: \% b2 istatic void McASPI2SConfigure(void)' S6 R, \) L' T8 Y' ]5 q. x
{. j$ g$ K) k1 P* E5 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% i3 P' d/ L! S( d! t/ n: M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( _7 v5 v$ ~2 |. \( Q# R6 h, E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: e+ z& ^+ M m5 z& w; Z0 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. S& T6 G: c; x* j6 z5 K% A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! ^+ A0 r/ f2 o& v% \8 v; }+ \MCASP_RX_MODE_DMA);. Z' ^% q% }( e1 a* i) Q5 a+ n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 S( [3 i r6 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, g+ A; M, a+ s0 _8 f v* W4 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 R, m1 B/ T" Y" C) @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% M8 t8 B/ @- J/ X6 D; {7 Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. G* B1 U s- dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ \! D% \$ ^6 z1 }& U% @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 W( ?7 @) s: t, P* K# T% H1 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 q d) j9 z! N+ b" A' zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, g9 A1 P I: |. p6 j" h5 [0x00, 0xFF); /* configure the clock for transmitter */
! c+ z8 z" Y6 a" z/ o, { }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 B3 O s, O4 w9 i8 [3 A6 ^$ H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 g' ^' Q) i8 o7 s' ^6 A2 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& J# ]9 _# F4 k9 {) X2 H
0x00, 0xFF);# Q, n/ c% @8 b, K
$ K6 } o9 Z$ X# q8 b: G8 R/* Enable synchronization of RX and TX sections */ - a& D2 Z( E) [' |% o! y. q8 w5 g0 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 v3 x) v, n- UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 U' s- m' n/ H0 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 T/ { o; C M! ~** Set the serializers, Currently only one serializer is set as9 ]& A- P% {5 d/ L$ e$ q' f8 \
** transmitter and one serializer as receiver.
Q4 P' Z1 `# E9 @0 a; W) Z; l*/
0 \ [( V U4 z- V" \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 d: l; `, ?6 F6 J, l4 c lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 ~, c- N% _$ F1 h8 P
** Configure the McASP pins 2 b2 m/ [7 a0 \- [
** Input - Frame Sync, Clock and Serializer Rx
! f" y6 Q) P3 Q) l8 p1 a$ F** Output - Serializer Tx is connected to the input of the codec 9 y3 p3 f, d# d' B( q: m: z a
*/" O- j2 M& F. x& Z( N6 N9 J/ P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 I7 | E; y) K( s" u; DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: j# Q4 s- ^* I8 p2 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 Q0 V6 ]. c" ]3 {( [' M9 Q6 `
| MCASP_PIN_ACLKX
/ t3 v* Q4 M& H( S" e" Q; G q| MCASP_PIN_AHCLKX1 T8 E3 V+ R0 l& s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 @6 z. L6 ~4 p. oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 t" T. B/ o: u) c| MCASP_TX_CLKFAIL
& p) A3 n# b8 N& J, k) e1 `& Z) l| MCASP_TX_SYNCERROR
3 D K- c; y7 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 n. F; V% }) u* C7 j3 D+ _| MCASP_RX_CLKFAIL
- n' j: L2 H H. R' _| MCASP_RX_SYNCERROR
% i9 X$ K t9 v+ _| MCASP_RX_OVERRUN);
8 Q3 z `9 Z8 Z/ P5 F} static void I2SDataTxRxActivate(void)
+ @2 D0 p6 A& X+ ], A5 _$ h2 }& M% b' K{
- g f! h5 [% w. u" G0 Z/* Start the clocks */2 d3 M3 ~0 J( p0 x3 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. I- w5 x' a$ F& yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' d1 `8 h( {1 X& P9 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 s5 r* D- K7 n( \4 n! \
EDMA3_TRIG_MODE_EVENT);
/ F& D4 v' R4 z6 s0 {+ c9 I$ C' w. GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 W! B+ g6 m: x8 C; L0 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; {8 n" b* C0 ]; M& M- U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% b, f( _5 }. X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% j. _, y$ V0 f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# o, v: A' ]* s; E9 S0 ]2 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) B8 s6 M; v) ^7 b5 o5 W( CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" \& Z+ A6 B# n0 A/ H8 ~& d/ g6 t# k
} * c9 y3 C& m- J1 W* Z; K9 E; W4 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
l8 a8 T. @: u |