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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 q2 P; z, ?$ ^
input mcasp_ahclkx,
" k! H/ Z8 |1 K- Ginput mcasp_aclkx,
& y: R# f$ k5 J# V `& cinput axr0,+ r7 {; Z( f' o8 I; p# O
: o( r3 D4 j; D2 P0 n
output mcasp_afsr,3 S3 x9 R! U6 E
output mcasp_ahclkr,, b T2 R) [ P1 Y/ g: H
output mcasp_aclkr,% b+ N N& T' v
output axr1,
* ]* b5 U, j3 S: u! g1 u0 W assign mcasp_afsr = mcasp_afsx;
. [# R+ @, E# }assign mcasp_aclkr = mcasp_aclkx;
$ B& R. w) R }" `: J: Vassign mcasp_ahclkr = mcasp_ahclkx;6 w1 ~% v; ]$ c9 I# i" e. R. B
assign axr1 = axr0;
5 ~. k J# E- a
* B$ d* _( Y3 I+ x& ]8 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 T g4 w/ i3 i4 F4 {static void McASPI2SConfigure(void)/ S% o& [/ w1 e7 o/ }% u% V4 ^
{
' ?! Z$ M- d2 U' kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ Z* M" x6 q5 n5 z7 \1 Z! s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# a6 R* A7 A G' a& _ e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" S6 s7 G0 P$ A$ [4 p Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% u3 Z$ O9 W) u M. A( r7 _$ N6 I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ a* D2 M6 L2 Y4 q
MCASP_RX_MODE_DMA);6 ]( x/ v8 m9 v Z; y6 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 `$ `5 [; e0 y2 {7 e. k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 i Z& |$ T I) zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . D- _: z1 H2 b- N6 p2 h$ U b. [% q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% v% k9 N2 \: D% V* Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * _/ t+ X( i( a0 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; p7 j2 @8 [! D( r/ d9 v" GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( u* y ^2 V: D- [: EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# c6 l$ T9 R1 R- F- NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% l4 M0 n2 o7 R$ N# g3 \9 A7 q( J0x00, 0xFF); /* configure the clock for transmitter */
+ @8 s$ W& w; l7 t1 J$ C# kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" ?, F5 O3 M9 Z1 M" v9 H/ t* xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 _' g9 ?. w$ P: Y6 _* wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' R# K: v: S' c8 n+ a0x00, 0xFF);1 a/ `! f" N6 m: v- m( n/ Q- W
+ y, N) Q9 p3 O7 B) O0 h/* Enable synchronization of RX and TX sections */
8 y& `+ d3 {9 h) MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* i, T; y) X, F9 r: b( ~) P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; ^% y" \% e6 D, T- g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# b4 l7 k0 y0 \9 C) Y% C4 g** Set the serializers, Currently only one serializer is set as2 i: [! w1 j; ?4 d {
** transmitter and one serializer as receiver.3 Z( v8 F9 R! n/ z3 i
*/1 x8 c' p2 R5 }: u; b3 T5 w; g! \1 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 T2 ~, K1 I5 x/ w5 f5 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% O) o% R* z% k8 l** Configure the McASP pins
- a( W' V/ @+ j** Input - Frame Sync, Clock and Serializer Rx
, c4 M& a0 i8 ^' ?! n+ U** Output - Serializer Tx is connected to the input of the codec * ?+ [( k% ^) r5 E4 S1 J' O
*/
$ s/ g. C. Y5 n5 k0 i, ^* S( pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 O; \# @$ ~6 n) u$ i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 f0 y4 h+ G8 d/ Y0 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 v) z7 l" l) e" y& m0 m| MCASP_PIN_ACLKX
" l: x8 i4 J3 u5 i# q# {| MCASP_PIN_AHCLKX9 J* {2 B2 W3 i$ B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 I r3 i" b' p) L0 b4 A) k' Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
D# d$ o1 R q7 a! p- T2 X| MCASP_TX_CLKFAIL * A" a# k2 T. o1 @ w! L
| MCASP_TX_SYNCERROR# h* u, {% |. l- u0 f1 W7 M) u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' V2 U% z: \- v5 @) S* D" d
| MCASP_RX_CLKFAIL
# B! c4 N, n7 d' P$ [" G| MCASP_RX_SYNCERROR
2 P) G/ i; G& I% Z. ~/ F" R| MCASP_RX_OVERRUN);
6 i: G T' K' |0 _, Z: p; v2 l8 Q} static void I2SDataTxRxActivate(void)( q! N- L7 e% P, s, k8 I D. }
{
, z$ v7 F! @8 |) S; r/* Start the clocks */1 R1 {3 f% ]/ ~! i5 k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; D5 u9 O u% j& F. h ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 h2 Y7 {6 K( H, Y X- [. T8 _0 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ J6 r6 e6 |8 l5 D& U& `2 {- q; ]$ ^EDMA3_TRIG_MODE_EVENT);, \& R J5 W7 C$ v/ U" Q6 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, o8 C0 d2 q. d' O% O( j' ?/ H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 Y% _' g% d5 C1 A- Q3 r; p' D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- m4 F" z$ k$ AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& d( N* `! R" f6 ~- L0 B, \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* \. E7 Y3 e/ @1 p7 |/ U. p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% N3 B% D$ F! c* H) u# P5 g4 v! }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 z1 R( N b Q& ^0 W5 k5 V}
- z4 Y3 u! }; ^# y- [0 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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