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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& P C. |* s, {) q2 M/ i
input mcasp_ahclkx,0 v% }7 P' M7 O/ c# E; m& M2 F+ A
input mcasp_aclkx,+ {* d; _9 n4 I4 t
input axr0,( O1 ~" z+ E& L2 P+ B) Q; a% N
+ ~, q5 j) O% c4 O$ v; m0 z
output mcasp_afsr,
; Z# o$ j- [! T% y5 i3 t3 Y$ Voutput mcasp_ahclkr,
" |1 Y2 c3 ~3 j' B# foutput mcasp_aclkr,2 X/ a u; N) O) B
output axr1,
- i7 o9 W, T! O, Y [2 n assign mcasp_afsr = mcasp_afsx;
" X$ G3 d' p% j% F$ F* hassign mcasp_aclkr = mcasp_aclkx;
8 J9 s6 A% ]0 ]assign mcasp_ahclkr = mcasp_ahclkx;
( n; d6 P7 g: iassign axr1 = axr0;
7 W4 m& j |+ X* M4 z, w4 V
/ l- `& r) {7 a/ r0 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 u/ x; S) L7 L Y/ J, Q6 T
static void McASPI2SConfigure(void)' X/ q2 w1 q) q! z$ k" @& a: d
{3 v: b0 r( b. [$ g) C0 |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, {4 X3 d4 |3 V( M8 l: O. @( zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 E3 R+ E: s2 s7 x8 l! b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) x" x/ j: c5 m2 ~+ rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 `( _+ o4 w0 o! [% \4 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 c9 _2 ~- W3 ]
MCASP_RX_MODE_DMA);
% Q: R( m- }* I# P; m) Y" [, O% h+ UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) l, } a1 V. h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# \0 I4 T. g/ f" F# t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# `5 J- O+ ]4 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ c' m* j. a: @/ O+ {% M ?6 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) G2 B0 w) V3 f2 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* D' X1 `" A4 G! _1 u' Y/ |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; S" } o! n# Y& J' n: A$ I3 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: [, l; J& G% |- e$ |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ e1 t2 w7 ?& K/ T: ~9 R3 g0x00, 0xFF); /* configure the clock for transmitter */7 X& `9 l; p3 j" O6 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! n: m! ^* [% J1 r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. g! @9 [, ~* \8 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& g/ v6 g) e A3 X/ X; q0x00, 0xFF);
0 u, x' E: ^. U" w& l4 c, |
- i3 R2 H% |. v. u- ]4 I {/* Enable synchronization of RX and TX sections */ ! R2 {& x7 J& @* _& \9 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" x* K) m h; Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); ~# v: ]/ X; [2 c+ G! C) Q5 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, U! L! C# }3 J$ s9 a* G" i** Set the serializers, Currently only one serializer is set as
) B9 W2 p! G: |! G7 O; q0 V5 B** transmitter and one serializer as receiver.
) J. A2 g0 u9 } m6 c0 d; A*/2 f) U; q% X* t# C0 k* E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ H/ R5 H- S, w) k( sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 C( U' i, f! s# G* B! W** Configure the McASP pins
1 @/ Q1 I/ |1 E6 ~8 y) N+ C** Input - Frame Sync, Clock and Serializer Rx7 k! v) H/ X+ { S
** Output - Serializer Tx is connected to the input of the codec
* Q& n: o2 ?5 H1 ]% k( |4 i*/: y$ ~3 t$ I" W' l) ~) v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 Y4 S, E% s2 y$ c0 z9 M' nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; }2 T7 O8 a8 x r# SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) P+ P: c2 s3 i& K| MCASP_PIN_ACLKX
, h) b$ j. a, U6 u; b| MCASP_PIN_AHCLKX9 g; e% Y" X y2 E" M A# \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- V# G' s, q+ s5 c6 _+ S4 A9 [5 G, U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 |0 v- I- T1 \( O7 ?* `
| MCASP_TX_CLKFAIL + f' ~# ^ w7 |" Q. }
| MCASP_TX_SYNCERROR
2 [' M9 S- \/ `% d) a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' a1 I) p) a* B4 p& P
| MCASP_RX_CLKFAIL% [! W; c, d) z5 t0 j# C
| MCASP_RX_SYNCERROR
" f+ u# E9 ^$ Z8 f+ M) U| MCASP_RX_OVERRUN);; u, l. P0 c( ~/ u3 l8 y5 w) V% i4 `
} static void I2SDataTxRxActivate(void)
. i2 F0 ~8 z/ @2 J{, d U6 E1 }# k' k
/* Start the clocks */
! N! n# ]' ]- b; U( w. ?6 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( H5 h3 L0 @: g6 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 }( M5 K1 v% X' g, k; b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 T) `$ s$ C) p7 x/ pEDMA3_TRIG_MODE_EVENT); w1 g3 `9 c& U# d* l& B6 Y4 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 x: Z% S9 ^1 R- F5 k2 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- Y1 m2 [6 }1 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 O* c. D, ^% IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& c% V6 s1 g# l# i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 g+ Y& y. U& J7 v" C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 J3 E5 M' ?/ D& g2 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ B. U8 a/ ^2 d" H' T1 f3 Z
}
7 X5 u' l( U8 C5 b ?2 _6 B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 Q; z5 u: _, x& @- s' c
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