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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! H4 Z: x; P0 f6 V4 @2 F! kinput mcasp_ahclkx,) _3 Z! G t$ {& g- v
input mcasp_aclkx,+ {1 S4 O) F) c, L) l
input axr0,
2 [4 X; F; z- C' v3 P+ ^2 Z: Y' v5 W; Z
output mcasp_afsr,, B2 p& `* M7 S+ T& f: F6 ]: k
output mcasp_ahclkr,
# j. `+ K! Q7 T I K, f' coutput mcasp_aclkr,9 [/ [4 a) y3 l0 G3 X3 a1 h
output axr1,, X4 y% Z; _- J9 f0 X7 }" H
assign mcasp_afsr = mcasp_afsx;
: j; V9 q5 d/ D; J9 C. lassign mcasp_aclkr = mcasp_aclkx;
; x- H7 h1 [! s. N( lassign mcasp_ahclkr = mcasp_ahclkx;
/ ^) i# O1 a) y+ k( [assign axr1 = axr0; $ Z* l5 j3 y3 g! J2 w9 R
# I8 z. a* }* R+ {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. j4 g5 V( {; O+ { sstatic void McASPI2SConfigure(void)+ x( x. N; J2 k# K' q, Z1 [" K/ |
{ ^0 N9 E8 \( r" ]/ k$ n) r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 M' m+ A% H {0 o+ U4 I% u. m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 k$ Q0 E2 ]2 X) u: T2 S- U1 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ H& }0 @) l: o$ a" F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- `$ n& n& |6 D" L# N8 ?6 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ]7 K3 a/ L) o7 Q7 y3 VMCASP_RX_MODE_DMA);
5 m- I# B! |* J" XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 b8 B4 w# f! ~4 u& d( o1 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! y9 @4 x- [% p6 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , E& i1 r+ _- |) k D/ b( g" U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); V. M) [% [: _4 N2 h1 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; [/ }3 K6 W, PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& q2 n$ n7 c9 l% ^- B5 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ H; s4 I0 U" N- d1 _" E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ }0 h3 Z; P6 \# y0 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. ?: |. A, O6 `! K0 O7 W6 B0x00, 0xFF); /* configure the clock for transmitter */
4 Z/ @" m u, E) c ~( c) s2 t' |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 f) R. ~/ {8 w9 B! u$ {7 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. h; k3 \* J) jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 G& O3 W' F7 a) U* A& r& l) ~
0x00, 0xFF);
3 H3 d$ s! d& v+ ], f
* u3 I3 R0 T5 O# S! x9 C R; u6 r/* Enable synchronization of RX and TX sections */ / G$ e3 ^; }( w N7 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" O" g! e& [$ o1 Q+ S& ]6 w& p5 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
U+ A: o/ b7 U4 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 Z' `' ^* h* h( h9 t** Set the serializers, Currently only one serializer is set as2 J, e. M8 e) l9 Y( l; _. t* G
** transmitter and one serializer as receiver.
. e. x8 w% Z* P- u" M*/* f/ x+ a) p1 m$ p0 c/ h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) i) G7 i! M! K6 s3 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% t# A1 A! K1 R9 W** Configure the McASP pins 6 T+ I6 l3 ]- C+ P1 z0 ]
** Input - Frame Sync, Clock and Serializer Rx
1 i h+ C+ }" X4 P4 I$ J1 q$ a1 k** Output - Serializer Tx is connected to the input of the codec
/ g, v/ @% n3 z( B" [& k*/1 ]+ ~. y; j0 B6 z6 S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, F, g7 k$ Y- s& `9 h6 {# B' k o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 H4 o) w! D3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" m4 G; n4 g, l- }* o9 V' }" k
| MCASP_PIN_ACLKX
/ i% A8 v1 p+ Y+ H! d| MCASP_PIN_AHCLKX
: S* ]) A1 p b# X4 l* L) P' c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" [9 d0 W' Y0 s7 V: h' i- T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# _) [, H& u$ k$ H1 G| MCASP_TX_CLKFAIL 5 G) f. X- z" E/ K
| MCASP_TX_SYNCERROR4 Y5 O0 k. p" ?4 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( a0 [) X5 {/ w6 w9 K| MCASP_RX_CLKFAIL
( ?$ j2 E4 k- w| MCASP_RX_SYNCERROR
% D6 ~$ f7 J, b5 t) N| MCASP_RX_OVERRUN);
8 z3 O& j; t( I$ J} static void I2SDataTxRxActivate(void)
, A' V* z; b( _. ?{* {4 p3 ?- J; t- n$ q' [, Z
/* Start the clocks */+ K& p1 b" z' _0 s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 x2 t" _9 l" c+ l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& N: q5 {' d8 J* ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 B) m/ p: T6 W9 |1 zEDMA3_TRIG_MODE_EVENT);
. O* D" I' u6 R+ F4 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 _0 t7 L2 s# C% qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 ^0 S- L' o( c6 g$ l& a; X9 F: n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' e4 g) ~3 W3 Y/ ]5 J8 \1 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; z4 x* W+ I" C, l% T# p3 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 o# m2 e, I. \$ M8 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# K( P6 ^6 s% G: b1 J) ]# b) H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: \- g4 w2 M1 S/ E' I; H; n3 H
} * G: F5 {' N8 j" L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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