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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 K, i3 [ I6 R6 w9 c; A. Winput mcasp_ahclkx,5 t. z& Y) W, F) F/ P: ?+ E4 D
input mcasp_aclkx,( j6 s8 |7 K* t0 O+ j O0 x
input axr0,1 n- |3 P' O0 P! O
6 c1 Z, a. [- b% g! A6 M& y/ x- Y: Uoutput mcasp_afsr,
6 g7 a q7 _8 I2 e. f; ioutput mcasp_ahclkr,0 ?2 ]+ R J! k4 N
output mcasp_aclkr,
6 b$ g$ w X' K$ C# }: ?output axr1,9 S) u( ~ X6 U! v9 @4 T% e# l
assign mcasp_afsr = mcasp_afsx;
3 M; Y+ {; a# f: kassign mcasp_aclkr = mcasp_aclkx;' w& i5 d* c& O) W$ P" x2 K
assign mcasp_ahclkr = mcasp_ahclkx;% P3 U% L6 ^% R2 a+ O! o+ D$ D" x6 i
assign axr1 = axr0; 1 q$ p* k: u$ F- e1 |8 ^' ?
, h+ T7 ?4 T2 h+ j5 R7 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* |, w% G& g5 i* ~1 qstatic void McASPI2SConfigure(void)
" Y' u% \& P( [+ y4 k6 g{/ ^3 q: s4 a7 i6 ^. o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ T, c, T" j# F: P9 v2 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ T _: T2 G) B" V9 b8 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 K* L2 H" ~" Z, a; {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( @- ]; `& W0 l, s2 U" h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) D A' X g- w2 \: ]
MCASP_RX_MODE_DMA);/ z6 K0 l) A6 q# E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' o1 M$ Q: j# \9 I: v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 E9 T, W& q" \ H" u% u6 S2 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 O; {1 B8 h4 c: P8 r; E E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) r1 K0 h0 V+ Q9 w+ Q5 h3 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 S. f7 S/ ?. r( uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 d7 M' |) b! f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% x2 i8 w5 X0 x" R% s6 a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# ]2 A3 n4 T. sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( E/ Q8 `+ k, o4 g' o% i) D8 p1 K0x00, 0xFF); /* configure the clock for transmitter */9 |& z4 Y$ H' D U/ ~* P6 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! e( J. p) C: _7 Q0 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- R4 w7 _: a" p6 rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- `) j/ t* l# ^& N0x00, 0xFF);
/ U, H8 A6 M+ r% N1 S% U/ j( T5 s( o) m7 n6 S$ b/ u& F
/* Enable synchronization of RX and TX sections */ 8 @; E1 p o! ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 P' O3 Y8 F; U! IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* S- {9 `3 x7 o& C7 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 V: n6 A- G4 X/ p( g) m7 X7 t2 D
** Set the serializers, Currently only one serializer is set as. m3 H+ V- a, Q
** transmitter and one serializer as receiver.
' q- m9 V5 d& T*/
* n/ Z- ]2 q r" X0 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- I2 J. W/ e7 F9 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# j+ V) N% i" v& E** Configure the McASP pins 0 q# ?- x5 A [: u
** Input - Frame Sync, Clock and Serializer Rx/ W K8 e' ]% M8 i" D
** Output - Serializer Tx is connected to the input of the codec % W8 M5 S0 U7 m: E/ z0 v; m
*/
4 g0 Y. E9 [; c3 _+ lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 Q$ A* \/ B3 I4 I' Y6 c4 f+ W5 M( F3 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- G8 b' K2 I, K' n) c. uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 H% G" w" S$ ^- a
| MCASP_PIN_ACLKX
8 R' d2 b! V8 ?2 D! P+ z* Z# T| MCASP_PIN_AHCLKX( b/ z9 l- f1 {& q( A: h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 s/ z0 r, i% v/ [0 ?/ F7 `. L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ v& u' _# {! m' T
| MCASP_TX_CLKFAIL
5 {2 r: V# }/ k+ W' C. v) W| MCASP_TX_SYNCERROR
/ W- Y* B( b9 ^ M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 Q3 I1 \7 m5 z$ h
| MCASP_RX_CLKFAIL$ X% ~- ~) J, i2 E) u2 `
| MCASP_RX_SYNCERROR 8 }# i' ]8 k" p; h7 z) v
| MCASP_RX_OVERRUN);( T8 E( ^) Q) b3 R! ^0 k0 ~( v
} static void I2SDataTxRxActivate(void). r( A1 I% C0 Q" B0 y0 x
{4 F- E2 ?! {# y' H) k* g
/* Start the clocks */: H1 V3 A3 ]& W1 I: o4 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 }" h9 g% C# s5 Z/ PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ x' ^0 c+ A: h% _' wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 @! G' o% }+ o6 I
EDMA3_TRIG_MODE_EVENT); j( ~0 j5 ^# E/ ~) t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 Q: ^* |' N8 ^8 ~8 P5 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 C& R- _) }1 S4 K6 U) ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ s7 P% h# \0 O9 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 w& W0 j% b0 r |$ N$ T/ Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ b4 r3 D. s( _2 y4 p) a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% g' Y, o/ l, z+ V" BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ U1 \- v" ^; q) f" Z m; d' v+ ^! X} . @ g0 R; ]! M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ ~5 ]8 A1 k$ B" q
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