|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 t/ ?* k" A( I' n7 y4 n9 c$ _# Uinput mcasp_ahclkx,# ^9 L. B) ~( v! m7 j1 x# e% O
input mcasp_aclkx,/ G! i& p, k! C. A1 P2 ^
input axr0,8 S9 X: M" r. [3 l/ Q( J) n# i
1 F& I6 U1 g6 `9 y. Noutput mcasp_afsr,6 Q7 D/ g, T# R2 }% j7 n1 [
output mcasp_ahclkr, g, @% X5 |$ _7 l9 N2 W% a( X+ ~
output mcasp_aclkr,
% K- ^, ]: F7 x0 [* O( K5 Doutput axr1, K, H7 F# ]1 _" h% |
assign mcasp_afsr = mcasp_afsx;
+ h$ B$ v9 p* W2 Hassign mcasp_aclkr = mcasp_aclkx;# ^3 q, E8 e4 ~. X/ S* j
assign mcasp_ahclkr = mcasp_ahclkx;3 W1 K7 Y4 U! M0 u8 I, }2 W9 D
assign axr1 = axr0;
) Z0 c2 c" P4 C7 o# A; Z9 Z+ e" X% f( C, ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" I) x' c+ O- b1 M7 \' C! Estatic void McASPI2SConfigure(void)
, o: H* t3 w# A7 f1 X{
: \4 l" b& H9 N& m7 { w/ W/ i- a, bMcASPRxReset(SOC_MCASP_0_CTRL_REGS); s, Z1 e k2 \# ]$ J. I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 h- G" G& z/ X& p6 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ }2 n' ^$ o. f7 {' n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// i( E& A; u9 F% I7 z, P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. t: O- K+ p: ~
MCASP_RX_MODE_DMA);* [, o# h7 e' |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, Q$ }0 d) h* e' V* i: p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 }7 j/ ^% n% x& l# O. x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! G! w5 c, L+ j m+ L6 h6 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 P" u# y" g6 g0 X2 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 x, Q7 L+ u) ?; m+ sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! A1 g/ m+ W9 }6 R# ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 d5 T- f, }, L. Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Q- ?# Z1 \) }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 }2 b' c9 b9 g% x# {. H
0x00, 0xFF); /* configure the clock for transmitter */0 F+ k2 [% G6 c4 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. t8 V/ L7 i9 }, g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * \' D- ~. s$ T9 `4 R! b0 [% P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," m& v8 M$ ]+ j$ g. g6 b& N
0x00, 0xFF);
6 K& Q. v6 a& e e( S. i9 n) n0 B% S
/* Enable synchronization of RX and TX sections */ 6 |+ C2 @7 K2 B. ~" _% s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" t& `! @! `5 m' m; tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( g$ A; P7 q g2 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 z/ e; w8 C; @) U" k** Set the serializers, Currently only one serializer is set as8 P; w- _2 }5 L; o5 K; b
** transmitter and one serializer as receiver.
# |4 q# G. D1 H7 k*/
4 W9 ]% d* A1 C9 R/ tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 E F* Q/ Q( y! q& d2 A: E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, w" X, y9 e; |3 Y
** Configure the McASP pins
/ E0 f* ^. S3 ]1 F3 q' A' @** Input - Frame Sync, Clock and Serializer Rx0 _8 ^! R5 O0 }2 v
** Output - Serializer Tx is connected to the input of the codec ' j% n( a6 u6 G* A# W |
*/
# {* J) H# J9 K4 z$ E6 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( l/ W1 _, E2 F, X' p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ S; [: i: I. Z+ Q1 j3 n' ~( c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' M2 Q0 P5 |1 F( N& O
| MCASP_PIN_ACLKX
9 X: q1 T3 e, Y9 u8 k| MCASP_PIN_AHCLKX+ X* w2 f4 k/ J* ^$ _* n1 ?5 z6 t* l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 }7 H6 U$ z8 |! B! l/ cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 l' m0 ?+ s/ r7 b) S+ h- n
| MCASP_TX_CLKFAIL . p9 a/ d( z7 u8 N O+ O
| MCASP_TX_SYNCERROR- K5 I% h) Q( O1 P2 @! Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . C/ ]% O& [. x
| MCASP_RX_CLKFAIL2 r0 d6 h" _) R" q; z5 d G1 O
| MCASP_RX_SYNCERROR
! u M) g* G' J| MCASP_RX_OVERRUN);7 t9 m) V+ p1 o* g. ~
} static void I2SDataTxRxActivate(void)
7 a0 S) V( o( v. _ b( ^3 g{
: ^. U& l3 L# t$ n9 L; t6 i& ?/* Start the clocks */) F$ Y) D8 _0 c3 g! C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) N6 Q, v' P0 [# B" K2 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" k; u5 t) {8 `& K+ d) Y9 a2 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 v. P# H! q) F. a2 Y9 d! s6 d! N" E! r
EDMA3_TRIG_MODE_EVENT);
/ m* n! a% \8 z" uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . d: m+ m+ a, A3 L2 D& L3 S/ F- ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 v! D5 D+ R% B7 d, a! q$ r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
B1 R/ @- e" C" D( g# @8 o gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' S% d# \. D( i0 |( i* `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; P7 W f1 O9 q& U# {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 |+ Y! A( E1 p3 i( ~: Z8 }+ ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- m7 g7 u8 g: I. g3 J# g
} 0 F" l9 j4 c* v* S' z, E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / y+ v8 j! W9 N4 H! e
|