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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 Q$ ]3 ` G9 C. |0 @2 U2 Vinput mcasp_ahclkx,
, x; X) D+ J" c% Finput mcasp_aclkx,
7 N. {9 C) L U0 `! ^8 I1 |input axr0,3 J ?- p# {3 S! f @) J
; V% A2 ^7 H1 F: _
output mcasp_afsr,8 Q, M2 q K- w+ O+ k3 R2 `+ m
output mcasp_ahclkr,0 T( W1 H+ \. K+ _
output mcasp_aclkr,7 B: J3 k4 |8 S+ f% Z D- e4 k/ b
output axr1,
. Q" }; X8 J7 U- T2 L4 X2 I assign mcasp_afsr = mcasp_afsx;
0 K; L$ h) l- v5 eassign mcasp_aclkr = mcasp_aclkx;
4 x' P+ W% j' ]1 x- u, Passign mcasp_ahclkr = mcasp_ahclkx;1 O/ G# D! ^- L) |/ S' o0 z
assign axr1 = axr0;
# j# n1 Z) Y/ g: Q @3 p; A/ c9 Y5 S+ B( h6 m5 L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& t# Q' Y9 G6 u. f- qstatic void McASPI2SConfigure(void) @7 `0 x; S3 w& W, v+ S
{
/ {+ N4 w; `0 a% j& p( b1 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! n( T6 ^' \ C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) \' K$ [, g) x& h' c8 S2 ^' I7 b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, h* x5 ^: S" R. b$ ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- Z0 Z2 G9 x7 i0 [2 o6 j0 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( h9 v; @) q# K( p( b" x# Q* OMCASP_RX_MODE_DMA);4 w1 M! p5 `. t* X1 V! [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" L2 R% e! o, k) O4 h# cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* c" ?) d, t: d9 u6 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ k" l I# {1 b$ a5 v% `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ I0 E/ `7 `% y$ M) A# A! G/ K. QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 \- u6 g- O% I5 d3 w- |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' z" W0 _1 `8 x) n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ G8 N' }8 s* H. _+ KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - B" ~* v" g7 N4 d/ k7 b/ |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 j) h7 Q7 i( E6 C
0x00, 0xFF); /* configure the clock for transmitter */
5 K4 {( z4 W/ E6 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 C! h0 u% n+ W& S% ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# H9 b6 `- f4 H9 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; j& U( Q6 |! G2 ]# E) B6 c0x00, 0xFF);- D$ v& I( j$ y9 O$ L- x& M
, H- ?7 {( V7 R7 \: \) I/* Enable synchronization of RX and TX sections */
/ K; Z; b; G2 u3 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 ?- X) `# S3 Y3 N Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 v! T/ y, p3 q/ K2 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ _$ j! [; O; H7 Z" k6 A
** Set the serializers, Currently only one serializer is set as7 C) p: P$ `7 _: |! n% w- a2 Q
** transmitter and one serializer as receiver.4 q3 f, S3 U# i! f9 [' I) |$ P0 k' _
*/$ @9 \2 ?. `8 e% ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 Q5 ]! _& z' k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, `5 w) ~$ R5 _$ _- ^$ w6 P
** Configure the McASP pins % J, d' V9 B: t+ y: V: k3 |; ^/ B
** Input - Frame Sync, Clock and Serializer Rx
8 V0 s4 B: B, p. N: F** Output - Serializer Tx is connected to the input of the codec ( T1 M. N+ X0 Z
*/$ S* P( Y ?) j3 U' j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# K$ M; S- d3 t6 C1 N: k6 i; h( aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ c" M' ?- A; _' r$ R6 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, ]. e/ D+ }/ b' e$ @. N8 v6 s: U
| MCASP_PIN_ACLKX3 U6 o {3 A9 \( x$ |
| MCASP_PIN_AHCLKX n/ i, k2 |1 ?: o8 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, a9 L8 B; J3 g& l6 ^$ q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; U# ~1 @- k* ^( t7 t, K5 a| MCASP_TX_CLKFAIL
9 Z q. a4 r, X+ W0 I/ O( {* \| MCASP_TX_SYNCERROR7 F* }5 Z# W% d' v' B5 o" U' b, z. m& t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 l& P8 O. e {" r5 P! q* D9 G& F| MCASP_RX_CLKFAIL
1 D7 D9 a- @6 H+ L, p+ V* l| MCASP_RX_SYNCERROR # h! Y l& X; d8 x% ^4 M
| MCASP_RX_OVERRUN);! J5 m8 D4 r0 O' c7 c
} static void I2SDataTxRxActivate(void)
/ D5 S8 o* @1 `3 o) W{
. r$ ~8 {9 j1 l2 F( S/* Start the clocks */
/ t2 I* V1 d1 U& oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 W7 L3 x) U/ G( H! z* UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ ^3 \2 f- B* C5 L, m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& g6 Z( |( `1 w) D7 ?' } D
EDMA3_TRIG_MODE_EVENT);# z4 R* @( [7 N" S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& s4 g4 Q5 X1 A. A) s' L+ \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( [* ~. Q1 k& j2 d6 HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
B9 Q3 z5 c. _, ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( Z/ d" r+ m8 a+ T5 I; c; twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 _% d! E7 I* k1 A$ C0 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 t9 D2 E. x& r# h3 n% S( F, @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' z+ Y4 v. }5 u, C& `6 t8 N}
9 C0 t/ m( O% D. ` v. L1 |9 }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 `% H- P* E- h+ B* O
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