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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% s: g8 W4 z+ n5 h6 S# {
input mcasp_ahclkx,/ s; k4 |5 G, k K8 M' o3 i) c9 T
input mcasp_aclkx,
; b+ A3 m1 O$ A( `" g! kinput axr0,: g0 d5 W3 F- h( K
A1 x' J m( \/ o# xoutput mcasp_afsr,
7 P: G1 o. _& ^; f9 H5 c8 Doutput mcasp_ahclkr,; o, v$ L# v0 L3 A }0 r
output mcasp_aclkr,
# F' f( y. a' |output axr1,
5 {3 }8 ~. }* q T& |" X assign mcasp_afsr = mcasp_afsx;5 o, H& B& i4 k) K
assign mcasp_aclkr = mcasp_aclkx;
9 {/ E3 }- m2 b+ O: Q2 gassign mcasp_ahclkr = mcasp_ahclkx;3 G3 {. }; ~+ ?9 V6 S
assign axr1 = axr0;
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/ S/ H }0 n2 B7 D0 K* L2 A* n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! K8 b. S5 p7 u- O/ o, D* C
static void McASPI2SConfigure(void)! L% `- y t S
{
. v3 R2 @' g" KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& _9 e2 \5 d) |1 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' f" _, @# w( }" T6 k( r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ ?. P, j* } e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 ]3 k+ I, M, x2 s4 E; OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 w+ O- b0 d% g, C# y5 D! h8 g
MCASP_RX_MODE_DMA);: j" \. U" |' W) B7 s. D2 ]: V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 l. N8 b0 w& U( w; `( uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! q# Y) a1 b4 H/ y1 m* d! r" u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. L+ T. N$ F& ]: WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 Q+ ^6 T- D4 Q8 l2 e( G# t( K3 \% }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 Q5 A: B# d/ sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( u6 _; l) U/ I7 X, @$ Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; o" Y" Q( E$ n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: | [. H x9 i0 k3 iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 G. y- Y3 k& D- x4 O$ ^ x
0x00, 0xFF); /* configure the clock for transmitter */" J9 M# Q; Q6 T3 B$ z1 V C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 Z- [$ R- O. JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) X/ m' T* `: h- D8 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 c% v q) S4 F0 }0x00, 0xFF);2 w3 z, X5 g0 R
1 q5 Z: I6 K+ t# k% _/* Enable synchronization of RX and TX sections */ 9 A5 D9 H* O; ~) X5 w: p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* h5 o- C( l) u, j7 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, p2 W3 [" V5 d! l: SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( t6 n( b& _/ E8 j' r) D- [** Set the serializers, Currently only one serializer is set as
! j% v, U6 M+ c( w+ Q& h8 A** transmitter and one serializer as receiver.
4 F5 L5 }8 k) r7 q/ W*/1 w5 `% w8 b% `* G8 s5 [% i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" P& t; P$ v7 M) xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 ^. {- t5 u8 e5 Y6 E
** Configure the McASP pins
2 W3 [# K+ ] s. b: h5 G, y** Input - Frame Sync, Clock and Serializer Rx
. k7 Z: X, @! N1 i** Output - Serializer Tx is connected to the input of the codec
8 Z: S) i6 V! g# C. y/ e7 o* n*/. L) E( }* {* \6 v5 x5 V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 u' W& {9 ~! k4 s- F7 f3 D6 H9 U* h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# G, q: ^: \9 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 ^5 v8 `2 Q+ a2 V& W0 w| MCASP_PIN_ACLKX
* w+ O+ o$ ^0 v$ A| MCASP_PIN_AHCLKX
0 T+ a% ]# d3 F0 @; Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 _9 |2 {' Y& G. r# Q1 h; @- T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " v- N; r4 W& I I
| MCASP_TX_CLKFAIL ( h, k$ C6 e: l' c( @8 X- G& g6 {
| MCASP_TX_SYNCERROR
1 Z( C6 u3 E, e- y. W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& ?& i j* m2 b2 m5 P4 _| MCASP_RX_CLKFAIL
; b2 F: O4 d; ^" {9 S: ^| MCASP_RX_SYNCERROR 3 L d: |: C8 v+ I/ T6 ?
| MCASP_RX_OVERRUN);
1 J; z3 i+ r7 y} static void I2SDataTxRxActivate(void)+ i9 o) d4 @! ~4 @! E4 b
{
& f1 r5 m. p& {2 c/* Start the clocks */2 i/ R ]7 [) h5 X" T+ Q' n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: I7 K2 ~( A. o8 k9 m: f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 P8 b' T: G# r) c& J& { Z, @' s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 J3 h; h& p3 |
EDMA3_TRIG_MODE_EVENT);8 r. V p- v/ T* H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ E; {7 o0 o& T: V" C0 R. }0 r4 b1 N2 }. eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& V1 ^5 N- [- FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- B' {6 R* w' j' \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( [. \4 `2 M- H; T$ C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" k! J! F0 x& h3 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ N- V$ O6 ^; _( ]7 p7 _( B( P) KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- \/ u4 H4 j0 U/ l}
$ f4 A, L. j, q# x# L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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