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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 n& [$ E) O, X4 vinput mcasp_ahclkx,( z: E2 b" Y, T. F! l
input mcasp_aclkx,
0 N1 H1 V9 C# b$ N. I1 A* Vinput axr0,
# v: r5 \& Q5 k2 Q; E& B& f2 U
6 ^, k6 u& Z. S9 Y8 Q) C1 Koutput mcasp_afsr,: E4 M) J4 Z: m0 k
output mcasp_ahclkr,
: F' m& E: O$ v Zoutput mcasp_aclkr,
- j2 W* o( b2 |# p% foutput axr1,; M! T3 E g# \1 d* t
assign mcasp_afsr = mcasp_afsx;
" u) _: K/ K2 P5 V) _ e" Gassign mcasp_aclkr = mcasp_aclkx;" b! W) U3 ^5 k: F* _
assign mcasp_ahclkr = mcasp_ahclkx;
t: }( Q2 L3 A( Y( J1 D( o: n i `assign axr1 = axr0; : J( ?+ Q5 T* d& g8 t
; P2 |! |* m% q! V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # U- j- K+ f4 ]- r2 g5 `
static void McASPI2SConfigure(void)
# g9 R' {% |2 p% G{
$ b9 h% b; S( EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: z" Z9 B( C K8 U7 y5 R ^8 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& s4 ?: r3 ~+ p9 N9 X: BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' H1 n$ A* `/ B% F8 p/ f8 ~6 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 M- Y: c* A9 k* b0 w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 V4 G3 r: k' C
MCASP_RX_MODE_DMA);+ G9 r- N+ H% N; [; i% Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ Y/ b3 N3 F9 ]4 G' WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( x" { Q: d' J6 R# l. g. _/ mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % B4 D# H! x5 H9 m- ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ W! K( s' \, A9 t: k( r. Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 Q' n" L3 m/ [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" X; q7 Y1 C N' p8 t( h/ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 P; Y+ ]1 p$ D* R' |, O: w9 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * P F/ ^% `; B& m, f7 ~1 ^6 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: |4 s* d; F- k" r- N0x00, 0xFF); /* configure the clock for transmitter */& `8 a5 P8 \% D# Q3 V) h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 C4 b0 |) l+ |' g _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; R; i0 l+ L+ R% V3 GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* d# x( M# X# ? K3 J# `$ z
0x00, 0xFF);
$ P% O5 R0 R7 K& m+ |$ w$ R: Q: d: Y7 t( E1 y- u$ W) a# V7 D
/* Enable synchronization of RX and TX sections */ ; k+ U7 J& |) L1 a1 M+ O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 q" q) _2 @1 v. ]; @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 O R- j3 L, v: { @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 r: i# e( @4 \+ ?$ s) g** Set the serializers, Currently only one serializer is set as; ~% E8 K7 `: x0 W7 u6 r2 F6 m
** transmitter and one serializer as receiver.0 u+ b+ G, l8 e4 Y
*/
& `) Y' m( z- mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 ]! c) p3 A& e! F/ h4 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** m' J" w( ?; A! @
** Configure the McASP pins ! |8 B; ]5 Q& j7 W# O
** Input - Frame Sync, Clock and Serializer Rx
1 W& f; S( R) B% W$ S( @; F** Output - Serializer Tx is connected to the input of the codec - H7 D6 u5 `4 ]7 F) |+ b7 u
*/: a* L" h! W) y" j- U2 B! R4 Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! h' Z& C9 U( ]3 WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( z. C2 b# j: v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 c4 j& B7 X7 |% W, ]4 M1 _| MCASP_PIN_ACLKX5 Z/ @. y+ L G
| MCASP_PIN_AHCLKX, K% O: S# D$ y9 p& M3 R& u& C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ p Y& W+ Z# H' m3 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ H- j9 q) w6 }1 Y& f. X$ ?$ W| MCASP_TX_CLKFAIL 7 }4 h$ R/ z/ h- N. F. ~) ?: i
| MCASP_TX_SYNCERROR6 q* f& U G1 A) m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, s+ ~7 }8 e6 E# v* V* ~! F% f| MCASP_RX_CLKFAIL
d/ v2 Q3 m; Z. N/ Q( P| MCASP_RX_SYNCERROR 1 ~8 `# O) `/ Q P
| MCASP_RX_OVERRUN);
# y" O5 s& `. z0 A4 W1 h: e. i} static void I2SDataTxRxActivate(void) f0 L* X2 y% a
{
% a8 a" x# P. h |0 W/* Start the clocks */4 ~+ L7 a8 }! U- Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 Z* p5 q2 W7 P3 E* d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 y% k' F; q; V4 i% U2 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 z! i h2 ^2 u1 }! P, B* J
EDMA3_TRIG_MODE_EVENT);9 a5 e: R2 D& ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; b! d2 z! L4 t N9 \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- ?; D, ^* ~" L- v) h6 g3 D- @/ k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
p% O: s- o3 F! x( v2 a0 v7 Z) uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( p) j0 ` C, L" D7 X# e m c: nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# q7 K u, s8 d4 B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; q2 D* f( [9 O# _$ EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; f) y0 D& }) m
} ! ^) y* z' b% r2 [5 r2 E w$ L4 H. D7 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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