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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ Y9 c/ ?9 b6 F% _: O; g# r6 Binput mcasp_ahclkx,
8 g2 l3 P7 }4 k2 R s9 b( cinput mcasp_aclkx,, @5 t, W8 w2 B5 C6 ~2 S% K% Q% B# `
input axr0,
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9 i! P% U8 I/ m- M* youtput mcasp_afsr,
3 x! T: _1 r1 |' L' u7 Y/ Joutput mcasp_ahclkr,0 y L( S$ |$ w% d' X5 m7 j
output mcasp_aclkr,- p( I4 e9 U4 E
output axr1,
0 H K: e& d1 r9 M* u% g assign mcasp_afsr = mcasp_afsx;+ Y0 q1 v6 ^8 G3 I, }' q' V
assign mcasp_aclkr = mcasp_aclkx;. Z& f6 t, l* c5 T
assign mcasp_ahclkr = mcasp_ahclkx;
W' c1 i& D* b, d% ]assign axr1 = axr0;
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3 O4 s$ s& R; X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 s) c) o! U4 I8 m6 \
static void McASPI2SConfigure(void)$ m$ e( y6 K7 H3 T4 z
{
a, d7 g) P% o. LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 E: E t* r/ P$ m+ s0 m/ O: z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* f8 a, l. |6 p( O9 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ m3 t2 K2 a7 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 r6 e0 [, ]" b1 B# h2 |5 P/ [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# i2 O4 K- p' V, {7 |# Y7 |& Y; l* K8 P8 M
MCASP_RX_MODE_DMA);
7 I A3 X/ T) g1 _3 M+ A5 @) U( fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ _( j( H* |' G; K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; l6 B" X3 I5 o3 D/ V+ F5 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- h' n( f1 E3 @( V. m- ~. X+ HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ v( w0 ~0 e0 a! @; e0 |. lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 z$ o* F. Z2 \% z0 `8 M( z6 N5 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ G" ? S/ F" n; C0 `" D6 r' MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* n3 B+ |0 s m/ d% f8 Z k4 m* eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / x$ @3 l1 p2 {* a2 \1 [0 Y j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; W5 v$ B: {$ y0 K8 o# ^0x00, 0xFF); /* configure the clock for transmitter */
. P U& U1 x! @6 u' Z# Z5 u- w+ AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 K- w- M/ ^1 UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; ` O* W. ?" x7 K: o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 g4 |7 P" K7 F7 S
0x00, 0xFF);- O9 Q( T/ }% ?- w0 m& u. |
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/* Enable synchronization of RX and TX sections */
" p. y* _$ V) M+ T( C- sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; i& t) O$ k' \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. x+ A3 s# B! k4 s! v7 R" |1 X# J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. t- l z" q7 D4 k) |- P** Set the serializers, Currently only one serializer is set as
3 h7 B: e( T8 F3 F: b** transmitter and one serializer as receiver.6 a$ o8 P9 _2 a* x+ f9 o9 j
*/0 N" G7 y; O9 f) p3 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ c- v! b( K s3 A. K$ QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; o+ H' F( N+ q$ Z5 B2 e** Configure the McASP pins 6 s- A6 X( C+ W2 }
** Input - Frame Sync, Clock and Serializer Rx# @, y4 N$ m! X
** Output - Serializer Tx is connected to the input of the codec 0 ]9 {6 ~: t+ l$ ?* h- v# z* }5 a3 L
*/
% I* h: e' a% @" ^& ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) W# T# w4 C! O/ I, xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; Z4 [$ x$ l4 P5 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 Y2 O$ G. I1 p* g% C. _ x0 F| MCASP_PIN_ACLKX C% y# P& F# i, u9 \7 J, G% W
| MCASP_PIN_AHCLKX0 x& }, S3 K9 ]8 T0 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) m; ], e! L! H# }9 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 [2 r7 l% N" I3 @2 m/ d
| MCASP_TX_CLKFAIL 9 w7 C s d+ _$ e: Y1 D9 [
| MCASP_TX_SYNCERROR! C* s9 d, B/ N$ K; W1 u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. `0 X+ d# u C: [2 \, W| MCASP_RX_CLKFAIL; j: Y9 q$ ~3 L/ ~+ R5 L
| MCASP_RX_SYNCERROR 8 k1 a8 z. q4 v8 h/ z& O
| MCASP_RX_OVERRUN);( m0 @& j+ B& g# F" c9 r3 f
} static void I2SDataTxRxActivate(void)" \& r+ q- K( z' {
{
) k m! x! y7 U) g4 e5 g. p/* Start the clocks */
: R, g) P, z7 {4 d9 c9 l' R/ EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' c+ f* u0 X4 x6 j, `0 g2 ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% d9 y$ X' |7 I6 Z8 V' REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; L/ H: S' i/ ]) Z
EDMA3_TRIG_MODE_EVENT);# I0 ?+ Y8 \3 y2 T( N, W: b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# B% @* W$ |; `( {3 O: BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" W V' ?9 M q" M1 P; j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 U; o9 e8 U6 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! P5 N$ ^* _8 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 \8 X! H- D2 z2 v0 }7 O; nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 V: [( z& }3 Z! W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 N5 u& h+ a' I6 k; O4 C; P}
( j& j( l* ^& V k* F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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