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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 }/ [# V6 K% T* L) |" S
input mcasp_ahclkx,
# e8 s8 O0 v( s2 jinput mcasp_aclkx,6 j# c7 ^- }: c# y- d
input axr0,) p% L+ k* v# U+ o) t8 H
- F; O6 L4 c" {) k G7 |
output mcasp_afsr,
5 [% {6 K. a5 Y' H) k+ i# Eoutput mcasp_ahclkr,! o) D7 \( w. B) M5 N* T" c
output mcasp_aclkr,
5 w8 X1 s; t( }5 d# q6 l9 J' joutput axr1,
, @- x q; j, ^8 N+ G; c- f assign mcasp_afsr = mcasp_afsx;
+ [' U8 K5 I, k) @' d, p' jassign mcasp_aclkr = mcasp_aclkx;% e' l" H. Z$ C! ^$ J! s$ h
assign mcasp_ahclkr = mcasp_ahclkx;
, a4 Q$ q9 r+ Uassign axr1 = axr0; " U0 r+ l/ x- P
" d7 Y. V, P7 R. k3 r+ Y4 h% ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , K9 G) f" k" w% Y. x. K' Z
static void McASPI2SConfigure(void)
1 K4 m$ o6 L1 v: Q2 Q{3 o3 ~" A2 t& r. g" l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" i! p0 F* V$ M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% q! q* U o7 Q/ l1 @: }2 IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% |/ E; R# k7 L, fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& I7 g5 _0 R8 L8 R: m/ e' y2 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! u: g* m C6 r) PMCASP_RX_MODE_DMA);
: n( v; D7 s+ q+ T, }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 Y* D. Z% L1 n. j0 O$ L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 d I; \/ m- ]) n/ d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 v2 d& V! o' H, U2 L9 [; j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 j/ v6 J/ E4 _ ~+ Q" @3 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 u* c, }5 G. p* i7 T3 Q$ m5 x2 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) `8 H7 t) y# ~ x0 ^9 k* C1 Q4 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
j; n$ c& N9 E; a- M/ u8 R" o8 RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 S& k, v% B, g I* ^) OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* p2 @4 C1 B" [
0x00, 0xFF); /* configure the clock for transmitter */2 B2 v" D, g! L1 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. F/ k# p& T2 \* A% _; m5 Z( a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 I1 W( A! {6 u4 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ S8 ?- t. x8 N+ j7 R7 [
0x00, 0xFF);
9 N# D( m! _3 ]5 S A! P, E* I& H% V" L
/* Enable synchronization of RX and TX sections */ 8 I' U. o1 I: K, s- f. e5 i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, X8 F' ]) K" }; U6 r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. e; B2 C; H$ L5 k# b9 z& V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 D* i( d. @4 ?4 Y** Set the serializers, Currently only one serializer is set as
/ {1 V3 Q6 S$ t, A: l$ X/ `. L** transmitter and one serializer as receiver.- C8 ^# T# B& r) A5 Z
*/
1 b x, Q) p9 D6 v* u/ UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" }1 ?! n( i& R/ VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' `! D, p$ B( [0 D
** Configure the McASP pins : x" S3 t7 s4 M- e2 v+ q: a1 G9 g9 s
** Input - Frame Sync, Clock and Serializer Rx/ ~ f: {6 y1 y+ t! m
** Output - Serializer Tx is connected to the input of the codec
+ L4 i, z3 W* P0 `) A*/- u5 _- r1 ]; G$ H: Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, i' Y2 r. T+ W. P _5 \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) ]! p7 M2 y" n* BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 i5 A" _4 x' t2 q| MCASP_PIN_ACLKX
7 m- ?& v* J; g5 T B; @- g: R| MCASP_PIN_AHCLKX9 `& M: p4 q: L5 z! f4 z# O+ @) n5 z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" c) D5 @* o5 h. U g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * M$ `- Q, m5 v: s8 L
| MCASP_TX_CLKFAIL
/ Z4 _" G0 D2 h# _8 w& d| MCASP_TX_SYNCERROR
9 H0 l1 @ n& Y. ^* z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 g" z/ J2 \ f/ I X# e7 c% B( D
| MCASP_RX_CLKFAIL" F8 S, j) j" F! Y; j$ l
| MCASP_RX_SYNCERROR
( u, v, K; h Z* R| MCASP_RX_OVERRUN);% `( a) v D$ b+ `
} static void I2SDataTxRxActivate(void): [/ G; K, P0 X0 ~6 b# c7 ?
{; A9 K* s, P" k( a
/* Start the clocks */
; J5 }& Y6 Q% vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! u. s5 u( e' _3 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 ~/ w$ N4 a- p" X; r. tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% N7 g4 h% k) M1 [EDMA3_TRIG_MODE_EVENT);
! B6 W1 p: c8 {9 j3 n9 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & L" v$ ?, c, p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
v( \$ u- {7 e: o' lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 R/ ~8 h' b- M6 c3 d- w& y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 }: Q2 x( o' Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ P3 {+ ~' L m D" }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* K3 R; }# Z |9 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ ^/ H" v, G$ \9 n2 n; q; D: u% G4 l}
, X( ^# o# G/ @+ o' J/ }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; f/ @8 T( u$ j+ F
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