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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' I# C' T! S6 M
input mcasp_ahclkx,
. ^$ O$ h6 v5 c! _7 l- h% @9 M# Minput mcasp_aclkx,
: w x, {( ]7 M% {! f, @" S) sinput axr0,
) c5 S, P; G+ l. X: _& h* n& W" ~# s. _/ P" `
output mcasp_afsr,
3 G0 }: f5 Y' }8 r. Z# l" Noutput mcasp_ahclkr,
2 h: R% B7 A h: u/ |) |, G; Foutput mcasp_aclkr,. ]9 j1 o- [7 j- V( w U
output axr1,
5 X9 w$ Z, o7 y9 m$ @; ] assign mcasp_afsr = mcasp_afsx;* }, V- N B! \2 d! \
assign mcasp_aclkr = mcasp_aclkx;
, J; I( M. Y# z9 b" U2 M, Cassign mcasp_ahclkr = mcasp_ahclkx;3 L# [/ N+ M) `4 ^* q4 d$ T
assign axr1 = axr0; / x& P' O1 x) z+ ^
# O: x& _% B5 B, P% q5 z, A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & O$ m+ ^3 h+ w2 Q' e
static void McASPI2SConfigure(void)
/ S5 O6 N" G" q% m* `( E6 \{. U( l8 O& ^3 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) W! D: W; o0 d7 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 \2 e' Y P% z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* y# x# \1 |, s, E" R5 a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! l& P5 A# l6 N3 ?+ ~) i( IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Y% z" m" p8 {9 J2 z0 S+ W
MCASP_RX_MODE_DMA);
' S/ w: P9 {, i/ c& o- J* j' I: mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
n( `4 [0 U5 L2 h0 HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: f7 @- D. A! S; `7 j3 d, F; v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 w: P* C) E4 W; H$ |( @, S: x8 h2 ?8 CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 {$ i! g4 J/ K: {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 A& T1 m) N) d; t0 f, B; x* d! |6 F @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# @* n. O8 v- M! U* DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* i8 S1 p. q; s& ^& F( A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; q- b9 ?3 u9 W6 K( _1 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# } K% f' V( F- D: ^5 T
0x00, 0xFF); /* configure the clock for transmitter */: U _+ I* G) o% ~/ b+ V( Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 f$ N. w4 F8 D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% K; S5 J3 ~( C8 KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' t: F% t4 x$ j- e
0x00, 0xFF);: h# P9 |% z: S, W. V
: @( K4 u+ E1 X% ]
/* Enable synchronization of RX and TX sections */
4 X( n V. Y4 a" H0 M/ M3 C: bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 l8 C2 N S* iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! E3 ]: b) {. C8 |" T! v# @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( v4 m# D& a9 @3 c2 e9 A** Set the serializers, Currently only one serializer is set as
6 T" {" R3 F! n; w+ l6 `! k! M** transmitter and one serializer as receiver.# v9 ^- w' R9 q+ ~
*/
' h2 M3 a, \; d7 Z+ uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 W \. E5 v" @: UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 I0 {8 n- a- Y7 K
** Configure the McASP pins
1 u% ^2 @ G6 u, C** Input - Frame Sync, Clock and Serializer Rx) p; t8 n! a) E4 R8 F9 u3 v
** Output - Serializer Tx is connected to the input of the codec
/ N- C0 I0 i2 n: R, U1 d*/
8 X5 A6 p; n/ W5 D# E* t& iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 {/ n P# W& q% o9 I* W/ MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 B, g! _% Q9 y- b( JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# S) L% [% z5 J- e3 L5 h% b
| MCASP_PIN_ACLKX
1 @1 A6 G, \1 p" o| MCASP_PIN_AHCLKX2 g7 q: y! [ N6 s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( n; n8 Z& {) E4 {/ QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - W+ B/ i2 W/ q b6 w8 H
| MCASP_TX_CLKFAIL
/ O2 _7 r# Z+ E7 L/ m& P| MCASP_TX_SYNCERROR
" Q& p. k$ I9 Q n1 d# _( `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! v5 y0 j0 \ V
| MCASP_RX_CLKFAIL
# M; a) O3 m# u. {- `/ o| MCASP_RX_SYNCERROR $ m3 | [2 z9 F* d9 u
| MCASP_RX_OVERRUN);
9 B/ ~: s2 [9 Y( A' ~} static void I2SDataTxRxActivate(void)# B9 r" `$ B* r( f
{, k0 C1 ~4 K) V& K, s
/* Start the clocks */
+ w7 _% f( T7 c) Q& E$ R$ L/ QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( ?0 a$ z; f; M+ F$ e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ s& f8 D# u4 i+ lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ O, ?! \9 Z7 o+ F/ H$ TEDMA3_TRIG_MODE_EVENT);
|. i! [7 _) {" D/ g% u1 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& ^% u+ {5 z' \1 d& |# yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 M& @9 e( e0 Y2 |! P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- c0 b' E$ n% v2 I! |' UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ K& B4 w; c8 F0 v) `; g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! }4 W2 ?2 B) E% Q5 h: iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 i' \# t1 E" C$ [- e W, fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 U3 G; U' H& ]' J3 ~4 Z}
) {! Q6 r) b9 h( P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . r: |6 ]0 B/ y- O
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