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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 y( ]1 ]5 H1 u( `2 x
input mcasp_ahclkx,9 i: i3 R2 ~0 T: A" u [
input mcasp_aclkx,
/ p4 Q7 ~5 p" K( Tinput axr0,1 _% h% n$ K$ r) Q: Q
: D9 ^ r" H7 A! q5 ooutput mcasp_afsr,* O' t0 z6 L" x" E% Q% b
output mcasp_ahclkr,3 Z# W% o) ~- _0 p0 K/ m) K4 ?9 M
output mcasp_aclkr,+ ^7 f. t+ y( u, q* q
output axr1,$ x5 ]6 p1 Z- {
assign mcasp_afsr = mcasp_afsx;1 F6 q- t: y9 J. F7 B
assign mcasp_aclkr = mcasp_aclkx;2 ~; J/ S4 I0 O9 K$ y% w
assign mcasp_ahclkr = mcasp_ahclkx;( w( e& G9 v$ J. p' u$ R, p* |: k# |
assign axr1 = axr0;
7 z) K' E! [. u# ?6 z4 l" w) s9 Y3 b* Y7 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" ?' z( g$ \( Q' Pstatic void McASPI2SConfigure(void)
* l) c% r% A% c) X" ^2 h5 D{
2 B: M; x1 f) X7 \9 k+ Z# n+ |" m) NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' G1 j8 U& r1 }: c/ T8 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 I4 n$ Y' p0 C& Q; r0 @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
g/ ^7 Q1 X. v9 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 N* f- t- ?8 [* b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, c% o& U2 C+ c1 u. u* H7 ?1 H3 S9 MMCASP_RX_MODE_DMA);
$ y& R6 Z2 y9 Q8 b% i. J# BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 S, F% {, @+ T! O; LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ Y3 ? e; w; G$ L- p/ ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 q J+ G6 W" N3 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 Z; g2 G; d. r" @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 q1 f, H- ?7 o1 \; G! y0 ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' R5 Z$ t" k9 ^% hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 n$ A; ]5 h+ U2 K0 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 l4 H2 [+ ]+ C1 ~* [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 l* O6 _( V- {- i6 f3 `* c! @* s5 z; u6 o
0x00, 0xFF); /* configure the clock for transmitter */3 j# r' \8 N* w+ _# ], G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 P% n- h1 W9 q+ {4 G" MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( P& e! L. o# V3 Q- J) C, ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 F) d# m: A& l2 e; U1 N$ b" g0x00, 0xFF);( U( o" |4 W( D' _$ N9 L9 j7 G
0 h8 o7 e, O* k" b6 S4 U
/* Enable synchronization of RX and TX sections */
! r2 Q+ i( E" P* i* H ~; F0 G, NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ |# j9 P( c# x2 i1 yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 k/ ]7 q/ U+ u" y2 _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 \0 u# u+ \) j- |+ v
** Set the serializers, Currently only one serializer is set as5 R$ l0 G I9 a2 h* `/ x
** transmitter and one serializer as receiver.
# V+ z' w, E, |5 a8 d*/
1 Y, x$ i' j: C, ~7 ~/ r PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. ]+ O9 K! N1 z6 `# _' |2 M1 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ t- x1 g0 I% t) \% N8 b** Configure the McASP pins
* [# @3 L) J* z: P4 R4 a. s** Input - Frame Sync, Clock and Serializer Rx
N: n2 V! X7 p6 J- j** Output - Serializer Tx is connected to the input of the codec
- Y8 h, L" ~& W( E( a*/
9 l2 S# w: Z' X+ a* O6 M3 _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 E. T; ^( b+ `, s$ w8 L6 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 l- ^8 e( l0 P6 p. \& x' t& dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX B l, R9 [- S( O6 F- h) i/ R
| MCASP_PIN_ACLKX
/ q* a3 e0 M- N+ G8 k: X| MCASP_PIN_AHCLKX
3 `2 t5 B+ i9 u& e9 s# f5 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 t8 y( b- e& g4 h( v1 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 l3 q9 x' _6 t5 c9 n' O9 h
| MCASP_TX_CLKFAIL
4 Z# ~1 i* m2 m7 F' I| MCASP_TX_SYNCERROR4 } P! F m" B7 C( Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 L/ x7 ]' y, |! n5 ?2 f! D
| MCASP_RX_CLKFAIL
m+ k1 W2 N" y5 c$ z# o( h- L E2 j| MCASP_RX_SYNCERROR 6 e2 Q6 L# u" b" g
| MCASP_RX_OVERRUN);
" t, Y. E/ Z! J- i' v} static void I2SDataTxRxActivate(void)
. F2 x7 M6 y8 Q' ~% V{
2 Z9 S9 j0 w2 @+ g9 n0 s/* Start the clocks */
s1 V* r9 }3 u* A; B9 }! n6 o. m7 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# A8 L$ J9 `" s$ y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, E* m( t; F( ?: WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) C0 |" r8 {: x+ h- M8 DEDMA3_TRIG_MODE_EVENT);
1 I# R6 t- A1 t7 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * L. I* [( X; |, a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. Z# b; n2 q; ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" e' H) {( ]( B0 }7 [9 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 ~+ z' `' n' Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. g( H! t6 i N T4 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ h' V0 H! p8 u- V; k7 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - V( i9 `3 h, v8 i1 d- G' _! u5 g
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