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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ P5 N( l: A9 v7 b( ainput mcasp_ahclkx,) E$ g' X- Z" j! w7 q! ^
input mcasp_aclkx,: x2 q" Q/ J; E# [
input axr0,- F0 S6 d0 L6 g4 a/ g8 I& M
8 w0 p9 f# q2 a8 s" }
output mcasp_afsr,
j9 L) W1 L, T `& Koutput mcasp_ahclkr,
4 n) `; l! M$ L& N) g/ |output mcasp_aclkr,
* E) U, ^/ {& Poutput axr1,
! j4 v3 Y* r# o. ]- j; B assign mcasp_afsr = mcasp_afsx;3 B: b t5 ]4 P: p- x6 i3 K
assign mcasp_aclkr = mcasp_aclkx;
% ^! z6 |* } B5 f ~, Fassign mcasp_ahclkr = mcasp_ahclkx;
. ~+ a0 J- g `. R7 l& q: passign axr1 = axr0;
% I& i% ~ \5 I$ b' d9 @* L+ k5 k( M( G9 t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! ?+ @ G7 v5 W8 u0 Z% R0 ~static void McASPI2SConfigure(void)
+ a" b* y( T* s{
0 L' x+ r: a% d* E3 a. B i/ H$ vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
@6 y0 g$ y$ s5 C3 ~. {1 xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 ]5 l# b' C: s( ]+ A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 b N3 I0 I- y2 E' |) V* z4 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ R# M- v+ I( ] V" DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* [" H/ \6 v# [5 b" u& w( x( B E1 k0 a# ?
MCASP_RX_MODE_DMA);; g( X! Y. [# G9 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 M6 ^4 v8 C7 u& O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' h8 x/ k$ ~- m% N7 Q8 e5 YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & |: n7 u1 w. f* c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' `/ _, N5 I& @4 }$ K2 [: R, f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; a, n; [4 G+ Y# q K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 c" w, L7 B4 c. q! a- ^# gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& v& I r7 S7 t6 y2 J: X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 M/ D4 ~) k/ k: DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& S3 n' U# ]3 g s2 M
0x00, 0xFF); /* configure the clock for transmitter */
0 O9 r: Q) E1 L8 l4 {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& d% s0 V6 Z3 M9 o- z1 K, r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' r( q8 y- \/ i; V* d+ O- x/ yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: Z" J; c1 n1 R, M. B, d
0x00, 0xFF);4 h% q9 X9 s. [; q/ A2 C
3 x) m- S7 M: d9 P$ W
/* Enable synchronization of RX and TX sections */
: r8 B5 R+ J2 D" H/ b |4 A- GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 u+ k# P7 G$ o& [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 f, E: y' q& g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 u* v8 x0 I& q. S7 J) |- |
** Set the serializers, Currently only one serializer is set as5 \" ]3 V0 N* E4 k2 d/ Q B
** transmitter and one serializer as receiver.
% Q T1 `1 ~& A5 }! E/ B5 @! T*/
6 Y$ u- J$ \: F: H8 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; X5 V) e% j5 d+ v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ I) e( x1 ]* i4 e
** Configure the McASP pins n7 B( P( M) s, S/ n; y; }
** Input - Frame Sync, Clock and Serializer Rx% f* [) z. E& F$ h1 C" K. S
** Output - Serializer Tx is connected to the input of the codec 3 ~ O0 L- \" W" D
*/
& `/ H8 S0 C. Z9 m, a7 J; rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 y( |# Z' Y" U- D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, X( ^8 T$ D3 I' ^* x- y; u" tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 S) X( X" M1 y7 [
| MCASP_PIN_ACLKX7 l* S$ F4 x/ j: B
| MCASP_PIN_AHCLKX
) g$ T2 L' o6 ^8 I4 l9 o7 V, u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% s( l* v8 o3 X5 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 Z, I: { ^: v| MCASP_TX_CLKFAIL
2 ?+ f7 Z- s1 M. o3 H| MCASP_TX_SYNCERROR, k9 {, m9 l' _1 Z, B$ B6 n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) F9 H$ r5 n2 \| MCASP_RX_CLKFAIL
' Y3 T: z# W6 v5 E W| MCASP_RX_SYNCERROR
) r( R! K( J) P. x0 |" F9 v4 a| MCASP_RX_OVERRUN);0 A& w8 }7 O7 m% g0 S
} static void I2SDataTxRxActivate(void)- y, w. S+ S. [- v7 r' Z
{8 D8 h9 l) \+ M
/* Start the clocks */: e0 s& T+ U% i- T3 W! F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 o7 w+ A( q+ }! ~% _* e0 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# b" @# Q% ` R, WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 R: i$ O0 G# w" G
EDMA3_TRIG_MODE_EVENT);5 t+ m; i M- P7 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 e6 h3 w& b9 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' J) r! {: \, e! y% S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, d0 j+ S4 \; l1 G5 u \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 h' N; B- Q) }0 p" E6 w6 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ C2 ]' {) A2 ]6 ^, l% Z; s- BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! R! Z7 ^4 S6 N* d* sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: |; n/ l4 }8 P/ l} ( r) C+ [; | a3 P: }, C# Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 X0 ]/ l9 S. N9 J
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