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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," T4 x- o* K; k% z: S" ^3 m' G
input mcasp_ahclkx,9 G+ Q" Z% K, ?
input mcasp_aclkx,
* H" X4 Z# ^% d% v1 W3 rinput axr0,
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output mcasp_afsr,
3 v$ }1 g y o/ d, i' @) Toutput mcasp_ahclkr,4 Y) a! G( a r& M5 E
output mcasp_aclkr,+ k9 P: C& O3 O9 C8 @; Y7 R, A3 U7 s
output axr1,
/ G9 ]( V# C9 U6 b5 ~$ ?5 ?- {! a assign mcasp_afsr = mcasp_afsx;
, ~1 T5 T& m) I* `) Fassign mcasp_aclkr = mcasp_aclkx;
" u+ {6 x& K0 E9 Fassign mcasp_ahclkr = mcasp_ahclkx;5 S( I- S4 ^" G8 n& ?3 E
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 t$ k2 v, f Istatic void McASPI2SConfigure(void)% e% v) C5 Z% A. [
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
A/ ]' Y, Q" uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, i7 [+ F# M0 g% f/ F+ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 ~0 W4 H$ a& \4 j# M5 @4 o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 z! {0 C( }, {' m4 M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- K/ |* n+ u, ]7 K! m6 P* Y
MCASP_RX_MODE_DMA);
; P+ }3 b5 O+ x) x- D" [+ {: eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- A6 _8 M4 x4 v" H7 ?; HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 h6 @& h2 b7 l* p2 X5 l3 v6 F! t; wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % l, Z5 I# H( O- F* A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 R1 e8 x) l3 e4 s e2 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 I2 T6 K8 v0 ^4 u, h( fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 c+ k9 l+ ]" N! TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& ~7 x W4 F0 b. A8 U3 w! E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & `7 S2 \9 G- F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ? x8 s" n( ]) r- X6 n0x00, 0xFF); /* configure the clock for transmitter */! E: n- S; n+ @+ {; V' c7 D! E/ s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, }$ Y! _% \$ m; C8 C: V0 J( GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 v- q5 p3 g# ^2 {. J5 A- gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) }% G5 R1 i6 M, K8 L P& F
0x00, 0xFF);
4 {- d. h( y% y" @/ m
( n; ^, n2 N$ @2 C9 N$ `8 t P/* Enable synchronization of RX and TX sections */
* [" N2 H- ^: Q1 k& fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* A8 P' g+ o" @2 [- i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( ~$ C8 Y8 ]; X9 o. b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( G- q" m: K: G6 r** Set the serializers, Currently only one serializer is set as0 r; p! `6 y$ b! ^5 _5 K+ v
** transmitter and one serializer as receiver.3 s$ h) h; R# Y9 e6 U
*/6 | _/ T; b7 g0 k% e9 a# L' I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 z& C) a: U9 Y8 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) u: B/ m! B. ]0 k: o** Configure the McASP pins
9 v2 Q! ?, E+ J8 O1 B7 f; N** Input - Frame Sync, Clock and Serializer Rx' A6 u. W' o- S: u- r; H3 ^
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 [" W# }. ^$ p5 k. w7 c1 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); g, z: V' O) ^! L# `: W' d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& w- z. [4 k' X( R: T, m5 x
| MCASP_PIN_ACLKX$ [$ o- a) @) R; \9 E- H$ n
| MCASP_PIN_AHCLKX6 f. e2 l- F4 O/ L& e/ Q; \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ O4 Z2 b x$ l' r( r0 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( B1 R# e) T% F9 f+ I6 K( A
| MCASP_TX_CLKFAIL
2 R! T0 B# N( j/ `1 S* M' K* i| MCASP_TX_SYNCERROR
: |( w9 ^7 v- k8 e8 m+ R! I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . V! I+ Y- a7 X9 T+ N0 S
| MCASP_RX_CLKFAIL
) m8 V0 W7 ~& l, K1 n- w| MCASP_RX_SYNCERROR
% ] ^! V% E% Q1 E/ W/ S8 u| MCASP_RX_OVERRUN);* w! R" w- r5 L, ^8 d7 r$ W
} static void I2SDataTxRxActivate(void)* T, O% c U# o- @! M: o, @" B
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/* Start the clocks */- {& P& U: J& u9 m' J0 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 n8 P+ ]9 |/ i) o6 d& R LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- K! p8 t' j. \: z! TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& r0 Y, P; _$ q9 @% m( w. ^9 R; A- dEDMA3_TRIG_MODE_EVENT);
: H1 h$ A/ ` G9 R5 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , J3 x" {. a' v) Z7 i/ u9 _* s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 D4 w, V, e6 J3 ~/ i* }5 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 o8 ]9 s- T" u8 J* `& N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 z9 m) C! V% ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ T: J' t! H/ }9 n" l' O( N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 |$ a3 U' A" g* O/ v* }- g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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6 O& o8 F2 e2 z4 @; W7 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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