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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 s3 H# X5 F6 l/ C- a o! x
input mcasp_ahclkx,- s+ N% o' W, I7 U
input mcasp_aclkx,
3 D1 R# }+ Q6 I$ b, J7 Hinput axr0,8 K; g# g# s5 Q( F5 h6 N
* H$ f7 o0 B3 @! l& Goutput mcasp_afsr,! S) l* U# X1 {% H
output mcasp_ahclkr,
) E: H. T2 F+ q$ soutput mcasp_aclkr,
# R$ J7 t+ s! _; Joutput axr1,
3 H/ Y1 r7 ^1 g/ P' n" t% u3 _ assign mcasp_afsr = mcasp_afsx;
3 I$ ^+ R4 T; |% V F9 [assign mcasp_aclkr = mcasp_aclkx;7 d+ S7 w D n2 y4 R2 ] U- |/ K# z
assign mcasp_ahclkr = mcasp_ahclkx;6 l: ~7 z0 r( [! }- N' I1 W
assign axr1 = axr0;
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- w7 q { P( z% \5 s4 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * H0 \% b8 |5 t4 A7 e* e6 Z
static void McASPI2SConfigure(void)$ }- }. W; h- V+ D$ D- n) E; Q
{
3 `- v. S5 ]- @7 t/ ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 r- w3 ~ M$ B( y0 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 X3 C4 @* p6 [: m/ vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' f- I. W: W4 ^. r' hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 T- S$ ]- H: ~( ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: F. Z% y$ y# i' E3 \MCASP_RX_MODE_DMA);' ]/ ]9 E* M/ ^( I6 R! k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. l5 B) r. ~" O7 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 R. j* p6 K+ U6 p" d; h+ |- ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , ?/ l+ ^0 }5 H) A1 q- A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' E1 T- }& e ^0 G# IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 G, U8 R/ G8 J5 h! K. V0 M) fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, U2 b& p* v. a" oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 e& ~: \- s- j( I, z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 q V0 J* E* n1 T' \# l; C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 X) i' i. p" J$ L- e; _
0x00, 0xFF); /* configure the clock for transmitter */
, m# e7 }) t5 B4 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: f5 I# F+ ~; j2 ~' }9 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % p3 w+ J2 P& _9 n. e$ `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: L: s+ E' f! ^9 U! U1 N4 U: b+ q
0x00, 0xFF);$ v$ `1 H. y3 `8 f E6 Y2 O
+ \6 ~. i1 R$ a6 U8 h W, h$ }
/* Enable synchronization of RX and TX sections */ ; L5 h J! C! A; s* \! E" o' x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' E5 _8 _0 g9 D8 z/ T/ s: FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 O+ }% ?! K6 C$ F# Y: p7 b$ g5 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 o T( V; }; r0 T** Set the serializers, Currently only one serializer is set as- o- X0 t& s' ~# V/ k
** transmitter and one serializer as receiver.( c9 D) }+ O; z( @# Z' J2 I/ t4 [
*/7 `' }* M% Z0 L# M2 I2 \( Y0 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: X# V4 y/ k. v2 }4 e- JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- O" P. k2 c& P+ T** Configure the McASP pins N$ q C. _/ k' _
** Input - Frame Sync, Clock and Serializer Rx
( G# v4 i% C5 i9 s** Output - Serializer Tx is connected to the input of the codec
, V: R0 U" h' l, _, |( f; T*/. S f L0 Y/ g7 {$ X0 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 p5 r) T2 J/ E( n2 w& mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! y7 f2 |! C8 [' e: VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 s! [9 v4 G3 ?+ L8 \5 C: S# L, I0 Z
| MCASP_PIN_ACLKX7 g2 ]9 ~- H" m4 s( c6 L
| MCASP_PIN_AHCLKX
" b% j0 Q% D* {2 W) ?2 x3 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* c' T$ K8 l+ H- Q$ B4 X' S* f( S+ }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& a7 z. [. B$ G/ @; O7 T$ l| MCASP_TX_CLKFAIL
1 ^+ y! ~. z* P9 m5 B| MCASP_TX_SYNCERROR
3 x, T$ p6 F6 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 r; f& ?8 B; S( Y
| MCASP_RX_CLKFAIL
) E/ E8 C; M, l& y* N7 ? U| MCASP_RX_SYNCERROR
" @% T5 k+ f7 K E1 @0 M/ x| MCASP_RX_OVERRUN);) q' `6 T: F: o
} static void I2SDataTxRxActivate(void)/ Z3 U1 {( c' p* o
{7 J. l, H) B6 X; D( P/ V( r
/* Start the clocks */
; E7 n( C& O9 }; _# ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ Q: R+ F8 ]* j( m& x8 p0 l# TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( t v- f* c& uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( R/ Y& c" U/ X; `( z# {6 S
EDMA3_TRIG_MODE_EVENT);
0 T" |# x& r- r$ r$ ?+ u. c, M: u3 k, kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# r8 v. r j1 }9 I8 K3 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 ^, V+ Z, s( y1 U: G- B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 C2 ]/ F7 o" I* B+ R sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 W& e* O7 L/ R: R! v- y) i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 `) G r! M2 j4 h+ y1 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, g" o+ b3 J, I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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8 s d) n! p' ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # R9 K' N7 X+ R$ d
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