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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 h$ @6 {% F' Zinput mcasp_ahclkx,
B: g$ m& `. cinput mcasp_aclkx,
9 U" S1 K u, l9 linput axr0,
+ t( ]4 R2 l$ ~' x* i
- z- {$ v4 S8 R4 Y1 t( boutput mcasp_afsr,
7 c8 }/ H5 J5 x7 v% Houtput mcasp_ahclkr, ~7 X9 b& F8 o8 n
output mcasp_aclkr,
1 X/ x4 d* O" x& Z; ^, koutput axr1,& s1 {0 e3 X! t
assign mcasp_afsr = mcasp_afsx;
9 y& i! P( b4 Q0 h# d- \assign mcasp_aclkr = mcasp_aclkx;
_( L/ h# h) }) L9 iassign mcasp_ahclkr = mcasp_ahclkx;1 ^ w3 P' [9 f9 e
assign axr1 = axr0;
: r7 R* d( k0 l: p5 H
5 F- K: I) l4 R; f* i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & r" _* P Y. d. E3 S
static void McASPI2SConfigure(void)
3 Z* t4 m! [2 r- x& x$ x: U{
: A9 r# U4 @4 j- r1 ]2 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% q; j' i C! h" K6 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. p3 i" z/ B/ I+ ]% g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% N( P) Y2 A5 I# j5 P) SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; P. F& P: V8 A( @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 R, w$ m# |+ U; `8 X
MCASP_RX_MODE_DMA); r9 t; {( Y( g }/ e, S8 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ^) w v, h/ g6 a4 @; W7 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; ]3 n. H4 y3 z/ J; b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * [5 y( t. H8 ^/ ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 @) ~( z! H. l( Y9 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# ]- \& ?& h3 w7 A6 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 \1 l" O) E' Q: K4 K* _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- _3 v3 a4 ~/ E. `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 {1 u- F- q0 C: a: S) S5 m2 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ w/ h* Z+ n8 k ^% G
0x00, 0xFF); /* configure the clock for transmitter */* K! v% e/ ? ^; A' y8 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! Q% ?. i" C8 N2 B$ F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Z6 x$ q( P' B! ?. d. vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 U. h! o' s6 M0x00, 0xFF);
" I, ?, g$ o7 U! ~; A8 x, |1 l) k+ u; v
/* Enable synchronization of RX and TX sections */ 9 d' H' S' e, t' z; o! I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: i3 l9 G. ~7 x' `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, W$ H/ ?: w0 d- n) t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! B5 ?0 V" A/ U% Y** Set the serializers, Currently only one serializer is set as
" A3 w) |+ q J. m. b% W/ w9 _( E** transmitter and one serializer as receiver.* M$ T3 Y1 c- d: q5 l8 J7 h
*/2 d3 G; h! Z- |$ u; U1 F' _$ t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ j+ y- J/ O, P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) s9 @' C, K: I' s. p+ n% r$ l** Configure the McASP pins ! {/ w9 J) L* q+ o1 V2 O6 i' L5 u
** Input - Frame Sync, Clock and Serializer Rx
( o. w% r2 l/ j2 r Z, [! r** Output - Serializer Tx is connected to the input of the codec ; y/ L& U5 F+ u9 }
*/
5 ~' j2 {- ]. w" _9 s' H+ |/ FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 E6 s! z, J G6 s' d( g9 z w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. N1 T' ]! G7 m6 v) E$ \8 B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% W' H# @9 t7 ?) b8 {& `; }1 m+ q
| MCASP_PIN_ACLKX
; n) _7 l5 B+ p1 G' F8 @| MCASP_PIN_AHCLKX
, K5 g( v3 e8 P$ a( M: }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 g: C- s& |( A" X! N/ c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 T: \( Z3 @/ c; E5 c. Q: a
| MCASP_TX_CLKFAIL 5 g# w/ G6 L% ^) N Q
| MCASP_TX_SYNCERROR1 {! [) X: p- ]- D& ~3 L4 L; _* `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , o; A0 q9 p$ r, e; R K0 k0 ~; ]5 U
| MCASP_RX_CLKFAIL
5 a0 e4 x4 _1 G y| MCASP_RX_SYNCERROR
5 b/ [% k& |* ?7 n& s( U| MCASP_RX_OVERRUN);
( R R. y, F1 \( X+ R4 a) K} static void I2SDataTxRxActivate(void)# O7 B/ {" h% E, c* E" ~- |
{, v, Y% U/ P4 j5 {' O1 t
/* Start the clocks */, z& f/ `8 b8 H. }# J% p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 l9 H% Q: x7 \1 [& iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// m- p$ e! I7 K+ `6 i- l; F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# ~; s, T: n4 p8 m+ N \2 M0 CEDMA3_TRIG_MODE_EVENT);
5 D- m5 b& l9 a* {5 c4 r; w e2 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 U- i1 ?4 x9 `; M1 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' E% w K. v" c- f9 i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. Y# f. z' V* q* j% v; W* h6 f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" A. p1 D4 x) |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 Q2 m) a, a% J S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' D( m" J; T d+ @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 N& [' T( {) @
} : J5 n: r# W+ Q5 V! V/ c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * p8 K+ K3 } D, {( d6 {
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