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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' w( w' I( [# B4 F+ Dinput mcasp_ahclkx,
" P. d4 z6 k- Rinput mcasp_aclkx,
. ~2 F& C; {- e5 cinput axr0,
: d( J" x5 J& a& R1 S7 g" s* o) z# K
, u, S3 g& N1 Z; [) I, e6 koutput mcasp_afsr,/ F" F' A, d( l6 o+ J% a+ o# R* [. ?
output mcasp_ahclkr,% D! G9 |! s x0 @. [3 t, b& L
output mcasp_aclkr,7 t- ~9 q$ s. F+ s% m) `% Q O$ F
output axr1,
3 B1 b1 @* k8 q# ` assign mcasp_afsr = mcasp_afsx;5 D3 M! y$ F4 N9 D/ U" c
assign mcasp_aclkr = mcasp_aclkx;
+ y5 C" \+ u0 o* n& nassign mcasp_ahclkr = mcasp_ahclkx;, r. \4 M, J! O& K" x
assign axr1 = axr0;
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; }) Y5 b- C. h! u; K* n l/ v在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & x4 j5 S6 `4 p0 ^; I9 V$ L6 ^% P
static void McASPI2SConfigure(void). e9 G( C9 G* D+ w: n- o* D) \
{7 h$ m( E3 q% n( F' ?, K4 ^6 e. |5 t# Q& T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' u: J& d2 L# GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 r4 l+ s) [4 K% l- o- CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- _% t. T1 a- K9 H K F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 b$ @3 z7 }* p* c v5 K2 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 l' p0 P; o6 L% B5 F7 P5 x
MCASP_RX_MODE_DMA);/ A' T9 S' ]/ d0 ]7 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Z4 C5 P" T A2 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* w; A% g& \$ B8 b9 q2 l+ `6 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. r( ?1 F T" \/ x/ AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 Z7 m/ |4 y) h, g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & ?, B9 s" v! \) [) x, C9 a2 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ c. o9 Y5 \ K cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( S6 F# r6 E8 w9 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 K/ b+ H' P* H M8 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 M$ ?/ W. T e2 r. c; R0x00, 0xFF); /* configure the clock for transmitter */
" p4 H7 ~4 |3 X r* r6 RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 p7 z& C/ N" I7 p" r0 ]6 x' `( f' hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 m, V3 p& U# q& B, [/ aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; i* \8 R) B+ t* V$ X0x00, 0xFF);, D0 H* x7 [% m. ?5 y& w
5 A) p4 L0 R# e! z
/* Enable synchronization of RX and TX sections */
& @1 M7 [) z9 D- O' x8 v3 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) Z# q' @+ [1 E# ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 m) _0 z1 C# S/ f1 k _! ?; NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: i& E- k# R% B0 c5 V3 j
** Set the serializers, Currently only one serializer is set as
; m! | u/ X! E3 k) p4 W C5 K** transmitter and one serializer as receiver.) I' ?0 }& B H
*/
3 i% W2 [4 J: A) g$ I3 MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ k V. S. m7 u$ x8 |' e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 o! d$ d* q- H/ e6 D4 D
** Configure the McASP pins 3 E4 u o2 W. B- m1 p" O8 X; \
** Input - Frame Sync, Clock and Serializer Rx* k% m8 o4 p: ?
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 x( @9 n. v* f. I/ A4 G/ p7 m7 I! r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 q& O& t/ F& i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ o* n/ Y/ u2 }
| MCASP_PIN_ACLKX+ J1 ~1 P! q3 }- V9 j3 C5 J
| MCASP_PIN_AHCLKX8 m+ n( S. T* h8 x# G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: @9 u* s) E- B3 h8 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 C% B& c& l. N5 y) R4 }! p
| MCASP_TX_CLKFAIL ) \; \ V# h% w4 F+ g
| MCASP_TX_SYNCERROR6 J0 v$ _+ c4 v( Q% j5 ?* d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ P: g. r4 ]* k+ p7 ]4 y. T8 V| MCASP_RX_CLKFAIL' |- h- g5 @, @- u: P) `! ~
| MCASP_RX_SYNCERROR D; \) G, F! n6 L0 c1 ]6 z
| MCASP_RX_OVERRUN);6 Z/ w) f- o+ I/ j
} static void I2SDataTxRxActivate(void)
' X$ O' b4 u a) y6 a( J{
0 M1 w. [5 }: w7 y* B$ P/* Start the clocks */& U8 }# T7 _0 T' t3 k7 `* o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 [2 c" W7 B. Q0 _6 _, P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* u/ }: y- v9 ]$ I# c. t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; H( ^4 m/ C, qEDMA3_TRIG_MODE_EVENT);( w E% m$ V3 t, J3 o( Y e% e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 d5 b5 u7 p% {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- ~5 j# i' Q+ u& [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 a7 }8 K$ X$ T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) B" F J- w2 |; \! ~! M8 pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- j8 @1 y5 S, g# o6 p# _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* e( O. o$ k! m/ E5 u+ T5 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 Z7 o+ @# X5 {! v( r, c7 [! w. U}
Q) j) M' n& O! R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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