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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: z6 C5 o- M0 `: Y' m/ Winput mcasp_ahclkx,* n1 |: |! i4 o! P/ n% D. i8 J
input mcasp_aclkx,, W/ y) P, Z$ L" E! F( Y
input axr0,
0 E$ K: @0 V a; l, l( {6 d4 R. ^3 }5 f
output mcasp_afsr,
; N* L ?' ~# F% X; u' Toutput mcasp_ahclkr,( p" \# ], S D _- s/ ?
output mcasp_aclkr,* p# J3 j: K$ \8 E
output axr1,5 Z7 e* e! W" K' y) o' k& m4 G
assign mcasp_afsr = mcasp_afsx;. i1 F6 m I+ I5 d
assign mcasp_aclkr = mcasp_aclkx;4 x4 t7 H+ G5 p$ [% E5 J9 X
assign mcasp_ahclkr = mcasp_ahclkx;( x) X* |2 ~$ J4 _ a; Z
assign axr1 = axr0; ) B5 t3 s- Y/ V% h% j+ k7 \" d
" d) e | Y- o' y- B/ ~9 O1 W! W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 O; r5 ?" e! B$ R' [( {+ p
static void McASPI2SConfigure(void)
- j' d+ L+ D1 w: j; ^6 S1 i2 v2 }{, u( Y& J) f7 K d; O8 c& P& z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 m3 E% l/ F# o% k1 q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& C% d8 _! n. b, G% M2 p5 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& c6 a7 }) P/ ]3 G; x% B: Z! x/ xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 W; ?, E! W% s3 r. m% c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 [: N/ Z4 P2 Q( T5 v+ W2 F( UMCASP_RX_MODE_DMA);, L$ l, W3 p2 I% o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- v& F" L( n" O, u; zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 o- W# c$ L, v# _: r& J- Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; ?+ \& m; }: ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* K! ^0 E! E G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; W# f1 G7 V- v/ V* m. m; JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ s0 L7 `) a. K1 |7 e. h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& W0 V* J; @$ h; T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 B) Q2 `% o+ u \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 ?9 l5 S. {5 P6 s2 ~; z
0x00, 0xFF); /* configure the clock for transmitter */# x0 a5 i& ?& {# l% d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 ?* N$ S% h2 S! ^" Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + S: ]! {- A( ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" g* T3 r( G8 H5 l0x00, 0xFF);" o% {; y0 m$ E( ^2 i$ o
- Q4 Z' J; v+ s9 ^5 p
/* Enable synchronization of RX and TX sections */
, i9 O2 Q( j3 K% j8 R0 J; d$ ^+ sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 w# k" K8 L4 I+ o$ wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! N* N; u0 K( A, O, B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& x: W% b2 ]9 }1 J/ m( ^& v0 ]** Set the serializers, Currently only one serializer is set as3 [1 M& k' _' Y) B$ U- `* ]8 x
** transmitter and one serializer as receiver.
. i' O# q& {8 A" ~9 E5 v*/+ q/ p8 l- K2 S+ _, T2 |1 W; q0 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 _ F7 ]# N" d$ P" u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" H# N0 u8 g ^, Z/ D** Configure the McASP pins 2 ~! D' b# [, m+ M
** Input - Frame Sync, Clock and Serializer Rx
6 @' ^2 J( P0 u. ?% x$ o- R& T** Output - Serializer Tx is connected to the input of the codec - w, }) ^" n0 L
*/
- `- y1 W8 b2 k4 r/ @- b2 L, nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 Z/ ^7 ~3 s! O5 i$ MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# x7 G" r+ a; v: S# [& oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: E$ E0 H3 U, h' r( y% V W| MCASP_PIN_ACLKX
: f1 T: x0 U, c, ]| MCASP_PIN_AHCLKX1 T! u. T, ]( R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
N3 W, O0 E1 p/ V3 z7 UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 v2 r& J, g5 ?4 x( G' B6 s| MCASP_TX_CLKFAIL * c8 h2 }: s- \ m: ]5 X* H% I
| MCASP_TX_SYNCERROR7 `$ B' T2 n8 [* G' Z# T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! X8 i2 o4 G9 U+ Y9 z9 v# W# D
| MCASP_RX_CLKFAIL
% R, a$ d& G: n& [1 ?; k. j| MCASP_RX_SYNCERROR
. A' [$ A& a6 U+ v| MCASP_RX_OVERRUN);
0 Q C/ w6 a0 M( W} static void I2SDataTxRxActivate(void)# e' |, ?; q! f4 U# f
{
( m0 X7 \' G# G. J/* Start the clocks */
2 R: x3 y$ ?: O7 z# R) J$ vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' |2 w) z) {% {6 A# [) `8 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% Z4 _' F; `7 r7 u$ X! X9 C( YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 T8 F2 M3 Y. v5 J1 N4 {! E" Q
EDMA3_TRIG_MODE_EVENT);
3 Z! W: N* S3 u) G% R7 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 ~5 i1 Q/ r) t* V% V8 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 |# I5 F0 X7 X# _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: B2 n9 q, P4 C; H- L4 Z7 _- |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 E$ t- @" \! ? zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 [" V$ E7 R2 M" ]; XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' O3 W% W$ Y2 q- v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# f/ U( @* V/ o% E
}
; E/ O, x* S$ J( C: E. @2 S1 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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