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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 H ^" }5 Y( y. m0 cinput mcasp_ahclkx,
/ q2 T7 _8 A9 A, Xinput mcasp_aclkx,+ ]' p. U5 x- j, x4 G* y I
input axr0,) E' L$ J: J5 o0 U5 T% ]
8 v1 Z# n, {' E" noutput mcasp_afsr,
, g! N2 @1 `9 _* Noutput mcasp_ahclkr,
' M" G% m: Z" G3 v( q3 `4 goutput mcasp_aclkr,
- V: ^- N3 L1 B! w; Y; i# Coutput axr1,9 m+ ?1 W' S% p+ ?! b1 A
assign mcasp_afsr = mcasp_afsx;$ \3 Q9 o* d/ |+ w" E8 P
assign mcasp_aclkr = mcasp_aclkx;3 \0 B M _) [" N8 s- o
assign mcasp_ahclkr = mcasp_ahclkx;
% S* Q8 ^1 j# J- M0 {2 C& z( aassign axr1 = axr0;
0 y/ L- q4 |/ ^( H- `
' p# y5 F. R% H1 `% ~! Y! |1 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 O6 i& ?# N9 P1 ~
static void McASPI2SConfigure(void)
7 u4 @* T6 ~& a' l$ T/ B7 [{
2 B2 ?- t8 o# d* BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( f6 e! s0 R8 Z% Y: O- ~& v$ x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ O% |9 m" P b9 H9 i. w! U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, c. Z" H* S! ]$ x0 |' V z4 T, dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' K7 |- W3 d' ^" [3 N1 x+ l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- u9 k1 d& O) X: k1 j+ tMCASP_RX_MODE_DMA);6 q# C$ F4 L3 J. y, R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: f9 v5 j- G- _/ Y5 n3 M+ DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 G2 e& w8 y( w. F' BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 }9 E( Q, [9 Q( FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% T; D2 u! p7 W7 p; mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' F" O* y/ T y, W1 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* q8 y& r7 U& s, H4 s2 q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, e, ~2 `* q, g2 q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 k$ d! ^( t* F: H& l( gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% d1 O8 B8 ^2 [, Q
0x00, 0xFF); /* configure the clock for transmitter */; Z) `2 m( U9 s( W. Y" V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 @/ n$ f- [6 E8 N- G& q" A8 E" oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + Q* J8 N, c& {0 n: P( Y! a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( |/ n3 Y8 v1 U* _0 f- w0x00, 0xFF);
& m# A0 b' X+ v7 ], s, i% z `1 h; {6 j7 g
/* Enable synchronization of RX and TX sections */ 2 e. q* x: j: }) I2 s! s/ x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" V! R! C* O9 H O$ E- m- rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' {1 A9 p5 G) Z5 f7 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' p5 C3 [# g6 E8 V0 p. U; }1 ~$ I% X** Set the serializers, Currently only one serializer is set as
9 P7 o4 h, j0 D+ @** transmitter and one serializer as receiver.7 S, ~5 J* j( n# M, a% p
*/5 N& Z; x2 a) N. X. {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. ~* ?5 s/ {& _, K5 P( X! D e; cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 H) g& N7 ]7 p H
** Configure the McASP pins
' v+ i( K! g# s7 q& d D** Input - Frame Sync, Clock and Serializer Rx
1 o: V* U4 R7 I# p** Output - Serializer Tx is connected to the input of the codec
9 s- ^1 C' D; s' k1 \0 _# ^: \*/
0 }/ @* Z1 b2 fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 D/ i( \& d' Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. v, G. c% {3 g: d5 g' rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, u. L) E" @( ~3 ^( K| MCASP_PIN_ACLKX
/ l9 t7 t4 y9 C/ j7 t) T) q0 f| MCASP_PIN_AHCLKX* H. }* M( D1 `! O9 j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: J% \( T" f: a6 p7 e6 S' }- H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 w" D' e# y9 e, h| MCASP_TX_CLKFAIL
" L( u& m( s4 E7 _| MCASP_TX_SYNCERROR+ n1 u8 M! `5 {: M7 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 _; B4 t) P0 S8 e8 K& W- {8 k| MCASP_RX_CLKFAIL
5 S- J8 _9 E! s3 f1 v| MCASP_RX_SYNCERROR ! j. ?1 I" `% w& I: F; y
| MCASP_RX_OVERRUN);* V# i/ k8 f. }# ]7 v& P+ w$ w
} static void I2SDataTxRxActivate(void) i7 n( E, j$ S; s' A
{' @9 W& R2 z( ^6 W7 ~, ]2 ^9 p
/* Start the clocks */
2 i2 [7 e/ }- p) oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* w: e2 _ b$ [* ^7 I" I, dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 S2 L% w, d$ |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' {# X( o# H9 S
EDMA3_TRIG_MODE_EVENT);
. X9 l& \2 y% A+ H6 s! V3 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 B; _! _8 q# `8 ?. ?+ WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
j& L8 M; H; WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 m/ P# k$ S8 O) O% i! P9 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 d; n- s9 O) O6 Q! m2 }1 m3 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 f5 G5 ?5 m' K, a7 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ n/ J+ T0 H8 j+ gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" ~4 A! {( [- @
}
/ ~8 e; P" C0 ]" ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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