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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 j+ f( L. b" x- T
input mcasp_ahclkx,
/ w+ a- \: M; l4 `! A0 j6 m. Linput mcasp_aclkx,
: C( b( e- {) C1 T$ R0 ~! D, M+ Rinput axr0,% Y# D& O8 k/ S8 _% x1 t; M- D+ }+ z
$ a# j% u8 v p2 d
output mcasp_afsr,
' ]; _" Z" |7 d7 t1 x- H4 Boutput mcasp_ahclkr,
/ i) q# E: ]% U4 xoutput mcasp_aclkr,
" G) D( c3 X9 l7 S/ Ioutput axr1,
# R3 X# j( y& ]! b8 v9 k3 `% z assign mcasp_afsr = mcasp_afsx;
" V2 B. f$ O) iassign mcasp_aclkr = mcasp_aclkx;, V" ~% \$ Z5 N. @% \9 V' n
assign mcasp_ahclkr = mcasp_ahclkx; z. g3 P [: t. h. c- n
assign axr1 = axr0;
. t& d5 X. l7 \( B: o& ?
2 p `9 O4 V& v0 W/ O; S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 K" d: w. f4 K% ]
static void McASPI2SConfigure(void)
( ^, \& [, k3 o- {' y8 s& s2 l{6 t/ X, B% q" f- m9 `1 J A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ K4 J5 ^# p* `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 V. c9 o# S3 U: G/ v' d; ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 t. ]4 H1 C0 P, ?/ p2 _' @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! m1 N, d7 V O; S0 @1 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! f# ?6 Q: i1 e- [. ?MCASP_RX_MODE_DMA);. H9 `0 _2 J/ e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# f0 M( e( ]$ S5 [$ e9 B4 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& y4 ~6 E; U% [1 e/ @: cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 F% `, b% f8 ]: P# `8 o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- \2 g5 P+ Z& \) {% |6 d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) ]+ J+ }" x1 s! Z4 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* ^+ R/ D# p& J( h' L5 Z+ Q3 DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 g9 v, u# y" M- W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! x) F8 m: @9 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 v' h# m3 I2 ~2 F/ r3 H. z
0x00, 0xFF); /* configure the clock for transmitter */
, v6 y2 m! S% \/ j6 bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' F O6 q, I. D! JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* U# J, k% w2 m3 o' w1 j5 y* dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: E) ^ x- _: \ |
0x00, 0xFF);
( V3 ^, Y6 l2 M
+ [2 c* F1 j/ O/* Enable synchronization of RX and TX sections */ $ W& w+ y+ x, K5 \* O a" W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- h' y" R& T! h0 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 G8 R% K u* _3 O9 V1 j" \: l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; z: T, H! Q4 ^* c& p
** Set the serializers, Currently only one serializer is set as
& K7 f- `: p3 M* e5 H, @** transmitter and one serializer as receiver.( x9 L* d* M, m) M
*/
! r, q" {/ `& S) A! uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 X. ~+ s( d" @- _% n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 o) x9 a- R9 ?) a1 g
** Configure the McASP pins 8 P8 ?$ x) l# U0 H" U
** Input - Frame Sync, Clock and Serializer Rx; h" w4 [ \; B' Z. `
** Output - Serializer Tx is connected to the input of the codec & b) ?# Z2 ]! K" }$ T& q
*/
6 N+ H0 I2 O' D+ H2 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 u6 @5 _$ u0 S; f* R2 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 E% x% j- L6 M& {. w# e) o$ s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX @" y7 p& P6 g1 j7 p
| MCASP_PIN_ACLKX
Z: P/ m, P8 Q; M| MCASP_PIN_AHCLKX4 [6 N8 f) I$ `! }; }9 i$ t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; A+ V8 q5 _( `- \. B$ `) o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 O0 X% N$ p$ ^9 g5 d| MCASP_TX_CLKFAIL : G, i# E$ }! {* q' t$ F- A! K
| MCASP_TX_SYNCERROR( i0 s3 i% a3 z2 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% T6 O2 }% {4 `8 m9 W- @6 {1 \# W| MCASP_RX_CLKFAIL7 K2 n2 e( b3 c+ d
| MCASP_RX_SYNCERROR
7 }; F u# }9 v5 b8 A% O( a: ~" s| MCASP_RX_OVERRUN);
2 k, ~1 F, H! E% ~3 h$ A} static void I2SDataTxRxActivate(void)( w* X' Q& v2 w4 v2 E8 ^
{9 t5 p3 K5 Q r3 S6 a
/* Start the clocks */
- x+ G) w: x: K1 P' T, H. OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ B' c" A3 H. `% ~7 g0 ^% `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# f8 r5 {1 Z" ?. s4 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 N" g5 M$ I; n' A% I7 u( N
EDMA3_TRIG_MODE_EVENT);
& c/ z* C! D% e! u6 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . n3 @+ w% ]4 L% K' y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 C& a3 r5 U6 ]# n2 c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; ^1 j' d& k. Z3 A, D% oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ q8 r8 A# y- h- l/ n( p6 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, \3 _3 i2 H6 z, w$ H7 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; z! n' N' l4 l6 X, bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* K% [/ y; ^1 M, |) ^. \
}
; Q/ L5 f; \6 D( P* r* C# h* F" Q! K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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