MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% s7 k' p5 r9 }- R% Vinput mcasp_ahclkx,
% x9 g- @$ K$ Uinput mcasp_aclkx,
input axr0,
  I) J* M0 G6 j
output mcasp_afsr,
output mcasp_ahclkr,
- e4 e' s9 M- p2 eoutput mcasp_aclkr,
output axr1,
8 W: J/ w4 b( e

assign mcasp_afsr = mcasp_afsx;
9 e: A* q) t$ A0 i8 t. ~assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
9 D; K& s1 N4 t+ gassign axr1 = axr0;

! E- v% t; ^+ q3 H9 w' r3 h6 D
" e0 ^! r# R7 Q, K

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
( B8 j& {. W8 a. \/ F7 y# EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 _% V5 f, X* ?$ TMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
* g! t$ i$ W5 y5 @3 j$ `" V2 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
: ]) Z. B+ S5 S- y' N3 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' N( Z+ @" m* X% q$ H3 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 P7 H2 q& t& Y0 H* P5 Q8 l. VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
8 k+ o2 q( f! d9 I- UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: y$ v1 f; P* U' C" i& ]  SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" i7 I# \' e: R0x00, 0xFF);

/* configure the clock for transmitter */
" R0 E: {+ q0 m2 K( pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! ~+ U6 ]3 y8 A9 Q# G% KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

. ?9 q0 d0 t& J/* Enable synchronization of RX and TX sections */
3 k' O% U0 \( b( h$ O. u- f3 j) YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
& G- o. {: a0 o, l! vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; b# G0 @! `% |6 B; h  vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
# i9 I+ A6 H/ @, j** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
4 p/ H- E6 b' _$ |; k8 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 b, I- ]. C. m/ |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
4 e7 U- U$ C# i5 O& j4 I5 q$ h** Output - Serializer Tx is connected to the input of the codec
6 ?& F0 J1 s" h*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) [7 u. ?/ R3 L  i3 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
; [' n; \: n9 B/ z| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
: p9 {4 j! A. M# X& t4 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
  I- j1 w# g; o7 ^7 E$ ~| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% f! F6 Z6 R: @& D| MCASP_RX_CLKFAIL
* L* x3 k# K$ `$ b/ Y. U1 F| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
( N; r; J4 C' Q$ i) o}

static void I2SDataTxRxActivate(void)
4 r) O7 X3 _/ ~6 s2 o( {{
) R3 ~( Z3 |( k9 D* E/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 M$ X! n  M, q( t1 |# a" rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) {1 F# n4 P  OEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
: Q( t  G, `1 D6 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
+ H. x4 a3 e7 ]6 V* s9 @( Y- dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

0 Y6 X4 A& f  i/ l

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

# T1 L) r, h" `* o$ g