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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# A9 T d( @4 G
input mcasp_ahclkx,! O: V3 x+ q/ w9 r, L8 D) h
input mcasp_aclkx,6 F7 U7 A( \& Z' E( w: }/ g
input axr0,% R* J6 p2 n% B/ _2 H
( U2 a/ P) e! U0 l0 U3 q& x8 p; i& [output mcasp_afsr,
$ s0 G% c5 D/ S! F& ?output mcasp_ahclkr,- j" h( n9 h; D G* X, } r
output mcasp_aclkr,: S: Y8 K( u4 t5 F
output axr1,$ T4 W# b: Y# a- w
assign mcasp_afsr = mcasp_afsx;
" ^! z: `9 b0 i( T' B: p9 Oassign mcasp_aclkr = mcasp_aclkx;8 c; J3 J( a, P9 x5 f0 M- _
assign mcasp_ahclkr = mcasp_ahclkx;) k; l* T7 e( r/ R
assign axr1 = axr0; 8 o4 Q& L! ~7 D9 c0 B. P9 ]
L1 w {( P8 h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ?; T: a+ o+ I+ _- g1 X4 b
static void McASPI2SConfigure(void)
# q/ `( I1 r! K# V3 z{# ^6 ~( N9 M8 t. X, o% o% `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ S- ~9 B0 D- d; d9 ^8 G3 J! Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" {4 b1 D$ m; H; ~4 u! b: F8 M6 K% P% lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 A. ^4 [1 j7 b) k4 [$ |" K& lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 F2 j% J1 p; q7 K5 J8 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. M5 G) @! h9 s7 W/ Q
MCASP_RX_MODE_DMA);" X* |8 c# L. o* {% H/ e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 V9 H5 q2 Z H% Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& u9 z& \: _" ~2 e0 J2 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . l5 k7 n, O/ H. e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( t4 t" F# N+ S; n3 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ w$ P+ K% y) ?* ?- e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 h0 W/ a( N6 g! a" [% Q: C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 r$ T6 B R I. X4 x" P( tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 w4 b& W6 N' C. w- u6 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& }$ M9 I. C2 F) Q8 [; c
0x00, 0xFF); /* configure the clock for transmitter */. w7 x/ v R* E4 g( T/ g7 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! S5 N* M' w) S- E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, V# A: W# o2 K o8 Q/ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," x7 N/ H* {5 @$ N+ k! Y
0x00, 0xFF);
9 ]1 K8 {: ^5 Q& c) A5 s2 U2 b3 N
/* Enable synchronization of RX and TX sections */ 0 [' T- r# f/ N, d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' r' [8 h9 O, @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ V$ C' k, a, A2 t* r! HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; ^; \# V6 Z8 R" [** Set the serializers, Currently only one serializer is set as' O- d5 t5 G9 a. Q, A7 F
** transmitter and one serializer as receiver.
/ `/ Z6 w" e& X" y2 l*/
! j, n8 D# S" i9 c2 _& S3 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ y& B* [# ?% c0 G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; ]2 O) J# Z: l, x5 G9 {, U9 T3 a* A& w** Configure the McASP pins
# Y2 Q% O( R% J0 C% _/ ^** Input - Frame Sync, Clock and Serializer Rx
) W: B' v3 w7 `* A; ^** Output - Serializer Tx is connected to the input of the codec
, ` `' k$ v) T. l- M*/
# @/ W& f9 e" N! k/ KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ _( S8 ^* r$ [- s( t# x" M# rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 }3 f+ Q) U5 v% K" s) C. F$ X' i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 K p, p: M, @- j& }
| MCASP_PIN_ACLKX
7 f n" E5 F7 {1 M4 H6 f| MCASP_PIN_AHCLKX" s6 D) G2 X, _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# j& I0 w2 }2 ~1 p8 w6 k2 k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: z; q2 @ [, a8 F| MCASP_TX_CLKFAIL $ N" @9 i. p2 Z. J/ ? Y. j) o1 C
| MCASP_TX_SYNCERROR
0 d: Y- ~) W4 A3 }% G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 ^) s! v. s8 V9 \( V
| MCASP_RX_CLKFAIL2 w3 ~ H5 ^9 a! P
| MCASP_RX_SYNCERROR 4 {1 T- d$ O5 X2 V
| MCASP_RX_OVERRUN);
& t" x4 W- T6 s* t7 I3 U} static void I2SDataTxRxActivate(void): ?( Z2 t. W; p2 l6 n* n+ Q- n
{' ~" w/ t& ^2 y0 _- {, u# w
/* Start the clocks */
" r$ F+ }2 I5 j& b7 E" e7 \0 k( uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- O7 S5 m# F& ^0 F6 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% n3 k' d/ c! D2 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 u: t1 D& ^) t* t* z: _5 X6 `
EDMA3_TRIG_MODE_EVENT);
, A; u& J, G) w0 V. GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 b: Z' K1 |3 _% L5 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 O2 K% a' ?1 {- t$ K) c: FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, X/ z( y; Q4 s6 w3 ?9 m* c+ W3 r$ h) fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 B; V+ B0 {. U- p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! N7 j3 c# i: i; v* t. W9 P. O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) p2 r% d) `+ J4 W7 E: v% H ~- kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: D1 X8 w9 }% S+ _0 M' s8 }$ B( F}
6 C; Q: H' y2 ~8 [0 u$ y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 e7 J1 ~' O4 c
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