|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: o' l% j6 S4 t- I! {: {- M+ m( zinput mcasp_ahclkx,6 Z2 \7 K& H- B
input mcasp_aclkx,% n" G& F( L' U x( p0 p
input axr0,
/ h7 m( C9 D- w y
' ]* I( Z% Y0 o3 ?output mcasp_afsr,
; @, ?3 _8 s H& O! f* Qoutput mcasp_ahclkr,1 n4 Z. k/ u; n: L6 i4 S
output mcasp_aclkr,
Z _% A; O% P6 b. F7 ooutput axr1,. }" m& A' d! [# s+ N
assign mcasp_afsr = mcasp_afsx;+ E% ?5 i! x. k0 @8 W, |
assign mcasp_aclkr = mcasp_aclkx;
" l3 Z7 C- [& E r& uassign mcasp_ahclkr = mcasp_ahclkx;: ~7 z/ {) T- S+ z1 Y$ L
assign axr1 = axr0; 1 g6 K, m( L# D$ _3 q5 }& o
+ m& X6 f7 u9 M5 ?9 I3 k/ }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) |; ?; B. J) E; a2 y
static void McASPI2SConfigure(void)
/ c: {6 o" G& o( N3 p& U/ }- {{; v: p1 m+ p+ S2 e5 Y6 C* R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( T0 A3 x& _( w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ r& v2 W2 l& pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 s: y* [( w' n/ E. eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( V, S) ~7 E! X' Y# h* hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ k/ c8 |& x. i9 U+ \MCASP_RX_MODE_DMA);" i ^1 r3 p, t. u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 n$ j( A3 t# E; O4 W" N& x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" X. a9 W0 B% ~3 d8 p- `/ b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! Y: O+ p( e# ?% t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! g% j* r% y' oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" m8 s5 X5 N0 t9 A4 C+ I+ h, C7 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 q, H9 }* p; Z) GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 N$ z, e7 t( F# r, P; c% k, W8 j# KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
Y3 i& ^* _. |* cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( ~" U5 I0 o1 E/ y5 u q& _
0x00, 0xFF); /* configure the clock for transmitter */ f7 V' v2 `8 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); l5 L0 A4 J3 w9 t) m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); v9 ]/ ?+ r9 i! {- g& O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ T' q: i! Y0 c8 P M, a
0x00, 0xFF);; i0 a! r. |$ q/ O/ `
' f8 {( [- l/ E) D5 P, Z& ^
/* Enable synchronization of RX and TX sections */ ! _* ~4 ^/ C) M, i; _8 |& S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# z% [" B% @) y' ~" U. m, J5 W7 f! zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 f$ I3 E) C/ {; H5 D8 N5 E6 x- }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** d8 c- i5 h* G4 K! d0 r: K
** Set the serializers, Currently only one serializer is set as. a3 ~( U: A" {! t# g: @
** transmitter and one serializer as receiver.0 q! w& J/ u7 b
*/0 ?8 h8 w, I" z- ?! M) U+ a2 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& S* s. A5 _" r8 L( d5 d, c' iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 s+ o; N7 Z3 O/ W' u5 |** Configure the McASP pins * r7 s: L: h) q! ^) G! l
** Input - Frame Sync, Clock and Serializer Rx9 G% T, B! e+ I8 r7 k4 ~# j b
** Output - Serializer Tx is connected to the input of the codec
, {, N8 `3 F; \7 m7 R*/% B2 A$ o1 x. l4 h8 ~0 ^# r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% m4 }6 L1 j5 J& B c7 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 T4 Q" g+ [* f* }( U( e nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 E2 Z, t1 N& K ?- @9 W1 b; h$ C| MCASP_PIN_ACLKX
: d. @/ l% _0 V. u# T- y| MCASP_PIN_AHCLKX6 v2 O( k9 D$ y2 z0 q1 U* ]$ E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# ?1 r d& W: u0 \& K9 oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - H. L0 W& v' r0 G
| MCASP_TX_CLKFAIL ! W$ m8 b7 S; x' Y3 R& k
| MCASP_TX_SYNCERROR
) t2 K3 c) p4 U( r* X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 y2 @; ]& F7 F- V* f2 U. O7 t& d| MCASP_RX_CLKFAIL
# n8 x" V: U4 ^| MCASP_RX_SYNCERROR
/ V! y; K! w% S, E; u9 C& L| MCASP_RX_OVERRUN);
6 Q- q/ {+ Z: W I) b} static void I2SDataTxRxActivate(void): O! x& d% w( z2 Y3 k" O
{
1 |9 Z: t" l: u) g/* Start the clocks */ N }% j% p2 ~4 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) C1 [9 }- a1 J2 P6 \& t5 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 y' {9 I+ q9 b7 F2 f8 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, z+ J' e: a3 B! w3 D2 ^! @* \
EDMA3_TRIG_MODE_EVENT);/ Q6 |# i" E& l6 Z, t- {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + g# {4 G: I" ]4 N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& K8 Q) X1 | J& G' h9 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% |/ W/ l# h+ V ?. N+ i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! \) m) t4 q& {; x+ jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ W; a3 ~% z0 ^" w. p' Z, JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ ^- |" b3 S# VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 s1 J. C1 x/ j6 `
}
/ v4 Z( f8 D$ X8 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; H6 M! a- v5 f) |3 U
|