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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# \* B" U$ _- Q$ ]. U7 C, N" m
input mcasp_ahclkx,
* \4 Y! V& s! oinput mcasp_aclkx,
* V. T2 _( ~5 n, pinput axr0,2 D) V7 C' Z5 O5 e f1 n
' [4 a0 V: @- ?$ l3 F! Toutput mcasp_afsr,# x: @/ j6 E8 k
output mcasp_ahclkr,4 W" N* K' e* i, {
output mcasp_aclkr,
% _! M# a, E6 Y7 X5 woutput axr1,
$ o! j, f5 G* b assign mcasp_afsr = mcasp_afsx;
4 s0 u" _8 }1 D" wassign mcasp_aclkr = mcasp_aclkx;
# M, a. y/ [; ?* o- {# }assign mcasp_ahclkr = mcasp_ahclkx;# C$ X: I! i# w2 Y
assign axr1 = axr0;
/ z9 t. K/ q& W/ T0 X* F. X
0 s" a$ h$ y. @$ J7 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 O! v6 Y& {" z5 i) Q* N; h5 D- ^static void McASPI2SConfigure(void)
: }/ o! Q1 N7 l* P) |{" N! L. m/ f3 N$ \9 x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 `, {6 k9 Y' l m7 }$ N' b( U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 ]3 y( J* ]9 Z7 o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 u% N4 }& B% `- D% A% v" \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 V! \1 y8 m& _' J: u4 v& N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% r5 @+ z( s, ?8 a9 HMCASP_RX_MODE_DMA);
9 Z( w. y$ R: @& [5 d4 u8 M( }, a8 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- J# D) n( M$ m# u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 Z1 B7 J+ f1 D8 q. D( `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 S1 ~0 p" h7 UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
f8 A/ U0 Z, h5 f" _ Q uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 R- M6 n8 _0 u! G% r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 T9 O# Y2 x4 Y1 |: Q FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ o- L1 g" j: Y! k: J5 Q0 W- i+ EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / c3 Q& ?7 e& I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, E& Q9 S$ V+ u& z! J# ?0x00, 0xFF); /* configure the clock for transmitter */
: c, D- @" K8 \5 `+ \0 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# \ a4 |0 S2 w* Z; K& R1 N+ q) lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ c( Q1 [' I! z0 ~9 J! oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 Y. x6 t c2 f; B) `- e
0x00, 0xFF);
/ l* A& Y5 S( _) U' Z6 ^! L
9 S- y1 c# L- O2 y/* Enable synchronization of RX and TX sections */ " q9 a! P g0 j$ T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 m: z& N2 O+ s0 Q. sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; D8 R3 r1 d0 N4 M, m ?9 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ u) k; K" q/ n/ u' i0 Q** Set the serializers, Currently only one serializer is set as
) G p" N5 d% Q# c$ u! i** transmitter and one serializer as receiver.6 Q: F2 U9 Q4 _1 q) X6 }- Z
*/; c2 G8 B. g- c3 k- x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 B! E; p* c; \! c ?! G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! R$ H- u, h& n& G
** Configure the McASP pins
! [' O$ P, N9 t** Input - Frame Sync, Clock and Serializer Rx
, c, D6 R' Z6 k8 \/ S% L** Output - Serializer Tx is connected to the input of the codec 1 M. b4 b- `/ T% F5 ^( o1 r3 V
*/% t! D; w7 P/ Y, L! P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' r" G8 c2 {5 P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ e2 q1 R, k+ NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( U, ?% }& b* I! [; r# I2 k3 T4 G. \
| MCASP_PIN_ACLKX
& s4 @/ t' w" i9 I0 }2 x| MCASP_PIN_AHCLKX6 o9 ~4 \0 N2 j& r; h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" u( b; M' k$ R" Q" a* A* m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , P( o5 r+ ]. {& P' [
| MCASP_TX_CLKFAIL . w+ W8 m" K, K; k' y& w
| MCASP_TX_SYNCERROR
2 m3 ]! O; \9 O7 G$ x, R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR w$ k* U. a+ _6 l' l( s
| MCASP_RX_CLKFAIL2 B4 n' s. S' Y* m
| MCASP_RX_SYNCERROR ; X# w3 g5 x2 E5 ~( k# I
| MCASP_RX_OVERRUN);
; i8 o9 H& T& W) A) P7 C! }} static void I2SDataTxRxActivate(void); k1 ~% C9 |' |% t3 `' W2 B# P
{
3 z; ], g; Z W5 n0 p+ `6 t/* Start the clocks */4 h9 P" O* [8 [$ P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# Z1 w9 b! m1 {& m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# ~2 a- K4 j* E& f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) t$ s+ t5 `/ Y. M; ~
EDMA3_TRIG_MODE_EVENT);
, a5 o; ~5 S! S: K+ @( O2 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 Y4 i( f) _# A, C. Q$ y! @8 `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! d4 T: _2 {' D% a6 [9 V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
X P# ?6 N4 [0 u4 t7 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 H/ D+ E, {+ ~" Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- o8 ]- x0 F2 C2 a; D+ p5 k5 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ W! w% H: t0 P9 D6 N# v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 \: c* ~! N* ]. u
}
: @1 C! X# q4 Z/ W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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