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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 _# `4 @+ ?8 w
input mcasp_ahclkx,; B" C% ~# t: W$ d1 o$ H2 E
input mcasp_aclkx,5 q3 C5 x0 C* k5 F, U
input axr0,6 e4 J* ]+ G+ x9 X* N
0 n; ~4 Z0 o+ woutput mcasp_afsr,& M/ n# |' N0 g4 L6 `8 o
output mcasp_ahclkr,9 c, A9 @5 [$ e& V; w% C
output mcasp_aclkr,$ I+ E7 d3 N) K B2 o9 _9 @
output axr1,, q. X5 j4 C9 o) Q: X$ J" D
assign mcasp_afsr = mcasp_afsx;
' Z9 H( W3 A2 E7 ~* Hassign mcasp_aclkr = mcasp_aclkx;( ^% A+ k% h j2 S: J6 ~; m+ q
assign mcasp_ahclkr = mcasp_ahclkx;
0 r" c& [( d; X2 B9 w( \7 Xassign axr1 = axr0; 1 p% C5 G5 o/ ^( x
, m/ m4 C Q: |0 T' g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ F# h: d0 `; Y+ o7 l3 o" @static void McASPI2SConfigure(void)
# o! y& ~5 L, h: R( a: _2 A{
, w% q2 n; ?; e. ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ y' s' \, D- ]! h4 R6 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 c2 T2 }$ A5 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 s; b, H$ P8 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% z$ x9 K0 b6 x: c4 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* u' a# S* N1 h2 X& N) p2 u9 nMCASP_RX_MODE_DMA);. a9 `! f1 b" Y& I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ t5 [6 p3 F, b7 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) j- L ~) |0 z3 q( y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - A+ f* E* z, w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' R& P4 C' P5 y3 D: p! x3 FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 M8 x( r% x2 W. L5 P5 p; S. f( X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; u. j. K+ M7 s, e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 k% _) y- l, A8 |( K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , k- c; o4 s' c% u; L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 v" J; I/ a4 i7 V
0x00, 0xFF); /* configure the clock for transmitter */1 j0 d( D0 j/ [2 f9 _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 o, J( I/ u9 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, K" K! r9 `0 w8 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% J0 C& H% ~8 u1 K- K
0x00, 0xFF);
% ]" z0 a4 V6 r+ M
: g! ^$ @8 ]9 _: I8 a/ d/* Enable synchronization of RX and TX sections */
4 c" O6 B y' L! K& G9 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 V' F+ k! K9 p+ N( Z7 X% bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" i( r- ?+ T7 H/ U) ]0 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 @6 ]& ~. ~5 E4 w: t* f I* z** Set the serializers, Currently only one serializer is set as
* B7 p$ T8 v- m* w P** transmitter and one serializer as receiver.
* ?7 {( z5 O, n- [$ O0 m4 k1 T/ b*/
) _1 e' m% u1 J7 S% k# r) R0 m! i5 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 C( C7 G: X2 w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ ]2 ~4 t* w' b, k% \5 I** Configure the McASP pins : c+ E- X) n8 `5 y7 ^8 y
** Input - Frame Sync, Clock and Serializer Rx
8 F8 a4 @* v- ~7 C( P** Output - Serializer Tx is connected to the input of the codec
" T1 M5 F, s" l& A*/0 Z9 g) ?. r+ e$ m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
g# m( C& U4 K; xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) V3 w- R* ]! ]8 \' z# @* J- H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. c% u- |. C1 ]
| MCASP_PIN_ACLKX( V x; \4 h; B- S/ z
| MCASP_PIN_AHCLKX
7 i1 q X R* ~9 T& O/ e( m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ [/ ?+ Z4 e1 K, aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 u3 u$ ?3 n; }6 k* {| MCASP_TX_CLKFAIL " s6 W8 X [, Z. R4 g
| MCASP_TX_SYNCERROR/ L+ s' {- ~/ c, Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ~. u+ v7 b# O- Y. B| MCASP_RX_CLKFAIL
1 O1 H# v( r. n3 h( m6 W| MCASP_RX_SYNCERROR 4 ]0 R9 F9 [6 R. `% X2 K; Z) y
| MCASP_RX_OVERRUN);! s4 F5 |: D7 o: k; r0 z2 Q) i
} static void I2SDataTxRxActivate(void)+ r! Q3 g! ~3 s
{3 w: M' \: \- b
/* Start the clocks */0 T% S& g+ w, f; r: \6 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, a( V9 y& O; F5 ?) \$ J/ fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// |1 ^* D9 p* S% U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# N; \% l% S a$ h' L0 }EDMA3_TRIG_MODE_EVENT);
+ M2 ^# z4 p8 I2 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 p% \& ]) h; J$ [( JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: o" _2 q) f9 \9 Q' y; YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 |2 I# J/ E6 W1 e5 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, }) b2 u+ E! Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, I; v+ e4 [* t$ V; r. C# hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 f/ F4 A0 _+ U) L' {4 AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. V6 K7 i, k9 q) P1 A) j; f} ) O: F# I9 _: v2 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 t& l! Z+ C F
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