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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; R# r) U* t/ f1 G# ?' J
input mcasp_ahclkx,
0 ` x% ]6 i' M; V6 _0 Z$ N% Linput mcasp_aclkx,
7 U2 E3 }" L* Winput axr0,
8 E; x. p; C1 y, n0 O4 Q2 U
- }- m& {1 q; m4 ^output mcasp_afsr,
7 V! z2 A- `" doutput mcasp_ahclkr,' d2 B8 n' S% v5 X4 b$ Z
output mcasp_aclkr,+ \9 K2 y% r5 m; x2 ~( R& |) H. s# p
output axr1,
; h. |; K% D& n- } I% K assign mcasp_afsr = mcasp_afsx;/ K7 ^! K. ^+ n' v
assign mcasp_aclkr = mcasp_aclkx;
" E0 v/ x' ^, r/ {) @/ massign mcasp_ahclkr = mcasp_ahclkx;0 v& w8 K/ F& F9 r$ r
assign axr1 = axr0;
: z5 h; L# @/ @# J9 ^
+ ^! x" m3 j7 f6 z7 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. Q( R. P! V3 y% u* E- qstatic void McASPI2SConfigure(void); ~9 p# N2 n7 E1 i8 w- L
{4 }* Q7 `" [! Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) M- X# X5 r( h6 _3 F9 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 b( L# s; V m6 S8 l; Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 u% s6 M* J7 {' [" z- Z$ o$ zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 x3 f! Q$ j2 N; X8 m' e' p# R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 U$ J% w6 @; u0 i; L! PMCASP_RX_MODE_DMA);
0 T& @. v8 r8 EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 A! b2 I& P; ?8 D) n- M7 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; I' i5 v( E3 S# jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 Y2 G% f Y& t; {9 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) j! J- A2 [, q$ Y$ A X @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* Y/ O5 p0 c# v1 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 s; H Z$ l; I" h+ u% l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# e( w O) k( o7 `& @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- t: n1 ]1 c7 T4 K* [$ G3 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ w: _+ E8 _( d$ h1 W0x00, 0xFF); /* configure the clock for transmitter */6 a; s7 E5 r4 |. h3 W0 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ A/ s1 K' a* ?# wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 t7 D7 ^: {3 s% j1 m2 s. G, ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( U2 [0 e/ w6 v; b4 @' C5 ]0x00, 0xFF);. s' {8 Z/ j) r' Y0 N' F
# H6 {% r. i' k( Z2 k
/* Enable synchronization of RX and TX sections */ ) F: m9 |/ H4 B! M7 A8 D0 c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
w) ^7 ~' y* Z0 V9 g! G J7 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ]( \# N( K9 _$ z v. ?: ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ D0 R- c' K- F0 z. ?- Y/ V! X** Set the serializers, Currently only one serializer is set as
1 H( j- L( h2 D3 w, i; Y) [2 n9 U** transmitter and one serializer as receiver.7 X* B/ r; j6 ^( R2 V' P. w8 v
*/. k9 z. d! G2 X1 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( }' { G3 X6 Z4 o- I9 g% A7 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- i ?8 {! r% q; f% P$ ]. i** Configure the McASP pins
0 d5 f; a7 V" r2 [** Input - Frame Sync, Clock and Serializer Rx
7 w* t+ Q. E/ G0 Y0 d- g2 D** Output - Serializer Tx is connected to the input of the codec 6 M* N- W J' a$ d! ~9 o2 O$ w
*/. B1 r/ K* F5 P# H" O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ ?7 }& l# U, ]. @" u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. I* N+ A, C- o9 G! Q3 {6 b( c- yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 f# A2 f; t9 m7 x9 F( B
| MCASP_PIN_ACLKX& r1 |: a* r m9 Z
| MCASP_PIN_AHCLKX
0 a5 I* ^% R/ s& i" k1 v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 X" a" [. J3 K- a+ K1 l1 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 l- \# F+ m) B5 _* M' ?0 R. Q
| MCASP_TX_CLKFAIL & v( H' |3 K; m$ p. m: u
| MCASP_TX_SYNCERROR
+ P( ^1 {' E7 v0 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; ~% M& U1 v4 P| MCASP_RX_CLKFAIL; m3 ~ m4 K$ ^! @1 O& j
| MCASP_RX_SYNCERROR
: s2 |6 G+ D4 n' N: C, H| MCASP_RX_OVERRUN);2 p0 D4 u% |& S7 s
} static void I2SDataTxRxActivate(void)0 C& p9 t# ~8 N N
{
2 R! n3 S' d' g" z1 z5 ]/* Start the clocks */
, ^* y0 ]5 H8 f9 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; s+ j3 H5 }3 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. F1 {- b" e$ O$ {( w9 ^- yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 p' w3 I r. [; F# Z1 ]2 ]EDMA3_TRIG_MODE_EVENT);
, m* X5 N! D0 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 D6 u$ T5 i1 O$ L1 J6 V! Q2 o1 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 z1 W& J9 Q( C. h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; `. D# R( h: h$ t9 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' c8 D5 E0 b+ q, P4 Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( T7 l+ O0 ~& Z: PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" R) U- T0 k0 @3 [, T* _, QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 T: S v; B8 k* y( v5 d
}
1 S1 _4 a7 u! o& |+ `; C4 t8 \5 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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