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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: \+ i- [9 V8 a5 I+ {1 @6 }& ninput mcasp_ahclkx,* ^& Y2 F2 z4 I4 s y, v" b
input mcasp_aclkx,
, G) x, S/ `7 B& K" oinput axr0,
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! l/ n+ Z& i7 m* W% K1 Coutput mcasp_afsr,
4 B2 k7 M& F9 ]( L- Moutput mcasp_ahclkr,4 y" x8 k: h- @7 H+ A
output mcasp_aclkr,
* i% ~; _8 t' G& qoutput axr1,* d" k: D" t# T4 N. _% S# P( W
assign mcasp_afsr = mcasp_afsx;' e4 C0 b" d7 t# g2 A8 B0 v
assign mcasp_aclkr = mcasp_aclkx;
% Y( c( ?4 I$ X( |0 |. U0 fassign mcasp_ahclkr = mcasp_ahclkx;
) [+ e1 [; _' t' r% Kassign axr1 = axr0; ( h$ Y4 U* h* i9 i* ]- b* L& S" n) w
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 ~: r" X/ } W- fstatic void McASPI2SConfigure(void)% \6 b. P0 v# |
{3 E$ f0 p0 m6 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& r3 P6 Z* W6 |7 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 M2 V' D! W" x& E5 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 a6 R+ u3 B& V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 a; q/ _) l2 q/ o( r. D* W" NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* \" }; n* P& @3 f( R
MCASP_RX_MODE_DMA);
2 H& Q( t3 }! IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ?' ^7 e- p4 U5 ]. c! h( l) |9 AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. h4 R3 I8 ]( ]& R H- |1 x, N- [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( t6 w$ g- W k. i! R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' J+ u2 ]' i' WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , N* n5 u# r! f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' q, k; Z, s* H- v, g: l% ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 D! u; ]% [% }! |; H/ P0 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 Z& @& I5 J; ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! \/ Y4 O0 [: d+ ?* F( o
0x00, 0xFF); /* configure the clock for transmitter */; g- c: A: c( \' }( K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, n* D; b- S& k6 m0 _+ t# [) cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& O& d4 F' R+ x3 e, ^* X qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 i7 R1 h4 ?" K( m3 u4 z
0x00, 0xFF);
! E! h$ ^$ S" e; ^$ Y: o4 f( r1 l# L$ u/ V
/* Enable synchronization of RX and TX sections */ , E }2 i: l) K! `3 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. c* _$ Z5 Q- E6 [5 t: PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); I2 L3 K+ [* C) \) B2 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: n% c/ x" I- l: r+ e
** Set the serializers, Currently only one serializer is set as
7 ^6 j9 i- f+ |) b** transmitter and one serializer as receiver.
5 J' D; F/ Q4 u! v# F4 B*/( x* h1 f4 Y( s& o& X9 {: @+ m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 i9 _9 w, h5 J4 y( ~+ OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- }. |) J# g. D, E8 Z8 ^$ i- W
** Configure the McASP pins
" W! \$ m3 _4 d/ c** Input - Frame Sync, Clock and Serializer Rx
& z% O5 x0 n r$ x5 h1 h1 \3 E& p** Output - Serializer Tx is connected to the input of the codec % _5 O( k. ]) o6 X+ ?7 u* M
*// u+ v1 o7 F* B0 H1 @/ k3 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 C; j5 D9 c# c5 J. l, I) eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 A5 ?4 A" Y- X+ E9 V! DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 `5 I: u' u, h* l# r
| MCASP_PIN_ACLKX2 i! @3 `& \& z
| MCASP_PIN_AHCLKX
* d) d/ X9 }/ V" n3 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; `8 ~/ d/ M: e6 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 Z/ L# N* _8 K( q6 x
| MCASP_TX_CLKFAIL
! U2 ?# X6 V% U2 M+ c9 t| MCASP_TX_SYNCERROR1 ?9 D- {* f; v6 K+ p" \/ S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
f; y% P; Y. \9 }+ c7 g| MCASP_RX_CLKFAIL
; e' i1 w( G, _2 `0 K| MCASP_RX_SYNCERROR
# |7 ]1 `6 ]+ u) }7 C1 K| MCASP_RX_OVERRUN);6 t) S' ?/ P& ?4 C% q0 j
} static void I2SDataTxRxActivate(void)0 t1 p9 b8 f/ r5 t" ] ~
{6 H& T% K/ U6 ]% G
/* Start the clocks */( [: B1 S; U1 I* P+ w G. S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 w1 ]# r& }; S- u# F0 U* A9 b/ f- vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 V2 g* J7 X8 f3 n1 U$ A" y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) P K( m8 k: X& iEDMA3_TRIG_MODE_EVENT);
7 H+ U5 j/ _, q! t7 y5 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 F& g4 W! c! U L& M' eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! q6 l% p& O, ]0 S3 j& w$ H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' H" v: e7 x4 Q3 \! Q* x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; c* a- H; v6 v! X) l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 M) L/ U$ C& c2 B4 |5 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& G7 h- d: v) n1 l# `6 q2 A- d/ YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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