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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! U* {" z7 n3 K6 {1 [& Y( Finput mcasp_ahclkx,
5 Y% V* u6 j2 L5 p/ s0 x1 }input mcasp_aclkx,1 [ k) @5 f/ i
input axr0,
, @# E( T/ Y6 N+ I+ }5 f. {8 P m# o& Y5 j
output mcasp_afsr,
* R# z, o D3 t7 V* noutput mcasp_ahclkr,
# Q+ k6 v. H, ]output mcasp_aclkr,
6 L+ S0 Q9 M! woutput axr1,- u* J# p. U t# B
assign mcasp_afsr = mcasp_afsx;- F* M% q- Q' S. c
assign mcasp_aclkr = mcasp_aclkx;
. l( b1 m5 m# X! Tassign mcasp_ahclkr = mcasp_ahclkx;
s4 g3 j2 z4 l2 l8 N" r4 P9 {assign axr1 = axr0;
8 t a6 a, M& e( W- y) ?: ~* v6 T8 `) L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 p# x1 O6 S# P
static void McASPI2SConfigure(void)) f2 ~3 C; X$ q- t
{& m1 _. o* ~1 {7 n2 U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; b F. ]: I4 @/ b& K; q7 X- SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 |) Z# L7 g7 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- N. n1 y7 C+ B# W3 |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' [6 {4 V( b9 \, @+ F& aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 V6 U2 {) M5 @ f& hMCASP_RX_MODE_DMA);
# V) l8 R! V* ?4 [1 ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' e* B% d, h+ y/ vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 M& O1 p) c* N$ rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # x Y l: |+ i0 m4 G6 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& h0 W" ?8 C, o! SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) I/ z' Y& |+ |( j6 m, } t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 M2 i- q8 b& I+ S o0 F, q( kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; [8 P; s' B% v: N9 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 _" T+ ~5 H* g2 T% W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 ?$ @: j2 A t4 n0x00, 0xFF); /* configure the clock for transmitter */: k" t! f# q7 g s7 u/ Y$ u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 e6 m+ J7 p( V" l: k8 R& q, a7 {5 c/ }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 I: ^; L! m; y6 d# GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& m r" \& T2 g0 ?; s; ]( }0x00, 0xFF);
. [* S2 v4 l- g7 V0 k
/ x/ ?7 Q& L8 ?8 d/* Enable synchronization of RX and TX sections */
3 n4 R! F; Q# zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* _! S6 s" U. a. {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 J0 p2 u0 Q$ X0 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: ~" c- ?7 u; u1 G8 b. N
** Set the serializers, Currently only one serializer is set as) @+ \% O, L P" i9 x
** transmitter and one serializer as receiver.% z0 G, R3 D3 \8 W: O* J; M( A. Y
*/
- F9 v4 R2 T: p, Y% JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 C" ~9 P) d8 ~( U5 |$ x- tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ T: v \% i- t6 `* T, A, p** Configure the McASP pins 9 z7 M, ?- y! o! z- u1 `3 y' n' R
** Input - Frame Sync, Clock and Serializer Rx
6 H+ {3 j/ P( Y/ M& m** Output - Serializer Tx is connected to the input of the codec # t5 F$ I R+ y1 U
*/9 e. b3 {# u" c- Q& @% J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 h5 k; F4 N7 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ i+ P. b, J4 `; AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. e1 l" `4 F, V2 }| MCASP_PIN_ACLKX
* @) P2 w& V4 L; ^$ {( k, e% w| MCASP_PIN_AHCLKX: K& c6 H; n7 O, J1 V, H6 s; o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# P/ d) G* Z( d& _8 D+ ?- W( q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 Q) Y' B+ P* V9 ~% E7 M| MCASP_TX_CLKFAIL
3 O2 e0 I4 r& h| MCASP_TX_SYNCERROR
6 k7 S% Z. Z/ G, [; a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR s- v9 a* `9 X8 Q# o' ?
| MCASP_RX_CLKFAIL
" f- b, c! b: Y1 @; [| MCASP_RX_SYNCERROR 7 `$ P& E3 U5 C! m4 T7 B( K
| MCASP_RX_OVERRUN);
; N8 N, Z' [/ U% N# V3 {} static void I2SDataTxRxActivate(void)
H. L& {9 @5 A. J+ a1 C: m1 Y{8 I' q& r( `- \7 t r5 D Y
/* Start the clocks */: {3 |3 Y' V( n2 L0 T$ s+ g# [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* e$ m! h+ Q6 i% H; nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. [9 A# ]6 h" q, O0 R, QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: W. c3 o. \0 Z9 G" @. c
EDMA3_TRIG_MODE_EVENT);
8 a. W- g6 r% r2 R! i7 m, pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; s( ^" R! K6 ^6 G- h1 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" R9 d* Z$ G! ^: T' _, F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 t2 x# _/ a+ z1 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- p8 I0 Y( V5 e0 [6 j+ H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- s! V" K0 E8 I' ^1 t& {9 c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; M0 Y$ ^9 r: |9 d) x$ a1 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ s3 [: f6 T. Z0 L}
7 ^5 \8 R) b( Q T+ a9 A9 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : K2 r4 X9 R4 A+ W+ D7 z7 X& x
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