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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 E: J4 W, F9 E+ V- ?# |
input mcasp_ahclkx,
4 Z" D; B, \# I4 hinput mcasp_aclkx,
) u0 c0 e& G, S& R' U5 Zinput axr0,- g; E( m8 y3 b3 k5 c! f8 m
& h" i2 h2 ~+ A, r1 ]2 {% b
output mcasp_afsr,
, b0 T% H. r# y* Doutput mcasp_ahclkr,0 e( H% Q6 ]1 B
output mcasp_aclkr,
, ~- k% l; \. toutput axr1,
' h# b! \9 L6 r4 C" } assign mcasp_afsr = mcasp_afsx;3 J5 i6 M( ]) m* v* w& K* y
assign mcasp_aclkr = mcasp_aclkx;
8 s& E* A3 m7 y# j. Passign mcasp_ahclkr = mcasp_ahclkx;
1 I# z8 g- _# w2 d9 Xassign axr1 = axr0;
7 Y6 o0 g9 ?- O# ^. n4 Q+ o# S6 G6 l6 O H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 d/ v+ h# A. t' i" |! @6 @static void McASPI2SConfigure(void)! U6 e5 F0 ^/ e% u+ U; i; N
{
7 |( w$ v) @- Q1 aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) i6 p* U9 C( F, D3 C$ r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ E2 j8 k' u% _0 {7 T0 q, J8 [) F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 p$ t% f* L. B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ]0 L. P( S# h! }/ `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' l5 b! b! \0 `- X% i/ _+ m" O
MCASP_RX_MODE_DMA);
/ V n6 K! x- c6 M3 n4 d- G ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, Z$ `+ j2 o! U. a3 Y) Z2 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 N# k2 o7 q2 e! g9 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 @3 y0 o. ] D% P# ^* U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" I8 c" \0 k- B0 Q3 E) \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 y+ z: x- o# E3 v8 K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ v" `4 |2 }% `, mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 a3 _1 H2 i5 j7 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! g6 g8 U+ G9 U; M) H; a, u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* U7 H" P g! x* Q% F4 ], n
0x00, 0xFF); /* configure the clock for transmitter */7 @# M( m L( `" i: }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: q# \; h+ V1 }1 b6 a& G9 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ {( I% `5 ~6 v. S! S8 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 ^8 c% S+ Z# u" c% X0x00, 0xFF);- M2 A) u( H$ N2 b
6 v9 G3 N4 ?" c
/* Enable synchronization of RX and TX sections */
* W) Y0 \ U9 A- s3 P+ I; S1 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: Q/ l+ i- K4 ^" |7 ?! R" G6 ~, k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% A7 s' _0 M- lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( m# |7 P' l& n9 E8 m1 N4 m** Set the serializers, Currently only one serializer is set as2 L3 I/ [! t6 [3 C- Q
** transmitter and one serializer as receiver.
; C# @) {9 V- n4 C*/
! p+ e" p' g" m8 R5 ?9 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; O6 `. `* A2 B' D, t+ [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( z) X. B ?8 s1 s2 ]- M1 Z- u
** Configure the McASP pins
( K, k/ C+ p! ?4 m8 ^4 A** Input - Frame Sync, Clock and Serializer Rx
! r2 ~0 R/ v, V1 ~- v- V** Output - Serializer Tx is connected to the input of the codec
) [& U- V2 @2 J& h' I7 F6 T*/
9 E( r/ L9 s/ X g1 X1 D5 h$ ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ^: C8 @3 _9 X6 X( W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
~5 W/ ~/ T) c2 u# }+ C1 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 w8 a# g5 B! g8 g. V" }% v9 \0 ~# c
| MCASP_PIN_ACLKX" I5 f n: N6 e# p
| MCASP_PIN_AHCLKX
0 k- f u4 v. l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 f0 O' u" O0 |0 v2 P" P9 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 B' V# X3 Y6 _6 N+ K' I3 ~! b3 G5 ?
| MCASP_TX_CLKFAIL / h) M1 r" j. G' ^" M' s1 q
| MCASP_TX_SYNCERROR; o( `% [3 Z6 W& ]) _/ i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% I9 x3 ^, w) k; {| MCASP_RX_CLKFAIL
9 w2 V5 q+ c: Y| MCASP_RX_SYNCERROR
+ {8 ^/ B/ z. A2 ^8 T- U) J1 P2 z9 P| MCASP_RX_OVERRUN);' o Z' n t; p! D( X, v
} static void I2SDataTxRxActivate(void)
) ]1 z6 C9 J- \0 t) N( E. X# u{, B7 T# X, w- C; g9 d6 u
/* Start the clocks */
; T# P, {3 z9 m( DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ F% E1 D2 M+ }$ U! N' N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ~: r, K) y' \, zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. [0 S8 b( F% M: M- ^
EDMA3_TRIG_MODE_EVENT);4 c# S% I0 X1 }5 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 T7 k W/ Q+ [0 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' C4 D2 W& e: _/ i$ CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 E7 v6 M9 l; B: h3 C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 z7 g+ ^8 i$ g; awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- C& Q: D* o3 @" |9 E% F7 D/ rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
V7 @9 q' R# t( Z3 P$ y: s EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. l" B, [6 _6 C+ Z# X
} 7 ^6 W/ M% O. o% r' Q7 T& q5 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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