|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# V6 ~, R' i; Y
input mcasp_ahclkx,
( ~; ^0 B: i+ Y* m( l& einput mcasp_aclkx," d3 t6 j4 g# A" l6 z
input axr0,; {$ J, I% r; Q% j
" @& D4 r0 r ]& J9 U, Doutput mcasp_afsr,& C2 n# U0 d3 O; z" e+ o5 o0 m
output mcasp_ahclkr, u$ B/ e I/ k l0 d; y' E
output mcasp_aclkr,& b5 D2 A/ i$ G
output axr1,8 p b; W5 U \. l9 r6 e$ |
assign mcasp_afsr = mcasp_afsx;
* q4 t# G/ S/ Jassign mcasp_aclkr = mcasp_aclkx;
9 O) u W% t" q# A7 g9 ?assign mcasp_ahclkr = mcasp_ahclkx;: Z+ {5 Q4 U# u O: `
assign axr1 = axr0;
# W* }4 D! i: G6 M! N- O
/ w" N1 t* ~2 }" b H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% [4 Y z+ O5 }* b& ?1 ^ F# Astatic void McASPI2SConfigure(void)# W) A T @+ i' I8 m
{* a! G- |; G) E1 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- j$ D; X. ~' k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& T# d. E; r5 l1 p# J6 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ E2 W2 C/ d; h: z. O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# L' R, W2 F8 s7 C8 h& AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ~8 F {) {' E" M' T, x* R7 n
MCASP_RX_MODE_DMA);
* s9 `- A& C. r* f. W; x: MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 m( d g9 _, |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 E9 ]- z% ?% @ G% r. v5 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' u& X' ] q/ q" ^5 |( kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" Q# m" X3 y$ b1 r* L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, t% z; O* I, c7 R2 T5 X5 `2 p$ ~: ?. M9 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 v! i1 }# O# l( ~8 T2 e0 |& e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); ?0 ^) u8 J J( @) T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + p; j$ t1 V2 t% R: Z( J6 P( d4 T" ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; H! o$ k( I* \: ?1 j5 v: W. F0x00, 0xFF); /* configure the clock for transmitter */
. v# w" X( m' e" J( @# m" }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( K% c' |: `) F: u$ qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. G/ `) }, T& C+ |1 ?+ }8 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ L7 C. z4 K* M; E; x/ V0x00, 0xFF);) t# E$ i- G! T* K2 m
: z: q; `% ^. D
/* Enable synchronization of RX and TX sections */ ' P, ]/ J; d1 I( q. x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ l& m. D0 ]; H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ h% H3 ~+ I% R. r1 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 Y+ ?1 c; \' i9 Q4 H' P( y2 f
** Set the serializers, Currently only one serializer is set as
: w2 T ]0 ~3 O' g+ H7 y% ?9 U( W9 a** transmitter and one serializer as receiver., z* `' Q6 |8 z/ t' N) n ~" A
*/1 x- Y$ @! R. u0 y2 o z- l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: u3 l" r" @2 zMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ c4 C+ s/ G7 h$ B4 y
** Configure the McASP pins
6 H; B$ b: @$ O: X** Input - Frame Sync, Clock and Serializer Rx
/ s5 \2 z4 q2 G% S- x9 J- w** Output - Serializer Tx is connected to the input of the codec 7 V4 u2 |: B& m F
*/
7 [; y+ ]. M! _4 f/ ^- PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 z; x5 H6 e* \8 `) m% y! C! K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 o% Y( `2 y) ^; l$ a2 j: @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 w# \4 c% C/ F# R! K| MCASP_PIN_ACLKX9 N& ^; R/ P9 C1 W! z
| MCASP_PIN_AHCLKX( g9 D' Q+ l2 U9 E$ _; }1 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) H4 g5 w* O/ ~2 E3 Y" F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) T7 G% |2 E" F4 G
| MCASP_TX_CLKFAIL : `3 ~! B8 g" u' S+ X) _
| MCASP_TX_SYNCERROR. W" R- }( i. D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- {4 w, v" e! F+ u/ Y# M| MCASP_RX_CLKFAIL& P, g" Q# C# ]
| MCASP_RX_SYNCERROR
! ]1 q! a( |- j* j: G0 ?9 r, \6 T: a| MCASP_RX_OVERRUN);' B3 J5 A U3 d& s. T
} static void I2SDataTxRxActivate(void)2 O8 k/ ~( d; K9 w& M, u& I
{
. c4 M# r) h( A( B7 s, F8 @/* Start the clocks */
" I h3 r2 Y5 M9 _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 f0 k( i: O" O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ U4 ^3 L4 Y+ E W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
h" B a' d0 r' }/ ~+ s+ Z0 |EDMA3_TRIG_MODE_EVENT);' q0 [* W0 b% W: ?, l) E5 x& q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 P1 r: l( r9 ~$ b: M1 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 U" `% W: m# H$ q2 C$ {* e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 V3 B% }7 ]8 Y( WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. h+ O) F, {! l, `6 o. Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) v6 d% w+ f* WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 Z" `3 b* L' `. XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" A/ A. ^, w* ]. M6 v6 L3 {
}
( B& u0 u# S$ L3 s4 b5 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) v2 |3 e+ h8 [3 J |