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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* j1 |* H' P7 n- S5 Z# v0 Minput mcasp_ahclkx, k" N" k% g) B9 ~9 B8 G' e# B/ U
input mcasp_aclkx,$ d1 c l% |' B/ K. j8 y8 j
input axr0,3 X( Y1 L7 B+ f
; Y( M# R1 `6 E7 R/ ]0 W2 h
output mcasp_afsr,
/ w4 h& D1 N) r* j& E# koutput mcasp_ahclkr,1 O( l! o4 T: S
output mcasp_aclkr,1 O1 I. Y$ Q; T( e3 d; w! Z
output axr1, ^$ e+ J3 W, W+ d# C7 s W- X
assign mcasp_afsr = mcasp_afsx;
& e2 t& c- k' ?+ ~; t; k, {assign mcasp_aclkr = mcasp_aclkx;, j+ j5 b) Y4 ~$ \
assign mcasp_ahclkr = mcasp_ahclkx;
" c: B" n! s$ l& Q: [assign axr1 = axr0; ; ^) V5 ]& R' b9 m. q
1 n1 r" }3 L4 g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. d/ l5 U; V! g& J# R/ mstatic void McASPI2SConfigure(void)
& @* y0 L8 B0 P& W( j{7 j3 H! A! X! c1 U V$ U- [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 o* @. w! G* d w' M" a+ W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" Z) f3 l Z/ A: G: T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) } P& }* |; `. j. ?# ~6 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 V/ Z" s5 Q9 j3 {6 x# A* _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) L6 `. g6 `- J- H3 Q! TMCASP_RX_MODE_DMA);
( V& A+ a" N3 L+ G: u6 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ A# L% y' }$ ]6 W( f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 ~2 n1 d' ?0 M1 p' t5 Y" dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , d" L( V; r" K% J' z# H* p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 y# V+ d z5 B3 w. p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 L% [" ~' v9 s, q: |1 z; VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 j( g; E4 }7 K( P! t5 p2 m7 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: ^0 f; X$ I6 J& k, aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 M- T4 r( H4 @! @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( o$ \7 m% j+ u4 [
0x00, 0xFF); /* configure the clock for transmitter */
1 H0 |- h$ l6 g3 w8 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
R$ m% W% P' R- Q( L1 `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; w$ R) G9 d% d+ T, W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 t9 j7 g( T7 U, B( d7 ~. c0x00, 0xFF);! l- R" }' N- m1 @$ a6 ~2 U
m$ y/ E0 C5 \2 `3 ~5 _
/* Enable synchronization of RX and TX sections */ / f+ e% i0 `6 z/ ?, S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 X7 A4 s3 I# p2 V! b) tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 V. M7 u0 R- R7 c. f; Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 X0 D3 r7 [! j- D* h. F* E
** Set the serializers, Currently only one serializer is set as% g; R4 y1 B& x
** transmitter and one serializer as receiver.- z. ^8 z I8 b. ? r
*/
: f; M$ N% i/ R2 k) f4 y& m5 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& ^& N3 t8 \0 c' D, I* Z& JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 Y/ q3 E Y6 _+ h$ t
** Configure the McASP pins 6 y: l' B2 Z: k6 P* l$ k5 ]8 e
** Input - Frame Sync, Clock and Serializer Rx0 D9 m& q& {0 H5 X, W/ @- k
** Output - Serializer Tx is connected to the input of the codec " v0 Q1 |7 R* m6 `" b: \) V
*/
# F1 n& |( c1 K. V; y# Z! u4 L! @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& S3 A% G. k* c4 {6 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# Y5 t* ?* _( z+ ^8 R4 a; P; yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ P9 b( h3 r& O. l" E
| MCASP_PIN_ACLKX6 y! w- N g4 o$ }0 k
| MCASP_PIN_AHCLKX
# a5 k& `! E+ S( k; h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- k7 y2 ~7 ~# C6 F k0 XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, I Q0 S8 N1 z! \" u| MCASP_TX_CLKFAIL
. t/ ~ e3 E8 Y2 G3 M| MCASP_TX_SYNCERROR% k6 V1 m! T2 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: [6 g( T k$ c* g W2 Q ~7 I| MCASP_RX_CLKFAIL
. N$ W3 T; C. P. b4 I% Z; Q( Q| MCASP_RX_SYNCERROR
+ t& O* c' n7 d| MCASP_RX_OVERRUN);
$ M: ^ v* Z9 ?7 @* i- [6 L} static void I2SDataTxRxActivate(void)
- G0 x/ J* s- B2 {4 C& j) c Y* B{& ^2 o& g! ]/ n
/* Start the clocks */
3 a m1 y. B& c9 y+ o5 N; OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 D: }# n9 S( E/ m% G3 i& j0 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ x% o" C8 G6 ?' u; mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 e+ P% e7 r( w; t9 ~
EDMA3_TRIG_MODE_EVENT);$ I( F4 @% E' o& I' j( w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # _+ c$ Y7 c! j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* h9 e" r% J" Q* Q5 H8 m, rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ i/ }. x2 q, }8 k2 x4 t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% B3 G, y6 T: e5 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& \: s$ u" L7 }" L4 r x7 U/ [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 M* V% w2 u; ^( WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) V# R2 u' x- z} 0 D7 j- B2 U; j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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