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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ L, X' U/ ?7 v/ x5 {input mcasp_ahclkx,
+ O1 `# h/ Z5 G0 y4 dinput mcasp_aclkx,) d% Y/ y3 C5 O1 u" y: ]! ^( y
input axr0,
6 _9 t0 d5 y( f! F4 n
& U$ x5 k. T% B, E% Z9 i r+ I+ \output mcasp_afsr,7 S2 ^# I5 w. K# A1 D
output mcasp_ahclkr,
. T- X% n8 e; ooutput mcasp_aclkr,
* r0 C3 U; K8 j" |3 V1 A: [output axr1,& Z. G! T {# K! j: W; H" Z: q
assign mcasp_afsr = mcasp_afsx;
/ t f2 C. r5 G; I) sassign mcasp_aclkr = mcasp_aclkx;0 A+ p' k, T6 _6 E
assign mcasp_ahclkr = mcasp_ahclkx;
8 i6 v) S; T3 E8 q, rassign axr1 = axr0;
' f) M# j( K9 u; v. w2 c& x) h e1 y( O& E9 G, o2 T& P9 s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : j/ ?# N/ |/ }- c0 z( F
static void McASPI2SConfigure(void)
5 B6 u% ?9 O# c2 e& \* Y{" E# Q# P" u$ D5 A/ P: J L4 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- R8 n- Y8 F# V. E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ P* {; S- C i' H8 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" l2 c+ v" G6 W$ vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ \, m8 k: E/ D! b- S, n M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; _) q% f4 Q8 VMCASP_RX_MODE_DMA);
3 R" v) K& |) P, x4 b3 ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 N) k9 @2 i I9 S& Y+ N1 t9 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- m& {8 H1 m9 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " I: ]4 O; ~. W7 m5 x2 z5 W: D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ i) X7 }, Y: [9 R2 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; R4 j; G$ j' W4 d9 |! y$ M6 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( Q( y a# t( H+ S' Q2 k) J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% Y( r4 [ ~5 Q1 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( `; u3 H7 }$ q' W. v/ CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 H; c) J% ^2 G1 l; x6 H- U7 h
0x00, 0xFF); /* configure the clock for transmitter */: c. j% M4 b" D" t/ C. ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 a% |" `/ j' y2 x CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! @# L8 Z `2 L8 O! k aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 v7 {0 `: Q' f* @. a0x00, 0xFF);: y S y3 \7 J- E1 o, ]
' Z5 S x( q& B/* Enable synchronization of RX and TX sections */ 5 ?8 g n. s% d2 y9 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. t3 N5 E) F9 Y1 p3 D. P! EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ J. p8 z) ~/ P9 f6 O- \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! o4 h4 m$ l1 {. u# ?
** Set the serializers, Currently only one serializer is set as
' u( C/ u- f8 j$ r; S- t" g** transmitter and one serializer as receiver.
. `$ I j) l* c4 l3 P*/
- l: h |) h: ]' I# BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' o( ?% u* n/ R E9 M2 t" B9 {! J, YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# |, G3 d" v' p** Configure the McASP pins
- ~5 j- [+ w$ X** Input - Frame Sync, Clock and Serializer Rx" Y- v, ~6 j" z
** Output - Serializer Tx is connected to the input of the codec
7 y# ^* N) J5 v*/; @" r2 w; b5 u3 {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. G! H, y" u* K, q# _2 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) n' q' [4 i1 e. g0 J5 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" `, ~! Z( r# k| MCASP_PIN_ACLKX9 g8 j; B4 W5 L
| MCASP_PIN_AHCLKX" r8 r S3 ?% Y" {: J" u. g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) w0 G( A* x" k8 ~' }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
?: c% T8 ^% @& `* ] _| MCASP_TX_CLKFAIL
$ m/ [& ]+ \) A4 r$ j| MCASP_TX_SYNCERROR
* I _; O8 V( X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' E6 a0 S& c. A| MCASP_RX_CLKFAIL
3 ?* I/ B& c; a) |: t) e8 T( r) C| MCASP_RX_SYNCERROR
% p3 B" k) e" a n9 M( N| MCASP_RX_OVERRUN);9 M; ^3 t. V# P! c* s: H |
} static void I2SDataTxRxActivate(void)9 m$ P& Q& f. ^1 [$ p7 Z6 _
{
9 S* m# i2 c' o& W3 F/* Start the clocks */' g; W0 [) W5 c. i- a% [" [, U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 X# C; T/ t: p+ o1 s& M; I! X! D0 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; [2 ]4 |9 c, u5 t& WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; t9 x* a; f5 c; {8 v' i( G+ k: n9 t% `EDMA3_TRIG_MODE_EVENT);
3 O- M$ h$ f, B0 j9 e5 d& }4 e" UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 S* M. G7 m! \) V* \- H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 u7 Q: |+ \! y w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ ~5 t+ x r& r4 x# c) b0 v D! Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! d. C }4 X3 g( y! [0 z Z; n2 [0 A! ]2 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: n; z& U P- B# Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' X8 v! t' H0 w5 F2 y) G0 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) s1 R. Z- ^4 J7 _8 O, l) Y}
; _- e% L4 F4 q5 Y7 H3 s' B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( V) E* x2 ?" E/ R9 m& U' D
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