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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 |1 b8 I/ s$ `2 Y: z
input mcasp_ahclkx,
, z/ U( F$ G! K3 Q- k. Zinput mcasp_aclkx,
! O# Z) M- \* p! O& V# L9 Binput axr0," @ O1 E4 p% m3 W3 |4 A# B* [
* C M2 X, U& B% S! x. \
output mcasp_afsr,, r5 W9 J# \! N+ G: C% l4 ^
output mcasp_ahclkr,
7 \0 t" a: ~4 W# Koutput mcasp_aclkr,
7 y6 }: z& j+ T, W0 d) I( ?output axr1,
% ~& U) R7 q8 t! X, \5 P assign mcasp_afsr = mcasp_afsx;
J! T$ {9 y4 I9 `1 eassign mcasp_aclkr = mcasp_aclkx;
% P9 C( s5 |, W1 Zassign mcasp_ahclkr = mcasp_ahclkx;
- D( |* e' n, g0 _# x9 wassign axr1 = axr0;
5 f3 D# b7 g( T5 a% [
0 b6 D& f2 }% o- ]' y8 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' T" O% l( o! a9 Q2 p
static void McASPI2SConfigure(void)6 Q9 Z0 B! l* G/ k
{( _4 \: r% [( X) M6 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ?& E0 \8 ~* VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 c, h" U2 n% ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 p- ]" _, i% aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ x$ l Z/ a8 m# C$ S$ F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, Y8 `4 d% r$ \2 R5 c! s0 Q3 d3 o: `
MCASP_RX_MODE_DMA);
- o5 \6 [% a. A8 h* GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 n* [2 b5 p4 u6 B9 [% Z: g" J/ y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: W V9 v/ S8 Y; Q) S# oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 g7 S1 F, Q. w$ g2 q9 W/ }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 g4 k5 E/ c8 u( C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * n* q6 O0 u) m6 ~$ M: G/ { h% E% G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; {9 d: \; b$ ^1 i' U& u& e- I) ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& |! q. Y- p; b) f% n9 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 ?4 q1 _+ Q+ }& l h- _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 d' F5 S6 b, x# z5 P9 Q0 P+ r
0x00, 0xFF); /* configure the clock for transmitter */" I$ q6 r+ Q* V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& w) M Z9 n- e, o, `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . O" b9 `+ M, e5 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ f$ h5 R8 X4 k! ~% \* k
0x00, 0xFF);
& Y6 T- ~4 N0 U" i% q6 n( O( H( V
" A' ^% c" Q% B+ D/* Enable synchronization of RX and TX sections */
. g/ w) F- m3 l0 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* f4 \; q! u" P2 n7 \1 U4 V1 gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ i h9 s8 _+ x" ^1 E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) K. I% P5 @6 e6 E# _** Set the serializers, Currently only one serializer is set as
* x4 R V9 V8 X+ l3 q( \** transmitter and one serializer as receiver.8 z9 _$ P2 }6 h' Q5 y% }8 k
*/
' c P$ U0 q1 q6 ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, Y! d( @2 \/ e6 kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 ^9 l# n% i/ E6 C8 J# Q# X** Configure the McASP pins " M$ J; K) E M) A$ I' b* Z/ _8 |
** Input - Frame Sync, Clock and Serializer Rx, I& i7 F& \" A/ B9 Q' M
** Output - Serializer Tx is connected to the input of the codec ( p i( d. G' \- K
*/( r- `: j+ s0 N* w/ C- N2 j/ r ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 X& a% ]& l) X9 R* _7 U# N' l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# U- i& U3 O1 V9 v" k# k3 P$ J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, J H7 B. c) H I| MCASP_PIN_ACLKX% _& }& g# j8 u
| MCASP_PIN_AHCLKX
' w$ |( L' W0 [" ?% ~) S8 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' T% M, D/ Z6 e' b" {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / _4 U9 @ x( f1 [! A
| MCASP_TX_CLKFAIL
; `0 _2 h# H+ {* H" j- v| MCASP_TX_SYNCERROR& u' a0 y }( U; B, U# c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! m6 E; o0 _/ A5 h5 c2 \" L
| MCASP_RX_CLKFAIL8 t" \+ \/ v; b" L
| MCASP_RX_SYNCERROR , t" |) ^1 B9 U, d: L9 }" _! m! ?* s4 t
| MCASP_RX_OVERRUN);" B4 T& A$ ^2 Z4 D! u8 D
} static void I2SDataTxRxActivate(void)
/ Y/ L' d3 ?- z: |# V0 V5 b+ E8 I{* W" f7 V9 j$ }; d
/* Start the clocks */1 p# o8 q G$ ]- M' Y* I* D* c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' x& l D+ `2 v$ d' v% wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% W, s( M6 x! X7 D" E6 ^) _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) s2 x! p4 T9 S* @EDMA3_TRIG_MODE_EVENT);
" d( }8 b/ y b r& P2 S# f: XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- J4 L1 y5 Q: M9 d8 e5 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: f6 v% j: ]; B% m) L( ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* j$ ^3 o# f4 w+ dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! n* v# t! M$ J* d6 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: r! }7 i3 A8 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 b( _. E1 R2 N1 g, w pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 I- }# \# E1 M* t} 3 V R, |: v1 [3 h# t ^! e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 n9 ?6 z H3 c5 q/ U8 h# u
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