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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ ]+ N- n T5 K
input mcasp_ahclkx,
! M* o- V% y- S- O/ c. minput mcasp_aclkx,
4 S+ u. x! T3 d4 t- I" `9 \' [4 tinput axr0,) c. h' I: B; s$ K, ?( m( I
9 q: A z" e) Q# coutput mcasp_afsr,
7 N) U$ f" T6 R$ E* F: j8 d5 o) I$ ? m3 Routput mcasp_ahclkr, f* J; Y4 {1 ^) ~8 z& P' U) i" h
output mcasp_aclkr,
) O) e) S" T# j. Y7 ^output axr1,5 z4 _$ q& N7 I R7 D* ?
assign mcasp_afsr = mcasp_afsx;
, A) X6 S! |3 ?0 I+ \2 k" Passign mcasp_aclkr = mcasp_aclkx;( u* T. J* {' I! }
assign mcasp_ahclkr = mcasp_ahclkx;( J; W+ h# B5 S& S3 Y$ @
assign axr1 = axr0; ( z) E; ^$ [* y$ q4 l/ _
- S; r- u5 m3 b @! v# a: ~' \3 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 A5 p# D0 J9 Y7 u
static void McASPI2SConfigure(void)
- Z+ n* C: V4 s& M( K) T{
2 \8 X7 k5 ?7 d' O& p: {3 ?- G2 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 Y0 K" p2 W, K: y" X9 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 G; [4 Y# W2 q. {/ J9 Z) T" xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; i: L- _! `) b y) b* C" PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 ~& V# p" c6 d' E3 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 M8 c, D. B. w+ p. }MCASP_RX_MODE_DMA);
& ], H& {8 U6 ?: I" K/ JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Q# \! n4 q0 l6 z" b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 _; p/ G: f9 d1 ~7 h7 ^1 b( _ _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, p# i8 P+ {9 M& e% R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. j4 e5 J9 h) v+ Q0 X p" z9 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . ` q' ]+ l, ^! c0 G+ l- U8 z. k9 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 V) {9 r |8 H gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 r' {- Q7 S9 R w! pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 `; }6 H4 U0 u& `; B$ R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 @* {1 c4 {6 Y2 x4 E
0x00, 0xFF); /* configure the clock for transmitter */
8 x5 U5 f) z( j( Z8 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 \4 C( y3 V- O4 q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% ^9 e/ ~5 l# `1 F) C- A$ VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! V! ], v: m! H" d& u7 @0x00, 0xFF);
, a3 |' R6 T) X7 r" G3 t" A" K: N! J* [% q5 G( J
/* Enable synchronization of RX and TX sections */ # U# m: S! A& Y& x1 p/ W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* a/ _6 X* _8 m. d) Q3 Q% K C& U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; D* R( d" }- v6 Z2 RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 \! @8 R3 @' V5 p) j( G
** Set the serializers, Currently only one serializer is set as& U5 J) o9 G) u% H% a( U- q) Q' C
** transmitter and one serializer as receiver.1 e' L8 t5 l" }9 G3 o7 {
*/
7 X7 P( C' V0 \% F \5 P9 iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" z" k8 v7 q8 s' U2 S. |9 J# s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. W& S. Y i& q# G# M( t** Configure the McASP pins 8 R. `) ~; L( l: k' p W$ _8 g) h
** Input - Frame Sync, Clock and Serializer Rx' H/ F- d3 i/ I0 u4 ^
** Output - Serializer Tx is connected to the input of the codec
( X" ~( ?/ k: s# Q- i; v: R*/
+ B: R/ M( K5 Y F& ]2 m0 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. ]2 m' D* H# I: cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) S, L7 X( i2 ]* l; C& B5 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* |. J, U/ o: |( F" y: n# {| MCASP_PIN_ACLKX1 t4 y0 q8 h! J3 J5 F0 I
| MCASP_PIN_AHCLKX& A+ G! w. m; O8 m3 Q( }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
~% C+ t+ j/ }, p- u" }2 j: L" VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ j/ K5 R" X! i$ ]- l) I& i| MCASP_TX_CLKFAIL
) l" ~; C( O( ~4 _$ s" }$ P| MCASP_TX_SYNCERROR, o" H" E, p0 |- W0 l7 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 A I5 l+ t1 T' _| MCASP_RX_CLKFAIL& W& J" \- D3 f6 ~% J% }: S% i+ y' Y
| MCASP_RX_SYNCERROR
/ T. I8 A, V& `; i| MCASP_RX_OVERRUN);
$ G7 W6 w- l$ `$ P0 Y+ W# i) y} static void I2SDataTxRxActivate(void)# _+ R2 e1 X) u p+ O
{
, P, m( D2 F/ e9 ?4 y; e3 W/* Start the clocks */4 Q9 @8 \% C! I! u& G3 \7 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* n; W& H) m! |& P7 t+ ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) t) l8 l2 z& i6 b5 K$ ~1 J- r. CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, k6 c& N$ K- H
EDMA3_TRIG_MODE_EVENT);
9 u: a7 d9 o# CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : E2 ?# u, O" S0 \, d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! s+ c& I( r" Z/ F: y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 E8 g& |( u& \1 L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 H8 v5 y" g9 S w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 N$ a: B, d5 ?; ]3 w/ \! D/ C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 \4 ~) h7 F# q( \8 G2 Z1 t: `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' k' n- W# I: |; D} 7 j" u# `0 P" D v, I& } C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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