MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
. P5 f9 _* G; q; X$ ninput mcasp_ahclkx,
. a  g# q2 C( g% C7 uinput mcasp_aclkx,
input axr0,

1 Y  z5 A9 V% Q: routput mcasp_afsr,
output mcasp_ahclkr,
* I& q% t  g2 A" d+ houtput mcasp_aclkr,
output axr1,
' W9 O* |/ R6 A* J" }

assign mcasp_afsr = mcasp_afsx;
/ l* o& O7 g- U7 c5 ~( \8 H) Tassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

/ ~! A9 w9 m% c% n( f& T6 o

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
% S; P1 q+ b& I' y! Q  c& B* L{
' [9 |4 k& a4 ?' ]) f* kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 E) q5 B; j4 x1 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
) z: D! G, b* tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
  _5 g4 o  r6 _3 {3 {6 [0 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. O. W# ~$ s" K0 f# `' EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( `& h8 X( R9 R5 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
; A7 T3 E$ b$ u3 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 q, d0 a9 F& hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# @% B  j% }3 a- X/ yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 O: L# }- N9 D7 ^0x00, 0xFF);

/* configure the clock for transmitter */
9 D8 D5 Z+ \/ d3 [% b; TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
. {, p, _# a# O, O# g& R7 S/ C
/* Enable synchronization of RX and TX sections */
, C& n; o6 L1 |7 sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 @% r+ |# ~% P4 H4 B2 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, D1 B  B, }% T0 y+ r/ _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
8 A1 v6 J8 B( o2 j8 h) o** Set the serializers, Currently only one serializer is set as
% V* C  f3 ]+ A& i** transmitter and one serializer as receiver.
*/
" T! D) L' y) H$ w  LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 K6 @- s5 W) G+ GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
7 C8 }) H5 `$ J" [2 J: n** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
. n' _3 V' p4 }*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! E/ h# t& Z2 Z0 C8 y# d, VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
6 b/ i# }: j1 G7 d| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
' a# S4 a. t0 N' ?| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
( p* B/ b2 \; a3 X/ e' {1 I) H| MCASP_RX_OVERRUN);
7 z. P, W2 o& t}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
  F, _  P3 Z  `1 h/ m8 EEDMA3_TRIG_MODE_EVENT);
8 N7 n) f7 @' G0 N( b/ [; ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 i' w1 D; _9 {! |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 v" y9 l( x, c! i+ S- HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
/ {4 z  E/ r9 r. x# l& ]. dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
2 j- b) Q/ _  LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" f5 @. k/ E" A' O3 x8 S}

9 |7 m7 h" g7 ^

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

& F# b! r5 ]1 G; }5 F