|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ p% A! Z, w) ` W( R/ ]8 kinput mcasp_ahclkx, \3 | Y! Y& h& _
input mcasp_aclkx,0 @, i9 k5 s' v( q, b8 P
input axr0,
# {$ Q% P* h/ Y# J( h q' C4 _1 N% X% b6 C! M1 h ]9 q
output mcasp_afsr,5 j5 A& t& l) i$ h1 L: ]9 c
output mcasp_ahclkr,
9 |. g3 i" d6 e3 N" M" T! n5 Loutput mcasp_aclkr,
( m. @; K0 P3 L0 aoutput axr1,
* A1 V! y0 ~- x; } assign mcasp_afsr = mcasp_afsx;; |2 A3 S4 r# o
assign mcasp_aclkr = mcasp_aclkx;& F* c* q% |( A) }8 s9 h' A
assign mcasp_ahclkr = mcasp_ahclkx;
9 |: u. e( s, a& lassign axr1 = axr0; 6 }* z3 I9 [) S4 r5 g) l) q
( m/ E' }/ h2 F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, W7 p h# }4 D7 u8 @9 j" fstatic void McASPI2SConfigure(void)$ @1 q) ^: ~: t. A- a0 U% Z
{/ B- Y( k+ f8 W& _: d6 ~" J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ c$ C9 X9 x& f2 B3 Z* lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! k5 V5 p( d4 A8 W1 o `. L/ }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 y: p- N) T2 S1 u4 p) N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ r" w( ^2 z l1 Z9 ?- ?5 S$ zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& @2 \( b( v6 @; s( S6 J0 bMCASP_RX_MODE_DMA);# w7 n ?4 R' o/ f6 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 O+ q8 z# E9 w! s, a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: ]1 q2 p/ t- H* s' ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ g+ v- P+ f0 y# N1 v" JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ z; j. F8 l6 b2 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) n6 P+ D) K9 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) s( J9 t' D, {# z3 u& KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' A+ z, q8 Y1 ^9 C0 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & y: l( C/ _( y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ I* w8 C- V: \$ m A7 L5 X
0x00, 0xFF); /* configure the clock for transmitter */, J$ K0 b; n$ Z( j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 n. P* a2 w) X- Q0 O, NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 F( G* g2 p; C) U) e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; a* I' c3 @1 u3 ^8 D$ M+ G6 ~0x00, 0xFF);
: F. i- Q/ ]) R% R' E% b% |* g, x i% o; G! G+ ]7 M: G
/* Enable synchronization of RX and TX sections */ 8 ]; ?7 R5 @! w+ e% ^4 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 T+ ~+ j% L5 `. a- a0 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. M( t( B, L% [$ V, p7 I D1 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 l4 n: }: J4 G2 z** Set the serializers, Currently only one serializer is set as: W- O2 }! f/ u' I+ l
** transmitter and one serializer as receiver. x& U3 \: i# \. T
*/
3 ]) C% ]/ x; V2 U, ^* `( @. JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' t5 |3 l1 p, C1 u; A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 ]2 W9 t) T; h8 H; j( W** Configure the McASP pins
( @' _6 b& b" _# I** Input - Frame Sync, Clock and Serializer Rx* ]! T7 I" P0 F u# \" Z8 s
** Output - Serializer Tx is connected to the input of the codec % p2 f0 g1 E: W; p5 \5 ^
*// ?0 Y( N/ ~: ^* v, {7 ]. @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ w2 Y; q* C X) f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" W0 S0 {0 X3 X- @$ L1 x$ R4 [2 q4 @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: P$ ~6 L1 _6 r8 o: T" ~ M| MCASP_PIN_ACLKX
$ Y. |1 a K) i# c7 U8 i+ R| MCASP_PIN_AHCLKX4 e9 H D6 I5 G+ h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 S0 E% r; T1 i' W' }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 G* g# U' I. |4 r! T2 E| MCASP_TX_CLKFAIL
8 d0 E$ y5 t" n. S# ?| MCASP_TX_SYNCERROR
% P+ Y, ~. W& A$ m" x; z b4 P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' ]/ p' y9 {6 k0 w5 H| MCASP_RX_CLKFAIL
( N i+ L: S9 n( t6 r' R' S% S| MCASP_RX_SYNCERROR
* N2 B, P s1 c& O$ Y, W| MCASP_RX_OVERRUN);
( O+ ~ g0 L# w% B/ w5 _} static void I2SDataTxRxActivate(void)
$ ~( @+ K9 _1 j; o" w{
3 P6 G; ~( U4 {) S E) R/* Start the clocks */7 Y7 d5 w" ?! I1 {% {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 Q* V4 m; M# M. a$ m) U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 x2 B2 n+ ]7 y/ T" l8 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ l+ c8 n& ^9 I, ?0 J3 l6 J
EDMA3_TRIG_MODE_EVENT);8 J1 d8 t7 m1 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " R/ P3 m' ]1 r: g% [5 c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 Y3 {! b* H9 R6 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* m8 l: L7 s* m. [8 S O5 h* tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" D' X4 t4 I& Q9 `4 q% a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 J- t1 L6 ~" EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 @# l6 h6 E7 w' g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 u7 M0 H, t& y$ A* r}
5 R4 H: d, H: h6 J" F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ V, l v: K. m3 n5 k7 }, @9 A! q |