MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" }4 r( \" Q7 e( S9 V" d! h/ t: P2 finput mcasp_ahclkx,
& w) |! s/ X1 x# Oinput mcasp_aclkx,
3 s) g; [% ]8 f0 }- W" _# [input axr0,
0 `& ]2 w' ?; N) X% ?, D+ d: i8 W; @! p
" j8 W% `( h" Joutput mcasp_afsr,
9 F$ E% e1 e, J; Foutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

3 W) c* [  L! u0 p/ R( S

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
$ R; Z+ N  b3 Y: A: `{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, V' O7 j% ?4 X1 F) OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Z# T! d+ O6 @  l9 x& \. W. [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
5 l9 }7 y' l+ UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: m# R9 X9 s% v% z( \8 ^- EMCASP_RX_MODE_DMA);
4 V5 G# }' y7 c1 k+ B$ Z( c/ VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 `) }" G, Z" Y( f3 G6 x* kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" c4 ]  v# l2 |6 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 x# F8 V# b1 U  c/ _) wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
" X4 q# _0 p1 c/ X( XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 N3 X! M% p: I0 t5 g. W* G& JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ a8 S  J! q; L2 ^- X, T0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
+ n0 u( c6 h! {: c! Z- }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- F0 U% @! Z0 h  y& K& z( \* BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
8 H2 J" j/ Q4 {( S. f*/
) e  n* }" p- R4 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
6 s+ A, }! p3 n* \** Output - Serializer Tx is connected to the input of the codec
. I( b8 R: g5 E, o8 A*/
3 |' y. ~( m4 @8 M% L* NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) u. A+ O" B3 \& k0 |2 w- O+ p$ w% }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- z& e  f4 b" \. {+ k| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
. G% ^) V, Y8 z! v| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
& M  r! |4 Y/ N0 y# [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
: ]+ w. b& S  Z( a0 c% `. D/ y| MCASP_TX_SYNCERROR
* q2 b6 S* S# q5 i9 Y5 F| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
. z( }+ u% c6 H& ~| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
! c$ k7 S; E. N8 `& Q- t* X+ E+ F{
) t1 v8 }) ^% h/ C& z& m/* Start the clocks */
) ?; Y/ [. s. |, \- g$ p9 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: I5 l4 e8 p' U3 ?  YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
2 T! o+ Y% l9 E. A1 [$ y' _; aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 b* g! t2 ^7 w& P0 \2 y}

- d  n; H' y6 [6 U: _- y

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.