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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 q) [* w9 c: L1 T5 I/ [! x7 i
input mcasp_ahclkx,) Y5 c% f; N) i# ]' d& Y
input mcasp_aclkx,
5 i% V1 m5 X* v8 ?* P: {input axr0,
% i( @ Z9 o. r
- d! {( t0 V$ youtput mcasp_afsr,
* G4 ]! b0 N: Goutput mcasp_ahclkr,8 I! b/ m. K" V, T( [9 s4 y
output mcasp_aclkr,; j# l) f0 S- f0 l/ r
output axr1, h: A: V: W/ {; m' X
assign mcasp_afsr = mcasp_afsx;
! `" X" e5 H" k9 i! H$ E" Dassign mcasp_aclkr = mcasp_aclkx;
% K* e, B1 q% S( q0 ~3 b, tassign mcasp_ahclkr = mcasp_ahclkx;
R6 `' p% T- C' m3 f2 ?9 r' C* fassign axr1 = axr0; 2 U8 F b7 e7 e3 G. K# |
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 W- M: `4 M* Y! {$ l; s$ dstatic void McASPI2SConfigure(void)" E6 C W4 |; ^ _$ c6 f* O9 y
{
, Q. A3 U; |2 r) ~3 u0 l/ NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 A: i( s" ~) ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 V5 [' w* Q% u- Q, l- IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; H: L( `% @3 w$ ~2 u! d5 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( x" g" U" Q1 v4 N6 A' A& _; dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ]4 O! l* M' ?2 |MCASP_RX_MODE_DMA);3 N! s% Q& Z/ c$ E) C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 _6 \& y. T" e, \! Y) B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. E, M# _3 u6 V( J- U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + o% V4 @+ K& {7 U. R/ P. n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 P+ q1 b- Y- L0 u; _9 X; D, u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* h; V) s* X: w' O" ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( g' y" h g5 H) sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) D& o9 e, U, n- e4 a6 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % z& A5 F/ Z' V7 v: ]! k- m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- @+ D% i% Z/ r0x00, 0xFF); /* configure the clock for transmitter */
6 a: f7 `: x; i# I8 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 H; W1 S' F9 q2 W! CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 j$ \& j" p" g1 ^: L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 {1 n5 x" |9 Z( M$ M
0x00, 0xFF);
% h+ U" t n% h* R1 l9 K: J+ d9 p7 T( s5 `
/* Enable synchronization of RX and TX sections */
, s" g" b0 G* K, ]0 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! C. D! ?; p* }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- p, v; i0 G& Z) D# ~% TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! r6 N- N- X3 L) n** Set the serializers, Currently only one serializer is set as" ]) ]5 Y4 F% @. h, Q9 Y( ~
** transmitter and one serializer as receiver.% x9 ~3 O$ \) D0 B0 d
*/; F' B* g5 g- F0 V) M9 B' e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! h/ b2 ~5 {! x3 ?& xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) J* z* [' B) L; Q: `
** Configure the McASP pins
1 Q; I' p4 P) n$ F$ x9 `** Input - Frame Sync, Clock and Serializer Rx
! r+ m J+ `3 B/ M# z( g** Output - Serializer Tx is connected to the input of the codec 8 p. h T/ V" R4 M
*/# S0 x7 }, n3 l0 t; u& I6 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ M6 @/ c. X! a+ d7 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& d4 T8 M- ~5 d6 n% M0 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* u1 ]0 @, h: ~5 ]0 d/ z- d| MCASP_PIN_ACLKX
+ }/ B0 t ^" ?3 L# ~# G| MCASP_PIN_AHCLKX
0 b' }" Q0 s- C+ ]) {/ r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. w4 q( v6 x8 I" Q/ A7 p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) Y e$ S# I4 m6 f7 X. S
| MCASP_TX_CLKFAIL
% w- C3 }0 B* O& o4 s| MCASP_TX_SYNCERROR
. P2 i& C$ U9 z" ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 f& | o% i0 g) T7 d# W
| MCASP_RX_CLKFAIL; E) V! Y2 n4 R |
| MCASP_RX_SYNCERROR & \6 m- n3 l* T& q
| MCASP_RX_OVERRUN);
o; d8 t; O8 v7 K S! t$ w} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
2 d u, N. g3 T# \; XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: u* S: C$ A/ T: I. [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% d4 F, ^" O1 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 g2 ~; b8 a6 c: MEDMA3_TRIG_MODE_EVENT);
+ S: p8 D: h0 e# s: z# w+ p+ G4 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 k9 [0 `5 C* D2 p' e' REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( A& {8 U# J9 C" \6 y6 u* h% D0 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& c+ s3 x3 g2 q: |% ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 G% f y d& v9 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% g6 N+ W! G4 H, n& |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. i7 _+ P4 s! C8 O2 h$ HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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