MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
1 S; G' X0 Y# L2 O/ h& N2 b& kinput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
" a# X1 i/ z& r4 Boutput mcasp_aclkr,
, Q+ V8 u) F4 N- H0 N; y7 \9 m. m0 E' Boutput axr1,

assign mcasp_afsr = mcasp_afsx;
, |( Q- n+ _" z6 @4 J1 d# Wassign mcasp_aclkr = mcasp_aclkx;
% v0 E! M. O9 ~& Q6 aassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

( `6 \- Z1 p( q$ V: C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
2 K" ]* t$ E6 A0 _( d  j" B5 ~{
; ?6 h9 @) y9 a1 p* z8 p0 c. mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- f  {) I+ R9 l* lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
% j7 x/ n: f0 j* `  Y: CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Y2 [5 M7 b( [' T9 WMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( a2 t. O1 F% TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- ]' t% `$ C8 a: J: G% ~. FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ o. s# W. e. R5 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- o4 J7 q* ?9 x/ r+ l5 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ j2 h1 e4 l/ Q9 w5 i" j/ B4 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 B+ v- j7 N6 I  b8 V& G3 j0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% W. @, p; t, d6 |- L3 K" s, RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 S7 }! i/ l0 ]2 j4 l. }0x00, 0xFF);

4 V# A+ s( {' r. ]9 ~/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: S+ S" Y+ A4 _7 ~( |. o( lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 x7 D, D' N' E* rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
* N7 W; _& S! q" [: V** transmitter and one serializer as receiver.
*/
* B( p% l9 ?- z( T$ M, L% EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 [! p8 P' @% `" f' UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
3 e; s# Q& q9 s/ [** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 U. h+ Y2 l2 w+ s9 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
& k" |4 e/ P$ O6 R& G; ^" {| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) K* W  O6 ~, U2 `4 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 p, t) {; l' ^# E) X! I| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
, S! x( h5 m/ D) N  d# q| MCASP_RX_SYNCERROR
! R+ }) x; p2 I; ^5 F| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
- K4 U+ U; \% G, T{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
8 t8 y& T! B  x# W. oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) Q- \+ a6 N' ?0 T8 p% d' e! hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: j3 C& M2 Q5 K1 ]( ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ t- o2 J( p1 z/ e- @# K- Q% OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 x, a" D9 m8 N# n+ O* }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

& Y# }$ t0 H& j( I1 y- i4 @, j