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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 e2 j4 l9 ?4 @8 f( i9 m. U! x( o
input mcasp_ahclkx,$ r" Q: F) W i, h% {0 r& ?% I
input mcasp_aclkx,0 u6 d) F$ n! b. w8 U( A- }
input axr0,) D: y0 y0 H( j( g- M" z3 R
R4 B& A# k! n/ w+ Youtput mcasp_afsr,! t3 Q0 N% b* X
output mcasp_ahclkr,
" |0 c/ C* u% ?" b' ]4 H$ ~output mcasp_aclkr,7 b& B- c1 ^6 t4 I- n3 V
output axr1,7 I3 g% L- D( q
assign mcasp_afsr = mcasp_afsx;9 o' o! A3 ?9 K4 e
assign mcasp_aclkr = mcasp_aclkx;
4 `$ V$ j7 P4 k9 ~assign mcasp_ahclkr = mcasp_ahclkx;4 T C: G- I4 J" u3 o. ?6 P
assign axr1 = axr0;
# @6 f' ?& W" o5 U W B
% G' j' q" t& g' ?6 V$ h% q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 n. p2 ~& ]9 F3 b+ [% ^- Cstatic void McASPI2SConfigure(void)
( Y6 W5 B6 k: [1 D{
/ t: i( z! m3 f, C2 x+ T2 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* }5 S/ |% `9 H4 W% a5 Z9 P: XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// z- F5 j' d4 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ^# K- z) A2 W& a0 }- Z/ ~- M) q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; J7 {- | ?# Z% eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, D1 G: k5 k0 k" \
MCASP_RX_MODE_DMA);
* }! K# h9 N" E6 \* g$ E% s7 k" ^# KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& h7 R4 ?; X0 o1 [* a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 J9 J# `- h8 e: B1 M" a4 z+ IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 N" P8 q6 G/ y* j) b& u' w. P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 p& l4 k2 U+ c4 Q2 N, `/ y/ _! }, `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : x/ v) E! b! L; ?/ e R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' z& T6 i, a5 A3 ]" o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) C+ |4 B5 O9 x W7 |& EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 @ O# F% E% S; k8 }- i: T8 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 J3 ^5 J% Y- Q* H, ?& K! X( ?8 [0x00, 0xFF); /* configure the clock for transmitter */
% M3 k% x+ @+ l6 X4 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ r4 `8 V6 p. m qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 B6 j4 L' ~9 e( t% w3 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ c$ S6 g3 ]8 c0x00, 0xFF);
0 i! ?6 r( h& W3 b4 P/ A
5 B% W, u q3 K/* Enable synchronization of RX and TX sections */ % ?% G/ e, R- e U0 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 `( P- O2 s* S- @2 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' h' d0 C9 _7 }6 Q/ [7 A2 R1 U( m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( C- D& n, V) T; @3 W/ x/ A
** Set the serializers, Currently only one serializer is set as
2 _, ^" ?' p: w! s/ _% x8 W** transmitter and one serializer as receiver.; y$ O1 {' N# Z ~; o' V
*/
! q! S; F! n6 N: o( b! @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ s# ^) f& s. \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' H# _/ S, h( E; Q! A; q** Configure the McASP pins
! x. t# M5 v9 z. D1 q** Input - Frame Sync, Clock and Serializer Rx* u) S: h1 q$ `& [
** Output - Serializer Tx is connected to the input of the codec
. d" @. _1 s! U/ H: Y# d0 ^8 v*/! K% y3 X# [% n' [+ m# w9 p; G1 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 p7 w5 L8 y2 p0 u* M9 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) O0 Y. T4 Q8 ^0 f% q# J. D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- Q7 z) c: \$ k4 Q6 V
| MCASP_PIN_ACLKX
3 x/ y! U* D# s| MCASP_PIN_AHCLKX* h4 { Q/ p9 P* W" W0 Q. o" u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// w" h, l; c l/ Q" \4 V6 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 t% U& b" R, e' C; V
| MCASP_TX_CLKFAIL ' Q9 F* _6 a) N; m2 c
| MCASP_TX_SYNCERROR* T" q' s1 f0 L v7 e9 t( J/ t% i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' E' y( G; g- G2 z
| MCASP_RX_CLKFAIL
- g; E: ~* ~8 S# @; x: i) O| MCASP_RX_SYNCERROR . E* t# F) N3 V) T4 [
| MCASP_RX_OVERRUN);7 p+ t4 ^. d- R& ^( r+ J
} static void I2SDataTxRxActivate(void)5 |8 }# Q6 ~' w' k4 v6 M* S
{" x$ Q& ~ ^% j. }
/* Start the clocks */$ P6 _% g% \0 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ V2 a( [- m5 F& M9 q! H) K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// s2 u. X: d& y6 A+ e& L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 W" g2 Z% M: l6 pEDMA3_TRIG_MODE_EVENT);
2 F8 o8 S* s$ g8 G1 g$ P4 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% o5 m7 O, X7 y# Z NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, ^0 G8 R+ d6 `6 P" j1 L: j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" L. M" [6 u: n+ ]% M8 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 G0 T! V! u& w# X0 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 E5 _- e7 b. z% BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ c5 Q- e6 [1 {1 e b$ V9 s' mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 R9 p0 J" {7 \
} : H6 [: ]& ]5 H9 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. I# d1 m5 w* m1 M; @
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