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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 `" W7 Z% s' w. ~
input mcasp_ahclkx,1 `; n* S: O9 ]( N' a( {
input mcasp_aclkx,) K' x% Y3 D9 e' H- u3 S1 \2 c: q
input axr0,
8 Z! M3 ~5 X+ T0 _9 I3 S
O9 ]% w* Q5 Noutput mcasp_afsr,
9 |' i: ?9 i, f' Koutput mcasp_ahclkr,
: u" w$ n( g* b/ G$ V0 zoutput mcasp_aclkr,
: x2 [# {& C1 f; ~output axr1,
4 \ R5 F4 j- ] assign mcasp_afsr = mcasp_afsx;" ^: B; ?' g9 o, ?% w$ R/ w$ k: U! o. G
assign mcasp_aclkr = mcasp_aclkx;
# J. l% W& P bassign mcasp_ahclkr = mcasp_ahclkx;# B4 b$ Z6 F, s
assign axr1 = axr0; 1 f% B2 B8 L9 M( I2 D
- X; f k% Z8 o$ U5 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : Y- F1 W( u C! V
static void McASPI2SConfigure(void)( b4 p7 p8 h, c' p4 m) H& S
{8 |4 u/ w! B& m( D3 L% ?! |$ F
McASPRxReset(SOC_MCASP_0_CTRL_REGS); G8 G: e6 g* u& @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 J/ \4 L! M% LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ }2 [9 r- U" n, G8 [# r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 M. w4 B1 e$ o# S. ]$ E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% s: u) O7 H5 H/ D+ K, B
MCASP_RX_MODE_DMA);7 S; z3 W6 o# }9 [! L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 b4 l7 P4 r, ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! o0 U" q2 G j4 {& jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ g8 m( i! j4 t# X# t5 Z# uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 h6 E5 S" H2 O1 s4 F) j! v( mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( d5 p P/ O; _$ x$ `, m- L' h) X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 E6 M& j$ H, I8 n+ h: f! k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" _9 H) L1 u* q2 X+ q. d! W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- }) @5 A0 E2 W6 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* H: H# H, T* m0x00, 0xFF); /* configure the clock for transmitter */ I1 p7 T$ R$ W0 ?( t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 p+ I/ F& Q1 Z) T" e1 Q& s! p; ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' F+ e* ]1 ^9 [0 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ H6 i! L, u+ @% D$ C+ d0x00, 0xFF);
0 d3 F* i F+ u& L! r
+ E7 l2 d' a2 V% t/* Enable synchronization of RX and TX sections */ 0 G/ \) I! e# k2 x7 N6 J6 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: f- n n) s$ C; e8 k/ l+ N6 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
n) J# X% v K4 E8 ^5 h+ n9 mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ z% ?2 Y! c" o e** Set the serializers, Currently only one serializer is set as
9 A; u, X. [3 u- r/ J, Y q4 S** transmitter and one serializer as receiver.
' Z8 L# [- s$ o. T" ]*// `4 W/ c) `. s% M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ R" N& D! o' M Y6 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 Z/ p- z R! o** Configure the McASP pins 1 a+ I1 R' l% H; U: K1 y5 n
** Input - Frame Sync, Clock and Serializer Rx0 J/ s, J2 @) z" |: L7 M8 c
** Output - Serializer Tx is connected to the input of the codec 3 |" G0 t8 F6 {( [0 o
*/
8 M, P8 L7 ?8 W# d8 l UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. l' w L( f& @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. R( m4 N$ T% F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: a. Z# P" M# M, U. o
| MCASP_PIN_ACLKX
0 z- }$ R: C1 d* o| MCASP_PIN_AHCLKX
) E3 G& r& f9 e' b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 N9 [) h8 u- m2 c6 l! M' z6 K8 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) q) n9 R$ u6 M+ h1 _
| MCASP_TX_CLKFAIL : {# x+ L& c/ _# U
| MCASP_TX_SYNCERROR
& Z/ g* {! ~5 Z, {, m! w& k5 E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% M* e$ t8 b! G& P; z| MCASP_RX_CLKFAIL( W0 B2 F+ l8 U0 |7 L
| MCASP_RX_SYNCERROR ! x6 P+ o* ~; k, `/ e0 _) d7 }" r
| MCASP_RX_OVERRUN);
: i+ f% Z6 n& K- t& [6 L} static void I2SDataTxRxActivate(void)
# q' M9 _( u+ ^{
8 d2 i% K+ g7 g* Y/ i/* Start the clocks */. \6 e: O# E* r$ Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* o. M L2 \) x3 g1 T. b& v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; T; k1 h* G5 ?: M$ ?* `& G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. T& d- U: I. o/ k Z
EDMA3_TRIG_MODE_EVENT);
2 _, A1 K4 ?3 X, \8 c6 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 ^4 _ f' M0 r0 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' I6 ~, B/ o, A& i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( E( J9 d- W# y2 u, dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" t+ J1 c1 o* p/ ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, |, E) Z# z- i: B2 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% v* `) Y# g" JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, E: O7 C5 f$ a# `8 l2 \' M}
. ^; u z; \; Z& ~$ j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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