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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ |& B, h7 M: a
input mcasp_ahclkx,% n0 Q1 ^/ h5 N5 l: S
input mcasp_aclkx,
$ ~3 T0 [0 A' S y7 k6 Minput axr0,+ s. R& G" l: B# y; O
0 g, X( V8 }3 ]
output mcasp_afsr,
. r$ r& i5 q) Y8 U) C! {output mcasp_ahclkr,$ b) X4 Y$ i5 Z! r9 _! `
output mcasp_aclkr,
) ?$ }" J2 x" V. h# ]8 o+ V+ B0 }output axr1,
9 I1 Y6 b% t9 L1 Z7 r assign mcasp_afsr = mcasp_afsx;
0 N, e, {! I0 j. P/ oassign mcasp_aclkr = mcasp_aclkx;; c% r: R, D6 K
assign mcasp_ahclkr = mcasp_ahclkx;
1 n/ V! @2 I2 R% V! I, `assign axr1 = axr0;
4 r8 b& c0 N+ S5 e# t4 ]* l2 K, f
$ p6 B: j' ~0 c1 S; i- J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 p5 ]/ m- Z$ F9 C* p: ustatic void McASPI2SConfigure(void)
% a; C( W0 k& ?: b3 X1 R{
9 `) Q# ?6 ^1 h$ sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! I8 {. o0 w8 I# T1 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 K8 w$ O2 S" Y/ h1 w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ _5 m! r6 r$ H4 y! ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' e* \# |- L) s; h+ V i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% f8 ^$ M' P! T) s) LMCASP_RX_MODE_DMA);6 @9 |1 ?/ ^# n* j# E; q1 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' J. s# k8 H0 m1 V6 f h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. R, ]1 d. }7 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , Y9 j- \( d( o' k2 x' V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
N# X9 g: S. Y% w- }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # t! P6 o+ Y. i4 B3 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ N/ `0 ?+ Z0 F, T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ x2 N( o( l0 L. U, A6 B0 AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 G" ]. B8 J" N, A; Y PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ V; N7 k0 L9 K9 `. F8 t
0x00, 0xFF); /* configure the clock for transmitter */8 e1 F0 T# q# ]) O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: u5 M# J, b- dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) O$ x+ u: t# }! mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ S9 T5 O1 F% C: |8 f
0x00, 0xFF);& S) f: c/ ]" D- I. _( `" _/ R
1 T/ X+ X9 t% ]2 Z3 b( q/* Enable synchronization of RX and TX sections */
( W3 d+ F) n) i6 W7 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& O. S1 n4 Y6 SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' O8 i/ i. f+ |& u# K h+ p% S fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. u$ e J" w9 o o+ }, ]& I
** Set the serializers, Currently only one serializer is set as
+ @7 @8 D, p. l O K- c: A( R8 a** transmitter and one serializer as receiver.1 S4 N9 Z: C3 x
*/
$ o5 {2 r) P0 ?5 U( Z* UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 M# l$ B. I) G9 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 v( I+ j: X% }- X+ p* |+ b** Configure the McASP pins
1 A) \9 l6 Y! l! p6 C** Input - Frame Sync, Clock and Serializer Rx
5 H: \/ Z# r2 X+ T** Output - Serializer Tx is connected to the input of the codec 8 H4 q' A% }) ]% P# n/ ?4 J( _
*/
' n1 ^0 e4 z) X" I" v. i/ ~ d7 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, a5 d, X# X; ~: C7 c, }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 r! Q' V% x- p* j5 u' W0 i: EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 {! R1 l1 M) x: N" l0 R| MCASP_PIN_ACLKX! v% a5 n2 q2 h7 h/ k9 a
| MCASP_PIN_AHCLKX
; u. ~3 S" v- M# o$ Y6 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ [. x0 {' O# x8 f% A3 |; `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 C/ l6 Q! n4 v$ l3 V% |
| MCASP_TX_CLKFAIL
4 p9 ?& H1 E, J; \| MCASP_TX_SYNCERROR
% y* [$ @& i. D* u4 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ Y P! H# E' R9 f3 ?3 O6 `8 S# ?| MCASP_RX_CLKFAIL5 g& a, a2 E( [& x6 z* e2 m; v
| MCASP_RX_SYNCERROR
7 F; U5 p4 f% {: F; q; W| MCASP_RX_OVERRUN);
, G* P# E, e1 u6 K4 { W} static void I2SDataTxRxActivate(void)
9 X6 {; w' @0 Q! m{
! N' @* R6 D7 c+ I2 I5 u/* Start the clocks */
+ M3 d. S6 [/ \ }% ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; |2 T; m0 p: A, X3 yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) Z T$ ?2 M* @' o) k* p8 L8 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, `% o) W# H% xEDMA3_TRIG_MODE_EVENT);+ \* C( {( A3 x4 ~# u+ B7 O, [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, q# _9 h# x* P4 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* g) `) m( [2 V. y/ \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, j+ v0 ^6 g+ w0 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ^* @* B: |) pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* f. Y8 K. o5 R$ K8 \8 d; l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ N6 R, l6 F& S( a/ H4 z7 i- m$ j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 B' R8 i: G: [
}
4 i$ X2 h, b# E4 X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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