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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, H$ Y" j* i3 O
input mcasp_ahclkx,0 B6 M- l8 @% J5 D3 w: z4 r
input mcasp_aclkx,, Z6 X$ k7 R' X4 c1 ]
input axr0,) ]; P# x+ Z0 [8 D8 o5 z5 s) E
& o5 j1 Z/ q9 ]output mcasp_afsr,0 }' D' \4 S) D; }
output mcasp_ahclkr,
6 ]5 Q* K9 K w) Ioutput mcasp_aclkr,( m5 h! j) p3 n* k6 I3 Y/ ^
output axr1,
* b0 ^$ x' e6 ^: {; _ assign mcasp_afsr = mcasp_afsx;% a( Q H/ v3 @" V3 B
assign mcasp_aclkr = mcasp_aclkx;0 }% h- r# ]2 T# m1 T! k P& n6 y
assign mcasp_ahclkr = mcasp_ahclkx;
8 i4 J) Q; L- S. H& }assign axr1 = axr0;
: [# n2 x& y3 B2 z% r' Q
0 A1 Y, f3 R& t6 n4 C2 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - s7 a, [- o; I
static void McASPI2SConfigure(void)
, o4 g9 Y8 v4 f# Z) z{
3 }7 L- ~3 n# I& }- f, f6 R( K" gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% ~ }% J8 d; e3 ]4 V5 v9 Y9 q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* w. l* K9 C6 p* {! A( aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% J- w4 U' b) r" H, zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 q: ~: z$ [+ S. YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: P. N0 A: u7 ^% @
MCASP_RX_MODE_DMA);
: U6 v$ E% u% ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 _ I/ Q1 x) k1 @/ s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. ?( R% I* T: L3 o5 j( ~- [8 P' V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 C% Q3 Y4 E9 {$ v4 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: u! Z: d$ C! }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . `6 F9 m: y! F+ b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 P; g5 q& K! TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 ?3 ~" Y) {8 ^3 x; n. rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# g" Q$ P) o2 Z7 J* \" AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# s" S+ i3 o' U
0x00, 0xFF); /* configure the clock for transmitter */5 a! E4 i+ v! ^ n( L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) V4 z( S( t- {# qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , w! ]. u1 f( i& u8 G, O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 o& `! b& t- t9 c7 h8 _# }; T. p. N
0x00, 0xFF);1 }3 ^6 C7 t7 [4 N* c
2 y0 G1 I2 [% K" b; z t# [/* Enable synchronization of RX and TX sections */ : m* m$ Y6 e" L* k8 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" n/ K' c/ X! r+ D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); d2 X9 O. q) R% o) V- e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& F1 A: ~ P3 N( M5 C
** Set the serializers, Currently only one serializer is set as
! Q- Q( T" o6 I9 t** transmitter and one serializer as receiver.' _/ f1 q! k$ |( @' n
*/2 s$ ]6 O( m+ F' ?/ R I9 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( w' m- \7 F% v8 {6 K. k! hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 a% f! K/ g1 ^, T- L
** Configure the McASP pins
/ U+ X1 j" g# |" k** Input - Frame Sync, Clock and Serializer Rx
; [# F+ g0 K! E) j4 M. ~** Output - Serializer Tx is connected to the input of the codec ( G% U. q8 @& d# m
*/
( L' V9 L& z* K1 a5 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; T' s) U5 D% y( {" dMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! K" f+ s" j# @: F, ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 Y+ F' t0 l: R& P: Z. y7 W
| MCASP_PIN_ACLKX
% \; Y( ~" K, o: h# s6 ~$ J| MCASP_PIN_AHCLKX
. n: O, T# I$ {) W3 k4 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 C9 n t6 W' a6 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ L* R) _1 q( V6 [- }| MCASP_TX_CLKFAIL 5 j+ W' I) N4 l# Z" \+ l5 l
| MCASP_TX_SYNCERROR* p& i" E. ]% c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. y: {; h- Y/ D5 b/ L| MCASP_RX_CLKFAIL
0 s S* z" ]3 ?9 R9 P! W+ F5 ]" _3 j| MCASP_RX_SYNCERROR
1 s4 B B! [# v0 D5 k* C0 f% N' s| MCASP_RX_OVERRUN);* U5 p& h* t0 r/ y7 @
} static void I2SDataTxRxActivate(void)& _: Q2 x" B& M3 T& d
{
8 e: t4 @. c3 p* M/ _/* Start the clocks */' @% P1 m$ t0 u3 e+ _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) o: O) i* O# V1 i8 t. ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 m$ q! b; b1 i1 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 J/ ]# Z% x6 cEDMA3_TRIG_MODE_EVENT);
. Z$ P$ C+ C% B) @/ r+ M4 A# TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / F( M( z2 p' r' }! ?; c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 k5 m: s/ `' P+ ~# M9 i$ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' i6 o3 x2 `6 O- f; \# b' D) s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! ]; G( m9 P! H& Y: m! x$ u& ?8 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 [! ^0 D: w, \2 p( CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! B8 v) M' P5 P% i- dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- @3 t) H& ~" @
}
& b# y0 S7 [$ T) ~* q e1 T! [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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