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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, n) V* g/ m M8 V
input mcasp_ahclkx,9 j1 J$ A' W. D; |' y. [( h2 ?5 w; S
input mcasp_aclkx,# w( Z' ?+ k+ S
input axr0,
6 y2 A9 |3 n8 Q! g9 G9 n
5 A. p0 c( m6 M. s% q- k9 K2 Goutput mcasp_afsr,+ s) L: z+ F/ A7 y6 N! ^; e* b
output mcasp_ahclkr,3 N3 S7 \5 G! H8 R
output mcasp_aclkr,6 W3 p4 L# \# L# s4 A8 }$ q4 b
output axr1,
$ M d1 z N* A; Z. u9 \! ^ assign mcasp_afsr = mcasp_afsx;. K+ M/ Q. o# H$ w, Q3 L
assign mcasp_aclkr = mcasp_aclkx;6 G+ L' c4 V5 X: O* l- |
assign mcasp_ahclkr = mcasp_ahclkx;
# H) ?. ~+ C' Y& M I$ kassign axr1 = axr0;
3 l& ]+ C2 ~% t1 J
& h6 g: x! T3 ~* H0 u. [" N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( Y! i! u- h; ?
static void McASPI2SConfigure(void)" Z7 x9 V0 Y$ o. F, o5 x
{2 L y: i8 N# ]( U( Y3 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 o4 P: k& T4 e9 @+ S; } ]% k- h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& a! i1 P5 b3 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ Z- c. |- P( ]& `. CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ K: H* N# E9 o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
p) O' _9 u5 ]: V1 NMCASP_RX_MODE_DMA);
1 N+ { l3 a7 x9 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ w, Z. H B! V' |" w" e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 W- }7 e8 x! P/ x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 ~. y* r5 L( M0 E. w6 T% W3 E$ }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 {9 k4 [* X0 v6 [9 F9 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * J& i) |& ?) S: Z% [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: e6 ]1 P9 ` l! |+ N1 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! G% x2 b6 A0 C" d& OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 U# [! F8 z* _7 }8 t) w' oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& _* x9 v! N9 I5 _' J0x00, 0xFF); /* configure the clock for transmitter */# p$ w+ l' M+ s, l) a$ h, p4 W0 H" r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ l& B; A5 l" F- z7 p# V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 v% f' y7 @, {& M4 C5 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* V& v3 C3 f& O5 b0x00, 0xFF);, H4 d P6 ]7 E
+ c' X) X6 R4 w. _% Q, z5 z
/* Enable synchronization of RX and TX sections */ # e0 ]4 a: C' c! B) f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 B5 l0 ^# s! EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% H L @5 S- O1 {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ d$ `; s! L( V! a0 J1 A: s
** Set the serializers, Currently only one serializer is set as; D0 z8 \. R( U4 t4 X t
** transmitter and one serializer as receiver.
3 v, t0 N/ N' s: E" C2 j*/5 L! `& M: n7 Z2 X( Q$ u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* m( V! a) _+ o/ I5 p5 C% l Y5 F4 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 M0 \* }8 V: ^8 e% W, H** Configure the McASP pins # Y% d8 I; g+ K3 D2 F( ]
** Input - Frame Sync, Clock and Serializer Rx
, G' K/ h- q- p2 O8 H, t** Output - Serializer Tx is connected to the input of the codec 8 w6 B# k5 z5 l
*/4 ~9 l% U( R4 x* [% R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 [* i g V7 o8 {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" _5 o. z' D& H, m* a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ N; a2 Z/ U8 i, J! b2 j
| MCASP_PIN_ACLKX
0 S4 N6 P x4 E1 u6 A| MCASP_PIN_AHCLKX6 A* C1 m* H* X$ c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 L. I O# l- j! j3 r# u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + }4 c. l( A( B0 y/ u, b2 G
| MCASP_TX_CLKFAIL 7 i4 u2 o$ W9 B9 H6 z6 Q
| MCASP_TX_SYNCERROR
4 ?. a! T/ s: s5 }2 h/ o& O* K( q8 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, x, l9 ]0 T, h( p! I| MCASP_RX_CLKFAIL. n6 D( |5 E3 o, O/ I
| MCASP_RX_SYNCERROR % s! D& a' ]. t
| MCASP_RX_OVERRUN);5 \! T C; S( {( n
} static void I2SDataTxRxActivate(void)" y% g" q2 B; `# s: ]0 q" E
{
, j7 }# X" e2 ]4 S. j! W/* Start the clocks */
0 C: W; R2 i. O; LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 q2 ^% a4 ~8 }- Q6 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 n! e2 o9 Z. y% e, R8 j/ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 o: h7 v9 D$ j$ P- X
EDMA3_TRIG_MODE_EVENT);. p+ e' j. H R2 y2 J. p2 O$ r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! r7 ?2 t/ b: [1 N9 }. O {+ @+ G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ W2 X w; q/ z: y# e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 H0 _% n+ B2 b! H) xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# ]4 [1 w' M1 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 B/ |- `& j: V5 C$ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# w* |$ T: ?% r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 z" d: [( l& g- r} 9 \# P; n# O5 z$ g" O- s$ _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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