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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( k. `, X# n( K: binput mcasp_ahclkx,
, x9 l ]) L- A q7 einput mcasp_aclkx,
" V0 I9 S/ Y9 J X+ G; ~! {input axr0,
# p7 T0 j# E+ V, D& i" |) c2 ~
) H: ~# v; w) |4 }, k* Coutput mcasp_afsr,# o, j, ?0 r! \% z
output mcasp_ahclkr, S" m8 T5 E3 A) _! P
output mcasp_aclkr,
7 f8 u) Y% F! l5 l4 r; i2 }, ooutput axr1,
$ T5 d8 E& [4 O/ p$ Z7 O, O assign mcasp_afsr = mcasp_afsx;
" G# H+ m V: ~assign mcasp_aclkr = mcasp_aclkx;
$ \! [! G8 L9 oassign mcasp_ahclkr = mcasp_ahclkx;4 C# w. d5 ?, T* [6 `
assign axr1 = axr0; / d0 m4 ~5 { l1 l6 ^9 x
9 l- N2 c% i) E0 r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" @/ _" e* v3 Estatic void McASPI2SConfigure(void)
' l/ s4 l" U% H E{
9 T3 C: D0 S7 b: M: ]% T. }# d' @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, j& T. K& `% d& y- fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 `' l3 Z5 ~/ c7 I/ K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 ?4 Z n$ j) q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* {0 `. K% s; ? `- x7 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 k! M$ ~5 q2 v6 z% N
MCASP_RX_MODE_DMA);0 u0 a, n# Q" D; G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) w" @6 e, x. ^6 z( m/ O8 i5 F9 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- P U, Q' h; I V) b% @4 ]4 X0 R- x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; n1 {9 h' M X# l5 v3 `% h$ O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" q v, t- I; D8 L; ]6 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! a4 B+ m a' F0 @8 \2 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 G# W6 m$ P; RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' |. |) q& B- D$ h" V0 G5 ?1 Q8 k9 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ A9 L' }/ Z( e0 {$ }2 @/ @ ]4 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 \; g, |% O! C% D0x00, 0xFF); /* configure the clock for transmitter */" s5 \" v! b2 m* L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( c" [5 y3 ~7 _+ s' _: mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& W7 g; ]4 m4 \0 W, `$ r( ]6 h# uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' e1 @& |: R& N. ^1 W# v# P& V0x00, 0xFF);6 ]5 v: P0 c+ i+ |* Q, R2 u+ e
- P8 r. n; \/ |, j! L0 B/* Enable synchronization of RX and TX sections */
' ?; j6 S0 k8 d1 g+ \% X" H% hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! o# I& U# x, b! `' m2 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 _8 j5 L( g4 B# V( e0 W* d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 U: e+ m8 \. E, ^8 Z& o# N% }** Set the serializers, Currently only one serializer is set as
/ y+ }1 `8 U+ k. R0 d; J4 g** transmitter and one serializer as receiver.
0 k: |0 u* _! Z2 \$ H*/
$ [" `$ R6 @8 p9 g9 k, MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: p1 s% ^. g& j5 U' ]/ |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' w: d" G3 e3 u) E, E' r+ {** Configure the McASP pins
& G# k) p0 F4 T, _" G' s- \** Input - Frame Sync, Clock and Serializer Rx0 i( S- ]# g; b
** Output - Serializer Tx is connected to the input of the codec - A9 \) X' l/ ~6 D
*/' g' ?; }3 `6 w# P: s; o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 v1 ~6 W# ^3 S2 \9 mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 s* Q. n" H0 {* V" O$ FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. t' k+ m. U4 h" j$ d: I8 t
| MCASP_PIN_ACLKX+ ]1 W0 [5 B7 G2 J) |
| MCASP_PIN_AHCLKX
; Y6 e; E( h/ c) g1 ?- }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, b: N, s& t. o, ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 F" b, P1 L6 l4 _! G8 p+ g
| MCASP_TX_CLKFAIL A+ S6 ?# G2 n) G# Q" o( y8 j
| MCASP_TX_SYNCERROR& Z, K. Z/ Q; m3 _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 N2 B# K: r+ m% \. r4 Z| MCASP_RX_CLKFAIL
- n3 a( }' X/ c4 W8 x8 ]| MCASP_RX_SYNCERROR 7 R6 z1 b3 M6 e( X* |
| MCASP_RX_OVERRUN);& Z- x; H. H0 M; ~- n) p+ j* a" @
} static void I2SDataTxRxActivate(void), r& k6 u2 D$ {* E# r7 L( d
{
1 M% Z/ U0 i3 h) u& x/* Start the clocks */8 G% E$ N- J6 i1 p; v' }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* P6 B; K1 b5 G8 \$ [+ ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( y# ]+ X% r1 Q6 \* ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 f: S" @: W1 z( E6 ]' T
EDMA3_TRIG_MODE_EVENT);0 }4 U! f* z, r4 t7 n* J' M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 A" b" V5 i& H! [/ e8 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
X, L" j* y% ]: V% _0 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 N( H+ `$ D$ W; q) u* IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; Q4 N8 P; N8 a4 F4 b/ Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* n$ z" [) r4 V0 o( H. @+ zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. m7 `5 J$ L* ?0 E' jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ X C$ I1 J0 P K: g( r
}
0 m& {0 X/ s/ l+ t( W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
1 [, J2 ~6 B ]% o: J9 u4 {* b |