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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 N2 ?& T: v- {; k2 ?1 ?( M
input mcasp_ahclkx,
0 q" ]. V* v- N/ |0 L$ vinput mcasp_aclkx,
7 g- a( R4 s% s* [8 Sinput axr0,: @3 ^+ v/ p/ R, ^) q: u2 N; n) U
4 V: R! b; w2 n) z! V) u: {
output mcasp_afsr, D5 ^, ^% }* m9 l% u
output mcasp_ahclkr,
0 L* F, P$ x' M- a, `6 Noutput mcasp_aclkr, i9 d1 J& @& Q- `
output axr1, F2 f# A2 S" s7 @; r; I
assign mcasp_afsr = mcasp_afsx;
$ y- g- s0 Y+ Z. z" hassign mcasp_aclkr = mcasp_aclkx;
0 E5 l0 C- V8 ^9 tassign mcasp_ahclkr = mcasp_ahclkx;
4 K: y& Y8 Y# `& H% m2 |2 dassign axr1 = axr0; ! L+ \. m- g; [/ k e( v
5 d8 L0 p: u' }" c" X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 Y: M6 a/ i9 y; K
static void McASPI2SConfigure(void)
- c, I+ Z8 I) x7 m{
6 N) _4 z }7 p @McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 s, Z& b5 y+ S, e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ E/ a8 w: e0 f& f/ C7 v- p) [ A0 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( o2 [( ~- K2 y6 OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. h I+ b% U8 Y9 P" ?* _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! z' V3 E9 C5 `1 J; g, e* I& F. eMCASP_RX_MODE_DMA);2 |3 X/ U9 {5 @" Z; ]2 a, g9 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. B ], ]8 @. q/ CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 V- S2 {2 V5 b& m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# U0 ]3 A8 F ^7 c( h6 a4 B7 L& `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); ^7 Q; u6 J% T' `6 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 S, z6 J: M/ w3 I) G( K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ ^8 u1 r N# W9 C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: U2 E% {" A3 v/ }$ |. {! O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 G8 E+ l ^- Q' EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 D/ n0 ^* e0 g4 b% U
0x00, 0xFF); /* configure the clock for transmitter */' K: M! B; H( b7 R2 i* l g4 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- x* V% b" L* BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 ^: m% C) v9 g: ]" p" g N4 R0 F% MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; l, ? S9 b, |4 ^5 N" J& u0x00, 0xFF);
1 {1 A8 |$ a& |& i% F/ {1 v1 t5 h9 ~$ W3 x6 R7 R. d+ Y
/* Enable synchronization of RX and TX sections */
3 |+ v0 W& f/ L @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' _5 o) d D" YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 G& s" g/ Z6 @; W, y% e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
a$ g8 X2 ?/ x** Set the serializers, Currently only one serializer is set as
* r$ \" _) Q) ^- W" z+ b** transmitter and one serializer as receiver./ l: M. o3 _9 Y8 n* K9 t
*/7 P& I0 H- D) @4 k! q$ {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( W; s1 d, `1 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** K0 z& m$ F: M) T4 L2 ^& ^
** Configure the McASP pins
' G$ F& D' ]. x* ~# ^5 c** Input - Frame Sync, Clock and Serializer Rx( T* S8 L2 f% D- `
** Output - Serializer Tx is connected to the input of the codec : Q; ?8 f' u$ T) i8 Q$ P2 \
*/4 G- T+ w$ r- \4 W. B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; B3 o" R3 h8 U3 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 x! Q* E0 Y" NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# k1 ]0 w6 f0 o* r
| MCASP_PIN_ACLKX8 y& \6 u! s" X7 S3 r N$ m
| MCASP_PIN_AHCLKX
. B O' a, m- z) C" J || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ b: _ W* c* U# g: ?$ k. jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% [; A# e+ V1 Y9 v9 O| MCASP_TX_CLKFAIL & J9 J; e6 k2 ^
| MCASP_TX_SYNCERROR
# i1 w/ c% [8 T8 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : J- q1 K% p/ C
| MCASP_RX_CLKFAIL6 p( u" Y+ \1 P& @$ ^/ z6 o! } r- W
| MCASP_RX_SYNCERROR , Z7 z. o. u4 J& A+ E" j# U
| MCASP_RX_OVERRUN);
1 I3 _+ l2 q5 O8 `" J; \4 g} static void I2SDataTxRxActivate(void)
! ~- e" }* @- t. C{
3 e% J d0 `" Y/* Start the clocks */
! u: w: M* ~1 K+ `2 O; JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 ^( s9 o& n! q# R; H! \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 }( z6 g5 Z$ Y* O! P: dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. s% Z! }# m5 @! H$ I" tEDMA3_TRIG_MODE_EVENT);- Q: A+ m e+ W8 S9 q$ D+ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; ]) p0 [7 a- L9 s# P5 S }; _4 Y. W" f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# a. L* P! h) k1 [4 v! |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); @" a- T. \4 e1 {* l! I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 F1 ]3 `/ X( Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# a4 E2 ]+ d- L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& i6 ]% Y/ G$ CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 [4 P) O8 ?3 _1 L4 f" J! N}
: J5 m" R0 r" l3 Y; e8 X: P0 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; H- R; W! X; e5 C! {+ U) G) `
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