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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& x* n/ B- e4 Q$ [input mcasp_ahclkx,& `9 v! z8 |1 ~; S# E2 N% z" q
input mcasp_aclkx,$ \6 k p z* G* }: l1 F3 q; K0 u8 w
input axr0,
, E. F P% U/ _0 |7 r% r5 V! m6 N' V/ I. Z$ |
output mcasp_afsr,/ t' g, o8 S8 U
output mcasp_ahclkr,
; K+ e9 P9 e* y# a6 r4 O! i3 loutput mcasp_aclkr,
& k8 }- ~6 b. |' v" x: goutput axr1,
+ b0 L: M( d; W# f* g. M) o assign mcasp_afsr = mcasp_afsx;" |$ s1 Z! P) R" h$ q
assign mcasp_aclkr = mcasp_aclkx;' P) ~& W9 U1 a0 Q) ?
assign mcasp_ahclkr = mcasp_ahclkx;
$ e$ A6 H+ f" F/ zassign axr1 = axr0;
& j0 l' l7 x, v% R4 t9 X9 s
8 |8 G8 T; D0 D3 n7 M9 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 O$ Q4 V! r: D2 U: j
static void McASPI2SConfigure(void)4 D, X/ H0 D4 w$ U5 c4 ?
{ }% G+ Q, z |" S U/ w" e% m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- _1 a: z8 U8 o8 h5 _7 O+ N! ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 T. S/ e6 o, c: n" F! g4 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% v9 F- X$ L3 K0 U5 k2 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 p6 [8 I: U2 @2 E5 l1 w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. g4 O! S6 r) U: n3 t. mMCASP_RX_MODE_DMA);3 S. b" M0 E- T, `* ]4 Y0 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& D3 q) U4 S9 s: e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 m1 Z6 _- R- D* Y- d" _6 D1 VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - q: K8 j! b6 K( ~5 m: h, w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 G% t( m$ F8 u4 _6 O" ^6 d p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . u, u7 K6 r5 ]' N. A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 D! c& S6 H# Z2 ?& b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' N" m' ]; R, h' _/ H$ B9 ?# R- wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( ^( J( R8 }; a. Y7 K# `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ k& C* j/ Q" i) g X" h0x00, 0xFF); /* configure the clock for transmitter */' v! _2 r" [2 ~4 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 G" a8 Y7 n8 U- aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 G3 q% M0 t! `7 i7 ?0 s! a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 t4 {# K% Z8 ^6 j# [! {! r# c* t0x00, 0xFF);
. l7 M' U7 P, |. f) ?7 z1 X! i: W# J {$ Q: m# `
/* Enable synchronization of RX and TX sections */ 1 f' l I5 z9 k) s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% K4 n( }- \/ a) R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. L& ?! e9 G; ~ z& ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* B, \6 v1 ]. h- \" W** Set the serializers, Currently only one serializer is set as+ N6 d9 j3 `+ s* W1 Y' B
** transmitter and one serializer as receiver.
) I) |, n: {& r*/
- K! H2 m4 y. D9 R+ F; e* z* iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ U. T& V( @: y: z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* F6 n0 c4 \( d$ ^. `** Configure the McASP pins 1 W' p. W/ x+ O( T: W
** Input - Frame Sync, Clock and Serializer Rx
$ H- U( I. M& y5 A ?** Output - Serializer Tx is connected to the input of the codec
1 |- E% [8 ` W9 J9 t" a*/5 r" h- u# K' t1 }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ Z, B4 Q2 ~% G+ ~5 O) I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 H; F; @( D; D. k- {( ?& {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 |* F G5 t/ Y L" M7 c" x| MCASP_PIN_ACLKX3 P% s( l, e, P) V
| MCASP_PIN_AHCLKX
2 S+ q$ }" c* D8 q% i( l) q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 Y- c& y! l+ s# v% Q7 m1 z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 F, `+ g( l1 ~7 L3 d| MCASP_TX_CLKFAIL % V. j1 D- K4 B8 P* g& r1 y! [/ M0 H0 E: \
| MCASP_TX_SYNCERROR% `2 m. C. p W% k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % R$ ?) l3 A4 n, R
| MCASP_RX_CLKFAIL5 R( w' Y+ ?: q
| MCASP_RX_SYNCERROR
}& ?) ]( D" X| MCASP_RX_OVERRUN);
6 B' Z q' `) ~3 \% u1 d4 P2 b4 z} static void I2SDataTxRxActivate(void)
1 r& I# H/ K3 N' j# H7 W- b{* ]* L- M \4 N( H
/* Start the clocks */9 b) n5 d* q- v8 V' X6 l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" J# ?) k6 z) R; S" t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) G1 I% `7 Y i. l2 c4 H, I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ A9 ~) L5 M7 u( \EDMA3_TRIG_MODE_EVENT);" j$ g+ ` I. R4 V" _) u5 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 ^" j& ?) Z+ J/ u- B7 ]- [& LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 {* x) H! c) H- S7 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 C9 B) q* ^+ {" nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 B8 `% ^0 j- H- [7 s4 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ a6 v! S: M* c3 aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) s# \3 |4 \3 L" w- D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 a/ t. r/ i. c/ G! g# g) F} ; j& A/ S& V/ {. [- w- ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 W. [$ P& D% W" o
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