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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. k! T ?9 F7 e# }2 k
input mcasp_ahclkx,3 \# O2 X) A0 {
input mcasp_aclkx,0 h% x7 ]1 N8 t0 J4 C8 R$ q0 q1 @
input axr0,
8 d6 t3 d( }9 o! @* G& S6 `& c3 u3 c4 [0 _5 Z2 i$ D
output mcasp_afsr,
. A8 h" F5 b q6 p6 V3 V7 f7 Foutput mcasp_ahclkr,
& d- ?5 M7 T: I& `$ x, j2 m) j( noutput mcasp_aclkr,
c/ Q( a! s# |( Poutput axr1,' k/ F$ F9 {& ^" p( H
assign mcasp_afsr = mcasp_afsx;
7 t5 R5 H+ v1 t0 bassign mcasp_aclkr = mcasp_aclkx;
+ g# m# P# o# F8 f( ^3 i& ^1 v# Qassign mcasp_ahclkr = mcasp_ahclkx;
" N. D% {. u5 v! \assign axr1 = axr0; 8 C$ ]/ [- F0 p3 W! O$ l
; K2 d0 W$ d" D/ v6 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! c6 Y$ ? o# M: r& [% Gstatic void McASPI2SConfigure(void)
. T8 P; W; d8 \6 R3 d- ?2 z" \{
) m# }, e: X$ W S2 i/ o) t5 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 Y5 | n3 U% Z5 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ J9 |3 K+ j1 b2 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 ]5 @, C# T( h- m' yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- U) f# O% B/ i9 P' ]& H% @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 G3 j b# t5 A2 U* s: JMCASP_RX_MODE_DMA);# ^4 ~3 U5 W k# I0 g- `4 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: H" k, J6 N( a% V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; E, m& y5 a* v& t2 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 u" C) ]( ~4 T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( @" o7 A5 T4 B8 f1 M* MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - O. B: ~' P( T4 b8 Q. f$ Z' E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; T; k8 p1 n3 N; W+ H4 I* V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 T! H5 o5 h. l6 A' x! u) ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + ]4 O6 h' {6 n4 G8 v m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," @( u7 |8 I& N: Q* p- G% G
0x00, 0xFF); /* configure the clock for transmitter */
/ B# B' u% i c' k% YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) f+ L! U, i+ n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 ?/ W( v2 _" _6 _0 p! {* VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, k4 |/ l. j, d! g8 @' o& c
0x00, 0xFF);" B0 N. l1 w; C) g- J5 I
5 b6 J7 Q9 R* _
/* Enable synchronization of RX and TX sections */ , b1 r& s# g) n5 F$ v1 o8 v$ P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 |+ E! n2 X' u, c+ L9 I1 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 q% U+ ^. o% s* tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: F* w) w) W B) ]! }6 y7 p2 L; d0 O
** Set the serializers, Currently only one serializer is set as" E% p/ r$ U: {9 F
** transmitter and one serializer as receiver.* o( c3 r0 W9 ^' \3 V
*/7 F5 c/ U6 ^( a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ P; S( R, Z7 A* k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, z2 s& @4 {$ l4 c3 j% P0 `. g! T: M** Configure the McASP pins 6 e: _7 o" ]' F
** Input - Frame Sync, Clock and Serializer Rx
- P3 y! E+ W' P# O9 s% i** Output - Serializer Tx is connected to the input of the codec 8 j$ @, @$ |8 S/ k
*/
) b7 O" ]) i, r bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! A: a& p; y8 n+ DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 r* c& X8 Y& L8 I. ^( Z$ B( Q5 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 u) k# Q) ~; _- _| MCASP_PIN_ACLKX9 }! E. [, f5 y0 Y6 g
| MCASP_PIN_AHCLKX6 C; D9 O9 B7 H1 F4 |5 ?2 h2 G$ A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 S8 T( j+ Q, p7 `: O' K; C5 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. J* r: F- p$ }3 S1 [| MCASP_TX_CLKFAIL
% k$ {5 C; N9 T- ~$ ?% I' q/ U4 f| MCASP_TX_SYNCERROR& W6 X4 Y% R: B4 i% U8 E' A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 c( U4 ?% z- q: z0 E
| MCASP_RX_CLKFAIL0 {& G h X, p7 i Q
| MCASP_RX_SYNCERROR
5 A! {( f2 H; e" _+ j! F: v| MCASP_RX_OVERRUN);
7 i: V! o9 f- j" K+ \+ T( f} static void I2SDataTxRxActivate(void)
( S+ X8 N3 }& n0 t( _) P" B{
* s+ v6 b1 X! L7 |+ n% x) Q/* Start the clocks */$ f. f. ~7 Z! G: m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( Q9 z% [# |) S. o, L- _$ s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- c1 [( w/ _3 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- n( N8 ~! J# }EDMA3_TRIG_MODE_EVENT);- R: o% y/ s0 M" H$ q+ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 E5 d1 [) M+ Y' J h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) d% ^0 s3 `4 m2 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- x! R0 Y# f J: l' oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% C1 t1 }; n; L- T. @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 V q3 {4 B; P( ^: e1 b9 ?+ ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" I' y9 V8 O: W9 w2 l5 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( @1 X3 Y. ]4 \* S6 y+ }: q9 B' J6 h
}
X- L2 `8 n$ g2 N% I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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