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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 N& H& z5 f3 k/ F5 f5 ~* A7 ^7 w+ tinput mcasp_ahclkx,
1 L" D" v1 d) H& V" Y. p5 F- p' H5 Dinput mcasp_aclkx,
; c& ]$ v# s- T$ Binput axr0,
1 H7 a6 ^2 A4 M" _( S) a% ?! l6 s2 P
output mcasp_afsr,- z, | u; I5 s, o$ |
output mcasp_ahclkr,
, |% z" Y& ?% E; F! z5 Youtput mcasp_aclkr,
( N1 G- `! [" |* f8 ^9 routput axr1,
9 N! @9 w7 T4 ~, U: f+ M assign mcasp_afsr = mcasp_afsx;
* X* c5 \( O9 Q- I: Jassign mcasp_aclkr = mcasp_aclkx;- c# ^9 e2 |/ ~8 K/ E) m+ t2 j
assign mcasp_ahclkr = mcasp_ahclkx;/ x! I4 _5 M5 f# }8 C. a
assign axr1 = axr0; % _/ ?, V5 W% j- j! v
6 x: |/ W7 l+ V. B: J" D! z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * Q% R9 `6 o% Q; S
static void McASPI2SConfigure(void)4 n4 \2 l; ~ c
{
. E! ]5 p+ ?3 u+ l. `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 I" k; W+ j# n1 W# u' i* W. |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 l% Y' w' E I- rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ^5 X1 E* ^2 q/ j8 b0 _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 n6 W, R/ S' }# u9 E( c" O' c" EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 i+ ~& V6 _* _. }5 J# I
MCASP_RX_MODE_DMA);# M3 x a R" ^* S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 [. Z4 O, ^6 C) T5 Z! M2 f' P1 @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* u! n# p3 |% N& g2 D: YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( n- i* z1 c5 @ qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 ]8 o5 V# z5 R- cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 M, p8 U8 H6 h/ |& X! NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 |( \* B" }" g$ J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 @3 Y) a0 o. K3 R6 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / e- Y0 n+ A7 [# n+ d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 w$ \) @. ]# G, A$ u( N/ R: M0x00, 0xFF); /* configure the clock for transmitter */8 P! ]+ |( w# {0 T9 Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); x% e% L4 p! ^( C! P) Z* }% W# x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . j! `3 l4 n- A) S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, U6 G* O% p# l- l8 P% p0x00, 0xFF);0 G4 i3 }3 Q+ L5 ?8 W1 b: F
! W+ |' B2 P3 D0 Q
/* Enable synchronization of RX and TX sections */ ' f! f& c/ I* r) E* T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. C' s; ?) d" G' r+ n3 _9 A6 tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' r: b. |6 _: A U. {4 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ Y3 ` D7 ^7 p4 j* G z" s** Set the serializers, Currently only one serializer is set as( n2 `) t7 ^0 F8 ~; j
** transmitter and one serializer as receiver.
, L% l& Z; I2 A: B' b' Z*/$ F6 U: j6 y+ j3 U! U/ \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 V! } C8 V) N2 s3 R# D+ B5 Z! uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 l( ^4 n( |3 T
** Configure the McASP pins " r2 C" J6 g3 w% [6 V, y
** Input - Frame Sync, Clock and Serializer Rx' |1 x9 s1 `6 [) n# o' v
** Output - Serializer Tx is connected to the input of the codec # b# r/ e/ k: v$ t S- E6 @5 V2 G
*/
. r b2 m: ^3 n& yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); m& F ~' k& k' t H1 m$ H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
D/ B2 ~2 e5 b( }/ VMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; x/ p7 V; O: s
| MCASP_PIN_ACLKX- r) d0 d s y% `
| MCASP_PIN_AHCLKX
2 L) n/ H+ }! m: v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& K; r8 E8 a" x& V! X4 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# _. V6 O7 L Q( A9 [6 {| MCASP_TX_CLKFAIL 7 X; _8 U8 f/ r8 z
| MCASP_TX_SYNCERROR
* _! V: d5 a. V9 i. X# a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , e: `: m1 d5 \, N, }7 e9 c# }- G
| MCASP_RX_CLKFAIL
* ?8 M! m1 o, j) ^- Z# `* a| MCASP_RX_SYNCERROR 5 O8 l$ j& ?4 O1 H' b$ i" `
| MCASP_RX_OVERRUN);% I: U4 c) Q8 K V
} static void I2SDataTxRxActivate(void)
7 S4 z' g) h9 i" n a+ i* Y1 I8 j' l{; d7 b; c" u& H
/* Start the clocks */
! w7 M+ N/ n* s+ r; UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- W/ \' n) n5 c- I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 @* k# m1 s2 D3 I- s/ |- rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! G! {0 N; x6 q5 G9 w% J
EDMA3_TRIG_MODE_EVENT);
+ U5 l' Q3 v+ xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : D V7 |" |/ f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 |8 x0 N$ d1 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% @' F, w; k r2 c) XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. ~) }1 n, m, q) T6 o3 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. Y9 b* l0 [4 I8 k/ dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); k- F" g/ y7 u: c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% x; H3 F e# R9 J8 \6 F9 R; M
}
% i9 m q$ L# l Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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