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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 ~+ ~7 Y3 d. {$ A' O+ s
input mcasp_ahclkx,
' h! g' a) O+ _( X9 linput mcasp_aclkx,
1 B/ o) o: Q" }% M, F9 m2 Iinput axr0,
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output mcasp_afsr,! r$ Q" V [) c* J
output mcasp_ahclkr,1 _/ e. _) |: y
output mcasp_aclkr,
c0 B+ R S% a& W- p2 doutput axr1,
8 z9 B, G# c3 h9 r0 i$ l0 p/ W0 V assign mcasp_afsr = mcasp_afsx;9 K0 L& g% q( K% J. y+ Q
assign mcasp_aclkr = mcasp_aclkx; F$ r- A8 K% z1 U- ^* F' P+ m
assign mcasp_ahclkr = mcasp_ahclkx;& C0 }, |; e' X" S5 V/ r
assign axr1 = axr0;
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+ ]$ n6 l$ P+ R; b& \5 \, C3 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- [4 A% F: |9 O1 X. `$ A# N0 }static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ A8 L3 y) a% d! MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 L4 C' P3 h7 V% ~4 v* \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; l1 V7 ~- P: m- N9 U# pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# F. c9 |% r3 [$ Q! P% r% eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
E3 C! n9 V4 g+ e/ x, zMCASP_RX_MODE_DMA);( \8 f. z# S; J! L5 |! [9 b7 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% ?+ m% K5 d, {! s1 ^* j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- T. a K9 q, p% A9 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ~3 H' _4 |! d* \( @5 W& u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) U3 i# o2 v' R! ^, ^. E% D0 I0 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 G! v6 M) c F8 n/ wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" G, n) M. ^6 ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 W& \3 I3 u5 F( LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 s! _, j3 h: S% wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& u# d7 g" I0 T# m. n9 v' X1 i7 L: |, q
0x00, 0xFF); /* configure the clock for transmitter */4 _* l! a5 E G! {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# E* V& t3 S/ K. K) p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " z, J% ^; P3 @* A* `& a. G1 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( ~9 v# v2 Q- P' l5 G8 B& `
0x00, 0xFF);0 ^( {4 b- V8 R" J* T& h% {% m
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/* Enable synchronization of RX and TX sections */
. K" T+ M- ?7 s9 R8 F U9 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 y) a( {1 M. v' gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ h' f( ]* B) |/ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 F3 |1 y- Y, k% d/ X** Set the serializers, Currently only one serializer is set as+ T7 V4 f' T4 @! \, v* h1 V; x
** transmitter and one serializer as receiver.
4 M2 T8 ]7 |, ~# F! m*/
- j# \( ]$ K9 ^' nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ m* [& g$ O' w1 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 Y. b' Y) c. {# `. V+ J- |' k) b
** Configure the McASP pins 1 @, q' { [ v7 J4 l. K
** Input - Frame Sync, Clock and Serializer Rx* s! q) F+ P$ a5 b
** Output - Serializer Tx is connected to the input of the codec
9 b7 O2 n" v/ h$ N% _& l*/
4 |+ q# U: z) E: d0 i- fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 T9 R8 F p8 V/ h/ JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, r" D( b& t1 N' y+ ~+ c1 z0 D* yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' S# r, }5 s5 h6 O% c| MCASP_PIN_ACLKX# Y' c2 `3 o$ y) z
| MCASP_PIN_AHCLKX
% c+ `' x6 |2 e( V, m( c) N" || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, K' D: P, G9 f8 |" _. NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) ^% V l$ n9 _# q) K6 W3 [1 U| MCASP_TX_CLKFAIL ; @: o* B4 B8 z2 P' v3 T. `
| MCASP_TX_SYNCERROR
* r( @( b# V/ e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 H) x$ ?& e9 a& s* T
| MCASP_RX_CLKFAIL. K2 E5 \' ]5 I7 P% o9 x- g, v
| MCASP_RX_SYNCERROR
- K! x) F& _+ k) c8 T1 C" Q. X| MCASP_RX_OVERRUN);8 d' d% M' ^# B; `8 T. v+ K
} static void I2SDataTxRxActivate(void). R8 l! L* {& d* @
{: {7 B" j% J, W. r9 ?) G
/* Start the clocks */
5 B% _ ~2 y+ v9 b& U$ `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& U3 b0 T* i2 J. @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; q5 ]% }+ `5 k6 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ i1 D5 T- d; W% N
EDMA3_TRIG_MODE_EVENT);
( W. @( \8 E, \: c& H# SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 c5 ~( v/ W# W& `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. Z5 v7 B T, U* W# p, I' I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 Z% w9 v6 B+ j4 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 @7 l3 l. R7 P$ R4 H, |; x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 \) ]8 C1 V+ e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ P9 i$ C4 V9 m1 y' QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& f3 J; ~% V7 n B1 [} ( H- @" d) \/ ]2 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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