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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, t9 K V2 _7 N7 e; q4 X3 `
input mcasp_ahclkx,
^: h. s7 E; W1 c/ P8 B. finput mcasp_aclkx,8 \* | o. p" j U" i
input axr0,
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4 K9 O/ @+ T4 R* V' u0 n3 ?: E5 C4 routput mcasp_afsr,
4 b$ u$ k: N, koutput mcasp_ahclkr,
. e: b. o# f2 }5 Soutput mcasp_aclkr,# Z' n$ e; C) _4 M# P5 G( o3 L- c
output axr1,
& K" `& O/ I0 `, X! J$ g assign mcasp_afsr = mcasp_afsx;- z8 n/ V" T0 k: n
assign mcasp_aclkr = mcasp_aclkx;
8 ], j' _% c4 @2 }- Bassign mcasp_ahclkr = mcasp_ahclkx;& [/ m: [; D' \2 @/ f, H
assign axr1 = axr0;
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' I8 L: I- I: l+ G6 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% _- {' E @7 ostatic void McASPI2SConfigure(void)
: _. h# y* f8 y" s{
, x7 o/ y3 B1 T+ `. sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 k3 c9 k! g% T& Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 w( ?" L. F7 \# x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 g, s1 x+ k% u4 m2 i+ MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& B2 d2 V8 \0 e: I* w/ k9 I7 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; X% n s3 h. B! @, a+ U' T3 CMCASP_RX_MODE_DMA);
% [' e0 S7 w" r# X+ \( eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' b/ X0 ~; m( \7 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. y4 u; ^: c. {/ j3 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + m) ?- R: C* e( q. `) O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 B0 W, u& N6 R x6 E& w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 z7 } v( G7 k dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 |: T0 `0 |! X" q1 [0 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% t5 A+ z/ t4 v6 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + N' ^+ S4 J6 H; [7 c+ U" Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 S( E# ? G. l4 ^$ u! R, }" G
0x00, 0xFF); /* configure the clock for transmitter */& O" i4 w$ Q5 a7 T% z; y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 d4 @; a' D( _/ lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / }9 j. ~% N- M0 X4 r3 j& G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ J- ? E3 k5 d4 k0x00, 0xFF);! i M) j3 l+ |6 n+ H, F
" g. g; P/ G9 I8 `9 M7 V/* Enable synchronization of RX and TX sections */
, r; L3 q7 T. t8 UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! w1 w, F: ~) u: b TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' W' r9 i3 d0 M3 p- [7 p5 o$ M( o9 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) X, x9 _0 k0 x/ R. t
** Set the serializers, Currently only one serializer is set as
/ k& ~0 v c# x6 [, ]** transmitter and one serializer as receiver.2 w. g/ R1 X |: d8 P$ C, C Q
*/' V. m* u; A" C# e! h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) z" Y; \- E. \9 q! g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- j" k' |& b' Z& W5 a
** Configure the McASP pins
0 g8 p5 B' w" V9 C8 V** Input - Frame Sync, Clock and Serializer Rx
6 ^1 k6 p0 K1 m1 h: O% c** Output - Serializer Tx is connected to the input of the codec / i) R: O" i- _9 J/ R6 p
*/
$ _# s& B1 O' O- i. }$ }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" E* z( y) ?; h+ pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: w8 e! Z \2 e% H p& z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 D: ~- n) x8 v
| MCASP_PIN_ACLKX' {1 b+ h O: u# P6 N. A& W$ H
| MCASP_PIN_AHCLKX' ^) A+ H1 {7 j2 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 [9 s2 K0 [! T* M2 @0 | a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ R4 ?2 I+ L' w# F| MCASP_TX_CLKFAIL
+ n2 t/ f! W1 u8 T9 l: l% [( x| MCASP_TX_SYNCERROR
! h4 m Q$ h$ ]6 c( K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, A; w! S3 V2 U9 X| MCASP_RX_CLKFAIL% M) |. y3 G$ X( [! D+ m4 T
| MCASP_RX_SYNCERROR
2 O7 r/ u e R2 V8 o* m" Z Q| MCASP_RX_OVERRUN);- b& y* g: K% z
} static void I2SDataTxRxActivate(void)
* n! H9 B9 e9 Z( C{
+ }2 |) P* Q& }/* Start the clocks */
( C& W5 {/ l) }! [( {& E! J8 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* S5 i+ I3 L4 @/ \; E% iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 d- S/ b; i2 j3 _2 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: {3 [+ E2 y& P, P" V0 \$ t* `4 l7 N
EDMA3_TRIG_MODE_EVENT);( O, m/ z9 ` }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 U, |' Y: z5 X% E% K+ R& nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! M- l3 I. o6 o) S' @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 A a, S7 S4 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 p. u: p* T7 q0 d* \9 |; F' B& N; _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& j& w6 w6 j- H; h8 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! X" M/ s: x6 \& s! SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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1 `; J" o" N. F. d8 c( p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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