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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ M" G& b0 L; d8 H/ yinput mcasp_ahclkx,
' t: b# ~+ {% u8 ^! v3 I% ^* Rinput mcasp_aclkx,; J7 N& @4 e6 F0 v0 f
input axr0,
4 [# W% s& |7 {- t" Q' E8 u5 Q- H8 D5 H F5 d
output mcasp_afsr,7 c: V$ M8 ^( N& \- z f
output mcasp_ahclkr,
. X* P3 N/ b" P6 ^$ j4 }9 \output mcasp_aclkr,+ b0 x W5 t! e. w5 E. O
output axr1,- u* v/ f0 a( Y! w
assign mcasp_afsr = mcasp_afsx;' R' E! t6 N: U' a6 }! l
assign mcasp_aclkr = mcasp_aclkx;
* k; R! y2 J$ @. Iassign mcasp_ahclkr = mcasp_ahclkx; d' V2 |$ r; E7 A' u I G( B
assign axr1 = axr0;
# P; G. w( q% @$ F% Y
( d0 Y+ @2 i* n2 I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # N% P2 Q9 Y! ?* @; b% ?
static void McASPI2SConfigure(void)0 d2 s, Q& I) o$ {
{
" \. J" u3 }. K( x3 d; LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 e) z, v9 Y3 E- N8 D' ^4 @. K* d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 X& }" e- ?1 [% q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' \3 Q+ r" ~0 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 r: I) `8 ^2 z) |% P) HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, d2 A: H$ Y; Z: G7 E0 G# `7 |MCASP_RX_MODE_DMA);
u, X ^# F3 d% `& p* jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! J6 x2 n: m$ ^) f% h7 \% r" ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ F! R7 _7 u+ N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) q7 S2 y1 H7 |" K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ ^# R* B; |; X3 v* D) G }# M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 H4 H& ~$ A4 ?' k- C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ o5 d: e3 T# s' uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" w& ~" a0 `6 u$ |7 `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: C+ U3 B0 w6 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 _; F3 o: q0 H9 w' j0x00, 0xFF); /* configure the clock for transmitter */+ J, v1 G3 g4 K. O5 @. }3 v% s8 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# R. w* j! k0 N5 e0 O$ EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 F! t9 y# Y! v' M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- J f' k' C$ K0 p: L6 v) c
0x00, 0xFF);( [/ }; W/ }( S9 H; S
; M7 U, n/ w$ T0 A9 A/* Enable synchronization of RX and TX sections */ $ ^; d% M. N" \; D; f3 r: A, g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: l4 ^6 c! Z( z$ Z* ?3 G+ DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; q$ X! V- U# hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 @! T+ \; ?3 r& W# r
** Set the serializers, Currently only one serializer is set as
1 \8 r, l5 D2 x0 Z! t6 m** transmitter and one serializer as receiver.0 Y4 A* `4 H9 c
*/
1 G$ `) E6 J. _' ]4 d$ xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. E. S/ C( o- W, x& L; xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, C; s" A( F% ~0 w: C% e7 T% b. G** Configure the McASP pins
: B! j& B- H, h$ c1 z& q. ]** Input - Frame Sync, Clock and Serializer Rx
! ?. N' a2 V" ?: L7 n5 U: f+ O** Output - Serializer Tx is connected to the input of the codec
* |7 w6 V8 u1 A/ M; O" B*/' Y% r$ R& @1 e2 l0 t6 D5 f& P7 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 R" c) \; z0 z, AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ c. ]" i$ b' G; ~* Z4 j3 aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# V6 ]. `5 |( ~4 m| MCASP_PIN_ACLKX7 s6 ]7 ~. Q) Z5 Z! ]
| MCASP_PIN_AHCLKX
2 c. D3 V( U/ l2 u' V/ h( C; J' O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ n9 Q: q( N8 s6 {- J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" r1 f) H+ x8 j# G9 `| MCASP_TX_CLKFAIL $ k5 b; {! u2 ], m0 j
| MCASP_TX_SYNCERROR7 t/ J( E$ J1 [ ^; E9 o7 r( F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR T7 G! S4 X6 x: ^5 x" l
| MCASP_RX_CLKFAIL
/ Z- L- V# b! B& Q) d2 v| MCASP_RX_SYNCERROR
/ T/ o4 }: Y T% V. M4 e+ J| MCASP_RX_OVERRUN);
+ ^4 _6 [2 e% r5 y9 ], R: S' ?} static void I2SDataTxRxActivate(void)
3 w7 s% a" {3 [& A- Q* i D( L# }{- r+ A2 D" x. V! ]8 |
/* Start the clocks */0 ]. I& a. z2 o$ r( i# |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ C( |8 b( E6 p' ]8 a8 a4 N8 L! uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; S; @4 B) s- n) k0 ]3 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! R! L5 A" C5 D1 w6 X6 UEDMA3_TRIG_MODE_EVENT);7 {6 Q* f% ~ Y: R8 G+ h O; e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% q$ D% F* x. {+ JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 M* C. S9 E! J4 o& e$ z* b+ Z; uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ P" A5 V0 ?8 Q, Q8 G9 v. iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 n/ U# A0 ~* h7 z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 d+ I8 T" E* m4 b5 H% lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 O1 v F+ z4 J. gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# h+ y. @% W, x" w3 p}
2 ?& @ T8 n2 v, |+ x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 P! i3 [3 F. N+ M6 m7 `$ @
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