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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 r3 I% b0 m. G& L* ?' W u" ^) q8 T9 R B
input mcasp_ahclkx,: T! c# j, _( a$ j# {& }
input mcasp_aclkx,
4 G0 y8 m7 n/ d0 d4 _+ F& ainput axr0,
8 d7 D& E' _7 B8 H5 P! D
# W9 Z, A m2 A& D1 C1 A; W( l& Qoutput mcasp_afsr,
3 _ ~8 S6 f c9 ?! n, poutput mcasp_ahclkr,
8 f4 S4 g G N* \4 _output mcasp_aclkr,
' p# r) N. C$ B: \; ]* Eoutput axr1,
# S& T: U4 M7 h' L" H$ }5 T" E assign mcasp_afsr = mcasp_afsx;
4 G" e$ ]( X! k9 @; yassign mcasp_aclkr = mcasp_aclkx;
+ r4 d1 A9 z, `4 Passign mcasp_ahclkr = mcasp_ahclkx;
; s- d4 l/ l. Wassign axr1 = axr0; 2 s0 }# J4 _/ c
+ R6 v; N3 p+ ?6 R; M9 ^2 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 V' ^. B$ o: L0 L2 M
static void McASPI2SConfigure(void)
: f, _" K+ L8 T" @5 u6 B! }- L{& J- V( O# y3 Y! m7 j, n6 \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. A/ X" |! R! e1 p$ Z" t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* b3 M4 v7 c. q( T8 r+ @8 MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! V `* K# O+ a3 ?, E% \: gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# P( I4 M6 V. U" q7 ]) i% C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ e$ o- n- H1 H% b1 W- x
MCASP_RX_MODE_DMA);3 E- }% E/ i5 d% {' ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: l* Y4 Z/ a* F. a# G$ M5 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ O( C9 w4 {7 D/ \9 TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 c, z. T( e& [& TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 D, y2 N# `! S/ _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! R% e! f% H, t0 ~2 Z' c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& n4 f4 J! Y. G' _, |) eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" r$ e6 q E4 d# A, P. v3 @. oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 E- T* o0 g& \$ I) Y2 f0 D4 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, O( M7 A( ^- M3 H L$ K
0x00, 0xFF); /* configure the clock for transmitter */
W. _$ y& ~% F5 p+ Y8 J$ M3 T' DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) l" V0 t& c$ ?) C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 z" f" @+ J6 |6 ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ u' M x6 k: p6 y. r( H0x00, 0xFF);
' |2 Q; M) P. r% l( a/ z1 N$ b% w; ?: c5 C
/* Enable synchronization of RX and TX sections */
7 [! ?4 A- D0 ^" X: YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. a' b( l- n* _- m4 I* R. W8 K8 u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Z) v. x, I! J. rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ q" ]" H6 j; X** Set the serializers, Currently only one serializer is set as
( G; x, I! m- d! ~3 H** transmitter and one serializer as receiver.; }5 ?. |! ?' a5 u
*/
! [3 G2 G1 d7 {5 r# d2 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 k. P/ z$ B! q8 C# A+ l# y5 v$ x' oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ h; ?: y# z% Z
** Configure the McASP pins
/ w" l- A: N M9 A( R6 p9 F+ s** Input - Frame Sync, Clock and Serializer Rx* a9 c y1 V/ `8 M* K( U0 Q
** Output - Serializer Tx is connected to the input of the codec
5 @7 f$ Q U( Q* G7 o4 c*/
! c* v9 y' [1 m. |" Q6 I9 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 [% M1 D% ]) x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( Q+ w( y0 _2 S4 `. @% ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ a' D/ c7 u+ U4 k
| MCASP_PIN_ACLKX
/ x9 V3 s; d! N3 _4 M| MCASP_PIN_AHCLKX
6 R) M& k8 i9 t% r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; h9 M' ]# I3 q x1 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, s6 S* e2 u! a j| MCASP_TX_CLKFAIL ( y" a2 V8 s8 W/ t% ^; y/ r
| MCASP_TX_SYNCERROR, P* M7 J, F' a0 ^% n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* B. V1 l) u+ y$ A" `5 S1 j$ K| MCASP_RX_CLKFAIL6 Y0 n/ e2 ^% C" A- k* `% p3 i
| MCASP_RX_SYNCERROR , F8 ]5 U) w. B' Y4 x
| MCASP_RX_OVERRUN);
- @8 }& B9 h- h* K) ^* [} static void I2SDataTxRxActivate(void)
. U1 j5 ~* R% V( V8 n4 a9 J# j{, Y& {: c @7 _' r4 E
/* Start the clocks */0 d/ J# b3 p5 G4 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- J! O4 s! l+ ~6 |' E) a6 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 r! O, F N" z; h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" k) y0 b! y K9 n# XEDMA3_TRIG_MODE_EVENT);
& K. P3 a$ o! p ?/ a; wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, z, T: r4 H# ]: J6 \! m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 i' x: t* m/ {. `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. M. j( M+ Q8 P* I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: `% Z2 \3 ?+ U# x: ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) ~0 |/ s; j+ k9 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 W3 q: z m9 B2 U4 j! B9 \. X+ O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% }" z. t8 x" I6 ?8 a5 D2 M
}
) V" J4 W7 o/ w( R' f1 i9 S4 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " [ c. ^6 g* h0 {# X, K r7 S
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