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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 I* [3 J" u- x+ m, b- Sinput mcasp_ahclkx,
c& q" o: |& y4 K% e N& a" linput mcasp_aclkx,
$ D( ?. }1 n: g) R+ R5 _+ k Hinput axr0,
3 u- @( ^) O0 Z8 t* R$ r
2 L$ O9 V- b1 z7 Routput mcasp_afsr," P0 _# _) x" N2 B2 B
output mcasp_ahclkr,
( Z% s3 {& ]5 K% u) X0 ]* Z) Aoutput mcasp_aclkr,
6 U& N8 n4 ^0 B4 W; g5 ioutput axr1,! d/ f* l% z7 d. ~# L
assign mcasp_afsr = mcasp_afsx;) j% X) ^( h$ _# W( x' `
assign mcasp_aclkr = mcasp_aclkx;3 @4 F. N% @7 E. V M/ |
assign mcasp_ahclkr = mcasp_ahclkx;
- T( r' R6 a" J; X) Xassign axr1 = axr0;
& s. P4 K2 {% m+ N0 ~% R5 ?) ^& q, v$ O4 y) P% y! s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 z5 R1 o) j" }. W
static void McASPI2SConfigure(void)8 i# @$ d, n3 S2 Z$ }; I
{, J4 ^4 k/ _! l6 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ d# |; z! k8 S# i% IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; b- U2 C; ?, U$ h7 n$ c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( D3 }5 _7 ?# B3 E( P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ h: S+ p$ m) U6 f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! H. S; x" |/ Z9 ]MCASP_RX_MODE_DMA);
2 ^% l8 N& h$ t& HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' O- h7 j& p* ?2 H, ?. a; ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- l! I$ {, C, mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) J6 l" f2 w: d; N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, ~1 Z$ r& i' E. g iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( f) u, Z6 J, z! k; u [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 W. p# S3 `" P" s9 D' K; K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% z5 I, d; J/ `0 j# ]0 B9 |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 Q5 L) u7 l4 G* S' o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, z) K7 `2 {% J4 N# Y0x00, 0xFF); /* configure the clock for transmitter */
" C" U3 y8 N: B5 X& {5 _7 t# DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. J6 Y, S, E8 ]) o9 W8 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 x7 a3 \% O. B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% Y, n4 j; U; u0x00, 0xFF);
N) g' n% N R1 [; q
* t" r2 c; a" x, y9 S5 O1 A/* Enable synchronization of RX and TX sections */
, K6 e; T% f" Y9 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' l7 f& e2 j3 Z% L. `! CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! O, l$ H: l# wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, x. p2 n3 `; g" @3 p. S
** Set the serializers, Currently only one serializer is set as
: ~$ Z. `7 y- m8 p* x** transmitter and one serializer as receiver.& y- o8 P+ R0 q5 m8 D2 L; J* U
*/
$ H1 \! B! f' w0 [7 E% uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ ?: j4 L3 N; [( ] F- J5 x5 f3 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ K5 h6 \ S9 q+ M2 X4 i** Configure the McASP pins
8 P6 \6 d' @6 `$ y5 A** Input - Frame Sync, Clock and Serializer Rx
. Y9 V2 T+ Z8 _* L8 q! ?( t& M** Output - Serializer Tx is connected to the input of the codec
5 n1 [6 R0 b: x: U4 ^*/- b3 w$ w4 g3 x2 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 q5 D4 K, _9 w) J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ^0 @) c% v8 R7 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 l+ C% b( a1 P" _3 q
| MCASP_PIN_ACLKX
+ {! E# r5 |4 _. G$ J! o. J| MCASP_PIN_AHCLKX) M c2 h9 M1 q3 X" o( H) }% }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. |1 x- p2 n4 I( c# }; u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) ~* T3 d! m6 R2 ?| MCASP_TX_CLKFAIL
4 U! t/ ]( t( D5 k6 M- {" b: g| MCASP_TX_SYNCERROR
7 z0 l" ~5 z+ G' @ \- S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & z! h$ m4 S! V, V s' w
| MCASP_RX_CLKFAIL& ? \/ z' G' {( G* Q% _) Q
| MCASP_RX_SYNCERROR 8 s9 I, ~. x) D7 Q, s' Y- l% G
| MCASP_RX_OVERRUN);
5 [( }$ X7 Y* |2 }2 X& Q} static void I2SDataTxRxActivate(void)0 ?$ _/ ^4 w$ e8 M6 O
{+ X3 G% H7 n: p* f( z( d
/* Start the clocks */8 n$ H% h* F; \6 A* Y1 B+ m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. }9 |! Y' h* R |8 g7 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 @/ M1 u- U- p8 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, e! s: J! j4 l- i2 k
EDMA3_TRIG_MODE_EVENT);
- k+ `8 X" N3 a( l: s0 c0 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 a6 t/ O/ d8 W; OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 ?% v# q, Z2 J/ [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 V/ ]1 X$ z D6 z, M- {' rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# v, \1 z. T4 Q+ @3 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: O7 P+ R5 F1 S4 e6 O( qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ k% l/ O2 t; N8 u8 r$ K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) c% U8 S5 W6 H% v# a, ?} % N2 _$ G7 x/ p5 B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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