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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& t* G h8 a9 Z5 M4 J t# `input mcasp_ahclkx,
9 F8 f; C1 f) m) D# Pinput mcasp_aclkx,
4 ^" N5 t$ ~1 tinput axr0,, v0 z7 _% C& K
6 e) T2 Z4 k+ X3 I/ {0 A$ o) O
output mcasp_afsr,6 E! }$ g2 S% Q% c6 [
output mcasp_ahclkr,( _: O& t' ~3 U
output mcasp_aclkr,
1 Z; }/ u/ w9 p6 B5 ~1 eoutput axr1, e/ K) v$ e) ?8 j+ \. R
assign mcasp_afsr = mcasp_afsx;1 x) o8 u$ q% Q/ A2 m% c9 r
assign mcasp_aclkr = mcasp_aclkx;
) e2 R8 l6 x Cassign mcasp_ahclkr = mcasp_ahclkx;
$ J* M! }; v$ @$ H9 B6 S1 u; Kassign axr1 = axr0; : v+ p9 X W% g
- E Q, Q! v0 s7 \' p# K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ N2 L- K; u# q( q; t$ U) A9 U. qstatic void McASPI2SConfigure(void)
& ?2 a! O) x( v! i/ Q4 _: b{
" o+ _( }/ j* N: [, k# ?7 y3 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ ~. Y/ ^0 U9 QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- N9 g& `" J8 z b4 ~6 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ p8 g+ Z" o V2 C2 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 W; Z5 [/ l O+ p& q- u* }5 PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 m! {) }$ ?/ B! j
MCASP_RX_MODE_DMA);" [/ | |. q& F8 `6 h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, n( H& x( }" M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 c9 T& ~* t0 \6 P1 p, J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 q* g: n8 k( k3 D: J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
s# i9 y3 |; N: j$ C! ^& i: U4 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 l4 d) { C# F+ @$ CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% ~+ O3 v0 s( B# M* `0 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 e' P. B7 `/ U5 k4 x( x/ \1 KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; U- G7 w! ]5 E% O" { n2 X5 t6 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 \' y$ j( Z. j; `0 `1 [. d6 n* C
0x00, 0xFF); /* configure the clock for transmitter */
8 z% c( F+ @8 U3 aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 @4 ~9 n$ W1 t3 j" P2 \$ v+ mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 F! _- A! g5 F7 q* [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: |9 I) Q1 T- S, @1 N0x00, 0xFF);
s3 ^- a. b2 f
$ `8 f W" T0 G3 J3 R" @. t/* Enable synchronization of RX and TX sections */ ) s& k2 [$ Y7 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& L, E' R" S# gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" q( n/ M2 ^0 b" N; T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) l/ d: }; l& |2 n, f8 @
** Set the serializers, Currently only one serializer is set as
! ^4 s# y" Y: ~** transmitter and one serializer as receiver.+ {. o2 V- H% t6 [( u+ H
*/
8 n$ O+ U ?3 n& _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 T- G5 J* C6 Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 K6 @' L7 d( Y1 R** Configure the McASP pins 0 B/ r3 O" T5 C+ |% A
** Input - Frame Sync, Clock and Serializer Rx
$ S) O7 b- K5 {$ G6 [+ }- L4 t** Output - Serializer Tx is connected to the input of the codec
" J, H$ i( e4 W1 [*/. ~! d3 S8 q% l& Z. A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ b' B: x5 G$ `1 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) G, ~( ^- T9 r2 C* G S: k" {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 l& u2 W! c, G4 H3 ~, P" s3 L% U
| MCASP_PIN_ACLKX Q0 u: `' s" A1 n4 v' q9 U: P+ l
| MCASP_PIN_AHCLKX
1 w' d$ Q* w" v) Q& }3 ^1 f) E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ P- F/ M% H5 S5 K: D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( J1 i0 V) W; l1 L5 \& Y' h| MCASP_TX_CLKFAIL ( a# \9 q$ H( ?4 A0 F. i- Y/ Z
| MCASP_TX_SYNCERROR' q6 ]! a. p2 c" H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
^" B/ ~" v4 t2 n0 [2 T4 E% t( p0 b| MCASP_RX_CLKFAIL
5 n4 Y( a. w! x- z7 z9 p+ Y| MCASP_RX_SYNCERROR
* C. u; }2 ~" K' b8 r# I| MCASP_RX_OVERRUN);
R$ c# D/ R, K) }! Y9 v} static void I2SDataTxRxActivate(void)& o1 z Q9 ]) n# V% ^( T
{
. K4 q' d; H/ [7 b2 r5 H- M2 G. u6 z6 ]/* Start the clocks */5 @: e) ~* u5 e" Q2 V; S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); i- Z; b# n3 ^9 n: y- m, W4 q/ l' }. s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 @* }' }& d/ Z4 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 T; J- y% M, E! s' B3 dEDMA3_TRIG_MODE_EVENT);
; n1 n! r v SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) Q' L, d) [$ l" G+ QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( a/ C- M- M# R) ?$ T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' |$ B( C: G( g" O7 x- B( m! FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 H6 l& L, `: Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ?# [' V* J6 L/ D1 u! x+ I' X8 y9 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 u* [1 y! y q* ~$ {" u7 w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% D1 R' C. K0 [' \; E4 P
}
" M/ g) Q% }# L3 J5 I% A7 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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