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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* n4 Y- y- O C7 uinput mcasp_ahclkx,+ V/ U7 m" i, D! H" I% a( h
input mcasp_aclkx,. }9 ]. a6 w. E" y9 s
input axr0,
3 s6 M6 C9 f7 M
4 _6 C) ]; g9 I# F* |/ a6 youtput mcasp_afsr,9 |. W$ ?' h! p; A: Q7 _' j0 \/ I2 ]
output mcasp_ahclkr,& e: y& P. L# x% ]4 h
output mcasp_aclkr,; U" a# |! R9 `9 ^3 R l
output axr1,+ _2 \. K8 V& C* k$ n* |
assign mcasp_afsr = mcasp_afsx;
/ e3 Z& M$ h4 A6 d! P7 Zassign mcasp_aclkr = mcasp_aclkx;/ I, R; q8 |$ y. q D# C. h
assign mcasp_ahclkr = mcasp_ahclkx;
( d- h, ]6 `, w+ M; Y8 W0 z& zassign axr1 = axr0;
8 U7 a( ~0 ]) `" C$ `
: Y; E2 Q1 n& s% F' h4 j) j. O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; {% ]& K' \( L% g% X& E
static void McASPI2SConfigure(void)
3 F" Q+ F9 m$ v6 y{
* O3 y/ D9 C) q/ w2 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" p! I5 H9 |+ D! J% Z" FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ q" Z& Z8 [/ i; B5 m; V# j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: j) I' Y' }1 x) tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; N# @$ m D/ j1 ^4 |$ B$ N7 FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ w3 J+ t# z/ Y( d" ~7 d8 _MCASP_RX_MODE_DMA);
$ X2 [/ I, a W5 x" O" yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ d3 b9 o: r0 G' _9 S- o( S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ p4 C4 ^+ E0 j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " J9 Y/ l. X w: ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' [$ j' W q+ {0 j1 A9 I& IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& h4 X: a( h7 Q4 n) {+ _! g1 RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# E p9 Z" Y! q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 q2 H0 N. z+ s6 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 ]& ^8 h7 |4 ]1 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 R! F: z& U: W5 q0x00, 0xFF); /* configure the clock for transmitter */9 Y1 ~8 _1 h3 _( O$ f k4 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# }$ x3 q% i: F$ E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : h! W2 V& K* x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ c( t% I. I/ x8 j9 z e& a& S0x00, 0xFF);, W& M: U y9 e+ d
) D" W. J. [4 a$ T+ G3 u/ A/* Enable synchronization of RX and TX sections */
+ g. V! O( T9 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. n) U# G" ]+ m9 R- A) e; v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 l: j( }: w3 v* q' lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 B- r& @( V6 |. o1 D
** Set the serializers, Currently only one serializer is set as
! b4 M+ n3 D# n+ T2 q) w3 w** transmitter and one serializer as receiver.! b" `: n$ R5 d% N+ O$ \% \1 k* J
*/. v! v' U; |5 g2 f; Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' }1 O# }* r) w8 U: O& @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 z9 b, F& s- H' {+ e9 n** Configure the McASP pins . c5 e( i2 k$ y% q5 Q7 C1 U
** Input - Frame Sync, Clock and Serializer Rx
* n& T/ b8 g0 V' ]+ t** Output - Serializer Tx is connected to the input of the codec & z" Q3 _* P, ]: h
*/- I) }4 N P) O! \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% s- M9 o, E& ]' Q! G% g4 D/ `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 ?1 T' V" A9 P4 y7 f0 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% f* g! g& l& y0 e5 v. T
| MCASP_PIN_ACLKX/ b4 q" j9 Y7 A( {' d4 i
| MCASP_PIN_AHCLKX/ m/ V3 `9 o$ a* `4 Y$ \) T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- s- X# E" Q' L p5 XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 s/ h+ d% Z, `* g2 S" @7 m# `/ Q
| MCASP_TX_CLKFAIL
' r9 m4 P' J5 a) J5 i7 C| MCASP_TX_SYNCERROR% S7 b3 G& n2 l9 N, H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) l& n' Y- e8 ~# I+ ~! G| MCASP_RX_CLKFAIL
, E4 q4 O0 N, K7 [| MCASP_RX_SYNCERROR ( I6 p, J9 J8 E3 v+ M& J5 R5 E
| MCASP_RX_OVERRUN);
4 {" }. J1 p& I} static void I2SDataTxRxActivate(void)
* i. G* t4 E8 X3 A{( |' M5 O9 k! g
/* Start the clocks */2 x; D2 D% d" J- ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 G# g7 B' T0 _( F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 l' V( |; B8 I9 r' A: ~/ r% \# ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; H" _- C" f, p G' r1 g7 T9 |
EDMA3_TRIG_MODE_EVENT);
. c) p) o. ^, K2 u: c8 hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ K v4 Z0 N. w1 ?5 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 e/ M3 M" n' {4 `3 h1 ]( o' m( ]* CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& N) p8 k+ |6 l& |$ y: G4 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' @- |2 J% A, h: Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" e D& E# B% k E5 Z |, I( MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 N* Z m2 k6 N0 C3 H4 zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 \! M: B/ }, R) g4 v* N}
`. O4 @2 R+ L+ s8 l0 |! {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * D; _9 s% R$ o
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