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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& l3 X3 o+ G7 Finput mcasp_ahclkx,- L. w" G0 |% i
input mcasp_aclkx,% ^2 Z* F* ~7 U
input axr0,2 A. j8 y; I3 i' d# \5 A
6 P6 E# W( @. U# \# T+ c; ~output mcasp_afsr,% c8 q% [7 X* c' t! V% U
output mcasp_ahclkr,0 [2 r3 \4 u8 V- p3 R) A/ Y
output mcasp_aclkr,
! k: r' L3 M- V/ N4 {% x$ R9 o5 koutput axr1,5 x! z8 _9 I9 W& K
assign mcasp_afsr = mcasp_afsx;
7 {( c6 O0 v: M$ m9 u3 u/ X, passign mcasp_aclkr = mcasp_aclkx;6 i9 j% `1 M% r+ b& x0 C9 U
assign mcasp_ahclkr = mcasp_ahclkx;% q& Z! n( j# x4 C. m1 q
assign axr1 = axr0;
! ~# t6 P7 ~0 A* W& Z4 ^/ [% ~- w- \2 p1 t2 }+ N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 X0 U0 H, g& N1 [) j. c wstatic void McASPI2SConfigure(void)4 I8 F5 K6 ?. a3 U
{/ x0 S1 n) N4 L" T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 B+ R! L; V9 `8 `! K3 O/ `6 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 X( r5 Y8 Q& Q" j/ i( V. \* L3 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% s* v& S6 S0 U* c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ p! g4 c. c) R9 ~, O, T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ p8 j; Y# Z. _& K; d5 c2 O; ZMCASP_RX_MODE_DMA);
' ]" f2 ^4 \9 I/ NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ w3 @' X, X# Q$ ~( C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 q9 S% N2 D2 L$ x6 [3 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( N7 P2 \6 ^) {$ t) H8 g: sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% ~2 d1 s8 L, {* t, TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ w, X1 t2 v; C, B5 p: M8 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) n5 n1 T2 a0 D9 w& \4 G' v* _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. E5 O: H* c* f& N' j. FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 t2 l; @! F) Y& F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ M \3 I7 G& m9 N3 H m0 l0 x0x00, 0xFF); /* configure the clock for transmitter */# c n$ g: x; }3 g5 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 \6 G2 e, E% p6 O; ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 E% R5 f& V( m: ?5 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. |" P0 G9 h: z: P8 S$ z# I) t0x00, 0xFF);
& U9 u1 Q+ N x6 {5 c; M3 w4 k" U4 z
/* Enable synchronization of RX and TX sections */
?0 @ w m) X8 k4 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 p; x& P. ^6 r& U' V% Y; y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 `) A' ?3 P4 Q2 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& Y# g! A r" M% e
** Set the serializers, Currently only one serializer is set as
% f X* n* v- o1 d& f** transmitter and one serializer as receiver.5 w+ V: ~1 J, o' L1 d; u' V
*/
6 H" ~- ]; l* f, l. _7 H gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 q; n. P* h) o% ^2 J2 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ }( [, J8 X' t4 Z% m& f* e/ M** Configure the McASP pins 2 y4 z8 y# r- y+ t2 @9 k4 n
** Input - Frame Sync, Clock and Serializer Rx
# Z8 ^6 \) @8 a7 u4 I$ H8 x** Output - Serializer Tx is connected to the input of the codec
& ^0 t% T# t% T) p*/$ a) l ]$ Y. Q' C c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
Q& i2 G5 p9 f/ @4 G) xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 a0 Q, t# M( s% G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, C) q! `* o e1 q7 _" d. Z% A
| MCASP_PIN_ACLKX' b( f4 H) F) u& M( u
| MCASP_PIN_AHCLKX
* K, c3 g+ J$ N( e8 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, u- Z8 C$ T( i6 u4 l$ ]2 |' }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ e) n9 g3 a7 Y| MCASP_TX_CLKFAIL - L$ R, p- }, p
| MCASP_TX_SYNCERROR
& k* x4 Y, \0 U9 E* j5 m c# ^( b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ {8 ^; d. a+ K. F( n; l| MCASP_RX_CLKFAIL
7 T- V, N4 S1 f1 B| MCASP_RX_SYNCERROR
, d* P% }5 V, K/ u% y4 L9 E| MCASP_RX_OVERRUN);- Z% K5 t7 ~& F! `
} static void I2SDataTxRxActivate(void)
' C; v% W+ Z- a/ s* h9 \$ k4 y{0 Y# w6 U* o, @: N# g! I$ u0 M
/* Start the clocks */
9 L+ z0 |, F! s/ `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 c1 j" l8 f9 U/ M6 O% M$ L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 l6 q* Q2 z1 e3 h5 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" ?7 c# R- ]; TEDMA3_TRIG_MODE_EVENT);
1 U0 | _, d+ n4 X/ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) H: n$ _: Z: U5 M# y. u2 L: i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 e, K7 M4 [3 y- m0 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) m' r$ O6 }6 t6 K1 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 K2 v8 T$ c9 ^* k" y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ O0 `8 q$ y5 W& k8 ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: `- `; Q8 ~; j3 N8 v- OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' z2 X; R# F |% y} % m# [; Z4 m( e6 g- E& R9 \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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