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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ l1 [- j/ Y6 z }% \( v
input mcasp_ahclkx,$ R- D/ ^/ Z0 f' L @$ I
input mcasp_aclkx,/ t L# Y" y0 s u: d+ i
input axr0,. u% s4 I, V; V$ g8 j5 q' ]9 K* |
+ A5 k! I& S3 Y& Boutput mcasp_afsr,+ C7 Z! A4 } T4 S' i
output mcasp_ahclkr,$ N& x3 t0 V9 U# k1 F0 ^
output mcasp_aclkr,
' \9 |& o4 w6 u3 b0 W# e2 ^# u6 Toutput axr1,; J' m' e) F; m4 ?% j+ R( U
assign mcasp_afsr = mcasp_afsx;( x4 m# z' `, H, i# S
assign mcasp_aclkr = mcasp_aclkx;9 H. p. X! }* V0 R: I
assign mcasp_ahclkr = mcasp_ahclkx; V! M3 v" K5 J; ?( c* ^0 r3 U! n
assign axr1 = axr0;
" N/ @" K) A3 L. c, l8 n
0 d7 X" _/ b! n& z4 m6 U1 N2 p: w7 Z6 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 B3 M/ D1 c1 lstatic void McASPI2SConfigure(void), U/ W3 e' Q3 K% _( @) I
{& L( J1 j& Z$ b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 q& v! i+ L! y- LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 X- A. z# D% r7 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 |0 L2 g2 V! {& N+ J, [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 a. p$ e- \: V0 r( B' a1 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 u; d' S0 U2 T3 Z' c
MCASP_RX_MODE_DMA);/ Y( Q8 I6 ^. \7 I j: c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," k: c- p* _! G, b2 v+ p( P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( C; }; X0 o. A3 H/ N2 u; h! n9 d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 r. t7 q* h8 j4 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 S. |# t% u6 R7 _4 Q$ {4 ^7 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 G& O, X" h9 J7 T/ d: R) _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, m o- ]+ J% o6 Y+ xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 }; P9 y. K5 Q( Q7 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ~ \. s1 s& f+ X4 n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 ~4 x9 c/ o; t# a8 d; b0x00, 0xFF); /* configure the clock for transmitter */
, d& @0 p& {2 B# a( XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 S' D% {& X* S* o8 S! U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & L- S4 @% F- m% _, A) V3 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 @# `" u) j, l8 w7 {
0x00, 0xFF);
, @& Y' x% A/ C( W' X F, b8 c8 _" B# {9 j$ l
/* Enable synchronization of RX and TX sections */
$ B2 {& I7 m: Y+ |# B; ^1 Z" KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 R* O3 G, S( R& f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! m; E' J; ]2 e# z5 x: j Q Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 z% l. Y1 m3 I q# U8 g
** Set the serializers, Currently only one serializer is set as
/ g( X* z& q2 [. J: x8 n** transmitter and one serializer as receiver.
3 u# k! o, w5 L' R) K. I G*/, V2 }, L _4 ?* d8 Y" F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 e- n# [# |# g- MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 g3 L- q# a2 O. k** Configure the McASP pins ' ~* Y4 m$ X: `% x, |4 F0 z
** Input - Frame Sync, Clock and Serializer Rx# b# w/ Z5 L6 B9 g
** Output - Serializer Tx is connected to the input of the codec * J9 I$ h8 v& K3 D! x$ l |- k
*/, [( }* U) p, K- Q" l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' a( K2 u7 a1 N: GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, I3 l6 ~0 _( \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; y1 R3 X1 s/ q2 J9 H- I, J, U
| MCASP_PIN_ACLKX
( A2 S3 i5 _( b5 a6 F! } `| MCASP_PIN_AHCLKX
, ?3 R4 [6 {( o0 u; z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ v0 a" C3 |* N$ `: p9 o3 H/ ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 R* r1 N7 N3 E+ H9 u) p* B| MCASP_TX_CLKFAIL + T2 S1 H: q+ ?) I
| MCASP_TX_SYNCERROR
* ^4 b5 _; J3 M' r8 \1 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
h- T8 J% x3 x) _5 c; W# v| MCASP_RX_CLKFAIL2 B0 d' i5 k _" p( G2 T
| MCASP_RX_SYNCERROR
7 E8 e* X+ u8 B| MCASP_RX_OVERRUN);+ G* r, A# Y; ~1 a+ E
} static void I2SDataTxRxActivate(void)* R0 j1 Q K N* Q
{ ]6 u3 k8 x( T
/* Start the clocks */3 \* U0 x! u* G( p0 b8 I+ _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ W% r7 c5 A5 | t! S' ?4 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) t. j+ \4 }1 `* Q3 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, S) z U- l9 J `* A N
EDMA3_TRIG_MODE_EVENT); K4 J8 s9 q% B2 m" F. n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 Z% c( l) x+ l/ v, O/ X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 S% _. r7 k$ v) ~" t+ f$ _- ~) qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 S1 u& G/ x! `; ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, I2 B: G) z- W/ w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ `. ]) _/ M/ L3 b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. r7 A: Y# K; j- e5 yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, s" T7 F6 \: t% B& r
}
# h& C, y! I+ A7 i6 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , {3 L7 y1 f; k$ J; Y
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