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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 F) E U8 T1 `, `3 S: R! H6 ^input mcasp_ahclkx,
* f1 b/ }" }% |. F6 linput mcasp_aclkx,3 S @: B! ^4 V
input axr0,
- y' e* k- s$ c
( K" U5 e2 w2 r. |( W7 `6 Voutput mcasp_afsr,
" ?( }4 E2 |8 h3 Loutput mcasp_ahclkr,
9 `* n* M' R( E; r& coutput mcasp_aclkr,
* y" q* F5 h2 k* N# A; toutput axr1,) f0 R/ x& Q" \% d$ f7 g
assign mcasp_afsr = mcasp_afsx;0 [, N' G' R2 Q: U) D0 k
assign mcasp_aclkr = mcasp_aclkx;1 H0 ?8 M6 k9 R$ ?8 T) u, F/ d1 [
assign mcasp_ahclkr = mcasp_ahclkx;
' q9 H5 n/ t: L iassign axr1 = axr0;
" g+ ]7 w W$ Q- Q8 q+ ~) V! h4 H0 B B. L2 }. K r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 S4 R- T8 w/ u' G) W3 _" \4 k9 L5 r
static void McASPI2SConfigure(void)
7 |9 K( s1 ^: j6 l{% C* {8 y s! ~+ g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: v! C7 W6 k/ s$ k! A% m UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ E5 }2 b) P, A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. i8 U; A5 E( ^6 o, BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- ~, Q* v6 y7 ~# T& }, LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 U0 s \$ N5 J7 I
MCASP_RX_MODE_DMA);7 \+ M6 |" v" F; E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) i! H5 ?* G0 b. x5 N. Q7 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! p0 f6 k( g! M2 v# z3 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & d1 b) O7 W& V8 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 v7 X: R4 g5 X+ Z- cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 T p' s* @% L& P1 d+ j2 r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ R# P" w q1 i7 RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 t' n1 C9 ]( Q% R) N# B1 _9 ~+ E& `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 k1 L) v. ~7 A8 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
g2 L+ u" h$ {- U0x00, 0xFF); /* configure the clock for transmitter */( K, }2 t# r: X2 N7 H6 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" W! b0 L$ }# a: s6 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / o" K) H& F' H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- B0 [9 ]( y1 g
0x00, 0xFF);, ~8 v1 j- M6 @& e" W2 x
4 c9 A& f# T/ H0 L* T9 D/* Enable synchronization of RX and TX sections */
) a1 g% f G0 o# ]/ J% `7 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. }2 g, p7 I- \4 z6 k5 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# v) W% U8 M: W8 ~2 q9 x) qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 o! f- c3 R" T3 k
** Set the serializers, Currently only one serializer is set as! P! D M# |9 G1 O& |
** transmitter and one serializer as receiver.) ]& _: D' M! o6 ]- t8 }2 g+ o
*/ a M1 X% [$ N9 ^% F' V3 D8 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; r$ `* F2 W2 f$ k0 d% ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 @/ y" R5 |6 [7 e1 J
** Configure the McASP pins
; B9 J6 K' |' W! ?! {7 n** Input - Frame Sync, Clock and Serializer Rx
4 I P4 h& H( [0 q6 Q** Output - Serializer Tx is connected to the input of the codec
; x+ d$ U( U4 T*/" I: G& a7 e" T1 Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 Y6 Q# g$ V, E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% R+ J! m& R- T8 k$ E; CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, L- l: ~# m" W- V( P| MCASP_PIN_ACLKX6 F. l2 X2 O9 [3 k9 @- S
| MCASP_PIN_AHCLKX! y3 Z! t: [% [: `$ V: [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 K$ j" L! D& y JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + X% ~- {- N* q4 |/ U! D
| MCASP_TX_CLKFAIL
/ y* t1 c' V, A5 z) J, ]| MCASP_TX_SYNCERROR
5 j4 S0 j* _9 s2 S; v% W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 G/ G7 `1 @, p" E7 b9 W| MCASP_RX_CLKFAIL/ b7 g4 w/ c2 }) e0 X$ r
| MCASP_RX_SYNCERROR
$ W; g& h t- ?% R) O& _% J| MCASP_RX_OVERRUN);
0 P% C: m" v* {* F} static void I2SDataTxRxActivate(void)
6 ]7 n& v1 ?2 x6 u3 W& r8 g# y{
6 M6 o- s4 B$ l3 G$ J: Z* S+ J/* Start the clocks */( I$ B9 D5 B# i& M+ I9 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 G1 N# n. g8 x1 ~2 k5 y* E" qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. m" V; @2 g0 H6 ]& e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 h7 R" Z. O6 `- y+ ]( x- t- cEDMA3_TRIG_MODE_EVENT);3 S0 h- C( A6 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 ~8 k; f7 N% G/ T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( u) g# s: |7 @$ \' c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( `0 q5 ?0 w7 Z% q0 N4 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! R8 _* J! m/ Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% Y8 k a. y. {6 ~, N* j" T/ ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& [) R7 W. [) k0 Z6 S$ S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 w. J' @8 n) P: n* E
}
' A& r- D( r7 E6 |0 V- l5 [4 j. X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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