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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 T; _8 b7 H3 | I. ?& M
input mcasp_ahclkx,
% q8 O9 W( D) E3 L4 Hinput mcasp_aclkx,
& I$ @* Q! C7 |% P# ]0 L1 y" vinput axr0,# R' d) @0 I+ A9 \( B+ _
2 t1 |* }4 y% x/ @; `output mcasp_afsr,0 `. O& Q% I- o) S( s) S0 n
output mcasp_ahclkr,) \# x3 X/ Z% \
output mcasp_aclkr,
# O p2 L- G8 Z8 E! W% poutput axr1,4 a& P2 ~# y# m* `
assign mcasp_afsr = mcasp_afsx;- f$ U# G: x+ \- P8 ]; y) q
assign mcasp_aclkr = mcasp_aclkx;3 H! c$ O2 H! t
assign mcasp_ahclkr = mcasp_ahclkx;' `$ w/ n/ I, J* Q' j8 A
assign axr1 = axr0;
% Z" s) q5 p# k) E+ n% [# `6 i' x. O# u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 {/ h1 c% H% |0 wstatic void McASPI2SConfigure(void)* ~" Q; Q3 ] a& \! Q
{
' n- ~! Z+ d8 `- Z* f! sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: g# G+ U1 ]9 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
|' m" A- @1 U9 g1 y* kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% D) j5 f4 |8 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 G9 z/ F, N1 g8 r! r7 ^6 @, {* O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( g: R5 J$ k4 {
MCASP_RX_MODE_DMA);5 j2 z+ t2 l4 B9 E7 I" o* v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 ^) | s0 N- f8 DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 A: k4 m9 o4 c' c" W# qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , {2 F/ ^( s+ c4 I7 d% J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 v6 Y6 L7 T# y& J3 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % |; {; x! S) P$ i7 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- V: ~, p' j# s7 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' @) g% x$ v% Y: a9 {0 ^7 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 N1 S0 t3 u/ m5 H9 ~# B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 ^, f, S. w8 Z! T$ d0x00, 0xFF); /* configure the clock for transmitter */
. H; l7 ^' a2 S- Y6 p/ l) P, ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- j- b) U N1 U" e& p- J( x7 ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( Q7 @$ u1 s+ a# Y- ~& M" Y* y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* P& a6 Y1 G4 _3 T9 Y
0x00, 0xFF);
$ I6 F9 t+ L0 g0 T4 W; s
9 T( N: ^, T( ?9 }/* Enable synchronization of RX and TX sections */ % O' h: `. H- j+ o; H J8 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 }' v/ T O$ U9 R7 \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 x5 Q" K% N5 S- q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' F2 Z, `) [$ I1 I* [** Set the serializers, Currently only one serializer is set as% x0 e/ `4 }) q
** transmitter and one serializer as receiver.# u8 r u3 R# [5 u3 Z3 _7 G
*/ o8 w! \' R9 v) T" x. ?0 |5 i* }2 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ p& }, F# v. P8 ]* D9 X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 D0 i6 O! q# S# k' X y% e
** Configure the McASP pins
% N8 q& i3 R; W$ ?& o) n9 V: V** Input - Frame Sync, Clock and Serializer Rx
& J$ E' z' C; D** Output - Serializer Tx is connected to the input of the codec
5 X8 T2 j/ Q* @*/; K) i/ Y: f3 \; L( ] M/ ]% _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 M. U" D, P) hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 J9 m+ i- ~8 Z+ U7 E) b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. o8 Y8 @# S( s/ B! i
| MCASP_PIN_ACLKX V* [* B: A2 m( Z7 B. x2 b
| MCASP_PIN_AHCLKX
& @) j7 \$ j6 C! X' w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 n/ ?2 A& m, C7 g! f7 {# K- g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ D; V3 J) l" L/ ?
| MCASP_TX_CLKFAIL
1 n" c" K* B" t3 U- q5 K| MCASP_TX_SYNCERROR
: g, \, z* ~/ d. I k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 j4 m& k$ Q* K% n$ \| MCASP_RX_CLKFAIL
8 u7 J: q1 v' v# K% F- `% h1 X| MCASP_RX_SYNCERROR
! k, K. Q8 {2 B3 S4 _0 [) m/ a| MCASP_RX_OVERRUN);3 g* G+ W/ n3 f7 y
} static void I2SDataTxRxActivate(void)
2 f, L7 V2 C% {{
6 o+ ~8 Y* } Z5 j2 Z/* Start the clocks */
( n6 u8 G; E y9 S) t; s4 _" XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! b9 F6 U1 S8 W& E- Q/ |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! N5 y: G& k8 K* x+ TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# B* P+ [0 u% Y" x# PEDMA3_TRIG_MODE_EVENT);: o' K$ |' O/ p( D- t5 I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , E$ m( _! Q }' i3 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; v. X' ?9 |& s- s8 ]. W" u) E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ n+ k1 T7 c- I: k" A* R, O5 X0 d1 S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: F6 G+ P8 Y! g: L6 J3 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) d" y" o5 V4 f$ yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: B4 \6 @% V9 S. a) e/ @2 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) ^$ p2 f* Q: P: ~" O& T# x7 n# I}
) P; C/ A! a3 B3 w3 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) ]# h/ I3 v( o5 K# m7 W0 f l# B |