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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: Q2 C* n- @' S1 s" h$ f2 j# cinput mcasp_ahclkx,! J' ^2 ]+ C$ X. h w
input mcasp_aclkx,
7 s' j3 Y; q! c2 zinput axr0,
. h# P% O8 r& y4 @/ @! {$ j2 \
% Y2 h2 p2 c. k! P+ c- f* Aoutput mcasp_afsr,0 j( G6 g- y. j: i' ~+ Y- ~9 I
output mcasp_ahclkr,
1 w1 S- u3 [* f6 t7 b% |output mcasp_aclkr,$ a7 @9 t$ u1 K/ J' ~. j) N: j9 v8 L
output axr1,
, L8 b" u! h5 i6 P: A) Z assign mcasp_afsr = mcasp_afsx;
$ j5 V' q t) [assign mcasp_aclkr = mcasp_aclkx;
* F( z( S2 K9 t6 r3 V. j# ^assign mcasp_ahclkr = mcasp_ahclkx;0 _/ R- W x- L9 }
assign axr1 = axr0;
# i% ~. L, ]* A9 J+ B0 p1 W1 ~; Z: h( V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " s2 [$ n2 z7 p6 O6 j t
static void McASPI2SConfigure(void)1 A+ ~. u2 c$ g2 s. F" S$ x
{5 k3 A+ ` \% k1 A2 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 Y6 w j( ^% D3 k0 ?+ _: L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. A* t6 x; Y2 V! p+ j3 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' R) K4 o/ J. F- w L4 W3 {9 ]: r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. B+ b3 j/ I& k T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# I" p+ R9 M# v
MCASP_RX_MODE_DMA);
/ t+ i o5 D/ J- PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," l% A% F4 Z: r# w+ V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& c5 Q4 M% F9 v' J! K6 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % [/ w2 d0 w& ]3 K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 Q$ n; y' |3 t2 X* c2 _2 x5 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 q; u& y/ n! |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' e! [( g6 Z6 |" H' I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 \! ?+ @4 o5 V; X8 }5 O6 q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 Q3 {% O4 s$ V( ]& ?* W- @( tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 G( J8 ]$ @2 e; ^* J0x00, 0xFF); /* configure the clock for transmitter */& c: |3 M- x1 ^4 H' Z/ }* j# Q) j6 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ]! Z% {6 K5 M8 E' o2 {- oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 ^9 x+ C( i9 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: \' N! p4 h/ b8 L! s* @* G/ v
0x00, 0xFF);1 T& @5 p5 q, E% Y% {* | ?* ?
4 m8 x+ R% T8 t# H I3 N( H$ p/* Enable synchronization of RX and TX sections */
, i, n7 J4 E; h( ~2 a% {! UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, O: g& m% }) u, v: R, H- u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' i2 X9 n! P1 S' A( ]6 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** t2 j+ {1 D% h! e) J; n! t
** Set the serializers, Currently only one serializer is set as% Q$ X- O( ~. G5 E/ ?1 F" t8 S
** transmitter and one serializer as receiver.8 }6 q3 D, h; n" _8 S
*/& K# q% S& Y+ e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& c6 N* x9 d6 M9 ~2 z5 N7 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* p8 |) l$ n' T1 H: Z# ~! [** Configure the McASP pins
$ F& S9 d* U/ \2 K** Input - Frame Sync, Clock and Serializer Rx
6 ?/ }* x5 v8 m) i** Output - Serializer Tx is connected to the input of the codec
% U* a$ O6 t) c7 U3 x*/
0 i; j. Q/ X, x' h8 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 R* q# J" e" X1 ]/ a. x7 mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( p( y; }0 `: z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 i$ G' [; d1 o* }( {7 c/ u5 p; p
| MCASP_PIN_ACLKX9 A# \3 G% L0 X5 w
| MCASP_PIN_AHCLKX
1 u; t1 }( d" ^! ^& v3 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 Q. {: ?+ ^. Q! G4 A: V9 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( w- L5 c( r5 K4 M( C. ]; Z, J5 f| MCASP_TX_CLKFAIL
2 }% `: i( R% ^* G; m| MCASP_TX_SYNCERROR/ y- _4 }$ }0 f6 d2 ?- h7 c1 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 o, G, \9 K3 s+ f: N
| MCASP_RX_CLKFAIL
, |; ]+ P; L+ r( c7 ^ D| MCASP_RX_SYNCERROR
, h8 }3 [) {3 V3 ?. G8 u| MCASP_RX_OVERRUN);
, Z1 F. q. `0 R- @; k} static void I2SDataTxRxActivate(void)
: I7 v) E3 ]/ J: `4 ^& t{1 l7 C( b6 r' e7 e, {- i' K) v2 \5 F
/* Start the clocks */
+ q8 ?* w3 Z3 Y" kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. ^ a- B6 y5 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 q0 R6 D) H! N; Z* [3 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- e* U: k F" T) n2 HEDMA3_TRIG_MODE_EVENT);
- t/ p) g6 O" ]. {; f* DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ ?- {( y4 O$ O1 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( x( h3 G( k9 u) B/ NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' H. \; X2 m/ m7 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ u5 e$ ]8 t$ O" F2 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. W( ~3 O0 |# v3 K. y* z+ f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! t8 Y# Z! B; j) \# W+ E4 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% o# p* G& h9 U* P, N
}
- V6 t* R8 R6 Q9 H5 e; V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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