MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
$ [) C9 x) v: j  I) J6 D+ A9 ~input mcasp_ahclkx,
input mcasp_aclkx,
0 y  z# {* w8 Z: `: sinput axr0,
6 z) X$ S; P, y
output mcasp_afsr,
output mcasp_ahclkr,
, \2 d9 N1 q1 Y) I& K3 _, Boutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
% Q% \1 k) k8 T0 ~; I) M2 wassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
3 u3 a% o2 z1 Z/ [' D; @1 N+ ^+ ]assign axr1 = axr0;

' i# b' Y! n- Y* H* H0 \
- W  r. Z$ q/ @7 C8 C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ b7 x5 E  G: K' [MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 Y9 t% ]" }! N7 w( G" ?- XMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. f- ^- c0 R0 f8 P6 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- C5 U- \. ?6 A) vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 ?3 S1 m) [, RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 {. Z& _# t& ^" n% }8 v0x00, 0xFF);

/* configure the clock for transmitter */
; t: l, J' X- C) h6 H# Q2 W. n5 m3 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 ~2 J" m1 m& h' Z9 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

9 u  j9 r. C# B: M/ r8 U/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 \& `4 `: P! f& [% |5 v( `/ mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
- Y/ [; ~9 Z; V9 p5 f** Set the serializers, Currently only one serializer is set as
% J2 g: f! e- X+ Q& Y9 c" E: M** transmitter and one serializer as receiver.
6 i5 o% W! s2 ~*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 {1 a3 a4 U9 l1 O2 c) S) w& J# dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
1 \4 K) {6 V/ {4 _** Configure the McASP pins
. q9 m; h  o3 X8 |. ]** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
# m2 n- A- r1 F8 U*/
5 e. K) G. m0 [0 v2 J2 I8 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: L4 m  H% N- a7 K/ k2 GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
( U' x3 C  ~8 _# V: }: n+ e| MCASP_PIN_AHCLKX
  `, e# u5 _# x1 i- O* u/ c| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( _, r, D# o% D( ~| MCASP_TX_CLKFAIL
* l0 ]0 ]  w; }1 k' X" F# F8 Z4 l| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: a5 A1 V0 e- r6 m3 n3 Y| MCASP_RX_CLKFAIL
2 d; u( N9 i# [( [5 F| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
) i+ J# k( a# K2 n. p$ U& Y: J1 _}

static void I2SDataTxRxActivate(void)
4 T; D% F/ G" j! X+ p{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 D9 _% s! z2 j2 ?5 ]8 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
+ M9 H" u3 N5 D! e( LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; W2 v6 H" u3 @5 w* H4 gEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 I0 V: w3 J# ~# @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
3 L; Z- K) z) I) dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ E$ a1 q$ n& {! o9 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 E/ |$ n4 g0 V2 t& I% |! r) ^* ^$ [}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.