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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 s9 B% j8 h( {/ Z8 t7 _
input mcasp_ahclkx,
1 i' f% k) m( d/ e6 A3 Q% X. _input mcasp_aclkx,
/ G l& O& S6 B4 Z( _% e4 o& Minput axr0,, X* N( l! C- h9 ]" D6 E& j5 C
4 P L P) r$ {! t" n5 { T+ o# B/ B
output mcasp_afsr,. O3 Y5 }. p3 I% O8 y
output mcasp_ahclkr,7 E9 @- G8 `5 c- b8 y" V& G' c( k
output mcasp_aclkr,. r$ ~2 K, y1 z
output axr1,' v c2 K1 B+ w3 h' X
assign mcasp_afsr = mcasp_afsx;
6 l5 {" p3 f& o0 g* U: v4 C8 i" k% @assign mcasp_aclkr = mcasp_aclkx;
6 _- B" w- F0 J2 O3 \( Aassign mcasp_ahclkr = mcasp_ahclkx;
) n# S0 p/ v. h9 F, G, U- B' @9 tassign axr1 = axr0;
/ M. B4 l) N/ k( @. H. I4 }) e" }' h4 V p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 J( g8 d8 U3 T
static void McASPI2SConfigure(void)
2 z, u" L `& e: `: [4 l6 e. S{
H3 W" B+ @, `" a" AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* x0 Q) b+ ?6 a2 h" G i1 JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( o% ]! o( V6 K) ]6 N! [% }& f& Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# g& I4 U9 m/ F" c0 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 ? I; X x- y$ {! \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- [- [$ F: D+ n: ~0 L* L2 v
MCASP_RX_MODE_DMA);% a7 }2 ?& v9 w: T! U7 V! t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! j, K* u, R* Q; {% {6 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ i4 d. j8 H0 W; [/ g. {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 G- F7 O6 _9 s) k3 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 f) p4 A/ K+ o0 k6 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* [* b" s( a. l% N' o& y/ ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, ]3 K) f. [5 m. a, ~. L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" u, W+ T7 J. ^. M" JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ Y* y- u1 F/ B5 p8 A2 y: ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, I9 M- S- R- _+ ]: D2 d1 j
0x00, 0xFF); /* configure the clock for transmitter */! J( [, j! u) _2 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 J3 z f; Q# K1 }, M" N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : q8 i# ^" e6 U! W0 L& \7 a* o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 e: y! e- W$ X+ x6 X; `0x00, 0xFF);% @- I1 c$ T$ Y: o( F. T" y
7 W2 m* J1 b6 f6 v0 `: Z
/* Enable synchronization of RX and TX sections */ / S" |7 q, \+ p6 O, F8 R; h. b, B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, e! ^" [7 k* e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. [9 y! T( T/ O1 w; P" \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 Q, |8 h0 u& A L2 R' L** Set the serializers, Currently only one serializer is set as. r1 | u% f$ |) l7 K3 R8 ~* L
** transmitter and one serializer as receiver. ]3 u% }* W5 B$ d+ f
*/5 `6 b% _3 R1 e+ b/ E9 A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 p& Q! T( X$ B( FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- ?* N# @! _8 }/ x9 u! \
** Configure the McASP pins
8 t; r' b$ o8 X* X& [( x** Input - Frame Sync, Clock and Serializer Rx) r; V- v7 d' |( q4 E1 p8 g
** Output - Serializer Tx is connected to the input of the codec $ n7 X9 x+ X, f8 K" [, e T2 _
*/. h8 b/ E; t3 J: }5 a* T* ]1 {. k9 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 q+ g$ P# x; {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) a4 n% Q& `: h/ K. Z1 N& h9 m7 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 m- W% a8 d2 O3 @, s3 t| MCASP_PIN_ACLKX& c- C3 ~& g. s2 C
| MCASP_PIN_AHCLKX
/ V# t+ ^- [9 }& H9 Q: ~) E" {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' `( a4 {0 w+ R' h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 h6 h8 B2 i, s( l
| MCASP_TX_CLKFAIL
$ I* _! i- s! n8 o| MCASP_TX_SYNCERROR+ j* a/ {& U5 ]1 U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% D4 w: v8 S/ j6 {# O| MCASP_RX_CLKFAIL9 h" h" V' P7 x1 L% r- C [& p
| MCASP_RX_SYNCERROR # H( H, n2 a; W; H% Y+ v
| MCASP_RX_OVERRUN);
% {& i6 Z$ A+ W5 d' \} static void I2SDataTxRxActivate(void)# D. F E! A4 l2 B: R1 g
{$ N% o- D0 h" Q: l
/* Start the clocks */8 M7 w3 O- S9 `. R( c, d) D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 `6 e1 d" k9 J wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 c( a5 ]0 _+ {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) J5 j) |$ A' p% s
EDMA3_TRIG_MODE_EVENT);- Y8 ?: X2 L1 c) _& ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % i* n5 f* c: f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: c+ X7 m" t5 l1 m: R2 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 m/ S; d! |; K- T: w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- m8 K8 h% a+ E* i) k& hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 y. K, ]- }7 C6 q) J; i. v) ^, g, M% i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ g* \! w) S& Z1 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 q+ U6 O0 T" y3 q) r4 x- [4 u) `0 E
}
. |( d# s! R/ D. I+ V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / E. v1 \" v+ x5 X% }" w: h+ w
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