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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 u3 _3 B8 r8 A4 q Z4 ^6 binput mcasp_ahclkx,3 n8 Q/ O3 @) f8 }) _9 Y3 F
input mcasp_aclkx,- R1 P3 L- i1 [9 I8 s
input axr0,
" ^6 p3 W! I5 b
/ a% i5 S9 i$ }output mcasp_afsr,
k0 t5 A" ~9 E! `9 k% a# ioutput mcasp_ahclkr,
+ f0 [. H. }, toutput mcasp_aclkr,0 c7 ]" E* s$ g. m, ]" ~6 f/ L
output axr1,+ I0 Z- I* t3 h1 X% h( z7 C) U
assign mcasp_afsr = mcasp_afsx;
$ t" o) \2 m) h9 E) ?2 Rassign mcasp_aclkr = mcasp_aclkx;
) [0 w9 E" x5 Y% k6 Uassign mcasp_ahclkr = mcasp_ahclkx;
* S1 w; ~: u# k8 ^assign axr1 = axr0;
2 s+ m; Y8 r9 p; u( T# @5 j! S/ R
# G2 A% v* T+ ?4 t8 f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 j+ T( j7 O, f6 o! R! U4 X2 ]" Kstatic void McASPI2SConfigure(void)
" Q$ h6 g$ H/ [2 x' A7 g{9 {; |+ n3 ?" l4 f% o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 V* C* N+ l/ V" l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; J7 N/ |% k$ {/ O2 D' _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 \8 T, d# O) F, y5 q1 g, l* CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) X! Y8 @. ]" u0 J$ k/ k$ ? v% M1 L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," F/ V: \% |/ k# A
MCASP_RX_MODE_DMA);
1 c& R0 J# P: RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 W8 E, G2 k' L$ O7 C6 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 A5 D2 t% k" ? e5 P/ n4 N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 M; w0 L; s$ o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& i# S# W! E9 {) |9 [; A8 A& zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - o" _+ I9 {* a4 V7 l3 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 z U! a" N9 B7 T6 R* h' r* `0 q& I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 r1 W8 F, F1 a! q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 R, v5 y5 F# b. y$ Y( Y* @) E KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 n3 N; c7 L: ]! w0x00, 0xFF); /* configure the clock for transmitter */
2 {0 M, v* C6 X; x- NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( K) N3 ^" q# D. ? j% G7 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 [$ @+ }# G! ^- g% h. p. v9 f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" s! S9 C3 y4 c2 L' K; g0x00, 0xFF);9 M, j3 I. p0 T( z# h. a' Q
0 w/ i# d& [1 n* q4 q+ i8 H/* Enable synchronization of RX and TX sections */ , ^; e* v! ^2 C$ G, @( M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ y$ C) S& T |5 O3 ]& L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 L7 `( y! ~: ~" {7 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) M& p# Q' g q1 R7 c0 s2 ^** Set the serializers, Currently only one serializer is set as
+ ]4 v" A( X$ o: B6 a4 x** transmitter and one serializer as receiver., L* g$ ?, H" N/ L) Q0 _
*/
& S$ a) D4 k- R3 l" c) D* nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- m8 O6 l1 i- s) a2 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: L6 ] ~( ^8 ]. r) m7 f** Configure the McASP pins + P1 U- I" T2 b3 }2 f
** Input - Frame Sync, Clock and Serializer Rx4 X3 N$ F/ K4 ?
** Output - Serializer Tx is connected to the input of the codec ( h% z/ s; M; `* _( v1 Y( x2 \3 \
*/
G+ y. S }. i+ w/ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' X" L% I, C9 l/ w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 u B' l9 Z$ k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. \) |+ v3 l8 }6 t }
| MCASP_PIN_ACLKX4 z. i8 P) _' h" H3 W
| MCASP_PIN_AHCLKX* K. ^: h$ _) z- j- I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 Z# q) T7 M/ r' E! m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) V: a- a% ?+ |3 ]# {0 O3 I
| MCASP_TX_CLKFAIL ) T# l- t* }! S
| MCASP_TX_SYNCERROR6 [) w' _5 R: }; q, s0 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ C ] @7 E$ [| MCASP_RX_CLKFAIL
/ E" n) T5 f9 ^- c. ^9 {- N| MCASP_RX_SYNCERROR : ?/ Z; |& r: o7 O* B: w. r
| MCASP_RX_OVERRUN);" \' p" w N# w6 E* y
} static void I2SDataTxRxActivate(void)! T# x7 f6 k; I, _* m) S- D! c
{( X+ K2 c6 n6 e2 Q1 Z
/* Start the clocks */
6 i, i: d K$ @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 }6 L) N# |5 g% y. {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; [5 w. r! T; X0 C. i; [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 D3 |- p3 T. o* dEDMA3_TRIG_MODE_EVENT);
# }/ {( u0 Q6 H0 @! f/ L' LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; ]7 i) z8 z, Q" P# BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* S* b; {: e$ Q! h. ?$ CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! k- c( R( ?+ z/ b: |5 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ h, {2 y0 q9 }5 b3 U: u: j" l y% Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 T, F2 \8 o3 U0 a; U& G" o( FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 I! Y$ F% R& e8 h- f) P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' q+ {5 ^& W, ?/ e/ V" A
}
7 Y4 p& i# g- w4 X* @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 ?# a$ M9 ?9 H
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