|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 ^ W3 P5 @& n3 D
input mcasp_ahclkx,
/ D1 l7 |2 O2 e& \0 {1 S6 |% i+ Kinput mcasp_aclkx,. e; W4 @/ n, C4 }3 [
input axr0,
1 t6 Q7 x$ T2 F% t9 D
$ z0 V8 S8 `- G# Soutput mcasp_afsr,. i8 _# I; u/ T+ O
output mcasp_ahclkr,
2 A! ]- j' D/ ?3 Uoutput mcasp_aclkr,
0 w; M4 M' F' Soutput axr1,- w: }3 ~* I4 P" ^7 l+ C D
assign mcasp_afsr = mcasp_afsx;
* S( U1 Z( O; w9 q: W+ t7 sassign mcasp_aclkr = mcasp_aclkx;: p& D/ J2 k0 u4 m" j3 W: L) K+ K# E& s
assign mcasp_ahclkr = mcasp_ahclkx;
+ t# N8 G' {7 zassign axr1 = axr0;
3 O+ Q6 u6 i; k. c# \3 H0 g, d* V- K/ B: {& J m* ]! }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * a# A ]& y: O3 d9 p6 s, q$ w+ P
static void McASPI2SConfigure(void)- Z9 D7 d; i0 \$ j& u
{& J# g8 V( i1 D( k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 y' R4 D* p( \8 v" Q% Q! @' i0 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: m) o7 F# P* \; AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; ]: N9 x3 T- }! a1 a; \4 @9 CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% u# z# B% E- r" W! iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! U7 {( {& V o1 b/ O
MCASP_RX_MODE_DMA);" n0 d: D) j! c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ]* V7 I1 t% t, y. O, T4 k" o# KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, b9 m- N2 |( p5 C/ D a& ?$ JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! O( r( I9 A8 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% k4 d& N w0 l. h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 q5 ]% J; K. I" g7 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 E% a5 \; ?( g1 A4 r2 AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. e$ p4 n% e4 M0 L" [' cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 L1 {: K' i( u* D* l7 Z3 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 L0 P8 P/ R& V6 P
0x00, 0xFF); /* configure the clock for transmitter */# b" ~ Q! c- w3 N& I3 g: R; X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# x" I8 {7 d" Q2 _; G& E" Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . c: q% e; K& S7 q7 H. G6 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- e& x8 W7 U3 G5 u/ t* T v
0x00, 0xFF);
$ Z# [+ v, R1 {$ M2 F( D* |0 H+ D# O. H+ z1 s
/* Enable synchronization of RX and TX sections */ ( M! F- [* ~% W6 x/ R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ d6 G. x, q1 W* r' W" RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- |1 x% J' `# ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: r; N3 f1 w8 H) h4 W' ?
** Set the serializers, Currently only one serializer is set as
% P& y2 H8 _% l; o+ d! i** transmitter and one serializer as receiver. x' b+ ~; X9 X& X" Q& O
*/; W5 c B( V2 K& g# ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# K0 L, z ]* F T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 ?5 q/ L+ J" n% W+ x** Configure the McASP pins
: d. t% y, i# c6 B7 L: K** Input - Frame Sync, Clock and Serializer Rx
9 c4 q9 Y3 R$ D/ m, G$ l: x** Output - Serializer Tx is connected to the input of the codec ( p7 y) T! M0 h5 L, j
*/, _% E& ~+ b' s$ ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# S3 C, a7 W4 \* G! `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 m/ a2 v) p7 S; q& {( y2 Q* SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, P% h' a C( q& i
| MCASP_PIN_ACLKX
! o! }. z7 Y2 m4 E C| MCASP_PIN_AHCLKX6 m9 d3 V4 x1 M5 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! i; l( Y, Y3 x- D' P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - t4 ~) ^1 P7 S9 d/ G6 z- W
| MCASP_TX_CLKFAIL 9 ^. C0 B' A# `; e" u: ^; G
| MCASP_TX_SYNCERROR
, H3 L7 m0 g: X. d. Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % J- N) M! D5 v. i; x
| MCASP_RX_CLKFAIL
8 d2 B( T* ^% e/ x| MCASP_RX_SYNCERROR 5 ^9 i% ~* b5 b) V0 i9 D
| MCASP_RX_OVERRUN);
+ z) v! \0 F! [1 O3 [& s& B} static void I2SDataTxRxActivate(void)) @- m# B: c( S8 ?4 U0 V
{' W8 k$ E2 T" V% n3 l& t1 m
/* Start the clocks */
}# Q( z6 l; O$ B7 q3 L% i' _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! \) {5 d, g$ t2 J6 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# F- D' Z6 `& F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% M, x% j7 _# [' x6 [2 [EDMA3_TRIG_MODE_EVENT);
: G9 _3 ]5 w. S* hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 u" a8 j$ w( E9 | F/ LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: a+ Z+ c$ k3 p' F# m [9 b9 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 L' ^$ {# Q) o# z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, x: ]/ d) S$ L) ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. O5 h9 Q- Y" ?" I5 R: ^9 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ j$ E9 A1 N5 `# u% j }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 Q! k" |0 `1 x% I5 P A} 8 `* w! u; |% C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 @& w ~4 F3 t* x# T |