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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" i! r" h6 w% o3 d' C6 M; r7 W6 \input mcasp_ahclkx,* A5 ~( C! Y, q/ E& J
input mcasp_aclkx,! r1 R' t& Y4 w3 J0 X7 L3 r: T% o
input axr0,! S7 ?1 j6 X1 T& l
' e+ ]6 F# b7 M b8 j* ioutput mcasp_afsr,
, H; e8 l1 I. u+ J7 T+ Uoutput mcasp_ahclkr,
) U( p* c5 k( O$ j* t2 z: joutput mcasp_aclkr,
) O4 K' s4 |; Z* joutput axr1,
: @* t3 B3 j# R5 z: s# _; E6 U; d5 M! [ assign mcasp_afsr = mcasp_afsx;
# _* ~7 U9 g l! ?5 w) ?) b oassign mcasp_aclkr = mcasp_aclkx;
% i7 j! e& H+ e* h& E+ ?- qassign mcasp_ahclkr = mcasp_ahclkx;
1 W2 I+ }3 Q6 U. H0 wassign axr1 = axr0;
, B4 F% M+ I; t/ I* |& a( R
2 u6 z( a9 T* Z$ I' Q! a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( ]# u# G" `& _. J& {3 ]static void McASPI2SConfigure(void)
% ^; @# ]; h; d) D/ ?" b( N+ z$ r, \" F{# q: |) g2 o. j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 _% \5 F5 \# p( ?3 x/ I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. ], }: V" G, B9 w% O7 J1 o! B% o0 O+ tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ \" a6 a6 O, z f6 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 p( W+ u1 j. t' ?: ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 K2 f( }4 B3 Y" F# S& N u
MCASP_RX_MODE_DMA);
2 q* D) r; d: [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 k" J" N, o& k! m0 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 H( h/ ~; @8 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, Q8 b" ? Q. a, c, P! u7 D! X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: b! L' r/ R7 m& B/ V( V' J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; x7 k' D% ~& c& K7 c! }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& G% ~6 Y! q+ M4 N5 p, n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* b2 _" P1 |3 Q$ l0 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ?7 B; `* ]% v$ j& V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ ?9 F8 N3 i l. g
0x00, 0xFF); /* configure the clock for transmitter */. s+ k% t: G' Z0 U1 c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* V) s4 R0 Z; W! wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& s; [, }. `8 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- I6 C/ e# }; s5 `( J0x00, 0xFF);! O5 S* l: ~3 n0 j/ _: h+ v. P
' H; ?# c0 t) h" ?/* Enable synchronization of RX and TX sections */
( A/ r' q2 W6 l `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 D' Y; I( g! T( h1 W, q6 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 v2 F& i. s: N- n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 n6 A* S) n# X& p
** Set the serializers, Currently only one serializer is set as
* c2 V2 x. A9 \) c, z% P0 J** transmitter and one serializer as receiver.! J1 u5 ^/ ?" L& ]% q
*/
, J; g h o* \- X! S& [- {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 L' K8 W9 \1 e2 G w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 s2 r! ]/ }7 H
** Configure the McASP pins " o( K4 N4 n5 m% t
** Input - Frame Sync, Clock and Serializer Rx$ @7 @+ Q& G0 y7 ~! Y; D1 T2 x
** Output - Serializer Tx is connected to the input of the codec . r" `5 y; E1 {5 D1 x
*/ s! |9 S6 D; m) S4 d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 Y J4 O V ]- N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 K6 L- F* k2 E7 D4 }& ~2 _$ {5 F tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
\, \# t8 [- y/ C7 r! k1 @& E, i| MCASP_PIN_ACLKX! {! U i3 r! Q8 k3 E' r9 H
| MCASP_PIN_AHCLKX: L' i; d$ ~5 a+ B' F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( G1 x G2 e& i0 }7 N! Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ |9 W, q# F: c+ M( P P7 {| MCASP_TX_CLKFAIL
. t/ [: \2 ~& e% T: {" ^* q| MCASP_TX_SYNCERROR
% w5 }" D# z& X* R4 v T. J3 v0 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 j C, w8 X/ K: ~' p$ W) H- _| MCASP_RX_CLKFAIL
; |* U' Y7 S7 ? o/ n( T9 F| MCASP_RX_SYNCERROR
0 m4 J3 X3 r8 T+ H: R& F| MCASP_RX_OVERRUN);
' r1 W7 [1 H; f/ _" M* g} static void I2SDataTxRxActivate(void)6 |' w) q* `* I2 j, q: r0 B
{
# ?1 h+ B: ^8 p3 U/* Start the clocks */0 y, j- ?3 O; r4 Y& W: t& K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% i- d7 `* L" x/ |. W2 A }/ s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 S" u N3 F+ G$ \; Q5 {7 [" zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& ~8 \# |0 S h1 `" SEDMA3_TRIG_MODE_EVENT);) y' q8 B# Z" X# N2 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( d, I# \$ V" y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 H' {$ m0 g0 I3 T# ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& U9 g; S9 _, b& d0 q) t5 q# M& E% [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' V2 E7 ~$ Z# a. G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 h! Z( X1 v/ g0 w5 [+ L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ @) Y* F- ]5 a4 G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% I+ Y9 l2 R& ^! r} 2 Q: V6 v9 L* K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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