MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
7 J6 J8 {# @, u# Rinput axr0,

' [: c/ U7 g9 _1 W7 ~output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
( u9 _! h, B, z2 y- h. r( [; l! |output axr1,

assign mcasp_afsr = mcasp_afsx;
3 F3 S7 N1 v- V5 E6 y6 d/ f% wassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
/ `- f' q  j  P4 dassign axr1 = axr0;

5 v( V& d2 A5 t- t9 ~' a( t
$ _3 Y6 }7 b6 _/ d4 y6 B

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# K2 l1 Y2 Q, F1 h1 f4 C: sMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' X5 ^% M$ l& Q" M0 v) r, T% a& e- _& nMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( ^. t6 `) ]3 M" u3 x% ~MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" }) B1 P" V; d) @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" O+ R4 J2 T3 D' G+ dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( r0 ?7 z9 W4 W- IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" O; n( m9 |% ]8 o/ W! z& sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! G# Z4 u  p/ m  a8 D. o* N( ^! l0x00, 0xFF);
7 b  h( [# ], R) c6 v% n6 ?1 Y
/* Enable synchronization of RX and TX sections */
# U) p7 g* k! T+ [8 }6 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 \2 j! m4 \3 Z5 r! _- i6 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
* S& M2 z' i/ l( h3 ]! X*/
! W( x- q7 c# Y# pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 u" L) {7 W9 F% ]2 o. I; AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
; P7 X, n2 E/ l  d6 r! G: w** Input - Frame Sync, Clock and Serializer Rx
( z) @) i" K2 B4 |- U- V** Output - Serializer Tx is connected to the input of the codec
! Y- p5 J; L) M, s$ R  k5 t! O*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. M' `2 F; z' {/ wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% R/ Y4 e7 r+ W  K" p| MCASP_PIN_ACLKX
+ O8 U2 ~9 K5 c- l: s/ V  \* f; S' \5 t| MCASP_PIN_AHCLKX
5 Y9 Z- Q+ `3 I" A& A| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
$ e  g1 I6 ?: `1 ^5 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
4 M: E% j" [. s5 R| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ L- }1 S- {$ X/ q7 n| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
& O: M8 p+ c: J) v# n| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
5 e5 O# Z. K' D* _6 B{
/* Start the clocks */
% D6 X. _5 U2 d7 v5 g5 z3 x9 q  y* ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# B* |  C5 G* Q% qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, s$ E* r# K7 j7 f; j0 o. _0 ?EDMA3_TRIG_MODE_EVENT);
* ^& v. b7 B+ B  AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
8 |1 `$ k7 ?- V, _) mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 G$ L% J( r$ k9 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" J$ ^4 H+ E+ }& nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

; X/ O4 ?3 \9 |1 u