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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 ?' s( M& k/ D/ h- ginput mcasp_ahclkx,: L+ N h8 u; a$ X1 g2 D7 B
input mcasp_aclkx,4 n7 V8 b; }$ E. l" o1 X7 g
input axr0,
y- V, ]$ g: ^3 X4 I5 U- i
/ b. e: J) e3 y9 `* Boutput mcasp_afsr,
, I( G5 d5 j, B2 g) H7 G& ooutput mcasp_ahclkr,
9 r1 z, d# z5 {1 `output mcasp_aclkr,
) l0 O. `! ~7 \output axr1,
0 N! G( I7 M+ P! I) O% Z assign mcasp_afsr = mcasp_afsx;
6 ]- ~, n( Y# j- k4 O/ e: Uassign mcasp_aclkr = mcasp_aclkx;$ J! G- n3 J+ R
assign mcasp_ahclkr = mcasp_ahclkx;
# s7 D$ c x. B8 i5 t) \3 G kassign axr1 = axr0; ( u: E2 ~) ?* g( _+ ~0 g' W
) O. r5 J j; }4 Z5 F9 \2 ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 l8 v- _( ]3 qstatic void McASPI2SConfigure(void)
3 y& G7 X3 j) x5 d* }: T# s6 ^{
- s/ Y3 {2 y" C" X( ? K9 c# fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 M Y8 P- W3 J. t' c6 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 b! o/ x2 U3 f: x- b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 }2 G1 g1 j+ ^7 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 Y V( g" ]0 ^5 F/ }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 d0 v" X& m, y: I9 k
MCASP_RX_MODE_DMA);( ^4 T- S9 u' ~. H! g) x' ~8 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- Q9 v4 n" e6 \) c4 \" R @, i2 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" _+ J s7 `; Q/ p* L' W$ i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# V. a* D c2 N: L7 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% g+ y( I* w9 ?! O9 \# S" n. |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) F. A' S7 [& A* H m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 S% ^. ?/ \6 u/ }! U& M8 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 L: t& r2 S9 [6 o9 L ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 y: f! s6 Z/ V) D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% J8 Z7 ]! w! J1 E% M4 C
0x00, 0xFF); /* configure the clock for transmitter */1 F; Z; w ]" }" |% X$ ~2 p" o: f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 D3 E, z' K' V. c" h" ]9 a7 _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( K8 {! g* @9 N( J) ^$ y d7 t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ Y3 Q+ b3 A( U7 e* c0x00, 0xFF);4 J: V6 P+ p: Z
. ]0 w1 ^3 v1 Q4 R9 z# `8 n
/* Enable synchronization of RX and TX sections */
! f9 \0 s+ }1 T9 n! v- K+ `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// V( X1 I7 V! V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Q# a; c5 z5 p3 s/ q" P; S$ TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 G% `: z2 O( A B
** Set the serializers, Currently only one serializer is set as
' _) j& G+ x) ?0 V+ a** transmitter and one serializer as receiver.. h2 b: l9 |4 N( @" @
*/
. m1 \1 M7 s" x7 s1 _4 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 ^0 P) R B2 x) w7 r7 j/ h8 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 f0 F3 v. g" w- I' K# K
** Configure the McASP pins
* |0 U4 u, ^" M** Input - Frame Sync, Clock and Serializer Rx$ v' O0 V% O: c- [4 E$ t) e
** Output - Serializer Tx is connected to the input of the codec
1 I! |9 b, W) a% O5 r*/
6 L. x/ Y7 _# bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 h$ U0 K# D' E1 E" r& r
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# x0 G- T* d9 {6 JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( E9 x9 w9 C! l S$ s
| MCASP_PIN_ACLKX
1 ?# |2 h) W7 i1 Z| MCASP_PIN_AHCLKX
. @1 {: }; V5 [) M0 p8 u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ b( \3 ^% `2 f, ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 L7 q- k/ H7 D% w
| MCASP_TX_CLKFAIL 8 n+ o6 ~/ s5 k; H8 f l
| MCASP_TX_SYNCERROR. ]5 i8 p. ]& v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( y, I% P z$ P0 A| MCASP_RX_CLKFAIL
T$ ~( z7 l) p, a, n| MCASP_RX_SYNCERROR
2 j) l+ o6 w0 X% X| MCASP_RX_OVERRUN);. q0 ~1 M2 o# e2 b& Y
} static void I2SDataTxRxActivate(void)
% E0 I/ g0 A3 g2 O( y U$ [" \{( n6 x' s% q* r( ~7 L8 h
/* Start the clocks */
- _" ^& a" e: X2 u' jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' t- Z1 H9 N5 }9 ~9 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 g& d% Z) E3 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 H. ~# _5 O5 y/ ?/ {
EDMA3_TRIG_MODE_EVENT);( T. e; y R0 g6 l9 h& r' B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ e: X$ O9 G v) E5 w9 u, A; w Q1 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* U% z4 x3 p& x/ `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" h. X* f4 M; V- @1 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ~+ }, L" z rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 B7 ^. Y8 H9 |! H7 B6 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% S! e; M( F( CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% X9 @5 i. M# N} : {; `# G: k1 A w* v; Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 Y8 x% G6 V, Y7 D: t+ `, ~ |