|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 k+ x. I# x3 ?* ~ T* Oinput mcasp_ahclkx,5 F. C0 O* ]8 o, {" A
input mcasp_aclkx,
c q5 c% y2 c; g7 |. Rinput axr0,
6 i' ]( _% J! X; _2 h; u0 l# K
: x8 A% f4 J! T, J- V- joutput mcasp_afsr,
: N; D3 Z) U& C- K, Aoutput mcasp_ahclkr,
# _5 V4 L [8 \0 z* d9 Youtput mcasp_aclkr,
) |' n: K4 w, @8 J' boutput axr1,
. [/ @* N9 I! Q; |" `! w3 U assign mcasp_afsr = mcasp_afsx;; K, X, Y1 B7 j- F
assign mcasp_aclkr = mcasp_aclkx;
( M& ^7 G+ l! a: S9 A5 a; Dassign mcasp_ahclkr = mcasp_ahclkx;( l* e3 M5 U+ O, X+ h1 K" m
assign axr1 = axr0;
$ h7 p0 _& S! ~$ x7 D- N7 q# ~" v) Q+ @5 ?7 a8 h: z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ]4 H/ u$ o' n
static void McASPI2SConfigure(void)
% w' S& S. ?/ I{" E7 {: t. z" ~3 e4 v$ {. p' o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 M0 M3 p3 Y9 s- j% n! t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 w2 T! u4 G' q) cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( k0 J H3 W8 s& y) t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# ^2 Z: q) m; U5 N5 u( a+ W# gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- s! Q( N( l; z* V6 D% zMCASP_RX_MODE_DMA);8 ~0 M: w- }& \: w" s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 R- J! e( W) l2 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% ^; c6 I! c7 O" z' m* LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - K2 Q5 p* B8 J4 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); ~2 F4 n7 J+ b3 g! Z# w4 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 @" N i- [# \3 `( }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 S0 A6 D G* `1 y0 m& Y: m& YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) o; W: ]% A# O2 Z9 ]$ a" c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! s/ W2 W5 w; R. jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. w; g$ X( G& _' {4 W0x00, 0xFF); /* configure the clock for transmitter */
. T6 S1 |0 C$ O& u4 p; _& ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) K4 {, _+ `7 Y! r# _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + M. i" X1 L$ W* t7 @( o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 ?: \/ y8 h: [: C; L# k0x00, 0xFF);: \1 K- j% @. i5 E0 p& e' h2 T
. \. m \4 d3 w5 k* b7 n8 U
/* Enable synchronization of RX and TX sections */
% I& s4 y$ h& B) xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. C7 } b' p0 G6 \- i0 X0 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# \% J E) r6 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 [7 I4 w. O' @0 u** Set the serializers, Currently only one serializer is set as7 M1 {2 x' y0 _1 \$ g* X* i
** transmitter and one serializer as receiver.5 n" q! B5 }3 w: z- o6 x8 X9 @
*/
8 B% `1 {( i& {! HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" c$ b" C# i: G9 [: h5 N/ |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! u, ^0 D$ X" q3 D3 v# F/ y! q
** Configure the McASP pins # ?! P$ F! d9 M2 F$ B. w' |( B
** Input - Frame Sync, Clock and Serializer Rx
4 H% w6 ]! k8 p) V* f** Output - Serializer Tx is connected to the input of the codec
& W! c# m; h, ?- X% V8 K) e5 \- f*/" o+ [) a) H8 i1 T( P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 \0 u2 P3 [. _. n7 I7 b, Q/ y, q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ }! ]; q+ I. @0 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% u+ \/ d5 i6 p% }1 J6 B| MCASP_PIN_ACLKX8 u1 B! `' K+ C- ?
| MCASP_PIN_AHCLKX9 V% {! j8 L1 J3 C& g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 l5 F) W4 @$ J. i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( S! r& x* s0 F. M4 u5 E: G| MCASP_TX_CLKFAIL
3 K6 `* F/ _! i3 S: h6 |) u| MCASP_TX_SYNCERROR2 K T: V$ u% P0 M7 k( H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 U J: o# V/ W| MCASP_RX_CLKFAIL
$ n+ x$ q5 [/ ?, o% f$ m: l| MCASP_RX_SYNCERROR ( ]( L/ |6 Y/ C/ w
| MCASP_RX_OVERRUN);
$ J3 f S# ^% z1 m} static void I2SDataTxRxActivate(void)
J' z2 c |4 ?5 I& C+ a{
9 W$ [- Y( J1 V4 h/ X) F/* Start the clocks */
- @4 f$ W# v: L8 ?7 N0 k( T. dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) W9 H$ M8 o9 _4 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 z2 T$ w) F% F3 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! \3 L. n& \% d6 n8 i8 a& i
EDMA3_TRIG_MODE_EVENT);
8 o; C. w" \4 ?- k. g, yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , f$ Z7 V, H. n) k; N% i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* B, r3 E# y$ M: a' XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* j+ D+ f- }$ iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: w2 ^7 O1 a4 Q5 \! ]+ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ N! S9 Q+ t8 ]. p7 t5 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- K3 u8 t( q9 M9 E3 d. g; TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# p' w8 {3 f0 C3 m4 c* B2 e$ T: P
}
( Y: E! o7 H( r! t, O; a- @" f5 i. i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ p- h. D' J. a" }
|