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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," A- O7 X3 q& D/ X
input mcasp_ahclkx,
/ V$ a: j# Y3 r" e5 Qinput mcasp_aclkx,# `3 @* D- r& F3 N1 J. {# R
input axr0,+ C+ N. U1 w( ^; |$ X% ^
: m# ~8 }$ y) O8 A0 Z3 h0 N& Koutput mcasp_afsr,
2 L/ o! e2 r1 T; p3 \$ moutput mcasp_ahclkr,7 P w% V" B) g8 X$ V; O8 s+ u* C$ J
output mcasp_aclkr,+ C% Z3 R* a `: u
output axr1,9 g9 ~7 b7 d+ p8 s" K
assign mcasp_afsr = mcasp_afsx;5 t% i+ ~7 t) P6 a% Y. { G
assign mcasp_aclkr = mcasp_aclkx;3 r# n3 U2 n0 i3 y* X( C" m
assign mcasp_ahclkr = mcasp_ahclkx;
j, }/ y! O. A |4 N, Gassign axr1 = axr0; 5 W3 C7 D$ l& F; w3 J9 X' F
5 \2 [0 c' Q" O, y5 e3 m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' o* ?" h* A) A, V8 A4 l
static void McASPI2SConfigure(void)2 D" v% q' m3 N9 `: ~% u1 T- f: N
{1 `$ T; J" @. C8 q2 j7 U$ n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( s/ k! _/ _: y3 Q" K5 b7 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' u% ?' U8 _. h( @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 l) F6 V; S+ @9 Q1 ~; D$ | A+ m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; A' q- {# U/ C8 p8 N ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( _3 {9 }1 r4 p2 PMCASP_RX_MODE_DMA);
8 u6 f- l' ^6 M8 t3 P/ @4 i- RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Z U3 h" Q: G$ a7 w& ~/ Z+ Q+ Z4 fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; Q# W5 T; ~0 Z3 u3 T5 b6 ~% tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( f& C4 w7 L0 A. `0 r# R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ]2 z6 y! `: V# \" q. G: `" FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 g' v$ z! Y, I. s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 M9 R+ U" f7 ?' dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) e( O, E" l/ Z' X, Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % O* b, U- p+ s3 y' h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- c9 W6 p/ N1 \' t3 W
0x00, 0xFF); /* configure the clock for transmitter */2 u7 A1 x- D2 U* Z& {, N( @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! h2 l1 [$ v7 v# F* z! xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 r& j8 f* X: r" d+ E7 @& n; o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 C5 w+ _$ y' g; g5 B
0x00, 0xFF);* k/ A3 i8 ]6 A& E F
( X- X* j0 E+ M5 b. n9 f- n/* Enable synchronization of RX and TX sections */ 5 J* B$ g! U9 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
g# V u, @3 t! g; p8 ?4 C: v; jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 i+ E8 f. x8 @7 E9 ?% ]0 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 o0 Y6 _ U3 I5 g0 `
** Set the serializers, Currently only one serializer is set as
; A% L& X: f+ N5 P** transmitter and one serializer as receiver.
L6 _. o: F# H) u& ~*/3 s. |2 b: T3 g0 `! X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ n! l" R7 j4 P5 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# g& Z' {, h2 s3 A6 e9 u** Configure the McASP pins
4 Q. U4 O: w4 F** Input - Frame Sync, Clock and Serializer Rx9 y% D, R. U7 L- X( D/ Q( a
** Output - Serializer Tx is connected to the input of the codec y8 ?( E( H6 j% n
*/
3 e4 O- E/ n6 F1 X7 m$ C# mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( P g* ?8 F: y; H: m+ m; [* S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# E# V" z6 P! e1 T! V& y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ o' q) [" v! u- ~| MCASP_PIN_ACLKX
& q. e0 ~2 ~6 X4 U t% L7 @- E2 W| MCASP_PIN_AHCLKX6 I$ I, c$ X9 R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" F) {( r. i$ x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! K) D( b( S8 a& l5 I| MCASP_TX_CLKFAIL
" J/ \1 {" n' `' k. v| MCASP_TX_SYNCERROR) ~+ u" r/ D9 v/ a8 X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% w! J$ k$ F2 ]0 y' I/ ^7 X| MCASP_RX_CLKFAIL% P% g0 ^$ @& Q
| MCASP_RX_SYNCERROR & J. A/ o/ a4 b r7 Y1 y4 B
| MCASP_RX_OVERRUN);* ~( {+ j6 |; e! p8 a. B9 H: N5 J
} static void I2SDataTxRxActivate(void)+ L9 J& Q! R: O
{8 d: ^/ f$ v' F
/* Start the clocks */
, _" M% d$ K% r; qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' S& N1 r" L- r6 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
z6 C" t2 g d/ X6 B) a+ tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 q; A, @' ?) B# g0 L: ^EDMA3_TRIG_MODE_EVENT);4 C/ H1 v# H3 v& H. I# d; I. C5 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 u) _9 s1 G2 y# k' _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- D" T3 s* Y/ M9 K0 j* ~ ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 \) S/ @: m: }" g3 |0 x0 s z/ ?; u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, k6 h G2 O- B( U( s) _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ Z, o' x z% F, @" r6 B! @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ A6 I; Q9 Z& q. F+ }) d+ _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, U' r0 \" r* v} ) W! ?3 p# v0 H# o! C, t, n& r) z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( L7 c& t& S5 H+ i/ j& j/ u
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