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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& ]" A$ r, g1 C# ~. E
input mcasp_ahclkx,8 [. h! A2 k4 O' z, W! ^% {
input mcasp_aclkx,
, `2 E2 I% S N7 ^; a: ninput axr0,
3 ?8 u: O, x" B u- Y. z5 d5 K0 V
output mcasp_afsr,3 K2 Y$ o/ j/ g) ~2 ]
output mcasp_ahclkr, H0 [% G5 M7 E# ]7 F4 r, Q
output mcasp_aclkr,* B3 N0 l* r, }* o. w- n) {; D8 X
output axr1,
, w! c! s. ~/ }5 @) e9 V assign mcasp_afsr = mcasp_afsx;9 f; E' m8 \6 ^+ Z& W1 m7 R C% U
assign mcasp_aclkr = mcasp_aclkx;; X: I& ^/ v1 U$ X2 B
assign mcasp_ahclkr = mcasp_ahclkx;
) z" ~/ G) [$ k* v3 y Lassign axr1 = axr0; % Y& m4 G, b9 Q# q ^8 c) e
* h3 O- L3 o4 Z+ T- T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* `/ S# ~# ^9 w) l8 ]. t4 {$ {static void McASPI2SConfigure(void)" ?+ \2 d F, U/ V3 B$ P9 m0 `
{3 \ S7 W2 |8 L, ~; p6 [+ n( `6 k6 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 T$ W1 g. G/ B# L, cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 `" [% ?( h$ P2 w+ D) G' j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 e7 K% t+ R! ^! v) Y/ b2 |" j/ YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 x4 U% u+ ~2 c, |* `& m# }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) P. T. v, K- T% x
MCASP_RX_MODE_DMA);/ Q7 J9 w2 x" X+ f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ _) ]. `! f# I! C. T6 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 e5 s' e: \+ S/ l* j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * ^, r4 {( {, K: s- w, ]) r; ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; d% }' z) R! d% oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 f N0 Z' o" a0 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 h' T- N, G- V" q3 t: c; L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 X% n8 F6 H/ o1 ^+ _1 V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ z: U7 b) p( E0 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% K) m. r5 B# j" |( D2 }
0x00, 0xFF); /* configure the clock for transmitter */8 D( v; z& [* i! {5 j* Q3 Q2 Y& s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. m9 {6 z* d5 o3 T1 ~7 P9 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; L8 m8 M: |! g6 f3 x4 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 y. h9 X7 z' A' u
0x00, 0xFF);: k0 b- _1 x, g, S6 X
- _& @6 B& v( _7 g" C* G$ B; N/* Enable synchronization of RX and TX sections */
( g0 W: I. [7 q# ~7 AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# [! ?3 q1 \" f5 x, f/ ?. D/ @3 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 z9 [ |) L1 t+ I- F# h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** n+ @) d6 \) V: Z' T/ x
** Set the serializers, Currently only one serializer is set as
* `5 @7 @3 |3 N2 C# [6 ~** transmitter and one serializer as receiver.
1 L6 E- S; x3 A% M*/7 Y: q: _( ?, ?9 b/ @- M. Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) i- f1 ?2 @. J$ u( b- YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ W; T+ ]1 M0 T; \7 J( B** Configure the McASP pins
5 U1 ?% @" w; _% X. B** Input - Frame Sync, Clock and Serializer Rx9 J) W7 }5 S8 ~! M* R
** Output - Serializer Tx is connected to the input of the codec 6 }6 }6 B: D2 \
*/
# p1 O& z- W( I" FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) q5 {2 k2 ~: j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. a; u+ r; Z. y( k, \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; A2 ?7 e4 b" l3 J: L1 ?| MCASP_PIN_ACLKX
3 R1 W5 x; o$ i1 i| MCASP_PIN_AHCLKX, y! v9 v6 w& B2 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 b; X. ~/ g/ EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 D+ }8 t* g) L2 ]| MCASP_TX_CLKFAIL
2 I( ~' D# K- k| MCASP_TX_SYNCERROR/ g& ~. a1 ]: E6 {4 M( ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' P, L& U8 J. ~
| MCASP_RX_CLKFAIL' ~( g1 v/ \: q2 ^8 b# {$ |1 y
| MCASP_RX_SYNCERROR
: v5 \6 P$ t+ q2 Q) j) u% t| MCASP_RX_OVERRUN);
* K" y) C5 i( \- x3 |$ E- \} static void I2SDataTxRxActivate(void): m/ }$ P) i3 g4 x
{1 y6 T1 H: n$ ]! L6 v1 G, f5 ?
/* Start the clocks */
. }8 d, w# j4 H, o& r6 q7 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 R Z8 U- w; o( a4 Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 S' Z. T) O6 a2 y, y. v3 s2 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ g; |! x2 D! L8 E% Y. D
EDMA3_TRIG_MODE_EVENT);- G) U# n* I+ Y% X2 y) O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + J- x( E, g9 y$ u" E' z3 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 Z( p( R# ?. c% BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# j6 q! G$ k' m G0 r- s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ j6 i$ ^+ v- @& J5 p9 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 j7 w: P# P+ U: O+ n$ H+ f: Q4 h. zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* \0 `4 p2 t8 d* {9 [$ R1 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! s7 z6 M0 ~# T* c, x5 t' l}
6 J6 o" a; ^ h" l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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