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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' l0 I/ p! c$ Z% V9 C: E: o
input mcasp_ahclkx,
2 r6 k. L+ k; w5 |/ T tinput mcasp_aclkx,3 r9 h1 M( X2 M! k6 A, j, B9 z
input axr0,
; b( j( m( p% I$ R/ O' d) G+ S" a9 S' Y+ x2 c: l6 N
output mcasp_afsr,( I$ K6 K. _9 O2 m9 z) F
output mcasp_ahclkr,+ Q$ X* D x2 n3 B) i
output mcasp_aclkr,) }' a8 m) L7 \( w" ?& u
output axr1,9 V/ K+ J: o7 N6 @" S, o, F) y
assign mcasp_afsr = mcasp_afsx;
- i& d( v( k2 R& F4 E# Q' passign mcasp_aclkr = mcasp_aclkx;. ]+ B! l- T* n) a+ F8 k
assign mcasp_ahclkr = mcasp_ahclkx;
9 Y& @6 Y6 Y0 Aassign axr1 = axr0; 6 u* X5 g. z- |
) ^$ _( w/ n; Z7 j- p& w- u( U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 b3 A: N* e9 h" G2 G, hstatic void McASPI2SConfigure(void) L+ o! i+ ? p% l2 h+ J5 M- j
{
, f' u$ X: }& K* ^1 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 _/ d L i% \$ ]# i9 P9 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% ]1 z/ C/ r8 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% [# @* K5 O8 g' @( ~: `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* \ h/ l5 d3 _4 {3 v4 aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," h: Z( g* s+ E* R( v# {. s
MCASP_RX_MODE_DMA);
9 P" I% E5 h4 i; ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 l. h$ P# R+ m9 a3 A6 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 b4 G; e4 L9 V9 k! ?$ L( N5 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 R2 n) n/ e4 Q/ T5 `% ~9 u4 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* n! g3 {. [$ h- n3 f( A$ rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; v+ m- {3 ~0 C1 r! C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; X1 p" ]/ J7 S g) DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% b7 X& I0 @1 I! ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 }* T: y3 |2 n7 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: s% j* ?5 a2 t: u- G5 Q! [
0x00, 0xFF); /* configure the clock for transmitter */% J% y2 h: `6 H2 _3 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ J; ]9 w" j- ^' k: AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 z* x+ E7 H' G; h) \ YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ ` \1 b( i2 c8 f9 a3 w0x00, 0xFF);% C1 w, Y0 z2 @% K4 m
1 l! i6 D! t; B$ u: u/* Enable synchronization of RX and TX sections */ q5 f$ h7 c7 i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& c6 |% p i9 B" d3 c5 M' O5 u+ i& cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, ]1 A+ s* J8 a# r& }4 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) W) Z1 w: q- ^' m+ C l2 i** Set the serializers, Currently only one serializer is set as2 g" V2 Z1 l: h5 W
** transmitter and one serializer as receiver.
+ a; q- P } B- z, ^8 N7 q0 O4 q*/
. \( Q& g+ \/ K+ }6 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 }9 S, m7 a5 j0 R: Q3 x7 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** N2 l2 N. B! j5 m! j( b. }0 T
** Configure the McASP pins
* g) Q) H1 a$ W& u' f$ v- b** Input - Frame Sync, Clock and Serializer Rx
' k+ j! q/ i* f* B. f** Output - Serializer Tx is connected to the input of the codec 0 k5 T* q, l; c Q
*/% F4 k1 [4 U" a9 O9 X# Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- A8 w$ h: ^" w+ c# @, w8 N n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( }0 K( |: z# R G$ x1 I# ?. XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- l$ \8 ^; ?+ }) u. l| MCASP_PIN_ACLKX E- c- U# l+ }/ l" K
| MCASP_PIN_AHCLKX |: f: S1 ]! B5 j, O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 x/ z/ Y. `5 M, U1 W0 I8 f1 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 K4 z; d& @ D- m9 ~$ c/ \% o$ f| MCASP_TX_CLKFAIL ( |3 |8 ?% Z" j/ {6 N$ s
| MCASP_TX_SYNCERROR0 H5 _: N d% W/ @3 j# p8 n( E* K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 f" J" {) Y, U) r' b| MCASP_RX_CLKFAIL; A/ L8 G5 c4 s/ S- v
| MCASP_RX_SYNCERROR [- }0 s" c: n5 U* B; ]& U0 Q5 a
| MCASP_RX_OVERRUN);
' F8 t, U! D: l/ W; u0 d% @} static void I2SDataTxRxActivate(void)7 M; I' F. F5 @2 Y& j Q
{ }$ F E9 z S* W* F/ e: C. E" S
/* Start the clocks */: g; z8 }" r1 y* I3 N! D: U3 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' y$ f7 b+ N. x2 cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 p: z& E& k; v2 r C: }, f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ O, j% \3 n* tEDMA3_TRIG_MODE_EVENT);
) @) s# s0 t `- \% y* aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, U9 R$ S4 V- o* A5 b+ PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, {" s4 `# i& [' ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 X, A$ w7 f; F$ p6 m: m% dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 t( T, U8 J5 c/ O+ Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; s( B5 n5 T; w3 H3 i5 U$ jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 q0 M0 x( Z/ t" L4 c& }( ]" j1 r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ a7 Z9 ~2 R( c9 m& N6 O
} 0 `/ w* m- h+ E5 {5 [, b, r" H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. p0 S4 S6 H0 _* b
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