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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 H1 z, U0 A3 ?! g5 j" B
input mcasp_ahclkx,1 o7 L5 d8 u& d% X& u( T) N) O4 d
input mcasp_aclkx,
& i! s D7 K% T1 H3 \) I) v+ P; ?input axr0,( K' @- v% u( y8 U% [! ^
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output mcasp_afsr,3 o6 x: ? s' Y _/ g' m6 p; n
output mcasp_ahclkr,4 d* d! `. p. k2 S% g- q
output mcasp_aclkr,
4 L% }' G3 X6 P/ aoutput axr1,& H$ Q. x8 V( ]! h5 U
assign mcasp_afsr = mcasp_afsx;
; S% w u! L! h; E% Bassign mcasp_aclkr = mcasp_aclkx;
0 F& X" e9 q* K( hassign mcasp_ahclkr = mcasp_ahclkx;
7 ?7 [+ b6 }8 G& Y. S' lassign axr1 = axr0; % x7 Z' O/ Q! t M7 Y+ k
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' J% F4 ~0 R6 a& p% {# X7 n$ ]) F, zstatic void McASPI2SConfigure(void)
' Q7 n* C( t) S/ n4 i$ d{
, P+ I- v6 I$ t& v# E% H4 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ^3 P3 o! c% O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& B* S, w3 R/ h' C, OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! }- q* J' i) i; U$ b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( |" _; ]4 a0 L7 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, K1 {* L5 B0 p! r- F9 u" { P( o
MCASP_RX_MODE_DMA);' g9 u! V/ Z: k4 k. `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 l9 H- X. [0 i) uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
Q2 }. M4 V+ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 g7 i2 W$ t2 _1 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ s) a2 ~) [; y6 c5 X- j$ uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, G9 { O8 A6 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* B1 i* _8 k% s9 ]( T& u$ [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- }0 ^- ?: |6 \2 ^* e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 [% Q. n/ Q/ }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- s3 K, u1 A7 B8 ? x
0x00, 0xFF); /* configure the clock for transmitter */0 t s8 L: Z& B' t+ X: ]; ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 i1 i1 b0 M& M% v% \McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! n" F7 T* U# |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, t7 G+ h8 c0 H0x00, 0xFF);
: Q( V" T- Z" x% n, M
; I) P- ?# l& h ?8 T) r/* Enable synchronization of RX and TX sections */
0 {1 B3 ^) v. L* m C5 a6 AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 j1 Z" g# R. I) GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, @/ Y+ e$ `& |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* H* E0 v: n$ K$ y** Set the serializers, Currently only one serializer is set as x6 S0 [- @+ u8 h9 G
** transmitter and one serializer as receiver.
* b, q. p9 ^$ j*/# s# G) l$ R6 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# Z" v8 A, I7 U' f# r, oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* j6 V' x& C& P7 I& T/ R. y2 A- G** Configure the McASP pins 6 j! Z1 T* p. g& [, B' N A
** Input - Frame Sync, Clock and Serializer Rx
: K' c, v5 W8 D2 D: A; h2 d** Output - Serializer Tx is connected to the input of the codec 6 F. c# L+ O R- Z% u2 W
*/* s& a5 P) }8 L# [ e' D/ Z7 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 g+ N- r4 Y! J9 I5 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% q. Y! W0 R" p nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! u4 ?4 a7 F( d# _' C7 t h* ~| MCASP_PIN_ACLKX! d, e" c% z D& B/ U
| MCASP_PIN_AHCLKX+ @2 A2 b0 \! }7 Z3 ^. G U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 Z: U' n( z% \6 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , m8 l* p) @$ i2 e/ h
| MCASP_TX_CLKFAIL " v5 s7 C# M+ x. R Q; c6 ~
| MCASP_TX_SYNCERROR
5 }2 A" Q6 U" x' R; d& h& h$ ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 G$ \- G3 l" L8 a+ T: f| MCASP_RX_CLKFAIL
; X; z4 f& e1 i1 e8 F i| MCASP_RX_SYNCERROR " ~9 h& p! w, L y$ ?( K9 i5 f
| MCASP_RX_OVERRUN);" U9 [ D! L I1 B+ M0 M0 L8 O
} static void I2SDataTxRxActivate(void)
$ C' t3 Z S }) g' m{# N! w2 r t! a9 g3 s
/* Start the clocks */
6 Q( C2 \( e1 u; X; U1 F1 h$ C8 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ]8 ^0 {, `, P, D+ CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 ~# j0 \9 ^( h2 ^3 C9 J9 g) a. _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 J6 ^) {8 h4 C: ^/ _; D
EDMA3_TRIG_MODE_EVENT);
" ]* w! M+ w2 f# O3 b6 `4 U" hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + r4 P( g; O- g. k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ c& ^6 ]- A5 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 C' \) p/ u2 w) Q, q& A& bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 F Z$ D+ J5 H; Y% L k xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 X0 \- ^; M# O" B }6 g- rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" W/ t% X& T DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 D) ~" M0 R7 ]} * E! Q% q. a9 @/ H- y4 c7 |1 \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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