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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% |# D' v2 ^" j% [input mcasp_ahclkx,( ~# N( `2 l) y8 P' @2 X
input mcasp_aclkx,! l; j7 T% r* K0 d0 T6 ]
input axr0,
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6 @- K6 B. X; L- {7 A: doutput mcasp_afsr,
, ^0 F, P) u0 p/ F% ~output mcasp_ahclkr,
: T: R) C! @/ K8 m, J, ioutput mcasp_aclkr,
& A/ Z' |. U( l; g& ~output axr1,2 l; y2 J% b4 i: A( [6 o
assign mcasp_afsr = mcasp_afsx;
9 }+ c$ s/ i* V4 l8 r% uassign mcasp_aclkr = mcasp_aclkx;
9 y; ~5 y# P( J5 }assign mcasp_ahclkr = mcasp_ahclkx;
9 X( ^8 ^1 E& ]2 Vassign axr1 = axr0; 2 d: {0 c% q( ?$ I! x& g3 ?
0 U* ~& r( ]8 D9 s/ t d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& `6 W+ X: b% dstatic void McASPI2SConfigure(void)
7 q: [$ d0 B4 }6 M5 L3 x9 `{ P# J2 E4 Y, d7 Y$ s. _' p4 ^' V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% X* m. q/ W" l% i' d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 V Q* l$ K% a VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, d! J$ L4 @; t s: [" [! SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! I f( h2 n! FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; e! F( G. J, n& W( G* w
MCASP_RX_MODE_DMA);
" t4 B# |3 D* a4 J EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 h2 |) ]- L2 m0 Q# \6 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 X% B) |& ~' ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' u1 t o' g/ [- W# y, [, TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ I% t* O. e$ V# a, z8 v7 b/ v9 w# U3 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) v0 ]! O* M( K7 C5 j# F1 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: M3 P) F0 l' E- G# ^- p$ ?5 e, O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ A: ^+ ]" G4 S V" g3 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% c8 n+ ^) H' ]2 K: \5 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" F5 i8 [( p- Y0x00, 0xFF); /* configure the clock for transmitter */
' n8 `0 }) n3 S8 `" a: Z8 W( s! \8 F$ gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 X* i3 v/ O& [- _. z' A+ ^# w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 M, q: D( f B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, @% O* c4 o" W0 F; q, Z9 U- A0x00, 0xFF);8 c* p( d" Q$ j; ^9 R
% ? @+ l o( O7 i! F& P6 R! D/* Enable synchronization of RX and TX sections */
, l* {5 M- c2 ? V# }+ X$ RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, l$ R( e! z& H2 V8 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 B% I; {- c5 y1 A7 K* ~2 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- }% u$ R; N4 v4 ]: v
** Set the serializers, Currently only one serializer is set as
) U% _( k A- J* o6 l** transmitter and one serializer as receiver.
9 @6 ]4 r' {7 Y: v) n7 d*/
" E, q2 o2 L* {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; f+ y h( N0 G4 Q# N, K+ z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 P* C& Z4 h( z0 I# c
** Configure the McASP pins # {+ c, K: s5 X6 y2 U
** Input - Frame Sync, Clock and Serializer Rx
8 O) N4 o) u3 z& j, J** Output - Serializer Tx is connected to the input of the codec
& ~: i9 x9 ]/ \! a8 J0 {*/
( m5 u! q% K- f) x! w0 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 }$ O" |: o5 c$ M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 b9 ]0 ^! a1 T/ G2 q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ f6 P: \3 e1 N3 `| MCASP_PIN_ACLKX
6 I! l1 e9 B$ Y3 v| MCASP_PIN_AHCLKX2 l* l9 }6 w, k0 V5 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 x) n1 L k' i4 |+ F* c, S9 e0 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' l, x! b; G+ z- ^) f N" H| MCASP_TX_CLKFAIL , o- a1 O6 C. Z8 T
| MCASP_TX_SYNCERROR' \9 j: |2 _) q. W3 P2 ^. Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ }8 Q2 V# p/ `/ P1 ?; t
| MCASP_RX_CLKFAIL0 V! P6 }) I, p2 z4 B# ^
| MCASP_RX_SYNCERROR
: ]+ y% h) C- r4 W| MCASP_RX_OVERRUN);1 L: j) j8 g0 [: c t) m
} static void I2SDataTxRxActivate(void)0 j0 ]3 J) O( e9 o. V9 j5 i1 ^
{( b* {3 ?/ L3 A/ o9 D, M7 q9 l( |
/* Start the clocks */
$ ]% I4 m2 H' H3 f8 ^5 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 C* X5 U. S. |) \" Z! W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& G3 ?# G5 A* j6 \6 k0 b1 D* ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) n0 e8 ^8 q I2 {
EDMA3_TRIG_MODE_EVENT);$ b8 \/ z7 G/ P5 [$ e3 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; D- O! ]7 m3 s( Z9 HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& _' w' ?% s+ \6 i7 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 X5 e% L3 O1 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. |8 w# j9 X& x) B: D9 g1 K# ]* ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. A) j9 K/ \7 h4 b/ }9 g% e7 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( B8 u0 s! s, Q2 V. `, vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 X+ c) _2 q& r* N( ]3 s% P3 h}
0 D! p) ]) [# _ E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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