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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, |# {. ~/ u0 G
input mcasp_ahclkx,
' n( j1 O' I* U, U7 k+ |8 zinput mcasp_aclkx, ~: U' l' G) P' a4 d5 F$ g
input axr0," L5 o! n! L1 c; L5 K1 N2 L
" A# D& j+ P/ C4 ?$ f9 |4 \9 e0 k# ?9 D( Coutput mcasp_afsr,6 a$ ?$ {# b- H4 x" l2 w2 j
output mcasp_ahclkr,
u8 X7 m2 x* g; `0 ?output mcasp_aclkr,
% r- T1 L0 S" O! H: s% w3 Noutput axr1,/ f- f$ S( p7 u/ I
assign mcasp_afsr = mcasp_afsx;
5 {* } v# d/ @6 tassign mcasp_aclkr = mcasp_aclkx;# n# p$ y; q A- A
assign mcasp_ahclkr = mcasp_ahclkx;- F3 c% q) R3 F. n4 B
assign axr1 = axr0;
) [; n* X- j3 {6 ?1 `; c2 p. J! a& z6 B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) ?) ~+ d2 F, Q% L+ Q0 z' nstatic void McASPI2SConfigure(void)
) \( Q4 W' Q ?' u$ @1 M+ r{5 e) H5 i1 ~& q, W2 G5 Y, y/ c# u: b# ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, R" ?# {, E8 u' P( UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% @7 d* b9 o/ KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: a' M& d2 g" a0 ~9 i% x: kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// T2 H6 L* s5 c8 f6 N* X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 z8 q/ Q# B$ F. H1 v
MCASP_RX_MODE_DMA);4 c2 i& ^- e8 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# J' {4 w+ a2 r: `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" g/ \! T% V6 S: @0 V: SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 D. X; D M, A, ^1 h4 w1 E5 _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( Y* k7 @: R8 c0 q7 t# m; z% d( [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - @) X+ {* m7 F* `8 b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 P: b7 U7 }" `9 J6 [/ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& q( o$ @9 I, t, R; u2 }1 I' i6 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
u# V5 M, E3 t4 s- e+ gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ U& O L: S% C7 N5 x' r0x00, 0xFF); /* configure the clock for transmitter */* S. J% Y/ j% o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 r1 `+ B, c5 B! _4 A2 p% t3 DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, j0 v) p o/ g. @9 r$ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 O% J, Z% \0 q2 z( p6 _4 d' W
0x00, 0xFF);
( T# n; Z1 h" q7 J6 Z( c9 n$ @- M2 J: |5 d
/* Enable synchronization of RX and TX sections */ % Y" M3 L* B; [6 q- O. p) t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// q" }8 M( M8 n% I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! B8 l( ?* q7 M" E: m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ z8 [! p: s! \" ]
** Set the serializers, Currently only one serializer is set as
' [0 `- z* q+ |& J" {1 S** transmitter and one serializer as receiver.7 q0 G: T0 A" X9 j$ m3 F
*/9 K7 E% S$ B. ? h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. D0 q9 @$ x/ y( { ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 |* I, v. Q7 W$ \2 E1 W
** Configure the McASP pins
& `3 l$ O S; ]% x* R# p** Input - Frame Sync, Clock and Serializer Rx
" f/ |0 ^+ B, V- O. o% S) H) V** Output - Serializer Tx is connected to the input of the codec
$ E* @/ V( t& |. m*/$ H" F3 S B7 H X! A g: [: H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* s6 ~5 z7 V1 n, Y& p: q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& i% K# t/ s/ s- Y! o- N2 `9 }4 o, |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ~7 ?0 k( j6 l: l' L| MCASP_PIN_ACLKX/ x5 P# C! r2 P# I
| MCASP_PIN_AHCLKX" A# e( b, F' P c: |% b. m4 P' p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 F+ z* N* K; r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 ^7 N3 w7 z( m+ `! P; t| MCASP_TX_CLKFAIL 2 s0 e' J/ m; z
| MCASP_TX_SYNCERROR1 s6 {' d, S5 N) N& M* q0 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 u4 I8 k4 b7 A4 ?) g| MCASP_RX_CLKFAIL
: {, R6 m( B9 P$ Q8 a m/ I U| MCASP_RX_SYNCERROR
; l6 T7 f9 h! G9 E; W7 S| MCASP_RX_OVERRUN);
% x5 j2 l. r8 d: J, A" H+ i0 v} static void I2SDataTxRxActivate(void)5 x. w+ I( ]( d' w5 H
{4 {- ?6 L4 Y6 O! w A
/* Start the clocks */8 K* y: a9 e' W& c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# f& E; b% k% @( B6 D2 WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# s5 n/ n Q. CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" R& u$ J3 z* D6 uEDMA3_TRIG_MODE_EVENT);
1 G8 P0 w K7 f5 b& nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : N a2 i- [0 i+ W, s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 r* Z1 i' H4 w3 e; X- OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& Y. d% t+ ~1 T# N! J9 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// n, q9 U' }5 ?. J" I5 ~* f* h2 K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! Q, h# e0 c1 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ y' [7 Q/ ^7 k$ \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 I) o# q% [7 N} 6 o2 p" g0 M8 p$ B% d8 T( X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " ?# O! j3 l4 e# M& r/ n8 n. W
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