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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 A6 c* f2 \* D! ~- Linput mcasp_ahclkx,
8 }$ M& Q# G/ E; Ninput mcasp_aclkx,! w4 v4 m& v! Z- \
input axr0,
8 O. k1 C! [! b0 Y+ b3 m, U! C. o& Q5 w6 ^& A* `% X
output mcasp_afsr,
: F! Q$ V$ [$ Boutput mcasp_ahclkr,
( L8 E8 z4 E; g3 y. Foutput mcasp_aclkr,# s4 s) n) Q8 @, i6 f& ?6 o- R/ K
output axr1,. J; h, {+ B& P7 r+ o
assign mcasp_afsr = mcasp_afsx;) r5 e; Q0 O+ ~1 \
assign mcasp_aclkr = mcasp_aclkx;$ P; S1 y( V! i1 x3 T; e1 @3 i
assign mcasp_ahclkr = mcasp_ahclkx;
( S" v3 i4 \0 ~2 k* b* U: oassign axr1 = axr0;
3 b) ?; g. [! ~, }+ ?% m+ `
" \6 j5 w6 u5 ?' ?6 y4 Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 j( C. h9 R; lstatic void McASPI2SConfigure(void)7 n# h/ p9 T/ s) D
{; s5 n6 N) S3 x! Q. H/ }) b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. L/ w( `. t, f& j5 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 r1 A/ j, ]# J- Z: Y# s+ ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# \1 ~$ n& y/ @) A& ?& m# Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 K* L) \7 x ]! C6 C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& G9 s* N3 C, ^4 X; P! \" pMCASP_RX_MODE_DMA);
1 w7 H( t. M' z3 K, X( U0 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( s( J! |: p, d8 X8 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 c! a! R6 X# {, `3 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- s/ t# P4 T' gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 x$ i% Q9 F8 ^3 }* y1 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 Z& L" ?/ R- a/ _) b: g6 w# ?+ e6 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// c0 R. ^* W+ d- j7 c# l6 C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 |2 H2 }# A2 I+ _& j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 l* _& q% \8 w# V5 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ r! K8 L. G0 n0 o O
0x00, 0xFF); /* configure the clock for transmitter */
U$ H3 f- L @# f" I8 q, l0 x8 r3 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 r$ G% R& h3 D: U% [2 d l5 c- UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ z* b# R; b0 r; S- `. g- z3 v( iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' A8 P7 Y) h4 f* M9 r/ O: L3 D
0x00, 0xFF);
9 _7 [& J1 Q! P: V+ B3 y& |3 M2 J4 B- z
/* Enable synchronization of RX and TX sections */ 7 L! `. y2 {$ {; W# g; K& e$ c: t3 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// g7 p, L* p7 [ J( J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' ~ G; F( B2 H/ D: qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, b* P( G0 ]; @- h
** Set the serializers, Currently only one serializer is set as
# X: _0 r; x) Y3 h6 R6 b7 k** transmitter and one serializer as receiver.
4 w2 O' P$ @6 W8 e+ E0 D, ~*/, H, B! Q& y% D2 ^- d1 ]$ e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 {. Q! D- O9 _5 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ `* N3 h4 M1 G" @8 k [** Configure the McASP pins
1 \/ P# `- B# I# x9 g# U5 P4 ]** Input - Frame Sync, Clock and Serializer Rx
4 _. M F; `% n5 `0 h E' V** Output - Serializer Tx is connected to the input of the codec
$ Z5 u- Y' Y* D4 q* V( R3 K/ D* V*/1 m5 }3 k8 S. G* S0 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' M0 \4 x/ r$ O# GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! E( J8 T. d/ @$ x/ K3 H' E# m+ vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# {& a; w9 o9 f! U7 A
| MCASP_PIN_ACLKX
! O. |7 K4 B1 \7 V4 U: c+ i| MCASP_PIN_AHCLKX
; J% W" C4 u6 N; l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 k2 p8 b; X( q% v. \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 I4 B. n8 M; v# g2 k( S$ D, V
| MCASP_TX_CLKFAIL 8 ]# t4 Y$ S1 A* c% c+ i
| MCASP_TX_SYNCERROR, ^2 k( r# b. z- ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 g8 y9 X% ~* L! W* |$ j! U, ]| MCASP_RX_CLKFAIL
2 F6 ]7 x0 s* Y) b& [2 ]0 ~2 b| MCASP_RX_SYNCERROR
' `7 @4 P7 B/ o" E$ d| MCASP_RX_OVERRUN);
8 }6 r' Q. R' `! S; f$ L5 E} static void I2SDataTxRxActivate(void)" Z. l) y# |' X/ H; n" G H
{
- @2 H6 h: B: S& y/* Start the clocks */
5 k Z9 B) N5 b5 C3 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. s1 t# H9 e; E7 x! }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) Q" H6 g- X/ P% d I) R* p2 m4 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 v* |! ]% Q2 X5 PEDMA3_TRIG_MODE_EVENT);
/ A: L6 f% L6 E3 N @: g7 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : @& ^" e8 c$ s: d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 @) C6 Q9 w, n3 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' a6 i, o/ T' L3 M3 W& z a/ f2 l R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 @4 M) u$ L5 K) U5 S' I% e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 h& G8 j- N6 A% u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 o3 r" _. B2 Z( L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! k s, s7 p/ h# w+ K l& w} 9 P/ C7 }! K" W8 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + Y% @$ G6 f& g
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