MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
5 c9 ]% {3 R1 k; z7 rinput mcasp_ahclkx,
/ l, I. x1 R9 [, u" [$ V+ Dinput mcasp_aclkx,
) |5 `9 s6 F. T8 x' \' n5 F4 B! Linput axr0,

output mcasp_afsr,
output mcasp_ahclkr,
- E+ T  e, W7 \1 m+ W0 f8 ?5 s2 a% ooutput mcasp_aclkr,
# m; E9 e" s+ Z8 {  {output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

  h- U: R+ K( \# v

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
0 d# i( B, r% e- k5 b( C% a2 W{
2 {+ I3 i4 B. {0 e) o3 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& V8 K* a0 Y4 |- A$ ~, SMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
6 e( L+ {  J3 U6 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
3 q# W3 [1 M+ C/ n' g8 H. VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 X* f9 e3 U- a( CMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 y; k2 Z# H" g) _9 F6 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
: j$ r9 d! ]; R+ S# kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: G1 y, ]: U: T4 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 \7 ^+ a4 U& `  N/ C/ SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 x9 A! O4 h- Q5 R+ M* `. y0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. d% R) E1 o5 A% N, z  w" VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! ^$ }' I9 Y( \/ x7 `! ?( |; x" N% sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ a7 r6 S) k- @2 [. T  Y: d0x00, 0xFF);

0 }) Q6 F2 v- P  h! S+ X" ^! w/* Enable synchronization of RX and TX sections */
% K, f1 t+ x. m  |* y! Z0 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
( s. L& M5 b* ?1 E; K$ {9 Z; OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ K, H2 j6 {6 s  N+ _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
( D# T$ u+ K" ^+ P4 A** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; a9 Z, d9 M; T1 x; CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
4 I" a5 s  \( D1 `** Input - Frame Sync, Clock and Serializer Rx
, y, q. C; H) Y2 K0 c2 p' r9 O** Output - Serializer Tx is connected to the input of the codec
*/
" e& J# n: Z. M+ M" ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# S0 J$ S4 M2 T4 i9 b4 _5 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
; {' |$ x0 S3 S| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
' c( t& x8 V- ^  ~: a1 f7 p; p" r2 F3 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 @, x) B0 C2 T! f- f8 Z| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. Z, `6 w$ P& W' P| MCASP_RX_CLKFAIL
) ~! P1 h" m  v1 || MCASP_RX_SYNCERROR
  J) G2 }8 ?) X7 Z$ E9 x1 L| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
' F, Y" L  ]' wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ f* D( M( @* r& _! r. Z0 aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
4 \$ c9 }0 a4 H2 D" K( qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* [1 d5 F  R/ ]5 ]+ [7 EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ q; z7 M1 V0 B0 [" oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
% ^  W2 r) Z' ^! jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& C; u+ }" D* @7 l}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.