MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
  D9 O$ K% q# Linput mcasp_ahclkx,
input mcasp_aclkx,
6 X' V' k) H) A& |5 S7 tinput axr0,

- z& ^  G$ |& s+ Routput mcasp_afsr,
output mcasp_ahclkr,
! D: o  x5 H' M! I# z. H+ Youtput mcasp_aclkr,
2 g, g/ E$ @# doutput axr1,
! V2 k. n& g3 N) n2 c- e/ P

assign mcasp_afsr = mcasp_afsx;
; X4 s+ }2 Y5 D. q7 Z- Y1 Kassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
* f1 o4 w% z5 G% K( V0 Kassign axr1 = axr0;

1 X: v6 j+ R" l6 s* s
* G( u; C% X+ Z" w

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

% v& J. x9 R2 p* |6 u

static void McASPI2SConfigure(void)
{
. R  h! X6 q& R4 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) Y5 ?) R& I6 sMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
) Q% A3 @% ?# }$ ]7 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 l# `6 y" d' W, h/ p" L+ I3 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
/ c# s6 N0 @+ J" Y! ?7 M+ N. NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
2 G# @) b* }0 Z/ X( \3 @+ v% sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
  c3 @% A% _1 s  j% X( ?6 \: T: IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 |( c) ]5 |8 ]" O' |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; i7 a" ~* |6 i/ F' K  B2 W( `- EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 _6 x; F$ @  }! `# X, NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- x  }$ G) A& A" n5 W) o! FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
  `0 @: ]: Z* r* d( t; UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' b0 W' [* ~# r! g2 D$ [  h0x00, 0xFF);

3 T+ G: N' p& i  ?7 m/* Enable synchronization of RX and TX sections */
5 C0 o* b3 }/ U1 j& `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 L% i2 q- @8 S, TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
6 c$ \" c4 `& }) q6 S5 _' `8 u3 ~3 z** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
. x2 V8 v( b7 Y1 b) y& W9 p: a( `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) D* n# ~9 x7 q$ v4 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ F. K* ^1 }1 q2 O5 m2 Z( x5 `4 [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
. M0 w* g3 i% L( v| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
+ h) Z+ o/ r- j% b- pMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 a" o' W9 ?: I! T9 B7 m) q| MCASP_TX_CLKFAIL
4 h  t6 f; P, o1 k& c! || MCASP_TX_SYNCERROR
' z+ h1 Y+ Z3 O7 F, [| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
* f$ t/ J* E2 S0 p, {| MCASP_RX_OVERRUN);
: e: y- X/ T2 D* P" f}

static void I2SDataTxRxActivate(void)
1 j8 Z: x/ `- E/ `) f( k5 Z{
& Y1 w* J0 h  y' b9 k! X' s/* Start the clocks */
) P- A2 O# a/ c7 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 H% L7 l) o# O! \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
* S# d( Z, e& W( T# F, n3 o5 U7 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 t8 c8 ~$ U7 Y# a% K9 B% V6 p* d) wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
) A) S8 O& z, ~7 i1 p+ Q1 n6 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
# N+ b, _! S2 i0 f: I2 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ O/ y2 E8 N6 z. q5 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.