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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# Q0 e7 M! m: ?8 a) H7 C
input mcasp_ahclkx,
# K0 \6 I* K( u. tinput mcasp_aclkx,1 V/ k$ _( a& Y1 k$ p9 G7 Z0 f
input axr0,% t( C' u! N) M8 V) l" r
8 y+ s+ f6 W- b" E4 G7 goutput mcasp_afsr,# H% ~8 ]) w, y4 b& w2 p% w3 ^: z
output mcasp_ahclkr,
. j/ K2 ~! D6 a& w1 b3 _& joutput mcasp_aclkr,
% F; I3 W: o+ Foutput axr1,# j( L$ ]5 E! T3 Y
assign mcasp_afsr = mcasp_afsx;. z; U3 T4 z4 H. \0 M; u& l. A/ o. Q
assign mcasp_aclkr = mcasp_aclkx;2 x' m5 {) z9 F6 e! @( {
assign mcasp_ahclkr = mcasp_ahclkx;
2 O, ?* M) r) p& f! wassign axr1 = axr0; 5 I8 Y. _" ], q4 G. ^) T
' o: ~+ ?* R/ c/ A. t* g5 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 }, B* s" i+ b+ O* C' Y8 l
static void McASPI2SConfigure(void)) s! N% x) w2 V3 E! u+ `) Q
{
+ C& v6 u4 D0 T* c3 {/ s8 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ ?# }; G" m8 u/ NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 Y' y4 T' h, L3 f$ t1 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 ?* p; [7 P" I. K9 R7 C5 f* `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 [1 M# L ?& h# U6 Z% {! L( eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," l0 \. [. V; x
MCASP_RX_MODE_DMA);
4 ~0 ]* A: r9 b5 n" |: u+ ?; HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! w# O% V t- ~3 @( `$ mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' Z9 P9 i; _* a& ]) T* ^- t. J9 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( d1 o$ y* B/ Z7 W# TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# R, @. @+ W* O t2 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( r, z" U. Z7 I: S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 C4 L0 y7 P5 j; K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# Z [" Q2 J: S2 J% C1 C1 ^8 i- m7 Y: x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% S+ I5 q5 Z+ x2 E& F# }& z8 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 w# H3 F ~6 z
0x00, 0xFF); /* configure the clock for transmitter */
! V' \1 d- I2 x3 W g1 x/ X# }2 E0 H9 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 d, R+ [7 j7 Q1 [% w. ~/ G7 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) a0 A$ [2 l- r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; H1 h- h& w; g1 {1 b9 U9 Y6 L' @
0x00, 0xFF);
% a+ \, Z; E, n
* Q$ R- J: r& b+ }0 d F' e/* Enable synchronization of RX and TX sections */ 8 m% G) y! l( K" n1 d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 Y& f4 ?, d! g9 R. h/ R+ O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
J3 m1 u! _/ q2 X; ^0 Z( I# C( s1 SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 N, L# ?4 k# q
** Set the serializers, Currently only one serializer is set as
( G' s, @4 E/ G** transmitter and one serializer as receiver.
" `) d. X# u$ m+ f6 x, d*/
) ]$ Y1 [' Z! NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ O5 d2 t3 A. Z. G2 Y/ w9 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* f w# @% p1 \- n; G; L** Configure the McASP pins 0 a, C$ F! u9 X( w- L
** Input - Frame Sync, Clock and Serializer Rx7 Q1 ~# g7 s( n" ` o. {
** Output - Serializer Tx is connected to the input of the codec
9 @, ^: T% a3 v: ~' n' U3 f*/- @* |8 s* I0 E0 g5 X( U9 o& [# @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' x: R8 ?# r& T( h! Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 [! p9 w' n! K4 @. uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: K2 o! w" y* V2 ^3 N| MCASP_PIN_ACLKX
9 k6 c# g4 C7 F7 [| MCASP_PIN_AHCLKX
" [" Q# } g. Q& _6 L( k7 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( T4 g% ^& E) OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 g% V0 g2 d: V6 v7 h. @8 B0 `| MCASP_TX_CLKFAIL ( H5 J5 B3 K+ A9 A5 O- X
| MCASP_TX_SYNCERROR
" c( `8 i/ [' B8 A# c: o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR Q* Z: z6 F ?5 b. U0 {4 \9 K
| MCASP_RX_CLKFAIL; [! J5 ?8 A8 E4 J. I( s
| MCASP_RX_SYNCERROR " n# w9 \3 e" X0 b2 ?: B8 T
| MCASP_RX_OVERRUN);
3 N9 \: U1 _: i1 I} static void I2SDataTxRxActivate(void)
$ T; B7 v2 `9 ^) R; h{4 ?# e* L) x2 z# W4 G
/* Start the clocks */
2 P- R3 Z* T( y* W) F( U9 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& w) ^, B7 c: _' @' z- j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ c0 j, K y, H5 O- N& K B3 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 Z* `) K4 P u% n" ^" z; FEDMA3_TRIG_MODE_EVENT);* E9 `" A! {' X2 F7 `8 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ n0 G. Q% }2 `* ?8 J# C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& f# K0 @5 z3 Z# e( nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 S) h7 h3 L3 l! m% W0 Y- [" z7 E4 p$ e6 R; g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" j4 J e5 P4 M9 y3 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ L) |( t( v" Z" ^ I5 t3 YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 H6 H. x1 m3 G3 M+ O+ }7 [; q8 G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; U* Z9 L4 C$ X( |( g0 {} 8 t, F3 o- t' B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. f; z/ N0 R/ K
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