MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
1 ?' s( M& k/ D/ h- ginput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
  y- V, ]$ g: ^3 X4 I5 U- i
/ b. e: J) e3 y9 `* Boutput mcasp_afsr,
, I( G5 d5 j, B2 g) H7 G& ooutput mcasp_ahclkr,
9 r1 z, d# z5 {1 `output mcasp_aclkr,
) l0 O. `! ~7 \output axr1,
0 N! G( I7 M+ P! I) O% Z

assign mcasp_afsr = mcasp_afsx;
6 ]- ~, n( Y# j- k4 O/ e: Uassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
# s7 D$ c  x. B8 i5 t) \3 G  kassign axr1 = axr0;

) O. r5 J  j; }4 Z5 F9 \2 ]

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

3 l8 v- _( ]3 q

static void McASPI2SConfigure(void)
3 y& G7 X3 j) x5 d* }: T# s6 ^{
- s/ Y3 {2 y" C" X( ?  K9 c# fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 }2 G1 g1 j+ ^7 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- Q9 v4 n" e6 \) c4 \" R  @, i2 qMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# V. a* D  c2 N: L7 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% g+ y( I* w9 ?! O9 \# S" n. |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 L: t& r2 S9 [6 o9 L  ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ Y3 Q+ b3 A( U7 e* c0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
! f9 \0 s+ }1 T9 n! v- K+ `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Q# a; c5 z5 p3 s/ q" P; S$ TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
' _) j& G+ x) ?0 V+ a** transmitter and one serializer as receiver.
*/
. m1 \1 M7 s" x7 s1 _4 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
* |0 U4 u, ^" M** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
1 I! |9 b, W) a% O5 r*/
6 L. x/ Y7 _# bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# x0 G- T* d9 {6 JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
1 ?# |2 h) W7 i1 Z| MCASP_PIN_AHCLKX
. @1 {: }; V5 [) M0 p8 u| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( y, I% P  z$ P0 A| MCASP_RX_CLKFAIL
  T$ ~( z7 l) p, a, n| MCASP_RX_SYNCERROR
2 j) l+ o6 w0 X% X| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
% E0 I/ g0 A3 g2 O( y  U$ [" \{
/* Start the clocks */
- _" ^& a" e: X2 u' jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' t- Z1 H9 N5 }9 ~9 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ e: X$ O9 G  v) E5 w9 u, A; w  Q1 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" h. X* f4 M; V- @1 `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
" ~+ }, L" z  rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
8 B7 ^. Y8 H9 |! H7 B6 wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% S! e; M( F( CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% X9 @5 i. M# N}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

6 Y8 x% G6 V, Y7 D: t+ `, ~