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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: R0 o a$ g2 \- W
input mcasp_ahclkx,1 j5 c5 z0 s, M g) L
input mcasp_aclkx,, d, s5 n& L f! m: N$ B! r: m
input axr0,
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output mcasp_afsr,4 u" b9 L+ C) D6 N9 R3 r/ g& J
output mcasp_ahclkr,! J( h1 H+ |( L4 H: u- D# L
output mcasp_aclkr,
" P$ A4 `3 |% M5 o( a4 ~# soutput axr1, j4 W8 L( C+ }" B y2 |
assign mcasp_afsr = mcasp_afsx;: Y. x* j+ n1 i
assign mcasp_aclkr = mcasp_aclkx;
8 G7 i' [% v* w( d% s& tassign mcasp_ahclkr = mcasp_ahclkx;# y' h1 h. L5 `" K3 q" W
assign axr1 = axr0; & |$ @& r6 [( _( r9 a2 Z& c& p
: c3 y! M$ u* N0 R$ {9 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 N9 k4 M4 \! c- C2 m
static void McASPI2SConfigure(void): d; k: p! t) X! i- J5 o
{' `! P- e: Y0 w" K7 f6 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ b" [5 R5 m* Q. A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# ^% @7 R/ m0 R; r- kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( D |) P7 U* G) A- T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" V" g( r! L% cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# A) E0 k/ v) R; c$ Y# MMCASP_RX_MODE_DMA);
2 _! i+ l) J! i& Q4 q& k% }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; k% W0 y/ k8 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* |& C; Q6 b' w6 {9 g# yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! s5 ?! m9 q( E$ BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ C7 c) T& T* O9 m- bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 ^$ T6 h% x" D" R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' R6 V4 I3 H( l! [8 X8 c! d% S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); P6 y) d, D0 |5 J+ N) Y, K' ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " D) D7 k* z0 {4 T0 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 t5 e; |) ~2 ]; W& Q! w
0x00, 0xFF); /* configure the clock for transmitter */
D5 e3 V' u0 G# p/ h$ ~& W" L0 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 @# r5 f5 n2 v2 l' g5 t |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: y8 q! Y& X( TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* P" z; S* B4 L* X2 U7 m- i0x00, 0xFF);8 \. K% i/ x9 L! p; k
2 W4 w, D( | ?5 _
/* Enable synchronization of RX and TX sections */ 2 Y% b1 V6 }' u% ?/ `$ t# F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. B# g, x# \+ }" QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! V- h. {! e- J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! a$ ^# X' `8 j5 w A
** Set the serializers, Currently only one serializer is set as+ T* E; S4 s( L/ N5 K
** transmitter and one serializer as receiver.
7 l/ k# X0 ~0 d( d% k' g; \( W*/8 ~9 d% \( h& C5 K7 q3 d* z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) |, H4 P' w+ u3 N( X* ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 v& s& v# `6 V- R
** Configure the McASP pins " Q( w; U6 G& M0 u% Z
** Input - Frame Sync, Clock and Serializer Rx9 S' W! V. M5 @/ _4 o
** Output - Serializer Tx is connected to the input of the codec 4 R! z( W8 t4 [4 U) U9 ?# \
*/
. k+ R/ `. K& X: S' @& n$ J6 hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) v0 ]) x# F6 ]4 V( F, d% }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: Q( [! z' r g; wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 y; ]% H! U; d- y: _2 }| MCASP_PIN_ACLKX+ s d; [0 h% D( I# R6 o
| MCASP_PIN_AHCLKX3 N/ R" }0 ?4 n' A0 i$ Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ Q7 c5 G; A( r1 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! V' q9 {2 c9 A' C| MCASP_TX_CLKFAIL
* x- p# ~7 K, p9 i+ F| MCASP_TX_SYNCERROR# t8 W5 ] h5 j6 w' I, M/ `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- u$ W2 r2 b" L7 m| MCASP_RX_CLKFAIL
" ~) ^& P7 x- B( t2 y| MCASP_RX_SYNCERROR $ {2 V" r% I5 x8 E! A
| MCASP_RX_OVERRUN);
# J+ l# e7 t: K& o! `3 U} static void I2SDataTxRxActivate(void)
0 t/ [* L: m# @& S{- | {9 d6 w; a) W) ]
/* Start the clocks */
# W* Y# `( K2 U e. p3 T; v$ [$ ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ L9 k, H" D; X1 H0 Y/ q6 |6 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! M# |$ p1 x5 ]2 V1 R8 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," u0 \. b- G+ T- K4 m
EDMA3_TRIG_MODE_EVENT);3 X3 L# V @3 S+ H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* u6 m. O& Z' M' a# V; rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% O E: ?+ |7 |3 w, u+ o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) n6 ?' ?. _% A; S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 Y* }, J' z2 ~7 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 l) y: e0 n! I6 p/ l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 r: ?# v5 V0 z+ F7 x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ T- v9 [$ o/ ~5 h5 L- A5 Z- a}
% |. R7 M, _9 J' X6 o" h+ | @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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