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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' {4 Z! Z6 h3 V2 k9 J7 p$ o4 n. e, A& minput mcasp_ahclkx,
( ^9 q9 C2 b+ x ^input mcasp_aclkx,
* ~5 R' Z- G+ ?; xinput axr0,
4 G; V6 z! z: M4 K- E+ y% T( y& N7 _" T5 P& M! u
output mcasp_afsr,5 q/ A5 Q3 Z$ y
output mcasp_ahclkr,; O7 {( A: @- N3 b @. n) E" z
output mcasp_aclkr,' \/ M+ l M0 v6 T8 j; @, I+ |7 \
output axr1,
- F5 l" Q9 E, O9 M8 ^ assign mcasp_afsr = mcasp_afsx;! D* b! y- a. q4 X; C, n
assign mcasp_aclkr = mcasp_aclkx;' w: y, Q3 \/ G7 y
assign mcasp_ahclkr = mcasp_ahclkx;
& y4 m3 E8 {/ B$ O% `+ Z! Z( bassign axr1 = axr0;
/ z2 c2 K* O' ]9 _' S
4 \+ X. A; H3 q* k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & C. ]% S' q, k8 u, P& m: i* c
static void McASPI2SConfigure(void)
+ p1 K4 U \: O; c; P{0 d0 Z5 v% L4 c& G% d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( ]- v! C% t0 s0 v o; Q i0 B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& ^# l% A' z' |8 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! E, i3 Z: t+ X! A: s0 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. Y3 m3 o% V' ], X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( f" t( m I. y2 ^MCASP_RX_MODE_DMA);
6 F: [# z6 x3 e6 JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 j! m9 Z5 o" t# f* ?) g( U) z% t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# m9 G( I( |9 y R5 G( M4 U2 [# `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 d" B% C* i6 z8 E; r( V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 N x4 K( g, c/ FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 D% {2 b/ i% x. L* R7 z1 }4 J5 _; p# QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. |# `+ l5 E) t: `4 ~/ i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& m$ U+ [' }; Q: n2 |+ A# C# n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 }! ? J3 B5 I$ J' _3 m! o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) f: U- @$ \* ]0x00, 0xFF); /* configure the clock for transmitter */8 |3 H( j( J0 z1 [# x3 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* v! \% X* T+ P3 W/ L, p7 D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . ^1 U3 R* g+ _' _/ k$ Y- ^4 C5 g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 A0 ]3 e) x t" N
0x00, 0xFF);
4 q; R) M% a/ g* J/ l2 M' l1 W' [
3 a2 [, X4 H! ?6 Y0 J7 Y5 I/* Enable synchronization of RX and TX sections */
& P* V3 W9 J1 n) `4 T) D8 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
y/ E8 C q) T* _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' d6 L8 q# v& r7 y" ~4 ~, E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- y4 P. v2 }- g- @& R8 H) b** Set the serializers, Currently only one serializer is set as
3 P' C. _6 P6 G% N1 l) W** transmitter and one serializer as receiver. D" v. P, b# h
*/4 y3 b, B$ Q4 N! P. B5 p$ L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" W) E1 X: H# J' t$ S fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: q* V0 S$ a4 C" P3 ~. |
** Configure the McASP pins
# _, O# Y7 P2 ~, | X7 F** Input - Frame Sync, Clock and Serializer Rx& R, n) W( m* N4 a) `! z" R/ U6 ~
** Output - Serializer Tx is connected to the input of the codec
, D% \$ k/ C) @! m N*/
) L- J) V5 n6 `! o0 y9 u1 D8 j- `: pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 i: Q! ], Q/ e+ M* {6 F- F1 ]; OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, j0 `6 [$ L! n8 M& l5 P) V: X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* W1 \' p1 j( ^- V; L| MCASP_PIN_ACLKX3 ]5 P" ]. x: n2 A) s) F
| MCASP_PIN_AHCLKX9 n. [9 T& _ Y, m. J9 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! U) a9 o5 f+ Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( I; i: l2 q; u% d' P| MCASP_TX_CLKFAIL
* M4 s9 V+ z$ E' [+ z! \$ w& g| MCASP_TX_SYNCERROR- \! l! d; `. F% @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# u1 P& F! M) ~$ I& M/ g0 r5 W" d. q w| MCASP_RX_CLKFAIL
& |- m/ m3 F: S$ S/ n1 f( P| MCASP_RX_SYNCERROR
: K: P6 w3 I" x| MCASP_RX_OVERRUN);7 s( D* c; t* I& Q) `! E
} static void I2SDataTxRxActivate(void)( }* G/ {* I9 h/ {2 F9 y1 O) h
{2 A$ j5 E7 p7 Z* D7 R- c7 k! U
/* Start the clocks *// H# ~0 s9 s2 l2 n# J6 u* F; B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 a, \7 q/ V3 R+ D9 R2 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" l- C p5 U0 o4 B9 d' t/ H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 s+ u7 W" @1 [& g" g7 t" l/ ]EDMA3_TRIG_MODE_EVENT);: ^0 Y1 z9 M: X: X7 C5 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 @- p1 u+ k3 ^) V% V' @# @8 m: \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- o- d+ u$ Z0 I9 b3 F3 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) h% E$ I6 V8 W/ c. n' {7 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 y4 O% o9 v1 w5 o$ s* A* U/ J( X! \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 N% Z, c7 `. t; b: S8 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 D0 S. {. v, O; w% VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 V! ~* g" f5 j; v& T# N7 C+ z
}
: h# v% u: k9 h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 e' \* Z+ B+ N3 P9 U, h2 h9 {
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