|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 K; O/ p+ f8 ~
input mcasp_ahclkx,+ D! E3 ^& ?1 F0 o- i! J' |% L: m
input mcasp_aclkx,
$ m$ l0 ^% k' B# _6 [input axr0,4 z, j& E- ?, ~: ^) `
; o0 q7 _' d4 ^' z1 C
output mcasp_afsr,
! h- J6 a( B- i7 a$ \* `output mcasp_ahclkr,
/ `$ T% s- ^% K5 Q2 s" P5 qoutput mcasp_aclkr,% f1 i% i4 A7 O0 B* G
output axr1,& z) q) H' c$ O* q/ L" o9 u9 {/ E
assign mcasp_afsr = mcasp_afsx;
$ b+ K* i, n1 P9 C' Hassign mcasp_aclkr = mcasp_aclkx;
. J; ^8 n1 x& X8 N- ~5 k* n* ]' e7 xassign mcasp_ahclkr = mcasp_ahclkx;1 @1 { ?6 I5 B+ x. @
assign axr1 = axr0; ( [( N8 |6 J% F" O9 q" P! ^
& j4 N0 X/ q+ l. A6 O3 t, A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 y' W' t) L* m# j5 r9 Z5 @( d
static void McASPI2SConfigure(void)
8 W5 j, H1 X! _; z- G' z% V. ^{
+ F$ R! s! m5 j% v G1 ?0 PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 W5 }. g' g0 G9 P& ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) } F/ w" L" x8 ]8 Z" N0 F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# T7 G0 W# t' ?: l/ E0 AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 S. \$ f2 M0 E! O$ n3 E: U fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: s, a$ B' m. {7 L1 hMCASP_RX_MODE_DMA);3 u0 P- v: Z8 X6 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 s8 A; S4 j4 M+ l8 K" nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ ?; N9 u# H! K! |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : D; L' M/ s* ^; Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ L; i; X) B+ C, xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 E" B! p' M5 f# l/ l0 d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 L5 ^* w* M% `! j' \+ WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ j8 y) s, M( d& e% W: o8 p* s) J- m3 u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); `5 ?0 H3 H7 L9 G2 V7 ~0 ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 M* E2 R4 H" G8 M+ t1 R
0x00, 0xFF); /* configure the clock for transmitter */
4 G8 ^- x- ^1 d% U( Q6 g4 i( qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# ]& U* d4 G9 N% I6 f6 u# _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) q' Y; E, R8 u; }; N9 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 h9 k) N$ N; i7 O- C0x00, 0xFF);
: Z; {0 \6 V! d: o9 Q2 ~! l: H U+ Q; S
/* Enable synchronization of RX and TX sections */
7 y7 m; v" g( _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 I+ I9 n' X3 C/ B% a3 M: | VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ M8 Q7 r, h' Q' O {; n# `& P$ g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, |0 B8 e3 _4 Y2 k6 B; R
** Set the serializers, Currently only one serializer is set as. V5 d* ~9 R% }3 Q9 g
** transmitter and one serializer as receiver.
& a: D9 b2 t2 C% l4 X6 K*/
8 B: |! Y, M! N, L! qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* U7 |5 v2 P2 [2 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) E1 y. d( B, ]+ r8 z: S, c4 Y** Configure the McASP pins
# V5 J& o; {8 }+ C+ m** Input - Frame Sync, Clock and Serializer Rx
" I! b- Y' y) ~$ p) q: \. x9 [1 ~** Output - Serializer Tx is connected to the input of the codec
: R. j- W) l1 V& ]+ r*/0 Y! W2 y) q: S! ~# p* }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ ` B) e% v0 \: u2 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; K6 i# s6 G) O( v' [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 M/ [) X) |5 ~5 {; y+ t
| MCASP_PIN_ACLKX1 z7 X! n2 b g! [4 M2 N
| MCASP_PIN_AHCLKX
; z8 X7 ~7 [1 R/ F+ j/ p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 C; w( D% a: C+ P: R" G1 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- q1 r6 w4 H" O# l2 z) P3 A, J| MCASP_TX_CLKFAIL
) J& e" e3 Z7 z# P* | a+ y8 j; ~| MCASP_TX_SYNCERROR
0 d6 h5 d4 [# b0 f. r3 y: z! l. b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ e6 O# i+ N$ `- E! ]
| MCASP_RX_CLKFAIL
& ]- }- h9 @ K5 d1 ^- ]) @& j| MCASP_RX_SYNCERROR
3 e) H8 k( j. h. E| MCASP_RX_OVERRUN);
2 Y! [9 `$ X4 f: x} static void I2SDataTxRxActivate(void)4 Y) s3 j8 E5 r# Y7 F6 o1 v6 k; n3 O
{
1 R/ B f+ X9 d) R/* Start the clocks */$ V7 |' l" [6 [$ O! ~# `0 s8 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; `7 [- }* b1 F, h* x. R) H' F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 E- c0 W' D4 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, G3 r4 M9 e# u& |& ]2 N* r" |
EDMA3_TRIG_MODE_EVENT);" o4 r* _* W6 ^* H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, b9 f% V- z8 B0 U d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ ~+ g. I$ Z3 [3 c* i& U; K. GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 o. J/ t2 z1 V) k* B- ]# p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 e3 U u% m0 H7 q! t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// V7 V# A, f; y) s: N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
u- l$ r# G- e$ r" L0 P# v8 i, k; dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' r u; Y* S0 W. A- q# @} ) N' W7 Q4 K( X, D! o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; H3 P; q! Q- C. D& {7 \) u5 S8 | |