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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ L3 T0 c: {5 A, o( a) Z+ u2 A2 _
input mcasp_ahclkx,! ]8 I" q6 V2 ?
input mcasp_aclkx,3 P, c" _' w1 N- O) l$ P
input axr0,8 J* H" E- b, P
' [3 e& I3 r$ Boutput mcasp_afsr,
' Q# `/ \- I% Z% L) h7 t6 c0 \output mcasp_ahclkr,
( B6 _- O+ ?8 E3 [2 Aoutput mcasp_aclkr,, G% M) R& y/ f! S5 X# {, G) T
output axr1,; F8 q" U/ K6 z) m
assign mcasp_afsr = mcasp_afsx;0 `' s3 k. a. n$ H
assign mcasp_aclkr = mcasp_aclkx;
9 {& \! m4 `1 j, u0 cassign mcasp_ahclkr = mcasp_ahclkx;
' J5 ]% W; I4 jassign axr1 = axr0;
1 s0 O* B% N5 ~. G7 _0 p
3 c# `+ O) [. ~" r: W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % t3 H* U+ M4 b. ?/ G" J1 d
static void McASPI2SConfigure(void): |0 r* t9 l j; }- G5 Z1 b2 h
{, U6 i% G e, E' L( T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ H( ^) {4 O* l7 |3 {! O+ G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 D- O" Q \" d. ?& XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& i! e) ^- y* x6 A+ e5 N% |9 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ Z" O! Y$ d( T4 @4 P7 F5 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! c, q) q* v! `MCASP_RX_MODE_DMA);
) q, Q- @. G* N$ q8 A; P5 l: ~, BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
z7 E0 E1 f( O0 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" K7 ~ N: T! Q- Q' h4 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; F! i9 ]3 O2 h& n- HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ a7 n8 O6 E7 Y6 H# DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 P* R1 a8 c) Q: M! `/ J. H: \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ {! z4 ^( v) e4 }8 ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& E% o: S" L- q/ _+ ]" b$ y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 B* S; I5 [2 L' _4 X% {9 S& YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! ^5 s5 q( R. v" E
0x00, 0xFF); /* configure the clock for transmitter */6 x; i$ `, R l& L. n: o8 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ z3 L8 V1 H B4 @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: `/ V5 g. o1 @6 T7 R* d9 Q* ]2 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ ^: Y7 }! X0 | w' A
0x00, 0xFF);
+ \" ~6 Z$ h9 L6 d1 ?" L
w" R4 k9 p" X i) _/* Enable synchronization of RX and TX sections */
' R4 o9 w$ y9 v8 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( V; J; Z* A) B$ F. t0 P7 c! U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* F7 q* x) V, d8 [' W6 E! R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
W/ q$ W5 }" c# x& `) m** Set the serializers, Currently only one serializer is set as
- ~* u2 R. ], T+ H! Z' Y** transmitter and one serializer as receiver.
" t4 P# r% B' j+ W*/
2 m6 I- x7 v9 P% P+ vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ v) q7 a7 i7 G; D$ e9 ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( I# h) C \+ Q5 ^
** Configure the McASP pins
. K3 Z, i4 a: x6 f5 C** Input - Frame Sync, Clock and Serializer Rx
2 V2 _9 D, j3 W& ]1 n2 E** Output - Serializer Tx is connected to the input of the codec " b; D: A0 W/ P6 X% @$ W
*/
; ]. s/ e& X& ^9 O5 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 g8 Q8 x; {3 u* a9 Y3 t# ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! h) U2 O0 Y# d( T; c" F7 u8 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- }8 Y% |/ E1 a- W% @
| MCASP_PIN_ACLKX
5 x7 c* p0 \5 @* A: E| MCASP_PIN_AHCLKX+ ^3 B+ o) ~& I) R6 i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ _- D7 l1 m s) AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 |+ o6 I3 Q) ]# ?- g" _
| MCASP_TX_CLKFAIL 3 J- o; d$ i+ k/ ^/ _- m: ^* N
| MCASP_TX_SYNCERROR
2 l3 C( y4 Z. R( h% l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) I5 a5 f0 S, S6 W| MCASP_RX_CLKFAIL
" _' J" h0 Y+ j: d5 U| MCASP_RX_SYNCERROR m2 X5 B' C* B% |$ z+ |' x
| MCASP_RX_OVERRUN);. J- ^ P0 n: {& V
} static void I2SDataTxRxActivate(void)5 X! z" F5 m- g: X d
{
0 q i) C" b. c( p6 W0 O/* Start the clocks */
5 O3 |) c' y/ G6 a& aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 F3 r% g" w, h4 j0 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* M% I+ P( H" R. d9 f, FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% ^0 O }! F$ [9 WEDMA3_TRIG_MODE_EVENT);" u. ]3 s( g& a& Z8 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % S0 _1 d* n9 b1 U6 |1 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 ^2 R/ Y! n9 a0 \8 a9 K/ P4 a' a6 v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, @$ g D4 T7 {/ j9 L5 v% aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 q) k+ ^( d) P5 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: w8 y6 t0 {) X% r- fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% j2 b# Q$ |+ A1 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 |5 h. G5 f# W( C
}
( h7 C6 C* a6 y) I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - i" K+ h5 ~3 H* [
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