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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& N7 p% ?# Z$ G0 e) v: linput mcasp_ahclkx,1 g9 q4 V* g6 S5 a' g) o. n
input mcasp_aclkx,' R+ c) t7 ]3 \1 B
input axr0,
* c9 Q- k# j% {: A+ F" Z" B: b0 `; C7 b, H7 E3 c
output mcasp_afsr,
/ C4 P& w) G: B, P1 l, \7 ~output mcasp_ahclkr,
! s1 B4 M% u+ q6 m. g4 E0 S6 Eoutput mcasp_aclkr,- c7 m+ f( u! B4 c- O
output axr1,
) x ?; F* _# P assign mcasp_afsr = mcasp_afsx;+ p% U! c; i" V8 i% ^% e$ H) i3 \
assign mcasp_aclkr = mcasp_aclkx;
% b! M8 M* v3 O" P9 T0 ]assign mcasp_ahclkr = mcasp_ahclkx;
" O( Y- y0 o2 n' A) f- |( jassign axr1 = axr0; ' l8 N2 L* l9 f; n. k! V2 z) R1 a
/ i- H' `+ K/ v! S5 s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: t! ]0 e0 s- Ystatic void McASPI2SConfigure(void)' l: D' ^ k, y
{, K! y7 r) h3 L1 e+ B( J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& Q3 `6 e' U3 f6 Z0 \* j2 g& L- A; F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 D0 ^& A, m/ ?& S+ `/ c8 H% V; W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
\8 V( A q- n/ i9 a$ M4 e* O0 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& U' J2 h2 v5 G" F3 f4 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 C! Q( j. Z4 `7 D3 v5 `MCASP_RX_MODE_DMA);4 s F) [9 e( |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" n1 C9 Z6 z; c% Z+ w1 T3 d5 J4 t- zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 m1 A, v P: g0 ^( B' y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" @6 h7 D8 ^; ~3 T- b* _: |. ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- F/ e7 h" A$ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, B8 t8 h" X4 q- @3 X' S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, l9 R) X* C6 ~$ _1 X i6 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
e0 y5 A, y9 ?6 z6 \& cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' N% F9 [. t, Y6 [# g: b3 I+ vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 T" l% Y3 j, e; ?' I6 \. s& @+ k4 \
0x00, 0xFF); /* configure the clock for transmitter */
8 g/ s% J; H1 B2 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
d0 a. ` \: Y; G9 l' eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) r1 d. W+ K! J5 D+ [5 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," t; Y6 y: ` _% f
0x00, 0xFF);' }$ s/ {! J( m6 b y* h
, e8 M+ B7 o0 p4 V/* Enable synchronization of RX and TX sections */ ! b; V o* _# m( m2 L4 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, n( x* `- N; }5 u# W$ ?$ X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# L3 X2 b5 L3 _: D) QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 E4 I3 ]2 ?9 y; p** Set the serializers, Currently only one serializer is set as
. I! o5 I1 Q& B- _** transmitter and one serializer as receiver.
5 X) o( _/ F2 S) c1 _*/ L/ q4 x9 S4 M4 a( H( ~8 }8 C! C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 D. `( ~5 m9 \4 x: j3 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 F' V7 S( J% D+ s$ Z** Configure the McASP pins - {; H6 R; O4 ` G. ?7 C
** Input - Frame Sync, Clock and Serializer Rx
0 b* M% ?( R1 t9 G9 [** Output - Serializer Tx is connected to the input of the codec ! I' m: M8 f2 [: Z6 Q
*/9 U* K C9 m" v. Z* R" |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; l$ D5 k$ l* H; c5 m! L( Y7 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ l5 Z/ j( a a/ u! Z7 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 l! z( y$ l1 t3 r3 F- A, `9 ~| MCASP_PIN_ACLKX
2 g/ q2 a+ C# q: q+ F+ v| MCASP_PIN_AHCLKX
8 B/ @* e7 p) S; ^! B) k4 O1 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) C: \% i% x& Q% w8 W+ I, mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 P5 k1 U9 j# z| MCASP_TX_CLKFAIL , b$ t2 W4 L: F r0 S/ t" }
| MCASP_TX_SYNCERROR3 E, c: {. r0 |# C: h% ]% V4 N4 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% d3 ^/ o" N- o" N9 W' m r9 ]* N| MCASP_RX_CLKFAIL
, z- F: |' S! c: ]5 D# ~$ l| MCASP_RX_SYNCERROR / c" _9 F6 Q5 ^: ?3 p
| MCASP_RX_OVERRUN);
: t& q3 b) s, x) G# T2 D% G} static void I2SDataTxRxActivate(void)
, S4 Z1 V1 _4 O0 l% M& D) K{
# m/ O1 {8 z5 Z8 }0 C, r/* Start the clocks */
* Q7 o) u& _, Z! _7 M, Z1 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) B F/ f [, Y- a/ I7 G: _2 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ i" @0 `( U' X0 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' n5 j0 [$ j8 P6 x6 @2 PEDMA3_TRIG_MODE_EVENT);$ Y5 P0 A9 ^$ N8 I$ L2 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# {0 r" J/ v V o: `4 M! nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) A* y5 C- K; Y4 c; h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 G; ]" V' z% V) TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) y/ F d q; i4 a$ l( A2 Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 a; Y$ }2 o% M& BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. x. }4 R: g+ g. v; H v" F( R: G/ aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
n5 I ~/ |# Q: ^} 0 h" x$ e5 l5 v( \- a+ v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # X! q1 u* p0 `; G! z$ K+ T9 B$ ?2 `
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