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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 k; G- }0 u5 ^8 B) n
input mcasp_ahclkx,
8 D! l6 j$ N# l; _4 L/ Jinput mcasp_aclkx,% B0 _! S v" T$ E4 s8 C
input axr0,
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output mcasp_afsr,$ R: y5 T$ j' z0 I8 A' Y
output mcasp_ahclkr,: f* D$ C" ]) F# _7 P' e2 W
output mcasp_aclkr,
5 T# S. ]2 v V1 C. [$ P2 q: u, ]9 doutput axr1,. i6 Y: ^" S/ j% K6 f3 D
assign mcasp_afsr = mcasp_afsx;
/ c; K; K( v% }) ?6 {# \4 |assign mcasp_aclkr = mcasp_aclkx;
$ h4 Z: _# B' w8 C+ nassign mcasp_ahclkr = mcasp_ahclkx;
" [# j2 s) |" R" J& v) iassign axr1 = axr0; ' D; R$ w4 c% D- U
, V8 Y% c0 C/ j$ i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' I1 B: u6 i; P! Q; i7 L5 d1 tstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- k7 K: ?2 `7 D! T" LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ l: \ E1 F. g+ |7 P! o: C2 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- C( _3 n3 S3 b! W. s `2 u5 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 s" P4 B3 c9 `$ tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; Z6 u3 p6 Y% c# PMCASP_RX_MODE_DMA);
. B* r. Y7 s+ }' }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ u5 n; Q2 L" N) v1 p" Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% l) }- {0 T- n* L! E; uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . z8 u% Q( }, p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' T% B/ j, h- a% n" v. M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " Z6 D$ z9 \+ r. E1 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 i( S7 u: |+ z; a6 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" Z$ u5 \( G# dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & d0 c3 F# Y" U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* C" ~& U( @& r" {' h' {8 y- G+ w0 D0x00, 0xFF); /* configure the clock for transmitter */3 {! ^- y2 R9 t( i! `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) k a& m% L+ N4 l5 h& j/ @8 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % b+ |' j# r0 ]( p1 H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) b# Z; _' @: v& ]
0x00, 0xFF);# a! u3 @9 i- ^& p# M+ {. z
; w {7 s- Y& a( t: |/* Enable synchronization of RX and TX sections */ & A) z# h) N7 n6 Z2 ^! W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 M% q" V0 g0 a0 t. b I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( ] p$ L& v$ q+ a0 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. _& ~ e1 c# v& z# A5 P
** Set the serializers, Currently only one serializer is set as
9 x1 l( O/ }, q' N" Z. L** transmitter and one serializer as receiver.2 {8 x; ]- c6 u; C1 m8 E) B
*/3 B4 H m0 K; @ H; H7 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& z( n t$ x6 A! d, j" mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 [2 ]0 i$ X$ |" B& y2 O7 `
** Configure the McASP pins * j7 z+ b$ ?, x' P1 V. A* q- M
** Input - Frame Sync, Clock and Serializer Rx
, o) B& f; b' v; A2 S** Output - Serializer Tx is connected to the input of the codec " r( ~, Q' b& h" e+ m! t5 [+ b
*/ u% S/ t" f0 s8 l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! t: o7 G% g/ E- P1 D' k( M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ ]! |: b2 ?0 l0 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( n1 p4 Q4 u4 U6 n# m& l
| MCASP_PIN_ACLKX8 F3 h8 K Y/ v/ R: F
| MCASP_PIN_AHCLKX- W6 n' t" ^/ M9 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" s' u, [$ l1 ]) B/ \* q) F: n4 o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! h/ m6 w' J" n/ P* b; T
| MCASP_TX_CLKFAIL
3 A* u5 |7 U6 D$ h4 H3 I| MCASP_TX_SYNCERROR
/ g0 o7 v8 _% Z5 Y2 C3 ]* P1 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. p+ N* J6 ^, n% x9 || MCASP_RX_CLKFAIL
; A0 y7 W& b, P. o: a4 u" @' k! m| MCASP_RX_SYNCERROR
8 n, Z3 u+ }6 X" L8 V| MCASP_RX_OVERRUN);$ y. k7 l. D0 I* K& |
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
2 _' r2 b! A, BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: Q+ O$ j; @( K# Z% R0 v4 ?# y( l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 D! a0 }! p+ U7 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 V9 H2 a& X3 ~7 q7 E$ A+ `EDMA3_TRIG_MODE_EVENT);- Q$ z% W0 ?# w: L* H, _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & ?9 \ Y. d3 n+ ^) J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 O: c; x f8 @$ n% z2 ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); \1 d* P9 d8 I9 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 t8 d+ W" T* D9 A1 s, P7 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% X# ]$ N) h: ^& J6 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! Y: P8 q- g* J* |9 r) v0 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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