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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 z; R" Q8 \7 b3 E; W
input mcasp_ahclkx,
4 l' _9 z9 {, y- zinput mcasp_aclkx,# k @) [* z3 @' ^, a- G
input axr0,
1 B; H" ~' q" A# V! V& T z; n! u+ _! d/ Q( `- I
output mcasp_afsr,6 I" \( m0 j4 E( U! y
output mcasp_ahclkr,
# C% W8 \9 a2 ?. b/ T4 koutput mcasp_aclkr,
, R- u5 W4 a8 d, c0 \output axr1,
% E0 q+ H$ `4 i7 P* F assign mcasp_afsr = mcasp_afsx;
; j0 T& y& ]! F# D* W. L! i- ?assign mcasp_aclkr = mcasp_aclkx;
% Z: q. F1 }* U2 C- @1 A8 Iassign mcasp_ahclkr = mcasp_ahclkx;* w& ^! p4 q. p
assign axr1 = axr0; % i8 n* l% r4 g5 z4 @7 d
& a# m8 U5 s/ r' K p" f( ~# q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ?* M8 ^% C. ?
static void McASPI2SConfigure(void)
/ n1 ?4 Q) W" }/ Q+ k# M+ E{
, H* u, x$ H) \7 Y1 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);: O. K# m5 i7 h3 F1 S2 l+ G2 G, Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: d; o& J, o3 _/ P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); V# D% X _$ S7 o$ ^( S4 q6 b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# i1 @+ T/ W6 o9 ?' {0 zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ?& c* p. p5 ~# [ pMCASP_RX_MODE_DMA);
1 ^9 z; W" u/ B) M) L" b3 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: t8 s5 j9 {. x# O1 {& A1 TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- {2 u. r+ a2 J Q9 B8 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! g: |( B" _6 F `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ ]) D3 X% S6 B! U0 \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' j6 m$ y+ Q$ Z' M6 U6 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ m8 {! [ a/ y* O5 _$ X$ SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% i4 B4 ?6 K$ ?* ~1 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# N3 o9 @ z: ~9 Q# i) gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: E: D! ?8 H0 g0x00, 0xFF); /* configure the clock for transmitter */2 G" q. f! B8 Q2 d* T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 K! R. I# N2 f8 p) Z' [, F. ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, l! }7 V0 @/ W' g. i- FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 n" o# r3 \4 l Z& n3 S$ R$ t: T
0x00, 0xFF);" \% }: g u8 U4 S: z4 ^
% d% a: Y1 l6 j, z
/* Enable synchronization of RX and TX sections */
! F" Q% y; y& q b+ CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& B# l% h, D5 L0 H/ X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 S# O! |5 v/ G$ }* |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ P' A0 M! d$ @9 ^# y** Set the serializers, Currently only one serializer is set as
* R/ m, D1 T3 K2 k8 j, B& Y9 U** transmitter and one serializer as receiver.
M& X% f. C* b8 L q*/7 W# T% l6 S% t) K* ?( @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 M+ E) Y: E5 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 T8 y0 |: `. q3 j2 {2 t3 l
** Configure the McASP pins
1 C( {4 C4 Q. J5 }3 p% g** Input - Frame Sync, Clock and Serializer Rx
2 J+ _; e+ O* w$ @** Output - Serializer Tx is connected to the input of the codec
+ k6 A% h/ K2 y. c*/$ O9 H: D+ o4 b2 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ I. g/ [/ g9 G8 R# P- sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 d8 P$ [% R7 p/ \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. r" D- i+ ~ c f| MCASP_PIN_ACLKX; [; Z+ q3 [/ g' g2 _" M2 V
| MCASP_PIN_AHCLKX
# a |+ h7 C9 `1 U1 L8 W& F( ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 a3 s6 c& s* d$ mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 t, q7 \% a& _ f
| MCASP_TX_CLKFAIL
C- R- M: R+ |, d* Q, q8 N1 n; `' k| MCASP_TX_SYNCERROR* [9 Z& w! f0 J1 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 Q$ _. v; x$ I! A! o
| MCASP_RX_CLKFAIL' X6 b f2 A2 X0 X# T
| MCASP_RX_SYNCERROR 8 J- [& y, |2 U) n& ~9 E- G7 m
| MCASP_RX_OVERRUN);
3 |2 _7 j% D7 y1 [. E7 y6 L: U- N} static void I2SDataTxRxActivate(void)
+ F' j! _$ S( H. u, C" L2 ^3 Z! O{, y( K) Q9 d: |+ `: i
/* Start the clocks */
% b% k- [2 i. L2 Y: H% Q7 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ a2 v6 [+ N0 g- Y' I: k IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. I) O' A A/ h Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# i& F" h7 m+ d$ ~4 B- c/ LEDMA3_TRIG_MODE_EVENT);) g7 l3 P! X5 r. q$ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) a! h0 N) r/ f3 g$ wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! z8 |$ Q: ?6 m0 ~$ b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, A+ ^* y# _, x: N; B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, _, `6 A* h2 Z5 _$ K, A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 n& x' u. _* M& a% x4 M0 E3 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ G4 {* N }4 kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 S) \( ~" H3 `+ m6 S}
4 B8 a; I8 [# O; h; Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & }9 \5 F5 e+ \! g) D% G1 I& C
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