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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 i$ o* h% p1 B0 H0 N/ {input mcasp_ahclkx,4 U [$ m+ @' O
input mcasp_aclkx, F0 j' ~' a% F& p7 [. z, x. b
input axr0,- W6 \; _3 T! X9 W8 c7 {5 P
) E4 G4 i' E+ M8 Loutput mcasp_afsr,# `8 C+ Q( m( U1 s! {
output mcasp_ahclkr,7 M7 a$ S, h5 E3 K: X" G
output mcasp_aclkr,
! E/ w& ?6 }: q/ {4 m; Eoutput axr1,% n- u. l" a5 w
assign mcasp_afsr = mcasp_afsx;
" U$ C6 O3 O9 k3 Z: |assign mcasp_aclkr = mcasp_aclkx;9 H% @! C9 E3 I; e+ w0 P
assign mcasp_ahclkr = mcasp_ahclkx;
' n( A- {( G4 xassign axr1 = axr0; + Y5 W e& v& r( C7 A4 i
: h7 ?- @. @5 c5 K3 h9 W; W9 t+ S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 k* a$ k" g% {0 f
static void McASPI2SConfigure(void)
; c9 B; I% e7 n) K3 W$ K5 Z" t, f{
v( Y' l# @8 [/ L5 \( \8 n. zMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 _& m2 E8 Q" C0 ]+ z; VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 D. q6 h$ g" X5 ?1 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) m7 G" c. ?6 X. t0 f5 E& a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, z' t: e: {1 e% f9 j; D' g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: d4 V, b {) B0 S& T# F% ^MCASP_RX_MODE_DMA);
; Z7 i3 ?+ I" [# cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 i0 h. X) a# W8 E; ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" J, T! E% s2 Q7 o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * l( d. F# y' r$ [" |( `- b2 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% R) O2 \0 i5 A4 X! `( Y: mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % W A/ I `' E" d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 N* T% y8 g1 o* {" \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, N7 b" C5 n* q7 \% s- O$ p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / a8 t# n: H0 v9 C& P, J4 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( z2 b+ v6 W1 _* @& |' s0x00, 0xFF); /* configure the clock for transmitter */
4 w' k; C- `% {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ v$ {" U& I) ], _/ g( V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 s9 l1 U+ q0 K* B8 v$ ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; M3 S8 D- G: f' K* Z1 X
0x00, 0xFF);
/ F/ _; z! _9 [% j. `5 h' A" x/ _! }. l5 U! c9 ?4 l; q
/* Enable synchronization of RX and TX sections */
' x( @9 B0 J# {. i fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# {) U( Y) {# Y, nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ R# [. V/ q1 j l" SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ?# l5 D- ^# Q6 z
** Set the serializers, Currently only one serializer is set as
1 P4 t2 i# o6 E s** transmitter and one serializer as receiver.
. m& g4 |9 ^9 Q, T: c9 N*/
( ?; V l( k$ r, D; MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); l, r+ c" V+ d% F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% k6 i: E1 f4 B6 A j** Configure the McASP pins
8 C( T) B2 u/ `' B# n/ u3 q** Input - Frame Sync, Clock and Serializer Rx1 @' p9 x& l' z& z
** Output - Serializer Tx is connected to the input of the codec ; [- ]" `& q: h% Q
*/# m% G/ C4 a. b: a* f. n# Y% a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ }* O4 L; g+ `( S8 A4 N9 _0 x/ m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% [! Y" s5 [9 F4 @- R% CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- m+ I9 d0 G' W; J| MCASP_PIN_ACLKX
! m6 x6 M: w" T5 S6 ~| MCASP_PIN_AHCLKX
: u4 Q% b7 w! j. o6 D7 E: [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( A. b4 s3 N& O2 R& ?4 Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " @ `8 d8 }: b. y
| MCASP_TX_CLKFAIL
& @ }& h1 \; s* g$ R& b: Y| MCASP_TX_SYNCERROR
5 V+ R5 g% i, _) q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) h& T- V f1 a- V
| MCASP_RX_CLKFAIL! ]. T; | H: P
| MCASP_RX_SYNCERROR
* @7 O0 t5 b: f| MCASP_RX_OVERRUN);0 k1 o4 |& H, r' ]
} static void I2SDataTxRxActivate(void)% b* e' U3 u5 @2 a5 ^" E
{( d8 U$ P3 S' ]% l5 @/ V" D. F0 A; q
/* Start the clocks */
V1 u2 x6 L# g# x8 S8 e: EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ P( a4 P% s1 f, \# U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: v+ |+ ^( l* O. l) I# Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' g5 [9 O) ]9 l* v, SEDMA3_TRIG_MODE_EVENT);
3 a, D; M$ S O: AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 A% R& D7 p- o5 s: q6 `3 |3 Y6 q% i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 w; V9 _( q* e1 o" @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 |- @6 W. D* R: O4 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) A1 c, F/ H( u8 R7 Y$ h6 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* d" K+ @- E- H" UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 O5 f* c* w3 \$ u- xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ M+ ?( I5 w$ g
} ' I: M- b% U3 P+ _% c& m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % |/ s8 \* I9 r$ L, P9 T6 L W, d
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