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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% P+ Q6 K0 f- e7 ~( vinput mcasp_ahclkx,( n8 Y1 J, w1 D9 T2 ]2 w0 Q" e- i
input mcasp_aclkx,* N; ~& e; S | C8 \1 `
input axr0,
5 r/ i# w7 T" S9 e$ |& [, q5 d& U3 g3 r Q5 `: _
output mcasp_afsr,
3 v! j5 V4 l$ X: q* L& N8 F- Houtput mcasp_ahclkr,
; K8 f3 m/ m" M) Routput mcasp_aclkr,/ G" Q6 p4 z( o& c) H5 l
output axr1, A1 H9 o" P: ` Y8 Q
assign mcasp_afsr = mcasp_afsx;1 W A: z# x2 Y& \! G' b
assign mcasp_aclkr = mcasp_aclkx;: d3 N3 c5 ]# ~; {
assign mcasp_ahclkr = mcasp_ahclkx;
5 |) {3 a, F+ {( Q. }! T( oassign axr1 = axr0;
- ?& Q N, ^7 Z- m( V
) F5 `/ h O8 `3 f. n+ R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 q8 [. H3 h: r$ t4 ostatic void McASPI2SConfigure(void)
0 x* d/ f j8 T6 f# f{& j4 p; \7 T" n" d- H, |6 T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; Z& }, T) y: O5 ?( d0 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 Z( D7 W9 h. r6 g Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; G( H8 a9 H1 O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& s4 m% c# d$ J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 j9 f, ]7 @1 K. o4 S6 ]# KMCASP_RX_MODE_DMA);0 Z0 |2 m: T- P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( Q: ]: V" z; ?: w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 f% q( X1 Q) |/ ]5 I! \1 X. p7 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; O2 L. r! A7 `: f) S- RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& ^: E) R& P E* t' xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, f& a: r3 k5 {' e- C1 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 g% A# m2 |* c I9 R, [( }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ O- B# F+ a) R2 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 t" C1 L$ `0 k! u; `( zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ A: [* L' M5 [7 r8 Z$ L0 o; s0x00, 0xFF); /* configure the clock for transmitter */8 p2 f( o/ u R+ S7 P' ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 k+ O8 m' N1 S8 q; Y% qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& R1 \6 m7 j6 t @1 C/ fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 a f) |$ L& v5 O1 o
0x00, 0xFF);& D! \! z ?1 ]$ @9 u
" H3 L, ~# _: v: I3 f6 k6 A% |$ H D2 D/* Enable synchronization of RX and TX sections */ 2 w8 m* t2 V3 k; k h, J5 o/ {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" D& ]2 @4 N3 p( @3 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Z5 L. c$ b1 Q4 j7 w2 [ \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- Z2 S! ~% ~! o: K6 m** Set the serializers, Currently only one serializer is set as
) u" M' `6 O, b3 `** transmitter and one serializer as receiver.
- Z+ n* |) t# p: t1 R) a7 m*/
% J/ Y) r! F5 N4 K9 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 j% M. k. h7 d2 s9 ^5 P( [5 V' G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, f. @' w8 ?1 q** Configure the McASP pins
, ?- m2 i M4 P; p6 D** Input - Frame Sync, Clock and Serializer Rx1 p# p5 Q" r& @) W) Y
** Output - Serializer Tx is connected to the input of the codec
: ^0 t$ e' [! b/ i$ P; P*/
9 T9 L0 A, H# q; rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: g. a+ s' O) j* L+ B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# n* I: K/ Z) ^$ d" a! tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" v3 s; T* t' \$ }
| MCASP_PIN_ACLKX$ X# u1 C* o) d. M8 w! q3 w: E/ Y
| MCASP_PIN_AHCLKX
# c/ s! R: A6 S* s3 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* J+ a! I4 D& W! AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . {* ?$ P; X$ @! f; _: }6 X
| MCASP_TX_CLKFAIL
7 x7 z5 Q# R. g# N/ y1 J" o| MCASP_TX_SYNCERROR$ {9 |$ t; @: l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' Y1 E6 U" _, s7 T L Y7 \8 s5 o
| MCASP_RX_CLKFAIL
) a9 ?8 s; u/ ~2 e1 T| MCASP_RX_SYNCERROR " Q' B! L+ W: F: M7 w: i: G
| MCASP_RX_OVERRUN);
; `8 R4 K2 A% `& {} static void I2SDataTxRxActivate(void)* \# r" E) h& e9 v; G6 u, g$ l+ e3 v
{
% t4 I4 ^1 v6 r! o/* Start the clocks */
' h2 g( N) W" gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) {$ [" a: {, F3 y9 u) i- p+ f$ \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ @! ] q2 i: ]4 ]/ H( aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," |, F: O# r2 d+ m
EDMA3_TRIG_MODE_EVENT);
- [) O4 V' u& k# `1 Z. j* W0 Q4 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 D* Q( w0 p, R$ S4 x; UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, J; V' z$ ^2 Y: E& Z7 |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 b7 G! G* g# i3 U; d; I5 |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 v& D$ |* d6 R6 f0 p* O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' h( C3 `, f3 P0 |0 L$ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 t3 `, Z9 s: b0 J4 n( x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 f0 m' [- s* [! l$ g$ i+ |
}
! W& j- O a8 H* c0 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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