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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 S; G' X0 Y# L2 O/ h& N2 b& kinput mcasp_ahclkx,3 e ]8 P( J0 s4 l
input mcasp_aclkx,' K* @, C' j- E
input axr0,9 x, H/ b' c5 t( T& V3 M
4 m: ^8 j$ b0 Q5 c
output mcasp_afsr,! e& h6 W6 [" T$ a
output mcasp_ahclkr,
" a# X1 i/ z& r4 Boutput mcasp_aclkr,
, Q+ V8 u) F4 N- H0 N; y7 \9 m. m0 E' Boutput axr1,+ k6 B% ~, e/ H! @/ x' p
assign mcasp_afsr = mcasp_afsx;
, |( Q- n+ _" z6 @4 J1 d# Wassign mcasp_aclkr = mcasp_aclkx;
% v0 E! M. O9 ~& Q6 aassign mcasp_ahclkr = mcasp_ahclkx;6 h" p( k& Z( C' d
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 R) ]4 y( b2 X/ n
static void McASPI2SConfigure(void)
2 K" ]* t$ E6 A0 _( d j" B5 ~{
; ?6 h9 @) y9 a1 p* z8 p0 c. mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: [4 _& G& B- O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% Z, ?, n6 D" p+ J$ _1 q7 p! B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- f {) I+ R9 l* lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% j7 x/ n: f0 j* ` Y: CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Y2 [5 M7 b( [' T9 WMCASP_RX_MODE_DMA);2 b- v6 L/ Y8 X6 O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. Z0 N9 k1 N. A2 H3 y: U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( a2 t. O1 F% TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- ]' t% `$ C8 a: J: G% ~. FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ o. s# W. e. R5 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 O; H1 W. |3 @1 _% _/ v7 S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ a+ J! u* A3 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- o4 J7 q* ?9 x/ r+ l5 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ j2 h1 e4 l/ Q9 w5 i" j/ B4 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 B+ v- j7 N6 I b8 V& G3 j0x00, 0xFF); /* configure the clock for transmitter */$ o6 D! ?* V# l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% W. @, p; t, d6 |- L3 K" s, RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , y; k' i- Y O. o. s) ?$ C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 S7 }! i/ l0 ]2 j4 l. }0x00, 0xFF);3 f+ C, N1 S" n3 o# F) Q
4 V# A+ s( {' r. ]9 ~/* Enable synchronization of RX and TX sections */ $ I! p1 v1 l9 X& g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: S+ S" Y+ A4 _7 ~( |. o( lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 x7 D, D' N' E* rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 @' s/ v$ A7 }+ R
** Set the serializers, Currently only one serializer is set as
* N7 W; _& S! q" [: V** transmitter and one serializer as receiver.$ t! M! [( l& r" f- G
*/
* B( p% l9 ?- z( T$ M, L% EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 [! p8 P' @% `" f' UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 e; s# Q& q9 s/ [** Configure the McASP pins " K+ `9 M" E8 V p `& n+ v9 u
** Input - Frame Sync, Clock and Serializer Rx+ A$ v6 F* u( ~. ^" z& F
** Output - Serializer Tx is connected to the input of the codec / J. O# v: f# a. O# d' B
*/8 ]0 {4 ^0 a' e8 F# S# o: u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 U. h+ Y2 l2 w+ s9 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 v1 H2 J9 K" b- T0 N" J% ~7 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ]( l: i: f2 m' S0 \+ t1 k `
| MCASP_PIN_ACLKX
& k" |4 e/ P$ O6 R& G; ^" {| MCASP_PIN_AHCLKX; a. {3 {: t( k' W8 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) K* W O6 ~, U2 `4 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 p, t) {; l' ^# E) X! I| MCASP_TX_CLKFAIL ' N$ [) G9 @% i3 }! i! Z
| MCASP_TX_SYNCERROR: a( a$ j, R" w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 }* V6 x; R) k; Y1 F
| MCASP_RX_CLKFAIL
, S! x( h5 m/ D) N d# q| MCASP_RX_SYNCERROR
! R+ }) x; p2 I; ^5 F| MCASP_RX_OVERRUN);% ^2 x0 i* J4 x1 j$ c: w- E
} static void I2SDataTxRxActivate(void)
- K4 U+ U; \% G, T{* U4 C" u S( F, @; G n
/* Start the clocks */' U5 w |, r" |% K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 E% { w- d9 y! V6 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ d" A- e% r# t3 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( a& r9 k; Q! l( a
EDMA3_TRIG_MODE_EVENT);
8 t8 y& T! B x# W. oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) Q- \+ a6 N' ?0 T8 p% d' e! hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: j3 C& M2 Q5 K1 ]( ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ t- o2 J( p1 z/ e- @# K- Q% OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 K) C: A( g# i! z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) O: @' B2 A" Q' E7 Z- P# c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 x, a" D9 m8 N# n+ O* }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ y" l) w9 ?3 y. @* ^, n7 ?
} 4 |& y: r# f4 K2 k4 q0 |5 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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