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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 I) B" Z( ?3 y& Binput mcasp_ahclkx,. L N2 C8 ~( t$ N* ~ M8 R0 a
input mcasp_aclkx,
; n( r M, D3 F; y( tinput axr0,7 L- e- I6 N& t! V' p3 C O' t- N; D d3 Y
# z$ {$ g0 B& z1 ^output mcasp_afsr,4 d" f u2 m/ `+ Z8 o
output mcasp_ahclkr,
7 y# f) B! G; [3 F( v( ~8 n5 {output mcasp_aclkr,
% r4 j. ]- }5 h: m7 doutput axr1,9 b/ R1 A5 u' I* D5 [* S
assign mcasp_afsr = mcasp_afsx;
# U& c% f2 z& [. a7 }8 l: _2 Wassign mcasp_aclkr = mcasp_aclkx;
) T% f& N& F8 w0 }' Bassign mcasp_ahclkr = mcasp_ahclkx;
# m5 Z0 E& Z n3 ?assign axr1 = axr0;
/ c! C6 p' ]- N4 B' B
: H' R; Y9 g1 `/ U, B: t: S0 {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * U' ^8 Q# Q& f. ^7 I
static void McASPI2SConfigure(void)
& Q0 w. b+ K2 e0 n% q8 C{8 D' d ^1 z1 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& c+ A3 g0 l# [1 E4 I0 i' MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" W& l3 Z8 a+ [. M- PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: A3 \( [+ W6 v6 n& T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 r+ L5 o9 e- U' B" i% H$ n9 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ~9 c" i& s' _( O" _/ A D
MCASP_RX_MODE_DMA);& p, p. w7 {. T6 k" ]- J+ g; f$ L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: K+ T. O8 W* v j' _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' Q4 h1 Y, N) N: {7 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 P c; x6 {. @% T* [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ K+ i6 }7 d8 OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ b3 y8 e" |4 {( }; rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ A- j2 p* e1 s9 s) ~# j9 x; P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. r0 w3 p2 F2 {$ N; L1 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: \. m6 O' ]& Q. M: }5 l+ y" eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( @$ [6 `. T2 K$ S1 c
0x00, 0xFF); /* configure the clock for transmitter */ c3 t# l! l, J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, S3 n) o4 u- K c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 D$ B m1 k, U, \9 W; y% mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 {" K! h" l2 n' u2 m7 ~ b0x00, 0xFF);/ l+ q* o. Y0 B7 l, I( u* Z+ E
$ z. o7 x# y& I3 V
/* Enable synchronization of RX and TX sections */
1 d4 l8 y( S- ?+ lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 |" u! }7 X* g7 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 c& V' X8 z7 y! j1 l6 w- P% NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ N0 R" |9 B/ f; ?! @** Set the serializers, Currently only one serializer is set as, c8 U: H9 R( P, [5 x
** transmitter and one serializer as receiver.+ k8 Q' |! |- h; E4 T4 n
*/
- E2 H6 M' l6 c+ @! O5 ^% [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; S4 T; G) G. K7 g% D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( M' Y" B) E5 t! k
** Configure the McASP pins
/ g# H. {( g* L$ k6 R; c** Input - Frame Sync, Clock and Serializer Rx6 s' K) K& r; F% C. V
** Output - Serializer Tx is connected to the input of the codec
# V: I8 B. Y7 y; @8 ^*/
3 g/ x" _% m& B; hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 V* e4 R& S6 W; m" g( CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 q4 v3 P. Z1 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% r$ }8 C, y" D% ^* I; D" X' y| MCASP_PIN_ACLKX/ D. p! p& @9 J3 b! N1 t
| MCASP_PIN_AHCLKX
3 l0 ^9 K# f( ]6 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! V7 C$ l( O! T8 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ O: j& n6 ~6 d3 t) P/ D| MCASP_TX_CLKFAIL + s+ i. k {* l7 x' l
| MCASP_TX_SYNCERROR
" b1 h# L1 `7 \7 a* N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# F3 h+ N, X2 O$ o, F$ G! s| MCASP_RX_CLKFAIL5 `# A4 D5 b5 J. A& T! R+ M* V) Q8 \
| MCASP_RX_SYNCERROR ( F) T9 ~3 Y; J; t, T2 S2 Q K( ?4 Y
| MCASP_RX_OVERRUN);
6 a7 o. k! J& b. p; y" B* o8 Z0 L+ J} static void I2SDataTxRxActivate(void)0 ?8 |8 t$ E9 N& o. V# o- V. H
{
. R- ?3 e% M: s$ x/* Start the clocks */
8 d- s1 _* H/ x* n/ kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* B: E1 C6 b$ H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* J+ H, y8 F6 {) @0 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: N) b$ P$ f$ j# VEDMA3_TRIG_MODE_EVENT);
- D/ m9 L. g/ e1 S3 Y% e% P' DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 `- N; K+ B8 n2 d( b5 {& Q& m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" w% [6 Y$ \" Z& i9 T1 I0 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ y8 E* ~* D. x7 C x- d \# Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 w$ @; v r2 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ R" Q0 l, U* g+ ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" W. o- t" d/ ~3 @7 A$ Y: w. w+ \. }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 v4 Z n$ X4 B} ! ]& h1 i# y+ y# |4 S' T$ S. f; y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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