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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* a& O2 ]* |# x/ G
input mcasp_ahclkx," S2 W( w K- ?8 x% R
input mcasp_aclkx,2 n( i n2 _9 o3 [( S" f, r( G- k
input axr0,
% b p! s& k+ ?: V- i) r4 i* Q1 B. T- W" D2 o5 Z4 q
output mcasp_afsr,
* S8 _4 o1 k; W' ?output mcasp_ahclkr,
$ }0 a$ V7 c: d# woutput mcasp_aclkr,. {) g* @# n2 R0 Q& d4 o
output axr1,: ?8 H- A2 z: E6 ~7 ?' }
assign mcasp_afsr = mcasp_afsx; f R# H5 Y! v, I% h# _( G8 Z. |
assign mcasp_aclkr = mcasp_aclkx;
/ V# C0 q9 M4 b$ f0 s6 qassign mcasp_ahclkr = mcasp_ahclkx;
$ n' D$ ?! h3 Dassign axr1 = axr0;
5 S2 `$ y) E* D8 [) {+ _
- f6 b5 g7 B9 I( V7 [: _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , Z8 _8 e, o/ W
static void McASPI2SConfigure(void)7 i1 _6 a' \2 r2 b$ y* X/ I7 q& J
{
7 Z0 t2 A; Z9 r; h' e( [McASPRxReset(SOC_MCASP_0_CTRL_REGS); G! \$ e( P" R% n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% ^1 z9 e! U4 [- X5 S( B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% D, a2 U& U% H7 d9 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ {! u* R- P2 ]! J2 I& |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 |* Q3 r6 ^6 X# a2 N8 y5 ~
MCASP_RX_MODE_DMA);
( a) r3 s6 R2 ?: ]- j5 e5 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( P5 E) [ ?1 ?; o2 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 }5 j. G# v1 i: t* i! P* ~# ]! oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ Z( m1 g/ s2 T) z( `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* I5 ]% W6 x- W, H2 b: L8 b6 f% m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ w a% r& A+ D/ y: g; k- ~ \2 ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, j6 D; U$ I* JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& C+ w A& q4 J5 ^7 ^ s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" e: }( g- n7 B, a0 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* ^1 J/ x+ G- W" ]( n0x00, 0xFF); /* configure the clock for transmitter */* H0 v. F6 G* t V$ C; ]. x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) b9 |$ J% ~ N! L5 {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) O( }- E% u( [) ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- M: M( J4 F5 X* n6 L
0x00, 0xFF);6 ]/ t, S* R+ `0 H. ?( y( m
& d1 ?5 W% F2 d& S. s& y7 \
/* Enable synchronization of RX and TX sections */
. R% l3 k" ]" z9 g% l1 J- NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
e7 Y* s9 u3 S7 I. g/ p% T3 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& a- D& H1 b, U' |+ ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 D* } z1 H: c** Set the serializers, Currently only one serializer is set as
$ [2 T2 d& q5 }7 ]* v** transmitter and one serializer as receiver./ M& T' a/ Z7 N% W' [
*/
- R" B5 D$ A6 ]. z! zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 C" O& ^! s0 r* o% o! o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ A# W" |0 C2 G( g- e) [" g** Configure the McASP pins
7 R0 K6 g& m$ n9 T** Input - Frame Sync, Clock and Serializer Rx
7 s8 W' a% Z+ M) r** Output - Serializer Tx is connected to the input of the codec 6 J3 A4 Y, j6 a9 I
*/
; Y* Q6 K+ D; x' dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! x* N; b- t- I, b3 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 Y$ F$ S0 p6 H# HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ r \, r% i% \+ I5 B% ~4 l| MCASP_PIN_ACLKX
, @: I6 q5 }3 B( I! [& E| MCASP_PIN_AHCLKX
. g. `" }* _9 D$ y" \( a6 }7 `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 |9 p/ \# d, mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + X& z2 `* D; J5 h2 C( P/ m
| MCASP_TX_CLKFAIL
8 r! ]7 \( l7 H* F+ j w5 U| MCASP_TX_SYNCERROR
; l7 ]" P9 n9 P* `+ H* z/ R1 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . e x" X( k9 _2 @6 k& H
| MCASP_RX_CLKFAIL
, N$ S# d8 h6 J, f1 m| MCASP_RX_SYNCERROR
$ {9 ?+ m0 @; M8 I| MCASP_RX_OVERRUN);
4 a2 l5 Z& [; |' J' K/ S} static void I2SDataTxRxActivate(void)9 `) n2 ~0 w' i$ @! W
{
. O* ~& R+ g8 h& e. r- z& `/* Start the clocks */0 Q r6 J; ?9 Z1 L$ O& N( P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 \$ J& M( Z* S6 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ A$ ?" t' i' \3 Y! nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 l z; F5 c3 o( ^& HEDMA3_TRIG_MODE_EVENT);5 q$ d2 H/ u$ q! z; P* W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * m& B" A# E+ ~( I$ O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! E/ V6 i% A! r( @8 `, I9 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 d3 }/ N5 X: f7 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, c2 ^( K+ _0 M o5 s7 {* Y1 H; A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) S+ u# _4 ~4 t1 A0 D, d2 C- E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 r S2 D1 q v I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! H3 j# g* N, H; o+ U& |5 b7 I}
o9 a, Q) X# e2 m$ L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * U6 ^" s6 X9 o
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