|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 z& ?* ]4 g/ w0 _1 I/ V3 ainput mcasp_ahclkx,. q- m% t B+ ?- h
input mcasp_aclkx,1 O. j) x& D( @# a6 V
input axr0,
$ D9 X. H% W+ A# }5 c) G( f1 U# _% g* s6 x' y: j& \. I
output mcasp_afsr,
+ p# q+ Y1 W2 Q uoutput mcasp_ahclkr,
/ ]4 _" O9 Y3 ~9 F9 ^4 Q: youtput mcasp_aclkr,1 g; v! P7 J: `9 R, p* x
output axr1,+ H L F) ]) q% o7 `; S: _0 p* V
assign mcasp_afsr = mcasp_afsx;% @% q2 @ `' H) t
assign mcasp_aclkr = mcasp_aclkx;
( j6 w1 @( s" ?% k+ hassign mcasp_ahclkr = mcasp_ahclkx; y0 R/ [& C, F4 x, m
assign axr1 = axr0; ! s4 z, P$ g i, a
% ]! Q, K% ?( ?: |; @" d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 k% Q) H+ V+ A& Q& X6 o8 Ustatic void McASPI2SConfigure(void), ~9 \! d& D+ r& i0 f& \2 G' t
{
6 s1 ^3 D/ @% k* J2 z4 x) W. W' u. xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ i- m7 p# ]" h& V: j- E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) m+ D; p, U; S: d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, A: Q; I. w3 e/ _& `: t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& ? ?8 [) g- Q4 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 L' X+ S6 Z+ w8 s, \6 L" U% iMCASP_RX_MODE_DMA);
8 l* r1 \+ |! Y+ G7 _5 F. hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' D X7 {% x5 L0 o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, b, [; y; n3 @) L5 X- x) s7 n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 N7 Q* D* e4 ]- |( P4 G& F& M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); ~2 {8 {+ S! {7 g0 n; d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ h, ]0 d0 S7 t$ M5 H. pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// k& _3 ]9 E9 J' v' v2 ?! t) U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ ?+ q* G; R6 F V! K7 J% l2 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! X( a' U! I( h4 `9 I7 y4 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' G5 J# s- [+ M' T* R
0x00, 0xFF); /* configure the clock for transmitter */
( T- I% W* W0 _6 X) s8 C0 E- }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% x/ S2 v: S9 [% V$ Q( nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 L: R5 c2 f: j9 W2 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 l* W8 E: a J/ Y) A7 g! f0x00, 0xFF);
- k7 u E2 [7 c- U! X% l9 P0 T3 S" }0 Z) e' q1 E0 {9 k7 z; E
/* Enable synchronization of RX and TX sections */
9 s5 `, G; W( T- e4 c- i1 AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 L4 Z& |$ D2 Q4 @ X# NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 n5 M3 r0 ^6 S4 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 v+ F/ H5 c9 X! S
** Set the serializers, Currently only one serializer is set as1 g" R1 Z7 `$ ~& w+ R& P
** transmitter and one serializer as receiver.0 x G; o6 P1 F6 k* ?
*/
3 W; t/ V% z" x: jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 }+ A2 e# y3 Y! I1 O$ p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 r* C- @+ {9 O$ m3 c** Configure the McASP pins
! W ?4 b: r6 b6 K+ n+ E! M** Input - Frame Sync, Clock and Serializer Rx+ E" q' a G! O/ d) T$ k, V, x
** Output - Serializer Tx is connected to the input of the codec
$ Y( \2 E, O8 v. {2 x& |/ O*/5 A, x* H; T8 K9 K. Q! n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) N$ M1 F9 X! H+ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 \6 K c2 m1 J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ X" G! j' G, E| MCASP_PIN_ACLKX
" W7 q2 U' V6 s+ f/ a6 ?) k| MCASP_PIN_AHCLKX5 s# R6 X8 m$ j+ l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 `% C+ C$ H+ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% T L/ _1 V. `. ^| MCASP_TX_CLKFAIL $ [1 v- D# M) r8 \
| MCASP_TX_SYNCERROR( q$ b6 _! c% B( P0 u7 v9 @7 s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ l( d+ M3 W& S* p! ^! h4 o| MCASP_RX_CLKFAIL# Y- ]( f8 o- O6 m3 K6 D; Z6 C
| MCASP_RX_SYNCERROR . P" s {, O1 T! y
| MCASP_RX_OVERRUN);* b+ N8 ]2 R4 I2 E1 _5 x/ b
} static void I2SDataTxRxActivate(void) }8 T+ c; j/ Z, Z n4 v7 k
{, U- P! M9 }4 S. ^5 |% T
/* Start the clocks */
. B' K- Y2 B2 X* kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ c3 n5 U+ o, V% @2 ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: t4 E! O. G. X) o2 ~. i) E2 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' a6 I6 W& @. V5 j# T' [EDMA3_TRIG_MODE_EVENT);
1 h' v* h7 `6 `8 ?, a# LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + N" R( R, z- j& B5 L3 Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ U b& r5 ?$ E: X: UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! b- q5 @! h+ V6 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# z0 ?& [ J. v. r, n" n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 [( j9 o& _; P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 Y( U- s$ t+ U' F% aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 K) f; e! i3 y3 m1 a}
( R3 _( I4 I+ f2 ^; ~& j1 }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; }" w5 D* J! F" m8 x! V5 Z
|