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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 n( z) z4 B+ o% L9 Ainput mcasp_ahclkx,( _& C* _! S* Y8 I! U5 _/ }* x, Z
input mcasp_aclkx,5 c3 H2 `# A7 g. s1 V
input axr0,
" v' x+ j% f- y x
* C: {+ e( U7 x% C Houtput mcasp_afsr,: F' k% I; E/ l% y7 n- o: r
output mcasp_ahclkr,0 X% `0 [( ~5 o+ P# y1 }5 R
output mcasp_aclkr,6 W8 E& k, E: r# | j, ~ W
output axr1,5 q s& {% u+ [+ B5 L; M# S* s, q
assign mcasp_afsr = mcasp_afsx;
3 ~3 @% p7 N2 yassign mcasp_aclkr = mcasp_aclkx;
/ T% u- u, k8 I% H1 P tassign mcasp_ahclkr = mcasp_ahclkx;9 d; Z3 \. k: T
assign axr1 = axr0;
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2 {8 H6 A: s- K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( c; W# s$ X9 A# Q* t
static void McASPI2SConfigure(void)
' o3 P' t7 P0 p{
0 N1 s4 Z. u! aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) H) X2 x, F) P5 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- l6 c/ T7 t9 s8 H% [9 E/ ]& uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. J3 W3 ]% L% J& J/ f" m% W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' l& a! ]* h( ~7 l, A% AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% i* K6 H- E: _4 [
MCASP_RX_MODE_DMA);
, ^6 x. _6 d) Q+ A# r% f" ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ C$ ^4 A4 ?" N! F- hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* n% e# c: k" e% WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( q' c1 r$ w/ x* C4 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ a, }5 ?+ K+ g1 K, i [( y2 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 z& r1 Q0 a: n8 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- X4 d8 c& P1 }, z4 U/ ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, V# R, z0 w, K* ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 I) R! }+ O. z) M7 i, w8 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 T" ~$ b. Q# Y' Q( {! V0x00, 0xFF); /* configure the clock for transmitter */; U$ R7 e- V o: |* s; P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ e S: h2 t8 B( n+ G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ [5 E( W: k0 N: ^/ l7 c' k9 `% UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 H! P/ m2 O8 x* `0 g! K! n0x00, 0xFF);5 ]6 `3 U' a% p8 S! o
3 H! b" p" W! b8 C7 R* T; j: W2 t' Q/* Enable synchronization of RX and TX sections */
" {0 N7 Z$ ]- B! SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ h2 R7 z. W* t3 u8 H& @( dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 U0 z* I" n3 h1 R" |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 U) o9 f1 j1 m, k, Z+ y
** Set the serializers, Currently only one serializer is set as6 i0 t* N% h% e* H0 s
** transmitter and one serializer as receiver.
6 m# l" b6 G* z*/
2 Z! Q6 F* }9 J. G& RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# J- O2 d. m! J( R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! h _( m" U% B0 l** Configure the McASP pins
5 ]9 U* ?8 T, W( M1 ]& M** Input - Frame Sync, Clock and Serializer Rx
, R! R' Q+ V; B% E- s' Z& C** Output - Serializer Tx is connected to the input of the codec
; u% `" {- [5 n% c*/
, c0 t; R k! Z( d3 d2 R2 L' LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ f; h/ r$ c: u* n9 s9 c3 SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ V' u) z- k1 e" A4 `/ u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' t* L- _9 r* T/ }" q" |4 }6 m
| MCASP_PIN_ACLKX
- w% C1 G. ` f, V+ |5 K( w| MCASP_PIN_AHCLKX6 h1 Q. F; |! O# ~+ Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 J% x2 m$ M2 L( dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . X7 {" Q9 Q0 M1 x$ X3 I
| MCASP_TX_CLKFAIL 6 _% `: }+ C+ ?; ^8 e* W D u4 ~
| MCASP_TX_SYNCERROR
+ g- V8 p! j# d4 } b: w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 Y3 q& Y8 `: P: |! S' p+ J& K
| MCASP_RX_CLKFAIL y) n. f$ i* T4 w) C
| MCASP_RX_SYNCERROR 5 a4 @ Q& ~/ I
| MCASP_RX_OVERRUN);# Q7 z# v& Z1 C2 p9 u/ E
} static void I2SDataTxRxActivate(void)
7 f. U7 m5 }8 e- k; n0 E2 \# z{* t: V3 M( r5 i0 }% L$ T
/* Start the clocks */
# _" p& h3 A* ~1 x% ?1 _" v1 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) u. q; _' E- A- z' _! F5 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ i3 R" l, a- i0 v: f g. @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 G; |" a% w* Z* r, u. }
EDMA3_TRIG_MODE_EVENT);1 n# Y5 S$ Z4 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) U* Y& E+ n) r' {5 m$ J4 m5 R& K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 B/ b5 L( T) i+ O$ J0 R% o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" E6 ~. \" ]2 X$ X% }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 e* b9 d' Y) d- n* x3 H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 m' Z5 t6 X% Y6 V" ^2 @. |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' q0 \" u6 ^; d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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) I$ f- v) o% L. f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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