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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. a$ \6 z9 T0 U( ^' r7 Ainput mcasp_ahclkx,, h3 m. y! m1 ~& l9 K0 y, \7 F& P
input mcasp_aclkx,
3 }$ k. x3 M p3 u# b9 k) |input axr0,
) R5 c9 j6 \2 p% t% T( z5 h, V3 V: T! n/ ]# a
output mcasp_afsr,
- c s1 ^8 W, K. N8 ]% boutput mcasp_ahclkr,
/ B, P1 p* [- D$ {' `$ X4 c* i# |output mcasp_aclkr,
+ f4 n/ _6 w& w" voutput axr1,8 l" D9 w; \" n7 z% I% B
assign mcasp_afsr = mcasp_afsx;4 y9 J- m: ^4 `6 R; d7 V" x
assign mcasp_aclkr = mcasp_aclkx;
- }" g k; t! w* _4 \: z; Yassign mcasp_ahclkr = mcasp_ahclkx;0 _; }; O' _/ J. y
assign axr1 = axr0;
; S4 C' V- L9 G0 ]0 a
4 Q! t' @; g) F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 g4 G0 X% i5 M, G2 h8 M, z( [9 \* d4 ostatic void McASPI2SConfigure(void): Z& T6 [1 l. M9 ]+ G! {- l
{& U* {, i1 |+ X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 w/ v. N6 n# u; ]8 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 k: A7 ^7 s2 o+ t3 I- qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! I2 ]8 t1 \! A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 b2 ~) L/ @$ o+ J& K' B- qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 W) \2 h$ Q/ `3 S0 [7 CMCASP_RX_MODE_DMA);5 t( @8 r0 Y$ B3 h* C. {, y1 U- H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( k* h h$ d1 v! n& M x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 u7 C' n9 ? K6 h, qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 D* i5 b \; u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: R8 ~: n. }! l) v4 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 l6 D% X! U2 R! v! n0 E/ @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" \7 J5 j! C: @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 o2 w* G8 n3 q( z4 y+ D) |& E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , F* O# L2 g n2 [& T5 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. k7 y6 j% t( W9 A! N! E, [5 v
0x00, 0xFF); /* configure the clock for transmitter */
$ }; S# j; M& c& a* z h! }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); K5 E4 L. X* @- t, J5 O( `: e/ Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % S6 ^' }( Y7 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. u1 E; [# o ^* b' p$ l) c6 c
0x00, 0xFF);
2 D# E" I* ^9 B: O& q) x1 N
) h i3 n# C2 x. u' E/* Enable synchronization of RX and TX sections */ 9 T& [; x& w4 B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% @+ O: X$ L6 x" E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); s3 u3 [6 n7 I3 ?# g' l9 r- l! Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. } R2 P4 G3 h
** Set the serializers, Currently only one serializer is set as
: `: E) N5 _, @1 N* H, H3 |( M** transmitter and one serializer as receiver.7 m5 v7 D# Y) b1 Y0 p
*/
! a/ N1 {5 k2 X- r* r- A# jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ h" V7 @' W( X `% d6 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 _; S, d" H% o, b; w** Configure the McASP pins 4 w! P- |8 I$ H. o% x( L( ~
** Input - Frame Sync, Clock and Serializer Rx) ` |5 v+ d& k$ F
** Output - Serializer Tx is connected to the input of the codec
( d- e* f+ [! C; L2 P8 I*/
. Q% R. J9 h' P! y5 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 a0 a6 _6 G/ W, x& b H7 V- mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! w& m! r7 z* Z) g/ ^5 }. `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' A9 H# r, a% |5 H4 M" h0 Q
| MCASP_PIN_ACLKX
' ^# T# w0 w5 g6 @4 o1 C1 ~* T C# \| MCASP_PIN_AHCLKX6 t2 s+ [* I7 p+ v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ m+ w5 m4 b3 L1 I Z7 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 t$ o, A; D& M( c9 e# \
| MCASP_TX_CLKFAIL
. }3 e3 Z {) F( U4 i| MCASP_TX_SYNCERROR4 r8 g/ t9 x6 f2 q# K; [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : |& E O, \4 O/ t) d% B0 c: z
| MCASP_RX_CLKFAIL
E0 o* U2 p7 k% W- q| MCASP_RX_SYNCERROR 8 V0 y' v- L, L/ l7 Z6 b4 c2 C
| MCASP_RX_OVERRUN);, e$ H) [) d4 Q; c y! b! t# T1 f
} static void I2SDataTxRxActivate(void); n% a* G# j0 k( ?. t% c2 z
{8 q) P M2 D4 w. ~
/* Start the clocks */
6 `) C2 r# \* j7 o( KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* ]$ v, ~' G% V4 E' u' S( f9 NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 A! K7 z0 k1 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. N+ b5 d% L3 Z: u: j0 zEDMA3_TRIG_MODE_EVENT);
$ a2 T n) K' j1 r8 e$ z' aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 K1 [& q# y/ M" l( U h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 f$ b; [% o! Z* Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. |0 o" A& F' r) J$ Z2 wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
r8 [8 K0 R+ \# s! G$ L Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 q( T2 C) J! ^# o2 I. L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& O) k" K" A' N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: O! V" U0 o5 }1 I7 k: x} 6 f/ T3 L( |- S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) Y) {" {7 E* g" I9 R3 _+ \2 Q
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