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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: y1 ^$ ?/ T& C# j1 v iinput mcasp_ahclkx,
5 G% U$ y! M) H4 R- H. j; vinput mcasp_aclkx,
" g9 t2 E% p# Binput axr0,
/ n" l; I7 _) `4 Q( I1 V+ F7 i s, d4 i$ g0 O/ P. [" I0 h* I' i
output mcasp_afsr,
. e6 Y$ J, C( q! O4 o; routput mcasp_ahclkr, Y- s$ \, L2 X) E1 i3 n+ K$ A# w
output mcasp_aclkr,
1 {, e0 R6 G; D/ c( youtput axr1,
& k- d; b0 M9 y( X; y assign mcasp_afsr = mcasp_afsx;2 x, D/ u; ^1 Z: K# e9 w2 j0 Z
assign mcasp_aclkr = mcasp_aclkx;) L r/ j! T c5 g- M4 _8 y
assign mcasp_ahclkr = mcasp_ahclkx;8 H9 c3 N6 h. m3 k% _, n1 _
assign axr1 = axr0; 2 }2 n' F& ? C1 [: c
) w ^6 Y; A- w3 ]3 D" U4 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 d" \ Z2 F) {8 U, A& Cstatic void McASPI2SConfigure(void)1 C- D1 x! U6 h- u' }6 \
{
! g7 `* J! K. o& jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% I7 a4 r8 r U* L8 z9 [6 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. X6 u5 O+ v; a$ tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 T& e4 m @& t) }" MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 s) y% x7 l8 H+ oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( n5 P) n# }' o; v; ZMCASP_RX_MODE_DMA);
' h) V$ \, X6 ^6 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ u% y" b- n# d9 X# H" t; Q0 a! EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% R5 k$ u. ~( `! G' y. rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , q. }; {$ N- P. G" w1 D, h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% k% u; Z% e; D3 v# qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 R R3 D. W# _! R4 K8 Q b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) D) @7 `% e! r; k6 ^1 B' K6 ^+ UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" j. K E6 P, M/ u9 H" q9 T7 u, T& NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & `7 ?/ B1 h a- N+ ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ P, I/ x t. ?$ z3 a- d: b0 h$ m" B
0x00, 0xFF); /* configure the clock for transmitter */& y5 ?$ ]. ?! q3 f# X: E! a; z+ Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 V M5 u+ o% e7 N* N" x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 G* w# Y5 i' v( m! ^+ lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# w8 G+ N: r1 K5 e% I. V/ M) D
0x00, 0xFF);$ c' d E, o s! l4 q: s
' [1 {. I' A! W% N4 b/* Enable synchronization of RX and TX sections */
/ |+ I# D |% S$ I8 [5 tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 [! h ^1 P7 `0 A8 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ~9 n R) F4 ?* H3 u0 q$ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; B5 r; Q3 Q% O% C3 [: Z/ P7 n
** Set the serializers, Currently only one serializer is set as
$ I2 {2 S8 N& i! m: d8 |** transmitter and one serializer as receiver.
2 o7 @$ l: ~( l! }*/4 `$ r& d, [! t, S- O8 _/ R; ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" I' h b$ i* V) i5 V7 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& H2 e2 r* T0 t4 \! m( j, s* @** Configure the McASP pins
$ P; B0 k& M r0 w+ f* \** Input - Frame Sync, Clock and Serializer Rx
8 ^) K Q. h h% V7 _+ y** Output - Serializer Tx is connected to the input of the codec
* g: n7 q& \$ q& Q+ |*/
1 {9 }0 W' ?7 f. N# XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 U' {: e+ W" Q8 o7 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; G7 {! j- x4 l+ |8 Z }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( m2 s1 n/ G( g, T1 y| MCASP_PIN_ACLKX
- e' E% @% j9 a- c! Q6 ^| MCASP_PIN_AHCLKX
6 k6 b+ N6 A* \5 I& W6 c B5 a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 p5 @( r$ {) MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ A0 Z f$ F& q3 g( [/ k| MCASP_TX_CLKFAIL
/ k, _" H* b" V, U# ^| MCASP_TX_SYNCERROR' y; p8 x; G% o5 @" H; M4 u& g" ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + E6 ~$ b' _& c% M1 w: t
| MCASP_RX_CLKFAIL
3 A$ o: d/ R0 V q# D& J| MCASP_RX_SYNCERROR 4 `9 r# p8 X# _! b% N Y
| MCASP_RX_OVERRUN);
8 t1 _0 P" r& m) J} static void I2SDataTxRxActivate(void)
6 |7 j6 u' b: j4 e{5 D7 F- z0 R# k& @* {% Q
/* Start the clocks */
/ R7 _7 ~: G' V+ n# H0 [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& A5 e5 @/ m4 a# X/ nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( c3 p9 u0 u3 Z2 L9 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ ?$ ]2 `/ Q9 f! c1 e6 _ p
EDMA3_TRIG_MODE_EVENT);7 v0 n1 w: S, _/ H8 x L/ m+ H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % y- Y3 g% Z L& ]" r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 P+ ~1 w; A! o' U$ m, I* U1 j' pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 x, y: Z! I: U$ t4 ~6 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 ` S) t( w! B; B/ O5 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: |- S/ e4 r8 f( G2 \3 k0 a% TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 F( S$ F) s6 G9 K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); @+ N+ _1 a+ \, K* A8 [! e0 I
} L! U' b4 f! e6 d* `2 U1 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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