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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% n" Z: s; r) c' [1 T* B, Y& hinput mcasp_ahclkx,
, z' P* m! f+ F9 v1 xinput mcasp_aclkx,1 e/ S Q9 m& w$ _
input axr0," G6 g/ l s( Z9 @
5 }. z" m1 q1 {+ P) J: ?
output mcasp_afsr,' e5 h1 i' H3 ]% R4 I) F
output mcasp_ahclkr,
# Y+ \# k/ p4 w3 }2 aoutput mcasp_aclkr,
5 w. e1 H/ H* m! ?output axr1,
9 o7 b! K8 I; ~ _* y6 |3 F. z assign mcasp_afsr = mcasp_afsx;
! D$ | n! X# }8 Y3 Cassign mcasp_aclkr = mcasp_aclkx;1 e* n. V9 J' ^4 U8 a
assign mcasp_ahclkr = mcasp_ahclkx;
9 A9 H( _6 X3 z: u+ Qassign axr1 = axr0; & @1 [9 z0 }2 H! w$ D
3 s( x5 e, L% k o; J- D8 u9 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 d7 {" y! |5 \5 {static void McASPI2SConfigure(void); f) ~2 A; I; x& ^* t% P9 A% `
{" B6 j1 n! E; O6 m9 U& ~+ f7 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, u; n9 b6 D& C' t+ i" L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 Z6 h3 o4 u: ?; T) y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! e9 W: O% o( U; n+ xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" I9 w7 S8 ^# u5 b2 c h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; z/ P8 l* ]# I6 P- b
MCASP_RX_MODE_DMA);
; b; E: e8 Y8 a" U$ f% Z8 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ N% z n2 a9 K0 g: H$ R' U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 r. y4 o( K# F2 ?9 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
j' Z: B/ l6 i W: K5 _2 d- ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 T/ l8 ^/ b5 z3 Q8 `* w1 R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # d. g8 E5 a( h" A6 [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 T" d" l6 r U: }' _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 u! h1 ^7 d4 w/ KMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 r6 T8 b) _( @0 R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# F" i- A: X" O t) f3 Z7 Q
0x00, 0xFF); /* configure the clock for transmitter */
& N/ x7 ]+ a: x, y: G5 F& u VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, F2 Q, q( H8 K$ l5 IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( G Y, }$ M! ^, D, X I$ C8 I4 q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" X9 w# l( v( x$ ?9 o0x00, 0xFF);
9 A2 ^' c5 d+ Q0 u8 {% d
- x; L: r; i( u/* Enable synchronization of RX and TX sections */ 7 \! x8 k. A/ @! N7 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: t6 |7 k( P9 E& p2 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' _7 T. B! T- H& tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 I8 W& [+ E y** Set the serializers, Currently only one serializer is set as! x4 D5 F9 v: O/ O4 q
** transmitter and one serializer as receiver.& v6 f ^0 F* ^4 m: I7 l# j9 s; I. [
*/0 U% f5 b- U# X- ^& X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 B `* e- c" n; l9 U( s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" \/ [$ K) j0 U
** Configure the McASP pins / I! d0 y6 y# y z/ a
** Input - Frame Sync, Clock and Serializer Rx; L4 H% W( i# h' I
** Output - Serializer Tx is connected to the input of the codec
4 ~; k8 ?5 C8 E: X2 V9 P' i- |0 |: ~*/& D. C+ o' p) {0 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% u$ n/ `9 h; ]+ p. SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 `5 i/ a2 v5 s1 D# ^2 R2 BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 p) V0 @0 K. f/ m- ?; A| MCASP_PIN_ACLKX
; _& W9 l1 e- b" f, _5 i/ ?6 Z+ Z| MCASP_PIN_AHCLKX4 _3 F0 p5 x; D/ L3 R. X( d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! a! `( h+ d3 X* D) ?! k; NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 C5 X, H" H3 p
| MCASP_TX_CLKFAIL
0 P, O$ `5 C( t" i7 Z: w! Z j| MCASP_TX_SYNCERROR5 z& `1 n+ Y5 e0 s4 A' \/ Z- \
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 _3 N; L$ G: y) \" I8 L| MCASP_RX_CLKFAIL# S# e$ B' c+ l( H7 s. u: j
| MCASP_RX_SYNCERROR 5 h" k" m1 T/ z8 q$ z0 `
| MCASP_RX_OVERRUN);4 t7 W* B* `$ q; F) u
} static void I2SDataTxRxActivate(void)
# ]! C6 u; [3 I7 h/ u{: @( M# E/ l- Y. v7 v$ t
/* Start the clocks */3 M! V8 D4 g* a% x7 ~; N$ w: R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ x* e7 H* I( g0 ~3 Q: uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 @- F. O N8 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ }) e4 `+ ?. s/ T7 t7 O! FEDMA3_TRIG_MODE_EVENT);. e& o: F# e2 _( x' g" w) R% s- p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * ?3 q/ ~; Y; f1 K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" r5 X1 H7 P: C- Y1 H+ O7 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& r' h E; R* s2 ^# M$ v- sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 o; j& r2 F9 M( a& }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, g' Y* q l1 q: i# ?0 F6 I) @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 A$ y+ d! @4 z4 n7 |( m8 W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( A& e8 r; H+ \2 s} - T+ y- C7 w S u7 h/ g0 \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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