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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 \2 s4 e+ ^* r1 o0 Jinput mcasp_ahclkx,. |: }: j2 t. v H; Q
input mcasp_aclkx,8 B2 b2 A% n* t5 U
input axr0,
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output mcasp_afsr,
7 T4 [0 Z( p" Woutput mcasp_ahclkr,
" ]# G' A+ @, doutput mcasp_aclkr,1 { M& ?1 D5 K/ }
output axr1,( ~1 K' n' D/ e7 V! w M+ W
assign mcasp_afsr = mcasp_afsx;2 {6 t) I, ]% f' j
assign mcasp_aclkr = mcasp_aclkx;, ?7 |; F- g" t& ~, A
assign mcasp_ahclkr = mcasp_ahclkx;
' L' s, I }6 b9 j1 | [% rassign axr1 = axr0; 8 t* D, ?0 {7 e: G
5 U" r0 K7 \1 A# b. r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 Z( p5 }* @/ l8 f) `
static void McASPI2SConfigure(void)
0 b; f+ p0 z& s" p) ?% U/ z{- x; ], \, a4 g- K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, f& I( F5 W+ x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 Y+ O# @5 X# K( N' v' ]1 LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 _* f: W& D) zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& g# f) L" ^5 \+ C) s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 A! C) F9 `5 a% Y
MCASP_RX_MODE_DMA);1 @: ~; M$ t3 n0 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
L6 l, E R$ I& U) X2 a9 \. M# G! gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 V; |6 m5 T; G2 M' YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' M$ L# a. \+ A# @8 KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* c# G& N. p8 c% iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 Y# V1 x0 _1 {1 V4 s. ]: l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ ?& H" O: V/ |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 a1 a# `- `: Q6 b9 t* ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; ]$ F& P) m; P. TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 P5 b1 w3 j2 N+ ]0x00, 0xFF); /* configure the clock for transmitter */
; @/ M c( [, |; HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 d! \4 ~3 w1 n4 C! HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# r! `, |9 U" q5 ?) eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, {9 i; O; R0 Y j
0x00, 0xFF);1 @5 J% G% y/ |. u
- U/ a4 T$ }% j
/* Enable synchronization of RX and TX sections */ " g* @; f" C; J" f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: m* Q0 k" E5 T+ p9 u, _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: n9 X. C3 p8 _0 t, l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 V5 O |8 |0 W
** Set the serializers, Currently only one serializer is set as; [, \. w, z) X* @& p+ T
** transmitter and one serializer as receiver.+ C' p. I/ f# O2 W
*/
. P. x* N+ T. |; a! i' OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 F' N' B1 a, |. }0 m) \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( w; t9 T" e2 T+ g** Configure the McASP pins , `) Q! x: X: j* e9 E
** Input - Frame Sync, Clock and Serializer Rx) h0 G2 ~+ ?3 v2 v" I, R, K1 B! d S5 \
** Output - Serializer Tx is connected to the input of the codec # B+ |5 t1 T% B. h+ A
*/% ^# i, ^5 p9 \/ L' x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% j$ e! t- ?+ YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. l& g; h7 w1 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! C; V2 z) E/ k| MCASP_PIN_ACLKX& A! d* v5 u7 [. \! @( h' b
| MCASP_PIN_AHCLKX
" J& }5 E, m% s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" Z, R# E. j! Z) }' v2 H! ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 q5 n. t' V$ k5 H5 S- K) ?
| MCASP_TX_CLKFAIL ' C, T- `9 g# X6 j2 C
| MCASP_TX_SYNCERROR" ?% g& Y$ E6 B$ A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) u9 Y/ u5 I% g! Y
| MCASP_RX_CLKFAIL" Q: [! h; Z/ w2 S8 v' K) y
| MCASP_RX_SYNCERROR
7 \! \2 ?, U T6 b% A8 w| MCASP_RX_OVERRUN);+ }6 O! O9 t/ k% t5 }4 f+ L
} static void I2SDataTxRxActivate(void)2 F1 @7 D1 v {) h7 D
{
" P) h& @5 b8 L7 {5 ?0 J- d/* Start the clocks */& U9 V8 |: n5 o5 w" I9 G1 p8 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( l4 p3 p, W) i; I% k5 A0 w- {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ ^! b& C7 Z1 B; dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 F( Q0 F2 Y8 AEDMA3_TRIG_MODE_EVENT);4 P) G: j, K. p. o9 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. ~, Z7 u3 n8 _2 g9 \) L2 uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 q( `" b0 m4 z: K. u+ d( {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# { Z7 y. Y9 ]4 h! E$ m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. y6 _$ q5 K9 S& p$ |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 M. V( v$ H. M$ b8 m) \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! q! b' E G t* q5 r" R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" g- d$ z, y. I! |} ( L J, P+ _$ ^5 J n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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