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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 q3 Z. o: E1 @3 y5 c
input mcasp_ahclkx,' K* [3 \! z+ }/ ~
input mcasp_aclkx," W. x: _7 i% g i/ c( U0 x
input axr0,
4 q* y' h5 L7 n" K+ i' R8 _% f$ k3 q9 D Z3 k$ V3 t
output mcasp_afsr,+ U( g: B; T1 x6 u5 E" |. O
output mcasp_ahclkr,2 G/ G3 P+ N* ~" _6 d. b$ z8 {" q
output mcasp_aclkr,) k2 P1 f3 `0 w$ y: ]
output axr1,
( ]3 Z0 R. |3 ?# n: z assign mcasp_afsr = mcasp_afsx;: V/ r7 B$ Y: q: `7 j. s
assign mcasp_aclkr = mcasp_aclkx;
1 I @! [7 a+ y2 c, a" [! fassign mcasp_ahclkr = mcasp_ahclkx;, W8 R' F/ Z. J. [) u
assign axr1 = axr0; 4 \3 a$ B1 c4 ^) |7 S' S
" l# s4 H5 f3 K4 y/ X& k7 X9 N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! f6 s* j4 R- t! B- ~( _static void McASPI2SConfigure(void)
6 G5 r7 W- V* I0 M{
4 L$ H' i) V, S: N6 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% f# x' s) c1 K9 f5 _$ }& `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 I( P) t2 M2 C! U4 ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" U4 W5 q5 X3 r- l4 E1 SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ e2 X* p7 D9 X5 I( VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. O1 z# N$ C: J9 S, j4 c/ VMCASP_RX_MODE_DMA);- L+ \/ }& r$ J% G& }# @4 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 H( O! M* v* B$ t( `1 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. i( O9 E: r* |- M& o. M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& f$ k) Z8 k& \0 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! H; e) I1 S: r( x- ^- p& a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 C$ x; a# L* B1 j* a* z) n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ b8 ]0 f4 p! v4 i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! v- c P4 b9 s9 b1 p+ f' r8 t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 l; ~/ ?7 U, ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 V. \! P- X4 o( k* ^
0x00, 0xFF); /* configure the clock for transmitter */) J9 s# S+ {' o, o M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 N! I0 z# O2 ^& g/ U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 x1 i* u& z& g$ pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ A' F) e' y" x8 a0x00, 0xFF);+ D4 f: E2 u4 ]2 H- j t- B6 k
, u/ Y* f+ W; e2 O# j' y+ }
/* Enable synchronization of RX and TX sections */
+ ], |! `' \2 w% j0 P( ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 F" J) B/ N4 g# ^1 o6 k2 i6 A6 V: ]. xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 p G' `# t* t4 d+ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 V6 T5 ~; x, O) X" q
** Set the serializers, Currently only one serializer is set as
* I* p7 h2 g4 e, B8 r$ p A( `** transmitter and one serializer as receiver." L% W( M2 I% M. _7 @' a
*/
3 o: B' Y- f# N* E1 M* lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 R& x: \4 B( U1 B' `7 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 ]. U5 E" @" g: q0 h1 i0 f& ^+ @5 g1 b** Configure the McASP pins 9 H; M8 ^5 N2 d+ |3 U& Q3 t: Q; b- g- x9 ?
** Input - Frame Sync, Clock and Serializer Rx/ d, ~( A# j% b
** Output - Serializer Tx is connected to the input of the codec
# l6 x% v: p. @' x$ C- j*/
+ n$ S0 O3 z& g4 b; NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" P9 `& R: P/ Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- E- z% ] N( v3 MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
a) q" b, h1 c7 m0 s| MCASP_PIN_ACLKX
3 ^$ y$ P( I& @2 A" b| MCASP_PIN_AHCLKX
) m. L8 ~3 y9 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 k! H% g) Y+ X5 Y) e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; L$ |2 ]9 Z: a, d$ y; S$ S
| MCASP_TX_CLKFAIL
1 D' R' h4 i L) C" }4 u! ^) z6 X. u| MCASP_TX_SYNCERROR
6 E3 x$ O& g7 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# I9 @0 ~( ~5 @+ X5 `| MCASP_RX_CLKFAIL
. I+ A, \& g$ U) U9 ?% A7 `( x| MCASP_RX_SYNCERROR 6 Q9 Q g* {- ]3 ^
| MCASP_RX_OVERRUN);$ Y/ N+ w, l* @' E$ S% n2 G' K/ s
} static void I2SDataTxRxActivate(void)
+ D$ p- s m0 G' Y& f' s{7 i. h; M- Z& K! O, M( a: A/ H
/* Start the clocks */ ^! g# h9 V' x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 p& V7 i+ D. s% C9 }5 E' @) xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 ?; ?8 q- W3 a$ t# F2 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ O7 P) \4 Z4 ~
EDMA3_TRIG_MODE_EVENT);' a* b6 H+ ~; P7 O+ ?% a4 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 _1 ]% V1 C$ D; v/ B! y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% |: g2 M7 j3 p# p/ u1 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; M S/ i) Y% f8 G8 V. JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- |1 I6 `$ S& h1 r+ H* e! m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; ~5 L% O3 O- m) N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 r) ^- e( B4 j2 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% t8 o" o. N# I}
% h& _1 L8 e1 j' ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! o/ K! k Q) {0 {$ `' w: c1 A
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