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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) v: t4 p. E3 P' U$ A' Ninput mcasp_ahclkx,; Q. Z. Z8 d5 I4 B
input mcasp_aclkx,
6 o3 \/ _8 J, H0 j; ~input axr0,' S( X* Y5 [& o P$ L; A
8 K) O% b5 k ^: x' d
output mcasp_afsr,8 t; `9 v' \0 Y) l1 {8 W1 ]( h
output mcasp_ahclkr,/ d3 C+ N4 [' O
output mcasp_aclkr,
0 b5 [* r1 D! G* o7 a5 b" ]* h+ Poutput axr1,
' a1 L! ]4 ~1 K: q3 `5 ~ assign mcasp_afsr = mcasp_afsx;
: E0 c+ V( L. r& a; {assign mcasp_aclkr = mcasp_aclkx;. T7 z3 l& u4 }: }% ]/ _: d; x
assign mcasp_ahclkr = mcasp_ahclkx;% m& y$ c% q- `1 u3 W9 h
assign axr1 = axr0; # h% X9 [) f: w1 o2 F+ q4 V. K& f
2 p6 \: M3 ^( w, f+ u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( Q4 g( x( I% z$ Astatic void McASPI2SConfigure(void)8 }( V+ z; S( T1 g. M, _
{
6 E6 [4 n# b! p* fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 y9 W$ v s& E; z2 OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& a. x( p# X, W3 Y ?' BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 f6 s, @5 ~% R4 f5 d3 S1 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& W7 I8 Z9 e- P; T+ E- E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 k0 o! h6 X2 Q2 l l. ?# g8 EMCASP_RX_MODE_DMA);6 i5 y) ?# h7 {. Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' P4 E; f+ x' ~+ r2 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% y/ ~2 O) Z' mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' c S+ {. w. `0 H* g9 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 S# H9 q6 \! _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, C; M; [9 m. b* E1 j* BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 b9 w. f5 ~2 b1 T1 h2 m% A+ J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ w5 x8 D1 c; _( q1 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 o0 {8 p# I' G5 k! }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 w2 T3 u8 c3 Y7 L+ j5 \
0x00, 0xFF); /* configure the clock for transmitter *// }& G y6 @: p y' C5 ~4 Z/ p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ v+ o! ~ P8 v7 m$ S" o8 K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: a' w- u5 w$ T+ x8 Y. fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 }: `' L( B7 q8 F- w8 q* ~. W5 |
0x00, 0xFF);2 g- T5 z4 V% `$ n3 X$ h
+ h: U' {& M7 E* ]1 Q. E
/* Enable synchronization of RX and TX sections */ % H& s$ @$ F) z& ?$ S9 q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 O1 N5 y5 j& `5 @' s/ y9 l# wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( m$ p# q, c9 O7 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 c8 M& H2 O4 Z& J" u9 i
** Set the serializers, Currently only one serializer is set as5 y& e0 q/ y+ e6 J2 P3 j" l q
** transmitter and one serializer as receiver.
% C# u; Z, M% E. `*/
: Y$ c9 N; ]0 X; e: ]4 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 L4 r* C) C' z2 Q% U. [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" F/ j- d( C- k) i( Q4 O
** Configure the McASP pins
1 q3 K: X+ q4 r3 c** Input - Frame Sync, Clock and Serializer Rx
% t: |/ E* D5 W8 t** Output - Serializer Tx is connected to the input of the codec 6 R0 q$ r& T1 l" J7 j
*/
. o$ o' |( B6 M8 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& w; _$ p5 w& y. _& K' A. d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
U/ N3 d/ t* Q" NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( [- I' o2 t: _/ _- h6 _* `( H
| MCASP_PIN_ACLKX
! B+ M/ m% e: D( l| MCASP_PIN_AHCLKX5 f6 A$ L, ^/ }8 Y9 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' E4 a4 t+ @4 H0 K+ Y" v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 u# g9 s4 m/ x4 L
| MCASP_TX_CLKFAIL . o( G1 C& f" \8 u2 `) x( N. Z0 d
| MCASP_TX_SYNCERROR
T# H. u& b' C( H( F+ a, B9 t/ B1 t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, g# |$ t: u& u8 [- ]7 e2 D| MCASP_RX_CLKFAIL
. w; X! q# ?- R2 ^% H| MCASP_RX_SYNCERROR
3 Y0 ]$ q8 e2 F| MCASP_RX_OVERRUN);
+ J; g, ^! T# ~! l} static void I2SDataTxRxActivate(void)
4 c- Y% b! H+ f S" H4 u3 ~" ]/ H. H{
- L% o2 G4 b' |% F+ k/ V/* Start the clocks */$ r# B8 U4 Z8 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, m2 w$ ^6 ^- N% @7 y0 r/ t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 D5 a/ n. v {( u/ k3 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 d- `8 W8 ]* p2 T# c- ~1 \
EDMA3_TRIG_MODE_EVENT);7 \1 d& k+ H3 s+ E) j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 R) t+ P- _4 D3 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 M# Y' Z( N( A' F! O, i6 K# U( ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 k8 q) W- S2 E6 o( z4 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 Z3 P) s6 E: v+ z) twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! v- m( i' i) D( ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 N- A0 [0 H) q) k# }: X! T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); { B; d {0 J0 u4 X2 ?4 t( u/ }
} 6 m& v9 ]/ G5 B6 X+ U% ^$ h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 t# t M+ c6 R; a
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