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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- s3 x1 ~$ ^3 T2 Y0 s
input mcasp_ahclkx,
; q/ \0 U1 F" q9 ?' C) d. oinput mcasp_aclkx,) M7 C) A1 l6 H8 Z" e
input axr0,/ ]& N4 E. N6 _: W% ~ J
5 F) X. _* l) m; d3 z" voutput mcasp_afsr,7 r# J o+ [. K/ u" u
output mcasp_ahclkr,
# b" ^2 U; |( [$ H* h. doutput mcasp_aclkr,
1 Q" J4 K. z/ }* M1 E2 voutput axr1,% m) n" b5 [( V
assign mcasp_afsr = mcasp_afsx;
. \! L4 F: b9 {9 _, Uassign mcasp_aclkr = mcasp_aclkx;! y$ `# C. Q* R! B% k
assign mcasp_ahclkr = mcasp_ahclkx;% t" c5 Z) F% l( S" D$ c+ L
assign axr1 = axr0; q6 X6 V/ i6 S
; G; E) Z- \% ^( }" H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- F& o2 [* A" ?% b$ {# x7 ^static void McASPI2SConfigure(void)& x! v/ S2 {6 t" a* [4 E
{
R5 B/ Q+ o3 G4 a6 I, s" b& jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' g5 l- J8 ?: ]; \; p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 q/ `2 z' i0 u O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 f' g2 Q% X# l/ u, m( J- J+ G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& m% ~+ x" D5 XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 F2 a- U# |3 H1 M) X
MCASP_RX_MODE_DMA);
$ M) S/ O, {+ S9 U: Y) g+ |% OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ x3 B7 a5 m% f& Y- u) ~: t/ D9 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! g5 l* P3 U d0 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! [2 e+ |) p4 B# E" W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- R# c2 Y: y$ k& E" j" |9 l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 {: Q3 y( M* TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" h5 R: C4 E9 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' i& |) g- K& [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) {. s0 Z' d( l5 A6 j+ Q) m4 J$ R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 \! |$ f6 r( t- E3 s7 g" \( |; C
0x00, 0xFF); /* configure the clock for transmitter */
( ~: y$ G9 ^/ u+ E2 dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" \0 s" r: r+ U6 i/ W/ Y0 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! G& n1 q6 K7 @. ]) {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ _ q; y6 Q% u0 E0x00, 0xFF); ~, d+ M$ W8 O9 l4 y( W0 `% \
0 j" ^) B' B% y2 Z/* Enable synchronization of RX and TX sections */
M9 q0 f0 @+ D! jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! t8 r& `* R0 m* d! v# HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 h9 j$ ~* D% J _/ J1 m. Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 r' x5 O! R) v1 C2 n& A
** Set the serializers, Currently only one serializer is set as
1 k3 V9 ?+ `6 ^( ?) |3 q** transmitter and one serializer as receiver.
0 R( @- [1 z: ~) B" G4 |& ?*/
' F2 W' `! w4 D1 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 x$ P9 R' C+ T) g; gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) w& W) B7 H. a. D5 y- a( E- K) u
** Configure the McASP pins 2 ?8 r5 H& l# d% o. c. \6 k4 ?
** Input - Frame Sync, Clock and Serializer Rx
! L% w: J8 E2 N5 ?; W4 K** Output - Serializer Tx is connected to the input of the codec
3 Q" a( `9 `3 j8 r*/
5 @! Q, b: e8 C) FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 H3 |0 b$ O" j$ O8 A# b( sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! w8 i3 [ _; M( C- d sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 c5 G1 D, ~6 J& ]| MCASP_PIN_ACLKX
5 V: q h$ \3 h| MCASP_PIN_AHCLKX0 b5 s& N& d- j+ d3 \' h2 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ s2 \0 G) v* N8 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 L: {! ~4 U- o1 a4 n2 t; t$ @
| MCASP_TX_CLKFAIL ) n' Q3 V# z. G6 ^$ }" L
| MCASP_TX_SYNCERROR
4 S$ v& W9 O2 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! |1 j7 S% D' E c+ E| MCASP_RX_CLKFAIL0 Z7 O6 S% p! w6 c( s% d
| MCASP_RX_SYNCERROR
8 n: }1 G& K* {9 F/ }& I! S| MCASP_RX_OVERRUN);
3 _' O1 T8 M3 T+ U1 v4 {& l: G} static void I2SDataTxRxActivate(void)/ J- p- Z% K% m
{
T1 E. p& _. `. u/* Start the clocks */
+ w% g) i. M! [# a1 C4 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- S# j& A2 @4 o& C1 ^2 N, Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; n3 N0 W7 F) `: P4 O/ q# X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 q' \9 @, @2 L8 s
EDMA3_TRIG_MODE_EVENT);0 a# k: c$ e8 m7 E: G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) i# \) I3 V, f( M" C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, l) B9 L$ K' N1 Q) m7 N& Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 P, L, B0 v! s) V# l1 EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- k4 e+ E" F% v8 M) r# _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: }; \" A* s' x7 E! |! o* P* B5 w; _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ }; O; e6 g4 a) z' d9 x7 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, F9 z, Z. o k6 C- i. O+ s1 E, |
} & ]7 g# v) Z2 \# z7 ^4 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 D3 u6 }3 o. g: \: o4 d
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