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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 X; }" ^9 D# o+ T/ } s+ einput mcasp_ahclkx,
# @2 ` l3 C& }- sinput mcasp_aclkx,
2 ?6 N# a- }. Q/ N) ^- [/ ?0 Vinput axr0,& `" E/ f; W: b7 A
5 m- A- r% i1 _$ F3 n# Voutput mcasp_afsr,
6 r; Q3 G: s2 `0 R3 c0 W5 H2 noutput mcasp_ahclkr,
) g& E' a# j" {output mcasp_aclkr,
4 Q, k# M& q: q* j5 M: Houtput axr1,
% I, }9 |3 T( a: l+ W5 \/ K assign mcasp_afsr = mcasp_afsx;, x* M3 f2 J/ P: C0 N% h
assign mcasp_aclkr = mcasp_aclkx;5 Y2 h( h& f: K1 M4 |+ i0 r; L" e
assign mcasp_ahclkr = mcasp_ahclkx;. \ Z! A e2 R1 n7 A
assign axr1 = axr0;
4 ^2 v) H( y& l1 d4 v- |. o! ^5 g3 h ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 T( ?5 V! H$ ^3 Z4 \" g7 {% P
static void McASPI2SConfigure(void)
3 T" j) T+ R( u. n, H- y5 @6 d{' x* t2 {5 U9 C0 |/ x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" o; r; U2 S/ H* c, G4 ?: e6 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 G0 U9 \% L7 ?7 e8 Q! |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ e" ]9 m$ N' f$ B$ BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 z4 W# u" d" `5 ?* m6 S7 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ K3 j* a! U: N: Y! f
MCASP_RX_MODE_DMA);
" l( y2 n- [8 |! N _! o' GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: b3 N3 o3 B) N7 K) i% ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 ?0 o' E, X" O9 O, G u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 y) |- r- e$ M) D* z& X7 e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
@9 o* R9 F9 U6 |& N, \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. T; T9 ~0 D& }7 p. p# j# L2 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 U Y2 p, q' e3 }0 ]3 W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* v1 d+ ^/ H( T( b* tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* }9 Z2 X, x9 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, w6 _* |4 W& D0 D
0x00, 0xFF); /* configure the clock for transmitter */3 y6 C( E$ H' A; B6 @, x: G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 e' r) c/ D. R3 }2 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" T+ H C0 b' ], Q3 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 J5 q) Y: P7 e: \1 q0x00, 0xFF);% }8 ]; j3 d% p( S# v( i/ H
7 i( e% l. K% e. z+ }/ Q9 Q9 ^/* Enable synchronization of RX and TX sections */ 7 u7 }1 Q V2 P* A$ X' \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 O" [% b7 J! o7 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' t: r& v% s8 U; d; M! E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ C/ d2 ]& l4 ` v4 ^** Set the serializers, Currently only one serializer is set as6 T( B* i/ O# A! x$ q9 t
** transmitter and one serializer as receiver.. G/ Y! M- t; k8 K
*/
8 a' e: h3 V7 N3 f; @, KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( n" m8 n3 W4 W+ y* y- C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** q3 Y+ g8 f( j& A$ ~3 z) u5 y: }
** Configure the McASP pins
! N( g; K: `/ U9 _ P. u** Input - Frame Sync, Clock and Serializer Rx
+ E3 O- b" |* _% W/ h** Output - Serializer Tx is connected to the input of the codec " ]1 c/ B$ `& }$ T, B. L! {
*/
* x e6 g, ?# ^' s; [9 O* OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& N# ~) p. b4 M. N5 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 x) B4 V. e i y- DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 C6 D8 s3 B& k- F" B2 ^| MCASP_PIN_ACLKX
; v B, J6 D+ u! v6 ~ Q( R| MCASP_PIN_AHCLKX
- t7 g: G) j! t( a. p& }: [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 E8 ?6 E# [. e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# O# T" F+ I L2 E! _0 B| MCASP_TX_CLKFAIL
$ ^" c* H& G! k! f& Z| MCASP_TX_SYNCERROR
; V7 ^4 u; H) t4 d5 {( T( E: I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 J5 d5 i ?: }4 H/ G" G5 W| MCASP_RX_CLKFAIL
% D/ o5 _6 H. T1 p& _| MCASP_RX_SYNCERROR & Y1 R$ I$ o5 w# }$ o# f' K+ I
| MCASP_RX_OVERRUN);, B) x: M/ D% m" G. ]) s- ?7 q
} static void I2SDataTxRxActivate(void), N" @! q* a- w2 h+ i. z: v' @3 T) e7 q
{% {7 [3 m' ^( o) D' L
/* Start the clocks */; L2 I/ L8 H) d N+ c$ o9 j) O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( [- m' m) S6 U; i L$ @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 H* M! q- Q- b, J$ U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 B1 y/ E3 x6 T7 v2 d! aEDMA3_TRIG_MODE_EVENT);
* b2 @, H; ? Q8 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ D& V5 \9 A- w0 ^; ^$ n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 o5 q5 W& F$ Y O6 k' ^& B6 W& Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; h- c! X) @! r2 ?' NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' H3 K6 M; \9 X/ j* M/ M3 D0 w6 n. N; jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 h. ]" [% c6 @0 P( [8 k6 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, G6 L4 Y6 ^& z* i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 S& y8 c& u- c4 x. ~. d! P} 6 R- E) j% X6 P& ?4 {& O1 v. n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * H; k6 q& i( @
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