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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 ]) s( F" w: O0 Minput mcasp_ahclkx,
9 D9 |! J; I% I4 H1 _% c9 o. ^input mcasp_aclkx,
4 o4 }4 _( L0 m- [: n0 ginput axr0,+ w0 B# Y; K+ o0 d% N) g6 k
q) V5 H; a3 ^1 [output mcasp_afsr,
; {3 J M6 B$ B% \* \1 B4 ~9 voutput mcasp_ahclkr,
$ O3 V8 U' a0 H* p# l# l8 Aoutput mcasp_aclkr,; t7 ~3 c8 W+ y
output axr1,; y9 R$ y! Z/ d9 J1 Z
assign mcasp_afsr = mcasp_afsx;2 i& q# ~6 l" u5 x
assign mcasp_aclkr = mcasp_aclkx;4 \/ |. v6 b; G6 l, w% ^
assign mcasp_ahclkr = mcasp_ahclkx;+ O1 b5 e' R1 v
assign axr1 = axr0; * n9 B2 a3 e& ^1 j# f6 |* y
+ F9 d+ w: G0 z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . ]- F2 q+ l( j" P' z l6 Y
static void McASPI2SConfigure(void)
9 X) f. l% e, }* D* k/ X{ H, X( l, z- v; i3 `* W P9 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: I0 @" W |( |# GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, @2 s+ [2 Z k$ H6 I, g0 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! E& b$ v( ^& z l: y: `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 `+ B b' E+ C5 }" b& U6 J2 L4 ^& t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: O7 P- [3 Z6 c3 N1 E) B0 f; JMCASP_RX_MODE_DMA);- `; u, U; s3 {+ U3 f4 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 U+ L1 p7 D: f7 jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# A9 C: B$ s* K$ K. F. L3 O) B5 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
G' _4 @( P- n7 G- lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" v$ N% u7 w, ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 \9 g: z' o- ]7 \) ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- b4 u1 E) v7 y% V& R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& F2 C0 J: b) C n; Y, YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! x8 Z8 F0 r1 ?0 N5 n% o: E+ tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; h m& C9 Z+ y: q8 h$ U
0x00, 0xFF); /* configure the clock for transmitter */1 Z& i$ N O, }) @/ q4 o5 r( C* o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% y( e- r @$ X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) o5 `1 L3 l% S) v" B Z( C5 vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 G0 P- a" j/ l0 @! C$ ?0x00, 0xFF);
" q6 g; c0 B+ M, z; u3 h5 j/ j# r! w y# u9 R6 F3 a$ J( m4 Y1 E
/* Enable synchronization of RX and TX sections */
' K* ]9 R5 Y# Z0 Y/ ^! yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
o' o0 U5 l* nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 T$ o; c9 E7 Y: H3 j& c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 q# V( u! U7 o1 W, X$ f
** Set the serializers, Currently only one serializer is set as
' ~$ J% i+ w" x, ]** transmitter and one serializer as receiver.2 k! r5 T* o8 n; \
*/
- a% l" \6 p5 K6 k4 e# H7 J kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! _, _7 I& v* h: O8 F y" IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 K* b7 s( O/ d& L** Configure the McASP pins 9 U+ y. y; q7 V4 u& w; u( l2 a
** Input - Frame Sync, Clock and Serializer Rx
7 ]8 o/ D: I7 \7 d/ B/ V** Output - Serializer Tx is connected to the input of the codec 4 l! W1 v) _# W# V
*/5 v4 b; E3 E) e9 U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- W) `% U! c* yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, E( k z( E( lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: H( s. y% E3 b| MCASP_PIN_ACLKX/ n0 G2 x: l4 k& j
| MCASP_PIN_AHCLKX
$ _/ [8 V* R; M" a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- Q6 k, _; ]6 q" rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * c' C. U9 M; }& i# _
| MCASP_TX_CLKFAIL 0 a) d- D \5 |6 J# \7 X8 m
| MCASP_TX_SYNCERROR
6 q2 q' b% q( {8 {* I0 M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& a, o$ x5 d$ a; M8 @4 v| MCASP_RX_CLKFAIL: a6 D& Z: o$ B: w
| MCASP_RX_SYNCERROR & j& g! M4 r- X! I" y
| MCASP_RX_OVERRUN);
) C/ G \( a& L; @/ j/ _6 B} static void I2SDataTxRxActivate(void)
- h; Y- D7 |! A6 ?8 T' J7 A( N{
5 `1 K" q- f. M$ ?: O/ }: [/* Start the clocks */
# E3 j2 m8 u2 d1 n; U QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ U# n& g% v, K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, T$ i* v! f: C. u* o/ n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 F, e" Y8 V& o# p7 C
EDMA3_TRIG_MODE_EVENT);
. S2 U# f( S- {' ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : q3 o( z4 \# O. z; l; y5 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 l$ q( x0 h& q" s9 t5 cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 x5 k \4 P8 N& f% ?, d0 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: ^3 P- @ n3 {/ b: F& nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; x/ }% a$ _; B/ wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 E+ h& t9 p; J! z; y6 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' f) J% K( `4 v4 A4 ^: `
}
6 B2 y3 y8 G: O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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