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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 r" L5 F6 z5 N& ?0 ?+ ]1 N' Vinput mcasp_ahclkx," G; h0 p# v( T
input mcasp_aclkx,; Z1 I; x& F2 P; W, o O
input axr0,
6 Z0 |9 S/ X' H' ~* l/ m! N4 j" z9 _( O: V( z
output mcasp_afsr,& K$ d8 ], z; Z% F+ U, B
output mcasp_ahclkr,' O0 ^- a- j; _0 Y$ ^
output mcasp_aclkr,# ~. X/ Z- M( M6 Y
output axr1,3 [0 m- p$ ?+ m8 }) {
assign mcasp_afsr = mcasp_afsx;# u Q. J2 x& O( E
assign mcasp_aclkr = mcasp_aclkx;
+ @- q$ A) i6 X: N# lassign mcasp_ahclkr = mcasp_ahclkx;
7 t9 a% E! m6 K+ c- \# [assign axr1 = axr0;
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3 W/ f3 X( t% K# l2 n, n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% Z0 ?" m q3 z Q4 Y6 x# @static void McASPI2SConfigure(void)0 f& \$ s0 n: w1 E/ D6 [* j. l
{: d1 S4 T0 A/ P7 A2 J. u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; s+ [* C/ P& E9 T% r# O* j; [ h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, D) X9 c! |& F% Y. w2 ?7 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* n( D& `6 b( t& N0 Q+ q3 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
G: n. t5 a$ L( G$ J: {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 q) Z; A, ?7 A8 P D
MCASP_RX_MODE_DMA);
" h3 j7 q) T0 X% G3 k5 s- UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 P I3 U2 X( \2 O+ j1 t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# H. J+ c3 } }6 o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : D) T* L; P. p% n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 l; X8 K4 r) a" C+ F" I- a9 V4 ^ BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- X: e8 Z/ m$ z& L/ q' \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% T; G( u- t; DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' {5 h' R. Z' w1 P- n! M& }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* T- M8 s2 n( Y* \) Y( rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' G3 [& s9 Q! ~2 C' ^
0x00, 0xFF); /* configure the clock for transmitter */
2 C# z+ ]/ J; RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ S- i4 m7 _7 R+ ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 I; R" W4 T$ NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 c: Z$ q- p( ^5 A4 _0x00, 0xFF);
! ~. q8 i7 r) ]" y) l# G& ]. }/ X6 a; b% o% ]& x- F
/* Enable synchronization of RX and TX sections */ & {0 k: f- ?$ K7 i( O6 g( @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 X4 n+ A) M7 G* X4 X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 r4 A2 a' i; z; X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* q p' E1 N: X** Set the serializers, Currently only one serializer is set as! W) @0 v+ M8 c0 `+ |7 L# L5 I! @
** transmitter and one serializer as receiver.
" l: k( F! _6 U. z i0 D( a+ L*/
2 \/ l! F, U2 J2 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* D1 V f+ ~ k! p( G5 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 ?* c. V' t* D$ `9 _- d: H, A** Configure the McASP pins }; g- v: Z z
** Input - Frame Sync, Clock and Serializer Rx
2 x* n- N( a0 |$ n: C** Output - Serializer Tx is connected to the input of the codec
1 R) @" t6 _( r3 c0 G*/
- P" y6 v3 F0 B0 H% C. l" U6 D8 e- HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 R: Q& H; l8 i6 F6 b0 V: I" EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; p6 D7 R9 d% b$ _% Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( r; M9 B, P' S2 {
| MCASP_PIN_ACLKX
& l$ {- O5 A+ O/ R. K2 N2 \| MCASP_PIN_AHCLKX
, @& N0 x( r4 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 ?+ o5 \& k3 @/ X6 S+ {% w, q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " N" D1 j' B! C
| MCASP_TX_CLKFAIL
2 ^8 A$ l9 L" R' }4 || MCASP_TX_SYNCERROR
' b2 [) m; Q! ], ]7 S s. p, {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# t O& W+ Z- K* r+ K6 n' L| MCASP_RX_CLKFAIL) Q* S- Y4 Z& N3 [- {- i; E' m8 ~6 P
| MCASP_RX_SYNCERROR / y H+ {$ ~# N, `
| MCASP_RX_OVERRUN); K3 X p1 y. m
} static void I2SDataTxRxActivate(void)" u# p; L, c+ v8 [3 H
{
6 G! w) `( C+ {1 T/* Start the clocks */' ^, m1 z" Q& a- x* N) D X/ n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 o' Q# T: ~! I4 g" I8 f0 ]* H' O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ d; J. ?2 X- C4 n3 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ P6 Z$ o6 `: \1 | w
EDMA3_TRIG_MODE_EVENT);' d. e) x% Y5 @1 {' m' i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' E& S% j" c- B% YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* j7 ^1 R- P3 z' D/ pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 H$ j j1 P. e; ]. v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 B- Y: B' c% k C8 Q& g7 x; Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; K/ z# r0 L3 m4 {9 a2 W& X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; V9 U8 m4 {) N' p7 c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. T* Z5 L5 |, Y* }" n. c! L}
4 @/ f- s+ a) C7 h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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