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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& ~ x8 S! p' g7 C* Z; _+ q
input mcasp_ahclkx,% F) S8 E* x) }
input mcasp_aclkx,
3 _' H8 A. P( }5 s- w% @4 Finput axr0, `; K% Y0 ? M2 X
- l7 I" h/ I# ]/ j; v T* Goutput mcasp_afsr,
1 u2 y" `: t2 I0 w9 eoutput mcasp_ahclkr,9 y; e$ \8 `% z: ^0 @8 s7 S- Z
output mcasp_aclkr,
* _- @* J: G; f/ w: c# o: N( noutput axr1,- r+ {2 \- k/ l; c/ A
assign mcasp_afsr = mcasp_afsx;; ^; [% W+ }" S. g) q9 R
assign mcasp_aclkr = mcasp_aclkx;; e8 t9 G, M/ _2 D
assign mcasp_ahclkr = mcasp_ahclkx;
" {9 ~4 k) B8 L$ f, a& g- u" f/ Sassign axr1 = axr0;
% R3 M, w& M3 t) H& b9 D1 _: d& K3 l6 U+ Q7 l/ n# {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " j4 F& J8 [% I9 [2 l
static void McASPI2SConfigure(void)# a- z5 j* _: V$ F. \
{
1 o) A, T+ [: a6 l1 m, gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" Y6 Y* H* y6 ` [ D6 n% g5 W% r( ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# Q. [3 s/ a$ E. j& C3 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ N" |6 X* F. X2 i! \; Y7 v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 C# D9 @1 y3 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) V8 y8 p( Z) }/ r% ]# w( W+ q) p
MCASP_RX_MODE_DMA);
# f s" p# B2 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: U l9 j$ t6 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# S6 n0 ^7 D' \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " i* `; J: p T5 p- s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; n# r: _/ }* E1 }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 D( s- i7 I3 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* k; b1 {/ ]3 H9 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' m; w9 B5 g$ J/ i0 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. |6 K6 _3 K1 e2 Z( XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% o) B" a. ^$ i: |/ o
0x00, 0xFF); /* configure the clock for transmitter */) y# x& l8 g$ N8 K9 I! M: f$ q5 u8 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 t% ^" G+ ]; O( ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: A, @, X! X7 D7 f" K% BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 `( N* m/ o- t0x00, 0xFF);
6 l5 \5 W! `4 B0 u( I
* m3 f* C9 w/ K0 C4 u$ B/* Enable synchronization of RX and TX sections */
7 p9 s# A- c( h0 P; d, ]# y% yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 Z$ T, }" S' k4 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# v( Q1 x* x! J" K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 ~8 }2 p1 g* o( [** Set the serializers, Currently only one serializer is set as
) w6 h2 N2 i' u8 a** transmitter and one serializer as receiver.
( k( D; {! A0 L9 i; {*/
+ g" S) A2 k1 C$ w0 i2 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, r! W( y7 w; G- U c7 r' ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- K* g5 E; Q/ X# X2 V4 y** Configure the McASP pins ) g' K5 E0 C) \7 Z8 x
** Input - Frame Sync, Clock and Serializer Rx& r; K' W% x" c5 Q! j. Y( N
** Output - Serializer Tx is connected to the input of the codec : m+ B1 R8 V, U; l
*/ n1 s1 N9 J! V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. f; _ w& b! m, {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( C3 ]- S9 c* b; S2 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# O/ g, w0 g2 M4 ~| MCASP_PIN_ACLKX' K" `/ C" h( @0 T3 C; `
| MCASP_PIN_AHCLKX
& u6 ]8 |+ q, n* `% l3 W% ]+ @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 S9 N0 g4 V4 L8 E$ g( r% l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 y7 u; g( z& s6 @2 D- `
| MCASP_TX_CLKFAIL
$ F0 s8 K! Y7 x| MCASP_TX_SYNCERROR
% n8 u+ ^1 T+ G* W8 |' h ^! s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR @/ d3 G7 J: E/ {, G R3 N
| MCASP_RX_CLKFAIL; v$ L7 o& Y$ V: Y9 P( @
| MCASP_RX_SYNCERROR
' D) W/ }; H3 `5 l$ W| MCASP_RX_OVERRUN);
2 n# |, {. u3 y9 V8 c& e Y/ w} static void I2SDataTxRxActivate(void)
( w: K" q. ?! {& T; {{8 ?- G3 a6 c ~; V1 g
/* Start the clocks */
, }- W+ _! J7 m% X1 Y7 ?+ `2 ?, rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# h' I. ^8 i6 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! h& p5 q4 j, ]# `3 K) n: `/ t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; W- d8 }5 |+ a: kEDMA3_TRIG_MODE_EVENT);0 K# {5 k% ]* g, v2 ?1 M9 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) [, W0 u7 V9 q7 B, K+ {4 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! r+ l( L0 i5 O* R. d0 B9 t. O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- Q2 w# i7 x& a5 V# x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# e3 G$ G. f l9 u6 U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# c; W! s2 _/ l$ s" B _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 {4 j( }' V! p9 K/ b" AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ R$ u0 b9 g/ u V3 K7 y9 p
} : |/ g5 U1 ?5 x+ A" ^/ g, d" v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 t# Q, H1 Q8 C
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