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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* p- c8 h$ [4 }* O5 R
input mcasp_ahclkx,
7 A! O9 H8 k h/ C! rinput mcasp_aclkx,
% K, R2 V4 _1 X4 C- Vinput axr0,/ u- i: T* N. C. r
: s+ F+ {! A; N9 }. W: W
output mcasp_afsr,* Z8 V8 O. @7 s9 ~% x. D
output mcasp_ahclkr,0 N) k* P, W8 c. x7 L5 Z
output mcasp_aclkr,
- K2 j6 j: u7 p3 moutput axr1,
" h" R! h* |8 g7 k5 Q5 ~# U# O$ ? assign mcasp_afsr = mcasp_afsx;
0 U; u% n* N$ @; [7 oassign mcasp_aclkr = mcasp_aclkx;
' I' E9 g% N- ?# j' V' }assign mcasp_ahclkr = mcasp_ahclkx;
2 `% D, }8 ^( aassign axr1 = axr0;
4 l+ C6 i+ {" N* L' i2 A( a& Z% K( d0 q j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% I% X, v Q4 ?( c1 Ystatic void McASPI2SConfigure(void)
+ n3 F3 m- Y7 r% t/ ^: [{
: u7 _ }4 R2 b: ~. Z5 Y- ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# {. q( O) \1 l: K/ K a, \ bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ `, W- P$ y; d# \ [) bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! u- M* N/ p: RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 J, c+ m$ v: J5 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 O5 g1 Y. I/ I5 ~+ N; B vMCASP_RX_MODE_DMA);# [" z& f- k0 K2 @5 H7 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 k* B4 x, g' _ @* EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 Y& L. o* r5 F' ~, B' XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 v, l- C( c1 X3 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 G1 V) E7 c4 m& P x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. @- f' U/ p( s3 B" pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; ~6 w$ D# B2 J4 J8 M* Q6 RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 v* }! H5 u0 [9 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, ~. s8 j! H1 U0 i* QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ B% L3 O2 C7 w' L6 |0x00, 0xFF); /* configure the clock for transmitter */
I; p) a" Y$ R. }) DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; ]5 S* z. f% ?& E$ O- ^& qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 I! L- L3 D+ v* W- Y+ M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# u7 E5 v$ L( ~3 x
0x00, 0xFF);: ^5 Z# B7 s& b+ A. Z& F8 [
8 j) c3 v4 g& I2 p
/* Enable synchronization of RX and TX sections */
$ Z& |- x* U$ a. `8 ?' }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ r$ {2 ?) [3 X, _; n6 B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( `, ?, R4 ~, |! L' s: }" { e2 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& o$ a- x* F3 v4 ~** Set the serializers, Currently only one serializer is set as! O, x* F. d( S- p
** transmitter and one serializer as receiver.8 k. W, E6 h( G
*/5 i. a D# O4 |1 L. r/ Z. r4 L/ C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ i$ ~" u7 X0 w7 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 t9 i5 t9 F2 \' U** Configure the McASP pins 0 x. D8 S) {. b6 O- y$ E
** Input - Frame Sync, Clock and Serializer Rx
# E$ V) I; l. {** Output - Serializer Tx is connected to the input of the codec
0 [! s7 }7 Y- ^# m3 u& Y; \# H*/
: P% Z0 a7 R* W9 f" V+ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 q4 N- F3 N$ p: x. H) }0 KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 E7 W r7 K' |: Y: H* B5 U% S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ A9 k/ ^/ U: G/ F. A$ D& ?$ B| MCASP_PIN_ACLKX
! b7 s: u6 _( E L* D! g" t| MCASP_PIN_AHCLKX( M# Y; h- d. F, @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 x) g2 z/ h* ^7 i/ L X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 q8 e. B3 V4 D: e* x0 h f| MCASP_TX_CLKFAIL ) ~7 W' D- S. \
| MCASP_TX_SYNCERROR) H$ J H& |" w, m1 K4 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 Y4 L u2 G2 c. F( _| MCASP_RX_CLKFAIL
2 v0 v9 r' S' J5 j) N8 t9 a| MCASP_RX_SYNCERROR 0 W" i0 t h/ ?* V" o6 _+ e3 j
| MCASP_RX_OVERRUN);8 V0 k+ R' p G# G
} static void I2SDataTxRxActivate(void)
1 o' u9 X! h+ K E2 a# g- U; Q3 Q& G{
& S. ]9 o$ s* @+ l/* Start the clocks */
. b3 l, P% X/ mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 j8 d& p% i! ]/ R% | d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 l' |5 R- q, u: ^ I" CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( F! \, W2 I P3 U& X+ rEDMA3_TRIG_MODE_EVENT);# `3 x1 {$ h: Z4 `- L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- V B @5 h& K( J" d4 m( {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. j, B, Q s6 b* ]7 i; v% s U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. u1 Y5 l4 @! ? y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) \8 [! ]' v. S% A& i& Q$ D1 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! o' y4 n# S a* J) z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 W' E9 M% A8 |0 \( I) S8 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 R$ |0 q0 p- {1 d( ^} 1 G# Q9 {: T5 o' A& q+ n$ ^9 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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