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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
L8 ]) r- S2 W% E0 |6 z' jinput mcasp_ahclkx,0 H$ I4 ^( c* J" N K% K! r
input mcasp_aclkx,
/ K7 N" E/ S( s; b, O8 zinput axr0,* @% _2 h& n2 z- }% ~ q! L7 h# S2 s. ?
8 e! ?/ z+ \$ \, `1 y- d) K( N6 Poutput mcasp_afsr,
2 {$ e$ u [* S+ e. T4 G+ L3 H& Xoutput mcasp_ahclkr,0 M/ g! w% }' g
output mcasp_aclkr,! H1 Q' @5 t1 W7 ~3 t
output axr1, L0 J( `) Q' `! _$ c# H
assign mcasp_afsr = mcasp_afsx;9 [9 ^% {! s& V# x
assign mcasp_aclkr = mcasp_aclkx;
" u" s- `2 ?. e- d1 A3 b3 Wassign mcasp_ahclkr = mcasp_ahclkx;7 H1 z" b# W3 j9 ]9 T
assign axr1 = axr0;
$ m& d$ z# c3 t! {# {" X8 @+ W' V: p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 N& t: A U3 X4 n1 W
static void McASPI2SConfigure(void)" K2 Q M5 w: x- {9 r4 M+ l
{1 b/ f- b" G4 |- M. d8 j8 Q! z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 J, O! J* g b% jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 r7 n$ X |2 r# v/ g% sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: @5 ` X4 v D. a, j9 g. lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 k& x a" ~4 t1 Q; e3 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 `( g2 ]0 |0 _
MCASP_RX_MODE_DMA);
2 A v$ @5 m' L+ xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 e. M# Q% W2 R. eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, A+ l& y2 P) A0 ]1 W# PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' E1 H/ i! T: B! \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( B$ ~( o$ S3 ~% G8 s( A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- Q% j3 W( e h& V" V7 g. eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' x1 @" {8 E( c% j! mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ N8 |3 j2 a' { l+ o! N+ AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( ~& [$ r$ ]( g) TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% r& M4 J% r! U# ~( O6 j0x00, 0xFF); /* configure the clock for transmitter */
4 U+ l9 K1 ]9 C' k" m! KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 B' j. F, W0 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 \4 K9 t, H4 Q$ v1 e& \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- b' ?* \1 v% F' |7 `3 Q0x00, 0xFF);4 H4 s5 K. f) |7 I5 Q i$ ^( v
9 D7 C! Y4 y k! N' [2 w$ P" e/* Enable synchronization of RX and TX sections */ ( x/ @9 t' S* c# f0 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 s6 {4 j+ K! }9 L C2 ]( eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ |5 y7 y6 V$ p4 V, O4 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** R7 M `' P4 R
** Set the serializers, Currently only one serializer is set as% f% |. @* v4 J- F4 J! t7 U/ m
** transmitter and one serializer as receiver.6 P7 Y, M2 s7 K( j
*/
3 S" L' U+ T2 @% F$ JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 E; H- a; [- L n$ h, p2 F5 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 ~$ `; G& j5 h2 C0 c# j2 [ }
** Configure the McASP pins , t# F" n% h: C
** Input - Frame Sync, Clock and Serializer Rx
: o8 |: }3 x0 T2 V" C% O& I- j. D7 g* O8 z** Output - Serializer Tx is connected to the input of the codec
/ t( g2 W3 U2 l" }6 H- Q: a*/
9 _) x" |) q7 G8 E, h* f2 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 N$ u, Y4 U2 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 \0 O( _1 K- ^% A/ T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
T7 [5 \, q" T& K( S7 Z9 L- ?: _| MCASP_PIN_ACLKX
% P( u0 o" J% F# E0 ?2 h| MCASP_PIN_AHCLKX
9 L6 Q4 I$ N2 w! C# f! V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# ?6 j m! P# H* {# ~% Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 F! D) v R" n9 ]1 \
| MCASP_TX_CLKFAIL
- {+ o6 W \; t# A| MCASP_TX_SYNCERROR" B- b! B* j8 d/ G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 G5 s' Z; q! S# K# b( d9 w| MCASP_RX_CLKFAIL
4 C$ E0 S" }8 H4 Y3 d| MCASP_RX_SYNCERROR $ L3 K Q) D: s
| MCASP_RX_OVERRUN); F" W% [ ?9 L
} static void I2SDataTxRxActivate(void)
" `, G2 m7 W% W( x{
( J) B; ^% v2 ?$ L+ z/* Start the clocks */7 b5 S; k9 x, w0 Y, i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) N$ ^, `8 w+ a8 w0 RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) @; d/ z+ h$ Y5 `* Q, iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; s' T! e; l' ?; TEDMA3_TRIG_MODE_EVENT);) c( g. H- B& a+ f7 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 _7 U- {% z6 T5 v6 z7 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& u8 }6 a: R% M/ _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# ]8 r+ v/ M+ J! u. b6 \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. \8 |3 e& o: \* u0 s, P1 o jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 P& Z1 x. X. I" ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! u8 F& |# L: b- ?* N6 C& ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 Q1 K4 D2 u4 t3 E} + r6 _' O$ L! R" O/ R! _( X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . |. |: x/ v$ q- i: y3 y$ |
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