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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 Q: m9 d- H" O+ L1 }4 T6 k
input mcasp_ahclkx,
8 l0 c, D5 \3 F' R Zinput mcasp_aclkx,
1 `4 _$ w) j- I8 d% ~input axr0,) f5 `5 |6 I. M( u% o5 `4 U4 y
6 E4 M8 V- U C0 A( \% F1 S
output mcasp_afsr,+ ?- s8 k. s# U+ W) {1 n" X' ~' i
output mcasp_ahclkr,# E7 y* P! W1 q2 O9 M; q/ a
output mcasp_aclkr,0 R8 m4 K* |1 o$ ~0 q6 |" [
output axr1,2 R$ c a1 j3 Q; ^6 r& ^8 f/ i
assign mcasp_afsr = mcasp_afsx;
7 h# ]/ w+ M9 c2 I6 |) iassign mcasp_aclkr = mcasp_aclkx;" @2 _# m6 ^. N# V6 B7 g5 Q, }4 U
assign mcasp_ahclkr = mcasp_ahclkx;
+ ~ F5 q6 z) ~- Nassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & d# M" G7 V% V( R+ k
static void McASPI2SConfigure(void)
4 f3 F( D) J: h p+ N{
% p- j4 h3 F/ G6 L7 o) ^; _McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. `6 o6 ]: U( g m6 O* O3 K/ }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' V9 M# e3 X0 y8 U# O: K$ }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ g+ @- E* i5 u8 n" mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 J5 W6 N& @0 h- f/ X( P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ [* r6 D; M1 SMCASP_RX_MODE_DMA);
( N x, E. i2 {2 [4 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z: U$ u3 T/ r2 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# C7 [$ v7 |$ N4 n4 z" Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & ^ U* A) I3 i2 ^6 i+ Y: |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 _ L! ~. z' A* K2 E3 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( }0 g% t5 F$ p! R# M; K3 y7 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ y6 P2 s, K! c3 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; O$ h" F9 P8 A: wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * e8 Y9 E/ k7 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 {( l$ s5 T$ X$ ~6 H0 [: S0x00, 0xFF); /* configure the clock for transmitter */9 f6 \+ h% B, S- D/ Y! S z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# G5 ? X- M! i$ _! d% f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - l* m D4 v. Z8 b' X/ G7 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, e0 Y# H2 U" C/ ~4 q
0x00, 0xFF); `5 Y% B- ^2 _: V( l/ }* z
5 e! ~/ {6 n* L( f( i
/* Enable synchronization of RX and TX sections */
- r) K* Z# f/ q0 z0 k q3 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 a) c: E4 d" [1 i3 H) Q7 u& QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! I( Q U( K' X3 K' T5 j1 @+ o$ ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! ]# j/ A! ^6 U' |** Set the serializers, Currently only one serializer is set as
8 V: g- o: T) e** transmitter and one serializer as receiver.
+ M" Q4 t$ E+ s) k* V*/# I! k5 e' I1 D. y5 D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: ?( ?. J% F% P5 X( O6 w) R `' qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* v) f; z6 q: p. }+ W' x** Configure the McASP pins ! L( K+ p2 d/ H; p
** Input - Frame Sync, Clock and Serializer Rx) p7 b n; y" j8 R) `* Y
** Output - Serializer Tx is connected to the input of the codec 9 p0 K/ w+ k* [2 c: P
*/
9 D( w: g3 X; K" d: i0 ?# VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); s* | J; S3 @% w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: h$ M4 T1 C& H8 b+ F3 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) ?7 ^- b( X( u$ Y8 n, v. D) U" }| MCASP_PIN_ACLKX
, t' H8 Q/ Z' c- o1 |, t| MCASP_PIN_AHCLKX# U k X5 Z0 J( b$ x1 q5 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 |6 X+ Y8 O9 q+ F/ I2 m( l% EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 J0 v! O' x' x; Y; C+ L| MCASP_TX_CLKFAIL 8 s% R. b; z: W' _& k
| MCASP_TX_SYNCERROR2 {" k: b5 G* d4 W! J) m+ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 A( J" c0 i7 @, v1 {| MCASP_RX_CLKFAIL: W( u* T2 J$ n# @5 k N
| MCASP_RX_SYNCERROR
3 U% e) g0 L" J {| MCASP_RX_OVERRUN);
% j0 t2 N% k5 {; E9 x ], _} static void I2SDataTxRxActivate(void)3 T: Z: x- J4 M/ o' ?: o3 T! \
{
$ z6 n" h- [6 L$ ]& v/* Start the clocks */
/ s0 U% z: L$ r+ K% W. |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& \. H3 q9 {# \2 C0 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ o% ~8 T# @& p2 L# W+ Z+ {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ X0 w& J9 w- A0 B) y7 c$ ~EDMA3_TRIG_MODE_EVENT);* N7 G- r0 ]+ L/ t1 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 x* j' q( b; OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 k+ G1 u# l* I7 `9 G: G/ KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ C# X9 M$ _+ Z0 Z% v8 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# F; n9 i: u& y8 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 y6 L1 r9 B: R* h, M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: r8 i( E0 S3 b' QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ g& }' c8 Q- U. G}
* c" t! [5 q& w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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