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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; `/ ^) C" h. p$ {9 M- i6 Ginput mcasp_ahclkx,
; r! X2 G# k. ^6 ?1 @2 c; H5 einput mcasp_aclkx,
1 B8 T4 o8 [3 E: {input axr0,- m9 s) `5 c6 x9 Y) n# d$ y) }
0 x7 L. E4 Z q
output mcasp_afsr,
' t7 w* _8 i: _( m& Y' \output mcasp_ahclkr,! N+ E t" r$ p# o9 z& z+ S) x% |6 H0 r
output mcasp_aclkr,
+ n i* m8 L6 j2 A2 Q# Doutput axr1,1 ]3 \2 \6 t# \# ?' Z
assign mcasp_afsr = mcasp_afsx;5 J/ z- T* g2 R; |
assign mcasp_aclkr = mcasp_aclkx;
, Y9 v$ W* n7 T0 T. @. Massign mcasp_ahclkr = mcasp_ahclkx;
0 e' [- r2 L- r! Sassign axr1 = axr0;
3 v+ N( z" r, ^: v I1 Y
( @) e" _; |9 U& i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & y2 n/ G1 Z! n" ~, l
static void McASPI2SConfigure(void)
. `/ @0 d6 u3 H1 a! L* L/ N% o{
' [; W7 \+ u' j6 gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. R9 T; a3 n! q% S4 N7 |+ ~8 @7 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; f" C0 O( q+ ?" [# G S ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* X) N" K+ A7 [7 V& NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( @2 P+ n) z5 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( I( z$ c8 _! P, d- ~6 ^MCASP_RX_MODE_DMA);
; {7 K( ?6 U* `# g% d; a2 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- u4 ?9 ]5 @' S) I7 N* S7 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! a/ v; S: ?8 e# V0 o+ n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ m3 L9 U& v0 p! q' s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 m6 A7 ?7 r. w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 B- M X2 \$ Z6 cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) f" q4 S: K4 r! f! a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) B) w+ h5 P; h2 {/ o0 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 L8 n" d$ d0 E; p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; D# p+ ?# |# Z7 I( G* j
0x00, 0xFF); /* configure the clock for transmitter */5 E, G* L4 q/ ^- G: o1 B: N. K0 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 d6 q/ M m% |: [* e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! N3 X8 _: k# a" h& q% jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 K; N5 S5 B$ C) d
0x00, 0xFF);+ U+ g; d7 _6 [
5 C3 b$ S4 w7 H' z# T4 N; n
/* Enable synchronization of RX and TX sections */ - Y6 g* }- I9 _+ j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! I& t. R# f8 F. c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& J/ N4 I9 Z/ R1 ^ R% Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 l0 ?* _# R5 K' \
** Set the serializers, Currently only one serializer is set as
. e1 S# {+ a! u9 g** transmitter and one serializer as receiver.0 L" y+ @5 j# O% d' y4 R1 {; k# H' A
*/. M) N3 M$ W5 w# i. @9 u5 E8 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 I6 s" u. _* _, D4 o% U D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; P3 v0 f c1 q' `' t
** Configure the McASP pins ; e+ a8 R% k' q; f9 v7 _7 L5 }
** Input - Frame Sync, Clock and Serializer Rx
/ s( w( `: H$ |' D. c, b** Output - Serializer Tx is connected to the input of the codec 4 k4 E1 o: o! z' `
*/
3 s# U9 \& q( }. Z9 K# q; y' I: ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 X' r7 n5 B! S. ] D9 z, I3 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" V1 N1 d& |, b! V, z* i) Q$ b i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 f, P' m! _5 s0 M| MCASP_PIN_ACLKX
# h {; d* B. b( _+ n2 n# H| MCASP_PIN_AHCLKX
. {3 q$ x, A% ?# j- ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- R! n( O5 q3 @. N% DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ p9 b( ~, r9 O" r- z, Z| MCASP_TX_CLKFAIL 6 Y; K9 {; a+ l' A* t, L
| MCASP_TX_SYNCERROR8 `' }: R! M0 j! v: x U: d4 E+ R: h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 ~: V, E, D; D" i0 T" Q, m| MCASP_RX_CLKFAIL
" t' ?' P6 w& ^4 p* E6 G7 w. \# || MCASP_RX_SYNCERROR
" g! x" S( A# e4 x6 e/ v| MCASP_RX_OVERRUN);
6 j9 Y& N( L1 F2 I3 R} static void I2SDataTxRxActivate(void) ?3 [+ s0 w" c! R
{
) g' e t) x/ C1 n/* Start the clocks */: `2 {8 b: l8 q: V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' I6 q4 {( [3 z8 ?( P! d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 d$ p. s& B% {- p, l' GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# O( n# K( y5 s q
EDMA3_TRIG_MODE_EVENT);. H t/ K1 R4 p0 r, [6 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ T" \* [( x- ]7 x3 r* M5 sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: l9 i- H" R5 {' R- q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ J* c0 h- o) ?( [2 Q4 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; t2 V2 o+ w- e. wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 c2 l& k$ W7 i' U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& _) J& f$ V$ T5 Z. m7 d+ s; V1 Q; pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: D- F# R1 h. L) k+ ?! \+ u} 0 [- D. D; l4 P" Z" w% u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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