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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 [3 r" a. C" Uinput mcasp_ahclkx,1 k% X0 L1 p" t3 W+ V; d: b
input mcasp_aclkx,: U: f; X# H+ G" `
input axr0,
* d0 J. y- p6 ?+ g! P2 X: H
, ^' ~; G2 @/ D3 [! ?' |8 Voutput mcasp_afsr,1 K# ]2 ^0 d/ L3 u" M
output mcasp_ahclkr,
2 }/ l/ C2 }/ voutput mcasp_aclkr,& n7 T0 V4 P( t+ V3 B
output axr1,) K6 G1 K! C' s2 |2 y
assign mcasp_afsr = mcasp_afsx;. ]9 Q$ D7 M/ D0 _- N* L1 g( C
assign mcasp_aclkr = mcasp_aclkx;" {( D5 c3 Y q, n/ A" A6 t
assign mcasp_ahclkr = mcasp_ahclkx;
. q: g5 O- `3 |' n3 J/ Y1 Dassign axr1 = axr0; ' a2 N# W5 x8 i$ |
4 o( |; \6 W& y7 p) A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . r$ V& v! Y! r+ A. G! I
static void McASPI2SConfigure(void)
' t4 K/ G5 F* d7 E{; n! c8 w, |( c) C. O' o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. N3 r* }. x+ aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 u8 x$ J) R) d) X8 k9 B9 z; w% u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 z9 B J9 w* V; }& w8 n' L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. v* \8 G2 G) D- U% T3 O6 @2 G9 E9 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," @/ [2 K4 D$ A% p4 D+ e2 `* m2 h
MCASP_RX_MODE_DMA);7 @/ Y+ |; W5 `+ C6 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! C6 Z1 {) k9 l" `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 ~8 E( U1 O' f: {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' R" v+ C# u7 |# p, j: J8 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, W6 [5 K' u. X7 p! k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - n: r$ C" ~7 @6 ]. y- X. h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 A" o( m; a5 U1 a' d# I5 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( _# y; H1 a$ NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% C3 y8 U: [8 U4 zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: \, Z4 p! [/ ^+ x/ ^) K0 X% [
0x00, 0xFF); /* configure the clock for transmitter */
3 k8 V+ s7 E2 e3 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* K& Q7 J4 N: JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) A' [6 H& W; K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, C3 P# L2 S- n$ E
0x00, 0xFF);
/ l1 J8 W1 K. q+ [7 N# B m, q4 l% ?$ M8 o
0 m1 Q' i) H# f/* Enable synchronization of RX and TX sections */
9 V( g" ^. H8 W) ?5 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' t$ M, f3 }3 m! c' _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# ]0 z2 ^2 N3 x4 G: X% d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 B0 I% r* d) ?** Set the serializers, Currently only one serializer is set as6 e* x+ H, g1 h N
** transmitter and one serializer as receiver.3 |, R( b6 B6 O
*// P+ {8 Y1 n0 u9 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% Y, D F# w3 o0 E* R3 VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; x6 `# a$ k- r: ~** Configure the McASP pins
: ]8 U( V8 a" E( k3 r6 U. s1 l g** Input - Frame Sync, Clock and Serializer Rx
. q6 M4 d' ~ `4 s** Output - Serializer Tx is connected to the input of the codec
/ o& J1 Y) R5 b% y*/
6 z" y$ o y3 k% PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 D. d+ L0 X" H# pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, \" J6 E% T* s F1 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 i/ a; _, z1 F| MCASP_PIN_ACLKX3 Y) ^- q, _( [( x
| MCASP_PIN_AHCLKX
" p% T4 E# F3 l( v4 \% q) q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: v7 z" @* F" D+ F) m7 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( a9 ? I6 j8 b4 w| MCASP_TX_CLKFAIL 6 A. e6 b& S* k# E
| MCASP_TX_SYNCERROR
- J) \1 {! a% T1 b# p+ |# d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 @1 P5 L3 M6 h) ^ y; Q| MCASP_RX_CLKFAIL
$ j; ~4 d7 V9 ?0 r( ]( `& W| MCASP_RX_SYNCERROR
1 v2 ]$ Q+ ]" g| MCASP_RX_OVERRUN);
/ ~+ x; L" P t# Z* R0 K# Q& z& S G7 ~} static void I2SDataTxRxActivate(void)
" R Q* C k: ?. G4 ?; ~+ t* g{5 J+ t' Q& c( I* V: w _
/* Start the clocks */
0 x0 \" S, W2 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 Z5 V- s3 U1 C0 J3 \) U0 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// {5 \& o9 M2 I& n( j( r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 P I! {0 w9 K5 [9 B
EDMA3_TRIG_MODE_EVENT);
* ]7 c1 }# }, S2 T/ J2 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . s9 e Q/ ]6 f4 V: O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: l; e% n! `* F8 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ t9 z8 o; b( DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 y5 B% F1 _. j2 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ f3 V" e8 t, T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: B; ~8 Z- ]) ~; P' E8 l: v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 `; D; W8 M# t% i
}
, m5 f: {% O" |7 |) u' D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * h/ _/ R0 c2 o# _# ^0 o
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