|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," B2 ]; _+ C' B8 O
input mcasp_ahclkx,
/ V8 j, n" v& C: u* {/ yinput mcasp_aclkx,6 o3 s/ X* t! a3 l- j* ~
input axr0, l7 i' ?2 I( ?+ i: X
; @- V$ ]! \/ C" _
output mcasp_afsr,4 u, w3 K' q3 Q) m
output mcasp_ahclkr,) P' w$ G: W Z" G; F+ H, x1 Q
output mcasp_aclkr,& p" ^/ ^: Y2 S" Q0 {, S4 `
output axr1,7 h4 @. u4 T2 | @5 g6 K; ?
assign mcasp_afsr = mcasp_afsx;- Y1 E; j& r) d9 d$ ?- c
assign mcasp_aclkr = mcasp_aclkx;) A* a. M# ^3 K. a7 {0 b8 ]4 f; x z
assign mcasp_ahclkr = mcasp_ahclkx;
3 d2 J% p7 @. U( B$ @7 n2 H- C4 Wassign axr1 = axr0;
8 f) S! p8 y0 @% H3 h/ X( c% Z" ?5 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* u& x& o' p2 A! L' G, q' W6 ~* s0 Xstatic void McASPI2SConfigure(void): F* }6 { G9 h4 l
{: W$ H% q. H8 p7 J( k. t0 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# T2 ~: g7 I8 m: U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( Y5 [" z; C b3 {8 l" V. x7 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: F/ f* \# l* l8 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& u" N$ O' `8 e- t. ^; @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 \0 j' I, m F, W: jMCASP_RX_MODE_DMA);) K+ e8 a( n3 H4 r, K8 y9 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ c' U! ~7 F N/ m: {' y0 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ^, S; f$ N( i) n5 f6 i1 iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" H% T1 I( N/ |0 s1 v8 yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: d$ {( }! q( Y. [0 e& HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! t1 _' k$ X6 E& j% X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: w: _% m% S6 |7 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 r3 a' |* u9 H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# }9 i6 Y+ |" S" N% Q# SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- S" `0 P% N' h+ Q
0x00, 0xFF); /* configure the clock for transmitter */( C! i; u& W6 x. k4 S% _( b+ l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& G1 `1 T1 m" T5 B+ SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 t5 ~; }6 m- E, a0 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," ?0 ^3 D4 K; F: F
0x00, 0xFF);
" F/ ?% J& x. Y+ V6 S
5 ?- Z& \) `1 w* P! q/* Enable synchronization of RX and TX sections */ 1 R9 S9 u" C2 w- o% v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# }$ X; x4 C D# VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! k1 m( E; [9 q/ ?: E1 C0 J( ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 N" Z7 o1 M2 n$ X8 ~# q6 L5 S% t
** Set the serializers, Currently only one serializer is set as
2 ?( |( b [/ d# X) w6 U** transmitter and one serializer as receiver.' g4 ?# ^* C5 p1 o6 q; o
*/
0 U, C. |/ z/ LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" H/ d' }0 s' d1 L' N1 Q! N1 V+ v1 u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( F& t( w" Q7 _0 X
** Configure the McASP pins 3 W6 E I& Y3 T
** Input - Frame Sync, Clock and Serializer Rx
9 y8 i7 U1 Q& J3 Y- @( T$ [& X** Output - Serializer Tx is connected to the input of the codec . `$ w( J. W5 S( Z9 P6 b, ?
*/. I+ a' q) [( U, M! y. g# n7 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# w; @$ M. z4 M8 {3 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ A7 L8 |2 L2 X" M( i1 V; pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 J- k* p0 ~ G% L2 v6 j| MCASP_PIN_ACLKX( \2 e+ P: j3 I
| MCASP_PIN_AHCLKX4 E0 g6 b6 }$ o) {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 [: e; i3 s& u' W4 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
d" i3 G9 y" F- E/ M" i| MCASP_TX_CLKFAIL 1 M" b. C) Z U3 u. n* z1 ?9 ^4 q
| MCASP_TX_SYNCERROR
! U) ]- _" [) C2 T" r4 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 g* V x. r! f! X$ S" d/ @
| MCASP_RX_CLKFAIL: F. M+ t+ S, ^+ S, h
| MCASP_RX_SYNCERROR 4 n7 ^1 p0 V. d3 t' x9 t0 C0 y& C
| MCASP_RX_OVERRUN);" L8 b1 R* o4 R& m
} static void I2SDataTxRxActivate(void)8 ]' ]) y" h4 b% ?! ^* j* S4 S+ w
{1 `5 _# t- Z% V k; |
/* Start the clocks */
# a v; r; g- N4 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. R9 R/ q5 n2 _; [, V4 B2 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ h `( I7 k$ A+ `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" y; R0 x, p7 V x+ ]EDMA3_TRIG_MODE_EVENT);- T6 t1 V$ F& [ b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( `& s+ M5 j; t2 b% l& }7 m, Q: dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- S# C/ a6 I4 Y) p" P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: s4 D. V6 q' L! p7 f6 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 O# e$ t8 a P& N/ o0 H3 B2 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. k) B% ^2 S% i% k8 K# xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 z1 U4 G5 l3 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% E+ Z8 x: Q8 m9 w7 V* j1 i5 n} 4 t8 H: i+ x/ @4 [3 K3 W* O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; X. `8 E; @3 p, [. r9 w
|