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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# g/ A. q2 n0 Y9 @, p* Sinput mcasp_ahclkx,- y2 ` I3 {6 k
input mcasp_aclkx,
3 H& i: X8 r) a1 |input axr0,7 f7 X$ ~- {+ [% ?+ O( h; b6 R* M
# _+ h' e, F3 ]4 d* [/ h& }
output mcasp_afsr,# y3 L# k6 M$ @% K4 l$ W! r3 S* {
output mcasp_ahclkr,
7 H, H4 Y* s& C- F. J' N2 z, {output mcasp_aclkr,
: `. t1 t9 N& k; Z b8 x& woutput axr1,8 |5 B+ L$ Q! C1 H. j
assign mcasp_afsr = mcasp_afsx;! [4 o- T; k; d, A# u
assign mcasp_aclkr = mcasp_aclkx;8 O: B2 `1 t4 r5 V3 n l; X7 m
assign mcasp_ahclkr = mcasp_ahclkx;7 V) z f8 u5 r( ~' ^* q) T
assign axr1 = axr0; # S) K# o1 x+ E% I1 @
; o, x( g, S" W' b: y9 X. @1 I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; ?( s( q) W+ u; F8 L9 \, p) dstatic void McASPI2SConfigure(void)
' M; Q& E/ W3 r{4 ~/ w: b- N* o- G3 E1 g9 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 h6 R) w1 `* N' Z: a3 DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 g% C6 i- ]) X& bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; Y$ H; \; B! j5 A( f3 d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 U }2 h) W% r3 C5 x" C. B" l; r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- S# `; o3 P7 k0 |: G
MCASP_RX_MODE_DMA);
* O. X X7 Z) v) R- C* G! A' }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; G3 F! V( o" o" O1 T4 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 o) x o# R$ \9 @3 H7 m: ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: U, \: i! c$ s5 A1 `. iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 ` [8 L1 v' ^, m, q) w8 ?% M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( M/ ^7 b1 M" ?5 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; Y$ U9 j6 ]( Y; r+ \) {3 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); D. b2 h' ]& f) O; P g4 ~% k0 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 P6 P1 t. Z/ l9 q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& y0 V5 P2 P. \8 u; \3 i0 U+ k) O0x00, 0xFF); /* configure the clock for transmitter */
( ~& Y2 r6 Q7 A7 QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ Q; F2 o, {( v" j7 b2 E% _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 ]3 i% }, X6 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ d" X/ k/ n0 C$ r( Z! ?
0x00, 0xFF);
9 r0 w H9 B, u# ~* y8 i" g$ {& O8 T) {) v/ z7 |
/* Enable synchronization of RX and TX sections */ 4 M2 {" a! y# S& s- N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! S8 r( K; ]' V4 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( R1 H$ \, q% N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ L0 k; a* T1 U# p
** Set the serializers, Currently only one serializer is set as
: x8 w3 D* V- s" @+ ?** transmitter and one serializer as receiver.
2 U' W, _$ D' p, C) R*/
) ?" y z5 ?8 c3 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* H5 _2 `: N$ s" n8 K/ F: a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 h8 t: }5 [3 b: F6 p* {
** Configure the McASP pins
- |: O* ~* s: S3 v** Input - Frame Sync, Clock and Serializer Rx1 e1 s1 P4 i8 F8 |" N
** Output - Serializer Tx is connected to the input of the codec
# {! C- W' m" m2 i*/
8 h% @$ ~2 c, T. U0 G$ `9 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, k: S8 Y) \+ G0 {7 h8 c1 J2 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ z- B$ x8 p9 U8 c0 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ j% J% E% ^1 |( h0 `7 k# X. V
| MCASP_PIN_ACLKX
! r: ]2 [# ]% X) T2 ~| MCASP_PIN_AHCLKX
: e* K1 K0 ]" [! [/ U! c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: h) M- G/ p: d: {( M) o+ w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 Z7 i: H) k: X" h, w
| MCASP_TX_CLKFAIL
; S9 q- \2 D) C0 _) r8 q| MCASP_TX_SYNCERROR4 _/ D3 F% M) [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: e: Y2 [7 z+ b! v| MCASP_RX_CLKFAIL
1 ?+ s4 O* U/ |- p3 N$ i3 H5 G% `| MCASP_RX_SYNCERROR 0 L Y6 x6 a% D$ ?' g! w! L u9 s- Y) f
| MCASP_RX_OVERRUN);( ^8 M3 o8 \% l/ t# p6 S' p
} static void I2SDataTxRxActivate(void)
- A3 v: [: J# Y6 F Z{
" ~ `( G* c) q6 P J/* Start the clocks */9 N; ^" L1 k1 k; c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 X5 }0 z( z( G% jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& H: t/ n/ Q. ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 {. d" y3 L6 r3 p! ~1 m
EDMA3_TRIG_MODE_EVENT);0 S" z- Y- |1 v# E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 N/ g2 k) x. r p0 X4 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: Z6 c! q+ C# }! L9 c. b3 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( h5 c6 G0 ~2 }9 [0 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* t) o$ O0 L. @! V" }4 Y6 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 T: N3 F8 Q" Z0 F2 ?2 T+ E, Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- m* k9 M7 B9 IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# l3 b4 A% M, w5 B
}
' v6 t, o' X( g9 P& t/ t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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