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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 J2 W; |% F8 _. b! s' i8 q5 X5 I
input mcasp_ahclkx,5 n& A2 @2 h) ~' H. {3 F
input mcasp_aclkx,
8 I( }2 \; |' ^3 s# jinput axr0,
3 R7 I* Z$ F8 K% i2 f' Z
. [# I g: |1 `8 G, coutput mcasp_afsr,
) [; c( r. Q ~+ [& K* goutput mcasp_ahclkr,2 ` c8 ]! q# Z$ |, @" F; ]
output mcasp_aclkr,
$ h& p6 d7 G7 k; Z1 n$ @output axr1,& ^' j. E% s3 X1 |5 R
assign mcasp_afsr = mcasp_afsx;
# s. o1 R* v7 U) M7 l9 eassign mcasp_aclkr = mcasp_aclkx;
1 H# c+ @5 G9 R7 |, m9 Hassign mcasp_ahclkr = mcasp_ahclkx;- k5 ~1 t( @7 j* a9 \
assign axr1 = axr0;
& k9 G! j( U- m6 s; W& E" R2 _; w2 Q# I4 d, P( U9 @8 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( j) R- Q: G+ B C. j Sstatic void McASPI2SConfigure(void)% t: f1 E7 {; Z! ^ o" k
{
% U; ~3 m- f4 gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, N2 b! j- m& }& @1 a2 i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& @3 P- @, K+ b! E) b. Y( p2 K7 kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; D) ~8 _ i0 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& B1 t, j) }* @1 l6 g& e Y+ v7 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) t- t! i5 f8 H( S
MCASP_RX_MODE_DMA);
/ h7 i( h' I# \ w$ d* yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ v3 ]% B6 {% A& `: O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 Z/ T' z$ F0 U! l) S/ K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; s8 z9 h( n( B5 ~7 E7 Q& [' VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 |& `3 \ q: x+ F% W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 l1 }& T+ W7 C2 a. EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. ~( r' U/ r: p, Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. X2 c2 ~: P0 |0 N- ^$ {7 nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 U, _, [/ L2 X( TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 {; g$ |3 V9 v
0x00, 0xFF); /* configure the clock for transmitter */: U0 r/ v5 s' n; H* v9 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 O: R! |* p# O0 s; WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( ] m2 U ]+ f* z8 U+ P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 J2 A0 J# K5 C* }
0x00, 0xFF);
; I. p2 @; K5 ^! U N+ @+ ]: F( E3 G |- H5 x! v
/* Enable synchronization of RX and TX sections */ # ?: e; V B2 _) I3 ]6 Y& R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- v3 Q3 I9 `6 H: O4 n. W- _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* c7 U t0 u5 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" [0 ~3 |+ q) I+ o
** Set the serializers, Currently only one serializer is set as# Z/ S3 k+ C) J' b4 ~- R
** transmitter and one serializer as receiver.
$ I) F3 d( ?$ y2 [8 E( m; c$ I*/
9 o3 F3 b+ L, ^# X2 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, R9 \, K+ V1 J0 S! z" \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- r9 L, v2 X. q( a2 m' @
** Configure the McASP pins , l, s3 J% {* B9 P
** Input - Frame Sync, Clock and Serializer Rx
% t! F0 ^! l2 { B** Output - Serializer Tx is connected to the input of the codec
; D4 K+ d' ?# a* q0 F* a4 ?*/
7 I. O% {1 f3 g) I( D( u' u! pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! z2 k* R0 V! b0 q% a# G0 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 W) k0 n9 ^6 c/ E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ x4 D* m+ k0 Z
| MCASP_PIN_ACLKX, E$ f5 u# E' x
| MCASP_PIN_AHCLKX
$ q. u% f) p8 @, @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ S5 B$ s' R+ X1 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 l2 l9 |3 a {3 P* d3 {! B! S2 O
| MCASP_TX_CLKFAIL
" B. T/ k# e' b4 B" I* Y| MCASP_TX_SYNCERROR D7 V; u6 `& j o* }- T5 |! C% m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % L3 o4 y, W. a( x# O
| MCASP_RX_CLKFAIL
( F+ F0 g$ ^9 C) o, O) D' T+ A1 a4 w| MCASP_RX_SYNCERROR : a3 m6 J4 A! P
| MCASP_RX_OVERRUN);
& ~- o: f6 f6 G+ G9 z0 L2 k- T8 m9 _} static void I2SDataTxRxActivate(void)) x' d0 Z$ y: Q) `/ u9 Z- q
{( X% X; X& |* ^' o3 m8 H8 S; M5 g) j9 K% u
/* Start the clocks */
6 { q8 y X' J. p. \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 \: l9 C+ P& Z, }8 e3 Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% O9 ?- k! _. y9 P! oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 B: ~) z0 T1 Q L
EDMA3_TRIG_MODE_EVENT);
R8 x! C+ J4 d/ P2 \1 o# j" x1 d8 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % {0 i* i; Y5 p+ x5 s/ X" r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 j: B3 y1 Q7 C- A# A) |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! G Y- y- r8 i4 `( jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# {1 k; |, o, u& m" o9 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 h3 v/ g9 e+ U' b! kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 T/ d& W& J6 x _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ T+ D$ i, t# ?9 V2 _* y/ H% ]0 \$ E}
8 Z0 Y, M- Q; c5 q- m8 b. n$ W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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