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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- w1 C% O4 I$ v0 G& E; Oinput mcasp_ahclkx,
5 s9 u+ }- q$ X! `) F4 Qinput mcasp_aclkx,9 B0 L, [# {( c0 R. |
input axr0, O& v1 A( {5 b7 r/ I1 ]
e9 o' O0 d; q: ?) m; joutput mcasp_afsr,
6 D2 s, w% L, I# B7 ?) i) ?+ joutput mcasp_ahclkr,
( q7 a2 ]& f5 X; B5 ?output mcasp_aclkr,% m: R' s$ Z+ D1 }0 ^ Z; h% L0 H
output axr1,, u% B! G. D9 w5 D
assign mcasp_afsr = mcasp_afsx;/ b* |8 c* q+ m/ T# L7 X
assign mcasp_aclkr = mcasp_aclkx;9 B: V4 x% \7 h4 U( S6 ^2 h
assign mcasp_ahclkr = mcasp_ahclkx;8 Q; m4 b ?6 X: b |
assign axr1 = axr0; , {6 ?1 W$ `7 ?( s" V: k
t. }9 T; @: n' u% b8 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( D J( p# u- Y3 k) y# W8 F% Cstatic void McASPI2SConfigure(void)5 J% S! Q5 T# T' }1 g! t5 D4 N
{$ Y u4 |" q/ b, g5 b9 Y/ h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 R6 k9 g2 c8 v; \/ oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ J. v$ b2 g: y+ s7 f, @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; b; T4 E2 U) C& x
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 V9 H N, a) c0 p& y k) D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 p' W3 o% a% ?/ j$ n/ O: X" ~; J3 n* D
MCASP_RX_MODE_DMA);
) ?; O2 \4 M7 a) h* y J3 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 X5 C2 l3 }" O- _/ E$ V" g+ t; c1 AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 H( H I% A$ w" H, yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# y, m: ?. _4 n2 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ n) _/ y) H5 `" M. k# n5 K7 _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ T8 f c0 d* \; Q! v V( e# H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' L# a4 |0 O3 f9 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 D) Q( `! t) J0 v4 W1 R, Y% y: ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; I0 J# } B, x; Q: r7 {* JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 H/ `: L5 B |2 y2 I1 V1 l0x00, 0xFF); /* configure the clock for transmitter */
8 ]. R ~2 f; g" S. Z5 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
[$ K' t$ e) \" ^" a* IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( P2 _' x* ?( w4 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 g5 R( f3 b! m A, e
0x00, 0xFF);6 x# P' J/ x4 @% O& ^, U* b9 U
) w! N0 m* J+ d' i; \! C. C/* Enable synchronization of RX and TX sections */ 9 [( t5 d9 G5 h- P3 I5 I6 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ j/ U5 i/ r. ?. ^2 e" \7 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ n' L$ R! ^5 F- z% H4 ?2 `8 C& ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 E5 i/ F, J n$ L. _
** Set the serializers, Currently only one serializer is set as9 u' G. U, @, T( D5 {3 {+ U4 D
** transmitter and one serializer as receiver.
8 w: E8 J* D7 X$ h* Q, O*/; b/ k: |/ c, K) `/ x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: u3 z: `! J7 A$ n8 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 j/ d$ ]. t9 s6 F2 @7 _3 N
** Configure the McASP pins ! k8 M7 ~' M% R4 |6 M+ k2 x' y
** Input - Frame Sync, Clock and Serializer Rx5 E2 y. |: r+ B3 Y/ ?
** Output - Serializer Tx is connected to the input of the codec
/ Q( G' R# ~5 A) O*/. b1 ] Z3 h' E" d4 Q4 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ a1 ]- ]% }8 h. e7 c! L7 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. {! _6 C, `, T* t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 U3 Q! P+ t3 P| MCASP_PIN_ACLKX5 s! z/ r# W/ L: K5 V
| MCASP_PIN_AHCLKX
6 f+ p! S" {+ s1 i% K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( Y6 f# H( j2 z9 s3 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ {9 `0 ]2 f& p( M7 J
| MCASP_TX_CLKFAIL
7 Z3 s* A# Y" U* a6 Q9 u| MCASP_TX_SYNCERROR. b Q4 Y3 r& u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + q0 |3 T, i* B( P" _, C4 N3 ]
| MCASP_RX_CLKFAIL
; B, m# K/ Y k" q| MCASP_RX_SYNCERROR 1 v' I- q |+ F
| MCASP_RX_OVERRUN);+ C+ N; ?$ @+ a' t' m
} static void I2SDataTxRxActivate(void)# p# ]' \ \: ]7 ?, ~" u2 b$ B" u
{
7 H* z; H0 _0 w5 @! b& d/* Start the clocks */; \9 S2 r2 Q0 Y0 c. u6 }6 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! F( R# k z" E& l/ x8 i, t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ T8 \$ s- t$ }: `* A( Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* V l; l: P% u3 v, G0 v* xEDMA3_TRIG_MODE_EVENT);/ i; F, o; E1 H6 E4 _3 V9 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' D, Z: ^+ e2 u; ?7 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" V+ v& o8 x8 q- S
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, o! T# G' @0 q3 V, {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( A/ g5 q% S: C! R. U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 l4 C) E3 N) D& n: fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 C1 B) K" \7 f- x. p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ t% k* A- E& z! x0 h: F0 z} 0 [1 n& e* N% y6 x1 n. T' P5 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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