MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
+ ~% A& k! M. b5 c, ~input mcasp_aclkx,
9 s9 S8 x9 J4 E, Q, y- E" qinput axr0,
. N2 Y6 v, X6 t! `: T9 a
output mcasp_afsr,
2 L* R- o6 l- ~output mcasp_ahclkr,
6 a5 L4 q# j/ f  V0 X* r+ ~output mcasp_aclkr,
output axr1,
, u. W1 G  B, R# R1 I$ p, Z

assign mcasp_afsr = mcasp_afsx;
" M1 l9 W6 x% y- _% ]  x0 W* Bassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

3 |. Z4 ]2 \9 c3 w

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

/ I- q$ Q1 v- O) p# P

static void McASPI2SConfigure(void)
/ F" E1 p/ T9 |$ Y{
0 ]% J8 K, Q. m, \. S7 X' P0 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ L. u7 m4 ^/ T9 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
: H3 y$ |9 u3 lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 V0 x8 K/ ^5 _. h! RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
- Z3 m1 D2 w$ [# O7 i" GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
! e& T7 q. `' r* e8 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: h; c$ L4 D8 L$ R; _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ p: ]+ Z" W" _9 t* H/ O  [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
. O/ z# a% U7 I: m5 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 ^' T' H# V: IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
  t* y5 C+ m6 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. ]% G/ k' F, i, G# O7 R8 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 p3 c; M5 g; ~& m7 n' g/ l( s, r0x00, 0xFF);
- n1 I6 W* s$ C; D
/* Enable synchronization of RX and TX sections */
; z) U0 z2 y' [9 |5 k1 P2 \/ }: pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
$ v) I3 s& V+ b* _4 C: P/ {** Set the serializers, Currently only one serializer is set as
. T: _5 r6 s4 X* r3 p# p** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
! u+ y& P: ^0 O. k8 r: N** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
* T9 `0 K( R* v: ~# B% A: y** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# D. q0 v1 q5 y- c' b. TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 t6 \: l6 Z: t! e$ a& a: B- T& mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ X0 r( x) J% A( I: Q7 T2 ^- V| MCASP_PIN_ACLKX
+ k  {( J( C/ i9 m+ M) k| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
  S$ ^& v% y2 @8 U| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) \( Z) Y8 w/ V8 h+ x| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
, _! T9 z7 i: @| MCASP_RX_OVERRUN);
/ x% f* Q7 J- D( w}

static void I2SDataTxRxActivate(void)
{
/ T+ e* Y; |4 V" J7 \. y. S/ d) e/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 Y" i5 l5 R* X( P! XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! B7 L+ U) x( YEDMA3_TRIG_MODE_EVENT);
6 }0 \4 _( P" Q- IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
- r, {6 e4 X( C% M, O- F3 cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; D: d8 R' n; KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
# c# ]# f9 w/ f3 F9 F, b* Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
$ A- L" G0 D$ G8 P" hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! S4 B( ^2 r$ v6 X' U0 H0 X# pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 x- q3 X3 ^0 a4 ]! n" `- {9 p}

/ ]& R. c  G$ {, G

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.