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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% @2 p8 ?, Y _input mcasp_ahclkx,
% s+ t3 f5 u, f8 h! S8 U6 C1 G+ T5 Ninput mcasp_aclkx, f" {" E* C" P/ _
input axr0,
U9 F2 r) q) N; C* P% m3 p, y/ O! \, k, s6 w) D' Q% }
output mcasp_afsr,1 M; X, ~# g/ _- i9 u
output mcasp_ahclkr,- g; d8 a0 I0 ~5 u! H5 Y
output mcasp_aclkr," b& @9 |9 T4 e( @0 z
output axr1,' }; y+ o- z. z- P
assign mcasp_afsr = mcasp_afsx;
0 ?; u. y; c, B5 h" yassign mcasp_aclkr = mcasp_aclkx;5 q# f0 t/ g1 G
assign mcasp_ahclkr = mcasp_ahclkx;
6 b! X8 J2 p- u' ]3 d# }assign axr1 = axr0; 0 `5 A2 G5 J3 R. O( d* i2 X
5 w- U6 u4 \* O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % f1 ~; V H, y M
static void McASPI2SConfigure(void)/ a, i! v- P5 E5 l4 O! a
{
5 e$ z4 C2 T& @# ~; @' Z CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; q/ W3 H7 H/ Z9 }! O/ n2 Z, eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' l" J2 S3 {% Q0 _8 L6 D! o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- ~ N9 z8 |8 y; V( S% ?6 a8 b' IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( U2 w6 T# H" ?- g3 m0 C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- r( k& j& G5 e t1 }MCASP_RX_MODE_DMA);
! s3 {0 e" U8 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ?; B5 g( a. h1 V! R% |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' U6 V5 m4 ^/ m% z7 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 b3 X1 x# R9 |8 z, aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' V) o5 ?: R( f; H4 @! b# a: `, sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. l9 ]$ M- \( z0 u2 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* c( [( _" O4 Y! b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 C j. S/ a& P: R0 [. Y, J/ cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' O6 G- W" F. JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' } F2 Q, I( J. p6 ?. P1 R
0x00, 0xFF); /* configure the clock for transmitter */
6 A) p9 V+ M$ U# g3 b5 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ K3 j. Z; n$ [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 X/ b4 a' J$ M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! b! B& }9 v! {' @
0x00, 0xFF);
$ J/ w8 e" V9 w ~6 D: ^/ {1 h5 j; F
/* Enable synchronization of RX and TX sections */ 5 q: u/ H" J& k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, h3 T V; I/ _+ q, u: p# HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) Z, B4 b0 e$ E8 _- c/ P' c2 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 U& `8 J G7 }** Set the serializers, Currently only one serializer is set as+ u6 \+ J8 ^: M+ V
** transmitter and one serializer as receiver.; E$ z0 c" A, P" B0 }, f
*/' c- ^. i5 W) |$ D# `8 H5 M! G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 n% w# M% ~9 h9 q/ Q# b" M" Q+ ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- }) J$ x6 B& X
** Configure the McASP pins 1 W$ ~+ T* z* m0 _
** Input - Frame Sync, Clock and Serializer Rx% ^2 I! z, l. q+ @' z
** Output - Serializer Tx is connected to the input of the codec
! J& d5 r `6 ?% v2 x, v5 y. [7 |' O*/
9 z5 N9 q$ i7 z$ n4 d$ a4 D, BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 n1 j2 R2 _+ b4 B" i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ e4 N/ ?# j( e6 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# A! h9 P# k% j- Y6 [+ f| MCASP_PIN_ACLKX2 @9 ?$ {% n- F( d9 ^7 _
| MCASP_PIN_AHCLKX
; t8 ~* l0 g% e2 |. i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. ]% V" N5 a, W6 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% t' x% G$ i' o3 C| MCASP_TX_CLKFAIL 5 d" i D, ^! y" o
| MCASP_TX_SYNCERROR
1 Q [; q; N8 d& S6 J6 j' G* R9 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 [2 [) s5 |+ o* ]* t
| MCASP_RX_CLKFAIL# Q+ z: Y: j* r2 f* W- {
| MCASP_RX_SYNCERROR
* ^: {6 _/ @* A; M| MCASP_RX_OVERRUN);6 O9 l& g* S \& u% h
} static void I2SDataTxRxActivate(void)
8 Z3 t" {* v' Y" q {{
, a& p% Y: `+ w/ D4 l/* Start the clocks */
$ U1 c" _) b8 |- sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 u( b5 K4 _2 L1 o1 x4 A0 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# L1 Z% h, G F* W, t `& \! Y: O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 `* Z, B, Y, ~
EDMA3_TRIG_MODE_EVENT);( V* s# g/ i! `$ s" q1 C$ m+ k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; k" V+ G! |4 Y; y1 X* n6 D- Z) e/ c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// R( ?5 {7 Y; w5 t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 i& r/ W+ R- [% j8 c0 t- `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 {) p3 a) J ^ [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 H- C% r- }4 ^* e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 y' K; P: }3 S/ t+ S4 g! ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 n K9 S3 t( I}
6 A: \4 u* `; [$ k' ?2 E8 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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