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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: U9 s: P `/ G5 G
input mcasp_ahclkx,
7 k, }) ~$ o, y2 G7 F: b, zinput mcasp_aclkx,4 N$ u$ v% g& j/ S" F
input axr0, U4 B+ H# I7 u* Z( ?( `% X
) z3 t# M! W- T& k, Y4 N# M; a E" |
output mcasp_afsr,
: x% t+ ?6 J- v ~# C3 D; O, youtput mcasp_ahclkr,
y& m" R9 C/ f/ b( C: `, w5 voutput mcasp_aclkr,
/ o- {& H9 c6 r" aoutput axr1,5 ?. j4 w5 V) F2 {3 N% @ G
assign mcasp_afsr = mcasp_afsx;
# M/ S. Q$ l9 p8 }1 U9 m' Uassign mcasp_aclkr = mcasp_aclkx;
/ H4 M5 }. q1 \2 ]5 X* u: f2 F( L( bassign mcasp_ahclkr = mcasp_ahclkx;
- J1 C8 W- y9 ~ p8 Gassign axr1 = axr0;
$ Q6 @1 y7 f8 b6 C
/ z% f) x) u( t+ ^( U, s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , ?8 O: U" Z: x1 M, c0 k0 x
static void McASPI2SConfigure(void) U3 W4 w1 ^: T `3 W( }
{
, c1 l5 U7 g' z$ e6 b( L1 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) |3 v% @8 f+ x% \8 ^4 A V5 Q a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 d4 {+ p x, ?% j& y8 `+ w& _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 s2 v' N- s- d0 {$ ~! T7 w: R$ i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ n }. _7 E( p% ^! j: j8 N2 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," `" Z0 Z! h3 G' `0 j
MCASP_RX_MODE_DMA);
/ P) m# O" T) r( C( J/ vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: A2 W7 x& }* V( m- n$ |+ NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! V9 ^& K6 L8 f1 V9 |2 x# C- @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " j' a+ x. Z1 f5 t( w6 i- f% T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- D* b! r5 J$ b' V0 B# ?$ h3 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. h. |/ c$ }( a& S- G: ~4 eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 }) E1 o5 i7 F6 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# f9 u, g6 k& rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 F% a+ w# F( D* lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# k3 G5 E7 u0 C3 ^" c
0x00, 0xFF); /* configure the clock for transmitter */( G2 a2 H5 Z, F1 {. T& y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 z' p9 ]$ O2 Z6 _: b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * J8 ~, z- w8 `" `( K/ {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; [5 g5 P4 S% E0x00, 0xFF);& F& ]4 F" ^5 T. @* P' v
, R/ ]9 v' o' q2 F/* Enable synchronization of RX and TX sections */
0 f) {/ J' o0 S* Z' P! t6 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ @0 M2 m; e: j; j- ~/ |' P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 k4 F3 J; b* a( _/ A; bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) X; t3 a4 e3 {; R/ c** Set the serializers, Currently only one serializer is set as
( ] b. A2 W2 {: C" y; |** transmitter and one serializer as receiver.
/ c3 Z+ |# s0 T' U* g' F8 S. @8 q$ |9 l*/* x0 |" O. S. q7 l; m1 x8 e* O5 T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 R2 k+ Z$ o% A. E+ j* OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ u, o5 O: u6 z1 H' z3 o3 ~: L, A4 q- b
** Configure the McASP pins
' p/ ]5 E; c; I& J: Q3 G& \1 J$ M6 i** Input - Frame Sync, Clock and Serializer Rx0 Q( C9 n& x2 z3 @0 {
** Output - Serializer Tx is connected to the input of the codec 8 p( g4 D4 V% b2 s* _! J3 T
*/
+ K x3 ?& F7 Q1 V* t/ q& lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 \, R/ Z% d# Z7 T. b5 l! YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ o W: u! ^2 w7 e( v! }' r1 A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) J+ ?% B) \/ m& D8 p* |4 \| MCASP_PIN_ACLKX! k9 x F6 `! D1 F+ H/ i z4 n
| MCASP_PIN_AHCLKX
0 F ^3 s6 ?0 p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 ^# A! B* ?% S9 j) E* }; `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 ^. b9 W( y/ n- B* K| MCASP_TX_CLKFAIL / Q% e1 X& J {1 Q) \
| MCASP_TX_SYNCERROR
8 h5 _$ Y8 m* y! r7 A0 t/ z, n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & ^ W" k6 N# m4 P6 w3 C
| MCASP_RX_CLKFAIL6 m7 q! l( H# r
| MCASP_RX_SYNCERROR ; W; b2 C! ~8 X/ x7 s
| MCASP_RX_OVERRUN);
5 u$ @8 j: `1 H x7 g} static void I2SDataTxRxActivate(void)
$ }) X4 ~' ]! L{* ?7 t! G0 G9 O
/* Start the clocks */
( }1 _4 C% G7 D9 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# b5 W& u m& ~: g' v1 O7 \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% @- L5 l, i' y' z1 e9 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ D1 _# u1 E& v, G) {$ O- `: O
EDMA3_TRIG_MODE_EVENT);
1 x. c% j# ~4 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( J _5 K: h6 g. D: N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 a1 U/ Q0 L7 N& O6 o; ~, U+ k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; a0 f0 m" k3 B+ p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 R' f; o9 O! K* ^7 i" U& x/ H% dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 N& D, D0 y; `1 x! V7 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- m! C( U- L' ~, P5 D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 |9 m# [& Z8 H& {0 n
}
; @4 u1 H6 ]2 Z. h1 p" D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 s5 j" L0 I- o6 k2 @# _ R2 \
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