MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
5 U/ @8 w" I" R$ |* h% ainput axr0,
. Q& [4 x) S6 ]9 a6 o) J
0 K8 |2 a# E& ^0 O: Toutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
& L7 q+ u' M7 |3 \. g2 z/ coutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
( L5 t6 |1 ?: }$ Jassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

! T8 e/ d2 ^0 x3 M+ C9 {& s

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
# k) b" f) A0 m{
7 F" t& d% W( `* v0 F- w7 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 }& N' p4 f9 \% \8 i3 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
1 W; t) p* y- K0 v& {3 Y, CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# U9 ?( o1 a2 y. }! M& TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
$ o- O- |  c* E: D: T' V  z3 tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 E( U! p9 G( q  a# L3 c$ gMCASP_RX_MODE_DMA);
6 ~: g7 w2 |& H+ _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) b9 B+ u- n' k1 f" \+ A: eMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 _5 n4 t1 W/ i, t& @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
' m' c. |- e0 M6 W: u' `  AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 z4 ^, g  P9 }' A3 q- I$ V, m9 m. aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: b* A- {8 Z8 y/ w5 k' Y0x00, 0xFF);

/* configure the clock for transmitter */
3 s: `8 U9 }) U7 Q& [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
( ?. o1 Q$ M9 V: W7 ?, MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 d, ?' D6 W2 y9 i  @. Z6 {/ QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
- s$ w! Y8 Q6 p+ F! @6 M*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
) @( L% ]0 }5 G2 Y( J; \3 S% M+ X** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
- |1 I6 O# A" C** Output - Serializer Tx is connected to the input of the codec
*/
4 Z$ ?" |! U) r4 m- b6 [. Y; qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
  @$ e8 |, I8 h; a& R8 v| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 @1 G; W$ w8 L6 l+ v$ }4 h| MCASP_TX_CLKFAIL
4 ^6 N5 W3 I, h" z| MCASP_TX_SYNCERROR
* r2 r$ E/ v  Y, F8 d, Z4 |( U8 f| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
0 z4 i  G# u# v9 f| MCASP_RX_SYNCERROR
& L" m2 p6 t8 @8 r0 x% {| MCASP_RX_OVERRUN);
# b2 Y- f) ~6 C* w* \( y( w( k}

static void I2SDataTxRxActivate(void)
2 @4 U  t4 y: n, P2 E( a{
* W$ S4 l8 c8 A& g- f8 j6 S/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 \" y# M- }4 \: l7 X  VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' @* O7 g/ S* D' Q( L: y) IEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
9 d6 ], K7 F% f8 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
8 e4 `  s2 T2 E+ b) G! }% KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
  D; i, }. k6 ~* `, e! q; O  ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

0 l9 o8 h' `5 c& a% }

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.