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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 T) e4 b: W( t: p& ]+ a; h& m
input mcasp_ahclkx,
7 Q4 x0 F# z8 ^+ e$ O, dinput mcasp_aclkx,
; a: @3 B2 `! I. A- e$ D, }; dinput axr0,
4 H8 i, j0 \3 x" u8 I, v: ~
7 n( P% T, s2 w' a" b/ ?8 H. doutput mcasp_afsr,
" m1 u( u. n; A- @/ loutput mcasp_ahclkr,
/ {0 |/ I: `) z- Poutput mcasp_aclkr,, F! d. M0 E$ t( H' @
output axr1,
" A6 \3 {" S1 ~) J1 \ assign mcasp_afsr = mcasp_afsx;
6 O3 }& m' k8 bassign mcasp_aclkr = mcasp_aclkx;
' j' q( f' @5 z1 F) F- b$ xassign mcasp_ahclkr = mcasp_ahclkx;) k5 C2 X6 n9 w T; E! e1 ~5 S
assign axr1 = axr0;
1 \6 ?9 l( s" }! g' M6 }
- ?% e" ?; C! _6 I7 F* K9 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- t" J$ N/ U# }. Z5 v. ?$ ^; Astatic void McASPI2SConfigure(void)
3 p; M4 G$ C2 m{
/ W0 K1 x7 V1 F$ c! sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* A9 d8 o- s1 Q |8 c4 K9 YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 b m3 ^/ o2 |) n7 {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; i6 R# s3 o/ @5 G b0 t+ CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 N" f: O! [, Q. G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 G) w2 J" k) B4 CMCASP_RX_MODE_DMA);! E0 g- e% Z8 s5 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
?6 z; Q6 g" J4 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ c% o3 k1 W; h- S: R; n4 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( ~7 q% G& g; F" V7 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ U, j& u! k6 j* d& J ]: s; fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% Z: ?5 G& g. }4 O; mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, D" Y4 B' I DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 K* Y; D' O! i/ ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 j+ m+ B4 h+ r# R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 }$ T0 v! k" e9 q. i3 M
0x00, 0xFF); /* configure the clock for transmitter */: S# W1 L6 t& \# K6 w% r8 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 @- D" I7 j! N6 p7 _8 LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) n1 D+ I0 L3 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, L2 S& T" {9 s |4 @
0x00, 0xFF);. g3 i; ^. r# X& e
# y6 v2 O( n; l/* Enable synchronization of RX and TX sections */
; Z% G* v' G: h0 @- s9 Q) sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- f% X) [6 @0 w% A3 k7 L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 r% c$ E. K* n. p. B" }# A! F) c- x4 E: gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% q6 H+ [6 q7 X' U3 ?, c3 [1 |
** Set the serializers, Currently only one serializer is set as/ v: f; o% `, i# N2 g4 j2 U$ _
** transmitter and one serializer as receiver.1 Y( Z5 W# k3 T3 D
*/
" S2 Z) `( Q, L/ c9 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 b) d8 D) e) g/ }4 T# \* pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ Z0 x$ n$ N% p$ b7 s4 _
** Configure the McASP pins
" e' T6 F8 f$ d( y** Input - Frame Sync, Clock and Serializer Rx$ {9 w) f8 u) X" H
** Output - Serializer Tx is connected to the input of the codec 1 k) G9 q9 F9 [2 Y0 P
*/( g# x, o2 L4 N" S7 e/ Y3 k' v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) @! O( \' c% c6 `7 y. O% d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( _( S* v Y" T+ c& s" G7 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; \1 N- a! {9 F
| MCASP_PIN_ACLKX
8 ] v" C2 U8 w( T2 P; w8 m| MCASP_PIN_AHCLKX/ F" T9 K0 H( B3 {7 Q" r5 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// A% B9 \" G- p( H4 ]+ Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 \9 l7 {7 p5 {) A9 P8 i: I| MCASP_TX_CLKFAIL 9 @& n8 y" b/ c4 C( ^
| MCASP_TX_SYNCERROR
/ |! F& V% \9 G3 @2 W" E: X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( L& e- }3 a* z& l5 `2 t| MCASP_RX_CLKFAIL
; |# A# n" F h1 C9 B| MCASP_RX_SYNCERROR
: I, r; e& g1 {- \| MCASP_RX_OVERRUN);
9 _! I3 i4 w& I: E* A5 Z/ p8 s} static void I2SDataTxRxActivate(void)
- D5 {# z6 a' g3 k, G! Z) G{
' G+ _. L( P$ {5 d2 _! E( H/* Start the clocks */
( ]* z) I) C4 u! e& n3 K/ zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ Y* L. ~! l( {5 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ V; s6 U* v. M# d, x# Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ j8 z* Q6 f6 [5 Z0 u$ MEDMA3_TRIG_MODE_EVENT);
0 B6 n* W0 K6 [6 D6 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / a% p& q+ a% F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( g) U& A- h3 X3 Y% V! H' G6 y% S2 g# TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 c0 |' l- E, TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 H, R3 E6 m1 X% v/ A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 E2 i. K5 r+ {1 I/ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ G# k F0 k6 `* b a AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 O9 w2 f6 z }& V8 P5 H" e}
$ |; ~: v/ N) l5 w. k3 R! c1 ~3 ?1 j& n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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