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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' h8 J" p, l* Z) `input mcasp_ahclkx,& A# h& ?5 |) a
input mcasp_aclkx,0 S5 Y2 b; w" ~6 ]8 h# X4 g `
input axr0,* ^. ~+ V) Y6 Y9 ^( W
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output mcasp_afsr,5 I7 X2 z% H$ O; ~. e
output mcasp_ahclkr,1 Z8 h6 _* d6 ?- [+ f
output mcasp_aclkr,
* _- C; C, R( h) A7 noutput axr1,0 _7 w3 N% B# a6 m/ C, p
assign mcasp_afsr = mcasp_afsx;4 P# Y! J, P* T$ {8 b) u% t7 a
assign mcasp_aclkr = mcasp_aclkx;; L9 e8 g0 S, Q# z
assign mcasp_ahclkr = mcasp_ahclkx;) @0 ?0 X' V6 o3 b
assign axr1 = axr0; ) A9 \2 b8 ?4 a0 e5 Y( f* N; L6 A
0 R0 [( f. z4 v/ C9 ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 \" I* K+ y5 P6 h
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# u- T' f6 S; `% SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% @( n- q# k. W' j5 ~& n7 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& h6 F& e$ @; e/ F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ g" z4 x+ X+ c/ R: }5 U9 zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: H% ^/ o2 r+ U" Z$ QMCASP_RX_MODE_DMA);( s0 P8 b3 R, P" I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 e8 P1 U% H6 a7 K' h0 E$ nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 j g3 P6 M$ G1 T4 J4 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . S) D) J! X4 w7 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% Z' Y5 i1 k6 ?5 w* M) d6 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 ]' Q; z& K- Y0 f/ p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 {! {+ F9 i) w4 d' XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) }1 T4 E0 A1 m% b: e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* u, I9 @9 N4 A0 i. c) _# r2 xMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 u9 K+ a; _/ u/ K0x00, 0xFF); /* configure the clock for transmitter */
- d# z3 ?8 q, b2 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# G8 H7 m/ |2 A3 ^6 I) M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : H/ q p$ d3 b* \& k& t; l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ V% H9 G* o0 I0 q" o8 `0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
$ y1 ?& F* H6 |8 @8 y" Y6 Z- ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% X0 H# U. ^+ K7 t7 I1 oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Y! I& G8 k0 \6 p: B" `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; |3 P% G- O8 A# o) A' m4 |) K/ g
** Set the serializers, Currently only one serializer is set as2 n+ V2 Y; _, I6 K4 `
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: T5 K" e3 w, N+ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 k4 h6 B2 ?* f. Y' ]$ r** Configure the McASP pins $ F/ P+ `% q0 ~. z/ ]
** Input - Frame Sync, Clock and Serializer Rx3 W& M, a) g0 I: T# r( q$ X
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) f+ P) ?7 S- G) I5 s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ K( a' [8 u+ c, z. ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: X3 j( w7 l* u& g2 i) J* ~| MCASP_PIN_ACLKX
" M( g" K c- q) l% W) \| MCASP_PIN_AHCLKX( t! G6 b3 j* ?2 X& a& B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 E& P$ S! `# A3 L2 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( ^1 K2 K4 ^; }" u4 n6 o
| MCASP_TX_CLKFAIL
' R) g" s9 C6 W| MCASP_TX_SYNCERROR
$ Z( \0 ]- l, t/ Y$ k, {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- A% y* [8 Z0 E; w8 W| MCASP_RX_CLKFAIL% ?# ^/ _* Y; d! G/ B
| MCASP_RX_SYNCERROR
! ?8 \( J3 r5 G6 r| MCASP_RX_OVERRUN);
; Q8 X ~& G. j7 a* O* O8 I0 b7 }} static void I2SDataTxRxActivate(void)
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% \7 k4 `/ o$ V% ~# i/ Y. _/* Start the clocks */. }4 k) R9 R. `2 |- G0 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 z8 q8 a8 S# l+ X2 O! H R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ M5 y b& t# v: mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- ]" H+ ]2 l# S4 e; u N( r, u. A
EDMA3_TRIG_MODE_EVENT);
. J% V" z" r! l: l! k IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
j) S! Z) N. I( _$ H& T9 w. CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 Y& _4 e Y; G( G' LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 F* A9 s4 O F6 Z3 [2 x7 K7 x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 @( u: p, r9 {/ S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 O j1 u, N9 O$ M, E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ s' ]: [8 o% z9 ?- G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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