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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 C% A7 U9 l& n6 _
input mcasp_ahclkx,
& U6 P2 L& u& s h: p; ninput mcasp_aclkx,
: \5 h+ D0 a2 V4 m( v1 Hinput axr0,
# D* K. }+ N+ w# z3 P+ I! Q% S9 W" Z9 ]! |2 W/ Q8 c4 {
output mcasp_afsr,& {+ @8 D% H7 s
output mcasp_ahclkr,$ B2 I4 Z$ u$ R+ {+ @( B% Z( T
output mcasp_aclkr,
7 t" ]- A) f8 w+ Zoutput axr1,
" W& K4 H$ `8 G4 O% U assign mcasp_afsr = mcasp_afsx;0 j% u R( P. f/ ?# H
assign mcasp_aclkr = mcasp_aclkx;
( g( y1 D9 T( u3 Gassign mcasp_ahclkr = mcasp_ahclkx;
( M# l8 U+ [7 j: _& _2 j+ V. ~) iassign axr1 = axr0; ! `( V: P. R6 @, h0 z- }9 e
- x3 ~; J9 H) H7 d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" ?: c0 h6 h3 f0 K! L' I3 @static void McASPI2SConfigure(void)
6 X9 X% }& f! n{$ N; |! {; W& c8 l: j( \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 H$ l4 P5 p! W W; i' V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// X) q, q! N* j- F! j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); A% d+ f) |2 [1 }$ \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) F/ H w; r6 J4 w' HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! v* a& Q7 W- U/ m, z) r) YMCASP_RX_MODE_DMA);
. m b) s1 t) {+ A+ OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, l# o1 b) c, Q; a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( V' h/ j4 r: j. @2 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 k& n1 Y6 R9 g2 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) `+ c& ^3 n' L; \0 a% J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ J/ R j) Q W) R0 }. _* NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! H8 a/ `7 l8 `% V6 B. @( {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
_; \" u& Y' D* n3 A- `- j' nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 o* ?4 p. V- x- o3 v6 w3 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 k3 p6 P3 _2 M) Q( ^9 p: a
0x00, 0xFF); /* configure the clock for transmitter */
0 b( B7 K+ B& u& UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) p# Q L- F) B0 D' rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " o8 `' Q6 ?; c8 D+ {/ J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& @! T" ]( {( e# g! x% y( C
0x00, 0xFF);
6 y: U; V) L/ w* Q6 x2 _
/ A y2 r6 P% o/* Enable synchronization of RX and TX sections */ + o2 r1 o" h4 A/ g% P' I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 O* s9 w- \8 m$ tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 \/ `* ]: U9 Z4 {5 B, R6 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** X) {) ?/ l' o9 i( d
** Set the serializers, Currently only one serializer is set as4 p, U5 }' L5 l" z" y
** transmitter and one serializer as receiver.
+ f2 L& [ c$ N1 Y( D*/8 z+ ^5 d) i; Z4 x3 t$ p& J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! a! a: e4 `1 T# f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* I1 f& ]5 T% `3 }** Configure the McASP pins
) G' D" I: L4 H1 f) `** Input - Frame Sync, Clock and Serializer Rx: t! Z3 a5 t3 f5 P/ d2 i$ l
** Output - Serializer Tx is connected to the input of the codec
z% U+ W' Y9 E O*/
+ w0 r0 c$ t5 S- |) A8 AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& Z6 d* H0 f' uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- R1 B: c/ }. w4 i$ P! rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 F' v4 O' C- W, ^& x
| MCASP_PIN_ACLKX
! s. L5 g0 ^# U3 s3 W7 z: @| MCASP_PIN_AHCLKX2 L3 e# K. b& t2 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# e% M, e n8 w8 x, [3 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 k' L% y7 @4 I2 m6 ^% I| MCASP_TX_CLKFAIL
0 e- q; |8 W6 W* W7 v5 [! F| MCASP_TX_SYNCERROR
/ k/ r% {* i' v# H! j6 O) ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : K0 T, c m7 h5 I1 g% | D+ z
| MCASP_RX_CLKFAIL
" b0 ~% c5 x ?! }: ^3 ?6 w/ y0 Z| MCASP_RX_SYNCERROR ; t6 t: p) E: I6 i
| MCASP_RX_OVERRUN);4 L, z: @) h) e% I" C
} static void I2SDataTxRxActivate(void)3 t5 @9 b9 K! k5 y* k7 h' k) ~
{
$ L8 N3 X+ ?3 N/ j% j! u/* Start the clocks */6 p7 O( _4 l3 D; |6 f* v/ W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' D2 g y' P. M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; @- W: p `" c# F6 w6 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; o G0 C- p3 C# z. h
EDMA3_TRIG_MODE_EVENT);8 c. X/ t& _, l# I: I' c9 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# }0 \% j( I! c% t( H" mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# q w, L# [% j9 g. K: \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. W. g. a1 x N, s+ YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 g9 O) Z5 z0 W( G9 q& R1 Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# Q' X" t3 @$ r4 x' R) P6 [7 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. Z4 C( G3 R% @0 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' X. m. y" O2 A6 S$ Y
} ; X4 S: a- C% w+ G! C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 j k" Z4 J( Q
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