|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& D/ n8 J0 _8 E8 Ninput mcasp_ahclkx," \4 A5 y( H2 f( }
input mcasp_aclkx,' o7 ]+ u% Y6 o6 I5 v
input axr0,% {- Z! } m/ V* Z' y. V4 Z
& S4 k# z. |' K0 O, G6 ~output mcasp_afsr,
% H' C {1 Q" Koutput mcasp_ahclkr,, h' i0 e" c6 ]/ R" u; `
output mcasp_aclkr,
# C0 V+ I9 A- V- x" loutput axr1,6 _2 v- ^& h6 b/ r* o. U% y( S
assign mcasp_afsr = mcasp_afsx;
) ]6 }9 E9 H. c: P9 S- F0 Wassign mcasp_aclkr = mcasp_aclkx;; N, \7 j$ \7 n1 K1 B+ ]5 g) u
assign mcasp_ahclkr = mcasp_ahclkx;
a! \7 j2 R W1 Zassign axr1 = axr0;
, e8 u) G- V* N$ l% O% J( @
; S7 a7 W6 t$ J1 v/ e' A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * T R, `( b% s: i
static void McASPI2SConfigure(void)
' ?5 C: r5 J1 @' O7 d- T8 V{
. f4 P' y5 y/ G( [" [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, j ?' Q7 r) I0 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 U* h0 {+ A% T0 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) g$ _- M4 |% j) r% P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 f- y9 m4 Q, k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ h* Z/ p* z# S) }7 S' a
MCASP_RX_MODE_DMA);
; m. H" ?5 f7 q8 g1 {5 P! A" Z0 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 p5 F/ }: W: Z: X: DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ G( P! O& M6 O& t8 WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ s1 t, ?& G8 U: h8 E$ i! y+ hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 ] U" }3 C# U; w# v' J: g. Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( z( s$ O+ }- ]0 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) a' f; |$ b7 z. z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; k. G, U# a( j) {: M7 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); d: c0 ^* d+ \1 ~* V6 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ {5 W5 n4 N q0x00, 0xFF); /* configure the clock for transmitter */
' I0 ^% a4 P! u ]; ?# {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); c8 A# K3 L9 y( w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ W# u4 y4 a/ @% Y5 C- \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% G% z4 W# F- _9 B0x00, 0xFF);
# W- p$ H1 b6 Y" d1 o' m, p. J) X5 E
/* Enable synchronization of RX and TX sections */
7 ?; @- |7 e' u7 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& n7 ?- t: I! UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); H K5 N0 z, v$ h/ t6 o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# S8 x6 B. m' B# [2 ]" K
** Set the serializers, Currently only one serializer is set as
& V. t! a* C) }3 H6 Y1 A! z& U** transmitter and one serializer as receiver.
& M3 ]/ B+ ^0 X* C, U, o- M; O*/0 N- Y( i& c: s& N7 O5 R. o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); q( R5 r) V3 b9 D6 L2 V% T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 J" H r3 U$ h' B** Configure the McASP pins ; j- \0 j4 \5 `- W
** Input - Frame Sync, Clock and Serializer Rx7 e+ F7 a( z/ O& T2 \
** Output - Serializer Tx is connected to the input of the codec
4 R7 p9 }; O3 {. `0 \ w7 @*/
z1 r$ E& I( f5 _$ P" L# tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) @( ]8 N/ ^+ q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 c9 m) W) ^9 e" [* pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. q c: @. x; Z4 K| MCASP_PIN_ACLKX
* L3 y/ F+ P3 V% M- Z| MCASP_PIN_AHCLKX
, g& g0 [% p8 p7 v& w; p6 `) D4 || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ j" I/ D. h4 k: {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 a5 `3 s; a7 G7 j# L| MCASP_TX_CLKFAIL
0 I3 L" k& {: v/ _2 a7 N| MCASP_TX_SYNCERROR) C1 h# _) D+ R2 {1 c# ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 b/ R/ o' w2 i" @' i* ]| MCASP_RX_CLKFAIL
1 y, x4 F$ m2 `3 O| MCASP_RX_SYNCERROR 7 k6 p2 s( O" G. K, p0 T) p7 h
| MCASP_RX_OVERRUN);
& s% K0 e5 r/ l$ P+ V0 U6 C, A+ q% s} static void I2SDataTxRxActivate(void)
; I" J1 h3 ?& r7 b/ }{
3 p0 z; ]; E, X! ~- ]" ^, v2 Z/* Start the clocks */; J5 r% |( U+ \5 m) ?% y n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 J+ G2 s! a6 y& j) m/ `0 m( [/ BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; j& w" X8 ^; u9 y- E+ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# t) D) O4 S1 Y4 X
EDMA3_TRIG_MODE_EVENT);
- v7 X+ `0 R/ P. A' AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 p( n3 u" `1 F4 j U" ?4 nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; k9 K, h! v$ a E6 `9 G" V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 x0 S }: |$ p A- o! l2 ^; _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' N$ x4 `# L( S3 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 d; s A( Q/ B) F$ dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 X- ^! s& [* B9 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ v" v3 l9 z+ T" K}
5 B/ D( V3 l) n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * |, P2 w4 S$ l# e
|