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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ V# X; \8 U/ y
input mcasp_ahclkx,
+ G! {' i A& t2 R C \$ @# }input mcasp_aclkx,
( C2 F/ a: V2 u: E2 y3 Qinput axr0,
8 X* n7 w' W }5 @0 Y5 \5 l0 J% {8 s. |: x* x9 G, z
output mcasp_afsr,. h7 r( V0 U' P( a
output mcasp_ahclkr,' F/ P0 J3 z+ J# R& ~, B+ T
output mcasp_aclkr,
. V" Q3 Q( H6 n3 B8 [! zoutput axr1,8 J1 b% ~9 J+ j# y J+ N
assign mcasp_afsr = mcasp_afsx;
0 `3 g6 f3 y# }9 a- m# nassign mcasp_aclkr = mcasp_aclkx;
5 V3 X' V% C; {! b1 m, H8 iassign mcasp_ahclkr = mcasp_ahclkx;
9 e7 Y% \0 @3 D& f$ T+ eassign axr1 = axr0; * p& ~9 x3 Q& M
; V, Z0 I. B, n h5 c; |# z/ D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " p* ]9 ]* H; I" r5 J$ r, U9 K
static void McASPI2SConfigure(void)
9 \) o: \2 n! n% E$ @0 {0 K$ L{
. f0 v& ^6 G/ O: K; cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. U1 y+ Q4 z1 `" O$ \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# f+ }' [9 E" u; E& O9 z8 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ Y1 N4 Z( V- \, A! g( B% vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 K% f5 T+ A# j8 U' hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ I5 q/ @+ l2 W# F( N
MCASP_RX_MODE_DMA);$ E# h: @0 J+ s _! z4 j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) G8 {( Q( P- o7 p3 |6 f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( A% {" E* e& K2 t5 A; o! A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 V2 n, I X; d+ Q3 @3 i6 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 k* B4 [: b) Q! A: x, d5 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; J7 H5 N& s5 ^. i+ ?3 [5 ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// F0 G& O4 X8 P" z3 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 Q: r6 e6 g5 n5 d. A( R. [8 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); s4 a& c/ a9 b0 d. D6 [& Q- m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, W; R3 E& E. U3 M: _( _1 A+ B0x00, 0xFF); /* configure the clock for transmitter */
; d7 I( [: ^& ]' L9 l* W) DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 r( N# V/ X# f9 J* D; L& p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 Z6 `5 z5 O+ t( _: aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 C8 C* c" x# M9 m5 D
0x00, 0xFF);
+ I2 ~, k7 i* r8 r2 f _' t4 K4 w) Q: @* w j9 l
/* Enable synchronization of RX and TX sections */ ( d$ _$ y; _: G. E$ I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 r* T% u* y, [. z9 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ P9 H$ D+ c A0 w+ v9 b7 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 N; A' C9 [$ `( s4 B** Set the serializers, Currently only one serializer is set as
- Z# ~; G) T, D6 G1 E$ N: J# l8 C** transmitter and one serializer as receiver.9 u- |) Z# @6 w& Q4 t
*/& W+ s, \! L, e6 w) p% {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; h$ B, i7 f. q- rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 q: a8 f1 m$ F1 V/ f** Configure the McASP pins / |/ J# M& O; z- f: c
** Input - Frame Sync, Clock and Serializer Rx
* l% `( w$ Z* c. b, o) n** Output - Serializer Tx is connected to the input of the codec ! h, Y* }/ E0 c ~+ w7 k
*/7 R- w2 M- q; A9 p# t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& u; t4 X' I# T, {2 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. {! L" i ?( Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' K' K1 G, l) q* Q| MCASP_PIN_ACLKX/ b, n p0 w9 l) _+ V7 T
| MCASP_PIN_AHCLKX
2 h5 }. S1 I: |& a% R$ F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; u* s( Z3 Q: X5 y3 a/ zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 w5 r9 g+ p# [( e/ J
| MCASP_TX_CLKFAIL
- Z8 a5 j- L" u1 p1 @| MCASP_TX_SYNCERROR
) z6 B: C& G( u2 b7 \- W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; X3 u; w2 R3 p1 o) F| MCASP_RX_CLKFAIL
; {: {2 s' H4 D0 \% e/ J| MCASP_RX_SYNCERROR
$ D9 m( |& c, ]' F| MCASP_RX_OVERRUN);* a1 H6 ~2 I/ i+ E U
} static void I2SDataTxRxActivate(void)2 J+ H( v; f& N# g
{
+ ^3 }4 |. M, _6 Y, G8 P ~/* Start the clocks */
9 n/ x( M9 X0 J7 G/ g) p; W- @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ j% i( T$ t2 F' l& ]" AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! ?1 G% N# |4 d; u# E# g! b: WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) f& n } |! T' Q
EDMA3_TRIG_MODE_EVENT);
0 r: {& Z( ~. M, R `( wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ M- ]; }. e; \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 D4 a0 h# s; ^8 |0 c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ }7 q/ F2 { H3 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* |$ [% h8 j, c' ^) j8 M5 D0 }" g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. G4 }7 }9 H7 b( J0 AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); Z2 h) A. G7 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! P; [6 k1 j: k; I) B9 J+ O3 r% u
} 1 D/ Q* k2 l) G x) o5 h0 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * E/ \# P- R- _( J6 Z% e
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