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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& T9 e1 S7 H& A; g+ H) ^& j9 e' ^input mcasp_ahclkx,
4 Z, a" A3 W$ Ainput mcasp_aclkx,* E, Y1 m' F( c" _1 ?; ?/ d
input axr0,3 x$ D6 J1 A, [4 S7 n
7 E! V J9 |2 K/ y0 k$ [( j0 g: toutput mcasp_afsr,
4 f! e W6 \/ C) u( D" x2 ooutput mcasp_ahclkr,7 j5 \! O! ]! S0 C9 Y7 M& ~
output mcasp_aclkr,; I2 |" x1 D7 r: Z, c# G
output axr1,; @( @ |: R% Y" f; S
assign mcasp_afsr = mcasp_afsx;- J: ^+ D- A7 z
assign mcasp_aclkr = mcasp_aclkx;
) V: Y9 C" n4 k: @0 V# }" Z. _) l2 tassign mcasp_ahclkr = mcasp_ahclkx;
, `9 J0 `5 h; P& X0 X1 P% ?# [assign axr1 = axr0;
! ?0 E. k: _, `) P% ~* n! _
: l5 c" G( g/ o" z$ ?/ i# W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 J0 s- A, M9 [, h' @, q' [$ t$ @static void McASPI2SConfigure(void)
6 L+ m3 C. ?8 Z3 @{
/ h4 F2 y8 F6 w1 w; M% L- IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 Q" I4 x. k+ K2 z: p& O8 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, ]7 @2 ~' w e( ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: N; U/ R9 B& j, R$ vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. c- V3 ?) r9 K1 e7 ]$ zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 n5 o2 i% w, E" S2 VMCASP_RX_MODE_DMA);
6 k( w9 N6 C, ~! C- SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 b# ?# g* F# J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 p& x. L' h8 i5 X8 q% G# Z c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 N' S# o6 w8 I- F, u# s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) ]9 F6 o% R* y2 X8 b% b( b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 y7 n. `4 e( K5 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, X0 h, P; a+ W! Y8 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- ^9 J' M9 M$ r9 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# F( O9 o% v0 S$ m2 v0 M" k) Y6 s& y8 n; j1 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 G; g: q t0 E
0x00, 0xFF); /* configure the clock for transmitter */
$ C7 \! W0 H" n v" T, q7 pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* \7 p3 Y7 Q2 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - N% b5 j/ h! ~$ `, b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& q, ]' k1 j3 y, z# U0 F/ N
0x00, 0xFF);
4 p, R o. s* {+ T* e3 }
6 c8 T1 j0 k2 r/* Enable synchronization of RX and TX sections */ , h+ A' |% }% Z# t4 u& j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# z1 X5 U8 b6 M0 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* q2 r$ ]1 c0 g6 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 T& v: X( W% |, P% L4 O' o1 ~
** Set the serializers, Currently only one serializer is set as$ t9 L' ?0 d& @ P
** transmitter and one serializer as receiver.
* H6 w9 M+ R' a3 e*/. p1 n& O$ @% H+ W' {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# b- x" {; Y0 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 Q* u! e1 K% [# c; K9 N
** Configure the McASP pins
! r4 O6 O: n0 a8 `+ ~** Input - Frame Sync, Clock and Serializer Rx( j" r/ I" k$ N# X! l* R
** Output - Serializer Tx is connected to the input of the codec
7 `1 q1 ~2 u& L3 }*/
. T% ^: n+ x; l8 C) q% oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 D) K; N* c' S9 v0 C& _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 j/ E1 C8 z" [9 u) w( E7 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 J* I+ L, q+ h2 P, ?| MCASP_PIN_ACLKX
! r2 Y( d0 @! {| MCASP_PIN_AHCLKX
' ]/ b! l6 z5 s3 Y R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 O: S! N* b8 q' `. V% X% W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 }2 A' d% h# O6 D) `- ]| MCASP_TX_CLKFAIL 4 G$ {- s0 g- o; }; ^8 X
| MCASP_TX_SYNCERROR5 w; H" P$ L/ N7 r- H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' f' V$ R2 }8 U& t! K
| MCASP_RX_CLKFAIL
1 o$ X9 }2 Z/ C0 f. `| MCASP_RX_SYNCERROR & E$ u8 {+ ]( S
| MCASP_RX_OVERRUN);( \( t( w% ~% D1 K
} static void I2SDataTxRxActivate(void)
" F% C. V! ~% u( U5 |- |{
9 J* R! d3 L6 _/* Start the clocks */
6 G1 S4 s q1 a7 H9 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; x* @1 J0 S' y' v) ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* Y6 W* [& b6 z: ~9 U( j, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 r$ H$ Q' G/ N' N1 a) CEDMA3_TRIG_MODE_EVENT);
( ~* E- Q1 o" A; f6 YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 F. R3 T+ z/ r3 H C5 l6 m6 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 i! `/ p/ M' `4 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. h# n4 f. |) v5 x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! T( A b3 i2 n) p/ U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 |2 f- c8 ~) [7 b% [$ J- cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 @7 G4 \8 L, D% d! L% K' Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& W" r: T$ o. l; O" [4 C' I} 4 ?6 I! Z( h1 f5 t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 W$ G( d& T- {7 l6 T
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