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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' e! n( V$ E2 m6 R7 winput mcasp_ahclkx,
( u% ^. |* \3 h6 U% rinput mcasp_aclkx,2 n$ u: ~, p! U/ B( B. U! ~* ^
input axr0,7 n9 L' R. _ \4 j! x0 p& j& y0 h
/ f/ Z3 Z4 I$ ]% t
output mcasp_afsr,
6 t) n) e% W4 q" ~output mcasp_ahclkr,
, l5 A& O6 X' m% [/ ^' l/ woutput mcasp_aclkr,! S7 m8 ^$ K7 O
output axr1,# g4 x" e/ ^0 ~# S! ]# L
assign mcasp_afsr = mcasp_afsx;
8 o) v( T$ ^) S8 [assign mcasp_aclkr = mcasp_aclkx;
' G+ S( k& `; m; R" uassign mcasp_ahclkr = mcasp_ahclkx;
+ x; w# G! l+ c* n9 Q8 E/ }6 R6 q8 iassign axr1 = axr0; P$ ]% J/ u- i9 `: K3 P2 c
0 l' T2 Z6 u- E2 H8 s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 p$ O( W: H; M8 t/ a1 f$ {
static void McASPI2SConfigure(void)
! X* o* z F5 M{9 h+ c6 }/ ~- u9 _* S, `5 m7 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ }& J% f! M" ?" n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 G, u: x4 K) s$ ~- z' T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) U) X- A& o6 Z' u2 U+ c+ q& b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 @* G' E- g+ v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ U T+ \3 u, {5 s( E" b# xMCASP_RX_MODE_DMA);
7 [! c$ h, I ~" t' C( m/ N" |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ?. c J& p' B, O5 d! z9 Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 @7 j9 n o" R8 S6 \3 C0 |7 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 u! X' n9 X8 o9 f$ a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' W. T8 ~* v0 s$ V( f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , q9 _: K8 v0 r) y: P% ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ {2 K, g# J9 v' E9 gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& L) x( p" L; m5 S; u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ Q J% o! n# X" h" `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," V; c% f9 S2 [0 r, X
0x00, 0xFF); /* configure the clock for transmitter */
( Z3 u$ d' E+ g) o/ n3 o$ V# aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ g1 V1 D$ s: d( W& J( F3 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) d3 B2 t; Y, D X6 y; i9 f: _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 I6 O( l2 P* X4 {
0x00, 0xFF);
) m4 X: i G: s) q
- n( |" ^/ p0 [! [' T/* Enable synchronization of RX and TX sections */ 1 u+ `2 ^0 G3 a6 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: C6 ~0 s. V0 X$ a) ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 U& R8 K4 }7 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 M" N3 d7 m2 H* W) I8 @6 t1 Q** Set the serializers, Currently only one serializer is set as: B7 D; ~+ ?' d+ s& S/ h
** transmitter and one serializer as receiver.
; B0 ^6 e8 Q% c. J' b3 Z*/& Y1 x7 Z- Z/ g5 ~* k4 V& I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) e8 T! j- V1 U+ C7 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ G9 l" ]8 R0 V& x1 v) ^ N
** Configure the McASP pins * q- V& X3 v" Y
** Input - Frame Sync, Clock and Serializer Rx
8 R# P* I! B) ~1 i$ c% e: }" Q** Output - Serializer Tx is connected to the input of the codec 9 R7 _6 j. u3 N5 ^" S
*/# E( Y: {. `4 G' i2 c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ [( Z- E" w5 C& u# G2 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 F1 _) N5 n* GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 c; a+ v$ \/ [| MCASP_PIN_ACLKX7 i& l# ^# A9 ~' M2 H
| MCASP_PIN_AHCLKX
0 q5 |: Y! q6 d8 d, I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 J- U3 X3 [; Z& v5 Z1 I5 ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % \ B9 N, k- F' W" R+ a( p
| MCASP_TX_CLKFAIL
0 ?4 `6 w* ?7 T2 e- g4 I| MCASP_TX_SYNCERROR6 ?" \8 \( S8 i4 F+ f; ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 K: h L& f( x+ |) f| MCASP_RX_CLKFAIL
; G4 }- U3 P$ m) Y% V( G/ t1 B( e6 O| MCASP_RX_SYNCERROR
& d5 f* X9 A8 j| MCASP_RX_OVERRUN);
7 \$ V7 R. B* |4 j' a} static void I2SDataTxRxActivate(void)
' `+ A9 t5 Y% ~) ^" v{$ k* @9 w/ o5 m3 g
/* Start the clocks */4 b4 R3 o5 c& Q, s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' w+ e! a$ Q$ j! u- {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 o' c8 c; ?7 A0 |5 M; a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: {' g# g/ f$ r* z y% M! \EDMA3_TRIG_MODE_EVENT);
4 ?/ V5 G6 a) M# O f+ ^* w& X& iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % ~" |* n: k0 P d U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
r% O- V6 H9 ` T7 I% v0 ~% nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ |: |: w8 B4 q$ J8 a' \' iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. `, g6 b4 I1 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 Y& e& U1 d9 ^6 Z3 V$ {+ jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 x: j4 F/ R9 f3 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" S6 N& r8 [' B3 b% E
} & ~0 o. K6 q" b2 l0 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 W0 p5 F$ D! H% x+ L
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