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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, W/ I1 B6 u& J+ {# Rinput mcasp_ahclkx,3 K! j6 ~$ G6 [! N+ Q
input mcasp_aclkx,7 G' A0 B' B' Y- J$ b0 C F- b
input axr0,
- n8 ?0 c3 C, u/ B
" V& d# Y- q# uoutput mcasp_afsr,
k9 R2 h5 [ z' V1 i. ooutput mcasp_ahclkr,# |& B$ W5 I& }+ y, L; |
output mcasp_aclkr,
5 I/ Q1 p1 z1 ?output axr1,9 t# h3 C) M% q4 @
assign mcasp_afsr = mcasp_afsx;
- g( a; V0 W! z- O7 j- a7 b8 |. vassign mcasp_aclkr = mcasp_aclkx;
5 U' {4 {3 J p' u5 F& i# Vassign mcasp_ahclkr = mcasp_ahclkx;% [5 U6 U1 e4 J* O0 X1 z$ @
assign axr1 = axr0;
0 _: w% x. g7 m6 j! w% T; w
" W4 B' j+ B: E/ C* m1 m2 q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 o1 |1 f( Q! e9 h( T. J' \/ v
static void McASPI2SConfigure(void)1 \4 g& n! _4 f* a! C6 {
{
# b# Y% `; y0 h: K6 \. RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 b8 H4 m t( q" O* b6 ?$ oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% L; d$ L1 }; m6 B2 bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# p" b( ^( Z1 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 E7 y" _. S- I! w) U/ E1 l4 K- Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' K2 X$ i8 |9 @# x
MCASP_RX_MODE_DMA);3 e% u7 s1 Q3 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ ], s! @8 E! b! @& JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 D( J9 v+ h1 X9 h) G7 GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 |6 u& V4 w% Q+ RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); V+ j) f$ l6 U5 [ W7 B" N5 ~. ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" z* l& p0 z" |2 T5 l/ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. W1 F5 l& j7 m/ |' R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 d: v) o/ P" |( ^' N) C2 A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; A; r# c; L. z" N' SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) {* R6 O p$ j& l; e1 u
0x00, 0xFF); /* configure the clock for transmitter */
$ C- {) W+ ^* g2 n: T yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) K3 G# u5 _! Y% U7 _) k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 \0 p/ a" z& Q" ~3 ~5 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 B" u* z' V( m1 W7 Y! B3 I0x00, 0xFF);' t1 Y/ [3 z4 d# ]: K* `% H
, K2 B; y+ v6 x/ g" I/* Enable synchronization of RX and TX sections */
* n6 k) N$ e0 `4 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& t4 L, B1 i, k, n7 FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 V* Z# K/ ?' S6 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; a7 `' |+ \3 r
** Set the serializers, Currently only one serializer is set as
! f S% S- O/ p" P9 b! f# ?- E** transmitter and one serializer as receiver., l* u; \0 e! }$ g
*/
. W4 |- i/ o3 }, g! e* E* xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ o/ C8 v( V- N8 j# H9 f/ HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 D8 j2 o* l/ T" ?, H' H4 {
** Configure the McASP pins
/ }: N, w6 L! y; t7 s, X, z& A+ v8 e** Input - Frame Sync, Clock and Serializer Rx
" o: Q9 ^5 Z- u3 q6 v+ [** Output - Serializer Tx is connected to the input of the codec & m7 j. f5 x' t* U! N( s [
*/
- ^0 `* ~; v" yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 [* \: x5 U# X6 m$ a: p" Y: l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 j1 d, G. j1 F9 e! HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ?# r0 J- ^1 P L$ a( m: Q0 J| MCASP_PIN_ACLKX( w2 F. S0 Y: x
| MCASP_PIN_AHCLKX
/ u6 {2 D" ?3 z8 J; g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 F" F5 R9 F: J2 l s i- a: yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : ]; I! g2 g i
| MCASP_TX_CLKFAIL % u( E& r$ m* |* R) \2 Y% r
| MCASP_TX_SYNCERROR
, [% T( S3 _5 l e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 `7 W' F8 v3 b9 Q3 V$ F| MCASP_RX_CLKFAIL2 B6 A* T+ ? L# M; l, M/ w# s
| MCASP_RX_SYNCERROR ) e( }- d$ i. X8 W$ @% f# M
| MCASP_RX_OVERRUN);
& J( \: A$ y5 ]& ~} static void I2SDataTxRxActivate(void)
# V4 k3 F2 _* _5 n8 y8 M: n# y{
6 C4 p. l2 e# b- j5 _% h0 l% `4 n/* Start the clocks */
. k' ?3 i6 B: s6 D$ G- [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ U- i" [3 i( S. }5 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" R! v' m: p z3 f$ fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' `2 K5 @& K' Q1 V5 xEDMA3_TRIG_MODE_EVENT);, o" \9 @, f( q. y3 }& S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 \' s% V" _4 W; h8 G5 X: ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 U1 |- H0 d8 J2 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; P# r' t3 R8 d, a* b* S0 L: E" eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 {6 ~: t& X& J( U2 ]6 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ p$ h- I0 Z6 q5 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' Y [" n9 l Z1 {$ ]6 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 A2 h* d& ^* o} * w: ?5 N* v: v. d, n$ c2 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! ~7 z% w$ G" {
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