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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," T0 X8 n3 Y+ N; S, \; y7 ?1 Z
input mcasp_ahclkx,5 B8 _7 N5 c2 S# m6 ~( D
input mcasp_aclkx,, x# _3 s8 [- i
input axr0,
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# X9 |9 A1 z) {% V! `3 r% m* soutput mcasp_afsr,; [( Q9 e8 l* Z! F/ ?, V9 ]
output mcasp_ahclkr,; P* T& y A" B# ]! r! P. f7 {
output mcasp_aclkr,% y1 m6 J3 C, q2 d, N
output axr1,/ a, C5 E4 b @) Y R
assign mcasp_afsr = mcasp_afsx;
9 I. J; h9 z2 E! Y; Zassign mcasp_aclkr = mcasp_aclkx;/ G* d, M6 I/ E' s& F! w4 ]% f" i% Y
assign mcasp_ahclkr = mcasp_ahclkx;3 C# H1 Q3 J8 Q m `) k, C
assign axr1 = axr0; 2 D* }; ^+ g' s6 ~* I, j+ g1 i
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / i1 y2 j0 `" {: t& t" k. m" I
static void McASPI2SConfigure(void)
- r# u4 {8 C- U, ?, e7 F2 g{/ V( s$ N0 t) \& ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 u( U: K' F5 C% k: E/ [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% w7 X s* u5 V; XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: T: l6 O7 A1 |9 c, T0 i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: m! N9 L" X1 h% X* L! y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& R& \& J& K: D2 ]# u4 s, v
MCASP_RX_MODE_DMA);
5 k( x# e& q* b0 z5 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 o) l) ~. v1 S2 C! t4 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' C) T* Z! r9 ]7 K3 a" M* e( b) r, s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# [1 T) e9 m4 j' nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" ~! H9 K i7 [6 |+ KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& n% i# Z& M' Z$ z, KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ y% \1 r, n9 l4 ~, J5 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 U+ o' j! N T6 j, p0 a. h; WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( ?; N' L: k/ L* W6 f) SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* S: ^# O+ H' n8 c# i3 W0x00, 0xFF); /* configure the clock for transmitter */
& e( k! ?5 l1 X1 K+ MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- y6 k5 F) {, y5 W y& |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 E, U2 E+ s' o. Z8 \3 e5 tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 [2 b! h; ^! }5 X# F& s0x00, 0xFF);
. | C) d+ N; d& X+ S/ O4 ]- K1 L; h; U
/* Enable synchronization of RX and TX sections */
6 @; v! S0 U# p& rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* e" }, A9 J* FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) j3 y/ e& [- _% v# c7 zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 `, {0 r. e+ N- X' k
** Set the serializers, Currently only one serializer is set as
8 h3 C7 P8 ~$ j7 v! M d7 h** transmitter and one serializer as receiver.
3 G [/ D: e2 d+ K*/
7 M3 e* R+ Q3 _2 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, n! k# ^: s7 P: d/ ]# {7 ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" u1 i( P1 @" e! o, @' D7 d6 X6 L. Z8 e** Configure the McASP pins & [! d8 f+ Z, P* Y
** Input - Frame Sync, Clock and Serializer Rx
; T( P$ Q; I8 Y+ i/ w** Output - Serializer Tx is connected to the input of the codec
) _2 |6 c) ~9 Z( q) b5 I" H. {*/" i1 }- S0 ?9 p8 q+ p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ m% d9 \: [; t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% [+ R# q, d3 u5 B" O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 u G) v7 ]! F1 r, Y2 E3 Z
| MCASP_PIN_ACLKX+ F% b1 y c$ z) K
| MCASP_PIN_AHCLKX: B. T* N$ A4 H9 z: J& u1 D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' e. y! X! y% d, x4 qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: j: o1 _/ j' C) }# n| MCASP_TX_CLKFAIL 7 o! h5 Y7 J4 b" w6 z3 r% E3 b, P$ e
| MCASP_TX_SYNCERROR1 e! O8 N5 E. _* z; w- T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 V1 V$ ]! ~7 c
| MCASP_RX_CLKFAIL1 C6 d5 J4 I2 [! Z$ h4 F
| MCASP_RX_SYNCERROR
3 d5 C/ H# I) o- x0 U' k- @2 Y( A| MCASP_RX_OVERRUN);
4 }# h- v6 V4 M2 f} static void I2SDataTxRxActivate(void)) ~+ [8 g' X+ X" Z( x
{0 b R. o7 x$ \$ S$ h
/* Start the clocks */9 T$ ~1 P1 t9 g7 L+ m2 H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' } }9 I$ G& JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 S" n [- j* L7 _0 \; m1 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 T0 W) ]; Z7 v! G+ I
EDMA3_TRIG_MODE_EVENT);
2 q$ N' |; w: ^1 [) O7 X+ I+ h8 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " f; G( U- @4 u- T+ m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# y g8 d# }1 c: Q: Y9 t z8 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 d* ?9 C( W! G& i% v3 N! l8 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 v0 a2 Z. j/ J7 ]2 Z" o4 E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 g) J9 ^$ p( \. A9 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( |4 k( K2 u/ GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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