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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. @; c9 \, v$ p" I2 ?0 o) i
input mcasp_ahclkx,
1 O" {, C( h& q) Q" ^1 X+ K) K0 iinput mcasp_aclkx,$ L4 J5 h. q$ }& ^0 J5 W
input axr0,
7 {) w1 r8 U/ Z _, J* P% Q5 O5 K! Y+ `3 J& m. F, ?* _
output mcasp_afsr,
5 h9 v, D/ i' |. Q! I. woutput mcasp_ahclkr,
9 N" [& `* t3 W {! j& Noutput mcasp_aclkr,2 E& |+ }: a' g: V8 i# i) a
output axr1,' b5 L4 d& X% O& L! o) z
assign mcasp_afsr = mcasp_afsx;
% l2 S: H, R* z9 l& e! o3 }assign mcasp_aclkr = mcasp_aclkx; T, ?& Z! A9 k7 |
assign mcasp_ahclkr = mcasp_ahclkx;
3 X- \. z2 _# }( P1 fassign axr1 = axr0; 4 ?6 R/ S7 Q4 P |; e6 y/ m% n; F+ R3 O' X
; J. C4 T. \- i# U6 X: f& R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 e' X. }8 {- P& O* Astatic void McASPI2SConfigure(void)& h- C- f. p* }+ x
{- G6 z+ ~9 D0 C4 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( m' C1 C3 Q! l. x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ x. T8 k/ \* YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# N- j: M6 z% _- [: dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, \& N7 \0 W6 I% g0 T# g8 v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) |+ s% v5 R9 d" o# P$ z" Q1 a8 H/ M: `MCASP_RX_MODE_DMA);3 n4 Z( G+ O& k' [; X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 I; l3 o5 {6 I* D& F& O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 I6 _5 e. k5 U+ T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' Q* T% G4 [# K: JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- D% h, A8 N7 ~! N, tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 [6 x! U4 y; @* J5 s5 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: Q) ?5 R2 ^8 H- m/ i" h+ F* X5 ?# iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ N2 _; _5 }, N/ E x7 N! Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( N u+ |3 U, @- }) O0 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& V4 T, X+ I" l5 n8 p! R8 |# G7 B1 L0x00, 0xFF); /* configure the clock for transmitter */5 e) v8 U5 m1 V5 e% O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 R; k y) y( X" U& i* L9 i$ GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 O: K0 O! B0 k! Q4 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 s( b# b- r+ L3 x- p5 i( e0x00, 0xFF);- c {3 \) e. R8 U
# W8 F( W( j) l3 _' f/* Enable synchronization of RX and TX sections */
+ `' b$ ]' d1 W5 W1 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* y& W% H5 e. s1 d, s+ w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 b% S9 Q; M8 I( [" U" d& c: D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. _; n! d) p. Y6 `( R
** Set the serializers, Currently only one serializer is set as
1 i: ]$ @# |7 S4 r4 g** transmitter and one serializer as receiver.
: ?4 K1 M- d$ T+ U1 R. n*/
: Y @# R7 r+ e& x# w9 z+ y; f8 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 B/ P/ u9 _& Y8 I1 `; D& B9 v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' j3 v$ D r# ~- m8 O* v: @
** Configure the McASP pins 4 p! l- C% E8 l0 O: K# N2 w, P h
** Input - Frame Sync, Clock and Serializer Rx
4 Y1 a3 d: Y( w$ Q9 R** Output - Serializer Tx is connected to the input of the codec * | N& e1 w% V6 ]9 a5 `8 e
*/
% S8 t* K# N0 c# N: uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! L# L2 n' G5 \0 E/ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 \; @) l3 D( ?5 A- F. JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& B4 d/ k/ f; y/ p% o
| MCASP_PIN_ACLKX) w3 K/ a6 Z6 n
| MCASP_PIN_AHCLKX8 q" ]' |0 }# t! |8 ~2 o( a4 Y# }( c- u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 P, s+ h6 h8 i' E: [/ R# o9 d3 KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* ~+ B; m( ` l+ J* R| MCASP_TX_CLKFAIL 6 c2 ^' k/ k5 I) J) S& r+ [
| MCASP_TX_SYNCERROR
% d- u9 Q# } l0 R( z. ~& D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 \/ p I/ s% ?) h4 J2 r) ?
| MCASP_RX_CLKFAIL
3 A9 e0 n. G: p| MCASP_RX_SYNCERROR
( n" X, `; R6 c- S6 F( C| MCASP_RX_OVERRUN);
9 B' h9 d5 W& ^; \2 _( }. v1 v' M} static void I2SDataTxRxActivate(void)
; z3 O, X7 m6 @% d( Q! f+ y" |& g{
4 |, T8 K8 o5 [' S: z0 y, y: B, b& Z/* Start the clocks */0 W( Y8 T5 h! T8 O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- y5 x- i% \& Y7 b6 v( a1 V4 D6 I% B( v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ `( r0 a/ {# MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 Y6 _3 }/ ?1 i' H2 VEDMA3_TRIG_MODE_EVENT);! L+ g/ ?$ \# S% W, J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % d. L; `0 m% }! U7 D* O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 @: Q/ ]0 H- E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; k8 j+ J, E" z+ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" v8 G$ S# D% ?( L' v: g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ z! I. r0 @; g& ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. w% K- D. W( Q% f$ |1 b2 ^; R5 A7 ]- BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 L# ?! L& w$ t5 P2 X0 U% L} / c5 V5 {9 _1 `/ J/ l; M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' b5 h' @# v! P7 {) S
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