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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 D! |5 F1 O0 {0 d* c* i& F3 |
input mcasp_ahclkx,
# x- Q( F9 ^6 H1 k( Jinput mcasp_aclkx,: A* T' D5 k+ E0 m
input axr0,; ? r/ A x4 r
* F. \' ^" g& c( R# h" g a+ }. \
output mcasp_afsr,/ p, e" e3 K* _5 l( J+ f
output mcasp_ahclkr,
0 q: o. k0 q+ k2 g2 T, Youtput mcasp_aclkr,, T9 I0 @1 B7 u/ T* e
output axr1,
5 D, }' H# z2 S9 I assign mcasp_afsr = mcasp_afsx;
! i+ j' B" i, z5 `, t' Zassign mcasp_aclkr = mcasp_aclkx;
. f& p u" b7 Nassign mcasp_ahclkr = mcasp_ahclkx; J; S9 @1 N& q) Y# i+ S
assign axr1 = axr0; & t" d. h* N- K' N* g2 C0 V/ O+ S
; e' Y! o" ~/ `5 ^& D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + L T1 P$ g! n7 D: k8 `
static void McASPI2SConfigure(void)8 i& r% @3 Y r
{
7 T: R2 I; n0 s {7 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# b" i8 ?: H' x- |# B- a" c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( i% w4 a) X+ }8 |7 b7 I( A- D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: n7 r! N4 s% @5 j3 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 D1 b3 t a) [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( A) t1 p% m$ }; d4 U
MCASP_RX_MODE_DMA);4 _& d% A( R& w! p. j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
u) w4 ?. S. A/ b+ f+ kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 o, P: x$ R9 ~7 n4 @( ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 e8 z9 s0 `1 }' dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' t, Z% c2 U- VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' D: ^# |6 l, a3 e: B5 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' T _( l, e9 T3 n8 y1 hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, a) Y8 K0 d& N8 s" JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 L/ ~, V' r$ ~7 T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* w" I& V+ }; \+ M v( K. a
0x00, 0xFF); /* configure the clock for transmitter */+ ?+ U# c. \9 U M3 h8 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& v, W6 q8 x8 s& W' o3 B- ]* PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- b5 x5 T' f& ?( `2 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* l+ U1 q2 C( I1 T. j& z( u. S% g
0x00, 0xFF);: ^5 ^4 O" Y7 A' ]& o8 ?
) g& K* H5 f. Z
/* Enable synchronization of RX and TX sections */ 6 o! v" H! u' b& s; b4 s7 U6 \0 l2 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// v; H9 S# L9 H4 W) R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, a% W& X: q5 m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** @4 D$ r( l% }3 S
** Set the serializers, Currently only one serializer is set as) S" P8 X8 I" D4 }( O
** transmitter and one serializer as receiver.* V4 [4 ^( t W6 i3 v
*/
8 F5 d: h' x" ~: W7 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, I8 j% J7 S$ z4 z6 N3 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 k! O' O4 p% u6 u
** Configure the McASP pins
( L- E2 L0 G+ ?** Input - Frame Sync, Clock and Serializer Rx
* A# m2 { m& p$ e( H" T** Output - Serializer Tx is connected to the input of the codec " ?# R) G+ Z$ v1 A7 T" A7 Y3 K
*/; ^& G9 O" z: ]2 A4 |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, p3 ]8 [& ] m. l9 S' @% T, U# `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* o0 B; F& {3 i4 P3 g+ j. T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 d5 ]7 u/ }) T4 U! x7 i
| MCASP_PIN_ACLKX
; X3 q+ d9 |9 u* H0 z| MCASP_PIN_AHCLKX8 {) X6 n! ^& Q' D" m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ e# g6 R4 b) L. A# J2 |$ r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % e) w5 U( V b8 l' C8 S
| MCASP_TX_CLKFAIL
% x( B/ t7 |6 i& p| MCASP_TX_SYNCERROR' s7 |- [/ w. b) S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 v7 |" b" z7 I; u9 f| MCASP_RX_CLKFAIL
. a0 S2 G: @& V R| MCASP_RX_SYNCERROR 8 A, ^. K' {& u- n9 Y% O8 x. X7 N
| MCASP_RX_OVERRUN);; e, y) g7 h3 Q/ P' l
} static void I2SDataTxRxActivate(void)' l: l2 @% _! o$ `6 M8 q
{7 W9 r" C" F( A P- [/ ^6 @
/* Start the clocks */ \ P' X$ f5 ?5 T8 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! _$ ~- d% B& nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 V/ k S# f8 @' x1 e! }$ DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* `& O% I1 x! E; V8 K- E0 u. |EDMA3_TRIG_MODE_EVENT);4 L; l/ _) k% K: I. j( m( }, h, y1 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! @* r, N, {* F9 S8 E. q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 G# y. q* |" } X% x' YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! o$ f8 B3 s- h7 C# n7 AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ ]/ P, q2 [* j8 ?4 Q6 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 H1 _3 j% I5 z! [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 f( S) \: B0 |+ a ]- @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 M5 d5 D M9 j
} 8 M0 N5 c$ P6 ^' l9 t- N3 G4 T* a P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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