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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ H5 ^' Y2 f# }0 {$ r2 G N$ qinput mcasp_ahclkx,
0 e8 \) s# ~; L5 I* k3 _input mcasp_aclkx,2 S( e+ ~( p X2 w% Q
input axr0,
, S/ H8 V0 t: ~2 s, j! @7 M( T( l9 w$ c" I* v
output mcasp_afsr,
. j1 e* X5 K$ E2 N/ Ooutput mcasp_ahclkr,
% C3 C8 m0 c+ Aoutput mcasp_aclkr,7 A2 N; \. q) ^
output axr1,! o4 k. U; W4 t3 N, B
assign mcasp_afsr = mcasp_afsx;
: j' w, m1 Q% a( f& }assign mcasp_aclkr = mcasp_aclkx;
& y9 h. Q; C+ } W4 C- Aassign mcasp_ahclkr = mcasp_ahclkx;3 I" F7 [* `' V% {. P! Z
assign axr1 = axr0;
; Y- M3 r; B5 T* Y$ ?7 {' H' k: ^) W1 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! a1 f7 @! r9 r. f6 Z i
static void McASPI2SConfigure(void)
) c7 B( t( A* Y- J8 d% y{5 T. s6 R! M) I" Y/ \% T, K. ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 ~* Z+ h& M. @4 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ A$ a+ \; v( h$ A
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: q! M6 T, U0 \. o8 Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- e1 U: J8 w3 u0 {& @4 \( I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 k6 y$ H1 G( WMCASP_RX_MODE_DMA);
/ m, n# F$ R c' a3 V5 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ V# Y6 L ?) z3 u9 k4 ]7 j; k/ ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 y9 j" a3 w. V; pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 {6 a# a( a$ K5 E9 VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 y" N& t- F h3 n( O, mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 l/ n/ p0 v) z+ r' aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) j/ K$ T# t* G c. ?( u3 C
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 j3 ^+ N6 U+ n% l7 q/ ]( HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" K$ w# x3 N7 F" DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- ?6 ^2 T/ ^/ O9 Q+ J, ^
0x00, 0xFF); /* configure the clock for transmitter */, u- \% w8 `" y$ P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* w9 R" m, `9 D6 P6 l E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 H/ Y% J: H+ x) T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' Q8 s" r6 d3 x- ^ j0x00, 0xFF);; ~+ m! x7 K& }. _4 o" |
! `9 C9 s( q- g2 G1 d( A B" Q/* Enable synchronization of RX and TX sections */ G! B+ o, R2 D7 V" S2 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: D" O! `8 i) W2 v4 f+ i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; |2 p7 Z; J' ]0 A- E2 E# y' w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" I# e$ j6 p4 ~/ i** Set the serializers, Currently only one serializer is set as
$ p% q7 }: } O/ P** transmitter and one serializer as receiver.. d% e2 b' r! y3 y- @1 [6 t5 M
*/
; X" j' y0 \+ A k# R! ?4 y2 aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 z3 F9 g; I5 v; |* p5 V2 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' a2 n D: L' ^** Configure the McASP pins
$ W4 b+ S! V5 A5 `3 x8 k) Y** Input - Frame Sync, Clock and Serializer Rx
3 C7 O0 P. G/ T& V! N** Output - Serializer Tx is connected to the input of the codec 0 p6 E! U. \1 P8 I8 {
*/3 L& F& N; p& t/ \; _0 P& G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- i8 Y* b' j, }% y3 K6 kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ V, f8 T! B I6 c8 ~, _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX ]# ~8 }; b& r5 M: u$ l
| MCASP_PIN_ACLKX% X/ m# q/ E8 M, Y2 \- w2 s, {1 u% ]
| MCASP_PIN_AHCLKX
4 O5 E% {) }8 Y( h* x# A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 C/ J3 B, E, u5 @8 n' ]- T; U7 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( |7 ~1 B3 ~. V7 |
| MCASP_TX_CLKFAIL 1 X k# |# M" o7 V9 V$ {
| MCASP_TX_SYNCERROR
4 C* \4 g5 b2 n0 E8 O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 w, R% s8 ]6 u| MCASP_RX_CLKFAIL
: A# T8 Q6 b, K/ L| MCASP_RX_SYNCERROR
" A+ S' J! Y, c& f. B/ {| MCASP_RX_OVERRUN);/ [9 W% W$ v3 }# e. `$ R Q
} static void I2SDataTxRxActivate(void)3 ?* g1 N6 {" l* N3 y) r: z
{& p- `, F# M% B" H+ |
/* Start the clocks */
. b% K! q$ N# O. z- r" P$ PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, J, D( D4 f6 S- ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: U4 B" C7 F. m' h V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ H+ A3 g8 `! V$ H8 Y) ?2 kEDMA3_TRIG_MODE_EVENT);+ i2 V6 l: ?3 c! V. T X8 }+ y0 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 _ t5 ^/ K$ L4 P5 j- D$ qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 l4 Q- L( c1 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 X u. W6 x- T& DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) u# `- B+ I8 `* t8 A* @: Z- k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 A) N& G7 u% B( f; p9 d; ~3 G5 f# k
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 x; W v# p: o2 K( ` `
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- F' _. M) w7 w; M+ ~7 R
}
) m4 x0 R4 c) L1 b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 {! q5 H7 l0 ~* Z. R
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