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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ K5 U. a8 v2 ]5 T" I9 {0 I
input mcasp_ahclkx,. Z' R& q: U+ r( s* k/ \$ ~& U
input mcasp_aclkx,
+ A% P4 U7 a! c* Einput axr0,
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* ^+ k* i/ ^* S+ i# F ?- boutput mcasp_afsr,
0 J0 T7 g; d, C2 Coutput mcasp_ahclkr,
7 y* c/ O& m3 w/ T& s0 Y: Youtput mcasp_aclkr,
7 b# K- K* A' l1 e9 W: c! |output axr1,7 Z& t. \( U* Q6 h9 C
assign mcasp_afsr = mcasp_afsx;
; f# x! N9 |" E! @assign mcasp_aclkr = mcasp_aclkx;
) Z" a4 O) N' a% ]* u, D8 nassign mcasp_ahclkr = mcasp_ahclkx;2 F/ x! M. [% g8 I2 ?" J
assign axr1 = axr0;
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7 @0 s- S2 c7 ^4 b& a9 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! J+ s: ]# C# P- N+ }( `% K
static void McASPI2SConfigure(void)6 R$ R! s: i2 V( I6 r
{
9 N( W) [# c7 F+ ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 y2 R$ D" r2 k, W2 _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 L& v0 z z ~6 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' F8 \2 V- R1 T( g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 T2 J' N3 y& C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 u8 [: e; ~& S0 v6 v
MCASP_RX_MODE_DMA);$ z, w* Y& d; @# |" `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% ~/ q9 \) \! x; o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ O% N) ^6 b# Y7 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % i+ t& p* E0 r8 L7 Y" `! y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- W# D8 U5 ^# D" \, qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 ]' u' l5 d d0 P, @7 g( H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 C6 C9 d, f$ p# n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 Y% r& n* h9 n5 p6 _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' c5 G" S/ r5 s6 t1 qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 O: h. Z( X+ O) f9 z
0x00, 0xFF); /* configure the clock for transmitter */
1 M$ _! W- @$ IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 o* R4 K5 L o1 s. t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- O- R$ e7 I* C: v3 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' K; b K$ w' x7 r& U' ]
0x00, 0xFF);
9 `. U Z: N0 t0 n9 B; v% k
z9 V# `! D8 ^2 ^. G6 V& Q& c- [/* Enable synchronization of RX and TX sections */
* b3 o- [5 X( F @0 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 H( w* t2 ? }1 T& b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- N, R4 m; u; B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. m" W6 r0 _! p; i
** Set the serializers, Currently only one serializer is set as T5 X2 y* {7 A4 b0 `
** transmitter and one serializer as receiver.8 k( I; Q, J! y
*/
7 X# A6 u S0 U4 IMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ s" G$ g. C Y5 w1 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 ~# o9 q$ c9 ^% ^
** Configure the McASP pins
# S3 ?3 L7 o+ u s% G) l** Input - Frame Sync, Clock and Serializer Rx# F5 c T5 Q+ B& g3 y
** Output - Serializer Tx is connected to the input of the codec ' n8 [) A% S8 _- k" h
*/
' S* {2 T: [! M" a& c2 [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" b) I$ r8 _( zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ [3 j* K; S6 ?4 o' N7 p2 n& C* I+ vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' u4 c" U s2 F) k% M0 g5 E| MCASP_PIN_ACLKX
# c7 |6 y5 e/ z$ j| MCASP_PIN_AHCLKX4 V/ c1 V5 J, h7 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 d( J, O; A( Y5 l* C9 {1 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " S0 c7 ^0 c4 F
| MCASP_TX_CLKFAIL
+ u3 x7 U6 \1 K) r& n& v| MCASP_TX_SYNCERROR
. V, t; o* J" W# ^/ h' V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ W, B$ j: W L% B( g2 j7 f| MCASP_RX_CLKFAIL( k* |. B* T) B% ^, a" \) D& P
| MCASP_RX_SYNCERROR
& r- o3 A/ P4 v3 u* {8 Z| MCASP_RX_OVERRUN);6 G* p7 h3 c% }6 n
} static void I2SDataTxRxActivate(void); b8 u7 o" ]) L! J+ v, ]6 n8 ?! B# r" q
{
1 A* R; T% g- |) l/* Start the clocks */
0 E0 M& R" }0 l4 {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 u8 Z: ?0 N* q' Y+ A5 a* ?, W n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ e N& y" m, ?; L8 c3 l8 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# m: [3 I/ a5 Y/ HEDMA3_TRIG_MODE_EVENT);
4 \5 k, J7 W) k2 h3 o8 c& SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ U* y+ v5 F# CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( e, c3 q& @" B: `. ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 v( v& u0 S: a+ Z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' \8 ]1 a( D: xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 ]" n- e# G" i2 W- ?5 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! {& q$ |. b! {, C5 W8 i* R6 xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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1 `6 I4 B& B9 U% F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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