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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- V' t! R& }7 P5 Q! ninput mcasp_ahclkx,
) j5 P% P7 q8 K8 V5 E- s- |* pinput mcasp_aclkx,
3 |% ~! D9 L9 z& F8 @0 hinput axr0,
k4 J& s# U' o$ R; `+ ^8 P, W2 F8 }; G* P7 Q
output mcasp_afsr,
- M* s: q. |; J: coutput mcasp_ahclkr,
1 J. v1 r* U" a3 P5 S9 Uoutput mcasp_aclkr,
" g3 |5 Z7 k. t/ u- K( _output axr1,
* g* F$ m8 t1 R6 M5 W5 I1 t assign mcasp_afsr = mcasp_afsx;
# \8 N& e% g. A( i4 q& j' jassign mcasp_aclkr = mcasp_aclkx;8 I. {" O3 }5 s$ L
assign mcasp_ahclkr = mcasp_ahclkx;. O6 r8 t1 ]6 F+ J
assign axr1 = axr0;
1 o, ?- W7 T' o) D) \" B! n& \2 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , b) D2 Y ~6 D4 m1 u4 J% h
static void McASPI2SConfigure(void), ^2 s9 e1 F- r1 {
{* Z7 c( U+ ?6 `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& b3 ?$ y" m4 Z' Z4 J2 k4 Y+ |. N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. Q% {5 k# E; J- uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) _; y: X3 q- L% G" p8 F# A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( a/ L9 m. h, `) LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' J i" n8 f5 V. ZMCASP_RX_MODE_DMA);) o$ D& ?$ V3 P4 x) s+ F; T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; W, T. C3 B7 {7 f% j QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 c1 }- m" U4 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & l3 A6 X4 E( k5 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 Q- Q p0 R1 F T% ~% p/ nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 W2 Q- L, x4 f6 X9 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ F8 y! T8 H. X1 o5 CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, N; k0 p; S; K$ E7 I3 l+ W( MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& K7 v# d3 j/ \1 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: m9 v# ]% g5 x3 g3 D7 [ s
0x00, 0xFF); /* configure the clock for transmitter */- B0 Z% C5 \" y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) d, {7 _" u, g1 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! ]+ z: Q6 x) k& _( p/ o9 a. O% V% CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 W+ _8 i. o/ K! X0 P
0x00, 0xFF);
" C& ]* Y2 `3 F$ D& U' D" g! X3 r0 b6 L
/* Enable synchronization of RX and TX sections */
+ Y+ Y1 r- @( e& o0 n) M! y+ _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* Z T& {! U9 h: ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' F' C% \' Q& j% Z1 x- D3 r# nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ g9 r$ R9 N2 E( p" s, X) M+ I1 O( u
** Set the serializers, Currently only one serializer is set as
9 X8 L- `/ j0 V- \** transmitter and one serializer as receiver.2 |4 m- U0 }. D6 R ^/ M) j
*/8 P; a4 I% l* p( e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" w$ B, p# O5 C9 l4 V+ e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ x+ `7 F5 V2 S. p# F p
** Configure the McASP pins
' A4 ]* u8 W8 V** Input - Frame Sync, Clock and Serializer Rx
! c+ l) q3 v; V& d& w** Output - Serializer Tx is connected to the input of the codec
* I: D! W3 S( \. P2 `# D9 ?*/
3 [+ ^( Y8 h9 k* F! Q( p# uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 P M* Y; M' J8 R% j4 T) ^( bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 C* w" @5 Y" `4 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, E6 r0 L9 b, T| MCASP_PIN_ACLKX$ E# A5 u) d. W: Q( g3 ?9 ^
| MCASP_PIN_AHCLKX' R8 g1 }( ?2 I# f9 Z# ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 \' k/ C L' X+ HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" O: ?: h! Z9 c$ n* G3 f1 S6 U3 l| MCASP_TX_CLKFAIL 2 w5 x( Y8 p( L2 z
| MCASP_TX_SYNCERROR
# P, v# o P9 E1 J/ g3 W, T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 z* ~7 }4 l. L+ x1 b4 ]
| MCASP_RX_CLKFAIL
0 y9 g9 L! F7 @| MCASP_RX_SYNCERROR ; |) v4 S. b$ o1 ^3 t
| MCASP_RX_OVERRUN);
7 U$ X1 @/ \1 P7 ~} static void I2SDataTxRxActivate(void)
, B4 g- }' r3 X: o{! ]: h# h, w, Z% ?
/* Start the clocks */( `+ @/ H; u, Y# z# y: n! i5 l3 ~8 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- A _ c K+ l' u5 Y% U$ JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 l. e- s4 H! o* S4 Q* g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) D4 p7 |. A2 l0 M5 ?2 L$ _EDMA3_TRIG_MODE_EVENT);
$ h( ]- G/ E5 _5 Z& `: CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! H4 y6 K6 A* J/ oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* v" z) f- p% `5 f( _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 H, t8 b2 f; T3 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# f' G5 i+ x3 I, O! d% Z7 k& l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 [% ~! _: |4 e& t, Z+ V) s5 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 U" [7 ]) V7 d* e, _" Z" Q7 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ i* |; l1 A+ r1 q5 m}
4 e2 F, X, M$ S5 a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / t' ^: M- M% e0 V0 M5 P
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