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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* r( n0 k p. winput mcasp_ahclkx,
# P0 z' w ~! G6 N, L* o. m* X$ ~input mcasp_aclkx,* e3 r' `- c* C* \$ G' {2 c
input axr0,
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output mcasp_afsr,
; V/ Z) _( c$ ]( A. a: Houtput mcasp_ahclkr,0 S! X' Q: ?) k a9 G+ ], M n
output mcasp_aclkr,
) @$ Z- d$ w! A% zoutput axr1,
& D; _4 V0 J9 V L8 R" a) w+ I assign mcasp_afsr = mcasp_afsx;* k3 ]& H3 P( `; o$ {; e) ~; w2 Z: a
assign mcasp_aclkr = mcasp_aclkx;
1 ~7 A* A* v- Z! Z* |* vassign mcasp_ahclkr = mcasp_ahclkx;
* Q: _8 E! i; _0 S, y7 rassign axr1 = axr0; M3 x! H( P" d( s& u
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " b4 _% M& }: X" K! C; J
static void McASPI2SConfigure(void)
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3 @, f- F* q9 `7 T7 s7 C9 m2 g- k& ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ W: O( g% \2 Q4 Z" Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// L' f9 l. s4 _- L M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: H7 g5 U( W- MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: D" I! K- I+ a$ x8 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& U1 Y' X o1 I" v& f
MCASP_RX_MODE_DMA);
# C" N, j! M3 j9 H) PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ?% g2 E% |6 _8 w0 l. UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ @7 z i& d: g7 ?- VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; `8 D$ w) P( }- h9 ]( [# T4 p0 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 Q: c' S' n: ?) U: j5 Q( fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- e6 m, [( R/ a1 Q1 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' R# P- Y0 H5 V. k% t9 K4 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; J' h1 M) H) f6 h A4 zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 k. U, W$ }4 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! Q8 }7 i+ o- r# x; X. Y0x00, 0xFF); /* configure the clock for transmitter */
6 D, l1 r; A$ O) g8 RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 y+ d$ C. U2 g8 Y- t# [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % y6 ^9 D- Q5 ]- F7 q$ j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: n5 X- L2 x. \& |+ A5 J3 P3 N
0x00, 0xFF);9 m/ ~. d2 P b, N3 n- G
" Y6 _9 H8 O" p1 n; T. J, \4 e# [/* Enable synchronization of RX and TX sections */
& T7 `6 w4 p. d. MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- G) v' L1 I% t" k! RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 j: m d, j) ^4 {5 {4 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ [& ~5 R, D- i/ |
** Set the serializers, Currently only one serializer is set as( O, u. T7 R/ b" B0 ~* Q% h
** transmitter and one serializer as receiver." Q5 c: c% k6 E" ? C \* y) W
*/8 \, P h- s$ N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! F0 e D8 ^$ T" z3 |7 B! h9 dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" `7 Q( L6 [7 s! b' V** Configure the McASP pins ) N a5 _" }: s# ?9 j" q5 b2 J$ k
** Input - Frame Sync, Clock and Serializer Rx/ d9 L/ y& F7 M* `2 E* _. b0 n
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 T! d- V, j: t' D; fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 X1 d1 Q- b+ _( R5 v( BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- R. ~! T+ v$ {( j8 H| MCASP_PIN_ACLKX% c6 Q* y3 \9 I+ R' Z3 e
| MCASP_PIN_AHCLKX" S% e, ?) r0 T9 u' S/ c; K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, D$ {" [$ P4 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! D* I5 U2 Y: W+ X
| MCASP_TX_CLKFAIL
; u# f6 z) Q& V( C5 x4 D) s, k| MCASP_TX_SYNCERROR$ {5 `/ ?/ ` K s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 h( {. e" z" |& O| MCASP_RX_CLKFAIL V- ~- W& \$ H
| MCASP_RX_SYNCERROR 3 t" V# B) ^0 M1 d$ V0 j
| MCASP_RX_OVERRUN);
& I1 \* E0 u. R, G, W7 G} static void I2SDataTxRxActivate(void)
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1 b! b" H9 N1 C U; F: K2 q/* Start the clocks */4 q9 }6 k! i* l, S' q/ C, b# ]0 F% s; x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* d, ]0 b2 n! o; D7 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
e- n- r* x% C2 y+ [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ~( z* c2 C- t
EDMA3_TRIG_MODE_EVENT);) }9 v+ t( Q2 ?+ b! } l2 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! O$ Z- F4 ^( g- N/ U PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* J5 a: t* |7 q, K8 a4 V" yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( r7 y; j" N' L0 WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 [# J2 Y: _. iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// a1 Y% q' N0 _: X3 S- p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" Z' V- i, a3 q$ M: S, d' z6 lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: _ X! X( F/ d8 x
} 0 s) ~' K6 G3 d- @; x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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