|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; G) Z% D" j3 [; Y* K
input mcasp_ahclkx,
1 ]- t5 p' @: K! [input mcasp_aclkx,
, i; c) G" l6 \input axr0,
6 Y0 z0 u" t4 }
# o$ p/ B0 l1 O. ]output mcasp_afsr," q$ W" Y, A- {
output mcasp_ahclkr,
~6 B% {& o" O' G. H+ L& z& Uoutput mcasp_aclkr,
1 i2 U1 ^# e! `9 g _% Ioutput axr1,
9 D, q; y; Y! v assign mcasp_afsr = mcasp_afsx;
8 K) @5 r- j) m# @$ }0 P, Kassign mcasp_aclkr = mcasp_aclkx;1 ^* w+ v) U0 ?. T8 l8 y
assign mcasp_ahclkr = mcasp_ahclkx;+ s% O3 L2 ~# Z( X) L% u
assign axr1 = axr0;
n* d9 \# S* l% ?0 x/ f- G, L/ l6 G- J/ f9 s( F: x( l" h4 Z. E) e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" I* \9 \: K! Q7 G" D2 y3 dstatic void McASPI2SConfigure(void)
4 L1 f. R" Z6 Q' P9 z# K+ c- O0 N{
1 Z: _4 _6 i8 R! j4 K7 r" k+ YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% h/ p. T, I% D' h* q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' b! u y1 h% v# hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 r o' R1 f7 r" f' M4 i1 |6 X3 qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 n$ t0 q* B& _7 P+ y+ s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 W- b7 o- N$ b7 n
MCASP_RX_MODE_DMA);
0 ^3 I" f* K T1 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 g* T( _: T4 c/ G' [/ [( UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 q2 u9 S( v6 z- p6 N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 D3 O( \, S# H8 c& C) s: CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' j; w; ]; _% z O+ a: ?9 s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ ^& \ ?, ], v6 T: k9 k! |8 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# @" G2 A8 j3 B5 J9 l8 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, y7 p9 d6 r! XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 L/ `$ @- \4 ^" H6 | T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( h6 Q7 k( b8 [( g5 v. c0x00, 0xFF); /* configure the clock for transmitter */% A' ?* |! ?$ r/ Z. ?) W0 q" o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 T2 i8 T9 l# L! M7 H# N& f9 e- u+ m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ `( n3 O, C c+ D9 a* _3 b' b% I, f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- Y# U- E! P0 b( V2 q& v0 Q0x00, 0xFF);
% Q% ~: {" y6 v5 F% b) ^& ^2 u0 f6 o! T& k/ t
/* Enable synchronization of RX and TX sections */
" G+ W% _8 z5 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 y- e1 w+ k( d" PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, R5 I" t% |6 L0 X8 J( ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 z8 U) o1 A( D9 j1 ~6 v2 E
** Set the serializers, Currently only one serializer is set as
3 Q x+ D0 [* {/ P9 d: u: k' x** transmitter and one serializer as receiver.1 x! z7 s. \% f, W- g
*/
( D! z& b- u0 B& G$ @* LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ h; P Z3 H; u3 h* H+ j% LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 b# q; A0 G7 `1 {5 [# q7 X/ i** Configure the McASP pins
+ U! h+ \: w, d0 P) ~9 S** Input - Frame Sync, Clock and Serializer Rx3 N' R" ~1 q2 O% w
** Output - Serializer Tx is connected to the input of the codec 6 o$ w- b2 s# w W" a' ~5 e7 z
*/. p! p- B+ I& j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( e6 }6 w( A( G ?1 b0 h6 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' J! f( b1 v5 G7 _* M: cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX o/ y/ J% f3 T/ e0 v7 ~1 c: {
| MCASP_PIN_ACLKX8 m# ?, V9 ?8 K$ K6 F. `1 q
| MCASP_PIN_AHCLKX7 U; V. @ f5 T j* o5 ^4 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 L6 W! k, u5 u7 @4 ` o+ x, xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 h( d9 ^3 E9 X( V; O# G5 G" N| MCASP_TX_CLKFAIL 8 @# w( k$ s2 H" C9 W* C& S9 j
| MCASP_TX_SYNCERROR
: [. @% e8 F( P; M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 ~/ j8 G- u8 k; x6 u: }
| MCASP_RX_CLKFAIL
$ i% V) G. w, @2 D, a# U; C| MCASP_RX_SYNCERROR " H1 w1 M" L9 @1 Y
| MCASP_RX_OVERRUN);
" Z# U# I+ v0 ?) J3 k0 B& m} static void I2SDataTxRxActivate(void) u- z7 X8 {7 i
{
& k* R- q, V# i/* Start the clocks */% z& t. W: s% V% q* n, o o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# R% _: g9 p! C! ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 S0 B; u, ^' p3 J6 C. t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ \1 y3 M8 E/ sEDMA3_TRIG_MODE_EVENT);
2 Q$ F Z7 K4 i5 u" ~: u! TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ E+ f$ x4 W7 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! ^( [, P. i2 N4 ^1 J+ C" Q( `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- x# a% Z7 D6 Q: Q' B' l/ K5 B/ eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 `9 X7 d- u! |4 a/ Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 {4 Z' I" t# \/ ?: f( `% _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& c* [6 |7 |- s8 p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& F4 w$ V$ q' p}
9 Y3 V$ L" ^5 E, g0 h- I2 K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 I" g" t( q: y% h' m
|