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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. @/ V3 n& E0 Y- E: _( C6 d
input mcasp_ahclkx,9 m, z3 ?- \$ J7 V. \( x
input mcasp_aclkx," Q5 T8 d, b5 f$ q/ ~4 G1 x
input axr0,
k4 G: Z9 R1 P$ b
+ n$ C: s [6 Q7 coutput mcasp_afsr,) f& B3 p& Q/ y8 Y: u
output mcasp_ahclkr,
7 }' ~* R9 z3 A4 coutput mcasp_aclkr,
4 U0 g7 w, C9 P$ Doutput axr1,
) m: a, P; j( H/ N, a assign mcasp_afsr = mcasp_afsx;
) A. Y7 S2 [' |/ Y& P3 eassign mcasp_aclkr = mcasp_aclkx;
/ Y& H0 ?. c$ c/ tassign mcasp_ahclkr = mcasp_ahclkx;% [& u4 I. G" [6 X
assign axr1 = axr0;
. B d5 a4 ~6 N* j. V+ s8 J: U5 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( v, `" v+ f9 V$ k' `' Z
static void McASPI2SConfigure(void)
3 N8 m' U% C8 W7 x( v% n" |{2 y, m* Y: _8 K. K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, T5 d; F) O. h' a8 Y1 M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- t% U' K! \( Q0 K/ I+ l9 ?* QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 X! H1 ]. K j& y- `McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' D5 W- w( n6 g# N: C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, W: C J4 I4 S; s; b; M
MCASP_RX_MODE_DMA);
4 H! Y7 W7 v; H( A v! g& ~7 n/ MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- y9 {2 K" ?7 \! g8 m0 S% \ dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% e, d! {& a5 }4 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, n) j- m) C0 B# K5 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( {3 O5 L4 \3 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 C8 {7 I5 d6 ?$ ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, F( }0 F3 }4 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ [ l) @5 ]+ M: nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 ~$ W2 n O% n# J9 a" Y, f8 \/ |" M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ ~! `# F( c2 ^0x00, 0xFF); /* configure the clock for transmitter */7 e4 Y0 ]: [: w; D( B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) Z0 h1 T6 @+ n( d2 {) OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% |7 W" J9 e$ t& a9 [+ |$ SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
^5 f# e# v( |: w0x00, 0xFF);
7 E! T6 J- \3 W1 b2 i. p
5 a" e& u$ ]& H' o" m) ?5 Z/* Enable synchronization of RX and TX sections */
# y/ s9 O% `8 XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! \1 H% N0 n. P" K) nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! o/ R* D* c8 R% e: f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
l. t3 w0 N, B, S& T8 p5 d' `** Set the serializers, Currently only one serializer is set as
; {6 |' x+ w1 n* c8 ~: v4 ?4 ?# j** transmitter and one serializer as receiver.4 |, Z D8 U) T) _1 n( w) A
*/2 }$ J& Y* {9 s4 U( }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 y* s( \! E( TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 O1 O, Q2 k, b! e5 p8 f6 ^6 Y' t
** Configure the McASP pins x' k7 W, x( g. z; G4 D" e
** Input - Frame Sync, Clock and Serializer Rx' o) x9 L: w% \
** Output - Serializer Tx is connected to the input of the codec
1 W& E. _$ H+ y" {; Y( H*/
, L. G0 t) r4 g @7 w) N5 {# d# IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; [4 ~6 O {$ o x. {1 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 m D i. H6 [0 p+ {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ _$ k; b0 ]+ h f0 w6 H| MCASP_PIN_ACLKX
- B2 ?: K/ r; b' \# X: W| MCASP_PIN_AHCLKX5 f! e6 g% \+ w& a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# z0 _4 _- q: g# b* `5 [; d; y$ LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- K! o1 o/ r+ T( S. s: Q$ T| MCASP_TX_CLKFAIL
' @* U3 l) r9 Y| MCASP_TX_SYNCERROR
' h' L, R1 h4 ^: z, y) ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% y: Y V& c! n* U4 g; @) i. || MCASP_RX_CLKFAIL6 C% S/ S) r+ _
| MCASP_RX_SYNCERROR
; q9 }4 G% ^, N| MCASP_RX_OVERRUN);6 [0 A$ }) O0 W6 V% z* x/ s
} static void I2SDataTxRxActivate(void)7 Q. @4 H/ {/ S6 ]
{
. }1 j0 L1 l4 O$ L3 m9 T( n/* Start the clocks */
4 K. U) t5 u6 D0 h7 t1 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. l1 e+ V4 D* G- e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 w; Z( d5 e- o/ n9 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; P9 \+ D& R8 Q) d. `' P8 [EDMA3_TRIG_MODE_EVENT);7 m6 h! g1 e. N. \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 d* k2 d8 U2 P! ^5 u( c7 r3 h: M7 n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
t; b6 L0 s$ O, O s1 V; N& QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- m! c& H/ C, P [. _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! ^2 G$ W. p$ U% a( X; J3 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ a% C8 T- N5 v/ B5 sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. J$ v0 W3 e2 u- l$ V3 e% |- UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! [4 {7 g' ]7 j( |6 Y}
9 H. r7 |" ]/ U# x; t k3 j5 w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 ^8 e# {9 {2 I3 n
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