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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ p F0 N; x$ t3 E" D; g! a4 l* y$ n( {
input mcasp_ahclkx,
7 V0 g' y( W% minput mcasp_aclkx,
" N: q% H# x3 j8 ~( N3 f& Xinput axr0,. b0 I; V" O% C5 j
# }3 @7 _- N# E+ U
output mcasp_afsr, m; |/ |- v4 G2 l
output mcasp_ahclkr,
- Y9 }5 f2 U+ m1 [1 i% ~1 p0 Doutput mcasp_aclkr,% ^# H# A) {0 J
output axr1,
0 ?' {4 K, {0 I assign mcasp_afsr = mcasp_afsx;
9 x! v7 ` } d! zassign mcasp_aclkr = mcasp_aclkx;$ L, E( _" S" h: B
assign mcasp_ahclkr = mcasp_ahclkx;
3 e( _0 F& h' S% Nassign axr1 = axr0; 2 O9 K, l+ E6 d0 ]; ~4 F: U" c
) z. h" r# ]& Z6 _* g7 [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # [7 q `& r. ?* J& U: P
static void McASPI2SConfigure(void)7 T+ N% q7 V: }% Z
{- C& n- ]% C, w! Z" D5 v3 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 C' N9 k2 C3 b# d8 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ J1 Z7 ~: K v5 L, e; MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) {5 h0 O7 g$ X& D1 L3 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& F9 E% S- X. p# @6 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ j# |% A' ~4 q5 E/ T7 u: gMCASP_RX_MODE_DMA);) Z/ J `- z& A( Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 l9 j/ H% h8 {/ r" b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 ^1 a- w: t/ v5 G+ jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 F$ H( [' M/ _, Q/ t: @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 O$ q+ t" n2 r4 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 p& V1 G7 y, `2 ` |3 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ |; P7 ], `+ v' R. o7 f6 lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
U/ d( v! B) D" T. jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. P j7 u+ B& X3 o, v8 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 R" _6 {/ N: J+ l0 Q# q0x00, 0xFF); /* configure the clock for transmitter */
d4 }; j. z$ T$ ^4 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 p4 l6 o' |, v0 A$ \. f# Q6 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 R& I& N1 q+ E. fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ \! v4 p B* ~& G; h; \: k
0x00, 0xFF);
% q/ ], ]) W( j* D0 m. Z Y; P, ?1 U8 r/ c9 \
/* Enable synchronization of RX and TX sections */ $ w" U6 A0 f g7 {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// P) J/ h6 ~; |6 l; r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ K8 S6 u, E4 E) A& v7 xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% G1 {8 I# O- X5 ~& f
** Set the serializers, Currently only one serializer is set as! K% y# ?: _5 [2 Q C1 M9 T
** transmitter and one serializer as receiver.
7 o5 M2 B" `/ L' T6 |*/& Y% e S: U/ X, Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 @2 i. d% a) c1 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
f4 L* |8 f8 o: G- `** Configure the McASP pins 3 d: D9 g& l) u. X/ p* I4 {3 Z2 _% y
** Input - Frame Sync, Clock and Serializer Rx2 U) Y+ ~* O/ }
** Output - Serializer Tx is connected to the input of the codec
# t x$ B. b* y7 G*/! l/ W! N8 V E) [, B# O% y, s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 s* U: q( X4 P# P% e; q, f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 n; r: J6 ?- v/ l. d x5 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 b$ p" }8 X% L| MCASP_PIN_ACLKX
7 o. T* d2 \3 |6 v" d) A8 r: q/ ?| MCASP_PIN_AHCLKX8 E' j# F( X$ }+ _- b1 z) s
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' E: ~2 [8 \$ r; _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
{. d' |( ~ @* O| MCASP_TX_CLKFAIL
9 Y; p! H3 z/ \8 R; O: \6 a# V' @: M| MCASP_TX_SYNCERROR* d+ q2 d3 j1 R: [1 B* A! E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & Z% E/ `0 `6 S9 I
| MCASP_RX_CLKFAIL; @/ U% K. |- r+ `
| MCASP_RX_SYNCERROR ( A# m: J" Y: M: ]# [8 q
| MCASP_RX_OVERRUN);, o5 ]$ g6 [/ ^3 M- X
} static void I2SDataTxRxActivate(void)* a1 d. l6 S% x6 `, u
{& Q/ M& e, C! R, P0 @3 n7 x8 \. \
/* Start the clocks */, S% t( _7 m+ \2 u8 c* e0 C7 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, T' x6 V( ?" p1 JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" l$ \" h ^" h: q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ ^4 K. z0 w; J8 V- v' d7 p0 C8 `EDMA3_TRIG_MODE_EVENT);
6 E, f% Y, [5 I+ _" C$ U' k8 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; l' s: s8 q- c8 i8 F4 I/ XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( s: E, P c) ~0 n9 S# ?" F( _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' ?* R" I3 d ~ t$ x) l4 D* X( _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! I# Q6 V6 F' N/ z9 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' Y! ? }: _. |' _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& @0 [+ Z' T8 C& Q% o" _" n8 M3 g0 q( l* dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! s0 K" U5 {! T# X0 X! [}
Y! l5 p4 r i8 G( r/ D* D/ _1 E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % Y% `9 u( N/ M u2 p/ s" R
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