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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 q+ e7 U$ S( \3 }
input mcasp_ahclkx,
8 F- Q v) I1 s6 i9 \) b/ tinput mcasp_aclkx,/ \) x5 q% U [( L) x. O) f6 j
input axr0,8 }8 F$ |6 B& w, X4 k% y" e+ B9 g
8 v' w& K+ B: X* n
output mcasp_afsr,# H/ K5 w: \% L& U
output mcasp_ahclkr,
% e j6 B% F0 M4 Z8 p8 }+ ~. }output mcasp_aclkr,
1 P h3 b8 H$ q, voutput axr1,$ K% i( z3 E6 d; a9 h' L
assign mcasp_afsr = mcasp_afsx;
+ l0 y/ @0 e1 ^$ W$ x* w: Y& `8 sassign mcasp_aclkr = mcasp_aclkx;+ G2 @& [1 {; C& ]' \* _ W; ?
assign mcasp_ahclkr = mcasp_ahclkx;
% u% X6 _; u& f; i6 Aassign axr1 = axr0; ( E/ u% D2 l* y( B& w" _
% i6 T+ W6 P. S3 y" ~+ U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * X+ Y; w8 Z* T6 }, {8 ]( p" O
static void McASPI2SConfigure(void); @3 m' y. e& D/ d, ?0 [/ y' X K
{
' y: G9 H4 [2 s& y, k# TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 w# D; L$ w. i4 @9 \' y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 t; H. @# t: x. B2 b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ _; K& t/ R! B- {2 Z: y" H9 x( vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) |/ ^8 n: z* @* yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 l* v& `4 R9 w" G' @6 t) jMCASP_RX_MODE_DMA);
1 H) h2 C6 \( ], U+ l' I9 q" SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 P; {' d5 @0 D0 p- N) aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// ~7 p, x# ?' G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% U! C8 K! A; {/ K3 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* \" w- W; d' mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 R0 |$ g; X" A: x) P% c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 i" S6 {- W" l0 U8 x/ L9 w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 r3 v2 y( }! H: JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 E2 X% x( e1 W, f& U0 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 A& M2 R4 M0 B0x00, 0xFF); /* configure the clock for transmitter */
* ^6 | m; J" D# R: g l* fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! U0 K+ o2 z7 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % H7 E$ x- ^( L& K6 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' F" C+ |. r4 G( O1 @. }0x00, 0xFF);
1 C( w' u7 e( O
7 S% Z ]/ U# P7 \# Q! v3 I+ S/* Enable synchronization of RX and TX sections */
% v. M- x) \* }6 `9 Z. N* H/ tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ F! d& j' d- }- e8 F6 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) A1 J8 c; ~, N5 S- yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 m @5 w! b# K' i4 H** Set the serializers, Currently only one serializer is set as' |" O( L* C/ v% l' w7 ]
** transmitter and one serializer as receiver.
5 d7 j" p9 P; r1 N: q2 y7 ^*/2 N- @- p: S9 ?. ~; V. H: F+ z7 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' w9 A: c, @, H0 j! K* k2 R3 M& l" V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ a: T, w7 c4 H* t% s** Configure the McASP pins " e, L/ q9 w! E! M
** Input - Frame Sync, Clock and Serializer Rx7 k# z1 c2 }& u$ P% R7 |
** Output - Serializer Tx is connected to the input of the codec ; b6 {" M2 I# ~
*/
7 [8 L5 @; b0 N5 h* Z1 u2 E$ H" tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, J2 ^& F0 L2 ~0 J# M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 S& T* G' W3 v9 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( t0 d0 b K5 {3 L9 @0 v6 H
| MCASP_PIN_ACLKX* @/ N% p& [2 Q) W+ P5 T
| MCASP_PIN_AHCLKX
/ H5 z5 c9 [4 W* W1 u# y. v9 P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; E! E3 q- B" n% q7 u9 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 K I0 S6 U' ^3 b| MCASP_TX_CLKFAIL
% h* T! H5 t& K. A| MCASP_TX_SYNCERROR
# K) ~; \* ]( o9 V9 j3 _4 p8 m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* g! p, f, ]1 |' p$ a& V| MCASP_RX_CLKFAIL7 c5 S! g0 |! W8 F: z* \' S! r$ ^
| MCASP_RX_SYNCERROR
0 V7 v* y& e( ^2 ~| MCASP_RX_OVERRUN);
; ]3 u) [) ?. b6 Q' b} static void I2SDataTxRxActivate(void)
& G/ X3 w) E9 b! b8 P4 ]; ]{$ S1 X7 V1 `' {' j
/* Start the clocks */
6 d& w! f8 \0 k. h; O! nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ j: V/ v/ w0 ^, sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 s; s, B- ]2 `" C. h) vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 `& g1 _5 V1 v- x$ b6 w" R; x
EDMA3_TRIG_MODE_EVENT);
; Y/ y5 `7 i0 m2 Y0 C. PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- Q, ?1 V- B) F$ l" G. xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# X) P7 S! N, f. VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' H+ j5 \: H* R! A8 I- J% w4 v+ P7 S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- c; F" q8 A% ^4 }* Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ i1 D; ~9 I. i% v! f' t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ ]. ]9 w2 [" l r+ T, _* u3 FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 S* t6 ]3 q, b8 p7 J# p* Z6 w}
& k- y0 V- c$ M5 A, O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # n6 u) K/ f% k% w
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