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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 Z8 {9 ]; _' e- q7 W0 S7 ]input mcasp_ahclkx,
3 ^! Y4 y) l, F* L, qinput mcasp_aclkx,* o4 D( S3 @3 @: U5 B. M
input axr0,
+ Z0 i! H& M+ S
% ^; Q! f# G7 poutput mcasp_afsr,
: Z$ I5 W2 S+ A) o* boutput mcasp_ahclkr,
9 K1 |9 e# w# X$ Poutput mcasp_aclkr,
# p3 e. ` ^# N. ]% C0 ^output axr1,
$ @9 O K- p$ `& a# u0 r assign mcasp_afsr = mcasp_afsx;
0 q/ `; {% A* C: n" v+ b0 z) Tassign mcasp_aclkr = mcasp_aclkx;+ v9 Y. G0 c7 Z0 O+ T8 J9 @
assign mcasp_ahclkr = mcasp_ahclkx;& N& F4 C* b2 F# J5 {
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, t8 |7 U8 x, \/ Gstatic void McASPI2SConfigure(void)! ]; R6 s4 a4 I w' @# r" C
{' s# N& f) d$ N! {5 d& b7 h+ E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 a+ y9 i) |8 l8 t& h- C, N2 \# E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# U X6 e' f# C% j8 G2 ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) f- B: z: R) U& W* b4 W) KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' g* A. D0 q# i" j9 @1 G: i5 w \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 c# O, N/ F' \) B4 N3 NMCASP_RX_MODE_DMA);
7 Q2 t3 E o0 e9 @% _+ S0 T+ t# yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; v1 H, ~0 P1 Q2 t$ D* `+ p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// P4 m# X' C* Y Q9 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; {0 T5 x# D( ?4 x4 B9 E" M' C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 ~3 o; h7 f& [% G. X, I) y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 F/ p; H6 K* b/ z+ HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 T0 M7 P. t$ V1 pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) a/ a# H$ c' F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 k9 _4 X$ F6 F& z4 G2 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. ?- p" m: k% d+ B/ J9 X+ l9 ]! f0x00, 0xFF); /* configure the clock for transmitter */
6 x2 R1 S+ P% b. DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! R% {3 `+ D6 W: m9 F/ d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) S6 G1 Z. o) h8 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 ?& Y/ K; o; f
0x00, 0xFF);
* x. a; C2 W- `$ q2 p% g4 q# E" _. x; ^3 Z
/* Enable synchronization of RX and TX sections */
8 I: G; \. O% XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& i% ^2 I! E) d2 g, s6 q' U5 F! {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" {/ F) }( _: l6 V% `7 V: t4 c( CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 @. j! G5 K( I5 }' @$ T8 t+ N
** Set the serializers, Currently only one serializer is set as
' i) q3 T1 ], U+ c5 @** transmitter and one serializer as receiver.
9 I6 E# {' j1 b2 F `8 Q u*/
% ^8 [2 t3 I9 v9 L: pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& P$ c- J r4 Y. x4 P4 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 `" k) l3 X' m" a( k** Configure the McASP pins
8 K* Q( t1 F+ e7 m& y** Input - Frame Sync, Clock and Serializer Rx X# Q$ Z" ~% f5 h8 K3 I; P, M; u
** Output - Serializer Tx is connected to the input of the codec
1 t5 C: d; T1 T2 Q, H( p7 B( w*/
2 Y) |% T! k) |) q. A! r# W% S$ _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- \, n7 w# w, L, H3 U* t1 D4 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' @9 |" m% o' B: ]! xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ l% |- w) {+ ~8 L. b| MCASP_PIN_ACLKX
8 V) Z' Y6 u7 L3 V% Q| MCASP_PIN_AHCLKX
9 F+ o' v% n: m( j, ~" o1 h" `: j3 m- T! G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* I, h+ I+ S4 ^0 d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 Y$ O5 e6 _; ^| MCASP_TX_CLKFAIL 7 w% t7 A. B- l* I v
| MCASP_TX_SYNCERROR; A# D- x$ @4 x& s/ ^* V+ Q4 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , y$ L# r8 ?6 y* B2 Z9 R* Q7 i
| MCASP_RX_CLKFAIL/ Z# `8 T/ G& P( I. _
| MCASP_RX_SYNCERROR
$ A& U g5 X3 Y7 I| MCASP_RX_OVERRUN);
& g+ O$ ` ?* {# j} static void I2SDataTxRxActivate(void)# b6 G. Y5 o' Y+ T; C
{
0 q' A+ u0 ~$ E: I6 S8 e/* Start the clocks */" |9 ~, D8 g/ X/ x- O4 a0 [/ A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 t+ q5 \( D% QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# L9 X' ^( ^+ H# o* J0 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# C; d: b; \% Q* g; j
EDMA3_TRIG_MODE_EVENT);( h. \9 M- f9 R1 q5 M% q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; E' r e* w( { i& @) wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 Y" c/ K) P. `$ ^, A) W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- p/ P9 }5 S7 z8 ^, j: p8 w, [. SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 b! S! l+ Y; z0 W, @& _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% i( q" o: h: _, o7 \! M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 A3 h8 ]- D3 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) s- L3 f# e) z* o' [} 6 V1 ]0 A5 `: t/ W2 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 R! {! U, _' t) s: \
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