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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 W4 O3 ]: |$ U& D( G) H: Dinput mcasp_ahclkx,
4 V; I, Y/ G! \1 s" Qinput mcasp_aclkx,# s2 B+ x m$ E7 L
input axr0,
5 m" p8 G8 R) e8 U
. [& B: X: p' S* k' boutput mcasp_afsr,& _" {) h. f" @- L2 ~8 L( _, e3 A
output mcasp_ahclkr,
7 `5 n. j7 R6 h @output mcasp_aclkr,
+ R% s! {- Q r! w$ f' r% S0 R: koutput axr1,
4 C1 [* t- d5 Z9 H& i; v2 o assign mcasp_afsr = mcasp_afsx;5 k9 c/ `9 Z/ G7 t
assign mcasp_aclkr = mcasp_aclkx;
0 ~- Z# y$ Q# L, m) ]3 ^- e2 Dassign mcasp_ahclkr = mcasp_ahclkx;
+ z9 q5 L# {0 v5 l% Gassign axr1 = axr0;
" ^3 \& n: o. X. M. n; _2 p) V9 i0 C2 d4 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# Y* `- t- x/ G! t) t5 _% cstatic void McASPI2SConfigure(void)3 Q! @8 C. D- [( K
{
) Y a, M4 N# m# [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! L% F. R5 @5 ?0 [- QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 |0 `! `/ \+ D2 g! w6 R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. @ `7 }$ H6 R0 y8 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' t4 n7 d; t* `5 x; H! h5 k+ Z6 J$ L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% v7 ]; N+ k! a7 e7 `' l& }& h' e! BMCASP_RX_MODE_DMA);; ~) W/ i/ O& Y3 ^3 `& i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ N, I7 h- }- N6 ]" x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ C4 m& O p- U& @( c0 D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% z) I9 S2 N$ @- c( f/ jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ v7 {6 C) H+ k$ H5 d( x3 GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: b8 C( I( ?9 j! ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% m$ L% p1 @2 ^# [& Z: p: w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ g, I" T) o8 V8 r; d2 Q# aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. \2 e( V4 h. u0 n# NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, V, C. y' c2 ^9 N) p" j- L
0x00, 0xFF); /* configure the clock for transmitter */
9 U! l7 u8 K3 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
r" j- l) Y3 f! H7 B% nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 c- K6 W: T H1 S: ]& b- p; A/ e/ `) r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 k4 c5 x' j4 C6 P6 }( m0x00, 0xFF);
9 y1 C% i! Z' L4 x
2 i" t- X% Q# p. s/* Enable synchronization of RX and TX sections */
, m8 B5 }0 i& e+ }' r( oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, ^) g c5 z- \7 X7 J" J% u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. U/ e _6 r$ L6 m4 Z4 |$ \/ v* u& sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 \( ~3 y. }! o5 B' J
** Set the serializers, Currently only one serializer is set as& O4 P4 R" A, g
** transmitter and one serializer as receiver.' R8 _2 n, u; b/ w7 d8 W* \
*/
' x: e9 m8 n. Y+ Z/ @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# X' _* G6 j* z% j4 e6 W- K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ C" G: Y( w k# `** Configure the McASP pins / @3 F7 \& ^# y; @: E2 b
** Input - Frame Sync, Clock and Serializer Rx( M* p: ~; ?! J, f
** Output - Serializer Tx is connected to the input of the codec
/ g1 A' H1 e$ r( g U1 d*/- t% S4 _' X# |- G8 Y9 `' m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
K7 R1 B8 k3 K8 ^( v2 {4 X' NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# P+ ?; B' F) \. bMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX X# A: Z# R" |. E
| MCASP_PIN_ACLKX
' |7 `% q9 `8 z) Z- x1 G| MCASP_PIN_AHCLKX
- }: ?( G" V( A. e! A& p' z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( g) x( W A7 ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& \$ Y6 T; V& B; C| MCASP_TX_CLKFAIL
+ a4 V1 L% n3 n| MCASP_TX_SYNCERROR
6 o3 r/ ~1 w2 S: @7 v3 ^+ F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; T! Z. h: r* i: Z, {
| MCASP_RX_CLKFAIL0 S! R2 X; u6 g: c) q, a- s/ U" y
| MCASP_RX_SYNCERROR 8 n: _* Q6 h0 B4 _: @
| MCASP_RX_OVERRUN);' T( D! x7 K* r0 t. ?3 ?
} static void I2SDataTxRxActivate(void)
" ?8 B7 C5 \7 V{1 d: H; b! ~! }% c9 E$ \3 F% c9 F) _
/* Start the clocks */8 F% W* y8 n* g1 O# g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 f- l0 {% S; q& z, P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 j4 {, T; R+ i2 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# Y9 c+ g- Z. [( V
EDMA3_TRIG_MODE_EVENT);
1 b+ ^+ z! E' s7 d/ t. @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 g" y# T- Q9 J$ h: PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- O, W& W4 X! k3 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 S1 t S3 W* N* x) `/ ]. Z# x" LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 Z' Z; j0 J5 w; X4 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 H5 N4 A' g9 C1 XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 L c1 |7 N/ }2 _7 E- ^( F2 F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ A% M8 A* {6 z( C/ s& }}
9 n. O4 ?2 u' e7 j; ]6 U: }; T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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