MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
6 R& I0 G, L$ m) |$ u( e" P" w/ oinput mcasp_ahclkx,
" Y/ f) R1 X( Q! @$ f: Ainput mcasp_aclkx,
input axr0,
, ?# N! m+ v5 D" w0 Q7 Q: L$ A6 L8 k
$ D; L6 T; }' s; P+ I, moutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
8 W' e) V9 d# B# }" aoutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
# e) Y$ ^6 W2 R! d# v  d2 uassign mcasp_ahclkr = mcasp_ahclkx;
) G6 x; I! N6 ?& E7 }8 h) passign axr1 = axr0;

6 D# W: ]' S& @  J0 N' g  x4 a
4 X4 i8 z' {$ M0 ^

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

4 W2 T* W. m* b/ g; q; P

static void McASPI2SConfigure(void)
, Y2 R% L9 F4 R6 e{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! v# T2 e" i3 X% b3 O8 u& X; RMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' j. @' b8 M# e) h. {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* G7 k# J. V) X3 s7 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, u/ }2 o' O/ ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 X  A0 C' n$ `* IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' p4 C8 u* l6 i& V; Q+ Q+ nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ }5 \4 S5 `# {$ r' t( IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 g: t5 C' O2 M% }1 z- ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 d! i- _1 W' t! iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

7 d/ o* G$ x! B8 a" l" b/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ Y! L" z2 P0 q4 J: Y+ CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
/ S9 |- \2 ^5 p2 l0 m2 h$ T! J*/
& C, E; c# ?/ P( I2 \+ q7 jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
( Q( Y  L, v, ^4 p** Output - Serializer Tx is connected to the input of the codec
  P" k3 r' z& o; M8 D*/
/ ?4 i# u" i3 `  `  z8 C! }7 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, z$ V. u2 {& ]/ P$ X8 d| MCASP_PIN_ACLKX
9 |/ X. q( I+ N( x4 m| MCASP_PIN_AHCLKX
' M  |6 P! q0 N: [' o| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
/ U6 f4 ~9 p  w8 _. P- I# ~% o7 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
+ K5 \# p! M, T8 G! o  A# w/ f| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# {& B# T. n; ?: [0 L! u: }4 d| MCASP_RX_CLKFAIL
  v2 I- `9 [# d# F+ s5 }| MCASP_RX_SYNCERROR
/ K/ l1 p* q, b# j4 v* F! \5 || MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
! ^0 U% v1 w9 m( W: A) l1 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
. t% B- K) A! P- U/ x% r8 t$ \$ E/ F! I( @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ X0 ?, W/ W" \6 m# T; z9 X' i. c& MEDMA3_TRIG_MODE_EVENT);
5 ^' J# u8 R+ [; uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' u5 f0 o+ p8 fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
; |& H9 }& @. y! w& H) \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, P- q8 h0 J5 C5 m4 k& ?, j! dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; P$ Q+ S# `# ~- A- ^" ~}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

; V9 h) z1 a  f# S( [