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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 M9 N9 h, G4 L9 ^input mcasp_ahclkx,
9 f: y$ [2 G9 m' | Zinput mcasp_aclkx,
3 i1 h# T7 [; s uinput axr0,) L: h! e$ u ~/ @( e0 j
$ U+ N& b2 Y# B. eoutput mcasp_afsr,' Z5 k- B. w C3 B/ J" p
output mcasp_ahclkr,; l1 S) p6 E2 G( d& h
output mcasp_aclkr,$ @$ ~. s5 Y' H
output axr1,
1 }7 h2 N- I! z# ?% F' l assign mcasp_afsr = mcasp_afsx;3 p- T! g, q# q/ K1 \
assign mcasp_aclkr = mcasp_aclkx;
# ^8 ?! l& y6 Qassign mcasp_ahclkr = mcasp_ahclkx;
% t$ [2 A7 T" A1 K) passign axr1 = axr0; , V) |% {* S% Q! v
' @& }- g4 H) R3 E" X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # l8 ]3 {0 c' I4 j6 T
static void McASPI2SConfigure(void)
( R; E- K/ D1 m5 @; k- n' f0 I{+ Y- `. d1 @+ t' l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 s5 u. T. H4 H& M5 u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* Z2 d/ I0 w: e5 j- D4 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 u; O6 W1 f3 J0 x% Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 ~) y* i0 \$ E" Q0 H! ?5 h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, e$ I8 N/ X( z0 b. G; A m3 EMCASP_RX_MODE_DMA);, J! C9 p! M( m) Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
d+ P; o, u5 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
o) q0 k6 O, y& z( Z, u7 ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! Z+ A9 ^$ _* ]+ x% FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 ^5 [3 k1 E+ y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 @$ L1 L3 I/ Z4 C+ t5 N. u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% o& a( Y! y' Y) E4 Q; R; n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, q0 _' y5 H Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 o( T0 v# z* H4 G8 j) E7 K% VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- q: r# O$ }& v3 z
0x00, 0xFF); /* configure the clock for transmitter */
) D# Z+ I0 ~+ LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ f2 v; T8 q7 m Y! o; n7 t. gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- A/ J# v4 Y* _: tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! l0 W( s4 D2 u) q, t0x00, 0xFF);: V3 e( G: U$ t6 L- g2 V
/ C u9 W3 W- v& d' o
/* Enable synchronization of RX and TX sections */ 8 _6 W6 U& }& a3 ?" b, Z4 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& L4 e/ |6 `( A7 p; m$ T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% Z& y4 x6 K' J, ^, M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& _+ L* C! r5 T* Q8 `& \+ J
** Set the serializers, Currently only one serializer is set as& `$ U% e& M9 l7 L
** transmitter and one serializer as receiver.( @+ o) u# J' k& _+ w5 }: [
*/7 b, \ O# Z: Q2 }1 u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- q8 A) o( i# {! W8 g- P! @/ i u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* [: Z8 O; L3 _6 y& E0 \" O; o** Configure the McASP pins Z7 G; G3 w+ d8 N' r
** Input - Frame Sync, Clock and Serializer Rx
/ j6 {# U9 Y7 G, d, ~; n** Output - Serializer Tx is connected to the input of the codec
9 b9 D7 ~$ A6 _9 E1 f" W, \) ^*/) `: u2 b' D L9 O6 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; m" @4 q6 F: U. h+ J# M) IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
K% o5 C0 x6 z, X- `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% E8 ]6 r4 C" h- t! a' l P$ C| MCASP_PIN_ACLKX" N) i, l2 J/ c. e/ I6 |6 S
| MCASP_PIN_AHCLKX
/ k4 _ j% J+ K; w$ c( w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ a$ l( {+ F" g/ L+ i% q, ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 r* k) j z# w: h+ E
| MCASP_TX_CLKFAIL . x( e5 u+ L5 Y. G
| MCASP_TX_SYNCERROR
X' v- \; r; Y- v5 x: f$ ]- w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 ~& {, H3 i1 n
| MCASP_RX_CLKFAIL
, U/ }2 m1 K* T# u8 I. H| MCASP_RX_SYNCERROR
5 G" D9 |- g |* W, \/ j) j! h$ j$ f| MCASP_RX_OVERRUN);' z% C% a4 x) D
} static void I2SDataTxRxActivate(void)
" ~- ]' v; m! o{
5 x* a9 e# ~$ D, K: h$ ^3 o- [/* Start the clocks */3 i* G+ S; b; \ R" d* W+ J3 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; ]& Y( H S0 ]& e. D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) g6 v2 i# J" a% E( bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- m8 ]& A3 C! @( ]3 v
EDMA3_TRIG_MODE_EVENT);
/ S& ~ w7 F- WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( Z: f& u: r, W$ r& W' `% N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% N9 |5 R. U: g3 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 f/ ~4 D ~3 b7 W5 Y' r( f3 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" C3 y" N* c/ F3 j- M) e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 r) b4 ^8 O2 l' l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. J0 X! E. k; [) O' A7 E# a! X) x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' W3 C8 A1 v3 n1 ?" j}
, u n$ q2 G j/ ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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