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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' q0 J: N, x5 ]8 h# Kinput mcasp_ahclkx,8 x4 F+ }, A; z6 V: \" H- g/ V
input mcasp_aclkx,
* W7 }; X7 {' j& N4 i" m7 l. Yinput axr0,3 q0 c8 ^! g6 X$ Z( V
3 E( H4 l& t. K9 ~
output mcasp_afsr,0 N" D( a! t- V+ B) D1 P+ d
output mcasp_ahclkr,# e( [4 J: p6 z
output mcasp_aclkr,* u. H. r: [) v" n
output axr1,
0 ^; z: W! K0 K assign mcasp_afsr = mcasp_afsx;
* n* ~8 m- u- |; Yassign mcasp_aclkr = mcasp_aclkx;
: V9 Z2 B( `& `; A, L- Passign mcasp_ahclkr = mcasp_ahclkx;' E* o4 R. T9 H4 [4 G4 y
assign axr1 = axr0;
. G) i; I9 L+ O& D8 [- Q* L5 E' g( a: {; l$ |. K/ I( p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 I! e7 b$ o! P& o7 r' z; ^/ b: Hstatic void McASPI2SConfigure(void)6 T' L( ^ t9 e1 K# X& G/ n2 v1 [( @* ]
{ z! X: o6 o/ I* Q5 H7 i+ j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ R$ Z0 K" J; QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 _$ a: b5 j" i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 B* \$ d! X4 k/ p1 V: d" yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ r; [# C* E4 C7 D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 D, g4 U" l; q! b1 r. a4 x& K
MCASP_RX_MODE_DMA);
8 v' T9 z& C2 B7 G6 s; o" m9 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ i0 `( j+ }; A: D9 u+ C& CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 r* N* x0 `2 u) p- w: N: l8 TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* o9 J$ ]5 l4 M Y# y1 D; DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: N8 [' t7 ]7 r' v, C, u' vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! R F3 ~1 E/ b& } g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" B+ U, V; O6 N" Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 a6 t$ C" C; Q, uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # v# Q; y; k* L( c% A" Z. P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) x: k- m2 d# I e, H A T0x00, 0xFF); /* configure the clock for transmitter */
2 b9 ]6 A' m; R% u& g# ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 e& B8 H; S6 Z8 g1 {, t8 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 p* X: ^0 E# [6 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 r( G; s5 a |1 f8 @: g# Y2 r3 @0x00, 0xFF);* Q3 `8 M/ P) @% |+ x
) ^3 b( U" u9 ~
/* Enable synchronization of RX and TX sections */
' _ q0 {- ]% L9 h4 B9 |! {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ K" L% c9 b6 a, ]# v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' J1 u) w7 v( S5 L# }, QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, K( _+ w y/ _** Set the serializers, Currently only one serializer is set as# p' t+ _6 H+ S7 [* E7 g9 Q
** transmitter and one serializer as receiver.2 X' @4 G4 h$ P9 k" M
*/+ A: h0 b; M0 G3 }$ F: I0 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 L8 `7 G4 U/ R" A* \0 DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 C( K! M: G$ I8 U
** Configure the McASP pins
2 G' D7 c- O6 O2 h** Input - Frame Sync, Clock and Serializer Rx
3 L3 t- {( B& b# n) M; ~** Output - Serializer Tx is connected to the input of the codec
5 j4 d: u% d; K: d*/: O: c- V% f5 G- q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 c7 g$ j; ]$ X3 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 J, n5 Q! J: \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: m8 q1 f1 \* i/ `2 i
| MCASP_PIN_ACLKX! u: O8 a9 Z# o! c% M* Y9 E/ @& H1 b
| MCASP_PIN_AHCLKX
7 o5 U+ C# _0 {1 i; P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( m* g0 E; f. {' t' p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! p/ V! |+ C% \7 S| MCASP_TX_CLKFAIL
! A6 g2 } W5 A& q: t v| MCASP_TX_SYNCERROR. g0 E9 T9 G' Q' O5 j( l2 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; j+ C. A. o( S| MCASP_RX_CLKFAIL7 S# y4 J i) n0 Z: K: V
| MCASP_RX_SYNCERROR 8 p; i; H5 X$ l! g9 N4 d! q. p
| MCASP_RX_OVERRUN);" B, D' t" f" ~3 w4 m$ c
} static void I2SDataTxRxActivate(void)' z. r- b, b( S' `/ L$ u
{
! O8 K( n4 Z3 ~$ J a/* Start the clocks */% c$ k) x7 r( w8 h2 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: I6 H& _/ v1 d" a" Y# nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" I! h) h- F( R' I$ b7 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 a* v% P9 C: u$ l$ p! b8 a3 \0 vEDMA3_TRIG_MODE_EVENT);$ q/ c& [( h8 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 n: X: `% R/ K! r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, n+ V$ p) A8 N+ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' S. v3 C8 N2 x/ r" s, jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 m# v% V3 q, @3 W# p! ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 y5 p( D( q! `; m! t/ u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. F9 w5 J% F: z8 X( }8 _$ I n1 nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! ]4 @& n# J" l3 }! k6 h
} + h6 l3 @/ F4 C" z) b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & s0 S4 [$ g3 i2 G
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