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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% G+ ^! ^& _3 S' A3 o3 l( D- i
input mcasp_ahclkx,
- E! s2 q6 f1 F1 Cinput mcasp_aclkx,
5 H( u* u/ m0 `input axr0,
( C+ L3 Y/ ?: ]0 l+ A
6 P8 U3 C# @* B+ Aoutput mcasp_afsr,: T$ v, j3 B1 Y6 W- h/ l
output mcasp_ahclkr,
* E) N3 U# q. x" j, L+ soutput mcasp_aclkr,
4 G/ m) d0 z# v- Ioutput axr1,
+ g5 y! M5 ?8 K( C assign mcasp_afsr = mcasp_afsx;, z) x9 M" e8 n* L- z
assign mcasp_aclkr = mcasp_aclkx;' n* q0 e7 J/ B) M
assign mcasp_ahclkr = mcasp_ahclkx;4 |4 b& F- ?. }$ i7 }/ F2 \, o" m
assign axr1 = axr0; [0 u% U2 l2 C1 y5 H& g! o& A
* _8 c' t2 b" N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : [/ I; H% R' j
static void McASPI2SConfigure(void)
! w3 m; w; b6 S. U' w5 w7 H8 M* o{
/ Q6 m2 a! O' Y- G3 M4 kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' }8 s+ w) S7 I& ~1 G/ u, v- iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" s' o* Z; i) [: IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 a; E3 y, f6 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) |2 i% M) V( u* B, S5 q" K" tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; z( L8 _7 e/ ?
MCASP_RX_MODE_DMA);" p. G' f6 k& }7 i7 _4 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' ~" _& r/ k( C2 F3 h6 WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# I. L& D$ t) R/ u, R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : h. ]# i; M# {8 u1 X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" x7 s" l: o0 Z+ M& p9 a) C/ U4 W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& O" u- s+ a4 m dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 \* ]8 s, Z& A% J/ l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 t9 J8 Q$ J4 ]2 U& ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , H! `4 u- P! g/ G* ~. i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ~% D& } F& C2 ^2 `+ N2 o9 ~5 }
0x00, 0xFF); /* configure the clock for transmitter */6 z' i6 ]: ~: f( E" ^4 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" T6 Q8 A, Y7 m2 L; T5 ^: J* A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- h8 r, j/ ?+ ?! Q" h \% V1 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# c: l3 W% g% k: n0 q, o- r! v
0x00, 0xFF);
4 P0 j8 d1 O6 p1 G
" V! Q. }3 M. X$ v* `; @/* Enable synchronization of RX and TX sections */ ; t& U# }- S6 K0 ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" I. D" w' ` s9 Q6 y2 G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 W8 d6 O' I9 J/ nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% m: H3 x5 t6 L' a2 s$ x
** Set the serializers, Currently only one serializer is set as
4 H2 Q9 { n! e* d7 k1 d( Y9 H- T** transmitter and one serializer as receiver.
2 y' I) y4 p8 K- ?! s*/
@! F6 K0 Z# |& Z5 u7 J9 i4 C- RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" Y$ n, o0 ]; ~. B! s nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# ^) L* O- `3 }4 O2 Y( e/ ]3 F0 T. R
** Configure the McASP pins & K- d3 R5 f5 l5 B* l" a
** Input - Frame Sync, Clock and Serializer Rx3 }, X) s/ B; m( A6 R
** Output - Serializer Tx is connected to the input of the codec 8 p( M" U. _( l- c5 L
*/
$ k$ y L: ]3 y: k3 Y8 G, X6 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 C5 z2 ]9 O9 {# J6 y7 ?% kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ z, ~ @ r: z$ y2 k& l: l2 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 t' t5 R: d* ^( N
| MCASP_PIN_ACLKX
1 p$ Z8 A% w9 L" P$ h; H3 J) s; ?| MCASP_PIN_AHCLKX
' B7 J) |5 t: U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 i& k& M1 r; i/ z6 b6 Y& g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 P- N2 c+ d, T) U# ^- z
| MCASP_TX_CLKFAIL 3 O5 R8 \: I8 k; R1 a! \% i
| MCASP_TX_SYNCERROR
& B: |# P4 m0 x/ n1 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! A. X4 @3 d, ?1 e1 n# B
| MCASP_RX_CLKFAIL' M) ~. p# D% Z9 {2 U
| MCASP_RX_SYNCERROR
5 e3 u; @5 K% ?& K% e% ]| MCASP_RX_OVERRUN);! R- s' _1 g: A5 E" S
} static void I2SDataTxRxActivate(void)0 _$ L2 \& ~. D# U9 L. u: \
{
1 o% H7 s( W0 L% A6 j: @/* Start the clocks */4 Y, f* i! I4 P2 [: Y7 [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# C2 q0 y( M& @/ k( m' E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ b: A: F5 z9 p( }( g. VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 @6 P$ }0 M7 m
EDMA3_TRIG_MODE_EVENT);
7 J$ y* E$ L2 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: H. W1 j* t' JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 e, @! Z( H' K' b$ w- A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. o6 h1 x4 X+ I& x7 |. l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 q- h; x. E, J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. J5 m$ {; q) J/ d3 D+ d5 n1 x3 d) DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ g* t; r' X1 [+ s/ A3 j$ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 z) v, F3 q- [% j# U} * b8 X7 a3 ?; `# Q7 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ~+ W9 P7 t0 q: a# i) c6 Q
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