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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 v) t, w% ? }; E, h
input mcasp_ahclkx,
* c4 M' L$ f+ }* {! r1 N7 Yinput mcasp_aclkx,* D I; u3 E& X- |' B4 x3 [
input axr0," R! z5 j `# S9 Y
" n9 ~* N( L" D9 L
output mcasp_afsr,
- K1 d. m5 u7 `3 [) d6 G3 E1 aoutput mcasp_ahclkr,
, j: _- }0 Y7 z/ C# `output mcasp_aclkr, ^, _7 }" ?% D& G/ a( b a
output axr1,+ s8 _& Q8 H% i$ {9 G$ p9 O, x
assign mcasp_afsr = mcasp_afsx;& Y* r2 O; j6 Q N$ }9 h
assign mcasp_aclkr = mcasp_aclkx;3 c- K, V# @3 R, }! w0 V
assign mcasp_ahclkr = mcasp_ahclkx;* ^6 ` ]! P, D$ z' f
assign axr1 = axr0; 2 e4 T% a0 m7 P' }. `- n- Y( Q" b
# W% x7 q# y+ w7 F- a4 J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* x9 ?& K! w8 ~2 V( y8 ^: {static void McASPI2SConfigure(void)
- F9 c* W% {5 F% s$ D{
) Z, j; e, S) {( l$ N- cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# {& g ?9 U$ Q1 X M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) v$ X V6 K- l$ S# h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ K/ e4 W8 t* Y' t$ ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 [, M1 R8 a6 C' y( I' C; t YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 o v/ j. d) N# }2 c7 AMCASP_RX_MODE_DMA);2 f# ?$ ]! |) H' M, X: J' L( z& o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 [; J" ?- d9 Z) ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 F) e6 m8 [( d! A* O/ e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& z: D3 d' Y: c4 p' L. |& WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 \9 l& d% R& M H% f) |) @; r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 y' @3 W( e7 O' A+ [' B0 c9 U: v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ s! ]2 v! u& x# kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 R# a" Y. u" W. }" wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, b8 V6 R" u! t2 e! p5 O, s* c4 qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: L( |! S% V' X T! I" P0x00, 0xFF); /* configure the clock for transmitter */9 A1 Z5 s% x) T6 d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ Q, Q) p6 g' O) u% O: G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 A9 G4 W" I1 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 M3 D$ D3 M: _% Y
0x00, 0xFF);7 q6 |5 M, a, a9 I8 Z0 d
, L3 ?6 u; x2 p) o& C S
/* Enable synchronization of RX and TX sections */ # v! _# m# W" m' X( f" M8 ^2 E$ u& D0 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ T4 R9 X. z# q+ BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( `; e, u; r8 Q7 U* h c3 ]' q: aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) @% z+ h3 p/ J: s** Set the serializers, Currently only one serializer is set as
; j0 U. u3 o) R4 r) J** transmitter and one serializer as receiver.
5 q! Q* {9 Y: Q0 H6 r7 w*/8 t B6 o, u k+ F5 h; [, s8 q/ p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 {+ E0 q& |& TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
y) j6 F- b6 `1 O) \** Configure the McASP pins 4 u# a+ ?+ S$ [2 j% ]' a
** Input - Frame Sync, Clock and Serializer Rx
8 s7 K0 T9 p5 a7 @) y% |! i** Output - Serializer Tx is connected to the input of the codec
, U5 G1 F( `9 `*/" c$ n9 [' n. N' P; v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 q/ Y( Y& v8 x6 R, H% ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) q3 X, {, J8 r; c$ KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 d) J# S% T4 X; }) ~) U3 I
| MCASP_PIN_ACLKX4 s& ]( i5 O$ [' }& D" r/ b/ N
| MCASP_PIN_AHCLKX
, K ]" f& k0 ~8 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% h/ r5 q7 n; w1 j& K3 E4 Y0 q5 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) D" s1 H4 w( v5 |9 i
| MCASP_TX_CLKFAIL . J1 s2 _6 k* ~2 A5 K
| MCASP_TX_SYNCERROR
4 r8 X n) L" P$ Z# a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - k- G' O& p+ ~7 F& d ]
| MCASP_RX_CLKFAIL
+ c& |2 U6 F2 Z8 d6 R; [3 X- a+ T| MCASP_RX_SYNCERROR : y1 ^" h4 m8 |7 ]4 A
| MCASP_RX_OVERRUN);+ u3 Z6 \4 @- a2 [
} static void I2SDataTxRxActivate(void)) j3 G6 R$ G2 G# G( u/ g# I) g
{
; |' K' P; c, H8 ~4 P/* Start the clocks */6 K# n' v6 Z5 f$ n- Q: d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 i9 m) @6 _* V- O4 {, P8 _: f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% n& s( K0 A. m6 D1 x* FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 a# _3 O1 O' h; |
EDMA3_TRIG_MODE_EVENT);
/ o9 b. S1 j! B$ L, h/ X) dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 G5 U2 S% W s5 M3 d+ O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- a: `1 J; e& I- S7 i) U8 VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# S7 F3 h/ E' ` P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( H6 l( |+ ^9 {8 g& j* I6 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. v; F& ^# e+ i/ p" h' I; lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);' m- M+ f3 z+ z$ r
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 J& y3 m; C+ R S
}
/ {: }6 U/ h+ r, k7 |# W0 y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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