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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. Q9 w$ n. `7 }$ N
input mcasp_ahclkx,& ~# Z) Z: g1 x$ i
input mcasp_aclkx,3 }3 {; V5 z# h8 q8 u; T B$ x. s
input axr0,
4 a/ d, v r: l; I' }& e$ j" V
& n8 G Q. G; s6 f4 woutput mcasp_afsr,
' m. _" d T! a- |' toutput mcasp_ahclkr,
# b* i y/ T5 J! H( r( h. Qoutput mcasp_aclkr,6 E: J8 K ]+ D( ]9 j
output axr1, D# [) Z) }5 O$ A
assign mcasp_afsr = mcasp_afsx;
4 J& Y$ o4 I( B) \1 R1 f0 f) nassign mcasp_aclkr = mcasp_aclkx; @8 l2 }6 B" r- ~) Y* |
assign mcasp_ahclkr = mcasp_ahclkx;
; ?* }$ |. c. h8 yassign axr1 = axr0;
# O4 _' T( i1 X7 h! x" ^
1 `7 D7 Y# d1 i; F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, N% E( _9 ?. l. ]. G1 Mstatic void McASPI2SConfigure(void)& P4 A/ r! b. F" V1 C6 v8 A
{
( j0 I! l: g# PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) U. F& _8 H/ m" h( ]: x" `; xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& p4 F4 T& x- Z) I: AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* l+ Y4 A% \5 z, QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 A( e: o# ~1 N0 y1 \" H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* d8 F0 D$ ~! s# ], K' d) VMCASP_RX_MODE_DMA);
2 F; ^; n2 K HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
d4 B& ~& ?+ }( t: b2 Y; gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! J7 t" b' y/ l7 |8 U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 v' a$ D& E8 P) ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ O: a. P; W- @! C- W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & ]; H ?7 P2 `! c1 Z" t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ Q; z$ e2 {/ y9 U) ~% ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) e% ~- y, [: P7 k9 V! t; m- {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- W/ X+ [: a0 }. M- NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. {/ o6 k4 ~8 j' h p7 \0x00, 0xFF); /* configure the clock for transmitter */
0 t, j+ B2 _8 U' u7 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. t+ H6 p/ Y8 H$ R( |$ V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% ]& g! s$ I# E; ]* rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; w: z1 P0 d- N' ^
0x00, 0xFF);
b8 `6 `" r5 u( @5 W4 A+ V" ]
6 ?% m& w$ }5 b: j/* Enable synchronization of RX and TX sections */ : v/ G9 M9 X0 T; _1 i& W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 s/ o: L+ f8 O) H5 E0 S$ _. J5 w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 ]( b- W8 k9 \: g. _9 g: Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 v7 j: B: v/ w** Set the serializers, Currently only one serializer is set as2 f" ?# j. y2 E& v3 c. V
** transmitter and one serializer as receiver.
% i, R* _8 ^) E# n n8 i: X*/
% H! O5 S% f# s" a0 Z C7 L0 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 ]5 D9 e! z/ W5 T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& Y5 q1 q C/ A7 G. p- [5 H" ?% o** Configure the McASP pins 5 Z2 j- p; o5 l! p4 s/ t A; s
** Input - Frame Sync, Clock and Serializer Rx
' J8 a2 r. |/ H) @, q7 w4 K** Output - Serializer Tx is connected to the input of the codec ( @1 O# D7 {$ @" c( I
*/
' z( B# ?& u9 Y- UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 K& ~6 T& _% P; l# o& u% X _6 j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- T: N$ w8 x( u* [1 y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( n' E# n. T* x7 x$ k8 B% g( W
| MCASP_PIN_ACLKX
1 b" X8 t5 O6 o" V| MCASP_PIN_AHCLKX. g' X+ p. G- T3 d% {/ b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 t* R( I- [/ v/ p' \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 f7 {9 L) d- t8 D5 p| MCASP_TX_CLKFAIL
5 U9 ^- G( X) p9 {7 Y2 B. f| MCASP_TX_SYNCERROR
( ^2 U8 a5 k l; ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% g0 v8 h1 Q+ X1 H* e: H$ I: ?| MCASP_RX_CLKFAIL
( I, C8 j8 M) R: O S& }| MCASP_RX_SYNCERROR $ y6 N+ b, w2 u
| MCASP_RX_OVERRUN);
1 U3 }9 t) q o2 R' `} static void I2SDataTxRxActivate(void)
4 I1 v5 n# @/ Z# G{
7 q5 O# R: u# o/* Start the clocks */
- P4 e# p% y+ P1 v L, u2 a1 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; p$ m) A) m* a6 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 M$ S: |1 k! d8 Q( U) i3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# \1 M @& ^" `/ C' d) x2 aEDMA3_TRIG_MODE_EVENT);
' I0 p. @* p; m+ gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 B \1 o& q8 ]/ q) T" {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# U6 O9 {: P0 \4 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- A& z8 Z9 M/ G% ?) b7 E; |0 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, e' t8 B# a: J. I5 j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 Q# _& I: ?( V, U& F5 W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# @7 |+ X) {% Y; u9 B9 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 e) ]: f' a" a# l% R5 t' T} I/ B4 v* f4 }; J# c! |, x) _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : Q" S. m4 L. t2 z; ~% ~9 B8 \
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