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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 T2 f# ^1 R4 r$ A X: b' s
input mcasp_ahclkx,
) o3 S0 G8 E: H9 jinput mcasp_aclkx,
' R8 X: p1 ]5 I2 linput axr0,/ A& T; F) _- c& U: w0 u- X
- W+ i9 x& {. n1 Poutput mcasp_afsr,# a& t. N0 Y8 L4 l2 I/ o$ G
output mcasp_ahclkr,
! r( {1 l% H- J* joutput mcasp_aclkr,! {* r( v" R% K" D# s$ Q% l
output axr1,4 ^" \# r( j& ?, |5 G4 y# D
assign mcasp_afsr = mcasp_afsx;
- i: Y) c& A! }: X. x% Yassign mcasp_aclkr = mcasp_aclkx;
5 v7 r3 M& z% `. Sassign mcasp_ahclkr = mcasp_ahclkx;% Z* ~2 L I2 j! A& e$ m3 ~: |
assign axr1 = axr0;
4 f% m; B( {7 t* d t+ E+ ?3 ^+ z5 o7 Y# d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! M% @, s6 S. `6 j+ m
static void McASPI2SConfigure(void)* V+ D& B# H' W) {
{
% T$ S: N: k0 m3 D; k! ^! W' AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' u* H0 ?. A. d/ B8 K' \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 |1 q1 M6 h/ t X8 v) Y* a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# t* k) g# v B/ Y5 j6 \( a! m% gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! G- M* ^* T2 QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ?* U0 K1 z3 }3 r+ G* d- ?MCASP_RX_MODE_DMA);
$ R: W5 L& k& H5 ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 l$ O$ E/ o* o: D, @% R6 G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* X; r% {2 |: u$ x4 X& L2 E# S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 S$ l/ r4 |' TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 |* K0 Z, P$ E6 i# c, g1 L: C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 T& r1 h$ o. I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 `' N! ]9 c$ Y: z- p bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 r/ c) \' F% k4 k# E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 i4 | e. Z, q: A2 s: s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 ?6 C) R- j# U; z' }6 f. P- H E0x00, 0xFF); /* configure the clock for transmitter */6 ? L v/ F) A/ d {, ^+ I3 N4 `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& e, ^. A- ?, S9 fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % l1 s% Q1 E, m! u5 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* d6 m R9 {5 P7 a, D& i
0x00, 0xFF);; q+ V! g7 F) t: G) J7 B* [
+ ]! q0 w: M0 E1 f* Y1 e0 V/* Enable synchronization of RX and TX sections */ $ @/ s w: p$ `0 v" Y/ M2 Z3 E3 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. ?, a% k8 s3 m0 P: \2 M9 P6 j9 L4 F+ I. ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% }* h7 B( Y' Z( D! EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: n( \0 r3 s% h
** Set the serializers, Currently only one serializer is set as: f9 U# X& t6 b" i: r* E
** transmitter and one serializer as receiver.% ~+ a4 K% k7 S: Y- A8 M4 L7 Q' o
*/
7 t9 j% p3 P; j- E' U9 E+ n bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, C* V% C" S; ^8 C* WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 H9 ^7 u9 M; M, l" X7 M& y** Configure the McASP pins
* e* T9 l3 D( A** Input - Frame Sync, Clock and Serializer Rx7 n+ ?, y6 T" b
** Output - Serializer Tx is connected to the input of the codec
1 B5 a: R( ~: D0 c*/0 G( {5 K- {- p9 P& f% r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ B, f. y- q6 s) ?" o0 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; ^9 U& O. v$ A0 ?4 D$ T! LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. g% P5 G6 n9 I# B" A6 o3 ~6 M& E8 G
| MCASP_PIN_ACLKX( o; z9 H" C0 c, b* Q; _5 H# h
| MCASP_PIN_AHCLKX5 {& @1 P) V# n. a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ l& ^* f6 ^) dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 w: P! Z5 U2 q
| MCASP_TX_CLKFAIL . |! q& ^" c4 a$ B1 Q1 j
| MCASP_TX_SYNCERROR
) K1 |4 f& X3 z( p/ i8 B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 E+ C. q9 Z2 @| MCASP_RX_CLKFAIL
6 o& i- }* _8 B" V: m, R| MCASP_RX_SYNCERROR 4 \5 U, d. a: U8 v* X: n+ k1 Z! z9 S" }
| MCASP_RX_OVERRUN);
* T: }7 d- i6 b+ i' p8 u} static void I2SDataTxRxActivate(void)
7 i1 r2 |+ @# M' }* y- J% p7 H{
2 B1 c) z% z; I; }# D3 [/* Start the clocks */
2 x. J) k! N- i6 [: `' O' NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 \3 Y9 X$ R, C: O) k# g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 m `4 d$ W- H. LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 Z) j. K- g! Z3 e) Z) H7 \; fEDMA3_TRIG_MODE_EVENT);
2 U5 h3 y( F* Y9 R! g' m* ^8 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 x' K3 L* L! k! _% [/ Z- a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( ]: K/ B7 F) o0 x4 F- W' L3 E* [" Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 m8 z. q2 h; a: T3 u3 N# |1 _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 o" i! F( O8 z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 H# h( F; b$ R: M( E( u4 nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( A) U& v) U1 I6 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) F* X6 [+ L7 g) j! F5 r @6 I
} 7 c* e a) A) j \; K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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