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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 r' o: X0 L7 F7 n- r
input mcasp_ahclkx,2 K7 k1 {! y- F+ p; V, g& a
input mcasp_aclkx,
0 L) c) ]) b" N3 [( k" F& O* Ainput axr0,
q5 T P$ T1 G" S, a( A; e2 s- P4 P, x; [- d0 Q
output mcasp_afsr,
9 u& o$ }5 M) x8 F+ t: a, v' koutput mcasp_ahclkr,+ I% ~% t0 [; n. |
output mcasp_aclkr,: P' w& X4 F2 Q/ Y5 b) w+ F/ B4 U
output axr1,# d8 q; M, `6 N- b1 w6 i0 J
assign mcasp_afsr = mcasp_afsx;
: W% j$ v, B. ?: g( ~assign mcasp_aclkr = mcasp_aclkx;2 Z7 g5 Z% R6 S: M( d# |3 _
assign mcasp_ahclkr = mcasp_ahclkx;
- @0 l# S5 J( v' lassign axr1 = axr0; - Y% q1 U# P. X# H. M. t# R* e: G3 }$ B
( D( n$ i: D7 n `, p9 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) s; Z1 L' Q E
static void McASPI2SConfigure(void)
) o* |+ G1 @6 x9 U{* A# Q e' I( U* [) |5 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 D! J6 r/ x3 N3 r0 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! Q7 `# J& l. h" `# L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: Y; N6 z4 g- J* B% p2 I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 |7 {* n2 o1 D" \7 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ b3 ^1 x2 q0 g" ?" _; O6 |9 J2 u
MCASP_RX_MODE_DMA);
. i6 M. J- T" o( j) \$ ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 G1 A- M) q8 X* X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- ~) v) u! u' }4 W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 ^3 v0 P/ z6 |" r9 z0 TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 S6 m+ ?7 I$ q# D D/ E0 M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , a0 }$ u- L7 r- {- B" z7 {5 u% X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# G, d. h' ^ sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 F) H5 e" n# q: ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + e8 w% i( E+ i' E; `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 \( ] p6 f' M" c
0x00, 0xFF); /* configure the clock for transmitter */
1 q/ H s9 f$ Q4 v) v3 R y& tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( r3 A2 F' U9 }5 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 W1 ^6 N+ ]# T3 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 w8 h ?! O5 ]- t0 t0x00, 0xFF);$ i6 g9 F) x- i/ F2 _
& u* j3 t; o0 V; C0 b
/* Enable synchronization of RX and TX sections */ 1 o4 }- i" N1 A" Y5 ?1 e4 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 m2 U* q- l$ `2 M0 d, A: _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 J* e5 u% \! k$ N2 ?- RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 o6 ~: u" s8 v7 F5 d+ a3 n
** Set the serializers, Currently only one serializer is set as
' a9 A: X. F5 a, v2 B** transmitter and one serializer as receiver.
1 X. [$ ?$ v: {4 Q0 r+ A7 |( Y*/$ m* t5 x- t- s$ _ h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: j' d/ }2 J' v" n! u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
I0 q1 k5 ^/ x** Configure the McASP pins
0 M0 C4 X7 w# Y% i** Input - Frame Sync, Clock and Serializer Rx
! }; q2 X" E! U. [9 i, N, t** Output - Serializer Tx is connected to the input of the codec
, V0 B3 ?( u! I# }0 c x$ C*/3 _7 X% v8 e* M `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ F0 [3 [ y& uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 t7 a! W0 [# J q4 A s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, U9 _" Y+ k, D6 M
| MCASP_PIN_ACLKX
2 q' n" h5 K. A! e% W8 w1 M| MCASP_PIN_AHCLKX. H5 P1 `* D! T0 T, z% z) q Q( Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 u& A o. K- y, B% A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' w; m. j( m6 X2 h* I \* o| MCASP_TX_CLKFAIL ) T# b2 _7 @6 D5 ]4 p
| MCASP_TX_SYNCERROR5 h1 C3 N3 g& Q" L: R6 Q# q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
`3 Z( I& B# u0 n7 K% k k' v# A| MCASP_RX_CLKFAIL) n! l3 b9 b" ?0 m7 Q% v, F
| MCASP_RX_SYNCERROR
9 ~0 ~& X& y& q! c0 `| MCASP_RX_OVERRUN);. Z! |( O3 S4 V2 ~( }
} static void I2SDataTxRxActivate(void)
& v0 s1 X3 a5 T* O{# w+ `+ Y8 k0 ^# @2 u
/* Start the clocks *// U" E& c+ {7 Y- N( N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 l& X) _+ C6 F1 j3 O1 j' P4 MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 m# E, m0 J3 S6 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ y; s7 n+ `1 e+ h' H# z% }0 X
EDMA3_TRIG_MODE_EVENT);
* U; _# v$ l" BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ x, K( a, B! F& `& C/ YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' _$ A* m! Z9 o; |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% v5 M! z7 [1 r$ x* Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( Q( D+ E6 Q: `. |1 A. P+ Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ c2 n# s+ V# m8 E+ v5 b' LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 Z0 Q G4 F8 O8 [- y' I7 ?8 nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 L: u; j* I3 q( f: V+ R$ S} 0 i+ X( w2 u8 t$ x( j" Q; K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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