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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 K: Z- y/ j5 c) x0 T6 M
input mcasp_ahclkx,; i* z, c# E# J2 t9 I4 i/ c% w! I% ^( {3 e4 E
input mcasp_aclkx,5 m! e0 Y9 [/ N- c7 A' r3 E+ i
input axr0,
1 w; L7 J: @0 z1 V+ K# @* Z! x
) V$ ]: h. W! g8 N9 Loutput mcasp_afsr,
8 ^4 P8 K, p. d5 i, }3 A: foutput mcasp_ahclkr,. H1 j& A7 F( M4 d4 X. X/ V
output mcasp_aclkr,
! C1 Y1 ^. n: w% Zoutput axr1,
& {3 q- |6 G$ Q! D" N) s assign mcasp_afsr = mcasp_afsx;
- T$ X& W1 D! ^# }: Z8 h8 L1 kassign mcasp_aclkr = mcasp_aclkx;
2 G5 J0 B% B9 x3 Bassign mcasp_ahclkr = mcasp_ahclkx;& v" l4 \; Q4 B% p9 ^( R( X6 L* Y
assign axr1 = axr0; ( [* r% [& J" x% e
B* \% F; G7 [# H7 U! p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( h2 E, \ o# L7 e# [3 q) }& O9 `
static void McASPI2SConfigure(void)- q' A. H5 S6 P! \4 u
{
/ \2 Y% q1 Y' [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 O J+ S0 S4 C/ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// c9 T) t% Y' i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) r, Z/ Y1 @$ J' J% x& ^. n( B/ nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 r( V/ t P9 u5 C5 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 x! R) P" [! V* D. G- g
MCASP_RX_MODE_DMA);3 Y. J1 }; d. k. t. u' [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 g F/ ~* @( ` T0 yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, J8 R W+ S7 s) W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: u3 t; K7 y$ J* M. z4 f wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( I5 h( t; W/ p: x) ~. {/ x; nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" n8 r! |5 L# W6 z7 G5 X9 b# ]* ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& g! n( i. C5 w% M F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! O p p' K8 H/ X, N! zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . `! k; s# s& A4 }8 G' m% \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 P. K0 N: K% f5 r2 {" C. @! l' ~
0x00, 0xFF); /* configure the clock for transmitter *// l* q, Y: M2 s6 c; D6 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% M4 x+ e* d& z" M% B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' t1 D2 Q/ U. [3 X Y3 k8 s$ `$ z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 b$ D# P& |8 J; ]/ Z; s4 g0x00, 0xFF);
. ~( s6 P b5 v. t$ c
# Y% r- ?% b. B; R/* Enable synchronization of RX and TX sections */
6 [, \" h" [, _' K c) t% `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ h" j8 K' |2 J9 f0 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; Z5 Y5 s( ?& |2 S* V/ i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' i$ Y/ A3 b. j# h** Set the serializers, Currently only one serializer is set as# x0 m1 C& M+ ~; G
** transmitter and one serializer as receiver.0 w" Q, R) \. s4 ^' |1 A9 y# O
*/, i0 a3 a0 ]. t, |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( @7 g/ `: ~ M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, L" v4 \. e1 ]9 H% s** Configure the McASP pins
7 H# b3 O$ N* f. n3 f! v** Input - Frame Sync, Clock and Serializer Rx
% K @% }* C, ~ `6 p! v** Output - Serializer Tx is connected to the input of the codec
* q U6 P: {) o- \, x: r, Q/ g7 G*/% H6 |$ U4 R2 c6 s p. R* n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; H1 ? y+ V( J* [' l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ p5 M( l4 p% A: r2 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: [+ S: d5 h0 b
| MCASP_PIN_ACLKX
j% U( a# h' C, a X# [| MCASP_PIN_AHCLKX2 `# ~- @/ z" C* \* h
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 p, J8 [6 C- v( g, vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR {2 x" B6 U+ g! v/ W
| MCASP_TX_CLKFAIL
; Z! O' b7 |* Q| MCASP_TX_SYNCERROR
" ] I( F) B. E X q. Q! Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& B2 {9 |2 A y# |( _| MCASP_RX_CLKFAIL
J* K+ _& @% {- O, y/ Z| MCASP_RX_SYNCERROR
2 \/ K6 a1 D* A2 i# ]4 |" F) H| MCASP_RX_OVERRUN);
* r/ j x+ M# W& d} static void I2SDataTxRxActivate(void)+ s& Z6 B- @ L
{
+ O3 w! |7 q# a2 B/* Start the clocks */ _ t- k+ Q7 g( i* y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( [4 y9 M# j3 a2 v& n3 v) G3 S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) g0 m$ Y3 t! i$ g/ `: ]" m& LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 m; q7 \2 y1 { e, x" X/ KEDMA3_TRIG_MODE_EVENT);
4 J1 G( A2 I/ I1 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : j. c6 a. z9 Y2 q/ _) Y: @4 R2 l. R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% L, T) b0 p: m7 }+ SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( ?( Y y2 s) s* k+ {# XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- g9 t, ]" [, Q. F: Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. ]- |% g. w0 J- K, N- z. B' MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# \- d! O7 |' O+ X' s5 [9 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# L0 m# }9 T7 P8 i6 ]}
9 E) B& F% _4 o4 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; R5 S. x1 o7 J- l
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