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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 b7 X- |2 |3 p3 V- zinput mcasp_ahclkx,
: C# f& g p8 P! _! y7 Pinput mcasp_aclkx,
) y4 j8 ^( X' E3 S2 d4 Q* x! h" ^input axr0,
. o8 y, h6 z/ X+ m2 X, y& ]/ ^9 P p$ k+ L" l) |
output mcasp_afsr,
. {( x: |% s! V. s! J0 |6 Noutput mcasp_ahclkr,
' E& G+ c$ e" D; s6 Zoutput mcasp_aclkr,% ^8 w9 U9 \* G. {
output axr1,
# `3 o9 H5 y% l/ N( i assign mcasp_afsr = mcasp_afsx;% y7 W* ?+ u% J# K# K
assign mcasp_aclkr = mcasp_aclkx;
- ^7 M' l& i: J2 G1 passign mcasp_ahclkr = mcasp_ahclkx;
/ E. C6 C, H) ^# A2 I" [' Fassign axr1 = axr0; , a( N& X, x3 s( f4 ^$ N4 Y
' o% U; o* d& ]9 `9 i% R- l" q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * x6 `; c) T- z6 @9 {" W$ K
static void McASPI2SConfigure(void)9 n. f, b, Y) D- H
{
! y9 l( n" t4 o& ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ Y4 f2 _7 @( \2 G; \0 y$ {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. y/ h' g7 f n# ]/ O% z' g F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& G E- r$ p5 ^+ g' OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: o5 Z+ i6 W+ ^: Q7 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) f- V/ c. }) D E! M% kMCASP_RX_MODE_DMA);
" g, |% d* |6 s5 T$ V' nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, K. P5 o- h" P* ~) K- S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ u2 r' x( C& C7 t T. E( B+ Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 W. R0 `9 J$ S9 UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 Z* b) s' _8 ^% U: [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 h3 S) s& {+ HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ n0 `3 _ M ?% K8 Y1 S; y) ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 F; ~1 K5 f/ b1 H0 s) N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- q9 I0 z& N0 _0 K7 p. UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% ^* K# P, {8 e/ ^0x00, 0xFF); /* configure the clock for transmitter */4 }9 \, t7 C# Y, O/ \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( y9 o) {: Q$ s. c, j8 J" {9 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! }0 Q8 O) X5 ]- `* k9 E; y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* z7 P. p' ?$ [% `- V0 D7 z0x00, 0xFF);) T# Z; r. f! v
6 k4 F, I/ `6 x0 d9 _
/* Enable synchronization of RX and TX sections */ 3 i8 z; K) x2 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 l; n+ r9 E1 [0 {2 U( g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- |3 M# h" h1 j1 _! D+ e5 ~" p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. J( r u) o% A& v- N1 i+ a: Q! R5 d
** Set the serializers, Currently only one serializer is set as9 F/ A8 D' [* O. S, w: N4 e
** transmitter and one serializer as receiver.
4 `/ G8 q7 L# s8 b: E, Z) g*/
. `! ], @ n3 F2 L; h0 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& {3 k2 x& U3 Z3 U+ l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' M" @. M1 g! v4 I" d** Configure the McASP pins
: V& l8 p& Z% y7 U/ Y$ E** Input - Frame Sync, Clock and Serializer Rx
3 V9 y' y0 S: X4 d" O; D. c** Output - Serializer Tx is connected to the input of the codec
. ?& Q0 ?2 b* F/ W' }*/$ E4 }# L% C# f; d. {3 Q, ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ h( r- ?& E; E- G' `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 f- M5 W% ?0 l# J8 `5 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% U- V( h$ n! P. |5 T8 H% [
| MCASP_PIN_ACLKX
- l; k9 ~" [, p9 r: U# s' U+ @| MCASP_PIN_AHCLKX
0 o% U1 f1 c2 ^. D( l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 X) _) w- T& h% x4 s4 T+ R1 m* lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 Q7 J, e9 J3 E1 |; y| MCASP_TX_CLKFAIL , b8 p ^" c' I! Z `
| MCASP_TX_SYNCERROR& k v( r+ j& n& q" z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 H& S6 A0 r1 s: e" L
| MCASP_RX_CLKFAIL
6 b! m. P8 F* y& m, H% J+ @| MCASP_RX_SYNCERROR
8 m- I! e+ A: D6 k" V| MCASP_RX_OVERRUN);8 E: ?% t2 K, Q2 M, l! e2 |
} static void I2SDataTxRxActivate(void)2 L8 l" c7 E9 T: S: X8 J2 C
{
- D2 y. l6 ]5 P+ t+ I/* Start the clocks */9 O" s9 [% Z2 t) B( f$ k& w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& h# i. u+ I& s) ]6 X1 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# h3 e7 H$ l) F5 C" M0 G) ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. N1 a; k' `* A- C- ?
EDMA3_TRIG_MODE_EVENT);
( E9 p" z! @$ k/ E/ d w9 g2 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, B! L) n+ p/ }5 B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" d/ L& {- D6 K# o( [; O& Q& A% I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 e2 c m- E; F1 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
[9 d2 w. @6 Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- p! O2 F# R$ Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ]6 |, ]5 a* d: i8 U) I) \' Y8 A8 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 r3 H. e4 k' y- o" S
} . o% K9 L9 E N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 q" i6 T1 W$ I5 A. s9 D0 P
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