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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 d$ L- a% Y9 G& finput mcasp_ahclkx,* A. L4 B y: U* A
input mcasp_aclkx,
8 a& V6 t$ i. }8 y! finput axr0,2 k. k/ D( z: h. C4 B6 e: R3 x5 Q
5 p! r# B2 V2 W3 `/ L1 M( u& O
output mcasp_afsr,
9 }( H' H+ E7 m* Ooutput mcasp_ahclkr,
" Z* n/ I; T1 ^6 U" ?; g/ l8 g, [output mcasp_aclkr,* p# ?! i3 O# W% S$ [( P1 w& p% @, M
output axr1,
' N8 J9 K' b" L$ D1 ~& O assign mcasp_afsr = mcasp_afsx;
, m* R w2 m1 _% Z' E/ Jassign mcasp_aclkr = mcasp_aclkx;1 S/ w" _# S3 R- a2 ?- T2 ^
assign mcasp_ahclkr = mcasp_ahclkx;/ \1 `+ c7 j. p5 r' _; e
assign axr1 = axr0;
9 A) n# n! v0 `$ H, z. V% g% U, x3 w% t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( E/ ^& H) j. q, O
static void McASPI2SConfigure(void)
: w: R) G/ o Y3 B- t( J{
: m H4 J; V/ E3 Z3 |; ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);: ?6 P# b- a' c+ ~6 J" o* B1 q$ q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, {. K5 U. t' e8 y; F0 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 O) B( T. [* W/ y5 f2 D- O/ {7 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
W5 ~7 \' {$ t! I! tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- x6 C' [) D. x: V4 x4 i1 @8 FMCASP_RX_MODE_DMA);+ {. n+ f1 ~. P3 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- I# x! Q" W# a6 E }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" r. y- ~* ^, R/ U1 c- T7 QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; D( a% m+ w, d0 \( i* JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 n( [/ W( W: q4 X6 i. B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 Z2 V T0 f4 R8 M) MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 _3 d2 j8 I' J# G' F2 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ w" h% F C' [( H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * O/ O$ c& g$ T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 D7 l2 S9 \1 [0x00, 0xFF); /* configure the clock for transmitter */
" T, E5 [$ r2 g: gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); H% n/ c: f* C& j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 x' m( \% C* |% c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; n3 w! [, O& q @1 ?% [
0x00, 0xFF);# y, x0 o5 J" T4 c2 o- y
: X$ R1 W a% z( S$ @7 ]/* Enable synchronization of RX and TX sections */
2 U4 @$ V# ~) N% O% H* M1 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 U) y/ i. H4 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 l1 e2 l6 T! n- D, I+ b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; k, U* y' Y n$ G
** Set the serializers, Currently only one serializer is set as, R3 C% J* E' m" H2 b& P) G
** transmitter and one serializer as receiver.- p& Q) \6 j( Q. R' ^6 v# w( J
*/# P7 B @6 P8 w0 P2 X1 g! l- a# b3 }' ^5 {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# q/ }) s; a0 v8 J6 x8 p4 H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 v+ _% P& L8 v** Configure the McASP pins
1 O# m+ U3 v3 U3 \ S) |: O** Input - Frame Sync, Clock and Serializer Rx
4 ?/ Z$ s8 @! g5 U6 z** Output - Serializer Tx is connected to the input of the codec 9 x( F: m! d: n' e9 R
*/
# {2 L1 @) [" NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( r2 H5 r/ e+ ^4 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 k+ I; _3 G; L# S" nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. Q2 U( x( B9 p
| MCASP_PIN_ACLKX5 G9 c2 ?) _" T; k* S
| MCASP_PIN_AHCLKX7 R# \: d3 [ b0 U1 K. E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% t/ x# M& E& `1 b( w, d7 y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 d3 q1 t% m4 k N6 @# ~) s4 K
| MCASP_TX_CLKFAIL
! i# m! j) O+ o; \+ K2 n| MCASP_TX_SYNCERROR2 w& Z3 I' e4 M9 D! ~& A# g' c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ z+ Y& L3 Q/ d$ }| MCASP_RX_CLKFAIL
7 I8 r6 A7 p" k L. z| MCASP_RX_SYNCERROR 7 E O8 \( I+ r* p- E0 f6 ]
| MCASP_RX_OVERRUN);, t) v8 S3 A2 T6 ?# a0 y* p2 ^4 a" E% o
} static void I2SDataTxRxActivate(void)
3 F: Z) Y2 A. v/ ~- J: F+ i" \. Y{5 j4 \3 j# {+ Y4 h- E
/* Start the clocks */8 M0 c# [: }2 a0 [$ W' {+ B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- j" K9 s/ h% n8 ]1 R6 X- j6 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ D' c3 k2 A) G3 [% P; V; TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 W7 W8 E! F. Q: x& ]$ AEDMA3_TRIG_MODE_EVENT);
- @& d! H- o& u' S6 j5 ]9 v+ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* Q) @3 V4 d0 t B0 e& `8 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- b: i2 [2 B5 I; }0 T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ _9 h O0 y5 b" M; }6 bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ n/ W+ b$ x' r4 Y* rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. G! G3 |: E" S4 @* J! e6 p# S9 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 b& r4 h) y' `" w" sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 p) L% u0 j8 w7 _, U} + z& M4 F7 ^; ]6 B n. J( X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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