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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# `- G2 j$ D$ f. \' X b
input mcasp_ahclkx,
. R; o. o0 \! B3 f8 ?input mcasp_aclkx,
$ U1 d: d8 i( X3 A, P. rinput axr0,
/ C' R t3 Z1 v" z. ]+ g& h$ L0 m3 w2 Q
output mcasp_afsr,2 d" ]0 [# { J, M
output mcasp_ahclkr,
' @' o+ U2 E6 ~& X9 Uoutput mcasp_aclkr,
4 [ ]2 g! S7 @. qoutput axr1,, A, E$ h: j5 y" Z* A+ K3 o& P
assign mcasp_afsr = mcasp_afsx;: D) q# W4 z7 r1 y9 W+ ~0 e
assign mcasp_aclkr = mcasp_aclkx;* A5 X: h- n8 K/ f& o8 o. {& a1 C2 x; p, Z
assign mcasp_ahclkr = mcasp_ahclkx;
4 p" S0 |* m" \' ^assign axr1 = axr0;
% F u0 y$ D% a9 A/ \* ~ _2 m9 ]6 z/ m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * L P( b2 V+ Y5 p
static void McASPI2SConfigure(void)" ], s% C. v" f3 ]6 j9 u& s
{
" S7 |& U q; w$ ?/ b6 g; TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* v! `$ G* S F+ F' T: R( W+ q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' S5 \# |2 O( ]1 d a8 zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" v$ h+ @# J1 b, e3 B2 [& c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ K6 L3 ^& l3 L, DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; G) @1 l( }, I. w
MCASP_RX_MODE_DMA);2 I, g, @& @ a6 A- G- _' T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& y" E, G& o5 k$ n1 `$ ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// D* ?7 v: G& C5 m j' n9 j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * q/ k; x# ~9 D! Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 \* i* g& S* A9 J& gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 f4 s) h R; K& b2 k5 k$ GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ o7 m6 g/ F6 r( ~8 I7 g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ V4 x" D) E+ _ Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 v( v- }0 E/ W( BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- R8 H* x) M! z" F0 G" z0x00, 0xFF); /* configure the clock for transmitter */
! L9 O5 [3 g2 O& CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- I+ J) K3 a* gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ g" p2 E' O$ {4 N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," K5 o. E+ E9 Q3 u9 A* f, Z m
0x00, 0xFF);
0 `7 f1 Z/ L' ? u) w! O6 B2 h& x/ V; p. n" G a& s: X
/* Enable synchronization of RX and TX sections */
" H3 j+ {+ B9 R+ E! N) BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 e0 B# I. |* zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- `. y3 l) y) \, n8 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# r- h$ f: t& R- d** Set the serializers, Currently only one serializer is set as8 a7 @5 d6 A" H' q
** transmitter and one serializer as receiver.; e' ^# d1 l7 w' n2 R. Q% [& a# j
*/
& U6 b9 y1 `0 y8 u; }& t; [& ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! [4 O; r# @7 s+ A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 o) K B- Q' c8 n4 R% L/ ]** Configure the McASP pins `! ^: R* B5 s
** Input - Frame Sync, Clock and Serializer Rx
- D ?9 B, ]- s1 o4 S: x** Output - Serializer Tx is connected to the input of the codec % J% N, }. E3 V
*/2 [6 {) M; h; Q3 @2 h0 m+ T8 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! y& p3 T% l. _1 F: AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 B7 E! v6 K" e) ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. K0 p; p2 H8 t1 Y| MCASP_PIN_ACLKX7 e; }8 c/ ]3 m8 M7 \4 U- \
| MCASP_PIN_AHCLKX8 c& l2 M& v5 p' C5 p: O% _3 z/ u0 E2 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ J" J- ~' t D4 z o- F2 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! B0 w( ~2 Z( s: n/ \| MCASP_TX_CLKFAIL 2 E! H \) H" i# _
| MCASP_TX_SYNCERROR1 r( K) { P! }0 b/ a8 K; Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 }9 |1 z# W- v6 }1 l+ F0 @| MCASP_RX_CLKFAIL# j k! x6 C/ I$ H8 x! \
| MCASP_RX_SYNCERROR
/ D {& [5 p8 F& v% g j- }0 g| MCASP_RX_OVERRUN);
$ X: h" [) q- J2 {% J. G, X} static void I2SDataTxRxActivate(void)* r- O/ ]7 u) o& c; o
{
. p6 V2 Z8 x5 V* k' w) ^) o/* Start the clocks */% [) v6 T7 n" ^1 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
s' ^* E0 y2 q6 d. E, p' y& ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) x! U2 r# C7 { ?8 I! \: G) cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 v) I8 P0 B( n! L6 {- ]) c K' [EDMA3_TRIG_MODE_EVENT);7 F0 r E( j0 N4 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 S% y, Z) N) J% i# p# a6 a7 jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& v* Z- Q4 m& V9 h5 _3 b- j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 |4 l& m! ^( b1 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: I; K: C2 m: S/ c6 H0 d* E, C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. x7 ?7 K$ t+ I( R* _. I' HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; N" m- I/ k% s9 jMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. r s4 O) Q4 b6 T
} 3 x! u+ F9 a% u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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