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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# u5 k/ i s# V( [input mcasp_ahclkx,
' v: o2 ~ c) A+ r8 Vinput mcasp_aclkx,% h2 `7 j- i4 c' e' q2 Y$ v
input axr0,
& f: P* n, j2 G4 ]) X, @0 E& t+ {4 @2 b4 l/ H
output mcasp_afsr,1 |' L8 p. L; n/ m y
output mcasp_ahclkr,
9 S. J1 s( Y, T" U( ~output mcasp_aclkr,; ]# |# N. q0 U3 ^; y8 Z
output axr1,& |5 e& |$ ?) s
assign mcasp_afsr = mcasp_afsx;0 h6 c* x2 t! T: k( Q" U8 C
assign mcasp_aclkr = mcasp_aclkx;
" b2 |4 p( z4 v* @1 yassign mcasp_ahclkr = mcasp_ahclkx;
D4 T( B- g+ `' ~5 {assign axr1 = axr0;
# S, e/ Q6 q N% E* Z: @- Y2 k" [" f$ @! A4 @2 H! M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : ^% V( v& f) R3 }
static void McASPI2SConfigure(void)& ~3 c& b1 h. p2 C; S$ O/ O, f$ I
{" g2 b$ k: W; r5 S8 N% k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 h1 a0 e' x$ }( _; ]$ N7 W9 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! |+ [- N3 l" tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' N$ n# N4 s! a% h6 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 f- L0 [" _7 d1 B% X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 S/ R* _2 @, K* t% {) [7 p. q
MCASP_RX_MODE_DMA);
# a, n' Z& L2 YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 W( I. g5 @- e4 ?. y2 A& s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 q8 {1 r! l. C8 `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 w; \# F0 k0 N; z1 T0 \7 y6 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- N8 v: m: ]4 Q) b* G5 L% lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) b O, o- q! w( V% Y) t; G5 J8 V; z9 P8 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 ]1 |5 a4 ?5 V9 R# K; QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 b# l: \: X2 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , H3 Y, M o1 p9 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 `9 g: Q' Z! y; i# Q
0x00, 0xFF); /* configure the clock for transmitter */( Z8 R3 m+ c& [3 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
C) g# v- }- S$ _( U8 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( y: p u& j# w) K" Z' I" Y0 ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, C( r% c( @! I
0x00, 0xFF);
4 T$ D; W9 T" `4 o
0 \( b5 x6 n' n; X3 U7 A( @5 e I( p/* Enable synchronization of RX and TX sections */ / w: b4 V9 }: ]% j# L' e5 [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ G( P1 N: S! h, ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* Y" `+ Q* x3 l2 k ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: j- ?7 ~4 f& s9 _. s8 W4 m* [
** Set the serializers, Currently only one serializer is set as
6 o `+ S, ?9 e0 W' Q** transmitter and one serializer as receiver.: u0 ]0 p8 }3 |% f; |4 F
*/; _3 p: A0 X8 F) V6 ~4 Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; b' S1 w0 r" f, M1 w" ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 y$ h0 S M: e" ?! ?# e. L# b8 q** Configure the McASP pins
' e. k- \2 a1 L" d4 M7 M5 C** Input - Frame Sync, Clock and Serializer Rx
; }& @* |% O2 @4 g- [** Output - Serializer Tx is connected to the input of the codec - T& ?$ k0 E/ d9 Q6 B
*/$ G7 A0 }& H5 H' J% J, H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, f* }9 ]; X6 I8 |, GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 _1 a+ ?* W( _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% T" |$ U9 J0 w `) ~
| MCASP_PIN_ACLKX4 Z' K- L& l# W3 ?. R" X% |
| MCASP_PIN_AHCLKX# e3 |" n* }$ A' {, Z( Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* t. r1 j* O0 S; g4 @2 t' ], IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ R* L9 e8 o: y% O& `% x| MCASP_TX_CLKFAIL
$ \9 z8 p$ z) o! u# m0 l" P- L! t| MCASP_TX_SYNCERROR
Z% P% L- ~' D: D) v8 r6 X2 @( l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( i$ a0 K5 ^! }" d# t| MCASP_RX_CLKFAIL- b1 ?3 Y8 A' H( t
| MCASP_RX_SYNCERROR , u% U0 l6 M- t6 G* m+ E
| MCASP_RX_OVERRUN);
% k) q9 K. H; b1 _} static void I2SDataTxRxActivate(void)3 x9 t3 u% W5 u1 a
{9 O' s8 h& k" z' y" i. v8 p, X% j
/* Start the clocks */
* h) l; f' T% f) `* |% ^# T5 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& w( ?9 j0 `- g5 f' s2 h; G. |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* c/ Z6 p- \ h+ n8 u7 O; zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: H) }$ K) |* _" Q
EDMA3_TRIG_MODE_EVENT);% m/ t/ a7 c' A; J O3 e2 U9 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Q7 @1 v! o# j( X" _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 m6 c' S# @( E0 h! GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 | p/ Q# D4 U1 s$ f' ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
l2 ` ?& W/ J4 I, D4 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) x' O% @$ r6 _6 f( x4 |6 jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- ^: \1 v$ _! k. s9 c' M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ s4 Z; s. T- l4 c9 h}
& r C# q7 l! A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; Z' o6 K/ {, A% F! e
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