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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 L' E1 n- ]% p3 t
input mcasp_ahclkx,
( R |" w9 T1 ginput mcasp_aclkx,& N- i- y% \: y4 O7 v+ e
input axr0,8 @" n- J( Q/ F
/ M- k; I' F o, b, W: k0 foutput mcasp_afsr,
5 [1 {6 V# m% R2 q; noutput mcasp_ahclkr,
% z7 C: D' g1 d9 B: ?' I8 X) noutput mcasp_aclkr,& D" y3 n8 p/ I. K J: I
output axr1,; I, Z0 s. V' j; |* v% H0 z
assign mcasp_afsr = mcasp_afsx;1 p5 ?' A$ H9 X* D" F* B2 V6 F
assign mcasp_aclkr = mcasp_aclkx;
) ]" L9 G# r: I/ C3 }/ S% a0 U. ^assign mcasp_ahclkr = mcasp_ahclkx;0 i+ V M( ?/ Q/ m8 I
assign axr1 = axr0;
8 h |1 W# j% S
- L2 \' Y( y0 C6 v$ N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 t& q4 B( ] h- y+ G, lstatic void McASPI2SConfigure(void)& Z6 c4 W: h m# T8 p
{* `* S2 ]% M/ f# L. p0 c# N: f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 C9 o1 f7 w6 W! `" Q# H9 X! H& `* MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
R# B% L: R* h, F+ fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ |2 q7 x) J3 m: E0 C# AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, f, m5 k; R# k0 r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ^' R# T% w8 G) R* C
MCASP_RX_MODE_DMA);
N. I6 ^4 m5 c- cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# n4 j) o R( q1 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* [' ^; I3 Z$ i/ [8 L3 _' d8 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ?) c7 `% F2 m5 t9 X8 w% [: DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( [ W3 y. D" e) qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % W6 F5 o- e' @ l+ ]/ W6 U% H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( q9 a) ]' Z$ p3 \" {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ G/ y2 I5 Z4 x% B6 w0 I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 ?! a( m1 E. E, G2 B$ u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," n. G8 {9 w* k8 I. A3 U& d
0x00, 0xFF); /* configure the clock for transmitter */$ B; j. N0 F, U2 F1 ~ `4 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); G) K3 l+ Z" P0 p! {3 O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 E T! [1 C; q( g& s$ |+ I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, R; m8 G ?- J" ]0 K0x00, 0xFF);
" _5 @# E1 [* f' g; F8 f% ?% ~" I
/* Enable synchronization of RX and TX sections */
5 \# e6 e1 b, \+ YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ Q( V p# w* ~# Q, r. y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ | I: {' e, e5 {2 }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. c: H$ e7 S) ~' |* @ Q9 W3 R8 t" v** Set the serializers, Currently only one serializer is set as
* F* Y+ o" G8 ~1 h** transmitter and one serializer as receiver.
5 P1 g2 k- q1 K7 ~ N) k# q& H*/2 B0 D& l4 i5 m5 w7 k# Y8 ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' l/ x. [9 }4 |+ O# XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ~% h; N8 Z" J. v% u( F
** Configure the McASP pins ' F+ |- v* l# E) A. C3 A4 i0 ^
** Input - Frame Sync, Clock and Serializer Rx
5 |( ~' ?/ _# P6 W4 K# B! F9 t** Output - Serializer Tx is connected to the input of the codec
& c4 W& k m" S a3 P*/
; y) Z* B2 c: ^9 n0 s) x# V ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' y) W' c0 z& [5 x M( zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; w, D; R3 ^ x9 w0 J# JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 N3 L2 `. G; Y7 E/ ~# E
| MCASP_PIN_ACLKX( Z3 _- z9 a) B$ q% B
| MCASP_PIN_AHCLKX: T' K7 ^' }5 ` A. P" H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( I$ `# F S& p) y! I. WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 ]( z5 q( V; t, F+ j; d1 \
| MCASP_TX_CLKFAIL
3 h, \. `/ K4 c( E! F| MCASP_TX_SYNCERROR9 _1 n4 r9 ~. L1 U. ?& X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# |0 K2 ?# x/ B* B# R3 T| MCASP_RX_CLKFAIL
: }$ T0 i$ l: C| MCASP_RX_SYNCERROR 1 b- w2 @' B, ]! ^: m
| MCASP_RX_OVERRUN);
/ ~4 g" \/ n I. P' A} static void I2SDataTxRxActivate(void)
2 M4 Z* L( u, ~8 U- F2 Y1 \' |6 l& m{
2 F% l+ D* M, j$ c1 z, a4 f! T/* Start the clocks */
% x5 O- N' a1 U9 y: h" ~1 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) v$ u( @! Q3 R, }" [, qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: P- o9 Z0 B6 P8 I7 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) X/ `& i9 J K$ ^$ PEDMA3_TRIG_MODE_EVENT);
" M0 B8 R+ i7 F9 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, i; J9 ]5 J! mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 w+ W" V# A' C* `! G( \" BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' I( P7 X8 X/ b# d! S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% b) N2 _3 c& a2 ^, awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) Z1 q! ?2 e/ ]" yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# B. ?: j9 z" [1 C& w( T2 OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 p8 w F8 m. w1 ?( d4 a: i( y} 0 R2 m- j; \# d- }; p) S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + t. o I2 G, E" o' N# n
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