|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 C$ s0 b; ?# X; Ainput mcasp_ahclkx,
$ u8 g% A# o) }0 z+ Y- ^; Hinput mcasp_aclkx,5 f9 h3 I. ]. K, F. e
input axr0,
+ k9 k, c# r. Z2 L' H9 U1 w. |# L0 x4 }' p: U; @
output mcasp_afsr,
$ S2 b: H! Q+ s, \. s" P, A- m1 Uoutput mcasp_ahclkr,) e5 G0 t: a$ R' J; Q
output mcasp_aclkr,
1 H1 d! m. K' x' boutput axr1,) J: U" Z7 h' v/ A* j
assign mcasp_afsr = mcasp_afsx;# i. w) ?3 b! X
assign mcasp_aclkr = mcasp_aclkx;3 O m- J4 I) Y% M
assign mcasp_ahclkr = mcasp_ahclkx;
& h( d7 z5 f0 q% Q) t5 x! iassign axr1 = axr0;
! x! }* \5 f( e, n" T3 J, [5 }: R' I( ?; U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 N& T. D: [% ~) G g! a: N
static void McASPI2SConfigure(void)9 E. S6 q8 \, ~, V" B
{; u1 O9 @% O! Q# K5 _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 L% [. o: D* H4 a* X1 RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 t" Y1 V$ S( x! iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% u- f% K$ `% I% E2 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' E* X) j3 q- r. w* K k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 s; S+ `0 L, ]
MCASP_RX_MODE_DMA);
5 l& F6 V I [5 v9 i, n/ kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, v7 G3 }9 z* V7 |( e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 F0 U2 {: u4 R, K1 H: ^# `( GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- o% q$ ]$ y1 ^7 c0 c, u8 bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& U, {5 f7 G9 {( n* I' F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ]' \" e5 R* \ i4 P$ xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
{0 M, \- H/ p) a4 o- m- iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ q( h( ], Q# t1 j) q) n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 P8 C4 j% Y, Y6 ?* zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' O0 T6 ~9 E9 a+ T( r/ V3 ?0x00, 0xFF); /* configure the clock for transmitter */
) [* |& N5 B! UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 j( z) F( x" R# i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ B6 f5 O Q% ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% G# m$ J+ f0 F4 C7 U0x00, 0xFF);
# }. A/ u" h5 h) |, T
, U' h2 d- y! `. @, K/ j3 C+ R/* Enable synchronization of RX and TX sections */ - H9 d) r+ f" v' _* M" S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 P* {7 i* l3 H0 ^- B) T* G- S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ M4 ^" D3 q* @% r! z( PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& x7 g* L. f: w** Set the serializers, Currently only one serializer is set as5 h& B1 _% c: X: B7 w! {2 s. l
** transmitter and one serializer as receiver.
1 ]- J& x9 @7 D4 Q" ]% D*/
5 M; i+ e) t& n& B$ O, @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ [; [) I0 c8 Y# WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; x& F, e: c3 w** Configure the McASP pins
7 [/ I) r9 p# Q; O** Input - Frame Sync, Clock and Serializer Rx
2 `' K6 R. @ V; \' j0 J, i8 ]- y** Output - Serializer Tx is connected to the input of the codec / c* F j: g T/ k+ m; ~$ [1 w
*/2 z. i- q$ t' a; X( j7 W& s# p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 n% _0 p) ?/ N4 s0 L: E# w, _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ Q9 \. F. A7 _. D, b J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" |7 [) u( {% I2 b1 [6 o
| MCASP_PIN_ACLKX+ E( w% U( D/ l$ L, L; s- N
| MCASP_PIN_AHCLKX. X- j# H6 I7 l$ z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ \- {. `5 S/ @9 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : Y/ ~" S6 N6 F' y2 `* |% y0 ?: P
| MCASP_TX_CLKFAIL 8 y& `. ^, q, r/ K1 Z. A
| MCASP_TX_SYNCERROR
( w) s/ V+ g9 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 ~* x7 z! d" X# |) l0 ~6 U7 ?| MCASP_RX_CLKFAIL
+ s: T+ e7 ?( L! c: f5 U0 x0 N| MCASP_RX_SYNCERROR
- x1 O* Y9 t+ c/ F* j) Q& A# q, E+ n| MCASP_RX_OVERRUN);
8 I6 k. w1 D5 J6 E8 s- \% }( G. M} static void I2SDataTxRxActivate(void)
1 f+ j! k) `& g( K{
8 K2 N/ d0 {, s) ^2 n% j- Y( t/* Start the clocks */3 \, {" N4 j$ ]! p; U1 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ Y1 Y( j4 w( u6 U' O7 [' d" ~' N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) S5 l @+ _6 s! j4 @+ u' JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, c$ s2 _ {4 [9 l
EDMA3_TRIG_MODE_EVENT);' U7 t, r& s; L$ k# Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + O4 @$ ^" y; Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// I6 J; V3 \$ d/ f* G M4 j+ V2 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, J9 V6 N6 d" M LMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& p/ }5 L* F! H$ M( S, y+ j/ Q! c" cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: c% t; @& H- l m+ E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ j% ]- D" x1 W0 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' Y. b7 O- ~8 V' P4 \} ; n! |$ J1 B) s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 m8 u) j6 e& Q |