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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 Y6 M4 @0 |- w1 Xinput mcasp_ahclkx,' j* Y( X( S5 Z0 e5 ~8 Q
input mcasp_aclkx," }# j7 y5 @) ]) m; w4 |
input axr0,! n9 Y# A+ |/ [. g. H' c
4 \6 `% O R% b* E' c, zoutput mcasp_afsr,6 O5 r* \- d. C6 r% P& h
output mcasp_ahclkr,7 R% g3 L9 }7 B' Q
output mcasp_aclkr,
' w9 M" n4 f& C/ X6 P4 Qoutput axr1,7 b% |1 D5 i N' G5 [
assign mcasp_afsr = mcasp_afsx;
* n1 W* U) F( C7 a- R- Aassign mcasp_aclkr = mcasp_aclkx;* P$ D9 e/ l3 x' s' h3 b3 c4 B6 Q
assign mcasp_ahclkr = mcasp_ahclkx;
8 z- c3 N& u% W$ C- e( vassign axr1 = axr0;
& `4 X# V2 C* A7 [3 o6 k4 N! F5 w( u+ J' k) L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! l* z3 U3 _1 Vstatic void McASPI2SConfigure(void)- e& ^( P/ \/ j% T ]
{
8 }0 N S7 q# E: [* m* rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ g# H9 i3 S4 P) |5 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! Y' D1 U2 r) o% k0 {, _/ _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# `- R4 _$ J* |1 k5 D, j. v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 N4 N* \7 m g; R! [; ?( b# }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 O, ~7 k. e1 v7 q1 p, S: B
MCASP_RX_MODE_DMA);
0 n0 z) S, M* D" Z; x( X7 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 }+ x" k6 y0 Z" C9 _" |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% z6 Y' o- l0 u! B; j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % B/ P3 O9 L. P% m+ z# c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- g* l+ Y) n& `% V2 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: y8 a( N1 W) s6 h+ t$ aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( L. \( s$ m9 z9 yMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 H: t9 c: t3 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 Q" e' e, k' P6 Y0 k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; k) B6 H$ M$ q$ d
0x00, 0xFF); /* configure the clock for transmitter */7 X" {- Q0 z% h E/ R$ t6 t1 w2 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ c9 ]1 N: `7 U. X% H( S, dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' O7 n0 e, X4 l2 Q; q" a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% y. n: y3 s: ~0x00, 0xFF);
0 X5 ]6 r- }# F, Y- ~ P7 c2 x) U B+ F+ ]+ g$ X n
/* Enable synchronization of RX and TX sections */
9 i) ?# I! K3 y& k8 O' zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 Y9 c# q& a6 [! B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 G& S' u; W- y" u6 jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 C4 I' e, p5 S" t
** Set the serializers, Currently only one serializer is set as
/ |5 c& a9 B2 W* ^6 x o+ x! d** transmitter and one serializer as receiver., O% ]' O, o% K( }
*/) B" S! H" G- X5 Z, m# V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, `% |7 l: p% E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 Z4 F/ N" |" L2 q$ r4 |** Configure the McASP pins 2 |$ B8 m: S6 q! z, @* [/ D B
** Input - Frame Sync, Clock and Serializer Rx
. K8 D- \2 ]% k** Output - Serializer Tx is connected to the input of the codec
% A f: N1 ^5 Y1 M& @' D*/2 p1 G4 P& I# Y( s- E3 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 x: r; k* ^7 Y0 T: z$ Z* C8 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ H0 J) ]& N- j$ AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; i A3 e3 C3 V+ e: i| MCASP_PIN_ACLKX
) D" F3 k2 W1 ~& X0 P* [; [" \| MCASP_PIN_AHCLKX$ U$ d* w9 F5 ?* O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" j) l- N* U! a N0 L5 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 k' m3 k4 @6 {
| MCASP_TX_CLKFAIL
! G( W% P6 ^$ h- ?* n) u5 J| MCASP_TX_SYNCERROR
# ]& z. r2 Y; ~' V5 p. F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ H; @' T' F, {3 V| MCASP_RX_CLKFAIL3 O) d3 ^4 {8 y$ K: }7 T3 L9 _2 T
| MCASP_RX_SYNCERROR
, M+ t0 c) g8 ~, j5 a* M0 Z& [| MCASP_RX_OVERRUN);2 a+ r$ F9 L# p1 g
} static void I2SDataTxRxActivate(void)7 H# w+ F9 }- Q* y/ O# x
{
3 P7 E: |; R0 g4 \ p/* Start the clocks */- U( n @" _* v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* Q( W6 P4 F3 `2 Q1 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ n. x6 _2 U2 p+ B$ z! \* E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. n& F1 v& q* ]& D& rEDMA3_TRIG_MODE_EVENT);
3 I* n# n9 @( V' LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 P6 Y; @. `' E1 h9 T8 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 p" p4 e8 @- P' L& m* W/ d! @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 F( ^. ?+ r$ ^+ Y, q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 ?8 r: e% F/ y( a0 L/ G. J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" z# B. S* ?4 O" H# f" {8 k- GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 z6 q' A* {, WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ C* t, s5 M. y/ T4 Y2 o
} / ~, H: m- ?9 L6 h# `2 h* ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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