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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& z/ v+ T6 }( vinput mcasp_ahclkx,
& Y, |& h) @7 W: y$ ^- \5 yinput mcasp_aclkx,+ g S3 H, |" Q& O5 v1 s
input axr0,
. i3 M4 k$ a) N9 K" ~9 ?) `+ v
3 s& E0 O Z6 X% P1 Voutput mcasp_afsr,( Q) e0 n% x2 t
output mcasp_ahclkr,
) P/ t M6 @1 X, F7 P1 ?5 u, Koutput mcasp_aclkr,, y1 C. A3 ?1 [& l
output axr1,; i) ?/ P2 l/ l' T3 R% R
assign mcasp_afsr = mcasp_afsx;
+ @* T a% E( F/ Jassign mcasp_aclkr = mcasp_aclkx;
, x8 a$ D3 j2 ?( bassign mcasp_ahclkr = mcasp_ahclkx;$ M) d0 a% ^* k# W S
assign axr1 = axr0; 9 f) w! j. ^6 B V/ m
' x- k2 Q& U3 h( Q4 \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 N, ~. B# x8 i4 W, Cstatic void McASPI2SConfigure(void)
7 `' w9 m! e" J, ]* w{) j3 R! ?3 o7 q' I. [+ L+ [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 K- Y# h) Y/ T3 N" {3 q& M( Q* V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 u' ]& d$ q$ |0 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 n& R: v$ k' D* t. `2 s- y3 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 H0 e: q5 d! z/ E1 v7 mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! [- I; w, J3 R2 S0 g& z- b2 oMCASP_RX_MODE_DMA);. x) R' d, I8 ?- v% E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ]2 ~7 y# I" n" R. |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) r! p# r. |) y7 b/ Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 H0 p' A0 y3 |0 l/ z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 L) z9 `4 |3 k+ @5 G. @1 X& }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 E0 [0 Z9 w: PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 @3 a* d0 _$ `" l& vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 L6 c/ \, p, h7 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 a- y5 i1 N1 D, C4 o+ r$ v) cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 X5 o8 d( t2 u+ G- d3 p. G( A7 k0x00, 0xFF); /* configure the clock for transmitter */
& {/ M# K( N4 \# _( {/ y+ BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' a! _8 P; v: [$ q: }, a* j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ X# y5 v" v5 s6 x; r# nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& Z, i6 |2 C6 H; P9 N0x00, 0xFF);
* a- }: K& V1 A2 E, }) P" b- ~5 A2 ~& h1 X5 P7 c& K2 ]
/* Enable synchronization of RX and TX sections */ 3 `6 O4 G% X- y O% Q# O9 d% b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% v( z0 Z+ r$ s& ]3 t d: V, l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% Q3 N* w& r5 s7 [) w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 K& l% L. T6 q
** Set the serializers, Currently only one serializer is set as
$ m/ t. Z! T) G0 I** transmitter and one serializer as receiver.
- x4 T" k; ~8 H4 e5 M8 O*/% K1 N5 `) o' l/ a' w) k( t. K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; E0 ?0 `) R9 ^5 ?" w/ o* |+ P6 R, O- t+ dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 Q% k( }' Y* f1 ]1 {3 I** Configure the McASP pins
5 x$ a! X% }, h2 {* v8 S' u** Input - Frame Sync, Clock and Serializer Rx( e4 j9 }- P6 k# P) c$ l2 B
** Output - Serializer Tx is connected to the input of the codec
6 S+ l; |- j2 V0 z+ o2 e, H4 W*/; p* f0 C, n0 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 a3 e7 _8 x! i$ MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! B9 _6 |/ H9 T4 A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: O6 V F0 v1 f7 c| MCASP_PIN_ACLKX4 m5 m/ f( l* b* f1 s( I7 B
| MCASP_PIN_AHCLKX
7 |4 g3 j, o- }1 `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ {* q G% A( a2 R f- R. C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 h" J3 L5 S/ Z# I- Q) M
| MCASP_TX_CLKFAIL 7 s' D' b2 y X
| MCASP_TX_SYNCERROR; e; x' V: F; c: v |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 i# @8 C5 F3 g0 c# T| MCASP_RX_CLKFAIL
5 A4 N C. R( U| MCASP_RX_SYNCERROR & ^0 @2 R4 \4 t& r: ^
| MCASP_RX_OVERRUN);
! s3 i8 D) k$ p& g7 J: w} static void I2SDataTxRxActivate(void)' E) [4 T/ D( g6 G* S1 x
{
8 F: v# o& [' j! N8 D/* Start the clocks */6 D3 z! }% e6 C6 G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, f0 H! U+ M. M. K* f( q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 G6 [1 L3 I$ E4 k+ d6 DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 N( q# V' I# s" y0 k6 R# HEDMA3_TRIG_MODE_EVENT);2 m3 y# N6 J$ }& G: T o* A8 l) U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( i y# f2 E3 }& jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 G- t! G7 {1 j3 m0 M/ N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' E8 O4 ?/ {6 p/ c' x. NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, p" |" ?, G; Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) c- y- c7 z) N6 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 f% k: L" |* U' b% aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# c0 {( U5 H$ |' t4 S* U" O5 V}
" Z& z- q/ Y5 e4 `' c5 {9 `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " W) P4 u# z9 \: f" ]
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