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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, b. z) w7 n" k6 @/ q C, {& m
input mcasp_ahclkx,
7 u9 p% x4 Z) }) |9 @+ ainput mcasp_aclkx,9 y1 n5 A9 y8 F( Y8 w8 i9 v6 i4 P
input axr0,/ I0 {1 G$ I/ ], u- K
7 C1 ~/ n: O7 z
output mcasp_afsr,8 D4 r; N3 p9 G' P
output mcasp_ahclkr,1 ]$ s2 H+ q$ ?$ q; P
output mcasp_aclkr,2 _ j/ u3 s( L+ g( I* n9 f3 m
output axr1,
2 X' X3 G+ N9 K; [9 ~) I& d6 h assign mcasp_afsr = mcasp_afsx;
4 l* w% `* a O u5 {assign mcasp_aclkr = mcasp_aclkx;) u- J7 o% p$ ^' q
assign mcasp_ahclkr = mcasp_ahclkx;. Z6 J( o: ?% d: o
assign axr1 = axr0; ! D, J# |- Q- j4 O. T. U8 e
$ z2 \' [3 Q: j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 O3 y; o- v+ b, W; v3 Kstatic void McASPI2SConfigure(void)
, R! o( l& R. A, f" X{: K% ]6 K6 t2 u q# N& H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! q! I( z2 c( L2 o" T wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 _; g* Q/ M6 [1 Q6 R6 M- p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! M% l& z: R8 w7 H2 Y1 G4 F# y4 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& {' E/ O+ T7 s3 \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! V* @1 n" {( Q' I p) ?* N( KMCASP_RX_MODE_DMA);
' u1 E- a7 y% v6 |2 a& wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ R- f, m- [# \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- J, O4 X- \: b, x }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 ^1 M" V! A% I5 Z6 u' z! eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* Z+ R5 Q. i7 n! Z8 q) C& y, OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
E) v* Z. m: r4 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* X, a; R3 h1 H* r: C; y) _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% B. U' E( R0 Y! z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ r) b* y* v; Y7 o6 |0 E5 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 K2 G6 x1 X+ Y3 @5 D+ i0 _
0x00, 0xFF); /* configure the clock for transmitter */, i% @7 S' X6 H1 Y) u, ?9 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; z, S. [8 N/ o3 P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 R( N2 G2 s6 E7 AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* f' o; D) ]& K) B
0x00, 0xFF);( ~. b; k1 a0 E/ Z6 [/ w- W" N& o% I
, N5 d/ F* a( M G6 e. y! j
/* Enable synchronization of RX and TX sections */
1 O- u0 [/ I% X5 |3 k7 r# TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ q3 y ^" ~2 v$ R) D# |& l0 B9 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# g& Y m# X5 W/ F# |& E& SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" u: U3 j2 C% I; h, R1 r** Set the serializers, Currently only one serializer is set as
' }# O; X# p0 s/ {+ f2 [/ v) x** transmitter and one serializer as receiver.
5 g! d, @: H' B8 Z2 i% i*/' ]0 Y$ v4 J' z* f4 H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. }# \7 H% M* B3 f9 V* h: A% gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 y8 i( r6 `- k9 ~& U" f" ]8 i
** Configure the McASP pins
) T A, ~- ?. V+ m$ W** Input - Frame Sync, Clock and Serializer Rx( C6 Z8 G$ @( L. K+ R( x
** Output - Serializer Tx is connected to the input of the codec
! _+ L b5 k8 O; K*/
# G8 A0 r6 P9 W: Q5 Q; QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ f7 T% Y" M. B) g; q. C- ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ D( w1 T; z5 R5 b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' o1 y+ j/ x1 }; V/ q! h4 l| MCASP_PIN_ACLKX
/ }& J% q3 T. D+ v| MCASP_PIN_AHCLKX/ @+ z E7 p; C, S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& H+ m7 W! ^5 w3 q! m2 k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 ~1 q; t1 }. y1 {# q2 n e| MCASP_TX_CLKFAIL % M; k: t2 H# K, C8 s5 C
| MCASP_TX_SYNCERROR
- u9 a" Q8 O6 u# j- }0 N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. h: V; V% q ^- h; k# N| MCASP_RX_CLKFAIL
' [( G$ y0 a, p& G8 ?! Z| MCASP_RX_SYNCERROR $ v0 M8 t: k8 ]8 y" S+ }' a
| MCASP_RX_OVERRUN);
5 x0 F# K' I3 e9 u} static void I2SDataTxRxActivate(void)! Y4 |% j; Q# r* Q5 p
{1 w! ] {2 p# ~% B( f
/* Start the clocks */5 n0 `5 O4 U4 Z! m7 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% k0 S5 c( L! e0 c7 t+ QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, B6 o7 x5 i' I& iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
e' W n: l# t$ B( \; y- P% qEDMA3_TRIG_MODE_EVENT);
* V, m' K# I7 f8 r- |8 R" M. k; aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 M8 a; e! ]+ J* S1 d; F2 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 b; Q) z+ _% t2 u9 j& W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 s5 J _- K( z0 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- V t' T9 u) x5 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; y) Z( g( [& g/ |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- u, I' H" V% @. ~9 \/ g% qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' C) @7 s3 g u/ h
}
( ]7 o# u& t3 G, ]$ g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & |: B; S' y3 q
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