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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 I9 C4 U; N p% T8 cinput mcasp_ahclkx,- f- r% H4 M( L, ?
input mcasp_aclkx,7 s* U8 K p4 B7 y8 v4 R- ~9 S
input axr0,8 V2 N# s' c8 x9 P
% l: z6 p' E1 Z/ A& y& w1 Moutput mcasp_afsr,
! P- L7 F0 u* T; E8 S, ~* u @( qoutput mcasp_ahclkr,
5 v; Y4 m1 u$ Boutput mcasp_aclkr,
. X0 [, `& ?% L6 M( R& L1 H% |output axr1, B) }+ n3 w; e$ _ n) x
assign mcasp_afsr = mcasp_afsx;
$ T0 o: x) a* p" `: k! bassign mcasp_aclkr = mcasp_aclkx;
* {) ?. @9 m% P( y: \& Gassign mcasp_ahclkr = mcasp_ahclkx;
8 I! k; ~% A' N2 A7 r/ v4 Tassign axr1 = axr0;
2 e8 R, s4 L- b- u2 L8 b$ W
# R4 ^( n- n5 S- C% ~! y. a# f9 h" ?5 V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 x! H" p6 Q- Q7 q2 M9 n& _& d; }static void McASPI2SConfigure(void)$ _2 E" N1 {) A, F4 S
{
' r' m }9 Q5 ~ o* L* Z' SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ ]9 p- c( A( R# u, T4 ~( q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 X7 K j* [! P4 XMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ y, f% X4 U l4 b% ?1 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ p& X( G4 f' ] e" L3 q9 c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," N- }* v2 M/ y& |, B; o# ?# w
MCASP_RX_MODE_DMA);
1 H+ H7 }# W: y0 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ]" M9 p% J' w0 Z( M3 d' i- ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" ^4 p6 R7 E8 P. Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 m) J+ H' O* U1 T3 [4 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; i) d @% i9 M- H( q ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 a; @( E- p/ [4 L* b! x( e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" a0 v$ f0 V( i- \' v% IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% r" A5 V. L) ]2 S! U6 l% @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 B: `0 V7 q8 q9 O9 ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! }3 v- s z7 V0 O4 z0x00, 0xFF); /* configure the clock for transmitter */- n$ a1 i% d. V' D6 ^+ S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 v$ ~* ]* {: Y+ r) k+ w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 b) b6 @ H5 A! M* R+ \8 n6 {* n/ bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: y- r% u8 M W' H w: N
0x00, 0xFF);
# V6 }/ e: d; }/ p3 Q
+ {5 b4 i X1 F3 h" d& ]/* Enable synchronization of RX and TX sections */
7 T9 E1 g! ?5 D/ I& y) W. l+ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 m0 i# E7 B; c" @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: ?, ` [) ~) w) U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 s8 }' `" T: q: q! _' G& u** Set the serializers, Currently only one serializer is set as- ~" F& n2 G) A- J& A2 [" }
** transmitter and one serializer as receiver.
9 g' C8 K/ Y4 m5 u0 a8 o4 s3 V O, P*/
- _* i. N) m) U3 E3 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) D; ^# S, `% A' n8 D9 n/ K5 ^, [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) j1 K3 v2 |& ?1 x6 X' A" Z" K** Configure the McASP pins
5 l+ ~& l3 ]8 e% M/ g. @: m7 F** Input - Frame Sync, Clock and Serializer Rx1 ]1 O9 H. l' f+ ~; {
** Output - Serializer Tx is connected to the input of the codec : S2 U/ a% U* e& b# k! X) P
*/
L' C8 U2 w% z' P4 FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
k I" K/ S+ m$ fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) @7 z! o# X, h6 T9 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 u# P+ a5 _% c% C
| MCASP_PIN_ACLKX' j/ B/ s3 v. h4 q+ S" G; \
| MCASP_PIN_AHCLKX
4 h, r. l0 c" b8 G' s k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, S8 ]; J8 `( n0 o3 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. s% x' n8 w" t, m| MCASP_TX_CLKFAIL 7 ]- G( X' p) ]' m% ]
| MCASP_TX_SYNCERROR
0 X% j: A- l* Q3 o8 X$ ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 t: {1 ^8 t7 H0 e5 v& N| MCASP_RX_CLKFAIL0 V/ f& e, h4 P) X7 H
| MCASP_RX_SYNCERROR
6 E: X/ w& b3 M; G/ ` [| MCASP_RX_OVERRUN);
0 v; V& k7 k9 S6 d} static void I2SDataTxRxActivate(void)* z2 O+ C5 _5 |4 [1 D
{3 U& C$ C* [0 s" T
/* Start the clocks */( ~+ M+ O% `& l# ~7 K6 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ ?$ U8 j" u! OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* @8 m; m/ G% R* u) t( q4 G( P( E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 ?# M l7 M N* f
EDMA3_TRIG_MODE_EVENT);) p( t2 K' L" v' E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. A; \0 W" F$ Z8 {% ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 _1 M% Y( l, g3 y8 @4 mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 E9 x8 ^, i! \/ U: X! z7 {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" y2 g0 R' Z7 i! b* t% _0 m- b3 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" B8 O0 l% [5 x+ l! ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# ~' {; J1 w" @) s) {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 w1 p$ \) ?6 J1 l}
8 J: k+ V4 v% u5 ~) V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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