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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! i# t6 R' [! |+ J
input mcasp_ahclkx,
7 z* e% S+ L. `3 z% Uinput mcasp_aclkx,. }& D; @1 h) W: d: x9 F
input axr0,, L( V3 B$ c$ \. b* d
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output mcasp_afsr,
g' {8 [6 C1 Uoutput mcasp_ahclkr,8 Y W" a5 [0 m7 }
output mcasp_aclkr,
. @( {4 I; h8 w+ Voutput axr1,# U/ u3 ?$ D$ A# X8 U* P6 i
assign mcasp_afsr = mcasp_afsx;
6 p9 s4 l% W# B0 W$ l5 ]assign mcasp_aclkr = mcasp_aclkx;
% K M K( f3 I8 Uassign mcasp_ahclkr = mcasp_ahclkx;1 a- b, H/ l( f+ z
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . ^ x* a! M6 Q' d2 K
static void McASPI2SConfigure(void)
8 j0 s8 x& O5 K0 D/ l9 D{
" G$ @, d7 ~' T0 y# A5 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 r3 p n+ C3 S( l: n# c; I* J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 b7 Q- o" W0 U2 g2 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& l, H6 r/ o" q' }6 K$ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 ?! [2 k' X) v8 F, k! x* VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 D" R8 O8 J4 B/ XMCASP_RX_MODE_DMA);
6 M7 t# S c" P3 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# W6 u J- ?6 z' |7 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ e) Y6 ]* `- e0 {( |: FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 B6 ? E4 x/ i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 K. y5 v" [1 i q! bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ O3 r a1 u) P$ q' S3 U r5 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ ?9 _! [+ V7 \% k( W( O3 a% d0 i' N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! }, F: n# ?, dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 W) s5 t5 J& tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' W1 `9 F' O# q/ {0x00, 0xFF); /* configure the clock for transmitter */) w+ J; F# j6 W+ g: y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); [2 }7 i$ N% w" d2 \: u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ D) {: P6 A2 k, s4 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 ?0 e/ x% i7 F1 F
0x00, 0xFF);/ _) a* w8 h7 o- K1 n5 Q
, z; \/ O8 q4 e3 y
/* Enable synchronization of RX and TX sections */ o; I5 w& T4 z/ l. f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ I7 Y5 `* b/ m6 S0 T8 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( n9 z1 z6 N4 Z" l6 r* l4 C L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 A- H, X& f: a0 p* N/ M
** Set the serializers, Currently only one serializer is set as
3 \. H. W1 F+ L h) |2 H** transmitter and one serializer as receiver.
5 M5 f" ]4 @% u4 f" f' P' T8 K* x, ]*/4 C8 K5 }, n% V3 e' X( R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: Y$ Z6 K8 |7 b& m! ^+ P% _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 z5 ^8 V* H! E
** Configure the McASP pins 3 ?* S' ^& s" z3 E; s5 I/ ^) |
** Input - Frame Sync, Clock and Serializer Rx
& A( w* V; ^& N" N+ ]** Output - Serializer Tx is connected to the input of the codec ) Y# f$ c" r. l+ @ J, W3 v& m. a& Z
*/
. |/ D. f9 B7 |. f4 CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 M% E! ~% c X& i/ w. c3 C* D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) m0 I* ~& w: |$ OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; M- p9 j- S6 m4 Z. V* L( F| MCASP_PIN_ACLKX( w8 T& t; S; y2 j% A( d( @ K
| MCASP_PIN_AHCLKX7 w" Y) d( P) {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, E0 ~: ~7 h8 w( N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' `, b% D; ?! O2 W m| MCASP_TX_CLKFAIL 8 D6 p7 Y# U/ b( H/ I$ e
| MCASP_TX_SYNCERROR
2 m! ^6 u1 P$ M! h2 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% J# Z# v6 E8 z0 M* n% R+ f7 [' o| MCASP_RX_CLKFAIL
7 o& ]' Z7 {3 M( M+ H: r7 c| MCASP_RX_SYNCERROR $ q9 I- G1 n3 U- E$ A, }+ j' P6 D0 k
| MCASP_RX_OVERRUN);
5 s* C: S3 B! ~- J1 k& {+ u} static void I2SDataTxRxActivate(void)3 k1 E. P5 O% ]2 F1 V3 h
{
( e* P+ }0 ~/ d2 O p# O/* Start the clocks */
$ Y* w" V* k: TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); L* X2 [. B- c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 A* ~) Z# n" m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! J6 F% f7 f8 _, I$ B+ s' d9 W/ gEDMA3_TRIG_MODE_EVENT);8 b6 @. D* {* L) N* Q8 C2 I1 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 b9 v0 b+ N; V& M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& a: V) L& k, u0 h" N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* I5 p% j) I* T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 s- j/ |% t- H0 T, |$ owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 v* h3 J* N9 y! jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 s: x1 K- X; z. ^8 GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( f# x. N# d7 F# z, w, g+ I3 O}
8 s+ n1 x& Z4 v8 L' {& ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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