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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ Q0 s6 i, N- A8 L8 a* T$ C/ @# D; \input mcasp_ahclkx,- Z2 ^: D- Y( O' f
input mcasp_aclkx,
* r4 W; [& h5 B: S( Linput axr0,$ T# D6 K1 A1 B! y+ a' L
( L% c( [1 T2 O1 Z5 v' }$ |output mcasp_afsr,1 w7 {4 g' ~! ^% f% I
output mcasp_ahclkr,1 J, I( ~$ L4 i. x6 p# T0 d. T
output mcasp_aclkr, U% P$ X( K6 e2 t$ L# F! o
output axr1,! i( l& s& q6 i
assign mcasp_afsr = mcasp_afsx;/ M- ^+ \% S$ v1 v* _: O6 C6 M
assign mcasp_aclkr = mcasp_aclkx;
; k* W: U$ Q# Y: U& v; wassign mcasp_ahclkr = mcasp_ahclkx;
0 h) u( |1 j+ j5 n' f+ o6 k% r& Eassign axr1 = axr0; ' z0 o( z+ X1 |) t% H7 C
- G" [9 _/ {1 c4 x. Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% M7 g% B0 \ ^( E: o$ w" W8 Estatic void McASPI2SConfigure(void)
$ ]+ r# p3 f2 z3 v3 S) [6 `{
k$ r r: C) T/ D8 p" t- ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) S- b7 Z( ]' J" ?( c \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
\; T$ ]' D0 X% F& \2 kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, R/ b& r: N1 i7 M" f. y/ fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; c9 b$ G+ @ T0 E6 @8 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ O' e6 A g% `3 ~! U- y% e9 A2 dMCASP_RX_MODE_DMA);
5 @5 {1 W$ h0 @; c0 l- ~* J. dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," g; B4 U0 f: q; O: x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; i5 R! l3 O! J" N: k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 f6 Q- v& M& g* }3 }, e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! C5 X, X, R, \1 e% w$ a' [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% U% A% G% O6 mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& f/ L( }( A. s: S RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ }6 M$ C' d- L. n# X L3 v# c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 k# Z3 k# @" K1 ]8 U: n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( W% W/ A5 q; N4 b0x00, 0xFF); /* configure the clock for transmitter */
& I- C" V& k# \7 V, kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
S7 U. P4 C. `$ \' h; C& iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ X( R4 M% s) J: W7 X8 q, ^, r$ I8 Q4 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 W" B8 B9 r h! x4 `
0x00, 0xFF);7 l9 {2 @3 J$ b# D
* {8 l# W+ [: R/* Enable synchronization of RX and TX sections */ ' J( N0 A7 T4 [: o/ x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 j6 B7 v4 w+ n1 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* O% l! J2 m! I% M5 @3 o# |7 R7 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 p$ P/ b2 E1 K9 I Z( v** Set the serializers, Currently only one serializer is set as/ Q1 P+ F4 Q9 ]# y0 |
** transmitter and one serializer as receiver.8 @3 g* M! T2 \4 Y% ]
*/ j+ _0 \) i) m' z" _7 l% F! n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! t. g: x- {) k) n7 r7 s. y: T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 d, H9 ^/ `( ~# M. V
** Configure the McASP pins - }6 ^3 f* m8 U5 s6 y7 u8 j
** Input - Frame Sync, Clock and Serializer Rx5 m+ Z4 M: e6 q% X. x' m
** Output - Serializer Tx is connected to the input of the codec $ b9 W2 s, ?1 a5 [4 ~5 o5 D6 t
*/
. ?+ ~7 U: z* Y$ K/ u/ L3 K! FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# [" X' d. {- S+ W# M- _% IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); I! H$ i& f, l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ R' a8 E# T* o5 k3 D| MCASP_PIN_ACLKX: l; g0 ?' F2 U' J# V/ S
| MCASP_PIN_AHCLKX4 f: `" q* }/ c! f2 h5 d' D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
R' c) ^7 N& ?1 i8 E6 @" a2 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ v6 z# y/ }4 R X- D P( S| MCASP_TX_CLKFAIL % q( B4 Q7 x# {: ]2 R \
| MCASP_TX_SYNCERROR
* Y5 q) e# G- \- y% c1 d6 D, ]3 J' ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, X4 r- b9 W, r- |) v) `9 o| MCASP_RX_CLKFAIL" U+ }4 z5 A$ w9 _) S
| MCASP_RX_SYNCERROR ( C, h1 X" G/ G2 V( ?4 s& {6 {, d
| MCASP_RX_OVERRUN);, ]3 X) [+ k4 o* f
} static void I2SDataTxRxActivate(void)* K1 {" O: H2 ]& S% y ^1 S
{3 a+ ?. R% P3 J/ n* V/ ?# H a
/* Start the clocks */
/ ~; U5 m, M/ v3 jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 g6 L Z, i% o" r& qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. V; `( b% l/ F' p& G$ ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 C5 @: G& v( j7 M- nEDMA3_TRIG_MODE_EVENT);
6 S% b' t: u7 T' j z* pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, E- I( k: j$ W* PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% j, ]# W, V" w, l0 ?% l& |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 L6 ~( V# N2 r5 W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* w; ]0 Z l$ E4 b9 p( \+ J. F: ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ c, A; }) @$ B+ rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% c( a% ~) m! s5 i/ T# Z3 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) ~5 C' R1 Y4 x% f2 `, @
}
: \, P0 W# `0 A- M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
" h! \* k7 c3 f& W2 E$ Z- ~; v |