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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- ^+ N7 R J# s4 C8 w
input mcasp_ahclkx,
& ]# `1 p0 i0 {2 \8 Q/ N: |$ Iinput mcasp_aclkx,5 {7 S: v) S/ n; O5 z$ t
input axr0,: [! k; P) \3 i
' e3 R: ^+ V0 l8 R8 ], o
output mcasp_afsr,. q; m+ h; J, w0 _
output mcasp_ahclkr,
& ? A; N; u1 Y* Z; U- soutput mcasp_aclkr," r" O; |4 D; e- d: z& [! v
output axr1,
# c' t/ K) o P- o+ k! f assign mcasp_afsr = mcasp_afsx;3 J0 M# N5 k/ O# Z( R
assign mcasp_aclkr = mcasp_aclkx;
$ L5 @6 e* q5 R$ z8 kassign mcasp_ahclkr = mcasp_ahclkx;
. @/ e, I( f/ \assign axr1 = axr0;
2 W" b* @ _0 z; D2 u+ m/ m, e I5 M+ X2 a& x m* E4 f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 k0 k' H: O, h4 \% Rstatic void McASPI2SConfigure(void)
' G6 _( a8 t( O0 ]& Z{% |$ {! B+ b9 D7 r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# V: X0 i/ p: `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: I* }2 Z4 T& P. bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 n1 X" z* u9 o5 U! b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. D( S% Q" R( v4 \& }% P9 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% g( T4 D1 e4 s& H& _
MCASP_RX_MODE_DMA);4 {$ y3 ~9 J% x! a B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( v( M' i% ~, g5 f1 s$ v/ `+ tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 ~- y& g2 D! _: K& i$ b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ F$ J1 j/ l3 K5 p4 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 O. `! v! d! _5 s1 m' D6 b0 C) C/ hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * c1 d5 A- [9 |( j' ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: _3 \7 d0 g a# `" \) z4 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% X1 n+ E$ T' P, WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); N+ o. N5 b! [5 K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 D T7 B2 m& P5 s# L
0x00, 0xFF); /* configure the clock for transmitter */
; C% }( W' T' O: w. ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ m) v! ^$ f4 ^/ e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 w! |/ v- f9 N' RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 S8 V& q3 S5 D2 e$ n% g1 Z' w3 X0x00, 0xFF);6 d0 y1 X2 p9 w6 B
( ]5 {. r7 ]( g- n/* Enable synchronization of RX and TX sections */ & p" s8 @0 U% f7 R" j" m5 Q0 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ J" Z0 G/ A3 m- kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 J+ q% z& j1 L& B. I9 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' d# a- X0 ^+ ?+ V1 Q% ~+ d+ }
** Set the serializers, Currently only one serializer is set as
& f! I: a- N. q# q- p** transmitter and one serializer as receiver.; M1 g7 O5 j5 J. f4 n& w4 I. n0 y
*/- l1 i7 I! P' G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 r: H; f6 {# a1 m4 ~* @; D7 c+ @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 O4 k1 v' I1 p! g. \** Configure the McASP pins
0 L8 Y3 l6 s* \' |; T** Input - Frame Sync, Clock and Serializer Rx# s" @8 X# D8 c; j c1 r
** Output - Serializer Tx is connected to the input of the codec 7 }0 T; V" s! M6 C9 g& ~8 w
*/- s- |' e8 s4 o7 a6 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 z) V2 {5 N4 y: R" q' q/ C. M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( D" I/ `( F$ d4 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 |- ?5 d: W7 d& E: S0 J5 i
| MCASP_PIN_ACLKX
8 O9 t1 @5 G2 ^& m7 n' c| MCASP_PIN_AHCLKX
9 w8 [, _3 G0 V, |+ c- l, t/ m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. b: W) U( r8 ^4 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / U7 G# U) m7 v! k) @) F2 }4 t
| MCASP_TX_CLKFAIL ) b2 l. F: o: c9 X5 x0 S+ m- Z
| MCASP_TX_SYNCERROR
0 ~9 v8 m) {' n9 r& L0 I! y( i/ d9 E% T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . z2 j( K5 { M h% q
| MCASP_RX_CLKFAIL& n+ h! v W7 F) ~1 \
| MCASP_RX_SYNCERROR & ]1 [; t" s N8 G# q! V/ b. y
| MCASP_RX_OVERRUN);
: f2 J/ X0 j3 v, J0 L' Z2 z `+ q} static void I2SDataTxRxActivate(void): ]0 h6 x$ S! I1 E$ |( W/ |
{
" k/ |8 q3 g2 i3 e( A/ g/* Start the clocks */
" f8 P" V3 V8 w0 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 Q5 e+ g) U2 o! o& V1 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% c( C' k5 i! z& A$ d9 l2 D; n }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 y4 S \/ b' E+ z6 l5 s7 ^8 l/ y
EDMA3_TRIG_MODE_EVENT);, v. g' g. e4 M' o/ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 h; J; K. g ?$ [/ J% e& s, k: E; kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ J6 l4 j; s& E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* {, i- B' z, GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ R: p& @2 V; @9 E3 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 g% W4 |% Z2 ^9 z! } i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 \, W/ p) r( ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ L, p' W% P% m W, e1 P
} 9 K7 n) I3 {5 A* v- U8 Q s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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