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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ w2 C: X" r7 _# f/ e& h/ }: E
input mcasp_ahclkx,: E. ]8 ` ^4 j) m# u$ W
input mcasp_aclkx,$ o' a2 V2 |) v# k8 m" G+ v9 f3 A
input axr0,
5 `2 T1 \" P6 Q1 b" l( O1 |5 W7 [1 C1 O
output mcasp_afsr,, |: g6 [$ r8 n/ Y7 z7 q$ i
output mcasp_ahclkr,
4 O$ Z# I/ Y9 U8 ]( youtput mcasp_aclkr,# J' o" g6 m) r9 w
output axr1, f* D- j+ g& | z
assign mcasp_afsr = mcasp_afsx;( l% H n% m5 Z/ p6 d% z) {9 p
assign mcasp_aclkr = mcasp_aclkx;0 u' t5 `! I# x# F0 h
assign mcasp_ahclkr = mcasp_ahclkx;
! w9 B" p c- X4 }, \9 ~assign axr1 = axr0; # [) @9 x6 h, S/ X# Z6 g
& F0 C) u( O6 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 }' Z3 X% b* v, g1 Z6 v
static void McASPI2SConfigure(void)+ \& g5 Q0 d, r9 D5 H% J" Y% x
{
1 K( B6 Q1 h) Z, o' xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 N4 S+ W$ y( H4 H1 f2 V2 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" b7 ]) J# I2 w3 R9 i, JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: e" O% l9 F9 |& `* z5 ] e9 A3 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- n/ J: {: r, X5 h3 B% dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ F! L% h5 m* B7 ~2 \- S$ `MCASP_RX_MODE_DMA);4 V- U7 y- @+ _8 c h! Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* B4 L" f/ i7 _; x% b+ uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 ^ H8 B8 \0 K h* b& Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + w5 Q0 R' `1 q0 R) ?# [9 H0 s: ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( h* B- T) }* p7 h& \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 }8 |5 |6 s, N+ B( w ~0 _8 V; JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* {5 g0 z% C& A+ {4 s! UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 _% T6 B4 Z* L( Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! a& q; f3 E) t- ^* `8 c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 p1 U0 T+ ` H0x00, 0xFF); /* configure the clock for transmitter */2 k) }+ Z: q, Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ e: ^2 O) x& g5 j7 B# tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' I( ^3 o$ k3 |! j& A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ X6 s1 R, I4 x4 ~% l) v7 t, \
0x00, 0xFF);6 A& R; S, q7 k6 [+ G# U, B6 w
1 T9 {% M" D7 n
/* Enable synchronization of RX and TX sections */ 0 D! P+ v/ h) `( P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% f+ Y) |3 Z) N' ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 [4 K! V! P$ s! M: L* HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ X9 {: ?) e1 D/ i4 W3 c
** Set the serializers, Currently only one serializer is set as, R4 i- f6 H+ {
** transmitter and one serializer as receiver.9 W, d8 C8 P W# p# M7 Y7 `
*/* X z# U7 p! A! B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* l/ b& ^& e# Q# c7 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- ` q# j& [: ]8 T' D+ \** Configure the McASP pins % N( v. ~0 N, W2 H
** Input - Frame Sync, Clock and Serializer Rx
9 r' c8 t- o, E2 P3 W** Output - Serializer Tx is connected to the input of the codec
8 w( n% C- h- ~9 E) j*/
+ }5 O J4 L; \2 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' z! Z8 j& s+ J! _; \* y0 X c% OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 f0 H. g$ ~8 n+ a* pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 s9 f) t9 i9 n, p4 o, U| MCASP_PIN_ACLKX* K. ], Z3 U7 X' s$ ]9 ]3 r1 I* z; s
| MCASP_PIN_AHCLKX
4 \ u* c: G m. g5 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- Q4 j" H) z/ f. i+ O( p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! {6 ?0 }* J2 ?. z4 S5 Q
| MCASP_TX_CLKFAIL
, h5 g5 ]1 R7 |/ [( G O5 s# M| MCASP_TX_SYNCERROR3 e$ K- @' l- [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; {3 _2 w5 ]: l6 X. j# Y| MCASP_RX_CLKFAIL
9 \3 n) i0 V- S! v| MCASP_RX_SYNCERROR , G9 [) Q* j. H$ T* B3 S/ d
| MCASP_RX_OVERRUN);3 F3 f( B. l7 g& u: G
} static void I2SDataTxRxActivate(void)
8 \$ W- L" x2 ~( K$ g% z{
" Y7 L, B i3 T3 U, d7 T0 K2 ^* [/* Start the clocks */
5 y; z) q7 {8 @" X4 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ p; b& Q4 R$ A( cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 V0 @! ?0 o s! s2 x' L8 A$ {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 V1 z; ~1 t- F" `, F2 w" ]
EDMA3_TRIG_MODE_EVENT);
/ `1 f' V5 X9 T2 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 k8 P- h! z3 ^, @ P8 i+ m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* a4 @3 Z1 i& V; ^$ C- ]: x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 o! n0 h5 A0 A5 B# nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# R4 t/ f: d* c( r' A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" }- f" M" ?4 H l' gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 d4 a3 Y- e5 m% T- a# {# p) _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% p/ ]9 A# C8 Y1 j6 ], D}
" y C$ ]" @) p5 H" Y/ v2 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + [: N' t. P; A( d+ `
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