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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 F2 M/ \7 f# a
input mcasp_ahclkx,
, W& M( S" z# k; Z; a ]8 ^. N B5 ainput mcasp_aclkx,
* m6 H# P& u a/ zinput axr0,& n! y+ q) X* B- _* s# K9 {
/ }& V9 m$ x3 C s% d. c
output mcasp_afsr,
" @: m; s+ k7 v, c1 p, Foutput mcasp_ahclkr,
+ Y G4 J' i) I- v8 l# z$ Q* T0 houtput mcasp_aclkr,
* x, A) h, Q4 E6 _/ b3 woutput axr1,, d; k( O+ L9 y: ^5 b/ ~
assign mcasp_afsr = mcasp_afsx;
0 U4 ]7 V/ [2 o, ~2 I' l( aassign mcasp_aclkr = mcasp_aclkx;0 b( y& Z6 T9 P
assign mcasp_ahclkr = mcasp_ahclkx;
% O9 n" |4 m/ h$ i9 r3 |3 e+ S% Wassign axr1 = axr0;
/ y. x) f7 T9 u! C2 c8 D/ Z4 w- C; I2 L% _' }- m- w6 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: O1 r9 n! h! K4 r8 U2 v! q& bstatic void McASPI2SConfigure(void)
0 w7 ^3 w! }/ m- n5 ?* l }{* ]! T- v& \2 \2 z j+ n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, X0 x$ f9 x1 C' f/ N6 X$ e9 PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- J* o b! D3 L1 c1 u# w+ xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
V6 u) O8 R' U5 W5 K, OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! P* u& _& A; M; \/ o9 m( w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% J, {9 n/ Y- G! ?" HMCASP_RX_MODE_DMA);) H, T S. ~, ?8 k: C, j, b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' G3 [- @1 T5 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 @1 m. Z! X- T/ p3 J8 m$ D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 p* X. `1 C- @5 A* K- Q; nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 S e; Z* n' [, n4 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 |; k# u9 K% }+ c. l5 u0 y) ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ }( u1 |' y* S5 M" d4 O% \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! N2 a( N, l5 T* h) h- p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - o* ]/ e' C* o4 j8 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 W% F2 n$ u! {. W7 x8 `" S. s0x00, 0xFF); /* configure the clock for transmitter */
* T0 C2 L+ [' l- O" `2 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 W2 k5 U' C: CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- L1 M! R/ M2 O' QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 \. }9 ~8 O2 I' Z3 i( R0x00, 0xFF);
5 J V# b: n; C1 o1 y$ W6 V
* ~, t9 o0 k4 x$ x. K4 c/* Enable synchronization of RX and TX sections */
& r+ X- I9 S! G. O& ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 w y- O" d3 c3 g$ aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ a0 r" q0 g9 v& s' j" |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# O6 P( A) m. s L! n** Set the serializers, Currently only one serializer is set as
1 c- g" |. i% L$ s ~** transmitter and one serializer as receiver.8 c8 _* K$ `' W6 Y' s
*/
& S- Y0 f) H! k z0 h" P+ nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 m) }% l) c/ G4 e+ z* [! c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* j* O: P, r6 G8 `8 e** Configure the McASP pins
0 G# q/ n4 u$ T+ L' S** Input - Frame Sync, Clock and Serializer Rx% Z0 M; H Z8 u) R
** Output - Serializer Tx is connected to the input of the codec
2 D/ R; k$ f' f) D+ e. ?1 i*/
7 Z, {7 L$ E7 X( n) oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 m, ~+ J( _# A* J( Q n6 ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ R5 H F3 q% ?; y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, V/ y4 z9 |. `+ t' M+ q| MCASP_PIN_ACLKX; E" k2 F3 A3 M; I9 g; a/ q, C
| MCASP_PIN_AHCLKX2 ]! k$ [5 e5 R6 x$ p$ Q3 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 y; z) ~0 t& G' h! O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 c A! b4 i7 S C| MCASP_TX_CLKFAIL
1 {$ W% z' ^# j5 f7 E| MCASP_TX_SYNCERROR* f/ b8 `- z' w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( N9 y5 x6 z5 \1 _, H| MCASP_RX_CLKFAIL0 p3 |; L/ U6 K5 s" c
| MCASP_RX_SYNCERROR
8 n5 y) g8 O/ ]& f. o2 A| MCASP_RX_OVERRUN);
5 W' [! N5 _& N& V9 h3 x} static void I2SDataTxRxActivate(void)" \* _, _9 u" e1 j
{
' E% L% O5 ^5 \( Y4 V: V$ y1 G' m/* Start the clocks */
, |5 @$ z# ?- R( P2 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' y$ D' ]( ]3 Z! T. f2 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 j1 n$ P4 E0 f# t6 H7 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; m! q( P4 e, t: k# n$ YEDMA3_TRIG_MODE_EVENT);; ]3 j' f/ a7 {+ ~0 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ~' e& K0 T: B. B8 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 k$ Q# t2 F" A9 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 f R! U0 y ~% q0 x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) a2 \' C7 @) ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ ^; _( f7 q' T9 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; o$ D$ ^; Z0 i3 N+ |' ~5 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" C/ q1 U* n/ q0 L0 `& ^6 L9 ^) f- u/ R4 `}
. @' E) N* v& I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; F4 b# g7 H7 L l$ |8 j' s |