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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; M+ n: u: ]# M* b, b
input mcasp_ahclkx,
$ p) P& F0 F( [6 binput mcasp_aclkx,: s% [' Y+ ]' X. `% p" G0 J, X
input axr0,
/ q3 X% @, v& O& v6 ~4 X1 v/ q) b7 g; ]! J/ A+ X* g; Q9 F# i
output mcasp_afsr,
. W/ j9 b* e) X( F4 L2 u7 A& w8 Ooutput mcasp_ahclkr,2 _) f; J/ t. C* W a: Y U s9 H
output mcasp_aclkr,0 ~1 f- w5 x7 b& ^) l( l
output axr1,
; Z, v! p8 T) T assign mcasp_afsr = mcasp_afsx;, C6 ^3 z3 F% _
assign mcasp_aclkr = mcasp_aclkx;
. U$ W$ B+ M+ passign mcasp_ahclkr = mcasp_ahclkx;
% j: i) u3 h; Z5 k( z |assign axr1 = axr0; , r* b; n6 [: {0 k$ w! i8 Q
6 M5 U, S( R2 \) `5 e# Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! N5 D% g5 X/ v* r0 {) ~8 p, m
static void McASPI2SConfigure(void)* Y+ g X8 H: a/ ?& G" I) c' p
{
0 v# t) k( ~3 V2 K7 b, M- RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 e% u" C/ s. P$ B& vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
K* ~: q/ h! E2 `) Z1 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) ?% v1 t' E% p! T5 b5 D+ D3 XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, {3 O! }9 Q- @6 `$ s$ Q' L8 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# t2 @ k3 p" z" a' S/ `
MCASP_RX_MODE_DMA);
$ }) ]/ W6 E" Y+ G3 S* \2 j! B$ z+ aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& g1 |6 w1 s; g+ F8 \' f* tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! h/ u% E1 V: I' B. ?# |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 _) c* m2 L2 k0 [! t# r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 K' b1 L$ z5 L8 s' {1 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) R# U Q' `. z7 q. rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. g1 h7 z) s! X/ o/ H! n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 g: L' p9 n) q4 }6 f6 C8 kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( `" q6 o. c8 K) C; ?/ LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 [/ U/ u' P x' B0x00, 0xFF); /* configure the clock for transmitter */
* R3 {+ P9 z, i) w% I; EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* L( X9 l3 m2 S% z: u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 _) {" y8 i; t7 y) V* j, F' DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% b. y, x- A# x$ i. ]
0x00, 0xFF);
" G6 W4 W/ ]4 i, n* _9 I& k* c+ p& k: g1 M. ?4 |4 P/ g
/* Enable synchronization of RX and TX sections */
8 T1 T( W' G2 p9 k3 V4 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& k4 @6 W# c: Y4 S% @2 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) p8 `6 q# | X0 V. e& k# Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 D: M! m& F! s5 o F9 c2 u9 ^6 n
** Set the serializers, Currently only one serializer is set as
3 ^" C" H/ {+ G5 V) g K! N** transmitter and one serializer as receiver.
, A5 k& |/ C3 P+ z( X/ F' n$ `# c+ K*/
* |/ `0 A: e2 j0 P* B/ `2 o" `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" K) k1 U+ M. k: u4 B2 B% J7 s" W, xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) s F0 ~' W0 ]- R! J; Z& z
** Configure the McASP pins
3 }* R" L* f. z6 Y9 M$ E** Input - Frame Sync, Clock and Serializer Rx3 c ~) ?* B6 q* T# i
** Output - Serializer Tx is connected to the input of the codec 1 R$ s. g6 l; \/ E& ]' I
*/
+ y- B$ q! b* t2 g% t/ T4 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 Y& }# r0 a: o mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 I, G# z& f* R5 c0 v; `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 c0 x6 `' n( i8 W' C' m7 c2 Q| MCASP_PIN_ACLKX
! n) U. _4 t8 u3 ~| MCASP_PIN_AHCLKX3 n& i7 [% H/ I4 c% E% p: k( T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 W) |2 Y9 d/ w: c% x! tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 s) v& u" Q. ^- S) L
| MCASP_TX_CLKFAIL 7 {( n, m3 N3 |$ P' b+ A, ]
| MCASP_TX_SYNCERROR9 Z9 k1 }& ~/ q# X7 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 L6 w: S* t, e; E0 Q
| MCASP_RX_CLKFAIL& s* l9 H* u8 U
| MCASP_RX_SYNCERROR
3 M: Q' Z# w9 N: R+ c| MCASP_RX_OVERRUN);7 N9 P5 T/ `9 Z% ]) b
} static void I2SDataTxRxActivate(void)# o4 C8 u: u1 r2 e8 h8 J! e2 _
{4 `. O8 s# i- Z; t
/* Start the clocks */
2 |" t3 H W% D) zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 _( a" K, c Q6 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
Z: a! N1 t- {& C6 x' wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 ^9 x) ]+ O! M. e. O
EDMA3_TRIG_MODE_EVENT);% ?$ h* d1 w" v1 i0 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " g+ `, \+ K5 o! R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 m$ D. u$ H" m2 L2 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 ~! b; n- r& T0 o# r# W0 L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" Y0 } Y& t$ Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, f' N+ R6 ]7 q* j% OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) N; e1 ?5 L: x- H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 }' {8 W% M' G$ M' z/ c} 1 S- O" }5 ^9 N: ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , T* N3 M8 Y) X# G" s; }) T; F/ ?
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