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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! C& t9 o- Y: o; t5 @
input mcasp_ahclkx,
) P1 `8 U u' _6 u/ }: ~1 Zinput mcasp_aclkx,
0 f: T; u6 a6 K+ h0 Ginput axr0,2 W( U, m1 G+ M7 e
: {' z4 y- w2 d+ w# W+ r& }& n* _8 x
output mcasp_afsr,
, d6 P/ u- E- V. woutput mcasp_ahclkr,
# l& S3 y. J: M( Woutput mcasp_aclkr,
9 h: h' D! D, n8 l+ l/ noutput axr1,; e L- C7 W o5 a1 v& a; B$ l3 ?
assign mcasp_afsr = mcasp_afsx;: k" E ?- w& w# V6 a
assign mcasp_aclkr = mcasp_aclkx;
* U: l) N) k3 _0 J/ X. z/ Massign mcasp_ahclkr = mcasp_ahclkx;
( @) K5 N& ^: F. @1 F5 f8 W; wassign axr1 = axr0; ' g- ?( N9 L; y2 E
: _8 G5 d0 S$ q3 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 g+ S9 G6 i. Kstatic void McASPI2SConfigure(void)
4 o& O+ ~1 F/ w) v* V{
5 Y- i0 b: ~- n( {3 uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 q* L* K2 P4 y% G) b4 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 J0 k" t" ]% e: p# ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ Z' k7 U& Y/ y/ Z3 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 K* T/ ~- S* R" L+ A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. i: w" @! W+ f( J; R3 Z& zMCASP_RX_MODE_DMA);) u7 y; I8 _6 _& Q. q" E( y5 r& q3 l- v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, H; s/ m" Z8 p3 H; r2 vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* B) x- U- X4 C+ tMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; H% `, T% y. S5 M8 O: v- aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# [. b& N( a( [- e+ D& h9 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 T i8 @* _: Z0 c, f0 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ @2 f; E& R1 R9 T( n+ t& r3 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. D2 H1 ?; C1 o8 w8 X+ i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + q+ X. Y4 P& [2 [1 t, g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 [) q% \; [0 j4 J K! Y4 W+ u4 a* P$ I0x00, 0xFF); /* configure the clock for transmitter */3 f9 G! E4 H, p& Z* P! C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); A' j0 p1 d% u* |/ g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 Q! S- K% U. [3 H7 y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ {; c) G2 o& F# \
0x00, 0xFF); |, c5 U& y6 |. R1 r" C9 c% m( K
& B; H2 j/ `* p0 {' E: q; y) p' M1 `2 c
/* Enable synchronization of RX and TX sections */ 3 q1 S- I2 X. L+ S2 H+ R* |7 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 K1 I, g6 m( q7 {) D9 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: N! m7 @' ^$ g7 L2 \* @% h I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 b: _ Y9 d# M8 ]6 Q: r4 o0 d** Set the serializers, Currently only one serializer is set as- Y. N y, y0 J+ B6 l; R T: F5 ^
** transmitter and one serializer as receiver.
5 u0 m9 t- ?! U0 D*/
1 l2 T1 J! o" G/ Z6 I, g! c. _& Y* GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 ^0 \0 M0 I- Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 K* Q6 K' t# D. q& R4 K** Configure the McASP pins
9 B, d; n/ U' _, v** Input - Frame Sync, Clock and Serializer Rx
9 x6 |/ d6 D' m** Output - Serializer Tx is connected to the input of the codec ( X) c9 B9 v4 h0 N0 h" c' Q
*/
; A# `5 e2 @ ]6 _: TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% ]4 R/ f s2 j/ qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
{. S8 j6 ~2 [1 H. RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX J) m& @4 b) T6 l
| MCASP_PIN_ACLKX' W0 N# J) V' z; E( N
| MCASP_PIN_AHCLKX
! N: r! c0 |/ k- R1 j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 s! Y- I1 d" ?; L3 k7 C; _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' U$ d: H, Y! b" Y( F* h9 z$ ?
| MCASP_TX_CLKFAIL
+ Q% L3 v: ~( _6 t" P# I: O" O| MCASP_TX_SYNCERROR; I5 U# w" _+ Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 b+ |; s' P1 B( D$ l9 O" Q# L
| MCASP_RX_CLKFAIL I0 i: @+ o+ G* Q( S5 |
| MCASP_RX_SYNCERROR ' W6 }% Y$ d3 T" Q: n% b
| MCASP_RX_OVERRUN);
5 z. }# ^+ x. T7 n3 ?- g9 I} static void I2SDataTxRxActivate(void)
: ?% T* L5 n o% X2 W$ H{. Y* p. I& x4 y7 l
/* Start the clocks */6 P& W9 H2 l6 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 r5 m5 O+ P8 M3 w& u" r7 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) G6 _: p$ T+ @- WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 s# `+ }+ z$ r V+ j0 E: G fEDMA3_TRIG_MODE_EVENT);
$ T$ w. f1 ^' hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" _; ~" c( u2 DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 O! |! e0 l6 J- U7 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. b& C# [4 f; F1 P) m9 j: UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# {- X8 @( L' f; r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* B. Z$ |, c( X5 R+ bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& U1 V" ]/ \2 \& I% cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 K2 x) j" } q: u0 Y2 o' ^: T
}
9 Q9 w: W- ~' m' T8 E* R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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