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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 A! a/ A' r% Qinput mcasp_ahclkx,- P: m) |, b& a$ x4 D" i' S0 k" `" ?
input mcasp_aclkx,! c3 P8 M$ e' t* [+ E
input axr0,1 L* f+ \& U% w* M
4 f. @( c, X0 }, m/ x, J* l0 i0 `9 I+ Zoutput mcasp_afsr,
; ]) q- ? c5 u a8 v1 ~2 q( v: Goutput mcasp_ahclkr,4 Q; v9 D m+ y: O" r0 ?, j$ @- t
output mcasp_aclkr,
/ \0 E, c+ D6 ?7 I% I4 Routput axr1,
* ~4 x0 X! s% V: [: u% E1 O assign mcasp_afsr = mcasp_afsx;# J3 [( Y$ V: M1 U7 J2 q
assign mcasp_aclkr = mcasp_aclkx;6 w1 a$ T R3 o1 C; o9 x) A% C
assign mcasp_ahclkr = mcasp_ahclkx; Q" `! W/ G- p9 ^, V% G8 J d
assign axr1 = axr0;
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- H. R( Y9 N$ F B+ B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! }* p! F7 s4 q" C! Ostatic void McASPI2SConfigure(void)9 Z+ d7 e; }& Y: G8 t9 [1 m' d
{0 q. u1 O8 E+ ?1 Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 t; D9 \. q, r% Z8 q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, K% f# v& g: M8 ^. f' c2 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- P' H4 A7 N/ ~7 ~" G6 n' X) B! FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 X0 Z* M+ S/ B$ g/ GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- L8 F2 \; f; v! `. M
MCASP_RX_MODE_DMA);3 W5 L0 F* M9 c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! h$ N5 [( C! {6 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 [3 o x$ ?. \9 T/ \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' i7 N& T- Q$ H1 n3 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% z" {/ ~: H) s# I5 N) p4 G8 v# ^0 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 H6 g! j. z! s# c' E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% G: E) O0 Q5 k" C4 h [' m7 R; v% T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 S9 O8 G6 D [9 z4 N, e. w! q2 C# gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ k7 M: f- `" B) o0 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 X I/ h: [9 k" \" }, F7 g e( X; p9 q
0x00, 0xFF); /* configure the clock for transmitter */
9 f, S3 }- h& N) x- J4 L& yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 l( F+ Z0 I5 s* iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 ?. C# N$ z, I! |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* I- H2 O- x, a u% `6 U5 l
0x00, 0xFF);% w" P# n; g/ f* Y' J! G( M U1 r
" r# c! l% J& S, `2 l/* Enable synchronization of RX and TX sections */
5 l) p- \9 D+ a+ ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 W/ x$ e* s! }! Y. O( y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' G& m* t4 `: a, q3 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: m3 Q) a/ ` i& j) E
** Set the serializers, Currently only one serializer is set as- e) X! [) V a
** transmitter and one serializer as receiver.$ F/ d, U1 ~ V! l! c1 }9 H
*/1 E- A7 X* ^/ p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 y( |4 S) t' f5 u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: h7 z: B: n9 D6 y. u9 ^" p" e** Configure the McASP pins 5 V1 _0 L7 O$ Z4 E' [6 v* F1 \* f' `
** Input - Frame Sync, Clock and Serializer Rx9 ?9 n5 z* S! A4 b1 e- A4 C5 W
** Output - Serializer Tx is connected to the input of the codec 2 k! s$ M U, a% r: k
*/
: _( }3 q- e7 O1 m! l; [& h4 d8 mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, p, g) @* U/ P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' p' I! R% k2 }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' L: }8 @& H7 R2 J" [) ^| MCASP_PIN_ACLKX+ N/ D+ s3 n' X' j+ J3 w
| MCASP_PIN_AHCLKX% }- {; A0 {( b5 X' B* Q% \" r1 T5 D/ R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, Y6 p* H- g3 K0 {% H& w9 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( v2 p8 ]& }' K" c+ V# L% C| MCASP_TX_CLKFAIL {- Z% q' a( y! s0 m- e
| MCASP_TX_SYNCERROR, }% e) w. ?# V, X. }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : V. s% A$ T- l6 ?
| MCASP_RX_CLKFAIL- j% V/ G' P/ ^7 ?1 Y% x
| MCASP_RX_SYNCERROR
; n) `1 N$ @7 K% w! R1 |0 f| MCASP_RX_OVERRUN);
+ i- n S, z ~! ], O4 `0 D} static void I2SDataTxRxActivate(void)% ]& l( |5 H/ v7 R% M5 G7 t: i
{3 Y+ B* p5 m; a7 C5 c
/* Start the clocks */
2 b$ ?5 f E/ l$ S* yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 d1 S( O. t0 S5 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- E# ?) k6 S9 d9 x; i5 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! f" B7 Y7 ^2 V; @1 R3 z3 H9 w! [
EDMA3_TRIG_MODE_EVENT);- ]. Y: A7 I" m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 D' {" r4 v# Z. hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// w" }1 R+ B* A; | X* a' [+ f, Y+ S' p6 _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: m* T/ i" V7 Z% f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// Y( [$ K, m( R5 f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& T7 c* n- x" q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 s) ^+ n, c i1 A+ p) ~1 ?- @& u* aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. [( P; A. R4 s
}
* l, J% s8 W2 I7 w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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