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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 F) L, `' g$ |. `9 q: R, {input mcasp_ahclkx,! t6 \3 Y; _6 a" e# {
input mcasp_aclkx,, g6 u7 |. V4 U) W9 R- p) }
input axr0,
& k/ \- q' m9 {& y1 j! a
& N& \( v3 G9 { w! F' z5 toutput mcasp_afsr,8 @ w, d. z6 ~7 M
output mcasp_ahclkr,
1 D4 f) \- [2 ^1 X) `0 Youtput mcasp_aclkr,
6 t0 O: {- y+ b5 A) X$ v; Houtput axr1,3 h4 B- w: Q& }- F/ A% i# C0 @ ?& y P
assign mcasp_afsr = mcasp_afsx;
; Z. s% D" W; l9 y5 U; ^# c, bassign mcasp_aclkr = mcasp_aclkx;$ V) j& |- X6 n4 G$ r1 p- p
assign mcasp_ahclkr = mcasp_ahclkx;
+ N& r H! ^& W( Z7 c' ]1 Q$ ?assign axr1 = axr0;
9 a* F+ M r& ~# }' a
/ `$ ?) q7 z5 |2 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( r( S; H1 V @* M/ {0 ~- ^
static void McASPI2SConfigure(void)9 r+ p3 q N9 |0 h! L
{
8 h3 G) l$ Z9 P+ j. y- U2 Q& HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" p8 m# k" x) N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% [! ^8 ?3 I5 I4 vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ]0 r b6 t# w8 g. Q) c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 B( p/ u2 [" f' ?- r5 e |1 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. y+ f4 N4 F5 S! z4 l/ U
MCASP_RX_MODE_DMA);0 y1 H9 n: X+ b: w* f0 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; N4 o0 @' N2 [6 S H7 h8 L0 f: T( H5 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ S: R/ h- h5 T- @+ J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 M$ K' Z5 t+ H, @# q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ G S S9 Z" W% R" f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) |! i9 C/ b8 y8 I+ W! h8 ^* }+ ]" B7 ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) h. y& o+ g# i0 \8 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); o2 r8 g M' Y; X) b. z J$ Z' K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 |& p0 T% Q w1 d7 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ H& J% @2 S4 k9 ^# O5 g- n, m
0x00, 0xFF); /* configure the clock for transmitter */% {1 z. r* d1 N% M/ }9 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) w0 l" E' |" L7 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " n9 f( P" H6 b' [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& ~+ B; Z7 [; K, W; \: k0x00, 0xFF);$ _" d% q ]6 E9 K) r+ m$ ^
6 L1 V y3 n8 y/ j. j/* Enable synchronization of RX and TX sections */ 0 D% n! s$ K) R3 O$ n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- ~* {0 i8 t% V9 ]* {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 V+ E. V, Q8 Y7 v8 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ U8 P3 O. C* y& I** Set the serializers, Currently only one serializer is set as4 U4 u. D6 T* L9 f% m5 a
** transmitter and one serializer as receiver., y( m2 j) x* t% }' B' u! ^
*/. P1 F" K8 ^7 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
_& @" r+ k/ x, I0 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 l0 H7 H: l0 M" {. Q7 Y** Configure the McASP pins
3 S2 Z1 L3 W: Y' e** Input - Frame Sync, Clock and Serializer Rx
! P6 t8 K3 ?. H4 e& H2 }** Output - Serializer Tx is connected to the input of the codec
) ^$ X7 ?+ ?. I! d! L4 r6 w4 }*/
% S0 j2 l& x( U% s+ N6 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, U0 b. i& N- C; d0 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& w5 X9 \" P# y4 Z! X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ n6 |- G! n( \0 f/ I* N c3 o+ N& k
| MCASP_PIN_ACLKX8 ~' q. I P! v" B' x' _ f
| MCASP_PIN_AHCLKX( J. R E4 [" ~3 ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, _# R6 v9 v$ C" S4 N" KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ K0 T6 H- U/ ~; U. G1 ]( t| MCASP_TX_CLKFAIL
+ P, A. z6 Z9 R6 |9 D# G$ a. [1 b| MCASP_TX_SYNCERROR
" e, u( I8 L: w4 C' c7 w0 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 V- Z& Z6 t3 X( ]7 }9 r- P/ H( ]| MCASP_RX_CLKFAIL
$ S# N5 I/ C4 v, |3 ]) u| MCASP_RX_SYNCERROR
' l9 b( a. o( t4 q4 H| MCASP_RX_OVERRUN);
, }+ p/ v3 F$ @ h) S( h* D. R$ l} static void I2SDataTxRxActivate(void)- Q- {# g8 c/ {( f7 {2 A/ a: N) C C
{
5 A2 e! x G8 Z0 W5 v& N/* Start the clocks */
% y0 ]0 Q5 a( s2 t( x9 ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' P. ?9 c0 r, f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ P4 }/ n& E: f( t, i( XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ `) u7 C4 d0 M3 }/ E- `
EDMA3_TRIG_MODE_EVENT);
" c+ A2 p% M8 J0 C2 e& bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ v O7 ?6 D' r) G( C& d8 j1 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 y7 S6 p5 t+ k' H! U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
j& K9 E) n8 G" O3 \4 |9 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& w: b* P6 H% W! U% t: V* Z( s8 c: S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 {1 h/ i$ X% {5 \. d" @1 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- j3 d! @, p. m7 H( `4 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: q7 m; a4 L; t7 g4 |
}
7 a7 E$ `# ]3 O4 v" x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + U* s( u9 ], c7 N
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