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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% Y4 Y. _( p- \* F
input mcasp_ahclkx,4 ]5 m2 g, q: t2 y9 X i! @
input mcasp_aclkx,
- x) x' v( `' a& ]8 \% k3 Zinput axr0,1 p- k& u& [; ?0 [
% w- X7 B4 u* {0 `. noutput mcasp_afsr,' o- Y: N+ c$ s/ l
output mcasp_ahclkr,
/ b7 N0 C: ~/ M' v$ _output mcasp_aclkr,
. n! {+ t/ t) eoutput axr1,3 V+ p& W( S, H+ Y
assign mcasp_afsr = mcasp_afsx;
0 |% h( H; s0 x+ @" o! kassign mcasp_aclkr = mcasp_aclkx;
0 r4 p* u; u: U5 t+ h9 B1 [2 nassign mcasp_ahclkr = mcasp_ahclkx;
/ S6 z1 j4 s* Q& g' ~- d& d) D' xassign axr1 = axr0;
' D, n X8 }& @( }0 K! o1 T9 k o2 K' r- x ]9 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, x- [3 x4 n8 W" E% |8 N- rstatic void McASPI2SConfigure(void)% H/ m( p9 l+ I% D
{, g' q: k$ [ G& K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 G& |! x6 ^* h. Q* _0 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 m* k1 @2 }. k. Y$ A3 U6 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% Z, }8 r& p: lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& l# i% b2 G4 r; c9 s6 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# S: {+ Q. D! g4 s! K& g0 y
MCASP_RX_MODE_DMA);
, }" G7 ]& a7 i* |( EMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 R0 r: q0 Q9 \8 zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& g1 u8 q! V( G- T8 f& J1 D5 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. R- f+ d9 b4 L# z) s# MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- b8 I2 H9 y8 ^6 m2 j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( T: ^7 z# l$ y! I' O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 ]! F2 A- j t$ h. u; T2 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: F9 w7 C7 M: \. c# w" d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . |- T, Y$ e! }0 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, j g1 B6 Y$ N* [( w
0x00, 0xFF); /* configure the clock for transmitter */( \4 E/ ?" l$ O8 z" ^' T5 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& e, I' `& ?6 L& Q+ F$ J. O% K1 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' e- M* G- P" e3 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ Q& F* s! j" D! n# v' l
0x00, 0xFF);6 E: Y# ^9 ^" }2 G) }
" G* y3 y6 y& X/ Q( k. b
/* Enable synchronization of RX and TX sections */
8 B/ L7 p5 S* T# fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& x* |' k' \) n% {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 p7 Y, @; L( p& tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 N8 z5 U3 Z* |+ ~; d) w9 g
** Set the serializers, Currently only one serializer is set as
5 l ^$ N" B7 D** transmitter and one serializer as receiver.8 Y1 a4 w4 A+ e" R8 h; H
*/
$ I' v R$ @! T8 OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 ~1 O& A: T9 `% x5 |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& z# T3 d$ ], p p- Z9 }0 s7 E
** Configure the McASP pins
E. j: I( L' r/ {) d8 t7 w" p** Input - Frame Sync, Clock and Serializer Rx
8 C% {6 X, [& t9 Z& s: ?6 ?0 f** Output - Serializer Tx is connected to the input of the codec : y: M& _7 D* N; v
*/( B: _% O) v5 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 T% L& ]. I9 P6 E( p# |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 L$ Z7 Q4 u0 z ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ _" N0 i( Y3 g. m& K| MCASP_PIN_ACLKX, W' h9 c! P1 ?3 R% X, X
| MCASP_PIN_AHCLKX% R& S, x% |1 P: E$ R. m9 n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 w5 L' @, t% ]; x) H: A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 X K, n" N4 v( {7 C& G' P! q" l8 U| MCASP_TX_CLKFAIL W& n! C7 x6 Y7 H. u" V9 |: v
| MCASP_TX_SYNCERROR
% J; R; l! E8 q* W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR G2 U* p! m3 [% J
| MCASP_RX_CLKFAIL1 P, ?8 f8 ]3 i4 j( i7 Y$ J
| MCASP_RX_SYNCERROR
4 d* O8 i4 X9 k| MCASP_RX_OVERRUN);
A7 i" L3 q2 E* s} static void I2SDataTxRxActivate(void)3 z4 O) q1 D F# T! A5 A
{( t- Z; p4 w; \2 Y6 q
/* Start the clocks */. x3 j- E$ o4 K/ A, a! F9 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); J+ Q; |8 @5 _9 I9 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 F! t" \+ U" J* U9 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 T* R O- g" t5 T' K- }6 gEDMA3_TRIG_MODE_EVENT);
3 B5 j" A& D( N( SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 i- g3 p [8 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; H, c' d9 M8 o+ tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 N$ e7 E+ _: z! S- kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 T4 D! B* u: i# i% _2 `* Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 m" c# C8 a% K/ j! f' }! XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# k3 }- X: J! E3 J2 Y5 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 k2 j: }, J% n5 k) F
} " _# Y- w9 H, j4 K3 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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