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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, v5 C4 W' w" i Y4 o0 m; e& `
input mcasp_ahclkx,
" c8 M, n3 Y( _ g; Qinput mcasp_aclkx,( U# a- i/ C/ L: ~- K
input axr0,
9 s0 ?& u* w( p+ e1 P7 \9 n* R; f" p$ I
output mcasp_afsr,2 F* t0 p% m5 [* A* y N$ s% h$ A7 B, l1 N
output mcasp_ahclkr,
& a, p1 L: U+ W! {2 D0 X4 [ Xoutput mcasp_aclkr,3 y/ b" J" b0 S) r4 ^5 q1 c
output axr1,
6 t. E% b" w' h1 T assign mcasp_afsr = mcasp_afsx;
, G' u0 p/ j* u" Y* B- R4 {assign mcasp_aclkr = mcasp_aclkx;3 b5 g1 e& g- w& c* R9 e
assign mcasp_ahclkr = mcasp_ahclkx;) [% h! d/ P. X& F# D' i: H/ f
assign axr1 = axr0; 7 c3 D* Y; Q$ z1 q4 R; F
8 r) I/ q) c" a9 _4 o5 ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 b, m% K4 v& k) X
static void McASPI2SConfigure(void)3 ~, C9 T2 m y L- n
{/ u: h9 s; A8 S5 P. }3 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ U% v# }1 n$ o- S& sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 P! S! W4 ^. X, a& c4 o% T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); X" I& a$ K! J8 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 Z3 @. b8 Y) r0 `; \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 S$ y7 z5 Q8 x% [( H- DMCASP_RX_MODE_DMA);$ j o& v! ~/ G( x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. S! W* d( V$ G$ m! M yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 e0 b, N1 O |; F3 h9 kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 p/ q5 k1 d% J& h& Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! }' m; p4 a" Z; u7 }2 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 `! L+ F0 K( {9 m4 ]$ sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 u7 j2 u& o6 l& e! A5 N' ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* z- v! R; w; H3 D% F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% I2 p9 n% I: K# ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 F' R: t6 y$ p6 b% Z! S- r" W1 @0x00, 0xFF); /* configure the clock for transmitter */! C& ~0 k! p$ Y' D% H( F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% A9 {9 V2 I0 k# f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. W% Z' z; m: _! M2 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ P3 P/ X% l6 f' O# V0x00, 0xFF);
* r8 t( K& w: _# X' W3 i! h2 k% }# w1 r5 f y, L
/* Enable synchronization of RX and TX sections */
' f0 b" [, A8 X* [6 L2 O2 e8 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; ^! m, c4 c6 {3 S2 `. ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ G0 @. g' ?8 b2 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! o; J5 E$ B' u* W# O5 o# ]9 G** Set the serializers, Currently only one serializer is set as
( f, Y7 k" v& t4 Q( u4 `4 P. g# Y** transmitter and one serializer as receiver.3 T `* _" p( w8 @2 F$ p
*/8 l; l) n! `5 _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ f' H& }+ b% K4 {9 \/ {! ~" b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 a4 c0 q9 N- M+ c* F' Q3 a** Configure the McASP pins
$ x' N: D: Z9 L+ @* R** Input - Frame Sync, Clock and Serializer Rx
- |7 [- f2 }+ F; g** Output - Serializer Tx is connected to the input of the codec 9 X; y% V4 e, |7 h* O+ [
*/
% @ _; B& R. c! T! w7 [' y7 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, W* X# Q' h& T( o' |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 y9 U- B2 g O Q' ^2 T, KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! I$ b2 w3 @+ \# T, j( W$ p| MCASP_PIN_ACLKX/ H# E% {4 m3 a/ H& A5 O" M
| MCASP_PIN_AHCLKX' {: V( X7 C- N t8 c0 F/ A6 i0 G- \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 W$ `% ^1 O+ V& }7 O6 \
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 r2 h7 \0 S& D& `5 @* ` @, R% X| MCASP_TX_CLKFAIL
5 c; i. }2 P M0 Q! ~| MCASP_TX_SYNCERROR
/ d! ?7 J2 E9 U; n4 H8 K0 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 C: W8 i; e: \4 q
| MCASP_RX_CLKFAIL
4 i% R3 o* n g: P| MCASP_RX_SYNCERROR " X* l6 K7 e8 g. Q& P+ h
| MCASP_RX_OVERRUN); v: z* |* d4 l Q1 P; I( E
} static void I2SDataTxRxActivate(void)
4 w F4 ], B- W& O; W9 b{( I& n, d! ]8 P( }
/* Start the clocks */% R2 m$ j! g1 \# b/ J( U6 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 H) i6 D. q: @0 U% h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) F0 [' x W# z* K2 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, ]2 C, G+ k1 Q8 T4 X3 o
EDMA3_TRIG_MODE_EVENT);
' y& t0 N# F+ k! o ^. w0 C' o6 u& IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 h; {, ~; n6 I) I3 Z/ BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 f& A. e; ]# B* Y9 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. a# A5 t" x" q2 U% R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' i5 t% ?4 e0 p9 i2 Z( H5 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 M8 d2 K% B8 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) w" a# i6 r9 [* iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 p- d' c' q, Y) Z/ `5 G
}
' ^* Z [% v! F! u- z4 B# R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( E; X5 S+ _4 A# ~7 v% s; r6 M" Z
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