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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- x, q0 j) S, z* L. Z: }+ ]
input mcasp_ahclkx,8 C$ Q6 M; R0 e4 u5 B: y
input mcasp_aclkx,
; b1 q% | U2 t* G/ Sinput axr0,4 B1 \" L/ E1 w" u8 ]
+ N" e0 Q7 i& Y- J: h" N& j
output mcasp_afsr,7 M8 U+ m0 w* c$ I d* J* X$ M N
output mcasp_ahclkr,1 l5 t' }, o o
output mcasp_aclkr,
; H. h# l! g2 x5 T$ X; uoutput axr1,( z$ c- H' `9 b4 X$ E
assign mcasp_afsr = mcasp_afsx;
6 ?& {6 o# J3 Q# L+ Massign mcasp_aclkr = mcasp_aclkx;
3 @0 O% k9 x# z; b5 Fassign mcasp_ahclkr = mcasp_ahclkx;0 Y2 \& y2 `) S, @7 b/ Q
assign axr1 = axr0;
; n. s( T8 e4 M* R+ D. r/ q
1 s1 |3 A6 o! L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 q! v! ]7 L& `3 b
static void McASPI2SConfigure(void)$ q. X+ J+ l) V2 u6 U
{
* I8 N* _- L, o4 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 u( u, |0 k1 v' l) C$ K7 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ U( Z# k, e" P# V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) G! Q$ y$ a: w6 w6 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( l0 C6 z' N" W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# @* {9 z$ s) D8 y2 Z* ?MCASP_RX_MODE_DMA);
' X+ Z. v1 p KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& m$ J/ v1 ]+ m) Z# M' O* {, Y% Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& a/ F3 b4 v3 M4 {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 G6 K$ H5 C! KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 e6 z) i6 D; ]( w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! E- A7 H$ V$ L4 D, C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 [% q8 d: r7 Z7 T1 r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 O# h3 q: \1 ~3 N, I+ _4 m6 n: `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 @+ Y" E5 y w* Y' U" C a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# o3 l6 h1 S3 W1 _. `0x00, 0xFF); /* configure the clock for transmitter */
, ]( ]) a# k) y5 `: `$ B/ DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# J9 ]5 _; W6 T2 `; H+ i) I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * P( y: o b |& d i' u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ C5 U& e( e% w+ [# ] @
0x00, 0xFF);2 X/ _1 o) J4 J% [3 i* l
- r& ]2 O6 z6 r# X U/ t" X/* Enable synchronization of RX and TX sections */ ' I" u9 I5 d3 s+ e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! |2 N. c$ E* j2 G! G+ Z- L* pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ ^/ ]% L( Q( DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
h' l$ q! f& B2 \6 }0 H4 U2 |) I** Set the serializers, Currently only one serializer is set as
# [ s3 R- I5 I* F8 W4 y** transmitter and one serializer as receiver.
( i# D0 [* S; ^* ~*/) K' i1 U( l! \% H) w& h2 {! S% F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' D B. |6 u3 g+ Y) WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. g1 h! `/ q( i6 s2 q! C
** Configure the McASP pins
: k; w6 u; M% k( m' L6 O" N: x8 j** Input - Frame Sync, Clock and Serializer Rx0 h% @/ q0 }7 @+ d7 A
** Output - Serializer Tx is connected to the input of the codec / g. F( Q; j* K4 y
*/1 J2 K1 p2 A* K" V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 t% o5 P. m) G8 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' v, [% c2 g2 R+ ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 f, M" h* ?9 N) S ~
| MCASP_PIN_ACLKX
; {: R% Y5 T n( D| MCASP_PIN_AHCLKX; ~4 q6 S x9 k* x( A& n2 T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ [1 ?0 Z$ l' N3 s4 G ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 _# m% T2 _! ]% o: Y- o! [ {
| MCASP_TX_CLKFAIL
. O# z4 M2 ~8 d; a| MCASP_TX_SYNCERROR
# C+ R+ D! X" c) X% H- K& X| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 `8 y. f0 l3 t- s* E
| MCASP_RX_CLKFAIL
! V7 R0 {# ~$ H2 B/ u0 \6 x| MCASP_RX_SYNCERROR % q- u2 ?: g/ I
| MCASP_RX_OVERRUN);: f* w8 R3 u7 f. e# @: ?; b4 |- c
} static void I2SDataTxRxActivate(void)
1 r1 y3 }6 A X, Z/ i+ C{3 B% P" A! N& f- ~- p+ ?, G
/* Start the clocks */
" g G& @+ t& S AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 x3 M9 w3 g, P' m$ SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ b! c0 l* {; w) h6 B xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& A. Q! N, H4 X* A- w5 CEDMA3_TRIG_MODE_EVENT);
]" z& B. N5 L8 j" J5 {2 t4 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ P4 _# p Y/ D* ?1 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 }( v. z7 [/ H! vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* Y! w" h7 H* U/ a g5 a% g5 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, c' w" z1 y7 B- Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' i# p0 m) _# C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 P4 J0 @) e& j9 A$ A# O+ ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 c$ D1 D$ A' R, F7 q}
; N& A) y5 S) w! q- _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( l5 U8 u ]% C2 W
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