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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: K' p& G2 |. g# u# Dinput mcasp_ahclkx, k* m4 A- f( z5 A- N) w& L! w
input mcasp_aclkx,% N# s" p: A% u
input axr0,) _( I0 H5 b# X, E
& r ]* u5 {* N w( L0 Eoutput mcasp_afsr,$ t( ^% b' m. S1 M. z5 |' L; T, W
output mcasp_ahclkr,: X" A/ @: l" u7 a8 G! E( w
output mcasp_aclkr,
* h6 ~2 _$ {; R% ^) qoutput axr1,# m# t2 A# Y- l: u0 m7 C' J
assign mcasp_afsr = mcasp_afsx;5 j; m7 s, d, ?2 a
assign mcasp_aclkr = mcasp_aclkx;
1 S3 @4 q3 ~ \( Zassign mcasp_ahclkr = mcasp_ahclkx;
/ Y1 }' c8 i* u% A) B% e$ rassign axr1 = axr0; S4 X: L! k, h/ g( i; L" H" v
" B4 O/ d5 U1 a- R& E/ d. h) f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 j6 ?, \( v! l8 u0 ^
static void McASPI2SConfigure(void)1 _ H+ v/ _5 _- _) c) N7 y. L% Z# L9 J
{
% t. d! t I) z }$ cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 c2 o% @+ G T+ U! p( Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; R/ `" ~- u3 [5 w+ J2 f" ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. m8 A4 G$ B. ~* R/ }& \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& P, u: C) f* Z$ B9 e$ zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) `) M. H$ _1 m
MCASP_RX_MODE_DMA);. O1 y- Q& [$ [, V3 n4 z; f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," ~& Z/ N* [& j+ l% ]# K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, r4 n$ g# v6 ^+ ?7 o+ B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! d- L+ N7 x/ R% S d* J0 z: {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 s- B, m2 `5 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % ^1 u6 q8 P) k. y8 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 W) ~, K' ~' V" x, o, c6 h3 IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
J# f' N" Q& a/ V+ W- {4 wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ u1 t* Z' [/ c6 r4 `+ S { {, VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 n. h8 H" _" p- f" @! |' n3 X* V) m0x00, 0xFF); /* configure the clock for transmitter */
4 K5 C8 Z& G% D. h6 i2 V9 Y/ A! yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, Z! n. @( A* M1 \/ D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; |; J3 |# E( O# h/ H) Q( V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 ]; }1 A; R, P0 x8 W5 `* U
0x00, 0xFF);
: u/ C: W9 `8 r4 D' A* I7 j) a' J4 O6 W% E/ h7 c& X9 B3 x' H
/* Enable synchronization of RX and TX sections */
( y# m& [. G( J: g2 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 `1 `1 d. z* \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 j" d/ c' v0 U* h/ DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) t. e8 O7 |( M d; Q# b* J, g8 E** Set the serializers, Currently only one serializer is set as
/ x2 j. m2 k$ _** transmitter and one serializer as receiver.) t; k8 h2 A% c1 X, h
*/
. x. Y3 M/ s( X6 M j/ o3 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 y( Z; N+ d. l7 j0 kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* R9 \) }7 L9 n& ?( }! E** Configure the McASP pins
" A' ]4 T+ l3 `- ]$ U' b/ Y% D9 A# R** Input - Frame Sync, Clock and Serializer Rx2 S$ |% m$ ]# P) u
** Output - Serializer Tx is connected to the input of the codec 5 m, @1 i! y7 k
*/0 ?" R, P/ Q1 b3 F: O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* _+ _3 n' H8 q) T: C0 |) T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, d/ ]% e/ o/ E1 N" l# V8 S- LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 E% g, T' y& i! K8 U% w| MCASP_PIN_ACLKX) b A* ?1 ]: P4 Q' E: o) l
| MCASP_PIN_AHCLKX# p X6 n1 W9 i( t- e: A- b7 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% V) {7 n& f' j. [- G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * i8 o1 z1 Z6 U# m8 C8 d
| MCASP_TX_CLKFAIL
8 z( U3 w1 P' i. `) t| MCASP_TX_SYNCERROR( S2 z0 f) \% x- R8 ?/ K, v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# P$ B" D# A4 d8 Y+ f| MCASP_RX_CLKFAIL7 v- `: M2 N8 X% N; ~
| MCASP_RX_SYNCERROR 9 i) A9 X1 b0 J" L9 a* E- T
| MCASP_RX_OVERRUN);) d C6 d1 p$ \
} static void I2SDataTxRxActivate(void)
. o; m+ ]& Y; Z( q6 l P{% S0 u0 X0 i e& v9 ] L7 i+ E
/* Start the clocks */
4 p; N6 j+ i9 x: e: TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 J% I8 Z. @; W. t. yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 m# Y1 [! c6 C3 _* Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ N, z( j) J6 {' A
EDMA3_TRIG_MODE_EVENT);4 `- _, }7 n7 F2 |9 h) c* |3 r2 G6 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 a' C' B3 O2 S! f1 [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: U0 k# H3 e& c+ S5 k1 G; ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( F$ D) d) s. N) Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, d+ l3 D4 E. P; L Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
u6 J! I' g: C; {4 ]" _0 KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ V4 F0 M: |& A5 O# {( E* I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 N. X+ Q3 W, I/ e% Y
} 1 `. k. Q/ b8 C3 C, X' {. @. |% M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & Y V6 W5 Z. }+ T7 p
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