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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 T& ]- d; f2 [+ N3 z; m
input mcasp_ahclkx,
# b; d( e6 n& B y; C8 x! t; \input mcasp_aclkx,
3 C4 M8 Y" S: w/ xinput axr0,2 t: T* ^3 {+ a/ E
2 ? z _2 p, t0 ]6 Y, i1 ooutput mcasp_afsr,% g; ^4 n3 \1 m
output mcasp_ahclkr,9 H* Y5 B& f" i! u3 \3 l, [. r
output mcasp_aclkr,, Z5 J: o* \4 e1 }! T- @
output axr1,, m: l! q J- d
assign mcasp_afsr = mcasp_afsx;
/ G) S! X( z3 O1 k Oassign mcasp_aclkr = mcasp_aclkx;
# G' V, a4 x+ v/ hassign mcasp_ahclkr = mcasp_ahclkx;7 j$ ?" z! D' q+ b4 e: U
assign axr1 = axr0;
5 T8 w1 Y) t$ S
/ V% X, n i/ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ [; u9 N0 M! I( V% Q
static void McASPI2SConfigure(void)% I0 w S1 y8 a. x
{
$ l* D8 }; ]* jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ }+ b/ f4 A( }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 k, _8 y. g) E& X; S& PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& u0 s8 I* s, K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" `" B% r" [" y Z3 p& Z5 R4 k/ \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' s1 Y7 s6 O: \4 Y% sMCASP_RX_MODE_DMA);; k8 M7 [ p9 ~6 w' k1 u5 I/ U# `1 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: [; X" C; J- D# q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 ~8 k8 I# j. n( ^: R& x' \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, @% [+ t0 g& Y) ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: d: ` T% [6 C k% c7 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. H( ?6 l* `% Z+ @, p- T- W, bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, U( L. {# @0 _3 `, _" h0 V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% M+ B/ `4 Q% |8 D3 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 O+ M0 N: d6 |+ h( H: x5 yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) u: e6 Z1 u+ b3 [& Y
0x00, 0xFF); /* configure the clock for transmitter */" U; V4 U- m S1 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: E5 I* p: D3 M. H( ?- I( i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% p2 G1 k+ H D: yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# s* K% _' c/ ~$ C
0x00, 0xFF);
' V& k$ U* r4 C8 h* G' q+ H& E& @. \) l8 F3 i0 V3 L
/* Enable synchronization of RX and TX sections */ $ Q0 _) f$ C6 ?2 x: M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 M7 ^9 W( @( {8 n. N# B% L: hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 p0 ?& d: {0 T8 D1 e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ M8 S3 R( d5 `
** Set the serializers, Currently only one serializer is set as! R5 c2 l. N9 S3 G# B. g
** transmitter and one serializer as receiver.
: c! g% v4 n( |2 N( D*/
$ Y8 s- _5 S6 _1 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 b T7 B, V4 c. A6 e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ l3 r0 P' G) S) J7 v: n
** Configure the McASP pins 4 B. W: i' a) C# \2 b5 @
** Input - Frame Sync, Clock and Serializer Rx K- q) L" g( }4 z- x0 `. J; |
** Output - Serializer Tx is connected to the input of the codec
. r/ s, t: r; d* b. M! u l( R*/, \- K6 p' U0 \8 b' \- ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. X7 x' J$ |& c( q5 R8 V& M1 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: n, h; l. V; o3 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' _- _( W) P+ f8 R+ F% j- O
| MCASP_PIN_ACLKX
; \0 ]; B1 s5 A# c! Y; Z7 Z2 i4 M| MCASP_PIN_AHCLKX
& h5 `4 r/ m9 l" s D( p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# _% J9 w% A& g3 l0 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 F. U' }7 a, a7 U; D6 r' X| MCASP_TX_CLKFAIL
, u* n7 l" e0 n; i| MCASP_TX_SYNCERROR
& V0 k7 t; j+ H5 R1 R! {1 E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' T* ^: x) q" @/ m' E3 {| MCASP_RX_CLKFAIL
I! t A+ k9 k. K1 D v| MCASP_RX_SYNCERROR $ W$ A* R7 D9 K
| MCASP_RX_OVERRUN);! _) z! l# l8 L7 y6 H" j
} static void I2SDataTxRxActivate(void)
- D/ w: {3 `# {. u, l{
. |/ {2 r# o& S$ c: {9 A/* Start the clocks */- w9 l" P0 t' }1 q% t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 n8 U4 B. W7 ]1 t( r' i, F3 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// @- T$ t, @! M4 ?1 N/ T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( W# q. _) w' m1 A/ y6 l3 Y0 _
EDMA3_TRIG_MODE_EVENT);8 ^+ D1 l8 q: j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% f; M9 Y4 D: ^4 V7 p4 {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 v! A! Z- ^& _% SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 _9 F& D2 E! Y7 {! D* Q; iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 h4 S9 h V* L8 Q$ Q& E: lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 l7 Q* ~: q6 }/ ^' h( G$ b6 J2 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 [! G w: [! [2 A) n* d! C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: m# Q' T t; P0 M; O3 T3 `
}
$ q6 Z/ o4 Y5 l K+ @7 H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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