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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 {* ?+ G$ l6 [4 L5 ]input mcasp_ahclkx,5 a: y3 J9 l9 D2 N k% E; }, A
input mcasp_aclkx,+ Z0 `' y% p Y
input axr0,1 ]( q1 o+ J2 v7 s6 x, r
% D4 h! j5 t. r4 S: x- ^. E/ Z
output mcasp_afsr,6 S: N* l W- M% q6 A
output mcasp_ahclkr,8 ?% ]) O( ~8 k3 \
output mcasp_aclkr,
1 t+ k+ G, D- w3 |; Uoutput axr1,( M. |$ x& J0 D! l2 l# _6 o
assign mcasp_afsr = mcasp_afsx;
* p9 R) S+ ^2 h$ i4 p6 a$ k7 Aassign mcasp_aclkr = mcasp_aclkx;
2 i* m z* z/ g# c4 Vassign mcasp_ahclkr = mcasp_ahclkx;7 q H( ?/ M, A; \) c m0 A$ s- K
assign axr1 = axr0;
( o7 A v: e, }/ [2 I8 I
0 d, Z5 n& {6 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # `( J: I9 R4 b; O/ N' {7 E5 o
static void McASPI2SConfigure(void)8 j/ F# m; {4 y, o" d
{% S7 b$ h2 G$ U. F! y. i- I* U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 U" M% Y [! N2 n% LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 Z8 Y/ g% W4 \9 y |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 a4 ?$ n2 x% G; }4 c2 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! n$ l. ?& v5 I1 M- Y9 f. z1 ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ J1 @ t h+ t; wMCASP_RX_MODE_DMA);
V4 T; G3 d; a H2 ]& ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 _! t1 b+ w6 S7 F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* v I! a8 u; Z" o7 ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 o, ~9 ^* E8 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* x& \; p2 F2 G0 }5 {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & ]% a9 t# z O- e& [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 R3 h3 |( i/ Y4 I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 Q! z. C1 j w8 _ x* m% yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ~$ [. |5 `( w/ G" J+ PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 l" J3 R6 b7 Q
0x00, 0xFF); /* configure the clock for transmitter */ E! C' ~0 s6 q0 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 F& _9 u# L& S) k) nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% Z1 B4 }! b7 J+ f2 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- I+ A! z2 e" o& c1 N' i& t& D! g0 x
0x00, 0xFF);
, ^8 G- c9 H$ v/ {: v
9 H, F+ j! M: |) n+ R/* Enable synchronization of RX and TX sections */ / y# f, k8 `- D' d' K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% }2 }: x9 G0 ^. N! B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 G8 \5 i) v( `) S e& Z3 c: t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ [+ m( {, D; r7 p6 s4 \3 L" I! K
** Set the serializers, Currently only one serializer is set as
* d y0 H9 |; {& D** transmitter and one serializer as receiver.4 j9 i' i4 e4 X6 L5 x3 x; |
*/# n' {7 B; z1 D" K+ i3 U+ a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 ~( u! B4 x+ o( L% JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" O" i! m2 F4 X" F! e+ R** Configure the McASP pins 9 f4 W$ ^6 E+ d, M$ I% G4 j4 z0 G
** Input - Frame Sync, Clock and Serializer Rx
5 {0 @7 K. m$ S3 c$ J** Output - Serializer Tx is connected to the input of the codec 4 [9 u; h: }' G6 t& d1 w4 c$ \
*/
@. w8 A/ o0 f1 g% _* M* hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, x$ y$ @. X, u2 `+ PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. K$ w9 f+ D$ h* m4 c+ m; Y2 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX t9 Q2 S! J R9 \0 Z
| MCASP_PIN_ACLKX; `3 e }2 o) Z, _+ O4 \
| MCASP_PIN_AHCLKX
. N3 B3 e0 B3 ~, h8 k+ Y) Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ P4 e7 s" T9 X' u8 A, u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 F- @& {* r3 N; b6 o# g| MCASP_TX_CLKFAIL I+ I) X5 C/ h' h% ?, e
| MCASP_TX_SYNCERROR
v% f, G' j' q/ o( G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' U3 I# E& _1 H: Y0 H9 _' W+ _| MCASP_RX_CLKFAIL; Y! \. M: ~1 V/ K# U
| MCASP_RX_SYNCERROR $ z b, U- Y4 g/ U K
| MCASP_RX_OVERRUN);" p) C7 x3 Y( p+ U
} static void I2SDataTxRxActivate(void)( G! B. P( h8 p* b U3 q
{
; M' d+ Q8 n# c' x6 e3 Q8 M! G/* Start the clocks */- {; ^ o0 J3 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 T- c1 W8 k; \; W" |3 e( u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ S2 j( e @( Z* W& k7 |( D( {2 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 v, W' t3 ?7 xEDMA3_TRIG_MODE_EVENT);# I5 d$ P5 e8 Z8 b f+ a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . N5 g6 `5 D$ j) {, T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* |; w3 r) I$ f5 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( B3 C! @/ w7 t/ s' d& rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 i( j8 \. e. U, D" W- h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ s: H Z4 _- n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 D$ K' t3 A6 t6 G/ D* LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; t# M7 p: r, k" A$ V} % X7 W7 u) u4 u9 t9 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 F* y3 [* |6 n) ]+ [9 S+ D* u
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