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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( C$ \8 W) Y, m; t; m6 J
input mcasp_ahclkx,
. W4 J8 f9 R! |) B1 {9 Cinput mcasp_aclkx,
, A$ `4 p+ _7 i$ V) @ winput axr0,: t; o: e$ l0 r5 G
$ V3 E: _1 n0 O- |# ?3 {* R" K8 @
output mcasp_afsr,! w5 S; b g7 \
output mcasp_ahclkr,
, ^) _* W; O" z9 g+ C- toutput mcasp_aclkr,- j3 _) w0 z, v
output axr1,; e- G) f4 B' a; a2 a/ o
assign mcasp_afsr = mcasp_afsx;7 r; `$ H5 j. F! K( v
assign mcasp_aclkr = mcasp_aclkx;5 }8 O( H' i6 ^8 e& E
assign mcasp_ahclkr = mcasp_ahclkx;& K! E2 E/ W8 q+ p5 R
assign axr1 = axr0; " x% _* A) S) x6 `3 m U5 u6 o Y
- X; n& {4 h9 ^/ }9 o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 ]# d6 N+ }% v9 x1 G9 k! T0 S0 ~
static void McASPI2SConfigure(void)
+ b1 _2 M7 i8 J1 b' r{
# s2 `/ g, X- X+ `! `% j+ hMcASPRxReset(SOC_MCASP_0_CTRL_REGS); Y$ M; H) G d9 |/ z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 T- v3 Z) W0 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( W) k0 c0 w+ p1 G3 t4 k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& ~0 Z4 E: Q n- i
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: o4 I- w; |& g, k3 L: d, {
MCASP_RX_MODE_DMA);+ Y F- Z- Y) ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! \ \8 j- ?% m' gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) P1 Z2 q9 x* E# E9 k! S/ ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. d2 m" W! V. V. @. s2 ^6 \% ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ E3 w# W+ L3 o% s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, A, N: g% v- `& A: K `- \7 xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 @: p# b; r0 x# j7 O( D, P5 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ R4 y$ C5 t. @. hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 Q) n0 A, S5 g6 S( V' f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' t7 Q l9 N# t, S4 f( V; l$ q7 n- u
0x00, 0xFF); /* configure the clock for transmitter */1 I( M+ [4 r; m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' T; m+ A1 z2 g3 d3 o# i& M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 M+ }$ Z, `- J" B6 U$ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* h( K8 |' E/ g. u& C) m
0x00, 0xFF);7 R2 l# U6 V3 A/ a4 V' P
+ J2 m F2 Q: t) B2 O
/* Enable synchronization of RX and TX sections */
* U- P1 a7 ?7 K7 F% SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 G9 F( G, [, }: `' R0 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ?, p' V# n, Z- j( ~# ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ e. Z f2 B7 T+ I) d4 K8 `8 X0 Q8 |** Set the serializers, Currently only one serializer is set as. j1 b8 `* ?7 p! N9 `
** transmitter and one serializer as receiver.' N1 c$ x- f/ c+ {! A# L
*/
2 J- e! m7 O* J" w, jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# ]2 K/ p- P* y" U- @, `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( b4 J8 i {% s) H" L! R** Configure the McASP pins
G/ _0 G6 p* v# d+ A3 w" Y1 U** Input - Frame Sync, Clock and Serializer Rx/ [- g5 m {+ P0 `
** Output - Serializer Tx is connected to the input of the codec ! J6 x' J/ h! Z& ]# g' |. a' U
*/) F6 d$ i' o- u( A$ S# V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 {& }3 c$ N9 ?/ r. R2 Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 q- x4 W/ h& iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, k- V. v" }6 E7 v/ V
| MCASP_PIN_ACLKX
3 t4 A% i5 \, D) o" T" q| MCASP_PIN_AHCLKX% X4 _0 I. O" g9 W3 J) r9 G L8 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
K6 W6 X3 h \1 A, T. A9 F( C) A kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # I( m" @4 J5 s" E0 u* W% d; y/ Y
| MCASP_TX_CLKFAIL
' B) p( j# e$ g* `| MCASP_TX_SYNCERROR1 V$ i4 r0 Q. o/ H+ y$ |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 L' F4 W! Q% [: E1 ^5 W
| MCASP_RX_CLKFAIL) I2 A* o( z+ |6 ? c y
| MCASP_RX_SYNCERROR ' f- j- W, D' @+ o( d3 \
| MCASP_RX_OVERRUN);6 Z- e) v9 q+ `9 h: x' S
} static void I2SDataTxRxActivate(void)
; ~7 I9 ]) N% c d! e{% v/ G' v# q6 ?! o1 m/ L
/* Start the clocks */. @$ S8 p* [* t# ^. c( b6 {) r$ f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" i8 `$ @- p8 s- q, O8 V' [& q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 k; s) e, D6 P, C. E% D+ A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% L+ M \7 V- x7 \3 o8 fEDMA3_TRIG_MODE_EVENT);
) d' i! S7 K/ J5 f$ z5 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 } Y) M8 W/ t, _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) V) X% Y) x @7 r2 }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( e- f4 T2 r5 i7 | \+ dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 b. S0 E4 `5 ?" k# a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ T( p' z( ^. UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ F1 q6 @ C; N; O" c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 s. J5 E. s% b6 }* k! h1 m" W} : y. ]' {* c/ E: _1 |: P D8 b' Y$ i; K3 J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / \7 j3 ? e4 k" h4 J! a9 ?
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