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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! k V, f+ t( @; V/ G2 H1 |5 }
input mcasp_ahclkx,
$ Y# _ G! p0 \$ B- A1 qinput mcasp_aclkx,1 q8 P2 r" Q6 |9 E. O6 X2 R3 n
input axr0, h) q0 C: G( \( F' ~
9 v- V. O+ B: O9 v. Routput mcasp_afsr,
# \! C+ h$ m! V, B0 u1 Noutput mcasp_ahclkr,
; B- q" P1 n( Y! Xoutput mcasp_aclkr,
1 g: G6 L2 P+ L& M: O8 D; n4 d |output axr1,6 b9 K4 g/ E/ ]# d% h4 c
assign mcasp_afsr = mcasp_afsx;
: i3 T7 R* J* o; W+ c* nassign mcasp_aclkr = mcasp_aclkx;
5 v$ a* a) d- {1 Q! R. u) I: K, V8 @assign mcasp_ahclkr = mcasp_ahclkx;* f+ E$ |+ G1 z7 M3 f
assign axr1 = axr0;
4 X/ r( n' i5 D8 p1 ] f
% L6 M) a% ]) w+ L! K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
q5 {2 } r' M0 v, }. {% Hstatic void McASPI2SConfigure(void)
9 ^8 S; }: ?* l0 {- e{: v0 n( C6 W! `" u1 v2 b# g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% M9 X# N$ V) Z6 K! U) L! J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 \8 |+ y9 [$ U$ S: r* PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: _, T! [" j- @. `+ F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 t/ K( u* }- `3 u/ Z1 j4 p( FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ?# h7 t- M7 {! v4 r% z
MCASP_RX_MODE_DMA);, L9 h; p6 |/ E4 N, d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 X; A& t* b7 A6 r% | n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 X8 I1 N' ]2 }! l. D' Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ L- t% L G# G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 K& \) \9 Q4 `, w$ d2 ^4 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & o. L- }3 k. h4 G0 b5 o' `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ J' S) w6 `) }( ]$ R- A4 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 ^' k6 w6 Y- K [# xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / Z+ f" l* z* M- b; c8 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. v2 h$ h9 o: N: t( l0x00, 0xFF); /* configure the clock for transmitter */
# w5 `8 N6 P) N. {. ?+ v( k" [$ \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 o) [. n2 t. K3 P" L4 Z% F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( r( q! P; k+ x. i' H7 H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 J* E5 ?, K" L! d0 P2 d; v0x00, 0xFF);+ q$ m8 a1 g1 t, y1 y! L7 Q1 S
1 P0 S( C9 t" Q8 P; K }/* Enable synchronization of RX and TX sections */ 8 v" L! b/ K( {- r" ]: s+ Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. g- A4 M& E$ c+ W. v; \4 y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: }- i; e$ S. e% R1 ]$ J- ~1 ~2 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" Y8 [/ n( Z' ?/ [4 d
** Set the serializers, Currently only one serializer is set as5 a8 w' @6 r$ L6 x5 \: C
** transmitter and one serializer as receiver.
, f( S! G1 O, ?) V*/
1 V/ _- M% ]4 g+ h9 G; tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
]% s/ j, l! b, Z/ ]% H/ u( Q5 h nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ H- r" k# P2 ~5 X/ ?, V% r
** Configure the McASP pins ( l! G" i/ i3 u% B5 L, f- G
** Input - Frame Sync, Clock and Serializer Rx4 `1 c2 F; V4 X/ |7 B4 s
** Output - Serializer Tx is connected to the input of the codec
; F& t0 V$ R3 q) q*/
& q4 w1 ~9 ?; rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 w3 s! A( d0 ~8 \& t8 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 U3 Y' d C9 p$ c+ qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. T4 G8 F* o3 k- Y% C| MCASP_PIN_ACLKX: O% ^ U1 \; j" T( N8 ?, W
| MCASP_PIN_AHCLKX
5 t$ r% \) r8 X! L3 D0 r p; w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' T l% S1 o& J6 n" ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ y$ c' W% { W& x/ O6 Y| MCASP_TX_CLKFAIL + J- g; `7 _; Z- L8 L
| MCASP_TX_SYNCERROR
/ r" F% N# Q1 `( `! w' n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% _' X( h8 f+ d9 k3 ~9 G! g| MCASP_RX_CLKFAIL
3 \- v6 M/ a8 b! y: c- R% x& ?| MCASP_RX_SYNCERROR & j. p/ B+ w' p K
| MCASP_RX_OVERRUN);
" [9 g% G5 A$ t& S& }} static void I2SDataTxRxActivate(void)
8 {( k6 I6 s- {, t! U6 \{
7 V: ]7 ^* I& J! @4 o" |. [/* Start the clocks */
' z% M4 l( R. A, w `2 CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' J( B5 N! d4 O6 t6 F1 I9 M! @9 Z# v' ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) P9 M% c# B) d: l |3 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 S# s) C: J z1 N0 v: wEDMA3_TRIG_MODE_EVENT);' X. a0 N5 A2 J4 h. n7 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 I" O! X' V/ A- }0 K( ]: _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 V& L2 G! v, l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 F7 E& o# K8 p3 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 L$ a9 U9 R2 }; G3 l% i8 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' s8 r; @' f8 X% |2 H+ X5 KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. X4 q" }" F3 o) b+ U7 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" P" C# y: ~3 B I6 `& ]( c
}
" G4 l0 G: n5 y* q0 k* x% k8 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) {/ _9 R0 g1 p; i1 r% A
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