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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) O* i7 D9 j' d6 [# a j
input mcasp_ahclkx,% q$ W" J7 t5 i% K0 H
input mcasp_aclkx,( g" P1 k, j* M% O
input axr0,
) L" K, R6 ~7 [& Z: j& C7 y; f: k2 o$ k* K* c$ e. c
output mcasp_afsr,2 e& f Y% j2 [7 J Z5 H# o9 v
output mcasp_ahclkr,
, M4 ?3 ~8 q2 S% {( Goutput mcasp_aclkr,3 ^( d" \9 W6 Y4 _
output axr1,
- u# B: }' M% u8 [0 k5 A/ [4 R assign mcasp_afsr = mcasp_afsx;
, h- Q5 f1 ]* F% N" Q# passign mcasp_aclkr = mcasp_aclkx;
8 A3 @! K2 G- W( m6 Z- c+ Jassign mcasp_ahclkr = mcasp_ahclkx;
) u$ w2 J1 c' Rassign axr1 = axr0;
. Z/ `/ h+ R ?3 Y5 z. W/ i5 t6 ^& u7 H0 K$ z# K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* o! u7 ?: Q# C7 qstatic void McASPI2SConfigure(void)7 p7 p- I5 O; }: e [1 d: b C
{
4 A; _. t1 H4 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 [: `0 r2 V6 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 E( _* g7 a- F( U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 O( h5 B2 [7 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 f2 s h" k d. N2 u! @$ mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ]. _6 ]9 \3 e& ]- y+ d b
MCASP_RX_MODE_DMA);" n( z/ W) W. z, k" V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( J' ^1 L( s% I- eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 M' m! W! p# L% P: C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # c$ n" }( [5 g2 j2 E0 G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; s( g6 `9 |( N6 ]2 O- P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / h" d* S% c% Y6 k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 p- ^+ N" }% w b7 b8 t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& U; v2 @/ p; n" O' d$ X+ tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( {/ u9 R" E4 W7 |% ]% w/ M, oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ a7 X* w' e; f& n; ^6 V9 X
0x00, 0xFF); /* configure the clock for transmitter */4 b* u6 t- i$ z8 g! ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: b2 E! V! @- r3 b& {; Q/ ]( ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 U; T$ ^* P! r( M8 `/ mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# B9 }" M4 t1 }# Q4 K3 g* Z0x00, 0xFF);( @5 l2 u4 u6 b. F! g% K) ~
! j9 ? J" f+ ~- a9 r( O4 k" G
/* Enable synchronization of RX and TX sections */ ( A% {/ E5 Z& t; Y5 Z! `, o& J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# P/ y+ f- q! z, l( \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' E. P( G0 e: M; m+ S5 M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' ~7 p: h* Z( m** Set the serializers, Currently only one serializer is set as8 S! D0 U7 e: n6 `
** transmitter and one serializer as receiver.' ?, B+ t* s& u6 ^# l
*/, R. W$ {7 j0 Q: x3 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 n) S# D; n# `) C: r- K; S! MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' H! `7 Q3 L$ ^4 P+ W* b** Configure the McASP pins
' S3 K! g# I$ D1 k6 q( {** Input - Frame Sync, Clock and Serializer Rx# }$ Q6 s q& g6 \
** Output - Serializer Tx is connected to the input of the codec
; y5 G. c2 n8 e*/
; f. [, a4 L) D- l5 X! S; qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 Y$ a: T* r% E9 N) Q4 R3 a1 A/ q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" [4 t$ J' v3 ]0 R: R# e _' d7 ?* zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 ?7 ~ S& W7 r5 _6 L8 Y5 d2 ~+ E| MCASP_PIN_ACLKX- p( M% d8 ]" u1 m# @# }' q5 b( D
| MCASP_PIN_AHCLKX
6 U4 X: N% D% v& ?; \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- n) g# U ?" ?. L9 K9 ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# t3 l. ]! Z- y$ P3 {| MCASP_TX_CLKFAIL
# k. J! l4 i+ j( G0 m| MCASP_TX_SYNCERROR2 r6 L& A9 [2 G o4 Y( l. G4 H0 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 }$ X5 p* H) Q
| MCASP_RX_CLKFAIL* p" T+ C5 q0 A8 F) @- P) g- r+ f
| MCASP_RX_SYNCERROR ) [5 v+ Y' z# O" v9 I
| MCASP_RX_OVERRUN);
) e1 j% ^9 V1 T* O& s4 u5 ~- F9 s} static void I2SDataTxRxActivate(void)
! `6 V& h# R6 {5 A$ N& ~) K+ d) H{
/ V; R2 d8 e* s( ]7 @/* Start the clocks */
5 m; U! s% Z7 x& oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 ~8 E9 d! b! |" w* {! sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 I% Q0 Y; n. U3 u+ @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
J; e* E1 b' Y+ B" HEDMA3_TRIG_MODE_EVENT);3 U2 {" J* ?( j' d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , X$ v" _9 K1 V X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 S3 {+ Z+ I, ?& K7 |8 p/ k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* C, y) E* R$ Z$ g4 | c- V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- k2 K* S" d9 ]: V! C! a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# k4 a, }5 G- z2 l) Q# J1 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 s( J$ }: z9 Y% h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 E4 H& O g4 Y
}
4 K2 S! T; K& u8 Y3 W/ Z. S" @; v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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