MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
" a2 D$ x! W& S5 [: g  S$ ?input mcasp_ahclkx,
! ]3 F; S7 H4 winput mcasp_aclkx,
input axr0,
3 G, `7 a1 K2 L- O: m
. p; \1 e7 m$ _# Eoutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
( M! N: Z. u8 f5 loutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

, a8 f) l3 B8 ~3 u" b+ n( H6 ?
- X2 a2 L. `' f+ p" _& C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

4 h, H/ ~% R5 d5 t- a$ M* j9 F

static void McASPI2SConfigure(void)
{
+ J- A( q+ c6 _; x/ |" A! lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) p4 R( m" U8 {McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, n0 D( j8 B- b9 J# {  PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' x3 h# C7 M0 h* \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
: F6 m- O. I3 l: W- VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
( ]: t4 d* I/ JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' |% {. j5 A2 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 R+ q, C# K. {; i+ z0 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 A2 ^) Q6 S* e3 E9 I/ P4 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 U" S  r9 H0 O7 m0 A* NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 c$ [2 ^& k7 y" V% c6 O  ]" yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 Y+ x' B5 t; y: K5 M+ B+ o% L8 J0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: Y  E* k. O7 _3 ?& C: ]) l9 FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
8 \9 Q- M! ]7 Y# O' ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 R1 E, p2 w, G# C' QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! I1 Q& m: ]. i& ?+ O1 y7 ^: `5 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% w) E/ N/ Q' ?8 i. c5 D& y2 f* i** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
8 V( r2 }, d- M' nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
+ }8 R% D; N+ F. A+ u- l** Configure the McASP pins
% \$ F4 S1 n, C** Input - Frame Sync, Clock and Serializer Rx
' T; \; e% ?* S( {** Output - Serializer Tx is connected to the input of the codec
$ t1 v: n  H& y7 w+ m*/
2 q7 P9 q# T% F; r& `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- K- f, z, n) r& OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
/ r$ p& X& [- ?& o. M; f, X( RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
2 w, |, n; c0 M, B6 \' z( z2 l/ g| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 b1 A4 m3 r+ N' o| MCASP_RX_CLKFAIL
# V& x) Q7 M$ a| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
, K+ q4 F6 ^5 j# X% y& b}

static void I2SDataTxRxActivate(void)
{
4 L7 q7 N; E* W/ r7 x/* Start the clocks */
; z2 K3 z) C6 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 q9 h+ }  y+ d2 q8 LMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
# H6 D% X* u! |. M; m  x. W0 f3 @4 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 y/ W# E& n8 R* B0 e/ u/ T5 xEDMA3_TRIG_MODE_EVENT);
) k0 j. O3 U- C. `4 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: H5 m2 A9 u* e! X" i; j/ xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* K3 U* R  ~# q. f# R- {: |3 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
/ [/ y! u1 r7 ]- a! w% IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.