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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, Z8 \6 a* w+ Q) k6 V4 m$ e. M
input mcasp_ahclkx,+ v9 j4 @2 q. U2 W" {( S4 }1 C. f
input mcasp_aclkx,
! l0 r9 P n" Y7 ainput axr0,
7 t+ K3 s, C) K- g9 ~4 p2 e$ O0 y: |# A$ I: L
output mcasp_afsr,0 |# @* M$ P7 r8 ~
output mcasp_ahclkr,# h) F7 P/ [" T( U G
output mcasp_aclkr,
# A8 v) F2 z' p+ Koutput axr1,
" I V) `, N& a! z3 r assign mcasp_afsr = mcasp_afsx;: R# V+ u7 s% [, K# t
assign mcasp_aclkr = mcasp_aclkx;
/ S9 E% N8 o7 |( j. gassign mcasp_ahclkr = mcasp_ahclkx;2 l9 P5 M, ^1 ^% Q; a |
assign axr1 = axr0; . C8 s. U% z/ q
! E/ s1 {4 O% j& U: ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, V6 L4 h+ L% u6 xstatic void McASPI2SConfigure(void)7 v1 Z5 f0 F. [6 S! G; o( p
{
; P" [! B# @; x& Q6 H9 g' cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 \7 f/ i6 K3 T4 [+ i$ gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 l" h a- ~9 r$ X6 C) ?: z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! c' \: k' B7 J4 D" o( n7 L" e h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# W- z2 A( U% y3 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; }- v+ o0 }7 z1 F) O4 g
MCASP_RX_MODE_DMA);8 I8 `) T9 p3 C# |$ `! d& f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 z( k% \. M4 [) {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& d& t9 \$ u2 W8 V. ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 g6 V J8 ^7 L! w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 h& i1 F1 o5 Y: G5 a" EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / K: Q& u9 e; }! \' m- R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ }$ c- R- a! `/ ~+ V: J5 R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 F+ }6 ?# Q# g6 G; y% d; V7 z1 N2 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; i' L8 |& W h3 M' `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* V# |- j {9 i0x00, 0xFF); /* configure the clock for transmitter */
' K) a) Z) W# Z$ f1 v) S" S- AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: I% S0 X) X6 K1 k3 _0 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 {+ T& U0 W( K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 P- N$ W3 @" W1 V) k8 Y h0x00, 0xFF);
& r! F- N& Q* e4 J" J+ a2 q1 C- f
1 a( W+ F& ^; j8 F/* Enable synchronization of RX and TX sections */ % J) W& Q5 i/ h/ Z3 @/ b8 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 v6 }/ J" t* O( [; iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 u% u7 E, ?/ s9 `& m/ bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 T+ ?# v8 d- s, Z2 d** Set the serializers, Currently only one serializer is set as4 z: u& H* O% A/ j7 X8 S
** transmitter and one serializer as receiver.
2 u+ N5 ]4 a9 }) a2 V! [*/0 _% e. o, U5 A: u' s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 T. F- ]- R9 x( Y+ z! v' T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; p" \3 N1 e9 `* C& _* m; f% C& }** Configure the McASP pins 1 [6 m S+ p8 T5 t: y( w
** Input - Frame Sync, Clock and Serializer Rx
; }7 @; |& `# I/ F% S** Output - Serializer Tx is connected to the input of the codec - X" Z# [0 `! M5 J* |& t0 q
*/
N* S! A$ m7 w" o* BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& \$ a3 |: ^+ a) a% y% `- xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) t- e, f, \+ V! GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 }' n1 M+ S, M; u0 S/ ^% q
| MCASP_PIN_ACLKX9 E! S; A# q/ q; V' o' D o
| MCASP_PIN_AHCLKX" d i+ q& G: ^/ j- X/ K% `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% v/ O% x& Z8 O; Q) oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 M! g2 j" _4 o& R
| MCASP_TX_CLKFAIL
* p# A) m' F+ V' L! ]| MCASP_TX_SYNCERROR
5 \' r: `& |: l/ |& h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! `% o' D0 o* d0 B0 V3 k! u| MCASP_RX_CLKFAIL& j$ [3 y5 y" P, F$ h# l* u* \5 }$ y
| MCASP_RX_SYNCERROR , U: P' \5 Y" W& k5 G
| MCASP_RX_OVERRUN);3 Q" m$ s2 ]5 {* F8 s# ~
} static void I2SDataTxRxActivate(void)
4 C9 B% F! ~! D& I- o/ ?9 K0 Z{
1 Z' W, Y0 S& C5 B/ Z: T2 T/* Start the clocks */
" Z1 ]' F0 m5 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 N% `# P0 a- UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 C( @( E: k* F5 P/ d! @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 Y' Z- S% d9 j U) o2 u# b4 T' @EDMA3_TRIG_MODE_EVENT);- V( N9 M. \4 X+ j& K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " Q" @$ k+ {* @3 v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: I# O! U L) O! N" p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: j2 i- p' P2 w, \" F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! N ~- m/ K8 T$ x# I7 Kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* v% Q8 G7 ^+ i/ n1 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; x0 C8 k$ \) l# T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% _8 k/ P2 t. V+ ^; m" ]}
4 r/ B( S, U6 @( D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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