|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& H6 p2 c( C* G+ x, M# einput mcasp_ahclkx,
; p+ M2 t6 _% {' G; c! Sinput mcasp_aclkx,
, `' r* y+ Q! o5 Sinput axr0,0 P8 B* d% O: z) }& o5 |
; i6 k" q# k) y- s
output mcasp_afsr,5 a. f+ M& q4 L$ D' j/ y
output mcasp_ahclkr,' N" z& p1 t7 E8 T& u5 k) h
output mcasp_aclkr,
# h! @. U- b3 A: R5 I. E7 \output axr1,
% A, x" [$ z3 P3 H assign mcasp_afsr = mcasp_afsx;
1 l1 U: {( `9 A3 ]! sassign mcasp_aclkr = mcasp_aclkx;0 S" S0 G9 T- ^% ], D/ @+ n- M' [/ e
assign mcasp_ahclkr = mcasp_ahclkx;
8 C4 n/ P7 E0 [assign axr1 = axr0; : @1 L# {* t) a, N: }3 P
4 d4 e1 l( m- M- y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 F% X M! |5 V6 D1 p1 mstatic void McASPI2SConfigure(void)
5 H# n. t! Q2 p+ }: _7 S) J{
' y8 y/ @! y: K) l5 S( lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# V2 z- \6 r) j* T/ _, J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 g5 |2 \' K7 n3 ]! EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# l! P6 J- R; M. s/ s8 v' c$ k4 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ Q" E+ \ p# } w! V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; C: k: j" ^$ s$ y( A0 t
MCASP_RX_MODE_DMA);
, G# d; |. P5 _1 a: C" j0 vMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 ^$ O: B: |/ C- [6 h% RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ `% j) j# u: W& LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 N- p4 P6 T$ Q" S5 a; G% S: H+ w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 |2 e2 q- J, x" NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 O9 x9 |9 E$ G2 L& m/ f- M: uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 H; k) l& H3 N; s- @* S: N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# l- V, m. x& Z" |; N% xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 {0 [! { K, N( s) `' ?' {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! S! W% K# s5 E2 z! v0x00, 0xFF); /* configure the clock for transmitter */: N+ S+ B: q/ q" U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ s6 T. }/ L) |- X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* ?: q$ F+ L8 X2 b$ `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, ^$ Q) X2 q2 O+ d$ {
0x00, 0xFF);% @" \+ U' k# t$ q
1 c' f/ F( N9 X1 Q8 J" S/ B A
/* Enable synchronization of RX and TX sections */ - i, I" P7 Q0 J) ^0 u1 F8 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 ?" k! W1 r" B# h# K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ |4 c9 e. B9 n# ~, i0 v4 b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( S o* h2 p3 R** Set the serializers, Currently only one serializer is set as N! c0 W* f" l2 r* U8 D+ R9 p
** transmitter and one serializer as receiver.* \$ h% u! x% F0 M* D
*/3 \- Q% S0 A _" n2 A' F; P2 h3 J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' o( S- _; f% T; F1 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 W, f1 @ i% `- ~! \. ~** Configure the McASP pins - k7 s1 H& t7 o; I+ X
** Input - Frame Sync, Clock and Serializer Rx* r* d) \' h3 Y1 o2 v2 i/ r
** Output - Serializer Tx is connected to the input of the codec
1 R5 ]5 v' M" z*/5 ^+ E5 }9 l4 n$ j$ T/ {' a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( X$ ?: A! m" ]% W; H; MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 @- J( s! b) \, t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* f' E1 e5 C0 b: I. G| MCASP_PIN_ACLKX, y5 B' K, j* @9 N9 O
| MCASP_PIN_AHCLKX- O# u) X6 F6 D. p6 h9 l6 c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% z3 @% }# D! `7 y; A IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # K, V ]6 o& O
| MCASP_TX_CLKFAIL
0 h" L) @- q, k$ l7 p| MCASP_TX_SYNCERROR
I0 n7 ?9 O$ m; O: b, \0 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: w! `! v0 X( K1 z/ v* e0 }| MCASP_RX_CLKFAIL
& v# A% c" ^9 h& r; v; c| MCASP_RX_SYNCERROR
# h* W0 K( w, ?7 r: z& Z, F _| MCASP_RX_OVERRUN);
8 U) v! l2 o2 j2 D9 U} static void I2SDataTxRxActivate(void)
$ z2 h2 y6 v$ x* d1 k{& n" R! k6 u% v' l9 Q0 w8 k- y
/* Start the clocks */
" w9 a. `) n% @1 _" h5 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" K P M# G( \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% v! a# W8 b# o J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: H5 y3 K. a9 o+ B# L# K c ]EDMA3_TRIG_MODE_EVENT);
3 V, ]% S: x* bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ k$ J6 R [( ]; a; PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 A) J) ]& h( }' \' [' a9 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ l5 ?0 K! y5 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# K+ Y- i0 O9 ~2 P( wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' }; S7 C! B8 N% s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& [, |3 }1 x5 T1 y/ p& f9 [8 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS); R* E! i. b5 L
} ) p$ p5 U9 r7 o D0 o4 V! X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 J; S, r# W4 a% s
|