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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 Y* ~0 C# m1 C. l( B% y: |; Cinput mcasp_ahclkx,; R# r9 e* {" q: k9 `' \
input mcasp_aclkx,
1 P. M; Y# ]/ j6 x5 n8 n* zinput axr0,
) ^- i" S- P. O0 |6 b3 p9 K* C4 E) T U# W$ D! x" E
output mcasp_afsr,
$ E# Z& `7 N% ~( q1 s0 P$ e1 Aoutput mcasp_ahclkr,
2 `# E3 D9 n& y; c. Z5 d8 ?output mcasp_aclkr,) N- w4 Z6 [# r, u; y) x
output axr1,0 z9 Q9 R1 @- i6 q' h5 S. b# V
assign mcasp_afsr = mcasp_afsx;: p5 G" J: i/ M, k/ K8 _) k
assign mcasp_aclkr = mcasp_aclkx;
. u2 V. c% r9 H% O1 e8 \assign mcasp_ahclkr = mcasp_ahclkx;% v6 Q9 \- u& T. c$ ?1 T% `/ t) k
assign axr1 = axr0;
/ J( u) X& z1 O Q9 v' {! O) Z6 K3 l* }7 i2 d; ^$ N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 \! J; r |, B, r
static void McASPI2SConfigure(void)
) I4 B3 J0 l7 y t/ W{
2 g2 s7 \3 w w/ JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 ?& s. [7 c1 B! x" Q" nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 [% S" r& k( L! R, c7 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" ~7 m9 i2 F/ z' x/ b+ s; }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) ^- o' V5 d- u* IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 M' L8 o W8 v, h3 q' Q/ C, @MCASP_RX_MODE_DMA);
3 \5 o$ d; D! K" Y0 i! \: X4 LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 B d" ?* M3 E8 T6 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* V1 n7 P, h6 i4 p {6 KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 V0 D3 j/ J. H( e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; ~ o% p; ^+ H/ l- j h6 u, D5 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% M L9 F. D, n3 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ F0 M- r- Q0 P' f# H+ j/ ?% QMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 ~ x4 I. B" D. c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
K2 k% b9 Q3 q2 B2 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. \/ g. Y- A$ N5 \7 V0x00, 0xFF); /* configure the clock for transmitter */: r& B( V6 F4 B9 \! Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) t( c# N1 ^! d6 P4 F% d! F- @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 W( C2 G ? M I) `! q& KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% b @. K" K6 E
0x00, 0xFF);9 |- O0 J3 |' G. |9 g6 j
) _' C8 q; j+ ^4 b i9 X' }1 r
/* Enable synchronization of RX and TX sections */ # G2 t* O0 o1 J. w l" w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& \ A$ b6 y+ }2 v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 a1 x- }5 o; j2 T, O. u$ {+ l3 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" {. j! B( y& U9 x b
** Set the serializers, Currently only one serializer is set as
2 b3 `2 R7 K& V8 N7 [** transmitter and one serializer as receiver.
) ~& o% z3 q; \9 e# H*/
: x# ]5 E7 o% K" UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; k# _5 F, K) n- z$ GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 I o2 g. q, p' m8 b** Configure the McASP pins ' D( W3 f" |$ L' l
** Input - Frame Sync, Clock and Serializer Rx( i6 n X" ~( w) p, U3 ~/ \5 ]6 M; s
** Output - Serializer Tx is connected to the input of the codec 9 q) ~+ A8 \) [6 w
*/
6 o3 `! w) U6 r1 }; m9 Y7 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# Y) x U9 [' W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); ]( Z/ O _# r7 T8 ~% d9 _% x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 J& H4 d# S( P! j. P5 n9 M+ G) V
| MCASP_PIN_ACLKX7 _5 [5 x* o s* z
| MCASP_PIN_AHCLKX& M- O0 \# |/ `0 Y+ e S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 ~( f" z3 d" _6 U: m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) B8 o+ |6 X# j| MCASP_TX_CLKFAIL
8 K5 N; q% d8 {, ]6 n| MCASP_TX_SYNCERROR
" I+ ?! N2 b7 R4 ^ _- j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 e# J# G7 i' f8 |* s% X& G| MCASP_RX_CLKFAIL% O8 [0 v; v9 D8 J
| MCASP_RX_SYNCERROR 5 k0 P% g" @6 X
| MCASP_RX_OVERRUN);
, X# V4 i5 X8 w6 t: J' g& k% \} static void I2SDataTxRxActivate(void)
8 z6 M y: A( F! W{* I+ C# V/ O4 J7 n9 d( y1 D
/* Start the clocks */
- z; }+ _2 F$ [; F4 p8 |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 c& G$ u7 y i' U1 `: s$ SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, J. B/ y# K% q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, {1 F7 m2 _$ D7 R. O7 B$ U
EDMA3_TRIG_MODE_EVENT);( w4 X& F3 k; g' c {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 P1 `7 k( V$ X6 c4 Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 e6 v6 A0 H M# F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 m& L* S! h0 BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 F4 ]7 R+ ^1 `9 j, P3 t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 B& D- ]& d7 m% J0 b( R- N+ M( WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; I( d% w8 L1 \& |; ^8 i! [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) ~. O n" g' M2 [/ Y}
% l/ h2 F. X/ p2 J0 X' d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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