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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 N) H. G9 z$ c0 Xinput mcasp_ahclkx,
% C8 ^( i) X. k# w% }input mcasp_aclkx,
' r" G/ ^3 w" D2 @! O# g( j. W2 ^input axr0,
4 Z3 F K0 ~* A3 z; M2 h: {- s% X
: w2 G. _! L6 g/ v8 \4 Q* ioutput mcasp_afsr,
/ W4 E) P- ?# k2 foutput mcasp_ahclkr,& F V: a2 q s3 j$ |' f
output mcasp_aclkr,& x9 B" _& N6 _) Q
output axr1,
3 P2 b2 H, \$ c4 O5 g assign mcasp_afsr = mcasp_afsx;7 X9 _! m" x. {
assign mcasp_aclkr = mcasp_aclkx;
* P' g! s+ L% ?7 O4 p- hassign mcasp_ahclkr = mcasp_ahclkx;8 o/ k- L4 o( L1 }+ }% Y
assign axr1 = axr0;
$ {! C; X% D' C2 T) b1 A, r* L0 z% Z3 g* o# ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 d' ~: g# j, v# N7 `3 Q, vstatic void McASPI2SConfigure(void)! x& o) P" {' j3 @. n
{5 u5 p2 G) A# g9 w, V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; r( H0 f$ ^2 X! Q* x; l" n. H' T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 P: `% \+ M+ [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' h' D3 K% u+ N: [/ x# k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; f3 S2 [* F5 ~1 \- k) h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 A0 ~" M8 W% R- }1 B* L
MCASP_RX_MODE_DMA);
/ x! P5 H$ j3 V6 Y! S8 \+ H) z7 \- XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# c( b5 l; `4 V2 J# m3 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 J; j" j* K! b# R: ]$ R4 r0 l7 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% f; n( a# ? @3 c1 Z, E4 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. O3 z P/ G2 b/ L" D, _0 ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* j7 }: K2 @# g/ a" |% fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 W1 c8 R( a) N- R0 c8 ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ G, [1 w& d0 L" b" G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 u# W5 {' r$ S0 X+ C$ Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* S# i9 a7 `' ?5 ?5 K
0x00, 0xFF); /* configure the clock for transmitter */0 [3 ^/ H, E1 `3 l5 V, X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, T4 D' u: R+ C% v+ F6 U+ DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ D" O" A5 v/ m1 T7 d! `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," P/ u( P B! L/ d0 b
0x00, 0xFF);' c" q! v& a) Q: m7 e
" {3 \# i$ M. A- c ^+ W- |& \6 V
/* Enable synchronization of RX and TX sections */ 9 H& B3 M1 {6 `4 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 E1 g" Q* H, k s* w( o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% t) S2 x$ P3 \9 k# j; [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 n8 R P: w9 s; I** Set the serializers, Currently only one serializer is set as
& V8 R8 X! O& @8 f L; H. Q1 c9 f** transmitter and one serializer as receiver.( U* E+ x# q8 T) w6 F
*/9 S% x7 C1 N6 e: A8 C- W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 D6 |. @& ~) p, Y# e+ T* E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, Z E2 f9 p- ]- Z** Configure the McASP pins
; z9 ^. |0 S! _% E** Input - Frame Sync, Clock and Serializer Rx
$ s; x4 H, N+ L5 f$ h** Output - Serializer Tx is connected to the input of the codec 7 v* B: E9 f" r
*/* |+ F# ?4 z9 \ E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" e+ K! z, C) Y2 g* h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& P X7 m. G; p! @) B; T& S, O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ ~! Z% u9 Q' E4 v+ I3 w
| MCASP_PIN_ACLKX
8 P" @3 T7 A& |" v| MCASP_PIN_AHCLKX- o- J7 F! v" k2 z, H' ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 i) j. L0 P* Y F G) J% g$ O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - ^/ G, u- |& r6 h0 H
| MCASP_TX_CLKFAIL
! D K" O8 V& P| MCASP_TX_SYNCERROR$ y$ _7 ]) x: `. Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- P( D. K, O) c9 t! a* _# ~+ x| MCASP_RX_CLKFAIL
1 `$ Y, B9 ?9 h, z| MCASP_RX_SYNCERROR ~# q/ r. j$ g) n" `( T
| MCASP_RX_OVERRUN);
4 O6 F3 ?9 P9 U- g} static void I2SDataTxRxActivate(void)
4 z+ w, Q$ ?7 r0 x5 [) a: n; j0 L/ F$ m0 q{ w- b) v+ `3 j% M
/* Start the clocks */
% ?* j2 b, j) F& _+ c. m* lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, ]( h( R0 P8 g R! H$ s. |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ V# ]2 l6 t6 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' X" w! v' S4 a, e- \. r; _
EDMA3_TRIG_MODE_EVENT);
5 h. h/ n4 o, U* C z; ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 j7 w- n: s( E: b$ l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. [# u+ t0 o/ C: q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' w, B G0 `1 U; b }/ T4 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' Q9 s2 i- i# `- K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 U% l j- R8 n" `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( d3 Y* _8 n+ y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ M+ i7 i, p" G8 t
} ' W3 S2 K% \ H1 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , d7 p3 W1 @( h4 F; y7 @
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