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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& g& I# f& }4 L- Tinput mcasp_ahclkx,7 d& _) J: Z: D- b
input mcasp_aclkx,& s+ L6 n B# g& Y* L; Q3 G
input axr0,
# L: P. A3 g9 U' ~" V; D% t2 Z
$ x+ N. q" r$ S* y' I) U0 aoutput mcasp_afsr,
2 I8 f& V$ D' S. k' a7 Koutput mcasp_ahclkr,
6 Y* G2 k3 g" `0 t: _% Xoutput mcasp_aclkr,
8 p! g% q; l6 B, M% m- youtput axr1,
8 C# I) \ s9 W% t/ d1 h6 Z" ] assign mcasp_afsr = mcasp_afsx;
\+ C* X7 n9 \assign mcasp_aclkr = mcasp_aclkx;6 K9 j' w& P" V- i3 `* L8 ^* _
assign mcasp_ahclkr = mcasp_ahclkx;
; I; x1 ?- w* R/ r y# a& Iassign axr1 = axr0; 2 }9 c2 r. G" f/ j* X
7 ]( U8 `5 g g( P3 a y: O( n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* ^! i( t; e/ S3 y" Fstatic void McASPI2SConfigure(void)$ e. a P7 w( v
{: @$ ?1 O% X3 Z! t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ {3 Y: X' T% }3 b. P) Y+ A7 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ n, h6 {, N# @- E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: X7 v) k$ E( SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& m- H; N4 O6 n! x5 J4 wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& x* S3 P0 W' g# d9 d
MCASP_RX_MODE_DMA);0 p9 I9 w7 a, L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Q: x0 p6 W: \4 z1 Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ Z+ `% E+ M- W6 ?* W, @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 w: O0 ]4 o0 ~" M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 e5 E6 L3 B8 k7 V7 a7 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 g8 z( y o& r& K9 ^; j" X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 _2 _$ C5 _. t0 J) O1 h3 Q" o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! [7 E: P% u0 x6 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% m/ \4 n# \% _: ]7 z+ Q% SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ o* Y' B- l" b( r0x00, 0xFF); /* configure the clock for transmitter */% j( J. i0 n& \% t; O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- A& I( @, \5 }* F7 L/ Y. l7 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 Q! \5 n% D2 J4 O+ m/ Q5 H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" g' n0 h7 i9 p+ K0x00, 0xFF);" g' }. `4 y7 v: m. y
! R; L* u5 p* a: J4 Y- f7 S" ~ [" b
/* Enable synchronization of RX and TX sections */ * ^9 t" _6 ]5 \5 p s2 }2 e) r+ e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! `( h5 m, O+ c$ ]3 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 W2 V- p9 H; G& {8 g% V. [/ m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 J% m$ B' U: n9 Y3 ?** Set the serializers, Currently only one serializer is set as8 O7 ]% e7 o. t8 W
** transmitter and one serializer as receiver.2 f9 y. R+ x* x- n- E) w, Y
*/
" G. j# D' i( X0 w( d% OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 n: ]: B2 w# Q5 y+ U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 k2 g4 s* [( [( n
** Configure the McASP pins
/ M' F5 a9 b: }0 w** Input - Frame Sync, Clock and Serializer Rx _5 i, @) e: u1 J2 @ }
** Output - Serializer Tx is connected to the input of the codec
# l3 k& U: ?2 z, a3 }# |* Q*/
% b7 G4 g& w' x9 i1 y5 ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); S" ]* c! X2 K' m3 z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% I" g" h3 j; [9 \+ Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 K8 N% L' \" }9 w| MCASP_PIN_ACLKX
; ]: }" @# J& Z4 q| MCASP_PIN_AHCLKX
) O4 b- a, Z6 a4 k* A2 E; T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 Y$ _/ s3 k; L/ E4 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + a# S) ~/ g( U
| MCASP_TX_CLKFAIL 5 D' J7 D8 i! F
| MCASP_TX_SYNCERROR
$ D0 v9 z! w- s& h4 g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 O; |, n; @2 K2 w! ?, D, Z| MCASP_RX_CLKFAIL
7 `( G) L' ?; @* r# U b| MCASP_RX_SYNCERROR
5 l0 G* J' @$ i0 z) }6 F| MCASP_RX_OVERRUN);( I3 d# x8 Z6 l" ^% d* l
} static void I2SDataTxRxActivate(void)/ T0 p- r7 p9 p( G
{6 u+ u' o5 d9 l2 h' _) y
/* Start the clocks */) D- x, {; `4 u# z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 Z( V: V" s# _$ D1 C- \2 x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) B- A* C/ s2 H& hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% y! p& l$ n P' b! G' K& ~: ?! TEDMA3_TRIG_MODE_EVENT);7 x' n/ i. w6 U( A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: q/ S/ |) H- ~8 x/ {6 }$ ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 t3 U- Z$ ^, X/ s( v5 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. \+ ?( U, N5 }! N& X0 t" m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 F r Y6 |) G) L3 x$ J: _. C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! a, h. d: Q' O% z* b! R, _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' h5 T$ ]5 x) j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 v5 r& K7 o0 g o
}
4 u3 u+ x9 ^9 d3 L- r3 B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + S, k( n8 d3 E2 ?
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