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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. i6 D) f7 u% }input mcasp_ahclkx,
' t* p" f; ]" N) g8 W3 c9 x' y. |input mcasp_aclkx," v$ d: g/ i# a+ G$ z# ]+ T
input axr0,
" w0 E! U& V' N( _6 Q( s
1 ~% W2 u( s/ k/ ?$ z- I4 A n6 Noutput mcasp_afsr,/ Y b! t) V, Q7 e) _( a
output mcasp_ahclkr,
* j2 S. T5 }7 Q/ X0 xoutput mcasp_aclkr,$ r; J% ^0 H5 _5 Q z* v3 k K" c' t$ V% U
output axr1,
% V- a. p2 F7 X) ] assign mcasp_afsr = mcasp_afsx;
6 F5 |( g' ]3 t8 ]3 r+ dassign mcasp_aclkr = mcasp_aclkx;
( v" z8 X9 H( c: o( T- Xassign mcasp_ahclkr = mcasp_ahclkx;
8 V; e) G* L% I% B$ V1 fassign axr1 = axr0; ( ^5 P" \; r* Z6 W/ v; P
6 Y; k8 v# N8 t4 b) J" S7 ^) _5 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, G" M7 @1 b# c4 Y- Mstatic void McASPI2SConfigure(void)% x- \4 B, _# ~8 B! V5 u# j5 n
{+ s& r* a4 L/ k5 `0 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& j+ y7 ]$ |7 b8 z" iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ P+ Y) F; X' t6 k/ L3 _$ A) F" cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ p- b" a9 g% Y& [7 N/ r. U- IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ k& Q) @# L, I/ T9 [4 x' n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 e8 ^0 D/ ^8 ~; w- X) A: F" V
MCASP_RX_MODE_DMA);
. x; V! u8 b5 N( eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' h9 V: E- I; P8 r. u3 u0 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' f1 W; }9 y N( D& J2 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 A% z) m ?% I0 ?% S4 z0 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- f- d5 S( J1 Z5 U! Y& @( Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; w. g. ]6 @) D! ?4 d$ |* G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! Q- }9 U/ C8 X/ _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ h5 M* s. ]( ?, r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / J+ \5 R: p7 f, G+ H0 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 o6 W, G" ?3 R. x7 Q5 w# Y9 B' T# y0x00, 0xFF); /* configure the clock for transmitter */
. \' i/ N3 ]; j' kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- ^ e. {- j# F7 {4 ]! S! e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; u* O# D( ~7 g4 P0 n: v# x. i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 \( c! }0 B# K( g0x00, 0xFF);9 q* W6 O/ _ n- A+ k
! T% c! T+ b/ {% x) ?* q9 m Z/* Enable synchronization of RX and TX sections */ 0 n0 F$ M4 t8 R X6 W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 F: h$ Y2 W1 h. k- l, J0 s8 N/ p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( g ]) h7 U: d. G5 \, T0 g L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 T$ L. C6 J' a" B2 l** Set the serializers, Currently only one serializer is set as9 Y# ~( u6 |9 ]: D M
** transmitter and one serializer as receiver.
# t1 s0 Z# M9 m" J# Y1 K! q*/& v: n4 }( Z3 y6 x. ^* t/ [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% p7 w, k; B' g! i d3 j- ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ S- z. W2 }, C- }** Configure the McASP pins - k: w% O6 q) s
** Input - Frame Sync, Clock and Serializer Rx( c' D$ n% I9 f; v: S
** Output - Serializer Tx is connected to the input of the codec
# U3 i B2 H5 Y# ^4 ?- {*// z0 D& K# I! O' @ r. x) S6 @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 y& b0 A" ?- H* U' f, A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 n( F/ n% v+ L9 _% v6 G0 cMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ T% l: O' T* [7 @
| MCASP_PIN_ACLKX8 E" Y; D4 l3 `# S6 s
| MCASP_PIN_AHCLKX
2 s2 J2 @; M1 L# Z" U6 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) Z9 b! r5 E0 n' r7 ?% b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' s2 N# b0 P# k6 R3 r; a
| MCASP_TX_CLKFAIL 9 `5 J: E7 l# T1 C
| MCASP_TX_SYNCERROR* y( p$ N2 z! `+ o$ l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 r; j2 F# C* C% U& k
| MCASP_RX_CLKFAIL- g4 l" h8 I: G+ c X7 X
| MCASP_RX_SYNCERROR " S# F5 Y8 v$ h. V6 x0 P0 x
| MCASP_RX_OVERRUN);. |$ b- }% d: j
} static void I2SDataTxRxActivate(void)& @6 d: w# t! I9 ~$ D" h9 j
{
7 C& d g0 @1 L, m3 f9 p* x* Z/* Start the clocks */* ~- E9 @! l2 [7 x9 E+ J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 r! [' B8 ]+ c- IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 u2 x/ F; |, ^* P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& _2 ~6 l+ R7 m5 U% XEDMA3_TRIG_MODE_EVENT);
" U9 b) e* V) \ c7 |7 o6 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 s+ J" y1 T6 a( hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 [: C! q Q3 W7 ? Q% u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 n! r4 F& M& t& a ~! p1 F+ E/ U4 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* ]" |/ G$ _" t, {& p N2 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 _6 @; `0 R5 q# E7 {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 d2 [" O8 r- \" hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 T# O2 m3 f. J+ k; N+ B+ u+ \' e
} / Y' u; |, U6 X8 S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " c* o3 c6 D; U' b* M3 ?5 M4 X
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