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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; G4 o% E! R9 v- z9 Y$ M) uinput mcasp_ahclkx,. k* J- ^- L, A) u
input mcasp_aclkx,
* T+ X6 @- n! c' V O1 l4 v) Iinput axr0,
6 T0 _& [5 N& g0 M
* u$ G1 I3 h8 p$ L2 x# \0 soutput mcasp_afsr,6 ?1 s4 @$ G$ w% U. W3 a3 l
output mcasp_ahclkr,, ~5 P5 Y5 {# q
output mcasp_aclkr,% h) C% r/ s# ?' y) j/ u# A \/ ]
output axr1,
+ n( C7 G1 j* ?& s; | q: s# O assign mcasp_afsr = mcasp_afsx;
& u0 e% P5 E" g* U0 Bassign mcasp_aclkr = mcasp_aclkx;$ e1 p" K' M, F: R! U
assign mcasp_ahclkr = mcasp_ahclkx;
; T5 V- L* K$ q- B- A; Q! k( Z- i3 dassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 Z$ f% C L+ [) N/ L; r# T* tstatic void McASPI2SConfigure(void)
x0 P& `( k2 l4 F0 Z- }% f! c2 Y{8 h4 v- n) Q, n/ L6 N( L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ e) W* t/ R4 ^1 w9 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 c1 [) h, d y; K. E3 q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" L* s/ N+ U" @! m& YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 {" h& O4 q. L6 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Z C/ @) B8 ~* m3 ]
MCASP_RX_MODE_DMA); z2 f# ?- ~6 R- _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 d6 O* L+ e+ t, x+ GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 e7 I5 D1 C$ H5 Y4 q, eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 j" a; [: Y& ]" [6 p7 C: r; NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! O3 _& |4 s! c0 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: P: b7 H* x4 W' |: x4 oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 r- W9 S$ \! ^4 G9 o! j6 o! jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, o% t6 D9 w) C# M1 V/ oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 g5 V7 v% N/ H. N+ I k5 w+ c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ Z# S7 O; F1 \0 X. B! [+ V5 s0x00, 0xFF); /* configure the clock for transmitter */. a8 b( B+ Q- t' z! H$ l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 L: |9 w d9 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 P: h U x' E x) P/ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 S+ `) Y6 G/ s) X+ Y0x00, 0xFF);
. Z+ ^( \& ?, U9 @" M
+ Y9 s* x+ R# s9 _- `: i/* Enable synchronization of RX and TX sections */ ' t3 Z# b! X% W( D# g& r* Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ K/ X- V+ V! i5 o# U7 _7 o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" G: H/ r0 G8 ]# Y6 C4 Y* n, X6 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# w+ O/ r% r% C1 n$ X5 P. `" V
** Set the serializers, Currently only one serializer is set as& Y1 c* N' V5 D6 M( E; X
** transmitter and one serializer as receiver.) P5 [5 ]9 e# r1 Z" H. Q/ O3 }5 E# d) q
*/
+ e) s( m$ R% e6 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 j( T: n+ [, V! J5 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' g9 n. N( w; R- g2 x7 c, @/ B: }$ M** Configure the McASP pins
. [( N! A- A9 r** Input - Frame Sync, Clock and Serializer Rx
$ {: S1 @) o( @ L9 ~** Output - Serializer Tx is connected to the input of the codec # E- _6 T# ?8 s% D, w' K" T0 ~
*/
6 I# H3 Z) I8 e. F# b- QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 W5 x- L5 Q$ Q' b$ P1 `- n! [3 o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ Y7 r9 z! v) f7 P: q. h8 n' DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 K4 H( ]$ g$ m) w: H) j1 A
| MCASP_PIN_ACLKX
4 x& K: x0 k# Q* J# L| MCASP_PIN_AHCLKX
5 i1 F: [+ M- m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' ~6 P, N, [- v) H- [* ], HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # T [0 q$ s3 @/ _7 b
| MCASP_TX_CLKFAIL 5 Y+ |, k, x4 h; g
| MCASP_TX_SYNCERROR! }5 Q' S1 x; |, v! \0 o3 r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 S# G2 U! D8 I| MCASP_RX_CLKFAIL
# t9 u, j$ \8 J2 q: N6 c. W" E: X| MCASP_RX_SYNCERROR 3 X. H+ B4 C8 ]/ T8 q, f/ a" U
| MCASP_RX_OVERRUN);
* O2 ]* }7 _; ]/ a: v7 h& X) ^) k} static void I2SDataTxRxActivate(void)1 {3 y, K8 W0 I) {
{; @: P4 `* ]/ \/ x ?; a Y- o* P
/* Start the clocks */2 I' f, o; y0 _- q+ ~! Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 n/ H T! w4 v2 L* FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ R5 P- ?$ ]' T; ]& p$ W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 q4 Q2 X" ^, S( B$ m0 FEDMA3_TRIG_MODE_EVENT);
# U0 N% ~& o0 J& `4 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 C) x. @& [$ ]: Y* _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" ~! r$ u8 r! S3 w% O$ m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- {1 N: |( \: b; s0 a3 q8 o a' ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 F; b8 t. n+ d. D+ k* m, jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, f+ l5 { T+ v( y: f1 R: _* P5 t7 d9 p7 P/ qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& a. Y; c/ W1 A8 s7 A5 s! W) EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* |; f9 G* f9 r7 X5 I+ H} / v K: |3 A0 l! {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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