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我的McASP配置分别如下:4 B7 T* w$ b8 _2 Q) V
管脚的复用设置是:: k7 k9 y: {2 }7 D6 `" V% Z: G4 a
void McASPPinMuxSetup(void)+ z0 Q* N( F: X: n/ }
{, v0 k+ w0 {3 e' k1 F
unsigned int savePinMux = 0;& Q) C) C# N: F2 ]! M$ D2 @$ h
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
x1 S) `& N( q( H$ N2 ] ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
: @0 w8 j- t# K b SYSCFG_PINMUX0_PINMUX0_23_20 | \# Z3 ]3 k4 t& W0 }& ~, E. Z" l( V, D
SYSCFG_PINMUX0_PINMUX0_19_16 | \( h0 f, Z' N1 ]) N0 m
SYSCFG_PINMUX0_PINMUX0_15_12 | \- q! C1 I, X6 M" c* r+ |
SYSCFG_PINMUX0_PINMUX0_11_8 | \/ e, y1 Y, Y6 ]6 k( X
SYSCFG_PINMUX0_PINMUX0_7_4 | \9 s! t. I3 `; I) x# Z* A+ y
SYSCFG_PINMUX0_PINMUX0_3_0);+ c3 l# V a: C
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \" K' t$ s2 D! _8 F$ H6 r# t2 N; ]9 B
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \; h+ I) F; A4 h, w( d! Z! k9 R
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
4 W1 o- N3 Q" J C3 W0 ` PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \' p' ?/ p5 `, b
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);9 e2 R2 e8 Z; j6 p& a- L6 L) A
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
5 f! K# d( \+ y+ [- j& k6 k% W) F! h ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \$ q/ P$ d j, W& z% e- G. |5 G
SYSCFG_PINMUX1_PINMUX1_15_12 | \
+ [$ g& K) Q# W, r& r SYSCFG_PINMUX1_PINMUX1_11_8 | \5 E; a% Z+ ^7 z1 e5 } {8 {
SYSCFG_PINMUX1_PINMUX1_7_4 | \
# O+ f# Y5 t5 `) N# w SYSCFG_PINMUX1_PINMUX1_23_20 | \! U$ E) k2 ]- r5 s( [, M
SYSCFG_PINMUX1_PINMUX1_27_24 | \
- b( e4 G0 Z( v, j6 E SYSCFG_PINMUX1_PINMUX1_31_28' y$ v& c" J+ h; Y$ v
);/ s+ H' O% w" B
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \: s' U7 \4 ]& F' T: q- d
(PINMUX1_MCASP0_AXR11_ENABLE | \' e$ e% g- M" O: _9 F6 i, b
PINMUX1_MCASP0_AXR12_ENABLE | \2 L+ @5 J) g0 K
PINMUX1_MCASP0_AXR13_ENABLE | \0 R" w8 ]1 A* c, a# q" Q5 b- S
PINMUX1_MCASP0_AXR14_ENABLE | \
1 W2 }; r2 A' Y PINMUX1_MCASP0_AXR8_ENABLE | \6 n- l8 b* [- }) t+ E6 i
PINMUX1_MCASP0_AXR9_ENABLE | \6 |+ e( M* ?5 C: g+ V( L
PINMUX1_MCASP0_AXR10_ENABLE | \3 Y, d; {0 u' ]- h5 }5 {- q
savePinMux);
- a- V1 D9 C. `8 P A! ]4 H6 L}/ x2 z! ~ [: t0 n. x
8 F/ P. g8 ?5 c8 R6 |; \
1.McASPI2SConfigure(); McASP的配置程序如下:
! ]# L0 T' R1 \7 _# p4 Ustatic void McASPI2SConfigure(void)
4 V$ t+ q9 R! a{8 O1 ~2 Z ]- Q" B" E! K V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: M6 G% Z* _/ c8 _% n+ P- e McASPTxReset(SOC_MCASP_0_CTRL_REGS);6 O. h, V4 a( B: k6 m' w- w* @1 g
( w6 \* @3 |' m6 F y+ t# } C8 R, A /* Enable the FIFOs for DMA transfer */8 E k& z+ s$ Q' G! M' n
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
* r+ b0 Z) U# }( ?; F7 s0 J S// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, g) X! [: R. T' v8 e$ g2 i9 t; w
X: Y8 G! n" {/ z /* Set I2S format in the transmitter/receiver format units */$ k1 D7 S5 \& W6 n; K8 [, F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; J# n' e: X1 V, H
MCASP_RX_MODE_NON_DMA);
. |9 V ~: ~2 S) l McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* P7 q6 Y% v" P* @& w3 q% p3 ]$ o% M7 Z, m MCASP_TX_MODE_NON_DMA);" ]+ m8 \7 y. N0 C
6 `3 [* N' Z7 V# W1 V
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. [& N( g# W' ?' c3 j+ x/ y u McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( N; f* s7 S% }7 J& q$ w, A MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 d) `4 A% x. q4 f+ \( } McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 _( M+ F+ d- }7 N$ m MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);4 w- }$ y( D" @
$ ~% w6 M/ V% O7 C/ w2 N3 P& P /* configure the clock for receiver */
) D& q$ F. }! A// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
7 I* @& K8 L1 |! ]; C McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" U& a f$ B9 I; O8 C0 X McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);8 |- D* V0 p1 A2 J, X4 f% |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( [. P2 O; _1 b# s6 S
0x00, 0xFF);
9 S2 n; \+ w/ I v# \4 _6 W: N6 c8 b2 o6 A
/* configure the clock for transmitter */4 W0 S1 W' l) r' |9 K: P
// HWREG(0x01D000A0) = (0x00001F00);
9 {# a' A# J, J; ~// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
t! S. C5 i( G McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);. D. V: u+ Y; {) t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);! K! i) U6 D/ t# y Y6 E2 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, @8 e- @0 K, }" r1 k6 v 0x00, 0xFF);
) L7 z: p+ |6 ~8 Q9 J1 c2 Z , [9 ]! k4 [% T3 J: F
/* Enable synchronization of RX and TX sections */
% F" p6 I. g: L1 F- \ McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);: ~" N5 l$ N$ `+ O3 O8 ]# s) _
! X2 a3 C3 }4 y# m
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 M+ \% ~, u- |6 h8 o0 O McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 z0 \, a+ P: |4 N& r McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# K" ], V% V/ a! N: V" l
* X0 _* |% z+ u7 N7 R+ u /*4 X1 b8 U7 m0 z: q$ E
** Set the serializers, Currently only one serializer is set as
/ b. T4 M8 @; m# ^ ** transmitter and one serializer as receiver.
8 g0 W# P9 p \) p6 {2 B& B+ `/ B */
o1 f( s6 R& R- ~" h( L McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 h8 L# ]8 i6 g7 w McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);# u, |, i# V/ e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);5 t& m+ o0 @* c* H. A2 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
( `4 O+ g9 M: p) k3 ^/ R McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);* T& |) ?- @. E2 ^% ~/ H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
& T5 h! z* A2 N# g a
' A0 m; g, {* K$ ]1 E0 c/ z3 \ McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
1 M# [( q# y2 Y% q; z5 o* ~+ {8 r- z" D3 K: q0 F
/*
8 e5 s2 L" n' |$ u/ y Z8 E, [5 r ** Configure the McASP pins
6 t4 q# T, \, k ** Input - Frame Sync, Clock and Serializer Rx9 _) m5 j; t' }9 M( m. r
** Output - Serializer Tx is connected to the input of the codec
4 x h f+ Z+ g9 v1 Q6 J */
& I' S# P; y& \% y0 Z# M McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! w$ O! o! o. I5 z) h$ G+ {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,) e: c& d S: S. X; L: x& A9 s
MCASP_PIN_AXR(MCASP_XSER_TX)
$ ^, ?$ g, V3 Q | MCASP_PIN_AMUTE) `1 H |& _. P. w
);
9 j0 R, B& {# G& c# x2 L McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,8 m' q( I- d8 P2 j ^
MCASP_PIN_AFSX2 W0 V! @6 f% I4 G0 x3 k* D
| MCASP_PIN_AFSR( m% G! o. \- v. c- H& o, O( _, ~+ M
| MCASP_PIN_AHCLKX Y4 g$ C2 y6 s2 P
| MCASP_PIN_AHCLKR
. A. ]+ o9 N" r5 x) s | MCASP_PIN_ACLKX
& C" c0 T2 j: `6 d | MCASP_PIN_ACLKR$ n& { k- T& e* D2 a" N/ v$ T
| MCASP_PIN_AXR(MCASP_XSER_RX)
7 }& q1 _" i1 B4 {& L2 W8 I* d | MCASP_PIN_AXR(1u<<(13u))
2 u8 N: r h. m! B3 O | MCASP_PIN_AXR(1u<<(14u))1 o/ Q0 j& T% C! u
| MCASP_PIN_AXR(1u<<(8u))
5 q! T6 B; h" j' M | MCASP_PIN_AXR(1u<<(10u))
1 Q( t, v: Q- ~- h8 f) e6 x | MCASP_PIN_AXR(1u<<(11u))
$ E( _! @( j+ g; i );
+ {5 c7 P0 f- d$ b, f8 W$ [/ Z8 T2 A4 s! k, h! }6 Q
/* Enable error interrupts for McASP */
* @0 w& j4 N& r/ h; d" D McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,+ G$ i. g Y# r8 y/ c
MCASP_TX_DATAREADY. Z; P6 A# Y) c! x* i5 ^# D2 f
| MCASP_TX_CLKFAIL 6 ~) w. f( O6 o8 V
| MCASP_TX_SYNCERROR
8 ?+ y; J" w ]2 `3 x | MCASP_TX_UNDERRUN); d, y7 s3 S! L w/ }2 s7 K
9 s4 T: f6 Y% g; P
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ j3 m, T& E) q+ t% ?3 _ MCASP_RX_DATAREADY9 W! `1 o6 @/ h: g/ ?0 O
| MCASP_RX_CLKFAIL" p8 P5 M5 D6 C" q, n3 m
| MCASP_RX_SYNCERROR 9 x/ ]( I- I9 \* K* Y# S
| MCASP_RX_OVERRUN);, v Y' J$ v) W
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR6 t6 Q- C C) k2 a* B; V' x
9 Z4 w# {, y) @, D, T. `0 R* O3 \}; g5 g/ [0 T* Y
0 @ Y Y; }, G0 l2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句$ h. P6 D/ K! S8 d* J- W3 v
static void I2SDataTxRxActivate(void)
. o" s# K0 Y- p2 m2 k* K; e- C{
5 l1 n. a V# U1 G& W /* Start the clocks */1 \3 N g$ v2 G1 P3 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 v- B% r- Z6 G; ~+ c7 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);' [) _% a, d$ [0 v
0 Y7 m2 G8 ?" k /* Enable EDMA for the transfer */
5 o5 ?, \6 H; w2 b) M8 t6 ~# Y// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# [& Y/ C. \6 M/ M
// EDMA3_TRIG_MODE_EVENT);
1 W: Q2 J, T3 }- k" L( F5 o: W1 T5 n// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,6 s+ m p$ }" k- k9 K* X
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);1 W* _$ I8 ]6 `- H
/* Activate the serializers */
, }1 Y! k! a1 v7 C# Q McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, I& G/ {" {' m0 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);0 a1 M9 ]! k+ I3 u$ G" n9 u
/* make sure that the XDATA bit is cleared to zero */" S! Q- _( E: T, V+ G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);3 ?8 L {3 o0 D. w% j
/* Activate the state machines */! j0 E. C I: d( m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- h$ Q2 q B# {) J! _) e McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# z5 l6 D$ e! ] L# @
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);# R. C4 }" Q# m. ]0 Q' n8 ]
}
9 J0 L% i( B1 t4 T% E' I5 r4 e! @1 N# s
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