|
|
我的McASP配置分别如下:0 t/ Y, A6 e- q- v. T# t) a! y
管脚的复用设置是:/ e. M# ^$ G G5 H
void McASPPinMuxSetup(void)
5 O$ k( P* z' B, L$ m{/ Z" a% u9 F+ ?
unsigned int savePinMux = 0;0 K# z O" L r# i( _" n: y$ v
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
* L- r O4 Z' Z3 s/ p ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \" m+ l( U8 ?1 O
SYSCFG_PINMUX0_PINMUX0_23_20 | \
$ p* D4 L! Q# I# z8 u0 a) e6 y SYSCFG_PINMUX0_PINMUX0_19_16 | \
1 k6 _ e/ c/ d! {; y3 w SYSCFG_PINMUX0_PINMUX0_15_12 | \
0 C2 ~) r& k- g: Y SYSCFG_PINMUX0_PINMUX0_11_8 | \
7 J) m6 L6 L$ c SYSCFG_PINMUX0_PINMUX0_7_4 | \+ b, u, O; i3 `3 i. Y
SYSCFG_PINMUX0_PINMUX0_3_0);
& C) L& w( K3 X# k HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
$ R& g+ F. l/ E [5 z. z" Q+ E( y (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \' A' z# `9 _8 [+ l. @2 \* b
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
% L0 ~4 D( B4 d7 L2 g, g9 }$ _ PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
. H5 o, y5 m" @7 O( a7 y PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);% }# c1 l" i: j: {. k% T
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \) ?9 ? j: k& k7 p9 j
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
0 ~ v- R; P2 w. m SYSCFG_PINMUX1_PINMUX1_15_12 | \6 v; b% m% k9 S6 v7 k
SYSCFG_PINMUX1_PINMUX1_11_8 | \
& Z: T# H3 N* t( E, s SYSCFG_PINMUX1_PINMUX1_7_4 | \
$ S3 b3 L7 q4 N( y( f SYSCFG_PINMUX1_PINMUX1_23_20 | \
0 H2 ]. S) v4 A& u1 j+ \9 W* O# d- m SYSCFG_PINMUX1_PINMUX1_27_24 | \
1 ~( ]8 I6 X1 {7 y% v5 X SYSCFG_PINMUX1_PINMUX1_31_283 V& `9 k) @/ K- G4 L
);5 h. Q& X; ~' N& D
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
! o( {& `8 i" O+ P1 c! j( Q# [% E (PINMUX1_MCASP0_AXR11_ENABLE | \' D+ O3 b' W( R: }' N. ?& d8 ]
PINMUX1_MCASP0_AXR12_ENABLE | \
+ {7 C0 F& W, E& ]. t' ]# p5 n4 r PINMUX1_MCASP0_AXR13_ENABLE | \8 I8 {, F; A3 a9 a9 ]
PINMUX1_MCASP0_AXR14_ENABLE | \. D& w0 y/ s4 U8 d w& h! d6 J
PINMUX1_MCASP0_AXR8_ENABLE | \% D9 n! `1 O! b4 l) p
PINMUX1_MCASP0_AXR9_ENABLE | \
$ O. v+ q+ Z6 ?. I$ [ PINMUX1_MCASP0_AXR10_ENABLE | \8 D4 |( V0 I; U4 f# u
savePinMux);" V. ]( N* X% x) j5 t% M) Z- T' R
}7 D1 q6 m: d! L1 {; m& T7 o
& p" ]5 h# b# y0 ~6 I' `
1.McASPI2SConfigure(); McASP的配置程序如下:
, S+ U7 D9 {1 p1 jstatic void McASPI2SConfigure(void)- U: e$ X. a9 y% r" \
{( w% {& K, ?" P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ Y9 H! P S1 b: M S+ r7 O McASPTxReset(SOC_MCASP_0_CTRL_REGS);5 T$ F" A( F9 P4 F% p/ H
0 k8 x! q( m3 i8 W. Y /* Enable the FIFOs for DMA transfer */
" `5 ?0 R8 l/ o8 }// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
' G/ q* {! d t" N4 X% L// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); e. ]6 k, I# O4 Q+ W- u# f( V
8 l6 ?' q. }9 Q3 f& a& @9 W2 W /* Set I2S format in the transmitter/receiver format units */# w. V! ^& f: w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 Q1 [' V) o, e* x
MCASP_RX_MODE_NON_DMA);: ]: \$ Z5 H: z, d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) ^% U9 P# I' B9 P6 K MCASP_TX_MODE_NON_DMA);6 R) P0 @: P" h
9 C' `3 R% Z: v6 h& h8 O. ^
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */! _% n. u7 Q& B/ e8 X; |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 K0 q4 v+ A% o5 I: Y0 q# u& B, T# Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); _- Q2 J# @$ z x( o1 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% N* ]$ e W$ j$ ~% p) n* _ MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);" @7 i! C( V' U$ e5 h
& z) F4 }) H6 p* C1 h7 i
/* configure the clock for receiver */
3 b/ _' I/ v Y- W, W5 x; k( d/ c: e// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);& `4 D5 x2 l; W W q$ c% c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ S, ?6 |9 R/ k' F. v* n McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);" d0 G* m3 L3 ?( \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 _9 i; x9 |3 x: l) _ d5 R+ C, X4 @ 0x00, 0xFF);
" a2 ~4 ~5 }" Q8 b" I- k4 p
. b% E0 W6 X8 b. g) a; P& J2 A /* configure the clock for transmitter */& y0 x( x( @3 Y: g4 f
// HWREG(0x01D000A0) = (0x00001F00);1 ?! C! w. v1 Q
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);. [" X& w) u' Y6 \6 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
2 b' n9 M p/ x5 L+ j( m- [# X8 d McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);( d+ T1 e% k! f U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
}2 P; ^' @/ }+ K d9 J& w 0x00, 0xFF);
2 d+ O+ z! J: X l3 v
0 i( T/ Q' m: N& b /* Enable synchronization of RX and TX sections */
/ v; ?( f( I" q( I0 c: E& Q& _ McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
7 s. c. c7 `# ?( q1 `+ P$ w4 K8 f
( K6 l, T9 ~. ? /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 N! A) o( W! L0 y' X: X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 ?( j9 w( A, G# \ M! j McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 m1 [8 E3 u) t0 A/ m; Z9 O5 l2 b2 o# l
6 g0 U Q( t# b- m7 J
/*3 J r8 n9 N; |" n! o% W, P
** Set the serializers, Currently only one serializer is set as
! x0 e) t/ ^) _4 s( @1 C, l2 w' D ** transmitter and one serializer as receiver.. C- e6 E* ^( f! H( U( e1 s
*/
: {, ^' U1 Z* x McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 O' K( I* s2 D5 X% w7 S6 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
2 `& j, m2 q$ u# n+ L' @ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);' [ }( N! O) F. Y8 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
" h5 H3 o* ~/ r. n- B( z McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);1 B2 R$ ^+ p- V- E% z) W+ {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);# h: w" E2 x" z* d: [
* F: G2 q8 V7 W" p: V/ Q6 `- r6 f9 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
( C( ^* b: J0 q
+ \1 G. G5 {6 O4 r& z k /*" R8 J, g+ \; \ ^( q4 v
** Configure the McASP pins 0 c$ k2 L. [* J' B0 a6 W$ o
** Input - Frame Sync, Clock and Serializer Rx9 m2 X) H# S' E9 G5 p0 |6 L' I
** Output - Serializer Tx is connected to the input of the codec K" i( [7 `% M% L! @
*/
0 ?8 R: h0 @! W5 w) F/ [* H) b% q McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ n/ Y3 F4 [9 y$ r' I4 f0 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, v' T; Q+ S# w2 E8 Z
MCASP_PIN_AXR(MCASP_XSER_TX)
# y1 j" K3 q/ v% L | MCASP_PIN_AMUTE
* c7 f8 {7 a G );
7 N5 I/ d% t2 y( T6 ~8 N2 ~/ a McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,) l v6 l, @3 K; l5 q" F
MCASP_PIN_AFSX
1 N, ^8 p/ D# W: u' z- }; ? | MCASP_PIN_AFSR
$ ^4 q5 o2 H. n# | | MCASP_PIN_AHCLKX0 M$ c( A& P _: I/ E
| MCASP_PIN_AHCLKR: e" f% Z" \8 G
| MCASP_PIN_ACLKX
$ q4 j: j4 i% @' g# q+ y | MCASP_PIN_ACLKR$ j1 J: `* V& w1 t- P
| MCASP_PIN_AXR(MCASP_XSER_RX)6 M$ O$ \2 P$ j% _4 z8 Q. t
| MCASP_PIN_AXR(1u<<(13u))
# O6 y8 t- D: ^; z& ?. }' \ | MCASP_PIN_AXR(1u<<(14u))+ J8 Z' V0 D& O& P6 u
| MCASP_PIN_AXR(1u<<(8u))
: Q$ O0 N2 o0 C; }7 D | MCASP_PIN_AXR(1u<<(10u))4 Q3 e' j: j4 K! K) j+ e
| MCASP_PIN_AXR(1u<<(11u))8 o0 Q3 [2 K) a" i/ {* X. ?
);
1 ?% e/ |! L. p; B- I. u) G
8 Z* [8 ~5 [) K; }! u4 l: m1 c: f4 ` /* Enable error interrupts for McASP */0 A+ ]5 Y% d& o8 ^7 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
- v9 K# J9 f6 C# w MCASP_TX_DATAREADY) d/ l+ W8 y" @- J& A% H) q4 S
| MCASP_TX_CLKFAIL ) @- R3 S! l9 m2 ]& T
| MCASP_TX_SYNCERROR
8 V _/ J/ B; B5 [ | MCASP_TX_UNDERRUN);
5 n3 u' w& W6 j9 L$ K! U! {5 y3 j( B. f7 M2 }. y$ J
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,* m9 k. Q/ h3 t3 r( z. Q) |6 i! c
MCASP_RX_DATAREADY* t* ~: K. x. _" E+ e, l6 V7 M9 h& A/ g
| MCASP_RX_CLKFAIL
' y- ^0 b% B" u! P0 v* m8 ^ Q: _ | MCASP_RX_SYNCERROR 0 u: {* B, O5 H% x! R1 d8 I
| MCASP_RX_OVERRUN);
7 z0 t ?( @ q* e0 u//MCASP_RX_DMAERROR MCASP_TX_DMAERROR1 L! R; a( z! Z. I' o/ C( w
+ T7 p0 y. c6 X; M- d3 h5 H
}
/ I& M, T5 D) E% U, L5 X
: n# w! F2 \; d, F, j9 [7 S2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句4 P, C1 x4 s& z" O8 F
static void I2SDataTxRxActivate(void)
6 \5 y6 [" R& I7 v( ~& \{
3 T# m, o- J& G% p, ~% c /* Start the clocks */
: j/ K' G8 c' g0 X9 m. W McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: V' R) Y9 H/ }) a McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);' c% e1 X! f5 _& u
, P. D% O) O% @. t, l- J( { /* Enable EDMA for the transfer */: _" J- G6 o2 O
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 j' W- u8 g( ?/ z( t+ z// EDMA3_TRIG_MODE_EVENT);/ i" k0 V _7 Z+ G
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,: S9 r5 `; f8 ]2 r
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
" I( S3 N3 V) p" Z3 U" n% P M( b2 f /* Activate the serializers */5 _9 j( M1 r- X- J$ N- J$ T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 N; b6 ^1 r4 P) a# p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);0 \4 }; {0 Q) a t: z( H" Z
/* make sure that the XDATA bit is cleared to zero */7 |" | ^/ F3 ^- B3 J8 i9 |, U* i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
+ Y# h( R0 E) Y0 T1 w /* Activate the state machines */- f, v4 |! _0 O7 s% x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, f4 l l2 w7 L6 l1 g/ \# s McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 R! w2 x" Q0 S- ^' q1 s McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
! m: t% h3 a Q% f! K}0 A& T8 X" K2 a. i
' V& I& a$ l- N- K, R3 v4 @6 t |
|