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我的McASP配置分别如下:
, O1 M9 f9 ~6 B& k管脚的复用设置是:
, ]; n5 k: B) }void McASPPinMuxSetup(void) `* q$ R. o% h- ?( x; H9 M0 P6 N
{2 \ Q% T4 ?! W, _/ d z
unsigned int savePinMux = 0;* F; K% a: z5 u* R1 v8 c" i. \
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \3 v8 S; ^0 k! r, H- _, |$ Q# S* ]
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \ x: s& n8 ^9 j, `) R
SYSCFG_PINMUX0_PINMUX0_23_20 | \1 t) |9 d: u, I6 Q3 H& }
SYSCFG_PINMUX0_PINMUX0_19_16 | \2 X/ P4 `5 b; Y1 o9 K: G9 o
SYSCFG_PINMUX0_PINMUX0_15_12 | \6 @! m; C* T2 i, [* a: {; `9 l7 \
SYSCFG_PINMUX0_PINMUX0_11_8 | \: q5 o, U6 P& W) `/ j2 p
SYSCFG_PINMUX0_PINMUX0_7_4 | \ A h: j4 |; f- ], A
SYSCFG_PINMUX0_PINMUX0_3_0);0 k+ r, B' W; p
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \* U# v7 ?5 ?( I9 L$ ^
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
, s0 C" G0 ]4 M& |! b$ f PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \( z2 U9 ]' O& w1 _( x
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
+ p7 r' @4 A" K% e+ Q: ?9 J) I, B2 e PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
: {& z; i+ F' m) Y savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
5 ~6 G) N4 ^# i0 a6 O8 J ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
# u0 j* S$ \' E- e7 P& e SYSCFG_PINMUX1_PINMUX1_15_12 | \
$ Z( a/ K" q$ r7 M4 n) }' l SYSCFG_PINMUX1_PINMUX1_11_8 | \
6 l: o N1 Z- v SYSCFG_PINMUX1_PINMUX1_7_4 | \
% W1 z- v _4 g3 L2 f SYSCFG_PINMUX1_PINMUX1_23_20 | \
) y9 {, B; R2 o$ t3 I' Q SYSCFG_PINMUX1_PINMUX1_27_24 | \+ T+ U7 m! b$ \, G. j; Z) c
SYSCFG_PINMUX1_PINMUX1_31_28
( z- t0 @$ [7 p6 V( S );9 @. K5 i' }- [7 r( Z8 l6 m" C) C
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \6 H$ q. s" g z( F( d+ \. |
(PINMUX1_MCASP0_AXR11_ENABLE | \
" p$ m# c- B1 Y, L- K$ p0 s PINMUX1_MCASP0_AXR12_ENABLE | \
6 y0 a' _( x* a' X PINMUX1_MCASP0_AXR13_ENABLE | \
- @ `' h5 R6 U; i8 p* P. ` PINMUX1_MCASP0_AXR14_ENABLE | \3 y% X! A n4 G: f4 i
PINMUX1_MCASP0_AXR8_ENABLE | \4 L2 ^& f7 E+ ?; R
PINMUX1_MCASP0_AXR9_ENABLE | \
" f& r7 G/ ] S: H- a7 C6 y PINMUX1_MCASP0_AXR10_ENABLE | \
. w/ j o/ l8 L) ] savePinMux);/ f6 Q6 _ V2 C8 ~
}0 A/ C2 I2 b: L0 y* q
2 g" N) b) p: R* O2 a* ~$ a2 H- z( K1.McASPI2SConfigure(); McASP的配置程序如下:. w f6 v* `9 x
static void McASPI2SConfigure(void)
, Z! U, ?0 z4 ^' a7 Z# H- Y5 Y{
7 P; q K z% v. \ McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( p# v9 w) f5 j& \( L McASPTxReset(SOC_MCASP_0_CTRL_REGS);& g5 N( P0 ?+ L
6 ~& x, B9 z) Q
/* Enable the FIFOs for DMA transfer */
7 K$ x/ D( V f0 P' w% P0 ?// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);- H8 U7 ?7 @* Z7 G W
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! ~: B$ B3 ?5 W. D/ t- O! L, L
3 S0 P( p6 S! ?' T( r3 h* J
/* Set I2S format in the transmitter/receiver format units */
1 ?& I- T; b& ]2 w7 o$ W# E9 y* N* w% C McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; h/ r& N4 T" C, D& G MCASP_RX_MODE_NON_DMA);
: F* b, N5 @) j' K# T9 t0 F8 T McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( n$ a( f. {6 Y# j: ]& R- ^
MCASP_TX_MODE_NON_DMA);
: A& w$ f4 K! z" ]
e2 ^ Y% s2 i' [ /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 q1 w$ o" ]5 w$ ~3 I: D McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ c2 {6 x1 b; j( \8 h/ f" a MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ `" \! q- g1 s2 K& T! W( Z McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - j; m& z* i0 _/ \3 D" Y5 A, H* h
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
7 D% O/ Y: E: f3 f( f$ w$ d/ `$ g2 s' ?- R
/* configure the clock for receiver */
) I4 g' k) P/ t// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);( o" F+ U4 ^7 I9 \1 l9 V3 I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 s7 {( m/ h" D' g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);& o6 n1 e* t- E2 Y- ?* A0 v# B/ `9 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 ~/ `4 o) F( u$ \* Z; x0 [2 k3 N* D 0x00, 0xFF);$ A) t: `. a* r8 B" c E' }: d
/ w. b! l7 n' _7 C/ b) m
/* configure the clock for transmitter *// o+ s- \' @* Z# N' v4 |9 d
// HWREG(0x01D000A0) = (0x00001F00);9 l4 Y+ p/ Q) X. ^+ H
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);: O: h3 I2 l! w* C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
4 j7 _7 s& `3 ~+ r3 Q: ~' ] McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);. x6 ?, F6 A9 o" a% k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 {: {' I% y& k W
0x00, 0xFF);
D. a; Y9 @6 s* d 5 y: X: g; e, f( S$ S" I. ~5 W
/* Enable synchronization of RX and TX sections */ ( r# g$ k f Y& U" w* u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
+ K0 n! Q/ x; w9 c! Y: C
( E% v. Y. E. _# B /* Enable the transmitter/receiver slots. I2S uses 2 slots */- _; D( v4 L- N* s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; S3 f2 Y6 ]3 U5 [. l$ D McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; T$ ~9 ~5 a5 n5 p' U1 D5 j" m
; N' |' A& X4 M9 | /*
5 U) g7 t6 s7 f: E+ x ** Set the serializers, Currently only one serializer is set as# k" B' d0 ]: o0 Y4 M4 j2 H; G
** transmitter and one serializer as receiver.$ v/ S$ _9 }- R7 D% q A. f" q
*/ l. g8 E* ~5 c6 j% w* J) Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ d9 X, p3 R* m/ |% s" E$ H6 S d McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
$ i, _' \$ v/ ?( v McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
0 o, b5 ~9 H' C2 g; t McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
b/ J; X+ q l6 e& h; w McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
( b1 l/ f' U O) {$ o8 P McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u); R7 ]* p. \% j
3 q0 l- c, F! E0 d McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
5 ^1 E: a1 {5 ]4 L8 |$ d$ r3 |: n5 X
/*3 E" L- x6 z$ @; Q
** Configure the McASP pins # K( }' t7 n# a8 u& s& z# \
** Input - Frame Sync, Clock and Serializer Rx
7 i. p9 k4 r& {7 c$ N- t0 i- o8 P ** Output - Serializer Tx is connected to the input of the codec
* y1 F2 @- k9 D: [ */
2 z) s9 w) Y, o9 x McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; x) g$ F( c- y/ X4 c) i# Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,' v# O( h) o, Y8 H1 x% ?/ O
MCASP_PIN_AXR(MCASP_XSER_TX)0 E7 F2 J, H& w5 {
| MCASP_PIN_AMUTE- J$ {( M& B5 i- \9 M
);- D1 R. k# w9 z2 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
! }* K' S, g# V, p3 @5 b( E MCASP_PIN_AFSX
2 ~& u+ d: G2 ~. b- N | MCASP_PIN_AFSR! V& J' Y( Z8 _: o
| MCASP_PIN_AHCLKX
$ x" E6 B( G% s) q8 k' r | MCASP_PIN_AHCLKR' ]' m5 `% N1 b Q4 Z
| MCASP_PIN_ACLKX& i2 P: `( T* S" h
| MCASP_PIN_ACLKR
. L- n1 e9 w! }$ \0 B" b, h% D | MCASP_PIN_AXR(MCASP_XSER_RX)( X) i2 D( l4 v0 i/ ]" g& F
| MCASP_PIN_AXR(1u<<(13u))
, }* P& \; l& R0 d7 q- o( H | MCASP_PIN_AXR(1u<<(14u))
4 W' q6 S n7 R/ z) j | MCASP_PIN_AXR(1u<<(8u))
[; j4 ? Q$ V M- q' ] | MCASP_PIN_AXR(1u<<(10u))2 w K. G# B8 C
| MCASP_PIN_AXR(1u<<(11u))
; q$ ]5 i: Q+ ?' ?; \' M );
# F% @' C! O: R6 B6 y( N% D, g" y7 [9 c4 i8 s
/* Enable error interrupts for McASP */. m; B/ ?% Z. ?! @) v6 N2 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
5 |# F- J1 d3 Q: q MCASP_TX_DATAREADY
% W X) S5 Y/ s8 m! R; { | MCASP_TX_CLKFAIL 6 `1 L8 U2 ?* J) [
| MCASP_TX_SYNCERROR# {9 v( o8 T/ T+ z( P
| MCASP_TX_UNDERRUN);
$ o0 p; H' G) d3 s
9 P9 {+ P" \! n: ? McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,' L) w6 L; d8 E( o5 J& K
MCASP_RX_DATAREADY. j, A5 R6 G+ z z" J
| MCASP_RX_CLKFAIL+ X; W* J" c3 J: p8 A
| MCASP_RX_SYNCERROR
8 [5 f" f2 ^9 q {3 w# m3 Z+ q | MCASP_RX_OVERRUN);% d: Y9 F& R1 O& N
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
- z% O) Z5 G/ W+ V6 x, k+ l! b* b, a4 X: r
}
9 r2 [+ \6 [% z- |
9 F- {) S( R- Q T& o% F- D7 _2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句7 t& g2 A1 z4 U" C6 j1 Y0 B4 j
static void I2SDataTxRxActivate(void)
3 f# |2 _5 ~4 M% Q3 d{
3 k4 r0 e6 h4 O% G* V" L7 } /* Start the clocks */; i! K& c8 G5 m- h# g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 I$ K' ] T8 E6 W+ W4 P' y; {/ o5 h McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
2 e. w/ @3 x1 w9 g! L( y
6 \- _( I( y( k% | /* Enable EDMA for the transfer */
7 {- h* y% F9 b( K$ T, |2 W// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: f0 b3 x$ S) }# ]% q8 r
// EDMA3_TRIG_MODE_EVENT);
4 D% s+ w3 `4 u6 R$ i4 J- P- y// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,$ ^$ u0 h* }' Z4 Y! Y$ ~7 s
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
! j+ x' L7 E, v) v; b& H /* Activate the serializers */3 A, ^# U v0 |# t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. [5 r S. |( k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 J# Y: N1 I; q A, T /* make sure that the XDATA bit is cleared to zero */
6 f8 G5 I, U. V2 x while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
/ _! b* {- I$ T& \6 ], ~5 o /* Activate the state machines */
% X3 d( Y! P, ^6 o- D) M L McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 y9 ?7 I6 I1 `5 v1 v" ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 ?0 x; l6 D/ T1 O; o% n
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
7 N, k- S6 E5 o1 k; T1 n9 u& P' F}$ X, J+ U! v% H5 q. e7 F
1 }4 U: M t* m- e, a' u
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