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我的McASP配置分别如下:
- [/ L8 o& j4 D管脚的复用设置是:
0 B9 ]- U: R3 U+ N& W5 ?! g/ ]void McASPPinMuxSetup(void)" t5 H7 Q3 t6 G2 g
{
. g# o; ~8 a& R2 x) R3 ^# @& M unsigned int savePinMux = 0;! \4 x* x( ]5 [( x' @" a7 O! m
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
: w+ U7 c+ M: M ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \ N' b& T% i7 W& ~& `
SYSCFG_PINMUX0_PINMUX0_23_20 | \& P6 U) }; y+ j2 H4 g
SYSCFG_PINMUX0_PINMUX0_19_16 | \
. D; M9 p% w5 B- h, v/ R* G- k SYSCFG_PINMUX0_PINMUX0_15_12 | \" V4 W7 ?7 A/ N9 L1 C% y `. W
SYSCFG_PINMUX0_PINMUX0_11_8 | \
' @. R$ u% q+ d4 S+ m+ F SYSCFG_PINMUX0_PINMUX0_7_4 | \
2 P v$ ?: C! _% a7 N SYSCFG_PINMUX0_PINMUX0_3_0); r9 K" ]: d& S5 n* u2 j
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \/ q( R9 B" a+ s9 A3 `: z
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
1 F5 W& @4 U/ a& T; h, U6 w PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
5 f1 F* I! u3 @ PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \$ S& b2 v& V1 s# F: K
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
6 S( N5 i1 [! ~7 J1 B savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \1 Y w6 O4 y$ l4 F' B7 ^
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \+ E9 |2 f$ S5 u C3 K# P; C
SYSCFG_PINMUX1_PINMUX1_15_12 | \3 \, ]2 E1 ~3 ]3 n" W
SYSCFG_PINMUX1_PINMUX1_11_8 | \9 E5 K' I2 X0 d$ J$ m1 ~
SYSCFG_PINMUX1_PINMUX1_7_4 | \
3 q& }! Q+ Q, x' b1 }$ O) |; O9 v SYSCFG_PINMUX1_PINMUX1_23_20 | \
- U: f5 z' A Q; l& U T SYSCFG_PINMUX1_PINMUX1_27_24 | \5 _. t. o! @( |5 Y0 {9 i
SYSCFG_PINMUX1_PINMUX1_31_28$ B3 a& Y. O! u2 M1 B" R
);# t3 ~: z! d4 U1 v# |0 V
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
" {* n) J# ]( h (PINMUX1_MCASP0_AXR11_ENABLE | \) v( a9 S' h; P
PINMUX1_MCASP0_AXR12_ENABLE | \+ ?' i& h, D5 M
PINMUX1_MCASP0_AXR13_ENABLE | \2 H' g; r4 b8 m# @
PINMUX1_MCASP0_AXR14_ENABLE | \
/ } e! }2 u; g1 U! s5 S PINMUX1_MCASP0_AXR8_ENABLE | \
0 K4 i8 a6 R7 \& s$ J7 A" U/ U a5 R! j PINMUX1_MCASP0_AXR9_ENABLE | \1 B& F* ]% k" d8 v* ~+ | d
PINMUX1_MCASP0_AXR10_ENABLE | \% g/ M, `# D# ?; B% n: N
savePinMux);
5 i, c3 @2 U+ e% W2 M1 d7 g7 S}
1 a: G5 c! _. S# _+ ?% s) B8 C" X; p2 m: D
1.McASPI2SConfigure(); McASP的配置程序如下:. |' O! x, v" j5 X! [ f
static void McASPI2SConfigure(void): L$ u! ]0 G$ S i* @# F
{
/ N& V: _2 W/ i! A9 e McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 h' L. E! F- p% y McASPTxReset(SOC_MCASP_0_CTRL_REGS);
: {" W# R, E ]8 t: @. \
{8 Y' N1 E1 N5 S /* Enable the FIFOs for DMA transfer */
# n* {; d# v% j& W1 v, P2 w// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);; V8 k+ E5 @& V% X' z( T* g
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; M* i' @. |! ]) z
2 v! |7 a7 b* J/ f% r5 Z' o1 S$ p /* Set I2S format in the transmitter/receiver format units */
; e1 r" l8 K: Y2 V% N3 D! r McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 |& q+ q" ^4 ?! I- U! r) @8 C MCASP_RX_MODE_NON_DMA);
+ j# X+ w- n& k" I4 Z0 h McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' B7 t @+ O- c% Z MCASP_TX_MODE_NON_DMA);
" Y' O9 w' r1 z( K% U! `8 P* t* M+ ~9 b- L4 h6 M
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */: I7 C, Q, g4 E( x' j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' h. _) g) R# c' C. @0 O. M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ m6 b3 A" `, n( X McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 H& ~5 G8 O; u9 _/ _/ Z! t* L
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
. @. Y' Z2 Y* H
7 ^/ }3 I( ]1 _9 i2 X /* configure the clock for receiver */. R' m) ?9 l1 e0 t/ P$ I& e
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);$ }/ u7 c7 [; v( [ }2 |9 |/ f* ?) Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 M) B/ G0 A( h0 c3 F6 K) N McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); _4 g0 _/ L' q1 F. w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) h$ r/ w. L6 q; P! `' T4 p 0x00, 0xFF);% D( H8 z, M, C6 c y( n3 J7 X2 P
( x) j" x$ }' a: t$ p T
/* configure the clock for transmitter */: _. _( m6 H& @; k- H
// HWREG(0x01D000A0) = (0x00001F00);3 \ Y& n# j0 Q2 C" L9 O% e
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u); x* H' Z8 ~/ [8 M0 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
* f D, l; M4 x) H% p McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);) Y' {' P( y% p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 s, t5 n d1 |
0x00, 0xFF);& H! G" O( M1 v1 j" R
+ Z r1 J5 Q) y4 ?! d2 @+ R" m# a( {
/* Enable synchronization of RX and TX sections */
+ l7 X$ F; J" v _6 h6 A McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);# `$ E' ~6 z* m E
, T7 i4 u2 n8 k5 u6 h /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, a9 K( T& S' K& X& u$ T McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! _% |/ ^8 E( `4 f0 K McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 l9 l+ i( N/ K+ c* u* p9 r. e
1 E9 |$ i7 Y* l& Q4 Z4 A /*
2 o8 {, o* w5 I& O9 C% O$ d ** Set the serializers, Currently only one serializer is set as. W6 ^+ @3 [) Q. X' @9 {9 D$ o
** transmitter and one serializer as receiver.! H3 M, ?# N0 p
*/
9 E+ I; F, {& [( H McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 C( N6 ]5 ]" s- h' S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);. B- h; o/ R% }# n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
; }+ }' \: y/ b6 L+ M! `% _ } McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);! e4 L1 W5 C1 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);/ f$ b2 D9 v" J6 j6 c9 |
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);: Q& o! b6 Q+ R% u8 p
/ E% P* u% _- j* v# U7 H McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);0 d( {" v$ N- Y$ r+ O3 y, a
* `- v( O) Q, q* ]8 \$ P1 S) | /*/ v* n7 @5 J) a; `
** Configure the McASP pins & C" C' }* m) d( z! j. W; O, @
** Input - Frame Sync, Clock and Serializer Rx: v4 M% b0 k D, _
** Output - Serializer Tx is connected to the input of the codec 1 M& C* U6 z3 @* y5 U- i
*/+ L+ h: O; z' V& y2 O6 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
F% ]# P a' r9 z, T% H5 {6 n McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
. G+ n% {( ~) J" q MCASP_PIN_AXR(MCASP_XSER_TX)
; R; u; t6 P0 X+ }, X( p" Q- h | MCASP_PIN_AMUTE
, K) F% V8 b2 D6 I );
/ Q7 O1 f" b0 V4 G8 e6 s; D McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
. u |- X3 F7 C4 p MCASP_PIN_AFSX
% c2 `- p: i7 W: B | MCASP_PIN_AFSR
, }0 k& j0 ]; ~: p: b9 H, Q* ] | MCASP_PIN_AHCLKX
0 Q8 F) f+ U5 c6 H' K/ r9 C, Y- o | MCASP_PIN_AHCLKR4 D3 H1 b7 V" l! n
| MCASP_PIN_ACLKX( P5 T* i0 x, _7 x1 b
| MCASP_PIN_ACLKR
3 k1 z' j2 x) T7 R- i8 p | MCASP_PIN_AXR(MCASP_XSER_RX)* `( B8 f" x! D3 P! Q4 z' m# D- t
| MCASP_PIN_AXR(1u<<(13u))
) e1 X( t, [* [) M6 {6 @2 B5 L: y | MCASP_PIN_AXR(1u<<(14u))8 T: V; U* g* g3 |7 i5 y, z! o
| MCASP_PIN_AXR(1u<<(8u))6 u0 ~- {0 E( ^* f/ ^
| MCASP_PIN_AXR(1u<<(10u))
: ^6 S! y3 q% w$ k9 h* B$ I | MCASP_PIN_AXR(1u<<(11u))
' V5 _% e! [3 x );
; H1 X# \ N% Z; @
3 \" A5 a! w: J& _' ^ /* Enable error interrupts for McASP */
/ V o; _* `' V, ~5 H McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
a9 Q. S+ D2 r# W5 W7 A+ y MCASP_TX_DATAREADY% H/ T1 {# q0 @) m, B7 x% e! c* _
| MCASP_TX_CLKFAIL & A! T$ C& R2 \$ o% L
| MCASP_TX_SYNCERROR
/ D |( I; R: w- u1 E% n# ^. J4 ^ | MCASP_TX_UNDERRUN);
& F+ ^8 I5 Q& q! r7 `
4 D5 W( x4 R1 [ McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,, A) j8 [+ a. c; |9 X; a$ R+ h J
MCASP_RX_DATAREADY& ~* p+ K- e* e* J4 K$ x
| MCASP_RX_CLKFAIL
5 x; e# F9 B& [ K% b | MCASP_RX_SYNCERROR 7 z$ ? a* W( d! R9 [1 ^
| MCASP_RX_OVERRUN);& M; V1 i9 V3 n. z6 W$ E5 [
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR- V3 h& I: Q+ q! [2 E! o1 |
/ A, t# U% O0 }5 d% X& j6 T}7 |8 O$ z+ H" h- I( c( c
6 L1 o) y- E7 c- W; p9 f5 ]) R: I2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句3 X4 j4 d S' e/ Y% f
static void I2SDataTxRxActivate(void)
0 D, G/ z2 Y5 t! h9 {, u3 Q' |{+ }4 t' c3 U1 J+ P0 b9 |/ M
/* Start the clocks */
6 E( j5 S2 R! K McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) U" m# |! A7 e# _5 W1 D6 D8 Y/ U9 ^ McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);) E( f1 S+ E9 z. L
4 i% X- g, k# V1 D: K( {1 B8 a
/* Enable EDMA for the transfer */
' `( X# b% R$ H1 }9 g# h// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- b/ z: Y! S3 l8 n// EDMA3_TRIG_MODE_EVENT);4 l: I( o3 d* @, b! D- ~! w& D
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( t& ?/ O1 g- q/ m! l* i// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
/ c9 b0 g( {# Y: g5 m' H& |' r /* Activate the serializers */7 f% J9 _ |2 F2 D. e' U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ g: j$ c3 _$ d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ e" u4 d! f! z% p /* make sure that the XDATA bit is cleared to zero */
7 f& Y3 i9 |- u& H1 i while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
' O; y. x8 G4 }# q5 k$ g /* Activate the state machines */ G/ D0 ^ _2 P) S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ M2 P* B# T( ^# |1 n McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 X2 L) G/ k% ~' R
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
) B- X8 ]" _( W% S2 `" t% w: a6 V}! l/ H& Y4 v: Z% a. \
: w$ Z+ o3 p# M8 p: u9 O+ L( Q |
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