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我的McASP配置分别如下:/ d+ o; g5 j" {$ u0 E% I
管脚的复用设置是:
& k% t+ p9 K0 R; T1 q" U, tvoid McASPPinMuxSetup(void)% h4 B+ m& R2 C3 A2 I6 l
{* s# K3 Q) C C% X' l$ `
unsigned int savePinMux = 0;
$ D* s# S3 i2 j! N savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
3 @. h% [# X. `* g$ C( \ ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
' y$ d3 ^# H' |6 r- f1 h SYSCFG_PINMUX0_PINMUX0_23_20 | \& ~( ^% U8 N$ y# {
SYSCFG_PINMUX0_PINMUX0_19_16 | \; P! U/ _( E0 g7 {$ F
SYSCFG_PINMUX0_PINMUX0_15_12 | \% b' g- D9 i! ~+ Q6 S) d- L
SYSCFG_PINMUX0_PINMUX0_11_8 | \2 F7 A2 i1 y& F; ~' f! @5 A7 v
SYSCFG_PINMUX0_PINMUX0_7_4 | \% n4 Z& `* l1 L; {7 U
SYSCFG_PINMUX0_PINMUX0_3_0);5 f% I: v- Q( Y: ]1 a
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
$ F* H- d; ]) f# } {0 N1 ? (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
1 d. |% D' V4 _3 @( c! V) r$ ~ PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \* ]) l' }/ |' p8 g% S
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \/ S K; Z8 q, X
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
1 B" ^3 H, M( @' y6 B3 P4 v savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
1 h# F% Y3 B! d4 @ ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
/ N7 E! D0 r: A6 D$ Z& l2 { SYSCFG_PINMUX1_PINMUX1_15_12 | \/ d k" J( _) }, V/ V
SYSCFG_PINMUX1_PINMUX1_11_8 | \' k3 @2 Y# u* V; i
SYSCFG_PINMUX1_PINMUX1_7_4 | \
+ R1 g# p: c1 {5 [) [- y v) W0 l SYSCFG_PINMUX1_PINMUX1_23_20 | \
+ |& h+ |3 `: |) o SYSCFG_PINMUX1_PINMUX1_27_24 | \9 s. s) ?0 e$ Y M( o" v# U6 q/ T
SYSCFG_PINMUX1_PINMUX1_31_28- n# s- @( R6 C9 G+ J1 L
);
' f- `9 y0 S4 o& V6 a- C HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \# c% k v; M( H& _% e: Y5 F: k
(PINMUX1_MCASP0_AXR11_ENABLE | \
6 j+ x$ g6 _( _# v! M PINMUX1_MCASP0_AXR12_ENABLE | \5 ^* I. y. |# t+ {2 N# g
PINMUX1_MCASP0_AXR13_ENABLE | \
5 D2 L$ F8 d7 _; i- ] PINMUX1_MCASP0_AXR14_ENABLE | \, w- T& e6 s! U- D
PINMUX1_MCASP0_AXR8_ENABLE | \3 L9 C, A V/ r5 v
PINMUX1_MCASP0_AXR9_ENABLE | \
1 }0 c0 a. q* y) I PINMUX1_MCASP0_AXR10_ENABLE | \2 Q$ x: N3 n* e
savePinMux);
7 n2 C( [2 H6 ]+ j( M/ g}
P1 T9 ^& u8 w1 F% E
$ }9 N4 n5 }" i0 Z4 K1.McASPI2SConfigure(); McASP的配置程序如下:
" Q( A2 I) [3 H3 R" y# Mstatic void McASPI2SConfigure(void)$ e6 J( M2 a. v; _1 ~1 k$ @
{
) ?) x# T4 s2 r- R McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 ?* }4 y1 S l% ?& b
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
3 u, `) w0 V0 q( t3 N7 s4 B
2 J% X. c9 ?8 z; G" a% G r) ] /* Enable the FIFOs for DMA transfer */2 j8 j4 }* j+ s. s
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
8 J2 y. V& ` C' i% W// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 h. I, j; t% Q/ o
K" Y" U, N: R* v9 l) T
/* Set I2S format in the transmitter/receiver format units */
# m* H; o9 y& z% U McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 b/ ]+ }+ m* a, L2 ^ MCASP_RX_MODE_NON_DMA);$ ?1 N9 ?: e0 T/ V" t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Z3 Z6 g- y$ C2 A
MCASP_TX_MODE_NON_DMA);
- x( Z% M3 L- u( T+ c
9 G, @4 E9 Y! I9 Z+ L+ b6 `) W7 p# E& N /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ e/ g5 ~/ I+ P( O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
n) ?/ i1 @9 g MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 E& I1 \6 X* c2 \& G8 x9 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 N2 [! L4 I9 _( l
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
* B/ V1 U0 x3 m, K+ Y
. H: `( o# L4 t6 C% \ /* configure the clock for receiver */
9 b0 ]( m% Z" E: X7 r) C8 Z// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
% @2 F* \5 `5 _+ h6 d McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 P# ?: J# |4 l$ p McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);8 J |. N6 j C6 N' N* _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 k0 X7 p+ B% [6 e 0x00, 0xFF);+ p+ E2 w0 _) ]% [; \6 T6 @& Z
; ]; m S% S0 S2 ^, |4 D" N9 _
/* configure the clock for transmitter */
: d: Y x4 y% j' y% P, U// HWREG(0x01D000A0) = (0x00001F00);7 T, K R4 }8 d5 u& }
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
1 }6 Z! e% q8 E+ r+ `5 b McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
) @' ]7 \1 d2 k, D2 D) P: G; T n6 g( f McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 C& L- j$ w0 h3 _" ?" X McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 t9 Y, p/ w0 w" T" @7 `) ~* f4 v0 V 0x00, 0xFF);
6 P t' X2 {1 t- y0 D- y ' \( a6 d! ]: i' V9 P0 @& |! k8 \: b
/* Enable synchronization of RX and TX sections */ ) H! j$ Z; x; g1 |& H/ R8 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
, T8 R. C$ G3 r# R
& [! O4 p5 h/ i& J* i, q3 R /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) E8 g5 u3 p ^" C: v; u McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 C/ ^9 A" W4 A- x% }# A McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 \) ]# u. m, U
- ~8 K; k6 v6 c3 \4 h
/*
7 o; i8 n1 D2 X$ I: } ** Set the serializers, Currently only one serializer is set as
5 P+ m, R& q) ~ ** transmitter and one serializer as receiver.
- w6 S% f: A$ |3 I1 W+ @. Y */
) o6 `1 R0 v2 A2 u, B$ t0 J McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ ?5 W1 D* h- J' F" ^7 q McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);7 F2 R+ d+ Q3 ^4 x/ e+ ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
2 o# |+ W3 d4 X D m+ V McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
1 X' g& T5 ?7 U% X7 H9 ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);, }6 p9 t- n8 g7 s) N3 U; s- g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
2 r: N. I) \$ g9 J; K% K4 Q+ M7 A5 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); v3 S; m' _* c% u5 P7 ~8 _
* i2 X- w8 X9 a/ d- X3 f4 z0 `
/*2 m( Z2 F' N$ h9 P8 g3 S5 x& p4 J
** Configure the McASP pins
$ c) }# |% D4 X ** Input - Frame Sync, Clock and Serializer Rx
: G6 A/ f: |7 r- ?* [ ** Output - Serializer Tx is connected to the input of the codec
+ o1 b6 s, n( Z, p8 B1 S */$ m! j; L: B4 [, X4 ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 P7 c* o, I+ P0 W. s6 x: B$ _6 H7 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,# ~" b/ ]$ [4 x
MCASP_PIN_AXR(MCASP_XSER_TX). O% P; C. D$ @. D' P" m
| MCASP_PIN_AMUTE i/ Q+ u' @1 G z' C: E+ d
);
: T% ?' E" w3 ~/ ~- j9 G, x McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,. _# ~8 s, V/ g
MCASP_PIN_AFSX
, q4 V; r/ i) `0 S | MCASP_PIN_AFSR; A* z/ m8 r: i9 M
| MCASP_PIN_AHCLKX
5 b* S6 K" S! A L* \- u- m6 m8 Z | MCASP_PIN_AHCLKR5 ^. ]3 W7 W5 g# S* f/ Y9 L
| MCASP_PIN_ACLKX9 G. p6 Z; F$ }; E1 w
| MCASP_PIN_ACLKR% f+ |, j2 m1 I! U: N9 g) j
| MCASP_PIN_AXR(MCASP_XSER_RX)" Y1 d8 B' ]7 j" i
| MCASP_PIN_AXR(1u<<(13u))$ }- i. x( j9 j% Q, j- e
| MCASP_PIN_AXR(1u<<(14u))4 j0 P+ h6 E E: _
| MCASP_PIN_AXR(1u<<(8u))1 a: O1 V; r+ @/ A2 q
| MCASP_PIN_AXR(1u<<(10u))
: E/ l4 l/ G z. H* Q' \, f3 _/ `' H | MCASP_PIN_AXR(1u<<(11u))
5 m1 p! M5 b" J; h7 s+ J );
% H( [8 p. D. X, Z- r% ]- \5 C5 H# l9 J% m
/* Enable error interrupts for McASP */6 R8 T( [, X+ {* B; l# Y: e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
% e% O3 k$ g9 I( N. y% O MCASP_TX_DATAREADY
$ x$ c) \* a6 }$ S$ N J | MCASP_TX_CLKFAIL
) I8 h* a+ v! J+ W | MCASP_TX_SYNCERROR# W/ D$ X% A6 ]: X( Z& H
| MCASP_TX_UNDERRUN);. u# \3 A2 f: { g
8 e+ h. \! ]; [6 T/ C c2 K( K McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,& K7 Q' Y' j& ?6 Q
MCASP_RX_DATAREADY) {7 w/ l4 l& K
| MCASP_RX_CLKFAIL. T+ b8 j8 z/ H w4 z
| MCASP_RX_SYNCERROR
* K' O' t1 ]4 n- Z7 } | MCASP_RX_OVERRUN);
8 Z% P/ h' H) \# W//MCASP_RX_DMAERROR MCASP_TX_DMAERROR' L/ U' Q) @7 o
" t% Y; C" a) z% Y& D}; @5 z: _5 J6 Z+ p; l) `* S9 X' i
7 ~' L: p9 m: J* @% c; U2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句+ ]& J$ T+ m1 r- F
static void I2SDataTxRxActivate(void)
# A( m S6 B3 J8 ?' m! U{
/ E+ L8 ]2 k# |) v /* Start the clocks */
+ g+ H" `& b, c- S4 }" E7 _, s' Q# V: C McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. ?& U8 f/ Z' X E, b' p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);9 E% l& m2 j E# i7 a1 B" M
7 I# E1 V/ ^( V% ^1 z! A2 V /* Enable EDMA for the transfer */
! ?- N1 B+ K9 L$ d- U// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 S. j! ?! z$ i1 G9 L6 a0 q// EDMA3_TRIG_MODE_EVENT);
& W" W/ h9 X; Z0 ]' W$ j9 a- b// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,/ i" ~9 E" J2 s* Q1 i! c& Z) l; q- n
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);$ M# v6 |: w9 f9 j
/* Activate the serializers */
9 h1 Y5 H8 g" A' w5 x McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ R8 A$ W" q8 d) H c: j! O% w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);4 f3 d5 y% S+ n# Z6 j
/* make sure that the XDATA bit is cleared to zero */
0 s; L I p$ E! y0 j4 _3 E7 H while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);) U0 E& H0 d( l3 S# Z
/* Activate the state machines */
1 J2 q4 {# U' l. D McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 Q7 r# P/ s) E+ z8 Z. G7 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 W4 s9 `: _+ k% c McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
1 C) N9 G5 a' c% d" j: b}6 ]: G) h3 j* h+ g/ H) m% H+ v
3 s, t- V7 A: _% o8 G1 ` |
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