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我的McASP配置分别如下:
/ p- }$ D1 u! j; c# f; Q) @. \( \! d管脚的复用设置是:
& i/ L/ N9 s2 G% y+ A1 _void McASPPinMuxSetup(void)
& T- V5 A( {/ _{1 O* B" Z8 N, M& t& }& I& ?
unsigned int savePinMux = 0;
: q0 p# E* J7 X( e8 t @ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \+ B% |! Q) ^, w" b% J2 F. P
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \' v/ G: s) Q. U# X( M: {: J+ t
SYSCFG_PINMUX0_PINMUX0_23_20 | \3 p$ n, x! g6 F) ]9 z9 [, `
SYSCFG_PINMUX0_PINMUX0_19_16 | \: z4 Z& {; b8 k/ F, W9 ^
SYSCFG_PINMUX0_PINMUX0_15_12 | \1 ? q9 u+ S7 y9 Q
SYSCFG_PINMUX0_PINMUX0_11_8 | \9 \& g1 B: t6 P* G4 ^2 B! U# A
SYSCFG_PINMUX0_PINMUX0_7_4 | \
Y/ a i1 E9 n SYSCFG_PINMUX0_PINMUX0_3_0);
: m) r3 B5 y& p& h# n' [$ z: ` G HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
+ @+ G* _- O( ] (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \; n* d% ? U7 D1 c
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \. T4 G6 Z0 k: E4 F* o4 n3 \, `
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \! }' _+ p) A, X2 l/ K q
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
" g! }& I8 f! t1 _) q8 Z3 s savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \/ ]* v& v. Q7 ?- m
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
" l* I0 F" a3 ?% _; Q* r: t SYSCFG_PINMUX1_PINMUX1_15_12 | \
5 n: z( a+ {& w8 w: _9 Q: ` SYSCFG_PINMUX1_PINMUX1_11_8 | \
+ Q$ B3 t8 d2 p+ J SYSCFG_PINMUX1_PINMUX1_7_4 | \
3 v/ A* t/ h( w0 } SYSCFG_PINMUX1_PINMUX1_23_20 | \* k' }, x. z, C8 M
SYSCFG_PINMUX1_PINMUX1_27_24 | \, o6 r$ X& X( v2 \% J% B
SYSCFG_PINMUX1_PINMUX1_31_28
1 e$ H, {: s ^2 P) `; v- r. t );) g3 P* a$ q: P7 Z1 X7 X% h( y
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
6 I9 h4 ?% K6 n4 D (PINMUX1_MCASP0_AXR11_ENABLE | \3 N, u; t- y1 _* V% k5 ?! a
PINMUX1_MCASP0_AXR12_ENABLE | \: T( G/ H) Y, C* B
PINMUX1_MCASP0_AXR13_ENABLE | \
& o$ C; ~9 S8 r, } U PINMUX1_MCASP0_AXR14_ENABLE | \
+ z( ]: S8 N& s, D& j& e( [ PINMUX1_MCASP0_AXR8_ENABLE | \3 C2 H: r/ c0 s; H8 ~
PINMUX1_MCASP0_AXR9_ENABLE | \. C, C: N- j0 `. H, o6 o
PINMUX1_MCASP0_AXR10_ENABLE | \- S3 K J6 V' [ Z+ b& S
savePinMux);
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1.McASPI2SConfigure(); McASP的配置程序如下:4 Z' T& C( }# |
static void McASPI2SConfigure(void)
4 o5 ]; U3 H' W3 p& |{- x" z% b [4 v: E6 |6 W, y, X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! {! z' h- c% c3 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
8 g: S1 \5 o1 W) `9 h( C. O+ Q! A% c! j. S9 ^. {: b1 D l% o
/* Enable the FIFOs for DMA transfer */
7 H/ |2 }$ M8 W6 B& Q% Q1 Y! P// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
7 b2 \" p- \( B% g) p9 V6 t* W$ A// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! a" k' T# h. }) q( ~" z: V
# T& n: R1 A9 Q, ?8 D, C; C /* Set I2S format in the transmitter/receiver format units */. ]# J# q/ f4 W7 M) B# _. X; {$ o# _7 f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 A5 _: T1 a% C5 O( v% a9 @9 m
MCASP_RX_MODE_NON_DMA);
, _3 l/ l# x. d( u9 x McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 T/ ^0 U) O3 C, p/ S MCASP_TX_MODE_NON_DMA);) Q5 [9 d- s- C" w- k; Z+ `
! a8 Q& E. G3 U' A$ Z+ n /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
J4 M. y% {$ u+ g# u, z/ }3 V! ? McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , ]' R- g6 X( J4 B6 B' m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; u2 b N, x9 B3 K c McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - ~, q& C$ l$ j+ D6 t, _5 i) ]
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);' D+ Z2 T+ B% N9 \) E
3 u9 X" f/ @& N
/* configure the clock for receiver */# m# T2 ^6 a4 Q2 o6 s2 l6 A
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);7 ]8 S' S( u6 r/ j# ~1 B5 B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% w) |( r' D; r H McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);" c1 J1 q1 y/ p: v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ }4 I2 X; P5 b" S
0x00, 0xFF);
& a# _% J( E% p9 j- d) z/ d2 I& }- Q. z
/* configure the clock for transmitter */
' Y% V4 c: c9 T" K7 B/ l// HWREG(0x01D000A0) = (0x00001F00);
' k2 Z' x5 z9 j$ `9 j/ }// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
- {3 } D' y. l8 v: h. F McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
; u& Y: [' i* R/ ?5 s: C0 u McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 Z3 ~2 c% ?+ K! W6 a: X5 ~ McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 B h# V' y# J
0x00, 0xFF);
' G( B/ `: O7 o& p: N J7 W; P) L- u4 x
/* Enable synchronization of RX and TX sections */
( T6 f! y& L. u8 n* Z McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
' m/ S F3 l' S8 o3 [- {7 i j. T$ I
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 R6 ^9 g5 @& z McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- i f" V! W& J' y/ K7 ?7 M McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 U; _' u; A5 d% ^) l
v. T9 ^2 f2 V% f; q /*: B" U4 O0 p1 T: w2 K6 o
** Set the serializers, Currently only one serializer is set as& K3 `! \# X' ~7 K
** transmitter and one serializer as receiver.# K& F& H9 D9 D, Z, n7 g7 M$ M
*/
0 w; X! V4 i2 ]1 N McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 f- b5 e6 W: s: z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);, i) e, _1 x- ?) K# v) F6 G/ \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);- Q/ n7 N! F) }8 i( j/ V' ^8 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
& U* `2 E- O! _7 ? McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
! V5 J5 d& k* T McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);# D& V7 v7 L6 W2 }1 Y
$ w1 W! b* b9 \; b" B McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
1 J" l1 ~2 v* b4 w; q }( u9 g0 e/ P( k7 j- L- s+ D2 Z6 M
/*
8 M0 W' G" d, x' k, z ~ ** Configure the McASP pins " T3 s% t8 D H1 W( J/ u+ n) W
** Input - Frame Sync, Clock and Serializer Rx
6 r. w) S2 H r3 ` ** Output - Serializer Tx is connected to the input of the codec
4 @% z) l3 M, }' X# ]3 r */9 i6 y3 Q7 x2 \+ b& Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ _0 ]0 p' a+ g' V3 B3 f4 S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
- I4 i8 H6 O4 B MCASP_PIN_AXR(MCASP_XSER_TX)
9 V9 y$ Y% e0 L& s& q7 R | MCASP_PIN_AMUTE& l% y5 e) o5 n/ \+ f$ [! _ ^
);
9 I9 e" ^- a# V; x8 S1 A" Q McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,* a4 A: Q2 p+ r% c% \
MCASP_PIN_AFSX
. @4 w7 |# W2 @ X1 {" l- l6 a | MCASP_PIN_AFSR
% U, ~0 \* R* { | MCASP_PIN_AHCLKX
% \7 a7 w7 l6 C/ s | MCASP_PIN_AHCLKR
6 [6 O; }/ E# f' a! i/ u | MCASP_PIN_ACLKX
u; S7 L" \* y* Z8 R | MCASP_PIN_ACLKR& y. D2 q% ]# S( m
| MCASP_PIN_AXR(MCASP_XSER_RX)
' H7 y. A/ }5 Q+ L | MCASP_PIN_AXR(1u<<(13u)), l+ C6 N( @+ M9 u
| MCASP_PIN_AXR(1u<<(14u)): E$ i5 M- K/ `9 V) _, o
| MCASP_PIN_AXR(1u<<(8u))3 }6 h7 g' [ {; O0 U* H) r
| MCASP_PIN_AXR(1u<<(10u))2 V4 }2 M& Z; H$ B1 B- a
| MCASP_PIN_AXR(1u<<(11u))
/ \ \* C. V! T6 x5 I" L0 B );
9 l, {5 Y9 y1 h4 P
p" g' v3 {' h- t /* Enable error interrupts for McASP */# B' x2 l6 e& w
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
+ G6 c" M' P; \) G, M MCASP_TX_DATAREADY1 m# T$ J1 O6 q- |, e( d
| MCASP_TX_CLKFAIL % z; X% ]& C0 k' w
| MCASP_TX_SYNCERROR
! Y8 J, R) z" I( ]/ u" i | MCASP_TX_UNDERRUN);
2 H6 P0 j; ~/ i! }6 A3 l
' a4 \, z) \- h, A1 z1 {: b McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
+ u5 N8 q) a8 h MCASP_RX_DATAREADY
- |) U' ~9 {8 R | MCASP_RX_CLKFAIL
8 P; U' d$ c0 S: H3 L( g8 |; r | MCASP_RX_SYNCERROR ( i' U# d- z& g5 g+ w
| MCASP_RX_OVERRUN);! P' f9 h6 y2 k2 G; Z' U- m: K2 N
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR) P4 d$ ]% R) |1 R" h* }! ^" o
0 A' A# i. ]4 w9 m; e
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2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
- |5 c4 `3 G& J# N2 P( k8 Rstatic void I2SDataTxRxActivate(void)7 [* w m* r6 }
{% M& g6 C# O. Z- R. L
/* Start the clocks */4 u! \* r: {- k3 N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 D+ X0 }) m8 L6 q( Q McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);) K/ e [! E& f) v" s
4 r7 q& X! o. Y+ o' j0 `8 b
/* Enable EDMA for the transfer */
: f+ R- V" R9 ~ J// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 U# D1 s) r" r// EDMA3_TRIG_MODE_EVENT);( A" W; x# ~' J* |8 l
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ Q" Z* \9 c* T' P; C O0 e// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);6 @* h; w# V! a+ N/ r/ t
/* Activate the serializers */
* a+ l$ E# p4 A McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" L6 m8 x. U9 ^7 i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);& \7 P$ t/ x. U6 l; q+ h
/* make sure that the XDATA bit is cleared to zero */
! z' {* o; y1 Y. G* y while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);) q8 c' s( j+ M' d# @9 y; v3 k4 x
/* Activate the state machines */1 q0 V9 p) l5 ^3 X0 R9 H( k. X7 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ z% O# A+ ^* ~: F8 P, @" O* C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" m6 A4 V$ K3 W0 }* M5 h2 v4 t McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);6 n& F) V& R; U+ Y7 X
}; i! e3 o8 ]3 q! s3 |0 ]2 `
$ T" J* H! ]. e3 u
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