我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, k6 X" R+ m; F% j2 u( f+ I' H
input mcasp_ahclkx,
6 _5 i* R; R1 P; x: r: Binput mcasp_aclkx,% H- n( [3 u9 I6 L D7 K: G
input axr0,
. [4 g2 {( v8 t
0 C4 G% I8 f. J/ H9 d1 @output mcasp_afsr,& |/ t. K) J: I# \* c1 p- w# y
output mcasp_ahclkr,6 e: Z- M/ i" g7 O
output mcasp_aclkr,
. a9 {! h, C" J6 Coutput axr1,
X8 e4 ^' r! |+ T6 t assign mcasp_afsr = mcasp_afsx;7 f5 G6 ]' \4 l+ i0 Q8 N
assign mcasp_aclkr = mcasp_aclkx;% n. J7 G6 V$ A) m: S& V! ^
assign mcasp_ahclkr = mcasp_ahclkx;
]$ B$ C* s: P4 l) L! Cassign axr1 = axr0;
) C* R2 }, R1 u3 ^ U0 S. l3 q6 y) k" d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ t/ k' L5 q+ j, h% r* P! h* M/ Kstatic void McASPI2SConfigure(void)3 `# w1 e1 T, A% g$ n' E
{9 I! W {/ ]: {6 y& X2 e: S% b$ }: O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( o& s) w) @3 T0 y! w& O! w- @' Q+ y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ E3 H3 k2 j( y4 R0 f7 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* R2 i4 e" K5 W# ]; m8 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 G! J& |& p& v* ^3 x' n$ K& u4 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B! d1 p4 X4 n$ h+ a: A, f2 CMCASP_RX_MODE_DMA);2 ], u( E4 J/ k, H% U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: V( X3 `/ H, S: E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 t+ z2 a9 G2 _+ Y+ MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 v9 A4 S! _" x1 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 v( I: k5 f6 Y* N* x# f- U7 ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : n V$ n2 n/ K" [$ `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- c& N B& B' D) A; J3 O4 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 h4 R( @( @8 @# A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & F. H7 i$ T. u; E; A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& k* a Y0 r' [. h1 ?% f2 A
0x00, 0xFF); /* configure the clock for transmitter */
" O; b3 C0 p& N- `2 b* a+ AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 c1 `) [3 w4 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ i* ^7 ?7 r3 g$ }$ O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ H* ~, R \ v( H4 W" o4 n
0x00, 0xFF);, F- c: h& {% ~9 c2 {
6 f u$ ~0 N: v/ A
/* Enable synchronization of RX and TX sections */
# ^! j. i8 O8 C8 E. {1 Y. j1 _! [7 X6 W- GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 R8 \" T7 s9 |, D3 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- U2 I J4 ?! bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 }; B6 F- t, V: p0 t
** Set the serializers, Currently only one serializer is set as6 F; v2 \7 w! s9 ^1 e6 I
** transmitter and one serializer as receiver.
6 W$ {1 [" o- q7 i V0 v( a# W# [*/! w: a+ j% c0 O* S# _/ r+ d0 u2 [; Y* y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 V* }5 B2 w0 y- E7 RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# L9 ]1 \/ g$ a9 B( Y' c' U** Configure the McASP pins 5 z% _2 V8 o" F5 v, E0 ?
** Input - Frame Sync, Clock and Serializer Rx0 R- q: {& G% D% F! {# q: z& a
** Output - Serializer Tx is connected to the input of the codec , G1 I1 G+ U U# C
*/
% j' ]8 q. m: q0 N8 D" f0 RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 }) S# G) i5 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ m6 G0 X! d; E8 J" z l" o+ t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 @& n6 X* S) @7 [" y
| MCASP_PIN_ACLKX8 E% _- C; C' |
| MCASP_PIN_AHCLKX& w1 v) f# l& X1 D7 o6 q8 i" M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 T& ?" a7 i" |+ v( a- nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 I9 h( D5 H5 V8 l
| MCASP_TX_CLKFAIL
4 X1 T* F9 k- X+ H0 p, `- g( {; v: P| MCASP_TX_SYNCERROR/ a3 c3 J3 D6 N! a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 [1 P" W8 |& v K| MCASP_RX_CLKFAIL
+ f# p0 ^& Z4 x% v5 d5 S' m% ~| MCASP_RX_SYNCERROR
, Q% i$ V% M6 |" m- }| MCASP_RX_OVERRUN);/ E; N7 t# N: U* P0 u5 L; M
} static void I2SDataTxRxActivate(void)
7 S, w# M7 e# a{4 s2 o- ~. Y3 J) o) N) q5 F, k
/* Start the clocks */
7 X8 p: v5 Y2 D, p3 CMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# i7 { ]0 Q. E$ n* N+ R1 g7 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! E! V! W6 l( g; g+ T& pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ h, C( R2 k* L# `! Q% |
EDMA3_TRIG_MODE_EVENT);: q) B/ {: _8 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# M5 V: ]1 o+ h3 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 b+ [- I5 A1 ?3 ?9 lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. S# x& c% l% `4 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: Z2 K _1 |& h1 [) N; P3 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* H) W r2 P t: L6 _* o" F! sMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' W, f# [6 D; f! q. SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ Q, @8 E: p. _+ g0 J3 U6 N! G}
. [# n5 g D. p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , {' G: e5 B! d7 u" W/ o8 N; G
|