我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& i& e* |5 Y6 A; W0 P s v9 Minput mcasp_ahclkx,4 c( y3 B: @. N+ r2 `3 ^7 k! o* E
input mcasp_aclkx,
6 j; v1 M8 w" ^# H/ o- ^input axr0,
; \$ }" K5 Y- h* e& M3 e' _0 K: X1 [4 G8 p5 M$ r
output mcasp_afsr,
! i6 s- W/ J3 [5 s( w Noutput mcasp_ahclkr, ~" X5 S' B$ z1 x& x8 c+ \
output mcasp_aclkr,! Z% x% b* G! S, z, O
output axr1,
/ a' x7 r5 @4 C0 F assign mcasp_afsr = mcasp_afsx;4 \" C8 j: j R. e1 n: W
assign mcasp_aclkr = mcasp_aclkx;
+ P# ?5 m: L( W& @/ p; hassign mcasp_ahclkr = mcasp_ahclkx;
: Z8 P. }, n. k s& l' J% Tassign axr1 = axr0; 8 ` b, ~7 R% q
5 G+ y0 J& a5 w7 J+ S4 H' |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' ~ s# l7 |3 G7 Z6 V1 o' Nstatic void McASPI2SConfigure(void)
8 R8 L5 d3 W8 [/ w{
4 ?( i4 a3 J* e9 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 r! M& z" r E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; E0 f2 k( _. V3 E3 x/ E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( m. J% H; @, S) I) cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% f1 t3 W- z/ k2 `8 j' a* E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ y# Q; O z& d. y5 m6 d/ N
MCASP_RX_MODE_DMA);5 H2 K2 W+ U: Y0 g/ X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 G8 `. q* J2 f2 pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 K& ~" z$ v9 P- @' p1 I2 p; W/ M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 x# u7 b! Z8 J% {7 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* O0 \* V t+ ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% [: f5 ]# V& B" j2 w7 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 l; a3 w8 t5 v. SMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 I$ a6 O" V" x# a) O) ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 o. U1 _ ?+ r" f! t B! d% m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 v$ |. H$ g G0x00, 0xFF); /* configure the clock for transmitter */
+ d5 k; L, z* s/ @% EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 t9 Z, s% N8 Z# G8 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 o0 A( o/ ~1 U. V0 |. Q2 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 U( V# b3 r9 i) a) o2 R& ~, |$ X0x00, 0xFF);+ p: _# ~9 F9 `7 ]
$ L/ ^* n. R7 `2 T5 W/ _/* Enable synchronization of RX and TX sections */
$ D7 y3 o8 G. [7 h- W5 e- tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ M2 S+ l& L, m/ KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# {9 |+ [# n$ @7 Y' ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; q0 n% i+ e. n& w" M, ?6 B$ G; e3 Z2 {4 d2 @
** Set the serializers, Currently only one serializer is set as4 g' C% r6 b5 a
** transmitter and one serializer as receiver.
8 X: M) ^7 N1 `! j- H4 u*/% y4 S7 |: V' w9 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* m M( {/ s5 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! D/ y, J# ?4 z, J/ g2 @1 [** Configure the McASP pins
3 Q; r7 I% v) I$ k9 K** Input - Frame Sync, Clock and Serializer Rx
/ ~5 m/ H+ g( Q6 @3 P, o! ~9 u** Output - Serializer Tx is connected to the input of the codec
% A; S" O: ^1 q) C8 ~$ }*/
- c! j. b' E/ H4 j6 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- X. @/ \7 [; h' jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 o" I5 f9 f+ l; R/ d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. D9 ~6 F5 ^/ S$ ^4 _; c| MCASP_PIN_ACLKX
% S1 U4 }* g! Q9 L# F/ M" o| MCASP_PIN_AHCLKX! J7 j1 t2 f* V+ S! L5 t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 i: ?5 Y7 u& G) E7 G |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 F! M! @% M4 f8 e
| MCASP_TX_CLKFAIL
" R7 x* R; g4 N1 d1 t| MCASP_TX_SYNCERROR
# m- h: x2 W% X% Z' Y# Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& e& R& Q' O1 r* z5 |. [7 P| MCASP_RX_CLKFAIL
" r: d' Y- z. q B5 b% l| MCASP_RX_SYNCERROR $ Y+ k9 {8 g2 w3 R# |
| MCASP_RX_OVERRUN);' q" e5 ]/ R* A4 J
} static void I2SDataTxRxActivate(void)4 y O* _$ T( b
{# c8 r) ^+ U; m" A& i
/* Start the clocks */0 I+ g- r z2 l1 [' ?9 O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 `( c' j) A3 e' a! @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ ?% X4 Q j% oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' @$ k3 ?9 N, i+ f! ~$ C
EDMA3_TRIG_MODE_EVENT);
- T0 Y6 r& Z" z* R" A, ^3 D d- eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# I1 ^. X* q0 H( N. m( J; dEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ R' t( b6 i3 e [/ U% X gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 H' { P3 F9 ]( g+ EMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) h6 _+ s5 M* y8 y8 J6 vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 u+ l' j; @* _ F5 c9 a; ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" X: h' G5 d ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 W' r. `- {' ~0 p' ~}
! V v/ B+ `3 y* m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. N5 z4 F# z( s t5 F6 @
|