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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
C- g8 n7 P$ z3 _0 }$ zinput mcasp_ahclkx,: ?1 C: @% ?6 M5 b
input mcasp_aclkx,
* b1 K7 I8 F* j! x9 [% sinput axr0,
+ f2 J- k! H/ j6 ~' o/ K# y& R& i7 r2 G" a( ^- j& K1 p
output mcasp_afsr,. Z" ?% X) _- G
output mcasp_ahclkr,
( m0 g; g5 ?( T- r+ Joutput mcasp_aclkr,$ a% ]! w" K( E, A& K
output axr1,+ v0 A3 ~. k1 i# H2 ^0 B
assign mcasp_afsr = mcasp_afsx;# \- y8 s. d7 e0 X
assign mcasp_aclkr = mcasp_aclkx;( B. `9 c) d! P. h
assign mcasp_ahclkr = mcasp_ahclkx;/ A5 m( c1 V+ o
assign axr1 = axr0; * ?$ U: i6 D/ V
" v% h( s$ H% { T5 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( E' o( g& M, jstatic void McASPI2SConfigure(void)$ p+ ]. f7 f2 N5 p& L
{# A- f6 p) S3 ^4 @8 K {+ c# t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& g2 h5 z1 I9 j" d- c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 K! y8 s& f2 ?4 u/ w% l7 K) Q3 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 Z$ k. x. t7 ~- e4 s0 v% @5 j# mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 M8 ~; ^, z# Y2 l" c: t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ S. l( J. k" O( [, E
MCASP_RX_MODE_DMA);6 K) D/ J9 [/ g5 k0 D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! v- Q1 q' l1 @* `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 u! @$ Y3 Y8 t! W, \* f" p' B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- f6 R# M( ~. D, m; g( XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 F' H' a# k( vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 J a7 m; z1 t5 jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 j/ A; \$ J8 b' P# h* Z! ^6 Q( bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, V4 f# H3 w4 B2 z3 @) s e0 \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
d( _, [6 r1 ~; J2 r$ BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 Z. n6 K3 {+ }! b0x00, 0xFF); /* configure the clock for transmitter */9 g& w9 v5 ] d9 r0 A+ y8 C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) Q8 |5 k0 m7 C4 q- f4 e, N' R+ j; PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! S" R S$ N, n" k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 Z# q; ^# f) t0x00, 0xFF);
% r0 c# `/ ]4 |: J) q0 o3 H4 B; ?- R! ~
/* Enable synchronization of RX and TX sections */
8 `) L7 f e; a1 ]3 _# eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 M |* A! y% lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) C$ g2 M: z" n! _, ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. B- M# A) }: T* ^3 C$ e** Set the serializers, Currently only one serializer is set as
2 `- ^/ t7 s: G** transmitter and one serializer as receiver., K* k* P7 s0 |
*/; ]9 w2 `/ @& L3 w+ u- E1 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( x) |; V. A, J* L- u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) E" _, f' x5 n& y** Configure the McASP pins
$ g' J# d2 e ~! G8 S' a U4 f% x** Input - Frame Sync, Clock and Serializer Rx. U' `: w" i4 X/ ~* c) K6 q
** Output - Serializer Tx is connected to the input of the codec S' |3 q' a- P4 V* E
*/
9 e8 w% i" K7 v7 Q) @8 h- sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; n. Z8 x) h; U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ j( M3 ~# g4 Q0 Y( gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- I6 A j3 N( ?& f. P
| MCASP_PIN_ACLKX
6 p( C5 o) x. ~" F% F+ A T+ E1 a| MCASP_PIN_AHCLKX
' ^% j q- K3 Y( J0 p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 G! ^# N( ]6 ^( ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 S! u7 j, a' T" u, F d
| MCASP_TX_CLKFAIL % j4 s6 T0 R- k/ Z$ u
| MCASP_TX_SYNCERROR
1 L* c6 c4 v0 u3 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ u2 t) g, A C8 Q! }' h& p* f| MCASP_RX_CLKFAIL
& t" m- Z. M- X8 o| MCASP_RX_SYNCERROR / [' j& c6 P$ [0 J Z
| MCASP_RX_OVERRUN);$ C' y. v! w) Q) e0 D, c* P
} static void I2SDataTxRxActivate(void)
& v F8 X3 ?5 h" N{
' W- ~; m- _3 j' \/* Start the clocks */
3 q# H$ C2 i; p) p- v m7 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: p; R, D/ y1 Y5 h% z i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. _0 g* x' J8 ~2 o( lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% t! ` d: A, Q' ]: u9 G% o; EEDMA3_TRIG_MODE_EVENT);. ]7 W# S' c5 @; I# p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / A+ [4 u1 `3 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: R/ G) F+ r D" A6 f7 p1 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 K) c l( O5 G# A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! {% Y5 ?7 I% d" N+ p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ ], t4 P* T+ \) h4 \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 d* l+ w2 K' Z& o( K/ `1 F7 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); |- I4 n5 P* }
}
' A2 w& n# w. D! x" K2 J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 u" e9 M1 V1 X d/ @: [: A
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