|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# W( M; Y! `% A2 Qinput mcasp_ahclkx,% G( a& z) W! D! _
input mcasp_aclkx,
9 d9 z+ J& o; Z) S) T! Iinput axr0,
9 P* v, G7 C, W. n% R; V; V! L- H/ W' B- s8 J, S6 N, B
output mcasp_afsr,$ D5 p# y) W, ~2 s( `4 j% K
output mcasp_ahclkr,
% v( B: k4 F2 L# A) d0 x4 ooutput mcasp_aclkr," e; P0 s% T3 F3 x9 b$ H' n
output axr1,' S Y- L9 K5 b i
assign mcasp_afsr = mcasp_afsx;
1 X6 t8 p P6 |- {8 z7 vassign mcasp_aclkr = mcasp_aclkx;7 w$ p) e) a3 y' m- `
assign mcasp_ahclkr = mcasp_ahclkx;
* N* Y; @; l: V1 H5 ?) Nassign axr1 = axr0;
* Q4 X* b' m( E3 s: p- U; @
3 {, p$ z' \4 w# @+ m- ^4 _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : e, I- H6 O8 Y" @
static void McASPI2SConfigure(void)
5 i" b/ q; F: _% n: c0 `8 O{
: l/ r) P$ A- gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 v$ X3 F% E6 QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" @! A" K' k/ Y0 E8 ?4 P1 o! eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 @2 H3 J; \' J& _1 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 O# q3 r* r9 Q9 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, C; c+ q1 X+ p; V. F! y
MCASP_RX_MODE_DMA);* n4 Q& \9 r( B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# C5 k' D% \( \3 }2 t H, vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ a# V& h4 O8 Q( G( W" H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , n2 z2 N8 e3 E- p; t9 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 Z9 P. p. D' a p, }( ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - f, R* a. C5 F4 A! }; c4 x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ P k% \$ c0 m p% }6 W/ x2 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ S; D0 m3 C1 N5 H: XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
M% } Z" g0 A- h# s" h6 mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 V R! o; T' Z
0x00, 0xFF); /* configure the clock for transmitter */
# c$ ]* Y" e# [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 U5 m( S1 R& a' KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 T9 Z; v; R4 T& L1 B: J c, y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 p1 [" S/ \( x T. j5 G
0x00, 0xFF);1 L) ^& h1 Z3 K9 p" D- \1 \
( N9 i* P7 q7 a7 R, m/* Enable synchronization of RX and TX sections */
" V# F1 Q- [. Y8 g) l7 v. QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 [7 M6 V: x3 y6 s( ]9 K& [ W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 m$ ]0 A8 Z/ \5 C, H% G* Y7 p! BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& n) N9 m4 b9 N** Set the serializers, Currently only one serializer is set as
$ p$ u- }3 l( o1 Y/ P: M( |7 F3 p" j** transmitter and one serializer as receiver.4 }0 n% O3 z/ S) Z8 i. c' G2 X8 O- K0 @
*/9 S3 `/ N8 g/ D& \# {& E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 a- S: l6 {/ w6 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- B; {3 ~5 U6 O8 c! q' t** Configure the McASP pins 8 O4 g" u0 B+ ]. O4 h& R1 e/ ~$ A
** Input - Frame Sync, Clock and Serializer Rx
2 l5 E3 J0 L, u8 Y( z** Output - Serializer Tx is connected to the input of the codec
2 T' C* i; ], U4 u3 F B% I*/
0 b9 W8 M2 i# h. b* `% nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 p; g3 c6 X. Q9 WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; a$ [8 q3 v9 a6 r h4 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ f7 k! m$ w! d/ _6 X% ]| MCASP_PIN_ACLKX8 C( A$ @) ~+ w3 Q; P7 l9 u
| MCASP_PIN_AHCLKX
+ L$ C% ], o; r/ V( E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# V, S) d% H$ K$ h' S ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 z$ C/ @& M& p+ T7 c. L% G; J| MCASP_TX_CLKFAIL
. K4 p' k7 R( U; G9 E- l8 ]| MCASP_TX_SYNCERROR
5 b6 k" ^' s" O5 n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / l, S6 L5 D" f
| MCASP_RX_CLKFAIL$ q' |/ `9 _- c& R' [: J, o# S
| MCASP_RX_SYNCERROR
9 }1 ]9 f! |8 p( {4 K$ Q9 U| MCASP_RX_OVERRUN);0 w" f8 ]& U" |( k: Y" s3 k7 A( U
} static void I2SDataTxRxActivate(void), |4 l& ~9 D! z: M4 N# i6 c9 A6 g/ y
{: Y7 `/ T# G/ C& q$ r9 k. W
/* Start the clocks */8 v' b3 d/ A, T, T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( {9 B( W6 N( L/ P0 V( O& VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 ~) d7 s: M+ c8 M ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ u; ?' d Y7 |/ d3 J' bEDMA3_TRIG_MODE_EVENT);+ X* E$ z3 {/ Y% i) c( P, c: Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + V) q; d# B [# ^% H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( P9 y7 N# j* h; @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& b( {0 M9 ]$ |- H7 p: IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 o; S9 q. n8 L# S4 Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 X* _$ }' m/ V- ~# c$ _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- ?+ \* ]+ X# U: U N$ M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 R, Y; |# U+ A} ! [: K0 P4 v: P L" m/ ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& v: y0 s2 D& d |