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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: J1 M; u1 g9 o3 D' p. p0 A
input mcasp_ahclkx,$ x, U R/ p3 R p+ G
input mcasp_aclkx,
1 ^1 ]; p- u9 f' J/ p t: Z( ~input axr0,
+ D7 L# e5 Q; A2 |' d
+ t# N* B" A+ f' s ~2 woutput mcasp_afsr," z/ l f$ }* [9 N g( P
output mcasp_ahclkr,# ^5 W5 @, Q& x0 V1 i+ B
output mcasp_aclkr,, a( E- [- b) `7 S7 q8 y- V: Z
output axr1,
8 q( q/ o6 z+ k n0 }! [ assign mcasp_afsr = mcasp_afsx;! E6 A1 i# m# r3 ]* }$ @/ U
assign mcasp_aclkr = mcasp_aclkx;
6 X; E5 I3 M4 f( ]( m) passign mcasp_ahclkr = mcasp_ahclkx;, g* L9 m. \: _8 t) N
assign axr1 = axr0; " y) N$ a T& S. q, |6 \
* w$ \' X( q! D; [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" F9 k) D$ U, y# @# P c) Dstatic void McASPI2SConfigure(void)
2 D9 n) E/ g! p7 ?3 U5 O( B U! o# E{
9 ~8 T+ p% b% v) h2 n! a; n+ SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ S, C% ]) h& J1 V$ C- e9 rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% \* i8 a R* k7 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 ~5 B! G' W4 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
J7 r0 A' f2 u4 i% ?- QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 z( t) L" E' ]8 U& y, Y0 k
MCASP_RX_MODE_DMA);
, e$ Q# ^/ p8 \ [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 O% c6 N$ b- q8 C: p. ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. s+ A+ h0 E" e; P. AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) k) I. w9 ?$ p5 [; m+ @. U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 \% C, `4 x3 a# [: g9 b: v9 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 Y+ r$ K. ]) j! Z. K2 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 m' Q7 R" _0 b( X& c3 e. y. EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ p! D2 C: |9 y L0 }1 i, M/ N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, W8 n+ G4 j1 u8 S; p, RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 p# B" p+ i2 w- |, k7 m
0x00, 0xFF); /* configure the clock for transmitter */
0 c1 j& P" ?2 r8 e% s; TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 B! H" R: @! s5 _- o& c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 X; y" @ d8 F0 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," o+ `# n- ? {0 \6 _; w9 D# r
0x00, 0xFF);
% G2 p3 P& U5 K; ~6 S
! q, T3 _+ W0 J+ \/* Enable synchronization of RX and TX sections */
& Z/ U* G# ?) D V% MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// d4 r2 Y) |7 a$ }9 u) I0 T Z# D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' F( ?; K) R( z6 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
S i6 p: K. o* B! a* D** Set the serializers, Currently only one serializer is set as
9 R, c5 A0 |1 G8 |** transmitter and one serializer as receiver.
/ B8 s% e8 ?( m! Q7 ^7 B*/3 C, R) U- ^, Q4 A1 t8 m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; [: u) z- j2 g2 B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 g" Y4 n9 j% |6 H3 g% }** Configure the McASP pins
9 M5 Q& O4 m0 _; ~** Input - Frame Sync, Clock and Serializer Rx/ H; I0 ?3 u# e% ^
** Output - Serializer Tx is connected to the input of the codec 9 I( L9 b0 h2 T" F* I* j' t
*/3 e% h i+ F8 l5 U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ V4 O* b0 y2 L" c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 k2 q* ^; T" n' H% ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 @+ W; ^# `$ ^ ^/ x; t1 R9 o) P
| MCASP_PIN_ACLKX' B2 }) x8 J5 m! H2 S2 T
| MCASP_PIN_AHCLKX
8 ?& ^% k- G1 V8 ~" f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// c9 Q q2 B" U2 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. ?2 D$ p/ K. x# O$ R5 C| MCASP_TX_CLKFAIL / R, D' ]) T! g
| MCASP_TX_SYNCERROR
9 R/ z+ d( @3 C( a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# Y2 L {0 t( @# X: K1 [| MCASP_RX_CLKFAIL" X7 V. V) }7 Q# x( s! Y
| MCASP_RX_SYNCERROR
. Q/ U0 n) x1 l) F" c1 T! o| MCASP_RX_OVERRUN);
0 ~" f: C1 p3 d# ^} static void I2SDataTxRxActivate(void)9 j1 ?2 N: o& Z; p
{
5 q$ d8 Q4 }$ O( z" c& G: H/* Start the clocks */
^! u5 b1 ~: R; \$ U bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. I L3 |8 }5 }7 @9 i% v' ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 t) y; \. v9 Y7 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; w) d% \1 }% c, M: _: J8 X
EDMA3_TRIG_MODE_EVENT);: V# q1 q# H3 p: a$ Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- J, p. }8 n$ ^1 t; J" aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( u% v% F& R! j |0 }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
l, r, y8 P1 G- n4 r4 v: f, gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& m; g `3 H+ a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 b( p. q; v1 ^4 P; h5 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; K& K2 a u9 l. ]1 m- U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 d; k+ ]2 |( m9 Y
}
1 Y2 Y) C) V) z! k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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