|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 J3 G9 p7 e. ?3 H$ B9 \input mcasp_ahclkx,
: W, [% N/ k/ s6 q& g7 cinput mcasp_aclkx,% j% G6 ?6 A3 `
input axr0, m8 J1 P2 s2 M+ f- Z o/ s8 w6 D g
% W0 e' Y1 p% W/ D# c, l
output mcasp_afsr,
0 [' f0 @- F" e9 Foutput mcasp_ahclkr,6 m; Z2 R" @1 X
output mcasp_aclkr,
4 V9 ~$ l: U2 O3 Ioutput axr1,
2 m) `+ @. p) {/ H assign mcasp_afsr = mcasp_afsx;1 K7 F8 b5 E7 C4 D
assign mcasp_aclkr = mcasp_aclkx;
4 P. n2 O* |0 h3 oassign mcasp_ahclkr = mcasp_ahclkx;' w) a: S3 o% Q8 |' F' O" O
assign axr1 = axr0; & Y, q2 M1 ]) e
6 p4 p' I9 K6 \- V- z( |/ o7 r( W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - L l3 M' E5 j8 |
static void McASPI2SConfigure(void)
' Y; f2 K8 g, }( T; `{
6 T9 K. O/ O5 ]/ `4 HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! N( _, G9 ?0 A! p$ F# D0 `# H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, y$ A/ }0 f- uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 o6 {- L* _$ j: l+ B- Z6 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- @# D0 T- c4 `$ _/ w" ~ W! A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( u' _: U& v e
MCASP_RX_MODE_DMA);! X% V) a' G- C; L0 R- i8 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- [) t' Y. ?; B: j( o" |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! V. h" u' T! w z2 nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # X' v7 c$ u) C% B" K/ \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 c' d! p* T5 |+ f6 e, Z- CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " M' C1 p$ \# k* m/ b- p5 v2 u' r |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' A) B1 h: N: xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ i$ H/ |( l8 j7 ]4 ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 z8 I+ b, Z0 |4 e* |4 z! n! U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 a5 p# ~9 w7 V7 U/ ?& p
0x00, 0xFF); /* configure the clock for transmitter */
" v1 @3 H' K7 iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 \5 I% o, J, L3 LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' d! T/ Q; p3 e( d9 T( tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, Z6 Y) N) R5 w" T0x00, 0xFF);6 o: x! h7 X; P; L( Q U7 n
/ g% Q5 \0 _1 ]0 ~7 s
/* Enable synchronization of RX and TX sections */
( N8 p4 p- l/ f. T( c# Q: D) ]2 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 W* h* g9 n5 B2 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ Z D" {; S7 }4 H, `6 t# ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 p7 M' j. p {6 q9 a
** Set the serializers, Currently only one serializer is set as+ X+ N4 }) Z" J% Q0 S
** transmitter and one serializer as receiver.
, j2 p8 M6 P$ z4 H*/
* u! ~6 U* A7 {, t/ sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; e6 k+ ]2 A9 M" H* e# D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 O' }( `! O) ? Y* ~3 n% L( ^
** Configure the McASP pins 0 Q% L& e- u( @) i$ _( l8 C, g" o
** Input - Frame Sync, Clock and Serializer Rx
q: @8 ~) B5 {2 ?2 Y2 J- Y ?** Output - Serializer Tx is connected to the input of the codec
4 P0 y' m* l6 w: I3 I- u/ f4 \*/+ _# G6 W" F9 `2 g @6 V* J3 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% e- a6 g+ T KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( ] e# {8 H& w0 w% [2 @. nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ O% {; \( z* v9 J| MCASP_PIN_ACLKX
) \7 s$ ~ K, Y& \3 \| MCASP_PIN_AHCLKX
; [/ Q2 a4 K+ a5 Q* a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' e- x2 E, _* F( q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' ?0 W! j% s) s9 k2 o( K| MCASP_TX_CLKFAIL 3 _& N5 Y+ E3 x
| MCASP_TX_SYNCERROR
' {, m; v) N! c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 x5 \3 q: S, U| MCASP_RX_CLKFAIL# n5 A+ O! D* I+ Q X
| MCASP_RX_SYNCERROR
4 y1 i3 c, _2 r& R, s| MCASP_RX_OVERRUN);
0 Q6 w" e3 }" O B6 M, R2 R} static void I2SDataTxRxActivate(void)! d( C3 q: G" E* @3 ~
{* x+ h. x6 w6 u, O8 j! ~
/* Start the clocks */
) b; }* ]$ \6 U GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, I6 O. X3 H# V @* a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 M7 `+ y F/ s, S4 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# L% ? ?/ a# ]& H2 N, ^9 L
EDMA3_TRIG_MODE_EVENT);
3 F# u8 u- H5 u0 r. F) gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 s/ V# {' X. F8 g7 R6 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) d$ j& N' C' V- Q a0 t+ l# \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! ~- H4 m; P$ O4 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
p1 e5 a: W9 a9 @/ l4 ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 A5 n+ T3 v0 o6 r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); L, q1 X5 B2 ^! o u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); T8 T) f3 {" @
}
5 e% N1 \: q" A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
: v- E; @8 U; w |