MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
/ X. ~" [0 F4 D. K$ zinput mcasp_ahclkx,
' v3 d# {1 v7 @/ c1 c- Dinput mcasp_aclkx,
input axr0,
$ u, m5 F! }% X. \- T. c
7 f- ~8 _7 h- |7 T( P/ [, d" }* Youtput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
9 @! T" u7 V0 V& q4 _  J" ]output axr1,

assign mcasp_afsr = mcasp_afsx;
% j+ O* y' j# C  O5 @7 A" F) V& H, R0 jassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
% Z& F8 l$ U; ^  ^4 H8 ~, m+ ^4 J% P% kassign axr1 = axr0;

9 |4 i! X+ A/ \& g+ ?7 l
, [3 W# \! z4 u/ R$ ~

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

. r( d/ Y8 j1 j. c. w

static void McASPI2SConfigure(void)
{
- B! |# }# ~) `% ~' P' M. a) u. GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 J4 W7 w0 l7 \$ L% }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
/ d% Z5 @& P" a4 S& E6 {: cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, g! I% ]3 d  E$ n) R* g9 kMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 c  O0 \: x, r3 L/ H3 z+ ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# @! N& r9 o7 G- p2 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
% ]/ l) |' W$ i: O: hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 V  f8 k* e- U7 G2 w. o+ aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
7 K8 ]* s3 a4 u. ?' NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 t3 J) W) @$ @% zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 p5 r( @2 _5 ^# }' x% W( YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 D% O! J$ O( Z7 \" b& q0x00, 0xFF);
& s7 O. H& z7 y7 ^
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 B: c: i. f# G$ O) iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' N5 n/ j  D# V/ L( m! QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
8 ?1 }% w- y0 \2 u6 h2 q2 K** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
1 z5 M2 z2 @  k) L( w** Output - Serializer Tx is connected to the input of the codec
6 W% ^1 v' X, k; D3 k*/
! B' x* K9 ]4 R. {. eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 v# o# M% v& [0 T* o+ H! i" a* zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
, R+ E! T& M( |: _+ h% ]| MCASP_PIN_AHCLKX
; k$ ~/ d0 W+ f! @" Z  o- q) A( D8 _| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 t6 a' n9 z5 H0 Y1 L; H. f: || MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
2 {# h8 Y; }3 W# F7 e; j0 q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
5 X) f% U& q1 w( |( d| MCASP_RX_SYNCERROR
0 g7 G1 z% U& M| MCASP_RX_OVERRUN);
! f# N2 S; ?* {8 K! ^. {2 I}

static void I2SDataTxRxActivate(void)
2 B1 ?( s, }3 ]% Q7 ?{
/* Start the clocks */
* {- y/ L* ?3 U1 T' JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ j# d/ _' L6 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' t0 u% w" w( S! l  P8 ?2 g, z) u! W" yEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; W2 U( w; I3 Z* Z1 |, n7 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' f$ M. \7 g2 W3 h3 QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
; X3 ~/ p( k6 V0 m* A" U" |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" H, V% W; V, GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.