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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; b! U; }3 T: \6 C7 Dinput mcasp_ahclkx,- b* d: m! R9 v' e: n; Q% y: a
input mcasp_aclkx,
' U( i) ^! y: W8 Z9 zinput axr0,' G( `5 ~4 Q) `% s( i: E
& E* [8 z4 Y8 j$ g0 Z( Eoutput mcasp_afsr,6 B R- e7 b U
output mcasp_ahclkr,
2 X. P7 f) d9 G) r6 u- B: toutput mcasp_aclkr, V% U T! h0 m
output axr1,
1 C2 f9 o* Y8 J1 d assign mcasp_afsr = mcasp_afsx;! I O) E8 Y3 H4 c# R+ T1 a
assign mcasp_aclkr = mcasp_aclkx;
/ N0 G. w' \3 ?1 \7 L. jassign mcasp_ahclkr = mcasp_ahclkx;* E7 ?! C& G2 O. n/ U: C
assign axr1 = axr0; ! b! b* h) i2 u$ E
" J& M1 g6 q( E( G8 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 Z$ c5 B; T% O& ?' W {$ I
static void McASPI2SConfigure(void)
* X* a; z: ~) }7 S/ r1 w{
+ Z f+ i0 E7 f- g" eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 Q* w2 M5 y9 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& S: M& `4 {) ]: }; vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 ]) ]- Q/ ?6 E; g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 s. G0 M$ J' l4 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 R0 Z6 U8 s1 U: x/ |# Q) F- G( kMCASP_RX_MODE_DMA);
/ a4 y. m; ]+ \. a1 [, l0 y, gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ~3 q' V2 M$ [# i8 ]/ n' G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 W; a' A0 N4 U2 p$ y$ E6 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. O7 k1 P) f1 v6 R3 u5 o7 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) D. i6 d! k1 y4 _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 F4 `7 I7 ^7 U6 N9 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 Q) @1 l8 E- t# ~& V. m' q# I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( h5 c) T* c6 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % i1 o' a) t( }. n# J- z4 n& u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* v- A. G0 Z( w0x00, 0xFF); /* configure the clock for transmitter */9 f$ ^8 c: t9 s% Q; s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. e) P* f' `2 M& h L$ [* n3 I' T( |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% p4 q5 J4 N( w* l/ P% I: `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 N ^( T% l8 Q+ v) n# H
0x00, 0xFF);0 b) o" d4 D/ q( g6 K5 j
( O; i8 j1 b/ E% a* ^' H/* Enable synchronization of RX and TX sections */ , }6 b0 S$ t- y9 Q* |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" K6 a! ~% \* G [2 w* cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" C3 l1 w5 o% }. LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, l. M5 H! K/ C; Q [4 S8 \) H** Set the serializers, Currently only one serializer is set as$ {; A E. H A4 |+ l
** transmitter and one serializer as receiver.
7 F( H: R' Y" [) A6 L, y' F. s*/& u, ~0 C+ l$ t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- r4 v5 G/ ~1 t! a7 j; [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ ~& P* U$ P$ E$ ?** Configure the McASP pins
- `( \2 R9 Z2 ^$ l2 F% r/ T Q# h** Input - Frame Sync, Clock and Serializer Rx0 O8 K) V( c: F! }& q
** Output - Serializer Tx is connected to the input of the codec
3 {, N; Z6 }2 ^' P/ P. F3 U*/% j! g' j3 M4 l- y! K' L( n9 V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" N8 g& t( k& o; U7 o2 @2 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% }% Y6 X- e7 B& ]9 v/ w. g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& B3 j& y$ i9 D# f7 a' j
| MCASP_PIN_ACLKX
7 H+ x3 O) G: @$ [; y6 ^| MCASP_PIN_AHCLKX
; C/ w X, j$ f3 |) Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 ^, ]3 j) i* l( D8 d, D2 xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( t* j7 P2 g9 \% a/ k" D| MCASP_TX_CLKFAIL - d% W& W$ R% U. B* B
| MCASP_TX_SYNCERROR0 Q" U! j6 P* t2 g' e5 f/ Z3 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, E4 j4 J; X, J' B4 ]| MCASP_RX_CLKFAIL
1 g) `: V* [: P ?; U6 J| MCASP_RX_SYNCERROR
# z" a3 |+ {$ J! N3 l% j' k| MCASP_RX_OVERRUN);1 {* L s- n' w0 f% N4 c
} static void I2SDataTxRxActivate(void)
% c* O! B8 j% g% s' Q" r{
; V8 h2 u, b) U8 N- ?& e* f/* Start the clocks */
8 Y# W9 t# o A( n3 t% Z$ F1 _" uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, r5 E8 c: Q; }4 t0 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, k, I* x5 k, |% ^( ~7 I; k" {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- n: E) v" G8 _ V$ R, N
EDMA3_TRIG_MODE_EVENT);
+ v x! x: t, X0 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 @3 p8 ?8 D$ @. i0 r. d7 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 s: w: E* z+ @8 }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 I n+ Z+ u) b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) ^: N, L, z( T( \9 _: iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) K3 z. U- f# i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: ]' f1 [( i" x' i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- m# ^! u4 a: ^4 @9 u7 j3 Z+ a}
+ U q6 h' C# B$ Q3 w0 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * f5 H3 z4 m3 [) ?
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