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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,: C) S* H' v7 P$ d# v
input mcasp_ahclkx,
/ z9 I7 e b: R4 a" ?0 S* J3 H* i/ |input mcasp_aclkx,/ p' m$ Q! ]) @, _( W7 o
input axr0,
: N+ I( q W) _9 {1 ^
3 [" m/ G- C* V+ Koutput mcasp_afsr,
, `, ?" z! S9 `output mcasp_ahclkr,
& [- X6 W: g: K1 X. m5 v0 S! Routput mcasp_aclkr,6 L+ s. ?1 d& j4 Z( m
output axr1,
- W; B( @7 o5 U assign mcasp_afsr = mcasp_afsx;( q) ]) m; p" d% A& Z4 R4 u% q
assign mcasp_aclkr = mcasp_aclkx;4 T1 h5 L' Q' i8 \' T2 c( c% m
assign mcasp_ahclkr = mcasp_ahclkx;
9 k- N2 q8 Y" Sassign axr1 = axr0; , @1 K& h {1 K2 p+ b/ y9 u
. F7 |% u7 t n7 g9 b# ], p" u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 Z! P+ K( b7 l" I$ ~
static void McASPI2SConfigure(void)
. U# B3 z7 _$ s- }{
0 r6 h( N& g2 u* B* u- O' JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) S5 F$ J4 z; z$ YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! j) p; g9 m5 r KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 I {7 B# b( S6 D- s! @1 ?! EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, p4 L; j& Q& q+ [* y q6 T/ }4 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- v1 l2 p# P2 B& \* ^; j! `
MCASP_RX_MODE_DMA);
( b$ Z- V% L0 t8 u& ]; r) ?# o7 Z5 OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% V H# v5 J* B, n7 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) I7 c, O" ]' r! h4 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: G& I- Y b2 A/ R, n* }2 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 o6 \5 G+ ^. {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' Q( [6 R# o7 W& y1 ] DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) Q" X5 L2 |5 e& F) M# I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 X( T! f) o) v4 ^, iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 I% ]" Y8 B7 W ^" t; ^* @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: o! D5 Y4 F7 M. C- z
0x00, 0xFF); /* configure the clock for transmitter */
. b5 x4 R& g9 b8 u! v# s9 kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 T# ]" G m' t- M/ i0 x, C# G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ M6 m9 L0 O2 H A9 ] AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ \! _8 J+ y) I1 F! W+ g1 _
0x00, 0xFF);; ]2 _ g) ~. k J% a& g
' W" X, v& |; C1 Z0 s* R/* Enable synchronization of RX and TX sections */ 5 o* I' \5 M8 L# H9 G$ T" X6 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 s! a5 ]) A5 r4 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# A% z% U# D% v8 D) NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- @% v# H) ]2 v7 M. @** Set the serializers, Currently only one serializer is set as, F+ V& t" n0 F: ^2 G5 `
** transmitter and one serializer as receiver.
e T: d* s, c*/1 K) l) ^3 A. ~$ X% X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 d6 |* t0 s$ d' l2 B- @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: \0 y$ N! T7 j6 Q5 s1 V7 K
** Configure the McASP pins
& D- A8 f3 J6 |; d** Input - Frame Sync, Clock and Serializer Rx
" r4 H; J Q" Y5 L; S3 B** Output - Serializer Tx is connected to the input of the codec 3 V9 k# k- l8 a, A
*/* |8 L5 [/ A3 b0 S T/ Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( ^ c" I3 F. H' o/ p% f/ [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; a, {6 F9 ~- `5 p* x0 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( m; K% q7 N; E2 ?| MCASP_PIN_ACLKX2 p" z, Y+ W& E5 o5 t# v2 E
| MCASP_PIN_AHCLKX l" @# X) c4 B2 g P/ K; l( K7 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" t7 u. o: M" S, sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: b# M+ P* X1 _| MCASP_TX_CLKFAIL
2 d) U) l' c. x8 t8 P5 x| MCASP_TX_SYNCERROR
+ I" t6 |* b1 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! Y m* \# P9 {% r8 ^
| MCASP_RX_CLKFAIL
6 r$ |2 ~* x! t& p| MCASP_RX_SYNCERROR 8 X e' s) d2 d0 ~* l
| MCASP_RX_OVERRUN);
1 w" J" V, X) N$ r% Q} static void I2SDataTxRxActivate(void)
3 ?3 {9 G5 j! _{& `2 z' p. Y5 S( x" m1 B
/* Start the clocks */& i. @9 s1 n# l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 g9 i q0 V& g; H5 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. h! G( Z8 R& x! k2 t9 t" v- t9 I5 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# c F" Z Q: ]; p
EDMA3_TRIG_MODE_EVENT);) Z3 Q( l8 ~" W7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - Z3 ]& [$ f1 L7 P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ N% ]& k2 i& |: s) b2 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* }1 j; W9 d/ T& v6 Z( V' \' I3 ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; i7 t1 s- c% x! X% Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* |' D9 j: `8 `% d! l( p% ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! M+ ^2 h; Q7 Q, @1 q5 yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' p; J* `7 C% c |/ u4 O; ^; q i
}
" L4 `* n a' T/ G& a! G9 c, I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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