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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ D4 h4 H+ w. ^* Q* y% J* {6 s! X
input mcasp_ahclkx,
! @; Y* W, G2 A4 N: j6 k" Hinput mcasp_aclkx,4 O* M/ |9 u- U8 d/ i% ~
input axr0,
9 e# r8 ~. P# |! \
5 }' [- F8 x. |! Z/ n) Woutput mcasp_afsr,
5 T1 W/ W0 A* m2 a! g; boutput mcasp_ahclkr,, U1 x% n8 a$ ~0 Z, v" o# v
output mcasp_aclkr,
$ S1 C# r' k- z& G% P; P2 O# E8 B. toutput axr1,
6 r8 Z J( E- W assign mcasp_afsr = mcasp_afsx;) }* s1 O/ N6 x2 [1 d0 V9 p
assign mcasp_aclkr = mcasp_aclkx;
Q. |& B$ J5 p1 f% ^assign mcasp_ahclkr = mcasp_ahclkx;
: a/ w* |. [( h2 ]. ? sassign axr1 = axr0;
1 S3 K& Z7 N3 ^0 v' ?: d' s
/ w' O( W, W$ z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) O# Z9 y# p$ k* zstatic void McASPI2SConfigure(void)
- [+ c) E* z) e{
9 h) P, [0 |! C. j3 B8 EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 |2 g% Z5 f" {% G7 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ e+ m' c# K6 a. n1 _4 s- SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# z' r Z& B& _: _6 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ l) w% \% Q: _4 h1 v: vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ `7 G* s3 h+ l: q0 g, K/ [0 FMCASP_RX_MODE_DMA);
- } }" }( r0 W6 B" p% E5 g( xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 Y- P8 R" y V r% Q2 J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( J) D! Q( U) o9 S. ], LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) ]; s( P+ L, I$ u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 }8 m7 ?. H c5 ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 n: P" G$ }9 z' [2 o% [( {0 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( p7 Z0 Z5 W8 k7 C4 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; q) I( [ m @# ?7 K0 T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : ^+ c# ?5 d: \# v; `6 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' }; r& H2 B: R+ ^) e: b2 M
0x00, 0xFF); /* configure the clock for transmitter */
- k+ \9 G* t N# vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& ^1 K5 S6 z i2 W- ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 m _1 d( V0 j! {% f/ LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& [. G( M: h' _" b# T/ {
0x00, 0xFF);
( b* c0 I4 f# y( x9 S1 X9 f: C: O: o+ p( u; p2 H# }
/* Enable synchronization of RX and TX sections */
5 t' B# z2 o$ C2 U9 p, D6 Z# \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
x! k* K" |! h2 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 m2 H9 `: w) }/ ~+ OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: o. A* q6 _& g: d1 Q
** Set the serializers, Currently only one serializer is set as$ \, s }( p# m. ~1 a( A
** transmitter and one serializer as receiver.
- e) z* E f* c( |2 G! q) y: B*/
' P1 [- s+ F4 `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, S6 ~0 u* Q% N; U( L' t& [) |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ^3 P/ a( L7 _0 `( [6 A" ^. I** Configure the McASP pins
2 S+ F# Z0 X6 |6 e- X** Input - Frame Sync, Clock and Serializer Rx; F( G& v5 g4 H; z! t3 z) R# [5 [
** Output - Serializer Tx is connected to the input of the codec 7 I% Y" E. W" j! d3 j3 K) V& Q/ i; ? x
*/+ K; P7 N% z+ ]6 T6 ?6 z3 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& Y5 Q5 a& q+ |- VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 g9 h* V) Y( ]% M4 a1 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 v) f1 r- H* b- E; q+ f
| MCASP_PIN_ACLKX
% v9 O; b% P6 Y: {7 [' N/ v: ^/ _$ E| MCASP_PIN_AHCLKX* l1 q" h- L8 @6 @9 P3 r/ o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// g2 b7 ]! d2 P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& b, Q, c7 C) B3 |2 [: [| MCASP_TX_CLKFAIL
9 o9 d* }7 n& i# {. U# V: m| MCASP_TX_SYNCERROR
1 n z/ w: L- Z- Z5 O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 z% l4 E* G, d+ R# G2 Q
| MCASP_RX_CLKFAIL
' D( u9 y) H% C5 _$ z$ b9 b6 T| MCASP_RX_SYNCERROR
+ S; u0 k: B& w+ ?& Y$ ^! g| MCASP_RX_OVERRUN);
6 `, A7 o$ p8 I {} static void I2SDataTxRxActivate(void)
* H, b9 a. B& W2 t' t2 O# M" J{
0 R6 f% @: m& t: ~& b/ g- T. k: ?/* Start the clocks */: \+ f$ ?- V' _0 x1 P" u% @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 {0 q# g) Y1 o8 q7 I, a2 z0 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 m2 m! G+ ~$ V; `7 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 H' `7 {$ L; E0 d
EDMA3_TRIG_MODE_EVENT);
: R0 G$ s* [2 d3 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 Q4 H" q8 g$ [4 R, J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// M( L2 j8 {* [+ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! O/ i) X1 @4 b7 y9 c8 g( ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 {' A9 {3 t$ |" Q1 }2 ^: z. K% S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: p" z, s0 P( ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! }( T; ~) x4 L2 ~/ v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: l" S% C0 n7 {( o, i
} $ }: S, O' r# b9 I9 \# d* x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 w, d9 T+ l) ]. i
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