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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- p: b5 o% v, e& m) A/ L* R) p3 n8 N3 _$ w
input mcasp_ahclkx,
6 Q0 m$ S2 o+ D& X* einput mcasp_aclkx,0 u, R9 z2 R) ^) A
input axr0,& u! W0 d+ `" k/ Z$ G
: z, ?' f; v# N" I+ poutput mcasp_afsr,) U" }8 a. Y/ J' Z& Q/ n
output mcasp_ahclkr," q4 D* S0 G& M' E$ p3 t$ \7 ?! `2 d
output mcasp_aclkr,0 O( R7 e2 L) I
output axr1,2 s4 C |/ x- N) E' _( Q( N; b% m
assign mcasp_afsr = mcasp_afsx;& _5 C: P! X2 P6 {6 Y* J/ ^
assign mcasp_aclkr = mcasp_aclkx;
' X& e( `3 a2 }% ?. v& ?( Sassign mcasp_ahclkr = mcasp_ahclkx;
: @! L7 P8 M3 U8 E- W k {assign axr1 = axr0;
2 s/ I% V/ _: G7 H @2 F2 w6 i" ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 H2 H- e+ K/ t
static void McASPI2SConfigure(void)0 H) U$ ~8 F, K: n0 R
{
& A2 q q- q, A, Z u# D; LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 K& \9 a( ?5 b+ z9 u) H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" r4 `# U) t; L( }1 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 u# J+ l* @+ I: H1 l, cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 Y1 i k: H2 r2 b% @) lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 B( R: E/ c1 }+ y$ UMCASP_RX_MODE_DMA);
" I6 _) a. ]% I; yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ Y5 [; u: [0 m# \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 @; v. K* N( j1 w `! q5 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 e& x9 q, `- [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" O" t1 T4 e* i) C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 N) j1 y0 U9 i- UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( R$ n, w/ |& k( Y& a; |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 _. _! N B7 {7 A4 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / y3 D# b# C: o: G7 R# Y3 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" U/ q a7 K) y9 |. m0x00, 0xFF); /* configure the clock for transmitter */
7 a+ n6 w) Y3 I" K2 S! rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ q1 _: |" x& PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + `5 n1 u( I! M S4 r% \# s% i- ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ K Z) l9 T- P- n0 x4 o& ?0x00, 0xFF);( _, v$ I) l& v |* Z+ r O
% V1 Z+ R, f- Z7 Q/ ] h+ X
/* Enable synchronization of RX and TX sections */
6 q) |+ ~4 I9 W& \8 |; zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 T. o* B5 Y: U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( q# ]" F9 ?) ]" b0 J* s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 w8 {) V8 H# z& R( M
** Set the serializers, Currently only one serializer is set as
. }" K5 U# J: _8 P** transmitter and one serializer as receiver.8 W* b! m! W% {/ m& C+ {0 O$ H
*/% f7 }" S% V7 q @' x# z5 _" j- T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 `+ @$ G8 U7 v2 J# r) {4 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 M% Q7 @$ m: w9 N. C2 L** Configure the McASP pins / E* n6 N4 `( b# Y6 N5 k! Y0 S- |7 s# L
** Input - Frame Sync, Clock and Serializer Rx
, }- |$ \ N) U& t$ P" Z** Output - Serializer Tx is connected to the input of the codec 3 N* }5 x$ i" A6 ^5 D# T' O
*/
: P+ z' v: q+ G! k. ^/ M3 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ S1 q, K, F" ~: s# U! ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% Z( `3 u% ?; \4 C0 Z, X; eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ E a$ L; p; v. g. x% _| MCASP_PIN_ACLKX
2 u- i+ i. y# D. ?6 _| MCASP_PIN_AHCLKX$ }: J2 e2 H' G+ t* X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 d$ P: D. k: j, aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / t( q7 b, a) V4 q* n
| MCASP_TX_CLKFAIL $ P) b- O, Q5 b) r; n9 l
| MCASP_TX_SYNCERROR! B0 Y& g: s% V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! }8 ?0 N! M% p% _| MCASP_RX_CLKFAIL' t8 T, w W0 k/ D6 A4 X
| MCASP_RX_SYNCERROR
; ^- y M# p2 y# ~5 u+ |5 v0 w| MCASP_RX_OVERRUN);
5 f* Q0 @, T7 D- a! `} static void I2SDataTxRxActivate(void)
M' i, u2 G7 ?( g4 @{
" n! a) N9 ?9 _ A$ I% ]3 g. i/* Start the clocks */
; s# m/ I9 l5 C( UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: z$ K3 P- Y0 h( n- V, L. q+ EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 o: d8 X' i- T1 J& Z" j) l! w( eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ W7 A6 r; p) P7 b& z4 x: P" AEDMA3_TRIG_MODE_EVENT);. ?* w# ^+ t( {' ?5 p* q) P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # I; z+ L% t! F( \5 T0 v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, `$ }: q; H: F! i9 j7 t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: A4 N. i: {; g0 L6 q% p4 e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% r$ w3 B- o" j: Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! k# Z) w1 ?& Y1 k! R/ r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ j. W6 ~9 T N4 i( E6 j3 [ z7 w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 f- i% ]8 _1 ?" g: M} * H9 a3 [: q, V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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