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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( h$ t# u) m2 q. [! L1 uinput mcasp_ahclkx, v3 u+ D( G; k) J) i" t- q
input mcasp_aclkx,
. N8 G9 x5 f0 }; L1 |% K1 Z; Minput axr0,
8 k0 k' K0 |, G: n) V' q
- _- C' x0 C2 `output mcasp_afsr,
& V/ f( f8 O8 a: aoutput mcasp_ahclkr,6 X, ], k, y9 s/ H4 I+ O$ v
output mcasp_aclkr,' A# s {! G$ i. c
output axr1,. m# j# J( K6 v1 R# d8 S
assign mcasp_afsr = mcasp_afsx;+ K2 ^3 x d: x, \4 ?- d& n+ w8 P
assign mcasp_aclkr = mcasp_aclkx;
, u; U0 T% z$ M2 H, K1 A% |; aassign mcasp_ahclkr = mcasp_ahclkx;
$ c* r6 t4 \4 {5 n# T' Xassign axr1 = axr0; * {9 y3 b q' y# G1 [# d
$ ?* u, w- {3 U( z* y1 d' z' D1 G4 F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# A y3 m1 Y" Nstatic void McASPI2SConfigure(void)
# D/ p r7 d u& P# ^{
7 L# n7 V3 z! @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: O E5 D; K5 r' j& d2 c8 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 c) L7 m, Y3 E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 X7 N2 Z* Z: i; v+ W2 nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 Z: r* H+ J- C7 O0 f+ P0 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# O/ `* \( \1 M& a) C
MCASP_RX_MODE_DMA);' i' ?6 `* q; f- H+ K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 W( M/ k& t9 s% J. b3 dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- g2 y" N+ C3 Q: M* DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 f; W5 d9 p5 R+ h5 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% `, W& i: L8 V7 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 K+ R" v! F' ^* b+ i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" u, J" w: a8 _" K' s% m# w8 t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- O' _: Z6 N( @, P6 P- }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
~+ L4 o; W; }+ X1 `2 j6 ^6 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 c' j: N. t6 i3 G
0x00, 0xFF); /* configure the clock for transmitter */9 g3 L0 j2 T. r1 e3 g) u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 N5 H2 y# M$ i7 J6 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- ~3 k( ^0 f: i# w; P1 C8 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, R( A6 ]) B4 O% o4 e
0x00, 0xFF);
?& r/ @; x8 e5 A; M0 y, y% e) S" h |6 H" g' X5 |, o
/* Enable synchronization of RX and TX sections */
7 v. V: [4 z H$ W6 s9 W. `& H; ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( {# `6 T V y- H6 |) G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, F& B8 ]6 ?) J8 _4 c
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) _* W; Z, K4 m6 Y: a3 _# ]% o** Set the serializers, Currently only one serializer is set as1 g: {( F$ @6 ^' s
** transmitter and one serializer as receiver.
- p- ] Z- b) {7 O, l*/
; X: c( t* O! F' o7 MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 Y' }0 c+ c, X. `9 ~+ f1 @& LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- W% Y. y6 ]$ E R" u5 v, B, g** Configure the McASP pins ! C; V Y ~0 {
** Input - Frame Sync, Clock and Serializer Rx
$ ~1 A1 r2 \% z5 ~% u b4 [9 k** Output - Serializer Tx is connected to the input of the codec 9 T( V+ P7 m0 ^1 M( I! h( S
*/
& [3 u7 }! H- [( x, k. v O& E( SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 {! H3 S, N' M6 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) I2 `/ c9 v5 g9 N; d( YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ Y2 z5 H; ?( }# z& C5 |( p' u
| MCASP_PIN_ACLKX7 B, @' B" C# a$ S/ G- B* A
| MCASP_PIN_AHCLKX9 k! J6 M- @$ Z p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 c1 b. s4 F3 r# T4 o. ?& q% e3 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 Q( q3 J9 \9 U+ h
| MCASP_TX_CLKFAIL
% V) }* Z1 @) u% i, R| MCASP_TX_SYNCERROR
+ D5 c8 u5 J# V& N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ Q5 x. f0 t; F7 N4 g
| MCASP_RX_CLKFAIL8 c/ [! i! e/ N9 u* F
| MCASP_RX_SYNCERROR
6 ]1 I) Z2 f( |2 y" `2 C7 \$ ~| MCASP_RX_OVERRUN);) r b7 W4 U) Y, ?0 |
} static void I2SDataTxRxActivate(void)
# R! d( a* m) k{" n4 a# o/ t1 q, u6 L
/* Start the clocks */' |# a/ Y, B2 l/ M0 I, A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 Z3 ^! T$ E& c- i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* c* C9 U( s a9 \- R' KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 a) N/ A4 `! O; X/ \' cEDMA3_TRIG_MODE_EVENT); a; w# w: ]- W' o" ?, M1 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( x5 v u3 M( o1 R% a2 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* K) d7 F; e- RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ t0 v) F" A% D$ p, Y" Z; ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, e7 r/ s) Y! @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% c" O! K2 w9 k, g0 x( k# x0 \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
V. [* u" \, _& G8 MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- d2 ~/ O# M% `9 v* C2 R} ) E* X6 A* c& R3 g$ d9 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 {; p) p6 C; _5 C' A, O( Y" B. H
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