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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! A) F0 i7 S& Z9 {input mcasp_ahclkx,
) X: G( G! o$ ?+ ~$ \: U- {" D6 Kinput mcasp_aclkx,
4 ~8 E4 V) W$ {, B! j5 winput axr0,8 t1 c: b! C, Y' w1 s
+ M/ V4 v/ l' e
output mcasp_afsr,
2 K8 ~- m* V* p' f3 p5 Ooutput mcasp_ahclkr,
: c' b+ ?$ B3 Soutput mcasp_aclkr,1 j8 K6 K5 O" U% y! N- U
output axr1,! A4 b, [7 x$ L# E# M* b
assign mcasp_afsr = mcasp_afsx;! J" F5 ~* g2 q
assign mcasp_aclkr = mcasp_aclkx;
- c7 y, I3 x/ t) u- kassign mcasp_ahclkr = mcasp_ahclkx;% v. E+ t$ o! ^' n& ]7 t* t1 P
assign axr1 = axr0;
) `8 J4 f0 f- _( X' S
# n9 J: S% k8 P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( o7 n) W; x; y' ]* Q8 e7 w1 ~static void McASPI2SConfigure(void)
) p0 p" }+ _8 K# E{
: |' ~$ h9 e3 a' bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ H2 Q5 L2 \$ x( ~- Y+ U H1 p& v# Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 h& @! { N* ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ p* y9 ?4 y! N9 K2 Y0 w) VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# I3 [" ~% F* IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- ]* d) ~2 e4 x7 t
MCASP_RX_MODE_DMA);; c* z! e1 ~, j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 d/ w% [* _5 k [! R( [6 P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 u3 c: I2 z) [! l2 e, C4 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 i% w& W1 S. zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( x, L; G! E; c' sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - ^2 f, T, h7 C2 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 R7 V' ^4 y9 o, s+ |, u; p+ @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 q! z$ Z. m- B' |, O, m+ F, f& T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' c+ G, a( A* z, l7 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* v3 p9 H' d2 ]. h. o8 N0x00, 0xFF); /* configure the clock for transmitter */3 B' U. Z5 G0 \5 i: ]
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 Y1 q e* { E3 [ V, [& TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - h4 F- Z& g5 T/ Z' y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ q8 y7 y' _9 g0 t0x00, 0xFF);
; ^; P* j" `* x1 u
- B& b6 K" |& ^3 J$ P' D/* Enable synchronization of RX and TX sections */
1 _& Z& N1 W9 P+ @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# H4 d* N8 u4 i5 q: |0 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% X# Y H2 s6 {0 rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 J& V) x$ c* G. ]* u
** Set the serializers, Currently only one serializer is set as
. \! S4 a+ { s9 k6 Q( l" A** transmitter and one serializer as receiver.5 N$ |7 u8 |; Z
*/
" d9 _8 @% r ~) I' OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; M9 j k8 V8 y; e: ?/ n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ H3 _! n; G/ N- L7 T N** Configure the McASP pins ' C- A6 M7 X( B7 o% E9 Y e" @
** Input - Frame Sync, Clock and Serializer Rx! \2 A6 B0 P' O/ D6 i9 h
** Output - Serializer Tx is connected to the input of the codec
# @8 M+ E) }% k: d*/7 _! n* E6 O) i7 e i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 y1 h0 S, X5 M& G9 B. r7 kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 d3 N T! H- z6 |5 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ k( g2 N; ^: ~- y
| MCASP_PIN_ACLKX9 _) b' S; L" p' o7 @. K0 G! Z
| MCASP_PIN_AHCLKX
$ `; p% _* e) q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 G% Z2 A2 j7 b6 ? mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) p+ u: v: X8 \6 @
| MCASP_TX_CLKFAIL
& M: M* c; J: T* d5 C% @1 ?0 J8 m| MCASP_TX_SYNCERROR
& B9 Z% G, n6 n' O+ d+ t4 I9 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% I3 B5 }& @' a| MCASP_RX_CLKFAIL8 U `7 N/ \2 |$ M) H
| MCASP_RX_SYNCERROR , x& w' z0 k9 a8 m3 V! V7 r" O; f
| MCASP_RX_OVERRUN);
0 f- Z- F5 q8 x5 Q1 H* h- j} static void I2SDataTxRxActivate(void)8 ]6 x d4 c' g3 ^8 b
{
7 U) i! Q9 M I- ^% P/* Start the clocks */
* g9 _% ?% u( s }( oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ g% V* b. o. D tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 g, U7 z5 t& V T% T* I+ s6 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% _" k8 T4 x) e0 f+ a H
EDMA3_TRIG_MODE_EVENT);
/ e/ ]/ D. ]# f7 t9 _- w+ a. [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
~9 o" n# Q8 W' q k$ REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( I, z: h9 I$ q m- h! [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- i& K9 n4 s6 Y7 C# V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# ^/ B+ u: U" {7 U: u2 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( z0 ~4 H0 o; _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. z( F/ }' J, R* M7 @/ QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! |6 i. u4 N5 @& H" H}
6 G1 A/ i8 M6 }& v4 m$ ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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