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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 T' C3 A& z' r, n* l2 \3 Jinput mcasp_ahclkx,; c0 \+ ]) v: r6 Y [& @ J
input mcasp_aclkx," a# @9 A# I7 D; b# s( ]
input axr0,
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/ T ?# U9 ?6 d& g* Toutput mcasp_afsr,2 z9 p2 o7 t; {' j) ~& w* g" i) a
output mcasp_ahclkr,! z( w8 l, L) n0 i1 O! @0 ^
output mcasp_aclkr,9 t6 ` U# c6 e. Y6 |
output axr1,
3 L7 n' L/ A+ I* v' A& n assign mcasp_afsr = mcasp_afsx;$ k, H6 S# n; \; R6 ]
assign mcasp_aclkr = mcasp_aclkx;& c. I; k' F$ k- Q( i: j4 @
assign mcasp_ahclkr = mcasp_ahclkx;
; ~8 i0 b: L2 G2 y5 O$ v! c, l4 T2 Vassign axr1 = axr0; F* J) u0 Q/ c! t% z! X
6 }9 q2 W1 w. ^" y0 k- o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 b: F# ?4 n/ b) N7 Jstatic void McASPI2SConfigure(void)5 I$ ^- i, w* U5 d
{
7 r4 M( o ^, I! ~. p3 a* E) vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 h" Y- i" P8 a2 O2 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 \% a% X) y( Z8 C1 K) G- g) X$ Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" V7 U% X: Y# U3 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
[" A9 }0 ~7 x- ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# p0 [$ ?8 o$ D/ v* k- C) |
MCASP_RX_MODE_DMA); ]( R3 Q$ E: o" R( r5 `- I* S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 W' [' L6 O3 o2 s$ oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& [( x6 Z9 A! O# f8 U1 e$ G4 x# \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% j1 A- u3 N$ V( G# `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( u2 M/ T1 O& z! TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# B; r- Q% C! D( }2 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" _- s; W5 l+ d2 r) x" n2 zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% A, p" v& j6 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ r: D4 ]' h; f! h% NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 l! b! |$ {0 M
0x00, 0xFF); /* configure the clock for transmitter */
) X8 r" d+ e9 wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 m; S, D4 Q/ A8 V8 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 [$ n; L% ^ p& _9 v DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 G z( h7 T, I4 J; N8 T7 {9 E0x00, 0xFF);
3 h, Y: d6 ^" F( |6 S; u- G
7 b8 e' V. a/ d/* Enable synchronization of RX and TX sections */ $ O& W+ t$ ]0 K2 o) F7 R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! D: V$ A8 p) Z( i; tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" h2 g7 Z: H& u6 N `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ p1 z9 ^0 E0 [- F) L
** Set the serializers, Currently only one serializer is set as
& s @1 Q. ^. h- Z0 M6 [** transmitter and one serializer as receiver./ ~) A8 u `( E
*/
. ? p+ s9 a5 m9 C \4 _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 g3 J% d, r9 ^, q$ n$ Z+ tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 f# R N. p( ~. H# f
** Configure the McASP pins
6 {5 |2 }5 { u8 Y) }** Input - Frame Sync, Clock and Serializer Rx
& R, R' ]4 z+ J( Y& @% h** Output - Serializer Tx is connected to the input of the codec
1 p1 V X5 O. [4 `*/
; w. b/ P6 s- aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 S0 @% E! U9 g8 l6 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 l" o. t" R9 @/ U- o' _/ M3 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! L; o% k3 I/ L' N& H V8 Y| MCASP_PIN_ACLKX
' c3 Z/ Z: ]0 ]| MCASP_PIN_AHCLKX! o/ v I- C6 F4 h( ]% o F" \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 Y' H; [2 f" VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
M. ?& q- H% k' J! H| MCASP_TX_CLKFAIL / C! |2 E% M# D ^; }
| MCASP_TX_SYNCERROR
! W( }& K- k# N0 s% U; D5 m1 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& b; q# U6 |+ F1 C| MCASP_RX_CLKFAIL
, M& n( U- ?# `6 z# |6 ^0 x| MCASP_RX_SYNCERROR
9 @' @$ Y. j& M( S| MCASP_RX_OVERRUN);0 z* N' _2 p9 R/ N# P
} static void I2SDataTxRxActivate(void)
0 h4 ] m' I( H7 g$ {1 v& {* X- [5 I{. J4 T( i, s, n
/* Start the clocks */5 H' S' s( |! z7 n' E7 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 V3 \: j6 U& b2 s0 ^% H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 v% C. s+ Y* @8 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' T7 T# E" e4 E& ?! w2 {
EDMA3_TRIG_MODE_EVENT);5 z# x" ]' ?4 i4 b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 J$ d m: b4 f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. ^3 r7 a# |! }1 _( {& B+ `# aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 o' R( p" K) `; H. @. M" s6 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 m8 D% |. Y" M Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( r7 y/ L/ D% @/ pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 D! x6 J4 g; g. M: ~' v. JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" V6 v3 q8 v4 @7 O6 ?} 6 Z* K" Z9 n# n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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