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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ I/ K) K6 u/ y+ F L7 F; ?/ K8 kinput mcasp_ahclkx,! u: M6 x0 N7 B- [: o& `3 C. u
input mcasp_aclkx,& ~5 E$ E/ W- v, [: N {; U
input axr0,
' ]! y a( ~$ S: e( Q; a" d9 a0 p( Q4 o: I
output mcasp_afsr,3 Y$ e V; y& ^4 a, ^' [% H
output mcasp_ahclkr,
) T7 `$ c9 ~. }, J6 @$ d, u3 r( moutput mcasp_aclkr,
' u3 x$ Y7 }# P6 eoutput axr1,
; X) s3 t+ U9 L3 ] assign mcasp_afsr = mcasp_afsx;
$ F6 Z' ~! `+ zassign mcasp_aclkr = mcasp_aclkx;7 }; Y3 k, I" y6 e6 w6 Z
assign mcasp_ahclkr = mcasp_ahclkx;
" Q9 V; X4 o4 e* G/ ?' b+ R* c: J yassign axr1 = axr0;
3 G6 A* |& P4 w/ _4 q v% |2 A5 y! B" j% E- d( o* t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 P$ m& f" Y7 j$ A' a: g) p9 P" ^static void McASPI2SConfigure(void)
$ k1 E" ?6 _6 Q% V5 d{7 y5 X. w: L, |) M1 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ Y' Y9 B3 R1 {" B7 v1 e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% a7 L% L/ Z S- K; S7 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 X7 c8 {, T2 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 }: F# h" b( F+ T' tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 D; N- Q' \$ y1 H4 y2 q; W9 R7 `
MCASP_RX_MODE_DMA);
: `5 F K p. bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," K% h9 z. ?9 P" O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& j- Z, o' P3 }8 F ]: \2 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ Q$ B ?4 c# R0 a: T+ J1 {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' p! _0 V5 T5 ?3 f) l7 Z) cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( A F7 q& @" a9 i, pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% O# z" P J0 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" z8 Q: I. U* X/ V0 w9 _) LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % p& \1 C% r0 f$ G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! h! x9 f& `( i1 i" L8 Y0x00, 0xFF); /* configure the clock for transmitter */& D; `8 \6 o1 {! S m4 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; Z2 k4 [: ~( t) f8 f# u: f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" ]' p+ n z# K$ u$ qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ ^) w# _0 {5 Q' S v' Z1 m+ t0x00, 0xFF);
1 X5 N! o4 u0 h4 X1 a2 U% d# B( ~
/* Enable synchronization of RX and TX sections */
# T5 X1 a' B1 Y* r ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; H2 N& N8 I, kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- r3 _, b7 B" i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, w* l C# H0 W: U** Set the serializers, Currently only one serializer is set as
8 m: C* U4 x6 t# k** transmitter and one serializer as receiver.8 J7 t1 E: f) k V" c
*/
; [; o7 m, H+ I# p. vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. X6 m% o! H0 w/ AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' B4 k$ s( p. w8 g( X+ E
** Configure the McASP pins
% M3 I0 M, J L# Z** Input - Frame Sync, Clock and Serializer Rx
4 R. i+ T' T f* z7 Z) E( A** Output - Serializer Tx is connected to the input of the codec * s6 x# P# K" ?$ _
*/
4 W* m; l8 Q" R+ q! n( BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* q' s, r9 \0 d+ J5 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 x- h$ |" L0 ^- p- V4 a. j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* E5 Z4 `6 [6 j; `0 O n
| MCASP_PIN_ACLKX
# Z- |! u9 m5 q| MCASP_PIN_AHCLKX
5 u% d1 e) o( H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) o% p8 `) u( [$ P7 o# @& y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 T' l& x" F$ e. E| MCASP_TX_CLKFAIL
6 {. }+ D6 t* H8 ~8 j, w5 s1 Y| MCASP_TX_SYNCERROR
; M G! F0 S1 y r3 f4 D8 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( G `& \5 {( h; m5 e- w$ J| MCASP_RX_CLKFAIL
, a7 e. c& P- c3 G0 C( `| MCASP_RX_SYNCERROR
8 @4 M+ m `4 ?$ Q6 ^5 \| MCASP_RX_OVERRUN);
$ M( ?: w! b% I2 B} static void I2SDataTxRxActivate(void)5 T/ P/ `7 d5 Z! G$ @. G
{1 O& w- M; b5 j2 r4 T9 Q* D/ g) g
/* Start the clocks */
1 H* X+ C) k5 J3 x7 H; oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 @6 S, }/ K# i# g+ d; b+ r0 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# o# e3 X' G: w) `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% r' ^- Y. Q& e" Y) z
EDMA3_TRIG_MODE_EVENT);
3 d- {- p* y9 G5 W. gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 s! L; v" r& ^+ |- }, w$ B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; l" @2 ] f/ W. t& q) G7 J7 h" Y; L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ e$ H% d: U( t/ R8 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! f* A& [; v3 G1 z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ c8 `$ T/ u8 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( _0 U0 N+ I0 v; t! LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: ?) U( f1 g* I$ g0 g1 ?: m} : E R% D4 \$ P0 {, ?" r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* S# u/ ~ f4 j/ {) b* R |