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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
T- e8 H) B3 C( A, Vinput mcasp_ahclkx,
/ U& E5 G" P* | [0 H. `input mcasp_aclkx,
: H& q( V. l" o I$ K2 Z5 Sinput axr0,
! b" K0 B$ `0 x+ J4 @. I! k8 j) R G$ q1 N: V
output mcasp_afsr,2 H, ^* ?0 B( a* D/ N( y
output mcasp_ahclkr,2 `+ k r. V* S8 m8 r
output mcasp_aclkr,
7 }7 O- m" C9 d( s: ?output axr1,/ C$ b1 I( [* @/ u
assign mcasp_afsr = mcasp_afsx;# V& h& `& V* v3 w0 k0 w$ A
assign mcasp_aclkr = mcasp_aclkx;9 f' _! \" |8 ^2 x4 v' B2 ]
assign mcasp_ahclkr = mcasp_ahclkx;1 e/ b4 p% i! r
assign axr1 = axr0; ; K2 @4 L# d: T) e" F8 B9 h" K
* S' |* u4 I0 O0 m ^$ x6 Y/ a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' U4 }! ~, G5 B' y' Z& ~0 dstatic void McASPI2SConfigure(void)) B$ D, e7 h; b* }; M
{" j& s, ]4 B& F1 n- F, N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ D+ Z7 P+ }7 n! lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 s! A! c: Z' N+ kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ I: x6 g2 p; ?: D" N; A2 `, B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% {0 X, ~* X/ i; |/ G' v6 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# d8 c- A6 c! w; I
MCASP_RX_MODE_DMA);
# g% p& f& }! X$ JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- Z) J& J7 E/ t6 w6 {* hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 a1 c# ?6 n3 K0 _5 QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" i4 E" d+ c3 E5 w7 |* y9 z; KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* a+ S0 v6 ~1 N3 kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; S/ |2 [+ l0 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) o- {" H. A7 D$ ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 m$ i# E: z" P$ j0 JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 R! R1 ?+ U/ V8 z& V5 K( aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; w$ C3 R" a- R5 F9 k
0x00, 0xFF); /* configure the clock for transmitter */
% | _4 G1 i( f% ~( IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); k, L9 C: l H$ u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - A5 z7 C: h/ ~8 n9 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% J4 C4 I1 K w6 @1 D
0x00, 0xFF);
" ~- v0 ~8 k t& d8 S
9 d! \" W6 \& x4 x/* Enable synchronization of RX and TX sections */
1 ]% F+ N$ l$ K3 ?# |# e/ AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 L+ U. W4 o" j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: b# b& d# d# ?+ V1 g8 R7 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! c% K3 O' o R' w9 V0 h
** Set the serializers, Currently only one serializer is set as
* H6 U7 C4 H1 x2 c+ c0 f& h" ]** transmitter and one serializer as receiver.2 @0 g2 G5 ~2 a+ @6 m# v! k
*/
5 ^- M' t& V$ a) f2 g4 @+ u9 ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! P" t; k, ~' _) o& v+ T: K# `0 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ D* }4 k& @3 ?6 f
** Configure the McASP pins
9 \5 i" }: m# ~8 t" T# i0 |5 H** Input - Frame Sync, Clock and Serializer Rx
0 W0 X; u1 d/ N- e** Output - Serializer Tx is connected to the input of the codec
$ f$ b) i8 O$ d2 X9 d, x7 Y*/
/ E; r0 b4 G6 v9 L# K9 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: @% l$ } ~' Q- n d! [4 [: H4 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); N- b. c$ F, `: ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. l8 _9 v+ |! u ^5 Z# h
| MCASP_PIN_ACLKX
0 C4 R3 [% V; C5 l| MCASP_PIN_AHCLKX, G0 D! b) [9 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// o) s S. \/ Z6 x7 |8 b- Q5 y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 ]1 C0 \, ~( ]8 T5 F/ |; [) s4 ~| MCASP_TX_CLKFAIL
, I* d" I) F" k8 H+ z9 Y1 m8 k) Y| MCASP_TX_SYNCERROR, D0 Z6 V1 I7 g2 N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ i4 U( l( P0 e& s
| MCASP_RX_CLKFAIL
$ I0 W8 x F9 b% Z| MCASP_RX_SYNCERROR
9 p. H) q' K, W* b3 l8 O3 Y| MCASP_RX_OVERRUN);
% D( e- w1 b# E9 q# B2 G+ L. u+ {} static void I2SDataTxRxActivate(void)
, u! l& K( H( w6 M9 o. y$ |{
- ?6 ^& ~5 Q X" I/* Start the clocks */$ _; H: n: a0 {6 |! V6 d( H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 u7 j- Q9 P4 }5 m: e( y( l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, ^1 C* o* F( O2 m3 ^2 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 Q5 V" o6 F3 [4 ]" }! XEDMA3_TRIG_MODE_EVENT);. \ j, u8 C2 u! E. {, i: l+ y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; o- z; ~8 h" q* Y3 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* S, n; ^! @" p2 z# X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ v. B5 L9 s' C- `7 y) NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& W+ _# `, t& v& m! _3 O7 |6 @9 ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 o1 _9 l0 @/ YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' G$ I2 N" u2 b8 t$ B( |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; x2 K. t% N' `- [" S4 F/ o( ^
}
+ |- D* G0 l1 A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 }7 u1 p% w4 _! Y- G6 v" s
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