|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# ^4 e0 ]1 s. ]& ~ D/ ?5 Uinput mcasp_ahclkx,
! U" ], l ?0 c4 W7 g: oinput mcasp_aclkx,0 v0 q8 i8 s: @/ _, y0 F$ n
input axr0,; l) z6 V& q4 ]' ~0 q
3 t% K* W' u8 ]4 w4 q" soutput mcasp_afsr,0 w/ g, C# ^( s+ N; w$ o
output mcasp_ahclkr," |2 m# A3 s) o! D) r. y# L4 n+ A
output mcasp_aclkr," C% J& d) x. f- y8 ]0 ]! U
output axr1,! i; J9 H U) {1 C, ]6 n6 O% F
assign mcasp_afsr = mcasp_afsx;; `' Q: I' U. s! R: H. f8 p5 C
assign mcasp_aclkr = mcasp_aclkx;% {+ z3 G6 T ?: L; b f
assign mcasp_ahclkr = mcasp_ahclkx;& s: Y$ A8 j1 _! v
assign axr1 = axr0;
! g* B$ r% X$ I
, n2 t+ d1 x# F! j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % h& b9 {7 F' o& n' R& u9 i
static void McASPI2SConfigure(void)* G+ N4 i0 s/ H
{* a) c& y/ J8 E4 }8 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 T( K0 I- y l! S4 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! Z/ ?4 z2 m3 ~$ r8 u" @5 wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& @: Z% x8 |+ _8 o; u$ ~( q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# A+ r8 r" l" W0 ~' r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: ~! J3 c9 ]6 a7 X3 l: `! c
MCASP_RX_MODE_DMA);
( ]. c4 V6 t2 G% A8 R6 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ v" X9 R5 u S$ T( _8 b6 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. K; p! S5 O" z( {7 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 u. Y' q2 \" ]7 _9 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& l2 j: o0 j3 u3 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & v2 U8 g7 [! M3 p) U" h; o* Q8 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* E, A/ Z! _- P' m" K( }* p4 [2 EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 @) [& |1 w' m. \. K) \6 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; h$ O7 m. x0 Z4 X3 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: J1 h0 x8 U$ q g" P) B
0x00, 0xFF); /* configure the clock for transmitter */
% i2 Y$ x( p0 n8 L# B4 XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 v7 K4 \6 q& Q5 t0 ^- L y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 ~# @4 H* U" X1 O9 S0 }& c: ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 L) E9 z4 [4 | k
0x00, 0xFF);& w' \; C/ y: O3 H
' D" q' Q3 N) {7 S' Q7 d; J& E$ S/* Enable synchronization of RX and TX sections */ 5 M- K7 D6 A8 {5 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ a* P* a: L& U' H. @. [+ z2 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- S9 Y+ }, S% A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; ~: |) |! w1 ]
** Set the serializers, Currently only one serializer is set as! k% ^7 j+ \- }: V
** transmitter and one serializer as receiver.
4 p9 r4 H- t0 v+ S% h*/
w5 k* z# m! X) B& p, ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, j7 u0 }3 }! n0 `2 w4 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" R; w) n$ I4 L4 _4 z2 ?** Configure the McASP pins * h3 j" |, P8 f2 X, H5 S( j
** Input - Frame Sync, Clock and Serializer Rx% H5 C1 C( b0 w# N1 Q) s
** Output - Serializer Tx is connected to the input of the codec ' H5 ]6 Y) j3 i$ d2 V
*/9 z/ B9 o0 @; Z m# t* W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 {" M5 h/ u8 i4 A8 L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- l- O; S0 ?2 b" ~2 wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 y4 i, m/ y8 N; P
| MCASP_PIN_ACLKX) t O/ Z) ]: M+ \# O! h) D
| MCASP_PIN_AHCLKX
, Q* G: ~, S% x7 l: A0 A# G6 n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 F4 V+ J7 W8 _: _: Z$ }: ~0 h5 w- g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 l |+ }2 u+ K7 h2 w5 v0 l6 @( C| MCASP_TX_CLKFAIL 4 K0 R' F( B, h o. d0 r
| MCASP_TX_SYNCERROR- w: e! J8 N& d W9 b! p# x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % l) k7 E/ T8 N+ q4 V* A- z9 G
| MCASP_RX_CLKFAIL
, P# b$ y2 h, |% v# T, l* Y| MCASP_RX_SYNCERROR
- i& F$ R" A: L; R K* i2 J! \4 f| MCASP_RX_OVERRUN);5 `- E) K- Y2 K. V& G
} static void I2SDataTxRxActivate(void)/ M' i% V4 @8 P$ ^
{
% A9 O& J& W# u( E& |/* Start the clocks */( Q* F- I3 m$ l q- {! R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 U) Z6 @3 f2 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 @* G1 {& L: m4 Y( lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" p" Y) N- b6 }8 J: pEDMA3_TRIG_MODE_EVENT);/ B |+ Y6 S6 v! Y# Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 o, t) S2 G( R0 s! V4 H2 Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 R5 ~3 _, G, Y, s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ m, V/ ], o0 `$ L+ jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 ]) U+ S3 T. s5 _; Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 |" g4 A! y M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# [& T: k7 \$ k9 D$ ]8 F+ u: E; AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" J" S5 W$ r9 H5 }( p}
3 n$ e% o4 h$ c1 `# v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 {3 o2 Q$ |5 x4 a1 H0 {* w1 h
|