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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
m2 U: I/ V9 |' Ninput mcasp_ahclkx,
3 V& Q+ q' d' J( `input mcasp_aclkx,
, D8 b3 P- C$ I5 O4 D4 linput axr0,' z3 L2 ]' u8 N& c* ^8 r
! p$ x V$ G4 C! f+ v/ G& W! z) E. moutput mcasp_afsr,
% w3 C' b! G+ m1 S( r: Voutput mcasp_ahclkr,
3 I; F) R7 S4 K3 t# ~+ G* ioutput mcasp_aclkr,
. B4 E8 a: i" w; ^3 w L5 soutput axr1,
# Y# }& t) O6 w7 O5 E6 [3 `7 P assign mcasp_afsr = mcasp_afsx;
3 ]% n; L: {+ N# b' O3 ]assign mcasp_aclkr = mcasp_aclkx;5 w E% h2 V6 ]# n: C' @4 I
assign mcasp_ahclkr = mcasp_ahclkx;) K4 S- ~$ ^. T- U
assign axr1 = axr0; 5 o. X4 L, J! K" z
0 V9 A7 ~+ f6 L S; N3 H/ k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. b5 o0 @0 ]8 M1 p, _! Nstatic void McASPI2SConfigure(void)2 _, G) o+ y# K
{
; ?# ~- W, ~ Z4 ^! rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 A1 w/ h2 B Q k G, h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 l7 g3 ?& b7 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 s. A$ S! F5 y, @: KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# P4 |; N4 J. l, A1 x! U5 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' K" b- h/ n4 J+ t. TMCASP_RX_MODE_DMA);
$ ~8 j5 w, f4 I: ?3 |# b; LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# I/ c. _+ \0 ~( \. d2 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; L( P/ J& Y% v) aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 @* K% y" A: y( v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& C. J' u6 |( q0 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 r/ e. L( m4 e0 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* B* n: L7 V: a/ P% Q, n: G/ N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# c7 N1 A1 Q" @9 K7 e9 S7 q) v3 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. K1 d+ a/ }- d" ]6 UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; B5 n; o9 v1 C' d/ `# E
0x00, 0xFF); /* configure the clock for transmitter */0 Y. i/ N9 r9 _/ W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( q$ g5 o! W$ |4 }6 \7 B" {4 i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; X2 ^+ |) x9 N4 S' w3 y) k* EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ {2 `5 N S7 s8 O1 M1 L
0x00, 0xFF);
. s% z1 U }6 P- h8 S4 ]
( _4 R& g) h4 b0 s3 A/* Enable synchronization of RX and TX sections */
N$ o8 Y6 h, ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* _0 Y- ^" q: n& B8 s) g& _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 h0 K8 y) G7 x+ K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ X6 A' N+ T$ y; f' w3 C( p# Z
** Set the serializers, Currently only one serializer is set as
* ?3 x0 B3 F* c) b- `- g** transmitter and one serializer as receiver.
: V; n; o( W% t- f2 F*// ]% m# M. b* z: S. g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; c% R7 d* y% }' ~$ k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 [: i! T O9 t
** Configure the McASP pins ' [+ g' n/ v/ k; W/ s
** Input - Frame Sync, Clock and Serializer Rx8 Z+ E4 G8 L H# Q# N4 a
** Output - Serializer Tx is connected to the input of the codec
# ^/ f5 A8 n* e+ n*/
, T. z: n+ S% j# ?+ W$ FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 a$ x" D" d9 D0 m0 F) \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; Q g7 {$ M! b+ s1 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 v9 y7 z$ Q7 r' \% b5 [| MCASP_PIN_ACLKX4 t( m* c. }: J: S% c
| MCASP_PIN_AHCLKX2 V; v# G* Q+ [" O! j1 c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ |% q$ \% a* [6 V X# Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " t, o0 t1 l: j4 O
| MCASP_TX_CLKFAIL 0 o6 h, V$ R$ J6 b# r
| MCASP_TX_SYNCERROR
8 R }; t2 z4 V4 @8 x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 O* s) Y& w; M+ g" O5 Q. R
| MCASP_RX_CLKFAIL
# Y5 ]3 C5 G* U- b4 P. R, q| MCASP_RX_SYNCERROR
* n- L4 w! a2 h* p- e' \7 j/ x6 n| MCASP_RX_OVERRUN);
$ O# j3 m7 x9 d2 F4 {% i} static void I2SDataTxRxActivate(void)
) u5 c1 W( y0 z5 J' y{
6 N+ m( Y( d6 Q, M+ L/* Start the clocks */) {, Q$ u: S$ ]5 k8 S0 U) q" v, X1 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 O& e1 L' ~9 x% `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' W. J* c/ h+ j2 `- J+ N8 Q7 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 A5 K. F) H1 ?1 N9 EEDMA3_TRIG_MODE_EVENT);
, `: p: `: ^" C0 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 g- w! f" D, o6 H' W) [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) q4 ]: ?2 O) O- t! f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" ?0 W0 f9 M$ W% p/ q6 {, y* nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ X+ I0 p4 E1 N5 J6 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% S! [5 |5 Y% F3 t% P$ ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' s0 x" X' Z" i! C {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 v/ ?+ P3 D. q' W
} * s& Z* O5 `" i1 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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