MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
/ d, N  U/ s1 H& y0 R2 u3 uinput mcasp_ahclkx,
+ F" L- E, j8 F# F$ Yinput mcasp_aclkx,
1 m2 @4 X  k, i8 w1 U  L* Yinput axr0,

output mcasp_afsr,
+ X8 ]; ^0 L+ l; x5 [output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
. q# M+ D: C( B5 l5 Y0 C, _

assign mcasp_afsr = mcasp_afsx;
8 `! |( p3 ^5 E( T" ^9 ~assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

8 K% Y$ o! k8 z, ~$ o
& a$ n, k& N% v$ i  Q

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
1 }" _3 |7 g( ?4 g; Y7 A$ z2 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" D# p( q: {& P1 F  T1 h9 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: v& Q- t- n8 k8 NMCASP_RX_MODE_DMA);
+ P6 e0 I( t9 IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 ]7 v8 j% ~: F: r; ?* f3 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ {! s* W  Q4 [) r1 u# [) lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 p/ [0 M0 L7 q0 {1 _$ M# cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 K! k" t! _* _' V0x00, 0xFF);

/* configure the clock for transmitter */
/ O! B# s1 b0 G. x+ M) IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ J6 X, C3 Y+ z. D0 w! T; g, c/ MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" t$ g4 ]) t* u) C6 }; M. }- \! ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. _% n, O5 H% ]) _# V, \; h/ ?0 r0x00, 0xFF);
& i" n8 I9 P: N! N. |# h- d
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
  A. G4 b8 M' Y! _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
! f7 A- l4 J$ l( [& O: X** transmitter and one serializer as receiver.
*/
  h0 F! }. k/ S0 FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ R' K3 X" h, kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
% s. l' t. ~' z/ U& ]** Configure the McASP pins
8 z- A* `) U, ?1 ^& F0 ]** Input - Frame Sync, Clock and Serializer Rx
; X0 Z/ b* g0 ^$ n** Output - Serializer Tx is connected to the input of the codec
2 G! \0 S, @0 o) K( X) d1 n2 @*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& [- T9 _" E2 }  q& JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 r! K- A" n+ u8 W  g' oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 v) }% H% o, w/ t; b8 |' w$ i; M, }8 u| MCASP_PIN_ACLKX
5 T1 v7 ]6 z' @, I, I9 D' J5 N* s| MCASP_PIN_AHCLKX
) _3 U$ L6 x4 ^* p$ |7 x9 r/ || MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
8 H6 w! N1 i8 m! L| MCASP_TX_SYNCERROR
9 P& `( f8 W% Y  p8 d) T5 E| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 X3 k' M% y; s, z7 @, ^| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
+ H8 K; N2 \) A" s9 G, F$ E| MCASP_RX_OVERRUN);
( T& _$ V2 N/ f. o- S}

static void I2SDataTxRxActivate(void)
  @( W+ L8 K5 ?# F  ~) q0 Y+ i{
3 t8 \, T& a, w& j  L: I9 S" i/* Start the clocks */
. u) I5 c- r8 v' ~+ qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) z2 u$ g+ x  J3 O) LEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
# ]# z* l( O* I! B; r1 D4 fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) e; O9 w. u, i- }! U& lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
" }1 i( {. ?7 [! Y8 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 h1 A5 w1 p( lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.