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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 y8 q. D. J8 H1 M" `" t" k
input mcasp_ahclkx,3 v! \% L* L: T% Q$ h! v$ v
input mcasp_aclkx,
" o* T# _$ @. W% Y' f3 _. Y' U4 Pinput axr0,
7 ]' a1 b v1 s+ S" |6 r, [, T, f6 f+ X0 t5 y
output mcasp_afsr,
: l8 K. N7 F3 t, q8 Koutput mcasp_ahclkr,. L3 Z2 v+ D4 w7 r% P- b5 x
output mcasp_aclkr,: w; a9 r5 I1 X* e3 F
output axr1,( z, F7 e5 V( p1 p) {' n& q# f' }6 k
assign mcasp_afsr = mcasp_afsx;9 g5 r# d( Q9 \" i6 u
assign mcasp_aclkr = mcasp_aclkx;
9 A d- r# L/ f- jassign mcasp_ahclkr = mcasp_ahclkx;$ x# Q9 ?% ?3 U @2 n& y' j1 K
assign axr1 = axr0;
$ _: w" `) o2 \8 Y: t
: @) H3 t! @1 h% [$ U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( f& |$ Y+ Z( H! B, f; |static void McASPI2SConfigure(void)) m: M+ z( S4 X3 m; K4 S
{
3 S# u" a7 S; Y2 R% a0 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ R+ N4 V- W+ D1 z/ q( o( ^8 y7 S& pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 F. Z' {; H4 ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. u4 I+ b$ |( r5 E/ vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 V3 Z' V$ _2 M! e4 d9 F0 jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ^- u+ P$ | |: `, ]
MCASP_RX_MODE_DMA);8 [+ ~' k9 W2 o5 K+ j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 w/ a8 h7 j+ q! B2 f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( B" Z6 r8 [) r6 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 t4 m/ E9 n. U; |0 e& e+ zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 O+ e3 K' a6 l3 N9 M7 d$ d3 oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) ?; e7 g/ n% o: o- A8 V; AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ a1 |) j* {5 G9 I1 b$ l% N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% ~+ Z/ L6 r- L. a7 P3 ~! ^' p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 r3 n% k- _6 F, D1 z0 ~2 KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 ]- X4 y) ?3 ^, U( t
0x00, 0xFF); /* configure the clock for transmitter */
- ], P7 W* i: R- v$ y7 ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 y. Z" M8 u7 ]* @, z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# W2 e% J. G9 y5 w" b' s! iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ S. Z3 E/ M! q5 P+ s1 l$ i2 k* |0x00, 0xFF);
; X& c- q) c, L/ g- p
# f; q' u( C4 P7 P/* Enable synchronization of RX and TX sections */
# Q2 I( b' S2 A# K4 W) K; u# hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 t+ R6 ^8 `8 m* a2 v; @4 O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# c# ^9 w% b! K0 @( Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ f. v f% l5 _** Set the serializers, Currently only one serializer is set as
h) _% S& O5 [ Z** transmitter and one serializer as receiver.
* `! U7 g. g# H4 r& c/ l; k*/1 `# T/ @; G1 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 E" \4 U) _- M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 t+ v3 b0 E2 b- ^9 E** Configure the McASP pins 8 W8 e& J7 q% }$ d' x0 S
** Input - Frame Sync, Clock and Serializer Rx+ z* g+ r4 `- Y2 V+ t6 f
** Output - Serializer Tx is connected to the input of the codec ! q3 k' E$ v' ~" _
*/
1 ~# S5 x4 D5 A g1 o0 w1 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 G5 C, I( @8 W3 h) OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- C# h, L; F+ |+ ]' I, x$ FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* r. T0 \' y3 @& m7 G8 H+ |
| MCASP_PIN_ACLKX1 Q8 ]) V& M" W$ _# N$ w$ A2 x
| MCASP_PIN_AHCLKX
7 d' ~4 w2 s) O2 Q" y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 }, Z! _8 o3 M$ a& p$ S% R- s* v; O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; p3 A# K0 D4 a- X; W3 S) H
| MCASP_TX_CLKFAIL 9 _/ K$ H) Y# A% F8 B0 ]& V% U
| MCASP_TX_SYNCERROR S3 t* L8 U. V5 f, X* q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 _% l% b) u# [2 t& r# k& l* C) x
| MCASP_RX_CLKFAIL3 D- u& w: B- o2 M2 u. W! V( j2 L
| MCASP_RX_SYNCERROR 0 b9 P+ u- S7 {4 V7 C
| MCASP_RX_OVERRUN);7 C* k- ?+ g4 q, ^: {! ]! g
} static void I2SDataTxRxActivate(void)! ^: R% E8 P+ ] J
{% L3 ^5 T; d& }7 A0 S* z5 k. F
/* Start the clocks */
# Y) j; M; u( s& |) Z" kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 ]3 ?; q' k7 n# B3 K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
P9 o+ d! _0 w. S3 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, }! O% e1 m N7 C2 A& A# s- {& `
EDMA3_TRIG_MODE_EVENT);
/ q4 m6 X. ]2 N3 d$ O; c8 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 R5 P! {7 w+ ^) m) u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& |4 k( m# @$ o8 o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 [: t; E: u0 o: H. }& u" n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 B/ a0 d R) ~) vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 _6 G( |! ?1 m' h3 ?% `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( d' a3 L* z% |3 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 R! I$ o- C+ }5 K/ t9 E- A
} : u6 i- d' y% t$ z% k! u- b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
! _4 L! _% ~& {5 `8 F+ k1 w |