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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- d- ]6 e( r3 _* r. Winput mcasp_ahclkx,
, k% r2 ]$ t+ W; F. p0 ginput mcasp_aclkx,
' U5 M. f; ]: h1 ?input axr0,
7 J, a* K: x B E8 }/ A
5 u) p5 k! [" w7 j, f( foutput mcasp_afsr,
0 G# v# U$ @! Y- }. W% x" houtput mcasp_ahclkr,: }7 C% f: P6 I$ X% h
output mcasp_aclkr,% J* r+ b6 \! a, R$ [* x2 d
output axr1,
( r9 `7 W% q& u+ I3 r2 d! u assign mcasp_afsr = mcasp_afsx;
! n- s: ?: D: ~+ m3 x3 ^assign mcasp_aclkr = mcasp_aclkx;
) X& W* s. W7 p: l, P/ h/ zassign mcasp_ahclkr = mcasp_ahclkx;, R' a4 F7 {" p! ] h1 i1 _' O
assign axr1 = axr0;
( ]% i2 C+ [1 t
# u- N: [: q( I) d2 _" D! n2 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . t( r( `6 F( ?: e
static void McASPI2SConfigure(void)% B. G3 P1 p$ P9 R
{: V6 @4 D# g5 \4 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- K, p8 ? o9 RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: u0 S; v2 H5 I0 @) p' K# A# jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 d- S) C( X) e3 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! s5 e' ~) _/ c3 U0 y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 S3 o/ G( u& B" `MCASP_RX_MODE_DMA);
; I% ]% L9 a2 v {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 V+ V6 E6 _& }4 o+ o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 z% X+ U" w- N8 @6 c/ K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! z2 {5 v. j& G" ?% F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# W( j3 D6 n+ Q8 mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 n# U" }6 y: M! v( e) A. J4 y8 zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# ~5 ]& u) A2 f+ j; h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ U/ b- d2 b6 P5 ]9 b' k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * {5 Q. D8 y( ?$ I- b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' ?6 q1 L! e: W, q6 [+ ~0x00, 0xFF); /* configure the clock for transmitter */
4 `2 n: j$ u% G9 W0 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 O1 m6 Y9 K; Y3 ^7 m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& L- _4 {+ A+ c( q! xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* m* J: f& I# G0x00, 0xFF); g. T6 I' H3 Z, Q* j( p$ }
2 E- r: ~* r! C5 [/ A
/* Enable synchronization of RX and TX sections */ " z; z% c& n8 N5 }% k9 P: \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! m4 K1 V; y3 P! U& w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 c3 I* r, i5 D: x' Z( q1 U/ Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 w/ o8 x- g, C/ e% k I* r** Set the serializers, Currently only one serializer is set as7 F% K! L& r# ^ E# S' }7 ~4 {
** transmitter and one serializer as receiver.
6 x4 z, G1 h+ }+ S1 Y n0 j*/$ Q O- w6 O4 E d1 \& d D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: c: v M, Q' w7 {8 X5 z5 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' ?. C7 T% D: e) R' h- u
** Configure the McASP pins
* S+ J5 o5 b P** Input - Frame Sync, Clock and Serializer Rx, z, Q' R% B9 I k% y8 g8 M: P$ V
** Output - Serializer Tx is connected to the input of the codec 9 y# _; N3 v$ \$ |6 g/ C$ u
*/
% A N: _9 l4 @5 L& i+ H5 dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 a" U" K5 u, F9 c: [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) S. e+ `: a5 B6 }: a8 `1 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- x0 f& v8 g8 N Y; f| MCASP_PIN_ACLKX
* F& Q* ]1 W/ G5 Y/ w% V i| MCASP_PIN_AHCLKX
& s+ Z$ e- ]( _$ h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 _" L; t( [3 R/ GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 G( z- X. R+ t% [1 G" p: g& G& K" T
| MCASP_TX_CLKFAIL 1 P, o3 c, U4 F( u2 h! T' k6 T8 Z
| MCASP_TX_SYNCERROR6 Y# W, R q, c4 a2 u2 [! z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 e5 D1 K; ?1 N& {" | C
| MCASP_RX_CLKFAIL
2 S* q E: ]. v| MCASP_RX_SYNCERROR
3 M* s! U8 U9 K| MCASP_RX_OVERRUN);+ [- A" x' Q( z' L+ X
} static void I2SDataTxRxActivate(void)
" F4 e( C( x, F1 w{5 |$ }2 q8 f6 g( e; T4 y7 B. Q) k
/* Start the clocks */
$ x ]9 c! j1 E! S! ]# M7 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; ~, [' W; P- z: ~7 j( ~4 D+ j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# i, m9 u* a3 e% O' z, M2 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% Z3 a' N* M3 U# D. r) n; Y
EDMA3_TRIG_MODE_EVENT);- @" o. N# Z) l7 `. y4 O4 w% N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 u# d( [. `, D3 G( Q* U8 _5 sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 s& }( v5 o6 M9 ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" Y# ~ w! }- a0 X1 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 ~% F/ u/ E" G/ _* k0 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! x+ e; w0 d f. T7 o( Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 A( C% C+ m p9 o7 ?0 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 a/ w3 Y) I6 Q: \/ R}
9 l" E, `5 c+ M/ K) O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , \% f- M; V% G7 [+ |
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