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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 {" x b' s% V3 a8 R! uinput mcasp_ahclkx,
0 E( m( d2 @8 m9 T9 A5 d o: zinput mcasp_aclkx,; `1 C8 @. t! E) k( |
input axr0,* F6 Q, ~! M7 P2 ~! B- J, U. Q
" }' e: L% ~9 i, ~output mcasp_afsr,$ i8 @, `0 i7 b
output mcasp_ahclkr,- P1 |! S7 v* ]% c. V7 `
output mcasp_aclkr,3 j4 s3 c+ W! w8 ^$ g9 B
output axr1,3 x Q% o* x. y1 @
assign mcasp_afsr = mcasp_afsx;) f+ c0 \1 U n8 M% X* |
assign mcasp_aclkr = mcasp_aclkx;
/ @! X9 J; o6 @. r2 a0 @; M) bassign mcasp_ahclkr = mcasp_ahclkx;
3 J! l! Z) P# T$ g+ Q* q* e7 \assign axr1 = axr0; 9 T3 V/ [8 V J
" Z# I) c3 ?4 G" Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
@" ^4 a% Z: C. z# o: \. w$ V) Bstatic void McASPI2SConfigure(void)
" V+ C- E2 T8 a4 y3 I- h{' P: ~( W. F) j9 J6 \" A( e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ z0 i. w6 z, E( j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 _! E5 t& x4 v$ GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& ?0 k/ @( m e: s% H/ nMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// ~( K- V! {) w5 g" E4 m. d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- f0 y( [6 W+ PMCASP_RX_MODE_DMA);0 ]9 _8 J0 t7 u4 x) ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- G0 n/ |0 f& d: ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ^1 G! j) |/ D; D8 s( |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! C! V, \% Z9 G7 }1 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ~3 ^) C& h! Z; m; W0 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 u2 Q& h; d% A1 h, V$ R& R2 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& N2 q5 t+ i+ A# d1 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); _, Y1 _) ~7 w1 @# ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. x! ]% a6 @0 FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# R7 `. T4 T8 N) c B
0x00, 0xFF); /* configure the clock for transmitter */
0 c: z( U U I( s1 bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: O2 }5 Z) H( V8 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + u$ O! R4 ?) o" S y$ b! V1 X3 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! @" E5 A4 ]( p- s/ F0x00, 0xFF);( U' _9 ]/ b. O) W
7 o; Y4 z& o- A# H/* Enable synchronization of RX and TX sections */
4 c- y) C' P5 p* |6 J) PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" B+ o' G, \* w- X6 [7 U5 ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; K; g$ a5 Y( k& v$ h3 C; ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" K- ] Q3 Z7 f0 H
** Set the serializers, Currently only one serializer is set as- w b$ c- _, b" c! D; k4 z% p
** transmitter and one serializer as receiver.( m9 c A! a9 t2 f9 _( A
*/4 I- R( C$ U; ^6 f$ k& O- ^& {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- s3 W% q) \3 O" l1 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- f. S3 w7 Z3 c0 _9 [; Y3 h** Configure the McASP pins
, E. [; x K5 M** Input - Frame Sync, Clock and Serializer Rx/ o b/ g( q8 Q6 A# m% w
** Output - Serializer Tx is connected to the input of the codec
# I) Q% ~% [+ e6 G0 h( _*/, Q K( @) l: r7 p" n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& |; X" V. x; T! YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 i4 N7 t5 q2 I W4 ^3 \! h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( J1 L1 B& u0 [2 H( ^| MCASP_PIN_ACLKX, L% A5 [0 e. p! w3 z# V5 s6 ~- }5 g
| MCASP_PIN_AHCLKX
4 L. O) n6 _! K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 z8 g7 P! ^1 `, X9 h; p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 A( \1 U# B' E
| MCASP_TX_CLKFAIL
% @5 i" R$ N! U' a| MCASP_TX_SYNCERROR' r' {7 `5 V' ]# r
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 r' N7 g) R$ o z2 z, a f
| MCASP_RX_CLKFAIL ]" m' [3 L1 C
| MCASP_RX_SYNCERROR
/ K. i0 u: ?3 J d3 h8 n# F" y| MCASP_RX_OVERRUN);
& X0 h' ]* E+ L7 [5 F} static void I2SDataTxRxActivate(void)
6 x" r5 {& B0 |3 N, C{+ I/ T9 p/ ]( A% v/ Z! ?2 Q
/* Start the clocks */
8 A8 T; B; y) T$ ]6 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ Z! p* @7 Y, yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" g) E |" o7 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- a: H# G5 L* I# l, ]# E3 {% ?EDMA3_TRIG_MODE_EVENT);0 N+ E! X+ ]" D( o% }8 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 O3 ?8 F0 T2 @; f, }, x. Q* P4 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 D8 u% y5 g. p* H0 K; P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. g: R1 J: k7 v- ~+ c. t7 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 i7 V/ D: B+ E8 l: U: G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, Y6 W0 e. c$ a% _$ l8 N/ f. nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. v' O( O/ [$ w& p7 b# o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 Q, ]) [" ^6 Q( D} + S6 D6 |5 i5 `2 t. |0 G/ ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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