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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 z3 j" C: E; `" D5 _input mcasp_ahclkx,$ ^# G3 J4 `, U% I1 @* Z3 Z2 _3 b) O
input mcasp_aclkx,
3 h2 q- v* t7 V3 w) h$ ~) Q% Zinput axr0,# Z% j1 r5 P* \5 T5 b% _' W: n7 H6 z
+ n- Z/ V8 n0 y/ Moutput mcasp_afsr,4 Z5 r, z7 }7 H& T! w9 W; @
output mcasp_ahclkr,: K5 h( s* k% ]
output mcasp_aclkr,5 o% C; i( `" U1 Q" a4 Y8 u
output axr1,) {; Q( C" c6 b$ k7 A# ?
assign mcasp_afsr = mcasp_afsx;2 O4 `6 z) n7 T$ p- b$ |$ }
assign mcasp_aclkr = mcasp_aclkx;! x; s4 E* `) D
assign mcasp_ahclkr = mcasp_ahclkx;
+ E" H/ X; m( H1 E2 x4 m0 t: cassign axr1 = axr0; 4 W0 h& ?2 i6 L
8 m' z6 `4 H" E) ~9 \' {3 S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 M% }) g( l" P; p9 h4 @8 U- X$ t
static void McASPI2SConfigure(void)
4 s' e7 J& F' H+ v! N$ B0 X{
* {& K+ I7 |, AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. e% @; q7 ? I0 t0 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. R8 d8 L( h3 ?/ tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( I$ d. L& F& e7 N; q3 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) F, Q4 B6 E: e& r6 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; D" F% y$ b4 Q1 T7 MMCASP_RX_MODE_DMA);# C; g* v5 I8 v6 z% o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 z' m& l! d! M5 H- J& u) c* Z, Y' V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: U% B0 ^* \ m, `6 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 P2 z. F* p& ^. F' s8 o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) z1 e- ^* V+ Q b7 T- G8 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 q" K: r3 R# `) fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ]# e) Z# C$ y& uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 c) f) A) F: G" m( W3 p* B& l6 P- z$ O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) l/ k+ A# |. m( V8 k' s7 V/ ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! i. `- Q6 R1 e2 ~" U4 W2 ~
0x00, 0xFF); /* configure the clock for transmitter */: b8 x0 f# V3 o% L$ B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: ^4 m) V) u: a4 o1 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " h/ g9 g; R. I+ l+ m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 o! w# I+ n8 ?5 f: Q" E/ n
0x00, 0xFF);/ a* \9 s4 n2 Y+ o
0 G6 x' p( `& `$ v: J/* Enable synchronization of RX and TX sections */ ) i4 t* a3 c9 r% c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: ~! u4 i% K K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 n; v: w4 Q- s8 V) J G6 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 j9 d: ]: A" j+ ?" Y7 R
** Set the serializers, Currently only one serializer is set as
- ^8 w+ C) q W. U** transmitter and one serializer as receiver.
& u& i6 A3 I& e& j: ^: w& w4 P! }4 e. Q*/( o- F% G8 }3 ~* |- U2 T# e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! W2 X9 G: h( p- g' A. L+ sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! L, F) u" ?- B% F1 M( |
** Configure the McASP pins
! o, x0 e) A% W5 E** Input - Frame Sync, Clock and Serializer Rx. g! w/ _! G# P5 f
** Output - Serializer Tx is connected to the input of the codec
2 O' T0 B0 @3 i, B# a$ {*/
& W9 S3 ~1 }% L: ~: OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* P6 c! y, b+ {6 z+ e9 |7 f- }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 C( Y6 [$ k% [' T% |$ |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 c5 e" K* ]) M- l. d# C3 c# }* N, || MCASP_PIN_ACLKX
# e6 S% q4 I/ y9 \* c- s% j3 g| MCASP_PIN_AHCLKX
, l k5 x: D- k3 {. D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& [8 p4 {, P7 U O. ^- SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 i7 {9 r1 N0 C- `| MCASP_TX_CLKFAIL
% _ I3 |2 U1 H" A5 S: V: n0 m| MCASP_TX_SYNCERROR$ Z2 Y% a! ]3 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) l8 d* y$ x5 n; _2 g' g
| MCASP_RX_CLKFAIL# v! z. |6 n0 c* _
| MCASP_RX_SYNCERROR
H# `; C5 F- \0 W* G! j! e/ z0 Y' w( w| MCASP_RX_OVERRUN);
1 O' z# m2 x2 W; P/ P! ]} static void I2SDataTxRxActivate(void)
- Z; r' M7 o, C6 w+ D2 \# v( C6 M/ o7 s4 @{; `# e) {& V0 B
/* Start the clocks */
0 A8 M1 ]& f$ u4 R' W2 pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- K, C6 o! Z2 ^5 u; s1 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 j" s) C0 _/ C; ` | K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- |" y8 j( R. C2 p
EDMA3_TRIG_MODE_EVENT);
( k/ O% @. q- YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " |3 [7 |; ~ E4 a7 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 F9 X7 @/ r( h+ J$ L* |9 S9 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 h& _5 p- N! z6 w7 P9 H8 D) g/ CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. v$ P7 Q) j+ T0 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: U p# q7 L8 v0 J0 \5 ]$ w4 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 b( X9 k! s4 v( l& I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. w" X r' T, X- d h
}
$ ~2 l" w" {2 z$ g# c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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