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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 c# [2 z: F8 i% C8 c
input mcasp_ahclkx,
# @1 U" W" i0 Q+ _( A5 p- `input mcasp_aclkx," S$ g4 G/ S6 H; u% i( b' r
input axr0,/ R3 s% U% v% N6 d/ c
. S; H" G* C! y; v$ g- coutput mcasp_afsr,# S/ S- W4 G& j" g' w, c
output mcasp_ahclkr,
6 `0 s! y2 A1 t) F6 g1 e4 soutput mcasp_aclkr,
0 K; ~" y! H {$ }! b2 ] Goutput axr1,
! k* R2 N* J, s- { assign mcasp_afsr = mcasp_afsx;5 w3 a- ~" a4 ~* T! _
assign mcasp_aclkr = mcasp_aclkx;
* _& q/ ]7 o- D0 A1 C2 B" zassign mcasp_ahclkr = mcasp_ahclkx;4 L4 c' ~+ i% e/ f5 ?, q- K
assign axr1 = axr0;
/ M5 d0 t2 d* E' @: M" o' o7 o
7 H! w# P# F, [& O; c- H* V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ k8 f6 v P& {4 tstatic void McASPI2SConfigure(void)! q1 w$ Y( ~5 c0 |/ T
{1 w/ ]& C+ h0 M2 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 ?/ u" [; Q& a# H$ G, M/ \2 DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 Q3 `' S3 a8 Q/ i8 E. M8 mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* a+ o9 U/ o4 y0 d$ H" \- @7 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 |0 S; [: }7 z9 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; Y3 [% {: c. m) L& M t
MCASP_RX_MODE_DMA);
* J. [* P( ^) ^3 YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" ~% e% \1 j5 ^8 c# dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 i! P6 R g; Q t1 Q& d! }9 v' _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 x1 s+ K+ C7 \/ h8 J, r1 AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ I( d- _/ D" w* Z# _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , q, H, G& @3 C# z5 J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 W, u! m* n, q/ ~6 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" [- L8 f/ Q5 p% _. t4 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ X6 B6 p# x7 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 h6 H! g& ^ K* [& |3 F
0x00, 0xFF); /* configure the clock for transmitter */; |( g, m8 d- K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# R4 Z6 x0 I9 G: W5 r1 w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & M W+ C8 p( L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: u. I; p2 i. H ]) L- ?0x00, 0xFF);
: N% V* f' [$ f9 D
s2 b/ O( r. h$ |$ L, l/* Enable synchronization of RX and TX sections */
9 c5 O' L. N; w4 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" z4 n! S: z& T$ n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( H. c5 }/ H6 e a7 A4 sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% {. A) ~0 K: a2 ?+ Y** Set the serializers, Currently only one serializer is set as* Z- X+ \' ?2 B+ \/ J
** transmitter and one serializer as receiver.
6 f0 y. f9 Z9 s1 O* o8 m*/& m6 V* I1 P* c" f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 x% B9 w5 F8 E) J+ Q/ F# PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* l& a) U5 i. ]6 b7 q** Configure the McASP pins
2 U2 A2 i; K4 V3 F5 p2 L( j! i** Input - Frame Sync, Clock and Serializer Rx6 ]. m$ p9 U; W; D" O' Z4 t5 K
** Output - Serializer Tx is connected to the input of the codec 6 Z6 [1 A% e: B7 h8 `- g4 \
*/
3 `" R/ u. s! a4 Z; C9 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" w# r' w: v: [! a$ a: ]. _; ? }4 N* {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 _/ M/ X/ z. P6 t4 s( ^' F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( p0 [5 A- Z7 l; ~
| MCASP_PIN_ACLKX* }5 k$ I; h M6 s! o# d/ ?) ~
| MCASP_PIN_AHCLKX
W% M3 k& T1 ^6 s! K' W' a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 D" A2 S4 p8 E! aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 |8 j0 w) H$ h1 S- x1 s
| MCASP_TX_CLKFAIL , }+ I) B7 |3 H
| MCASP_TX_SYNCERROR- p% P( [" y8 u# I9 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( {; E" B7 R G: y$ v9 j
| MCASP_RX_CLKFAIL
: i" o* W5 u! W6 e, j/ A0 S4 m| MCASP_RX_SYNCERROR
3 G9 ?1 x# [) ?/ ~- B| MCASP_RX_OVERRUN);! d* s7 Q) r6 I7 q8 H* o# @2 C
} static void I2SDataTxRxActivate(void)
. d0 x4 M7 b# u# c! a{. @5 C$ |/ H7 Q2 F
/* Start the clocks */. D: F7 I/ r9 b7 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 x1 f& j- R" l& b1 p2 fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' @6 G4 l+ a% U/ B4 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; j! R5 s- i* K) @; r. r6 iEDMA3_TRIG_MODE_EVENT);$ N' ^2 O. r" r* Y. C$ h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 l" o+ F: s6 T* } OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
^: U6 Q1 e7 `, B+ nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& ?: Z( G6 c; U7 f) `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 [6 @, M- F6 Y7 J+ \5 l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; W. o" v! W/ l" V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 n$ {$ H0 P; D! f- B) j6 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; _0 I# ]' V" W. @! X7 f9 P} + h3 _* V- g) o: @! N- a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 z/ H2 z2 K4 J; C$ z7 H
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