MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
/ ?; K1 U/ o* D; n9 Cinput mcasp_ahclkx,
, X; D0 [" E+ U1 E& C# A1 Oinput mcasp_aclkx,
input axr0,
# ?9 N, U! k" J. n" |' U2 a$ O4 |  H
output mcasp_afsr,
# _* y" I* H. P1 `$ v: Boutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
) Y; n% g; s# e. F

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

" i; N1 U* v  H) [) o7 H/ M3 Q% A
& _4 K% g" Z' i  @" B0 S

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
! l& b. j0 v5 |! M9 N6 B1 e{
* B& o" \; L  _8 G" {0 {, xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' @  y4 `8 F1 o# q" T+ u, ]" FMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
% n& B, G" G3 L: n% |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  a- h9 ~* V6 F6 O* mMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 T* O4 v1 V5 r  x+ @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
9 q: x$ v* r3 S% c! U9 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
2 R3 S  j3 @, X4 {. q- x: B
/* Enable synchronization of RX and TX sections */
9 v2 B8 N  d, E3 Q4 B  n: ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; X9 X. h* `9 i7 o. ]$ N( t) RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
+ H: E' o; M$ Y) u3 ]$ L** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
  W. p( U* T5 M, Z8 G*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
+ g4 G6 m# I! K** Configure the McASP pins
  p  j2 x5 [  t: p) `$ s** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
4 ^5 e' h3 ?# RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, E2 x9 x+ X) v" h3 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
4 q! @" L& y  d! d| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
7 d4 E6 \1 Y) Z8 r8 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 a4 h, o6 q$ L| MCASP_TX_CLKFAIL
. v/ {  @/ P% ]+ g% [- j| MCASP_TX_SYNCERROR
0 R3 u  O' s6 b, e$ [6 K% `+ {4 T0 H| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
5 r4 _+ t! ^8 K) l, `- Z{
/* Start the clocks */
; X$ ]) S5 y7 X% O( |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 h: ^" o2 w- E2 ?& _: r" K7 fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
  `4 w. O9 E) L  n( TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
) H5 l& ^2 I$ ^3 f& B7 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' ~$ t: e- D3 r" o& SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
* z( W( e! i- }! R) F- fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( d/ _' j% [! d0 U8 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
' r) q5 {, y5 ]! i" e$ Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
. I3 I9 }  E4 P# V; j+ {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 y6 Q/ a- a$ d3 d9 n1 f6 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

2 G! a/ p7 I' `" c; r7 f