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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! Y0 g9 p0 e* C* j& |6 x" U+ m
input mcasp_ahclkx,6 I% i$ |& j; O4 A. B; j
input mcasp_aclkx,* r' g* @5 k L5 w0 @0 e
input axr0,
* H) V6 ~( j" b; ?: [. G
6 C& f3 A) k0 b1 Joutput mcasp_afsr,
& k6 a2 Z+ {* q: Loutput mcasp_ahclkr,
: |( h' f/ e8 {output mcasp_aclkr,: v. v2 n; \. ]7 c9 c
output axr1,6 w+ g, J7 l# I) u
assign mcasp_afsr = mcasp_afsx;
0 Q* g: e2 Q; Q% P! A1 m6 Dassign mcasp_aclkr = mcasp_aclkx;
+ V: L+ K$ f" w6 h/ a/ eassign mcasp_ahclkr = mcasp_ahclkx;2 E* J; | |7 p8 M
assign axr1 = axr0;
& O5 c- J, m6 C/ M9 V$ j f, H& t- ]- T' x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" @0 _# m* \' M1 o. pstatic void McASPI2SConfigure(void)# }* _9 M8 A1 |9 H7 K
{
/ U" `) P4 }" a& C7 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- I* n# w1 M( B# {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! }3 `) I! o3 v) G) L7 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; X. G* M. k3 u5 M- F y5 C4 S3 S( L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ` Y5 E* M' f* jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 }5 @& S2 Z- L
MCASP_RX_MODE_DMA);6 T& a& a2 b! d6 t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
F3 Q5 \ x1 C& I ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; G" m) X% _) ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ^3 `* V% t/ N2 U& t& o% bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ i, N( H7 v" d8 e$ |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : m, D8 a9 X' { |5 E& l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: ? Y) F9 n. z2 t$ s2 r3 y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% g/ u) s7 ~% g4 f) ~7 C+ f3 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 d* T+ I6 z( F O1 W, J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 p8 ]) P2 O7 F$ d1 |5 k; A0x00, 0xFF); /* configure the clock for transmitter */
2 L+ H7 O6 W7 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ X; B4 l @% d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& F2 b0 J7 p: K7 A7 A1 d. n) r% K. ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ s& `2 a' x* u: ]% g: M* ?% P0 e% F
0x00, 0xFF);' Q7 Z1 ~* X. n, X: V& l% y; }+ R
/ w& W/ B U8 E, ]6 U \/* Enable synchronization of RX and TX sections */
& ?1 `! d( {2 T# |& YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( X& k4 M1 I5 k6 ^& LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* T( Z) g4 w$ @+ w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 {% a# E; m# A3 O** Set the serializers, Currently only one serializer is set as
3 k7 z7 z. T! v0 d** transmitter and one serializer as receiver.+ `" t9 Z* p5 f4 b, }9 S3 D
*/
- N! d' m' @' z* g% \$ V" {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; |" c: d4 m/ l. b5 ?/ qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 n. G+ g6 A, D4 J7 `- O# n9 E: e** Configure the McASP pins z3 j3 C! c% \. M! c) ~
** Input - Frame Sync, Clock and Serializer Rx
% n/ y5 |( P- L) a( S( L** Output - Serializer Tx is connected to the input of the codec
0 K7 O f' M, F$ _" G$ J*/ P* \; X6 a, ^4 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# n4 ]! M1 l( u( ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 i) k+ l, w- m# u% V0 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; V, R) ^* a( `5 J| MCASP_PIN_ACLKX+ u9 H. a4 Q* g
| MCASP_PIN_AHCLKX/ @5 w" a, K. r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ L4 x0 A9 }6 j6 D6 o0 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 c' m- K5 U4 ]* w' }
| MCASP_TX_CLKFAIL
, Z: H1 [3 A# j, x8 b, q) E9 M4 o| MCASP_TX_SYNCERROR
$ b& o# Y2 k0 K' f- b+ o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % p% {2 ]+ f0 P9 n1 F( c$ r4 S
| MCASP_RX_CLKFAIL9 q8 c& T4 z3 ], V& \/ E
| MCASP_RX_SYNCERROR * n/ n1 e. _6 J9 m& y
| MCASP_RX_OVERRUN);
# E6 V$ ? {0 V2 ]} static void I2SDataTxRxActivate(void)0 c m7 B9 |% g9 t3 e( |
{
& |( r2 D" S3 H; d9 O# |+ F1 V: [/* Start the clocks */
3 l; k! M" b+ Q; Z9 \! b& p! @; mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 Y1 p# x% h5 j; g% F l$ ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' F( z" |' V- i( P0 R4 \ l' _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. Q) O& K' a/ R1 ]9 H" e! C
EDMA3_TRIG_MODE_EVENT);
! n( k6 Q k0 W! R' |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ` b& u" v4 J9 s3 X, p u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 ^7 y4 h, O4 s6 @4 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 Z. K1 ?+ V& M5 E/ X: J- ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. I# h; d: K9 P% d% Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ o+ H% A6 J+ {$ J3 g' MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( p# A; @: t" g2 Q qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ W4 q3 {3 a7 u: ?} 1 h4 t& B" P6 e/ Y4 N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % q- `5 \- Z( e" \- |
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