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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, T' o7 Y! D' q0 d, P5 ~8 ninput mcasp_ahclkx,
7 _ B& _ L* v2 z$ qinput mcasp_aclkx,, n$ }2 C4 a" u( D( Z O, d" N. k
input axr0,
+ q; a2 v7 ~! G4 \
, D7 ~- D7 s' O! xoutput mcasp_afsr," N$ ^9 D+ b- ?0 x6 v! `
output mcasp_ahclkr,9 ~9 ]5 u$ {8 d: e' I# _
output mcasp_aclkr,) r2 J2 N: S0 a s0 a8 u
output axr1,
/ q4 z* i3 W6 h5 m' t9 P assign mcasp_afsr = mcasp_afsx;+ q: I2 k! n* H9 T: y7 U
assign mcasp_aclkr = mcasp_aclkx;
0 E! }5 V9 l! c! E6 e3 Wassign mcasp_ahclkr = mcasp_ahclkx;0 F5 Z0 e2 C2 j/ N. M/ U! q7 T
assign axr1 = axr0;
) z, Y. H3 s" \' t, Z' i; V; h5 F! Y. r; y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 W! R" r, k4 e
static void McASPI2SConfigure(void)5 m+ w1 A/ {1 c8 U8 I4 F8 G* Y, N
{) c' b" L; p; Y0 m$ ^! Z+ C( `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 O- p" e" k! ~: m" {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% K; O- E1 |. H6 lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; u* q$ z$ f: J" z6 lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" |/ n# e3 g- e' A! b J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" v; j9 P1 q9 \0 E5 n7 B; XMCASP_RX_MODE_DMA);
6 G) X; w' ~& Z+ a, k! U, NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B) t0 e* x: t: e( |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& T5 @7 o- ?5 w6 ]- E2 y( l. lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' D8 X& O1 s, c+ m9 {5 h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ v0 x. n1 l9 ~$ g/ S7 Z8 q' N, f: R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 i! U' w2 X- b$ X& ~5 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 ?4 c- A7 b9 y' {, [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. `: D, T2 K$ J7 ^# r" s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# `0 @: P( [4 }. x, nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) ^+ K. u! l5 k) u( h8 F
0x00, 0xFF); /* configure the clock for transmitter */5 k# A2 \" \% z8 |( [* _% k/ z7 z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ Y. R' E; D( ?4 z8 @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 K* r# q5 I( b8 kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 o, A6 i x1 L9 H
0x00, 0xFF);
8 O% Q+ x2 S2 u+ Q% A- V( P _! Q; h: g, ]/ w7 ^+ B
/* Enable synchronization of RX and TX sections */ 5 b( ?' m8 j4 q$ D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. |' {- B" b2 m' }7 DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 }% J4 o; r% X! TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# K9 f; a+ I( k
** Set the serializers, Currently only one serializer is set as% J, P% U% S# m: ^8 W: Z
** transmitter and one serializer as receiver.# B& I% O3 b7 E4 H) E$ V
*// f! O* O: C* R5 V: D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 k9 s# Y9 n0 [/ Y6 h" ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 ~5 v# {0 X* T2 y: A+ l# j# J. S, A9 ~, f** Configure the McASP pins
0 J5 F, B2 E1 q+ s** Input - Frame Sync, Clock and Serializer Rx
9 n6 L Z4 m8 Y/ \; M0 J** Output - Serializer Tx is connected to the input of the codec
4 c# I9 c/ l/ ?*/
8 q; c4 k5 A# G& PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 ^9 A8 S! ]+ [6 Y3 r" \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ }9 s+ l0 d% W4 O; a) D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: }( @. H4 o) L4 ?) I, f| MCASP_PIN_ACLKX( k; U3 ]: g/ g4 J1 T$ p5 [* H& h- U
| MCASP_PIN_AHCLKX
?$ B+ G. ~7 a" }3 E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( J! b( H+ m v+ ^# x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 v, [, a& t, M( |& K| MCASP_TX_CLKFAIL : Q. O' [, `0 n6 W
| MCASP_TX_SYNCERROR% |" s9 |5 a9 Y* Q8 _3 ?1 d7 t, f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 c$ u' D0 T& {; y$ m| MCASP_RX_CLKFAIL1 m; x- e& h" U) p6 [& o
| MCASP_RX_SYNCERROR
B, l6 S' r- [' c| MCASP_RX_OVERRUN);0 y1 d* Q' v g* g6 L" l
} static void I2SDataTxRxActivate(void)
P. J3 T! U$ d" t" j& x! V{
# ]( b' I9 N9 Y) _$ [/* Start the clocks */$ d, ~' i* |0 ~0 D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, k& x2 t: R! o$ r z7 J& _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 r" z8 O, B( n2 A: L# [/ wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& J; d" o7 `# d: B" O% T
EDMA3_TRIG_MODE_EVENT);
" R' O; |0 N* T3 j/ MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 Y0 ^8 h4 {) k. F! [- _' B- `6 I* ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- T1 g O1 i8 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 a0 L4 f7 d$ S8 M$ p7 _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( _) y D. J/ S, h: |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 _7 a7 p( j# L; ^/ M r- b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
I8 x: @: v2 I5 FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. U# c( g2 @, ]; r# L* v+ X}
8 ?8 y0 J# p4 M, g$ u: ?( d$ G, i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ]: L3 h) g0 M$ x: r6 `2 L
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