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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# i% n1 e' \ v9 u/ Y2 C% N3 p& L5 b
input mcasp_ahclkx,
+ j- ^# j; H$ g: Y$ ~/ ^input mcasp_aclkx,
% }! f. Y, e9 O# X, L2 ainput axr0,
: A( N5 Q E( M. }$ u- L: L
3 |; z' {) s4 a$ P2 joutput mcasp_afsr,2 B. }% M& B0 N) q
output mcasp_ahclkr,; V5 J* A6 r5 Q8 l
output mcasp_aclkr,: N4 Y g0 [0 e3 a! e+ u* I
output axr1,5 \; ?/ U4 I" P7 E9 P) X
assign mcasp_afsr = mcasp_afsx;- `1 p( F0 H0 W
assign mcasp_aclkr = mcasp_aclkx;
$ p" x; B2 @0 rassign mcasp_ahclkr = mcasp_ahclkx;
" }0 j H; X; D$ bassign axr1 = axr0; 4 r. ?# R+ D1 s# _+ R+ M
% R+ I4 d; x' j/ X1 t6 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 H; Y3 x3 M$ q/ h/ Q4 Ystatic void McASPI2SConfigure(void)
; g8 u7 {& z6 k9 P{
; i' V, n2 ?. X& \7 T8 |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% ^) _& t9 J; G4 N( S$ T2 v$ [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. E6 `: s3 G" V% t/ MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, Y$ J T8 d4 D: L( v9 ~8 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 j I$ {+ b! O4 R2 R( I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 A. V+ q1 }& k0 S9 S) D( dMCASP_RX_MODE_DMA);7 H. r2 _) r5 C# }6 v- T0 Y% X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' q% j- z' l! g: JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. t+ @- q1 [* T& gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / W+ X" ]9 p/ S( J6 ~5 r$ Z4 }. s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. s( [7 A- m8 @ L: }* F+ v* ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' g) k- x1 V/ Z2 n1 q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ A3 t& l, V( P! F0 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 v3 U. O- r$ L3 Y+ ?- {+ t: e& m5 u) QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! J0 G7 h! Q M7 [- Z/ H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. \# g' v! [: O# a
0x00, 0xFF); /* configure the clock for transmitter */, s7 c# E! ?$ A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) O6 ^& u0 m8 h- O/ J8 @. C4 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : U1 d9 J* m* T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 g4 a% v7 _% v( p
0x00, 0xFF);0 w# \5 b# n# r+ ?
/ u, A+ k- W9 W: z
/* Enable synchronization of RX and TX sections */ , p% n8 l4 j% e% a$ Q5 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ ^; ~4 L1 n1 u6 f% f8 ~) ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) A: q5 ]9 `' J; w5 L' m5 y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 `5 }- v, n8 S1 h8 \ B** Set the serializers, Currently only one serializer is set as
5 X" ?, [5 }5 u3 |' O3 p** transmitter and one serializer as receiver.) F* V7 M- ^7 q4 C5 v! ~0 d6 H( y ^
*/+ E: X- ~' y$ ~" i# Y0 @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 F2 B; a: Q, @# v" Q! W& V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ |( C7 Q6 d; E: d6 v** Configure the McASP pins 6 U$ v1 x. D/ y4 |
** Input - Frame Sync, Clock and Serializer Rx. F4 Q+ D& V% k
** Output - Serializer Tx is connected to the input of the codec & a. z: B( U; I! O
*/
* r! ~# d# A wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. I R+ s" e, l0 ~$ _- D' w# p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 G: Z3 x s% L* PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, r m' c/ o- O9 |
| MCASP_PIN_ACLKX( F6 s$ y, q& `8 X
| MCASP_PIN_AHCLKX' B- Z8 ] A+ X" b8 H5 k8 Q( g% p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' `5 L3 ^1 G) f& }, v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! B0 V9 ^- ]% K( n' u- b, H
| MCASP_TX_CLKFAIL
4 R$ u; e" l: [| MCASP_TX_SYNCERROR! i5 T9 i5 i4 f8 {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 @( j* i L' P5 c. ^5 M* {8 z" K2 E| MCASP_RX_CLKFAIL
, v" {8 v9 M/ C| MCASP_RX_SYNCERROR & I Z2 Z$ Z1 M9 f' `6 ?* o7 j+ a
| MCASP_RX_OVERRUN);
* u. `5 B/ V: Z; F' I6 j3 N' L} static void I2SDataTxRxActivate(void)' g" N- i! P* N6 }2 O
{4 Y# I3 O$ D2 x
/* Start the clocks */
( e0 x) ^3 |) V0 t. kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- T9 u( |4 K: O: [6 c, G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 H7 F- |# u( U6 E/ _6 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 O, R: Y/ }' U7 ~* DEDMA3_TRIG_MODE_EVENT);; r& `- K4 ], ^7 ]% a# x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 L; u$ {$ _* lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& f+ o! S% T- P% Y; V! x# _+ HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ i' G3 P. c% ^, E+ cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' [% v; ?. y* iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 _" O1 p& j. l/ V6 `5 d: hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* V n/ m, c: K! H. B& X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 p N8 O6 `; f6 O; l( ^}
u6 [( J. k2 ]# _* @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. o- i; k4 b/ O# B/ X& a
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