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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 H! W' R# D& dinput mcasp_ahclkx,
3 O$ |8 h+ h; i4 ]input mcasp_aclkx,
. h( u# c4 I* u& v# |6 ]4 U3 R0 Iinput axr0,8 k0 m# |- u0 b: V
1 A5 q7 e V( qoutput mcasp_afsr,
4 G% T0 d$ G+ L, xoutput mcasp_ahclkr,, W6 X j1 h& v2 x9 m
output mcasp_aclkr,2 |* X& G, D, d9 P" \
output axr1,
6 [6 E6 U p4 J- X2 b0 B5 q assign mcasp_afsr = mcasp_afsx;, Q, o$ T# R5 j
assign mcasp_aclkr = mcasp_aclkx;3 F! T7 K' e8 f% w+ T( W7 d
assign mcasp_ahclkr = mcasp_ahclkx;/ a' Q( A3 C7 k% d
assign axr1 = axr0;
/ A7 b$ l( U' q+ A/ @( K% `% G2 g, b: S+ F8 j# t9 |/ X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& J T: y3 M! n' Gstatic void McASPI2SConfigure(void)
/ f- _+ q" H2 ?" U+ N! Q{
! p1 K' g) B# W1 L; G( nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- T/ \2 i" \1 Q' p# NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- w/ [/ A) _) k( ?* j8 b( ]" ]; @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 S7 |9 }$ i8 n6 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 a) F; g/ R: qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* y) m5 R/ {( {; a$ eMCASP_RX_MODE_DMA);8 i0 S. ~& |% A1 ]) w/ A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- E9 e8 u6 L, j, @# \7 s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 s$ k! ]% n7 u4 C8 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- M( H9 J- {! S N9 e) iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# B- u4 ]/ d$ s" Z4 \0 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 S- Z3 @" A3 ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ `+ g( p8 A- ?$ q& A& C% }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 [) Z4 [/ a2 L/ R NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 l5 ^) u9 w q! B! `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. y- {! C3 l; \- k9 B
0x00, 0xFF); /* configure the clock for transmitter */
* _* p" T0 \3 p+ w7 F: _& qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: S5 A& w q2 a5 Q; d8 _: h# RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + A4 O: ]+ G f* B3 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; J V' k$ R' a% q& n- U) Q0x00, 0xFF);3 }; K! }5 U6 D
0 \4 ~! |1 N8 F2 m( R3 j' ]
/* Enable synchronization of RX and TX sections */ - q4 L6 |( v9 Q: N3 I! n, W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" Y, |6 w. V2 I. e/ L5 N, b% ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% z2 h7 K4 s) s: \, k1 Q4 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* |; C, E1 ]8 A P6 Q8 P1 q
** Set the serializers, Currently only one serializer is set as
- k( l! E4 p$ ^** transmitter and one serializer as receiver.
" d+ j8 u/ G/ G7 B% T" D) P*/
2 H3 J! H. o4 N0 g" n3 D" b2 GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) B" d$ i! f* d/ x g5 h# K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** X7 K. z% [* D4 x* |" }
** Configure the McASP pins 5 d2 p& ^ S/ ? a, P
** Input - Frame Sync, Clock and Serializer Rx, f2 ~( K8 ]% `) m' d
** Output - Serializer Tx is connected to the input of the codec
9 i' p/ C; ~5 Y2 f w3 A*/8 X4 J9 [: J4 w0 M: m6 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 t3 G2 G3 q2 f5 G+ AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
g/ O7 x2 x# u# ~1 jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# y; B1 i0 H9 T/ @| MCASP_PIN_ACLKX. ]7 r& r1 E: W& q. I% ^
| MCASP_PIN_AHCLKX
+ G: w/ X$ X% ~3 E; }2 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 _2 E1 W: E- U: s( r$ `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 c% ~7 j0 \/ J/ j& w
| MCASP_TX_CLKFAIL
( R: Z9 U4 r7 t' X. Q$ e- h| MCASP_TX_SYNCERROR
& u, E, _: `0 w; R. o7 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' h# b: [2 q- j( c l0 S* b8 c3 J| MCASP_RX_CLKFAIL
- L) V0 C4 A* Z+ t3 ^. N7 d| MCASP_RX_SYNCERROR
+ y2 V9 C2 U$ B* r5 C || MCASP_RX_OVERRUN);1 T; e) T, \3 G) {2 l. \6 u# X. h
} static void I2SDataTxRxActivate(void)1 J8 I+ l! l. G6 \
{
# o( C% P, M0 m4 s$ H1 ?' X3 f/* Start the clocks */* y% O, Y# i- j) i5 a/ I) Y, G6 }: z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" J% z& w5 Y. V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ x% _( ?) G e3 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ q2 Q" R# W+ `8 N/ ?1 p& @* ]EDMA3_TRIG_MODE_EVENT);
7 [/ ~+ _3 B8 B# O% O! v, OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 B# X1 e) Q3 n+ }8 M5 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' u' _2 q0 f2 b. I( U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 D6 f p$ x3 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) Y. T; c T# b+ `: s) _, c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 |3 h: b9 a! E" m+ N: b$ W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 k0 w h! k( ?6 O/ pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 G1 E+ [8 I. H8 |
}
0 G8 l6 b( ~5 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " d K8 Z( O, H: p
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