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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
J8 o/ d/ [: Uinput mcasp_ahclkx,
- c( G# V r7 a- g+ v2 cinput mcasp_aclkx,
5 y5 v3 z2 K% U u: minput axr0,
8 W5 m! P9 z, C+ C3 V0 J# y+ \" p1 t9 X/ i
output mcasp_afsr,
- I' m; X6 y6 ^4 S. }* goutput mcasp_ahclkr,
0 Z5 N: L* y; I6 ^, N" b( `output mcasp_aclkr,
1 b( a' B1 ~( L. K5 ^ \# ~output axr1,) D- t4 x b( I6 Z
assign mcasp_afsr = mcasp_afsx;
M/ l# v+ U' E1 yassign mcasp_aclkr = mcasp_aclkx;
- T% s, q1 q: n7 R( d$ C/ v6 Kassign mcasp_ahclkr = mcasp_ahclkx;' p* t* S% m7 V/ O
assign axr1 = axr0; G4 r* ~0 F; D- c
2 |+ f; J, \ y9 M3 z% l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* j, P% x# y' W5 j5 M. Astatic void McASPI2SConfigure(void)1 D# l, ?- d6 a2 h9 f- e7 E. N0 i
{
) K2 Q' n8 ^" F( gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 o- v) p3 a: u- a3 E/ `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 }0 E+ \1 O G6 m. sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: o+ M. X" f Y8 C& @* [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 a, [, f) L4 M3 p8 ]1 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) u! q+ S6 C. U) {( M" @MCASP_RX_MODE_DMA);8 [2 R8 u1 z9 w1 w" c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 G# C. I4 [% Y% `, c1 X) R! H& Q- w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# }0 X X0 N7 W% r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! n6 v' c) D. M/ ?* P6 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! R6 B* I& [, g4 AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% c! e# u* B9 V2 ]! BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 I% P- Q( a5 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 u& Q8 p: s( CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ C* L% F" O1 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: b, @4 U( p$ S' [) S. {/ o0x00, 0xFF); /* configure the clock for transmitter */
3 V% n# K3 m0 WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 x- h6 A4 |) S- u# e( g* ?: GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; E0 }7 K+ ?* N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) o' I8 F# G s v
0x00, 0xFF);' }+ v! q& q e$ w
( V O& Z, S% r/* Enable synchronization of RX and TX sections */
( h/ f2 S$ s" J! j' v/ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* d4 m$ i# b1 Q! q% G0 m+ K: y6 ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 n3 S+ N$ v2 G1 m, e* e; x5 Z! _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( l+ t* ]5 _5 s& ~" S( k! D, f
** Set the serializers, Currently only one serializer is set as* ~$ J$ m7 s* S3 l8 n
** transmitter and one serializer as receiver.
, T- f7 b- E2 K- n+ t o- z*/
# _6 }8 @; g. N7 B7 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ P6 {3 b% X1 Z8 \3 ]# J; o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 c! x* ?$ T Y+ K% s$ m. l$ j. U" M** Configure the McASP pins - M7 U% U0 J( G. b
** Input - Frame Sync, Clock and Serializer Rx% q5 I4 ?4 `' t3 _4 n- G; j$ r: Q
** Output - Serializer Tx is connected to the input of the codec
; b: r+ w' d, I, s4 g*/$ I% N T7 ?0 |' L# {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# P. C0 d# T7 \; A# ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 K+ f3 c) G9 f1 u: a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ u" W) I7 t+ ^: v2 L2 j
| MCASP_PIN_ACLKX
) E, q) D3 _9 g8 I) {, G| MCASP_PIN_AHCLKX* {* y( [) x. C, I" L3 u9 o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( a! R2 ^2 v8 T2 f3 r/ Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' m6 D! ]4 K0 Z! \* ]4 x
| MCASP_TX_CLKFAIL
]* {/ k; x/ X1 a& \. M" L| MCASP_TX_SYNCERROR; X, J8 m4 ?; N& M" ?0 o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + e, ] w8 k" i4 g4 h
| MCASP_RX_CLKFAIL
% q7 o9 ^7 d0 J! @& J| MCASP_RX_SYNCERROR . C R& g- Z5 b2 b8 D' h" _
| MCASP_RX_OVERRUN); h7 _, d, z( _* Z5 N
} static void I2SDataTxRxActivate(void)( b" R: O; D& V; J- g
{6 ?* F8 S/ C! U7 J+ y8 o' J
/* Start the clocks */# ]( C, ~* }/ Y3 q& _' R# G0 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& e" X$ I; d' l3 XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 F. J7 c1 j- T( v# C* K" C! t6 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 E3 w/ O/ R8 _1 }
EDMA3_TRIG_MODE_EVENT);
a: b3 C) |9 u( u! PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" d! e8 A5 u( O' T$ \/ k# \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( k1 C+ t9 A7 [! d1 UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: K6 `4 F* L6 n) @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* y, o0 Y5 V1 J+ i8 |4 W" u7 W: Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 a- a- ~& ?! Q9 [! c; J* qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" _1 j, o$ F/ f+ f+ {7 _$ X9 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; V1 a M6 R: s0 h* n1 m1 {" |* ?}
1 g9 r3 r1 m! K/ B/ D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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