|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( {4 S! w9 |& B9 m& Pinput mcasp_ahclkx,
& L, v) N) Y( K5 {7 G- iinput mcasp_aclkx,
2 @/ |2 H) T: C9 S4 q$ J9 ]input axr0," K# a' W. a. f, P
! T; O/ O8 ?" \4 G/ V
output mcasp_afsr,5 R6 e' v/ ^( K. g2 r
output mcasp_ahclkr,9 p: w6 U! ?& [% o; e
output mcasp_aclkr,% [1 Y/ V. P6 I b- w( S" V" a( _
output axr1,# J( S" i3 U8 J2 p
assign mcasp_afsr = mcasp_afsx;
9 W- t+ r4 O) r3 X1 |assign mcasp_aclkr = mcasp_aclkx;
h6 x8 t2 l% P8 y4 c- q# G9 Tassign mcasp_ahclkr = mcasp_ahclkx;5 @$ @$ H% f8 _& _& ?4 L5 P8 u
assign axr1 = axr0;
0 f- Y( ?$ D2 i' b+ ?5 w8 T8 X) M2 `( n/ f1 f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . |8 r1 H* Q: A4 K" k( l% z5 f
static void McASPI2SConfigure(void)- S6 i& e" n) C/ T
{& c+ B0 h6 u( D+ d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- Q* z: i5 Y V6 f: d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# {6 T8 V! B+ t( H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# b' v0 G& @, B/ Z6 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' \9 A" @# ]* X( R% s" \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ }* M3 B7 K7 g7 m+ t1 h* Z
MCASP_RX_MODE_DMA);
2 h' W; ^! Z, z) _7 ^3 R1 P! eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( f& z% A( {; y2 h) R K' k# v' qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: F" ] ]2 ?+ S" X0 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, s+ h9 T6 I; J2 P e1 Z* r6 B) W0 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- X# P2 q5 T/ \: g1 v- fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - c( `# I% `2 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. o" G& @; C, p' w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 _/ `8 |# x W- vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 x4 i4 Q! H8 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 X, L! R; i" r, y. l( j9 e
0x00, 0xFF); /* configure the clock for transmitter */5 l3 R5 N, i$ Y: R2 p6 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; U8 H4 G! r$ z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % O8 z' C. V& b- G: _# e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. s% f( }5 M+ G3 p7 |/ J
0x00, 0xFF);3 }+ ~, f& I, R4 }2 u5 l
! k4 @ z" w4 x8 b
/* Enable synchronization of RX and TX sections */
1 }& `5 d/ @1 Q* G! s8 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ @7 C( y2 h, f* |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 s1 Y1 K! z9 j4 Y3 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 r- c% W, X6 v% C: ]
** Set the serializers, Currently only one serializer is set as
/ S0 R/ A. _5 k4 m8 U** transmitter and one serializer as receiver.! ^9 v% @$ K/ x
*/' y6 J! Z( x, v7 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 k: K; e6 A5 F! A: eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% o* Q/ |9 o5 Z# }2 M. d
** Configure the McASP pins 3 r9 Z( q) k, f0 B
** Input - Frame Sync, Clock and Serializer Rx5 v8 S0 \8 b h& \1 ]: J
** Output - Serializer Tx is connected to the input of the codec
, b9 v4 L* c6 w. q$ ]* \*/! L1 v! z) s! i T4 e5 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! g$ x8 z$ s, s" }$ \3 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" J( q! q/ v7 z8 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ c2 {9 m. G7 ]7 x
| MCASP_PIN_ACLKX9 |! Y' h8 t# m+ W, D
| MCASP_PIN_AHCLKX
0 ]: O' L, p. O: n0 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, k$ v, S) ?# L; YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & n" \: R3 l2 k2 \9 o
| MCASP_TX_CLKFAIL / ~5 q) `7 E3 c' u' X
| MCASP_TX_SYNCERROR% p0 E- F- N: [3 j! t4 ~: V; H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! A1 V& E! k* i! Q
| MCASP_RX_CLKFAIL5 P7 s# q# T* Y# `9 \
| MCASP_RX_SYNCERROR
6 N0 T8 z, Z/ k8 R. o| MCASP_RX_OVERRUN);! @( A; A2 p/ h `
} static void I2SDataTxRxActivate(void)
( r* e+ E6 N3 D& |& e{1 m ^2 K1 Z" }1 D
/* Start the clocks */
% a4 I8 a8 H1 F. fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* Y) `& I1 l! L$ N1 C; e) ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- F6 r4 y# n9 G" HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& F2 @/ K, S& N; K: c1 Q ]$ nEDMA3_TRIG_MODE_EVENT);
+ i8 H# E7 n3 D" E1 c3 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
c1 `) |% \1 ^$ cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; F4 ?% Y: ?$ r& ]- T0 t2 mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( g1 ]! |( m$ R- C/ i) x' Z# YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 ?/ o/ q- ?; }1 M) B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% A% t" z8 m& Q5 JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 R) d' o0 U% k- q/ R: q9 L: oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! B7 {/ ?* e0 t+ E: W
} . ?3 H& U8 u' `# I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 c0 C) V4 e# S$ A' E" B6 u+ ? p
|