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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, l& I3 S/ Z7 I
input mcasp_ahclkx,; d0 y6 Q# D5 e
input mcasp_aclkx,
( o' ]9 l4 f0 jinput axr0,
* C K: o# H% R: W' a
( _% Z W: P0 C m/ Z0 ]output mcasp_afsr,% o' X* x6 E. ]' g
output mcasp_ahclkr,
% H! N( n [* koutput mcasp_aclkr, v5 v# e+ \7 H" g' p/ {- z1 Q
output axr1,# |8 S1 Z. h+ [8 J) R' q+ ^
assign mcasp_afsr = mcasp_afsx;
& J2 c( \$ a' l9 C1 U- bassign mcasp_aclkr = mcasp_aclkx;2 @. N$ E" w3 Y7 ]
assign mcasp_ahclkr = mcasp_ahclkx;
2 e' E& y, m+ Eassign axr1 = axr0; / U2 T; h) \/ ]# b$ i+ S( A
3 F- k8 {, d3 x5 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 W$ p X' o1 h$ }
static void McASPI2SConfigure(void)
. t n1 N6 }2 ]0 m/ j{0 V H4 P# d% M6 C& N# u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ F/ E% m! e- ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
t9 j5 G! ^8 `8 }+ F$ D& cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( r3 n# Q6 \2 a: R: ]+ Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ ?$ R+ h5 C3 E# h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. _# r7 ?4 t5 l2 h- hMCASP_RX_MODE_DMA);
/ I; F# R M b# NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' D+ K+ g3 {1 Q( nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ~3 ?* N1 ~9 J4 i! E( p4 qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# p0 r2 F2 u( y; VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ B; y: P% ^: t& ^9 u5 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # Z/ d6 W# r- u1 ^% b1 H& {0 o# B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: m9 }- z, r( r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 d, m# S& n; d) hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, S4 g( e2 u @4 s( P0 N" f @6 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( m* w: H* c2 ]0 c& m# j/ v0x00, 0xFF); /* configure the clock for transmitter */* j' J Z# R$ q0 f
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& c8 w; x3 \) w% h" _% \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; n; [- C" w. ]$ |% a! Y; A# uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' m# k- {4 g/ y- A
0x00, 0xFF);
1 c8 J X$ B v @' E
8 ~9 Q* d8 Y0 X7 W: P/* Enable synchronization of RX and TX sections */
N1 j; Z$ G5 R6 t7 Y4 C5 M PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. s& [. _/ X( U0 K8 w$ i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ w: p- W! n; I& H% m* m0 x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 V5 T8 Y% p& Y/ b5 m; N: h5 Q** Set the serializers, Currently only one serializer is set as
' T5 ^0 y* w8 D1 x; [$ \** transmitter and one serializer as receiver.
1 e; o; U% Z4 w! e0 u*/
$ u& o! D8 X, T8 x2 Y/ N AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# u; q. i3 d% l# X2 y# E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, S- n( Y( G! }: S. A. X$ d0 G** Configure the McASP pins & V T3 q z8 q" T3 m
** Input - Frame Sync, Clock and Serializer Rx
6 T: }, `: D7 Q! X& J** Output - Serializer Tx is connected to the input of the codec 1 P) @' T& @+ ?; p- ^- I
*/
3 N W# H" r: h$ S- s/ p2 i0 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 u" o% j6 H: ] S7 e5 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ j6 T2 d. ^8 {7 n; I+ i8 j( i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( d/ R9 ?; }% |9 S( x3 ^| MCASP_PIN_ACLKX
! M! u$ D+ T! Z1 n| MCASP_PIN_AHCLKX! J* E+ l6 J: A, W6 C9 M* M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 R& p/ A8 L g5 u$ z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 Y2 S$ V; L6 }5 | D: V( w| MCASP_TX_CLKFAIL
0 t7 I: Z6 W' L7 k' S9 ^' E; a0 r| MCASP_TX_SYNCERROR
6 ~7 S6 O) k I1 [. X* e; h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 W5 d7 `2 f8 o: k. D& M/ c| MCASP_RX_CLKFAIL
) A- X- N, q5 E8 A: ^; ]| MCASP_RX_SYNCERROR 9 K' N1 w" i$ L* f' G% x
| MCASP_RX_OVERRUN);1 v$ @) J- V+ x. K0 T: l* }4 i6 o2 }
} static void I2SDataTxRxActivate(void)
2 z5 _" g% Q' B/ J+ |0 g{, {7 e2 `& E( Y" x
/* Start the clocks */
. t6 s2 ]3 k nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; P( h% W" }# g0 g$ D EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ e4 S' Z7 y" f$ \0 B1 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ {; X+ V; x+ L+ w9 d
EDMA3_TRIG_MODE_EVENT);
, \3 R5 s5 C. o+ y( bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, |+ V0 v( G1 H# tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" [7 f* O6 D* D) IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ ~1 y% G$ S1 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 H: K3 o# {) `- I5 z: W# Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. R6 g) Z- F' @, jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 W' O& }1 R8 D# KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 [* j2 m: i( e4 r}
; F5 }2 D, q. @/ x/ h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 o% ]3 m. \$ m7 B7 m8 z- \! y
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