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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' g" R1 G+ Z9 l, M2 C* Y5 C8 Oinput mcasp_ahclkx,
6 h/ G! b9 ^9 z X6 y( q8 iinput mcasp_aclkx,, I3 ~" B' Z' l$ k+ U. a
input axr0,7 o$ V& P5 H! h) k
: c! G. L# @5 J6 K) y
output mcasp_afsr,8 F" \ [5 J D+ m
output mcasp_ahclkr,
% V2 D4 d6 i9 N9 O1 e4 \( Ooutput mcasp_aclkr,2 k, K5 m5 x* k$ O/ f. K
output axr1,
2 Z4 _0 A) E% \ assign mcasp_afsr = mcasp_afsx;
0 [# m# S5 l6 e N4 Dassign mcasp_aclkr = mcasp_aclkx;- }: |. z* e5 u2 m. m6 M
assign mcasp_ahclkr = mcasp_ahclkx;
- a# G5 H$ D% rassign axr1 = axr0;
+ B# J% ?8 Z" H: O2 I3 o* [* t5 N3 K; H/ J
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 l; I; J# d! [% s. F5 T! c4 L
static void McASPI2SConfigure(void)
. j2 ?3 v6 l0 r$ i. Q: X{& Y0 C8 {& E9 F9 Y7 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, d5 l$ l# ~) s7 K6 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ I4 O. B8 f8 I! e: IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; S4 H6 K1 `' V. c! hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ d7 N/ {+ D5 A& W: jMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 s/ Y- i1 v" BMCASP_RX_MODE_DMA);
: N* Y; i7 Z2 fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: b, o$ L4 {% g* x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, S. g( k3 v4 G. K3 n! A+ P* oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( d; l+ b4 Y4 R, O7 Z$ A$ J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 T1 J& S: U5 E' E2 b2 W8 p- ^5 D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 i3 M6 b* n3 _% u0 D1 P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! Y6 ?+ u$ O9 ~/ g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 A9 ^$ h, K: d! I7 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 k6 I5 n0 `7 O- g& [8 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( J8 R a: s* Z1 m0 Q3 `7 R U
0x00, 0xFF); /* configure the clock for transmitter */
' m9 @+ c; V' s# r! O4 T! WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 W1 I" L: d3 T2 p) L' FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; B3 [ M8 ]. u( D& l8 X u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- S& O0 @$ k) f( A
0x00, 0xFF);
* V5 B3 y: e, O1 {9 P
+ Z# s u, l6 D4 M& P2 q/* Enable synchronization of RX and TX sections */ " {" I* b$ I/ w! z$ W1 G' A( v6 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 Q$ [# n2 g2 _; b2 j' o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ V; k2 a- e% r; P3 }# D L+ V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* {% n v5 q4 ?0 B: ~" o** Set the serializers, Currently only one serializer is set as
0 H8 }# z" V( s0 r h8 W- J; J2 W# V' B** transmitter and one serializer as receiver.8 p# \3 p- d9 y1 l5 ?6 t- c) c
*/
2 T Q- |/ B/ H( T1 e6 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. M2 o# M0 `# t: r/ l$ jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 ^* o8 m* e. b1 F
** Configure the McASP pins
; e* o" b, g' Z6 W6 Q S** Input - Frame Sync, Clock and Serializer Rx, {- ~ s. m# n1 v( s! y! [' N
** Output - Serializer Tx is connected to the input of the codec
1 c, Q2 N7 Z% r) [- ^. }*/6 f1 N! x. C" c: [2 T3 m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 {* @( E: \* ]1 DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, [5 v r& k) z3 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 _' V5 F! \8 r| MCASP_PIN_ACLKX
& k' t! v2 L" J2 k: v/ S8 {( R| MCASP_PIN_AHCLKX
8 X1 v9 A* L5 g: ^2 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: V: \6 I d& B. _5 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 Z" Y( w# V# i4 V9 y
| MCASP_TX_CLKFAIL
4 R+ N& n) T9 H0 _6 o| MCASP_TX_SYNCERROR6 U% g% C! C1 _6 i) Z5 r( `8 k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( Z$ w' O9 I; U| MCASP_RX_CLKFAIL
- y5 a1 Y3 _+ [. Z' f4 v7 k% N| MCASP_RX_SYNCERROR
- D5 m4 H* v# q| MCASP_RX_OVERRUN);/ F; q6 ~0 t& _9 v! \9 U
} static void I2SDataTxRxActivate(void)
3 z# H: I+ d1 k& @% j' _" P{& v) p5 _1 F" |4 l# N8 k8 j
/* Start the clocks */7 ^+ w0 Z( u9 r; ?: d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ O" F4 @# V' _( @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* `: K/ j5 u, }5 V9 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 V6 R' _3 Y. p5 w1 W& C) PEDMA3_TRIG_MODE_EVENT);
9 C" w4 f* n' X6 p) vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& t8 g; ^6 k. d% ~- WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" P! K* w0 a- v. Y: N0 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! k7 f% w2 H% V/ R! [% o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# u8 n, a5 f1 M* c" h( q* @1 a9 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' S* F5 a* i3 eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; n5 K Z% C/ q! O* ~8 @. s# W5 n/ ] MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 p5 E& h* y6 {8 A
}
* `8 e" B+ B; q3 \9 b/ w9 d* O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 A/ x7 w6 d b4 f1 }4 |8 F6 m0 D
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