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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# N: _$ k) p) o- }! Vinput mcasp_ahclkx,
7 h0 \! l" I% n! N* _input mcasp_aclkx,' o3 j; c$ m2 ~* V8 }5 m
input axr0,% S- a( h. n# d9 }; R. G4 G" H
2 d6 J6 q+ ?$ N: }1 W4 {
output mcasp_afsr,$ w1 K' B& R1 M1 [& r9 u! g
output mcasp_ahclkr,& i9 M- c) k6 I% B
output mcasp_aclkr,- S- Y" m- ]4 k( f
output axr1,
, \, V2 W. d( p1 o' L: A7 ]% t assign mcasp_afsr = mcasp_afsx;; M+ P: M6 M6 W# D. b4 {4 f- S
assign mcasp_aclkr = mcasp_aclkx;% b! G' \" d& Z; G7 x0 B! ?" \7 {. l5 t
assign mcasp_ahclkr = mcasp_ahclkx;
) O% I* A* D$ [) Q# Aassign axr1 = axr0;
1 y: S! p" l' z: M& x/ V
( ^* o1 o8 n" ?$ k2 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " h* s( S' s$ {' @0 \# ?- H& n% c
static void McASPI2SConfigure(void)7 k# Y2 t1 C8 P4 F, G
{
' I& q" G) ]0 O E8 x8 d/ AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( e" S; ]0 N. u0 Q- d9 D2 X. |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 L9 {. M+ x- d) M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 Q% S& n& H: i9 N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ o' U* c" ]1 { o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, K" K. f* h- [* vMCASP_RX_MODE_DMA);
' @( N/ ~* C: t" hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 H* ~. y9 a) m1 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" F( f- U, U# y$ Q2 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, m" L6 c+ ]( w3 V% s. pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) |- T4 U5 J% IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 ?& C) Y& t h2 }6 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 V: r5 T! {% x+ P; Q7 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 p2 B8 p& B1 c3 n' UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 k1 V$ Y u+ c" K1 w% DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' C5 Q) d8 ^- C7 V, V- T
0x00, 0xFF); /* configure the clock for transmitter */
" n* P$ L- S) R) ~5 F pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 D# d& D" y/ c$ @; T. y- u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) s+ x7 t! _& g. T6 B; p: vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 {1 M) p; m9 z5 e/ n# {+ J
0x00, 0xFF);
" W1 z0 f7 o. L* P. _6 N- y H4 ~: R# O3 d H% Z
/* Enable synchronization of RX and TX sections */ " m% [* f3 n- g4 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- r! q- J r- s& A' h, l' O y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 l# O# O# T# R9 B: V5 w7 ]0 `( LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- F. p- s2 C3 i6 @3 J7 @** Set the serializers, Currently only one serializer is set as
, \3 v" N! B5 w. t5 R6 ]** transmitter and one serializer as receiver.
0 q9 l: s1 X2 `! O/ j5 }*/
. H2 a" K8 T' ?6 hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" h- e" S6 G) a# p. y% Z" z( {+ n* l, ?4 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- r) j: }. I5 x** Configure the McASP pins
0 V5 w2 i; E8 d% _/ T: Z** Input - Frame Sync, Clock and Serializer Rx" I: d/ i4 |5 a4 Q) o
** Output - Serializer Tx is connected to the input of the codec
+ _, d3 m$ O* a9 U: h*/
! L! m: Z$ x @7 _9 NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. N3 o# d4 j. S. b4 [8 i$ P; g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 z& m' Y+ [7 p: @: L1 [9 P& U4 Q" y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) B* v! g- z1 E
| MCASP_PIN_ACLKX
2 A% c/ K' p0 C9 m) R$ ~+ q| MCASP_PIN_AHCLKX
9 W! C# a7 b0 U9 V2 N, ~& B7 W( q+ w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 S+ v. X$ x5 Q* `& E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' \' l) c4 L" c( q1 k/ B7 S1 h| MCASP_TX_CLKFAIL 5 t- x1 ]8 d6 H
| MCASP_TX_SYNCERROR
9 i6 ~7 W$ w$ Q) B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 s! f3 y7 n+ F. x5 N" X) c
| MCASP_RX_CLKFAIL
. G# u$ l s9 t' p7 m) g8 b8 G: ^| MCASP_RX_SYNCERROR 7 b8 H6 j$ H) v# v* A# w
| MCASP_RX_OVERRUN);
. [, R) s$ `3 X: `; g0 F6 o: F- R) ~} static void I2SDataTxRxActivate(void)
" G$ K, q/ G& {3 O{% j5 W; Z8 v& |
/* Start the clocks */8 X3 v. V! U2 F7 b1 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# L# n v5 a, O0 S+ TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 J' ?5 R$ G1 Z C: D j% rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 b: b+ D% i) S+ E
EDMA3_TRIG_MODE_EVENT);
' `! W6 h+ j: {/ U, J! j% ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 q& q' Z* b! X" d \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ l: H$ E: L+ `/ @/ RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) o" V! f7 b& }! |: e& |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 p) ^% O) j9 E b/ `" b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 ^ V! K3 t: D. R6 w/ r6 P5 p9 N$ w6 XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% x; S# ~7 r: v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, y2 s N; u. Q
}
7 A3 n/ |: P/ b" L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 y& ?$ }6 @( f# {# L4 \
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