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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 O, u/ ]0 B/ a4 F+ P6 m
input mcasp_ahclkx,% j s: g/ i9 \% ], m; u
input mcasp_aclkx,9 J/ I/ I% ]4 Z D
input axr0,
5 }. ]' S# C/ W8 W$ Q4 u7 f8 I* e; H0 q
8 Q: W/ X: B. O! ]3 L, Voutput mcasp_afsr,/ e" C7 ^- g, q" j
output mcasp_ahclkr,) s7 l a6 o* N2 @4 P3 k
output mcasp_aclkr,9 e( ?( P" t0 j2 q% ^& _9 ^
output axr1,
% r: [5 Q8 |% [! W1 ~8 p2 k assign mcasp_afsr = mcasp_afsx;
- \; j3 Z; Q( @assign mcasp_aclkr = mcasp_aclkx;
- T5 F7 _/ e5 iassign mcasp_ahclkr = mcasp_ahclkx;7 `& J: a( d8 k9 v' K
assign axr1 = axr0;
6 b1 _' k: I G' |0 H) y* `% }4 N$ |! o3 w: I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, U, s3 n, b8 k& r2 C/ T3 \8 a- ?static void McASPI2SConfigure(void), O+ H& O( O' q: `3 L- B
{' B$ Y5 Z6 z" F% K! E0 x# ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ Q# o4 r" f6 W0 A. Q1 r! s. Z8 l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. d) k$ N4 m8 ]/ K" }2 b. g& \ l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ W* _" N3 i4 e9 C3 |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" X9 l( i, F4 s h4 K8 U/ b6 c: TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# u1 r& M g6 W/ u: _MCASP_RX_MODE_DMA);
7 g, f+ k9 G2 f. NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% Y H* U( r: v; O0 ?* v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" {4 ]1 S& P$ @, N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! q) L) _/ E2 s5 h& C' M8 d" A1 g# y) u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ O: w' J# A% [ ^, l. K( M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. ]1 Q+ P1 ~1 J4 X! j' }6 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- ]8 o& i x4 r" G3 v* H/ F. Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ `* E, K$ N3 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! Q$ H! W& S Z2 F1 x1 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; D, q {6 A3 M$ j8 P1 P' s9 {0x00, 0xFF); /* configure the clock for transmitter */6 K' G9 \! `& H+ M. c$ j: R. V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" |+ u% i) \* y& h/ H! `% K8 b5 ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! v" H. O* H5 `# f+ ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," ?2 \# j' ?) [) P; ^
0x00, 0xFF);
1 _ `8 U5 h5 r
& I& S$ m; a: H/* Enable synchronization of RX and TX sections */ 9 h0 H k' x3 Z7 ^) F4 V6 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 g( a) y7 _/ ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 ]7 v4 P m2 I, B4 [# MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. P: l1 I7 [5 t+ E9 m
** Set the serializers, Currently only one serializer is set as) Z- I& D2 F9 O7 f
** transmitter and one serializer as receiver.
8 l7 V& W! s w! [" H7 N2 U*/8 q+ r' i- ]! }6 V6 ]! C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 |" r" U$ h$ z5 [+ o; |1 F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 c% Q0 s' d0 _5 {1 w( I. _) @3 ], y( y** Configure the McASP pins 6 B- [* U: M' t. ^
** Input - Frame Sync, Clock and Serializer Rx3 h# H4 T0 k. S2 |5 @8 C' c5 r! M
** Output - Serializer Tx is connected to the input of the codec ( U2 o! X2 S( ]; S4 G1 |! \; Y
*/
. p5 z4 [5 \# E1 e2 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* _2 p P, r, b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' f3 V+ @: P3 r! g% F6 CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, `* ?4 T" s/ t- R2 l5 c4 L
| MCASP_PIN_ACLKX
8 l6 A0 w2 A+ q+ }2 ~) M, t, m| MCASP_PIN_AHCLKX% O8 p# g* w* H) y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ d% x, S! I5 m" M: Z: L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) p9 l. p* ^( I/ y
| MCASP_TX_CLKFAIL 8 |9 k( Z+ q9 q7 {9 ~1 P1 j3 i
| MCASP_TX_SYNCERROR1 O6 j4 T6 k% V+ E/ E. N6 s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, C% d! \+ }8 ]( |. M| MCASP_RX_CLKFAIL
/ i4 d" `9 m% [; {1 N" M| MCASP_RX_SYNCERROR 4 b) w6 T, c9 r7 Y9 m7 g
| MCASP_RX_OVERRUN);1 x3 R% j' ~ m; [8 z i# H: g: s
} static void I2SDataTxRxActivate(void) @0 z/ `. V0 U& y0 |
{. c+ W2 c1 {" j2 \( r, e1 t
/* Start the clocks */# [* r& p( f) }& Y2 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 R% \. ?( q% t; T$ R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 Z, H8 w' F' t- T0 F8 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# ^0 u8 s5 X1 |1 i4 S, SEDMA3_TRIG_MODE_EVENT);
( [$ m: X+ ~$ a5 @. gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ o8 m" t9 |: o ?* j- B) b i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 B) O$ w* S8 b% VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 l: j1 @5 G$ M5 A$ U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ S h i/ M2 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ Z0 P- m/ V4 N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( @4 f0 g7 y) j; j hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ ^0 k* |0 `) Q g D9 o} 1 x% \8 w. P4 ` g( s7 p* A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) v( E% ?" J a q
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