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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# X3 Y0 K4 @4 N! J [/ ^
input mcasp_ahclkx,
0 y9 W6 T. M$ d4 Rinput mcasp_aclkx,( _( ` \, u. |5 Q) B
input axr0,
N; ]7 M, ?. S+ [
) h. r6 Y" U M: g7 L. z; Foutput mcasp_afsr,) c$ Q9 m# T# x1 |# d& N) [
output mcasp_ahclkr,
: d5 h* Q) a. m9 O# {. B) Qoutput mcasp_aclkr,
7 _$ A$ K- `, e6 O" S5 A/ H6 Foutput axr1,, B; g4 C4 }2 _! ?
assign mcasp_afsr = mcasp_afsx;" D, [& M2 Z9 }
assign mcasp_aclkr = mcasp_aclkx;9 X7 I/ K e8 {# N, o
assign mcasp_ahclkr = mcasp_ahclkx;
: d8 w2 D! ?' z/ o1 Jassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # l2 r' E. K4 i# g- c: {6 G2 T. K
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& s5 y) S3 P0 A: |8 ]2 dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 `6 ~+ ~: C ~1 L* C' I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 G8 S& S: h/ ] I
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 |% d' M) W& [+ F/ w8 qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" I% k2 [: b- ^9 M, [ @) D# l' XMCASP_RX_MODE_DMA);4 `& Y1 H8 T$ ~/ H' K0 ^) F6 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 j+ j( ~! Y" N) N4 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 l' Y8 W# h6 _3 D' F. d! F KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, s. Z& a1 _4 a. P. C& PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ [' c( K @7 C) W( _' f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , \6 x4 Q. j p3 ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( f( M4 D! d1 q5 [4 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* C# K8 V$ v1 u* Q& Y- Q) IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ Q' y h* V% l; M' {+ \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# J8 g ?& ^4 o1 s
0x00, 0xFF); /* configure the clock for transmitter */$ Q0 p3 N/ x0 U N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, ^; p+ b( g D1 z2 u* j$ n9 q0 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
g. f$ r& o- h0 J3 X6 H4 Z" o9 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. t( `; }; a: q8 {: T+ a
0x00, 0xFF);3 H) q7 H" f7 j( J1 w! u
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/* Enable synchronization of RX and TX sections */ 6 Q9 \+ U$ \2 O% B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 c) h9 j2 E% I6 l% L" s; vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 V5 n/ q- f/ o/ Z1 ?' a8 I6 \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; H/ b4 Q% V ~: D** Set the serializers, Currently only one serializer is set as- V$ X2 L9 q/ N( M# T
** transmitter and one serializer as receiver.
7 E1 }5 i3 P7 \4 ?*/$ h$ j# D1 e" i6 e" u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: z! T1 _" D# hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 C. K0 C7 ]# i5 f+ L' ?6 c1 ~6 y
** Configure the McASP pins
$ Z' i* H$ \2 b; Y** Input - Frame Sync, Clock and Serializer Rx6 G8 K2 M% C; d
** Output - Serializer Tx is connected to the input of the codec
5 F1 X9 t4 a2 p z; H*/9 C0 n4 Q m: _! w U8 ?8 g# h; l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& ]0 h! \( H( j- n( Q& n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' K* y) L1 q; Z4 d' f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 y: ~! P" I/ r; w( D9 x
| MCASP_PIN_ACLKX
8 t0 i1 {' t0 `| MCASP_PIN_AHCLKX7 l% ]$ x: N$ }8 `4 x; s5 D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ m8 {4 L8 F2 a& c0 k' [; JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 I7 ?% A( i0 T
| MCASP_TX_CLKFAIL 0 h' k& S9 o1 m% N
| MCASP_TX_SYNCERROR% ]* D2 N" z# c9 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 c% v/ l y& g1 A# ]( |0 `| MCASP_RX_CLKFAIL1 ]' y7 j' Z& k
| MCASP_RX_SYNCERROR
1 z; N; M7 q$ T" a( H# E0 V| MCASP_RX_OVERRUN);8 @8 _4 H- r: g4 p4 |
} static void I2SDataTxRxActivate(void)$ l; N, ]; o3 F, s2 u+ ~; t% v
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/* Start the clocks */
" k0 \' c b: AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) e) R$ j7 R; q& O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ W) p2 n& H4 t! w% A2 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) c6 E4 w% l9 g9 \8 r+ E3 rEDMA3_TRIG_MODE_EVENT);- D# a$ a: _' J& T! K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ S6 w4 H0 ?0 \) uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, v) A; a# |: x; j) E6 _' O" o5 aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' Q6 i6 [ S3 `, Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! A3 Q. b, }! x6 {% ?# O) Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- A( ]" e1 K4 J3 t# b* ? v2 W7 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ R) o7 P/ f c! L8 @$ P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % _$ _4 ~' u5 v' J4 _- Z
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