|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, z r! ]5 }8 p* G. p, \- R
input mcasp_ahclkx,
3 y1 ~8 m4 V8 ^0 G9 Zinput mcasp_aclkx,
( A: B% O n0 Zinput axr0,/ M- y K% W _/ {
% D( G( g4 Q: b7 g. t0 Loutput mcasp_afsr,
- f/ F. L! v4 r$ b g& b7 ^- B( uoutput mcasp_ahclkr,! x. U. A3 @: f% f
output mcasp_aclkr,3 S( j/ ~. ~3 F" V
output axr1, I H! m9 v8 H% J7 R: M
assign mcasp_afsr = mcasp_afsx;
& Y6 d" G) }3 J7 k( Dassign mcasp_aclkr = mcasp_aclkx;3 }' y/ J" I! L' g
assign mcasp_ahclkr = mcasp_ahclkx;
# M" W. E9 l& k, h7 l6 yassign axr1 = axr0; # P( c8 h* r; {& p
1 S" e# j4 n! I' j- \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ p& [$ Y; j6 x" V$ h' Wstatic void McASPI2SConfigure(void)6 j+ @$ J2 T' J# r8 A
{
5 [ N+ K6 y, @, h' ~9 B( u* _, PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( ?: O; r$ A0 ~- V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ Z5 M) D7 x# I* JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" S7 Z1 L- h7 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
W3 R1 F- w |% R5 u" YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 z: S5 k z+ L1 T* H _0 ZMCASP_RX_MODE_DMA);0 y( Q- C. G k* D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& g t+ E) i1 e% a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ ^2 I9 }+ G$ d* d4 L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 g% h2 C0 q! F+ w( I8 \" H/ NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: S3 u/ u8 N; f3 o" y1 U+ y/ ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. g+ z; X: a- m# R# tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, X6 Y" a$ U% U; m% IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 Y; ~6 c! P& y3 I' ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 q0 n k. o, @3 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 r; x7 s- T, K0 p
0x00, 0xFF); /* configure the clock for transmitter */
! Q/ {& D0 A- s" J7 c7 E' sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 }& S1 U1 A/ f$ K( e4 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / d3 C6 S }+ `% z B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) p1 Q5 y+ l: a, [$ H) m' D0x00, 0xFF);. k ~' _& E0 B$ q
) f' z/ e6 c- M. Z2 I
/* Enable synchronization of RX and TX sections */
+ m, a: a) M3 qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 S R- m D* l" H7 o) BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 o4 d" }9 @4 R+ ^4 o; Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 u- q* K. A3 ~& P. G$ Q1 }( m** Set the serializers, Currently only one serializer is set as: b3 C6 L [" W# F( o7 @& x* |/ |
** transmitter and one serializer as receiver.0 w- h4 B1 ^1 X- e
*/
. J$ R) \& n1 V8 Z& ?; T1 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! |( d U4 h7 n% p3 ?% k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ C* Q! N/ ?9 S# m M4 L
** Configure the McASP pins 3 `$ ~* }) U+ ]3 {
** Input - Frame Sync, Clock and Serializer Rx
; P& f2 f, i4 `# \** Output - Serializer Tx is connected to the input of the codec & o! P* i) L6 p1 P& D! E
*/
5 Q2 q9 G* ~2 f" LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% A+ i3 u: o5 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 m# h! K7 L1 N" r* v' l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ J" o0 D1 r: d) e. @| MCASP_PIN_ACLKX
' M. ?3 W. A( ]8 n9 p. a| MCASP_PIN_AHCLKX
, Q; z0 T7 V- P, ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 n2 A- N2 z% m& ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. e( Q. R* l$ {/ q+ Z0 }| MCASP_TX_CLKFAIL 1 |5 ?. F. p7 q3 T" b1 x
| MCASP_TX_SYNCERROR4 Z# Q& ^8 o3 J, e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 I2 G- p+ F+ @* S8 O3 w$ f
| MCASP_RX_CLKFAIL
: v- c r$ P- f/ y| MCASP_RX_SYNCERROR % a% C0 R2 Z$ k; D8 N2 ]
| MCASP_RX_OVERRUN);; c7 H/ N! N0 ?8 y, C( `
} static void I2SDataTxRxActivate(void)
4 s3 V4 \2 |9 w& d{0 O; l8 t6 a- y( U+ f: u
/* Start the clocks */
6 @, C" n/ X7 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 \% A+ I: g' N# ]) X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 E7 R* t8 g$ ?( _% TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% w& W/ s8 p% z* D1 A( O7 a
EDMA3_TRIG_MODE_EVENT);; s+ v% X. |1 S4 X) W# H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ |* z( ^( q' J& G- \ H) g8 VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* ^' G7 n+ d# V7 B, t3 T OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ Z1 [8 q1 i5 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 x9 p4 g$ a5 o% m/ e6 k3 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- m' n- M( E H' m4 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ~, A0 }& P- n2 i9 S; Q% p9 I( UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 X# {1 }% U4 M+ d( g}
, P! l) N1 A) A2 [: w% Y) y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 i, t2 B; R) H* u4 D+ Z9 S+ d8 u; y
|