|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! \' p9 G- X; L8 {; c5 u! f
input mcasp_ahclkx,
7 P) b# K6 i5 z }& s/ p/ l n1 einput mcasp_aclkx,/ L$ s8 v( A1 h8 j
input axr0,0 K$ J% ^; d% R5 Y1 k
. E5 z( s4 [6 y. j2 U$ youtput mcasp_afsr,9 n) @1 D9 I' z. F2 V& M: x
output mcasp_ahclkr,% ]- T ^( h: }& y6 o$ R* e
output mcasp_aclkr,
- ^! f' C- x' ^8 N1 soutput axr1,* d3 w$ R& q" y
assign mcasp_afsr = mcasp_afsx;' I' _( x" H1 [4 ]1 Q/ w( j0 h4 s, c2 F
assign mcasp_aclkr = mcasp_aclkx;
* ^# R: |$ z, r9 W$ Massign mcasp_ahclkr = mcasp_ahclkx;% {; i$ _( `5 D" u4 \' F$ D
assign axr1 = axr0;
' o8 `+ D. r4 @( w; g1 H; K' z% l# W i' x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ f; _9 f/ A0 r+ {7 ] Lstatic void McASPI2SConfigure(void)
9 J. w8 v0 h4 |! `$ x/ h$ o0 p& i{ C3 u) x4 }* D0 u& C+ U' T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! v- \7 W$ h9 I% X) B/ \4 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" G' V* x! x3 i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ^% m Y1 _( r8 s' d. k4 C1 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' N; r) J; g4 C! Y! zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 w* }- l) V3 N% dMCASP_RX_MODE_DMA);
H6 ^" l8 r9 B9 ~( G/ ~* I+ YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' a' q: Q! T( K% v6 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% I# f& I& c {# G% j4 _* c/ lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 I2 l7 O8 F( S& D2 X9 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( g3 a, R( ^2 @2 W3 t# k- qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 F/ J9 [# z: T1 \2 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; F) R8 o: j" {) v& I1 ~% w1 f# q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 @/ o: o7 i/ h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # D% b' p4 d& z1 ~% S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 S: b, ?: i0 n L0x00, 0xFF); /* configure the clock for transmitter */7 e8 {1 c8 |; N' r& g3 C& v& u8 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. r) ?+ a6 W* i) J6 V+ M6 Z& Q5 VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / w$ s' L [2 t B. P! r* r q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# P4 j: P% z, y$ q v0x00, 0xFF);
; y: O9 U8 u9 e8 Y3 F5 Y m- t; [6 n6 q; K7 U; j
/* Enable synchronization of RX and TX sections */
" P7 c$ h5 U" i1 G. W( C/ u9 q- \7 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 I0 ~6 @/ c6 z7 ? I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" d7 M' ]' O0 d2 K1 KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) Z3 P5 r8 }% B3 d
** Set the serializers, Currently only one serializer is set as, D: [% p J5 {( R" m
** transmitter and one serializer as receiver.
1 g2 E$ b0 T6 k4 C$ D*/" {- q' _' C5 z4 T9 [/ e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* B) F* g! `% Q) n1 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" m/ S& N; g' e1 D
** Configure the McASP pins
. \, }" R. T$ u R** Input - Frame Sync, Clock and Serializer Rx j( m6 z$ v* s& Y7 C
** Output - Serializer Tx is connected to the input of the codec $ j. v1 o$ z7 Y1 m0 |. B
*/
9 V# n$ |0 F, f( N1 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* G8 O* L1 p% e! y1 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: o8 Y( a) L" Y( |6 ^1 W& SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' m' `' d P! W( @
| MCASP_PIN_ACLKX
/ [2 Z9 ?3 B$ k6 M; i9 M9 U3 [| MCASP_PIN_AHCLKX+ I- V) R" e9 E- g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ O3 N, _7 t2 Q) M( U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ @7 ~5 U3 h- Z| MCASP_TX_CLKFAIL
4 [$ X1 }4 W" I2 u- s" M| MCASP_TX_SYNCERROR- l# m5 ]. ^0 _( b& C$ N4 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , _$ c! l1 E0 K2 b9 _$ G
| MCASP_RX_CLKFAIL+ m) ?8 G! q" s
| MCASP_RX_SYNCERROR
2 d$ q# U6 m: S5 m4 R| MCASP_RX_OVERRUN);
& U2 t+ o, @2 Y9 G6 U. p} static void I2SDataTxRxActivate(void)
$ s @ W1 z" z. f% Q{
8 ?& t$ P$ ~0 b* m/* Start the clocks */
8 i, d: u; S0 j. t$ D( bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, l0 e& K6 V/ r2 }' ~3 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 @( M: }$ \9 Y$ o/ uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 j- p) r' R9 [9 M9 K' T2 E k' dEDMA3_TRIG_MODE_EVENT);. B: m! l2 F/ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : d, n) e4 u% P6 h! ~$ m" m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ |. f. \2 y: w! mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ l: q2 n* E& E# z5 P7 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ U3 j% i: G7 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; t* p. S7 [$ n8 NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 a# h6 G) x5 F. wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* D! `, j |' t}
/ c, j. z( O/ M5 H6 X, S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # ^9 G7 }3 N6 U6 b D/ y
|