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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; H, n) P+ W: b# `( m/ p
input mcasp_ahclkx,
& [: Q0 E5 S" A; ?0 |. v' dinput mcasp_aclkx,
, d) Q# ^2 j1 y H7 d9 minput axr0,
7 [5 o- }6 W1 ^
% c* y' w4 V" j! w6 toutput mcasp_afsr,
( ~7 ~ T" u+ m+ k4 W3 Houtput mcasp_ahclkr,5 P% r' W/ b- ~) M, v6 {
output mcasp_aclkr,
3 y- Z |" e- Zoutput axr1,
; H& g: L. y7 o7 t5 r& m assign mcasp_afsr = mcasp_afsx;
! g; t9 R. L. }8 h7 g# [assign mcasp_aclkr = mcasp_aclkx;' S* M8 S0 C+ \: H7 N
assign mcasp_ahclkr = mcasp_ahclkx;& R8 l6 S. ]) l! C$ M W* S
assign axr1 = axr0; 1 d8 M" {$ n) C: f9 F2 a9 R
4 e0 H/ t) c5 C8 e) z$ ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# K+ x% n" o% t' n2 U* sstatic void McASPI2SConfigure(void)) k- e! v! L3 B$ I6 a$ R" d% k
{% H- e0 R; \% p5 g! K L3 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% M& W) [, a; _$ Y# L' nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% L: Z! \$ o0 h8 W0 A; q. I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
z; b: R9 K+ _+ y, u8 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 B z- L% B% Q! {: Q' ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( w% Q0 j: R2 U1 D( r1 o
MCASP_RX_MODE_DMA);
! e& {' q0 d" s+ b0 Z; [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 \' z8 |! d% s, \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 g+ `* n" Q$ H1 |5 \' Y3 [3 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) P. V5 }& o8 @5 v# d4 n2 uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' C8 {% N0 b+ ~5 dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 V A+ D' [* a6 P- ~7 l6 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% O' B3 u+ [* u' f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ d; d5 K; {9 c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' Y; I2 T" b2 C* [ E8 T9 O5 N$ z uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 k$ s" i+ h' M* s. A! F) X9 i0x00, 0xFF); /* configure the clock for transmitter */
6 m- x% L: I4 h- L' n+ mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! G8 I- u, u% _9 B7 v3 T4 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ s2 E# L6 G3 F5 @3 xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ A5 _+ _. k) \ {0x00, 0xFF);7 U1 l, E5 t: W# n& L) b$ y5 }
; S" z8 F# p o) e* _
/* Enable synchronization of RX and TX sections */
: r. R2 t8 a7 W' N5 n& V# ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# s0 e( E* Z B$ t/ r0 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: _' C. E& T" |8 u) _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- J, r( m+ {- k- ?$ ?/ k: |** Set the serializers, Currently only one serializer is set as/ u! ^- C2 h! E' m
** transmitter and one serializer as receiver.
2 L7 j4 R& n6 N1 y*/ V R$ O$ Y- t8 H) x+ I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& H- G2 L, ^8 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" {$ \ V6 f: h3 _# u& ^' H** Configure the McASP pins
) v, u4 H6 m4 F$ `: Y" {2 N+ J" R** Input - Frame Sync, Clock and Serializer Rx
" e! p* `# m: v3 k) E* I, a** Output - Serializer Tx is connected to the input of the codec
* s7 Z2 I5 U4 X# r* F: t o*/: \1 j3 G4 ` M$ T3 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 K L' l X4 d" ^% JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. b. J6 ]( h5 o( SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* X0 D- E' T9 `: V# @) ]| MCASP_PIN_ACLKX
( O3 d" x. A. ?| MCASP_PIN_AHCLKX
* v6 W2 f, a- z% ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 x1 B8 [) [3 D6 A+ D5 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) `* W6 C, r4 C' k7 U" D| MCASP_TX_CLKFAIL
9 w$ K8 c4 f0 L; t7 n$ J| MCASP_TX_SYNCERROR9 g3 T9 \; m! X9 v% l$ j6 m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
s1 F# z5 [3 ~1 V# L+ P5 e| MCASP_RX_CLKFAIL
5 Q, r% F* M# C| MCASP_RX_SYNCERROR 5 d- p% e8 Y8 O
| MCASP_RX_OVERRUN);
8 J1 e+ X7 E$ v& e/ V9 D1 s} static void I2SDataTxRxActivate(void)8 k3 l) l. p, `3 ^( Q4 e' M9 J2 U6 |
{ d) M0 \7 ~$ S, h
/* Start the clocks */' T2 F, H" t6 A5 B3 j% v6 B# b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' e# o$ Y4 Z' l/ N/ u b/ l( `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 h% K8 j( H9 S3 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 `& E _ N# \" R
EDMA3_TRIG_MODE_EVENT);5 L2 n( w6 R/ Q7 B. H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: w; N* T8 l# F3 l. {' E9 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 N6 \) P5 i8 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( \/ a5 J7 U$ s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' p6 f7 ]9 u+ Z5 n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ X4 A' t" y7 c2 q! w5 `! J( I* J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 l7 V5 {) w' t3 ]4 j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 k+ e% C/ @0 [3 s8 @! T} $ `+ W" t) F0 k. e% p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 ]9 o- R3 h) @. n. o- G
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