|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 b9 Q7 U9 a; N- c$ einput mcasp_ahclkx,
& E$ y! \5 T$ A! hinput mcasp_aclkx,
?* H: S, [( t0 ^input axr0,5 F7 P1 f& P5 g) A/ c
* V' \" c5 C" R+ Q8 r2 q3 Z1 X+ Qoutput mcasp_afsr,
. N& n7 I' O) A$ M- o! T6 e9 xoutput mcasp_ahclkr,
2 r: }0 H, Z5 T( C) \output mcasp_aclkr,! E5 e8 e, o/ G6 \
output axr1,- ]+ Q% e% H! b9 Q
assign mcasp_afsr = mcasp_afsx;
$ f2 f, h' \: x4 M7 xassign mcasp_aclkr = mcasp_aclkx;
* N0 w, [9 W/ R( ]% G0 rassign mcasp_ahclkr = mcasp_ahclkx;. j& J. k9 Z6 L2 u5 Q
assign axr1 = axr0; s) G; z7 x7 [3 E* o+ D
7 V- P: Q. _( a: W. P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 R8 F9 u4 U7 V# V4 J
static void McASPI2SConfigure(void)
; o6 Z% L, g+ D% ^4 H. y* L{
- A0 ?: O9 [2 ]6 j3 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);& W& h3 _% [( H1 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 ^4 c4 H% H# R4 Z: _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 F1 p" G! z3 L! ^3 y4 E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ ` t+ q, ?+ F3 N' K! M1 z) y2 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- Z+ }( |( T q% |8 C
MCASP_RX_MODE_DMA);' S( x; r+ i1 J6 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ J7 h( n; ^' F+ F8 n+ YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' c& X+ T, \3 f' f+ ^: u( f/ TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( m5 {& J# `9 U; z5 n9 B9 N: j( r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* n3 ~" V( @, \2 }& I* `: _2 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 U, Y# [1 `# rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. v8 Q. |# L! y+ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 h: j1 n7 H" w" C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : Z: c% }0 D" [; l# I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 U9 ^0 q1 N! F/ K
0x00, 0xFF); /* configure the clock for transmitter */
4 R$ O7 Z3 m* O0 j& E1 G( JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* o% l" O. H! }0 _ oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- f; z' S& l: r" G$ C7 @. JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 S& a1 }9 @/ W
0x00, 0xFF);/ p/ i; [6 N- F5 r2 a6 k3 P
) T" A! U3 v7 k4 I( n- k/* Enable synchronization of RX and TX sections */ 5 b$ Y. f# k# u) t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
x* Z4 R$ ?1 `7 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ I) I7 `! b4 R7 e) H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( M; D3 S+ I3 s+ K& c5 ?** Set the serializers, Currently only one serializer is set as7 C% M" m) V: [. x& A/ y2 a$ D
** transmitter and one serializer as receiver./ M) N8 K. R% I. a$ h) l3 c
*/) Q( w6 q( C! p( n' {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 {8 [7 y, f, ?: m/ k1 o' fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. D, g; \3 ^* L+ w4 w0 A, A* h
** Configure the McASP pins
7 J& {) Q0 t; E1 ]8 [7 i** Input - Frame Sync, Clock and Serializer Rx
4 q5 z( w7 `4 Q; R& y3 R3 B; H** Output - Serializer Tx is connected to the input of the codec
9 |( F9 @9 }7 ^ c' L/ C9 {/ s*/2 d6 C* E1 v! k0 R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ P, C; ]# v. ^- ~2 g; d! A* s) \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* L6 d8 f: K3 _( y% |5 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* X$ T3 R# E w| MCASP_PIN_ACLKX
3 s% l# p5 h: D* B! w( \9 e| MCASP_PIN_AHCLKX- L3 o/ A7 u* ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, [, C, l% ]- \9 j" W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; B( Q$ Z) H5 D2 T| MCASP_TX_CLKFAIL
* X) I1 H1 M, v+ }| MCASP_TX_SYNCERROR
8 z- `( `2 ^; C& v! w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 y7 Z; q2 Z: U' p, Y9 }% T; p: P) [| MCASP_RX_CLKFAIL1 \! x0 [/ y9 o/ A
| MCASP_RX_SYNCERROR 0 J$ r# X4 m8 k( g
| MCASP_RX_OVERRUN);
4 c% ?( y: ]5 l% k* H1 w. u2 |} static void I2SDataTxRxActivate(void)3 Y, Z7 ]; `- I" h
{
0 A# i' f& [% j( T$ S# ]/* Start the clocks */
( y1 F. R; {9 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, F0 J. L; H) t" E. r& ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- B; S1 s' C7 W" c) ?( _( cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, d( y/ s9 J4 mEDMA3_TRIG_MODE_EVENT);
* ?8 G9 ^ h, ?; R5 H) oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, J+ D A3 p% i. r; x' t. fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 s9 A+ H3 u! H0 ~$ B1 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. N; N! _ S5 P+ n- D. }9 Y- q; \, PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 z3 j3 [+ o" S/ Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: g& v t2 H8 I1 F& p6 g, D! {7 D) YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' B, L6 \. w- rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( y4 z) I' {+ I) D. |}
5 z# ^, F/ p7 A: S0 [; v6 ?1 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # E% O3 o) V" |4 m/ |
|