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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- k g2 R- v6 G( f6 N& S
input mcasp_ahclkx, d) |% V7 x1 v
input mcasp_aclkx,
- o& N+ U# f2 U! ~* Xinput axr0,7 d* ^* i. x5 B4 q- g( c- Z
e7 T; V7 V( Z( \+ G9 qoutput mcasp_afsr,2 L- m3 p3 y$ G( _, g
output mcasp_ahclkr,0 Z: V* p& i; [% U- W7 E
output mcasp_aclkr,
a) f) ?, x2 r& zoutput axr1,, k5 t7 S# e% j2 t. Q
assign mcasp_afsr = mcasp_afsx;
5 T. L$ }; u2 n1 ?1 u S4 Iassign mcasp_aclkr = mcasp_aclkx;
( r' C2 a" k- ^assign mcasp_ahclkr = mcasp_ahclkx;# B0 ]/ G: T+ E' N; d/ b1 L9 a" C
assign axr1 = axr0; + E/ b( Y9 `- }* B7 p" m
. [# z5 Z9 B. F% P G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , C" k2 }2 K+ e% W- j
static void McASPI2SConfigure(void)! Z/ Z. m3 \5 j: @
{
; D9 r" l, q# P. q }; gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ I& w$ r' z3 H2 X3 I1 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 ?2 z* y, m+ g% W! p" S3 V. {9 @- D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' i" H6 N; [" }: d* k9 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" R! s% e( P) ^5 PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) C2 x' e9 Z# S7 q2 N a& Z
MCASP_RX_MODE_DMA);0 z8 r! @/ W C5 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, I* |, U3 H: {3 w/ g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! X" j# @' L0 P1 u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 ]8 V: b: m: R( X- ]& X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; `: c5 p# y. q, ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, N* {0 F2 Q, r, _! p" o5 }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& w/ H2 W8 M- F- T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 j: d' W3 ]7 |: H: i- t* d' G& d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- s1 C) a" [; o7 S3 D" [/ l" MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ e( s: d) j/ h. V
0x00, 0xFF); /* configure the clock for transmitter */
, ?* R3 h' k; N# z. OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ z" g1 L- Z j; e% J, `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , Q. F: X* S$ q+ y. E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; M$ V r- m: ?0 ~* k/ {+ C0x00, 0xFF);
8 V: G' d7 ]$ U2 \6 T0 t* K( p, N7 y, o& }- b) h! W
/* Enable synchronization of RX and TX sections */ " K9 n. n* G9 ]# m# F( I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! J+ p$ T; Z P6 j- h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 X# X2 g' W7 W7 T$ Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) [- H$ P* r b4 ~) _8 Z0 i
** Set the serializers, Currently only one serializer is set as
, C$ D( N$ ~. k0 p- q8 \** transmitter and one serializer as receiver.# D2 ~( I0 b) f$ |9 N( `
*/ o& p7 E" I9 ^) e- n/ `3 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, X9 H+ `( V1 r9 ~7 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 w# _5 |1 g4 e6 S/ o; N, z( n** Configure the McASP pins * R/ O4 {+ m4 \
** Input - Frame Sync, Clock and Serializer Rx
* _. P" |; N: ]7 R/ F* l/ G/ B** Output - Serializer Tx is connected to the input of the codec
) ?7 {2 ?" Y1 Y. K7 m*/2 K+ b G" W- N' u% J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: _6 J% [+ v4 u0 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ T$ ^/ d' Q: X3 c3 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' n. c2 {$ N: r. Q V- A
| MCASP_PIN_ACLKX$ s( P, e% P* ?9 n
| MCASP_PIN_AHCLKX. n8 K5 s0 n- D- G5 \+ f7 {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! \$ m! O5 L p% O! k8 j; gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / _& V4 B3 r1 [# U
| MCASP_TX_CLKFAIL 0 B) p; I" y$ H& e) U( O
| MCASP_TX_SYNCERROR3 c2 B- }5 ]. K/ y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 U6 Q" e0 h. R. a' [ U! |
| MCASP_RX_CLKFAIL
" o3 [3 V$ p! _9 I) t- x3 o7 {5 z| MCASP_RX_SYNCERROR
( h, Y/ A$ l) {. ?: @| MCASP_RX_OVERRUN);
+ ]5 ~( R# b7 R7 H% X$ ^} static void I2SDataTxRxActivate(void)
( ~% b! M! y$ p' n{8 E0 j' j1 P0 V B4 x
/* Start the clocks */
& Z: P: s" t" A0 T6 e& iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" D9 a% ~: ~* \) I0 Z& I7 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* c: E- a6 A9 r* U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, D$ @' M2 `) L) EEDMA3_TRIG_MODE_EVENT);+ T6 K3 `9 n6 P/ @1 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 @7 {7 Z4 A3 p( `' r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 \* V4 ~% O5 L, oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 A- q2 X2 l3 {: g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: S# A$ M/ b! pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 `) i6 r$ {2 J( J) `* @) W. e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 U# Y/ M% _+ T+ f$ q2 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# K3 E& d- J0 A" F9 O" Q4 R) S}
, i# ]$ Q% v* o' ^ A. B' _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % r3 ?% n8 N! P3 J2 N- { @' Q! k
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