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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 ?$ x2 g: R5 @% \input mcasp_ahclkx,
+ _3 H* m |( O0 h. r/ Ninput mcasp_aclkx,
' N. E/ }. h7 W9 l) R# qinput axr0,4 d4 p# J# S" ^( d( k' \& ]; N" t
: X7 j$ Z1 A; `2 |( O
output mcasp_afsr,2 {8 ?5 S. X9 p# E4 z& t4 o. I
output mcasp_ahclkr,
) O2 M+ ?0 E6 `5 poutput mcasp_aclkr,
! ~* d- T. P. @1 }( M% l0 A4 ~output axr1,% f, z% A' t( {9 {) t9 E1 k
assign mcasp_afsr = mcasp_afsx;! G. [6 {. F5 D( y6 p
assign mcasp_aclkr = mcasp_aclkx;
7 I7 p& O* K2 M# l0 }assign mcasp_ahclkr = mcasp_ahclkx;
( c1 o) ]* F" d% b7 ^assign axr1 = axr0;
/ u: C- H; E4 p: ]4 c8 ?. V9 {, Y+ ?2 ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, f& x6 o c! T/ o, x: R3 rstatic void McASPI2SConfigure(void)
* |0 g0 b- h5 D5 Y6 G{% b2 Y" I- Z% F3 v! T. k0 I. k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 f1 F4 L3 [$ l" o6 O# HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ J& t; q3 b* r. u r& N- C6 Q6 tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# u& e4 M4 W) R0 L' j1 [
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: Z. o0 B) h8 q4 l2 kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ Q3 l" _. \9 QMCASP_RX_MODE_DMA);% x" W9 _9 e& M; j2 }1 r0 }6 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ T# j# Z4 e6 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ r1 D$ i) M# P2 V2 L" ~4 CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! \" S* `9 M/ D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! W1 i) v2 u$ k9 x/ c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 R6 H/ ]5 m% K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' |6 Q! E* A! l0 }4 g6 H6 @7 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 G3 P& ]) S0 P& c: ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 V" k5 |! f; f" j$ W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 p+ {7 Y+ f; B& ]" c
0x00, 0xFF); /* configure the clock for transmitter */
$ s8 Z3 @- o6 a5 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# x+ `6 q; ]) G2 y! T3 N# G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 Q6 {8 k% m4 ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: _. C6 K6 \" B3 ?, l0 i) z0x00, 0xFF);
: o4 x: ]8 e/ y1 W/ J0 \
' E" W" [8 F c: J3 Z8 M/* Enable synchronization of RX and TX sections */ 4 J. Q1 V4 f1 x4 O* K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 J) d: o2 V0 _& A! u, KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 U! q# b5 h( Z6 U4 v) AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, k) U' L9 _1 C** Set the serializers, Currently only one serializer is set as9 m3 ]4 |- {. `; Y
** transmitter and one serializer as receiver.
/ h+ y, j! C7 A( ^# U' k1 V*/! c# t. z4 t! | b& j2 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 s' X1 m$ L' i6 J" _0 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; l2 _+ m+ x# z. H/ e** Configure the McASP pins
6 X5 H7 V6 Y+ C** Input - Frame Sync, Clock and Serializer Rx b H7 Z- h( ^
** Output - Serializer Tx is connected to the input of the codec 9 P% n& G& e( D( k, {
*/' A7 l9 P) X3 f- c* W/ m$ |% E! j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 b' I, \# n! ~% G$ V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) `; X# F5 O8 y& t( E3 c) R/ u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 z& z& B' l2 Y; I| MCASP_PIN_ACLKX& Q+ j3 z$ y% H
| MCASP_PIN_AHCLKX
7 O8 j; k- E$ m" y, @1 N9 j" x7 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 O: ?3 V- w( K( W) l5 s2 j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR t& N Z2 ^" S! X
| MCASP_TX_CLKFAIL
. ~4 q3 k, Z9 `( [8 p* ^| MCASP_TX_SYNCERROR2 B0 k8 T" {0 |4 {0 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 f% |0 Q' V% h6 ?; R| MCASP_RX_CLKFAIL5 i0 r3 b5 t9 {! x4 U
| MCASP_RX_SYNCERROR 9 j5 i' t! o e% ~ Y8 I
| MCASP_RX_OVERRUN);
: M7 ~; o$ U' ?. G" d} static void I2SDataTxRxActivate(void)- r: L+ ]7 q5 ?+ C" D! p1 j" B
{
! {! m$ }8 Y- \0 m7 O9 N/* Start the clocks */
4 o5 F3 M, ?* t% K% A+ hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# v- _6 t# t+ y; `. @) ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' h: d/ G7 h4 p% P' u4 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
v* a! e3 O) G0 M7 pEDMA3_TRIG_MODE_EVENT);9 S3 N g+ N0 {3 k' B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / ^3 l' u! [) `" n+ B0 e4 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( \' ^ D2 M* k& H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 f5 c( t h- Z+ U# j( `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: |. C5 A# D+ \+ U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" Q' e6 S( `, y# d2 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& r) v, u( W+ W; c# @& PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: |4 `' N6 o: e( G0 W" _
}
/ I' s) J6 q0 x' Q( ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , c, w; ]# V: U5 p8 C
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