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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, b; r& q, p8 x7 I: E- Q9 o c
input mcasp_ahclkx,% @4 m+ ~4 R' U
input mcasp_aclkx,2 q9 X# A! p* g" c% j
input axr0,- M3 M- Q/ X; g; u4 j
; v5 C m2 X8 K u& Z' qoutput mcasp_afsr,
: `. {0 |# V0 d7 G; }5 soutput mcasp_ahclkr,
$ x$ l. [5 l' w& Y$ L9 P/ S1 woutput mcasp_aclkr,- B2 v- O# H8 k" ]4 h) H9 H
output axr1,3 ^6 A1 _8 o% S+ ^
assign mcasp_afsr = mcasp_afsx;" a' x/ B, F% ]; e
assign mcasp_aclkr = mcasp_aclkx;: a" V* U7 B2 Z" W$ v
assign mcasp_ahclkr = mcasp_ahclkx;
$ e) s1 O$ Z: m; ^, @2 H, rassign axr1 = axr0; ~5 f7 V" v3 ~4 \0 P3 M
2 U& Q) i, D! t. {* q% U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
a& {+ }; k) X4 e! y! [" Z; Mstatic void McASPI2SConfigure(void)
9 A# M' _' I" J4 F! D{* }; R2 _' p. T+ U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* ?: S. n0 Z( _# | I: I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 N/ X& }, e/ R2 kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& C) ?" o. A/ r/ R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 V4 o0 X0 G: C+ t8 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 h' y6 N9 k& E. B7 D9 B& ~
MCASP_RX_MODE_DMA);4 k% ]$ W' q, u- y% K9 c+ O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ N) @ a( K4 ?) g* ~8 F( gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 d3 j7 D- [7 x$ E2 g) n+ [/ Z7 [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; b e! M. W- P6 c! a; J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& a6 I2 S8 o! V* L% F! q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , t l" e7 {1 h! U2 w/ _! j. }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// X% B J/ b& N# `6 B9 v9 e
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* @: F% C' }" C+ W5 U' i" y: ]/ EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 J& ]& ~+ o2 {( e5 K& V: t7 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 o9 b3 [6 [; C; \; g! \! ]* S0x00, 0xFF); /* configure the clock for transmitter *// h& v' D7 h# e6 F9 s8 z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, x0 z% c. _% u# S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 `, _( k/ B1 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% m/ E7 a2 W0 f: i, M+ ]$ |, B7 J0x00, 0xFF);) W$ t$ e8 C) H1 X
. X. N: k8 U0 _$ _- D9 J/* Enable synchronization of RX and TX sections */ 5 E: |( V+ R* ]# V* I* K1 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 _' U" N1 O2 [( ~1 R" }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ y; L' x; }4 T4 R4 R4 bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. m* a$ J+ s7 w- H1 z# G** Set the serializers, Currently only one serializer is set as
8 d" J" _! g- S& \& P7 y# D** transmitter and one serializer as receiver.: A t: a' l! z* i5 x2 g- ?
*/
% L y( d' i& f7 [. \% CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: n# C4 _) L: e, mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ D% C# [+ L- V7 G5 } F: |** Configure the McASP pins
# J; @; w0 X/ h; T h( W** Input - Frame Sync, Clock and Serializer Rx \ T9 q- w1 Z6 F- h* M
** Output - Serializer Tx is connected to the input of the codec
) u/ @) C% [4 ?*/2 e1 x ]3 Q- @' `0 ^! b Q2 Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! @* v c9 S* \9 o( ?1 RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" y7 ]& y w; n6 x+ [; D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) r4 Z2 [. u2 g3 u. I* t/ F. P4 W| MCASP_PIN_ACLKX# @ t4 Q0 f+ C9 F- J% \
| MCASP_PIN_AHCLKX
" H0 _ r$ D c1 F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ e( H, N- ~2 T+ q' A$ yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" t" h) X ^, I& ?1 i$ Z| MCASP_TX_CLKFAIL
; m( Q' W+ l( \0 F5 o. I! v| MCASP_TX_SYNCERROR- ~2 n# y+ h. g6 C( e2 m
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* {2 z) {0 ^& Y, I* M" m7 p| MCASP_RX_CLKFAIL7 a- E+ d2 ?2 H
| MCASP_RX_SYNCERROR
( {9 b1 s4 r! P& l" |1 B| MCASP_RX_OVERRUN);& u4 P8 o0 j4 ]( D
} static void I2SDataTxRxActivate(void)9 S; F: p5 H( e4 t- T
{
6 U+ s9 F- R$ j, A& e- }' w/* Start the clocks */) r2 G8 Z+ q3 C1 T; B* }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 h: s7 r6 x9 d, G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" n( }9 j4 I2 W, V% rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 K1 i7 Y+ \! w' J" bEDMA3_TRIG_MODE_EVENT);
% r! c6 o; D$ AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
u! e+ E7 F1 A) V' g( N0 p, uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* G1 Y1 N/ j3 P# D+ S3 f# x0 j& f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 s O9 f* X1 ]8 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 e& i" o0 E$ Y* q4 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 T! M5 ~0 @2 G: `: f9 d' \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); ]% R/ R3 j" o( e3 H/ \9 q9 E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" {4 {. M k# B} : S( T2 x4 ?" T! y( U9 G! j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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