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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 E& E% P9 s' g5 a" G
input mcasp_ahclkx,% w# f+ D. p2 u A- s6 K. C
input mcasp_aclkx,
$ k4 f% L: h5 K( y1 q0 p$ _input axr0,( a3 m" d9 K( t* D" s8 f: X
1 O9 \& q% I( z+ r
output mcasp_afsr,
' w* M0 K. m/ poutput mcasp_ahclkr,
n3 A" S& z# Loutput mcasp_aclkr,
1 z. l+ \% a; F( e5 x4 o1 Coutput axr1,
( d" n+ T" }0 ]( G, ?2 Y. }- I assign mcasp_afsr = mcasp_afsx;
8 x7 M8 p% D$ s/ b8 R9 Hassign mcasp_aclkr = mcasp_aclkx;* }9 u- L2 p( u. K9 ]
assign mcasp_ahclkr = mcasp_ahclkx;
9 D, r) b3 I# lassign axr1 = axr0;
- f2 E2 ?0 G* F6 T+ k5 K1 f% Y% o1 k- g! k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 i! H; o& ^: s! Ystatic void McASPI2SConfigure(void)
, i! {* z: [' X/ h) A{, K, I1 l; `3 v/ i9 S% ]& V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, B1 H: _( v/ O* F: w# X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" B+ V& L6 U; l% Q) q8 I: T% oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' E5 a @; V* Z+ t' dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" M! H' |1 [" N w2 b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. N; X9 k: M9 h! c- xMCASP_RX_MODE_DMA);
1 {# E' ?" D# W XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. h' l( x; [1 W3 s) }9 Y0 B( YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: X5 X8 b C* H" A& U4 i/ g% H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 _! w# w! f9 x5 z+ G7 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' |0 b# h6 ~, m* t/ QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ^1 L# [9 ^7 O; oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" C6 o4 i/ R: q5 e7 S; Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 E5 m" X1 N; h, L+ TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& F- [) S! W1 R1 U. b; t% LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ C8 ^2 c: c" o5 V) b0x00, 0xFF); /* configure the clock for transmitter */" E) H6 ?0 W, ^( Q' Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, ?2 l& j& Q6 Z& X, U2 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 ~; S! i1 c, D! F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 x" X8 {) {4 V# e0 L! v
0x00, 0xFF);9 U0 u5 k }& A2 u, v& ?6 }& |
% Y% M) L* [6 [7 z) p/* Enable synchronization of RX and TX sections */ 6 o, e- l. [0 \1 r8 b, `# K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 _6 w2 u" G5 w: \9 L! oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( y4 q4 e4 ^4 a1 g) \( U0 r7 I) a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' ~8 P7 ^- L' `3 h
** Set the serializers, Currently only one serializer is set as
' S4 D# H! j. S" B** transmitter and one serializer as receiver.
& v, f3 q' q1 }*/1 C' b/ }5 {3 E7 r9 H$ F4 t' _' c: t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
c( Q5 @* m7 c" W3 M& [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, \$ a q# F) h# b, x) {$ D** Configure the McASP pins , Z$ D7 \& y+ k; ~$ k1 d& z
** Input - Frame Sync, Clock and Serializer Rx! G3 h! A% d+ G% z- |- M% J
** Output - Serializer Tx is connected to the input of the codec 2 N! {+ U" R" P/ K5 v! K. }
*/
+ s ], m6 s/ u, @1 r- z4 y tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, [: L! E& C8 u1 _3 }$ x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( }6 T; e8 q. E& S) o/ r+ g# F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# x$ ^+ B! \& i; Y
| MCASP_PIN_ACLKX7 _) q/ _' b1 D; `& ?
| MCASP_PIN_AHCLKX$ b3 Y/ i+ W; T9 m) F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) n) e. _0 F% D7 f" {7 v! BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ `" ]9 s$ o' k4 {3 @+ b8 @1 v| MCASP_TX_CLKFAIL " @5 \% N* F \; S9 J+ o4 p
| MCASP_TX_SYNCERROR
. t* r! x: K; T8 h+ g* l6 S- m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) q) x" ^6 z7 d+ L% i' z' E
| MCASP_RX_CLKFAIL7 w7 E5 O5 f' J. M2 C9 w
| MCASP_RX_SYNCERROR
* ]% z; n- h9 u+ ], T- ^" F| MCASP_RX_OVERRUN);' _0 r& e5 z6 f: I! q! Y$ E
} static void I2SDataTxRxActivate(void)7 j. i! p0 p6 L
{
6 t% ?6 P: A- a5 g# u/* Start the clocks */
: l" B6 r1 M$ X& sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! f+ O7 a! k* w5 _1 s o) h, O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- ~1 ?0 Q1 N- [- REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 g# J: X# t! H; ~- y5 E
EDMA3_TRIG_MODE_EVENT);9 B) r3 o2 F6 L7 {: C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 V. \8 V! J- o6 e8 m* jEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: n* n: n7 @- ]- c( v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 u" G; [7 L( }* Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; r! S" w, n" D, k: E: R, Q; A# v/ g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% t+ a* w; d2 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS); v) a. t; [$ H; r" U3 _1 v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- b$ `& L, N9 g/ ?8 B
}
s2 @3 e- d, e+ E& ~; E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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