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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ p# U! m- I1 h% f/ T3 }) A( J
input mcasp_ahclkx,/ q. n) J# P+ S
input mcasp_aclkx,. `9 l1 }0 n+ G/ N$ x5 ~; n& `/ r
input axr0,
: ~1 S7 j8 R$ p, s1 v+ d
' L# a+ Z. j% }output mcasp_afsr,
/ F& k( I2 @8 m2 V2 ]% l) aoutput mcasp_ahclkr,8 Z/ {# W7 O6 \ ~1 t
output mcasp_aclkr,
7 L) M4 N) G/ M' H; coutput axr1,. F4 ^2 s# M4 i* n; [" o
assign mcasp_afsr = mcasp_afsx;
6 u( [/ ^( p6 i* A! t+ }; cassign mcasp_aclkr = mcasp_aclkx;* y+ d3 Y c/ z! q7 g& D
assign mcasp_ahclkr = mcasp_ahclkx;
1 G; X- T) j+ t. J; D- F: Vassign axr1 = axr0;
: U+ d: R! H& a+ ?1 v3 g% q
9 P5 S+ G* H) @& q( s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 ~( X7 N+ V/ }8 D( w3 ]
static void McASPI2SConfigure(void)
8 V7 ~" v$ _/ T* f{
* q2 ~' Q& [0 iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 \+ r+ c0 i0 Y: n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 a/ N0 ^: ]6 p0 y/ x6 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# q( w p3 y! g; _ m! d+ ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- {7 e! ]% X5 s3 C8 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- H- _* [ o& y% jMCASP_RX_MODE_DMA);! o w! d2 L4 c) g$ y; q8 L4 Z( ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ J# L8 T3 l1 s4 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 u$ B1 Z+ }) u% J: p( A3 I) v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; B6 [8 a4 u4 p" L6 w* c9 w+ ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% W$ K9 x. {' T9 q2 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 o% t' y; b/ U/ N/ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 c" i6 o& u# R9 I/ D5 S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* g5 r" y# R. t: \$ u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : t1 J& S# l6 ?0 `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* ?6 a# V& a1 W) L, C; l. j
0x00, 0xFF); /* configure the clock for transmitter */: |9 i* u* y5 W: O, M: @* r- A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, L- Q5 T$ y0 S0 G1 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! W2 x; k2 S' b) @ NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 a; |- h4 _( j' d+ d' z0x00, 0xFF);: x: Q; G- f8 F, g
9 }' A7 Q/ s7 ?6 X' s) l3 @$ m. C
/* Enable synchronization of RX and TX sections */ 3 l, Y" Y" |. L. P2 q" }& K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 c1 H6 s% c. ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% s" z- m8 z1 z* \4 Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, v& C; {; D5 r# ]( q s7 H* f** Set the serializers, Currently only one serializer is set as
- u3 R! |& [6 Q* Z** transmitter and one serializer as receiver.
2 D' \* x/ O/ J4 @1 y*/+ d5 H. K6 X% Z/ r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ U; n: e2 M* z" K) D/ gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 q0 T& N/ b: z' R# u7 Q- W** Configure the McASP pins N" S& Y- S j' N# O4 E- U. r
** Input - Frame Sync, Clock and Serializer Rx6 L5 n ]6 B, }7 `' ]$ d6 C
** Output - Serializer Tx is connected to the input of the codec 7 f7 B: X9 g/ J# f
*/+ m4 N3 N U1 x$ L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 i6 {& p1 H1 Z7 L4 J! Y0 C, GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* F b- \" F8 K9 f2 U6 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& n; w6 t5 M0 J6 X& r9 G; I| MCASP_PIN_ACLKX
8 F0 _! Z# E9 a' N! Z' p| MCASP_PIN_AHCLKX
5 A/ @8 Q! `# T# G7 D8 A- \, e1 S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 s, s# G6 y/ {5 [1 g8 o: W. d) GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 l& o6 D8 z$ F3 T7 B$ ?7 g' || MCASP_TX_CLKFAIL c* a j4 o, p5 N( |
| MCASP_TX_SYNCERROR' j- D+ v+ h/ s; p2 m) R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( m% \) s" K+ h7 P2 [4 t! N1 c| MCASP_RX_CLKFAIL# R6 }. M8 q' [1 v3 h
| MCASP_RX_SYNCERROR
( ?; ?* x/ j6 @| MCASP_RX_OVERRUN);
- W/ O# f% H2 g8 J- N; o7 J$ ~3 b} static void I2SDataTxRxActivate(void)5 C$ }" ^" J( a& L
{
& m* o! i+ T1 `4 ~" M/* Start the clocks */; M( q2 E, ]3 g9 Y# k0 P7 u$ ~/ e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); J( m* T8 |" v! r2 o. i4 d3 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 I: c/ i0 W$ H2 d- m! Z- t. LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# |- A" \& p, _$ N! R4 j. ~EDMA3_TRIG_MODE_EVENT);
/ e! S! d! w# d$ A @/ bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' L0 {2 @; ~. ?- ~8 b# b' \, q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# m7 d* _3 r( q* JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& k9 Z4 d2 e, B1 l q" k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ _8 |/ q/ p5 _' E7 Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ A2 t$ `$ X- L' p) [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) q2 k1 k9 e: U! ?5 i( q4 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" e6 W- X+ }+ q. s! t; |& T, _} 7 v/ Q, D+ |/ z' k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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