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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; r5 g m* ~4 t# W7 S! o
input mcasp_ahclkx, ?7 _. N5 Z! w
input mcasp_aclkx,. W4 T( ]4 u' t% m+ {
input axr0,' `4 w7 `* H" o: z- `
" z& ]1 t8 |% P, R: F9 z- Doutput mcasp_afsr,
0 p5 G( I! Q3 B7 U& Foutput mcasp_ahclkr,
1 |! b& u0 Q: Q- k5 m" |output mcasp_aclkr,
, ]7 z& o( d. g/ X2 xoutput axr1,' {8 ^2 W& d1 \. o' R! L" L
assign mcasp_afsr = mcasp_afsx;
6 I& Z |' h" W0 d: Eassign mcasp_aclkr = mcasp_aclkx;: y2 d3 f7 c; G+ M. \3 N! ]
assign mcasp_ahclkr = mcasp_ahclkx;
1 B% q5 M( E4 z3 G* b+ ]& rassign axr1 = axr0;
+ B% f" S# D5 M0 x
' h* F1 x- b% Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 C# x8 J( [& B
static void McASPI2SConfigure(void)
8 R: [# |: \# r8 y' Y+ }{
- u8 @7 O+ ~ D) d" L, }: x; uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 ]( L$ J9 N1 DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 Z0 X% y8 g8 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; n( C- q5 W2 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 k' y R6 h7 e: Q$ nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 Q7 M/ A% D8 p. f% i g
MCASP_RX_MODE_DMA); h, r1 l1 u1 Z# M8 o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* ?7 {! H6 [$ @9 f: r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& d. w* T2 U- F: o+ z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 z+ F. R* F' W& k. s) SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. C0 D2 p$ o' h) {7 |7 r" Q* w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , h7 n% J9 w8 j- A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) h6 u( G9 L5 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 r, }6 s7 U$ s1 |) w3 v
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - y& d! {8 e. y! q7 }# n* [# S, m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 G0 @, _) B9 N
0x00, 0xFF); /* configure the clock for transmitter */: _' o$ u' H( \0 v6 y2 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 K& o @- |. ?- g" H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / H/ U, U. _& t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 F7 S; ~7 ^8 C- ]3 E0 E
0x00, 0xFF);8 S7 l; c) l. X1 t8 w6 Y' U
0 [% u7 |( U* I* O) [- j+ w8 Z
/* Enable synchronization of RX and TX sections */
+ o( N" N$ d4 w1 f6 e" n3 A" e7 }9 v1 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: C6 Z4 [2 _) `) G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& O( l' n8 @- o" W, q5 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) |1 y* u1 P5 f+ W' M" K3 X _% z* K
** Set the serializers, Currently only one serializer is set as
* F G& \# T k0 n( }; \** transmitter and one serializer as receiver.
, L$ F# \( A1 W; E d! `*/
& s5 y, x+ Z) t0 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); e: ` a' _# b) |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 M# U* X7 X& [8 d5 m/ p/ T4 K% y
** Configure the McASP pins
& D7 |. q; P j {3 y** Input - Frame Sync, Clock and Serializer Rx) g; b' A- X& i* W& X1 L
** Output - Serializer Tx is connected to the input of the codec - k7 {& }: }. E0 B
*/( s! m- d; i3 f" A% \: ^- }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
E E! D% a" O: C; u) N qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 o' A! H3 l$ ~( g+ u. FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( {8 T3 j V3 K; e/ P8 k- G| MCASP_PIN_ACLKX
0 k9 R( V) G. U$ f& s" J| MCASP_PIN_AHCLKX
- y6 |7 \$ N& Q" e; X$ W4 p; [: T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 |# j8 K+ Y! H! XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * U: r# W) k! Z' S5 S+ y
| MCASP_TX_CLKFAIL 3 y5 w1 U& }1 B( G% j* p( T
| MCASP_TX_SYNCERROR b: I. j! C8 e% o1 ]2 T# `! B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , f r5 D$ A% A; F
| MCASP_RX_CLKFAIL6 {) q, o7 w& J4 d$ N& U9 j
| MCASP_RX_SYNCERROR
2 W6 h. j7 ^( w, O( S p; b( p| MCASP_RX_OVERRUN);5 w# q# ^, Z& R
} static void I2SDataTxRxActivate(void)( t4 j: J* [6 i- w5 b7 }
{
: Q; ^. c0 b, { h3 E% c8 s4 M/* Start the clocks */- K8 S2 r5 p/ I. r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 H) ]8 M4 r6 Q% s7 ~* PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// z3 h- X( S' m8 }5 W. U6 R: L$ T2 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: C5 c3 ~0 [& f& k5 Y% w& FEDMA3_TRIG_MODE_EVENT);; u; y6 d1 D4 w, N( N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, e) y6 l1 Q# i( n" J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( Z9 z! h0 n' ^* O# z; |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, C+ n2 o: ~) D4 ~& o/ g" p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 G! K; P" ]; ^" [% T$ v' d4 u6 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# X' G% L, n1 W* g% X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 V; v! d# j P m% {: U- y9 lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 y- @7 `# H+ O" }1 e% e" a} $ ?& G" u1 w+ F- n5 q! k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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