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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. G9 O4 M7 F, T' R! A/ r2 a
input mcasp_ahclkx,, k1 A# i0 v* N# Z6 z( v# }3 z
input mcasp_aclkx,) |. R; C5 g* N c
input axr0,9 d% s' ?7 ^# o" M" \
; h) a8 m" ?& I5 Y4 W/ \) T0 Foutput mcasp_afsr,
, r" J1 W1 C/ r* w Joutput mcasp_ahclkr,
# _: }1 m2 H" O4 Qoutput mcasp_aclkr,
3 w& Z" G# Q7 H3 T0 routput axr1,# X: C N8 K8 s) y6 _
assign mcasp_afsr = mcasp_afsx;
& e0 T7 T% A& Aassign mcasp_aclkr = mcasp_aclkx;& a2 L) X. z1 H& Z
assign mcasp_ahclkr = mcasp_ahclkx;" d; ^7 D3 L) Y; P6 ~, }1 V
assign axr1 = axr0; % ^ E! h# P9 Q* M2 e5 `
: R, I9 W8 z6 j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * p! w2 x* v1 O; }* K$ a+ N. A
static void McASPI2SConfigure(void)( C v. L1 R6 G
{( a$ R- z# L3 z- O2 G2 m& l9 z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- e i, t: X* W/ _3 dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- Y# B* h' c& [3 u- K" q i! FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& G" k- u. ^# w* Q. fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* N, F% F* Z1 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 \6 s! @5 h2 q1 t/ M4 H" h; FMCASP_RX_MODE_DMA);
, ]3 y9 ^* q6 x+ `- G/ t7 W' D' SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 B$ i$ d" Z. ~4 ~2 O: r% [' f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 D0 Y" O0 e" L6 a3 j2 L0 a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; n) W" g/ c- ^1 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 I, ~, N9 R& @- S- f& f3 I0 \; A5 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 c2 ~' M+ [9 b+ K9 j ]; p; F/ pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: A% a$ x! l: H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* S% ]# d2 c- O# ^! h: E3 P9 J2 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; V$ U& d3 L. N2 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 N- u, l8 I" d: \- I5 g! H0x00, 0xFF); /* configure the clock for transmitter */# V/ f A/ `# Z/ ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& Z F3 X. D$ t( V1 m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 {& \5 n9 E8 J: l I( cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) A8 V0 z: [- z
0x00, 0xFF);% A2 D' k6 T0 T$ h+ P4 b( N& z
+ ?: f/ J; ]# F" C/* Enable synchronization of RX and TX sections */ ! c0 I& J6 s }! @. V1 e p! v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 f# `7 a: \9 ~: kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 Z# X) ?2 o) S- H' m4 S- W7 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, E0 G( s8 B. [' `/ O. m** Set the serializers, Currently only one serializer is set as
; M2 s; B) w$ o** transmitter and one serializer as receiver.: Y1 f$ T, V* E) q) \
*/: k- |1 U5 Y( W0 d7 w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) q5 l3 s( T' r( z) |8 L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 G) B* A+ M7 V5 t! `& `' H8 {) S' k
** Configure the McASP pins
. I/ g/ c6 _/ J** Input - Frame Sync, Clock and Serializer Rx
. Z* L7 w0 `4 y5 W3 w** Output - Serializer Tx is connected to the input of the codec / F4 k" Z/ @; H& n$ p
*/2 W0 I: o% f& @3 Y% Q7 P) O% Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 F( g1 Q( I3 k2 F* ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 i' Q, t$ x* f4 NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& U% H' c" d$ g& N' I" U5 g7 z9 y
| MCASP_PIN_ACLKX
Q* _" \) ]# H5 q| MCASP_PIN_AHCLKX
2 h/ V4 d; Y8 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, x5 N/ T" E4 F$ W5 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 T& u% G8 W( O# O7 S) K| MCASP_TX_CLKFAIL
8 @- j" j- ~1 a2 q| MCASP_TX_SYNCERROR
2 s4 E9 Y2 f4 Z" z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , h3 b' v( l, u# y2 |8 c( o8 A4 ~0 ?
| MCASP_RX_CLKFAIL
- D0 t3 ~5 p$ j" x# X9 a7 v; O| MCASP_RX_SYNCERROR
R) v; n, C/ P: U; r* F| MCASP_RX_OVERRUN);# f; R+ T2 U: r, t2 m+ K U
} static void I2SDataTxRxActivate(void)
+ ]1 v G8 n+ D, y3 S{5 w* j6 [; l; E1 v$ n& ^
/* Start the clocks */
3 G) d |5 |7 P4 W7 YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 U: A: J) u! b9 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# r, J, W) V( N, t" b5 i4 H# x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' v O* E. N7 Y% P* A8 y, j P0 nEDMA3_TRIG_MODE_EVENT);" [4 T+ Z) ?! m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 v: Q! p4 G( C- i( O8 cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 |0 g2 A! j$ R/ l$ w$ VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 C' y; T5 z+ l9 K* f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' g* j, E2 e$ U( a5 c, w( Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- |' D! I+ Y) A! j7 B z3 a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 {) ?( a9 U) I4 W0 J C$ |0 n! ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, R* |8 \7 `# P! }: U: U( [} 8 L9 Q# k* Y) u/ _" O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' Y# M# y# W8 Q$ U: d, w
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