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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; A4 L9 T+ d: B, c- }
input mcasp_ahclkx,1 r" j2 ^0 B% A( ]" D8 w
input mcasp_aclkx,
3 y4 r" T' @& @& @: z+ C( ainput axr0,
# G6 T7 [/ a0 L
; l# a! u U3 N+ y W6 E( p4 l( Koutput mcasp_afsr,
8 I c2 d( w3 @1 q0 koutput mcasp_ahclkr,2 x6 G2 b$ w' K8 A4 i
output mcasp_aclkr,
4 R" S: u! [/ d% e# C% Houtput axr1,
/ V- [" u0 g! X( O assign mcasp_afsr = mcasp_afsx;: m! z7 i7 P+ T- E+ I: |& G Z! G @
assign mcasp_aclkr = mcasp_aclkx;
0 J1 f& ^: }$ l' o1 _. N+ Uassign mcasp_ahclkr = mcasp_ahclkx;
" |- Q* g" Y% z# Qassign axr1 = axr0;
/ j; C) P4 P4 \2 q( N: K4 p- b0 m% m9 i" T" d. ]" S4 C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- b$ a( T R: A' Estatic void McASPI2SConfigure(void): }' ?, R2 U8 K. L, L* `; Z9 n3 W
{; i# k- |) a5 k+ |( w0 S6 p, d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* g' S% q' d7 M0 h i) r$ b0 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 F' j0 k- W* w9 a) P% j, @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" F" s' u8 ?# q1 |! F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
: Q+ _) v7 m( Z) M4 K+ p; T5 XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; g# ^5 R- H8 W% p- PMCASP_RX_MODE_DMA);: o3 Z8 g8 R8 v: A$ @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 x3 o5 t9 ]- ~3 w2 s% I3 g+ h, I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 A7 [' m) E6 Z! Q0 G/ O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 L6 P& r, [& {) g9 K& r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ F7 t! f6 H( ]3 @; ~) o5 J1 ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( W* E5 q! a; j/ qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* B7 m1 z, c& x9 h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 D6 X0 e* o; z$ ?2 n8 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 a( L% j4 m% u3 p( l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& D7 x8 u5 J; k1 n+ [0x00, 0xFF); /* configure the clock for transmitter */1 i6 R( k g/ P* L" h. \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- S. m* @* T% a1 o0 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + ?+ C" ~& `- u7 v `- z2 D$ v( p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 Q7 Q/ v! q! [- m$ v9 v0x00, 0xFF);% m: N$ J4 [& q# ?
4 Q6 b+ n" D: N; i4 I/* Enable synchronization of RX and TX sections */ ; F, G0 u* P, Q0 s" E* u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ @1 E, x, W+ ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 e- f! m( Y5 Z/ S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 Z: D$ D$ W" g0 Q1 j** Set the serializers, Currently only one serializer is set as
# M% D9 H. Q7 S: i7 b" j** transmitter and one serializer as receiver.. C7 V& n M$ q' u0 w8 d
*/: w+ `& O3 r9 c# ~3 O/ X4 G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ z" `) n- F! F. B9 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- e% n* O, c, o3 w. s** Configure the McASP pins " |0 o7 T8 S9 P: u! D8 v; x0 ^
** Input - Frame Sync, Clock and Serializer Rx1 M% N9 O8 \& |2 U% v/ J
** Output - Serializer Tx is connected to the input of the codec , F# E6 P& L! J- u3 C" r
*/
& C5 E( U# p# v! \ k' b' a1 M# SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 l* M# S) T8 i3 R7 J7 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& X7 \9 B* L5 {/ T; B% nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. ~) K3 E! I' `: b1 c
| MCASP_PIN_ACLKX
( X8 H4 F; B3 r. I u| MCASP_PIN_AHCLKX: v& B" r: o& k3 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( @* s3 R2 c c, J+ i4 v% H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 D# U" i- M: q$ @( a| MCASP_TX_CLKFAIL # h y R5 w* w4 x% k; ?
| MCASP_TX_SYNCERROR# G8 @% `% B! |1 A9 ^" t" O. M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ ~$ Z4 I' L1 \! f% V* p3 l# a| MCASP_RX_CLKFAIL
# J" o9 D9 R; D| MCASP_RX_SYNCERROR
. q! B3 ]! |( Y8 v0 X5 C( f8 f: K| MCASP_RX_OVERRUN);
& ^4 W) |: l0 c3 t} static void I2SDataTxRxActivate(void) n1 h! q6 W+ a$ C$ X' P d
{. o: O0 j3 i6 X* K" P8 u$ n
/* Start the clocks */
: O& P' _/ R4 lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; t8 _# J9 i# ]0 ^8 E+ ?3 j* z9 \7 [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 {7 Q; Z6 d6 h: g* X/ Z& E3 K0 J" R% hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! \, N4 s" @: Z8 U! cEDMA3_TRIG_MODE_EVENT);
# O, ^; w3 k" S# O% b+ M4 n. yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # F* g4 Y2 s. o" D, {" e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, H8 R7 ]/ c: ^ M5 N( g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ R7 ?3 [6 u7 q( e/ l h* M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( r) U( [' E) X4 t$ wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 W3 r+ B2 h, H2 ?" @. Z3 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% R4 y2 y3 ], P2 ?/ z. r5 wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% b# }6 P) l% B: o; |1 Q7 r
} 9 _0 J( q0 I% k; x% w4 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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