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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& |5 o! n% D! P3 T. y- @
input mcasp_ahclkx,
! [* A. u4 e# }5 P% iinput mcasp_aclkx,
8 q' x0 E7 L7 R6 q& Kinput axr0,# W/ ?& C# `+ g- R
9 b) v* O+ G! s# _- M
output mcasp_afsr,
5 s( R3 R$ }* qoutput mcasp_ahclkr,
. d7 y; x+ ~1 U" p! Joutput mcasp_aclkr,
/ v6 `7 Z. K. N& t) `# q) ioutput axr1,) o8 J" P. x; e/ x7 e7 W+ v9 w
assign mcasp_afsr = mcasp_afsx;$ S4 A# M7 f: i' c3 V
assign mcasp_aclkr = mcasp_aclkx;
7 L0 {# H( @3 F/ h" ?9 Qassign mcasp_ahclkr = mcasp_ahclkx;
% ]: h! _( G2 |assign axr1 = axr0;
4 u5 @ V, j. x: r: `! I6 X3 x z V" C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; d" A5 y: D4 A+ x
static void McASPI2SConfigure(void)
- e. {2 u/ K! z& ]( _1 J{* x% N! C3 R9 J% ~* n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 I- u7 z' m, M- g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 h: Z$ A9 b6 v4 o5 D2 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 i; }& c h# B# b% x+ D2 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" s; T, \ i6 n9 I" r" vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 X( s1 d) D& t2 A1 c: ^
MCASP_RX_MODE_DMA);7 e* N# L `5 ~! b& V- |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( W" E- d) p) x% W6 K4 h: l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 z3 z6 A2 Y% n" x4 z0 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* }2 _8 Z' D' QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# v4 q$ q* [- N1 ]- ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 y& b" b* s& |6 O- M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" M; B- S2 D, [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 M. J# i# x7 t! B2 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* W5 i& Y: @; D. F% J6 H; _) I# s( @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( t) k2 O9 D! g9 e0 a0x00, 0xFF); /* configure the clock for transmitter */9 [% n7 `# d+ Q' a$ h$ W+ a) U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 d1 q! C- T4 R) b jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * i5 E& R; n! y0 ~# c+ |: b* J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" ^$ V' i) O9 A/ j, q0x00, 0xFF);/ F6 b& `! n, S3 M" R
8 m3 d# _. c' k) g" X
/* Enable synchronization of RX and TX sections */ % M: J C/ W$ b1 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 y# Q0 {$ G. t$ d3 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, s) z& \" W( B9 |6 ~7 w# Y! nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 l3 s! D6 ] h, B$ R- w! K- y** Set the serializers, Currently only one serializer is set as
5 v9 {: c9 u! {4 A** transmitter and one serializer as receiver.
; o7 ?# p1 h4 ]! X: K*/6 \) S$ R0 G4 g5 J) {7 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ {6 N' m2 ^0 x( CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 k7 R8 q3 t" C5 I& [8 _( B& A7 b9 s
** Configure the McASP pins
* T7 y% `1 t* V, G8 T* X1 I** Input - Frame Sync, Clock and Serializer Rx- t3 r( z% k& g6 R! c; q4 Q
** Output - Serializer Tx is connected to the input of the codec 5 a% g1 @1 P8 {5 l
*/- }0 m! i( _) a! \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. h9 D+ j# f$ SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" u( ?/ z6 U7 a$ L2 y% ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 u( b- G+ W8 t6 o f% k; ~( @6 i| MCASP_PIN_ACLKX
& ~! f0 ]5 P! E- C" v* R! [, W| MCASP_PIN_AHCLKX/ ]" u w8 W( L2 D8 o. F3 O" c; O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
x0 ?( Z- \& T: QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' a; C- D; i( P- ?0 Y, f| MCASP_TX_CLKFAIL . Z5 k! z) Z k+ W
| MCASP_TX_SYNCERROR
p, J, k+ \* v; W: e& m* G" {' ~7 v! D. ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* O+ p, _# L+ Z% o6 n3 s( y7 B! y( w7 y| MCASP_RX_CLKFAIL
% y( W: f% n0 R* J$ x$ G| MCASP_RX_SYNCERROR 3 U! o! \! a* z: ?' J" z) i
| MCASP_RX_OVERRUN);
" U5 R _- N/ }2 F: r+ j; Y} static void I2SDataTxRxActivate(void)
$ F8 U- k k5 \: `{% x( S4 i/ J2 |
/* Start the clocks */
7 ~6 f, U" y4 t8 r* A& I+ ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 A- v0 T& f$ @$ T; [3 D: p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 A# H- M; N1 J1 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," Z0 O" F$ y+ H
EDMA3_TRIG_MODE_EVENT);: Y6 k( Q$ ~" X& R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 U. ~; S0 O! F |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ I6 [% ]4 B w5 l `' u2 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# ~# w- g0 G) D4 j- Z+ ~! ^8 I3 C3 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( d3 U0 M- B/ I& o* U- uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. ?. _& q9 n, n" T# Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 x5 a* r+ s S" cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
V0 f& j$ k9 }: O9 w6 D0 C}
8 X$ {3 g# J8 Z2 v; \" f: |- M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 U" g) M4 z8 a+ N
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