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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, q( r- v9 h2 V/ O: h8 E0 X5 L( V
input mcasp_ahclkx,
9 `( X8 P# X1 H4 k6 Q0 \' ^# M! Pinput mcasp_aclkx,( F, T+ q" ?+ x' |
input axr0,( F1 X1 W; V* {- n% _
9 h5 q# Z0 \0 `6 Y1 M6 woutput mcasp_afsr,
: Q# u- c: k0 Routput mcasp_ahclkr,. R4 i" [1 M" L1 M; |4 m
output mcasp_aclkr,3 m2 o3 n: F1 |/ R( ?& i4 t! x* d
output axr1,5 |9 ^1 b# w/ n; w. e, u+ N
assign mcasp_afsr = mcasp_afsx;
M! b5 b. s; M1 zassign mcasp_aclkr = mcasp_aclkx;4 P' y% p, A# `
assign mcasp_ahclkr = mcasp_ahclkx;' o7 e" U( i. ?) ]: I
assign axr1 = axr0;
, z [! g) D0 ^. |/ e% i8 E$ M/ t4 l2 y6 B/ O, r7 m. K6 ^8 d, s
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! r, C, n. ]) N9 R; {0 \
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 G v5 S6 _8 L4 l* ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# d3 ?' s! g& _$ z: O0 N: S" rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ k" ^, r$ _' m9 |) H: n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! }" G, {% l, `/ P8 Y( `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 U5 f1 l, L+ T6 C
MCASP_RX_MODE_DMA);( @# D6 z$ d' j4 B) P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# I# d( r! o# _/ N5 y X k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 k; u6 O) k( ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 v' h; v0 ? b2 \7 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 v, p% y) g- w; P& PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ F% `2 w- p5 T) |7 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- \; g( S% {; m: A# ]: b3 N6 a3 w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 I0 m+ U& l9 k/ I: s1 L0 ~% lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* D+ }+ Y# k7 m" K, q& q& WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ z% b; O' N: m, ^+ i0x00, 0xFF); /* configure the clock for transmitter */
" ]% T4 f( T- K/ vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# z" N) K! ]' r2 x, n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& V. D/ q- |. N3 L8 u5 N3 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' J/ b8 ?4 r$ e1 m0x00, 0xFF);
9 `7 g: P8 Y! [( p7 x- V7 |. N# Y( p7 K1 V4 q2 b
/* Enable synchronization of RX and TX sections */
- t) q- e Q- N! ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& e3 H! g, M: d' s& b3 T4 J# `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( Q @! F% O5 Z& f1 J9 o( B5 d* wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 j/ |) ?! N4 [
** Set the serializers, Currently only one serializer is set as! M9 F0 M% Z% l' j) n$ H/ {4 D4 e
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: h/ `2 p+ u% X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 \2 u. J( C2 c* F3 g( d. P
** Configure the McASP pins . J8 i# Z" Q+ x" Z7 H x
** Input - Frame Sync, Clock and Serializer Rx
+ ~5 O9 U) Y/ m' I8 `** Output - Serializer Tx is connected to the input of the codec . `" p" M1 I$ b9 I
*/
) D, a7 G$ P9 ~+ ` ~! JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: L6 x# R/ o* t; _9 R0 f. P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; ~+ O- g4 L( ?) [& {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, |" H, s+ n% k- ]& w4 e* v
| MCASP_PIN_ACLKX5 N3 P" q L# P
| MCASP_PIN_AHCLKX
, w. `& d) a5 l$ F4 @9 y; U/ N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( E) h7 }' ^9 E# ~, f h* @! u2 oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 a. _: C7 C8 h+ `# ?
| MCASP_TX_CLKFAIL
+ t, j `' A8 P| MCASP_TX_SYNCERROR
9 l! ~+ ]5 P7 n# d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* X2 I$ m* e$ P5 B1 Q! {2 i| MCASP_RX_CLKFAIL4 \1 U) s& T' |! ~4 ~2 h2 P/ t
| MCASP_RX_SYNCERROR
- m( Y4 T. }2 q3 D" Q+ S| MCASP_RX_OVERRUN);0 z% J, M) L6 |/ z
} static void I2SDataTxRxActivate(void)6 x0 Q) [6 F& ^% T% @! z2 u$ _: h
{! S/ h8 Q6 \# @ F- a! b
/* Start the clocks */! E2 w8 u) i* g/ x2 R3 ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 [" v z7 Z! c9 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// U, L9 {1 {9 h$ C8 S4 b6 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 k8 N8 T0 E8 h$ X9 ?
EDMA3_TRIG_MODE_EVENT);9 q5 x. e# v( d- l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, u0 J5 e q( L/ i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& o, t( Y+ C: C+ i& m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% P' s. u& q$ @- \& kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- S3 W9 ^6 C3 ]( ~# D' o ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 L: Y- `& E$ r6 pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" A/ C6 d4 j8 B4 r1 f- P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ B/ u4 v9 i* y# V2 @} ' y( ~3 U4 f4 b( `$ @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : ]0 w8 o2 S' t
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