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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, r6 {. C! u- L( [3 ^
input mcasp_ahclkx,
7 L- ~ W1 n% Binput mcasp_aclkx,
" U5 t8 n8 _+ S9 m( O- J. |0 ?4 R( ninput axr0,
; _) |7 ]( t$ T$ @% V
4 a% n [1 u4 {7 t. z0 E$ Routput mcasp_afsr,% p. T/ U# X# k- a6 ]# d \1 [* P- `/ O
output mcasp_ahclkr,
* v+ G' T8 L: I% I( P! Xoutput mcasp_aclkr,
) d- @$ H; r- F$ A' goutput axr1,0 N& n) m2 u8 |. o
assign mcasp_afsr = mcasp_afsx;$ Z& a% ]* t' r* S" n: P; ?
assign mcasp_aclkr = mcasp_aclkx;
8 @: D$ h" n H) ^5 Q8 u2 C$ dassign mcasp_ahclkr = mcasp_ahclkx;
2 l! @ h! [2 H5 j8 |6 Gassign axr1 = axr0; " n8 e1 C% l, S8 M" O! [3 Z
7 P: ^+ H7 h- K" g4 R( v& H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# a2 N# s/ z; u" k2 C W" u5 zstatic void McASPI2SConfigure(void)
) _% Z, N: [. {4 ?! z' r* J; H; ]{! \ A4 A9 a$ A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* h! X0 T: y% _8 k, |0 p0 F/ BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ f) y) m3 K0 T2 M J J% ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 w' z; Y% h& q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 k7 L5 b0 p9 j( C) L4 z" i" D+ u f9 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: y/ J& g. |' n. t
MCASP_RX_MODE_DMA);. f( F6 P* @) O8 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 K, W: x1 v- y: i J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# Q3 ?4 }, C" S6 x% y; M" ^- |# Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: u5 G# {, C1 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 P. s9 F9 }: R' c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 C6 O$ X# a @- i7 f& R/ H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ A5 J) s7 v7 X9 E. s5 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 v0 j N, S: ?0 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( @7 E4 B X6 U& t" u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ n% f3 g$ m4 j) @0x00, 0xFF); /* configure the clock for transmitter */; F" E% Q& z# z! |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, M6 ^9 ]" {2 @2 S$ l0 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 x" f- y ? L gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 z" L! U, H( k0x00, 0xFF);
I3 l5 i4 e( c4 F: b: o z
# g6 [7 `8 R0 q4 U/* Enable synchronization of RX and TX sections */
& Z4 p# G, C% L# h8 \0 C& ? FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) c- I n5 c1 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ ?! s9 _9 v0 D: k# U5 y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 i- Z2 T8 d( q' C
** Set the serializers, Currently only one serializer is set as
; |! |. O/ i1 r# D** transmitter and one serializer as receiver.
2 X3 h) N$ `! H/ x8 n8 P*/
* p' s! j1 E& g4 k+ h+ mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); A! ^' \" i) l9 x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 v" k- S- m4 r, N. l- H0 o** Configure the McASP pins
' d) `( u9 e9 Y1 `4 s4 R** Input - Frame Sync, Clock and Serializer Rx
# \7 I5 G$ c- P, C9 B6 a( }$ p$ E** Output - Serializer Tx is connected to the input of the codec 6 b, K8 @5 P' V& ]2 M1 Q
*/
+ O' ~/ |# z5 I& A% J% _6 r; yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; W3 w, g: V4 z8 A! |6 ?. uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ u. }4 l% D4 D: h2 b+ XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" b& p3 h% C: \1 C4 V
| MCASP_PIN_ACLKX! Y; F! V. V% r: |! R, {3 S- I, X
| MCASP_PIN_AHCLKX$ q: d' w: [6 i( W8 F* k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 D [8 Z+ T+ p5 [5 I9 C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' S0 ]$ |) [" o| MCASP_TX_CLKFAIL ) d' f* `3 C& q6 b, t
| MCASP_TX_SYNCERROR
9 c) w& i& D/ n4 g& M4 K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * ~$ _0 Q7 }: @- a( e4 Z/ X
| MCASP_RX_CLKFAIL
5 ^3 x8 ~4 K- }- x| MCASP_RX_SYNCERROR $ g: |$ x' A1 z6 U7 L* O
| MCASP_RX_OVERRUN);0 \& p8 @# t7 Q. D
} static void I2SDataTxRxActivate(void)
K7 }* R; \. J# x6 f: C" K{
6 n& |8 n6 g* z( K: F/* Start the clocks */
" I$ y; z+ B/ I$ i6 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! \+ C9 y, Z6 g5 w& a- X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! Q+ ]4 O4 L! b+ i3 {8 M- v/ A" SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 U/ b# G1 }" ^1 N& mEDMA3_TRIG_MODE_EVENT);, ~. L& O6 L3 g) Y7 U7 w0 f" a% u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . A: x* }0 Q/ f: F( e" J* w) T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ g# |3 v/ \4 l: T1 x& b" I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 T1 T5 m+ ~/ m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: f& C- ]/ W0 f8 C, G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 y0 M: |! a1 e2 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ X3 Z4 w$ j; h: o' n2 p! W3 ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: j& r: A! G& j' {- u) E} : |- J, x# ~9 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ H6 [3 {8 ]5 m+ U |