|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 ^( q8 _" D6 w: h8 m" Iinput mcasp_ahclkx,
$ ~/ S; G2 q! y# J* y' o$ R- yinput mcasp_aclkx,
0 s# B; M, y7 h: Rinput axr0,
) |6 o6 q/ P0 ?; t0 c
- t8 U [/ ], Q0 {( ?output mcasp_afsr,2 }8 x4 ^# m8 r9 }/ E; C
output mcasp_ahclkr,& L1 b5 Z. U6 ]7 [% V1 _7 W: y: O
output mcasp_aclkr,
7 F0 ^; k' m6 {0 Loutput axr1,. s6 A' Z; C& \! t
assign mcasp_afsr = mcasp_afsx;
. R% k& T5 j, X! M8 T; m: fassign mcasp_aclkr = mcasp_aclkx;
7 [/ B2 Z; l$ k) p6 Jassign mcasp_ahclkr = mcasp_ahclkx;
- \* D5 `* ]1 D( Dassign axr1 = axr0;
& T5 o+ G; x- T& `/ O4 h1 h; D( W; |* l' i( ?8 a6 R6 p; n& i: x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 q; t$ g: a, B. C( r$ |+ L& p
static void McASPI2SConfigure(void)
6 S- c q8 P9 F. \% d{
5 d) E+ r( o0 A2 J+ e [McASPRxReset(SOC_MCASP_0_CTRL_REGS);- w% F6 ]0 ^! j2 f1 Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 l9 M% Y# C h' g9 e* C: SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# H, ^, W5 A, q" T* d: w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' B3 Y, G: O9 nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# d7 ?# t$ M% S* A% w
MCASP_RX_MODE_DMA);# Q. r, c, Y) K. L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ^- q4 w; K$ k& y2 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 j. p/ S! S+ D& {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% H3 `! W. b" b5 Z" g; ^( }# hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 t% z2 c9 B" x8 d# cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ K7 Z% K6 |7 h8 l; l; UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; g! r" w# \" ]- OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 _: ?; I7 i: s" C, v9 a; d! I% B( b, ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' ^; `/ a$ o% u, F0 e+ w3 p" W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' x* n' v# {$ u( B
0x00, 0xFF); /* configure the clock for transmitter */
5 u4 I6 p1 u$ s1 Z4 V: Z5 @7 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ^9 p- d& `+ `5 I( ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! Q9 C( }) c1 ?! B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 D5 H8 A& |. g2 U& _: X4 |6 W0x00, 0xFF);
3 @9 q% E7 w) g" E) @6 n# J
0 |; z0 \, b4 q& |' v( T# r. d/* Enable synchronization of RX and TX sections */ 8 C9 v# s" n* J' F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, W% [" V" M/ CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: d' |: E, |; m7 ^( Q/ g( SMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 h8 ` M" f, a8 X$ e
** Set the serializers, Currently only one serializer is set as
8 u$ j# _' ?/ B! E$ [) v) r** transmitter and one serializer as receiver.: r, R% @3 z3 i7 X$ ?+ ?. l
*/
( a0 y. Q2 Y$ H+ C& i5 F3 g$ RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 S# J% M7 x. W, N- ]) F* EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! R. [% h9 q) I2 a4 G$ {** Configure the McASP pins
* k% u* ^$ a. _9 w** Input - Frame Sync, Clock and Serializer Rx
- X# I. t2 [0 H. z+ ^6 f/ d0 G** Output - Serializer Tx is connected to the input of the codec
2 \' m' I/ R/ g: ?6 }*/+ a- D" U( X: J( N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); i# K1 S- N: t5 u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ e, C* j& u2 SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 d* {0 X1 Z& E8 A% s5 ~
| MCASP_PIN_ACLKX
" y' e; x* f) l: ], A| MCASP_PIN_AHCLKX
; Z( A! V* j" Q# s: A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 C2 _; m" ~9 d; |1 f! Q; n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 i5 `1 \5 [5 G* J" W
| MCASP_TX_CLKFAIL
, c6 Y9 j" ?8 j& T| MCASP_TX_SYNCERROR8 G5 \' a) l- n$ f9 `8 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 v/ |+ l1 o$ @% I0 s3 d| MCASP_RX_CLKFAIL
5 `6 U8 z3 h) {| MCASP_RX_SYNCERROR " J R. z/ z3 N% H2 V- G. D) u/ z2 _
| MCASP_RX_OVERRUN);+ }) V# O) I6 X! {) G
} static void I2SDataTxRxActivate(void)
* L0 N9 W% {# ]( {{
9 g) M6 ]! [" j/* Start the clocks */+ @* ~. {$ j! A! k3 k& y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 y6 f8 b" k% O& z6 L; aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. B6 P5 A" r& a6 @6 y* C" v- FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ g: t" y) n# ~( p- e' Y
EDMA3_TRIG_MODE_EVENT);* _8 j, Q4 i' r7 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; e5 w+ [# D& U* k( |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, a6 J" ?# K" V0 q5 S3 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 V l; \7 s6 J/ O/ t" m$ l8 V% x$ YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 m( m8 \7 }+ q% B7 d' ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* O# r! y( z; ^( h9 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! B% X6 b+ M; L' zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! g& m1 u2 y- M* z0 ^9 R2 e5 ^1 x
} ( ]/ e) R( E" ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / d/ Q. M. ]. n: H9 W0 ]
|