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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 u7 c; c- x9 h: jinput mcasp_ahclkx,
2 y: r; m2 V5 K2 sinput mcasp_aclkx,: \% R& H: R4 J4 S
input axr0,
. _$ f; `, m: u+ c8 C$ }
; c+ P; p' I/ f" H. O* Coutput mcasp_afsr,
) Y* w, r' U6 Toutput mcasp_ahclkr,5 Q2 R9 o$ s0 P' w+ R* ?
output mcasp_aclkr,
2 m' k1 V3 i* q o$ W; b% ?output axr1,6 K3 l4 u) F5 F* l; x/ ~
assign mcasp_afsr = mcasp_afsx;9 ^8 j# {7 L. x9 a
assign mcasp_aclkr = mcasp_aclkx;, _0 h! x( @; C+ r0 w& e1 C
assign mcasp_ahclkr = mcasp_ahclkx;; d0 S7 K3 q1 v" J
assign axr1 = axr0;
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7 U% D+ i5 q* A: X) O+ x- R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & ]5 B, d; m9 @2 M, g1 R
static void McASPI2SConfigure(void)/ M" u5 |" ^1 _9 Z
{* S( i7 |* w# } l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' o( R1 U0 q7 U8 j% i4 [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 @9 [6 e2 i( c z- G! IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 s! b9 ~+ r! _# Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! ~! t2 m9 H! dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. e" D* S: w' _% JMCASP_RX_MODE_DMA);
. _% o( w& M. _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& a* J; t$ c* s7 G r* X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 n% g: u/ Q6 ?0 f8 P1 S; Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' ?7 z# U4 W! [% X0 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% L: a$ d% b/ A7 ^$ g& p7 c8 L. f$ RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , h3 G0 Y2 }8 X& J% O2 D" _8 Q$ Y1 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ L" z/ Z1 @7 u3 c; ?" P; M6 U+ B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 J* x8 E2 V: k# G. w4 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( K9 J) k' w8 u( o$ [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. p9 }* I) Z- I+ _' _5 a- r9 _0x00, 0xFF); /* configure the clock for transmitter */1 h# p! }+ c. o( \) H6 c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% s4 Y0 J, {, x' u( E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - Q% G @! M$ W0 n8 j! L8 n" z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* W2 X$ T6 i) d. |! x
0x00, 0xFF);
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- h; B7 {2 O$ Y8 D+ n) V/* Enable synchronization of RX and TX sections */ 3 o/ W) M! w& p! _7 p, [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# t/ ]2 v9 h! y. I2 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 g" ~) O5 B1 N- U! M: A5 U3 @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: u) f5 E' z' Q# w: V: W
** Set the serializers, Currently only one serializer is set as) d( R. }! {, [+ E
** transmitter and one serializer as receiver.
5 G6 n3 i- d6 N; o+ W; Y*/
% t5 r, c" u8 e) aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 Z( O/ f" T% U) e; R+ [8 J) J! d dMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& J6 R3 b/ ~: f) Z2 S8 ?& O0 d
** Configure the McASP pins
* K X5 r& F: {8 }** Input - Frame Sync, Clock and Serializer Rx
9 l0 u/ T, C; t1 @( v** Output - Serializer Tx is connected to the input of the codec
5 ^% s* G y J& E- {. A+ j*/2 U4 q! F6 K' h2 k. U- V! U3 l! L; I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 Q- [& G$ ?# k9 S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# `+ e' v! `2 c( u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ ]6 n: Z' v5 B6 w
| MCASP_PIN_ACLKX
# u, F* C/ `2 ]8 x- C| MCASP_PIN_AHCLKX
1 B% I- D- f9 T- {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- [+ n |! D b. G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, F# p8 L; }0 _: d| MCASP_TX_CLKFAIL
. V# B" n0 M( B2 k/ c+ D3 z# u| MCASP_TX_SYNCERROR9 f+ I9 g2 W8 H+ n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / E) S+ j ^6 B/ `. v [& t
| MCASP_RX_CLKFAIL
- B1 x4 T G. `4 X6 W| MCASP_RX_SYNCERROR ' T5 K [( K6 w
| MCASP_RX_OVERRUN);' M) I# o; d6 q) s, D0 p+ n
} static void I2SDataTxRxActivate(void)
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% ^: ~, H& }# p/* Start the clocks */, m3 [& \) \1 T* x, M e9 e5 V8 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) d! p; v8 W/ E6 O5 x! c% f6 ]6 M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 i/ {0 w8 C$ P) v# E5 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 A. M& f7 N" D: R
EDMA3_TRIG_MODE_EVENT);
9 Z; K/ D- {9 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ t8 A, p$ G3 B" G5 c3 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ y# P$ ]! C3 \' g( x: b# u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 Q: B0 i( W- g" k" w# |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! X% ^/ O: E8 C# vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& S4 { J& j/ _. {McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ G. s ^! k; f2 G" s4 v( S0 ^. h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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