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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. P( |1 \" `! e* p6 Y
input mcasp_ahclkx,1 m" q) R* x4 ^* ?2 O: h
input mcasp_aclkx,8 B" D" s% o) h! C/ h) W
input axr0,+ d4 t1 O1 l" t( n' Y4 z
' @& X) {# M: p/ R& aoutput mcasp_afsr,
- B2 A( v t7 H( S0 N, [) Routput mcasp_ahclkr,0 x- j8 e6 @, ? v* c
output mcasp_aclkr,: U8 \8 H* l: j! e' f
output axr1,6 }2 F' I& O" b$ s* e
assign mcasp_afsr = mcasp_afsx;
. s' \8 R: B& P( V9 G# X$ ?assign mcasp_aclkr = mcasp_aclkx;
/ J2 w+ {5 n/ e2 n: d( b, h% Qassign mcasp_ahclkr = mcasp_ahclkx;, B: G3 |0 a7 h2 B# F+ I: J3 f/ q+ {
assign axr1 = axr0; 2 E/ u- \8 f- P+ i
v7 [# [+ i: ?& X) j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & a5 W" h7 L: i
static void McASPI2SConfigure(void)5 @7 q; J+ T$ k3 R0 n
{
, {" P4 a0 K: S8 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- S3 k" R2 }; b0 @6 a) Z1 S* _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 N) o; o6 I9 j7 ^1 U6 n" g& FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ q" S6 r J7 V! @( G* m2 C7 F& N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, n+ Z: D) V) m9 P: {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: I" A8 A: O5 L+ ~$ [* MMCASP_RX_MODE_DMA);+ b s& `8 ?0 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 j/ x9 K, t' W7 \8 G0 M2 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- U: Q2 r( M5 b1 s* F$ V% I9 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 g' u( ]* k' \$ M* BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! x1 H) ~8 l( a% u( q6 b& aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * A: c1 D+ o- Y# z$ _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ y4 t% i! j' X' n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 g+ A: \ k% O8 f) bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 E1 o5 A; W# ]; IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, Z2 ]- G) C* x4 t
0x00, 0xFF); /* configure the clock for transmitter */
- a5 q3 q' V* H! T/ y/ WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 H2 w) M' r: A. X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: y N S' C3 a; J. R! @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, Q5 l. f& o* g9 k0x00, 0xFF);6 k- P( n1 f5 K# e+ r' u2 a
) d/ I5 ^9 C6 t& i! }" |& t
/* Enable synchronization of RX and TX sections */
1 P5 J# d6 z& h. ]3 { h' T: wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) C/ i$ N; Z3 B( kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& t3 f) |& `; W4 A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! h0 P7 b3 ]- \& p7 E
** Set the serializers, Currently only one serializer is set as7 J& T5 S$ m" w8 b7 N% Y; g
** transmitter and one serializer as receiver." n: | S: |! m) p5 }7 v4 V* S
*/
) \2 f) A$ z0 H1 \1 f, @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% Y% i$ m8 x+ e* E( GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; v; z( x7 S7 X6 B. y4 ~7 E** Configure the McASP pins
' m9 W, ]3 k, O) x( K; ]; }2 X** Input - Frame Sync, Clock and Serializer Rx
$ g$ Z: d- X( q- W* e) e/ Q** Output - Serializer Tx is connected to the input of the codec
7 C$ X5 a# e+ d8 }/ W; d! k*/: h& P' `$ l9 z+ Z( `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 u9 C9 l) M; z0 @3 C# w! ~+ mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 e9 s+ ^7 t. y& z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ m2 ^) F- w% o1 _9 h* t* M| MCASP_PIN_ACLKX
8 R! F/ q/ T. S1 K" n7 Q$ _+ || MCASP_PIN_AHCLKX
6 a# ^0 J4 Z8 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
^2 X' `% h9 E/ b: OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 C. a+ g7 @% N: D: a" y8 @! [
| MCASP_TX_CLKFAIL 7 q) H) {2 p F( v
| MCASP_TX_SYNCERROR5 ~# C) L! X+ k4 `& u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 n2 b% Z: a% C8 d0 n. l5 [
| MCASP_RX_CLKFAIL
1 Y7 `! @9 } J9 b| MCASP_RX_SYNCERROR 1 {2 t% V# e2 y2 m4 ~' y4 T" n, E
| MCASP_RX_OVERRUN);' q9 O. s6 B& [9 a
} static void I2SDataTxRxActivate(void)9 ?0 l& P) d( A. O6 J
{" p% X% \2 ~ | t) p
/* Start the clocks */
' s% P5 v6 v! g8 `# aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, e: [% S/ S( MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- A0 | w" I+ t- [3 N7 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 L2 b- _& q& z% EEDMA3_TRIG_MODE_EVENT);9 ~) X4 v8 T3 I$ N7 u2 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 H5 E8 D! ?/ ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- d5 r; l% S; c, a9 s% p0 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! V8 F/ A. s! z# r$ }8 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 ?! X& {& p0 i- V% _7 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 H& W. N$ B4 P6 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 P: a4 l4 `8 J7 I' l* t$ RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 Q8 ~) C* E! O# T) P' |7 e
}
4 R' g4 Y6 C9 I+ A! J3 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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