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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 N0 F1 \6 {( t. ?
input mcasp_ahclkx,) b+ Y3 m# j( E! `* h
input mcasp_aclkx,1 p& a2 `% M3 O$ u
input axr0,
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output mcasp_afsr,$ \% E' a% }; y+ O2 c
output mcasp_ahclkr,
4 Q" w$ l/ }5 c: eoutput mcasp_aclkr,7 }0 k1 ^& r, N; ?* z! L; U
output axr1,) G+ u8 F9 q' n# _3 \# i/ u) {/ Y
assign mcasp_afsr = mcasp_afsx;
1 K# B# g4 J1 k) z6 h6 zassign mcasp_aclkr = mcasp_aclkx;
, J1 K: x# \( B* [assign mcasp_ahclkr = mcasp_ahclkx;% V6 ~: ]9 n) E) \& W+ C
assign axr1 = axr0;
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; _0 i, g8 T' e8 q/ s1 F5 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 O+ v# i: [, |! `$ s" U1 nstatic void McASPI2SConfigure(void)( I# V1 D" D& x1 a
{3 N2 a f3 N2 h" ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 a* N4 b l9 D8 PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" D% }6 s! v4 X, T! ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! [6 r H7 j; J8 `. d5 B2 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) V2 J3 D' ]- U: ?. a% @9 K9 ]) J3 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* V7 Z9 y8 _5 D- G0 _3 _$ }5 t$ V: r( g
MCASP_RX_MODE_DMA);. V9 x5 F( I8 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! f" R* @4 e0 o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" ]1 `7 f/ d/ f, \$ z2 B7 C- mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* S: s: D* f8 o% d, SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) G. s1 ^& f# X5 _ b) A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; k( V+ J! w. w7 rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) r" n$ e* N( l+ p! S; ?/ w: o! R! WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ |0 u3 j0 g0 O+ U5 ~; e' g; L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % C3 q( k+ [; _5 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 [3 V8 B. I1 M8 A4 h& u5 W0x00, 0xFF); /* configure the clock for transmitter */
; k, P# o( u/ V Z9 L/ ?# TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: o- G$ L. v/ ~5 O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 X3 g7 Z' x! p Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# H& e3 ^6 z9 Y' H( t* T
0x00, 0xFF);$ P3 j+ i5 ?7 B% ~2 k
+ L) i( w w% [/* Enable synchronization of RX and TX sections */
$ _! Y( f+ u" E8 t! U/ x( bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: E& J% N* @' z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! b# B$ e% ?0 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 o7 z _4 ]6 G6 ]9 ]4 o0 E** Set the serializers, Currently only one serializer is set as
) h* F6 J% c+ s; \** transmitter and one serializer as receiver.
5 `* w3 N1 D( T! h; P, Q*/
/ T8 m8 z, p" J4 g% `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 z$ U5 [0 R5 g& s% Z! H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 n" _8 e; M# Z
** Configure the McASP pins 5 G4 P5 \3 e+ _9 I1 M) Z
** Input - Frame Sync, Clock and Serializer Rx
) e! d# I) r( |/ B. z( W- _0 Z) _** Output - Serializer Tx is connected to the input of the codec
* a- c& [% I. H9 E* o0 l9 L T+ [*/
% ]$ ]7 `. ^4 ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 |# {; k; F- aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ U8 n* r. d8 G9 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& y0 z$ a" w4 L* S" Z
| MCASP_PIN_ACLKX+ Y% `) g. f( q5 n
| MCASP_PIN_AHCLKX8 Y/ I- [: H0 C1 [+ \; k. `4 ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ~1 V Q+ \8 n! x RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 o* }2 F- d1 L
| MCASP_TX_CLKFAIL
4 {7 z+ p7 m* K! i( l| MCASP_TX_SYNCERROR$ k- M) K7 B! e! R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # r- Y* y- i7 d6 j* b
| MCASP_RX_CLKFAIL8 v$ ?5 l% Q3 w/ D4 z# w6 z# P
| MCASP_RX_SYNCERROR
5 e; `8 C* l% n| MCASP_RX_OVERRUN);( G- Q9 B# q% B# _
} static void I2SDataTxRxActivate(void)( p$ L! Y3 N$ t& d9 u9 o
{' _) P" h) g7 f
/* Start the clocks */
, ^- [, K. a; W1 A7 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! F, {2 K: b+ J. ]' n cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* q; h- K% g0 M5 ]$ r3 m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' B5 Z& G& A- v3 H
EDMA3_TRIG_MODE_EVENT);# i5 X, |8 p; a b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , s' [- I. G* X8 E! T) N n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* X0 v' [! Y' L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 D- @. l% ?+ c" W$ E" `3 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// m5 {% n5 a2 Y' s$ \$ f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 A+ {' b, S6 L) _1 y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 M8 j2 ]) P- @# E2 _- X. `1 e9 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ _( ~ }$ k1 z& e, P6 o
}
* o7 L3 C+ J+ e; M1 S% }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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