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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 e D+ p- K4 S" V& m: B5 A
input mcasp_ahclkx,
4 }2 ]8 y) B: U6 \( ?: P3 H! Ninput mcasp_aclkx,+ C4 v; i0 @7 e
input axr0,7 H0 @7 `- e* k- D) }2 A% J
* Z& _7 r8 `5 G2 @( G% T
output mcasp_afsr,
3 ~. z7 J* s. H8 r; l8 Foutput mcasp_ahclkr,. A7 I- I7 T. \ G
output mcasp_aclkr,' y O4 _9 I( }% B- {
output axr1,
9 d) j4 W$ u3 [# i% c* q4 V' N5 G- A assign mcasp_afsr = mcasp_afsx;/ H$ G$ W: G% k. w
assign mcasp_aclkr = mcasp_aclkx;7 `" T) S7 K. F# W/ o
assign mcasp_ahclkr = mcasp_ahclkx;
7 ^. V, ]7 U: a- ?" fassign axr1 = axr0;
" H. A9 x, i3 H8 T" w: q2 T. J m0 k% Y
8 j8 D8 r' c5 V5 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ ]0 d B4 B3 Fstatic void McASPI2SConfigure(void), y4 J, x& p( D) z1 ^2 k/ K
{# g. h& I _% \3 }2 E. k! Q8 J7 N
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* x& C" p& I! T4 D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 l1 D6 D& P, i* e4 {/ s- d( F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 z; n! W8 c2 I7 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ N* V8 B: f8 S- _" t! t' q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' a8 n4 m4 H& K3 L7 B
MCASP_RX_MODE_DMA);
: m" }- X% B9 a! Y; w' g& |0 HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! l! G6 S. _+ n3 `: B, ~5 f3 W, u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 f# H% Y% c+ y/ [7 S! ~* W! o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 [( d- c* u2 t* b1 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# J4 j& |0 Y+ a; c6 _& a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " ^$ y" q/ A% i# f2 J: [8 x% ?) C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. Q) n& @4 D; ^+ C1 s# Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- a2 g0 q% U5 Z F. ^0 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + ^9 c- H4 I$ Q. U6 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% f/ ?; z Z2 f8 Y
0x00, 0xFF); /* configure the clock for transmitter */
% v- N- r7 A: d' \& \/ bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. T' t% q. w( TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( c7 p1 k5 Y4 L# ^4 D3 f' EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 D& q" ~1 ? ?7 U0x00, 0xFF);
: ]+ Y4 ?2 ]( j/ @# f6 ?7 G
* b' e7 ]) F, O/* Enable synchronization of RX and TX sections */
, `$ S. x5 }- _' I" H, u, BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* O! K! @" e5 _4 H# ?. n& t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 A5 ]) t" i# Q$ r& s& z# ^* {2 ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: S( u6 k1 r) K9 t7 Z
** Set the serializers, Currently only one serializer is set as2 a& ^! n& ~. ]" n! g/ u
** transmitter and one serializer as receiver.
: d7 K$ }0 G* J: q*/0 }5 R& x( U Z1 W4 x$ m$ }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: r0 \) S- l- s! M0 z1 ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 _2 q* A, L. T9 j8 D( A, T
** Configure the McASP pins
% {; ?7 D W( X** Input - Frame Sync, Clock and Serializer Rx
9 @5 c3 {+ ?' E** Output - Serializer Tx is connected to the input of the codec * {) N" l A) k/ U7 F/ g
*/
* j7 ~# ]0 i' A7 p* o& MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& p) p7 G' P# A9 \' E2 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' {8 e" W2 y0 u; z \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; s, {! Z; U5 a F, Q
| MCASP_PIN_ACLKX; Y- P' P# J v$ g
| MCASP_PIN_AHCLKX
3 ]) ?; q+ e, s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% Y' @4 l6 ~$ n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( ~3 W! M0 B5 v/ O# q4 Q3 a| MCASP_TX_CLKFAIL - S$ z; R( s" k
| MCASP_TX_SYNCERROR
7 Z$ K: C! m. q& ?& j$ U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 l* W5 K" b1 h. b0 I
| MCASP_RX_CLKFAIL
1 p: j# g( U* O/ D9 b1 h* I3 C| MCASP_RX_SYNCERROR
) S' P* @3 n- R) g5 K6 [| MCASP_RX_OVERRUN);
0 _) e! k# c$ ^. m8 Z4 q3 `} static void I2SDataTxRxActivate(void)
' i: o: r6 D; L, z" I, q' G8 b{
# A3 ]0 ~" U! a8 k/* Start the clocks */
& N+ B3 N+ |5 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, t, o5 [+ g9 r( @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% [' `9 j9 E5 K- {% B" zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 `1 ?' m3 y; k+ \) V0 f7 Z- ^" Q
EDMA3_TRIG_MODE_EVENT);, v1 z! u, R& t8 C8 e4 Y0 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' v/ l9 ` K( G1 S- {/ \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 D# |- r8 a4 `: B8 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- v; a+ O0 s5 J* D u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! y' Q, Q# w8 F" \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, v$ ^# ~; ]" ^5 Y4 K+ K' |+ @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 C6 C' ^1 u6 ^0 z+ a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% n, x0 A, Z' O
}
: a6 r+ R4 A5 u4 {请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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