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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 p* {; x; j! \5 L$ P/ B, d5 \input mcasp_ahclkx,! Y* p' N: H3 O5 P. A- ^% ?5 h. H
input mcasp_aclkx,
: }/ e/ I6 a% s% E% V9 y- Cinput axr0,
1 G Y- |5 M3 F- O$ N# a" @) A0 Z6 R/ Q" m) u5 l
output mcasp_afsr,
! a! @' H6 j- |: ]" O) q% j7 T) {output mcasp_ahclkr,& m3 L! L: |( n
output mcasp_aclkr,1 x0 J( _7 y5 Y( |
output axr1,. ` R1 Z$ Q# x* E; V
assign mcasp_afsr = mcasp_afsx;4 T5 R2 k3 _" d$ o
assign mcasp_aclkr = mcasp_aclkx;6 ]: _8 U+ T7 i- f( W' F
assign mcasp_ahclkr = mcasp_ahclkx;; L Y" u1 Y8 I+ v$ M
assign axr1 = axr0; ) e. V# n+ O+ v3 I' J3 s" x( n
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 l8 I" }" h9 _ X' lstatic void McASPI2SConfigure(void)! L9 g6 a8 L; x0 S, j1 l7 w
{
/ R, v! [- U6 {6 PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Y. ?9 ]- A2 q* e) n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 s/ d9 \- x1 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 h' B1 A! P0 l* e0 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 x0 o! `8 S! J7 {9 V+ w7 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 G1 W: T7 P0 p' i% }- x9 iMCASP_RX_MODE_DMA);+ P" K, m' M! L5 L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, q |7 O8 u1 B# ]! ?# G- q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! `: a; O* z2 G0 CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. z6 z! h E; {) p* XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 m) I: l/ h' O! U r. k% J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : I8 l/ S0 w3 i. S; R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, y" i1 J4 d" c& Y0 lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% [7 s& |- t& BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! n; w- C6 k8 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; ]6 j- J& ] ~
0x00, 0xFF); /* configure the clock for transmitter */0 ~4 D! a: \8 c: e& E2 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); a4 ?+ V/ z# T+ s$ K1 j& |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 ]- [& K8 s' x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, S7 U! a1 C+ D' @% z4 K
0x00, 0xFF);2 @2 `/ i& G0 o5 o/ G1 ^
6 X8 ] U" j8 D' d' I2 a
/* Enable synchronization of RX and TX sections */
7 b' p! w6 {; r- F" `# O* E1 r6 ~" bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ a$ z; B3 ~! T% [: A" G, H6 h- p2 s/ _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ?" n: N! M; m- pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 j- z! x0 n1 s F+ r
** Set the serializers, Currently only one serializer is set as" A% L8 s2 i" M) ^ `! _* @& \0 L
** transmitter and one serializer as receiver.
6 t9 H4 o! W' R& [2 p% {*/
7 |. D2 R' B+ b0 VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* P4 F0 A6 h. K. |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( T0 i. c$ B9 d
** Configure the McASP pins ; p. M% ~9 N# C% Z) n8 Q) k. i
** Input - Frame Sync, Clock and Serializer Rx
/ |( g( ~( C9 F) }; E( N& j** Output - Serializer Tx is connected to the input of the codec
4 G: w9 ]) A- @, I*/
5 }& l; d! t: q) P4 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) Y* ~ o* N5 q, h* X* _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 c: O% g0 A6 K' a" |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 e3 L/ \% V {; Y| MCASP_PIN_ACLKX* N) ~4 h' }4 L
| MCASP_PIN_AHCLKX
; h) o' |9 p4 b5 A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. }; g9 _0 z5 d) D% [1 A& N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# ~- a, }5 X. [. ]4 O, e| MCASP_TX_CLKFAIL ! _, s# a, w+ e) q) Y1 W
| MCASP_TX_SYNCERROR
2 [( D# O) L9 y0 t* \0 J$ t t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 K, x+ W. H7 G( J4 y& K| MCASP_RX_CLKFAIL
( v3 x9 q1 ~( R# a( M' U/ a5 f| MCASP_RX_SYNCERROR
\4 ^& b5 g% _' y* m| MCASP_RX_OVERRUN);
% Q4 J+ h- W& _6 a} static void I2SDataTxRxActivate(void)
; E9 R& [$ R- |* y+ [; \{* [2 p' s0 q& A! s7 U- M
/* Start the clocks */% K2 H& |# C5 A1 e6 k( a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( o$ |' w) N I) \- ^$ \( lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% T. F/ d3 M9 u+ x/ J. a- z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; w3 H8 @3 c& q3 b, k
EDMA3_TRIG_MODE_EVENT);
# j; m) u: o4 [7 Y3 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 @1 e( j7 m) c0 G9 t$ ]9 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) D9 v, U, N& m/ k+ M- YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 J1 i/ S. ^8 W6 E$ {# g2 T, ^. w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# v( A+ W. Z* _' I: G, J9 T E5 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) n2 @8 G. O' { w+ {7 m1 cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 T) x' `4 d; w; [7 n( Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ ]+ R( @7 i2 H* e2 ]}
0 i7 I, s9 i" H. q% s: j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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