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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. v3 X* C j/ e7 x2 ]6 h \
input mcasp_ahclkx,
% {: M' P6 a6 P% w! `input mcasp_aclkx," M0 ^- S; M. i# o" {1 Z6 V) L7 ?" d5 v
input axr0,/ ?% l; F$ m K* \) |. F) I
. J0 [; c4 S7 [' ^' Boutput mcasp_afsr,4 b7 }) F- O8 f: `8 i
output mcasp_ahclkr," ~# @+ Z$ s1 b+ O5 v: a
output mcasp_aclkr,
3 t' w0 b( V/ q3 G2 Foutput axr1,
; S' s+ R" Y1 m: S9 K- c; C- c assign mcasp_afsr = mcasp_afsx;
0 [0 b! F; p0 p" W9 T/ Sassign mcasp_aclkr = mcasp_aclkx;; f! v$ c/ w R2 H
assign mcasp_ahclkr = mcasp_ahclkx;
* Q- ~/ Y9 V6 W5 j7 xassign axr1 = axr0; & t. L# c! d- W8 J
7 @ G. F( S; n3 @% [' U3 x. O* V5 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ _* ~7 s7 I K5 y zstatic void McASPI2SConfigure(void)
! h0 ^! u4 O. w1 p: K{& T" c8 x# Q% P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 ]+ l4 [$ _, L9 ~5 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 T) x! \( n) q& W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ k+ U4 E" {7 c& l* b9 ]$ q r# `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 u$ t$ }% ~5 E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 ^) m; a2 j% F2 ]3 q9 h4 @MCASP_RX_MODE_DMA);6 K9 p D+ ]" I7 g* m2 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& B- `, o# g' A/ u+ d* Y$ r: g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) A& X8 C3 M( I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, F X8 f) d6 ?* Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' _, X5 r+ z/ y; K9 F- i! g" ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 X% J; G7 N2 _( eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ E# r; c+ h' h- i: M- h5 ~- n8 t3 \ Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; H+ e5 D% I+ y: [6 [ y( Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 ~$ ]4 K K& H6 J% P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 |2 m/ h, H! ?- |0 b( Q0x00, 0xFF); /* configure the clock for transmitter */
- ~' t& s( a0 S$ \+ PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. k/ j. Y- M* H- O6 I a" h2 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; c, d) ~9 L' u ^* Z, V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) ^: ^ _8 K/ G0x00, 0xFF);
, S2 g2 o* E$ C& {% d3 m: X) ~0 C9 a; D
/* Enable synchronization of RX and TX sections */ # ~7 O( a1 _4 v) Z: B, g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, s& P) _" c$ N8 y* u, v8 @8 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 u, G6 ^2 d& t! n4 F4 G: {# }: N- ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: ]- Q& @, E, @. Z" p** Set the serializers, Currently only one serializer is set as
: A3 `2 _9 Z! E/ e8 ^' W** transmitter and one serializer as receiver.
1 }1 s% s1 V& H6 Q$ q*/; s" @6 N4 ^8 M2 @3 j( d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# a6 b) k2 S2 L2 F3 ?. s+ AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ c W, O) E! p8 p7 Y! G
** Configure the McASP pins # T# v1 `) Q1 v* a E& R: R2 K
** Input - Frame Sync, Clock and Serializer Rx
( }# _$ w, b: U' U, _* o** Output - Serializer Tx is connected to the input of the codec
: s; t- R7 }; a* B# C: V1 v+ @*/, N1 s0 \9 [" l( d! Z1 U4 h# v) @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& M' Q4 p. h; `$ r7 j, l+ tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) }6 j& ~$ n& K8 {4 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 P8 ^! a$ O" O1 \" M| MCASP_PIN_ACLKX- D) {' {+ p- k$ T+ M$ i
| MCASP_PIN_AHCLKX( L! a0 v' J' A {; R6 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 |2 v0 [0 K& W) U. f# w+ rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 t8 O7 g" H. r7 e
| MCASP_TX_CLKFAIL V# s& B8 |5 ?/ M. e1 D2 C
| MCASP_TX_SYNCERROR- S" e* L6 T" T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ @. J% |0 a6 h& R| MCASP_RX_CLKFAIL
( K- J, _$ y) ^- \| MCASP_RX_SYNCERROR 7 U# ~; {1 Y; q q5 _
| MCASP_RX_OVERRUN);0 m) @9 u8 ? P: I. ^
} static void I2SDataTxRxActivate(void)
0 e0 X" I& S; ^7 n- n{2 |0 i+ v1 Q+ V9 ^1 n0 J5 h3 j
/* Start the clocks */+ g% ~8 e5 `5 c9 v. s" W9 H2 k, l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 {: E# L) M' d8 {- S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 E, E3 e- X- C+ W; F! m: c7 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ H% V/ m& k! H: q+ U9 P: @2 n# M" G
EDMA3_TRIG_MODE_EVENT);
7 T; y; R5 p8 B) D$ {; @% K; c1 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) d, Q0 m$ S0 r" PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, v- v/ k' O5 ?' K6 SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 n m, B1 j% u3 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- C- n, `0 v A" j7 ?; I: t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( I: X+ o/ W$ C/ J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 _! M5 H% v. Q& H4 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- T: W1 `7 ~+ [2 D1 u} 7 _6 l& }4 J/ I* k& `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! U* F1 U$ Q. o7 L/ @
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