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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 e: |; C1 k4 y* Q9 Q" Q2 ninput mcasp_ahclkx,
% R) V. A2 H! T, j+ K: Einput mcasp_aclkx,
+ K! q# p6 q& D7 y! oinput axr0,
% b8 y7 O' C/ r
% \1 _8 V; z* k2 eoutput mcasp_afsr,9 a' A O5 a; q3 D! `
output mcasp_ahclkr,. W- j! i: j5 O( a/ X c2 u
output mcasp_aclkr,
* f$ f, C; O- }$ ~) Poutput axr1,. O- V1 D0 U* E' h
assign mcasp_afsr = mcasp_afsx;
3 O4 |2 W1 c& Z4 d$ vassign mcasp_aclkr = mcasp_aclkx;' `9 m6 i3 Q7 _7 c! j9 e( L; x
assign mcasp_ahclkr = mcasp_ahclkx;
" t8 V6 g% A0 s" U, F, T! m- Zassign axr1 = axr0;
8 ]9 ?0 J ?: e/ B6 }7 ~
1 c$ m* T: m) G: h5 ]; S% h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " p4 L) Q; r5 n/ Y
static void McASPI2SConfigure(void)9 V) x, _% _: m) N# c
{
F4 V" @0 E% i% c% DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* A9 B- q& A% m `, h: p" |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# F1 a( a) U$ `( _$ TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 s: D& _3 v+ [; G8 z/ ~2 a# CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: [$ H7 ~. a# u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& R1 v, D( p& t' ~* n2 A
MCASP_RX_MODE_DMA);+ p) Q8 j9 n. ?8 s( Y/ f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 T- h) Q* Q) B$ ]+ {5 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) l; f3 Q0 F" ^( i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 L- E6 x( _ ^/ E6 ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- {7 \3 o8 j. P9 O! P* B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 D6 B" N _* W" D* w! |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 P; y# F8 f2 R0 R9 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 P/ I; v/ R+ h, A0 eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; c$ d& L4 W0 [$ O* K9 u( u+ D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) ^0 t0 e$ G. \+ W* U C0x00, 0xFF); /* configure the clock for transmitter */
- e/ _5 b4 Q1 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 f, t/ W: q8 \+ ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 y$ N5 N3 B6 j T* [% L7 j9 R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( X; ~# C# r; x, H0x00, 0xFF);
5 z/ K' j2 S, X; L
. C/ b9 P4 B+ ] u/* Enable synchronization of RX and TX sections */ ' L0 a/ P3 V/ j- o+ L# P2 _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, n1 ^' A) [) ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& N) J* t% g9 c) P/ k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 e+ c0 q9 x1 f7 S2 l- ]! q9 _
** Set the serializers, Currently only one serializer is set as
d* a. ~+ @ J. I2 {/ ~** transmitter and one serializer as receiver.# |/ h" W9 {' |7 `' N* k N+ M H3 U
*/
2 {1 U3 y6 r4 x$ ^7 H- L/ Z) A' sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 U% `$ c6 H* w1 }4 o, FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 M; I' T; L/ b: r9 |, z6 R- n** Configure the McASP pins , D' b5 {/ o$ t+ B8 @# U
** Input - Frame Sync, Clock and Serializer Rx, B1 b& n, x& X4 c* X- V& h0 s) y9 g& ~
** Output - Serializer Tx is connected to the input of the codec
- M! p! q0 ]9 e( ^! S) [*/
: I4 Y' ]6 u: J) d; [/ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; \! {* K v' v0 `, H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# Z [$ m$ U8 d, T7 e# u) D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 h% P; ?' q5 L5 M% K5 V8 s6 q
| MCASP_PIN_ACLKX
% I* E' @& T; \8 R1 z| MCASP_PIN_AHCLKX
9 G9 C" T8 n* B: h: K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: o. D( E) U0 H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; a( y3 ^) ~$ J% n# t) y
| MCASP_TX_CLKFAIL ) S, H+ S3 B5 F! E, g# i/ t
| MCASP_TX_SYNCERROR6 [( U8 M* N: u2 k2 O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: G* y }. O* D5 || MCASP_RX_CLKFAIL9 i0 b9 C1 p/ [5 }
| MCASP_RX_SYNCERROR 9 f9 _6 [, c2 ?8 u/ ~ w
| MCASP_RX_OVERRUN);
# ]. e5 W0 h; a& z) m} static void I2SDataTxRxActivate(void)
& f, @1 {4 S' ^- H3 [- Q% O{
7 X" s1 H; [; p/* Start the clocks */
4 W; [/ k( V6 I3 ~& qMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. q! z7 c2 I. A: `' s- U4 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) S8 I# O! h8 F* i* Y) QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
b# H; c7 X9 P2 s9 D6 mEDMA3_TRIG_MODE_EVENT);
; V" d" p2 _+ mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 U3 O3 H0 _8 b+ r& \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ _: }9 Q5 K3 b, E& mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 A! o/ a4 g* `, S- I$ v2 X# s7 o BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) Y. @4 c( B- q! |& t2 @0 p& ^1 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 u. e: H2 |# t2 A2 ^3 i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 P7 t7 y: @( i; J4 F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: n% ~5 H$ X! p! e}
' T; K6 Y; X3 ~9 l( P. D* P q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . w) M5 A; A+ q, ]4 t5 f
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