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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* N; w1 X- W3 q3 t3 H6 s2 ]input mcasp_ahclkx,
. p' l, O5 [; z4 _# Minput mcasp_aclkx,
' P" |+ t' N# h3 y; B+ w! P5 dinput axr0,
7 K% p0 J2 C( z6 q) F/ Q* g; K$ @4 P6 ]2 J; u- C2 Q
output mcasp_afsr,
# g$ T. A+ N9 Y+ ^; Moutput mcasp_ahclkr,6 M/ Q3 f6 f( U, |7 {( R
output mcasp_aclkr,
s# R# v2 x5 p I6 m! r+ x+ ~output axr1,
9 b6 b& ]$ W3 F5 h assign mcasp_afsr = mcasp_afsx;
! e* o F& U6 p( X- Vassign mcasp_aclkr = mcasp_aclkx;! v' N4 ~) M0 [( |3 k
assign mcasp_ahclkr = mcasp_ahclkx;8 w. v& p: J# F
assign axr1 = axr0;
. t0 u5 u4 i: Z' \8 n% p
$ u: e( u0 U5 @2 `, ~- o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 `1 \, o2 i, {# j7 h! T
static void McASPI2SConfigure(void)
( w+ P4 c- B8 V2 v( q" z{
1 I. _' b+ u4 h3 w+ LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: H; a u) Y- `3 n! D: d# x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 r* |' d0 F V9 @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, P9 N% g7 e+ x* A! M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 N, c$ f8 ^' `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' k6 [9 I/ L: L
MCASP_RX_MODE_DMA);
" m( T2 Y& u# @( ~9 q' E; V, FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 l4 _: R, m/ ^6 u! MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ k5 a) T$ J6 V% K" c* H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 m3 Q$ q; s; k, aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* m" ]* p0 z8 b( K7 t) ~
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 p& l+ ?- d/ i7 h1 U3 b* U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" {+ ~; |8 ]6 A4 c) S4 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; A0 q* A5 I- i t% T- m& F/ QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " ?( Y/ D5 D1 n' N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' t3 L2 }: r Z0x00, 0xFF); /* configure the clock for transmitter */
/ V6 H6 m1 H5 g3 T' ^8 W, nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) G! [# |) V K- Y6 V4 T1 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' x9 T- _; O9 k, N4 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 t% b8 M* J0 p5 u
0x00, 0xFF);
: f4 Z. O$ J- F
# M! d+ I( G) l; t* T/* Enable synchronization of RX and TX sections */ / F' N! z5 u: {8 A2 \1 ]6 c+ {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. Q5 F; X7 e T, d5 f7 r6 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); h7 V, C7 p0 h6 i- j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( S& R9 y* x- r$ O2 [( X
** Set the serializers, Currently only one serializer is set as% W$ t6 d: L& N- E
** transmitter and one serializer as receiver.
5 m Q. G, Y' h$ r. w6 Z N3 x*/8 h" k' F7 n' l/ R' p6 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 [& t# D/ k! ]- E4 u" ?* v) cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 f8 {8 N* Q7 w; N; M1 A** Configure the McASP pins 1 c; A! @ _% j
** Input - Frame Sync, Clock and Serializer Rx! u* z7 G+ K; o( \% E. J
** Output - Serializer Tx is connected to the input of the codec # j% A3 c4 L& q& N) h
*/% j8 U( Y$ U. G* Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ p$ ?7 V# [! O* `5 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 ?( ^4 Q' `7 O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ p4 e" Z$ f! X' k| MCASP_PIN_ACLKX
- A( D# N$ X O0 R9 s% P| MCASP_PIN_AHCLKX
- l" q% B$ t7 o- ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# H( b) e, m/ bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 z$ m& Y2 T( ^
| MCASP_TX_CLKFAIL
* d0 G9 F3 M2 x4 x: K| MCASP_TX_SYNCERROR
7 h/ \$ \3 A, ~5 c) [7 T( d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - _7 m; m+ G B. y
| MCASP_RX_CLKFAIL
P e2 Z! y! k; U- a7 q" o2 o| MCASP_RX_SYNCERROR
+ u" I7 g. T/ E# a- I8 E. J| MCASP_RX_OVERRUN);
1 @$ N; ~& z$ y' a4 \} static void I2SDataTxRxActivate(void)
) H r& d& B6 Q- K+ B2 T{+ D# D% j, \+ t* U1 ]1 k
/* Start the clocks */
. D2 x+ o5 N' @$ \( pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, W$ N9 N L8 _/ i3 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) J5 m7 q& P T- g( ~, k/ lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% Q g6 W7 z7 C7 i" |
EDMA3_TRIG_MODE_EVENT);
+ ^* c* ~) ^) q7 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) W+ e9 D* H d& I4 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; [4 y- U/ {1 ^ H. Y: ^" d' ~& r! t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 Y- S' K2 I5 R2 u6 _# \; O: O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 B0 R' y# `: c: G: m3 g! Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 v8 v% M7 `" E% mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ p Z8 i6 X! `) N: g) q+ l* K# f; UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 A- U9 a9 q+ _8 F. x! k5 {4 ~% s} 2 e+ d% F; E& C# U8 Z* t) v6 s3 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 k) n R: M- d
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