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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
B% u. A$ m* w* linput mcasp_ahclkx,
: u* T/ j2 g. _1 p( G ^4 `input mcasp_aclkx,* _6 G7 i9 W! O4 m
input axr0,
! m+ y% A# d4 U2 a. v# X2 z1 p2 k& j
& v K0 p6 @: _5 ooutput mcasp_afsr,4 a9 \9 s& Y' i7 b# ~! J5 H
output mcasp_ahclkr,- Q/ T/ X8 a- X
output mcasp_aclkr,
0 J* k1 ]6 U" Qoutput axr1,
: N4 t1 M: H. Q& |! I9 c assign mcasp_afsr = mcasp_afsx;4 [5 u* G: p+ F# Y
assign mcasp_aclkr = mcasp_aclkx;
; h. w/ U& c& d0 g% x4 massign mcasp_ahclkr = mcasp_ahclkx;
) H8 K; C$ B/ A( @/ i* g5 u3 }assign axr1 = axr0;
! B! E% k* O- O2 Q7 k) K. K$ g) _% k! y2 E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( q3 A7 s+ W7 Z# ?) X- Wstatic void McASPI2SConfigure(void)' `2 |3 ~4 E* _; R+ l7 B# u
{
7 n6 x u- R( W/ B$ T0 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);; C/ _0 l1 @3 `* e; _* K5 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, ?8 N6 U; W8 \4 H' C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 n: O7 m; Q$ N0 Z+ X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
O# e E! ^# tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ~ E+ ^) {7 i" l, Q, GMCASP_RX_MODE_DMA);
3 t5 h2 F- m) r) PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ b1 Q# ~( _" ~( ?, Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ g4 ~9 S2 s+ T/ f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % x# W% ?! V+ \9 R' W; m. w( U X! ]! J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 Y( ]8 Y0 \# l; {" BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( C5 h9 s; R, ^& iMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* P v, f: [( @% `5 E4 p- ~6 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ X+ I7 q! S4 Z$ A* d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 F* P, p/ n0 _9 _/ z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 v3 @7 |7 `- ]8 |( \0 h0x00, 0xFF); /* configure the clock for transmitter */
- N8 @8 s4 [& i. w: UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 a* v3 V, S; c7 w1 i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : Y F- _" b# F9 m I3 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& G3 `5 H3 W$ Z# m) \1 T9 j3 E: W6 I3 j
0x00, 0xFF);
- i% p/ z& q* y+ n. v5 `6 }3 C6 S" `
/* Enable synchronization of RX and TX sections */ : k0 _ w3 e0 Z3 `, d) u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' H0 d$ f' L4 T7 r, |3 w* e( Q, y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 I) q. E' T: t2 C& rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# O s& t- \8 J0 |& T( R
** Set the serializers, Currently only one serializer is set as
9 b- w d0 U5 G1 B+ S** transmitter and one serializer as receiver.; y* L. b" F+ i; q' d
*/) }: j: A% @- N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 Z: U0 O/ P4 e0 V _8 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 g( r/ o5 K) z+ Z/ x& |** Configure the McASP pins
2 z% W6 K5 k5 N( s8 I3 e$ @** Input - Frame Sync, Clock and Serializer Rx
4 K5 M6 t% C4 K** Output - Serializer Tx is connected to the input of the codec
4 Z! h- Q. L4 U: g, _*/6 S3 I, Z0 m8 y A; @
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 k: o& `9 R0 T) t; Z4 U6 u* }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 N0 `+ {" y8 C; z% `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ ]* M/ E' E4 G6 Q4 a1 o4 _4 K
| MCASP_PIN_ACLKX9 g% l! d& ~2 k/ a/ a+ U8 r
| MCASP_PIN_AHCLKX
) U, x6 ]% e- p! E4 X# {6 [1 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ ]4 l/ i/ ^1 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ b; A* W4 K! t& \8 g
| MCASP_TX_CLKFAIL g) Z4 T9 s5 G% W
| MCASP_TX_SYNCERROR- m% r/ a7 |* r* h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 k r& L" n6 O( p x; d
| MCASP_RX_CLKFAIL2 t( v( w/ q& E% Z9 f# V
| MCASP_RX_SYNCERROR
" [' f, M3 G3 U! M| MCASP_RX_OVERRUN);
# e# `% {' O* j& c+ |} static void I2SDataTxRxActivate(void)
+ Q1 b1 h) ^5 v{8 a" e9 }- M# n! C/ Q8 [6 a! K. u
/* Start the clocks */6 t, [1 h) e0 r9 S
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ D* V- H$ z& w8 h9 r7 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 k7 c" d, E: l4 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) l" G1 ^& H$ o* ^! }& V qEDMA3_TRIG_MODE_EVENT);% w1 e9 O& z% Q, G! [7 @- E6 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 g9 g1 x5 C3 _ u8 k7 ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' {( T$ T3 s- @: Y; F5 L& TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& P5 _; @( K4 H; yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- ` e& B1 `& g% P" w+ jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- W# E r/ u1 `# ?' [2 ?+ W( o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* a2 X3 l. j1 R" S2 _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ z9 t9 h) L; m: i: }
}
7 ^; ]- E4 @, N) k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % u: {% s3 }/ D' q, k5 z
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