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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 P8 a% g9 _$ H! U' y F: S( i$ N9 g
input mcasp_ahclkx,$ b' u" D4 J$ c$ N5 {) o
input mcasp_aclkx,
( H2 ~" W) ~1 j8 {% ] U @/ \input axr0,
. H% B2 y- T/ @7 i5 J
3 H v! i% c% x% v# Q) S Poutput mcasp_afsr," e3 [! p$ Q) c( f! Z. y& Y
output mcasp_ahclkr,
4 p' w: b! @1 X. N5 Y9 n2 X& [output mcasp_aclkr,
5 X8 t! U; \1 e1 |output axr1,: k) ^, p" g% F8 L$ w0 d3 I
assign mcasp_afsr = mcasp_afsx;
* z4 C2 l. ~. ?" O1 k/ Cassign mcasp_aclkr = mcasp_aclkx;
: `$ Z: H) h; h& e" F# `assign mcasp_ahclkr = mcasp_ahclkx;
$ G4 L8 r- t G: `2 H% J/ ]assign axr1 = axr0;
( ]( F* V( t$ w( E/ C* o, V# v H) z2 a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 U3 H6 s a5 L- F: c9 j: Y6 ]
static void McASPI2SConfigure(void)2 \& L8 g1 y: d s' j
{
4 o C$ y$ q1 _3 B: o3 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% D% b1 I2 ]& j% X/ E0 t, wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ V9 e ~% K) `) n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ @4 k( [/ ~3 i, B/ `: Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 i% W9 c/ |0 t: u4 F+ l3 Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) z' M% |, J2 L: l2 i" T$ U& ?MCASP_RX_MODE_DMA);
/ l3 { k$ u, S$ R- XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 M% [/ r( Z+ Z1 Z Q \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# K1 F* H: e% g* \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - U* [# u) r7 \. w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; p6 j/ r' C+ _4 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% S6 G/ E" E2 s3 t4 L; n, ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; r Y- m2 y' v$ m, @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: f' [/ d0 P0 L d) [' r- L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: q1 j3 ?5 C+ H) cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 m# ~# A/ @& }# d; I) W0x00, 0xFF); /* configure the clock for transmitter */3 v: s/ c0 k7 Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( `9 F6 S2 S) e/ ?# }+ I/ h, p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: W! Q. n( _" r% mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( q* V, `8 k' \! @
0x00, 0xFF);! ^ o t4 X+ n$ D2 Q' J& w/ L
5 a$ e2 L% p# N2 b: _
/* Enable synchronization of RX and TX sections */
0 y" `# p5 T L/ d1 F4 j0 _8 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 R% X* y" F9 b$ S0 t. QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 T+ l" d: y6 y( s5 v2 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 H9 C6 X \$ ^: r7 g** Set the serializers, Currently only one serializer is set as
8 s/ T& N# f. p; l q4 q, m' Q** transmitter and one serializer as receiver.! p; W' |6 u* O2 P3 B/ g
*/
[9 T, m$ a+ g k. ~8 a, sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, g, F+ ^1 \. e& r, S2 IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" M! ?2 z5 v& c3 X9 U
** Configure the McASP pins 2 J9 }6 j: w" n" m; M5 |% ^
** Input - Frame Sync, Clock and Serializer Rx
1 t/ o' H! t0 B% ]& {** Output - Serializer Tx is connected to the input of the codec - I g0 P& ~* B
*/
X! M0 }5 k9 U6 i( U2 D7 [, g& HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 @- d# Y7 P$ P1 W& e% [+ jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 S# F- G4 G2 o; J, I# L/ y9 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# X5 |( B' c! y; n8 L x| MCASP_PIN_ACLKX
, R4 J& x" f( Q! D: j6 N| MCASP_PIN_AHCLKX- W- v" D9 \5 z1 f) l" P$ f3 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. W: B& ^% Y; L/ n" {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- X- w+ H# Q: a# T" g1 V| MCASP_TX_CLKFAIL % K# ?& O. V+ {- n& f3 O' _+ f( G! D9 u- q
| MCASP_TX_SYNCERROR! @! o$ y: f0 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + c/ a+ Y' I9 |: L4 q( j6 A
| MCASP_RX_CLKFAIL
, e3 n6 X) r( q- E3 V| MCASP_RX_SYNCERROR
5 k- O2 C8 t3 n% ?7 ]| MCASP_RX_OVERRUN);
9 {0 E: ]4 ~) p! f/ {. X} static void I2SDataTxRxActivate(void)9 q4 s# s9 z' s% J8 e0 v
{6 U* ~. d. k8 |9 ~9 b9 E
/* Start the clocks */
- W2 S; W& }( B* a$ I6 D& vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 W7 i5 Z! r- `8 a# n# N9 @2 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* n# ~3 P; F% uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; A! e! S u4 h! O
EDMA3_TRIG_MODE_EVENT);& Z4 U! ?3 I* n1 Q+ e5 k- b; Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ x. n. m9 g# g Z, M2 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, w3 N4 e. y. i* `9 G$ _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& P5 F8 W3 c s: C7 k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 j7 Q& S1 R# y n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( [" B9 A5 W9 Z$ y/ F7 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! `2 ^- R+ y# O( H b! }$ Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ Y; P8 v# e' X& f5 D}
) M |. `; e* r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( `% t1 ~5 {' E) g1 L& F6 n* k$ o
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