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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 t1 ?. ~8 E3 Q8 \, h3 X/ ` }input mcasp_ahclkx,
4 q& b8 X8 W7 _( ]! L& Rinput mcasp_aclkx,
# B2 I, V+ ?$ t% S l L; K+ R' tinput axr0, |5 _, L: }7 o: v- b3 P z [
+ X5 f3 D9 m& U+ Coutput mcasp_afsr,
9 _ l9 n0 o6 X" Koutput mcasp_ahclkr, l2 H# P' ]; O0 B8 f8 X' r# l
output mcasp_aclkr,; i Y' {; a! }- Z! D* z. x, Q% X
output axr1,
, `# C+ b! [8 v4 `8 H! ? assign mcasp_afsr = mcasp_afsx;
4 j, o5 U5 f- ~; passign mcasp_aclkr = mcasp_aclkx;2 y6 F: i% C7 I2 W* t
assign mcasp_ahclkr = mcasp_ahclkx;
d2 K; }* N, }1 [- ~assign axr1 = axr0; & |# c( m# Z# k3 X W+ ~
/ C( c9 a; b0 _! i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + Z* j7 O0 `4 ~6 E- u4 T
static void McASPI2SConfigure(void)
, p$ ^. }8 y$ q& W. D6 x{
[- O2 |7 F& f& pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 M) g5 h* m# O( P9 N( D$ bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# h" {, I |' `' H n d9 E- _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% c# E( y+ m/ R& G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* {/ N2 s" ?+ l. U3 ]; \' nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 ]& o0 e' ?4 z2 L# x* g" ?
MCASP_RX_MODE_DMA);4 p- W# }# b$ H0 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 V4 {$ t% y# d$ T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' x; Z& J- @; u7 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! f- [# M1 X' S* E) X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) R! J: W4 N1 q% V& \; ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) h( ~+ G4 j3 c4 PMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 H; y% L7 U# b$ p5 x' xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ y* C8 v& b' C2 }% i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% K: d6 Q; l& x: h5 S. r: ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 U; U( B+ ?% O# |7 {, b0x00, 0xFF); /* configure the clock for transmitter *// q. p y9 S2 Q Q( K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, x& l0 }; s' `9 E! a0 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); `' n: H: n) _7 `. p! ?- `4 F W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 {0 q7 [; w% e7 ]6 b! O
0x00, 0xFF);: `4 W2 C0 X, x2 ^1 H
( K( D& B: r! g! | [/* Enable synchronization of RX and TX sections */ ) o# h" t+ x9 B. X; f* o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 u/ {$ Z# d! b
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) i4 s: S' E' N! E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& R+ ?, ?" Q6 q5 F** Set the serializers, Currently only one serializer is set as
2 Y9 a2 J% \- d; ?** transmitter and one serializer as receiver.) f9 _' t" m' |9 F6 X
*/
: X' u. k0 \' i: \4 T d7 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: @; d# H9 H! N9 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! X( J2 c) v5 Y2 S6 N* e' D
** Configure the McASP pins " K P6 H4 B0 }7 Y1 d
** Input - Frame Sync, Clock and Serializer Rx+ J; Z# S8 g' t' f6 k
** Output - Serializer Tx is connected to the input of the codec 1 U* v, W. j4 f7 g; E& V$ m+ A+ V) ?
*/* x; }% A2 E L' \, H& u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 a0 Y: j3 @) M2 HMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( W. R W) l& v$ p- e. Q% AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 f( V0 W, L9 N3 h| MCASP_PIN_ACLKX8 L, F/ v$ p8 Y9 H1 z! V6 X
| MCASP_PIN_AHCLKX- D% S+ Y3 T( ~( n& ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 E7 |! }. X% P5 D! fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 u' @3 D2 }; X( N/ Z| MCASP_TX_CLKFAIL 8 G% H' S# T0 B" i0 v
| MCASP_TX_SYNCERROR& ?5 G+ ^# p6 Y! b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' o6 U9 ^8 t; |! S) f0 \$ b| MCASP_RX_CLKFAIL$ A' M/ R+ r3 Q! w( d
| MCASP_RX_SYNCERROR $ r9 H* ]! I& F
| MCASP_RX_OVERRUN);; \) G; E2 X4 G( r7 e( X% |) n/ X
} static void I2SDataTxRxActivate(void)
2 |. R8 ~! `$ y" I, o, i* |{
+ Y6 z3 a$ \7 U' [& R; Y/* Start the clocks */
! Y! h" v7 z0 N: I& M& Z7 T# dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 ]* B2 Y& Y6 O/ h& N# S4 s! _McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! E* @3 \* w- K+ c% A5 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" @8 \3 b; h/ ~$ I! {( MEDMA3_TRIG_MODE_EVENT);
! e0 Q6 w( ], B) y; @$ L. SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # |4 ]# i3 N- |- i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 D: B( r+ F& ]/ G* @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 P+ [6 e' j/ i' N0 m! B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ I: F1 D1 b$ x& ?0 E; x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& u8 W% F, K# p" b* @! S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
M/ ^9 o3 h7 @) TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 ^8 t: E1 ^1 J ?
}
$ x2 N3 b, o2 w3 @1 Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. {* y' D( j. T& \+ O" `
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