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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 T+ E7 u$ m; ^3 d! Q$ w2 E# o
input mcasp_ahclkx,
S7 j n3 }/ ~. S# O; ?7 Finput mcasp_aclkx,
1 v" k3 D. ^; I# Einput axr0,
* s5 G2 ~8 w: D2 }( L3 l6 k0 |& k: x' T$ C+ |
output mcasp_afsr,2 p& a4 q' Y( h
output mcasp_ahclkr,
- ^. I0 Q* Q' [2 d/ }+ Coutput mcasp_aclkr,# u: M; E; W t6 K! E6 N; I
output axr1,
8 B+ {/ @8 s$ E& K7 }, ~4 u9 L assign mcasp_afsr = mcasp_afsx;
/ Y+ u4 s2 o; kassign mcasp_aclkr = mcasp_aclkx;3 C9 b4 D9 B) ^' K
assign mcasp_ahclkr = mcasp_ahclkx;
2 u* l( r! g& k% r( passign axr1 = axr0; 7 C9 N5 v% J5 k
9 O8 H8 ~ R% {! H
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 e- m& |3 q/ N0 ~0 X
static void McASPI2SConfigure(void), D# j' S$ d! Z3 s
{
2 |0 F3 B! Q% l7 V. b% `0 {7 u. P RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% w+ J+ w# j$ sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ {& ~7 R @3 s4 i% [4 f& b* V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" f/ T( I+ Y, g$ H5 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( W3 o% y/ v. H0 _% ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 @+ u6 j$ Q( n" n# v8 e
MCASP_RX_MODE_DMA);& w6 W4 f: i1 Y/ s2 J0 w( Y. h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' o4 {4 W4 w: T1 `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ k4 a; @* j$ U! ]) q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : Y7 u& g9 o3 ?2 c# L9 L9 R B3 z8 m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& w0 A" l6 |/ G6 h9 \3 F1 z" q5 }0 |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 |5 S* K2 E: w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, K% Y2 j( K" r2 u' H( uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 O+ \, E4 _( e- zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 w3 J! w9 j. w) S7 N. a7 gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: B c9 a! L n2 _3 H$ s* @
0x00, 0xFF); /* configure the clock for transmitter */
, d+ R8 C. ^ g! N7 ^2 J5 Q/ v' EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* C$ j" e# z8 ]4 f# M# YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' l I, j" w2 V$ M0 h* I6 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" H) @1 ]7 w( _9 B5 Y" I0x00, 0xFF);3 b; L6 W0 o; g
1 {: l e5 @$ R" G
/* Enable synchronization of RX and TX sections */
* |+ s' x1 L" H2 \7 m$ h6 T& @; kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) Q4 f3 ]9 U5 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! R2 Z s2 o) \: LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
j7 B7 b& Z# \) }& l+ n; z** Set the serializers, Currently only one serializer is set as
% w/ l' o$ L( h) V** transmitter and one serializer as receiver.. t8 N$ g7 z. |5 s
*/' A5 ~( ~7 `* ?) y. T; ]. k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! x# ~9 L7 Y- S0 x q$ ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 J$ U0 i X, M4 ], E** Configure the McASP pins 6 ~: J% _. T) N/ K r B
** Input - Frame Sync, Clock and Serializer Rx
9 |7 {( o3 ` I, X l6 U- v. ^, {** Output - Serializer Tx is connected to the input of the codec # x; c1 Q. R6 U8 X* }! Z
*/
3 ?# z9 A b/ mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 k! u' q9 `+ z9 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 d" b+ O t# M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, r3 q* S( P# }1 ~5 B7 u) |! ]& v
| MCASP_PIN_ACLKX
' F, P% s& V( b9 k: i( J& Z: R| MCASP_PIN_AHCLKX. L* L% J3 s2 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 i1 F, `" V& |% ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% ~5 h0 Q m& x( d4 K0 a| MCASP_TX_CLKFAIL
9 S' g+ m ?' `) \: G- [' i% i| MCASP_TX_SYNCERROR9 m. ]* f9 i* U S, y0 {! ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' Y; f0 M5 y2 J- Z' k- `
| MCASP_RX_CLKFAIL
& H' q3 [, A0 l E4 B* L| MCASP_RX_SYNCERROR
5 `) E2 L2 p. Q| MCASP_RX_OVERRUN);
- i ^0 P9 a+ m$ d' M$ [} static void I2SDataTxRxActivate(void)
. t3 p- @ r! }/ ?1 F{! U& Q, |: P5 P/ ?6 g" e
/* Start the clocks */" G$ _9 G$ {( o$ W& p0 X G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 k+ C8 Y3 a, I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ U5 c. ?: d( H zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 K/ r; t. f, b9 }: ]. `3 t1 I
EDMA3_TRIG_MODE_EVENT);3 n3 c$ c+ u9 a: U: b/ D# L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
Y6 e9 O) I) r* S3 s+ @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) H) O7 ?2 {& Q, }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 k8 h4 n" t, S0 d% r3 p! J. L
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// W5 j8 Z$ f( {6 o* h9 }2 O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 ]6 v/ z# m9 NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; k! _$ G% C$ R' x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ ^/ [ u% b9 m- R} ! Q: P( e/ j' h* f6 L0 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * T9 l6 H, k6 Y5 M6 p" u
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