MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
& ?7 O. h  T  Tinput axr0,

1 j$ e. b& x, U. X' u* Loutput mcasp_afsr,
output mcasp_ahclkr,
( B/ E  m7 r1 c+ @' d  G, W9 c4 coutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
) ~( n5 I7 C( }& y6 cassign mcasp_aclkr = mcasp_aclkx;
4 j# c" J# i+ a' Qassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

% Y5 g4 V1 Q+ G/ i9 P5 ]

static void McASPI2SConfigure(void)
{
' `, O2 \1 h, }. UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 d' {- f* ^* o4 E# X4 m, OMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# ?' `7 D1 f2 o  h% k" T2 o2 f0 YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ X! @& e% f* A$ MMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; F0 b0 p) H+ _7 F2 d& MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
/ F/ C$ r+ |5 Q' c# ~4 b3 YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) S1 o8 O5 E9 g1 w* ]4 p; t" x" a8 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. ]) V. Z! Y7 |7 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
+ j' y9 n0 Q3 S9 E5 _) ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ \) y6 y6 v- _+ _- x1 CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 _+ E( F+ ]( \# [# M8 }. @6 ^% n( \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
) F8 K: Y1 W9 h8 [) t
/* Enable synchronization of RX and TX sections */
' p6 p3 ^6 y8 c8 o2 t; [3 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 x$ g3 k% P" x7 Q. yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
* ?; h5 b8 w! F: M** Set the serializers, Currently only one serializer is set as
. y; Q$ o5 k7 i** transmitter and one serializer as receiver.
) h$ V3 C& ^# p. e: A*/
& p" }) ?5 P9 P; f; ^; g# mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
$ w+ Y8 ?% B3 a4 _5 s1 L. ^** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
! ?! ]/ c6 |* c; x& vMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) n8 B# o1 i, R! J) eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) i6 {2 F6 h" g" Z: `| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# W9 M4 s4 ~. u+ ^8 D! _3 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
1 P9 i( {/ U0 U! l6 y& [, E. {0 _| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
$ y1 T' [* n1 ^0 d* [' R: f9 R}

static void I2SDataTxRxActivate(void)
{
. b8 ^# s" K/ F# c" F2 h# _  h- q9 H/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. O& p# z) M) VMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" T, Y. [& d1 S# ?) s$ D8 GEDMA3_TRIG_MODE_EVENT);
5 u$ k& p1 w, Z' R" FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) P8 L: U. I3 l$ l' o2 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 A, L# d; t, U. c+ Y$ R0 D- H: UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! q: z. |8 q: @) k0 E4 GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
: ?* ?6 R$ a: p, r) _* Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& {6 E6 _# e* y/ k- H% a+ k5 @6 {' X}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

! c( z4 M# s" ?6 U, w