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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 j0 H* w9 @$ e; L% F' v" E( |
input mcasp_ahclkx,: d. R+ P' M4 i: ?( y4 r
input mcasp_aclkx,
- `6 a+ D& {9 w- `! T; Q" d" [4 _input axr0,
) Z+ J5 L( L# I/ ^
' f; r; ~8 [# W( @! W$ V& Routput mcasp_afsr,3 I& |% L. Q! e, P
output mcasp_ahclkr,
1 I3 n n( {. Aoutput mcasp_aclkr,* i+ W" k; s5 C$ \* W/ s* ^
output axr1,; p2 M5 B q, z/ s
assign mcasp_afsr = mcasp_afsx;$ l# M8 Y( o7 u& C b+ ~# ^4 @
assign mcasp_aclkr = mcasp_aclkx;
' a/ b* T+ l* d4 Cassign mcasp_ahclkr = mcasp_ahclkx;
/ v/ U+ {: E6 U- l0 D" O1 E9 |assign axr1 = axr0;
" p: `. \7 W' D! _* F4 A; T: o4 G) v# @2 p, s% ~+ l$ k4 a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, { U/ u: ?/ m4 ~" \! a" Qstatic void McASPI2SConfigure(void)
+ U/ ?0 ~9 {* X" W; x3 E; q3 g{
- R6 t' k. P$ f, O7 p- oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 F, Z: q/ w9 v3 i/ bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; f2 v1 f2 G' _$ k# |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! h: r7 ^ F6 b% a+ O4 o; F" m, Q3 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 [2 z \0 @% b, a0 @8 E7 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 Z9 L7 r: ~; J( S& i! l2 z* H% p4 m
MCASP_RX_MODE_DMA);6 P8 u8 S1 ~4 g6 z/ n& a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 S/ Z0 \3 F$ F9 y) `" [/ F, [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 W8 d3 I5 K9 c! @, l3 M$ ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; A# P; ]; S# j; s9 ^- i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 u8 u( [# o8 i% w% \0 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 Q- f/ z4 R+ N& ~# v1 BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
I# v3 ^4 R: F& `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); t* V: T+ Y0 ~& F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * B! L" F8 e0 A' J. v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 f. f- A5 d1 B% @3 A7 ^% k# [
0x00, 0xFF); /* configure the clock for transmitter */
- O1 Y* }! Z) @0 Q [7 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ J O# w, X, c3 |# zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! j% z4 _9 p- h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: q3 B" W! d$ F1 T( F' I
0x00, 0xFF);
$ U1 a4 s9 y& r/ [. } b/ g" y" T* I, Q- f1 g5 D1 W/ `
/* Enable synchronization of RX and TX sections */ 4 L* q/ o9 s) A8 M$ q5 ^2 l+ E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' D. ` p- T6 |% p2 ~$ CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 X' m7 q( z6 f- h6 j9 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
k' l1 s2 j5 K** Set the serializers, Currently only one serializer is set as: G: O: h7 ` t( Y1 i
** transmitter and one serializer as receiver.+ l- ]! ]/ B# x: o5 d
*/2 o2 o& L* q" G; D$ L( M/ l/ m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. u7 b) k% z+ l2 R' \& z! Z& WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 d, y8 X' E, u- N; }% l** Configure the McASP pins , Y" j1 J) Q( w( |
** Input - Frame Sync, Clock and Serializer Rx, w; l1 O# N+ I
** Output - Serializer Tx is connected to the input of the codec m9 s3 X7 S0 w4 _5 ~( Z8 g
*/% m, J. V6 e3 n1 z" `) [6 L& S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" X' {: D T9 f4 p% ]# U q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, u7 x( U0 _% q& f$ [* }+ ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 E: W: ]4 |( [2 c
| MCASP_PIN_ACLKX' I( S, r# J3 f0 I
| MCASP_PIN_AHCLKX
; a3 O* C. v& @1 Z" Z1 S: p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ?+ b6 u, B- {9 V( OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 d. u* o1 l3 r8 }
| MCASP_TX_CLKFAIL 7 v& s3 w' n& g0 A2 R$ Y+ C& u
| MCASP_TX_SYNCERROR% C1 ~! Q, ?! W; j; m! V6 s; D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 U0 q" T& J3 _/ _1 @+ _- V7 c. ]| MCASP_RX_CLKFAIL
1 ?. J% D9 v. @) k; \& o; G| MCASP_RX_SYNCERROR " n* I6 e. G$ ` L) R* A- p6 T8 | ?
| MCASP_RX_OVERRUN);2 w* ~ I* @$ W6 a' }& V* b
} static void I2SDataTxRxActivate(void)/ m+ O. z5 N0 q" g
{
' s' L$ u/ }" O& r. ]1 e) q/* Start the clocks */
8 F7 O1 c8 U6 M7 R8 i4 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 l: ^- ^9 j8 m# L# Y+ i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. w$ M2 \" o% a% u! ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 o. y& [9 I J3 Q
EDMA3_TRIG_MODE_EVENT);
. h% [4 e7 O0 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. c( k) w9 r! ~. [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 o! C+ Y+ ]9 k5 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- y) x8 g, j. `; v& s4 v4 dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. v- o9 s) N4 F5 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" m- z9 A+ w- {. @+ Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 L1 L5 g! V/ z. _4 v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. P0 r# c, Z5 w, u4 V+ T
}
2 q+ ~$ Z/ t& b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 o8 Y: ?! c# k6 b! F
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