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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 X/ [, l/ Z5 l2 N/ n. O" pinput mcasp_ahclkx,% ?3 S7 c- {, O8 H/ p2 `& A& M0 Q
input mcasp_aclkx,
1 y$ I4 [" x( _input axr0,
: ?; {' g- u1 n& Y; c
" P& ~0 \: { k0 ooutput mcasp_afsr,+ C+ ^' r1 a, e+ B6 ~$ ?0 F* e
output mcasp_ahclkr,4 u! w- N) y* U- h K" v7 K0 ?
output mcasp_aclkr,
$ S) v3 G# G7 k3 \4 Toutput axr1,+ F* q7 o! N7 M$ K/ e
assign mcasp_afsr = mcasp_afsx;0 E% M, `+ {+ C* W! I
assign mcasp_aclkr = mcasp_aclkx;. {* Z( L* v5 }( `/ }% w
assign mcasp_ahclkr = mcasp_ahclkx;
/ t: b% v, q) L$ massign axr1 = axr0;
8 P8 _! \: k) w: O y# ?- J& R0 f8 P- C3 w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- O: b& z) R6 @' O/ P" f5 y' A7 L) Gstatic void McASPI2SConfigure(void)
: v; E$ C' Y- R+ }1 t( f{
2 l; X& G( N6 W& J+ h. nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- p* D8 V8 G! z6 Y7 E) k9 s: Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 q8 p3 }7 d! O2 R" W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% r7 Y1 W7 `% f% XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 t9 Y) E+ z1 A c2 a6 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 {5 S" T* k) \8 fMCASP_RX_MODE_DMA);
: F2 ?# J7 l* X3 e6 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: c, O, L. I7 |" L/ G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ }' J( D6 p0 l @3 e3 o/ B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , R+ v f& Z4 g( c# _4 d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ L9 Q: t; j" _ ]( ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 c |: [8 j! A5 n) `9 T- J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# n% T4 @4 E2 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); @ s) A) d0 ^" H2 K5 h# d0 F- ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% E6 U6 E6 A! t3 n7 k' o' {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 I3 a' l6 e7 a1 E9 O9 c' e
0x00, 0xFF); /* configure the clock for transmitter */1 R2 u( E* [8 N5 {8 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 O% _0 _8 J; i( V# |4 T2 qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 F) F; H2 a J$ |+ e2 U# BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ e( j" `: K0 q1 Z& N: w" J" q
0x00, 0xFF);2 [% q4 d% c% Y; b" q( q
/ B/ h M& P% d6 ?
/* Enable synchronization of RX and TX sections */
* R7 p& N, a) P. [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 |: A! m$ \9 r2 A) x6 G+ ~! s tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- A! i m! X7 `& P+ gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: L `- W$ R) M: Z$ ^% q4 G9 |* \** Set the serializers, Currently only one serializer is set as
4 {# i" Z$ |7 T. E1 x6 k** transmitter and one serializer as receiver.0 I- U7 l0 o2 K% E' v3 A
*/
9 p, M q0 m! g7 L3 e0 mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 K2 O7 J$ Z) Q# z' ]3 i7 _- JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 s+ g4 w4 M3 [% ^8 P$ S+ D+ b: ~6 q
** Configure the McASP pins
& X- J# Y- n c' c** Input - Frame Sync, Clock and Serializer Rx! J! u% Q/ q9 {# w: Q
** Output - Serializer Tx is connected to the input of the codec
) z+ [% b! K! M*/
1 ~0 B+ b) @ O* l CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( G* ` j! V, K, h& X& tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 ~' J0 F/ ^3 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' h8 B) X& K8 C, W6 F, l| MCASP_PIN_ACLKX1 E# ^5 g! {% {
| MCASP_PIN_AHCLKX
4 G& U9 t% }1 B0 k7 t2 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" E. u% O% z4 T+ z/ X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - {" p% |6 c @+ J
| MCASP_TX_CLKFAIL 5 D- b8 D4 v. g; I! w5 ? X
| MCASP_TX_SYNCERROR/ v9 k/ N- F+ {' O) X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + J8 A z+ Q+ i5 |9 F
| MCASP_RX_CLKFAIL
8 P8 \$ O0 r: r1 {5 R" z| MCASP_RX_SYNCERROR
% O; ] i0 n, ^* n8 u| MCASP_RX_OVERRUN);- |( l4 r& i- w4 y: t
} static void I2SDataTxRxActivate(void)* G5 y* J5 k7 ^
{
9 H O9 d0 c+ V/* Start the clocks */( q: @' o) F* O0 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& G- n5 H) L2 k) mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 V: T( W5 X4 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 r6 Y3 r* j8 | K; R& {! i
EDMA3_TRIG_MODE_EVENT);
, v; T9 F4 U1 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 N& ]7 d7 u/ xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, C( n* `! K) q; R* F" }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! V* t# x, }7 T# ~# h! AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ ~- }6 j: C1 h) u1 e$ W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# J$ o/ n) ]% |) \( PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# F' f* C8 a6 S* y1 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) }0 d: S- x: i) a! Z1 s}
. j- X( m# `5 S* V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % `, h- h% e0 r. l/ G
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