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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, N& [+ m4 Q/ `& a3 Z
input mcasp_ahclkx,
' @5 |1 Y/ F& m" K, \2 ?/ [! a. V U2 ^input mcasp_aclkx,/ [' L7 P5 X" y$ `" a3 e$ V
input axr0,5 E D. e ?4 C9 m0 u
+ B( P4 d! t' c& o8 qoutput mcasp_afsr,
! G6 O* R: w# Youtput mcasp_ahclkr,
! K7 X" L9 f( goutput mcasp_aclkr,
8 `* Y+ e" k+ f% u' Koutput axr1,
9 T9 ^7 [2 I. a2 z' `# ]2 b assign mcasp_afsr = mcasp_afsx;
2 X9 ^" F9 y! ]- Tassign mcasp_aclkr = mcasp_aclkx;
( r! j5 g4 C# A0 x0 G4 S1 J4 Jassign mcasp_ahclkr = mcasp_ahclkx;
$ F, W, h: x0 P Zassign axr1 = axr0;
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) w* s0 o# C$ |! K9 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + Q) K% I* D0 }4 _" f8 ^4 v
static void McASPI2SConfigure(void)
6 \( v2 ]8 Y9 ^" e+ Q{
: L4 a6 U3 `( ?; R8 q2 KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' ?8 |9 ]# ~8 t2 F* `; J. a! g/ S4 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ Q+ V3 M. ]# h4 `1 U' x ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% F& W+ m2 H, T% c3 f4 m0 m/ q& RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# C1 O1 I2 H+ K* i9 @: o3 t5 z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" \/ L# d1 x2 ^. k hMCASP_RX_MODE_DMA);1 A5 j- Q. L9 L' c& a# W$ c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. B0 t4 Z. Z& x- V* [8 L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& u( ~9 F0 N8 ]1 h2 Y& YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' h2 R" j4 v. N) }5 G9 W$ h# n5 h) MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: n4 a. F& b9 r# c- J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" ~: h8 v7 d# J* u! \8 q) r8 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 r( R$ ]2 J, [( t2 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' i# W0 L. c+ K5 j. W* WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # `7 H* m4 j- a( t9 ~+ T. A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- [- v9 [4 u- F: G0x00, 0xFF); /* configure the clock for transmitter */3 ]- [! m8 S2 h a5 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 M. \3 n e7 }+ a) |# I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 l( w, |$ j4 R8 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," K' u3 |' g3 w2 {- ?/ o7 W9 O) {; y
0x00, 0xFF);: t" J3 h$ b6 o/ [' P0 V
4 c' S$ p2 R* ^+ H* t
/* Enable synchronization of RX and TX sections */ , C3 l( f- Z; T: D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# c" V) v8 c! [' h p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: k; [5 h1 N; h+ D: L) ^* FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 o1 }! l9 u! ] d0 i6 q
** Set the serializers, Currently only one serializer is set as
4 G q9 W9 a- {& n; b** transmitter and one serializer as receiver.
0 X, B: M5 P# e0 j*/
6 v, K' o' E+ V; `( r- g# m1 o, l5 u4 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& o& h2 R0 U. K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# o" t7 H9 |0 ^& E' [" p' p** Configure the McASP pins
% X2 z: Q/ b9 m! S0 j1 X** Input - Frame Sync, Clock and Serializer Rx8 K" D2 t: U+ ]$ \% L
** Output - Serializer Tx is connected to the input of the codec
- a, ^9 f& R. m: R9 S; k1 d*/ w& c! C9 S% L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' f# h9 R5 z0 R* }0 T, z* U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) Z! ~( [1 r( i6 \0 O: C Q; KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 m J' a7 | g) R1 {% W| MCASP_PIN_ACLKX
5 x6 n a. o" H4 P! ]( V+ I| MCASP_PIN_AHCLKX
- G5 Q4 H# c' x1 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. J3 D" g( O- W( d, dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" J7 F6 L. a7 h/ e| MCASP_TX_CLKFAIL
D" w& D# N3 y( s) x2 M& l! n" I$ y. O| MCASP_TX_SYNCERROR
5 V1 [+ q- }. k# I- R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 s/ b" m! L6 {( g) @3 x| MCASP_RX_CLKFAIL
/ N9 L" [1 @# D6 u2 \7 U2 S0 A| MCASP_RX_SYNCERROR ! F( [9 s. w4 D( O! A: g+ m# |
| MCASP_RX_OVERRUN);$ A/ a2 ]! A$ y) Z- U" H
} static void I2SDataTxRxActivate(void)
, j+ Y, J+ ] i. v! g1 g7 y9 ]{: U5 J# w# N4 o2 i; {6 M* k
/* Start the clocks */
* u. G' U1 U4 PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 C& C2 P2 ^! t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" [/ \7 R" N% G) E" }2 [0 R4 S* FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 ^3 }) n+ ^, m; e4 h$ [9 i
EDMA3_TRIG_MODE_EVENT);
0 I7 ~3 R' U9 e8 p2 B5 x) uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! ]; t5 l, M4 q5 t, B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 T9 p0 F1 o9 i c- Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ~; I# i$ n2 s8 }( U$ ?0 {* ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 ~! x- {& Q- b4 z) `5 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% j( Y9 ?# V( _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: q y, I0 n% h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# m& d R+ q! M5 K4 _; N} % v+ s7 f" @( p/ Y! ?, |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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