|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! L0 s2 F* _! W6 z& a$ n& w
input mcasp_ahclkx,
% _, [. s% h0 U* s' t s! ]input mcasp_aclkx,
! } O ^) l' p R/ \8 Ninput axr0,
& q7 R9 f8 }7 L" v% S" N/ _3 B6 ~$ r+ ]. F
output mcasp_afsr,, K, e: d& e+ w. l
output mcasp_ahclkr,
( ^3 C, v6 x6 noutput mcasp_aclkr,4 V7 A% e4 C8 h
output axr1,( ]4 q' ]: E5 U' N1 ?
assign mcasp_afsr = mcasp_afsx;8 x' @" }% s% q
assign mcasp_aclkr = mcasp_aclkx;
0 U3 T; Q' r- N. _" Wassign mcasp_ahclkr = mcasp_ahclkx;, i( ~4 D) ?) V; R' i& H; ]
assign axr1 = axr0;
, X3 s" q& B+ C
3 N7 `+ Z% d) k1 M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ Z! H; G) l1 b& j# e# fstatic void McASPI2SConfigure(void)
3 |# V/ H5 }8 P{+ a; z) C+ D/ f" b! S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; F! b. ?. A. E$ `6 H) y4 P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' Z2 S- E6 \, MMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% s) R: U) S" t7 q, MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 V6 x' i$ g0 }4 [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 @0 P P! v' p6 ?/ k9 l5 J' h
MCASP_RX_MODE_DMA);
2 h: r, U+ p+ u1 l1 }# ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& v6 [" Q3 z) ]! p1 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* `, S% h) f% G/ O# f( O$ VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! h1 Y% H9 P0 ~3 e7 h6 s: [0 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& i* `( ~& z/ m s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' |3 P5 V3 a* T; t" y$ m& Y) ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 y8 Y( t: e0 a" ?3 u3 ?" b# \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 S# u. \: o% j$ J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . y t1 @5 B5 K. _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 J8 ?& U; b& \* N0 m, S4 |0x00, 0xFF); /* configure the clock for transmitter *// N$ P( T. n$ R% ?7 X4 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& i' Z. d" |! j! a5 I& j, d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# L3 M9 K! \, S$ k9 _5 Z( eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 q% Y: l ^8 N. o, r" P) O* N7 A$ ^. r
0x00, 0xFF);
& X- }- L$ j+ T' r, L) Y3 J {" q0 q/ ?) Q/ @
/* Enable synchronization of RX and TX sections */
J8 v9 V+ n7 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# p9 T5 i# A4 w# p9 [8 J# b2 PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, z1 s" E, ]$ X4 D# J# ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, _' ]1 W9 m6 l% L/ u8 N; G+ C2 b** Set the serializers, Currently only one serializer is set as
0 h) O& G0 ]+ F7 `** transmitter and one serializer as receiver.
/ Y4 M, Y7 h. {$ p*/
( A2 a W6 x% p5 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( K+ V6 E8 ?1 `5 N1 eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" p' Z# v S4 x4 u: I
** Configure the McASP pins ) i# _! i) T8 D. m1 U `. o; b
** Input - Frame Sync, Clock and Serializer Rx
! s* a# g' n. V/ t( O+ v** Output - Serializer Tx is connected to the input of the codec ) R2 T0 a! F, @3 t6 t4 u
*/9 c. P; S9 O, p+ W& N; N) ^! D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, ~1 T- c) X4 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 D, C1 u" x( w( w' U- W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX M" [" j$ r9 Z9 O- ~
| MCASP_PIN_ACLKX
9 r1 ~* R( l- T) e# v2 v* g| MCASP_PIN_AHCLKX* f( o. \1 f) ]9 G5 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 N3 P( k( J' _ b. R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR Z r7 q+ e3 V, G8 `
| MCASP_TX_CLKFAIL 9 {+ u, m% E+ q) |' Q
| MCASP_TX_SYNCERROR
2 J3 X4 S1 q o5 ~; y' t$ x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . _0 Y% x2 W- I0 e, @/ G4 q) J, Z
| MCASP_RX_CLKFAIL( T u# F3 ?) @" x( o
| MCASP_RX_SYNCERROR
$ l9 v( ~6 i1 m0 C! R8 f| MCASP_RX_OVERRUN);
0 [; p) d. F5 a8 `} static void I2SDataTxRxActivate(void)6 x: p' D7 V/ c- `2 ^' T2 x
{! M8 Q" _& `& A
/* Start the clocks */8 K6 k6 b5 M( E7 }3 Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& }' z/ e: k6 q9 T9 g3 {, h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! P. {2 h. z0 c) X* `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 i4 b: Z" Q$ @3 k
EDMA3_TRIG_MODE_EVENT);
6 a& y' Q$ a! F7 |) p% QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 V! O( ?- ]5 R2 E: D. s- GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 a- m7 M7 n) w( m; n2 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" {& D- P% }9 ?! K* z9 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 T0 a+ l7 j+ a/ rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 s' K. H: `$ O4 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. D. B ]) ], r U/ D N& z2 h) ^, ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! w* U: k8 a+ v x
}
+ j2 y0 O0 `/ E" n; {2 b% Z4 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " i. k9 n q1 _; J
|