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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 G" i% h+ t, a4 E) Qinput mcasp_ahclkx,3 ]+ t5 C n+ P
input mcasp_aclkx,' J& e, k( k. t( Z% X
input axr0,
2 j; P) n" O0 R8 H& O
( N: H2 N. S5 r6 h, toutput mcasp_afsr,0 P3 ~' w3 c$ R2 R
output mcasp_ahclkr,6 u9 j% S1 s3 y2 F; N# [
output mcasp_aclkr,0 s7 M) O/ M' ]9 q
output axr1,
0 y: _5 d( `8 u; e5 J) ^' w* `" f& l assign mcasp_afsr = mcasp_afsx;2 L, h2 ?) F% d) r+ d" Y1 H( Y
assign mcasp_aclkr = mcasp_aclkx;7 t' E( i6 s# Z" Y
assign mcasp_ahclkr = mcasp_ahclkx;
x$ M5 }3 Y6 l6 J% wassign axr1 = axr0;
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1 }' B5 n1 b0 z" Z" n9 f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " F8 i: @3 i6 |2 O6 @+ [9 `
static void McASPI2SConfigure(void)
/ a8 s+ {1 r {) O{' l" Y& E; K& s; w) ]3 U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- R7 H" A/ {& qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 A8 p! a1 K% F4 s( @: ~# W4 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 p) W* H* k K/ A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( X: y: K3 U$ @& e$ g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 x5 @# C+ Z* j) b1 n3 \) {# ZMCASP_RX_MODE_DMA);
$ Y- A I" t1 {) `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* T$ {/ B* s7 r1 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 i$ j+ `. J. |/ o5 L! e; S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ Y6 O6 L6 S i2 e% b9 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; e# T4 ?7 g; h$ O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - c2 J0 [. ?9 e7 {9 F3 A- J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- N K/ ]* K d3 \& ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 y3 \9 G/ C. @" T* V" a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, l9 ~9 d) |+ |$ cMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' O* r% q6 G0 }7 b( }7 R
0x00, 0xFF); /* configure the clock for transmitter */
- g0 ]6 g! j7 A0 [8 Q8 n! Z0 IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ?- `: P2 [' T7 G+ {5 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ g c2 @9 x# [$ y5 TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ O; H9 \/ D4 I m7 e0 a4 O% q
0x00, 0xFF);- a* ~$ Q' J5 i( q0 F
/ |$ I" }9 e: h3 |, v2 T2 z
/* Enable synchronization of RX and TX sections */ 4 {6 |; P/ n9 \; c) u: t% @2 ^ h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( {& d6 G- Q; A/ C. \; [ c& ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 b% U, c/ e' w' ^5 G3 A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% u! o% g2 G- D: J1 p+ [8 a** Set the serializers, Currently only one serializer is set as
* X4 |8 q5 v0 p+ Z0 w; T/ R** transmitter and one serializer as receiver.6 @& V _1 E' p! u
*/( Z4 n. g! P9 A! l; E \1 g: n" m3 `/ R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 w( S/ c$ L h( o1 k5 oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ ]0 s" Y# g4 r) n5 z* V
** Configure the McASP pins ' ~' _0 R; o8 u7 t3 w
** Input - Frame Sync, Clock and Serializer Rx! c4 P( d: t! ?) C8 O
** Output - Serializer Tx is connected to the input of the codec
- Z1 E7 A, \- X- s*/
5 w2 [7 l8 M+ e+ R1 [) eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- D( U6 `/ {* ~: ~2 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( s4 I8 v. t5 a$ A: WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- S4 l( M3 S- q
| MCASP_PIN_ACLKX
0 {5 H' |! {1 \| MCASP_PIN_AHCLKX+ W2 q3 c/ {9 I* Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; w/ t% l( L9 U a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 @1 k, N! b$ h( Y8 c h% G: v
| MCASP_TX_CLKFAIL + Q; P0 I5 }2 b( @; o
| MCASP_TX_SYNCERROR
1 P, h: s& {* e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 `* b: L7 c' @: T| MCASP_RX_CLKFAIL* |% }% _- D; H+ _+ [4 ~* E1 Q
| MCASP_RX_SYNCERROR 9 @! J. A! z! B# {# `- }# y
| MCASP_RX_OVERRUN);: k8 R/ G |7 k
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
b1 h5 J0 o2 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, J1 ]0 o7 q" b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* Z1 t; v2 u: n, X# y, u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! P6 f- `0 n8 B" q& WEDMA3_TRIG_MODE_EVENT);
" G( F( \5 |1 I% g% |* ?" Z1 c# d6 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ |' k: d& Y U- y' u$ G% m. r6 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 @8 |" V) O; @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' V2 b' D! y; B g0 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ U3 x5 ?7 s& T. \. p) f6 w% ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 |7 I1 o5 ?& N6 p2 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 d( t( |/ y& N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 y1 w0 Y$ _1 `: _) T}
( \% }0 W$ T. k7 x! ^3 Y' C. \. g4 V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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