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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 R3 n' k3 |. d. |# A, z o
input mcasp_ahclkx,
& ~$ C2 _0 {1 vinput mcasp_aclkx,# n4 U- F: n2 h# |* q9 l8 x8 \* D7 T
input axr0,
( r; |; @" T4 I! O& C. @7 u1 V+ M7 a. T7 O
output mcasp_afsr,
' A0 N3 @9 u! o# t0 P% }- v- Eoutput mcasp_ahclkr,
! f2 h! Y! ^- |1 boutput mcasp_aclkr,. |! G% v7 T( c
output axr1,. i# W& y d/ s2 A" I' @! w8 e
assign mcasp_afsr = mcasp_afsx;
* N5 j- _: D8 Y! V1 a0 Zassign mcasp_aclkr = mcasp_aclkx;" {7 P4 i: i5 ?- u
assign mcasp_ahclkr = mcasp_ahclkx;. H& |$ t. e4 d- ~
assign axr1 = axr0; $ q; q+ L& Z7 u7 z, q" C g
" t0 q3 k: t/ C& O9 B* C1 T( q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * Z, @/ }1 w( i* @. j8 Z
static void McASPI2SConfigure(void)& {7 O% h; b7 ]) G' f
{
% A/ Z( ~" S0 Q, l: d; A; AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 ?* n* W/ Z$ p y0 o" r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) `$ b% h' ?% |2 V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
z9 C( f0 w+ _' p# s! a" d/ XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ b3 V3 S9 N+ D1 m$ TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 b$ O3 L% @$ \2 o' y. R0 ZMCASP_RX_MODE_DMA);
4 @& R8 v, D1 A" VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* e3 p, p- N: @, Q" [( |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 |2 V* s3 r8 Y- s' \# K; d' cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & ]9 \3 p4 G. J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 a% A5 F: Y% f2 j: G; z5 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ i! E$ w: R+ p+ C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 h# v! K& F. d9 n K- j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 A* B( N+ i7 P# d% A0 }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 |9 c: s+ p2 j2 [$ j# ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: J5 N* a& v& G0x00, 0xFF); /* configure the clock for transmitter */
1 }* T" G9 A/ x& }- W. KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' k S. w$ p9 R u9 h: q! E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 H/ [; r b4 I5 ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 q* O7 O8 p% K6 [0x00, 0xFF);
; @4 V; L x3 C- Q
% b- U6 E& o7 j1 X3 ^/* Enable synchronization of RX and TX sections */ : Q: d& C3 m" ]8 n( L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: J2 e% x8 `, Z3 H! m5 d7 u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 X' A# Y1 ^* Z2 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 }9 o! Y0 g' h) j1 X** Set the serializers, Currently only one serializer is set as
# ?8 t/ X8 d5 d6 l" [8 Y** transmitter and one serializer as receiver.
! s) }, j: X1 k! p3 M! i$ D*/
' {) N' P! a1 F9 V0 b! k, KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" _' g& I- @$ {- rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. B0 H: @0 x, |# J" }! Q** Configure the McASP pins
( k) Q3 I* A! G& z# M) m4 | T** Input - Frame Sync, Clock and Serializer Rx, t- T* R" X# J# {2 c
** Output - Serializer Tx is connected to the input of the codec " i- s2 f) O$ w# Q
*/
+ @' \5 e3 d4 o6 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ C. u0 @1 j$ m! s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 j& Z1 T" Z+ x/ }, U, c6 f& k' a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, H2 p* v2 |( B: V$ b| MCASP_PIN_ACLKX
; Q! O# c+ g; y8 j$ u| MCASP_PIN_AHCLKX4 {+ V# |/ _4 n& }( n2 o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. _( R, G7 g" VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # C! g' p" J# I7 f! g- M. b9 a. h' |8 [
| MCASP_TX_CLKFAIL
9 X6 v) L9 u7 L3 x| MCASP_TX_SYNCERROR
. m# l' R; m+ q6 ]' k% `7 d) Y0 w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 I0 b9 b9 h* b2 r| MCASP_RX_CLKFAIL
4 C9 [2 k) F5 Z% O% T: Z$ ~0 w3 r6 a4 ^| MCASP_RX_SYNCERROR
% c& M! i% g5 r5 w! q) J8 w| MCASP_RX_OVERRUN);
- s- A' l9 i& J/ l7 E3 o& E} static void I2SDataTxRxActivate(void)
2 `) H. T+ {9 R4 {{1 d' ^ h4 t2 |7 h$ b
/* Start the clocks */
' c/ o* p6 R% L" U: NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 c" R8 F- R0 ~! ^6 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* o6 e* a0 j* }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, S- }6 a/ S% L$ y& S
EDMA3_TRIG_MODE_EVENT);. M' C% l* r7 \/ ^5 H$ s3 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; N3 v9 Q5 C8 ^: P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; [7 s3 w3 C' u; [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); @7 I( i2 Z: V4 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( y: \7 i n2 H. C: E8 ?: D- x$ S, S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 i1 y8 R3 g, E8 E1 ~! ?" }8 Z6 v" b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& S0 b- v* a9 P+ H! j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 h; `7 Z+ U1 ^: W5 P
}
, J+ @% n' F$ T* h5 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + w& V7 F9 V. v# i( a( a" }5 n" F! M7 E
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