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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 h8 W1 M+ J8 C: e/ Cinput mcasp_ahclkx,8 r! u7 ?8 ^0 R7 ?4 c0 J" P" n
input mcasp_aclkx,
5 N9 q7 v' J+ z0 B/ T$ Yinput axr0,
9 ~$ b' @/ R' d2 g- N7 `
" V: h& x7 {1 c! n8 Youtput mcasp_afsr,
( H) z5 A7 r# A- y6 P/ Aoutput mcasp_ahclkr,8 q5 C* \2 n5 [) Z
output mcasp_aclkr,
3 F9 R" G* Y, F( goutput axr1,+ j3 h) A# |: M3 X
assign mcasp_afsr = mcasp_afsx;7 K2 C( _$ Q; ~2 [! Z9 M1 }
assign mcasp_aclkr = mcasp_aclkx;
3 X# c$ o- v! ^$ D% D) M) aassign mcasp_ahclkr = mcasp_ahclkx;
4 D8 c, O5 b; v2 d' @0 Bassign axr1 = axr0;
, V3 Y, L1 c9 J
" x# G, C5 F/ x# S9 U( _1 }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! V! w, C, u2 ]static void McASPI2SConfigure(void)
! c+ g% L8 |/ m3 B* z! y{! d0 }) _9 [$ x4 w( t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ P- B, v* [ {, N: E8 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ V' R% g# R$ X; S/ d0 L% EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 ~) n" K2 J% ]* U2 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" e3 f& E- z9 D$ ]& U DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& _# @5 t3 x7 ~
MCASP_RX_MODE_DMA);+ ^2 w( d, i& v' {- \/ G. L5 V' `0 ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ _/ R- r7 I5 |# j$ \! GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ V4 \- }7 B; ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 g! p4 ]( W, S& V: |# H( C: VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 k0 t1 |3 P# j1 Y9 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* M. L1 R2 y) }* z$ A- MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* B$ |8 B* F$ M. h6 s7 u* W! r- CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 Z# ?# M! }/ E8 h3 U, ^/ J6 i, p" @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : O4 C: Q- s: k8 I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
r4 Q' o3 C$ e' _% i0x00, 0xFF); /* configure the clock for transmitter */. s. X* U5 ^: q7 Q8 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
S- ^9 Z! A( L! Z0 d$ rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & J" u4 K9 E5 X/ z# a- Q8 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% g% ]- ~# K& {7 {7 L$ Q4 e7 p
0x00, 0xFF);
2 t/ P, k& D# j/ p9 I4 y
Z% D6 i; a* T" `. p/* Enable synchronization of RX and TX sections */ 6 i( A, u R4 {/ k" H# \3 W ?4 U- D, r7 Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 s4 C5 e2 g( _# \# |# {0 f. B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ H7 ?3 e7 F6 j2 A$ @0 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% r; N) d2 n+ z' _/ B# ]. J+ {** Set the serializers, Currently only one serializer is set as
/ e+ D- a, w. j) R& m) d** transmitter and one serializer as receiver.* q1 Z3 W, g$ D' ~) [
*/
2 Y( b& t7 L" }; j( v. J! e* C$ eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 q4 a& Q( B$ \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' v7 |. r: Z5 u** Configure the McASP pins
. Q1 c; A1 S9 x** Input - Frame Sync, Clock and Serializer Rx
' Y: q% r" C: j/ s* h** Output - Serializer Tx is connected to the input of the codec
0 S$ u5 ?9 h1 M9 } K9 w; M*/
% p, Q% M3 s; N' PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. a; g, y0 x3 C( V$ j6 a- {# gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- l' |/ P; n) i- s% U+ z P/ e6 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 E. x9 \% C) j
| MCASP_PIN_ACLKX8 i" A4 w: d2 |) b- F% `0 A$ }* A
| MCASP_PIN_AHCLKX
- T" U1 q6 S J; n5 q+ |4 y# n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 W& _' c( z; A3 I' _, m6 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : e2 j: y' _6 n) h, k& ~
| MCASP_TX_CLKFAIL 0 P5 g n9 Z: F
| MCASP_TX_SYNCERROR5 a4 z+ m; `4 S& p: l) H) i+ Z( |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" ^: ]% e! I2 w2 Y| MCASP_RX_CLKFAIL
. V* I" S4 k: G| MCASP_RX_SYNCERROR 7 X* a) ?& f; q% x0 V( @. k
| MCASP_RX_OVERRUN);4 ]: q1 R. }, N
} static void I2SDataTxRxActivate(void)/ j* j3 {0 x1 I* {* {
{' D8 V3 D1 ^+ \% y
/* Start the clocks */& l! R; u) d+ t' }) M2 t* n. Q7 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 i7 P* _. t( Z6 Y' x/ H$ }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* k- H! H2 Z0 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' L5 v" B0 ~ ~4 v) m$ {
EDMA3_TRIG_MODE_EVENT);. m/ e8 j; B. F% O9 _4 a* e' c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. R! O. z' w2 I8 P8 w# r6 uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) [+ y& l; t% m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 J, `( N9 u* L7 ]% X6 yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ I% D5 T; f+ O7 H! ?( n5 T9 J& h3 {% ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 C/ C, b. \# ]; } zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 H$ x# B/ p2 t& T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ D4 W+ U& o# D4 J1 o: t
} # L* _- H6 F/ E/ X# B/ h7 r$ b$ _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) g5 j4 T( \9 M" |1 w5 y7 Z+ s
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