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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 w" F9 s+ H: ^input mcasp_ahclkx,
/ p5 {- r" @2 V3 p minput mcasp_aclkx,$ U" `! ~5 B4 b n1 ?. W
input axr0,9 I& z6 }) n0 B4 A& O$ u3 K
7 W& D* a( c: j4 M5 routput mcasp_afsr,
7 G8 J0 Z% G* w% E2 Loutput mcasp_ahclkr,
2 X- y Z% Z8 h& Joutput mcasp_aclkr,
1 R8 [2 Q2 r# {3 S y, w u+ Poutput axr1,/ [$ K# e, ~+ H9 U4 E6 y
assign mcasp_afsr = mcasp_afsx;
! ?% |: {7 N Y& s( |assign mcasp_aclkr = mcasp_aclkx;
, S' c4 l" r" v7 N9 ~$ passign mcasp_ahclkr = mcasp_ahclkx;/ F) S4 I1 S. r8 `; H0 ?" G4 s; R
assign axr1 = axr0;
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1 p$ G7 [8 k1 o3 k2 o: u在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + ?' Y5 d4 I# t3 T
static void McASPI2SConfigure(void)
/ O$ x* t; k' n7 A, z% h{
( E+ l( u# B8 D; aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 K( g" p- D) m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 z% n* K* N' ?! I6 v+ vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 l7 P/ ~, W6 N, Q" p3 eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, P% [9 V& g% _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 n) |, C1 _" Q0 B7 ~MCASP_RX_MODE_DMA);3 T7 S" N% N O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' O: v e8 K% ^$ QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
j; N5 v. L9 f: [5 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ ~' l/ n6 g: P7 r R; C) u# ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 k2 {' D/ F- ^! ^* o! H5 @: c7 DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / S4 j [- U% i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, A" c Y1 ~3 Q7 Q: C j1 ?& ]. nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; C! Y( _0 C* ^' s, r1 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # d% p% s( n5 d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% }8 }" ]: e' j8 `4 R* u0x00, 0xFF); /* configure the clock for transmitter */
6 R7 P4 ^; M. @4 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 T! M! E3 D+ Z5 g0 a8 S c nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / b& I8 N% o2 V: P% M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 u( X4 W/ t( a; e& T0x00, 0xFF);
. A8 ~/ T# L0 Y! q6 f
2 L5 I9 `4 _$ ?$ h/* Enable synchronization of RX and TX sections */ 5 J9 h6 `! M3 r: x, Z2 o# T9 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ ~, Z. n7 N/ _: y9 \$ [. x2 h; | p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" r& C8 V9 ~7 u6 _- }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ _: V5 N' d/ O** Set the serializers, Currently only one serializer is set as
% V* X+ D0 p0 v1 K** transmitter and one serializer as receiver.- r( U0 z) D/ m- w5 s0 s
*/1 Y: O1 b& T% f- @" Z" `/ `5 i; E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" W# x/ C- }6 N0 t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 F* |( t( E% R7 q6 Z** Configure the McASP pins / P" i: e/ O- H
** Input - Frame Sync, Clock and Serializer Rx6 a; f/ i+ I* Y7 Q7 ]0 h3 a+ }
** Output - Serializer Tx is connected to the input of the codec
9 t6 _- y, V; Y3 G9 [*/. A: c3 M, @' ?+ F& |: W( z. l) r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 V. b$ d. E1 J+ B+ L) f8 D1 O) bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 q0 W% H6 c5 p- ?% C+ a8 @+ j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 h8 O. `6 `, I- m, Y- Y| MCASP_PIN_ACLKX
$ Z8 v2 I0 B/ e| MCASP_PIN_AHCLKX
/ G, [7 p% g) r! J) w0 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' p7 T& V# x) |, XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* b) P* G ~' z| MCASP_TX_CLKFAIL
n% O8 g0 T8 U' D1 Q$ H* Z| MCASP_TX_SYNCERROR
! d) ]) D8 o2 H$ E% u" C1 ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # f! ^3 @$ v3 J; ^7 v' D2 Z
| MCASP_RX_CLKFAIL$ j i7 }% S% K! U8 ~' ~: r
| MCASP_RX_SYNCERROR
8 g. K% g" x- _5 ?| MCASP_RX_OVERRUN);- F; `% {# l; M# h2 g
} static void I2SDataTxRxActivate(void)) p/ T$ f0 U- {5 Z
{8 I9 p# k0 i% c- D! c5 k: ~
/* Start the clocks */
& P2 b9 y5 b9 AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' Q6 K+ K& g6 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& c' s$ e, g% N4 ~- U) A/ zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- p# k* A6 O3 F2 xEDMA3_TRIG_MODE_EVENT);
/ X& w3 x$ _: y" M! e: k& { jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' f6 W1 r( Z6 d8 s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& Y( V9 C& z8 q5 y1 ?; E, DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- \3 [1 s1 o6 y7 E% V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* s0 K" ~* V m$ @9 ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; l* T0 ~. v' L) N$ ^; p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, ?5 G; t; p5 s( j- J' ^5 X9 W4 h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
J1 r% J& m7 N, a} . m4 y$ n) G& x: I" A& r3 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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