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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( J& b/ c- g: B7 O# x$ V
input mcasp_ahclkx,: v& D$ X; q# U% }6 t
input mcasp_aclkx,
1 e$ y9 F9 y% Z' r2 B( k, }! n( Z0 L( Ninput axr0,, C8 T P' s! k+ `
! \, l! `! ? |- F( p% D; routput mcasp_afsr,
# [' o% d6 u# ^; b( Joutput mcasp_ahclkr,5 C9 `" k! @: z8 J( ] Q
output mcasp_aclkr,
7 ^6 ]# ]/ k! q, d/ J" i$ Routput axr1,
; d1 D' X$ t% X$ Y& l0 F assign mcasp_afsr = mcasp_afsx;8 G" `: b) Q- o! F
assign mcasp_aclkr = mcasp_aclkx;& B" B; J, L8 f( ^- ^
assign mcasp_ahclkr = mcasp_ahclkx;- m) H( e7 z) Y$ O6 E4 ]2 d$ f4 T4 T
assign axr1 = axr0;
/ W- u# G% o: j- D% K1 t1 ^0 x7 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 s/ }& ]8 Q( u9 p- T& i9 Nstatic void McASPI2SConfigure(void)
+ _; E5 W3 v0 |9 R" T- F{* x3 O! X/ S* d! J, C, _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 M' f8 z# s! ^- N; i/ e" B! M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 k% {$ P2 v8 g# B! j$ rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 D6 `/ A3 ~: E1 v OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 J) W: r5 `( b; O* C- I" PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 F. [! ^$ ?* G: y* b9 j
MCASP_RX_MODE_DMA);7 }. F7 f! m0 n& ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 {. m" O4 `% y2 |4 v% N* }8 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ }+ {4 c( u+ j: Y% l! [/ C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : ]4 M1 x! t4 H/ ^6 q7 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& ~) K; E% N9 O; d& G$ P& q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . O' P6 W5 |* j3 ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. i" g% D( {6 jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 S3 E8 g+ _" o. s1 B* E8 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , U+ O+ T( g0 Q% B2 B+ }" G5 ?7 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. { T6 i/ N# ]4 M
0x00, 0xFF); /* configure the clock for transmitter */6 U( z! {1 o+ V1 F! j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- V7 ?. j, d; a# a- L. N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- O6 b* G! _% h& n$ C* C @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% t3 S% k3 h4 t0x00, 0xFF);
4 i, F2 |; B; h- |2 v0 x X5 e( d) J! H( Z4 U7 `1 b
/* Enable synchronization of RX and TX sections */
, Q/ B( Z1 B" HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% @! y+ a, N* `6 z- W: C8 M( A6 r" V/ vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
H. i6 l2 _( ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 {$ c0 i" m4 {: T
** Set the serializers, Currently only one serializer is set as$ q+ z' t3 Z) B" O8 T2 B2 g4 k0 k
** transmitter and one serializer as receiver.
; z( e; U) }, i4 y) K*/
1 H$ l/ ^5 F8 Z0 B5 |+ r: XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 v Y$ j R5 u% x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, [7 X! }+ V# K1 X
** Configure the McASP pins
* ~$ ~+ s, y F6 U** Input - Frame Sync, Clock and Serializer Rx
6 G+ v0 J/ E8 H0 m# m, k. X** Output - Serializer Tx is connected to the input of the codec * V3 M- K. v3 |6 d7 Y5 m9 g
*/
. z& w, f" q' u! @; AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; ~8 z3 }+ L! @5 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) E, d( ?1 q" r$ @ GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# v0 L1 P& t& b2 U- N5 ^! l| MCASP_PIN_ACLKX
# x. {; N- s4 ~; \| MCASP_PIN_AHCLKX' @" Y) v: N7 A1 P2 R* `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- I; Z3 B- T7 ~2 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ [* J4 |# H0 }1 k5 t
| MCASP_TX_CLKFAIL
Z- c3 l+ [% q! P| MCASP_TX_SYNCERROR8 A- J" N1 C7 X4 s' \: N0 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 @3 e* H0 h: G3 o" ]$ M: F. [| MCASP_RX_CLKFAIL
: s9 @; i0 E7 G' Y/ ^| MCASP_RX_SYNCERROR : W0 ]2 K# g d
| MCASP_RX_OVERRUN);( Z9 @ h0 v' H$ y
} static void I2SDataTxRxActivate(void)& N9 x2 H: G1 `9 U% Z/ B
{
# s# \1 ?' S8 p6 T1 m& N7 r. u/* Start the clocks */, p1 u! H& o3 O$ _4 [) n% A2 w6 ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 z: l U R: y# @* Z& a# I- U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 O3 A" m3 \, q& |; aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ A; r1 D- V, j3 t, D! ~
EDMA3_TRIG_MODE_EVENT);) n. C) ]4 d2 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) E7 o9 X' [ s1 U5 q1 c6 ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 v9 Z2 g; u- T! b1 M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# O/ T# m' B/ m4 N) k1 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 i! `2 [' c5 R" |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' u. _( ], Z: k5 \% y$ d% _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: y' c& L" ~" o- {$ XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! Z0 T6 y1 Q1 Q
} I* G8 [% H. }2 q7 A7 M) m+ o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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