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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 h6 w+ M0 Y! P# qinput mcasp_ahclkx,1 f! P, ]5 O0 `+ |' ?
input mcasp_aclkx,
+ x/ d8 `9 g, J: |2 S; s3 Ninput axr0,
) u) r S# y# f& g5 d
) q1 O2 d" p! b3 routput mcasp_afsr,5 h2 e* c$ H# W5 @- i
output mcasp_ahclkr,1 y9 A3 m' J' Q9 N8 B
output mcasp_aclkr,) t2 h$ D! F: _; L
output axr1,
1 }( \" d' C6 e% P$ V* X0 v2 q assign mcasp_afsr = mcasp_afsx;
6 |6 ?) Q4 [8 t7 s' t) Y0 I! Gassign mcasp_aclkr = mcasp_aclkx;
& s# z' g* x4 k" S8 {assign mcasp_ahclkr = mcasp_ahclkx;
H1 L2 I5 @& E( ^assign axr1 = axr0; 0 S: Q. A( r# U4 f( u9 @- i1 N( v
. j5 n: a% o' d+ }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 [" m- P( v7 `+ {' ?
static void McASPI2SConfigure(void)
4 {- z4 q* J0 C{7 j6 W; Q* {5 u- Q* k5 R! o5 d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 ^5 @% c* L9 c) H% QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- S- Q% v3 F4 _" [( I0 a" A- Q/ z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ @2 {! A1 z& }2 {, g2 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, L# K% L) N$ ~ K$ | r1 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ o/ a1 e Y9 o0 d) }MCASP_RX_MODE_DMA);4 r4 J X2 t7 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ A5 b: W1 [: V6 n9 P$ g) ?; }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: Q/ D1 ~2 _/ X* Y6 G( I5 P. L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' I: }9 M$ F, B% iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 M5 w s" K$ u) U1 cMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . ?3 D' H1 r8 h4 h; u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; O# p2 }4 W, t9 R- NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* [9 ^+ L+ M" k: n+ g( i' Z5 `, K& RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, w- P/ I! _( ]' v: k2 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 e% b+ `( e" n1 o/ T/ g& H( F3 s
0x00, 0xFF); /* configure the clock for transmitter */
$ m! l9 J: n+ n8 c5 @! S- K0 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. H( k/ a6 C5 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& ?6 U' U4 A* ?6 u, }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 M' R, s# k9 G' x" [/ [6 y! z
0x00, 0xFF);
2 R y- ~* y a; V2 P% L
) k; {4 Z& W* h) Q( m8 g# W0 a/* Enable synchronization of RX and TX sections */ " o' ^, v4 l% Q s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# p4 w; n; F' PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' t( v" {2 y+ W, b7 lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; v y1 B+ ~8 v7 X2 o. P( W9 f8 b
** Set the serializers, Currently only one serializer is set as2 G6 F, n5 v, F% J
** transmitter and one serializer as receiver.
9 [" c; f) J- e& T*/
0 |' W [0 L3 A2 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ |2 o' V' p8 {0 U$ ?$ `" I5 n& S1 k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ L1 M8 C+ r z" B
** Configure the McASP pins
& w' d7 p* D/ Y% ]** Input - Frame Sync, Clock and Serializer Rx
# U6 S. T9 t- p; I$ _% C** Output - Serializer Tx is connected to the input of the codec : G0 T% U- @( M6 a& }! T
*/
} f: P/ w8 G5 ?1 \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ i' p" y3 P5 C' D7 k* PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 [: d5 N) {' S# } |5 v3 z& JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 |6 {5 U3 v6 _5 C8 |5 |) R| MCASP_PIN_ACLKX
' T ]; u, o+ [9 I$ ]| MCASP_PIN_AHCLKX- V$ E/ u( V3 A/ P* u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) j, x+ f1 ?& `" P- v9 M" iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " v0 k0 |" R. l. M
| MCASP_TX_CLKFAIL
, p4 N* w. d' o2 j+ P& @' r| MCASP_TX_SYNCERROR
1 a" g7 Q$ | ^' W" m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, ]0 c$ |8 [4 `- a| MCASP_RX_CLKFAIL
7 O7 {. N* K% M: k9 |7 x6 D' O| MCASP_RX_SYNCERROR * V; x1 `, E# U! h, H8 {/ ~
| MCASP_RX_OVERRUN);7 C& ~& w O5 s. R% p
} static void I2SDataTxRxActivate(void)
- C& X" q3 Q# ]% W i x/ U# ]( Q{5 ~4 o; C4 e1 n1 N) n4 ~( P
/* Start the clocks */
. V" f* n# ~1 M7 m1 i8 ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; i' e% V. B; l2 i) F0 P9 I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& r3 d# \6 d) y: i8 l d' |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: C" _$ @+ b1 J: o0 g5 w
EDMA3_TRIG_MODE_EVENT);& m, G% l1 s' t4 b% E0 t0 j' G5 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 Z( J' p3 J( F& aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
j0 k9 I" e8 UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( }& p+ c Q3 [5 t" X I6 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 s( f' Q/ X0 ]" Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" v# ?- c3 A- _3 [5 x3 t/ K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 v. w; l4 F# T' f" v, F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 H1 a! m' g0 ~7 J}
+ S* B9 ?1 @4 f8 g$ X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / W {1 t( G" Q, w4 l, p
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