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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 g8 ~/ o5 h! w- Q
input mcasp_ahclkx,8 C7 c# Y4 M! U) L* [
input mcasp_aclkx,
1 P: M( V2 r" G# H; Iinput axr0,4 S# S" e) h$ `1 p) j- j6 c
6 Y% k# U9 b& R) C2 G6 `
output mcasp_afsr,
9 m) ] I2 e( @8 _8 T0 qoutput mcasp_ahclkr,, H" @6 s# U* P6 u
output mcasp_aclkr,3 H3 r% a! K( {
output axr1,
6 R# {$ @- n- Z3 C9 o5 v assign mcasp_afsr = mcasp_afsx;3 T$ ~9 p \# H$ U/ @: M
assign mcasp_aclkr = mcasp_aclkx;
* U6 \, `7 ]3 e- B$ Zassign mcasp_ahclkr = mcasp_ahclkx;
8 h4 G3 [+ z. p' l# F6 w# iassign axr1 = axr0; 1 d& J2 k0 d$ j
; j0 m) Z! W; B+ z* [: j& S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: ~: B1 ~0 u. M- A* ^4 c! xstatic void McASPI2SConfigure(void)
0 [/ [# M. Q0 M4 Z{+ L8 q& m+ w% X- ~$ G: @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! p! a, z8 L8 v8 l4 B% y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! ]! ~" |) l) s* o% O' n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 `" u' E) I) S* C+ \; jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ W3 @( E( U" `, H" o3 v1 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& g) Y; {8 j: B ^) W( _
MCASP_RX_MODE_DMA);
3 X5 t4 l0 `. \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, l2 m3 E" B, M- U4 o+ F6 e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# y! p8 f! |* ^, V4 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 l! F: K* o' P s. HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! P' y* D0 _! q2 J$ f6 A: k) c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ j1 f/ \/ m% i( P* ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) S- q4 c. O: |7 r1 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 Y; r! q, P, Q ~4 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; h& D" B" K8 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& ^9 I, w7 S& A, b1 }7 @0 d4 D
0x00, 0xFF); /* configure the clock for transmitter */
3 }6 v$ ]% ~4 \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 w" b4 M5 L) U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 H& k3 b, N0 h2 _% E) y0 K9 k9 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) O5 ]9 K0 E! S% n6 D% X8 a
0x00, 0xFF);
0 J/ p4 l V, V6 m* Y j8 F3 f) w7 i5 q" l. {
/* Enable synchronization of RX and TX sections */ " i" W& B% J7 M1 f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 o3 y7 n/ Z- x3 ^0 Z/ d3 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( p8 `7 L6 D/ w. e# p" l9 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& c' `9 `! O) V0 C! W. g** Set the serializers, Currently only one serializer is set as3 [% Y. v$ Q$ J/ _! x3 M
** transmitter and one serializer as receiver.6 R% s( U" t9 r8 _# o: M( w! Q
*/+ P4 h- @8 E8 X( u
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- a2 d+ U4 i: Q! I [( B: c- M" |! k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% N+ K% ]2 i* z4 [6 Q' C% C
** Configure the McASP pins
2 \& W; x' ~2 r5 P+ i0 E8 ^( D' Y** Input - Frame Sync, Clock and Serializer Rx
4 d* K5 U2 u1 c( I- G5 }, s** Output - Serializer Tx is connected to the input of the codec
6 E0 c, Y+ }7 x% f5 n4 E*/
: Y9 F7 _+ l" m* {& }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 G3 l3 g) I" D5 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); X& ?& g% \& \* K0 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 I, `3 i' ?* E P8 | c
| MCASP_PIN_ACLKX
/ ]" x- B8 K; Z: N* k, u| MCASP_PIN_AHCLKX: c; c& @ v! m' Z6 s+ I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 O! \1 w0 K0 S, c+ k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 F" P: f# q8 @| MCASP_TX_CLKFAIL
; B- {. W$ S4 S0 ?% u$ ]8 h| MCASP_TX_SYNCERROR
- w N' a t& `( B) X5 _5 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% G; y2 n! [; _! G| MCASP_RX_CLKFAIL
% ?$ j: | ^) v% ?+ }9 k5 F: c0 A| MCASP_RX_SYNCERROR
, t: X; o7 t' ^| MCASP_RX_OVERRUN);' K' q8 E( d# X* U! [2 n% p
} static void I2SDataTxRxActivate(void)
7 t3 Q8 ~# Y- v$ x* P{
+ L' L) d* j% ?1 T4 W& D/* Start the clocks */+ e3 A9 h7 w5 l% P0 b& x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) g* ?( A9 V! M/ aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 H1 V! T9 @8 m( V% Y& W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 h8 w# ~& k% }! z/ vEDMA3_TRIG_MODE_EVENT);
6 C8 a+ O. B( O; jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! Z: l- v5 E( F) s) f9 N: BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 R0 u% L6 o& |4 l5 r, UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Z$ _0 a6 @4 O S/ x! l! s- Y) DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 Y2 E3 Z6 l `, X! ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! F3 ]. e0 b, ^& M$ K i3 `9 a8 C0 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ ?3 E; `1 n5 z& h: xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 ?% S$ d4 y9 A z/ ] X d}
% P+ v0 W3 R( K7 C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' u; L: \4 d- y( A, {3 ]: c$ @
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