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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 s" P0 ]) S+ m$ A2 u
input mcasp_ahclkx,* `6 c( x. h. G. ?: b
input mcasp_aclkx,1 n% v% \% R+ O* Q" I8 M8 H
input axr0,: @, t, a& D* ^
) _( F; O$ P4 V4 ]! k/ N: R8 x
output mcasp_afsr,
& n5 O# r1 ~% m5 a+ T. Y9 b/ xoutput mcasp_ahclkr,
0 w8 g" |3 T' c/ D4 H: Goutput mcasp_aclkr,* |0 b0 A+ {( }0 `( Y
output axr1,! _6 g7 H! y) c; l4 F7 p7 c, x
assign mcasp_afsr = mcasp_afsx;0 C1 p" P3 z! Y& d- Y3 [ K( O
assign mcasp_aclkr = mcasp_aclkx;
- B" p. M- p7 E# ?; ^' C! Nassign mcasp_ahclkr = mcasp_ahclkx;# p- p F+ B5 q7 c: U
assign axr1 = axr0;
% ]& K2 }8 d3 f! L' \ P3 ^( g: c
) Y1 H" W% D8 y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) s; d$ C$ _; {4 G# f }# N
static void McASPI2SConfigure(void)
% v: k5 S; O( W/ a{5 @( a5 [8 o* c0 r: f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 b1 R$ i* ?7 h- G% P1 j8 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* |+ r# R, T- L) H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( y2 Z8 U( T( L1 T/ ?# TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 A% V" Z6 g" e7 O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 U0 ^5 F* {( V2 j3 k
MCASP_RX_MODE_DMA);6 V$ l4 y+ j1 r& R) p+ y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. V) o$ ~6 C% \2 l6 Z, q7 HMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 N. w0 f% |5 p1 q; K+ M: s" o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% U& l- d3 a( k1 b; }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 `1 j0 D! U3 _* L5 S% \% ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 d* F6 ^' Y q6 |: }& z3 T4 Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: |. {7 Q' ?6 J3 W6 A G" E" [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: E( X, R0 v; S6 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / q: Y& A5 E4 }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% {3 o5 f" `# m6 w: F4 N
0x00, 0xFF); /* configure the clock for transmitter */
0 k7 s( W& G' D3 y( S! Q7 tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ Q. I# Y8 z0 q2 A1 F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . ` ]& d/ {; A, `
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' j! o9 _1 I9 j0x00, 0xFF);
# P B; s# j9 t6 q
5 [. b+ w5 j! a/* Enable synchronization of RX and TX sections */ + V* c! P/ L- g: t Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 J a$ x3 l. X" h$ U: R2 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 G5 _5 }2 I' ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 m6 K" D; g) D/ H1 E# {
** Set the serializers, Currently only one serializer is set as
) c5 Y) |5 S" k& B. y* E) J2 R1 c** transmitter and one serializer as receiver." _1 e; I5 ?4 R- T6 q0 m; D
*/
* _6 K" w% S: h7 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- [6 o- f% a1 I2 W9 b+ p RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* d. t1 b9 Y3 H0 W2 b** Configure the McASP pins . Z. w, V! _) t! X( R; z
** Input - Frame Sync, Clock and Serializer Rx
0 z! q, o! `4 y5 _4 k7 P. t** Output - Serializer Tx is connected to the input of the codec
) s0 o; R- P% X" d2 I! p*/
6 V. Y- ?. ^: M! ?* WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( `" H1 A2 h: A7 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 R4 y7 f/ E1 T! _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& Q m3 d. P( c1 v( U# a| MCASP_PIN_ACLKX; e) r8 T% X3 O3 S6 R9 ?- V* E
| MCASP_PIN_AHCLKX/ f) Z. X4 ?" I- {+ Q- C& m5 `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 d5 S# n, W/ Z, N1 _2 m2 N3 d: g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! W: G' R1 }+ O) [: I8 U+ X; z' D| MCASP_TX_CLKFAIL
+ @7 W$ P2 N: n9 ~| MCASP_TX_SYNCERROR
" Q/ t/ {' t3 f' ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % w& m+ \! f0 A5 ]: u/ C
| MCASP_RX_CLKFAIL; F0 h) {6 S! A* p8 w! y
| MCASP_RX_SYNCERROR
. B- i" _5 {4 ^% X| MCASP_RX_OVERRUN);) I% i. N. e4 T" W n
} static void I2SDataTxRxActivate(void)
1 R4 e r' T1 E{& u* m9 g0 t( A* v# j8 @/ p
/* Start the clocks */% l, s+ T7 n, ^* z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 G6 c3 A2 T. ^# w, hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% D) r3 F i8 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 ?4 a) S/ C oEDMA3_TRIG_MODE_EVENT);( D; c6 p3 r4 ~4 q4 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 i0 J0 z7 Y( i: H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( M( T3 f( ~ r) N4 tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) ]. ?' x2 q7 p2 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: J. |6 k/ J. M e% Z$ Y$ D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ ~" K. t7 X7 FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) a! I$ {& c* v% X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: }3 u' i+ A7 E9 |4 C2 ^
} 5 A* w# [/ k" V& B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : m/ b$ r+ [: p
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