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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ [. F) i) M( z+ ^! d3 o3 yinput mcasp_ahclkx,% l, z# v) ?/ o( q5 g
input mcasp_aclkx,# |3 i" r4 _& r: X' s9 q
input axr0,0 S( n( y& Q8 R+ j
' I& p, C$ Y9 F* q9 Youtput mcasp_afsr,
3 q' O$ e; _ k& V3 loutput mcasp_ahclkr,
+ Y- Y& s1 \5 M/ t3 B' s+ Toutput mcasp_aclkr,
4 |/ \9 I9 Q4 [% k1 A5 S: moutput axr1,
0 r# t& c/ g J" f% l/ t" ^( T assign mcasp_afsr = mcasp_afsx;
- J0 O6 Y! d% o$ ^8 j9 u& qassign mcasp_aclkr = mcasp_aclkx;* U% G: X. G7 Y2 |
assign mcasp_ahclkr = mcasp_ahclkx;
8 ^/ N# y W8 E: ~$ sassign axr1 = axr0;
7 {& m z" C0 ]# d+ U! z/ y$ B" X/ R, w2 ]- ?- x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* X; s! O! z$ t+ bstatic void McASPI2SConfigure(void)
8 f2 F$ b* g* Z) J$ h- O, S( c3 n{
8 @& m1 o0 f V2 U% QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. p+ M" }4 \$ S3 D$ S/ SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 _1 f$ h8 ]$ H3 m: p' C3 |6 V& K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 B( I0 V' M2 T; S0 @2 O/ }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 p; r* s, D. Z# v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 f2 T4 z& X% F2 {MCASP_RX_MODE_DMA);
" `4 x% _7 M5 F# c* aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; h( ~6 `) H( WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 M) N: m/ G, {7 ]5 |# {- w( ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + R4 X" J' H# m% e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ` G, z4 z* s9 K' z- GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 O# w% w% U# P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% o6 ?7 g. I; n4 p2 a: i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 f5 c r3 H. cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' @ j5 M( K# G. o' P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! r+ u8 K `( U& }
0x00, 0xFF); /* configure the clock for transmitter */
! b: {1 X6 \1 t* O( MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 P# Z' f! I3 I; G+ Z% aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* k6 p+ j# W7 A2 z5 e( z# T5 wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& T* D$ a/ u d( g3 ?" P; A1 b- `0x00, 0xFF);
5 {3 y( u8 ]. r: n! Y
@ q+ ?' j( ^& ^; d3 s) o/* Enable synchronization of RX and TX sections */ 3 T% i; k7 d* [5 M' g0 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. e& R5 k/ C. a4 ^% w8 ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& @; j# |2 S& h9 K, B; ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ p& |) B& m. V8 {9 O0 }
** Set the serializers, Currently only one serializer is set as
* e- h) y2 ?0 Q( ]1 a8 J( H" r** transmitter and one serializer as receiver.
/ { J7 [/ u$ [7 e* [1 ]*/9 q6 }& V4 s3 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ E% n* n* O: @' XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* S8 z. d( P+ B4 X: E
** Configure the McASP pins
4 B$ d' ~6 Z5 |) s3 X% ^6 n& i** Input - Frame Sync, Clock and Serializer Rx3 h1 r8 x" {, [
** Output - Serializer Tx is connected to the input of the codec
# [! e* g) g; `' n) n C*/# b/ F0 V# y% M1 r/ v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 V2 k; O% `- v* FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% E: _7 K" i( Y" M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* \3 E, T# ]1 H# ^6 @
| MCASP_PIN_ACLKX
} `% f! F3 O- H+ Y% |6 g7 M| MCASP_PIN_AHCLKX
0 d6 u2 V6 E2 \. f( E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; v, ^ b, s5 x, O; \ X2 A( yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' u0 c8 q' K" H% C+ f; j# Z| MCASP_TX_CLKFAIL
- z0 `8 a& J @| MCASP_TX_SYNCERROR
5 o8 h9 [, h4 S* M% r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' w. x& t- e+ i! r
| MCASP_RX_CLKFAIL; O, a L- f- s6 N: v( W6 Z
| MCASP_RX_SYNCERROR
/ S* N" H7 W8 e1 l2 M| MCASP_RX_OVERRUN); S9 \4 S* {/ C- Y
} static void I2SDataTxRxActivate(void)
5 B3 E$ F" _- v9 }- _{* C& p# k9 O2 |* x; ?
/* Start the clocks */
! D9 p' Z7 [% A6 G: f c: d3 EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ Y! h. r. c1 v! `% JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- h' Z6 y" e0 v% {7 c& X* P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 q7 O/ w* h& k+ Q9 s. v
EDMA3_TRIG_MODE_EVENT);
* `# t! g! Q+ Y% N2 W4 T& XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 v0 g \! ?% i5 O: L* [6 I$ sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ }% ~, C1 t( ~3 N6 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' ]3 w1 X+ [! T7 N+ w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 p) M3 M3 B0 _6 T( kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) S# |9 ~7 n5 g& q: WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ r5 g- S/ [1 x1 y0 ]8 W2 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 `2 e g4 j+ p. b}
6 {/ x; g3 F$ W* ~* \" p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 Q$ b( ]1 n0 m! @- K5 b, H |