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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& n8 Y* u$ I( z0 K
input mcasp_ahclkx,
: k7 o! C$ n, M- K, L7 o3 cinput mcasp_aclkx,; y- m- @" j" X" `, \: g/ @
input axr0,
( v3 }* L9 k( i6 Z* a
, F0 D6 D& V" ?! p& @8 H& U G0 {output mcasp_afsr,
5 g0 d( d. i; h3 z6 _* ~' Boutput mcasp_ahclkr,
9 e# f: Q; F; p9 [, I4 b) e# joutput mcasp_aclkr,
7 M; K+ e( }. Q/ I+ poutput axr1,
( p! h) e. _: k4 n! \! [ assign mcasp_afsr = mcasp_afsx;
; L4 \0 Z; O, t1 q# C" z; Eassign mcasp_aclkr = mcasp_aclkx;
3 s: q, s: H5 Y+ Y- Y% N) passign mcasp_ahclkr = mcasp_ahclkx;
1 d! V2 d2 ^' l. m3 M$ h; `assign axr1 = axr0;
# u* b' I( u* s
9 R7 ~7 O* Z; Q. x5 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, t2 ?' O0 l* Z) J! E/ {static void McASPI2SConfigure(void)
" Y# _; @1 T$ }# u" A" R$ _{
& r3 F9 O( D% U5 b3 h4 PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 t+ a+ ^+ z& @* h9 n V" V+ XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 @; r: k4 O8 X4 d# ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# A- P( s& ]+ d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* i6 Z: M4 I+ x/ @: X1 G- a3 T6 G* G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 t$ D$ D+ v: z; \# @- ]9 R6 [
MCASP_RX_MODE_DMA);6 P/ [. i) k& u$ G( {" X- X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 L' [' h; ^! n$ u0 j" rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 R3 z ], {+ mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, N/ A5 j4 A# }& s8 T: {4 B- yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 o: @% R/ B+ r9 C' _1 ]. Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : y0 O/ ?9 E! k6 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% z4 g3 U5 q) G( Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- ^- f' s; K7 f) `: F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / e b: Y, M: @/ k2 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 J2 @* r2 O9 z) m. I; k
0x00, 0xFF); /* configure the clock for transmitter */
. K) M% {0 @( t0 |, h# a* dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 `4 u) F$ m% P: d' F4 TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / p/ B) U4 E/ m4 A$ @+ G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; f. d) ^8 q% |% X3 s
0x00, 0xFF); G; }7 l3 B: i" a) g1 D3 ~
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/* Enable synchronization of RX and TX sections */
4 Z* D- j7 `3 p3 q+ VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 X4 D& Z/ z. M' }5 d9 h
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: z# T8 s9 r P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& X& t9 G/ P( X, H6 t! c
** Set the serializers, Currently only one serializer is set as
' e8 B4 _7 x- W8 G2 P" w** transmitter and one serializer as receiver., L b b; b( n5 r
*/0 b5 O* ^; g+ @' h; C/ N+ G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* O0 U' l$ c$ N. ?+ t+ t* UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** r! b2 c, f0 M' X0 l
** Configure the McASP pins , q' N/ f6 A" j u4 z# i
** Input - Frame Sync, Clock and Serializer Rx
1 w% u# _' U, t' f P0 i) T( M** Output - Serializer Tx is connected to the input of the codec 5 T$ ~( G2 z( u! t. i
*/
4 |1 U% A) N& v) D6 B& RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( e* }" y9 y2 ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: y: e0 A) U, g; y' B8 J% e4 I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: n3 C! W' R8 Q# D% u0 X* ~8 {| MCASP_PIN_ACLKX# I. ` @' a% @) w1 Z$ G
| MCASP_PIN_AHCLKX: h4 ?( T. w' A* T4 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; U/ y/ D& U9 I7 n) M$ [0 k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. |2 {4 t" W- o5 D) ~4 Y| MCASP_TX_CLKFAIL
/ D9 |4 f% r) P# L| MCASP_TX_SYNCERROR
2 w/ }& }! z3 Z* n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 M8 A# n# g8 C, ?: R7 a
| MCASP_RX_CLKFAIL
; l8 m) m! h( D& [" d8 s* |# N| MCASP_RX_SYNCERROR ( p5 G/ f& R0 i5 O7 S/ R% Z6 B1 q
| MCASP_RX_OVERRUN);
! s' W2 ]/ m7 [1 p/ R} static void I2SDataTxRxActivate(void)
, H9 R- o7 _; @{
S' S. n) `6 p/ p: j0 |* ]8 X5 O/* Start the clocks */
% [; l8 d' B9 H$ V$ ^) UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 h: }: y" H) p- g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ K6 w0 M0 O6 V2 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 `$ k. B) ?3 ?. _0 @EDMA3_TRIG_MODE_EVENT); ^ B. T1 N/ b( s7 F0 o4 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; G2 T" P% @9 M% g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* ?$ I w$ e2 m1 T4 {% j' f7 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# P% S' O! q6 n5 g$ W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 a& n5 V6 P2 f% F8 E% c; y- F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 }2 T. g4 c: H) B; o, V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, u) e& B/ }( UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; ~, c+ \4 u6 W- L. s k} ! H' ?8 H* a% s$ M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 r9 s3 l/ c$ u2 ?2 F. O
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