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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& n/ B! V+ j. u! Binput mcasp_ahclkx,
: h! s2 l' Y O3 @input mcasp_aclkx,
, N* m: W# ]8 @* h) M8 r9 M9 {input axr0,; O' N t+ U+ T" \
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output mcasp_afsr,# H% n. X4 I8 r( A- p0 _6 Z
output mcasp_ahclkr,! L+ K" h8 {9 I
output mcasp_aclkr,& v# t& X- V/ V" S$ w& }2 [
output axr1,
1 U; r; R* I+ S/ V) a assign mcasp_afsr = mcasp_afsx;
0 ~( t2 W& k- ? z3 X- yassign mcasp_aclkr = mcasp_aclkx;+ u: Z: t0 T( q6 w
assign mcasp_ahclkr = mcasp_ahclkx;; r. c% L1 {6 X5 d3 o/ c
assign axr1 = axr0;
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, z. L. |+ R6 I5 X* o! e! Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; i# V$ t) o, M! a! H- Istatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! n3 X/ e' T6 v; k! V( {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 r: L* R% @2 U8 l6 x7 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 N+ d) w8 m* O; ~2 YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 X0 M$ R. N3 u9 M. A4 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: f) C0 o* `/ n8 PMCASP_RX_MODE_DMA);
8 @2 o$ z$ @" q! g7 I7 Y. jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 `5 u7 v& I& O0 I& ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ d: A3 F& m3 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 ?; q( k& h$ ?. B3 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 m/ H8 U, f( J1 q- uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # B x5 l6 p0 P8 G4 @( ~ T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# E: B& h' S5 I2 }1 `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 Q! @# C: r. t2 Y- @; BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 I$ @) ~3 \/ y5 `8 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) k) H5 M! I# h0 s) z# l% w: d0 t0x00, 0xFF); /* configure the clock for transmitter */7 }# l6 D% f- q' b- b( H6 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) Y: V6 }2 O) ~5 w% XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; C/ n( d$ k: G0 A0 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' m4 B# `9 A& C2 J0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
% E/ Z1 k$ q$ e: {+ T# A; lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ _! E% B# Q+ y0 ^+ pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ v9 [5 m! M1 e$ E% d* ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( b* R3 Q1 U1 Z1 N( n/ ^# @1 W
** Set the serializers, Currently only one serializer is set as
( \0 e& r' J# I* V* R** transmitter and one serializer as receiver.- A/ u6 E( `$ R. A- j6 g& Q- A
*/
, U* s1 s, C+ |& N7 `7 M1 K9 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 T9 V; u W; K( Z1 M+ aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
x0 c; n6 y; E** Configure the McASP pins $ t9 i* U1 R3 R5 S
** Input - Frame Sync, Clock and Serializer Rx2 l4 X- y% N% u, H* Y5 k, ?3 m
** Output - Serializer Tx is connected to the input of the codec
+ J& _# _% \; h% w" a1 `# D*/! `0 y* i3 `; p* H, w* n% h6 V' Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; m( x& m, n5 w+ A7 E1 B* z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. P# M& m* Y0 d& |$ g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( j+ r' ]% I4 E5 V| MCASP_PIN_ACLKX
& k! C2 U+ H' e' l| MCASP_PIN_AHCLKX! v# d6 v9 u1 W! _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ V' e7 b9 f/ ]% S: BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / B- [* l% n r: e% D; R
| MCASP_TX_CLKFAIL
5 X$ S5 N( r8 ]3 p$ l' D| MCASP_TX_SYNCERROR
! T5 W! k6 o9 X, H4 Z6 D1 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ H) d! M: {' M1 m8 O2 A+ k$ N| MCASP_RX_CLKFAIL) |+ I; X/ T3 A" K7 P
| MCASP_RX_SYNCERROR # X8 C8 I: P1 G1 {0 W ]
| MCASP_RX_OVERRUN);
' K& z3 J2 M! `, q1 o: S8 e7 p$ ?$ I} static void I2SDataTxRxActivate(void)
9 h% h' C* c$ K{9 f7 M1 u* d2 M8 P$ u9 s
/* Start the clocks */
, C) ~' l; E% p9 _0 ~4 W4 yMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" b' r7 B7 ]9 y8 C; v$ e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* T& w* j8 e0 x7 A5 S- u0 `' O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 m& |) l# y4 UEDMA3_TRIG_MODE_EVENT);
) c% h8 N! D q' F! NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' N) k4 G( c! H; VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
t% T, K7 R& _0 g$ O2 x5 P4 ~0 jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ D7 h# n$ I0 K) c+ l0 }) k7 G& S- g# G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 \) q4 L8 g: ^4 l, Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' o) [; m0 m: j( B2 Q% MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. E* F7 J9 q5 W: Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 J4 v; q: _$ w5 m( p/ D}
9 L' {4 E( p# J) J( T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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