|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 Y! Z+ y& K6 p1 Einput mcasp_ahclkx,
* g/ H+ Z: E9 G2 @3 Einput mcasp_aclkx,
2 e3 F' `% M) \- |" X/ ninput axr0,- ]. |6 H0 \9 P: r1 ^& u) t
% v+ J# n/ n8 j! p5 K4 Z
output mcasp_afsr,0 Z s1 K! D& {7 z
output mcasp_ahclkr,) ~; R; G$ t' t* e6 v! P; C/ j, c m
output mcasp_aclkr,
2 M- c6 B' T9 l) ^, i) R6 Woutput axr1,
0 I% g- }- a* d1 i2 }2 n assign mcasp_afsr = mcasp_afsx;1 U2 X/ V5 e: J) _
assign mcasp_aclkr = mcasp_aclkx;9 B! x. j& W0 R9 M- Q
assign mcasp_ahclkr = mcasp_ahclkx;9 M7 v% P1 B, y2 h0 [3 M
assign axr1 = axr0; ! i d$ {2 c: g2 }+ C0 o! P' M4 W
5 R* v1 ]% j9 A; v" o9 P7 ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) V0 `$ v2 s# W( ?
static void McASPI2SConfigure(void)
* d9 H8 v# t% [' N: H7 h{7 m ?0 F8 H+ }# K' N) |/ N. a9 v, Y* R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 V3 @% p: c% `7 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 c% ]( H0 A4 n" N& X, f4 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% a: a! d9 H' Y6 m" t# EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 n9 O3 z# E: S" i, B+ K. ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# C& w) \& N/ o DMCASP_RX_MODE_DMA);
( F% x, c- { U" XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, K- s2 r9 b& U: W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) j' S9 K F7 U! E2 I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; s+ h0 _3 c; V8 `- f- ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 N6 G; ?. q2 n7 l, Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; {5 \0 f' ]6 s8 R7 @$ u/ IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) j/ w2 {& e W E7 t0 b3 e: rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 x% O1 h0 y) k1 O3 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ `& n3 |1 w% E* t+ J+ f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- D2 H0 S1 F4 N9 D6 g, U& s0x00, 0xFF); /* configure the clock for transmitter */
6 C( R+ B1 v3 g6 S0 d; VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 A; ]/ g9 p7 \& ]: W! A/ {* r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 R. Y+ g( r" F' WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 m# R/ G3 n. A8 ~9 R0x00, 0xFF);
, w3 a" W( A# B' U( N/ q, K8 f1 [- L/ @# i
/* Enable synchronization of RX and TX sections */
& a& M- F4 @( t( L6 w' V3 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 R. C6 l/ x9 g( z F4 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 x" X3 f2 u& ~+ I; d, U7 [' ^% Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 t- d" X2 D8 ?* A
** Set the serializers, Currently only one serializer is set as. Z1 L& P' o/ x3 y4 r
** transmitter and one serializer as receiver.
: ]! n6 N: z6 U' Z/ ^6 T*/
0 j: l" F* J1 g+ hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 c) u- j2 m. `" w' |; B$ V4 s8 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 Y/ M4 V) g' ?% h** Configure the McASP pins
% f% a. F" D! W( T/ @6 X% |* E- s** Input - Frame Sync, Clock and Serializer Rx6 o- ` O8 |% G# D1 z: m W
** Output - Serializer Tx is connected to the input of the codec + y2 }$ y. ], E$ H
*/
! [9 i# n9 I" g( @1 zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 p) N5 I5 C6 u; S6 Z& VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 H3 F# c; I( V# }* l/ p' V( l$ ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 Z8 L; g6 M9 B! H5 [| MCASP_PIN_ACLKX2 u3 G! n* f9 f
| MCASP_PIN_AHCLKX
/ s1 _# m$ W; ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 } E+ t9 E% r. y* GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 z" Y u7 {* @6 A* H| MCASP_TX_CLKFAIL w1 L" \/ Y3 N" D' T3 G
| MCASP_TX_SYNCERROR
" A; e3 ?$ z) Q2 c9 X* g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 x5 @8 A! K" c9 a" b# S, l+ N! t
| MCASP_RX_CLKFAIL
* c p1 Q+ e [$ r4 l| MCASP_RX_SYNCERROR
4 Z. e! B! m" o7 j- ~2 M* b! K| MCASP_RX_OVERRUN);
) s4 y+ A) j0 Q5 m} static void I2SDataTxRxActivate(void)
5 Z' V" Z0 f3 c) \{1 m2 m7 K3 i3 G
/* Start the clocks */* y6 ^. }% f3 W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 k; ~6 i" ^) K1 [: d" V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 ?8 r0 \. o7 Y* Y% v( S; q# ~# y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ Q' r6 U$ B! `: xEDMA3_TRIG_MODE_EVENT);6 F1 _" `9 W! c+ g: V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ J' j4 y% t- R$ _( v0 VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 u, F6 n! G5 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: k: c5 v! S: z8 I) T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 r# X% q8 @/ u- h" |7 Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 }9 k$ p3 j9 w5 W! U6 ?' e5 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, y4 L* |6 E% x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 p( j2 H! l% h1 p3 i. \9 @}
+ d7 w+ `7 h# a3 a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. L7 R1 `: j3 P |