|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 c" g. i5 a2 `% Vinput mcasp_ahclkx,5 D0 \5 Q& U& }0 u+ R' q( e
input mcasp_aclkx,, \# J4 U& p/ z& m: o
input axr0,
+ {" f* u6 j! k7 E
, }- M1 T) q2 Q1 W/ z+ H U- N2 zoutput mcasp_afsr,
0 k6 s; _ h6 z9 z7 X( y/ ]output mcasp_ahclkr,! D! B' r* H4 `4 X* s
output mcasp_aclkr,' u# v( W, J$ a8 R0 ^& E
output axr1,7 _1 j9 o. i" w; O9 `1 e
assign mcasp_afsr = mcasp_afsx;+ U8 N/ p2 B/ H8 A5 ]
assign mcasp_aclkr = mcasp_aclkx;" l" i0 R0 T" r! H6 L' H8 I# g
assign mcasp_ahclkr = mcasp_ahclkx;
- ?6 s9 l; d8 @& W" U( m9 v3 \assign axr1 = axr0; , V+ p- K& w! ~3 {% ]1 E
1 k$ l& ?# e3 L6 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, n) t1 M; p) t1 \6 Xstatic void McASPI2SConfigure(void)
! n. Q' M+ U7 _: s& C{
7 k9 _5 E9 A$ C3 k# e! Z/ KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 {7 L& N; l5 }" E) g% B
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# z, d1 `+ q& r# R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 I8 K: `+ D. ]& K7 G9 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ A) J5 ~3 q+ F3 w& S* A( Q# g, YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& r% Y& C, e9 h9 qMCASP_RX_MODE_DMA);& k0 Z7 e7 R, Y6 X( h6 s3 h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. I' ~5 y: m- E3 MMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" t* ? K$ _3 j0 a# bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! M H5 i7 {8 x7 v1 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ J7 l; L8 R R' M! f' r1 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + o3 B% F3 W$ c. \1 d3 c1 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 H, Y% V8 N7 z; }/ J, pMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 Z& c' w0 U/ |7 {2 [, g7 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ ^+ K* p% b5 i. `. VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 T9 Q% x" V- x8 `* X' t0x00, 0xFF); /* configure the clock for transmitter */
+ S. w% J& h5 g, x4 W' VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# y3 W, h0 F1 F# B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 z9 }: A9 K+ @# Z" b0 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# q1 B4 Y5 t2 p2 U) A* t( N
0x00, 0xFF);4 S; v% X3 T) s( M/ O- v
5 v8 H! X' V9 G) l3 f/* Enable synchronization of RX and TX sections */ ' f; v0 F2 O) d; P! ]) D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 M/ t5 e2 L. f7 l$ kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# w+ h( x+ Y0 p' Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 c& V: M. W% d4 C! p2 x** Set the serializers, Currently only one serializer is set as# S y4 n% m, O D; R7 w+ {
** transmitter and one serializer as receiver.
( O: _1 I" r# y* N' Z/ O) g$ V*/- t7 T' E0 T( u( X. A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 j+ K; |/ a {4 Y. y7 a9 V' U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! S, z: H9 c4 r0 @1 c** Configure the McASP pins + y" x, C: f, I9 {; w" d
** Input - Frame Sync, Clock and Serializer Rx, a9 @0 m4 j7 A0 ?7 x; O
** Output - Serializer Tx is connected to the input of the codec - j0 M5 S6 j" O9 w: `) j0 l7 e
*/4 s C: I6 R6 \7 M. h0 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 x) g& M, g! k' b0 p7 [! s' O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 P( x+ X% Q `+ TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ r6 {9 p2 [0 q: n2 P| MCASP_PIN_ACLKX1 e- j1 F. R4 N9 a/ p
| MCASP_PIN_AHCLKX
1 J3 i+ h. L: y0 }' q( H4 s Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 C8 E l# ?' [3 j3 W5 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 W$ Q7 H& ]/ d" F4 W: Y! b
| MCASP_TX_CLKFAIL
2 D( \9 V. H; X1 T! ~| MCASP_TX_SYNCERROR: O; v9 R8 [. }, a1 D4 f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 B) b2 t- R% ?
| MCASP_RX_CLKFAIL0 w8 Z- g8 C2 H- a; P1 c
| MCASP_RX_SYNCERROR
" {+ L k" B8 q$ X, ]9 ^| MCASP_RX_OVERRUN);
& z% f8 n' d7 v) F0 q+ ^' ~" x' f" M} static void I2SDataTxRxActivate(void)
9 @( N% _; q/ M# ^{- x0 }5 W3 E0 c0 N1 t0 `- U' V- S/ D0 `
/* Start the clocks */
7 H: n0 s( _* s4 A7 y- x! fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); h! G5 w7 V$ s; [6 Q4 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 A& m5 J+ \& p( I9 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) h# g5 u. b3 R
EDMA3_TRIG_MODE_EVENT);
3 O, I! X2 _% H zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* n4 w, @4 j% r" U# t6 v, Y1 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 ?' ?; I& @( p/ t, g- W' s1 ?5 M# ` EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 P4 h% f0 y, V7 N, ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// y/ X; P7 V6 C) {; A5 ] \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 D) p# t! r1 l% j. J* y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. ~) B& |* [& y" e1 ]# w& i1 OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( ~" q; D" i6 Q; L$ N}
+ W/ o7 E5 T }5 P" R$ t6 @6 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ n7 ~( g% _ l3 n |