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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% G! `3 s! Q: j3 d7 K Iinput mcasp_ahclkx,( A% d @! b' Y) D5 @5 `
input mcasp_aclkx,5 m. l# s& n; B& P5 K$ l
input axr0,
' C% a# ?( G5 s$ z3 s* V( l" z( [) H4 Z H$ E/ x0 }/ q
output mcasp_afsr,1 d2 f) L e" `/ z: s
output mcasp_ahclkr,( d& w3 J3 n6 @9 f) m
output mcasp_aclkr,
2 [1 F8 i* f8 K2 q2 p& _output axr1,! ]! Z* H g; d: p# A
assign mcasp_afsr = mcasp_afsx;" f$ Z$ u! k0 `1 Y- [
assign mcasp_aclkr = mcasp_aclkx;
0 |; F0 W7 y Y9 Yassign mcasp_ahclkr = mcasp_ahclkx;
1 D* E; t& ^8 _9 w( \8 T. ]% D0 Bassign axr1 = axr0; ' |3 e3 i; V# j! [; n! ^5 ^& w
! P% i2 ?" ~; M: V5 |& L9 ^3 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - w0 }1 q' L! ^) @. P1 C
static void McASPI2SConfigure(void)
' T6 R( V% I, L: ~3 l{) X c4 C; |# r1 t6 f W0 x! {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 m& y% a1 G. e! ^: ?' M" J. vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) y* R3 N& ~/ y$ R/ iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 e: S v/ _, M$ j0 `1 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 B/ q. w4 n( i! c0 M$ @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 K" Q! m& G) j) U& D
MCASP_RX_MODE_DMA);
! c; b+ p! p+ D1 k5 i! gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) N9 H2 M1 T1 V) u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 \6 ]4 G! C) M) p; S' I& m7 }) vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 B$ j! v! E' Y. _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- H, ^% }8 p) o7 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 Y" d8 \/ R8 K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 S6 x* {% S9 {+ R/ C& J8 ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' }- Q4 y4 \" X# ?; ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% ^/ H3 X8 O5 z7 a3 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. n/ y, L& V6 h% Y9 o" [ H0x00, 0xFF); /* configure the clock for transmitter */
7 C5 A6 `- y$ v. j" A/ eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! P6 v$ ]1 V; x& iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 g2 E1 @7 ^0 g! @0 v/ l! E! T7 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 c3 t9 j1 q4 F S% o
0x00, 0xFF);
% {8 l1 _. ^3 f* z
0 M4 `' W$ h+ z( y( b/* Enable synchronization of RX and TX sections */
6 X) A, Y; Z) B/ N; iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; ~* p4 ~+ x8 ~9 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 D0 h: w$ D' e' y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
{- I+ A/ U: t0 [+ Q- |$ h/ x5 Q1 z; i** Set the serializers, Currently only one serializer is set as
: Y; O1 n9 @0 Y) o5 h** transmitter and one serializer as receiver.
+ j# Y! k* I- P `2 L$ E( `*/
5 @* Z. T5 y& g Y' pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; D. J7 R$ P0 {8 g* `5 e% W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# B3 @5 Y9 G$ D E
** Configure the McASP pins
( R4 e0 y2 i% l: I( P** Input - Frame Sync, Clock and Serializer Rx1 E1 Q2 P; O7 g, C" b% I3 L0 k5 f) ?
** Output - Serializer Tx is connected to the input of the codec
& N4 Y8 e3 F" F3 q( Z*// u7 c. X8 G) J( H: V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: H& p* l7 F3 R/ f* x% `2 b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* k# A/ f) K6 [ jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 c" w+ g" l* w+ j0 Z1 y| MCASP_PIN_ACLKX
, b& q5 s! V% R& p| MCASP_PIN_AHCLKX' _) ^# V8 W; k* |/ `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ _" N9 h0 O( Q& v i- U; L( H. kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# ?6 a2 i8 f0 r' || MCASP_TX_CLKFAIL 1 X0 q1 a: Z3 ^
| MCASP_TX_SYNCERROR
' m, O' P4 s" I @! J5 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' N- j" {4 A; H' [0 i| MCASP_RX_CLKFAIL% k, u* F/ u( Q1 c0 u' P, E9 D( U
| MCASP_RX_SYNCERROR 1 h, G0 z- M9 v7 I6 x
| MCASP_RX_OVERRUN);
) R' y( q3 K o0 U* M} static void I2SDataTxRxActivate(void)
% E* U7 R" t8 T, ]9 y* r o{- }3 H R) { q2 f: U* C. U
/* Start the clocks */
: e2 o6 } T j3 a0 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 }! |7 B9 B8 _; t. ^
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! o' t, l/ v& u& `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ F& q- q; ]- Z4 N& lEDMA3_TRIG_MODE_EVENT);( e! ^) x* K2 z9 N# Q" H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 ^. C. |. N e4 m4 r$ S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 w# n! p+ V2 N6 C5 f2 c) I3 u3 {* A$ f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" W8 q, {/ c% Y+ a8 Y; z) F$ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ?9 l& D- _% A: C, B% Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, Y1 i7 J6 @- \. ~5 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 A+ R8 a, G) U" J, yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* x2 V" ]4 N* z8 e+ C: N: W d* d} 5 f, d) D8 G7 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. U" O U. t: Y% L
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