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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 l/ h( b5 w$ ~3 U; Q& Vinput mcasp_ahclkx,
6 _, w( A# q/ F0 k* ^input mcasp_aclkx,& y1 P) L9 a. y, b3 g
input axr0,
' b: V: u' w; E' e8 A
& N) J$ S9 k) b6 u6 foutput mcasp_afsr,5 G7 F6 S# n; X5 P0 Z1 k
output mcasp_ahclkr,
% Q+ A4 V8 V% u% N( E4 L6 u% Youtput mcasp_aclkr,* V7 O0 a; ~8 b1 ~& Q
output axr1,% [/ e9 D) w$ x$ ]
assign mcasp_afsr = mcasp_afsx;2 \8 `- _9 |8 R% O# R. m* W
assign mcasp_aclkr = mcasp_aclkx;$ }8 l: X4 ?; y( {5 }
assign mcasp_ahclkr = mcasp_ahclkx;, l. t) p/ R3 r1 B/ ~" L" D! }( t) R
assign axr1 = axr0; 7 y/ B2 V( J8 }4 {
7 A, z/ N W$ X% j& ^# ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! s+ K0 ?2 N# h+ W) G2 wstatic void McASPI2SConfigure(void)3 O0 _ O: k: B0 z4 e" _6 q
{1 e. h# z8 q* g- D( B2 j% ?' _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; O* X& g! p" s0 F0 H1 C2 J3 b6 EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* ?# L, @# t! a4 @& DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) G- ~6 ], a( b- Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% C. T% ~$ v: k3 i, s: i2 Y( |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 b( b# _. x8 IMCASP_RX_MODE_DMA);! V% m. ?) X$ p w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ v7 M' ?. }' [9 W7 Q' t9 ?, F: W4 k" cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ B, i3 U- ]# l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ B! V% ~; \0 }2 wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 |8 O, X) Y5 f/ x3 R+ MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; q& h' Z$ n# q, _ `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& q" ?3 J; { v% `' \/ CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. S8 l8 E& m0 |* jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * a3 l' N' ^" {. k2 _3 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 c0 j* @5 {4 O% Z+ ]) l0x00, 0xFF); /* configure the clock for transmitter */7 ]$ b: e3 d5 K% h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 [3 c3 N& i5 K6 ^7 a r0 ~' E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
k$ a1 Z: f$ b+ I5 u. YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 f" v# E4 h( L, d
0x00, 0xFF);4 `2 D$ T/ d F2 d
6 i9 }3 O6 y6 P8 {, p/* Enable synchronization of RX and TX sections */
7 G) H, S0 [- @$ `2 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ g1 \) `; @0 Z D z$ @- ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( u' v% o' ^! n% ^6 p. S& l* W9 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 |; U+ k! g3 m' v% l1 H/ ~7 w6 h** Set the serializers, Currently only one serializer is set as
. x9 Q2 n. r# f- j! Z+ I% m** transmitter and one serializer as receiver.
2 i2 {# w9 Z2 M) ~0 a! B# B/ q*/, w" ], _: e. ^( {7 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. g" v& h% I- RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 E. Q* Y' d( b- g** Configure the McASP pins & ?) T* S3 ~/ I9 d7 A1 K3 t3 [/ h
** Input - Frame Sync, Clock and Serializer Rx. @8 z7 A, ]. Q) z# Q3 U
** Output - Serializer Tx is connected to the input of the codec
. S) @; W1 ], ^5 z" Y4 C* M+ {*/
5 Z9 y, f! H% f' _' _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ~+ A- z0 L% i. R0 {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 x4 @- I$ y, y' Y" y: J& W: Y- ]8 i/ RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" v5 e' ]7 J% x* n| MCASP_PIN_ACLKX% G& e: T& N9 A% w; a& X* {
| MCASP_PIN_AHCLKX
9 t! W- W* X' O: P: ?) ?) H9 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& f b* f: y: Z# W) X7 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 i( W0 V: \7 I9 y, t2 M
| MCASP_TX_CLKFAIL
! m+ F6 Q4 j1 l| MCASP_TX_SYNCERROR2 A, R0 f4 ~8 q& ], X$ h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! e& c$ u) k1 }' o+ |) a
| MCASP_RX_CLKFAIL
0 c3 v$ ~6 K0 S. J6 J| MCASP_RX_SYNCERROR
* _, r& [' P7 M. Y5 R| MCASP_RX_OVERRUN);, B3 N# _' L$ ^# _9 v2 h! G
} static void I2SDataTxRxActivate(void)
& J& ` P2 S, t1 D! {) h2 G7 ]{
8 {3 d& w7 h% H& D/* Start the clocks */
; c6 K0 G7 u9 g/ h" g% y3 k1 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 W$ o7 d& o* k5 U2 N# D3 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* ^$ V0 ?$ n& REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( o( h, H5 l' nEDMA3_TRIG_MODE_EVENT);
. V1 r. e+ T& M/ q& l0 r& }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, a6 C2 G0 X% ], @! yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; {4 W3 Q$ z) s, i6 t6 n0 Z6 e4 h5 k* W# c9 cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, k" _+ U! u" }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( G, P; n- p9 y. I9 H& v& ^# E7 wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; }* Z; Z9 v: }+ H6 B5 W$ r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! k; z0 v/ ] S. O' P; [, eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
w' b3 }" h- x' _+ j; |} : [: K5 M' x, J4 Z1 q8 {/ ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 N% e: h! L+ K9 ~
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