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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 M- |9 i, d) F
input mcasp_ahclkx,
- W1 v: A: h! u& r U/ l% p, Jinput mcasp_aclkx,
* ?2 o+ q' M* {input axr0,# n0 N8 J& r( Y( O1 J
4 \4 {: G. w/ y% u
output mcasp_afsr,7 j3 U9 `7 `- l1 J. K& n( F
output mcasp_ahclkr,- }7 C2 v' V; T' k8 [* ]9 S+ \ M
output mcasp_aclkr,
$ t n: Q& }) I6 M; goutput axr1,
. v' x5 i4 r$ I5 } assign mcasp_afsr = mcasp_afsx;" {9 I5 v8 e C0 X
assign mcasp_aclkr = mcasp_aclkx;1 a' T0 N3 w( y* d5 w7 y2 ?
assign mcasp_ahclkr = mcasp_ahclkx;7 N/ C1 V( i/ f1 a% B0 R
assign axr1 = axr0; ' D; K- K# `" l( \; x
2 y) A3 V3 K# }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 ^$ a- S# L* S( g1 p) g
static void McASPI2SConfigure(void)
3 d" t1 e% u( a& I* u0 Y1 N, G{) V0 X' K3 |2 G) i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# B% l2 c, l$ V% k# s/ kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) x. K7 a! | P# _ uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- b |/ g6 C$ ~5 k6 E4 VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; J+ D2 M: [( I7 P* c& k% r9 j) t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- b. T2 J" c# t; M/ v, P( lMCASP_RX_MODE_DMA);
/ W% O4 ^: ]! O, t# cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ a5 m; m- c3 A9 _# ]0 y. z2 B! C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 n% L! z2 c8 OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 m y: F3 K) H! y8 t# F2 a8 AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ t/ h& B: I& S4 n- L! L7 e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% N, }9 T! B4 g' u. yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 |0 \7 N, Q6 z- Y0 {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 p' A$ C) R7 g7 P9 ?1 I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 k- I: A7 l6 b7 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 S2 ?# w7 c" D1 _3 k
0x00, 0xFF); /* configure the clock for transmitter */. M2 c( Y0 Z8 t; ?1 a- K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! }/ m6 T$ ~: k& R: O0 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- S* N! f2 D, z2 ?' kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) t) W/ U; m. r0x00, 0xFF);
: y2 p% s! n9 A+ a
9 p. f0 y; l2 o6 Y+ q# l, l/* Enable synchronization of RX and TX sections */ & `- m! |0 p! g4 o# Q% A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 Z" T9 f0 d0 D- WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); e: A. ~6 | ?1 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& F1 e6 v: T6 g8 v/ W5 v' @! w/ j/ g
** Set the serializers, Currently only one serializer is set as$ L5 i: |8 i# ~9 [ K1 m
** transmitter and one serializer as receiver.6 m9 v. c/ c: j: O3 x, h2 a
*/
( q8 N' H5 N+ d. jMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 q* \3 _- T+ B4 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# n& s! R+ n! u' P0 `& K, {0 u
** Configure the McASP pins
) |, g# r& K. D) d# @1 I- W: n** Input - Frame Sync, Clock and Serializer Rx
7 w: S. K3 y. @9 a( y5 D) O: b }% a** Output - Serializer Tx is connected to the input of the codec
$ k$ [0 Y) |2 ?$ p) ]+ d*/4 r0 ^, U: k6 k* [) x
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); L! c7 ]' a) A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: c+ S" D2 d0 {; T6 c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) n) q9 {6 @8 I" W6 ?/ n* e# x| MCASP_PIN_ACLKX- c8 S" f U% W) x' h/ \! Q' G
| MCASP_PIN_AHCLKX
& J- G" t, X9 ?3 P3 K, L: V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 O# _ b5 m0 w) p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . Q% t1 k O2 L {1 d
| MCASP_TX_CLKFAIL
. i" e; k0 y6 ] v| MCASP_TX_SYNCERROR* H8 S+ X g- r3 b9 C' u- a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; \5 x% Y& R- ?$ e| MCASP_RX_CLKFAIL
1 j5 B# x5 {! i \4 n| MCASP_RX_SYNCERROR
" \4 y6 \/ G8 j0 D# S u0 z| MCASP_RX_OVERRUN);
4 w$ X; g8 z) ?3 f0 g& O; `. o% Y} static void I2SDataTxRxActivate(void)
5 [: }/ j, E6 a$ [7 N0 U{7 L* X) H$ Q- D6 o J0 o
/* Start the clocks */" }; s# \# Q0 |1 y, q5 f3 }) L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( z) Q4 |0 ]6 }7 E- WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* r, v, z" }+ w* Q: L# wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 j) k4 d' K! S' s
EDMA3_TRIG_MODE_EVENT);
# \1 D, V* R0 o+ M# EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ L/ C e0 v- k! [9 y! A+ EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- a% R% M0 u0 n' U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ n- B: U! q+ q& u3 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 G9 _- B \% [; a/ b, Q5 u% X6 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( @: m- `9 y( {+ x4 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);) J3 G/ A; d9 H0 S0 S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. n9 [! U3 U3 @% e1 ]
}
& R: |' @* Q$ }+ B* t, U7 H l2 c2 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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