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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- d3 ]0 T* Z8 J( q1 a, ]! w( z5 d Qinput mcasp_ahclkx,
) \- n. \7 C; Y2 G$ ^$ Xinput mcasp_aclkx,
# ^2 S( K+ o' }, ?; ainput axr0,6 @7 d7 [# G- F2 Y( A7 z( `4 x
- {- s/ Z3 r4 t+ [; ~+ j
output mcasp_afsr,
7 \1 B* m# v7 @4 b" _output mcasp_ahclkr,% [3 R1 G3 N" p% p5 i/ X W2 O+ e
output mcasp_aclkr,: \/ P- p9 F! \. `7 l
output axr1,
- |& R% t* q$ _2 l2 h9 |% v assign mcasp_afsr = mcasp_afsx;
3 [6 M# D+ O! y1 q& Passign mcasp_aclkr = mcasp_aclkx;
. \- z1 ~' }% q: m5 I8 bassign mcasp_ahclkr = mcasp_ahclkx;
+ {; V$ }/ [. m( N. V6 tassign axr1 = axr0; & O! j, m4 Y$ w) O( J
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' l1 C, ?% y+ ?6 @+ I+ i1 q
static void McASPI2SConfigure(void)
8 q- M$ U0 L1 C+ L1 ?+ M, c7 {6 ]9 _3 O{
: c* @9 x! l, \# J4 ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 a" G! n7 o, ^) ?. d( q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% l! o+ n* @' t8 s1 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 H" m7 H7 G* Y; M" }2 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! B$ {* D/ E- x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 m9 R) Q U" i% RMCASP_RX_MODE_DMA);# H* y: f# }% w7 C x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 O2 @0 t3 i) V% @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ n, g0 s. g: W2 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 s: l' q9 c1 H K" ]) l8 V; l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 d# \, ?; p, l& |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; G1 M# d9 |8 H/ R7 s0 o! d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ U) X, H) |/ B) L$ b; S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: e/ w) I: _( W5 L3 f. U2 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: D% i- a2 v8 N% I5 [9 dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 @( }# X! w. {* Q4 T0x00, 0xFF); /* configure the clock for transmitter */
0 G0 N k8 J8 V- l4 l' LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- H" ^5 G$ z. G/ R- x+ }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; g" D) j5 ~2 k# AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 S7 ~ c7 ]5 u; L0x00, 0xFF);
- Z- y1 J V- f4 O( Q2 O; q/ t( m% L4 [2 n8 R* f
/* Enable synchronization of RX and TX sections */ 3 j# A+ @7 A8 x, x5 f6 y2 j( F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 e% C5 D, ?! H( r$ ?4 G) n$ J3 R0 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 [3 Y% c6 @# `. l7 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ m0 h' n* _. [- f
** Set the serializers, Currently only one serializer is set as3 O7 B% _4 f% \0 W
** transmitter and one serializer as receiver.* L4 v5 s* o+ R& J5 }* t1 v! B
*/7 [/ ]" K& j- l! J8 K' \3 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* K5 Z. T! M: X0 V# M. T9 [; U/ C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 o& G' C$ Z$ F9 _; j* B** Configure the McASP pins
8 C4 w! N( @0 _+ I" G+ `# g8 }* b& W$ ^2 \** Input - Frame Sync, Clock and Serializer Rx
! u0 I+ ]( h8 g1 Y6 p8 Z) f** Output - Serializer Tx is connected to the input of the codec % W v9 n9 F! u% M
*/% H3 k5 k" I( \0 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% o, T/ b: Y& YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 o5 q/ I; d6 {! f. L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 h0 D; o; F- Y4 g- ]3 S2 i2 y! B; [| MCASP_PIN_ACLKX7 U' q& d1 d/ f$ `" F( N
| MCASP_PIN_AHCLKX
! S. t& Q0 j+ y2 {' c& K; F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" l) B3 I9 l3 b5 h0 w, u" JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; q0 u$ R, I \6 |* c4 k9 O- o| MCASP_TX_CLKFAIL 2 M5 Z( j8 Z" m2 K. j: `
| MCASP_TX_SYNCERROR
; [4 V* T1 [- t6 A& V: }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 l$ e& G# y, _) }7 F| MCASP_RX_CLKFAIL
5 l: ?+ A# U9 U: l+ U| MCASP_RX_SYNCERROR
6 ~! H; X8 a# o| MCASP_RX_OVERRUN);
7 u' o' d" c4 Y1 M} static void I2SDataTxRxActivate(void); u8 t. ?( S6 F+ ?
{
( Z5 U7 a5 U) y/* Start the clocks */
6 p$ |0 ^; b, o6 {7 [8 o5 V+ @9 S |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( r% K1 }5 c+ x* b3 G7 \. A6 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) A% T3 L s- a8 n; C" M. C Q. B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' |2 N1 @3 V% P, w- B8 f
EDMA3_TRIG_MODE_EVENT);8 {1 S/ O7 }- A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( ~- O6 Q$ j& cEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ `: \! B& T7 v# T) tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# Y2 E% j2 Z6 B, o, GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 }5 Y1 _: V$ G6 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' x9 d; J9 a( p) U5 z1 T \% V" C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; |) k! o F+ v% H5 d+ P8 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 B/ S5 V+ R! V8 q% G& S, n E} + B7 n2 s! |9 E7 n- W7 j; E0 Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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