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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 ^2 W5 e1 Q. K B4 \% x' Q# g
input mcasp_ahclkx,
$ `2 J- d4 r& k: B F: ninput mcasp_aclkx,
$ }* }6 C' O* l2 y; [4 yinput axr0,
2 F' |+ o; i m5 L% Q3 ?. K
" V- `$ u' e- d5 g/ s3 Q- g' Foutput mcasp_afsr,
$ w" c) ^+ E8 W8 B# G% Goutput mcasp_ahclkr,
% ^' G$ {2 Y4 `' f+ V8 `output mcasp_aclkr,+ }7 F5 @! I1 @& b/ v- l* U6 n
output axr1,
( P+ i% c& m# h assign mcasp_afsr = mcasp_afsx;( r% l% Q/ M& Z
assign mcasp_aclkr = mcasp_aclkx;
0 `$ E( V$ S: v/ X. b5 T# Vassign mcasp_ahclkr = mcasp_ahclkx;" j. t& B% x. d9 L
assign axr1 = axr0;
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2 w$ F g9 M! X7 b) n! F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ G2 C. ~( u8 f2 M( I* r: Tstatic void McASPI2SConfigure(void) A* L4 n8 C" i9 s5 _% y; Y6 y
{2 h( {& V+ V% j5 C: x* e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 G+ M2 ^5 q" f, v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ v& u9 r- ^+ }8 ]) \; oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% s. t5 o4 Q6 U8 T5 s8 z7 t+ G% [. \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 K, f- T- J. X& L) F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 R3 m& B3 } U
MCASP_RX_MODE_DMA);8 r9 R4 V. K$ t( M- Q$ B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 @/ P, H' Y7 S3 x0 t3 ~/ H) a1 b# vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, B1 y; @4 D8 f+ h9 ?$ `$ [1 YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / b0 h. X- e% ` U. _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 V6 Y2 x* D* m+ n5 f+ k; z5 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 @4 X+ A$ n+ M3 Z; E5 r7 c% r. @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" ?. q& V h z/ D: ?8 A( C5 C" G" Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
e* g8 K/ q. t0 J$ L8 s I! @0 n: vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , l0 A2 b5 @4 L* I: `2 l5 r" [+ u' J8 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; I! u3 L& t+ n9 V0 m9 r9 ~0x00, 0xFF); /* configure the clock for transmitter */
; s6 z6 d7 S# l! b( yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, n- T/ ~2 g2 N7 Q3 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; t( a1 Q& d+ A0 j8 [$ U; QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ O5 u4 K4 W5 E9 i/ o* z0x00, 0xFF);
$ e3 H- w) ?1 ^% n9 ]
0 x; `% y: T0 }( X4 r# L5 m1 u. A/* Enable synchronization of RX and TX sections */
2 Z& B' z, s, \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( |6 g( {4 J7 F5 y g, ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, }: K) k6 Y9 `' }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, c5 u% j' o% s7 b
** Set the serializers, Currently only one serializer is set as
, U: `* W* ~% ]7 W0 Q0 ~3 i2 X** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: r: W* S6 @4 BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' C3 p3 w+ I: }4 [
** Configure the McASP pins ! a5 l* J7 m, M) D# |! _& f
** Input - Frame Sync, Clock and Serializer Rx
$ o& m9 `1 I& F8 Z: S** Output - Serializer Tx is connected to the input of the codec
, ^6 n/ z) u( I' \9 c*/! V9 ?: z! C2 W% Z! H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 i" I/ U- B4 p) ^/ c% W' `! H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 ]1 O% O" G2 D1 I5 q- L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 Z1 B& h( y. |9 V2 o3 F( y
| MCASP_PIN_ACLKX; x: f; d0 F3 G8 A6 T2 ~! n ~
| MCASP_PIN_AHCLKX" c- i' c; `% @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ k1 o% ?- l1 g# \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# V4 t+ C5 r- E: U# [" u| MCASP_TX_CLKFAIL
/ Z) n! S9 o9 E- c| MCASP_TX_SYNCERROR
# G: T7 d @1 f8 f5 f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & w" c/ b: a) {% e7 F
| MCASP_RX_CLKFAIL( |7 ?5 ]% u2 C- I. }
| MCASP_RX_SYNCERROR , s" _& n4 ~1 p9 c. z" | M# I
| MCASP_RX_OVERRUN);- {( D! V& B8 v7 w& L( [5 V0 _
} static void I2SDataTxRxActivate(void)9 z$ p+ ^/ Q3 T' d( u
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/* Start the clocks */
# u( D/ ^% n( C! _; A1 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 E. K/ W ~% e5 Q: G' @5 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 u9 y9 w5 b7 r* i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 L) d! q% @: C! M; J; WEDMA3_TRIG_MODE_EVENT);) |2 j! h- w8 Q9 G" [0 `9 K) ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 m' |& Y- M9 V1 U; |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% p& O6 O- |5 ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 _" i6 r) ` ]' Z' \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 y' Q7 r3 F, k" f# rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, \' u$ ~0 s2 s+ a0 L4 L$ i# O# h1 s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( w( W0 x: ?/ ?% _& E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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