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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ t( W$ J2 k$ N. f" v3 ~) Minput mcasp_ahclkx,
# [+ r9 j2 }; C$ g5 [1 rinput mcasp_aclkx,
7 Y% M0 T' b( C) A1 ^input axr0,) u/ D2 `5 ~/ w7 K1 K
0 w, Y* l) U# z% G2 K% Q
output mcasp_afsr,# c" \1 T( ~7 S
output mcasp_ahclkr,6 ^# T4 @. a( }4 @" |
output mcasp_aclkr,3 B$ h0 I6 u8 L6 j9 O
output axr1,8 ~# F' i9 E9 k+ E
assign mcasp_afsr = mcasp_afsx;- n7 ^2 s, T5 n
assign mcasp_aclkr = mcasp_aclkx;
8 X/ z: B% j! R/ sassign mcasp_ahclkr = mcasp_ahclkx;
) g, U3 [( @* A, Nassign axr1 = axr0; ) T1 w3 O" q( W# s0 y+ \
0 s; f6 [' o7 Y9 j" f! u# h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) ~6 ^1 i- ^: R3 R+ w, c" [
static void McASPI2SConfigure(void)
2 p8 ?- g# N, E{# c c+ r5 F, e; L( F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# ~ R$ `" ]9 r0 }# ]$ w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% l1 ?+ H6 I$ I# W4 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
}- D0 q; f+ F# N1 X: m6 G% XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' u) h/ ?4 D3 Y6 i7 P9 s+ ` SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 x+ h$ d* ?. w0 xMCASP_RX_MODE_DMA);# W0 i8 a3 O' S# c" Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) w& g* I G% `+ n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; \/ g3 Z0 e) J, ~; d" rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 h* P/ d2 X% T/ iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' i9 r0 z- H; J- n; `6 l& LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% @, E ~8 |% g2 z/ p IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: q: N% X5 o2 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* g# ^- {! S4 c7 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! K( D' x. B' X* [$ _. X# m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: g; T. o* E0 m7 m3 D+ l2 _
0x00, 0xFF); /* configure the clock for transmitter */, |7 g8 s4 c9 f; V& Z. B5 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 U! o1 }$ B3 o: F7 ]) ~2 l% B9 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 ]) k2 U, C1 B- w7 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 S" K4 A' r+ |( w0x00, 0xFF);
$ Q0 n7 U9 w8 Y2 N) F' H* g
. l* z9 b# m9 w2 a2 }7 k/* Enable synchronization of RX and TX sections */
& x' j$ U1 l. Q& m& wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 \& z; Z0 X+ ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) W7 k/ [& W" a8 ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 r5 `7 ?+ S7 X2 F
** Set the serializers, Currently only one serializer is set as
+ T! M2 z- g& O' v8 C** transmitter and one serializer as receiver.+ N I3 Q0 U8 C3 b4 V
*/
8 F8 a" Z4 e5 o9 ?" {$ F* OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: V% J( V( \* F6 vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 F8 f) `9 {% C6 ?) j& h** Configure the McASP pins
& S7 V: _+ x1 a) q% @. f** Input - Frame Sync, Clock and Serializer Rx# I- g+ r c5 k2 P, ?6 g2 D
** Output - Serializer Tx is connected to the input of the codec
6 f1 A4 c3 X0 C, m$ E& t*/1 [3 p1 D! h" E7 w3 F! G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; a4 f# ^4 S mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. U Z; m# J6 \# |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
N( B! N: j) T# j7 u1 W| MCASP_PIN_ACLKX
@7 @' u$ ^, O# Z3 F( G| MCASP_PIN_AHCLKX
% W* S% p+ t0 F. J- A; W( K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 _9 w4 L3 L$ b" _+ DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 S+ q( s7 t, |$ ]# K3 b. B
| MCASP_TX_CLKFAIL . h3 O z3 h; F( e9 E2 B" x. `
| MCASP_TX_SYNCERROR% y' y u, `( D* M$ G) h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" u! B) Y5 X+ t/ a& I1 g- J| MCASP_RX_CLKFAIL
/ j6 z6 V8 w4 Z: {4 m| MCASP_RX_SYNCERROR 2 p3 Y7 w3 ^/ h/ [: u
| MCASP_RX_OVERRUN);7 v. p4 @' z$ v+ x& t, v
} static void I2SDataTxRxActivate(void)1 ^" { ^; v, {& t" S
{+ J5 @: k" ]* q8 t4 q& ~- Z1 _
/* Start the clocks */
. S; ^2 ?& ^3 c6 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( `, k' G9 ]5 D( ~, |5 N vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& p4 d$ Q- n- g$ |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. b, M$ d$ ?4 O6 c7 I
EDMA3_TRIG_MODE_EVENT);
" c% J9 ~* G% ?# ~7 r- i/ w/ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , I2 y2 K( O1 u2 [# n: A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 _7 X: V! H% ?: X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( J( y( k) |4 `$ A; i: [3 A5 TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: F7 D* |* V6 J7 N; U2 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# Z( B0 o! _- M' X/ W1 h5 x- e5 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 o8 r- x; Q* ?$ _- ^( R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: x2 q7 {+ _* D7 k7 Q} D7 o/ P+ a1 v1 T4 u0 `' l) n9 H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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