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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# D! a, ~9 h3 s8 r
input mcasp_ahclkx,# r. j" J m$ K
input mcasp_aclkx,
8 @8 F6 c r: z* R0 C6 X) Vinput axr0,
3 p; u* J3 r! y% D8 F) q
0 S, a! O; t# N% doutput mcasp_afsr,
% `5 i2 S3 P! P# [0 |4 eoutput mcasp_ahclkr,
! T1 W( b! c2 _5 \1 ^+ Y' noutput mcasp_aclkr,
0 P9 r: S/ \: ^, c, koutput axr1,
1 J9 l" \; d" j+ z3 Y2 O assign mcasp_afsr = mcasp_afsx;, b1 z( G/ ^3 P1 q8 z
assign mcasp_aclkr = mcasp_aclkx;
% { }/ S& n5 ^9 l0 qassign mcasp_ahclkr = mcasp_ahclkx;
4 G! Y9 D! v" M& a' ?0 |assign axr1 = axr0;
- y" R, a1 T& r- B3 u
# n7 m$ n& N) Z+ T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 q0 V% r0 n! \$ x7 H
static void McASPI2SConfigure(void)
7 b- `/ K: C. X9 A% @5 t! c8 n2 D{
7 d" z J! j9 C3 o ^6 y1 lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ Z% x) W7 L, nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* R: x' ^7 o; eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, q; B0 J( ?5 |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' \& F4 [7 W: M7 c0 B/ u2 K- Q0 V4 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Y/ o+ _) q* b& b# rMCASP_RX_MODE_DMA);1 A1 i6 ?/ m8 {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 C7 |% G- H+ z: CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// }( D0 h+ x( F, `1 O7 x* O6 K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' Q2 e5 H( ^- C- U2 m2 j, Y; g: T/ i3 u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) W" k' n% I+ b6 C+ A) t2 p2 `* X) ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 {* a5 N+ m* s9 V4 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" J7 v1 [5 V3 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 J& r7 B* r" T' [7 C) a1 E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ T* Q" X2 H' g: G: n/ h. ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ h* T3 R: T6 P, w I2 x- \9 _
0x00, 0xFF); /* configure the clock for transmitter */
" ] O( q. H" ]8 NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 v; {' Q/ y) h6 x" n6 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* g% q1 F& ?% u) PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 S( T) D3 l$ ^
0x00, 0xFF);
; `% V" C, @; O& o5 U! L5 n- N7 I8 k# u$ [
/* Enable synchronization of RX and TX sections */
' P! i* N% [' vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. V- d. V: c$ B; x1 T4 h6 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 C, N( B) M, C1 {% i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ v, R6 r/ c& u' A. U" K
** Set the serializers, Currently only one serializer is set as
8 H! Y% ^ m2 t2 l** transmitter and one serializer as receiver., U/ f3 G# q! ~& o* q
*/. y! y5 ]$ E% S0 O b5 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 Y; D8 o1 F5 q* C6 J, I9 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) H8 f& u: i6 E4 ]** Configure the McASP pins ! m( p1 ?$ k5 E" U4 t* _
** Input - Frame Sync, Clock and Serializer Rx+ ~5 l- t0 A# Y& G( k" Q
** Output - Serializer Tx is connected to the input of the codec ; L n" } [" N
*/
5 I8 F1 ^# D+ `# L( CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ W/ r% O! e. }9 r. t2 P3 ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& ~- H* h7 a8 a, YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# l' k' G; w. G| MCASP_PIN_ACLKX* F8 w" Y" `1 {+ t% j4 K+ ~* N) E
| MCASP_PIN_AHCLKX
' k: g+ O' t) k; o& t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: S' o7 T( B, L1 y- } {+ `! }5 p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 H& C1 n# y4 Y' |* Q9 W| MCASP_TX_CLKFAIL 9 b2 D/ P1 h P& P/ q+ a
| MCASP_TX_SYNCERROR
# |9 x% U( Q7 _6 h6 w! C8 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 e- N% m( g& v9 g: r
| MCASP_RX_CLKFAIL* V, W y+ N K/ H0 T9 ~
| MCASP_RX_SYNCERROR : X. |9 `' ^* V) H. Z! O- l
| MCASP_RX_OVERRUN);
0 P# G3 X C( g" j6 Y1 ~" B0 ]} static void I2SDataTxRxActivate(void)$ V( k6 K7 V( g5 z. }& [
{
7 ^. e5 E; v: O# f4 G- y( h/* Start the clocks */
- P' F! {3 g% t( ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) O+ a& j! F3 AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ g+ Z+ S: Q8 T2 H1 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 y0 f4 G% N) w& `" VEDMA3_TRIG_MODE_EVENT);1 r% V6 F9 r' ^) _4 _6 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 U' j: G& r& p7 U( iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 n" t+ @/ B) I/ N8 sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 ^5 Z2 r, J! ?7 |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. \! g2 f4 a; m# B+ x j, B( y# A, @ t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 I$ M4 K6 ^/ r4 Y& A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! T* E* u% S2 q" N" p' `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ e- J$ m% m1 u @/ Y- j} 8 ^' D5 @8 W- C& p8 ~3 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 w% \, w$ t8 C9 p9 o2 w' G
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