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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 M+ k- r* R$ L( x* [) o( e! s# B
input mcasp_ahclkx,) b' @6 I1 C2 ]1 u/ v( z
input mcasp_aclkx,
) S) }/ @( U, `& n6 w' |4 \input axr0,
& ?8 Y2 r/ D# |6 Z P1 y8 Q; ^# G. R& Z- u1 X. q
output mcasp_afsr,7 r! C. D% q' Y) F( Z; p0 M, p
output mcasp_ahclkr,
) L+ \( e& X$ ?! O9 n3 J! \output mcasp_aclkr,/ p/ S) [5 U7 Y9 N
output axr1,
% |/ w) J# I. K& i* r! X- Z( @ assign mcasp_afsr = mcasp_afsx;
+ s3 j% e; H, c; W2 [assign mcasp_aclkr = mcasp_aclkx;( z+ N# j6 L: \( T6 x2 ]' V8 n; q* s8 ]
assign mcasp_ahclkr = mcasp_ahclkx;/ D( h- H2 F. P% x# M/ E' K
assign axr1 = axr0; , b3 f) M: Q6 J) n/ }. X
: N5 k+ E3 _7 c" f, L- X9 _% o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 r/ v1 p; D" p; D! X0 T0 bstatic void McASPI2SConfigure(void)' k4 S! ~6 t7 q7 {
{4 A. m/ Q8 A8 B3 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 f# y/ j$ j8 B3 T8 R+ b2 A- u$ vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: U6 M9 x4 j2 m/ ]( ^0 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ a I: v6 D3 oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# _% e" \7 u. G# q! RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ^# z8 |( t( l% ?MCASP_RX_MODE_DMA);" u. T( w# \: n1 X- I1 e3 c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ \4 F2 {" M& Q! u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 L# i+ e* X, e M% D' Q7 u5 |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / T1 c9 I/ l! e# x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% A) q- T6 s' t3 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) [" z5 w. C& u7 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* `4 x" D' a5 K0 U& sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 y1 u) l- i" D% w4 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . h" G- p: ]6 V5 V7 y9 Z+ C4 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- X4 `7 g, D3 k/ ?5 d
0x00, 0xFF); /* configure the clock for transmitter */
0 B* x- `% C* B8 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 S: Q5 G4 J% zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 T2 h) c* C0 G: pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% d' L/ t8 Q6 r \0x00, 0xFF);
8 b9 j( k* V# u3 O
5 e3 _% ]0 k* e8 n0 e# ?# ?6 [/* Enable synchronization of RX and TX sections */
4 L( k0 u+ \0 _0 _( U3 V: L# hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: @: Y6 p" t: n4 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- w) ?6 d0 A5 b* h; pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 ?* ]& i) D# |) G u# s8 y
** Set the serializers, Currently only one serializer is set as5 |# c) G# Z3 O! R
** transmitter and one serializer as receiver.
; o# a* u) b9 o8 @% E; q*/3 y$ Q9 a# j$ s! j( y4 T0 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% B& g) Q- W' ~ r7 Q e" L% Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
e& _& V0 b' s% F/ |** Configure the McASP pins
" e" t0 o, |: M1 G& K8 T h" N8 B** Input - Frame Sync, Clock and Serializer Rx# r* \% _- ^( E1 k e
** Output - Serializer Tx is connected to the input of the codec 5 b& C+ p( O+ X( \; ~& c) I9 v- O' G
*/. |' h$ O1 Z9 _, U) Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 e0 b9 _3 @. v7 E" P4 o l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ ?* A. @& v, ?& q# r9 }7 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: ]3 f- x9 j. o
| MCASP_PIN_ACLKX
1 J& K5 N5 l8 }% o s| MCASP_PIN_AHCLKX
+ l8 l& e7 H7 b o" q7 @5 ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */+ U# L" Y7 R2 d" |2 ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ ], z; R$ x4 }) z* K G, u| MCASP_TX_CLKFAIL ' w" x' `" ^( k9 H& l1 p' ^
| MCASP_TX_SYNCERROR6 o2 A- l* x& w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # U" Q# Z+ a$ [/ K2 [
| MCASP_RX_CLKFAIL
+ ^7 d2 o. t& U3 s5 Z| MCASP_RX_SYNCERROR & z& F5 i' A8 J) D
| MCASP_RX_OVERRUN);
; p5 T& b' R/ k4 \4 o! g} static void I2SDataTxRxActivate(void)/ c* k. ` f1 V" p
{- J: ^ ]9 D6 j& b6 N
/* Start the clocks */3 k/ i# q: H/ [$ G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 @7 v" Z- m9 B% y* S9 S: x2 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: M6 w( {# r E( p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- y. w8 ]# Y6 S+ `8 mEDMA3_TRIG_MODE_EVENT);
! C9 B9 g8 L+ b7 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ _, g# J r2 z4 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ a" ~. h: r+ L3 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ a" ^) S, l/ G8 q0 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 Z6 E+ `* m" V, \: i- [; V9 qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 x ^) O1 G8 u, w; u- jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 @7 _/ |- j8 ~) q& LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ M" P T3 ~9 L; ^} ; a% N" r: m" Q$ G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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