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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) _8 ~$ K7 U3 p6 c0 E2 o4 }
input mcasp_ahclkx,
% n' I; N+ A( S7 `$ u: h7 k, g' ]input mcasp_aclkx,1 e& d+ y; n' e7 o' z. w( W4 W
input axr0,; z# f$ _, S* q- m# n& A. s2 X
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output mcasp_afsr,
$ u9 |+ ]' N% [/ U. ^. K+ R0 eoutput mcasp_ahclkr,# D$ r2 O% l; W4 t$ t' G5 ?
output mcasp_aclkr,+ J0 L/ G+ w/ R* z
output axr1,; M8 G- K0 A3 f i8 X- u \
assign mcasp_afsr = mcasp_afsx;
8 B @, j- @: ]6 a, Y) qassign mcasp_aclkr = mcasp_aclkx;
* t1 @3 ]; A$ A1 Z \ `; N/ |assign mcasp_ahclkr = mcasp_ahclkx;" i" ^0 M H. X. e- f3 }
assign axr1 = axr0; 8 K3 |" j# G V, W5 G) p2 Q# T
6 | \9 I3 M% E0 `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! Y+ C& l. a W( S
static void McASPI2SConfigure(void)0 [" ~4 b! P0 c6 M! c- \
{" o; b, R6 V2 Y% e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# {" l( _: f1 V" s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. F( y5 S( P$ [( c/ C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. G# H' a- J: Y; k3 J$ I, i7 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 F2 g; e2 Q$ Q, O( j' K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, O; B, N! l# o9 x2 W, C, v
MCASP_RX_MODE_DMA);
P% R J# d: Y! _ rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' r( B3 e, @% L- o9 `# h) `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& p) G" N+ G8 E b# |& K5 `7 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; W& k* h: e$ v- H: O! m' O V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ U0 F$ G/ j; B% J9 m3 z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( `' D9 F l% C9 W) G& [! F* O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) z$ L+ z" v4 |; q( w) X% L& ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: P+ m7 b5 T ^8 d* zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * |: i( [/ ?# E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 ^( W9 L, D5 r/ l! J# L0x00, 0xFF); /* configure the clock for transmitter */
+ a# D2 D9 Y7 e' DMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ O4 ^0 j# u$ U- VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 U( S8 t. t9 d: R% ~4 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% Y5 n; C; O9 e6 _% D8 q& ] {& t# j: ]
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */ Z6 @2 H0 e% A7 K8 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ q! S8 b! t+ m4 W6 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ P/ l2 d7 j) T! q0 x: U+ Q8 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 N% V4 `6 E+ C- r: Q; g* h
** Set the serializers, Currently only one serializer is set as$ z) g% g: H/ F2 e. W8 G
** transmitter and one serializer as receiver.6 ?, k# U9 V+ y- T9 \+ i0 e R
*/# }( O3 P) |$ { j+ y1 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 ^$ g6 Y/ t$ UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) c; C2 t3 M; N+ I9 {; m
** Configure the McASP pins
+ U4 u/ o4 X0 f# h1 F; I1 M** Input - Frame Sync, Clock and Serializer Rx" u& x! ~3 G( N0 \
** Output - Serializer Tx is connected to the input of the codec 3 \6 `0 W& T, G7 y, P8 r
*/
6 s" Y l7 K; ^8 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
J. o* \5 v( [/ qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ N/ j$ r1 }' X( i& ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 b; X9 v$ t( u. |8 i* F! c| MCASP_PIN_ACLKX
0 ]2 S* ^1 P- O, B' T, ~" |1 P| MCASP_PIN_AHCLKX
4 @- q$ e% c- p5 F9 R# s( `+ P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ B. V- V* }( m- WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 b% B7 P9 B4 f; d/ V$ r| MCASP_TX_CLKFAIL * @0 Z8 W1 } U% k# a! S
| MCASP_TX_SYNCERROR o% D! O/ _) o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 `# Q' h$ y2 h# x| MCASP_RX_CLKFAIL
1 P2 `! X- q( c& {$ u| MCASP_RX_SYNCERROR 7 E- ~) M* @ c5 w
| MCASP_RX_OVERRUN);5 U" W3 C; p2 x0 r" [
} static void I2SDataTxRxActivate(void)
5 n. s. D! y' U2 t2 b8 u |9 o{
7 P& g& T1 b0 Z: P, D. n$ K/* Start the clocks */
$ h; m2 G m4 ~8 v w. Z" PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 m& f' u8 O# ]1 _ M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' P; \ a( U6 A4 Z' x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 g4 b9 I" X9 ^" V5 YEDMA3_TRIG_MODE_EVENT);
' `+ I# ?# r8 s/ r- B6 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ L; S5 N v/ ^$ }3 u' F% |1 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 m' B, r8 d7 `( XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 J& W2 ?4 U0 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( e, B( z4 ^, A+ `. twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 m& V" G8 Y: ^- }" M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 L1 z) [. z% W
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, o" x) R! T% o* n* d0 g9 A
} " R) [1 W7 N' K1 K$ y- \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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