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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, h7 D4 a, P- n0 I- u
input mcasp_ahclkx,
. K! \) ^; m1 N! _# g {input mcasp_aclkx,
0 F8 Y" |- c1 D! N- E- Winput axr0,
* q6 e! j9 Y' u! Z1 s& ]. h8 s6 y! {5 [% p6 I( d/ g
output mcasp_afsr,1 W( l) |/ e+ i3 k. j' m' h
output mcasp_ahclkr,
# V* C* [- R4 p( m" C3 l* Ooutput mcasp_aclkr,
/ H/ G3 ?$ I& j: m% t% m* ^0 G2 ]. Boutput axr1,- y! L0 [/ y4 ]! A( K7 b
assign mcasp_afsr = mcasp_afsx;
) T0 G0 ]% r* v( A7 E0 p. S+ L! Tassign mcasp_aclkr = mcasp_aclkx;
% \: d, M6 G$ w/ R4 B0 eassign mcasp_ahclkr = mcasp_ahclkx;
8 X R/ {. I8 X* W2 T |" V. r- Passign axr1 = axr0; ) j$ u4 O( x: \' j* J# R$ x; u+ M6 h
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 S1 m7 Q# S, u! a. K, z7 E" ^( ostatic void McASPI2SConfigure(void)
8 H- D& ]$ F8 ?" u$ M% O% L) _{" T9 e; o% m6 f& B4 t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# M+ N c" e" {+ u/ }/ D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: H' p! d7 _3 Q4 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ F. | s" L; D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! ~" C9 I/ }9 d0 O* zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, H% j" d; I0 q! J# n
MCASP_RX_MODE_DMA);
* R# _! t0 p& H! z5 g; x; n* WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! I6 f3 k& q: M% L2 S1 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, m; T2 Q, V* `% n' j: k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 G$ o5 O1 M+ V4 [7 |( @( B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 `7 k9 T5 C1 u- Q6 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' \; i! K5 O0 t/ Z: b1 T& a2 [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- S4 {% c+ M% m* ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# z% \' s% N4 D d! x/ X4 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! Q" E# o# q. C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( F4 |- H, a% R' w7 y
0x00, 0xFF); /* configure the clock for transmitter */& j; X! M3 @# _9 J5 s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 Y T4 p/ O2 M I O$ s# TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' f! }6 ]) K3 {7 P# hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 g5 q$ [. c+ f, @8 v7 j
0x00, 0xFF);7 H3 y5 X; [* g( `8 _! [
3 \3 P3 f' u6 Y! Z( P
/* Enable synchronization of RX and TX sections */
" E9 c# |3 u7 O& V: `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 o: A1 E9 ~; t$ g6 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 }/ F4 }# G3 \/ `3 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) {/ S% f! M$ L X7 x** Set the serializers, Currently only one serializer is set as1 s5 T6 ~1 d0 N1 k4 y, t
** transmitter and one serializer as receiver.
, Y! ~4 K& z# g( H% B) {*/
1 H0 G P7 d5 ^/ cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. B5 O" `% F9 |+ z8 F3 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** f& q: i6 h' D, e* k W b7 T
** Configure the McASP pins
7 h8 ^ i+ [: }: A** Input - Frame Sync, Clock and Serializer Rx
, K6 q n/ P9 D( x+ F5 k& U** Output - Serializer Tx is connected to the input of the codec 4 v* K6 E* w' n E. U
*/* V |# c' V2 v5 O5 S- ~2 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% K+ ~3 ` g9 e3 x7 o W0 g: X- FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 q4 I" D. J }3 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 T5 u$ B) w2 W/ c4 r$ `6 R: {4 D| MCASP_PIN_ACLKX
9 N6 V2 M( K7 D" \1 h| MCASP_PIN_AHCLKX
' P5 A- c+ k; ^& O: D9 U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& l+ `& h4 _! Y! N9 y4 K: W0 qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' ?7 f2 ~# L5 c5 U% F9 I, }
| MCASP_TX_CLKFAIL
3 x5 T! K j1 b6 c| MCASP_TX_SYNCERROR
+ M5 W& M5 u" A* u7 i1 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 e u1 I% u+ O4 e, ~1 t) S| MCASP_RX_CLKFAIL
( ^* L" B& ^2 [' _ a- @| MCASP_RX_SYNCERROR O- A( q: y! r: M( C4 n
| MCASP_RX_OVERRUN);
$ i. x' w! m8 N2 v* ^} static void I2SDataTxRxActivate(void)7 c* g9 j% G; z' Z0 G3 \
{
4 U% z0 w9 |# h; o& O& p3 H/* Start the clocks */
$ y) d5 v8 T& e( ? a3 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ w# M9 J# D9 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 O; F' C6 W* g# }4 C$ ^$ aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: W2 r( o8 `* H3 K1 w8 DEDMA3_TRIG_MODE_EVENT);1 u2 K, I' Q+ Q0 |6 h9 `- n2 v& |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 N8 w: F% i0 z5 MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 p* } R2 Q8 y* O& Z9 d6 T }$ KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( m+ I: a8 @# {6 }' r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 ~7 Q( j" c; K& z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ C9 X0 B. G2 {7 z8 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 o3 Q2 Y4 c- H; f# BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- Y$ \5 W* ?& N6 S0 `
} # a& X- d* g+ k+ B% ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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