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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 g! b7 D6 h# v7 v
input mcasp_ahclkx,
/ e2 @3 a) G. x/ [% G6 _8 {input mcasp_aclkx,
5 W7 {% _2 P, j. s linput axr0,
2 t! O: m# M# H* q3 E
6 j& |4 M& ~+ e8 p* Routput mcasp_afsr,0 x; h) s$ ~5 l
output mcasp_ahclkr,
' ]9 r* n! ?! q- T( ^( Toutput mcasp_aclkr,
+ q2 }$ D. b9 C% Boutput axr1,
: |' h. ~) D/ C6 @! v5 k4 P6 Z assign mcasp_afsr = mcasp_afsx;6 A. N( b. O G$ B& p* C
assign mcasp_aclkr = mcasp_aclkx;
' \# E% ]2 O' e; _4 N$ s5 lassign mcasp_ahclkr = mcasp_ahclkx;
" J" i9 ]0 m$ m# U. aassign axr1 = axr0; ) o6 R4 q! ^) \" B9 W
4 h4 K1 g( ~$ _# e7 G4 @) Q+ B. V! {在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 I! \9 Y3 w' S: b8 f
static void McASPI2SConfigure(void)4 T* X' ]) d' D4 F
{
1 A. Z. ]: j+ { gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; H/ T8 I# `9 p ]1 p0 x" UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ ?3 H3 t# m+ @3 b* [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 }2 ^& A& w( \; J3 z6 i& TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 W$ ^5 H6 D [) i# ?8 X E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
E8 A3 s# N6 B/ o; R9 CMCASP_RX_MODE_DMA);4 Q2 R) @% q% g4 b5 |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 T5 ^. c8 X6 X+ n. Y# U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; U2 ~) D+ A; q$ m- gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 o: k/ _& o2 \6 jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 [7 B: V, n* ^0 C# M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! [) o6 }9 v) V0 ?; j$ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 o* e; Z2 H; E% @ f* bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ ] \ S4 \4 U$ o. H8 gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 Z3 j6 `, _. g& PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, o Z) M& W' ]1 q& Z; Y x0x00, 0xFF); /* configure the clock for transmitter */
2 @7 y: G/ ]# B# U4 m8 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 F0 U, S6 f/ T4 b, i' K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 U! R9 U n% a6 p' VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- }+ C- q2 w% v$ o
0x00, 0xFF);8 }7 t1 X: x. C5 N. I
6 g6 y/ B& Z1 E' j) O$ B7 T/ n
/* Enable synchronization of RX and TX sections */ ' @' R3 b$ I, D# p4 C( u& F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. k. V& u" c6 L0 E nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 x+ [+ t' N2 v) B3 j; L( H2 d/ KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; R3 _+ J3 h7 z. K** Set the serializers, Currently only one serializer is set as
. _7 a3 y+ h( V _6 U, k** transmitter and one serializer as receiver.) i- e3 V. P* G+ b
*/9 _8 D- c' q9 k; t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 ]8 N6 s& Y- ^* n9 F" VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 l5 C: ^8 [) R' s6 p- o8 W# W
** Configure the McASP pins 6 G; ]4 P7 Q$ y; t7 k$ G. n# S
** Input - Frame Sync, Clock and Serializer Rx
9 X3 L: W! r: m, ?7 R** Output - Serializer Tx is connected to the input of the codec
- ]# R: }& J* C; n3 b*/# L( h& S- P% m- Q* X* }6 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 {# k' H9 t& b0 g& w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# p) W! v; d2 n3 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: p5 L& k8 Z) q/ z% F
| MCASP_PIN_ACLKX
, f( a" @& v; l0 x6 f( J| MCASP_PIN_AHCLKX+ Y! U" U3 r! Q4 R& R- l1 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- |8 [& x' X% Q- E6 A+ O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ O e# u+ B* \/ \$ c
| MCASP_TX_CLKFAIL / ?. V1 `" R# ]* T# a7 s' z: q
| MCASP_TX_SYNCERROR+ P/ _# \; l S9 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 T4 F4 E5 M: u6 K, Z| MCASP_RX_CLKFAIL7 {; i. i# j# |6 @
| MCASP_RX_SYNCERROR 9 R; x% q4 x2 K1 t7 c8 f5 P- u8 j$ \
| MCASP_RX_OVERRUN);
4 ~/ Q( A; X- Z- j6 P& Q} static void I2SDataTxRxActivate(void)
* W; P* [( t' l; a) t' N{
$ T+ d8 G7 {. C5 n- T/* Start the clocks */
* `" q1 B; c2 b6 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* L& V3 F6 S1 H' o) i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 j# z. w1 }% ?& r [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# _1 f3 v! T7 L9 \1 v( H4 o0 aEDMA3_TRIG_MODE_EVENT);
! k4 _+ _; A. J" p% @* g/ R* yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ T9 S3 f) j. Q6 ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( A3 k3 {2 ^8 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. x/ q8 Y3 g7 c+ {( lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) {$ u5 S! w @ N9 P$ G% A. }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 K- c( a; M: ?( O' ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; e' C! {, | z& ^- e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 T6 ^% N; P! t+ \4 j& W. m
}
0 b6 m- [- v! l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
9 r/ T6 ]; E- T3 q+ } |