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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* g5 f) h! _% d1 S
input mcasp_ahclkx,3 y& \' P6 a- a2 B& T/ d
input mcasp_aclkx,
2 ^" U6 k& ^+ C* Linput axr0,# q; b7 _$ N* H
' t6 M( u! Z- ^; b
output mcasp_afsr,8 q* o8 E6 y1 t0 J
output mcasp_ahclkr,
" S3 P7 _( F. |9 c" |output mcasp_aclkr,: A V2 s5 ?9 a& P
output axr1,
3 p9 S: ]+ z3 W+ z assign mcasp_afsr = mcasp_afsx;2 O$ X% O1 L( D; m7 J" ~
assign mcasp_aclkr = mcasp_aclkx;; g9 u5 N5 j; r# m& |
assign mcasp_ahclkr = mcasp_ahclkx;
9 B2 `/ q9 F9 Gassign axr1 = axr0;
`( u b& U# N* `9 \# w
% K1 {/ m0 `% S( q4 c7 P7 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' l' J$ f: ?0 v' [* k2 I- \3 A
static void McASPI2SConfigure(void)
: {6 R. U% u; b, P: p& V4 O3 a{
9 A* ~# k7 N* d5 H. FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ h! @8 `# L5 n, O/ ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) a+ y& U1 W6 i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; ?" X! O+ g5 _% D' V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 p6 r) ?" ~2 C' {; pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 Y3 N, f. I# G# JMCASP_RX_MODE_DMA);
% {) H3 V7 G: I+ _, l" OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 y; K6 y* ~. `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 N. d3 M% T' H4 Y, _5 i7 O1 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , r4 [) d: J( ~0 f8 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ o) [- Q/ B; r1 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) w; J1 |6 M! Q# ^$ zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: `' {! H6 Y5 P2 `& ?1 `9 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( T. T3 E8 K: q2 U) rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 t9 a" S8 O+ ? z( n$ n; P* ~/ X+ }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( M Z7 k1 q3 o. b; _0x00, 0xFF); /* configure the clock for transmitter */
! Y0 r: j6 H9 Q+ Z& n% eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* {' T9 S9 s- ?5 `4 D) JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ j/ x8 o. |7 N$ C9 zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 X p. a9 t, M* I5 l1 W0x00, 0xFF);
' ? G: L2 n) l5 O' t$ E: i( [ V2 t. j- e
/* Enable synchronization of RX and TX sections */ 4 J. I4 ^8 w$ p! P" {* B R5 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- r7 O6 `' k# R7 D# R- t/ @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 i7 b% Q/ [3 B; p' _1 G8 f9 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ a3 Y7 N, o. G+ d7 |* i
** Set the serializers, Currently only one serializer is set as
% d1 G+ `2 m; m8 t** transmitter and one serializer as receiver.7 |+ p- Y. p, w
*/
' C* k. Y+ ^3 uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ y' B; e; `8 O! x5 O1 W6 xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 f( T+ X n( z. C* ~/ o( G** Configure the McASP pins 2 z/ C8 i+ v: T/ i" V2 t1 L
** Input - Frame Sync, Clock and Serializer Rx
6 o. j' d: ~- P* F: H6 Y** Output - Serializer Tx is connected to the input of the codec
- c i4 j2 l/ \5 u*/
: Y7 [. d$ S( O: o& a* FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 c8 B. n& [; m4 k0 ?3 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 k M( N7 [6 N" v l5 S E' _! \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 y2 [! `% i. O; O" Y R
| MCASP_PIN_ACLKX
4 v8 Y$ Y h1 f2 V3 f- O0 ^ }| MCASP_PIN_AHCLKX
8 G$ { ^3 i. D5 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" M" @/ Y7 c) ]( a) A4 m, x5 E, k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 Y+ P6 f! I6 w9 b0 K8 D0 ~| MCASP_TX_CLKFAIL
% S9 g: ~' W7 ^9 s) M| MCASP_TX_SYNCERROR
* {9 }- ~6 C# H6 [" y8 Z! v/ N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! l' i* }) `3 s; n| MCASP_RX_CLKFAIL
( @( a! h# _/ L) || MCASP_RX_SYNCERROR 3 O! L! T: O1 o C5 a2 }
| MCASP_RX_OVERRUN);% M0 r K9 N6 { b
} static void I2SDataTxRxActivate(void)
2 [! Z6 y A/ O# s' L* j{ Y$ P+ Y9 r$ n" e
/* Start the clocks */2 R# c/ G% j. Y2 A( T) G9 p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 |* u8 y$ q5 T: Q" C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// d' o# ^( b8 o1 B' C \, R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: P+ N: r6 ~8 F
EDMA3_TRIG_MODE_EVENT);- J: x0 |6 T: u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; u) |" A& l. U% W$ e1 HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' ?& V: ^0 M1 m& \$ N6 I8 h* \, p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; E0 O7 z& P7 x: n r5 l8 o) A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 |6 ^9 A6 V5 @* Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( U- t" J8 O5 T7 p T3 E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' b5 g; o8 r2 u% U: cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); L; J% h) O% c
}
! l6 D+ ]# I. C请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) ]9 P, e! S) [/ x6 y' ^+ B
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