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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, j- V' d7 V2 K! i$ s9 K6 G4 z
input mcasp_ahclkx,
7 }; f. h ~1 f- `8 _1 G1 cinput mcasp_aclkx,2 o% p9 Q8 ^+ X3 l3 X; R3 M5 L# S
input axr0,
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output mcasp_afsr,* [2 x" @* U, F- J( ^
output mcasp_ahclkr,3 ^* ]; P; O/ G. O! z1 y
output mcasp_aclkr,4 m" V; y% x9 t! t7 ^/ }
output axr1,
0 I0 W: H: I) [ assign mcasp_afsr = mcasp_afsx;
# K$ z1 f$ E1 h Sassign mcasp_aclkr = mcasp_aclkx;$ ]; U: K$ N( `
assign mcasp_ahclkr = mcasp_ahclkx;1 t+ ]- F2 T$ N2 R5 X
assign axr1 = axr0; ! { H" e. i! ~
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 I: E& H( Q2 fstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ x8 t3 j4 q. q) o, c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 \1 @' u) Y* ~1 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ n9 }7 |+ @2 }0 C0 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! T3 ?/ |. k8 c9 Z$ `' n1 X6 a4 F, Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' H: l3 r$ Q. d$ o- W; tMCASP_RX_MODE_DMA);6 ? b+ Y$ N) R, D3 ~& h$ X7 G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( L* b, e3 K' rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 `. o3 R1 w9 |5 u3 p, H. }( {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
g) F( o6 g/ s6 g+ @, rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 m O& s; N5 Y8 WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, }5 _+ D/ m! q( CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 F( R }# T n# _! j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- v, f7 L7 g7 u2 h7 p% ]* O: e9 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + \; m$ E; X6 p6 D, u2 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 h5 l" D" W, l5 S
0x00, 0xFF); /* configure the clock for transmitter */1 g6 H2 Y8 r& w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* s" ]+ `/ J0 U; T- F0 Z. |/ aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: C5 \2 _: I9 h0 Z1 q6 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 m- E1 ~' N9 H7 W* O" u0x00, 0xFF);1 D+ r, s. z! ]9 d6 Q; V
) i( u9 c* _3 t/* Enable synchronization of RX and TX sections */
3 Z% ?5 D/ P8 y( b5 z2 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 l! D2 b6 m9 U( TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) }. |/ H. v9 |, \7 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( r, r; K! F$ k" ^8 {0 r& O! C0 a
** Set the serializers, Currently only one serializer is set as, p; G3 H# G6 X4 [
** transmitter and one serializer as receiver.' T b7 _! k ^+ F" B
*/7 z2 Z% A( y; J5 T* `1 ~' M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ S" q6 b8 I' S% b- V: R- k- d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ b- K4 h [9 D: [, w; S** Configure the McASP pins & r/ R' [6 V/ B, B7 D" [4 W1 \: T
** Input - Frame Sync, Clock and Serializer Rx j( c! K# v6 A% H
** Output - Serializer Tx is connected to the input of the codec 8 A. y. h; w2 W: _, u2 T" C
*/
! f* ~. m- ~1 M* ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 q4 F' M6 l/ U% eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( t' L, b) ~9 h0 A( RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 x9 } L, n& F X2 s: j
| MCASP_PIN_ACLKX
- f0 ?: R, S, l| MCASP_PIN_AHCLKX( k8 f1 h- D9 p. N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 b: B: D- n6 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 s. h( D/ w, L0 }
| MCASP_TX_CLKFAIL + s1 J, r% u: O: w- i
| MCASP_TX_SYNCERROR
: ~+ B0 P) |7 V! h. x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 C$ y# u, Z4 q4 D6 q+ n| MCASP_RX_CLKFAIL7 g: A& A& H& C+ j' p' H
| MCASP_RX_SYNCERROR 6 _/ F& W6 V5 h& x, i0 d6 }
| MCASP_RX_OVERRUN);
, _$ \' a. G$ ^6 m} static void I2SDataTxRxActivate(void)
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4 G" j* ^+ Y" ?! m5 U. ~5 D/* Start the clocks */' J6 j2 C0 _& s) d
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
e( B. E- l- M9 y: ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 S/ D( H& p" z5 B6 s2 J' E% ]; Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& k {. C7 _* t. C/ S
EDMA3_TRIG_MODE_EVENT);( p# ]8 }# F" N1 _4 j9 v6 p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 M% J9 Z, k4 @0 M5 c$ V$ E i: GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 p5 l% [% C- L# S$ WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( Z. L7 O- t$ _" _/ O. cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 O: m* @2 n3 v9 ?! y% M8 x! [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& r3 M" h3 Y2 u; G% n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ P6 v5 y7 D5 n, L m) S$ TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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