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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* {' x6 U/ `3 b: R" Q8 u1 _
input mcasp_ahclkx,; G% G/ o4 @7 Q) E
input mcasp_aclkx,
6 a. P! d: ?9 f1 |- s9 D+ sinput axr0,
6 E* F0 d7 X* p, P r& n& B& a9 V: a7 A7 L& j$ |. H
output mcasp_afsr,. v* r1 M5 Z* ] o
output mcasp_ahclkr,1 O* F' K1 M0 ?
output mcasp_aclkr,. v8 k. h) j# s0 X% D7 ?: y
output axr1,
+ ?) P; {$ W% t+ I+ d# O assign mcasp_afsr = mcasp_afsx;0 W! n$ W. O* g: d
assign mcasp_aclkr = mcasp_aclkx;
7 U0 x5 V( J/ A& c8 gassign mcasp_ahclkr = mcasp_ahclkx;
7 K+ u8 ~1 {+ w7 y) j/ Y0 Eassign axr1 = axr0; 7 s; c5 \9 G# i: k. h
( }: T v# p! x7 h# E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ c5 W7 }0 ~5 o; Z [7 ^static void McASPI2SConfigure(void)
. e: U {, y; g* e7 H{
" _" y+ @- N `/ K1 x/ hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
T+ W+ E( F- `: oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
i7 R7 q! }' l/ W; x$ ^+ DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, k- K+ Y- s/ w/ t7 D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( ]- y6 u4 f$ ^, gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 a& U7 E* |. B4 u U8 l
MCASP_RX_MODE_DMA);; m! q: L7 l! G# E- j) G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 u7 M+ ]" h: sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// {: ~+ n, m% S6 F; H3 D, m
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 q5 ], _5 i& y& a/ s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 F+ G9 ]6 f5 u( a( x; O5 b YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ N; \9 h, f3 rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 s: j3 j$ m5 @2 I8 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* }; N; P6 C4 |0 u& |' h: |3 y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! c4 N, ^# R- f2 c+ F2 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* v" A) t6 U+ `4 A7 W0x00, 0xFF); /* configure the clock for transmitter */% I$ m; V3 I7 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 x" d! c0 b- s( A+ h7 F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! ^1 _8 `6 ^! T; }3 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 \1 @5 O& W4 K- L" X# y1 d" Q0x00, 0xFF);
3 j3 ]+ G) k, E+ s' h* p8 v) b
& c, N, U! N) u1 U! t, F8 G) m/* Enable synchronization of RX and TX sections */ ( I* {6 r7 W# m) } t( G( z8 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 d) _7 l# U$ \! `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 n2 ?9 e* O+ }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) b3 O& e9 f" d! H% e** Set the serializers, Currently only one serializer is set as
, T) R) r$ ?) N9 M- N, Y1 |9 W* ]** transmitter and one serializer as receiver.( w) X. H$ J1 w# i. n3 P5 C4 a2 t# }
*/
2 t4 M! U+ Z! O' H: T2 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. t& j3 z* A! D/ D, }- z/ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% H4 n; {7 U6 R2 ^** Configure the McASP pins
! q( y$ T& J6 G- K** Input - Frame Sync, Clock and Serializer Rx/ v2 [; r( a- G! I! }1 t* l% L. R& L
** Output - Serializer Tx is connected to the input of the codec
& `# u. J/ u! M6 _6 K& v*/
* J) T5 u+ l7 x9 h9 Y$ bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. s# u/ l. d5 O* DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* I }5 h, i$ `4 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 e, [& l# l5 W$ h( }) r| MCASP_PIN_ACLKX( X/ ]4 z C" G% @
| MCASP_PIN_AHCLKX5 l. ]8 ^, S( U9 n6 x2 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, h+ \! n+ R' ]- O2 m- Z/ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % |: `1 P& v' m5 ]- b
| MCASP_TX_CLKFAIL
& J! i( y# h5 E, f: {- v9 y6 i; m| MCASP_TX_SYNCERROR( [) ]5 \1 ]0 ?) r& u( l3 {/ C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 W9 n# S! L$ ^* U B! i, ~8 A( M| MCASP_RX_CLKFAIL
2 {4 Q! R( ~# E6 z$ A' f| MCASP_RX_SYNCERROR
+ z: y& z S: ^9 O q8 d| MCASP_RX_OVERRUN);
4 {; J: P, Q$ v0 Z0 B" {/ w} static void I2SDataTxRxActivate(void)2 _& O( f$ _1 R, q
{
. a6 h) `2 ^2 [! X/* Start the clocks */5 p* f2 L9 a. p% h8 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ h, A' m+ ?) r7 X8 x" Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- K% V- X6 Y; Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
q( O0 ?. Q( }1 G8 {' JEDMA3_TRIG_MODE_EVENT);
( Y$ T5 F3 w/ m2 D) e8 K) O# ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . J, b7 }! b2 S% F4 z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* ~' E. }$ \/ n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ z7 v/ K8 M: q6 j6 ?/ @5 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
W: s( i) H7 U0 Q7 g1 R1 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! R+ k: ^5 W: H1 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 Z% u4 D4 l8 [% d# H4 c6 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% e& `8 U; ?, `% O9 ]
}
' Q( q9 e" x3 E+ D* e% v" v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 q, A9 c! E: y9 k" f
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