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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 i( [# R7 p b% }2 h4 p; u. e
input mcasp_ahclkx,
' x2 u, h4 R$ v( `/ l4 i/ ?input mcasp_aclkx,! f4 i$ x+ @: @! r- y$ n
input axr0,
2 w% H7 R) b$ [' j1 i6 y
( X6 W" ?+ J* G) C( Voutput mcasp_afsr,' p* R0 m3 i/ e5 L& w9 o) ?0 O7 O
output mcasp_ahclkr,
: }/ n7 Z1 z p' U- \" P$ t4 h# boutput mcasp_aclkr,$ Q$ ~# s4 ~1 ]. ]2 F; f
output axr1,
2 t1 {, d) `% I$ k/ o( V! R assign mcasp_afsr = mcasp_afsx;3 n% h' X6 c m x
assign mcasp_aclkr = mcasp_aclkx;' B: [" B: O5 z3 J
assign mcasp_ahclkr = mcasp_ahclkx;
" b: D5 Z: V8 P& u% eassign axr1 = axr0; ( B) N9 l. r. h3 C" C4 P& l- J
% t4 J) m a' K6 q% ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( L6 t) Q" K/ p8 Z1 H
static void McASPI2SConfigure(void)# }! C7 L; _6 a; V4 _
{
" m% g: ?7 H' M# ~/ YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* k7 `: A8 v" o0 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; C3 X! K5 g6 T' F8 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. j A3 i; Q0 G% E- uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) w+ x7 |6 d9 H, V5 h) K. ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ D% K6 P D; `- f5 m7 P& pMCASP_RX_MODE_DMA);5 O D/ r Z; u& v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% |5 G+ h# A9 A! B D: M4 o) @) uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) |2 k; b; Z; x _) |0 H3 z( z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 u0 e. ?5 h, ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ \; b% `$ [9 p% B4 w/ P+ |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; x- h* s3 Q, P6 } Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 V2 V0 \4 G8 k% C, L) `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 o k6 b! {% c# \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 G! {+ _# T: `/ Z1 J2 SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% b: [6 B$ l0 u4 Y- g$ a
0x00, 0xFF); /* configure the clock for transmitter */+ l( [: A1 }: e3 J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# P- @4 m- M0 P' @5 I. H5 J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 j. i0 O1 X- B* WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# C( A U' ~: t/ {* @! ?4 R5 c0x00, 0xFF);
# v! W5 {7 }0 O, G s I) G
5 l# M7 a, F) p, g/* Enable synchronization of RX and TX sections */ ) j" x4 {: n" r/ {! x( V+ _2 p" g+ p# V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
J" x, [, }9 t' j3 hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
y/ y* h3 D1 k. [% dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& j5 d5 u8 ~' e2 n** Set the serializers, Currently only one serializer is set as
" v, b+ t" @% D& {& ~** transmitter and one serializer as receiver.! l- U1 z. Q; d/ \! y; U
*/3 U, {# w0 U3 O. H. U" F n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. {/ T7 G0 ]/ [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# ]8 N! D8 i+ D! E& H% V# i6 E
** Configure the McASP pins
' u& y7 x+ k7 s" P** Input - Frame Sync, Clock and Serializer Rx
' h/ P/ J! Y' G8 x0 @( e- Q** Output - Serializer Tx is connected to the input of the codec
7 p! Y& m" S( B i4 N*/
* X9 l% A) T& k2 w* `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 z6 l6 x( ?/ R2 t: S' l9 _. JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 h) E0 ^7 _' E* F" A9 l0 ^3 G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 `/ J6 y; [, U- Z% ^( i0 ]
| MCASP_PIN_ACLKX
7 f- j0 {% o! a3 C' `; C| MCASP_PIN_AHCLKX
# O3 i, W. ?2 Z* a9 t1 J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 s) i* G9 L# q' G- D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" U: Q9 k' B8 T% ^. u% }# t| MCASP_TX_CLKFAIL
: z. Z9 L$ U* d| MCASP_TX_SYNCERROR3 ?# f% ?; f3 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / @, K% Y+ Y+ K) \% ?3 N( b7 y
| MCASP_RX_CLKFAIL; t9 K& t! ?. p; @. }
| MCASP_RX_SYNCERROR
6 V: k; i/ }% ?| MCASP_RX_OVERRUN);
6 R* t' I; {( P, k2 z# V} static void I2SDataTxRxActivate(void)
7 J; P$ u: C- _5 K' b3 r3 i{& q5 [* \+ }6 ~. a; \
/* Start the clocks */
- O2 I3 B( T/ |: f* @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ?& T1 C2 U: B% IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 Z8 J2 F" @0 r6 `6 G* x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 c- i, m$ z& f( S
EDMA3_TRIG_MODE_EVENT);( ]! v- w* b6 u% z6 g+ Q O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! U, R- g5 a: C& S/ c% I0 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 M4 U1 y. D* TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" Z$ D2 c: M8 D7 {5 v4 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 d7 K( a) s$ Y& v( Q7 f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! r. D' r( I& ]6 j# j' g1 Q' m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ i) V9 K5 y/ g; PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 E2 f2 c/ o: [2 k; j}
5 A' ?, S* J- V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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