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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 i1 z' z7 n U ]
input mcasp_ahclkx,
4 T+ O( Q# K3 M4 k+ v" zinput mcasp_aclkx,4 o: A' w$ v' \- N
input axr0,- p& o6 Z3 @# l( V
! Y3 V/ o) f1 {6 ?. ^$ `- Boutput mcasp_afsr,/ ]8 s. g/ W% t/ H* h
output mcasp_ahclkr,* Q8 i' ^! l! k' r) T. `
output mcasp_aclkr,0 W2 @9 H5 \/ @
output axr1,; J. p# e% i6 w/ C1 s9 P
assign mcasp_afsr = mcasp_afsx;
/ r2 W3 ^( k. X5 d3 [# vassign mcasp_aclkr = mcasp_aclkx;
8 u/ B' R# z3 Dassign mcasp_ahclkr = mcasp_ahclkx;
2 u+ v6 X9 q3 s9 hassign axr1 = axr0;
) \5 |/ V9 H; g" z! [( ]5 W) a. Y, T! Y5 M) P8 e& w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & a3 E( L$ u. y6 @$ G: U
static void McASPI2SConfigure(void)
. B4 |4 m# P ?& h! _7 j{8 ^# ?8 h( O5 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% o! Z0 Q* k% a2 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 o! V$ G0 `" g- d/ m3 R3 ~5 |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 T: w+ C# ^8 C4 S! m+ UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 G3 R) } E8 E, {7 s5 p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- `4 T4 E& k2 q6 m% Z0 h
MCASP_RX_MODE_DMA);) B1 u$ z' |) b: M, T" e# {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 ~( j* A b: y/ w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 ^5 L) @8 R/ o! l- q2 c! lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& {2 e7 R' N ?) A' Z0 O+ nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 z* E5 M/ q i4 b. c- ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 `7 C4 u& O" UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 R9 Y6 j8 U# S; q( A( NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. Z9 L. ^9 t1 _1 l1 v4 T1 |- d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) z3 w" ?. c( M: n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- G- p3 v. G; P) V% P
0x00, 0xFF); /* configure the clock for transmitter */; A, J6 I* Y n' @$ b. D% O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ V7 w; w* D' g1 D8 M9 z% xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 K2 g5 n0 R. H6 T! Q1 v+ y. ~
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; B% B% }8 a! p, W) U# V) `
0x00, 0xFF);
3 W: K5 B4 z, d9 N- _" Y8 t! a" A9 H- g/ A. ?7 z: v8 d
/* Enable synchronization of RX and TX sections */
* n' i8 W- T& vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' {' U0 {7 N5 ^ I9 W- a9 B/ yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 T4 i! o$ x) v$ J3 p, Z! O" n/ N/ m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; Q4 A& c! A9 a9 q$ F** Set the serializers, Currently only one serializer is set as% C( T: [" h3 p1 }( J) S7 Z
** transmitter and one serializer as receiver.
1 C* c4 k. j F9 a* O*/
7 i/ i: [3 a, U3 s& A% ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 y9 S) H1 z' R* p) }" f/ F; A K' EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ Y: I n/ q6 r** Configure the McASP pins
: X) b5 C& ]6 p6 n* ?2 }' l2 v8 ]** Input - Frame Sync, Clock and Serializer Rx! H1 G4 Z7 r* c9 m3 Q3 R8 N* L
** Output - Serializer Tx is connected to the input of the codec
+ p' ~: n; X+ |9 f( J3 }0 d2 S*/
0 z* c9 v; K4 l* AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 G+ e0 Z6 [5 e; C ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' C; w/ H- J0 g* I$ m5 H7 [4 \3 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: o, g* b0 n$ u7 `| MCASP_PIN_ACLKX
W2 o' ~, z7 z* {: i| MCASP_PIN_AHCLKX
( ^; Y! g5 N- a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- C( B1 \ U0 E2 r( J) r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: H1 {" e7 c3 k# ]- X6 a| MCASP_TX_CLKFAIL 3 n% z& m7 C& K/ f( y+ `
| MCASP_TX_SYNCERROR7 I1 |; P8 g. e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 [" C1 e' ~8 H| MCASP_RX_CLKFAIL
% W# Y, q! ]) \# J# @$ K) z| MCASP_RX_SYNCERROR 8 l+ ^" a$ J2 |9 I9 t' H
| MCASP_RX_OVERRUN);/ o" E+ a& F) t' a) p$ y& ?5 ]% Z
} static void I2SDataTxRxActivate(void)
- m, e7 \6 M3 E/ j( w) S: Q{
$ W" L, ^$ G7 s" `% X/* Start the clocks */7 r( L4 E* U; `1 @$ h. I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* M- ^! P$ C h: R3 G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, i* a# i1 \6 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 \* s F. i! ^$ s; c$ _: X/ AEDMA3_TRIG_MODE_EVENT);
- b5 l% F5 v2 ]) QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : t2 _5 X- Y- B7 \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! t0 o' {; g8 E' j; D# Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 e: P Y( b; \( gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
w# X/ B' H6 p8 C- Y- p6 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 R( k/ W' B5 N. W1 R$ Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( w0 y; m2 V2 d! E9 O5 s0 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" k$ O+ r# t+ b
}
0 d* i1 o; k4 z9 D, e' q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 s- k. j; S& {6 Y) l( c0 g
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