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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 C$ _9 v1 ?1 P$ j
input mcasp_ahclkx,
+ \- v* h3 Z( m$ {6 D6 C) Q, Oinput mcasp_aclkx,2 ^0 K3 l, z& u
input axr0,
, ]4 p+ _0 @, V; O* T2 ? P% p
% q! ~4 H/ u' D- `- m routput mcasp_afsr,
9 ?& E+ y: l9 ?1 `4 T6 T( F' G: G# Routput mcasp_ahclkr,
! m2 h; b9 P, z/ g6 T3 e5 n" |output mcasp_aclkr,- S* _# t5 [+ i" C# ]1 `" i/ {& q
output axr1,' n: U* U {- t% ]
assign mcasp_afsr = mcasp_afsx;# @, `7 x4 n8 Q) B
assign mcasp_aclkr = mcasp_aclkx;1 o' }4 ?4 X% b+ y' M" s
assign mcasp_ahclkr = mcasp_ahclkx;
/ E/ i, n/ Z: F6 l2 E R$ M7 cassign axr1 = axr0; ( ` b! J/ ^3 Y( O6 N
6 s- Q) K% I8 }! ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + S s4 ?3 ~/ J/ z" b2 y
static void McASPI2SConfigure(void)* G1 |+ Y$ V( w f; P4 u9 R
{
& |8 v! W8 ] z) vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, P0 n2 g, T6 _( oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, k1 W/ e5 d/ K5 \5 ~/ YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 r9 d# h' O/ L" z# N3 d( qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ J* {& u K% k, D7 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- b3 d; q6 N$ |3 p9 W2 t3 A! T
MCASP_RX_MODE_DMA);
' i$ B1 w) d( S7 P% l& r* U2 v2 WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) D$ I" j/ H4 ^! ~7 c+ a) X/ |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% [- ]+ m$ Z$ c& s- W' L& Z. T: kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) J" F- r; C- e: ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! t0 k& J$ f7 w" C% C, a" L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! Q5 ^: u. C" M$ O' Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 R: n1 x* c" F$ S; M$ ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* R5 |( ?3 _4 X m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; d: b- q+ \0 l$ u6 Z( K9 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ B5 L, w0 M! \+ @( }0x00, 0xFF); /* configure the clock for transmitter */
# K7 L2 W: r& [& | R5 f; E; LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ d) p! P$ I, G3 t! r: h FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 t- x n; p: ^$ Q. T: M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
W! c6 s: c& s$ _0x00, 0xFF);
! U/ T* K! B% u0 q h
7 }" t1 n( p6 q' j( z3 ^/* Enable synchronization of RX and TX sections */ 0 Y1 p: @/ h% X0 W) k/ e b
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- F/ B# ~' }: C, S g) ~) x, I$ q o% P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 K2 z; u/ j TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* M5 t$ ]* F( m j** Set the serializers, Currently only one serializer is set as
$ J \. n2 S7 X" M7 M** transmitter and one serializer as receiver.
% c$ B+ y9 p& Q: x) U8 R*/
1 |- ?5 \8 V7 K2 L0 KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 A' X9 D" u" Y' H% W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" E# H. }1 X) }- ?** Configure the McASP pins , {/ N, a0 d! O$ G% M' P& F& F
** Input - Frame Sync, Clock and Serializer Rx
- p( u: G+ c! f1 \5 T+ v2 J** Output - Serializer Tx is connected to the input of the codec ! z: s3 P9 _! L: u, b
*/
. z- M, ]& I, c5 ?7 S: y9 R+ WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! r# p' ^) m6 i" c. D. ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 q+ o" h, \. g8 QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' _7 O: }+ V) Z( A; H
| MCASP_PIN_ACLKX( `. z# ?) D0 L& v7 j
| MCASP_PIN_AHCLKX+ V3 ~& {8 z& u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 h4 C4 {( O9 d) j0 Z8 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 z& X, t1 {2 P/ Z
| MCASP_TX_CLKFAIL # w! y8 s$ V7 _: m' }
| MCASP_TX_SYNCERROR
/ H2 i# x0 d3 I& ^0 z/ B) E p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # }2 X, ]: G7 z" Y
| MCASP_RX_CLKFAIL6 C; i0 h0 A4 ^5 F& J- X$ w# o
| MCASP_RX_SYNCERROR 9 O& l X M7 b6 ^* C
| MCASP_RX_OVERRUN);
2 U% E: }% R2 |& n; H9 _} static void I2SDataTxRxActivate(void)
+ I) W; m" [: o$ _* g7 R{8 L3 w4 n1 A0 ?9 a1 @: |
/* Start the clocks */
8 J! f& a5 e# E, M: b' o5 X! l* JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ R2 x0 B2 i% J% K; ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 p7 S4 f" }5 u/ S) f5 [; `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ P: Q+ B) A2 i% ]EDMA3_TRIG_MODE_EVENT);/ W/ A! K0 s u& m d" z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 j7 L p( ?5 h9 U% K9 AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% n, p; G( G& C R7 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 z1 y8 a* t' e9 r* j) k, g7 u( c* JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ ^0 C% K) M2 Z* x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& J$ N/ L% C5 Z: o7 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 }5 W/ ^* B( @! |# ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 d3 j% f k8 d' M" U
} 7 ^# k3 R* \3 z4 x" p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 D: N& V# c8 c2 x& E
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