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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 P @5 ]' ~9 A9 |" d5 S. [input mcasp_ahclkx,+ d$ B6 l8 x1 P9 X4 ?: p5 g
input mcasp_aclkx,# ~# f$ t! N0 ~8 a4 y
input axr0,+ ], q2 p6 D6 k0 g' s+ ~/ ?; u/ V1 \
& @9 H: r1 d* D$ f4 Youtput mcasp_afsr,
( {5 Y5 _8 f5 t* A4 S0 \. i3 routput mcasp_ahclkr,+ d# U) K$ b0 S- ?" Y' Y* V' q" W
output mcasp_aclkr,8 G* O3 ~6 J, T2 C1 |
output axr1,
5 K( D" p x+ e' r assign mcasp_afsr = mcasp_afsx;
* I9 j7 ]5 x0 ~* z' hassign mcasp_aclkr = mcasp_aclkx;: o4 p# W0 |( A0 A
assign mcasp_ahclkr = mcasp_ahclkx;' m- f5 U& u7 v5 }: [) F0 Y9 y
assign axr1 = axr0;
* X8 v. {& L3 l* v& [, [; @5 h! ~) K2 l; t
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 F/ ~. C, L1 u. D/ K. Mstatic void McASPI2SConfigure(void)
' O- g* p( B" P- r3 P( [{" n$ i5 T4 L( ^2 L4 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ e3 L- ?( J6 u; i' \; O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: L4 Q5 H; ^* H. Z; D! @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ T0 t, W* {6 l; [0 Z& U6 e6 IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! k" p! U2 h% r" [ NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 x3 [8 z4 C5 c8 UMCASP_RX_MODE_DMA);
" B- ~: K6 l5 J, }, \% g+ aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ f- |) Q" o8 E$ U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( h) s) @8 r7 u" u. R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( ]- f: L% G. q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 g1 A! M6 Y; a2 O; [/ yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 F M4 A3 K3 B5 A7 S9 {
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 Y, x$ ^, C D1 T: G- {' CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 e; h3 h: X: B( f. K8 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + C; J4 Z" n( F" W6 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 {7 q2 _: ~( Q, J+ ]; C
0x00, 0xFF); /* configure the clock for transmitter */
. J; _- i* y2 T; s% ~! s. RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; I: N" E1 F3 Q# A6 V' G1 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 B2 ?: F2 g9 A) oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; o3 P: b: [5 ?0x00, 0xFF);+ J( U# W" U) ]: R6 ]
# g. z* F' _; a4 O) ~2 p
/* Enable synchronization of RX and TX sections */
3 e& e+ k E, FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 |/ s* ~* O# |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* c8 j- d5 X. T+ R0 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" q, `3 i2 _; J c2 B- P# p y ]** Set the serializers, Currently only one serializer is set as3 H L: ], ]( g0 G! P1 C
** transmitter and one serializer as receiver.; R; d% I3 b7 }* L7 i" E6 E
*/
. ^! r N, b! i8 b yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, m, A: ]; U" I5 L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 }' A- @) K, D f: m: U** Configure the McASP pins
6 E9 l: g0 e0 Y: w5 u** Input - Frame Sync, Clock and Serializer Rx( V1 k$ E1 ^4 Q3 g/ A, V
** Output - Serializer Tx is connected to the input of the codec # w+ @2 ]- P8 P4 ^) m; B! [
*/
- B2 c' o& c9 d! D4 |' yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 u$ d7 I. C. X* K7 OMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% ~* A$ H) y7 s2 ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ m+ Z# o. u. J& u) r6 ~1 R* h| MCASP_PIN_ACLKX
" }/ x' |6 D5 W3 h/ e/ y- R3 \| MCASP_PIN_AHCLKX+ u- J" n7 F: v& j! ^% k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 l* [ u; S5 A) Y4 s" g8 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' p+ k2 J* y- ~+ ^| MCASP_TX_CLKFAIL - r/ U5 v6 ]( R" A, O+ }
| MCASP_TX_SYNCERROR6 x6 `8 Q# B, t4 C& J$ \. q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 K3 d3 ~) H& v0 Y
| MCASP_RX_CLKFAIL# ?7 O: A9 k& g7 ]. {, b, _
| MCASP_RX_SYNCERROR 7 u N s: Z' e& {
| MCASP_RX_OVERRUN);1 W; ^+ G- g5 b% ^ ^5 x
} static void I2SDataTxRxActivate(void)
2 t4 G, w1 V' \: l7 f @{) r/ |6 S7 i/ q+ B/ f6 ?& d0 |
/* Start the clocks */1 c; m) L! Z5 W/ J0 Y/ ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 d$ C0 X/ e' P4 lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& d( W& |: ~3 j* r" m x6 c. H2 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: t- D; T6 O$ a) x2 d- hEDMA3_TRIG_MODE_EVENT);. H, m6 s, c9 ^( |8 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: X% E# y$ C! P3 R) s( kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, V! r1 w, {! T* {/ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 `0 Z# V, h \# \0 J9 C+ t, n3 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 y4 N8 [" _3 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 W' H, x# T' p/ z0 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) W) h @* e9 n
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( n+ r: i6 k/ M& ]- H# z. U% T}
" |8 k8 k* m9 U! p8 X6 X$ u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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