|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 o' x3 o4 Q1 P4 _3 }2 y% C3 yinput mcasp_ahclkx,
0 C: v' g$ S. Pinput mcasp_aclkx,3 K W, I* J) m6 D, Y/ u7 l
input axr0,& l/ _1 l: Y: u% R( ~& J" ?
! ]: a: Z. X. c
output mcasp_afsr,: M6 C5 I0 X% L0 u# V+ e" Q
output mcasp_ahclkr,
& ~7 k" x# o) E- j$ N8 o9 ` Voutput mcasp_aclkr,
( h# b$ X! T6 N- A) b2 l7 houtput axr1,
( c8 Z; `6 L2 r3 H9 I* E9 R" r assign mcasp_afsr = mcasp_afsx;2 _& m" P' `2 T+ M, U
assign mcasp_aclkr = mcasp_aclkx;* j) r7 m: n; u8 n2 k. f
assign mcasp_ahclkr = mcasp_ahclkx;
8 X2 k9 C) g6 R/ tassign axr1 = axr0;
0 u( @& s) z, L3 f8 G
) f2 D: x' E3 j$ B- ?0 r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# _- Y* {1 V! G2 _/ c: n" y1 |+ p, wstatic void McASPI2SConfigure(void)
9 L. H! o# p& N{5 ^' t2 d0 ?" a4 m, @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 Z1 l' L y! y! { {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 y- N* y3 D% w0 R0 N) m8 v6 d7 N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ E5 A" A+ y& [ d6 v+ ]. u$ G& W' o IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* y5 ?0 W7 ]; n, {3 j# j {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 y* A! v: V( b" i2 d6 ]2 MMCASP_RX_MODE_DMA);% N0 f5 e A" B6 ], ]) g) ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 A6 e& \( G% ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# c( f" o+ @3 P! x, v% t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' L* q4 c. p( }/ T/ hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 e0 D/ Y" {, s% X9 T- H# _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. C+ r3 c4 V8 W/ qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# T# ~8 Q2 F6 U5 e' p0 u3 f0 v3 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( g3 P0 w9 H% R3 R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) w/ t: h: ]; I& G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* A/ E h3 f' z8 Y( r/ }) a0x00, 0xFF); /* configure the clock for transmitter */) \ i2 M# w* q8 I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* _- i" W- @9 G: I4 f) DMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 V3 i3 S" `/ y9 q2 n" r& D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 m' B' q6 v q" n3 s0x00, 0xFF);
i# k+ ]+ P* p9 l8 c- f1 J# c! T0 L8 V
/* Enable synchronization of RX and TX sections */
( x, g$ c( v" t! u9 K8 O5 QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: I' [# T% R9 \# a' uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 N1 J$ @! _- |$ YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; T! C1 C, S6 I2 X$ z9 \. X
** Set the serializers, Currently only one serializer is set as
# T S9 u6 {- J& m3 g% N; m** transmitter and one serializer as receiver.9 j$ ~3 v8 h/ w# K5 f6 T
*/
. X1 g/ C0 I+ K/ G1 I" u" i- WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 A$ y! o+ Z3 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
m- g) t6 Q J** Configure the McASP pins / X h9 m! `6 [+ Y# ]7 T
** Input - Frame Sync, Clock and Serializer Rx
3 t0 i C" C( q4 I3 ^# K8 H** Output - Serializer Tx is connected to the input of the codec
: C4 ?1 F& }' ^+ W5 o*// J" L) e. x$ {& Z' a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 b* S( p% l" @ k8 R5 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ D3 f$ `1 m, X- X* |0 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ P7 i' c/ i: _ h# e. F, N& a| MCASP_PIN_ACLKX
) t1 D7 n( d, h/ S' j| MCASP_PIN_AHCLKX
; x4 Y' U! V* C0 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* V& {+ K8 \. v7 R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 G9 H9 u- A& U: a) ?
| MCASP_TX_CLKFAIL
( ]7 |9 B8 W. Z1 S/ k$ d! D s5 || MCASP_TX_SYNCERROR8 Q% {; n- W1 g" c0 s+ t' L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & v; C+ R% J( a) |: m2 f( C
| MCASP_RX_CLKFAIL# x( F. c* F# c7 T/ L8 c8 I
| MCASP_RX_SYNCERROR
3 N/ w5 r n+ E+ ?1 o| MCASP_RX_OVERRUN);) u! q- o$ y9 B' E: B0 a) t4 ~
} static void I2SDataTxRxActivate(void)" R$ w( O) `9 ]3 k
{
/ o5 i9 F q% c5 C, l7 O/* Start the clocks */
0 \- k y! t, |9 Y6 T2 ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ U W8 ^3 A/ m* i1 R3 ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) Q6 e4 ?4 [/ k" N4 l' YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* R7 L# ^ |; m, dEDMA3_TRIG_MODE_EVENT);2 \- X, \; ?& \/ B+ T) c0 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 y0 T& o' T. D+ FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! g- n( j% M+ y# y5 E8 u! U& X$ q4 TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: w8 U' D! a9 z6 A6 J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* F, _! }8 b' s/ {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% p6 ]; i+ V6 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. B7 J% v6 m, p% f8 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 e% c# K% Z- L2 ]0 ~}
- r7 R- D$ O" a! o* F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
) N3 @5 f/ R. F$ v D# t, j |