MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
) _9 w, w% n% y4 ]) g0 qinput mcasp_aclkx,
8 S% ~7 ^% ~$ Z+ y/ p4 S3 G( j9 Yinput axr0,
( v/ o- z  Z6 O
output mcasp_afsr,
# y' D- H7 |  Toutput mcasp_ahclkr,
0 d+ V1 Y2 v' noutput mcasp_aclkr,
output axr1,
  l3 x$ x/ {' ^; F

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
5 q( q9 J. P, A& J5 x' oassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. O, Z0 @- c. R' R5 O

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
3 B: n8 O1 }; u4 O* ]# ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
5 ~6 J4 d9 O9 M" X' PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 o! }1 n2 I! L: ^MCASP_RX_MODE_DMA);
& k' |8 k( @7 q  B! kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! z+ J& A5 c; ]& Y* y; g7 XMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 Q4 l' n- j( i6 x% x3 ^/ [3 n4 gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
' n* M6 B2 @8 K: l6 ]1 z  u" MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 ~: E- K5 R# i- _* R3 nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" N, Q# L8 I+ m3 p% N, {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
( |4 Q9 G* P% q" pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ {! U' C) Q: h/ @( tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
, M- Y! B6 s! S/ r. PMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
! T6 c# a" x4 X! [2 j. J# y' {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
% h- a0 k3 T+ n4 \* D' w- x' y/ o*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 A+ _, G. ~. d9 d. X1 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
! V3 A! [8 [4 ^0 U$ X9 T** Output - Serializer Tx is connected to the input of the codec
*/
6 f& D) c( g) FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
) k" `, s% d6 i* e| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 Z1 V! ^8 U7 f  j" M| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
: _) m, D1 V2 O9 E8 W5 K6 }4 Q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 q- ^0 X% ]& c| MCASP_RX_CLKFAIL
- t- h! w" z3 K# Q% l| MCASP_RX_SYNCERROR
* G4 b/ j: A% N5 ?, a| MCASP_RX_OVERRUN);
, M; b3 s/ F: Z  N) t}

static void I2SDataTxRxActivate(void)
3 _1 v9 K/ ]5 A+ p4 I0 |{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, M. y6 |1 Q* i7 }+ A+ g9 N5 fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
+ o5 J$ k" T+ T; ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# U) s( l3 m5 K7 G! e/ {% QEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
8 L% r9 l2 W0 @& o* dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% H5 Q, \6 n8 Q" [* y; |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
6 U+ M+ W4 }  X# I- rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
  R% o/ n% Z" O, F: P}

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请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

! W8 @6 T- M" }: q0 D( Q0 ?& Z