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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ ]/ I2 L* i( ~' U" t, `input mcasp_ahclkx,/ d& U8 q! U+ q$ |& y. Z
input mcasp_aclkx,. Q! h0 Z4 k0 g! q, T6 u
input axr0,# X9 _2 s- i- I4 k" _ f
+ y, `6 k5 Q, l# aoutput mcasp_afsr,/ m0 c# |7 w: y1 p
output mcasp_ahclkr,
# \( u0 E8 E$ [& x- Aoutput mcasp_aclkr, {- Y& f- F1 t% {7 P+ E4 j
output axr1,6 m0 F' F7 [+ ]4 f* _1 P. U+ C2 j
assign mcasp_afsr = mcasp_afsx;0 h$ N- r+ I+ q" M: i
assign mcasp_aclkr = mcasp_aclkx;# ]/ V4 T7 i" q$ f, X
assign mcasp_ahclkr = mcasp_ahclkx;3 T# A2 T" O% M" k3 W; |
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & [9 Z" B9 P5 q, C
static void McASPI2SConfigure(void): H7 O( z( b: j0 G) c
{
2 l& D4 @, D8 M6 r- z+ }. ?7 w: oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 \3 J: u$ Q& s$ I E" S: LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ t4 h$ \. Q; \2 u# v9 aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% q* _7 l0 M) F; U6 K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# G" X$ t2 Z9 e; N+ m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! s! |6 r+ o5 g6 CMCASP_RX_MODE_DMA);3 c; p- p9 U# |: C5 ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 J( L5 K+ z6 D6 P/ w# q$ QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! [) D4 v# E# [% ~9 L2 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: a% y* ]+ w$ H; X# g/ D N4 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 s+ m6 N1 `7 d ^, ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 k7 U2 T3 C% a ~0 o gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; J$ L. h) C U; N$ y- Q4 {( ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' O8 {/ q; a3 C% I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
G! f- B6 o }( Y! b% M0 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 J' A' e# l- b+ V4 z0x00, 0xFF); /* configure the clock for transmitter */# d" `# ~+ k, n6 a0 v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 R# R6 G/ {% P! o: G9 }9 ^( G+ q; yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 a3 f* @# |$ d) u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% v' z4 m/ a" F) Y2 J7 T0x00, 0xFF);1 |! P( z% T3 m- g1 @9 ]8 `" z+ ~
2 p* Q9 I2 d! F6 M& e
/* Enable synchronization of RX and TX sections */
, D7 f' Y& a) Q4 \2 T& a& w- R; dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// D$ v# x; `. h F u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 w3 r: y( v& t' I: FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 n7 O& \- Z5 k, q* X( M4 Y' T
** Set the serializers, Currently only one serializer is set as* P8 S; G) R% E& t6 C& y7 S4 C
** transmitter and one serializer as receiver.3 M; H+ ^6 I( \1 k& p" j
*/
) R1 N1 k( r! a0 |# DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* P B v. ]; o6 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 V- e: M4 T( ~; i: t
** Configure the McASP pins 4 Y# R X# `% R$ F
** Input - Frame Sync, Clock and Serializer Rx
0 K7 |% I L. P$ I* }8 O9 _** Output - Serializer Tx is connected to the input of the codec ; [: \& `: M. x7 Z p
*/% Q" m w1 r3 T0 t. T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 S8 y9 u# Q+ ]) i/ r5 I1 f0 B
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. A- h! [' R# ] hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 Y( n4 C8 x5 c/ v% j4 J
| MCASP_PIN_ACLKX* T& D" S1 d! S" y! x) _+ w
| MCASP_PIN_AHCLKX
0 ?( [7 b9 i( ]' x+ N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% Y. ^( `# V0 j5 e. l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / Y0 U W/ f1 S1 h+ S, s
| MCASP_TX_CLKFAIL / k' C! N o3 v D2 b
| MCASP_TX_SYNCERROR- P7 m" g9 t+ A7 \8 [& _ J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( D, Y( e& I7 Q* O7 P
| MCASP_RX_CLKFAIL
7 |5 u4 N) t- o* \7 L8 w| MCASP_RX_SYNCERROR
; o8 T% w1 y& b* S$ _| MCASP_RX_OVERRUN);! W& z: R3 f" w1 O/ T' o* O
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
: p; W; e2 T0 m7 @! w2 xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% o# v; `2 @; H! y- ?+ ]McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: Z% m4 ^. n1 P. z# e/ @' YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 k+ ?9 e, O: w/ E8 IEDMA3_TRIG_MODE_EVENT);
% }0 O+ H7 J y% e+ {0 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # w) [; X f+ p) T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; K0 j1 x, m# f, S# ?4 E. qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- t! ~4 l' ~ ~" z8 G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
\+ O4 |, a( H7 E2 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. e* E2 g' m8 V; i( o! f! [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" Z/ A" c8 b5 I8 e3 Z. k* `% G( G2 EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); m. e/ u- l$ O2 P, b- t
} . ]( {; h$ K) t$ h! I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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