|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 y9 A5 m! m u9 `" d/ a
input mcasp_ahclkx,8 F& `& Y& P3 D8 g' a2 q7 E0 y
input mcasp_aclkx,3 G* X% o! f# b/ l, H% `6 ?0 Q
input axr0,
; v, } k% B f- }% t. g
) G; h+ a8 d8 n1 X4 ?output mcasp_afsr,7 t6 ~! J5 P9 m8 G
output mcasp_ahclkr,
# g( h. o" m# O, \0 \2 Y* uoutput mcasp_aclkr,. E" `) w& x+ A
output axr1," H0 z9 L$ M v: X3 w2 ?1 @/ z
assign mcasp_afsr = mcasp_afsx;+ \$ W3 x$ j K. }$ W, E
assign mcasp_aclkr = mcasp_aclkx;5 N) ~& u ]+ h1 b9 S3 P
assign mcasp_ahclkr = mcasp_ahclkx;
& N, G }7 R( Eassign axr1 = axr0;
3 i) j; c) d" f9 | f9 G1 f
9 i! u2 i: J: g! D: J, D* o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, e- R' z: `) f; l: _1 |1 astatic void McASPI2SConfigure(void)
/ c1 f' m9 A8 b' f, c( p) U{
7 Y( [, J1 V# P) Y( q. \& rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ u; S P) J# k3 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! C1 E6 C* s4 ^. U* D- P' n( v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( j' Q+ I I. X" hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* X' s, b R. s$ M; \' f' sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 |3 l ?. A, |! z4 x# P1 r9 y
MCASP_RX_MODE_DMA);
4 z! a# A8 x. o% r5 _7 `8 D( cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* _ O/ z( X: `# `( x8 lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 v2 K l" V, {, R0 v& f. }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ E- m; {4 R1 H# `( IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ Q( q9 F: c" |; dMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 w4 i; Z: u0 |, ]9 f* g4 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 o W7 g/ G# F: ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* n0 \' j$ w" }* }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 j: x% W+ [' s7 a: u0 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* b1 C3 F, c5 a. @! `0x00, 0xFF); /* configure the clock for transmitter */0 L: ?' Q9 e. e7 W( ~" Z) z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 H. }% v) v& c+ E+ p0 e1 b6 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : U8 O/ A0 s9 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% v0 I' Z) ~6 n0 {# G/ q9 @. F0x00, 0xFF);
9 o! I8 B, f2 r) U5 J8 C# J M
0 J& W* A( C: ~/* Enable synchronization of RX and TX sections */
( r, \) c4 M" tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( g) ^' h# t n( f9 q7 ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* ]8 P! k. x+ UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 i# X' A# |7 P
** Set the serializers, Currently only one serializer is set as& i6 u. @% q7 e
** transmitter and one serializer as receiver./ ^& D& t/ q1 J9 K3 a8 p
*/. ?8 h* o1 m" K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ J7 g& K& n( hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** D0 j" Y( _( X2 m# j N
** Configure the McASP pins 8 ?3 d. k5 Y! \; B3 G" d
** Input - Frame Sync, Clock and Serializer Rx
$ O6 }7 y: \+ C. _1 ?& |9 v** Output - Serializer Tx is connected to the input of the codec
4 M ~5 h4 i n7 S*/
% W3 x9 ]8 @* X0 C s$ NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ s! M- z# @# J/ s6 b1 ~! \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 b1 c8 P6 [9 A9 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 i$ R8 N L0 f7 b: g| MCASP_PIN_ACLKX- V$ t' C. L @* x$ ?6 q9 @
| MCASP_PIN_AHCLKX0 c! K2 x( z- t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. J, o+ U8 [/ B" Z% d1 x3 wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 A! w( J3 o0 g- S- a$ W| MCASP_TX_CLKFAIL
4 g: D! ^5 r$ T* f. d3 J, t| MCASP_TX_SYNCERROR( Z1 a; ~+ _3 Z% P! X, y3 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 }& K1 b. ]; z7 z5 q! g* d| MCASP_RX_CLKFAIL3 \+ [ H$ o/ Q6 W+ p o6 z" a
| MCASP_RX_SYNCERROR
6 o! l5 z* n/ B' n* O. h| MCASP_RX_OVERRUN); p3 L1 o7 ?- h( j& `- P
} static void I2SDataTxRxActivate(void)
7 B* i' \: z# O3 d8 p' k& V4 s9 j" Q{
& u4 n+ s" w: i* w. s/* Start the clocks */; g/ j/ ~5 A- V5 [4 w) i7 r/ X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! v4 t @* u2 D q- CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. Q8 a, c; S" n6 I% k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ }- Y E! A! ^4 l* A+ w/ I
EDMA3_TRIG_MODE_EVENT);% Z5 f2 d8 U) E; u( U5 R4 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - l5 }8 K, V& L% m8 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; b: t0 S. c$ KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( h' z- F7 X) w2 d; D `; x, c: e. O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) N7 c% M; k$ r' a8 j0 a4 A5 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: i- |" u7 m& s# A1 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, l! P( j1 b0 j* k6 B5 h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 ]2 c8 p2 e; h' d} " D2 A" z3 G4 Q4 \ ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 f. I# n9 ]- q: E% k |