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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 G0 x" c8 K: G! `input mcasp_ahclkx,9 ]) p0 o' ~+ f) M: A
input mcasp_aclkx,: |6 y( E+ a1 }3 R' W) R
input axr0," K- }5 w7 q0 {/ k# f- D2 I! V' w; d
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output mcasp_afsr,
) v% r" p' D8 D* H" @8 |output mcasp_ahclkr,
# c7 j' u6 \, Q6 i% S" a( Routput mcasp_aclkr,
* @& K& k) ]% W- m3 s0 y9 y6 poutput axr1,4 ]2 ]+ e _! `& C( f4 x
assign mcasp_afsr = mcasp_afsx;; _, o9 m& l% d# ~& z: j
assign mcasp_aclkr = mcasp_aclkx;% M3 X1 L3 B9 I( e
assign mcasp_ahclkr = mcasp_ahclkx;9 W- P% D+ l! F2 ~4 o' V
assign axr1 = axr0;
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S! _4 V* I' W' v M7 n0 w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 s, O( V. C/ Y$ z- o- Y0 lstatic void McASPI2SConfigure(void)( }1 h) a0 O5 K- @/ [
{
& }$ H" K1 D N6 `3 W' SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 g3 |* ` S x$ q. ]9 s6 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% i" _: V% M% I. [! Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( B# d$ z z, ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% R' w, ~: q) }% ?" ^1 Q* P' mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 F7 L \ m% s" s7 Y1 n
MCASP_RX_MODE_DMA);
4 ^5 ]3 L4 C% {6 mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( a- q% N0 t0 ]) ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& [* o3 B8 f2 f9 ~4 J2 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! F- O2 A D% P! |* j1 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* u" w2 f5 k1 k. g8 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 E+ j0 t1 n# r. N8 m! B oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! ?9 i# I; q" d# d7 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ r# b( t1 N) N$ q) D' [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 u' M# E" W% M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( f: B( a. j. P, m6 I) \+ Y0x00, 0xFF); /* configure the clock for transmitter */. b& ] s3 ?+ I3 m
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* B4 q) U; r/ w3 p8 l* B0 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; j3 J. }# d0 \7 A. qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 n/ ]$ P0 j& Z3 C0x00, 0xFF);& f0 i2 R- O& @5 X: N7 I
4 G6 @2 _& I1 H! u+ y/* Enable synchronization of RX and TX sections */ 5 }2 `% l, L; @2 M& h/ m2 x( d4 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
r2 \8 H) W+ q) A! nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& i+ V6 x2 f# s/ AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 ?" u! \- o( B _+ g2 {
** Set the serializers, Currently only one serializer is set as
- }) D4 y3 v- q, X! w, X6 c** transmitter and one serializer as receiver.0 Y; q1 R/ I z5 g! ]
*/
6 q7 ]+ q4 D8 l _- D. j% k# @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( \$ m: T; z: ?7 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 d: G2 O& w; C$ h% `" H** Configure the McASP pins
' _9 O+ h5 ^% H. {9 ?4 Z** Input - Frame Sync, Clock and Serializer Rx$ U; ]8 |8 A# Y% [5 k
** Output - Serializer Tx is connected to the input of the codec
% F3 R, w, c, w3 T) D8 M+ z: R$ T*/& S; X, Z, F9 K; x: `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! E" r" Z1 ~3 z& L( }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 @9 _4 D& r8 Q6 f0 a7 n2 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
b. t5 e6 j2 k) }| MCASP_PIN_ACLKX( g0 K& a" v, W4 y
| MCASP_PIN_AHCLKX
1 t8 L# ~8 ^& D" c- A% d5 ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. M" g8 I' F* |: ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& h* G2 a# i* L) c4 }0 [| MCASP_TX_CLKFAIL 9 X& c0 `5 x) F! I+ y
| MCASP_TX_SYNCERROR y+ m+ e& R0 J1 ~0 Y% U8 L, z1 P8 }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( U; x9 U) D5 [2 A9 D$ q$ K# F| MCASP_RX_CLKFAIL
1 T. D6 k6 F) w9 c! v7 \/ B' V| MCASP_RX_SYNCERROR
2 w( |4 y6 s! F| MCASP_RX_OVERRUN);1 K$ H4 L r% `% e* J% W1 O2 `
} static void I2SDataTxRxActivate(void)
9 N/ X0 U* \1 R& _5 x{
' N' x8 _( J8 v7 I- t3 f+ d3 A/* Start the clocks */
: q: q9 a$ f: ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 P4 v# T. a& [$ ~+ p) _! q% j* H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 Z* h- n6 K. N9 F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& C/ L2 r1 Z) u' T: U
EDMA3_TRIG_MODE_EVENT);
" G9 ?* A% j" w/ \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / N0 r9 m. V3 {$ {, B: Q) b) }# I# H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ U* n b: f. q* @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 {3 { o& y; Q( W' t9 G* X7 x5 yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( Y+ }" e6 @, r- E& w$ i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" g) p! E4 g4 S5 ?" h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ I6 q7 T( l+ D' _/ Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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