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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. Q( I, W+ F6 V7 S
input mcasp_ahclkx,
- {, a2 S& O/ @. Dinput mcasp_aclkx,2 H4 d8 i2 s8 d& E/ C
input axr0,
% r4 ~9 M% y; g. L+ R
5 t& m' i# r' F% v) `output mcasp_afsr,
) m: U1 M4 P# t( r- ^output mcasp_ahclkr,
3 p( ?( A+ K5 a3 O2 i( Voutput mcasp_aclkr,
( w F4 T3 K- S# Youtput axr1,
1 T% Y, k$ {' n+ h/ M assign mcasp_afsr = mcasp_afsx;
* o3 `* T$ P) X0 [6 \, aassign mcasp_aclkr = mcasp_aclkx;8 M; ^+ h& M0 P
assign mcasp_ahclkr = mcasp_ahclkx;& Q$ M Z6 O* s9 e
assign axr1 = axr0;
3 A& L2 V# u- [% K! Z
: c4 H: x% H0 X$ z) ~0 }1 {" L" L c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 T3 ~ b h" \" t7 Nstatic void McASPI2SConfigure(void)# E& F( M+ h, V' g! L8 Y; y" _
{
& A+ W( V% f. R" U1 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ^. Y! ]- i. d6 e/ ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 S0 R1 @' _/ D# V
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 t% Z+ d9 T# g4 c! `6 }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ~4 O' q a( r& [ d8 ^3 W# B% ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ?% w1 f2 D) s8 W5 YMCASP_RX_MODE_DMA);
% ?3 ^1 u+ W# O6 jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 [1 {5 `& s: n1 z, N& v0 k! G. e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& X5 j/ J& h& ?& ^0 W( }4 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 q( q9 [! J- s C3 D* `0 u( UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, e# c8 _. C% s0 ?& w) FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- z0 u7 [6 D6 |MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. @7 C7 Y& t1 V5 l- D, e9 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ o6 _5 }" h2 M0 s+ \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- Y$ a3 M3 j. @ o6 O$ _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ x% w8 O5 h( t3 I
0x00, 0xFF); /* configure the clock for transmitter */
4 d4 f5 [9 x' U8 oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 X$ E" W0 W' D' D. M8 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 s3 [# b, d9 W) e- [5 k- eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; Y( X) M; M, ^+ V. P$ f z0x00, 0xFF);
! x: I4 T1 f7 x6 ~- k
- H7 C# o, H" \/ Q W/* Enable synchronization of RX and TX sections */
$ q. X8 y$ {( c# x5 d$ dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 l e9 L& F) ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. K. p+ k3 b; B- u. X7 @. pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 [/ b/ s ^4 D4 P
** Set the serializers, Currently only one serializer is set as7 N# Y2 h6 ~' S1 W
** transmitter and one serializer as receiver.
8 i6 `2 c% ]2 d' Y! C*/
: M9 c5 i8 G/ ]* xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 Z8 Z+ c- V4 T6 c( R% h7 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. T3 e; {4 J1 M# c3 E% i( W
** Configure the McASP pins
3 {; ?& ~& |8 r+ I** Input - Frame Sync, Clock and Serializer Rx7 M8 X# C8 S+ n8 g5 n
** Output - Serializer Tx is connected to the input of the codec
" d) T4 r7 m. S( \# N*/
' r( F; u' _3 BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 b1 g s; K) b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 B/ d* m0 \5 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 y! j8 R0 V: M* S2 I; ^" X/ || MCASP_PIN_ACLKX
, _' C' L/ O1 e" X4 p; `| MCASP_PIN_AHCLKX$ M, c8 G! W9 j; g0 @; r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 ^3 D- C( S D0 m5 [0 m" E5 h5 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % L/ l' c/ H" s U4 _
| MCASP_TX_CLKFAIL - m8 z3 U$ i) ?% r/ g9 _1 x! C& \
| MCASP_TX_SYNCERROR
% {0 R9 e" _3 m9 I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 T2 z/ c' q: h' W, |( e) e& n
| MCASP_RX_CLKFAIL
* p5 I, x' L V. ?| MCASP_RX_SYNCERROR 5 j# O- S# q! H# M3 }
| MCASP_RX_OVERRUN);
1 b4 ?, Q; b K4 A3 u. Z} static void I2SDataTxRxActivate(void)+ E) K6 D3 J: |& n
{4 {: U5 j9 x# _( z" T
/* Start the clocks */
# I! O7 L# h2 x/ b# jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ p e( J8 Z6 b4 e& p& M% I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* A* W$ J$ H3 j' h5 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 h1 ]9 a& X, W6 n' S- D5 `& BEDMA3_TRIG_MODE_EVENT);! o% P4 f* P1 c! h( b# q/ f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - a3 i& S6 o1 s( F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 [7 u5 c2 K2 ?6 R# F$ J1 r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& Y. X" [/ t* [: PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' L$ }3 t! b/ c# G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, t; _' q* `4 O, G! kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ ]+ V' m# P5 K4 a r M. U% P; t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 L+ J% Y+ f; l4 W
}
1 F4 o" c. g' D2 R3 Z5 f/ G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " E S, B8 P9 x1 \* M
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