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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ b$ K; S$ D! z$ L: Y
input mcasp_ahclkx,8 J$ @! G( `$ m0 ~. o3 C( N
input mcasp_aclkx,. ` Q+ s- `3 U& k
input axr0,7 T; C6 h, m# X
& s; `8 |% x) w/ N* z. koutput mcasp_afsr,
/ ~- N3 Z5 {. C9 ?8 E$ Poutput mcasp_ahclkr,8 J5 T( f- _# A$ s
output mcasp_aclkr,
; [/ U' M% U9 l W& X: ~$ goutput axr1,# ~9 c! c3 j5 @: G! T
assign mcasp_afsr = mcasp_afsx;/ h; ?/ E8 @: m0 U2 u) p
assign mcasp_aclkr = mcasp_aclkx;
2 z$ x* v$ g" L( Sassign mcasp_ahclkr = mcasp_ahclkx;/ z. P0 S7 h) `7 q1 f. E) x O) ~
assign axr1 = axr0;
. A, | d( x0 k5 B( N
6 W, T! e! L/ F9 P. ?/ P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) v- C6 L! _% y1 |5 P& U
static void McASPI2SConfigure(void). x* g# E1 T0 J
{
' |* R; a* b8 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) h8 m- y$ r: e) M oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# u0 e! _4 g7 h o5 [. oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 _) h6 g, }2 Y7 H+ c* YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# ? e( X. M' a/ I' S% @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; e, A8 Q2 ?% O" q4 QMCASP_RX_MODE_DMA);- w) Y* k9 G6 a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 I) ]# t" @+ q; WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! Y. R5 R+ ]% ^8 x9 N) \6 J5 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& ^* |6 a* u4 A" Q% l" ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ W- B6 V7 R! R- t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : T: N7 k- i& D; @( P; }1 b. @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! W6 U& I0 ]$ i% Z; d# e2 P" ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% q+ M& i( e' Y! K( q( M$ pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' A1 W$ ^* U* p1 X* p. FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 Y2 s; ?5 X# z
0x00, 0xFF); /* configure the clock for transmitter */( ?6 s# Q( e- n6 c% ?: |% U+ K/ p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. `2 B# V# o1 a; V2 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* w; p7 O# r8 C; G/ r' p2 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& k: e/ Z; h3 C, A) n6 O! B
0x00, 0xFF);0 L5 Y3 I. @: A+ f
7 ^, k- V* I: O1 Q# `/* Enable synchronization of RX and TX sections */ ; p3 p7 A) M$ Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ ^! ~8 n! p- J+ ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% S3 z, O9 T6 o9 C v Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ Q$ z0 w3 M0 s# H
** Set the serializers, Currently only one serializer is set as
$ n3 o" S' m8 Q3 q7 T" B** transmitter and one serializer as receiver.6 J7 D5 I- P. i3 L
*/
) u# J* k/ k0 d. A$ J( E6 m8 MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( E/ O8 W* U3 V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, r! c" q% I& h6 w0 g# z L** Configure the McASP pins
4 D4 v5 v$ K4 N5 X** Input - Frame Sync, Clock and Serializer Rx) U" ~2 a/ q: r$ e! @7 l
** Output - Serializer Tx is connected to the input of the codec
6 Q5 G) A: r7 {' T*/( h2 j. L- ?# ]7 l1 r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% N5 o. X& a- }) n* u; l+ f" K. f/ B) s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ H* l% w: ?4 }7 V5 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 G, C. v6 O- z| MCASP_PIN_ACLKX
" z/ J8 v: T2 }& p% Q| MCASP_PIN_AHCLKX% J9 Y: l" o+ P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 t1 ~. a6 t5 Z: H6 N, h& w+ q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& Z% q% u0 w% m| MCASP_TX_CLKFAIL
& r, m+ K' S4 o z2 w. b| MCASP_TX_SYNCERROR
! ]' I F. h4 E5 q2 o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 n% s( O8 u0 @* e( j2 |0 ~* F* I| MCASP_RX_CLKFAIL
0 H4 ?- X% l c' g| MCASP_RX_SYNCERROR % \- j( o; z' |
| MCASP_RX_OVERRUN);
( a, F9 l/ c% k8 C* G1 g} static void I2SDataTxRxActivate(void)
9 G4 r3 ?. \% K8 w{' i# X% y2 ^/ X
/* Start the clocks */
: P" \ Q: e6 ]- n! D; OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 l. {) {1 \' e6 ?- @: o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ t5 a; g/ c$ t) i! N# E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 h" T& ]/ g4 [% U/ u- x* _/ O
EDMA3_TRIG_MODE_EVENT);
5 _! x1 _! h) zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ [2 _% D5 ~# [1 ^, ?1 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
d6 U5 h8 H0 } e. T( A4 z% \) ]0 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. u# Y$ e6 d5 M2 j# r# y, d* sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: F1 ^3 X1 y& g" Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: V1 D9 ?: ~# X+ R8 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 _; U& z, E# N: `5 C) N0 N. |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ S1 g' n E- R5 I6 \9 k1 o5 n} * K& [. l' Y. K1 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 \& G" G, t$ S+ r1 E+ b* d
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