MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
& \. A* G. E9 oinput axr0,
% @" }7 c, Z) a' _  i! `
( W. o. S$ i2 W) M0 goutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
$ r+ K' E( }, w% F6 d7 L9 S0 |$ S4 V" Ioutput axr1,

assign mcasp_afsr = mcasp_afsx;
! @, k5 Y: D4 P5 b6 `5 f) J3 U' {3 y/ ^assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
1 q8 ?3 U+ m9 `7 n+ Bassign axr1 = axr0;

( U6 x" b. u: {4 v6 w4 s! j3 {: }
& c2 [/ K% {. `# W

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

$ o  @/ j  a" m

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
  S( O; [5 z1 e) w; n$ SMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
0 S/ `2 \( ~* I5 q) \4 ?7 WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ^0 M# _& f. R# y2 R% p8 Y* N0 D, IMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# U  _6 V0 W& y5 A& d$ _3 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ x" [0 J* s9 ]1 v  d  _; a5 IMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 L* K6 ?+ |8 _4 U7 t" iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
  K% O, M7 r7 g4 r6 r) qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 Q) [+ |, R- \1 ~1 x9 `' _, z; @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 R$ N6 [& F# m. F9 mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" ?$ N" z1 e; L( C' E8 a0x00, 0xFF);

/* configure the clock for transmitter */
! z) a, w* [) Y0 j& W5 G2 TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* K1 P( m3 l( }- o( wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
$ k/ V5 Z6 V' r- M% G
* F# I3 n; A) U0 h/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 B/ j* O4 R3 V4 P6 {7 V( RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
7 G$ o; c: y, J$ P4 D, l+ ^** Set the serializers, Currently only one serializer is set as
6 x9 n  o+ |: O. B8 N9 {1 [** transmitter and one serializer as receiver.
2 f2 G2 g1 a0 b+ o*/
$ Q; }9 T& C  ^0 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 m8 u0 j8 \' [2 ~7 V/ ]$ i: T2 FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
, Z% _2 \3 x( I+ l/ b** Configure the McASP pins
/ d2 p1 l4 G; v( Z! B** Input - Frame Sync, Clock and Serializer Rx
- v; B8 L( b5 A* }1 i** Output - Serializer Tx is connected to the input of the codec
- l0 R* a+ t" a% v  A3 Y5 a*/
( N1 M, P; ?; B3 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! k( a0 _9 w& z" r1 r: KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
" |7 a( S2 g7 w" e* k| MCASP_PIN_AHCLKX
" U4 w/ u4 G, Z| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
: @* \  ~1 U- Z9 @| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* q+ L* ]4 A* u2 }' O: _| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
6 H  x: c0 ^( |7 m% @/ B7 L| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
" R/ h2 w, G- x5 i{
/* Start the clocks */
. s2 @5 R6 }. g- d  vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) e! z0 i8 m' b& b; ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
$ J% W% x1 l# m1 j) J! KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 z7 P! g) M0 l: f$ _EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
6 d- Z  s3 H: Q5 s6 hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
" m8 G( Q. c. g; s6 l# U# @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
  ?# d3 x9 B/ L# M* A5 J2 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

  W) V/ M" Q2 P  w

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.