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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 ]5 ]( D0 C, K" b9 }( W2 Binput mcasp_ahclkx,' @# i* E% u/ R" N
input mcasp_aclkx,
9 k& t( M2 b( d( p/ n( M: pinput axr0,6 k" W" n" c! c |$ Y* G2 c
9 X6 a8 C9 @6 d- e! w/ ^
output mcasp_afsr,9 P8 Y2 U7 o" r8 R
output mcasp_ahclkr,7 b0 e7 E* R( L3 j
output mcasp_aclkr,
* I4 C2 u' N( ^, R8 [6 h f2 E- |output axr1,+ N7 Y8 U9 y6 S- c7 w
assign mcasp_afsr = mcasp_afsx;: V' {( Z6 b1 k" |. S# W
assign mcasp_aclkr = mcasp_aclkx;
6 w8 m9 v& b8 ^( K2 \assign mcasp_ahclkr = mcasp_ahclkx;; ]* E$ T( I0 {
assign axr1 = axr0; I6 ?3 Q, e& n1 G/ ]
& M4 E- R C) |2 R9 G+ o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , }* I, S k* O0 m" C8 e8 r" i
static void McASPI2SConfigure(void)
% B6 W, a8 M; B{
, f9 y# `4 ~9 G- _7 ^' w# Y) TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% O4 o7 e4 {% v0 N! W' uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# S# j1 g9 }& P6 x! N( C, |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 v4 _% M8 Q3 f; Q5 O7 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 E# Q, R. N6 N% ^ L, v; DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' k3 ^3 o% z% L; R3 NMCASP_RX_MODE_DMA);+ w- P8 ?6 U; x: S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) z( D% n4 r# Y$ S% gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 Q8 C: }" d. V, _2 NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 _) N* P& D* d, d+ OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ F2 G3 t( J: t! p, m$ g7 j4 c; @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 C5 z& U( l0 l4 O/ pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 M8 Q2 i M1 ]* Q# }8 N+ vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! C0 j" V1 A5 q* u4 E7 M/ B" `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - A! ]9 `, z0 K6 R. E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( C5 S* s/ M, M& P! t8 E( H
0x00, 0xFF); /* configure the clock for transmitter */
! @) g9 g* _. Y- K7 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
o1 L! Y- _( ^$ {5 L; U: ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 ^( h: N+ f0 o' j5 \. pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* R* \4 p6 p, K' o) V9 r2 ?0x00, 0xFF);
3 R' m' f6 S0 z0 U
6 D/ i5 X# t; S- ?9 \# m( w/* Enable synchronization of RX and TX sections */
" J. }7 | Q5 D* V' WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 A9 p1 Y7 O1 [* c- q |: D! B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 l, D+ S( a! c1 w. n; u6 g
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ A9 q& t5 L+ s6 I6 v
** Set the serializers, Currently only one serializer is set as
0 X. C! C# R6 h8 d5 B5 U6 a** transmitter and one serializer as receiver.
6 h% [' D3 Z- Y6 V, Q4 g) [*/. W, Z0 p0 b5 l% Z5 [; {# J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* j3 x! m! O$ |; LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( f- q7 J* T' E! O# V7 L3 ]** Configure the McASP pins 0 c# X6 d7 b0 _
** Input - Frame Sync, Clock and Serializer Rx
" O K, _- d Y K/ |# j** Output - Serializer Tx is connected to the input of the codec ' ^% ^, G- i5 ?+ }9 b* a
*/
4 m* e% K$ [! D0 kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 O& b# z$ h q/ k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: e/ V4 i u/ i: t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 o3 q9 p2 Q& ~
| MCASP_PIN_ACLKX
2 m8 N3 D" }: g9 }| MCASP_PIN_AHCLKX
: z: K2 C {8 s: }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: O. Y, M' }$ Z; R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 H2 h0 p- L# i" U$ w
| MCASP_TX_CLKFAIL ) E6 e3 m, F6 j# s
| MCASP_TX_SYNCERROR6 s3 R' o O9 h* f; s' B5 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) U3 Y2 v, }1 v| MCASP_RX_CLKFAIL
- B6 W) v0 l5 W5 v| MCASP_RX_SYNCERROR " N2 f, n2 T) { H, A% U
| MCASP_RX_OVERRUN);% u0 v' M; A5 v$ v+ M: Z
} static void I2SDataTxRxActivate(void)
, I; c6 `9 ` G% T3 _" @8 b{2 m$ ?5 E L6 w* G7 j
/* Start the clocks */
# l4 y. X4 x4 {* _; |- ^: _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' \9 n8 \5 _% ^; |9 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' C+ P( Y1 Q" G" K7 K) O2 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# S7 o, ~$ Q: E6 J/ T
EDMA3_TRIG_MODE_EVENT);
( Z. ]( f( y: g% o6 @' ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# |" \* h2 ]3 q9 D+ H5 a0 h7 \/ sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 u) [2 q8 E% dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! Q9 c* e) K! O9 p& g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 C2 ^; ]; J5 B' Y; o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' S7 [# K; E* Z) ?. R5 @6 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& |1 h$ w. s6 o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 ` ]( T- X- v" q4 u6 q4 h} + J4 p1 R) \" n% ~- h$ C( C& e! v! Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % U6 \% I( K3 d9 t5 p' y
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