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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," c2 m6 o, C. U% H
input mcasp_ahclkx,
- l: E5 O: H" B1 \* }8 Dinput mcasp_aclkx,
0 j* X9 j# e/ U6 P! S+ vinput axr0,5 s9 u. f9 z+ g7 n2 O6 h
& p# |, h5 @: D& _4 R
output mcasp_afsr,
+ r0 @. z# e: n9 Moutput mcasp_ahclkr,
9 f7 l/ z5 ?, Q- R/ R; foutput mcasp_aclkr,
0 O9 S6 x4 g/ Z- P- \/ {output axr1,
( a- r6 X+ ~1 X8 c H1 C! k assign mcasp_afsr = mcasp_afsx;* u: z4 \5 t* w( Y* {0 P
assign mcasp_aclkr = mcasp_aclkx;! @- \! q) t' u, o8 l4 E# d
assign mcasp_ahclkr = mcasp_ahclkx;
! E. \5 F- @0 e# n8 Qassign axr1 = axr0;
# L8 k# x3 ]7 n7 F* N5 c
1 m2 @/ B8 K+ ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 e; j& h" A" z4 m2 Q
static void McASPI2SConfigure(void)8 M4 n4 c9 b, {9 I0 j/ w
{/ U; t: q- u- @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- s) M2 s0 X& _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 Y9 u8 S/ l) l/ {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! x2 A) B- `( m$ _8 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ r$ C( D9 Z( j) WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; a2 T6 z/ `! ^; b
MCASP_RX_MODE_DMA);
8 R9 Q$ L& r d3 p, |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
a2 C- A- r3 t0 SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) r! k) o: O `; e2 E0 p: aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 }* f* A1 @- X& k5 m' VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: W* q7 ~8 F0 C9 \0 B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 z' G4 @2 G+ k) R4 L4 M- t3 F; @& J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 y2 O/ G! b: `# s5 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& | \ t; E1 F( u+ T& b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 U9 {0 v: A* u4 E0 D, JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 I$ o. Y$ G+ ?; t0x00, 0xFF); /* configure the clock for transmitter */
' C* e5 m& F% j5 K# T7 `: V" q! NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* R. i. C" ]; L1 ~/ T( [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . \. o" p$ i* _$ F* i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. r" H) r4 i I f! R0x00, 0xFF);, z) j+ l' S# v0 H2 C0 x% R5 v
. A; e, X l, u- o! l8 `) K5 }/* Enable synchronization of RX and TX sections */
+ {7 r- A% T) P1 qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ C5 |1 q# L3 t* U# j! s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 N! U, x) |0 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% f2 U" P! x" p6 c/ f** Set the serializers, Currently only one serializer is set as* ]: v# V1 l7 `; S, q
** transmitter and one serializer as receiver.+ c! `5 n. \' p8 Q! p2 A% V
*/6 Y/ `/ Z$ B ^/ X9 F. S: B8 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 f- I1 K2 ^% P0 z2 }& N4 M/ z, pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# a( j" w: U4 M, @: g5 E; k** Configure the McASP pins . k, C2 G1 Y( g
** Input - Frame Sync, Clock and Serializer Rx; H- L) W T7 U
** Output - Serializer Tx is connected to the input of the codec 9 [! P* [$ u$ G. R/ u5 O& G
*/2 }+ W! N; |7 _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' w9 ^& }# j( pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 G3 ^8 S" g/ y8 B, y6 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ _3 P; j0 J- K5 j' U
| MCASP_PIN_ACLKX1 w0 b9 c+ b- E( x c
| MCASP_PIN_AHCLKX& F* j3 u/ E, P. `* W6 B2 m( b2 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# ]0 S" A/ N" W! z7 [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # P4 p. \+ B+ T) B
| MCASP_TX_CLKFAIL , \- w: {- d' Q' x5 Y7 j
| MCASP_TX_SYNCERROR
' u+ H2 N- F1 m6 }# [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: m' J* V, ~) t4 t7 S7 v( Y| MCASP_RX_CLKFAIL
, S) r8 R" B; \" V2 O" i* O' Y" a| MCASP_RX_SYNCERROR
/ _" @, e2 @. E: n. m5 j| MCASP_RX_OVERRUN);
& Q" q. O- k, y} static void I2SDataTxRxActivate(void)
$ E% f) O' ]+ r' _, B{: r" x# k G; h- C% [
/* Start the clocks */ W9 i2 P- D( z* G- f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 a; f6 [# ^6 ~) @4 |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( ?8 l' p# k# t n) ~. }- rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 \6 ]) ?. S, e+ [0 `& t8 W
EDMA3_TRIG_MODE_EVENT);
' B. K! ?4 ~4 R! z: WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, ]- b+ E( t, Y* U2 YEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& ^& G+ w# n$ E& z. WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 q# X8 r$ n# Q5 s D: ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 V: O+ x( a$ V7 \while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 g" a* s, {% K6 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 G3 a) ]! f& r( b5 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 `/ \* w: `' C
} 2 T2 i2 Z/ R6 ^1 W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + B/ Q$ D# o# C4 c9 H4 G
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