|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 t6 A6 H/ v( D. t6 {
input mcasp_ahclkx,
* e3 O9 g- W# o; jinput mcasp_aclkx,
( n' M0 p6 i3 D2 `( W pinput axr0,/ p1 P E5 W4 |+ K
# Z( W: }, W" f' g0 eoutput mcasp_afsr,8 K" c) c P7 K4 I
output mcasp_ahclkr,
5 O9 o/ h$ e- Youtput mcasp_aclkr,
/ D& c! p3 s2 _% O7 ~! z0 X- l# Voutput axr1,
7 P# w+ L# s# E0 d2 H8 E assign mcasp_afsr = mcasp_afsx;
A; p4 |2 H4 Iassign mcasp_aclkr = mcasp_aclkx;
% a, A p. `- [' H$ hassign mcasp_ahclkr = mcasp_ahclkx;7 g) j4 |/ X# [2 }3 I8 z
assign axr1 = axr0;
" G: P' O! Y$ H5 k7 W
4 V1 Z& [# @2 B9 [) G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" {. b& N0 W; Y2 |' [, {0 w7 mstatic void McASPI2SConfigure(void), U0 Z3 s4 ^; ]$ o, B
{
3 [. ?3 P7 v) Z; z, e0 pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ s1 Y+ |3 X/ C8 x2 UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* Y7 n) q2 A6 p2 ~# L, o6 D( z( Z3 w7 Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: H9 a4 W" g0 q1 ]- lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// h0 j8 e" n# {' \/ W# ] H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; R& v. E- q' L0 \6 bMCASP_RX_MODE_DMA);; S4 X0 K$ F1 v! }0 R, v- |! J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ M$ B( B( ~+ I& ?$ U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* E( {& ?2 x7 a4 g- w3 L4 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / D- z- N8 Y- n2 W' y5 M( x4 C& g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# W' T) s8 G" v- J8 c- Q0 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( N( N @2 [& {6 ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- O. M: \% O( l5 M% i& `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, ]" V; l2 p& g) V+ E* n4 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 `$ C B7 Y4 V$ D$ B/ d% ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 y; z, u. X9 |1 v# j, q& V Y0x00, 0xFF); /* configure the clock for transmitter */% J1 r# a$ Z9 v& c6 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- Z1 C# ^- p- ]" T% \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) q6 }6 y6 N" H* y5 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 @6 B) p! Z, V4 v& C+ S8 O0x00, 0xFF);
- I- A' l; P& Q! Y& l5 n6 Q) h7 V6 G* D
/* Enable synchronization of RX and TX sections */ + j& `3 t' {2 Z, I6 a: W% M, D6 {$ U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ Z8 y+ j2 ^# ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) R; w$ M& j0 Q/ `3 V0 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- o3 s& H1 X8 L; y9 D- K% Y. t: i** Set the serializers, Currently only one serializer is set as
& ~% b$ u; J3 i3 N. D. R1 u** transmitter and one serializer as receiver.
$ {4 K* g* I4 F+ D7 A2 h( Z ?*/" U7 `# B& [2 P. \7 d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 r' `- g% z* a9 E: OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, L# k) L$ { \8 [0 l
** Configure the McASP pins 5 i" A" r. W: P8 b
** Input - Frame Sync, Clock and Serializer Rx! K0 }/ c; f+ w2 _0 T+ Q" f
** Output - Serializer Tx is connected to the input of the codec / W9 P/ ~% E- W; M5 a5 M
*/- W5 @) b% N* r& Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 Q# J# I/ _. t% H. NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
D: A# W: Q2 f& {: A uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 X' R# a6 \. O5 l6 r
| MCASP_PIN_ACLKX
1 y/ R5 l+ o+ l$ f| MCASP_PIN_AHCLKX" j* y* N4 ^( Y8 p1 P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ l% A. O2 F: b& n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! z9 r* x6 [/ V8 j| MCASP_TX_CLKFAIL
( [2 U3 L9 t u' ^| MCASP_TX_SYNCERROR
) M6 {. r- e6 I0 E; ~1 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : K g9 J3 S7 k3 q
| MCASP_RX_CLKFAIL
9 @9 D: Y: a& b$ M S5 U; D8 A| MCASP_RX_SYNCERROR w+ O1 {. Y" F- Z5 {
| MCASP_RX_OVERRUN);/ y8 C# I' y" V8 z+ ]# g$ o
} static void I2SDataTxRxActivate(void)9 h6 |# T- t+ Q9 i
{( `8 j* y6 s$ ^, s8 K
/* Start the clocks */
5 v& v7 h; I: i' n' x; H0 AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& T* o' K0 X: w2 V" _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; y' k& }, @1 p. }* sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 d4 ^. @- f2 j3 R9 ]* D- }# wEDMA3_TRIG_MODE_EVENT);
# y. j% B% P2 b* }2 v8 c- Q4 G; qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % U6 b. Y5 F! m+ h
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% H9 _& o) J" ^- J! |: C E+ @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 \8 N& j! ?3 O7 l* ~$ ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ _8 w& e8 Z+ n* ~ L+ Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 Q# Y, K# V- { {: ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 f1 W. X, A# \( `) }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ g$ x5 T. R, G: J1 A0 X& _! Y/ l} ) O8 P0 ~+ v5 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% V* s1 v. k& p |