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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 e8 A0 r& r2 P. L, J8 ?5 xinput mcasp_ahclkx,# O" [* O: n3 k6 z+ ]
input mcasp_aclkx,
4 T2 e# ~+ V! d2 x5 ^ u5 w0 Tinput axr0,1 ]/ H; ?; w" i4 i; ?; i; i/ p
5 f) O) E( x- woutput mcasp_afsr,
( _ |' L! b- T) Q" }! H! ]output mcasp_ahclkr,$ t: z0 ~) U- g/ B' u. b- h
output mcasp_aclkr,( g" H# s( Q! P* l; X5 Y' C
output axr1,. c7 w# l& n) Q0 [
assign mcasp_afsr = mcasp_afsx;. ^9 u3 u- ~0 s" r$ R5 k0 b3 G
assign mcasp_aclkr = mcasp_aclkx;$ {* u2 Z; c! W- \4 n
assign mcasp_ahclkr = mcasp_ahclkx;
% c+ q6 a% \: ]. A3 K5 U, q% @" b$ Tassign axr1 = axr0;
! n& \3 N. l) ?0 W, o6 D2 ~ z ~+ `" H3 b0 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) t) g" U, l z+ s$ V1 u4 z1 ^
static void McASPI2SConfigure(void)
4 ]/ i. b' o% r{
) s# \7 g6 A" V5 I; ^9 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 A0 B& O% g PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. ?8 g* ^* N9 i3 D% S1 J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; g, O+ Z0 t: P- d( sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ ~7 V/ D7 U; e6 m1 j* [0 xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% z c* T7 W1 M' r! m& UMCASP_RX_MODE_DMA);$ H# _/ ]6 b. ?0 L. R& ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ s& d1 H# z: W2 p5 C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) q5 ]1 J6 P4 n9 N' `- b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & D# O, j* V, M% a3 q- c0 [2 {) Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' b/ }/ |* I* F y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
N. Q( |$ V6 n1 u8 w/ A' [2 uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- K4 t7 T, M# a% C( Y! D. tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 p2 s+ E2 _* C6 Q6 O% k) m( L3 U6 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 V$ f' s: B) b* D* v: ]0 {( V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 E. o) j! q1 m: Y3 H9 Z
0x00, 0xFF); /* configure the clock for transmitter */
7 I% L1 x9 v/ p3 C) | W/ [+ I1 P$ gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 Q4 W+ L7 ~: y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + S5 O$ l# l7 E6 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 M/ e3 V0 H9 G0x00, 0xFF);
$ D( u/ n1 X U" F- G! [1 q: M s3 _- K3 j
/* Enable synchronization of RX and TX sections */
5 r# B& U9 l0 ~/ gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) B$ ~ Z0 u+ a4 H+ O9 p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 b% d5 q2 o- T! \) r3 R6 b9 y1 e
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' O. t- y# e! X# L' I; b** Set the serializers, Currently only one serializer is set as
. z2 o, ]: h( ]* i+ D* D3 i# S# a# I** transmitter and one serializer as receiver.% v) E$ i5 @) B8 y2 U3 ]+ z4 v$ S9 }
*/
0 q: r8 ~9 c" {- c7 B% v( wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, \1 } {- X( m7 g: C/ }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" Q4 L: ~7 S+ e** Configure the McASP pins ( Z2 ^* [9 j8 J) O2 v1 E
** Input - Frame Sync, Clock and Serializer Rx6 }) L% @$ q2 J
** Output - Serializer Tx is connected to the input of the codec 0 n, z8 i" K1 i# H' S, x
*/0 ~1 _9 a7 e7 m6 {6 y/ T! a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 ~2 }' i& D* @4 G( m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 V# \) W. a" Y9 I H2 r H0 c% |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
f3 c7 D7 X2 Q: n| MCASP_PIN_ACLKX
8 z' x, {6 a+ r, X| MCASP_PIN_AHCLKX
+ i# d2 }/ Z% v2 Y. s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 B/ u5 K' ]( m! o3 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 _+ y0 u+ L G) }
| MCASP_TX_CLKFAIL - O8 n- z6 ^3 U, \- @) y
| MCASP_TX_SYNCERROR$ M \4 _+ l1 _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR O; c$ | [( j- l: t, r
| MCASP_RX_CLKFAIL( w3 q7 a/ r# o3 D
| MCASP_RX_SYNCERROR $ s# |6 w3 A% V& i- U
| MCASP_RX_OVERRUN);
" X! T) C( Q5 i8 V2 u! c, `} static void I2SDataTxRxActivate(void)8 X' @# \& D3 l
{
) h/ o! K6 n& _* E4 C, i9 w/* Start the clocks */
6 ?" D1 n# X5 ~; ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, X& `* x* q: g& v
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, s3 @) t" t/ i/ V, \9 ]+ O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 ~# _3 n$ N* E, n6 G2 @
EDMA3_TRIG_MODE_EVENT);
( @& f, m6 m! \1 e! \& K9 M# @$ YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ Q/ R2 c0 s- ~- J# i/ JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' x7 A# v: T( n# a) z+ BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; w- R- Y6 k9 r$ {! n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 K: O8 F% y& t |+ O" l% R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 H8 N3 y+ m# I/ Z# K: [8 c4 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 g, g# n$ j+ j. e! N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# H8 b) m% a7 n) t& R) [! Q
}
: P) g( W: w) U, Z N) y2 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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