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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ F: L! a8 ~) c! v' T2 t% y5 y2 pinput mcasp_ahclkx,2 J; b' ?5 d/ A4 M# k4 ~7 \" n+ ?
input mcasp_aclkx,) O9 F% A G1 r; Z2 k
input axr0,9 n' U2 e7 T9 _' D3 ?
) _( M7 {# z% H" E+ Woutput mcasp_afsr,
' A7 ^. b' \- T+ Toutput mcasp_ahclkr,
- _9 r( t, u uoutput mcasp_aclkr,
8 O5 s5 t7 ]) ] |output axr1,
5 H0 P9 H8 O( V5 ` assign mcasp_afsr = mcasp_afsx;
: E* M2 g/ ?5 yassign mcasp_aclkr = mcasp_aclkx;
* J' t0 e1 q8 n! u0 aassign mcasp_ahclkr = mcasp_ahclkx;4 D, `& z5 r9 S$ \9 ^9 n
assign axr1 = axr0;
- a3 F. d2 T' e' ^
# j. |: {+ \" c8 s6 P1 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( C. ]; B7 X( n1 D/ a& ]8 ~
static void McASPI2SConfigure(void), K+ u8 L2 C; Z% k. g. g
{
$ D5 W0 J* V- w( ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ e% C: `' G3 |& g0 c. i7 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ `5 Q9 Y/ ~; ^7 X2 IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 ?0 O4 f2 {9 Y9 ] V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 p9 `) ~, }1 W" fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ d, y/ I! ?1 D5 k5 \, }MCASP_RX_MODE_DMA);
+ K, w; `4 l8 A) lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 q2 l& m8 c4 ^* cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( D, x0 z' U7 L6 @' _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& x/ Z. p9 j' x: JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# s7 N' A- s5 A( `" m4 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; g$ R* G. c/ G9 L7 g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ `. T# t. F: M4 t0 O1 ]: fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* n$ S. L3 M8 _8 l& s: QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 6 q+ M/ a$ e- |+ [! v) G5 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 B; }) k2 w3 a$ }
0x00, 0xFF); /* configure the clock for transmitter */
' o" p6 l8 h! l. x/ cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! G$ B6 d2 S7 s6 C! \1 `1 k2 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& X+ u6 h! V7 _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 C4 z9 Y. u# p( E3 m9 Y
0x00, 0xFF);' s, V7 N, s. M, `. _- C6 ^
6 B) u+ l" s4 ^& }. a, [
/* Enable synchronization of RX and TX sections */ 7 M0 O& z% t: _) |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 L. d" J' L% C9 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 q8 q/ M# f0 C C, ~McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, d) a/ v+ u4 e, P** Set the serializers, Currently only one serializer is set as$ D$ G) Z( h( z( O: R5 p- U
** transmitter and one serializer as receiver.9 i# _ W9 r+ y* ~
*/- v, f) f" g' P& P# \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: L6 w' S6 F% _" Z& t! ?# {% p- a6 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* w! C8 u6 B1 U6 ~& A, a- a, P
** Configure the McASP pins 5 I/ a9 Z" A3 }
** Input - Frame Sync, Clock and Serializer Rx4 @# j! C- Y% d* w6 H" o# \
** Output - Serializer Tx is connected to the input of the codec
% [) S. E: d9 \- W% V*/5 _0 V4 M0 j6 f9 O& Y) M) n+ i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) b! \0 U8 m q( S, v; u* |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ J7 b( v. o7 M/ `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! N) Y9 ]4 G- f1 n+ R
| MCASP_PIN_ACLKX
( i* {9 ]6 p/ ]4 ]2 w) s| MCASP_PIN_AHCLKX
; b( V* h1 f6 u- s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 P, P& u, N% z3 F7 W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & V. C0 D w. o5 ~# l6 V4 r2 P0 U
| MCASP_TX_CLKFAIL & `6 _$ ]9 h: t0 [4 v" H% u3 ~+ }
| MCASP_TX_SYNCERROR
. m0 G( }4 q, y: t8 _2 @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : }# _0 F7 Q2 q: Q6 V8 G
| MCASP_RX_CLKFAIL; R2 y) }- x2 B; X$ h
| MCASP_RX_SYNCERROR
2 K/ ~" n( b& v8 P| MCASP_RX_OVERRUN);1 O9 c" A. c1 y; y+ U
} static void I2SDataTxRxActivate(void)$ E; g* ~/ h! N! R5 z
{
. C; d; n) k) k' p( Z/* Start the clocks */
7 c! C' _$ W4 ~: D/ _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 @# G3 C2 U( {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 t) h3 o8 F! {7 E: C* X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; j* L2 x+ o' dEDMA3_TRIG_MODE_EVENT);
/ V7 }6 r! o+ N8 m8 r. oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / d" c" ?1 k" z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- P1 z6 }; z" N4 ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 }% M, u* c( y3 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 j' z3 {) D$ `: x5 ~/ p: b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ e9 ^. d2 `; C8 n5 C! x/ E7 CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# R+ Y' ?* ]# K8 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- x: V5 X2 t2 V1 b5 M: v2 P+ f. t, z9 Y}
: c7 |: S! [' g3 S. L3 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
& c2 R- I# a, v+ ~# h |