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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' Z7 H* z4 {, oinput mcasp_ahclkx,, K8 v: X1 S0 ^& i" P4 ^
input mcasp_aclkx,
8 \. Y5 m; S0 | p" W8 E6 Kinput axr0,
& R( e; x+ G3 J2 m/ X
! ?0 C/ E3 U6 N, d. z% ^5 K7 qoutput mcasp_afsr,# P+ J: B8 ]! r1 k- E3 y; c7 M
output mcasp_ahclkr,
; k" m5 F- w) toutput mcasp_aclkr,5 `& t' C+ V- V
output axr1,1 a4 ^7 s, ]2 p0 Q0 ]
assign mcasp_afsr = mcasp_afsx;
" j7 B$ N1 i) j4 n/ Nassign mcasp_aclkr = mcasp_aclkx;6 I7 P- w, z9 \: q
assign mcasp_ahclkr = mcasp_ahclkx;$ O7 w4 j8 Y9 U0 f
assign axr1 = axr0; & ~ c6 A) X5 f
) x, z2 F: m+ ^! ^. N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* V1 S- U7 P. m& s, lstatic void McASPI2SConfigure(void). b# g9 k% q( I8 ~2 [
{; T5 y* m V r5 \6 ?" {5 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 j: J# l7 s) c) \% \ z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
m5 d5 m M ~" j4 L8 K9 t3 i! yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); \- c' |. s/ @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" m" u' {. y0 K U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( r# X6 D* J0 r' T" T& q. {; E
MCASP_RX_MODE_DMA);
3 R& V& A' V% N2 x3 M+ H4 ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* I! S3 @& f+ b& m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ a" ^ V5 a1 T. v2 ?: f& F0 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- Y# x5 l& v) C$ r+ M* mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" K S4 t% r8 d- Z7 t$ i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 ]8 P; m9 p' X: \' {6 p3 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) D0 k. g+ M1 H/ p1 H) z( xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, B* n2 P: d4 K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, D% Z( m1 h- S0 D* IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 R2 ~* S0 l1 O# h! d
0x00, 0xFF); /* configure the clock for transmitter */) S W1 m7 X+ s7 t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& F3 @) y" Q: y- sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% V+ ]/ P8 [ U+ fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) q" r7 l- i; e, M
0x00, 0xFF);
Y; K1 M6 ^: I; f2 Z
' ], P9 s; d9 `, y/* Enable synchronization of RX and TX sections */ N2 P5 @' n6 t' o' H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ i% V" @- d+ _( HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 ^1 O# s% E1 V/ f( A. G& |$ {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" M7 u4 ]( Y6 t. A2 G
** Set the serializers, Currently only one serializer is set as
& ]% p* [; H9 g' Z0 ~9 o4 s" d** transmitter and one serializer as receiver.+ ?; e% M5 a3 I9 D: `# b! X6 j: M
*/
; [' R; i' \2 d6 ^4 F+ xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- y9 b9 x8 ?/ I' ]+ eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: |( a% C; g# A$ u* J/ K* h) F
** Configure the McASP pins
5 t4 `* R# {- l% x5 @** Input - Frame Sync, Clock and Serializer Rx9 Y% S' r8 x. A
** Output - Serializer Tx is connected to the input of the codec 0 u. v. l6 B& ~# |- P
*/
8 H9 a3 n: F8 E+ v6 N5 ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% s; e, K9 A' q2 U) @; @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 o" p+ A$ k, O' }- Y0 |7 t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 n e# X# B7 _( j- I* _% P; @$ r' p
| MCASP_PIN_ACLKX/ v4 }& \2 Y% W
| MCASP_PIN_AHCLKX
4 ?8 s- S1 T$ D9 l/ k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& }: q: ~/ K4 b& w* S( L3 [' AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( H+ _6 E2 Q$ G( o% W$ J) a
| MCASP_TX_CLKFAIL
9 _" C+ Y; x! e4 c+ j% p" D| MCASP_TX_SYNCERROR+ J) U6 @' i7 |8 Z3 H7 _& F
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # a# m' I; A/ o# w$ q
| MCASP_RX_CLKFAIL/ F! h( q6 C2 Y
| MCASP_RX_SYNCERROR q( Z, d- r% z4 \# E8 f6 M3 d3 S
| MCASP_RX_OVERRUN);$ N3 h% V; b! C. L
} static void I2SDataTxRxActivate(void)
s! X/ P' O1 J! l6 j+ X{; b, Y, h" u7 l& O @
/* Start the clocks */1 a0 g9 c$ t$ E) S6 B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- g' x4 X$ v* M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ V1 m l' i- L9 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ [& N h3 Z6 N) v2 OEDMA3_TRIG_MODE_EVENT);( F) r1 `( v9 S+ [. D2 F% S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 E4 E1 L" f q E6 d+ @1 j* bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. [ y# _: \5 i% EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ i2 E- E( s4 _1 y" O" ?- C, FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, W! Z [2 F' V# `6 @4 j. {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) A) t+ s- ~8 v- `8 X# {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' {/ j- N+ A6 c+ U* A9 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS); }( |- d* A9 k/ `0 A& a4 y. t
} / n* V- \3 Z' S1 G/ E4 `$ v5 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * [* {% s" j: b
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