|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 w6 n/ t8 _ o! e( {
input mcasp_ahclkx,! Q4 m0 v2 q( r2 g6 M0 q
input mcasp_aclkx, P+ L5 W# `& B- m9 P
input axr0,
" J$ h& w+ @, e; C
5 p2 k- n% ?* voutput mcasp_afsr,
$ C2 [, _6 K% `' S& {output mcasp_ahclkr,
. k% s* W( D' a Z. xoutput mcasp_aclkr,
+ ]- J1 x' q' W- v/ p6 Y3 s9 G; E6 Moutput axr1,
, ?/ c( J1 \/ U( N+ Z, Z assign mcasp_afsr = mcasp_afsx;
9 f l& m$ v0 s) j6 _assign mcasp_aclkr = mcasp_aclkx;
1 ^. g8 a7 O' o" Aassign mcasp_ahclkr = mcasp_ahclkx;3 K7 L5 X! u4 o' w2 y3 U0 y0 r
assign axr1 = axr0;
5 W' k$ ?/ m7 X/ G6 C0 k+ D2 k2 i$ ]% L9 \9 m3 `* Z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- T0 U$ z9 f0 K) ?% X- @static void McASPI2SConfigure(void)/ T! L: _( N7 ]0 p2 f- U& ~
{- Q$ Z. b8 D# c1 d2 n7 ?+ S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" N4 g4 N: m, e' x: ?8 I- k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% k0 h5 Y h) T8 [8 K. |+ b( F) Y' a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 \: Z3 P9 }) x# \9 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& B; C/ z5 ]) q5 _; k$ T; V+ S" e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' C* c; x" F u) zMCASP_RX_MODE_DMA);; u/ P: j, t! ~/ d# ?+ ~! I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: U, V9 }4 }$ G& }7 D' X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" a" D! Q2 d# YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) i$ D6 Y# u' U6 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 T, M; L W) g" b1 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! K. Z+ `5 s3 ~, [6 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 ]8 `" \: e* D" v/ z0 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 [9 M! @9 G/ U' nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : S3 n1 y7 o- l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! |9 `% W& }# F: T9 d0x00, 0xFF); /* configure the clock for transmitter */5 R* i6 z& c. e+ t7 O: m1 H; \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! c! F7 Q* z6 u1 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & I1 k0 N# i2 c8 Y3 [9 W6 ?) V, Z x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* b* X8 f4 I' F1 F5 S4 ~0x00, 0xFF);
8 _, P$ v& k1 O, O) H5 g
( N6 Z& @8 \1 \+ `- n8 @: |% V. V5 W& S/* Enable synchronization of RX and TX sections */
4 p3 ~6 p: d6 k' ^/ j( s! q& T- o0 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. K- U0 p" }- v7 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) W& ]) S0 L5 ^& R. i6 Z2 r" m" B& YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: H7 o1 l7 D; `6 u/ ?** Set the serializers, Currently only one serializer is set as
! m6 o, |* l+ d) u/ ]/ V** transmitter and one serializer as receiver.9 U0 i- \- \; m# H6 q
*/' f9 C# x: q" ~ S7 K% K2 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% j k5 O8 Y% e5 p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* k% V+ g- m* k6 \% F, T** Configure the McASP pins
8 V; O5 l2 P' `# `. _! u Y** Input - Frame Sync, Clock and Serializer Rx( k% V# r6 H" F+ y, f" p
** Output - Serializer Tx is connected to the input of the codec ! e$ N* z7 @, K" ]2 ^; j! @
*/" }0 F* H% `( p2 {% ^0 J) P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( W, i1 q4 b2 G8 M" \5 w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ u9 X$ D! O8 v2 Z% Y f# HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 v O5 ^6 X% z5 l# p; ?' J
| MCASP_PIN_ACLKX/ `1 U8 N2 l9 V2 e. [1 P
| MCASP_PIN_AHCLKX9 q* Z+ c7 [8 b, {$ K& ^" w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( R" S1 e+ [* c+ `9 DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % e. c9 `$ R; `8 e' s# W4 P
| MCASP_TX_CLKFAIL - {2 }' S) r. }) m" u9 l
| MCASP_TX_SYNCERROR
: b+ O2 h6 b; j! O0 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" @9 k- S! k! j/ H% @ I+ `6 n| MCASP_RX_CLKFAIL
9 Q+ x0 x* ^7 l| MCASP_RX_SYNCERROR ( E w' M! m1 q
| MCASP_RX_OVERRUN);
: c& ?2 I# H: E2 Z( \4 M} static void I2SDataTxRxActivate(void)6 Z( {8 w/ L" m% D* l+ G* c
{- O) |2 A. |& C. t# Y- s/ p/ y- A
/* Start the clocks */
9 h8 O0 A% q8 J0 }6 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; C# |2 U# b* L7 r& P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ E4 w* U- q9 X8 Q# \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' I( |( v$ A: k l2 _
EDMA3_TRIG_MODE_EVENT);
+ j+ b' W) _7 J9 ]; j, jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 y8 v; r1 T& A3 `5 T! ~ `% x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 l8 z3 ?* C% v4 |2 \. d. V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- r: q) ?% D6 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* F5 Y5 k+ ]5 \4 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 i5 t8 _. L, g' F( KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. {1 K5 m H. l' ?: h' ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 O/ K$ e, \" u- v1 P}
7 `. S% b, i) l" b. o- f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 W0 ?3 v& [1 Y* S% J
|