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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% c; b% P, _% }/ ~1 [8 V! J4 ` D% H
input mcasp_ahclkx,
2 P2 L; N1 D3 k+ F& A! ]& M& Finput mcasp_aclkx,
4 L2 Y9 s+ @1 winput axr0,
# @/ m7 x* }; d9 k( X! l4 ~3 U* W2 @# _4 ]( J9 u( [7 k7 J2 V
output mcasp_afsr," X9 j4 ]2 {2 ` n: N, ^0 ]; r b5 z
output mcasp_ahclkr,
* u$ X2 d8 [+ m: ^. p6 qoutput mcasp_aclkr,
' V) M A2 a Youtput axr1,
% x4 j9 z, u8 g7 G! J' j! h assign mcasp_afsr = mcasp_afsx;, n# @" o6 S3 {+ T$ f* y
assign mcasp_aclkr = mcasp_aclkx;8 j0 r7 o+ o7 i
assign mcasp_ahclkr = mcasp_ahclkx;; @) R& q: f8 t/ `7 t- V3 r9 k
assign axr1 = axr0;
! s, @1 K* u: M$ P. v5 ~5 {0 |3 V! f3 |' `: [% M7 e/ i
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ ]+ J4 p# O4 Tstatic void McASPI2SConfigure(void)
; A* m& ~6 {4 {8 j9 y& T, W( y g{
! {0 S" T" v& ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 a1 D; Q, L5 w/ ?$ p% n7 l( t& [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" }8 p! [7 o( l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% ~ F6 r" w' \3 G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 P; `- j7 y8 oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 f; e4 S0 C9 |
MCASP_RX_MODE_DMA); v7 T/ Y8 r' m) @$ ], _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 K% t/ M0 y' |6 K: lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% y, a/ g! r9 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 e! i" A! n! _, C( v5 R3 N t& AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% e! R5 O1 v) [2 t8 \" k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 Q6 O' }2 F; E) ~4 B2 L9 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 y' P9 i1 m+ H: Y; H% h8 Z! NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 S b2 ^9 [5 x$ C+ dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 N& |- U! ?1 _0 h: }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 d1 U p( O2 n, J4 }( d
0x00, 0xFF); /* configure the clock for transmitter */
, |1 t! _! o) h( z0 R. O; s0 u* C8 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 b4 X9 \3 L, M3 S2 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 B7 ^9 i# V' I v) lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ m$ n d, X* l4 m
0x00, 0xFF);
& ]8 Z* q: U% t' Z- z) L3 l& h' D, L/ g9 W! |
/* Enable synchronization of RX and TX sections */ " P% a- N# n* t6 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// H7 L2 ~4 w9 \ _
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. e4 p L7 u& k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. a! l0 Z9 d# h- z# B$ h8 h# @** Set the serializers, Currently only one serializer is set as- I: c1 _, B6 Z7 a; Y/ d
** transmitter and one serializer as receiver.
9 l% m3 _9 F2 G*/
: \4 n1 P6 S" D3 V7 C9 C7 ^8 H7 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; X5 K3 Z. N' k! G4 g. w2 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 ]$ k# _* E* m. E$ R/ t1 R% S
** Configure the McASP pins ; r1 Z1 P/ F* g* S9 {7 r5 O
** Input - Frame Sync, Clock and Serializer Rx1 J5 ]/ l' B/ n: p5 J q
** Output - Serializer Tx is connected to the input of the codec
6 w, k$ k4 N1 q* X*/
d3 z+ L: C" P" H4 ~( z8 b- X, {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# q9 _4 _: x- o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 u1 T8 f9 _+ q J7 t& V r, J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! x- R+ X9 B* l. i| MCASP_PIN_ACLKX- H1 L- O$ F$ e% W# V
| MCASP_PIN_AHCLKX% |" P8 g) X: p7 G6 Z t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ^) j: a6 k4 L% J# X5 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - r7 M4 S; a9 h6 I2 ~6 _- `& p6 A1 P
| MCASP_TX_CLKFAIL
/ L+ `! f1 h3 K/ ~| MCASP_TX_SYNCERROR/ ~; s' F1 R' f( S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # z! n4 J7 L$ k) a. k
| MCASP_RX_CLKFAIL
+ v* A4 `! a. {; T. X2 b; F| MCASP_RX_SYNCERROR * l4 ^9 J7 ^ ?: z1 Q5 p0 s% V9 x7 [
| MCASP_RX_OVERRUN);/ {% F X4 P# [2 _& F
} static void I2SDataTxRxActivate(void)0 L8 b, V; G2 a x
{
m( c. \/ w9 V) r4 |/* Start the clocks */) B1 ?4 r# |# W. T ^1 G
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- T7 f9 f7 f& ^) |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 W% u5 b4 c: |7 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 \0 M6 T& V. C3 Q* b" o2 sEDMA3_TRIG_MODE_EVENT);
4 a# s1 P: w" Z0 c; BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 e4 ~% u$ j+ {7 n0 D \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 y# x- u y( g4 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 T/ @( t$ S- }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; n3 A; {# r4 W& }0 I3 h/ U: Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; D# _! c" A, @/ l$ i: a4 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. H) @6 n; \' O9 s% @' Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" S: ^$ ?/ V% _* O( C
} 2 w7 i4 Q) x5 `) N% t5 i2 t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. q' W* {9 B# k, R' }5 S5 p% |
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