MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% B. h6 {5 e2 `+ E! E7 d  Z4 C0 R; A9 Dinput mcasp_ahclkx,
) P& R3 I/ g' h3 |input mcasp_aclkx,
& |  r! i9 C( w4 s# `% _, Oinput axr0,
9 R' J5 m9 r+ W: \
output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
8 g# n" m) V# f. ?

assign mcasp_afsr = mcasp_afsx;
6 C! V: `8 J- i8 _0 k9 X. a4 vassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
6 K% O7 [& a( Vassign axr1 = axr0;

( d2 }7 u( w; [% A; q6 j% k
. T7 @! ?3 U' O

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

5 R) G/ M6 X2 ~: ^3 b) k- t/ r

static void McASPI2SConfigure(void)
+ n7 \+ C- y( V$ p/ `+ g8 `{
/ @5 l& S# z0 A' W3 I1 C3 L1 CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! h0 {, y) j- t' W) C% dMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# @1 q# @! R: EMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% i' Y6 ^- a, [3 u1 DMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! n1 O8 e2 D, pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 D; B* J: z$ [5 n; w% SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 Y7 |4 P% G  [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 e- o- P, V  q, IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
- u$ l* q; E* LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
- w1 A7 X, M$ b( C& x1 vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
. k; Y' ]7 |: Z  \4 p0 b
/* Enable synchronization of RX and TX sections */
6 s$ ?, W% B; Z! o  {* RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
# H( A4 }9 |) |: I) V** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
$ Q$ \/ M( g1 d' i: x, a*/
' E' E9 z. K% ]! E8 O5 ?6 U# OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ R# S0 x% P0 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- s! g* o1 {7 \: [/ e9 w! hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: k# C0 j! \$ ^) b7 l, z| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
/ b* l/ |$ A% N5 W1 A4 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 D# i7 j9 h  b3 x| MCASP_TX_CLKFAIL
# e0 T! r' f7 f3 w8 `; k  c| MCASP_TX_SYNCERROR
# x9 u/ [* t; ?/ H& r0 ^| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
! v0 C( Z" Y' H0 r' _3 Y. {| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
- L( K: Y! N5 b! x' c}

static void I2SDataTxRxActivate(void)
! J9 d, N+ j5 k9 O: R{
/* Start the clocks */
' \& }& o- Y9 L0 E% vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
8 M; h, Y. i* j: W3 K9 D1 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 e4 C, O" z% y2 a) HEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
, Z% B) V+ V% |* O' G0 Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& D) e: N$ g. H4 Q, KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 j% R/ w9 y; x5 z9 _& N1 }}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.