MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
) d4 q1 }1 \7 _5 k9 {! V3 b( J& Yinput mcasp_ahclkx,
# \' v2 V" P; x: u% q* ]input mcasp_aclkx,
: ?$ x) v7 T, v: F+ `) i* D2 f) @$ uinput axr0,

9 R6 x3 J; s- ^) _8 _! Boutput mcasp_afsr,
output mcasp_ahclkr,
# Z! ~; \* [/ t( I; D2 _* Toutput mcasp_aclkr,
output axr1,
2 `+ }% _5 e2 \# ?2 d1 ]5 b

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
7 P$ q4 W& l6 h1 l: R+ Cassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

, ^" C. [( V# l2 B% a- @

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
6 @4 p1 h1 C4 k+ z2 j. o7 s{
. Z% o8 D6 L" o. X9 N$ AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# M- R6 i# W& V/ b$ ?+ N: zMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ l+ O% |, Y( O( j+ ]8 R2 ]. CMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! {& t+ }) P2 A8 j( QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 E2 {; o4 O, i  RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
; W4 U2 s& U( e( FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ ^3 [; d* g9 ~$ S9 w! a0 W0 nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ ~2 \: n0 E. E3 k* P0 L3 oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" z2 |! a. T9 D0 U  m$ I! RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
3 m/ }$ _2 p+ w
, V+ Y8 c% R, i. K/ D  J7 X( t/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 B% z2 \) g0 t' G9 N; DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
3 o, K: o" E- m, A, \' W/ GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
0 U. s6 D' Q! K4 Z4 E** Input - Frame Sync, Clock and Serializer Rx
2 s8 \4 S/ w& b& B5 @** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ f* h8 n3 K$ [1 _# d% iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
  L6 d! f( k* Y- c* r% M' Q$ OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
1 |( {- c( N( H% o  a4 E4 k6 n) k6 t| MCASP_PIN_AHCLKX
4 s5 G% K; h% j" D3 R7 `7 }| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
6 {3 P5 ?# \3 M7 Y( O3 O1 O| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) g3 [! l& `+ U! r0 q' n| MCASP_RX_CLKFAIL
) V8 J2 |+ Q# G- z6 `* j| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
' N! P7 f$ b3 l  J* b}

static void I2SDataTxRxActivate(void)
{
' r0 O( k9 ]6 P/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
& h6 l) S4 x0 Y. C7 q- TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
7 F* O+ ~+ x8 Z% ]/ @, K5 w  LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 |* b8 ^) s1 G1 ]# p; q1 `  AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ Y7 u7 s+ [& @! _0 Q. A+ QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
" q7 J  v. B: W2 M7 U; h6 Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) x" e4 n# k; r1 @5 s; w) P- uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

" l- Q& ?7 }; C' e% e

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

1 t+ c# z; e5 s1 k, d7 ?2 k