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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 V$ w8 w5 C0 L4 W$ i' Ainput mcasp_ahclkx,
- {8 `' R" m, n( I- \4 Einput mcasp_aclkx,
3 ^' S* {5 E8 Ninput axr0,' [# t0 n* c! t- r! ?+ U
( [8 _7 Z2 X6 \( Z) noutput mcasp_afsr,& ~, U$ e$ K/ K" U2 ]7 ~0 @& f
output mcasp_ahclkr,
8 S: a/ B e1 g! w4 S4 W& ~" d$ r7 Loutput mcasp_aclkr,
9 [# h, Q _5 R6 L0 x. p8 s9 soutput axr1,; W# x, S: h& C; K
assign mcasp_afsr = mcasp_afsx;
# g& G' P9 j' P& k7 xassign mcasp_aclkr = mcasp_aclkx;
9 x) i" Z+ w/ F% h/ f! uassign mcasp_ahclkr = mcasp_ahclkx;
, m" T: h6 h/ c+ E* K+ _4 kassign axr1 = axr0;
4 g- e7 N# P7 F7 `; V4 X Z
& V6 m* J8 ^1 v, j2 d+ F2 c/ t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' E& }4 Q+ V' D8 ?, y
static void McASPI2SConfigure(void). Z# {' d# c5 j7 \1 n% Z
{
4 ?+ L3 s6 g. ?8 B' v( @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 i3 X7 M- |! [$ u2 f- |( t1 l' UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( O o1 j% k* F! T/ e) bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" [; [) i( N+ IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ F$ ^* r6 R! [7 H; Y' G5 ]' ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, r9 @2 }$ u7 M/ NMCASP_RX_MODE_DMA);
4 r1 l+ z6 H) mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ]5 K* V, `" O" gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& w& s5 G7 M( i4 H" @, F, J; I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 O2 I1 X, d* Z" a* XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 D; a% t; p) ?) L7 V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ L$ W% \. D gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ U' P# R* k7 ]; |- ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 _9 E6 \ N: G0 G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) R$ H4 X$ l9 u8 N( o) [, D8 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' f% o6 \/ K1 l6 D5 @% L& Y c0x00, 0xFF); /* configure the clock for transmitter */
4 |, k. L! u4 ]- o( {9 P6 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( w7 c+ j/ H/ H* p/ R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : z! @: p3 X6 j. I% H8 C4 h2 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 j; ~1 p+ s u0x00, 0xFF);* |' W& A: \/ x2 ]2 I8 U+ T
" P) V U% x+ H
/* Enable synchronization of RX and TX sections */
+ Z" N9 X. z: b: C. R. bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* F. |5 u! g5 w3 h9 _; H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); N- y, Y8 ^# c4 Y K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ?: A: Y' a% u7 G1 B4 Y
** Set the serializers, Currently only one serializer is set as
) X+ @- N8 N) X& q- u4 w2 u** transmitter and one serializer as receiver.% F, I5 [ I, h
*/- D0 [; Y+ Q8 t/ B7 X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 |7 S: c/ |' k( HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ g8 K9 r2 d6 t* a j0 e% G, I: _** Configure the McASP pins * Z# w, S) V7 K. c- o& M! J7 {$ L
** Input - Frame Sync, Clock and Serializer Rx
# j- K( Z) h7 q1 \5 N3 }** Output - Serializer Tx is connected to the input of the codec % j) y4 r. }! c0 }, |& Z6 h) z
*/2 r" W$ \1 w! K% M$ v( f6 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& `) t$ q3 R9 h6 n6 B; {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: m4 |! j; p5 T- D+ aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# _" y" Q( m' f4 v: ~4 R, E" W| MCASP_PIN_ACLKX4 B A R- m$ v4 o8 _
| MCASP_PIN_AHCLKX3 }9 @" H' e1 _: |4 i% t% z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 L3 d9 H7 p3 e- g4 O o/ ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 r6 {8 I& [, a! g| MCASP_TX_CLKFAIL 7 `$ m1 m7 c2 Q9 o1 ]8 S
| MCASP_TX_SYNCERROR
8 ~+ E7 O3 F6 X3 D+ T1 i1 F1 i# S' h# N: ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ _/ J5 }2 h! I% n| MCASP_RX_CLKFAIL
, Y! s" I- F5 v) t| MCASP_RX_SYNCERROR ' e% `2 L$ S( u. O- i
| MCASP_RX_OVERRUN);
, x% C- I0 X; @: [/ A4 T4 P) B0 a- I} static void I2SDataTxRxActivate(void)
2 P/ P5 \- S, f2 t7 A{
/ ^( L' P9 L3 r' E+ A( j. A, |/* Start the clocks */$ M( C7 ?! s# [% z, h7 n1 k: c# X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 z2 O: k% T! _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 ?9 h& V. W$ z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 a# ? ~: Q* I3 q+ o$ X
EDMA3_TRIG_MODE_EVENT);$ N) r' o8 D7 v8 t& @8 ^4 y% B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . G: K( O0 Q# l, R" o4 j3 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* P* g( y! M0 v o" k% y0 _! T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 ]7 u4 H% V: ~( uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. ^ z% l: v: Q* D# z- R4 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; E0 ^1 m4 e: e8 {% K. @' b$ ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- I+ A( j. G. z! U& n, S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 a1 n& ]/ M, H/ i4 t
} 8 m" B0 q) }7 P, A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
1 n3 S( U& f* j' g8 m |