|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% f7 K4 E: i) F( v Finput mcasp_ahclkx,+ H2 W4 |, `1 s3 U! z
input mcasp_aclkx,
2 ^, p# E, H0 x' _input axr0,5 P8 N( w: c3 c( G. b
6 f/ W% j% m3 [7 G+ ~output mcasp_afsr,
! I( q0 x% v4 \( i" _output mcasp_ahclkr,
2 E3 {3 G* P% C4 H4 Qoutput mcasp_aclkr,
}# s* u6 V$ O* y" w Foutput axr1,
9 f: P* Z: `2 y. n o assign mcasp_afsr = mcasp_afsx;2 C1 C; J0 @6 Y' S/ C8 C+ F
assign mcasp_aclkr = mcasp_aclkx;
) a7 x5 ~8 X# a; t6 c+ W% oassign mcasp_ahclkr = mcasp_ahclkx; { Y" f! Y6 U7 }1 U
assign axr1 = axr0; , X% |" U( E6 Z6 C. Q/ a
2 N4 D, ~, T F+ W# I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 U, N" f/ h/ g: G; c$ Vstatic void McASPI2SConfigure(void)7 Q7 C: _% ?; O h
{
2 `) q7 n6 {; g% ^, F. cMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! F9 N* n6 [2 S0 PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */+ V3 U, m. m' _% Q5 Z" O/ b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); M: P8 c6 W8 {1 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* G2 w8 k; w6 ~. e$ n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ j/ ^2 O. y i
MCASP_RX_MODE_DMA);' A7 N. k, O9 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ }% z: u( H( i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 `5 z0 M) U2 r* I2 B6 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ _0 Z P3 Q, v; F7 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# }# y- ] I! z: {5 z2 D; v# X$ fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( f" L3 L/ C7 a0 u A" b- VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 Q& \2 E6 y0 u. e: K {4 fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% w( e) Q6 d, ~+ j; lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 h5 v5 r4 q/ s, {' V. C4 i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) X; `' H3 i2 f6 {3 j0x00, 0xFF); /* configure the clock for transmitter */
* o& y ?6 |9 l2 s% V- v8 J# HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 q) o. e8 v1 E s/ `4 k. RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 S! w# t5 w6 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 d% y! w' D( D
0x00, 0xFF);
. ?9 w9 Y$ B7 O8 I6 x3 H0 T7 p& S7 {4 N3 p8 A: j
/* Enable synchronization of RX and TX sections */
% i# u7 Z* ~/ }* }9 R9 gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: g3 I, ], b8 Z! `+ O# c: a2 G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ J0 P+ M' F1 _% n: tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& @0 B2 i9 _+ H8 d; u** Set the serializers, Currently only one serializer is set as
( p! C# i0 x+ d- V& H** transmitter and one serializer as receiver.
% Z7 m8 @$ w% _7 c) U4 f9 P& C*/
, r# P4 A+ m) M2 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ Q9 _ ?& A* T0 i4 \+ U' T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 ^, I1 Z+ p+ U
** Configure the McASP pins
) j& N2 d2 E, M** Input - Frame Sync, Clock and Serializer Rx
; H8 `+ }$ a2 f** Output - Serializer Tx is connected to the input of the codec 3 ~, g) e! F+ j" K3 Y/ c; X
*/# I& N, ^+ C8 g8 t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ Z* j; S/ j- _3 W( kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 s9 P7 P3 Y/ a. l: f1 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" A1 b7 j! U! R( n7 Y1 m( y5 u
| MCASP_PIN_ACLKX
: P9 Q9 M* u; T% b| MCASP_PIN_AHCLKX
" z# V" R3 {1 G( t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 Z% d" A% ~! ]6 l, TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 V1 H* y1 F& U) I0 U7 A
| MCASP_TX_CLKFAIL
" g3 v5 u f8 j# P" }| MCASP_TX_SYNCERROR
1 _4 n" F$ T9 N8 i; e. `7 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % D8 {# Y. ` Q$ s
| MCASP_RX_CLKFAIL
9 o9 W$ ~6 F0 x4 ^$ || MCASP_RX_SYNCERROR ' z, H, Y. b& u) r7 a
| MCASP_RX_OVERRUN);8 Y4 q5 h/ ^6 j/ ^0 U- ^$ x, R
} static void I2SDataTxRxActivate(void), W9 c# R8 v0 M
{
% [. \7 U$ c' }1 c5 x& U. ? A/* Start the clocks */
: x6 W3 i; {' Y7 [: J: VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 V- L( @8 D0 x# UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 }8 r, d9 H" m* w9 [2 L1 f X8 \6 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 C+ E8 I/ X2 Y) k
EDMA3_TRIG_MODE_EVENT);
1 s+ P; P8 r7 p8 }! YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % @4 M9 o C# s" l8 z0 R2 d: i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# v* O& v! p3 |: m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- j4 \5 c9 K0 _; N1 a! AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( r c7 f" K4 `9 n2 b% X `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: {. ~3 g# M1 ]' M% bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 r; S; W8 A/ h- _5 b- ^' N* M* I* mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' v+ E! G Z. X& K}
) S# }& E- l" e; e3 p0 ]1 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; S! y8 n4 Z6 a! {9 q( {" t |