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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ W p- X3 Y4 O: H, i4 F$ h1 {7 F8 Minput mcasp_ahclkx,, y2 T! e5 q5 U0 e. C4 L
input mcasp_aclkx,
# a1 }2 P' I2 S- \/ ]9 M# finput axr0,6 z% }! |" G) g% T( m `6 e
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output mcasp_afsr,
' `; A1 W' s. U; A. |: C* \0 loutput mcasp_ahclkr,, _- q6 l7 B/ @: w/ P
output mcasp_aclkr,
& @# I) N- S# e5 ^' j! Moutput axr1,
! R( x4 _( U4 c assign mcasp_afsr = mcasp_afsx;
7 u1 I; k) t: a: y( _assign mcasp_aclkr = mcasp_aclkx;
! h' F/ n' S" S7 c: }. P/ B" massign mcasp_ahclkr = mcasp_ahclkx;' @6 o, O' {: C" e4 o$ l6 Q% t* D
assign axr1 = axr0; 9 W) r# X; G5 _% L
. L0 R7 t9 J! l; O: G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 {! f0 P" v; d; t) c ?
static void McASPI2SConfigure(void)( z3 O X9 a2 O: \) M- A
{8 f" I# J: d _. j. U/ m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 G- x' c' T% S* e, U/ _ K% h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" C q$ o) z% a! ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& J0 g, Z4 I2 O% n# \" S5 I$ R6 d3 Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: z: C j* A8 I5 f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ Z) z$ F/ O! w8 i% ?; K
MCASP_RX_MODE_DMA);' @0 s. V+ T* a, u6 S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! n# k0 ]3 z8 [) Z3 n2 M' D
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ s, ?; d& e1 J$ a$ L' U+ ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! v" @$ M3 |8 i, D9 MMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' n2 b4 A7 x3 I; e* @' r4 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * z; N1 z* J) A9 V; Y% y+ l; F+ f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ Z6 h E/ w$ r# e) o8 \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ ~6 B9 a/ j6 C6 B8 R8 n/ u5 L7 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# x' r) A6 E4 |' uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 R% M5 B0 t4 p3 i" s6 m
0x00, 0xFF); /* configure the clock for transmitter */
; G' \3 I( i4 X4 r0 u- x; H. B6 L2 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ l7 C+ @6 t% a; G4 u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% V# f# s% M* EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! V- ~$ g% w5 Y: m" M1 X5 d9 |
0x00, 0xFF);1 u9 ]( M5 c% Y1 a
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/* Enable synchronization of RX and TX sections */ 9 G; B, D7 y- r* u% _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! l/ p8 ~9 |' i- {5 [( {4 s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( l6 n. I- j% r& H7 u% X+ EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# v. v1 R% u; U+ {
** Set the serializers, Currently only one serializer is set as" n6 C$ {$ X) h% g# U" X# K
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% ~# ~* P" ]& RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ _4 N) j" q9 E# O** Configure the McASP pins / F7 U2 ~& y, ^& P
** Input - Frame Sync, Clock and Serializer Rx
4 ^2 b0 E/ s) f+ H3 G' a% H/ Q' {# Y** Output - Serializer Tx is connected to the input of the codec 8 i0 U0 x+ S# v" D' G- e1 v
*/& d/ ]- S: M9 w3 h. A4 l* P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 j" V- q# \* [/ m7 e, q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 D6 L I( K: H! O; m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( f1 @. }, p$ W) ?) X
| MCASP_PIN_ACLKX
5 f4 J# g4 t* {+ N3 I| MCASP_PIN_AHCLKX
( e+ \* d( r2 g& V+ p/ f1 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 J5 Q" v: y) R; E/ K' L" l: U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# f2 R' A. M# X$ i$ Q/ d* Q| MCASP_TX_CLKFAIL
- y9 a. C1 T, C1 V4 u4 q4 y| MCASP_TX_SYNCERROR4 C1 w% D* a( G- V- Z- Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) t& F Z5 m' I0 z$ Z
| MCASP_RX_CLKFAIL/ Y$ C, n. }1 v) z# Q2 O# C9 V
| MCASP_RX_SYNCERROR 1 z! {8 s# \* I- h
| MCASP_RX_OVERRUN);
8 q: T4 W5 f- x7 _4 L} static void I2SDataTxRxActivate(void)* p; F1 R" K6 o( S7 w- d
{3 ?5 g4 C, d7 R7 X {# k
/* Start the clocks */4 R2 o( o8 v% i: \" `8 n/ ?
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# c2 v) a% l" L; U$ k5 qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 y: O+ B9 {( s* I4 z. HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 Q3 R6 @$ P* l. GEDMA3_TRIG_MODE_EVENT);
* O* G n* }5 u1 |+ t( ^/ ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ W3 l6 D- m1 {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! `* O2 i9 H! { fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ?( H0 j# h) R) j( [" h$ V+ Z. G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: b% l1 X! N5 Y# `# J9 t$ @% X) d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 b0 H* k$ ~- C6 `3 v7 b5 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- i6 p m: T! hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 Q' K+ ]& Y3 X
} ; V0 S- G: i. }2 y# ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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