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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 n1 M- P* Y/ tinput mcasp_ahclkx,6 `0 F( W& A2 T- f" U
input mcasp_aclkx,7 c0 L# T# s$ h; i7 V
input axr0,
2 v3 Z' y& s3 [3 \6 B7 @/ N7 j" N' U2 M
output mcasp_afsr,2 u9 `# f2 a8 F4 ]& ?, o( Y" P9 Z
output mcasp_ahclkr,# u4 B% S, p* n/ G0 v7 l
output mcasp_aclkr,
8 w7 l) B: c2 j! U# c5 ]1 B; l; ?! `output axr1,
/ v7 F4 q& g% U' @ assign mcasp_afsr = mcasp_afsx;% u$ a w- ]+ E1 L) X
assign mcasp_aclkr = mcasp_aclkx;
c. W }: y+ E+ y( n. Kassign mcasp_ahclkr = mcasp_ahclkx;
+ k1 U% ]& H( B" d4 ~1 Nassign axr1 = axr0; + R, L* @4 |' i
4 n6 C ]+ J1 R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* C: S5 F3 i" o: }. w- a1 i. R; Rstatic void McASPI2SConfigure(void)# Q1 L4 ^9 A" w, h- J7 Q
{
) K; g: |0 M+ t& LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 @) J9 T1 w- T0 p$ m( [3 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 q9 j$ A* i7 B& S+ Q7 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ b. {2 w( Z3 O; |3 I* y6 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 A- I& M; z) k0 Y0 F* t& j4 \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," h% p" C- @) b4 l! g" A1 L
MCASP_RX_MODE_DMA);
$ [" d: }/ f* p. j+ T$ }0 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 C0 F- F" X1 ^$ ?0 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" ~/ w) D$ W' G5 M; E: o. q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* j, U. F. ?% Y6 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 v; C. B4 x) N. {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' f( { R1 C& _2 i% Y& \$ |2 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ V; T5 M3 h0 r( F5 O5 Y( l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 |5 h+ L+ Y3 K) j6 A3 O8 B" i w- ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# O9 w1 _; W( g+ N3 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 f. t/ a$ N @) |- b" P" l4 G" w# q0x00, 0xFF); /* configure the clock for transmitter */4 |- I" l% c) t$ N8 n9 G3 _5 _! W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( s/ G2 ^3 E9 b+ ]4 W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' u! W8 L% y$ S. PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' S& {0 d/ W6 T1 G' n7 y C
0x00, 0xFF);/ n; _/ u- c6 A2 A$ B
& ~/ O8 ~1 ~; q v/* Enable synchronization of RX and TX sections */
9 T# g7 p! W* ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) h% u- l0 {: R4 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 E4 Y( P6 M/ I3 p# O6 BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" C+ C2 L: e- k! l. O+ M! {** Set the serializers, Currently only one serializer is set as w8 j% H! H& v, K b( |, E; u+ x
** transmitter and one serializer as receiver.
8 y* J( X" v r1 q, H*/3 e" e% ~9 ^3 N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ P, M( d( A8 A9 c3 \3 u l KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" K4 H% G# o7 v
** Configure the McASP pins , Z+ v6 D' {0 q6 w+ L. t
** Input - Frame Sync, Clock and Serializer Rx# `; U' r+ @: \! B. L, ?
** Output - Serializer Tx is connected to the input of the codec ( D; q* u3 L3 @# G0 Y
*/
" v* }0 t" k& ~5 j) |' eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 G% U$ ]. e3 x2 a6 K+ U1 C1 t9 ^. `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 d* \2 h8 _9 @2 x' t8 t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 d) V/ R. j" Q! g( r| MCASP_PIN_ACLKX$ V6 s( ]( C, u+ P
| MCASP_PIN_AHCLKX0 ^0 t( c) R" l* [; O$ D% v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- o/ J+ R1 B4 \. }: x% |$ l% r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 C* I& a W9 Z# P Q2 l+ s: T% w
| MCASP_TX_CLKFAIL 3 U U* E% J* Q. C
| MCASP_TX_SYNCERROR. g$ {( {- ?5 B3 J& \) k% \+ K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 x: T' p( X; s. S) h
| MCASP_RX_CLKFAIL, h7 L# ~) [) Q h- S1 N! o! ^
| MCASP_RX_SYNCERROR / _, h6 @6 R7 l4 C2 E
| MCASP_RX_OVERRUN);
. T9 ?( J2 y: `" V6 P A} static void I2SDataTxRxActivate(void)
' Y- F. J* j' `- B7 |) N! e, o( J{
- J. M7 [ U8 m/* Start the clocks */7 q- h4 E3 B( f# V4 ^7 ~5 l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 Y7 A; }6 o7 Y( p$ N1 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' c; @5 F; [5 Q% R' T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 g6 X1 t. w$ w0 {5 F3 O/ ]
EDMA3_TRIG_MODE_EVENT);; ]5 |$ K1 } }$ `1 t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % `7 X* _- Z7 c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 D$ e! `& h' u3 I4 M* d: a. X% EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 B7 q3 ]- ?4 E0 ?& z! W0 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( w7 _0 L, M9 o& Z8 a/ c7 H/ | E* O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* n# L* R0 t( [% g% Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 Z T9 f" Y4 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ {6 V* f# ]& R3 [+ h7 c}
, X/ |( _# ^2 j+ n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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