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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% E0 H w3 D4 {3 rinput mcasp_ahclkx,
1 s! N& M" g8 `$ j7 A! y1 n2 [input mcasp_aclkx,
/ ?/ x+ k9 f$ g) s! E- linput axr0,
9 ~8 ^. T" ]( Y7 ^
# @* D4 U& Q/ ], M; B* @output mcasp_afsr,
; Z4 ^0 j7 T" ~7 ioutput mcasp_ahclkr,
7 W; ], e& ~/ t# D9 ~ o2 g; foutput mcasp_aclkr,2 q0 F! U8 w/ q7 S- \! e" |
output axr1,2 [& N% e/ x' ?0 a, {) U% K
assign mcasp_afsr = mcasp_afsx;
6 z8 A5 A5 p0 _! l+ E2 i2 t3 Nassign mcasp_aclkr = mcasp_aclkx;
U6 u/ w( L8 _8 f4 } Lassign mcasp_ahclkr = mcasp_ahclkx;3 v) P+ r+ S" f
assign axr1 = axr0;
4 ^7 u7 w/ C, m. C2 x
8 t% r2 E; x8 l! u$ L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 z y0 N& n7 Lstatic void McASPI2SConfigure(void)- Q2 r2 Y3 `5 A6 c
{2 a/ i5 l; k0 D- [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ f. m* m1 M. c9 [8 B! L8 Y) kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 k. C( G9 R! |4 X# X3 f' rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: H$ a) m- Q, p# s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ c, t1 u4 G# e3 {2 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 I _, e% M, Q! O2 @) B8 x
MCASP_RX_MODE_DMA);; p2 R, F8 K: v. L3 E
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ d" X% f) O9 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* ]# V* W. \; u% [! ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " k' |: h4 C8 [3 [) ^9 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 t; m8 c+ v- [$ K2 f4 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 Y7 R: ]5 c, [- c2 t YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ {6 Z" N' g/ qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& ?" k8 d) ? ^9 |6 U( X4 Y2 N' uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) T- A, E8 m% D/ s5 m* j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 N$ c2 Y' I. ]7 N8 [
0x00, 0xFF); /* configure the clock for transmitter */! a6 }3 O0 k+ m" [! M- H( X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
r! w& c$ V+ H; C% qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 O6 b6 L- ?9 V5 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% i0 P; `% Q% l8 {4 {0x00, 0xFF);5 a+ c5 D# A& W
% ]% K: w, |5 w8 f4 F1 b1 {9 O
/* Enable synchronization of RX and TX sections */
" U( E% m/ C3 l6 l' {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 {# M' I% h) Z7 JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* |* ^6 ]/ \) D. w1 g! O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 R. t5 |5 O: \( V9 w
** Set the serializers, Currently only one serializer is set as
6 A/ Q+ O- Z3 j, _- s' _6 z. b. H** transmitter and one serializer as receiver.% ~# g* f$ g* |: r2 M
*/
6 [9 ?- p" ~- S+ A+ j, s; CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# l' M, ?* o3 j4 a6 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 h6 ]$ h: w: ~! V. t
** Configure the McASP pins
j( `. Q! m& N5 i# U** Input - Frame Sync, Clock and Serializer Rx, {$ P& v! L5 o K- `8 q1 e
** Output - Serializer Tx is connected to the input of the codec
) Q9 n% k% a2 K: Y) f*/
, r; }+ E& n( y% W8 r& qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# I$ t5 a$ Z9 X6 UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" d; X' Z# [. N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ @2 t1 E6 w( _3 O# j% T. ~4 R$ d| MCASP_PIN_ACLKX# \2 A* U, E( m. @, a4 V* P
| MCASP_PIN_AHCLKX( j3 b" x0 J) c# l* O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 L- H' c+ j% e1 A x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
D: m5 o' l" C/ X [7 h& O# V| MCASP_TX_CLKFAIL 0 B. u& @1 X( b, e |. ^
| MCASP_TX_SYNCERROR
, _, N- o: h/ h; a* || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& A- y; J4 x9 c! m: ^5 N| MCASP_RX_CLKFAIL- Q' N( |9 [0 q& ~ m
| MCASP_RX_SYNCERROR ; o. f* _/ G2 k9 C0 d" `+ K3 V
| MCASP_RX_OVERRUN);
$ z9 n% ^9 C$ M3 d} static void I2SDataTxRxActivate(void)
' d/ E; \& b( f7 G{& Q5 p: V) Q2 O8 @4 O
/* Start the clocks */
9 `: `) Y* ~7 N4 C1 K8 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 Y, A$ @* U. c' \ O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; e: N1 E8 v' |6 g' l1 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 E m+ B0 X$ e+ g5 r' S
EDMA3_TRIG_MODE_EVENT);
( ]' ~/ k, d, b* u$ g4 Y0 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ D% @+ Z1 S- L( q/ @- ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- @3 g" p- |( N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' m( j1 ~" P( I* Y" o! y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 ]' O7 b" ~$ A% Z' D' t, ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 u" J& T" [0 `3 _8 i. T1 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 U% x, l" M6 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- b0 K' ~+ | q2 v0 r' |
}
+ o1 B! v8 t! m8 F/ J- r6 m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
- h- @; ?: ^+ ?6 r# |( b |