|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* a9 l1 X1 l' H% T. c0 cinput mcasp_ahclkx,- `6 i" _( Y4 ?" ]/ O% J8 U
input mcasp_aclkx,
0 C& Y, G. D. q, T$ qinput axr0,
, T2 S b0 o; S" y+ E0 A# Z" p" A- W, o J
output mcasp_afsr,
7 ]9 r% p2 o0 [8 _/ W8 }# `( B! A2 _output mcasp_ahclkr,
, j' p: b- M# i4 }" eoutput mcasp_aclkr,
$ V) D( s6 z- [2 u7 P. O* e; ?( doutput axr1,6 `# k- ^1 Z1 H" m4 S l, q( O
assign mcasp_afsr = mcasp_afsx;
0 n' T7 a: n* Y3 D" G2 q& tassign mcasp_aclkr = mcasp_aclkx;& m: S, D( X8 R+ B! n: y# l
assign mcasp_ahclkr = mcasp_ahclkx;+ _6 {+ J0 f8 J% t6 k' t% y
assign axr1 = axr0;
7 n6 B- u H+ i. F4 Y8 p! }9 e
5 g$ @0 g6 x$ @1 c& q f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 N2 f* X* Z! ^# A! y! O
static void McASPI2SConfigure(void)5 e: J* p. C1 Q' Q& Z: F
{
' ~2 i' m4 e5 a% jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ H) U& r9 z9 A1 ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. |) }: [9 n$ m8 Y% s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" J5 E# O. _8 f6 F h& ?4 y1 Z7 A6 Q ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* x# Y7 S. t# Y2 ?9 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ g+ _7 T: e! p0 hMCASP_RX_MODE_DMA);
7 m8 q. ]3 \' HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: Y2 f- A" D( M: J( ], l+ N( u( @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 P b+ _* o8 q/ Y) S; ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) C( s- |1 U: c- R4 ] i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" a7 V* e f7 _: @4 K% U# w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! e$ ^+ o! V' w& lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 @; V% `: s. K9 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; v! P" a- {) V7 Y$ X, e( EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ B0 {; ]' O8 f T4 J! {/ pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 x) Q. R9 J4 C/ n9 `
0x00, 0xFF); /* configure the clock for transmitter */
. A; `7 d! b7 ]$ a1 W" bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ |/ ^) H5 {0 B' p5 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 y* j& {/ b9 d" V" r9 B) U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- J N* C, d" O; g7 ?, r% X0x00, 0xFF);$ s6 `7 C9 ?1 k
7 V+ c0 K8 W& M/ r
/* Enable synchronization of RX and TX sections */
l3 m' L3 l3 b9 a, w, g/ U: }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* Q( u- j& {* \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 H* y5 V C; E R6 |- j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 E$ K# c' K4 F( C
** Set the serializers, Currently only one serializer is set as& C) Z: L K! Q& T1 G
** transmitter and one serializer as receiver.2 ^& n, X, T9 _0 U1 t* h& q
*/' ~/ n; }0 U0 j% J
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: i* g- W) x1 ]. `# C1 G6 k3 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ k6 }' O" y5 n3 ^
** Configure the McASP pins ( Y' p5 ~& x9 b% f; X" ?
** Input - Frame Sync, Clock and Serializer Rx
& B2 Y1 l5 Y& _2 [* H** Output - Serializer Tx is connected to the input of the codec
( ?5 a/ R3 W3 G+ r*/
1 z( k' I! }% L4 V9 Z, nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ [( x5 L7 B. V1 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
R4 Q' P* X' V. lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX G0 J* p- g4 j! ]. D2 a
| MCASP_PIN_ACLKX' E7 r& M! S* g4 M' B& z6 G" }9 I
| MCASP_PIN_AHCLKX. z* b& a, w& T1 c8 M/ M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 W& M, J: t2 P% `& @1 h3 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. q) ?( \* ]8 a) l" D| MCASP_TX_CLKFAIL 5 @' I, V' y) `. i2 J% V
| MCASP_TX_SYNCERROR" F7 E3 w: m9 h' F# G( @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( P% u" V1 K4 E5 W* U" S) p/ a* `
| MCASP_RX_CLKFAIL
, N; A, v ^. |5 a1 ?| MCASP_RX_SYNCERROR
$ g3 ?$ n" e& s| MCASP_RX_OVERRUN); m' s: }: U3 n& L% i# @
} static void I2SDataTxRxActivate(void)/ d* s8 ^) s, \' p
{ T0 E7 |5 b! t9 |( O% I
/* Start the clocks */
2 ]! F% p( A0 u G/ tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% V' R7 }5 I. j0 y1 @! |: d: K3 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 n/ }9 w; _) j! Q1 }: Q' {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( u l- e6 y/ b8 U* t; i, \# ?: k4 H3 LEDMA3_TRIG_MODE_EVENT);
" |- w+ p- p7 x3 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# f( M. N0 d+ Y& m, H6 [/ f( tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- ^8 Y( z5 ?1 e& B( i% }$ y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 ?( [; F( P0 l5 `0 w, ~7 E9 I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 w) G" o5 {7 y- q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 r6 H' @: m0 f: q$ i3 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- x! U* f8 Y+ u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% H7 q) w& ?: G} , ^8 @# W( p: L# Z* |5 r% B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + r" r9 S( V4 R; V
|