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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 j/ T, E8 z- C7 Y1 \' j9 Jinput mcasp_ahclkx,( F! b2 s4 u2 ` w
input mcasp_aclkx,( J- p0 R) d) S( l
input axr0,
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! V5 s* {. `3 |; Voutput mcasp_afsr,
/ _$ h8 E! c& R2 ? T! voutput mcasp_ahclkr,$ H* M7 ~, D* n' K
output mcasp_aclkr,
, \. z5 D, c$ {! D0 o4 qoutput axr1,
1 `6 _# e, q; w0 F6 R assign mcasp_afsr = mcasp_afsx;
: k7 u) Z5 n4 E( [% Oassign mcasp_aclkr = mcasp_aclkx;" u' f5 W w" m- n& d& X" }0 H
assign mcasp_ahclkr = mcasp_ahclkx;! z3 b6 U0 Z8 [ O2 r; S
assign axr1 = axr0;
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! E) P. e1 o# e6 \, F0 M" W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - r+ i0 `/ {+ s( {# y* ?- h
static void McASPI2SConfigure(void)
5 e! i; H1 K' A; a; |! S$ V' N{, M6 N4 y7 f6 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* X% W* @' ?! X' ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ m% M5 C q. H E" DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
b4 J6 @# q& U* y3 G' W+ @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( W; X# P" }0 g$ R& PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ^& B" n9 U* E; V
MCASP_RX_MODE_DMA);1 b: I, K: P, Y) H5 v# E! q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ L2 W) L/ o! ^- K4 J9 v, y: NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% I/ ^1 G4 x3 O3 _/ x1 y- Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ z/ E% L7 m2 y6 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 z3 O5 N! H6 D& Q3 L# `) X. u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . B+ Q# e6 [4 l W" t! h* V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" y! u; A4 l. v5 {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 u& `1 g1 H2 F; C8 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 T. ?7 X" Z5 w2 T/ Q3 |+ `( U$ n
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* V3 x$ Q" |5 [# i+ q0x00, 0xFF); /* configure the clock for transmitter */
8 P3 h# h" t) t }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, J& n8 V9 z0 s+ HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" D6 o2 M V# k: }/ D/ Q' ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, I( o j" h* d( d/ a; V
0x00, 0xFF); e, ^ \0 _4 n' c6 K4 `$ P
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/* Enable synchronization of RX and TX sections */
4 p. ?: U3 x) ^1 H8 l: LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 x4 {9 L, w. p) d4 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); N8 _2 F0 k# k4 z0 [3 k$ f K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** t0 |- L7 f7 J% U% f
** Set the serializers, Currently only one serializer is set as
% H0 G! Q8 S+ q2 M1 q p" U** transmitter and one serializer as receiver.
/ q5 X/ u3 b) V2 J) ^: T- k*/
2 u. p8 u- n: G0 `8 c: O5 L- UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- d% q# j8 d. l( CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% j5 x6 L& N, g3 U# C
** Configure the McASP pins
$ C5 W1 h& Z6 f3 b9 Y4 F** Input - Frame Sync, Clock and Serializer Rx
9 j- s" Y! y& F% f* f** Output - Serializer Tx is connected to the input of the codec
+ c" ?% R9 a) I$ m. O*/
* H, [# F+ n) ]& d" f- x1 uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! u" P; K' Y( s) K4 Q5 C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; @4 A* p- R; X1 ^9 u7 B. a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 y( U' z! w- T' [9 L" Z| MCASP_PIN_ACLKX
# V. s3 Q. k' v5 K| MCASP_PIN_AHCLKX! w, G4 d V% ~) S; q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 @5 _8 c* u; z: p: _% x: t3 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% ~7 d; A% n7 @9 z; A! H% X0 B| MCASP_TX_CLKFAIL ) P, z- Q# [6 y0 X( I# [* s2 T
| MCASP_TX_SYNCERROR! ^$ n/ d2 D% ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( _9 d9 W% A0 @" L| MCASP_RX_CLKFAIL
6 }* O5 D& K' v( c; [$ @& g| MCASP_RX_SYNCERROR ' ]3 l# m1 I5 G2 d! _- s
| MCASP_RX_OVERRUN);
. n$ g# C3 H4 e+ ?+ P* _* _1 O- Q6 x2 h} static void I2SDataTxRxActivate(void)7 |% V7 Z. c( @1 O
{( q1 T7 A7 h8 \3 b+ A9 { V
/* Start the clocks */) N# d! d9 D; {# f* k# b/ t4 v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% p+ J% {+ K r4 k+ lMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 F3 j# U" ~2 U4 H2 tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; n6 D4 }6 j( A4 BEDMA3_TRIG_MODE_EVENT);
* {) ?5 x* U: |8 v& c7 Z/ }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 X! B$ Q l: G5 b/ Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, P, p+ r. B/ C. @+ m; A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
m# X; A* W2 d BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 E! a# X5 P: h; w
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// [7 F9 D/ e+ V& u% J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" k9 z* Y0 D; P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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