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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# C0 A5 v& J0 `& ^4 x: n* N H
input mcasp_ahclkx,
! ^$ h% a1 Z5 r5 [# N* ginput mcasp_aclkx,
4 p% l8 U# | hinput axr0,) { S3 ]& I5 q
: G# n6 s! ~5 Uoutput mcasp_afsr,! Q; d5 X5 u9 _ S# s
output mcasp_ahclkr,
& T3 ?1 |2 I/ N' ]- coutput mcasp_aclkr,
3 Q$ r* N5 ^% o. L {3 |* youtput axr1,4 s& y: p. O/ _
assign mcasp_afsr = mcasp_afsx;( ~; I# Q6 R: q
assign mcasp_aclkr = mcasp_aclkx;
' \, o b, a+ M' N+ v7 Vassign mcasp_ahclkr = mcasp_ahclkx;0 q8 R( O0 k# h. b$ p+ D
assign axr1 = axr0;
" `% ^! }8 r# K8 A q
4 q9 ]9 Z- R$ i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 o5 b" o9 B& V+ m+ n' ^; `
static void McASPI2SConfigure(void)4 P0 i( k5 x) c) H: A
{
2 q' r8 f4 |' r" O1 b6 @; P& vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 _9 B0 B2 y! X: \. }5 c0 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* v$ Y7 V, R9 {- B# pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: H1 h$ g7 V" A0 n) |
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ C7 T5 X/ T# m$ v* J7 s2 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 Q; w* v6 g: S- \, ~2 Q
MCASP_RX_MODE_DMA);# e5 P! ]) n$ l% s# l" p6 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ A& ^$ k: U0 D% a/ F/ {: `4 I- R
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 d& t; ]6 r. S g3 U7 s/ u# `+ V' nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 O" n) K' u9 `6 A) p B4 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 Q" Z9 n3 P; H% t, ^; y, PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, g" t- f9 [6 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 P' g1 R. ]$ [* ~8 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 T, v6 G6 p( y$ \* \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 t! _- Q6 V, RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& {# n6 X; X5 u& Q5 J9 `) h
0x00, 0xFF); /* configure the clock for transmitter */
: @& x) E2 q8 y$ m& J( EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( ]4 J. i1 o% H+ L2 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' M: F+ H: @" y1 P0 \& Q( m" l5 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) `- m0 Z, }( C' u0x00, 0xFF);
) V c4 `9 E! Z4 {8 n$ V
) y: ~% h p; O& x6 W/ D' [/* Enable synchronization of RX and TX sections */ - w- ]* F' U; x6 c3 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. Q# [9 f- i: pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 r0 t6 g: W9 Y7 L$ t& V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) T8 ^* q' u7 p; U0 H
** Set the serializers, Currently only one serializer is set as. a) D+ b" f6 E
** transmitter and one serializer as receiver.! ]8 D2 u1 o# N5 C5 d- D
*/* W- X* [' R! {; V2 S' Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* V5 I8 P+ A5 y7 p8 Y& G4 e2 ~. X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 M; K5 s: ^- z/ ?3 y** Configure the McASP pins * O- b+ l6 x# g% k; N, L4 w
** Input - Frame Sync, Clock and Serializer Rx3 F- Y: h% I" f
** Output - Serializer Tx is connected to the input of the codec " n/ j# V2 O/ w0 P# r3 f4 Y
*/! E6 @, c# c9 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" M9 x( \4 j3 m* R! H+ [" _0 L% IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, `- a: @$ b% n0 M' b' E8 d, q+ _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 O# ]2 V5 a# Z( @0 u2 X, V1 [ _
| MCASP_PIN_ACLKX% ]6 p0 w" \& }- R0 ^! x3 N. B; ]
| MCASP_PIN_AHCLKX( T3 Y# v/ T6 O3 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" A! T! ]8 C9 W6 F) ~/ t* CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ w8 J! W) o9 g& |8 W! |" a| MCASP_TX_CLKFAIL / t7 f: i, t! [: u6 N" D
| MCASP_TX_SYNCERROR, `8 Q$ e5 s. V3 K2 B x. {, c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# s, T0 i( ]" x5 J+ x4 N2 d6 ~| MCASP_RX_CLKFAIL
+ e6 T5 O4 Y- g" h; k| MCASP_RX_SYNCERROR
2 B0 V% [7 A* k8 k| MCASP_RX_OVERRUN);7 d' Q4 N" T5 K5 }
} static void I2SDataTxRxActivate(void)
4 c' f7 z$ C* h) l6 E; t{
8 Y* g! v$ c& G& S$ T, R4 t. t/* Start the clocks */, V, Y. Y4 Q( T% S7 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ _$ k& z* d3 ^9 I1 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// j3 o5 r; O0 l8 R. e7 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 |( I/ g7 |5 bEDMA3_TRIG_MODE_EVENT);* \. J: A( t' m% v& s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 k( z3 M& K) w& p0 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% p: x* D. C" ?/ G9 A2 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! ~9 S: Y# M7 ^. V4 _3 ~- W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' I1 l% X B+ u3 n1 ]0 T5 r- Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( `; q2 N0 U5 W; E! H: z3 z+ Y, oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- o$ B, Y I, e8 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 y; e) @" n }9 b% @}
# B: C! a* x' [% n S+ d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 v3 S- @8 N+ o, Q; I8 m% l4 S
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