MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
5 a8 u' j8 q' }9 Ninput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
0 x2 Z$ X' z2 \2 L% U1 X) }
# M8 Z/ \7 Z3 }$ G: \- M1 `! T# @output mcasp_afsr,
7 Z6 Z% U: p$ _  r$ Coutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
' _: |1 u( E3 L: Uassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

$ z; x% d; C: H& T# K

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

  }! \& x9 k" c7 ?9 _

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 \* h- N- X" W! Q9 A, ^7 ^4 S1 gMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, U8 U7 w! h* Q- W+ GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 P6 \. ?5 @3 _* ^- jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ E3 p+ q0 S% E+ xMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) |1 }, r% h0 @+ F7 AMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 r5 G' z9 T* P7 c0 E' D! D" K- d8 _- OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
3 L% u+ }5 E  e3 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ D: p9 b& t4 c/ [3 b, T- w( wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) ~) o3 O* ~) f, h0 S; K1 b. FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ }7 a* n/ W9 ^% b- j( P0x00, 0xFF);

/* configure the clock for transmitter */
" l7 B  j+ ^$ Z9 u1 i' MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, t' [$ {. R3 z0x00, 0xFF);
( e* e1 m  {- N' h
) k- W  V! o/ ^" X8 ?& Z/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
, r8 B4 ~6 f& i. d/ H7 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( t0 \" `- c, o- oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
0 R1 I8 T. c" V8 T+ D*/
7 W3 B) J, f0 C* t6 `4 u: ?/ NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
) E6 W( g4 P/ K; V* r- W** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
/ k' F! [& d6 ]' a) A! _; ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 G8 W4 t; a4 E( ^" d9 Z2 z0 A| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
2 V" v7 k2 a8 M7 B# ~( A- F# y| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 {( u. V+ R* B) W| MCASP_TX_CLKFAIL
" [: T0 I/ B4 D, R| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 D, U' d8 d# W$ z9 d0 `  p| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
# `' ~4 [  p: E& u. r$ G: g; M# P| MCASP_RX_OVERRUN);
) l; l) U7 F0 J}

static void I2SDataTxRxActivate(void)
" z, K! ~1 Q+ Y# g6 O7 @( G) b{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ z, @: t6 A$ Q, @, f% G3 Z5 j! q* I; QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
! P( d. S" a% b0 v9 Q2 U: ^) WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 L% C9 Z: _3 W5 k( y& [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
4 i- u# U2 ^+ w( B! x' g  Y4 |+ MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) ^* e( c' e- `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
' Z& W+ J4 z0 {3 R4 X& }* xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
) @* g* f6 a4 Q( B6 x; d7 d6 y, o4 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& z& u9 L. c  qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

1 \8 n1 |: H1 @& p