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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ S( T) O/ k P) I% _( v. ]3 Iinput mcasp_ahclkx,) v( [& T S, i% J7 Y; b
input mcasp_aclkx,/ t' a; E( F* F @
input axr0,% ~$ q/ Z8 `' P$ [
5 M: B5 o1 Q5 h" G, x
output mcasp_afsr,
% Y( J1 q5 y. [$ ~2 @1 Moutput mcasp_ahclkr,
/ [5 m$ ^$ |+ m; j3 M$ ?. Toutput mcasp_aclkr,
1 [2 S$ t0 n; c0 |) |# \output axr1,# @2 ~9 V8 V& Z1 y
assign mcasp_afsr = mcasp_afsx;
( u! D& ~; y9 K6 m1 s5 S0 W' k7 v: K1 cassign mcasp_aclkr = mcasp_aclkx;$ w% v/ Y6 j8 ^
assign mcasp_ahclkr = mcasp_ahclkx;
, K; V3 j) y( s- x+ lassign axr1 = axr0; 2 D" z/ Y+ Y) L: j6 v$ n$ I' K6 {1 I
: \% J6 ?& ^4 |* G, y8 d9 ~5 M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - n: i0 t4 a5 h+ M: l
static void McASPI2SConfigure(void)! z3 c9 O& c. J% ~4 U% _
{
( o# ]7 [2 d6 n; V) z9 V+ T) ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);; U' H; M5 A2 z' S1 {8 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( ~8 K9 W2 b8 a" ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 p8 D3 U; m/ @* c7 y6 bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% g8 m) D) o- C1 V6 _3 MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. X, _- u; D w- {
MCASP_RX_MODE_DMA);
" @+ C! `1 f8 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 Y: z6 d! b2 BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* a$ S6 L: }0 N, e+ X1 _& D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( u1 f& B; A: t A* K) a* S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); ^8 t4 K; `1 }6 k* F& n5 U
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 g: O) g1 J* q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ W: b2 j, l# r9 F" H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) \( N! B, L/ A/ @7 x& z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % P# N1 S* i' M. j- c& g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ m/ j3 ^ U* l' e3 J. e2 m
0x00, 0xFF); /* configure the clock for transmitter */
" [- V( p9 l8 P8 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# J% I8 J3 B! D% v3 |) _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% _/ }, N% g/ e& K" Y; T% w7 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) C4 _0 z+ t8 ^2 S: f" i0x00, 0xFF);
3 k9 ~* X. E$ c' D# u
( p8 X: e. ^' X$ F9 H9 M" r6 K/* Enable synchronization of RX and TX sections */
6 W+ c/ y" Q8 x/ z0 s' r5 J5 R3 o$ ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 c( j1 k+ a( R0 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! Z0 B. l; Y% }$ K5 u: r' J5 f& G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 y6 N# `$ C; y$ Q& W9 s** Set the serializers, Currently only one serializer is set as
% \7 } f7 m ^. a** transmitter and one serializer as receiver.0 b" Q) L+ t1 V+ o
*/" e' O, c# u- F- Q; o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& z, L- G( f% `" q, K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! v, E) V, A$ P** Configure the McASP pins " U o. p; q- P: D3 T
** Input - Frame Sync, Clock and Serializer Rx* a! t! \, H0 L/ a+ H
** Output - Serializer Tx is connected to the input of the codec % l" @9 l- @/ W: C m6 O& Q. B
*/- ~% a7 }% R( u- B1 q6 W4 q0 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" o* c0 l0 M8 @! C2 `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: J- m" d$ ~; E6 }- [& P. @! S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" X2 l4 J& `5 B a( v' H! L& \+ g| MCASP_PIN_ACLKX
( q" e! ~5 ~ g: p/ v8 k| MCASP_PIN_AHCLKX
9 L1 `* A0 N( }. g: N( O4 e. a| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 Z* R, s& Y+ j$ M3 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% Z, w) M" G, T2 q m- Y9 f( K* _9 M. l| MCASP_TX_CLKFAIL 9 |$ M+ R; L0 i2 \/ U& o
| MCASP_TX_SYNCERROR1 }: j3 o- K( x& T! c: x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR a0 ]' A( e! I! ^" _$ @
| MCASP_RX_CLKFAIL" [, w1 y; w+ Q$ j+ l' E. K8 C/ i r
| MCASP_RX_SYNCERROR 8 a+ Z# s2 ]9 f% A3 ^* c
| MCASP_RX_OVERRUN);
0 y4 F! l- E2 m: @3 n0 @; I, v} static void I2SDataTxRxActivate(void)
/ r& }+ a1 k1 C8 f% C{
4 f$ d$ ^4 o4 |/* Start the clocks */7 {8 w4 T* w5 |* @, K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 d) _% h8 T- K2 u/ d. JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 D( k5 K$ |+ v3 n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& p3 l0 J6 l( ]* a1 EEDMA3_TRIG_MODE_EVENT);; L9 H$ N2 U. r* {4 `" m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( o! [+ r2 v8 e, EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, }8 U4 d! ]& U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
L. i. X* k& G7 k! v' q3 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 N4 s3 D: z% k2 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- K( u7 ^) X/ G1 i) b: u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% R! D# u: x9 J) |; JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 V) o/ C/ S0 g7 O6 L
} 2 H. Q; A% W9 ]0 P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) Y' _3 [- n$ B7 Z1 d( R8 n9 y
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