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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( o& e0 B5 ]; U
input mcasp_ahclkx,% @; P F4 u9 W- c
input mcasp_aclkx,! r" p. L( l# y( n) ^: K
input axr0,
- q( Y( P, @! d- N: k! \: u6 v$ n9 Y% O# ^7 @* {# }5 k
output mcasp_afsr,/ v1 `2 K# H+ y7 H8 L- m
output mcasp_ahclkr,
8 `* b8 d/ o( Y# Koutput mcasp_aclkr,7 ]+ k! Z5 k! T1 b' S& h4 ]" ^: `
output axr1,! [) r/ P# u8 y' t6 d% x& z! O; H
assign mcasp_afsr = mcasp_afsx;" T( H2 w/ P3 R" T. D" C; M3 }
assign mcasp_aclkr = mcasp_aclkx; u" U( \8 Q" i
assign mcasp_ahclkr = mcasp_ahclkx;
6 C- U) _3 n. e. o$ Dassign axr1 = axr0; I; A) X7 l, r6 [* Q
& e2 u" k u" \# y0 D" F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & x/ n; ? I B' f) r& J
static void McASPI2SConfigure(void)
A5 d& P3 s7 b& V5 P$ ~{2 h* V& W2 A% v. i8 e3 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 E9 M( v$ u. D" O8 D' ?* ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& v' m+ U7 \ h& b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" p" o* G( O6 l8 a) jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
n* M. c0 i% M3 `3 F/ Q |% r6 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, F4 l" p V7 XMCASP_RX_MODE_DMA);2 w7 d z! W7 F5 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 S& w' e' k7 }2 K vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, _2 A" Y. k4 C8 @" b5 E5 \3 f& z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- X+ F+ Q+ \7 j2 H8 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( a5 L! U4 p( S" [2 {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
D, ^7 |8 x3 U0 |* L2 WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: R o; X! e0 L6 H8 n) m! DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' N3 n* s8 m/ w' j5 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 ~: {) x/ F \% ~4 J8 G2 D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
I6 d/ N$ J/ V& r3 N3 J7 X0x00, 0xFF); /* configure the clock for transmitter */
& y- {* Y- M$ K- m6 p$ Z1 Q& sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% I% [8 j. L5 ~. y/ SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( \7 I0 D2 k9 _( v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( J7 W) y0 A- u T6 J8 ~! L& h0x00, 0xFF);' f+ \: Y* _( @1 ?! c
9 c5 _) x( Z7 D9 r( z6 x
/* Enable synchronization of RX and TX sections */
2 Y+ l s% X. \5 n* [( Z4 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 ~. Q0 \4 [7 I, ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 M4 f2 U- l2 w3 J( U, W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# ~, ^8 W6 j- N1 i1 ^* G** Set the serializers, Currently only one serializer is set as% B) N# }! L- }: J& X& b7 a. e
** transmitter and one serializer as receiver.
1 i: W- O" Q" O3 H/ O+ I*/! ~1 [ z" @1 J4 ~( P! u8 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# N$ {3 f8 E6 a) C0 G6 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 \4 }- P% ?7 a0 c; j
** Configure the McASP pins 3 ?* D; j! C4 G/ W* r" D
** Input - Frame Sync, Clock and Serializer Rx6 N4 D: L# c8 i9 u0 N" z4 ^( u
** Output - Serializer Tx is connected to the input of the codec ( V; } ]& A3 l( V- a/ x d1 I
*/
- q4 e7 c6 v* \ N. e$ d% H- JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 o# @' u1 w- Q- |* C' R* I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ s9 I) s& K( }1 h" F* g4 q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; V4 y! I! D- p# t! h7 {# V3 L# q* G
| MCASP_PIN_ACLKX2 }( y+ B! W1 `4 N5 d# ~# n
| MCASP_PIN_AHCLKX% e1 L; u* o r: ?, p5 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 w, n r9 R# A: G/ R" V) M* f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 @2 a( E' w0 i$ @| MCASP_TX_CLKFAIL : Q, l3 v8 l1 r
| MCASP_TX_SYNCERROR& `7 T: n# V' z4 ^6 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; Q7 B& G+ M- ^6 A; Y1 [' n| MCASP_RX_CLKFAIL+ |# w5 E; \3 ~( E$ [, f0 f: B
| MCASP_RX_SYNCERROR
q! g1 w, c. K) V! F| MCASP_RX_OVERRUN);5 m: C, C% \& X' }0 |
} static void I2SDataTxRxActivate(void)* i$ |5 S& O' y$ Y- t/ _5 g0 R2 R; }
{% M$ M9 Z! h j7 F8 }6 r5 z! H3 E9 ~, F$ r
/* Start the clocks */1 l8 H$ t: y6 [ _2 Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ {. u5 ]& b; ~# H4 e7 p' l3 O7 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 t3 U M5 y& I) P9 D' S/ V* ^8 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: }2 }8 `! Y# @0 c/ L i" n$ C1 |EDMA3_TRIG_MODE_EVENT);
2 u9 }: X9 D' j3 n% k4 g5 o. o9 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; h$ D U, \" I2 f8 F6 M; `- F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 r# y5 `% ~7 k( D+ IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: Z- N/ U7 Q2 q! L( I% y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ H" g+ O/ f \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. d v' D0 }0 P k- d) H2 A9 XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" @% @' K6 E8 x7 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% j6 x( Q+ ~7 I. b$ C
} * c2 |3 L" S$ A' \( Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - m' l4 l8 ` N" ~0 P0 i z
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