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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 W, y6 i* D5 y8 P+ t! d0 c$ minput mcasp_ahclkx,3 J$ ?. P% g) Z; _9 \# t# f
input mcasp_aclkx,
6 w! n% Z6 V) t. Pinput axr0,
( T! p# @2 r- ^$ o, z& ~9 Z0 p( N: D; g. `1 J3 K, q
output mcasp_afsr,( l3 D# X6 S7 d y
output mcasp_ahclkr,
) x0 U) R h. y5 _output mcasp_aclkr,
4 F( k" c( q H0 v( I `, |output axr1,
! w) ~# Q9 e7 i assign mcasp_afsr = mcasp_afsx;8 y* L% I- o$ C7 C( v7 e
assign mcasp_aclkr = mcasp_aclkx;
3 P% p/ K1 A6 r& y4 `, K$ ~assign mcasp_ahclkr = mcasp_ahclkx; G% e0 o, m9 v+ @
assign axr1 = axr0;
5 i2 v" P+ F8 `% \9 W" m& v" O3 |7 h" ]8 R8 t/ M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ X1 l1 A# C. g/ Mstatic void McASPI2SConfigure(void)
" Z% \8 Z: D; }; i. t- z5 V{3 D' `. o$ H% W; R/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 c6 o- A5 G" Z" Y. m- H; z) V1 |McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: d3 c" l1 E' a! x' y, Z. S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' }7 c5 R h2 |% [( S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: c8 z% r6 [5 B* {' X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# Q* k! [3 ]* E( k4 c/ A. @MCASP_RX_MODE_DMA);
/ Q0 J; N B5 O+ B) s7 o: iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ U: F9 \$ y3 l7 S6 [ t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# w- x, K0 X/ y# s4 K5 T+ R! C& n: M: N
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) q* M3 `5 E% q2 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; u1 F3 O" ? `; S& ^6 g$ O8 _+ D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & N$ g6 l6 ?/ |' k7 Q2 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' h* S- l7 A$ _# v0 \; Q1 l- u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 T7 V, x' ~ m/ aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 q! D2 e( A( x9 S1 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( y& z) I+ e& a6 s* t
0x00, 0xFF); /* configure the clock for transmitter */
' Q! U6 q. R8 r4 e, ?; P, kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ m" t) d5 m. T" l; q; n. }
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 [' f2 Z. L0 l) y4 P& U; i! eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% w/ g- z" R* X+ w% P2 E0x00, 0xFF);* i& W" r5 |% J/ [
b1 f/ g; O, K! b ]
/* Enable synchronization of RX and TX sections */ ; P- g" O5 z8 Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 g1 l: J3 i5 C$ IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# @1 k+ P" u( c6 [( s7 b( C# s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! `0 v2 \/ C* W3 X# h3 R$ Q5 E** Set the serializers, Currently only one serializer is set as7 M, \. Z: t8 R Q% ^
** transmitter and one serializer as receiver.' d, k( C* z+ D& {: q) v9 w% S
*/
% m8 y, ~' |+ M$ e/ dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ K; @. T- |; S- y: p a7 x# K1 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! _$ A$ y+ b1 f" E& d2 J7 l. D* w
** Configure the McASP pins . Z; A1 v& L- U$ ?; t
** Input - Frame Sync, Clock and Serializer Rx
+ G; L+ g; T, K' _. p( ]! w' @** Output - Serializer Tx is connected to the input of the codec
U' B" Z @# T5 V*/
2 Z1 G4 g/ K- k iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 j7 Y! _" a9 DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) F2 l; f' D" o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 s& p1 f5 ]; H1 w" G
| MCASP_PIN_ACLKX
6 Z- g6 z+ }# e* f0 {| MCASP_PIN_AHCLKX G* a- {2 E& S: Y" X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 }7 e& Y3 n9 E! ]0 j! k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# Q7 I5 B- E4 M| MCASP_TX_CLKFAIL
: q/ B9 M7 ~9 U8 k- l) S1 j| MCASP_TX_SYNCERROR! r: N3 J* ?0 `! Z. s t& m& |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 Z+ t( j" T, c' P) S
| MCASP_RX_CLKFAIL
# Y8 W8 b7 i# [0 P' w: d| MCASP_RX_SYNCERROR
3 |3 ^# x S* K| MCASP_RX_OVERRUN);% y I3 _/ f) ^+ S0 D4 \% y
} static void I2SDataTxRxActivate(void)
/ |1 N' ]$ T- Z9 p, G! K! C{
9 ?8 h% i+ F; f3 o1 c/* Start the clocks */! u0 k5 D5 B$ r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 c) J" V0 X: ~* D' L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- L2 a' b% R6 {( G% m$ D5 _6 n7 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- C, l: H1 C1 v- l1 ?5 O; L) `: OEDMA3_TRIG_MODE_EVENT);
; ]$ c0 G, u3 l! h/ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; F+ x3 K3 P4 o i, j0 j& _( u- eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! E( a! q+ f! ]# }! f5 H* T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 X; Z. N! X/ G* H6 e1 s; VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 {; N2 b- s: z% t5 Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 Z U5 Y, W( E+ }5 S0 t; a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); d) W+ `9 o% l& ^% o" K# b* L% U, z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 V3 q3 X3 v) j! s7 X
}
5 a+ R& q' ~: @4 l" R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; k# L+ v8 h! `$ s6 V3 `
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