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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ S# t3 }' H4 s2 g6 Hinput mcasp_ahclkx,- ?3 r; G) Q9 g# v q
input mcasp_aclkx,
- ^7 _3 }- u8 Q" S0 finput axr0,
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output mcasp_afsr,
! ^2 \2 |4 y' _$ g3 Doutput mcasp_ahclkr,
" H3 I* B& g5 Z! U7 Z5 Woutput mcasp_aclkr,7 s# u0 h! W/ ~; P8 @
output axr1,1 O/ y2 u1 q0 b1 D) @6 s2 x/ v
assign mcasp_afsr = mcasp_afsx;
% t" D$ {- g/ n6 {( ~assign mcasp_aclkr = mcasp_aclkx;
4 E' X$ P2 `& A1 @/ f9 g( nassign mcasp_ahclkr = mcasp_ahclkx;. m9 L$ T$ B) i# {1 E7 O7 [, K
assign axr1 = axr0; $ V+ [/ z" U e
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 K$ i2 H4 }( r& h5 [% n8 Hstatic void McASPI2SConfigure(void)
+ U* d: ^! p& m; f$ [# S3 a+ |; r{
$ r1 V1 \5 Q2 r0 M" B, EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 n4 d& @# O+ A: q; S- T' T5 H8 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 r" z. e! z# G: r6 d+ C- g4 A. x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! E( O! n( j. D5 H9 Y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 h" d* x; L8 r. o$ T/ G! c& C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% L% j! Y& l. D8 J6 kMCASP_RX_MODE_DMA);
0 N8 e# U- t1 F5 P" m! i! N v! q M" JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ s! b3 H! M2 {) o4 b) O" {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 v+ @- ?' ~* o/ u; a8 n& F: Q( i0 G8 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + e6 K- Q5 e$ t+ C& i, `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 h* s2 L$ n1 c! MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 b8 G7 z2 ]% j) NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 k( q {' E9 o0 hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( d) W8 ~. z7 ~& }+ [5 y1 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # @# m. J m$ l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 a5 d1 Y% |; J: i
0x00, 0xFF); /* configure the clock for transmitter */. W" A/ E3 K9 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" z7 l/ V6 T; H- g+ RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 L: _3 d, T w& A+ u4 Q; ~6 A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! y+ @" E- | L; H1 i% v) J0x00, 0xFF);
! P# e/ b% X9 W! S5 @
% H# _6 \/ f4 [/* Enable synchronization of RX and TX sections */
& \, w: z+ L- sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 B+ A! n7 z6 W& {! z! g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( L1 r/ Q7 W, L" Y6 T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
w& O* j) U. j: D3 c3 E! E** Set the serializers, Currently only one serializer is set as- z7 ^# j6 c- P$ m L9 C
** transmitter and one serializer as receiver.
3 S* o/ [# K6 D- c( Z1 k*/+ e. M2 B9 c. D. ~' J$ M5 Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 r0 n% R+ [2 M5 n/ ?3 z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: f% _% o4 M# A8 B2 p& {( D** Configure the McASP pins 7 y( M; n8 e* v. i" u. W( T
** Input - Frame Sync, Clock and Serializer Rx9 W/ @5 a$ w& N' a( S" \
** Output - Serializer Tx is connected to the input of the codec
8 y6 I3 I$ I# D. p*/
- n+ D0 q. P& G" V7 ?$ H2 ~McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# C* ? B+ A6 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: `% B" e' V6 m2 V# G* D2 |, I7 B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" A+ R- g. z9 w6 _1 R
| MCASP_PIN_ACLKX
; p5 S7 Y. b G6 i& B| MCASP_PIN_AHCLKX- |6 \5 Y0 g* b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, a+ c( X3 `* a, y5 U, m- { f( mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 i) b- }, L0 ?; _: l2 s$ C6 a
| MCASP_TX_CLKFAIL 8 i4 e- G! O/ n/ o; D( M: Y( [1 G2 B$ e
| MCASP_TX_SYNCERROR1 S/ B/ i$ `8 K0 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " O; j' c; `$ F! m) r7 m0 Q
| MCASP_RX_CLKFAIL" Z$ q. t) V' M P" P& L2 a5 H
| MCASP_RX_SYNCERROR 4 B$ [7 @9 [. D* W P
| MCASP_RX_OVERRUN);
l4 ?4 G, j( R+ P$ [} static void I2SDataTxRxActivate(void)
: ^" M- b% {+ {8 E. K{' b# h k! \! c6 C1 [! j k
/* Start the clocks */
$ i& `& L2 ]0 t' s- {0 _' Q* MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 t& p, w/ r3 g& ^! c, wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 n: N8 O( B1 P* ?9 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ I- V4 z1 m1 C. @9 ]+ y1 w3 dEDMA3_TRIG_MODE_EVENT);2 ?3 y6 b, B% ~0 ^5 e4 x. T5 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # B% i) h) m$ O, i- a* M( A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' [# y# f% G4 v: b6 g0 s! ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! \! w B2 d( ^" w9 y# TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' `+ _* N2 {+ j2 i4 D( G; swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 z. t, i8 ~8 R1 T+ K, c( D& |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 Y) O) M: w) q: n) T1 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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