我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, @# z# |! O ?% Y" P; g" u- Y
input mcasp_ahclkx,
" j2 O: r: H, |9 D( Q& `0 z9 kinput mcasp_aclkx,
+ {& Y: \: Q G3 T0 I a+ V2 \input axr0,7 ~/ _1 I$ R% T, m X
6 x" H/ a& w0 Y$ d8 ]; Youtput mcasp_afsr,- V+ J J5 ?' k: m
output mcasp_ahclkr,
0 l( j" w J' g/ x* }output mcasp_aclkr,
7 c4 ]. o4 E& b7 ]8 f$ ~output axr1,9 S* m) M8 s1 R- j; N' q* B
assign mcasp_afsr = mcasp_afsx;
! T7 h8 x" p% i5 hassign mcasp_aclkr = mcasp_aclkx;6 s! ?: v4 W9 n0 P: l
assign mcasp_ahclkr = mcasp_ahclkx;8 k) c' ^+ W# _" X$ w3 {# U
assign axr1 = axr0;
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: O; {1 o; o5 ?5 d& |; e7 \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 m" A" b; q& B* j: D" U- _2 Istatic void McASPI2SConfigure(void)" @8 x, l3 A8 F: q
{
8 e& Z/ d/ }7 R8 s& OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ F/ W, x$ [' G) J2 h7 S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 B/ o/ F' V$ a% }& R# d G/ s5 \) N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& m. x7 [ g/ z) p4 l$ l- R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 l9 a- a( b& l, c: ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 A# A( j& `$ F0 g7 B4 l
MCASP_RX_MODE_DMA);
- ~) Z: ]9 o: m+ q) t5 k" bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 l. ^6 Z0 Q3 k# d4 b$ bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# h! Q8 T6 F: f, T( rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + ?. I" b g# _: L% [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; c$ Y5 X1 \1 N" L+ q& @/ @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" c5 d \! F/ m) o# Y7 ~/ nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 D' F# L* L9 O9 m7 y/ ^7 o) z q- w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' g3 M( S' I& A0 x+ d2 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * Y+ i( N/ M1 b6 K$ Q/ ^2 O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# o6 z3 ]" p7 j) A& j+ n0 s
0x00, 0xFF); /* configure the clock for transmitter */
9 ^6 Z0 t) Y9 Q: x4 K+ B* ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' M% ?( o: Z D9 j. `5 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( L+ \. u8 |4 [5 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ e6 w* u0 r: d( p3 x5 V: z( B7 E
0x00, 0xFF);
: w& l) s& H) r( j G! Y) i0 \# L& ~! B; Q- i: a
/* Enable synchronization of RX and TX sections */ " q1 x( P& F. T, K+ _8 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- B6 `, ?, q u8 |4 I+ hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ O+ q7 N9 Z& ^0 \' f; n" kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; a% e& |/ O2 x- k9 M
** Set the serializers, Currently only one serializer is set as. _- e: D' W& ], i8 U
** transmitter and one serializer as receiver.3 j6 z- I- M, r
*/
/ Q9 _- Q: q3 o1 VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. ^/ u F2 ^2 \$ m, c6 T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 d c$ ^4 _, A+ f7 k( J
** Configure the McASP pins
3 s1 s! ?( H2 ?1 l** Input - Frame Sync, Clock and Serializer Rx
m4 Z7 v0 }0 h8 l. k7 y$ j A/ I** Output - Serializer Tx is connected to the input of the codec 6 S8 m. N9 ^: H3 O @0 ?. l" z
*/
5 ~ r+ c$ \& B; CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, A/ d! F2 |5 {9 U2 ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( j4 C* ? X. W4 B# U* T: V2 L5 V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ `" [& U6 W/ o. `. u, D: V
| MCASP_PIN_ACLKX- ?5 q- t; `+ q, R/ ^) d( C
| MCASP_PIN_AHCLKX
/ V. W; F) N5 P9 f0 k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 d3 J ^) |/ n9 ^; [- z+ n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ E" L; Q5 W o& ^/ S| MCASP_TX_CLKFAIL
4 g7 z* x7 q/ m; ]6 ~ c- |8 ]| MCASP_TX_SYNCERROR
' a) K8 P* l9 i& |# {$ n4 k" z1 j' ^| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& b" C, h+ `$ O# m8 ^. F/ Y. Q) q| MCASP_RX_CLKFAIL
- X# {) l: ]" ]! v| MCASP_RX_SYNCERROR u* ]: O( K& F; t0 D
| MCASP_RX_OVERRUN);
, Q) R, U! s& m ^. ^& H% c} static void I2SDataTxRxActivate(void)2 }8 R) D+ i1 K5 {+ [) ]- b
{0 ~& h4 N' _ v2 x+ o
/* Start the clocks */
* e7 W( T+ Q! d1 f; s s! ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
D) |& Y8 B1 ^8 w C: AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 l8 i* m4 C% {1 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 u, O# b" @9 }( \4 J; X% ~. K
EDMA3_TRIG_MODE_EVENT);
4 R5 ^1 L& c) i9 \6 _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) R7 D1 G( Q! o! p* ~1 _9 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: Q% Y N! L9 I7 M% e4 W+ [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* A. B# r) g2 z/ c: aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% Z. ~! y/ f/ n0 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 O3 K2 X$ m1 e2 e/ IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; H P2 D c ?+ n3 Y+ D3 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. ^" W0 o8 s8 ^8 `$ W
}
X1 o+ s* o2 P$ w3 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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