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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* g. C3 ?8 J6 |# [% e( p$ iinput mcasp_ahclkx,- I& L6 \2 {5 i
input mcasp_aclkx,* j5 J7 Y* o4 l
input axr0,# p9 u4 C& d6 f8 _3 T
4 l0 E: @# b" Z6 |- z/ p% ?output mcasp_afsr,
0 m1 g. p% {5 n0 ]output mcasp_ahclkr,
# b, S( s6 |9 ^$ Coutput mcasp_aclkr,
, b l4 |6 n ~9 Uoutput axr1," c9 F0 j" M1 N5 x
assign mcasp_afsr = mcasp_afsx;& Y+ \3 l8 p8 j3 g$ W
assign mcasp_aclkr = mcasp_aclkx;- z/ C0 `: l# y
assign mcasp_ahclkr = mcasp_ahclkx;
7 X' ~5 _; w) e- zassign axr1 = axr0; 5 z- X6 I& |$ C
1 u8 i' H* ^ g( \" G6 G! L m2 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ a$ _( V* b% l% ]3 Lstatic void McASPI2SConfigure(void)
) X3 F; z H/ |! b c$ J7 i{
! v, s ], o7 y F1 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! `# D& a& Z) r& K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 i: |) s4 t- jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" a1 n! [8 q8 T$ L* C G! LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 x H/ Z% S: m8 x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) g8 w: }7 X* @$ ^) _) b9 r7 f
MCASP_RX_MODE_DMA);
1 z# _, T! C1 G5 e1 \9 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 s; W& `, A9 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& o3 u7 y' \; C5 F ?7 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 a3 P1 Y' \6 m9 {( B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ x' ?! f) Z8 w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 o1 C! l4 P& T% E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: Q! M' L0 I k& GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 I+ [) d5 g W( O; U. k* J; i, X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 |% s* P3 i; WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ u3 z$ a+ v& N/ n0x00, 0xFF); /* configure the clock for transmitter */
$ d1 A S! |' E0 C5 eMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. o8 q4 N$ F; kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 ]- w$ \) Q* L2 v) A/ b6 pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. u( T) _0 G; W5 W1 w0x00, 0xFF);( z. `: f6 n% l K. G
: u2 @7 J9 C! V, L2 o/* Enable synchronization of RX and TX sections */ 3 A! ?1 m2 d; c. {% B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! Y8 S2 p4 M! W+ ?) G5 j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 o4 C+ k& j" H9 K n; w; y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 z' }& P3 W6 a( j4 `& z; w+ T
** Set the serializers, Currently only one serializer is set as
. I, m/ y1 q, s0 s** transmitter and one serializer as receiver.
& z* r7 X, I$ o6 w9 z2 W5 r. f*/
4 H* |, K& o9 S8 w9 c( c3 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& G7 e( b5 \' b/ \4 M2 [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 W% }! `" _0 {
** Configure the McASP pins , ?, h6 T! G- M! M8 W# f
** Input - Frame Sync, Clock and Serializer Rx
6 q- E8 {$ M D1 f, N1 [& r** Output - Serializer Tx is connected to the input of the codec
9 O7 \! ^0 _9 E* g4 ^*/
: ]0 [- b+ m7 S2 X& pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: t6 c i% m5 e: lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" K7 ^' f. p' E9 W, b3 D. c% b/ S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& t- m/ R U; T3 d8 T
| MCASP_PIN_ACLKX2 @! |2 U/ n1 z" l/ a% X
| MCASP_PIN_AHCLKX1 f0 @# n( O9 l6 @2 x8 A) p, o
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ r: d: L1 D: H3 E7 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ ]* K9 `. y: g/ Y| MCASP_TX_CLKFAIL . A! G; E8 K% O, w
| MCASP_TX_SYNCERROR y* e3 G, M0 |/ L2 m' U* @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - j8 D( z N4 W7 l
| MCASP_RX_CLKFAIL
/ `% V. I0 [" a6 v, Q- g6 @1 c# ]& u| MCASP_RX_SYNCERROR
) A3 m. \1 V5 W& x: T| MCASP_RX_OVERRUN);
9 a/ A8 [# Z3 z& }1 e} static void I2SDataTxRxActivate(void)
4 N% N- N+ G3 E2 v+ C% h. P6 N{7 l% D$ [- y$ { _+ w9 _
/* Start the clocks */
" W. ]2 {( s* C8 WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. G6 {' O1 ]+ j- r* ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 c! n; Q* M% j- Z! s9 d8 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ @& y, Q2 z$ X2 x5 S! ~EDMA3_TRIG_MODE_EVENT);
( g6 V" |1 R- z4 K$ k% HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' a8 w0 L) l8 {0 t' g/ c* |: ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 M' N; D2 v# ?! JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. X1 I0 v+ }8 r7 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 i% F! k6 @6 x. F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 K& a6 E: Z! @) A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 ^2 h! e( e6 I. p5 ~6 \) \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% u8 V; Z( q' |: D
}
! C* J* A- V& b$ ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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