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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! f" L$ W5 v; w1 y
input mcasp_ahclkx,
) s5 Y- y4 x/ `$ D, G: |6 Uinput mcasp_aclkx,& h7 \4 f% _4 g# ~
input axr0,' J- ^# q2 V& ]; `
! v; l! s3 x( ?* f6 L
output mcasp_afsr,1 w. `. m5 F, ~2 G# O
output mcasp_ahclkr,
- y9 R+ [9 Z2 T8 n8 Z3 coutput mcasp_aclkr,
. I7 N& o6 S! {$ |output axr1,
6 c2 g( x, d; s; ]0 C% i& Q9 W# ~. c assign mcasp_afsr = mcasp_afsx;
! v0 ?3 s0 n, T# s q2 B9 M: W5 {assign mcasp_aclkr = mcasp_aclkx;
" W; K# g8 o" Hassign mcasp_ahclkr = mcasp_ahclkx;
3 F7 \. C C2 l2 q- Z+ ~assign axr1 = axr0; ) h" E! J! b; x
0 W/ u5 U- p3 i2 N9 C m' M" V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( f3 F3 T2 @ i1 ~static void McASPI2SConfigure(void)
0 K; l* h, M9 W0 g) S{
( O, o9 t M& w) z G' }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; q9 C' e* E9 ~# d5 l" D" VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 R: I7 w- p: R2 JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 L" s( u% ~3 p. s" H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- d: L/ S# o* ?9 A; a$ m6 f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ ]6 W$ i5 y+ f+ e- v6 _* mMCASP_RX_MODE_DMA);, _# {' g, c+ q. W, M5 U$ z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' m# J9 t @: }; {6 G$ {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ I- \* Z" X' d/ I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 n* R/ k* ] q( _5 Y6 ]7 q; _( k n& QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% t/ B( H. @* {. hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 Q) o' }- c% U4 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% A$ G) n, {4 w, w) S+ j: h$ `& NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 ^+ h5 v9 `8 k6 c1 d: DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * [: b9 p; u! D* U" V, x' k5 {2 ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, |9 E4 I& R" f; e6 [0x00, 0xFF); /* configure the clock for transmitter */+ O0 T( p4 N9 m7 z6 @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 Y: R% n% ?0 r) I" m8 |+ |& [3 ?( t) pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ Q1 K# s! B& ]. `+ }% BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 t% A/ K- A k: T- W# V0x00, 0xFF);' o6 f. O3 r7 c* z% l+ }) P* F) ?& r
, @' h# e3 E* i# ^$ q. `
/* Enable synchronization of RX and TX sections */ ' A. Y2 K j/ g8 h1 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" G7 \8 M2 P9 r' T; a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ |3 Q S5 D5 {& [6 p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! y( R1 G. \7 h& |** Set the serializers, Currently only one serializer is set as
! E: f% ~! D7 G# J7 _** transmitter and one serializer as receiver.
$ p; q& |$ x9 E* y2 u5 d5 V* \*/' ^! z7 i* J4 E* U! L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% U5 z6 H3 V+ g/ R" qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 b7 D4 w0 U+ [; B, d( h5 e
** Configure the McASP pins ! a1 N2 ~% T5 x( H8 q+ F9 n# \+ u
** Input - Frame Sync, Clock and Serializer Rx
5 U" x$ g* R9 ~" Z0 e" Y* J** Output - Serializer Tx is connected to the input of the codec
# l5 c+ M& ~8 _# f" ~*/
6 k' Q; C0 S" ], u% gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 ^' w) s* D8 l* Z+ N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! }% U8 E) }% ?2 Q+ i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ ^! b1 H3 F- `+ F6 y- L/ u| MCASP_PIN_ACLKX
! O8 V( }, }/ [9 M2 {% c" c| MCASP_PIN_AHCLKX: C7 a- m8 R' R/ R) M' p* k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 C: F& [- q l; j* v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" y* X) Q0 f# l5 I' H| MCASP_TX_CLKFAIL 4 S/ X* U q, |/ f
| MCASP_TX_SYNCERROR0 `, t6 e* r$ W2 E; p2 m" t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % |+ c( L0 u! q" c9 k
| MCASP_RX_CLKFAIL9 T* u3 E8 M0 a8 F" z4 u) K; P6 w
| MCASP_RX_SYNCERROR
$ j# Z7 c0 p6 r1 E| MCASP_RX_OVERRUN);& H: N4 Q/ A# b8 E+ W* L, q
} static void I2SDataTxRxActivate(void)
, ~7 Y+ ]. C0 C{
$ g" G" I2 D/ n& z/ Z H2 B# P/* Start the clocks */
' n) c5 z0 G8 P; p, [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; ^ p D/ Z `1 w* R" b0 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" T3 h; s3 V( K, BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 L8 c9 ?9 k! W6 U# `* {9 _EDMA3_TRIG_MODE_EVENT);& V: t0 K8 f# Q0 Z2 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : m4 z0 Z1 J! i5 Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; j y; ~$ B5 w# Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& [, A9 r+ H( {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 ]; K. E2 F! g& S- }0 o# q s+ C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 o A# s% I& r! S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 r, M4 A% n% `# ^7 _) F- d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- g! I! ^! Y+ n# [}
: N7 L$ ?( ]* a S& ^9 q+ l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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