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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! ~/ x) |8 q6 o* Zinput mcasp_ahclkx,/ r( I1 a, D- G1 w
input mcasp_aclkx,: Z9 g N U) w1 o$ b3 X, k/ D
input axr0,
$ j+ o" ?8 ]* h7 r; c' e0 W A( T% A9 f8 s3 N5 h7 ~
output mcasp_afsr," L# F. ~3 ]+ m# e6 p8 ?. e& Y
output mcasp_ahclkr,
0 j. W, }# @0 J( Ooutput mcasp_aclkr,
3 R. J0 R) b0 X2 p5 koutput axr1,
& O8 }& P' P% M6 d4 r assign mcasp_afsr = mcasp_afsx;1 p8 A, S/ i5 S( x4 L$ t
assign mcasp_aclkr = mcasp_aclkx;# D y; f3 d r% h) N. u% A
assign mcasp_ahclkr = mcasp_ahclkx;
: r7 r' i/ s/ g' {2 M8 `* F2 _- Aassign axr1 = axr0;
# `0 C8 e2 h& ?' f* O/ ?$ C& e/ l; w$ g. A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) Y0 N6 c% F6 V- W: h. ?; ~- k1 w
static void McASPI2SConfigure(void)& t4 h; s1 q, v& R7 R
{
6 i# d# v) _, R& [' O* u1 }; \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: r( W% }0 J) L3 W& `- j% sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 a+ [% V4 s$ _5 P( z8 M3 H: uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& L) V( J7 ~# V( L) a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* e, a" E+ y3 Z* Y) IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 e7 s4 }6 w5 O1 ]7 u6 {# C
MCASP_RX_MODE_DMA);
& ]& N8 p, c6 c; i) IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: i# b# l, V' |+ F* L+ K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- e( l3 n J+ Z( [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 c2 X; ]/ @ A& |# HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) [- O3 a! k! I4 F/ C4 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 |, e$ Y+ ]$ v3 t$ N! B& @% T
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: u5 ?0 Y+ y! `; b- NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 D6 r0 N! A/ `* g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 J. G/ R! y* \3 \( L8 nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 p+ o# h% N" k" f* |2 a0x00, 0xFF); /* configure the clock for transmitter */
1 W/ v. W4 r+ m* `3 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 P0 D# L' J SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 |/ D+ z6 ~. i. BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- h# A0 X% |) Z. n& n0 o
0x00, 0xFF);7 x" k4 @1 K. C% n% k
8 V, v; W; V; U' J/* Enable synchronization of RX and TX sections */ % M2 l) k" u1 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 @3 A R! f! I: R E5 Q/ I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, s5 G' x. K `- @3 C$ ^% f+ J# HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ c8 O; [0 N* i/ Q8 \0 I4 l- Z6 j
** Set the serializers, Currently only one serializer is set as. L: C9 w2 C# D1 h
** transmitter and one serializer as receiver./ @' x" X/ S1 r0 }! t
*/
* r8 P2 B$ o% \/ p* |+ J/ JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ E7 L' b) d& p$ ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 I! T1 |# D/ s2 r** Configure the McASP pins
: ~' l$ U3 \# P( ?* o** Input - Frame Sync, Clock and Serializer Rx
+ T8 h1 U' |- A x/ N** Output - Serializer Tx is connected to the input of the codec
7 d, e& ?$ a/ G, C*/
6 i e1 s) s( H* h2 d6 n3 jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& G& V' {6 G$ E, ]: O' Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) y' e( f. G* f. |! EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' r3 ?7 X, p) k4 H. q' N" t| MCASP_PIN_ACLKX! [+ b: A. Z: R: y& W; [
| MCASP_PIN_AHCLKX
# a0 H/ r4 x8 q# l/ N, C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& B( y0 }0 P1 ]* uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ p+ z2 Z7 g& i! F K| MCASP_TX_CLKFAIL
, P' \* F) r! v| MCASP_TX_SYNCERROR4 H1 Q9 _' d/ K& B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 Y. Z/ u8 i F3 l M0 k4 ?| MCASP_RX_CLKFAIL
5 }* a8 a3 R% x- ?9 P4 W, h1 N| MCASP_RX_SYNCERROR : p7 p5 o1 ]+ s, W% Q4 C" K; H
| MCASP_RX_OVERRUN);+ b! d+ `9 Z% Z, P# V
} static void I2SDataTxRxActivate(void)
" ?" \9 f" R: g: d{1 @, r/ ?" Z, c6 e
/* Start the clocks */
8 B3 ?# Y7 V0 s6 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 K6 T; K; @* y+ ~1 v! [' w0 b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ `9 m( n" ?+ [: B" G5 |' A9 B! \8 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; a. w% y; [+ V+ }* H9 v$ VEDMA3_TRIG_MODE_EVENT); O1 P; U, a, a5 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 u( g5 h. ^4 X+ y, p) x7 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- | \7 F( i# T! Y9 D% y; s9 K. XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- [0 j& ~8 x( X8 d% g4 ]McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 f, _3 t8 A- L' {+ @& D* g7 ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ Y. c5 v) ^4 q3 |5 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. J4 p0 ~ C. f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) L3 D! R3 U* d1 f" k
}
4 F) B$ D9 a. L0 i/ y8 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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