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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 \* O, C7 O% ?
input mcasp_ahclkx,: B e4 J }( L: {
input mcasp_aclkx,3 O- r$ m" f& Z- P* A9 U
input axr0,
& F: j" g! ~4 x& l% [4 x5 e/ g8 W( v7 R, t9 q1 ~. E
output mcasp_afsr,! {& N4 e1 Z1 O5 `
output mcasp_ahclkr,
& r/ N7 e {& H, B) }" Goutput mcasp_aclkr,6 ]" x. F, P' {" S
output axr1,8 Z* n# c( S& i6 r1 T
assign mcasp_afsr = mcasp_afsx;* a3 Z6 N9 \6 |/ [
assign mcasp_aclkr = mcasp_aclkx;
- b' Q& m) J& ^6 p. N0 Fassign mcasp_ahclkr = mcasp_ahclkx;
; S p- [9 {0 ~, a- _5 kassign axr1 = axr0;
# Q L$ o/ Y- M% `
2 I( Z; k* K! o, p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ y, I& o- A& b4 J# y/ }static void McASPI2SConfigure(void): M$ ]' Q, P, W9 T* I- m1 W
{# e3 `* G" m; t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 U* ]5 U- V, H0 \2 h# @7 g$ T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" o$ C, S$ }: h# q# iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 q' c0 R: C' J8 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. `& Z- j, H% `8 V( ~1 o$ j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 S& F2 `1 a) m6 \
MCASP_RX_MODE_DMA);$ @% Y, O+ |8 K5 Y8 N. T/ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; V# v |$ e0 u$ `- a& v8 u0 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 M# n" Z$ [; Q3 ?% D. `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + @8 |9 z# h: w5 P S* f5 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' c% o6 ]; F v6 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! R& P+ E. r r! S# _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. D, R5 g+ l. M9 v' u4 @ UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) |- e: q8 ^* D, p3 S5 G
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 ]- A3 l$ A$ I0 M6 H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 Y" x( T' N) ~% g& o& C
0x00, 0xFF); /* configure the clock for transmitter */* U8 |) V" h& H% J2 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 `& j9 `9 c! G% l1 RMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 G& G! | o1 _; E& p, M% m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ g! |1 b$ {, A3 y8 I0x00, 0xFF);
2 Y( C! q7 y' V/ `, M3 m' p5 S W4 |: M# \* A/ h& A
/* Enable synchronization of RX and TX sections */ T1 Y+ H1 _5 {3 ?0 R6 N: w" `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ W9 u' j" p( v. v7 aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 I7 P- T( d9 {. k) S4 r+ b) JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 A% }# v& b# N$ P) d
** Set the serializers, Currently only one serializer is set as
8 _/ s N; B* T( M5 N; h** transmitter and one serializer as receiver.
. B8 W. r7 d+ P4 k7 e3 L& U*/+ ~' A1 r% z3 D+ Q6 c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); r# f) J- F" B) h6 A+ ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% w+ C4 p" U# [! J0 v# F: A& g$ p
** Configure the McASP pins
% a) c6 X" E7 j9 X+ p3 B** Input - Frame Sync, Clock and Serializer Rx
, d( T6 j% F& C; d' `1 K) s** Output - Serializer Tx is connected to the input of the codec
+ \ V) u0 L0 m+ V9 r" h*/
" p; ? S8 |4 T1 u; s2 yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 q8 a4 m, b9 X% @& b6 b5 G7 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# B+ i5 V3 u0 x7 GMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ M* r- m) a$ h1 p| MCASP_PIN_ACLKX$ P& G# @' Q* I% f+ f
| MCASP_PIN_AHCLKX
8 @1 Q. I* s) C: {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# X" |4 a+ Y0 [: r2 U- Z/ X, Q7 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ A. e5 X; h' P" C| MCASP_TX_CLKFAIL , ^* [8 K; J9 z1 A. \5 m+ n* x
| MCASP_TX_SYNCERROR
; u5 K! b! Y7 a' z, z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! Y! k/ ]( |. ^& p6 |' e* J+ W
| MCASP_RX_CLKFAIL- Q5 i- C/ F, @9 T, f$ r
| MCASP_RX_SYNCERROR % A! t6 m/ d1 Q- E- j
| MCASP_RX_OVERRUN);1 H# K- [% W" i: X2 H! O3 r2 G
} static void I2SDataTxRxActivate(void)1 }7 e9 [8 R% W
{! P" {. a1 e- a j
/* Start the clocks */
+ O( S/ C" }- x5 X9 J+ D. \0 X% uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 o* C: l7 z$ _: J, w. t! mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) _8 M `7 c/ D8 r3 K2 L; j' G3 k1 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 f! m% m& J* H; `EDMA3_TRIG_MODE_EVENT);; ?2 J! b4 M' K3 M* t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % _6 q$ K& y* l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# b2 I: z; W* |' m) ^9 E' TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 z0 W2 g; X r" w4 c5 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& p9 o' k+ N0 F0 O/ @# j: kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* M$ k5 E2 z$ C2 s6 O+ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* E4 J' K$ J' b; {' i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* a/ X0 H- I- V! [: u! \; z9 a0 y} 9 @8 O) V- n5 f- e( ?+ l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 T: i: M7 E4 q h3 Y# |
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