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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 `$ S! E' e& K; o* E
input mcasp_ahclkx,/ C3 C% l8 x; u. A2 r. N
input mcasp_aclkx,
5 J9 ?! _3 t' X% I3 Finput axr0,% |, Z" T# K2 P/ |3 [
+ D# w- e9 C3 _2 ?. N7 M; toutput mcasp_afsr,
$ q. D E; c% o' Y/ r youtput mcasp_ahclkr,* Y( _, h! S4 X4 t: P
output mcasp_aclkr,
# t7 p2 t5 V+ loutput axr1,) I: ^! B3 X2 O9 ^# b7 Z a- Z- E
assign mcasp_afsr = mcasp_afsx;
: a# J: C4 K6 a+ I+ f/ bassign mcasp_aclkr = mcasp_aclkx;. O2 G% ^5 d0 U9 B+ e& ?7 ]' O: k
assign mcasp_ahclkr = mcasp_ahclkx;
! v6 g1 W9 @/ }% I$ |% dassign axr1 = axr0;
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- K8 K, y3 t$ I+ d, P+ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% D9 N( z) b, `6 _6 Q/ _( pstatic void McASPI2SConfigure(void)8 j+ a8 b4 t+ D% k9 d; g
{8 h. X( p, r, _! |' A% i0 ~0 o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 J# m$ G8 y% ~3 o# Z7 k' r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, D/ {* K* ?$ o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 B3 N2 Q! j, X! l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 s2 d: [& r* J; n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 G3 o2 i) j( g8 k! [# C2 g
MCASP_RX_MODE_DMA);
' P# x+ k" ]% d( L1 k0 e6 GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# v7 T" B& t1 X5 d7 K- eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* _5 F9 |" ?- w0 i3 O' _3 e A$ Y! OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. ~% e. v: ?# w/ h5 r0 j! e1 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% u* k( m2 |8 Y ]3 jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # E# ]. j$ E' G" ^0 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ \8 X# Q4 F; \) E. LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* F ?+ s- J, A4 |1 }/ WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + e7 q" B6 y3 j- L! t0 c( c8 B
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. o9 e/ G6 }) w( X o1 u0x00, 0xFF); /* configure the clock for transmitter */ T7 n' W, q. `( [1 X: o6 S$ K0 H
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& H3 h( T: }0 ]8 h# T0 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ ~$ U0 ^: }# A: W4 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. c \- m" I" V! h, e" g0x00, 0xFF);
# S; [& X) s, A# w
8 x6 P" k6 @" H4 r0 a2 v/ _/* Enable synchronization of RX and TX sections */ % e! L% Z8 f4 Z' S4 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 c" H+ C, h9 Q) f Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) W+ N2 J# M- D* RMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** k, r1 g2 _3 u" C' S; A6 L" Q
** Set the serializers, Currently only one serializer is set as8 K& a4 }- P* p; m
** transmitter and one serializer as receiver.* ]. y. c5 O4 u& L
*/+ r; S# `0 }9 s& [- w6 L8 a T: S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ c( D1 Z, P6 K, c1 E7 `8 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, Z M$ |, P8 d9 Z* \! L2 R8 \( u** Configure the McASP pins , V# E# [6 d, Z3 P1 }% w3 O
** Input - Frame Sync, Clock and Serializer Rx0 I# D& X) l! P$ H
** Output - Serializer Tx is connected to the input of the codec ) \+ k! h) K$ N
*/: i! @) _* Q* i$ d" F5 j# g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- Y# n9 v" g0 S' O! Y6 R6 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 L+ Y( ]5 R5 d9 d7 ?' D/ R- d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ t L/ f S7 t: _| MCASP_PIN_ACLKX7 b5 f ?0 E, e6 F2 G' K. l4 A. d
| MCASP_PIN_AHCLKX1 w$ S7 a- T7 m' T8 r9 @/ y" Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( o6 H1 I1 d A* G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
C, l4 [; @( c: A| MCASP_TX_CLKFAIL : c. A: N% Q: a' }- ?9 K, [$ D; E
| MCASP_TX_SYNCERROR5 j" C! }5 P# y% s4 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # f& ^7 ~! z0 o1 M7 v" M
| MCASP_RX_CLKFAIL
1 M6 W' D* k+ y' q6 n5 d( W% ~| MCASP_RX_SYNCERROR 4 k3 ^' z! y( `. Q" x* Q/ {
| MCASP_RX_OVERRUN);% w/ l/ s! f* f0 [4 M/ a! e ^! L
} static void I2SDataTxRxActivate(void)( C" f d' I' R1 ^& r
{
7 b* O5 o2 i" x+ ?; o/* Start the clocks */
) ]7 x) x) Q+ ?4 }& b! P" |4 m. tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 i2 _$ b, g4 O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( l$ ~( z& w4 {9 z' \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 | ~7 T9 v3 a! S4 oEDMA3_TRIG_MODE_EVENT);* v% f$ e/ Z0 K: _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " _ y- M, r! g9 ~% I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 ], V1 M. G. z0 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# x: L' ?1 U# rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 ~% s k1 a3 B8 j+ ~' I* I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ p5 h! E: J' P( \) cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 L( e; I2 p6 y3 Q: V7 d' aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 [+ S0 O& I- I( ~' g/ R: I: }} ; x6 e: t. P. f q7 q V; j6 V9 ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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