|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: y7 w8 ?0 V: b% Linput mcasp_ahclkx,) D0 P, Y) Y$ x) W8 W
input mcasp_aclkx,/ m8 H* S9 F" ]- ~5 S, y
input axr0,
) R! M6 {1 ?) e' E- H* y6 Y' A: ~
5 Q) v; ?) V: Z( youtput mcasp_afsr,; Y; x: A+ X8 @0 I2 S
output mcasp_ahclkr,
. w' V4 \; o! }3 zoutput mcasp_aclkr,
+ I; R1 ^) W* J6 Poutput axr1,
- }3 b; z7 U! y# N! m/ P# l assign mcasp_afsr = mcasp_afsx;
) H# y) }7 `$ L" m1 Lassign mcasp_aclkr = mcasp_aclkx;
. k# H$ y3 u& Tassign mcasp_ahclkr = mcasp_ahclkx;
$ ~8 T3 i1 d% q" \( Y( e* h# massign axr1 = axr0; 6 L- T& r% ], X3 L4 M' U
9 `. K& e# c! V* g" [
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % k! D9 i" Z1 \! d& g3 H
static void McASPI2SConfigure(void)
. H% ]- d: I. O1 |{
U7 |* g4 i' `2 C, B9 }: |1 mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ v3 Z' H) I* @# RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& `" F0 J) h, V' Y% FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 O! J5 G/ g2 ]. j& H) h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 P0 }& C; ] u5 N: L* FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 S. ~; b/ k# j q: _MCASP_RX_MODE_DMA);* z$ n: ]7 a: |! N: a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, _9 ~( z( A% h0 _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 w3 L# h1 |% K" s( K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, Q1 E0 z, A7 d5 v9 v1 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 w1 ?; }- t: F* _2 ]4 T# qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & l/ c& J4 U9 F+ _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 p! A# s7 j* }- g; C8 v; c% o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
]6 ?) w% t6 z, O0 [' l7 v% A4 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 N) d, V( m$ H' b, k9 |2 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) F" m$ X9 E8 `( y4 z" E5 H- y
0x00, 0xFF); /* configure the clock for transmitter */$ C( o' f# g7 G8 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% w8 y, e# K6 A/ cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( N& t, X, S. d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- S8 U% ~4 j: l6 Q0x00, 0xFF);
" N! J$ |7 c A& U( [9 X8 A0 n* r" p2 G$ ?& E/ ^
/* Enable synchronization of RX and TX sections */ 3 ]; c" e' \$ i! V Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' p) w- T3 Z+ V( ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 o; C3 F& Z- V' h% ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 m7 |+ p) Y. x" k2 X* q: m3 T
** Set the serializers, Currently only one serializer is set as" z" c6 p3 J3 P. @
** transmitter and one serializer as receiver.
: G2 W! i4 ] }) @*/
% m# g# [' q/ o7 i( K9 `" fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; s5 K7 R5 v0 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& U! y5 ~+ D$ U& m& L; j** Configure the McASP pins
7 q" v- A/ u" C' f** Input - Frame Sync, Clock and Serializer Rx% X _5 ~ m l& _% F/ H
** Output - Serializer Tx is connected to the input of the codec
* {+ k: {1 T+ I4 c; a {*/
7 r3 g& W3 a) T0 X; l/ M) qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& j! z( p/ l f% J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' t: n! `4 m# N7 Q) t& YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' |- Y1 y5 ^' V' c+ P0 D9 i| MCASP_PIN_ACLKX
E* b/ w' |! b% |1 M1 j: ]3 g| MCASP_PIN_AHCLKX
- T0 c) B2 G( i. U# r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 {% [) S, ?) d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ n/ ]! f/ Y9 q% O1 C! @ V| MCASP_TX_CLKFAIL
5 P( W8 R5 i8 p6 n/ r& l| MCASP_TX_SYNCERROR$ d8 x% `* l3 r; i" _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; n0 G4 Y' U9 ]$ g/ \
| MCASP_RX_CLKFAIL
7 K/ E5 _/ j, i5 `8 V8 f| MCASP_RX_SYNCERROR
4 W1 u( O3 ]6 b. Y% `| MCASP_RX_OVERRUN);7 R0 g+ `* ]) M/ \4 \* X
} static void I2SDataTxRxActivate(void)( }9 H# B8 w! ?/ Z- S4 D1 b
{6 _6 p5 H; w& a0 Y. I/ Z# J3 W
/* Start the clocks */- y8 P( d2 Y: `8 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# W1 K8 |3 \2 z4 \; G6 {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
s1 K0 N8 p1 q [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 v* d9 {: f; X: ]EDMA3_TRIG_MODE_EVENT);
5 I6 d/ }' Z4 y0 x+ I p. [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, m6 K$ c7 ?# l9 N) X+ `" b0 \) {. ]6 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// q. v( g( c3 `0 \$ `, ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 Y$ N5 i2 y! \' r) u' fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' h. n- a- _1 w& m. hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 W% i! Y' ~% `/ }% n6 g [0 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' T4 {( O9 v" xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 B+ |7 C, i+ J, y% p; H" T2 E2 K} 6 U: ^' i, ]# c8 P7 @* c( J) }3 y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * K6 h" j+ y# o$ Q9 U- w
|