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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 t8 x; h5 d. E0 y3 ?input mcasp_ahclkx,
% z7 q# i5 b7 a$ vinput mcasp_aclkx,' Y( [9 k! f7 o5 X, n6 ]
input axr0,) e+ W8 q6 S( h
# L! B1 | A$ n" O$ H' S' [8 doutput mcasp_afsr,
; ^0 j0 x' \+ i# e, ?; A/ ^; \! moutput mcasp_ahclkr,- s8 O3 ~ W" K0 l8 ?
output mcasp_aclkr,
: ^ x2 x6 Y v1 \output axr1,$ r0 d8 G- C3 c" _, ], I
assign mcasp_afsr = mcasp_afsx;! l# M0 b! `" @- C* J
assign mcasp_aclkr = mcasp_aclkx;
; i' r1 A0 @5 ^assign mcasp_ahclkr = mcasp_ahclkx;! ^3 ?# k, n8 x j. A
assign axr1 = axr0; ' @/ r0 e$ e" r6 [: m
3 \# R* g+ l. ]7 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 i7 n" T* X9 v7 @
static void McASPI2SConfigure(void)# h J8 n7 V; s$ |( |1 i
{
: O9 y# {. v- {& O) y p9 g% RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ L' M8 I( b% K. {0 ^3 nMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) `3 f- f4 ?) q6 R7 O. o4 M& hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: N8 s3 ?; s3 R! @0 C3 m0 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% {; N; R$ N* [9 N; ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, g. L2 R0 ]. R v0 [% k9 _
MCASP_RX_MODE_DMA);- c) l& g, l' I4 X/ d8 P7 x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# ?7 N6 u& u) i6 uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 t) G h0 t( ^8 C4 H" b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 [3 Y' A! ?; u6 r7 f# C4 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 q, K1 M2 N5 x+ e, E7 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : h2 Q! @) r% i- M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 y2 k4 K" r3 C/ y2 C6 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 F/ O# j; `& N: n w' @5 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : B+ h9 f% _7 V) @, D: k* H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; x: P- j, @" X0 |9 g* w
0x00, 0xFF); /* configure the clock for transmitter */$ ^1 h# `, H3 }/ j7 \2 j; S6 F/ h- N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. W* i4 l. o j( M& C) KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + e6 g0 g) J2 x8 |& @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; X& q, {% f* H0 w0x00, 0xFF);1 x" @. x2 ^$ c( K' r: i! }$ d
* A. F4 s* ^% b9 g/* Enable synchronization of RX and TX sections */ / r8 X7 J5 l& A5 e' V, i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; @, |( A* K& P; \0 }4 v% h' ^1 L& h8 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' }/ u2 l; a, I# g! i; x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** J) i% }% S! R* Z! Z, f+ `1 {. k
** Set the serializers, Currently only one serializer is set as! n- r/ R/ V5 J I
** transmitter and one serializer as receiver.) q2 R$ T& |/ a( T
*/
& z" O4 g& u V2 b/ GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 K* R( F4 a4 }3 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 @1 W( I B5 S- S0 \** Configure the McASP pins - i+ z4 W# v% r7 n; t6 I, K
** Input - Frame Sync, Clock and Serializer Rx
- Y1 Z$ @" A+ r; }** Output - Serializer Tx is connected to the input of the codec
) e* H3 Z2 T4 k) X4 y- k/ H) E*/, o' A8 V! m7 J P9 `) u* q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- Z0 g9 P4 o+ y) e7 N" s6 h+ V# i& F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, R% x) b9 W# S/ Z _9 I) DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# w W% e' X# g4 L/ @3 B| MCASP_PIN_ACLKX# f9 i0 c0 H/ R/ E) o" B! l
| MCASP_PIN_AHCLKX! u4 o2 l4 K" t, _: k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 h7 z) ]. \3 Q' O) k# W5 q+ `- z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' U9 J5 G/ [' j) ]# E4 \
| MCASP_TX_CLKFAIL
8 F4 A7 O4 g* `) N- p1 E| MCASP_TX_SYNCERROR0 j- A9 V& S0 y0 r! X0 w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 P$ f/ l# b9 m! l. }$ C
| MCASP_RX_CLKFAIL* P1 Q( M4 K5 q2 Q+ s6 i& i
| MCASP_RX_SYNCERROR 0 n. ?1 _( s0 x$ ^. W0 z5 P H9 H
| MCASP_RX_OVERRUN);
+ q5 C0 a; M7 A1 @8 c/ \! `3 r9 Z} static void I2SDataTxRxActivate(void)- ^+ O$ i) H5 s! _1 _" D" m
{. a. F' H. f8 V' n* q4 r
/* Start the clocks */' P/ E9 ]7 u2 b( H9 R" H5 @% {1 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 b8 w3 W/ _& w: uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ q- j7 g/ {% l) H0 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; a! [* J( z' _& ?6 c
EDMA3_TRIG_MODE_EVENT);
+ A1 N/ I+ \0 q0 q" y" v) x: s; q, r; CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' |9 [" n6 V9 w3 h& q- _0 A8 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* x5 h$ D. _+ J3 f) B$ ^* [6 H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 S. U L! ~1 l9 v6 B( _$ p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 Y/ g0 H4 z' U: f& m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* E- m$ z$ Y& t; v5 e% e; vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# Z' Z2 Q: F9 Y' N( O2 j5 T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# ~) R: M' m/ F" ^. L& V5 I
}
# z+ d0 p8 B' ^5 I; n& f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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