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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& _, z- D; [6 i$ _) V# Oinput mcasp_ahclkx,
, R4 ~, e9 j8 ^ r6 ]input mcasp_aclkx,
% j$ F) j& s. P5 }/ minput axr0,) c# i/ R& J4 r5 I) X) A
9 X& M9 c0 `, ^
output mcasp_afsr,. k' @/ Q: r. C6 D7 P- t# \
output mcasp_ahclkr,
, N f$ D6 b/ g: t+ Aoutput mcasp_aclkr,
5 G% j w8 w6 Houtput axr1,' j8 U4 K6 U5 L, ~
assign mcasp_afsr = mcasp_afsx;/ b0 U h) d' \" S4 b
assign mcasp_aclkr = mcasp_aclkx;
( x, E6 r& h. p, ? Nassign mcasp_ahclkr = mcasp_ahclkx;
S/ h& s2 Q9 Uassign axr1 = axr0; 7 K2 M1 A3 c6 M9 _5 O) ~
) Y/ o* a) r+ q) z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
s. f5 r& @5 `. U7 K qstatic void McASPI2SConfigure(void)
& L9 I, j+ H& Q{
# l7 h& E& A, f# L+ BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% T/ @6 j; M& s: l; u1 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( [: [8 U$ r, b4 W' _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& X7 v6 s8 v" U/ h2 i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 }9 B$ x! Q) {/ P( i1 `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) m0 a2 `# E! z6 }5 o6 E
MCASP_RX_MODE_DMA);3 _9 T" {6 F$ ~# A$ @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 I9 e6 F' X/ K' bMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' a: }" O" j5 L3 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 ]/ }0 w& y: u, WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 R9 w, a2 q5 O4 hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 j) V4 @2 H0 A3 [- N! p1 [! n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ u+ \4 Q9 E3 [$ ^ L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ I B5 x+ s0 S0 R2 D8 {5 R. xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 |+ i$ n0 x* W- p% u1 q; f9 K: AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 L; t' H) c! G, R0x00, 0xFF); /* configure the clock for transmitter *// n) W. z# a) C( }- G; X; d) Q" x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 P9 r( x* {6 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 R9 S* t- y3 E6 U- O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ ], a% \' ?' G" x# r0x00, 0xFF);
; X( X% {2 v9 o3 }0 g
' n$ k% B% q3 g/* Enable synchronization of RX and TX sections */ 0 t% f% m" @+ u) V( m4 K0 a% _
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 d& y* Y* `( i- q. f% vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 m) |" _- x8 h( ~, b' t+ FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( I4 i9 h5 M8 F4 u; ^0 r3 v** Set the serializers, Currently only one serializer is set as0 V* ~8 W) d+ C7 N# Y ^
** transmitter and one serializer as receiver.
% M7 a4 W5 W3 J" }/ r# V0 I*/
' m" L: ~% }2 p- K3 DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% N; E' s1 T! Y0 B2 E: k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( N! j- \+ [8 c+ B6 l$ C9 N- S) ^** Configure the McASP pins
# W2 ?! T _$ o- M# Y** Input - Frame Sync, Clock and Serializer Rx! }( g M) e' `
** Output - Serializer Tx is connected to the input of the codec / t7 K7 \8 d& N/ ^! f
*/
: i7 P7 m0 \. QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 [( K6 n& I6 \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. P& R3 v" R9 e3 t, [. IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* H" a% {6 M. R9 H3 ?( U# h
| MCASP_PIN_ACLKX
. t+ J5 {( e9 w5 e| MCASP_PIN_AHCLKX
; {7 {8 m; R. c0 l; {! K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 t& f* w" l: \! s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , A) k0 P ]* T, ^6 h( C1 C
| MCASP_TX_CLKFAIL
4 l- A; x& t: x i! G7 g| MCASP_TX_SYNCERROR
/ S2 Y% s5 z* f6 n2 ]# J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / o+ q' z& z3 R* ^9 D
| MCASP_RX_CLKFAIL! U1 F% B. `( z. w
| MCASP_RX_SYNCERROR
% \; m7 L; Y1 B' t( v# g: @/ D7 i T| MCASP_RX_OVERRUN);
0 A4 r# f2 {: H; j5 P: R) S} static void I2SDataTxRxActivate(void); u$ M" y* n. {
{
0 |( s( @- ]9 B* A l/* Start the clocks *// B/ R" e: }. t* U9 h+ a2 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- _ p; l8 H1 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: f2 |; s$ o/ a. n( _: M* A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; C+ I! _6 X$ ^; D' k& x
EDMA3_TRIG_MODE_EVENT);
! w& w5 z5 h+ r2 G& g8 l/ aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; Q% i9 Z6 \6 C+ E' |% Y% {6 B5 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 d2 F6 P( i" P, X; NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( A/ S! F6 K- h) zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! j3 A" X6 M2 P: Q6 m: vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 |( Q) s3 z, R7 u& e- z% _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" g9 g, H7 k2 U9 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
Q/ f- y7 ]9 a' C8 _0 }} % ?- U$ w, _5 Y& g |0 W; L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 z. _& _ g6 ]( C9 b
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