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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; R& D' `. R3 V, B1 M$ Ainput mcasp_ahclkx,
6 `0 f. }; x) w, D- E! @! A7 V; v$ iinput mcasp_aclkx,; W* B, \3 u: I9 s* ~' z& ]3 H
input axr0,
. U/ v4 E8 b4 z2 g8 I, v3 s( P3 u: {1 ~6 l7 F
output mcasp_afsr,
% M7 U6 T. w, O; n" ?( \output mcasp_ahclkr,
& f$ B% D7 {. ^7 J/ U) _% }output mcasp_aclkr,6 K7 p: H8 Z! n. ?, t. h L
output axr1,
3 D! \8 _4 p$ u3 q. k7 K/ r% r assign mcasp_afsr = mcasp_afsx;
+ M0 y" E6 k3 U6 Q) a/ F: e lassign mcasp_aclkr = mcasp_aclkx;
6 u' ^: u3 I7 ?/ ~assign mcasp_ahclkr = mcasp_ahclkx;3 Z5 m9 A- x9 s# w
assign axr1 = axr0;
/ x% g5 N. k; [/ I/ @; m! {
2 [7 o3 q. X$ b% m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 j( |! C" e* O/ j% _9 m2 Qstatic void McASPI2SConfigure(void)* \' C) }0 a; @* E# f% Z
{1 s d. ]$ N9 g
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 s$ b. l% e+ A- TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: ]# B( ?6 G4 u2 n' q8 a6 v& e! hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( F; s* ?: C5 p: j7 J, ` |# ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* v5 x9 m. G$ @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 R& R# k$ F& ^5 {, U1 Q8 \MCASP_RX_MODE_DMA);* q. ]( o6 F& S/ ~9 w+ I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," O. d/ s/ w9 @" C8 ]/ E9 p2 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% R; r1 T" N+ x, `2 D7 W5 }6 @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 E; j$ W7 o: a2 P* x; ^( ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 s6 t4 ]0 P& V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) _0 r& l/ h8 O8 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ C' c3 @4 r* ^" n i# b X" Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! t' K& N, M9 L; [6 w8 M6 a9 xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 c) n! Q7 u5 X- }- e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* }; G8 _1 n6 S$ Y5 K
0x00, 0xFF); /* configure the clock for transmitter */( v3 g# o1 \5 U* Z" w* O/ t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 J) M G7 T5 G7 K0 q1 f* X( m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 v$ V7 @8 l# i- U9 m5 y5 v/ A, e+ f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 O" L; r# t& d4 U% ~( ?7 O* d9 e0x00, 0xFF);- a+ P: ~' o S9 v6 f
! I2 ~4 G# x+ o* O4 a/ n9 ~' [/* Enable synchronization of RX and TX sections */ 6 a6 f8 e$ I. p8 Y/ a! V9 t9 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ Z9 q6 ^) E5 i a9 W) ^5 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 U$ H' A B# j- K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% N" Z% |$ Z& Q# K" W2 Z- _) z** Set the serializers, Currently only one serializer is set as& r, F P& [+ N/ n# }8 n
** transmitter and one serializer as receiver.
+ ?2 f8 T) F$ _ y*/
9 I0 f$ X3 J, h8 x$ ~# @6 SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- p: ~, V/ r+ a: g/ Y+ J& o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( D2 d8 F7 U2 j& i3 t# D8 t/ F: C** Configure the McASP pins @1 z) I2 l& o
** Input - Frame Sync, Clock and Serializer Rx
% P# [! D" @, ~7 \3 W6 |4 q1 s** Output - Serializer Tx is connected to the input of the codec 1 b4 G5 p* \8 m
*/
. A1 b' e2 g2 R. N% SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, G) Z9 ?9 |; X) E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# j0 \8 X2 R" A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 o, H2 s3 R3 x( o$ y| MCASP_PIN_ACLKX$ d; W# _) U: \
| MCASP_PIN_AHCLKX6 r5 `& O+ D6 H; E+ C# w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 Z9 o, @( L' z$ I# ?/ I0 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, n* M2 @ ~3 v' s; W| MCASP_TX_CLKFAIL w. B m: A- I$ g! c
| MCASP_TX_SYNCERROR
q7 E7 T3 f9 V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 A1 }/ z5 r3 N0 X/ D7 C| MCASP_RX_CLKFAIL
0 Q% `8 J3 G# K2 _- d3 p/ R| MCASP_RX_SYNCERROR
a# q: p: n+ D# t2 {8 ^7 x| MCASP_RX_OVERRUN);
3 l0 j: s J% d} static void I2SDataTxRxActivate(void)( u) R2 v( c- M% @, m/ x* D, C, k
{
* }' J+ f' I4 C. t y/* Start the clocks */2 D2 } C q' w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% Q$ J- @. U$ i; `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 _: W9 Q- q* n- d; G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) N, I+ @" U6 Z6 i" F4 Z0 [" H0 Q& v
EDMA3_TRIG_MODE_EVENT);( d3 _. L+ S& s5 j& o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( T8 P- Y0 k" H6 R4 s% J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( i; O, _4 @: t2 C% g7 ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 U1 S+ h( @6 k3 r8 v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ _5 x/ W8 o* ^" ~6 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) B: L. t7 D6 t' U0 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! _$ T2 i, c; QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' g$ C' ~$ K, U* n
} 7 l4 N0 h/ o" J B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * S7 {1 }& K4 S) `+ }% Z1 [6 F
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