|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 D& |- o; I0 d% U. C$ M
input mcasp_ahclkx,
% `" @2 e) n. L9 a9 sinput mcasp_aclkx,$ I7 {, k- I0 X5 @$ j
input axr0,3 u) @) @5 f' A' k* s5 W! ~
: H+ _! ^" P7 \) K0 M9 P e
output mcasp_afsr,
, S' O" i& {5 y' F: Coutput mcasp_ahclkr,' S4 T" r0 z* c5 U2 O3 j' j; m
output mcasp_aclkr,
5 @- ^3 Q- w, ~: C5 p5 q6 Boutput axr1,! E5 H" |1 ]% j$ n" h% N1 j/ ~5 l
assign mcasp_afsr = mcasp_afsx; T; ~, F' s. ?/ Z
assign mcasp_aclkr = mcasp_aclkx;
- z6 e( Z3 e) S: a* ?# d" `assign mcasp_ahclkr = mcasp_ahclkx;
, e( h4 O2 D5 y" k ]2 s, Jassign axr1 = axr0;
/ u9 r0 _' Z0 J& ~+ u* u8 r& [6 G# T: A; e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & C1 j! h$ }# Q: A) W- T; {
static void McASPI2SConfigure(void)
6 u+ O( i+ Y# K# Z{
# B* W; [5 t) Y- t8 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);# `1 @" U9 B1 R5 K. P( t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 P( }* m/ b' K, M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! q1 ` m: {4 }6 r, P( e: r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) _8 `# ?, ]" C$ ?1 Q: B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 d; P3 I! ]3 ]' l& h( ~ b
MCASP_RX_MODE_DMA);# e. M K6 B' v$ L3 h0 w9 |& N- O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& {0 J; l( q, ^8 M3 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; c+ @7 n& ^, MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, T+ _3 ~+ z7 ~+ r) R0 l7 G% fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
@2 b4 P% s8 q5 b \' U+ w$ j GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 N( e \; K# k, J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ k; q$ o+ \; ~1 N) o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 Q( b# J$ f: X9 q V$ s2 L) x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' n. v) J5 D1 ?+ G, d- | l9 YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& P+ o# ^8 W2 l% l
0x00, 0xFF); /* configure the clock for transmitter */
3 S# O. b+ g5 p: d+ @) a! AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! u7 {; O9 K5 t6 o- B4 ?8 E+ F$ h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # B1 u" K3 L/ p5 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 J# U G7 ]) ~, j* ?, |0x00, 0xFF);3 Z) {0 V/ Z) q/ _" Y9 C: b
8 O: Z. o: H* S
/* Enable synchronization of RX and TX sections */ ^2 U3 G5 `, S# P+ P& ?9 v5 ]1 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! n* v) m- r! H( L& O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ @7 y5 Z; b5 g/ X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 g/ K! {- B" b( F/ e% [** Set the serializers, Currently only one serializer is set as
( f/ u; u/ J1 t1 r% d: t** transmitter and one serializer as receiver.
, o; @! J2 u' u- L, H*/
7 Z% X ~& k* a1 u G0 e8 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: I6 G6 n3 h; t8 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ o( v# L- @3 x# L: }8 M
** Configure the McASP pins " K6 y3 `+ U6 p+ L. V/ f
** Input - Frame Sync, Clock and Serializer Rx7 y/ J) ~( @$ ?$ ?
** Output - Serializer Tx is connected to the input of the codec ! ~- ~7 v L8 {6 I+ X8 V8 K. b
*/
" N6 _2 n4 F& k ~5 N3 [7 Y8 q" cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 a* a% V/ N8 t. R3 c' i# b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! y! n) T5 q2 c( N6 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( Q- K* x2 q3 k9 h| MCASP_PIN_ACLKX
) G" c# W) d& R. u1 k; R$ b| MCASP_PIN_AHCLKX
f" s- { I2 i8 Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ s. }" Z8 T8 Y, i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + x( R: m3 ~ N0 v* y" ^
| MCASP_TX_CLKFAIL : n: V8 f; s/ u( ?5 M
| MCASP_TX_SYNCERROR
: t, _7 k* j% w; K7 q# J5 U+ r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( V9 A( T2 v3 T+ m' y0 U9 X| MCASP_RX_CLKFAIL
& C; |! F! {3 _9 k1 Q, c! p| MCASP_RX_SYNCERROR 3 x8 S% F+ G1 i* k6 \+ {
| MCASP_RX_OVERRUN);
- x4 g0 D! {$ e} static void I2SDataTxRxActivate(void)7 G9 y& v: h- H$ T3 o6 n) ]1 n
{' ]. O1 ^' o( O9 Q6 Z7 [
/* Start the clocks */
+ \3 c9 ]* O+ r4 p/ {7 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% ]4 W7 v0 n$ q# n/ ]5 L- IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: l- a- r1 `, T' s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' s! t% K' ?$ `" n9 }
EDMA3_TRIG_MODE_EVENT);4 M f4 ]' l" r- V) {; b8 a' a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : t* F1 s3 t7 t' l; T, W% M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' q; Y6 i( J" s! J! d$ w, zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* y6 a) e9 M) b, KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ o+ v- H: g4 w7 z7 q- c9 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ G9 ]9 n4 T0 y/ cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- H1 d- G( X* l/ X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 l7 H! r* c% P6 k, e7 s6 m' d& G}
9 g$ J4 q! C! h C" _: E; N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
: E$ D$ K; A! L6 ?9 a) V2 j" J: B1 r |