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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 ^. ]+ P8 Y5 X0 F& w# l* h
input mcasp_ahclkx,7 K. Q% P6 _* l% b& C
input mcasp_aclkx,8 G1 r& C$ t4 C# u7 V* f
input axr0,
0 V* w( o* ^/ k' k+ D: I
: s2 ]6 _" D1 N8 Voutput mcasp_afsr,6 V# A+ z: b9 P
output mcasp_ahclkr,0 c1 R% F j: O% m' V# R' T( E
output mcasp_aclkr,
2 H+ F& U9 Y/ @% M0 ~- qoutput axr1,, m; z) |0 W L. x' E) e2 i
assign mcasp_afsr = mcasp_afsx;( ~+ {, i% u5 w
assign mcasp_aclkr = mcasp_aclkx;# [( @- W6 n7 A6 @: }
assign mcasp_ahclkr = mcasp_ahclkx;
% ]4 k+ o6 ]/ Y# v+ t8 Wassign axr1 = axr0;
. K- X" [; U+ M: t; x
: s; u7 g, |+ y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 r$ R5 Z" p4 U$ r; e
static void McASPI2SConfigure(void)
- b- u5 d A2 G{
7 D6 f3 k& J1 h1 m# A( S: U+ EMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 B6 A) Q* F& ]: h5 ^7 z) x& C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; E4 i7 C0 q% o7 }* j/ U! g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* F7 [, l; N$ C, MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
O! D( i2 h+ r9 |, J: E0 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ M) U6 v ^1 p1 W
MCASP_RX_MODE_DMA);
% F$ J+ E7 Z5 P3 m, [- R& RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 {" J' ]( Q. a! s3 a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& |; e' C/ R: P( g- ~8 k! m. gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / `2 K6 w N5 n3 N$ l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 d$ f/ b6 s, W8 p3 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 p$ P( P3 j4 T$ L* v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: S0 E. g3 Q) w; e/ v* X- t! rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 C. J* [% a k- `; q5 q3 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + o$ O0 W" ]; r' c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 M3 E- y6 z5 _7 m' r! y8 t0x00, 0xFF); /* configure the clock for transmitter */4 i: F. P+ l" @7 y* x ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, c" O7 Q+ P$ L2 t# T, f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' G. P3 m$ f" G" D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) K% P+ n% Y7 C' V3 G
0x00, 0xFF);
' N( _: f6 I! `/ L
1 p% x& y# W" Q; M/* Enable synchronization of RX and TX sections */
. k& t# @9 I: R2 Y# o& xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ O) L3 G: k4 r \' n. dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 @9 u$ S* B- K: x5 R1 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 U# h0 \+ W' C7 M; B# J0 @
** Set the serializers, Currently only one serializer is set as& e( Q# ], [) q0 Y
** transmitter and one serializer as receiver.1 a& }7 }6 _0 d1 m3 D+ L. @. o
*/$ o8 {' V, K, t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ G% Q% \0 U. V1 z6 U5 i- oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** s% J- u. s- g; a1 k! ]
** Configure the McASP pins
v4 l5 w( l; U6 X+ x8 G** Input - Frame Sync, Clock and Serializer Rx# I& G, S& Q/ V- q2 X
** Output - Serializer Tx is connected to the input of the codec
; Y8 R- E/ j5 F4 l*/
) r, R% G7 y& }# [9 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" f6 X( U5 `+ G' h% n+ LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' r5 j! G& t+ _* ?& ~! J& c, Y' xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 ]$ s+ v; d7 W- ^
| MCASP_PIN_ACLKX
9 u" i+ s7 S* g! F8 }! E5 J| MCASP_PIN_AHCLKX
, i& m" w. f2 V9 c' k4 v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 P0 h$ _6 e% W1 h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 v* X7 T2 E5 o' S5 H: s$ e- A f
| MCASP_TX_CLKFAIL
7 ]) }3 t# _8 }$ S6 u* a| MCASP_TX_SYNCERROR
% W+ o( G" t- C8 ^- C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! w) }8 E) O; d8 F
| MCASP_RX_CLKFAIL
% E8 L# Q5 ?9 J# Z| MCASP_RX_SYNCERROR
" _$ O6 o( q" C5 e( o7 S| MCASP_RX_OVERRUN); W5 P' T" Q/ L' b- o) S
} static void I2SDataTxRxActivate(void)! m- s! N8 a" `- j; [
{$ f+ R( u3 o+ T3 N
/* Start the clocks */
5 t, v) _, N1 E1 Y# |3 Z; t0 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' [9 N9 \7 v" E E% {. q) R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- g% r+ x" T N; P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, |& o; H. U( u
EDMA3_TRIG_MODE_EVENT);; w+ K/ l9 g) l v( m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 `; J" n r$ i5 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& L, \) p# ~( x2 NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" L+ n6 N8 |- C9 [ `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ e+ ?* u* {0 E7 M% twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 _& j) n9 a5 o; zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ }9 k; h" d, c: ^7 o \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ w4 P7 P5 ?. d% F}
1 e) c( S7 K( n# @7 b) m2 R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ F$ ]' S7 N |( c3 V
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