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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 a( W+ }; l4 p3 Z$ c$ ninput mcasp_ahclkx,& ?2 D3 _- a9 S0 V; a
input mcasp_aclkx,. o1 b4 z' w5 F/ i
input axr0, E8 }) }! B) a# u' o5 i
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output mcasp_afsr,
# l7 Z/ _( A/ B Qoutput mcasp_ahclkr,
0 C* S$ E( l- c( t! w! ~* Houtput mcasp_aclkr,1 f" G7 Y$ k& [0 z% W
output axr1,
6 K% e( M9 ^( v9 E, w& X# Y$ B assign mcasp_afsr = mcasp_afsx;
X$ z9 M# q6 Gassign mcasp_aclkr = mcasp_aclkx;
! J$ f/ u9 z8 }; k3 L' zassign mcasp_ahclkr = mcasp_ahclkx;) Q4 t: r& O- }
assign axr1 = axr0;
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4 `% C& v, W& ~1 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: X4 h8 I- i, M& D" fstatic void McASPI2SConfigure(void)
' n. z$ x I7 k/ g ?/ w8 [+ [# f{
, ]/ Y Y r* R6 ?, aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 G/ i( ]9 ~/ S( o. W, J% fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: `1 F0 w7 q- m, P8 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ e0 R5 k8 p2 o `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. }* h1 K1 d# H( y4 }; PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. [5 R# ~# f3 l3 p. }4 cMCASP_RX_MODE_DMA);6 q8 H% `+ a2 S1 `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& `5 h& l" h8 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// h* N7 w. d+ `$ K) t7 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 y' ~0 G' |* V- T' Z/ @2 n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ^7 w: ?* i" w& p* sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ x1 F G9 R. N- h9 M" P: q% v, IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& {- n* z# n8 v" N( { e& I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 f! H+ B X& @5 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / V- ~. e6 n% T2 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ n3 O6 ^& Q8 {% U F8 g* z: [0 T4 M0x00, 0xFF); /* configure the clock for transmitter */
' J; Z+ f! ^5 {! ]* V* dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: _0 h) n3 u5 n7 p4 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 l6 r' O/ f8 y r; p5 R4 J" m- s$ q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& a/ K; ^% Y4 j0x00, 0xFF);& w. Y/ Z3 l5 \# a8 g
1 b) I" R& J8 n. H4 S; w/ w
/* Enable synchronization of RX and TX sections */ M3 X# y: G* }3 `1 ?, y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 k/ L s! x2 B8 OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% ^/ W8 _: o% t# S0 P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( G! d" `! s0 d1 q5 l& M** Set the serializers, Currently only one serializer is set as
0 B7 f4 v& d4 R6 o4 Z4 j7 x$ A** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* U$ U0 b `2 |( @/ q# s. O2 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 o3 E0 }+ Z6 U- p; t3 Q' U
** Configure the McASP pins 0 M( r& O! Q+ h r4 k7 g+ O/ H
** Input - Frame Sync, Clock and Serializer Rx
* A" y) _1 U5 A. b** Output - Serializer Tx is connected to the input of the codec
J" z+ ~& ?4 w3 r- Y*/; n# i9 [5 k4 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); l" h k/ a/ h; Z) Q% `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 i% O' F F2 ]9 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 \* V8 n( A3 O4 c| MCASP_PIN_ACLKX
9 w% v x8 g2 y W3 E| MCASP_PIN_AHCLKX
; k/ z0 Q7 W, I! @9 I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 i$ S) d: l4 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , B$ |1 M ~* O+ B, o
| MCASP_TX_CLKFAIL # ?- l2 R' W+ K% T3 u. ]( H
| MCASP_TX_SYNCERROR5 s+ K0 q3 L5 r0 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR U/ L, V$ L- O# k# C, `5 }6 Z
| MCASP_RX_CLKFAIL9 |- U7 G) d5 ~) p' ^4 h' T! j
| MCASP_RX_SYNCERROR
0 W( W+ T/ B+ d1 v1 n& m E* X }| MCASP_RX_OVERRUN);
- b1 U3 G8 `! O, R8 ]3 @) S. Z3 I} static void I2SDataTxRxActivate(void)- w2 j2 E. x9 S1 G {2 a, S+ Z- A
{
* u0 B. d: p5 `2 h k2 ^- J/* Start the clocks */
/ L( Q$ H$ l& i& k b* nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 H( F# a$ v9 e. J8 TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 k& n8 Q3 t4 K: K9 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 ?/ L/ t. n! T9 n9 n, L
EDMA3_TRIG_MODE_EVENT);
% t+ S( X5 k* X& KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 Y- f) S9 g$ x+ P7 n5 S& r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; q/ t9 f* `2 {9 y& T4 p* |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' X" B4 g9 S& H- Z+ ~. [0 t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 Z8 T8 J6 ]! x: m$ Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' y* D: q1 f% S2 R. i0 P) ^% h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 [$ }. P9 J8 C$ eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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