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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ W5 Y2 p n7 v5 E
input mcasp_ahclkx,
$ W/ P" y$ a, E4 winput mcasp_aclkx,
! ~ E# T; F! i% [) ^6 zinput axr0,' X9 g, B) j# u# b
$ V. v- }. M3 N' p2 ~ ]5 K% q' C, W3 F
output mcasp_afsr,
8 s2 b0 G2 i: h: |! S; a- O. i' Youtput mcasp_ahclkr,- k5 u6 S. ?7 _
output mcasp_aclkr,
. [* e0 V; d) Aoutput axr1,: n2 I3 S3 \1 ]- A
assign mcasp_afsr = mcasp_afsx;5 h% u7 x, F& T
assign mcasp_aclkr = mcasp_aclkx;
- r8 T; c4 K8 n+ oassign mcasp_ahclkr = mcasp_ahclkx;1 A+ ^, A) k# J" j+ ^
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 E$ f5 x! h; S. s. z7 Bstatic void McASPI2SConfigure(void)$ z2 ^6 i$ I/ L- K8 Y$ d, p6 d7 g
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 ^3 G- h" h6 H& o/ {' ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 }5 S7 p5 n2 D# I/ zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! ^- S: H9 Z hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ _- l! Z7 w' V ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) |: J; \& D9 P0 P4 G4 P' I$ |( d+ h
MCASP_RX_MODE_DMA);
1 n1 `! X+ R, K. y% ^# W1 aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ^* X/ b# K3 f+ P N, |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 i2 o3 j% z% i9 u7 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 N" v& b3 w% M8 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 J# d" `9 j0 c( _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 g* O8 c% T( q3 \& CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 w* S/ Y9 K# U$ D& s" W+ f/ R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 F/ [5 E; { F, x, ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 A3 E! U5 t5 z3 `/ \0 K/ WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 v8 j Z2 w w5 a, e& D# Y0x00, 0xFF); /* configure the clock for transmitter *// E; r( m' e& p' d# n0 ^4 [! H" e" ]( v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 m1 g5 A# n6 c, `, d: xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - f' u% J9 o% K0 Z7 j% K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* D& V* P6 l: z; k6 u% o0x00, 0xFF);
; m$ b) T, A" L- a" X. J; V% w$ w6 n- Z( o) g9 f6 j4 \
/* Enable synchronization of RX and TX sections */ : W0 e+ i# X- o6 |; S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* N/ v0 H$ M& y% H! {- H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 K- b. [+ }/ h7 X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# ?( C; e* r. F4 f! f
** Set the serializers, Currently only one serializer is set as4 H9 j% u( P* U7 s; C7 d9 c% h% H
** transmitter and one serializer as receiver.( l2 K# Y% l) R3 v$ `+ n6 H
*/" h/ a; F: x" l/ M$ _! d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( v+ F3 R% V! D7 ~' f: ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 k" d* p/ a% x( J' k+ B5 ], U u' S** Configure the McASP pins
- R5 c( p# K. {* o L' Q** Input - Frame Sync, Clock and Serializer Rx. [! g: G6 o5 R+ Y) v# U
** Output - Serializer Tx is connected to the input of the codec
3 D- ^- q4 n a' b8 s8 y*/% B$ g& Q3 k7 S) ]4 v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# m2 v' F* ?6 M2 t+ q) A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ E! Y: c) @: u* s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 N7 ~. g$ s* X& O7 z) F2 A| MCASP_PIN_ACLKX
2 s4 S2 m7 c4 f% K- || MCASP_PIN_AHCLKX
4 s* { E; q9 K4 s4 D9 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; [; k; U. n% k4 Y( }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - S" Y8 J2 o9 |" n: S4 D
| MCASP_TX_CLKFAIL
! _- i. J% }' q' m| MCASP_TX_SYNCERROR( {8 v) `4 F) d: n* j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % B n# e0 E, b( w6 k3 s
| MCASP_RX_CLKFAIL8 S4 v, Z4 w" B
| MCASP_RX_SYNCERROR ( X% a- `* n U, S; u
| MCASP_RX_OVERRUN);
# [$ P/ }) u1 U& I} static void I2SDataTxRxActivate(void)
% s3 E% s$ Z% _, D" D. V1 A{2 t' f- W7 a! \" A" k
/* Start the clocks */
( W' w& \6 d A2 m5 K% XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 N3 ^- b' d, }7 P/ p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' k* T6 N7 |0 O8 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, Z8 o7 W' a% I& Y/ l6 [
EDMA3_TRIG_MODE_EVENT);
1 z: @ h6 ]2 j+ A3 J, Y9 s3 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : y8 F+ B( z: j" F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: V, b7 A6 ^" v* H1 E- f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" ?( c5 Z) U+ E$ R' V" m: _) W: i/ \9 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 ~! `4 W# w6 c/ h$ Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 t' |. ?2 c5 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# N4 f `3 h2 a: [ N% N! YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- ~- s" V# m) h} ) g' P. `, n: e- x5 O. |/ g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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