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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 A+ w2 X! p. N" [) e
input mcasp_ahclkx,
" P( `# p# r% Q: _ c/ Finput mcasp_aclkx,* f" ]% ~4 i' [( g* l+ P
input axr0,! w4 `* ^; A; V. o$ O( {' d5 Z/ m
0 i$ c4 X' |; ?7 l1 D
output mcasp_afsr,
/ v# S% E& d/ H6 f; Z' joutput mcasp_ahclkr,
5 v9 A2 u# G& v2 y9 } _8 M6 Foutput mcasp_aclkr,, g3 C; c2 `! G. `" E; i( o
output axr1,3 R, X! Q4 I, W: u
assign mcasp_afsr = mcasp_afsx;& M- B! \% ?% \$ x1 O* V
assign mcasp_aclkr = mcasp_aclkx;
& l9 O$ ]) `8 c+ A$ h2 yassign mcasp_ahclkr = mcasp_ahclkx;0 p y1 b% G5 L0 u) Z8 c
assign axr1 = axr0; " O0 @9 y- u; }% z5 a8 s. P
' }* p& T4 J( f" e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: j& w2 l' ^5 dstatic void McASPI2SConfigure(void), G+ _3 `9 m, c4 X& t1 U7 {9 U7 R& a8 @
{
7 h. K1 y; V6 O2 T4 {. P% }2 VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% T6 d: W# w! q0 z2 n5 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 M) Y1 n4 Q. l5 X1 V) P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 q% M: Q4 I4 Z$ P. {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. p# f' G" f: \3 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 Y* a1 _, l) I: X5 y1 ^
MCASP_RX_MODE_DMA);' [9 t v4 L; U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ W9 e! w# Q5 w! YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 @, ]/ F* l6 v' V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 u U, H$ `. n5 h/ ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 U9 j6 ]' M- V" O7 D {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - L7 j" S9 N$ n3 {( K$ U) @: d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 |. V, g& |6 C, XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ |1 r8 j3 V4 s+ A; ]$ lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% Y0 o: Y8 Y3 TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ }( m- D; w# A6 }7 U
0x00, 0xFF); /* configure the clock for transmitter */. L) W/ |0 V% U0 Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 Y' H% ^$ | ]( I. [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( s6 {# ^8 p7 h/ DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, x+ r8 q$ {" z3 f
0x00, 0xFF);' W( ~2 Q+ l7 \3 F3 F; E2 U" b. r
0 ~* q' J! y# R4 F7 {1 z A5 s
/* Enable synchronization of RX and TX sections */ x0 C4 B2 V+ m9 [4 w8 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 T$ d1 I9 k: K# AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) m1 x2 ~, E8 I4 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 w9 p% b0 B( T( c# ^ x
** Set the serializers, Currently only one serializer is set as6 u* _! a: @0 }* k s( Y
** transmitter and one serializer as receiver.: m. I! r, o C1 Q
*/' u8 {" x* Z) J/ ?) v3 a) _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" F7 K% P7 k, i/ n# P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( M. A# C, R& I4 \** Configure the McASP pins 6 m2 W3 w* V* D: R9 Q! T' k# p H
** Input - Frame Sync, Clock and Serializer Rx
+ A5 Y* D* @, A* ^) K** Output - Serializer Tx is connected to the input of the codec
* q* c6 L3 g1 k, @1 y% }4 e( S/ A*/
/ d, {& A O3 N- r" ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) S% E6 J2 K5 Z, Z' H2 JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 G8 T W" c7 N1 M" r/ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. v: x8 `. g* D3 N8 i: p| MCASP_PIN_ACLKX
6 R- ]5 N0 s& }. l| MCASP_PIN_AHCLKX
8 x. H' R X; H. Q* O5 `- m: f; W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 m+ J& C7 E* \: FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* x/ D. b8 p9 f3 L `, }| MCASP_TX_CLKFAIL
1 \8 O$ [! ~* A$ [9 m2 A| MCASP_TX_SYNCERROR
8 n5 w5 c) F' U9 ]: Z- p7 `, ~, {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( Y8 a Q( B& z+ ]1 f2 y, }
| MCASP_RX_CLKFAIL6 X$ j" }& T( ?9 H4 ~
| MCASP_RX_SYNCERROR
) F; V6 q6 Y) _5 N| MCASP_RX_OVERRUN);; v' |; x" ?# H5 ~0 ^ \
} static void I2SDataTxRxActivate(void)
/ v N" O" l6 @/ n9 R1 r{
0 t- i ?) a' s/* Start the clocks */4 i) q% Z4 O8 @( v2 L* ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 w- d7 F! d+ a% X$ Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 n4 I( @* @8 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 k g: A& q" T& A% Z2 i
EDMA3_TRIG_MODE_EVENT);
6 W7 c9 ^0 b$ KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' ?" l7 d+ g( |/ ^0 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ |" H' g* j' nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. a5 N4 M- i; l+ U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. v: P; f* H' j3 e$ fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; _/ p7 \& }# o0 D$ G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" p5 u0 l5 r: T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ O5 q$ \5 m. ~3 k' N# a' |2 J, M* U
} ) m5 G% I% q& ?1 `/ s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + X+ p( {9 B0 p( ?, J
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