MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
9 ?/ b0 H; E: h1 f3 q  l  z3 G* X7 v$ s1 Kinput mcasp_ahclkx,
input mcasp_aclkx,
/ W- W' P$ X' H* Zinput axr0,

output mcasp_afsr,
/ E* B7 Y% W/ h# i  q0 D2 Toutput mcasp_ahclkr,
output mcasp_aclkr,
0 ]! J* s- t7 p9 v9 u; J8 n8 N  D* joutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
1 `- Z+ p( T* t) ]* l2 m& [assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

: A  V; A- @' G5 O7 [3 G

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

8 p- h5 |2 I7 G5 o! r. c( z

static void McASPI2SConfigure(void)
! b/ T4 i. U- Z, C8 e  J: A7 B: g{
2 l8 \  }6 ^7 y4 pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ i; z! @, M, C- iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
# ~! V, G* h5 H$ BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& R5 z& I6 `) A  ?; P, _3 tMCASP_RX_MODE_DMA);
* i2 _/ U: y3 Z: q" c4 u" s. b+ A! QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ]  m% z- s# R9 d2 hMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, |, }" F- i5 D1 e  w. fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 F8 j" R0 `6 h, {0 G' R; _% N! \MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
2 |& I& D3 T& z/ J* [) o. I; S; m: [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: W2 j0 v3 z8 T6 b" ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
4 J. E; z- J6 J, U& b; }" bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 M) B% [9 L2 S6 g: \. oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
0 g7 b# J( u/ U3 I  V
( D. c- h# D  c/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
" ?# I  H1 `7 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, l. p2 _, `5 c- k% mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
4 L/ b: p- Z5 @** transmitter and one serializer as receiver.
$ M0 b- Z. K2 I- N- a5 T; Z+ u*/
; H) e) o* a! [7 M* pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ l- r7 [. u+ [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
. c' v% q/ b6 O6 w, X- ^3 g1 @** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
8 [0 w. R/ H% w2 Y, A*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
  q# @+ X$ `0 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- e5 E- H5 e# z9 y& y) {! ^5 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
9 C9 a# {. R$ ]0 j| MCASP_PIN_AHCLKX
, [/ e* Z. }% I+ X6 g3 C| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 X8 N5 _) q" X7 X7 W; i| MCASP_TX_CLKFAIL
! D  _7 H4 [- g" R' n4 d% _0 Z| MCASP_TX_SYNCERROR
1 Z" m- L; }4 M0 m| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' |4 G" C2 V' d| MCASP_RX_CLKFAIL
% R; o) A+ A# ^| MCASP_RX_SYNCERROR
) @3 E- h: g  J) S| MCASP_RX_OVERRUN);
; v8 Y3 `: i5 t: j, r: e- Y}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
3 m2 V1 |' |; \6 o5 z, xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
( i2 q3 c9 T* DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
1 a1 g0 T5 \& K3 m8 p! ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ L. v; Y3 x, r& Z3 X7 U8 \0 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
1 v% B6 I& q' J) ]+ yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; x% s8 D2 @7 Z. y: lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
! }: g/ |7 f, JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 `+ w0 |8 z  RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

. a  g; M  ?% b7 i! \' D" n