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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' q F0 h8 X; e# pinput mcasp_ahclkx,; Y: L0 ? A) f: ~3 R4 a
input mcasp_aclkx,
$ w+ z% o" U& ?) j5 F6 Sinput axr0,( ~3 [5 U+ }0 f( a. Z
: B9 F: T! U! Soutput mcasp_afsr,
" r7 F" M, H. a8 F! zoutput mcasp_ahclkr,
2 j& d) a2 f& D& N" }) woutput mcasp_aclkr,+ W8 O9 `, \; y+ U( j
output axr1,
+ A3 \3 W' v7 s3 a, \/ T. R assign mcasp_afsr = mcasp_afsx;
G/ Z4 C0 j1 X% q( N, qassign mcasp_aclkr = mcasp_aclkx;
( r w) A" M j- N; ?# b! @assign mcasp_ahclkr = mcasp_ahclkx;! `) L: X1 u3 I
assign axr1 = axr0; - Z2 W6 ^. Z3 H1 I" G9 r9 c
% H( B1 e: W6 H! q2 _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: e/ c) d3 D+ Z/ A4 T; ustatic void McASPI2SConfigure(void)
# b3 V* K# x% _ F: ^6 C4 K{
2 l3 Q9 j$ L0 W7 u/ `+ e6 }McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ H9 v, I; ? e7 n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) m- q/ ~) V3 _7 l) w _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# K: x6 ^. W+ k5 k) }( @" ]6 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 R) M, W/ a/ U: A# ^/ IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) \6 L( f8 _) @$ C
MCASP_RX_MODE_DMA);& u' U( A( a3 I( Y' p, s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 J% ~0 T) O2 J4 N! I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! c, X' I5 W& s4 A+ w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! c, Q9 u+ E; hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' c+ w9 \. }2 i8 z$ l6 R1 G' n/ GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( s( g4 N1 h- n! o9 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// u( p9 G' s' U& J0 x5 L: t$ ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: E& e2 E9 w5 K# E; g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% n& y0 j* Q5 c, LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, n+ x$ D4 e! q* k( L
0x00, 0xFF); /* configure the clock for transmitter */
+ ~, _& }# V3 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; d+ d" `4 {$ A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 Q, Y& f' \. P6 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. c) X0 e$ I. |6 W
0x00, 0xFF);: J: h3 d9 ~" D
2 \$ Z7 s9 E& D( m" y( q/* Enable synchronization of RX and TX sections */
0 V* F' b, i# M! e2 Z QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 A) n7 m4 K/ a' i5 b: s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" b1 V) K/ e$ W) i/ i2 `% d6 a. Z8 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, `3 F& \2 {5 L; z) G& L7 H** Set the serializers, Currently only one serializer is set as
8 C" ~' X& o7 y$ n9 c** transmitter and one serializer as receiver.; M5 j1 F' U6 b4 E' j8 V$ p( B r8 U" S) `
*/
; v# E1 i" P Y. tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 Z0 e M4 U; M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 ?/ y& K6 M T( l( E( N! s** Configure the McASP pins
' J' k8 H$ }, M5 v: H, Y% @1 ]5 ?** Input - Frame Sync, Clock and Serializer Rx% n0 z$ k ?! j2 s/ E& w
** Output - Serializer Tx is connected to the input of the codec
$ E$ a5 x; e# a g5 c*/- }1 s0 c9 \" F7 R& G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# g/ Q8 d7 o3 t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) A/ J2 a5 e$ }/ \2 K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& l( k8 G; Z5 n2 x8 l1 ? {9 u8 z$ x0 _| MCASP_PIN_ACLKX
5 I( ?6 B [/ u: L# x; g( b5 V4 N| MCASP_PIN_AHCLKX; m2 | q# `: v& ^8 a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 k( @: O \9 k0 P; c% kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 l5 ?& W: {' ?2 A$ Y| MCASP_TX_CLKFAIL + @$ K: n" S6 l- @2 z
| MCASP_TX_SYNCERROR
$ d3 W& C1 _) Z4 c0 || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( Y$ p7 z" ~1 W- |' e. _: O) N. O$ g| MCASP_RX_CLKFAIL% \0 m6 \' {$ `+ Z8 B
| MCASP_RX_SYNCERROR 7 H+ C" y8 ?' q) r% @# ?
| MCASP_RX_OVERRUN);
2 Q2 W' \: U) Z$ @- p} static void I2SDataTxRxActivate(void)
3 Q4 {$ H( \- I+ X3 `' ?{4 g. B8 A% q# c+ b; N e
/* Start the clocks */ u" d0 `" j* p! d& D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 T8 N' A6 U6 N, K M5 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! E9 X4 F$ ?( [% N- o WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ |9 ~8 o3 o4 I" R7 w! i
EDMA3_TRIG_MODE_EVENT);& ^0 R4 P* a3 M$ J& H( l* ^9 `6 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) l: z) u# C) e" w+ OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 Q6 D: ^! r- L9 H, X; a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
K5 q: L3 O2 N1 P6 o9 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 g/ O* f( f3 R4 P2 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& r9 T0 i4 A8 u8 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 L5 X& d0 l/ I y( M6 u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- v+ `1 P1 V& U; N/ j q( X
} # y4 ^# `* a3 G% u9 d" A1 s Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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