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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ A( M8 V( l9 Z G" N8 Q4 d- X Qinput mcasp_ahclkx,
, A4 k7 t2 W0 l- B- e9 X% K4 z+ xinput mcasp_aclkx,
0 H- C4 N2 [3 Ninput axr0,' o! h( W: Y& y5 Y- ]$ `2 x; a
+ F2 j- H/ c0 ^( ^! z4 r2 voutput mcasp_afsr,
: ~7 H8 r! K+ @9 ?9 poutput mcasp_ahclkr,. K& W0 v( Y9 a1 i; b
output mcasp_aclkr,
5 \* k) g; Q- poutput axr1,7 K" p; r* j4 F* q( c! F7 U
assign mcasp_afsr = mcasp_afsx;
" `, V `5 M7 d( r6 o9 Tassign mcasp_aclkr = mcasp_aclkx;
% W& L6 {- B! [assign mcasp_ahclkr = mcasp_ahclkx;8 B7 M8 D3 }- I
assign axr1 = axr0;
9 |* Y6 Z3 C% U; ^& v* N( A" c2 l* x( a0 j9 x/ J/ |" Q& M! K) `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / b# M* n) ?4 k, o
static void McASPI2SConfigure(void)2 D, ` V& _; P. R! j2 f. I3 b
{+ K5 M+ V3 n6 |2 ~9 L6 R1 L. m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ~: d% N" ~" u; I* a) _: Q# C! kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% v( X% r6 @3 C" r/ ?% D* e! T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, A* m4 n+ `+ t# v( b- o% U% N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 y6 f- x5 ?% w" g0 N1 u+ pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, v6 l- c" W# f/ j$ h( EMCASP_RX_MODE_DMA);
- u) D& b* p2 f) @$ ~0 K( W5 ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," _7 p; z! o9 X8 M3 @& o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& o. a% ?# _+ V1 g$ h% l hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ r. B$ I& j/ F! l( U0 F- JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 J4 Y3 K! v4 J: W4 [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ t; Y/ p; q; ^4 Z& tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! b; y9 ~) N* O/ Q7 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# s3 L, t" p/ t' L( k. TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 W7 K7 ]$ }' y( _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 o0 F# _, j! F$ X% I0x00, 0xFF); /* configure the clock for transmitter */
( c$ e" C Y9 z, \! HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" ?% r% a! n$ ~( v( q8 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); B9 ?$ l% _* A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 {8 j- j! }8 ?0x00, 0xFF);
1 B: l+ N P y1 c7 Y/ l+ Y4 X) f( e6 g
/* Enable synchronization of RX and TX sections */ " a( S1 S; D; q" Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( h" F/ ^& O: V) a2 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; H8 z0 p- H2 a* E$ S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 }! P+ ~8 }( \' ]6 N, z6 A** Set the serializers, Currently only one serializer is set as: e6 z1 r# `1 \! L2 u
** transmitter and one serializer as receiver.( ], l3 X K+ Y; n9 p/ y5 K
*/' M; {0 y+ F& y1 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" A% y7 ?! A' _! D) q& D; qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 ^) m! u- Y, e6 X, u- i- Q** Configure the McASP pins
+ ~3 r: E' e9 I/ w b3 D** Input - Frame Sync, Clock and Serializer Rx- U3 z* b" H- p. Y* T3 D) z
** Output - Serializer Tx is connected to the input of the codec
# u- A* a4 }( t: O1 \, c*/2 u$ y/ _+ V% m. Q" M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; @% C! S; r* Q! E& K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 ?, C( D0 d- {, P7 e( t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 X2 M0 g, N o2 M) q
| MCASP_PIN_ACLKX T1 R- t% W/ |; L2 {0 R7 |
| MCASP_PIN_AHCLKX
3 }: V. T n' F& `7 @7 I2 V/ V# e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: \: g# l, b7 c) u+ h* CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 @2 r% ~& z: n8 W i, R7 L. a
| MCASP_TX_CLKFAIL + ]& H3 |% v Z! G( g
| MCASP_TX_SYNCERROR
9 q# {( Q8 o* V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; u, @ N3 X) G U1 o1 p. u| MCASP_RX_CLKFAIL
6 ^; [& O- Y- M3 J' _3 `+ a" G3 n| MCASP_RX_SYNCERROR % Z# [: ^0 v; k' J* |7 N- T* \- g
| MCASP_RX_OVERRUN);9 w( ^- _) q; m, B
} static void I2SDataTxRxActivate(void)
- M( G" y5 Y! A' I3 P: O- E{
+ n! j! Z: L' N/* Start the clocks */* p, s, d5 v7 U; j6 R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ d( p% R8 ]4 U1 {* O9 w" W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// W1 b3 O; i, d( r, m3 X) x* E2 N8 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 U3 _3 c& x0 S9 t5 j7 } X; L
EDMA3_TRIG_MODE_EVENT);# t0 @& d! x' n$ y2 P8 N; f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 `" Y8 R; X5 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ i) Z6 ?; ?" ^! V9 [1 Q% T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: h7 T b! @) N- G+ D6 I; c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 G" J+ K% N% A! I1 m3 p' T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# [- E7 H1 a4 }: A" |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 Z5 J# R) ~$ @2 k) g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ p% @# ^, \$ V' R- A5 k5 h}
7 J( b5 g( ?1 H! ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 `9 ^0 _8 j0 w2 \, a- h
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