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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ d) w7 K: A# s& @- J! y: ^& ^ y
input mcasp_ahclkx,
$ c$ E5 T8 _/ ]* L8 T3 ainput mcasp_aclkx,# e+ d( J/ j4 {& ]6 A
input axr0,
K3 W5 b6 A* }+ ~; H1 N/ V8 w& S# E: h" @% q& x8 i
output mcasp_afsr,
, H8 n8 q0 G, {/ {output mcasp_ahclkr,
! E& i3 A# }( h. `& ]; xoutput mcasp_aclkr,/ r1 \2 E+ Y) ]+ Q
output axr1,
* |& g$ }5 ]. v( H/ K7 [ z assign mcasp_afsr = mcasp_afsx;
8 z6 F7 \5 d* Dassign mcasp_aclkr = mcasp_aclkx;9 |% n/ s: R- ?2 b3 t$ B, L
assign mcasp_ahclkr = mcasp_ahclkx;
. @4 |2 }4 u, @ s8 j& f! v. tassign axr1 = axr0; 1 @! o5 q/ t6 X$ J* [% u
% g6 \9 ?# L2 f9 i {1 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( @! q3 D) Y4 f# B' d- Hstatic void McASPI2SConfigure(void)
! `5 J2 u8 {; [5 V: G{( D2 z6 V8 }2 Q$ R: y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 B' J8 Y6 |6 L1 ]# ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 e9 R4 R) d! `/ P5 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ X* p9 o. g$ l' v+ N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ C! {* a* \- }. c3 d/ c; l. G: y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 R( j( w: `( U0 f- XMCASP_RX_MODE_DMA);
0 ], q2 N# i: ]4 B! V& aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: x( k& E0 h+ B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: U' i$ j. ~* J+ Y! wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : ^ p" Q+ M! T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 \9 ^1 q' \. g% D" m9 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / `6 m* J: X8 E9 R$ t. z l3 D% W- L4 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# J L: W0 I7 D0 F4 C/ t0 r8 PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 w4 Y# {% W' d5 w/ c2 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 ^9 p, o, `; M7 r/ W* U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 l5 ~. j0 t4 X6 L% C$ h( r0x00, 0xFF); /* configure the clock for transmitter */$ Z9 W4 b5 K! b# h# e# s& t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; b- b5 a8 t3 U4 ?& C' V6 ?/ y. m) D5 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; i$ W [4 C# k" `, I: o- w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 W7 l y3 B( b* O* l7 b0 q. c0x00, 0xFF);
) p* K* T& h- z; o3 N
# V a2 \# W; M- H9 x/* Enable synchronization of RX and TX sections */
' @6 G7 {- g" zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ g2 k i" i* F+ R0 {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 I9 s3 W5 ?! P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! k/ K7 }! R# e0 B& _5 G) k** Set the serializers, Currently only one serializer is set as
; D% C+ h$ u- Y3 D** transmitter and one serializer as receiver.
% ^1 ^$ s. Q$ U& X J2 I7 ` l*/
& t5 o( M9 U) z$ q7 fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 j5 ^9 F" b2 W; s1 P- l. \5 y, P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! a1 K' g( x) e H** Configure the McASP pins 8 c' |0 @$ O9 I4 S1 |- S$ M
** Input - Frame Sync, Clock and Serializer Rx& t$ b' O2 `$ x
** Output - Serializer Tx is connected to the input of the codec
" @* W1 }( I+ u# W$ A# m% K3 x- q+ h( i*/; a, Y3 S) a! L' Y$ W2 b. d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 @) s/ z! t2 s+ n# CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; b7 C, A& k; Z, i7 k1 I# n, S1 l* ?& c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; i9 {; ~* ~, w3 t3 k1 c| MCASP_PIN_ACLKX1 x5 a0 H7 @$ M' x9 [' _( }/ P" U
| MCASP_PIN_AHCLKX
4 O# U' B, h ^( z+ G% E. {% \. s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
f4 [ L8 k% v2 B: r( kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 Z- ]$ h. j# \% T5 K. l" D) W| MCASP_TX_CLKFAIL
t$ z( O; {' g7 N) T| MCASP_TX_SYNCERROR' [" [5 ?5 U" e0 p( q, r4 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% @9 J( a# I- u& ]! R7 f| MCASP_RX_CLKFAIL6 z& g. w5 V7 A
| MCASP_RX_SYNCERROR & X! U7 o7 P) u' s) d
| MCASP_RX_OVERRUN);. e+ ^# e8 o2 ~0 X+ ^4 U7 @
} static void I2SDataTxRxActivate(void)% o# J0 A' j |* y& r$ m
{/ c, J6 Y4 b- L E
/* Start the clocks */
: n6 q- E* C& N" Q2 _9 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& K% O& t! B. n" rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( \1 L3 k0 w" s$ }' w1 p- qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! H- ?; X! F1 a- i7 T' Q- oEDMA3_TRIG_MODE_EVENT);
# U' ^1 A9 y9 }. D9 g# r1 e5 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 O8 {# O9 I- f3 P/ ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 M' e. y4 V' T& z9 Y, p! L6 Z( b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! \! v9 ^2 p) X7 f; c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// U, j' P. Q5 ]0 p" k3 Y' R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% b H) j! a5 T3 d& m: eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 _0 U( F( T+ A: v; Z' L% ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 y: ^' v5 q; z) U; [9 F4 E
}
b! B+ @5 ^9 P) k3 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' T) E( m r7 |, C6 _4 u% B: K
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