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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: Q1 a" G$ t! o" a p' M$ n, Minput mcasp_ahclkx,$ a, G0 c, j$ n8 B4 [' U
input mcasp_aclkx,
. U7 [4 \7 |9 b6 v! O) i* [input axr0,. {/ t; K& Y0 T5 `
$ L" n) }; w Koutput mcasp_afsr,
( J' M" Z* {: e3 Moutput mcasp_ahclkr,
3 f; I) H* b# }1 c5 Coutput mcasp_aclkr,+ d- L- h3 c2 f
output axr1,; }) R8 t# {4 f, ]& p- H
assign mcasp_afsr = mcasp_afsx;! ]# {% k0 Q F' \: _! `- T% c
assign mcasp_aclkr = mcasp_aclkx;
r6 U% S* b$ f8 ]% \+ f# Lassign mcasp_ahclkr = mcasp_ahclkx;+ P# j5 C! E7 _- Q3 ?) v8 z/ n4 q
assign axr1 = axr0;
3 ?- P' B2 i/ R' \. ?. B( n4 b; A6 _0 d$ q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 l, ~% |7 [% j7 Ostatic void McASPI2SConfigure(void): b- x6 z+ [3 a9 Z5 Z
{; x. _+ w2 e- k( B9 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. h' D' W Z6 I7 L, T% d! SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: a' m. z0 K3 R0 Q, R( Z* {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# g: {3 w7 `4 e8 u! {. xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; h9 S( c& Y( N* M5 r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& `7 {9 y5 B$ x1 B3 ~+ X2 E: q/ ?8 O' GMCASP_RX_MODE_DMA);
! M) U( {& @' h2 oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. l1 x) U8 H7 ?8 k X6 b9 dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// g# ]. |: t8 {2 O! N! h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% n3 j# C, w, \5 f4 s- L. }$ aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: ` U3 p- e2 N/ U' _) `# uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ~2 _1 q" s& p. h' UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- m5 e4 V. D: VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) M! L( D- g3 \, q# l- p: Z7 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% U) `, `7 T \$ A% o7 Y3 j' ]( FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" B7 @- e( }% A0x00, 0xFF); /* configure the clock for transmitter */2 q1 G) i- r0 q9 `" d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* W* y. A" q( O7 z0 v" L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ {8 w- Y2 @& l; @' b: nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ C6 S$ z8 q" w$ }9 @( y) e! C0 l
0x00, 0xFF); @" r: _: [6 ? m) o) A
% Y3 {% @) s C7 H7 `
/* Enable synchronization of RX and TX sections */ " f/ m; [6 V) ~* z; }4 l- J: n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% D8 A) B/ i4 e9 P. F1 N" t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 G2 A* [5 r9 V- s* [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 c# a }! S6 I! ^4 H! C
** Set the serializers, Currently only one serializer is set as
# ^ a* A, f) l; g9 V3 h) O** transmitter and one serializer as receiver.
% ], L7 N2 n0 z! z3 ~7 _8 n$ @1 y*/3 h* t# X3 Q, g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. U0 g* F5 L* [2 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 z7 G j2 O3 |" a0 p) j** Configure the McASP pins - e7 g1 Z5 e& j; x* ?$ d" T/ x
** Input - Frame Sync, Clock and Serializer Rx+ [3 [( N+ E7 D+ g# m6 |
** Output - Serializer Tx is connected to the input of the codec
9 r: P% r) a/ A; E4 `*/
8 I4 e0 Y R" a; V+ MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 M* o/ ]0 x, o2 \( S0 [. G0 o1 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% s! W$ s- O/ k2 T( z, V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; K3 h N3 {: a# ]2 E' G
| MCASP_PIN_ACLKX
( Q( _+ i% p' n) \- S| MCASP_PIN_AHCLKX; T4 o8 M* G+ M, }" q& Z! w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" b& B) R1 T* F0 q4 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 {. x+ T* D0 b+ Z+ K
| MCASP_TX_CLKFAIL 8 \9 m9 R% T3 \0 ?3 s
| MCASP_TX_SYNCERROR
6 d* m( q5 c. Z [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 ^/ j7 W% E4 r- o; O' @| MCASP_RX_CLKFAIL' |7 H& X! Q A. r% z2 Q* \
| MCASP_RX_SYNCERROR ' r9 n6 @1 c. H9 C: }
| MCASP_RX_OVERRUN);* n+ O X6 ] W5 Q
} static void I2SDataTxRxActivate(void)! T, t6 J+ K. ], J3 _& g5 Y
{( W. F2 f, y5 x' c8 x
/* Start the clocks */# L' P3 z' o- T+ `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ x, j7 x4 y, g) i+ h# vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 s5 t' p; R; c- G: R4 K7 g' X3 ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; r* P5 h N' k8 w: W) G/ p
EDMA3_TRIG_MODE_EVENT);9 W* E, t* g- X- H: i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 p5 b% {, N+ W5 B4 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 K: o7 {3 A1 o: x8 q+ Q+ ~5 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ a! E4 N7 a; M% M- A7 ^2 o$ s9 ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' T- R. ?: q9 S& U; t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& Q o# P9 s8 A4 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; y, B/ s9 K! H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. M( q9 }2 x4 L: `8 m5 h}
1 t2 h/ X' O0 e9 x! G& v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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