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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# y* B: o/ Y* Z6 s; u
input mcasp_ahclkx,
. D( A9 m2 V# `3 m, r2 i4 j& r& yinput mcasp_aclkx, s$ J9 g( h% Q# W- s
input axr0,
& F1 }2 E" ~" A; k5 `2 x. E9 \0 P5 W" w4 I
output mcasp_afsr," }) f. M. r, i, A9 ]
output mcasp_ahclkr,
/ D7 K& _6 k M% l' H, g; P% Noutput mcasp_aclkr,
* w. f* f5 T8 Q. D; e7 ? Youtput axr1,8 y4 o6 C |" D
assign mcasp_afsr = mcasp_afsx;! p+ C) e( u9 \+ k
assign mcasp_aclkr = mcasp_aclkx;! `& u' O# X+ b1 ?# `$ {
assign mcasp_ahclkr = mcasp_ahclkx;
6 j8 I, E7 A4 g/ V0 v, D+ lassign axr1 = axr0; 1 _. b' e. H( {
5 S! J( g' e& B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 s2 C' j) M, h/ m' r, tstatic void McASPI2SConfigure(void)
9 p8 S! Z& G& H8 z# }% e9 w{3 X# k% m, H2 |4 P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 a, L/ h1 A$ ?& A# @7 ]' D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 ~ @5 j% p9 g8 \7 e6 s4 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, f0 G, K5 n* p! n1 B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 c' c+ S, X0 A9 HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& c( |- j/ x, ]) r
MCASP_RX_MODE_DMA);
, i; D4 k0 K7 R5 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 w# N: t; ^: m* b9 N, ]- \9 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) A7 ~- `9 ^9 S* T& S7 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 u7 g' ^- l# M' w% m+ H0 {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' ^( w1 t4 T' s |) X- ~# I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, g: O- b$ E7 Z. ?0 Y3 ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 `# h9 Z) H0 W9 ^9 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ j; n% P* @- S& R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 Q1 i) k/ W& E9 p/ U7 z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" d- x+ ~! V3 Z4 n+ E! w# t0x00, 0xFF); /* configure the clock for transmitter */4 F2 i2 v5 j; e5 P k! D- l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% |. y- m' W9 n- j" ~/ c- UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- p6 N. d0 `# vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; t9 C3 @# B O* N: A6 E, D X" n0x00, 0xFF);
. F! ~6 [* @1 M# Q
( ~4 b, J, I" i9 c) e/* Enable synchronization of RX and TX sections */
1 w7 v6 r2 K: E; wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' M0 U& ^ } ^' PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' O i* ]7 T. Q2 c+ X2 v- [1 z. TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, s8 A$ c# [5 {8 [9 C1 `** Set the serializers, Currently only one serializer is set as
& H, G2 z/ X5 v# i! g3 S( F/ y2 i** transmitter and one serializer as receiver.2 U$ `# v3 F! L0 Y' G1 e$ C. i
*/( {# J' S" \/ ?1 T/ t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" K# r7 N3 Z/ ~( X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( |$ X t0 [* }$ I7 I4 X** Configure the McASP pins
8 z/ l, w# N4 Y+ u' {! |** Input - Frame Sync, Clock and Serializer Rx
9 X; r) X; R. c4 S0 j** Output - Serializer Tx is connected to the input of the codec + j2 u1 t) R$ B' _% ?* p
*/, Q' f Y$ n1 E
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& i4 E' |8 @. \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ F2 g8 e* D) [8 f) M S7 _ OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' V* b7 B: }7 y! _$ i* r/ m+ M
| MCASP_PIN_ACLKX7 i7 c1 y: d! E( U) L+ E
| MCASP_PIN_AHCLKX7 ~+ c" X( L% ~5 `8 P3 W5 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. r; i+ L9 ~3 Q# C) Y3 W) bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : V0 z3 M; L u
| MCASP_TX_CLKFAIL ! V- K7 ?/ G& P; X
| MCASP_TX_SYNCERROR
]" e- X) t8 i" ~* i B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% ~& G) E% \9 ? e. L| MCASP_RX_CLKFAIL
. V4 @: A" G1 r5 t' D6 ~| MCASP_RX_SYNCERROR : v' C0 V3 _( K1 b2 A, s! J7 [
| MCASP_RX_OVERRUN);
$ f* K& N) \9 u' [! B} static void I2SDataTxRxActivate(void)
# m8 @, ^5 a& `7 m% Z* A, ]( E{
4 ~+ @6 ^3 |4 g h3 o% u/* Start the clocks */
( v0 E, X7 ^/ Z4 N* ^, A: WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 @* `9 D2 s1 R J5 a! g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 b, ~' h1 X/ d( A4 M$ x% }* e4 o+ uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 ~, J0 Y+ U9 p; u( G, ?EDMA3_TRIG_MODE_EVENT);
+ Q. W" u7 z5 m X* |) uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
X$ d' y8 Y5 g% a- N! {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 @: I) k% Q$ u. I& v2 u" L+ W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 i7 R t8 f- ^! u, i2 ~% r4 j2 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% U& f$ ]+ X7 i5 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 [+ d& a+ b% V% Z4 O, y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' Y( N* a5 ~( W: x+ y7 y; HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- a1 D! G! n" S' B& M}
1 H$ W# d7 F. n; K7 T! u3 ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : e& Z& R- Z, S: D
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