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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& F2 S4 o$ A$ O# g) Ginput mcasp_ahclkx,
- L# T" {& `# I4 [input mcasp_aclkx,
3 i9 m/ Q7 b1 @input axr0,9 V- v2 L5 p4 H$ c8 z3 O
1 t, c" U5 g' W* voutput mcasp_afsr,
$ w. S2 @1 Q- r7 f+ D v: Uoutput mcasp_ahclkr,
3 n$ g$ G" `4 y3 L) voutput mcasp_aclkr,) y3 F: U: V$ w
output axr1,1 P, H4 q0 J+ X% K# X
assign mcasp_afsr = mcasp_afsx;" W$ O W4 b: m# N. g
assign mcasp_aclkr = mcasp_aclkx;4 J0 W) u; u6 n, N; ]) x4 f+ U
assign mcasp_ahclkr = mcasp_ahclkx;
0 w# t8 c3 [0 Y6 [0 W- w9 e; rassign axr1 = axr0;
4 J! I r3 y2 f9 X F+ S) S
/ q5 r4 G9 R5 L! c. Y. t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " W3 b8 e5 A# N* c$ q/ ~
static void McASPI2SConfigure(void)2 t" V5 ]5 i9 n V# d# A
{6 V1 e) L- @ D4 R3 d9 r8 M- B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% E, W9 e% K% p' }McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 n! O6 u3 M7 r+ \! iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ T3 g' W8 t- D5 e) k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ l! |5 H+ U6 ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% \1 Q! V6 P3 J+ |3 m
MCASP_RX_MODE_DMA);
9 c" e1 M. a8 R! a q1 l: bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" w( q' X' L0 {- {8 H! fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 ^ i8 ? g# h O" N/ v9 Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: v2 R7 n' N! t9 M( A! u4 CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# J. v) Y6 n7 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, b$ a3 ^6 X8 _; O0 e% t! tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 V5 L# ?' T3 c L' D' C) R. LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) A% k- P" O& w+ T8 @3 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 X7 l4 F7 q1 \ ] |, r; X/ RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ S, s3 F: X" E" N0x00, 0xFF); /* configure the clock for transmitter *// A6 Q4 B4 |0 [% H" Q% O7 x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 t3 K' X1 f/ N: F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' a+ h ]) }/ T1 T) G7 o* H JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) U' I, ^0 e, G8 }0 l" ~3 g
0x00, 0xFF);( `( g( Z; w# }
% n! ~- D- d/ l& @) ?/* Enable synchronization of RX and TX sections */ ( v! S9 C8 \) W$ o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% U0 Z7 `' n3 F M! R; V( F: [( lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; A7 P" k* e: J1 I! \- w% r p' UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" W! Z. ?- R; ~: p8 r A** Set the serializers, Currently only one serializer is set as
5 g( Q6 g; F& ^9 J; p** transmitter and one serializer as receiver.( g% f, S, @! G
*/
3 Y5 J4 F* a: ]" zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, h& S5 D7 K! y' ?7 `5 T& B6 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 f- T9 W6 D6 G" }$ y1 ]
** Configure the McASP pins
0 @6 ?* {' |; k' ~ G2 S** Input - Frame Sync, Clock and Serializer Rx- `6 T) C3 r8 _ p: t
** Output - Serializer Tx is connected to the input of the codec $ e$ V& E0 U V% Z0 U0 ^7 n, o
*/
. g7 X& H+ a/ [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ w- z4 G: v( M' W- ^4 e' K, Q7 ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 |# V% p# ] L. mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. W( ?5 V9 m/ O/ o3 ]. F; p| MCASP_PIN_ACLKX$ ^ S' ]; L8 W
| MCASP_PIN_AHCLKX3 t* v* M( `3 `; h! q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 m4 z- h% r" W5 O- R% x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 P: T% a4 D7 |7 p| MCASP_TX_CLKFAIL
, o) w D- F& R7 j| MCASP_TX_SYNCERROR
. e% i s# {6 r& s p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( b* q$ o, e" K# X| MCASP_RX_CLKFAIL
# D3 W2 S' x* y: y/ h0 B v| MCASP_RX_SYNCERROR
: t J8 M$ u4 R+ V7 Z; V' t| MCASP_RX_OVERRUN);1 w" L& t1 E) ^
} static void I2SDataTxRxActivate(void)' S$ Y+ N5 w8 ^5 X
{
( x8 i5 T+ ?5 }* S/* Start the clocks */% E. m+ M9 N! ^( f# z6 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 }' I$ E- ~- ]# u5 w, ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 S5 K4 Y7 K: MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 N+ {* Y, l0 ~9 z
EDMA3_TRIG_MODE_EVENT);
- Q* p `- a8 i- aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 H x5 t; ^, Q. ^" U8 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" v+ G+ J9 x! i5 i* E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, I7 u$ i& }, y/ b! O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 G+ K: {6 f& i, A# a7 u3 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 T' H, U* \" D5 x1 r A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 T( D, t" m# o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 t0 U% @4 q" ~7 W- O1 m}
! g2 s% v! C' s+ H( y3 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ d* E4 f% E; L0 b
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