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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' S/ o B, p% |. Q' O$ z0 f
input mcasp_ahclkx,
# m# J% P$ u% _9 D$ m1 qinput mcasp_aclkx,; U% s/ R7 _# `. ?
input axr0,
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output mcasp_afsr,
" x5 G. s3 X& a8 H9 u/ A0 coutput mcasp_ahclkr,$ t5 d6 l4 Y3 R
output mcasp_aclkr,
, L3 ]. l+ o' W" B5 j3 _output axr1,
* P! y$ {: V+ p- J; A2 F3 i assign mcasp_afsr = mcasp_afsx;8 ]' y/ w9 j5 M. {) O
assign mcasp_aclkr = mcasp_aclkx;
( c; k/ B; E5 Y) Eassign mcasp_ahclkr = mcasp_ahclkx;+ }& w; I e5 l9 v9 U% E
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 p. r; i, z* v& a+ vstatic void McASPI2SConfigure(void)* l# V, ?2 g0 _, P
{ G K. T+ Y# m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 g. U! P( S; m* u j$ uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& p6 C1 V$ Q; ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ L0 j5 y5 `/ r* B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 p* p! W5 @9 D1 K2 q5 S1 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. l( T) H0 I# p5 _# H0 [6 X( d
MCASP_RX_MODE_DMA);
( U1 | I l' h, T# x4 A6 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: p1 z9 S& ?8 D/ ~$ o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# e8 b4 T- j5 g5 D/ u2 O1 w, \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; |* Q" z+ u! Y; e4 y8 \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! R$ e0 x; H2 ~/ \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 b. y2 v( A3 w, i2 |1 C: e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// S! T0 A$ G) p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* l0 v5 K* J# b P% D. B) u& M0 P, MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & F3 y) b5 G3 t% \: J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 H& w @* H: B8 {1 k0x00, 0xFF); /* configure the clock for transmitter *// Q( H/ ^+ U( i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, O5 t+ w" N7 S# x3 n XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ H/ g8 {$ U+ H* b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ b" }# h3 l# R) p1 U/ H
0x00, 0xFF);+ w% N. x" M6 @& G+ X
5 x6 L+ C. \5 F+ N9 g4 u9 u/* Enable synchronization of RX and TX sections */ " Y7 p4 @ ~( k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! D; X: m( J# y* v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( R- I; O) F0 g* J9 d K2 v7 B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 F# L& w9 K) M# U6 v** Set the serializers, Currently only one serializer is set as& E9 i+ P! m# C; ^$ d5 x
** transmitter and one serializer as receiver., R( c8 j# l7 S$ t9 [6 ]
*/
. S/ Y+ C T8 p0 K0 {+ H AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 y0 c: N E2 c, y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* h \% q0 V" t' G/ a6 H0 F3 c** Configure the McASP pins
- v& \% t" d/ b T) s** Input - Frame Sync, Clock and Serializer Rx
5 Y0 K* a: j' L u5 {+ t** Output - Serializer Tx is connected to the input of the codec
1 K. W( z0 a1 T*/
( g9 k7 K6 L$ l4 E: o. nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 m6 t1 w, \5 G6 P2 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 P: l* X* h: M# F3 ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 `9 c* [0 s% ]' t. Y
| MCASP_PIN_ACLKX: x/ j1 B( p0 z/ R
| MCASP_PIN_AHCLKX
/ l0 _* ~, M5 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 G) h6 x+ ]4 j* ~" d" L# \( C6 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! U C( r e0 n
| MCASP_TX_CLKFAIL j. T" i7 P, u; x; B
| MCASP_TX_SYNCERROR1 _8 m! u$ ^# N0 |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # e! |3 j# X' X: V
| MCASP_RX_CLKFAIL5 `6 [, t/ s% x# D1 w' C
| MCASP_RX_SYNCERROR 4 r" r& \; J2 T5 ]' {4 E
| MCASP_RX_OVERRUN);
/ H7 P9 O* ] c. K( @} static void I2SDataTxRxActivate(void)- [; q; \7 ^ ^2 W3 k, U
{
, y5 }$ L& j0 {$ ~/* Start the clocks */
, e4 Z2 P# {; @& f/ NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 `( w5 E; p& u/ R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ G6 b! I0 H' Y" Z0 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ W7 ]/ j1 N4 h1 b5 X' S' J# E
EDMA3_TRIG_MODE_EVENT);9 }9 I7 V% v! v) g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! H6 B0 T" E' G9 {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) O: E+ G# v% V) A v6 v$ X" B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) G) ?" Z4 U# I! s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 h: w) p" w3 P3 q+ e$ f9 q% i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 s. ~7 e4 F0 w# e2 Y: U7 h% {* j7 ^, \/ KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! P2 N' ^1 i. B* \% VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" U# h, P! ]8 b* T- a
} ) F! o2 a ^1 W/ q2 F, o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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