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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# O" Z6 i7 h* P" n4 D( V0 _! {2 Q; Qinput mcasp_ahclkx,/ ?" F/ ~- C) d5 b; D
input mcasp_aclkx,
8 M6 L4 h2 |; p0 `" Ginput axr0,
) C/ d/ m, C! {7 p( x$ i" G' a( b. I1 s, z8 A$ A# t
output mcasp_afsr,4 l: }8 D3 Q# |' K& x
output mcasp_ahclkr,
9 x/ D3 n; B, r' \: \5 O8 Qoutput mcasp_aclkr,$ R( b5 P) S# b6 V% t/ o
output axr1,
1 z1 _! m* ~% P& z& ~( s. k assign mcasp_afsr = mcasp_afsx;
+ `4 w" y: Z+ S% Xassign mcasp_aclkr = mcasp_aclkx;
2 m% ?7 o3 K7 y3 H$ J2 xassign mcasp_ahclkr = mcasp_ahclkx;
0 x# l8 _ q( Jassign axr1 = axr0; 5 g n3 Q4 U, _- z# S
6 B' J8 @' `! d1 i! H( y' m1 [在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + L: L; Q2 L. w: k6 T! I+ ^
static void McASPI2SConfigure(void): L) ~) Y0 d$ Y% ]
{( O7 i9 w8 H5 o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& R1 G2 g' [0 D# X5 y: {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. U6 z1 k) E- l5 j1 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 y* }& z) e) W1 v6 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 s* l# [, p: b8 k0 [. R l! |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ^4 [- E" R0 B. V- b1 fMCASP_RX_MODE_DMA);
& X% P4 j' _( G1 SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% z/ @3 L3 r. D" i( Z2 c1 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
k# W4 ~- A5 IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
Q3 t4 d# ^! C0 u4 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* A/ `4 Y% D5 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 m1 v5 k7 N$ Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# p d$ P; q4 i$ z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& \2 r& k: K$ U/ e& }: H7 C* Z- D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% s# M v8 R+ X5 QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 o: Z8 q; | N( h
0x00, 0xFF); /* configure the clock for transmitter */
' q0 L9 Z+ ~5 C, c7 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); r5 G' Q$ `0 _8 e0 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 N7 h2 _7 n' q; F# I2 F9 P+ DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 T6 I/ E. @0 W Q C( H) ^6 {9 k
0x00, 0xFF);
, ?. f% {+ H- X# N$ J5 N2 q9 F3 V7 E$ {' E3 E" l3 B* M
/* Enable synchronization of RX and TX sections */
4 f0 W! W1 P& E8 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 c7 d+ _8 K) @$ w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ G$ y+ z H: j1 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ i7 I' f+ }0 m$ W' Q% S5 n5 C** Set the serializers, Currently only one serializer is set as8 j5 |5 [, X* Z9 ^% w
** transmitter and one serializer as receiver.
Z/ i& s5 z- _/ i+ u% Y- g*/
- l& g8 e$ k& F- I5 Y) V% dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 r- l: X# T9 [" f3 u, L0 c. ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' A9 F8 K2 O3 y** Configure the McASP pins . k$ L, {( B& r& H1 h1 S1 T9 S
** Input - Frame Sync, Clock and Serializer Rx
# I$ ?! J5 R1 }! T** Output - Serializer Tx is connected to the input of the codec % H. d3 u1 Z- u) v1 ]
*/
2 R# B' S- \6 y& ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! e5 D. c" ?9 y- b2 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ Z6 {: c+ ]8 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ `) [: h1 D6 f* N0 H: m: q
| MCASP_PIN_ACLKX0 @: T! I" c7 P( d% w
| MCASP_PIN_AHCLKX
6 O" X! Q' Q* o ]/ H9 l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 p1 z( R2 e& G9 n+ s; ]6 k. L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 S* R$ S. ~; C- R% {. ?| MCASP_TX_CLKFAIL + v1 l$ o$ C, a" b5 |$ U/ u
| MCASP_TX_SYNCERROR
9 o+ p0 f R7 f0 X! o8 V4 X7 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - g2 ^. X$ c5 H: W/ X d4 |) B$ E
| MCASP_RX_CLKFAIL; e8 ~+ n0 z3 U& p
| MCASP_RX_SYNCERROR
( F2 I2 [* U6 F, b0 D| MCASP_RX_OVERRUN);
& R+ u+ M$ A" }: a( G} static void I2SDataTxRxActivate(void)- @# J$ |5 m1 C, x
{
! I1 e, l# t- y$ B% n; P/* Start the clocks */
6 \* ?1 }4 A* h1 ^( YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 T8 E9 u4 ?; V& X7 Z# L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: X$ l q! w w m: _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 ?* Q6 V: {9 X) h8 C; M, i
EDMA3_TRIG_MODE_EVENT);+ Y6 N! }: x7 n5 K2 V- \% |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / N0 T' v% d. S* U, l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
R) e8 k3 L$ r2 f. P1 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. O0 {7 h' A4 |* ]. yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
{6 G1 E9 o0 [6 Y0 ~, }# g# Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ ]7 W/ Z/ v: y8 E; o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 a3 D- A3 i9 r+ A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! w' U: E# A" J; N
}
) ?- g' q* y' P: l- ^1 i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 w* S% w7 A$ ]+ a% M, d
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