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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! p. v/ r( `4 [3 M! y4 einput mcasp_ahclkx,
* s) b7 z, o/ f) hinput mcasp_aclkx,/ b% S) p4 R- ~0 U6 X2 _
input axr0,, ^" J! Z9 p6 G% j5 d& ?! A0 g
2 ]7 h, ?& O [. f. _& Y- H
output mcasp_afsr,; M3 U; e' V4 X# g9 S! x9 u
output mcasp_ahclkr,
+ g0 |9 |+ ]" A# f) moutput mcasp_aclkr,
0 T4 k& V+ V, Y1 doutput axr1,3 S$ ?5 H9 M' \+ u3 |
assign mcasp_afsr = mcasp_afsx;; q4 ]& [- V' B& O3 F3 j, l8 f
assign mcasp_aclkr = mcasp_aclkx;
1 N& j4 V: S7 }+ w. b* Massign mcasp_ahclkr = mcasp_ahclkx;
) N2 y8 u8 E' f4 \2 n* Aassign axr1 = axr0; q, @( `$ h1 @- r/ f1 Q* z' ]: \
$ B, h- J' P( a# A+ r" \* y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) l; g: o( k6 ?' y7 B2 p$ Fstatic void McASPI2SConfigure(void)
8 M5 H, Z% X1 o, L1 x{5 J9 J- Y- `5 X- ^; n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; c- D0 C+ q: x4 Q- `* e9 z$ _2 e8 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 V" r) s4 W/ \6 B% _2 I1 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% j! T" C5 \8 }* K" h% j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) o( R. }) u: G, Q X8 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 c& B+ I( Z3 r6 F
MCASP_RX_MODE_DMA);% w; q/ E/ P. u$ c6 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ v0 a( k# ] N: o# E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 [: u5 y, W8 o' a1 y- J0 J8 f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % l3 w7 g& Y: f- z) C0 C6 k) ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' M- b, t, k+ i% [# u2 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- U( R* j# ^) u& mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 i' ^% ^/ h+ u! EMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 K( f3 B6 L( m2 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 J! ?2 ?+ c/ X5 F8 i( pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( @7 |/ Q3 A% G, {0x00, 0xFF); /* configure the clock for transmitter */
4 ?) E+ M) U6 z/ g7 t' c- {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! B/ b4 p2 R% y6 X" j( ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 U. @3 m0 ~$ o5 b% CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* Y: y, v7 Q# k1 a9 N1 U0x00, 0xFF);
! t5 w$ v* l3 ]1 H& v( _1 K7 f8 b0 k4 [! `: V" D- ~5 ^2 q- |
/* Enable synchronization of RX and TX sections */ 3 g, @. c J" ], h! d+ K! z. n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 I2 q* _( _3 Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( \, i0 K2 f6 N7 t l6 q# M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 Z/ |3 G/ g6 ]% `
** Set the serializers, Currently only one serializer is set as+ i' C- d. M* E
** transmitter and one serializer as receiver.
d1 d7 O7 K* F( E8 d6 M9 ]6 L*/8 E$ ] Q5 v; y- X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' C; `4 I, s, d, x' O) RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 l* P; a; l0 h3 F1 d** Configure the McASP pins
" u0 A0 ^3 r" s0 Q** Input - Frame Sync, Clock and Serializer Rx4 Q6 q' U T6 Y3 R% L
** Output - Serializer Tx is connected to the input of the codec 6 \, Y" o( M2 k0 n
*/
* U; M& {. \4 Q4 ^. `; QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 s3 n1 V! Y0 Z; m2 V( f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ v, b6 c) R+ D# e7 RMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* {( S b, e" H; D2 [* Z3 Z
| MCASP_PIN_ACLKX5 W0 n9 h- \8 m
| MCASP_PIN_AHCLKX
1 G1 k& r3 n, B0 @6 i' V; U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% f+ x' k, H% d l0 \1 yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % C3 n/ w) E, r4 T7 _4 a3 l5 D, G
| MCASP_TX_CLKFAIL
' U- `" b3 x# e/ Z) o2 q| MCASP_TX_SYNCERROR3 p' g! B8 Y+ n K$ R
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( ]8 f* \8 X9 p) |* ~: U% F+ B
| MCASP_RX_CLKFAIL5 y# _+ F+ f) r4 R/ r6 G7 o
| MCASP_RX_SYNCERROR 4 Z4 j$ Y D8 ?& D- a
| MCASP_RX_OVERRUN);, d" c7 N6 r0 ?. O
} static void I2SDataTxRxActivate(void)' d1 @$ ?2 a w; J& z, {
{
! \! }0 F9 l" ?# ~2 L# K! ]/* Start the clocks */
2 K; [" P. E+ ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* T/ c$ c3 M& }1 t- e8 _- v! k, p1 t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" f) `- S4 B. K4 ]. N: q& M! I5 x: ~% p: i. fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- T7 G; X/ `7 ^- c
EDMA3_TRIG_MODE_EVENT);
* t- N6 \0 b0 [8 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & o" I5 q# j0 n: T* p: B t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ Y2 `6 H; Z5 e/ L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" S! |3 B4 N& p0 u$ J' [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( W) p7 ^9 m1 B) E! C; j) awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, f* n6 k& n p" w, Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 @* t; } Z9 E2 Q- g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- n6 I; f/ I- H+ L: [4 y) {! [/ m} " w+ ? M# u0 i. Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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