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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
]5 F5 C' [* n0 }input mcasp_ahclkx,
3 x3 H% S0 c( `! `( R* Oinput mcasp_aclkx,
2 X. @/ U) W! R' d7 \$ Winput axr0,
6 V2 n; W7 G5 P& e0 G+ H
; Z( T, s) i& R9 m; q, ]output mcasp_afsr,
# m- Z% j; K. i' O( Youtput mcasp_ahclkr,
3 u% X. m: A( A; i* k8 Loutput mcasp_aclkr,6 p' z3 v% G: R, y) A4 r
output axr1,
$ o! h: @/ f' ]% C% |% t assign mcasp_afsr = mcasp_afsx;
) E5 X4 D/ Q, ~; S9 T/ Q0 Bassign mcasp_aclkr = mcasp_aclkx;
7 v4 w; _2 `% V( z, sassign mcasp_ahclkr = mcasp_ahclkx;' l, W: b5 ^$ V+ j$ N. w
assign axr1 = axr0;
: s" Q9 t+ X" @# h1 ^& f8 \
3 E/ W$ c, ~ }& P: m1 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) g4 |1 z9 E! ?. P4 I! Gstatic void McASPI2SConfigure(void)+ i; F# T7 v V3 f
{% `# ?# Q5 S1 b ?7 R3 `& o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' e+ P* [0 \9 ]# e( l4 ]4 M) p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ a7 j0 ?& C ~! J; o' _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: I7 x }7 n: @! f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& q# S: F: j1 ~) FMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 P( D& D. l0 ^1 MMCASP_RX_MODE_DMA);
# \7 N! q+ ?0 C4 D$ b: {+ SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ f) g8 d& {& O7 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) {) W: H0 x+ @* \3 N) ~$ }- rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 a4 q l9 a6 t% I& v( `" ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. `" o& N2 Q/ b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 V2 N( t' D6 h: a% HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ F I, k) `/ M; M4 o9 \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 k" X6 }( p* d j7 Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. s( e( X" |: } m& l$ eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) c" ^7 ?3 n& S" Y& p- P
0x00, 0xFF); /* configure the clock for transmitter */
+ W/ \3 p1 p' D1 Z) R2 Z. yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# `/ }6 ]! o c! g, NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 {/ g& R/ s. w2 W0 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 H: V" S. h8 `0 L3 _3 a& s0x00, 0xFF);
( p4 G$ K6 s0 G6 `' [) D
$ R8 k( o2 Y/ p% j5 q$ f/* Enable synchronization of RX and TX sections */ , j6 D% p: Q, J8 |/ Y- w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' L9 J8 n4 V, X2 Z! rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* {# @5 z) [6 h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 G& V/ u6 K+ v6 U% n
** Set the serializers, Currently only one serializer is set as
# S* d1 {2 I+ N, @0 E** transmitter and one serializer as receiver.% W2 Z- r/ H0 L0 S& n8 s; N: @( C
*/' |1 j+ _1 s1 {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
W' g) J) q' }- ~: |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 f0 i( C$ U8 j+ J: R$ Q** Configure the McASP pins " Z( C4 f! ^8 D9 J4 n
** Input - Frame Sync, Clock and Serializer Rx
4 F+ S7 w1 ?8 A) L7 R, l/ v% j** Output - Serializer Tx is connected to the input of the codec ! n# c. H2 |0 C) o5 m: g. m% e
*/% \6 p1 f' L- U9 J" u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 y1 |5 h( o' y9 E% c9 uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 ]- } X& n. a) xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' z( k( U" e/ I6 Q& F6 J
| MCASP_PIN_ACLKX
# \$ u3 i# k! t% I| MCASP_PIN_AHCLKX w k6 _0 u+ u9 V; i* g$ M7 W ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( e: x6 f8 x/ KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 Y6 I( L- ~$ {: \" I) w| MCASP_TX_CLKFAIL
2 u1 [% m6 y. Z8 }, N2 q. j| MCASP_TX_SYNCERROR
$ u! a) `& Q8 E. n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & ^- U: G$ p# V$ ~4 r" N8 Y
| MCASP_RX_CLKFAIL
, j1 n2 D- _) `* o, {| MCASP_RX_SYNCERROR k x2 Y" r; |) [5 X) O1 X
| MCASP_RX_OVERRUN);% a5 H; x8 t$ i. \8 I' n
} static void I2SDataTxRxActivate(void)+ \( o9 k# g/ g/ k/ X
{
3 B/ ]1 H5 i* H! r& H/* Start the clocks */6 \% c3 C2 P7 V+ B( L3 `$ \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 j$ C3 j) V' H. S& fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" E1 L0 y5 a% i B' _9 B E CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 @1 |. ` B' `7 XEDMA3_TRIG_MODE_EVENT); _6 s1 r2 a' s. v4 K! z" e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ p& ?$ a9 Y& n- \- d, ]" mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 y9 g% I p0 u. \- xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 o& ]* u: D0 o5 Z- h, a7 \1 m' V1 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 ` O+ @: T% S; l m+ S7 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 s5 B& I/ r. I& S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, ?7 w) Y# W, P% m# b" E% i5 ^% \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: E" l$ |+ \5 `# R" a} 1 y! f0 b4 K% q* o" E( c/ j' p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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