MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
2 _  r5 p5 {) a6 Q" Y7 F$ w$ @9 s& Jinput mcasp_aclkx,
input axr0,

' z4 K6 Z  K; x- b. I6 b' c: \output mcasp_afsr,
output mcasp_ahclkr,
8 ~) R/ C$ f5 v4 m, M" woutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
/ ~5 s7 |) E3 [6 \! H3 Iassign mcasp_aclkr = mcasp_aclkx;
$ _: j' f- f7 L8 h  s$ b) W- Zassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

! R# w9 t3 T8 @7 Y) `- ?, A" p

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! A9 F# W2 J1 F# a# V2 aMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
! i9 k6 n& B2 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ e: O8 k6 h" p7 e  F1 o; {6 NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
( w" @& g% C9 F3 n) D0 _* x, E) v1 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 J" s# E8 x2 p/ Y. ?$ EMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 h, e" O" X; p# b, P( {; p" @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; e' X2 a" Q2 g' W& D* AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( n% W2 _( |9 j/ |# m1 uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
: P1 i7 M6 d: E& T  b; YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 I( ~: ]! I4 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ?' }* |# g' o6 s0 ?0x00, 0xFF);

/* configure the clock for transmitter */
+ b' y% y6 r6 J- n6 d1 T7 XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
  B0 T" ]" C* F. f2 Q. z3 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
0 F: P. C  J/ d
7 v. e0 E0 j" H! x1 }' t/* Enable synchronization of RX and TX sections */
  Y0 a* K- r3 ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 T' l& I. u( y! ?4 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
0 L) F$ A2 \7 Q** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 z. m1 a. d3 C9 i% PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
% l3 }& H# ~7 b1 X# u** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
3 Q, _) |; V* w** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, w4 U4 j# @5 p( p6 A! B; {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ D" c) `- N) m( h1 w8 T0 n4 N& fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
/ g- Y$ M7 C# o3 s% ]0 qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
# K- Y3 ^* f% q2 t$ @| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 x% I2 J' z3 v7 H5 z+ u| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
8 j3 z+ G0 S- ^% k2 N+ x3 ^}

static void I2SDataTxRxActivate(void)
3 r3 B# g+ g" l- @: n7 }# u# E{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
. j5 U% T' v0 ]: x2 r& W. @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
- p: E& p2 ?5 q, M- N( P$ XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
) L% W3 h7 m+ R2 w& U) FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 h/ j6 h4 R- w1 C$ I1 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

, G5 L# a+ ?7 a: {

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

9 @# ]8 i9 ?3 H: K: k9 d