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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 t# [4 L- T. g+ p5 M% T+ Y
input mcasp_ahclkx,
$ h& u% _0 p$ z, I$ yinput mcasp_aclkx,4 D8 g* |3 x/ n0 @: l
input axr0,
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output mcasp_afsr,+ {) o; e y: X7 y: H4 l H: o+ o3 \
output mcasp_ahclkr,1 k1 R( h( w- B1 i, C
output mcasp_aclkr,6 d$ o: ~9 e8 ]
output axr1,
5 u( Z2 g, G. f, R assign mcasp_afsr = mcasp_afsx;
" Q/ ^& ~- H: v8 ]" |& bassign mcasp_aclkr = mcasp_aclkx;
: ], P1 w& x8 P2 R! Yassign mcasp_ahclkr = mcasp_ahclkx;
o: p: c+ _5 w! P% b4 Kassign axr1 = axr0;
% p, t* A3 l, f# O5 R0 e" F
; Q" e* k( Z7 }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 e1 O* e: W6 b b
static void McASPI2SConfigure(void)
+ r; X2 @9 P |* M8 \{8 i) h \$ J/ A4 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) {4 k, \8 E& U7 a$ d0 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 m0 m; N. x( J4 T: q K& TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; `) n) |" r( K2 H$ V, W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 l) N% q2 Z8 I/ J& |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! |& W+ ~1 ^& ]- b9 w0 hMCASP_RX_MODE_DMA);& P3 l: k8 Z5 Z" O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 n: Q7 ^1 q# j9 P5 I7 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: |; N: M% G8 p& @7 YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' c( C/ ]& j1 I. c3 t/ VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% G* g; m) H. C' a1 B. h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & j$ [& d8 B, r' N, p k5 B; }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ w$ e w3 q" G* R5 G8 I% w. T. eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, U5 s/ I. Q( u7 H/ U/ b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* F& u \1 A9 I& j3 B) EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( O3 o0 u9 D* l& B2 _& d0x00, 0xFF); /* configure the clock for transmitter */: o& M. e% x$ k" H' O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 y4 L( n+ H3 P6 s k+ x; Y; I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 U# x$ Y+ E: r( P* {7 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. S# j. h% W b% k0 p3 X0 k. {' L
0x00, 0xFF);
! j% _! [: |! ]3 m. o, K9 E8 b$ p7 B* L6 L9 F+ {. a
/* Enable synchronization of RX and TX sections */ + ]9 Y9 }" ]8 C, t; `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 Y+ B$ Z' w. p( F7 W8 ^0 x& A1 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); x d& p3 P" R- ?3 C& p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 E r/ ^' f( C$ k U/ W
** Set the serializers, Currently only one serializer is set as$ Q5 h7 F }: z$ ]- Y y
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 g4 f, m0 j) D+ t' `- E7 W* T* pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ w" C' N) Y3 W9 w6 Q
** Configure the McASP pins
E1 X) C( |& i; R** Input - Frame Sync, Clock and Serializer Rx
# X3 o6 v" J8 D** Output - Serializer Tx is connected to the input of the codec 4 c6 {% G7 v/ p+ H
*/
+ Z6 X1 s6 ?2 |. C( `4 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 M; e$ c$ p5 G$ O, h: r% U- xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ?( |( y! `7 v1 c3 ~6 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! [" P( Q3 X+ e" ?9 G' F| MCASP_PIN_ACLKX
6 [" A8 T6 Z/ J| MCASP_PIN_AHCLKX5 t7 L2 O% |# {1 N& W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( \7 K: T& b; X* tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" M5 t# H4 ~, T( Y' h+ T/ ~! [| MCASP_TX_CLKFAIL
D: h9 A L8 y! _| MCASP_TX_SYNCERROR
" s2 o' `: k& ]4 c" |' a* Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 L3 U& l+ a. D1 d) r) p| MCASP_RX_CLKFAIL
- X% A% g& g& i+ d" M| MCASP_RX_SYNCERROR + d5 |- W' W+ o9 {0 d4 o
| MCASP_RX_OVERRUN);! H* K7 T# l3 T! {2 V
} static void I2SDataTxRxActivate(void)1 j" ?: i( S7 I- |! i
{
3 M/ M* L G/ S+ d2 _/ O, Z/* Start the clocks */8 {0 \* u) Q$ r# Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& M5 D: c; P2 M5 e! X( L( ?5 l! DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 \0 U4 |: B. e8 d' a9 E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( E I! f: }+ B( M
EDMA3_TRIG_MODE_EVENT);
' j7 v0 y6 t" r* jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 h6 i; p, t& L. r/ |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// l O' T+ t8 m+ @4 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# C9 {+ w' \6 p4 L, }/ j& Y2 H& k% C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 [: d- a8 S, ?- l# K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ o% [) b9 T0 X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 u( L7 G0 l3 A/ K9 w+ TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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