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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; K9 J& Y2 e" i- P7 Iinput mcasp_ahclkx, s! Q4 X) I( g# `1 l
input mcasp_aclkx,3 s" p3 c7 F2 j7 X) J
input axr0,
9 X8 Y; J! C, w0 R. ~" k5 Y
( p8 Q& H5 L5 ? v6 V# x4 p0 joutput mcasp_afsr,
! a/ ~% O$ Z- B n0 \' Uoutput mcasp_ahclkr,
7 o$ j9 ~, G' o/ E7 F0 w$ D+ _output mcasp_aclkr,3 g& o1 |$ \) T0 A, a
output axr1, f( z; M! S7 y" V1 l8 {- D9 d
assign mcasp_afsr = mcasp_afsx;
' }7 C$ @6 j# _& Vassign mcasp_aclkr = mcasp_aclkx;4 a4 p/ ^9 h+ H+ c; m4 X T
assign mcasp_ahclkr = mcasp_ahclkx;. E; V) S3 K& C* q
assign axr1 = axr0; 9 I1 c9 j- L* K
2 R8 R5 |, Q/ {* q( J S3 v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& o/ K7 R: {( S) w2 P6 `static void McASPI2SConfigure(void)$ T k; _) U: u j1 H6 B
{
/ P6 P" h1 O* uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" A- j; z+ ], Q6 Z+ d7 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 n0 X0 a9 N- y) R9 K% p' i4 `0 pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! {* ~( v. S- e ]( H2 w$ N/ iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 ^1 x) |( d k! ^# x8 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ D9 J9 ^) E8 r% jMCASP_RX_MODE_DMA);7 [) q# ]7 `6 E/ v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' l3 F, h; n' m8 n3 R& R) O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ S& i. a2 M9 L" e: @+ _: I6 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" ^' x- h8 ]9 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, X1 u1 f+ }- e$ U. I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" f2 n/ `0 S7 s: G, w( yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- Z1 \( ?; Y( J6 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 @) r; c0 f6 `( l& C0 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 |0 G" A: C* {0 IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 Q1 ~2 {2 S5 k, L0x00, 0xFF); /* configure the clock for transmitter */& P8 S1 X+ \: E7 K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 L7 H. _' r" d& w# a% d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 D; D. F" t3 L3 I! @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 Q" k. x& ~* c2 }* C; Y" S
0x00, 0xFF);
- |* d$ r& @, t
' p" I" L) C6 o3 n7 P/* Enable synchronization of RX and TX sections */ " W) M: ?1 j6 p# _- h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 ?0 d- V& R! {9 f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ]* b; q6 B8 k) g4 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' ^/ R! l1 C! R1 [$ ]0 D. `$ d** Set the serializers, Currently only one serializer is set as
) F' L) H! u! ]1 y3 ~1 Q** transmitter and one serializer as receiver.% X7 o; L0 m/ D- U1 w! T6 |
*/" Z7 u6 B; s$ ~2 G, L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
M1 E6 z: @/ M$ U" h' i5 c( OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; I% k6 n3 F- L
** Configure the McASP pins / T* _0 A9 F8 |$ H: F3 J% S: s4 E
** Input - Frame Sync, Clock and Serializer Rx# _/ ?; Q, w- j
** Output - Serializer Tx is connected to the input of the codec % W; Y8 o9 c. f0 M( e. j1 y. @9 x
*/" H8 m; |/ H- u K9 |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# r% w6 b$ R7 L! _1 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 u8 v( B2 i+ F$ n; @1 P6 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) Z8 S3 n9 C4 U/ c+ e1 a7 i
| MCASP_PIN_ACLKX
- S4 S5 W: ~5 s8 y1 ]4 t| MCASP_PIN_AHCLKX
9 P* R8 M! M4 h- o2 V! _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- Z$ {6 r5 h$ ~9 ?5 O* ^' iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 K) U- a: Y8 y2 `" Q; M| MCASP_TX_CLKFAIL & j0 R& q9 |/ Q- p; y y8 G
| MCASP_TX_SYNCERROR
$ A) v- c! v1 _* s3 T- N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ S' J! A p# G) i: E% N- A| MCASP_RX_CLKFAIL
. k. T/ c6 I, g8 d9 z| MCASP_RX_SYNCERROR 7 |+ v' u, b4 B- |# M, }
| MCASP_RX_OVERRUN);
$ X5 H# p+ {! I, R) w" r8 A} static void I2SDataTxRxActivate(void), t: j& ?( x I# \8 I' N
{
0 g, Y4 K5 k: |* h: M* _/* Start the clocks */ F2 S( ?9 T) s. F; l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! l4 j' p0 o2 _& G ]. |2 |+ f0 u/ Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 D) N0 X6 [0 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% z& R( ~, W- z+ h) ?
EDMA3_TRIG_MODE_EVENT);
' |* G8 j4 e5 I: ]7 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + ?6 V7 F5 | v' [% T- z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 I% F" K( z. gMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ f. K# M& c, q" b7 @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 F" o( U. w" H$ z: r7 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ U& `& {! s! F; Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 B+ z6 _# W3 b6 s- J5 ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( Z( S c5 i/ C' g, }7 m
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