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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 }) v! j4 C7 K& ~, z& B3 k4 M
input mcasp_ahclkx, T i3 g4 Q8 p
input mcasp_aclkx,
4 q4 _6 ]3 R2 g: einput axr0,
$ j) {3 I0 r8 e- h8 F3 J
! m! O6 {8 i2 {! A A- Aoutput mcasp_afsr,
4 o# ^ G! f$ P+ woutput mcasp_ahclkr,6 s6 ?3 g1 Z2 u) e% n
output mcasp_aclkr,
- q1 N4 Z' O& a. Foutput axr1,
" l) d3 k- F6 `8 n assign mcasp_afsr = mcasp_afsx;# |' N# ^# U6 P3 O% o
assign mcasp_aclkr = mcasp_aclkx;* U4 Z: B) u' s" P+ s
assign mcasp_ahclkr = mcasp_ahclkx;
' O* y6 U N& n5 r5 Rassign axr1 = axr0;
8 O# Y) a; _: L a& y# n% x+ D- g+ I/ C1 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 L/ m' a/ g/ V3 d8 k$ W3 O
static void McASPI2SConfigure(void)
4 y8 t2 Q, A, `: f. R+ o2 M{
$ L/ J+ o( u8 F4 hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
& n* H5 M: I6 v4 H" bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) e9 |% ^; U9 w, j: [. u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( S. H, |& g3 E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 S8 c- E3 H, p# c, C' H# E* h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* i+ p$ h9 V# \; f
MCASP_RX_MODE_DMA);8 T, F. p5 |9 w! K0 W
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; s( t0 P4 s/ [) w! e+ l/ u" K4 ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( X8 O) D9 l: ?4 C6 O# h5 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 N1 @# Y. s8 I3 B( ~5 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
i1 X: [( {- f& J6 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! R" L# `! ]) tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# k, l: P. R5 i3 m- V. h" J; `0 n1 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; T, y* M7 y+ f, m7 F( f; Y4 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ R! J4 I1 j2 e6 m/ C* S, c, }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 Z) q1 v& E& x& ]0x00, 0xFF); /* configure the clock for transmitter */
/ Q# b+ F% t' c8 ^ wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" |/ O. L$ _8 O) a) m" ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ `0 @6 v8 f$ x' B8 g: \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 Z% ]( `) O' ]; O- m$ h8 \0x00, 0xFF);. a8 |* [5 z) p) o7 C
) a: z6 M, j& E: ]
/* Enable synchronization of RX and TX sections */
" D' P: F# U. @5 B; IMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: Y2 Q$ G% n/ `3 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( @8 A- I# ]3 h+ e8 PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, U" X7 c, [6 h1 H! s: }- P
** Set the serializers, Currently only one serializer is set as
7 F" \) ^+ l& ^/ d** transmitter and one serializer as receiver.. T, g: h5 ^1 W. k8 B5 K& ^
*/8 y" p! N9 G) }: R& i8 O$ K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); t, G- T! D% |9 ?# d: C- c- e* ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. C0 \( B) u8 {! G9 J, K** Configure the McASP pins
" F! l1 d" @: L0 n( O** Input - Frame Sync, Clock and Serializer Rx
6 @- [/ S% `5 @+ @** Output - Serializer Tx is connected to the input of the codec
, a4 ]. N; c# P& N2 x+ _*/
: R& a; X' }/ o) X% AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% z$ n$ b% d0 m* T0 T/ C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ t# v$ d/ r8 J) FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- b. Z- |0 X$ T2 T/ q| MCASP_PIN_ACLKX
2 X$ d! z+ j9 p+ J1 B: A% Z| MCASP_PIN_AHCLKX H, `# U0 Y2 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ f5 X( H1 A2 z( [9 rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% A3 g3 F; L6 }0 G& ]) O| MCASP_TX_CLKFAIL
2 Q. c& h6 }( B| MCASP_TX_SYNCERROR, D% o1 m6 ^9 p0 j% [/ `: ^- i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 e) ~' k( }& W& P `9 P| MCASP_RX_CLKFAIL4 y2 d& ]7 f3 Z1 A$ a
| MCASP_RX_SYNCERROR
; @+ ^ B: _7 q* A* S9 `9 I| MCASP_RX_OVERRUN);
o; C* U! I" D9 B4 X8 ]} static void I2SDataTxRxActivate(void)
* g* T! k; c: p( @/ u& E{% f. Q: b2 k c+ |# F, p
/* Start the clocks */ @$ Q9 |3 B" y( T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" M0 z: I+ }! h& e; ~5 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: P/ n1 a+ m& K' Q' DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 {9 ?* k+ |; y9 j: O
EDMA3_TRIG_MODE_EVENT);0 {& P) ?' d, _. ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! l8 X: s1 M4 }7 B) P: q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( b9 F+ \% E5 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 T# n( L1 w" c/ G2 c- b* [9 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 ^& b4 S+ l0 ^" Q( N) y0 Q5 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" ~$ M' g: l9 F6 @- I; L$ U& ?, W/ @7 I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 r" O+ \# P% K r' r3 o. }# NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- k9 e' y3 N- w9 p$ I/ [} T3 d2 G# W) m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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