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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% j' U r& z! V5 [6 {9 ?input mcasp_ahclkx,
) M( F! ?8 k) m4 N6 s' Uinput mcasp_aclkx,
3 C1 N: P; J% R4 T8 Xinput axr0,
% X2 Q3 @7 n3 ?
0 I' E3 O" D: @# V E. Foutput mcasp_afsr,3 T; G# v, J% T5 T" g- \! T
output mcasp_ahclkr,
) u+ v4 Y0 b4 Ioutput mcasp_aclkr,
, v4 Z6 X+ J# i* R1 w8 h$ \3 q( Soutput axr1,
: F. X9 `2 X- J' I. C2 C- P assign mcasp_afsr = mcasp_afsx;- h' G9 b: k- N! C, Z4 W% S9 X
assign mcasp_aclkr = mcasp_aclkx;
, Z+ ]2 M. v9 A# J) Q) g% Eassign mcasp_ahclkr = mcasp_ahclkx;0 s: [: |) i3 T
assign axr1 = axr0;
- }3 q! D- Y# f% n+ u
9 D: I- D* F u0 H) d+ z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 z( ~: ~$ }$ @6 Y6 c4 A# o/ c8 q
static void McASPI2SConfigure(void)
3 ~4 o% \3 |/ w; o% k7 O' R{
/ d9 l- |$ W& iMcASPRxReset(SOC_MCASP_0_CTRL_REGS); n! y5 r7 z4 D0 a/ h; p; t) R! T( T
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% }: v3 @0 |0 ?+ ]( K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ Z' O3 _5 R8 W0 S/ [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ e3 \: @) {8 Q# r% \" z$ W( G1 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! J; `9 `; L5 [; u s% n, @MCASP_RX_MODE_DMA);
+ q$ d( I: ]! y1 E3 Z x6 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ J: Z3 H& P& U4 s8 c% P; l4 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. d0 V4 z; ^0 x- XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 A9 U2 ?& d- f: w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 i; f4 i! B4 B8 J8 q( O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # A* @) y4 b- p2 O, f8 P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# j8 @" H$ r, w: f6 a* ]+ M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) f$ F. P2 g7 B$ ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 H* G1 L) l; q2 [9 C9 S; b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 X4 W% j, x# p8 Y. y; \
0x00, 0xFF); /* configure the clock for transmitter */) w- N% c7 \3 j |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: p! k) Q5 V( r( Z1 p: q& i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - A# N, M+ H* E8 n
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 _$ B! f" b* {9 O$ x9 X
0x00, 0xFF);3 f8 I6 f, [4 ^
6 K& ~% v, z- l- U& b
/* Enable synchronization of RX and TX sections */
! N( e' o% `$ w; C7 }4 a8 ?8 OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ i8 x* Z4 w8 P$ v% I2 Y6 @4 J. \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& a/ X. D7 g% L4 R. i, S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. O3 F9 s! `( w7 e** Set the serializers, Currently only one serializer is set as) P! m2 R7 _+ a( a- m6 O
** transmitter and one serializer as receiver.
( x, x4 J$ k4 w- c0 c+ O- ~*/4 ^& ~: h. H p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 v- Y! k( r7 C5 ?; L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 R) b. ?9 Q8 A7 h' o
** Configure the McASP pins
" K* j h. @) i; d5 G$ l** Input - Frame Sync, Clock and Serializer Rx$ f6 g4 O& z5 r4 r- I7 x5 }0 V
** Output - Serializer Tx is connected to the input of the codec * x/ T: m$ A+ s8 n3 m
*/
+ L1 ]8 m' t1 }& i1 k5 g, n$ U5 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- W7 [1 R: I3 K; F0 @6 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# g0 _) h5 t, `& zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& f3 l4 I) \1 O" `! Z7 r/ i# z
| MCASP_PIN_ACLKX
: ^' f6 ]8 |1 ?9 ]: ?5 z5 j; V| MCASP_PIN_AHCLKX
0 n( ~( b- A# k5 r& s3 H. U| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 g" O+ m. v" Z* |4 q1 I5 I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 ^+ b) Z) [3 G+ h5 o| MCASP_TX_CLKFAIL
7 M: Q: t6 F" C% k| MCASP_TX_SYNCERROR
" E. r' N9 C+ b7 ^5 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % v0 D* i6 U9 {& {+ W3 W: x
| MCASP_RX_CLKFAIL0 [- b% s8 B0 y- }( ~! [0 ~
| MCASP_RX_SYNCERROR
9 t. F8 ^, g f- @7 q| MCASP_RX_OVERRUN);
9 w# Q, \7 [3 _) f} static void I2SDataTxRxActivate(void)
% `+ @! J8 a7 H9 Q{
, T% L3 y7 N1 y4 h0 S/* Start the clocks */; o: a3 Z! K: S+ h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 E4 p% H* O! r! |6 c& y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 b: M0 ~8 ?* C, O2 _2 q! M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ R( I4 y# C8 K! J2 a' ]. o5 vEDMA3_TRIG_MODE_EVENT);
9 _* V5 l# W9 |6 b6 y2 F( s% T+ o- kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) L8 P: ^, L z. ? OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 `; c; T2 k8 e/ ?( K: R @* pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! e# i+ |* E; L1 |8 M4 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 `$ g9 m# d2 O3 t ]. s6 T! o% Z0 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, m2 f) n9 W3 r# h# g; ^9 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 e, e g# {& |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; T" }4 }, J# k+ C} / {8 s* b: [0 i( |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 ]" t, U5 x2 \! B" A2 W+ p |