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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 I" T( S/ ~8 C0 r" }% U5 h; Iinput mcasp_ahclkx,- G& i8 o# c4 M
input mcasp_aclkx,
% w7 O! s6 o2 ~input axr0,
: e$ |$ O3 y8 @& Y7 M" y& Z* G# b" \8 W9 |) v
output mcasp_afsr,1 p5 b7 {2 h1 [0 d. N5 J
output mcasp_ahclkr,0 v e0 {2 ]7 k/ `: _ J" M6 B
output mcasp_aclkr,
* k. E5 ^/ j% e# c1 U& @3 d% Zoutput axr1,
4 C3 M- X% U0 o& k, Y. F3 S assign mcasp_afsr = mcasp_afsx;1 d6 c: ~+ ~7 T' r( @: N7 H( p/ |
assign mcasp_aclkr = mcasp_aclkx;
2 ?6 m" |5 z a* h7 |! z) x( Passign mcasp_ahclkr = mcasp_ahclkx;
5 A7 p8 p# W/ t/ \6 aassign axr1 = axr0; 8 G6 k+ r. u. t8 j
3 o6 ], r: z$ Z% w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 w/ K! n3 T4 q; Ustatic void McASPI2SConfigure(void)' b3 j+ u7 e3 V1 u$ {
{
! C% l8 x6 k+ ?, E0 c# M/ c- NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. n5 u! z) `+ ^" X8 W5 {( ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% T- u' j) j, A# [$ Y% ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, x/ p2 f$ @8 J& H9 c* t0 l& Q1 v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( B9 t2 D0 E5 p& z# a' `$ O# S! AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) u; R* \+ @" ]- L0 ^0 T
MCASP_RX_MODE_DMA);
8 W/ E3 u! f0 `. g2 a1 yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! Y4 [/ @4 j& Q* JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ l* C! s* H y9 x! L
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
z; g3 i1 l) Z: b: J7 z1 LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 v1 h+ U r# P& J, g: ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 w1 B% N( F, E/ k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& g9 H6 o0 u$ u7 U) \' j; i9 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 Q: D4 b3 Y- H- ^' x# ]" QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 g) ]# B8 Z7 |* p" M! J3 P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ V- \# W8 [' |: O9 G0x00, 0xFF); /* configure the clock for transmitter */
; ~: L1 o0 g, U- T) K; G5 Q3 cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 H8 e/ z% I# r, f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; h* D. ~0 [' S2 z; qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" u' n! e+ W7 N4 W) R2 B* R8 d0x00, 0xFF);9 B* M% m% y, N* Q! I+ P- T& W
. p# J) L- f" T' v/* Enable synchronization of RX and TX sections */
+ F K/ {: Q" p s( i3 `) VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( I: a9 w* r- W& tMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; Y! O0 P- k n# H" b" J$ jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ e4 F, ]2 R, T3 S5 W7 }! Y$ _! A** Set the serializers, Currently only one serializer is set as
$ H/ h+ u' P% Z" {) n5 {) U* m! a** transmitter and one serializer as receiver.2 \. Z. T* E; s
*/
. X5 W: g# v: _" t+ I- q/ [- d! tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& c" @1 g5 b8 l7 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% P9 k% E. Z) `0 m
** Configure the McASP pins ) x" q {/ Q: u1 \* C# z
** Input - Frame Sync, Clock and Serializer Rx
: z Y1 f: B; I) _** Output - Serializer Tx is connected to the input of the codec
- t9 z; d+ ~% y*/
8 R9 T+ L8 l8 U7 C0 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ c/ @, _* d! G2 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 t; O2 ^8 _- G
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 m; G, Z0 b: w0 ~% Z4 c, U' q
| MCASP_PIN_ACLKX
" r. v, G4 o+ k; @- m# i* W$ n! j& O| MCASP_PIN_AHCLKX1 Y- g0 C7 m4 I! u, B5 f- S% @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% S6 P4 t; t. nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 S2 l5 _2 _* U7 y( E
| MCASP_TX_CLKFAIL
" r3 Z4 i8 c0 Q. m9 f| MCASP_TX_SYNCERROR
# z; \& M4 s7 G( s1 I; {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 ?' I5 G- y {( G Y| MCASP_RX_CLKFAIL' H/ H( r5 `* b0 _
| MCASP_RX_SYNCERROR
$ g( `! S I" Q/ J| MCASP_RX_OVERRUN);
2 u, Q' W% s0 |: q% E7 I( p} static void I2SDataTxRxActivate(void)
! x& J) L, Z. n' k9 t{
% s! h$ {: v' N/* Start the clocks */4 f6 R1 A) Q# P5 Q0 `/ N% [+ h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* D* G( d# ~' T3 y- pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. J/ ^7 q7 k3 H# d9 ]' T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ \6 o( ]: x) k( H% n$ a! b
EDMA3_TRIG_MODE_EVENT);" M' v9 M% T. Q9 Y0 E, U0 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 ~' T8 j' ?. j3 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ I J! s8 ~+ ?2 w7 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" F! y: C3 Y+ O: P6 F. PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 c$ H7 K8 ]/ }3 n0 Q5 e4 ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. w1 G `" N7 S7 u" wMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- n p; }! a/ U7 i7 k1 ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 r* V5 [# w4 \/ F
}
$ Y+ Y' e! P. v' q. p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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