|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 C6 \) E. Q# i% C$ A9 l
input mcasp_ahclkx,
& a, c8 y* D) ^9 Yinput mcasp_aclkx,
4 M4 B1 w3 j' Yinput axr0,
0 h* s' N# q( k5 T- n d5 F8 T) Z' k
output mcasp_afsr,
, N6 w& }7 \7 x9 |3 R/ doutput mcasp_ahclkr,3 q7 t1 \7 y# v! H# Y- A
output mcasp_aclkr,; T. I( g3 e5 N! F3 @3 X4 i
output axr1,2 h) o2 v7 [! n& u1 C$ R
assign mcasp_afsr = mcasp_afsx; k5 j3 W, K' z( k; c* H
assign mcasp_aclkr = mcasp_aclkx;9 Q8 c& Z/ |* |: X
assign mcasp_ahclkr = mcasp_ahclkx;
% m( \* L5 c0 W) T4 J1 M) Oassign axr1 = axr0; 0 z& W( P1 c3 g: }; l0 [$ V0 k
. k% l* s1 S2 _3 Q' v# C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# m& y# h5 A3 @2 Istatic void McASPI2SConfigure(void)
% k6 ^3 t+ ^( v' w9 J: ~2 p6 c{
" L/ } m3 p5 H; r0 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);. T6 r8 e% W( J$ z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 |: @9 x5 b, u- E" vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# x& j3 N8 l& I* x* v, @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! w" d$ Q. P. w' y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 ]& v! v: [. tMCASP_RX_MODE_DMA);
% m% N% c! x) y' }5 N5 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 j4 R! @3 R; mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, A5 P) l; Z7 ~4 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! a' c- _/ Q1 G y; k$ v9 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) y$ P* ^7 U, K) R4 WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " o! ^0 g0 X+ K8 }% v+ k4 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 [8 i* R5 ?* F( tMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 d2 [. }, ~: j3 n" p7 K; R* D/ bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: o% L( t' f4 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( d( N7 A8 D1 S& m, L9 m0x00, 0xFF); /* configure the clock for transmitter */" `7 w% ?# X1 @3 |3 g6 w; x X/ y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( u/ m1 v9 A6 L5 \, q$ v" |! b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. a) r- x6 m2 H u1 k1 K+ ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 C( y8 \: \5 D
0x00, 0xFF);
- C) z& p* Q! l9 O5 o1 M
; G& _: m; E6 A/* Enable synchronization of RX and TX sections */ 1 b3 q; o4 [* @/ h. W, J$ s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 z' z$ M6 A- a* E$ n( {3 o: H2 \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% l6 R# P6 ^$ c1 bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 z% E7 q+ x( y$ i$ Y* a** Set the serializers, Currently only one serializer is set as) C- _0 D2 L3 W- I) m |
** transmitter and one serializer as receiver.
0 C; J4 Z* h T*/, z: X+ H) Z% L- }; ]! j K( `. ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 ^5 u5 G K; i; h3 T, L3 P" oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 B9 T: S& p, O n
** Configure the McASP pins
2 h) S4 h0 ~6 Z8 _* |# R* I7 X+ u** Input - Frame Sync, Clock and Serializer Rx
5 O6 L& k' |' \5 [** Output - Serializer Tx is connected to the input of the codec
0 y' r8 e( M5 g4 G% }*/% Y9 V: {, G2 _ k' Y% F8 E. U2 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 t, Z6 l' }$ ?7 M8 YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 p4 r7 x$ ?. ^( ], f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 |5 P* b, z5 U4 [ h+ k2 t5 r' {| MCASP_PIN_ACLKX
' A* \) O9 {9 c& S( k+ }. V| MCASP_PIN_AHCLKX- G7 @# ]( I7 o& q0 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 A" P/ X3 G+ _% j9 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; g( d/ Q5 ?7 [1 N1 y; A* K% n| MCASP_TX_CLKFAIL 8 u: H& z! i3 ^; I {* n7 P q
| MCASP_TX_SYNCERROR, J# R% A' w9 L" ^& |. H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) Q; T7 m2 {! s a9 X| MCASP_RX_CLKFAIL
7 e) H8 J" U- Y1 T9 D8 S5 I| MCASP_RX_SYNCERROR - _- b! K1 c+ g: q! U# T
| MCASP_RX_OVERRUN);; f T0 q* r3 F; |
} static void I2SDataTxRxActivate(void)
. M; [9 T+ R4 d* Z* O1 J2 T{
/ L; q/ p8 G, X u( D/ F6 h7 w/* Start the clocks */5 U2 c. I) \ W9 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ D* z1 }% r7 s6 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 \# s! k, r; _- J% H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ B! Q: m3 Y- K# {$ V3 m, P
EDMA3_TRIG_MODE_EVENT);
' p q8 v% D( x7 h* pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. e2 N& n. K2 Z7 y+ p9 e* }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 j" ]# W% E4 d% ^0 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& m# q) o2 E) BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: ^$ W2 ]; K7 b F' `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 y( G8 q$ Q3 S0 f) x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& }0 X# J7 s* ~6 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 [; V9 E2 `& L} ^- u$ ?- Z- ~* N2 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
s+ ` A% ^4 G |