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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 J) q* G( \' o/ V U# Q8 cinput mcasp_ahclkx,% D4 D! p* v& M3 e+ |/ c
input mcasp_aclkx,
$ z" i4 J H8 g- o- _input axr0,. x7 S+ S/ q- q$ u+ F5 W
. d0 Y Q9 q6 ^# j
output mcasp_afsr,
* d; V: @+ Z+ n( r1 p) b5 Poutput mcasp_ahclkr,. V9 B- a! ^' I3 O, i: C! ^
output mcasp_aclkr,/ t1 p0 l7 {/ |% i- r
output axr1,
: {) h+ ]/ k; H" Y assign mcasp_afsr = mcasp_afsx;
% V [* U. u0 q' eassign mcasp_aclkr = mcasp_aclkx;
2 `4 G- P3 w: Kassign mcasp_ahclkr = mcasp_ahclkx;( [$ g0 _3 M9 s. R# l
assign axr1 = axr0;
) f( ?( y! R5 q! D. |8 O/ Z, F* I8 }1 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- \& J2 G2 o( M3 Astatic void McASPI2SConfigure(void)6 ~2 _4 o1 R" U
{
8 e! d* w h; V3 R p0 c* uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" R x. ?. R0 b* p/ \# W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 X4 J- d( B9 q5 k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' t) g9 x9 L, K9 }! }& l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 u, b1 N! e T7 g* ?7 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& }4 B9 B! T+ |- P% j9 `MCASP_RX_MODE_DMA);
& }( b/ V/ s# A _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- A/ S) `6 E0 i
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) Z' [7 r2 ^/ F1 E: v/ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 `# h& _% E- k7 nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 l3 T$ `* _$ ^. @5 }" N% tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' ^$ \" K) B2 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 [, R- _( p: }; F* ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- Q" x7 ] M' ]! ]7 A+ | lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' j7 G/ U: H2 D4 E+ @7 LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: w b9 k+ e, D4 O, F
0x00, 0xFF); /* configure the clock for transmitter */7 g `9 c$ s( g4 I7 Y# Z# ?3 G* \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 @5 e* Y; d( V% n' u( K6 w0 z `! w" r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 Q! n7 Z/ ^& S& _3 P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) y' J% a2 o" Q' X) a3 o: V$ {
0x00, 0xFF);# I k3 u, j, i. u
9 @$ {# g& T1 D, O4 h/* Enable synchronization of RX and TX sections */
% S) ~" Y! o, ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: B" n$ s' V; Q0 S I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 B9 @& E9 q a( z+ xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 ^/ B- X9 m; W6 z* ^$ r** Set the serializers, Currently only one serializer is set as1 }5 k' X3 b: z l* U. X& Y% e2 n2 g
** transmitter and one serializer as receiver.+ l& R# R# |) p9 `
*/: Q, N& Y% s3 o( O ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# p' B! a# Y& }4 V) WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" p% I) C. C+ v: c; @* M
** Configure the McASP pins 0 M' H3 U* L0 j4 g. t$ D% k
** Input - Frame Sync, Clock and Serializer Rx
' A m$ F* G* E** Output - Serializer Tx is connected to the input of the codec ' ^& ?8 m6 G2 H/ F. {
*/7 C$ J# j) U2 V7 _0 M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. D1 O9 ?. Z8 M
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* `3 N& T1 [* U2 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, m$ X) i k. ^4 v( M; u1 A$ K| MCASP_PIN_ACLKX
8 G$ G2 g* ]" `6 ?" z3 H& F| MCASP_PIN_AHCLKX
! K; @ n5 G+ z/ A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, P4 c! U' K T. X9 Z9 o2 q. Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 Q% C( ]; l6 {$ K0 F4 a| MCASP_TX_CLKFAIL
/ d. D. }" ]) y4 C) [9 ^' M( a0 ^| MCASP_TX_SYNCERROR7 f7 }. |' ~( [4 B h1 C$ e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 K# N. ~* K( i
| MCASP_RX_CLKFAIL
- s/ w, N! S+ C4 z, l| MCASP_RX_SYNCERROR
0 w8 x& E" T5 N7 G| MCASP_RX_OVERRUN);
- P* H$ v/ ]/ \( q- U} static void I2SDataTxRxActivate(void)* g; J. u) {3 O+ s3 f! S
{
' T; Z( y2 y5 t/* Start the clocks */2 y* a% \, b) O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. x6 D+ Y' Q5 ^. y& Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ c h6 `" I C. t! \; QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- z; e" \) m% p( X" ?EDMA3_TRIG_MODE_EVENT);
# f1 S; {* n, M pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 f4 d* N7 d( F$ f; q, l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% {) @% m- j9 k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); d. }( V7 l3 E! o u/ h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// {( a# r* |' ^7 @1 V# L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# v& G1 C: o G1 Y* ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& y6 S ~% Y* f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. x" Q9 y' z) q; S* i2 |& l} # |1 ~6 R4 g, a# v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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