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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 s- p' G9 g k0 e$ K q/ Cinput mcasp_ahclkx,# x4 ]: Z* ?& F
input mcasp_aclkx,2 a( h! z+ z& y, Y% l
input axr0,
/ `, {( n2 G& J# m, A
& O1 r( R) U& I( Uoutput mcasp_afsr,6 ]& j+ x7 O9 e( ~; p0 Y; h9 o
output mcasp_ahclkr,
/ t5 H+ a. M9 Y, F1 T$ y) V Joutput mcasp_aclkr,$ m+ B- R" e, {# c( ~/ ?' w3 m
output axr1,
$ y8 G! T- l. F6 y" I) |0 } assign mcasp_afsr = mcasp_afsx;0 D9 h: ~: k8 X& a. t* b
assign mcasp_aclkr = mcasp_aclkx;
' G( Z" K/ }' O) [# V! M6 p j1 Yassign mcasp_ahclkr = mcasp_ahclkx;
9 F& A' j5 W: ]* ?2 u8 A2 tassign axr1 = axr0; - s- _: n: G; n, r. G- c
. n! k! |- z1 Z8 ]. G0 t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ p; k. j$ `/ Q( qstatic void McASPI2SConfigure(void)
, S9 j% z7 V5 ?$ n{) @# a- n3 L5 P( L% P3 D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* `0 P0 L/ p! I6 D9 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 C, m" }7 a% r% j1 B1 a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& \' M# S! K9 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! p" c5 N& D) o4 v1 ?1 |4 zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; U* W# |/ u" b; S8 S
MCASP_RX_MODE_DMA);
2 w0 F d0 P( y8 M7 m8 \+ lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ J# u/ F* [1 n# Z! RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! X$ e+ B* O) E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* Q7 u1 V5 C% E- O) t& m+ XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 Q' q7 G1 ]( Q% R1 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: B! x$ o! Q5 r7 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 {7 f$ W" t/ ^7 K1 H% g7 P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ T. r, A2 k X! ]8 \# l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; `* S3 h F0 {+ c) MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 k9 T! z. X# ]- D1 k& R0 M0x00, 0xFF); /* configure the clock for transmitter */
1 N& V; O9 i' w! RMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( s+ y+ I; j+ q1 F$ d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: I' \" _& h! ^+ d: ^+ O* Z$ FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 p+ d" @" o0 |: n
0x00, 0xFF);
, B( m. A }! K1 T6 \, z# x# {8 k. `0 M. z4 W
/* Enable synchronization of RX and TX sections */ / m+ Z0 y; I: f+ k$ N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! w3 h0 s+ g, F1 K& d2 |" X1 v! xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 g% H' g3 g* J6 q1 \2 R& D$ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 y0 |/ F1 Z7 L) T** Set the serializers, Currently only one serializer is set as
$ l2 m% h7 Z! c' X+ O( {" m** transmitter and one serializer as receiver." _+ f. `+ x) f# @3 B: Y
*/, L5 U9 A8 {: _; p2 t/ [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ L, F# F! i; EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' H J5 k; I/ H* i** Configure the McASP pins
4 ~* n3 c+ \2 J3 F/ g8 U** Input - Frame Sync, Clock and Serializer Rx+ r g# w0 v3 ^! C9 e, Z4 e' i
** Output - Serializer Tx is connected to the input of the codec ) Q0 L4 Z4 T+ }3 K
*/2 e+ O4 g4 J' r" z# n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 }6 W% D+ E1 t* n' n+ g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 w$ X/ K' n& y$ B" S5 H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' s1 c# a8 j2 |8 I| MCASP_PIN_ACLKX3 |) }+ s+ Z! e+ X
| MCASP_PIN_AHCLKX
( D5 Y% S& V$ v' A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 ^) I* M: m+ a; P$ m6 n$ [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" c& {3 @# a Q/ C| MCASP_TX_CLKFAIL ( f% y9 R. \& \4 W7 [- f( w
| MCASP_TX_SYNCERROR
, N) ]: g5 N' n6 l; a1 J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 {- v) F* T$ a' {7 K
| MCASP_RX_CLKFAIL
X9 Q/ B% A1 a7 G8 | k| MCASP_RX_SYNCERROR
/ x: j2 F9 q4 F7 a4 c| MCASP_RX_OVERRUN);
8 x0 y. o' n4 n" q3 X8 `8 U& _# G" t} static void I2SDataTxRxActivate(void)
# p/ |- i7 Z' Q7 g# t{9 k* v+ L% D: V
/* Start the clocks */" [1 l% }7 ?, O4 Y% }9 R! ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 {' [8 k( D( O5 V3 ?# K0 [; |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' f# e' T/ C* F2 |" qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ L& c c# a8 w! a( f* y
EDMA3_TRIG_MODE_EVENT);
$ Q+ H. }8 z! A# h p0 Z; OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 r! x/ z/ |3 \$ [8 i/ REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; A! n3 w' N: g+ j( |- C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( d) r2 Y _) q: s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: e& H3 J2 q- E, @) F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 O1 i9 {+ _8 G" _ z0 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 U: Z* C5 I- i$ R2 w: mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 e! X! [. J5 ?2 {- \/ o$ @
} 2 v0 D! g, x: M! K7 `% i
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' h5 u5 m: [( O2 j: R" l
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