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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( w0 j0 K8 ^5 r* ?( E+ Uinput mcasp_ahclkx,
! t" e- J) O3 A R `% M# P, uinput mcasp_aclkx,
5 P/ m1 I6 O9 Q P/ cinput axr0,
2 U% Q' d6 }" M- \, x9 d* M- M3 k
5 ?, B2 Y D/ Aoutput mcasp_afsr,
$ V2 u' Y# |0 Z/ q7 k6 z. Foutput mcasp_ahclkr,
2 c7 ` j. h1 K8 |, eoutput mcasp_aclkr,
+ c! F. W' j' C: t) poutput axr1,
' @# @$ V6 s- s/ u+ L0 n- H assign mcasp_afsr = mcasp_afsx;7 V- O8 T# B9 S* g* o: d
assign mcasp_aclkr = mcasp_aclkx;
5 J y @3 C# r7 o& n) i' bassign mcasp_ahclkr = mcasp_ahclkx;
( H4 y7 W* y, U! bassign axr1 = axr0; % j; c! c% S2 M' c( j
. P1 B2 O* L. l; h2 F; a1 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ R u& @- q: @% X Gstatic void McASPI2SConfigure(void)
# I0 s" T. D- _" U2 \{5 l/ @& ~2 ^$ S' z1 f2 i5 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 m+ B) ]+ p, d% P0 x2 l( g* X7 T W) P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% k9 B Q: n" M' t& {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 |6 K9 j4 g/ g: `$ Y2 `; ^- m+ Y/ DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% V, ^' P+ f, v N" R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% `+ ~, y- H: mMCASP_RX_MODE_DMA);
; S. b& B& j9 v) J8 |! `+ NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" u5 y9 k4 F7 d/ d+ o1 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ w# |& J4 p+ L0 S6 \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 T+ Q2 y* X% D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 [3 x: B8 z6 p7 N5 [) P+ oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 [8 i& S9 H U0 J" L' @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 {; S$ R% y6 U- hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. I% `% y4 P* G) N5 i. p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; J+ j+ Y& I9 Y& G, I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 {+ y4 n. Q' n* c" Q# [, b0 Z0x00, 0xFF); /* configure the clock for transmitter */3 t5 D; Q% j9 Q" A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. Z1 _) P5 Y5 i( C1 m% j4 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! t, a! G6 G* C, [2 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 ? X( U& ]! K! F: a$ I0x00, 0xFF);
6 ]- Y( x1 ^6 l
# J; G+ Y5 B3 z/* Enable synchronization of RX and TX sections */ # C3 q3 p9 K& r" _" I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" E5 I% j6 ~/ m/ s8 u% A$ Y" UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* [) G% D! f% F" I) C0 P$ S
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 D/ f3 v8 [- B** Set the serializers, Currently only one serializer is set as
+ O, [; p3 j7 l1 z( p2 m$ T** transmitter and one serializer as receiver.
- a7 A9 m( o8 ^: I+ A& M; e*/
3 k3 B7 Z7 [2 X7 \/ L; m6 {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 {" u' L1 H/ G0 f# G K, P/ xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- v h7 f' u, v8 p; b. A/ [1 V
** Configure the McASP pins 9 O7 g' K" f' ?9 e
** Input - Frame Sync, Clock and Serializer Rx
+ g' L* z, U A0 z** Output - Serializer Tx is connected to the input of the codec
- \0 b7 k7 Q- r n*/ G" S4 j r0 G o% J. |! h0 f8 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' Y* C W/ N" y! e, N) h( gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, }' c7 I: q2 d* }3 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! I2 i' I' N, A* z
| MCASP_PIN_ACLKX8 j Y. ?; Q" K( P: L
| MCASP_PIN_AHCLKX
& }5 M+ y$ S$ N1 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 K; @" E' D# ^# w7 d$ ]2 W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" L+ e$ ~3 W/ Y# j/ F| MCASP_TX_CLKFAIL 4 \3 E: d' H0 H k( Y7 a h+ u
| MCASP_TX_SYNCERROR* D& {4 F6 q0 p* E3 C( _, U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! C: K8 u. ?0 Q- f, y
| MCASP_RX_CLKFAIL: P) C9 K$ ^ h6 _/ D: i0 ?% N
| MCASP_RX_SYNCERROR
9 R- ]* F! `0 U) Y# }! }5 D1 U| MCASP_RX_OVERRUN);# b6 W4 M' q$ ]; q7 `- ]
} static void I2SDataTxRxActivate(void)# K2 O6 r% r+ k# o; ?
{/ s% [+ B/ S" v9 n; J3 \% j
/* Start the clocks */
( F- y) H$ w& Q$ x1 q3 L+ xMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 r& @' f- x! k2 p& O( V/ F- ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. @8 `2 |+ A! j. fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ E( t6 w5 G x4 ]: [
EDMA3_TRIG_MODE_EVENT);8 G+ k/ y$ S9 l- D( v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
v$ b5 Q, g8 s7 a5 |- R5 sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 }1 }% N8 O9 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: [" k6 Q' {0 c, a2 X5 y, mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! V' _/ x# n8 \6 M: b0 fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 B6 G3 q! ?! R/ o- E6 N
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 S1 `! s& |0 f# ]/ M1 o4 H& NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. Z% ^% V. _3 v. f' `0 r
}
" U9 M9 B& l( I/ P0 Q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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