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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( [, d# b. ?$ p' E5 q& ~2 A
input mcasp_ahclkx,! ^4 W. ]* F) {
input mcasp_aclkx,
) w1 V9 p8 x5 ]" y4 ^) }input axr0,
8 q3 T9 u, t% f5 @, p, Q9 Q- \. _
9 d/ J* J- g" {, {; C% boutput mcasp_afsr,
5 l6 c% @5 ~+ V; G( M+ soutput mcasp_ahclkr,
7 o" |0 r# R8 W3 ^output mcasp_aclkr,
$ ^9 m2 m+ m* I4 n. xoutput axr1,# i7 e5 B( s+ R \* l' y
assign mcasp_afsr = mcasp_afsx;4 g/ X. m b2 {/ b4 a( }: m, B: X
assign mcasp_aclkr = mcasp_aclkx;
/ A2 {7 A$ r! ^0 `assign mcasp_ahclkr = mcasp_ahclkx;: N+ j+ n/ \" C! ~! F
assign axr1 = axr0;
* K8 s% o! U1 K# q* y% _6 u! j7 q1 l& U9 [1 h# ~0 O) Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % p4 l$ @* f0 \. R
static void McASPI2SConfigure(void)7 G" R) V1 F# a
{4 t' y' M' v" b5 F, J+ ^0 ~) Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 {$ E3 ]# |( ^/ O5 y9 Z9 _3 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# c8 F+ U3 I1 q" D& F7 N. l$ WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# Q" |) j' M. j% e3 [( M/ L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) O) N- v* i# F: tMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 F( O; D2 Y# ~! J1 P& lMCASP_RX_MODE_DMA);
' C6 }- P7 N6 c5 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) p3 h4 k5 z7 S) G- g$ P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 C4 G8 d C8 f! c* ~. n) VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, F' K# G# `' l: _3 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- E. }4 H1 m( R# b9 u' {
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , h0 F' |4 `; E' r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 p6 h( @/ K& _% r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 n( _1 d: @8 G8 e, W8 \3 TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 [ F( l1 d) A* o2 g9 U* `# bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! O a0 W0 U' T4 M1 K2 z0x00, 0xFF); /* configure the clock for transmitter */
4 s1 W( _+ t ~8 {9 _% SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 _ h+ m2 g) N! L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 t/ c: g& ?" {# L9 z. u: vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 r; A4 I, ]7 t, J- |0x00, 0xFF);
$ M0 }; E- d" j7 `1 b, B; ?. w* V0 D" ?) O
/* Enable synchronization of RX and TX sections */
$ w- g0 I5 ^* b% p7 E* kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ i) ^1 r) X3 v3 Z" p
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# p+ B( {0 I; q+ o; l LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ v% m- l8 O. @9 A1 }! q& L* C
** Set the serializers, Currently only one serializer is set as
- X, X7 ^4 j( s% |$ K/ t; @** transmitter and one serializer as receiver.3 s4 c2 i, K: C6 `: r
*/7 Z+ n' f* M& [- t3 A; [0 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 Y3 d) i2 i0 v' t8 r, g4 y' w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: ]$ {0 v' q; Z) w
** Configure the McASP pins + a L: f4 |- F( B2 i
** Input - Frame Sync, Clock and Serializer Rx
- t9 Q8 l' q( d( c0 i: g4 E** Output - Serializer Tx is connected to the input of the codec 2 r" z* u; F4 M% Q
*/6 B, Z ?. v* @9 M; Q1 t* P3 C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# J+ k1 ^- U2 C$ m: Y$ Y0 X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% g1 B8 }. S# N& ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& R7 H2 R5 ]# Y$ W
| MCASP_PIN_ACLKX2 U/ |9 \, P% d8 v3 Y! M" Y
| MCASP_PIN_AHCLKX
- N, N. b: l9 o, I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 i- H" x6 D2 N+ T7 {# a' P
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! E. u+ u/ a# a/ k W| MCASP_TX_CLKFAIL
& `. E: }- {% j2 n0 y, I| MCASP_TX_SYNCERROR
: c: N) Y# D/ U. z' c+ W( x! @5 f( R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: b; y5 y" E+ ]9 g# Q+ h8 }| MCASP_RX_CLKFAIL8 s3 q; L \+ `
| MCASP_RX_SYNCERROR % u2 g: U7 L" Y, g
| MCASP_RX_OVERRUN);
& d4 M& _4 e1 |/ h8 a" ^( i/ z} static void I2SDataTxRxActivate(void)1 T5 ?' y4 U$ w. \
{* e( B+ `$ e5 `: A0 u' m2 z, r
/* Start the clocks */6 i; L2 N' L5 b, J5 {& z" Z, A; i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 N! s6 W8 M, [) q& R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! {" r4 N3 [/ SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* |0 T) J- e9 r/ u D* I( gEDMA3_TRIG_MODE_EVENT);) n( v" U0 r8 P4 e. o9 ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' N1 Y7 x- g5 n' ^8 B) s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: a/ Y$ c5 T ?( }" X8 c, K/ ]" j, I$ Y0 HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 E2 R: l3 g0 W/ z$ P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 D; \6 {$ M# E; [$ y' o/ f, s6 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. [4 u9 n* x+ f2 i1 c& }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 ?8 h: ~- A3 d; e* ~/ \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" E8 N2 k4 f" \. f" X} , t4 u1 x, N: g+ m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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