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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 _3 u2 ]2 q+ z/ ?# linput mcasp_ahclkx,
7 `% X6 f) j% ?1 _0 i" Yinput mcasp_aclkx,( _, {$ J% }! W) x
input axr0,$ {* V: U% a% ]
9 Z' S1 g+ b$ h K
output mcasp_afsr,
9 Q8 @4 k* i( Z5 ]$ L8 ~6 C2 o8 }output mcasp_ahclkr,
# C0 m$ f8 ] w# moutput mcasp_aclkr,
- F- v$ p( n5 F, J* Koutput axr1,! q7 h9 C+ i( ]) D
assign mcasp_afsr = mcasp_afsx;2 [ d- ~6 t3 e/ N$ q
assign mcasp_aclkr = mcasp_aclkx;
) T* K$ x" b, d; Gassign mcasp_ahclkr = mcasp_ahclkx;
! e# j. c5 m5 F7 ?" Z6 }assign axr1 = axr0; 7 K& N7 ~# b. k2 z. f( X( ^
+ u/ N$ D. o0 l7 ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ L/ Y, i+ r# {- C* kstatic void McASPI2SConfigure(void); ]6 f& {! Z$ M1 ]* U, ?; T; n; ^
{
& P" x0 ~: F7 I/ [ ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: D( ]+ K9 m' Q! \; B# YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 E" |9 Y5 [, q6 C+ u9 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% _% M1 |! t o) l9 V# ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ g2 f' m: R4 Q/ ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& ?" ^; D5 N$ @
MCASP_RX_MODE_DMA);* l5 [/ \& r' `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 O# [$ K; G) P1 a8 W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! }; [+ h: L% Y% JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' B- z: S. v# k n3 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ _* j8 j4 t8 K" m& TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 m8 P9 }. ~* @/ s# K* j2 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 C; d2 M* x( P+ E {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) |3 M# @* k1 S6 r/ Q# O: S& q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 g1 O5 W9 Y& a; S) X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," G; X+ |; V. {: Z
0x00, 0xFF); /* configure the clock for transmitter */
4 _$ {- F; e J4 G% [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 Z9 z- j+ j3 L* {$ ?) J; e. IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " A! _! r+ G0 g' ^8 d* W4 v1 H$ S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 n% \- {1 m/ ]7 T* E1 ]0x00, 0xFF);7 l6 d- T/ K2 H4 G7 _% F, D8 s
4 t' s8 J2 d0 A; N4 b
/* Enable synchronization of RX and TX sections */
# G5 _+ i5 N/ [; s6 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: d! X; j* v* J' R* t: iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 B: v$ o8 Y# a8 u$ Q. l" U4 nMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' k, ~7 y- A' u/ W1 ]! z' _** Set the serializers, Currently only one serializer is set as
8 A0 a+ M6 n% s2 N% {3 Q2 ]** transmitter and one serializer as receiver.
! ]2 A' b$ w% @' i1 o' j*/0 K# D9 f/ ?3 T2 h g2 X7 Y, I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* c* ~( v/ M0 c5 g( I8 ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% ]6 b+ B! M1 f: A$ f% x' [$ b** Configure the McASP pins
8 V* B, h8 P. Z# B** Input - Frame Sync, Clock and Serializer Rx1 a0 |3 V0 }7 n( l0 w' o ?
** Output - Serializer Tx is connected to the input of the codec % ]) h/ X1 A( \/ ]% ^2 N3 E6 d
*/
; P. _% V. R! u) [* ?* nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( y4 f0 y& m0 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) J( A" v3 J) C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* O) \: ^0 m9 u" O" v& L| MCASP_PIN_ACLKX
$ h" [9 |) a% p0 _: U" \| MCASP_PIN_AHCLKX
9 Q) w. ^: }& g# {% y0 F6 O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" A) N$ {6 E3 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 x9 Y4 o) h9 H
| MCASP_TX_CLKFAIL
- w1 l( i. q( _3 g| MCASP_TX_SYNCERROR
2 y$ Z& U6 M. y1 [( x. b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " b1 S! H. v4 e+ u$ R0 q d
| MCASP_RX_CLKFAIL7 O% X8 A. V8 `
| MCASP_RX_SYNCERROR
, L3 Q* ]/ F z- q| MCASP_RX_OVERRUN);- }- a7 j& h/ p
} static void I2SDataTxRxActivate(void)
$ G( M C0 v( f2 C7 g& e{
( [" u( ~+ c; ?/ S/* Start the clocks */
8 K3 `; M7 Z wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 U1 I, @9 }' z! P9 \1 jMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) z2 m2 ?/ j+ P" z& Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, z# |4 D4 L) {, c+ G8 ~& D
EDMA3_TRIG_MODE_EVENT);: S) n- V1 u. e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % m6 m* ~# i: I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' r* S8 {$ b5 j/ z b1 i% {0 c* J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: S8 J/ w* O% i' h5 D! T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 l5 K$ R' O$ M h0 R e, awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& e4 ~! f7 P7 Z7 h4 ~$ ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 }3 t8 K6 M2 h j: B) }( f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: E& U; N9 @' V; i, K1 O& Y7 O} 3 R) e9 Y/ V5 o+ [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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