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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: D, u/ s/ `+ _7 rinput mcasp_ahclkx,- f9 [3 S8 N7 {) F8 X% |# D3 `
input mcasp_aclkx,# s/ a I0 m- R# s/ J
input axr0,' m: Y! N! C% N0 A8 ~1 w- y0 E
: |0 Z7 m0 R+ ^8 b. M& `
output mcasp_afsr,$ p- X$ ^- x' N; A4 t
output mcasp_ahclkr,
1 L( n& s( K5 E- q. c' P) uoutput mcasp_aclkr,
0 K7 {% n/ \8 s: G0 Goutput axr1," O( E% M) P Z, A
assign mcasp_afsr = mcasp_afsx;
" y0 `* I- V3 Y, J1 Massign mcasp_aclkr = mcasp_aclkx;
7 L0 {6 \. u5 Iassign mcasp_ahclkr = mcasp_ahclkx;
+ a Q; U& R9 K/ Iassign axr1 = axr0;
& F& p5 ~" X! A* q8 K, T; `" v9 k$ i1 I9 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ~+ z. e5 F4 r; z! n& j2 I A7 B2 k
static void McASPI2SConfigure(void)
' E0 o J9 o& m' _; d{+ A+ ?: d$ u$ q! n: R _6 y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) z, [. b& x& J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, b& _2 e4 R5 O+ V; z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 R7 O6 l& ]- \+ R( U% @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. S* J9 `7 Z* S5 }- ]% c1 w5 ]3 sMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" \9 e3 y/ M# G, z( \MCASP_RX_MODE_DMA); E% {: H- w$ d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! @* |+ V9 B9 J0 O5 s! H! }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; M: z8 h. t. [% b' c8 u) f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 F8 c+ k% A; a% U; f i! f' cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 t: q, ~# r$ H2 B g9 B& ?# r, r/ kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % r( u& `6 W& k" f9 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( r. T# Y$ n' Z+ T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# Z$ ?1 l3 f0 S/ k2 WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 |! P- t9 C2 R1 F2 v1 V* J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) B3 b( Q5 Z8 T A! L6 y. X2 [0x00, 0xFF); /* configure the clock for transmitter */
5 l$ Q. F3 ?6 k$ g1 P. a7 ?4 J- @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 U0 C" {" H6 m4 F- z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 Z9 _* Y& T* T* a( wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," z; w9 ^4 j: w# d+ D
0x00, 0xFF);
5 y$ s( q5 o2 D4 K7 c$ k
) W- ~5 `; I* ^! R/* Enable synchronization of RX and TX sections */ ' C. K1 G: N$ x; j' Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 Q7 |! _5 f! Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 G4 n, _ j' j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: b! T) \& M0 f: |* v** Set the serializers, Currently only one serializer is set as1 U8 C% N9 ~. N, F
** transmitter and one serializer as receiver.
6 [1 Z* k, w6 F& b% Q1 a*/+ f9 e" ]# h, H {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ o% H |4 f5 C8 T! M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% P" }' _, N v i# k2 C* S
** Configure the McASP pins
3 B; y$ ^! X; q** Input - Frame Sync, Clock and Serializer Rx2 f; Y! T* D% ~+ H( \! X8 P# b
** Output - Serializer Tx is connected to the input of the codec
0 W1 n" V+ M n$ S6 f7 \*/$ `2 f8 E9 d5 {( C' o6 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- T: k. f( n( n' _: {( N3 W9 C* }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 C ~+ Y8 u! O3 ~7 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; x) L, G" h" f( V| MCASP_PIN_ACLKX
: G% l# s# h. d1 h2 c| MCASP_PIN_AHCLKX3 u! M' h4 I+ s) l: G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ T& R7 ?6 h: J9 O8 U3 [" }% u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) { y- o# B# u5 Y7 w
| MCASP_TX_CLKFAIL ! ?9 L9 Y6 Z! }1 O; i, w' ~5 X
| MCASP_TX_SYNCERROR5 ^+ R- d+ F3 ~2 i: O! I% h! N1 m" |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( F, S* g7 f" Q- J8 K. P
| MCASP_RX_CLKFAIL
) _ l' j+ h& F: J. || MCASP_RX_SYNCERROR _, S- o8 C: W6 t
| MCASP_RX_OVERRUN);0 _% _+ L- \) |4 t( K0 d2 j
} static void I2SDataTxRxActivate(void)
4 Q1 y8 }9 k2 l8 F' t( e" C{8 t$ X! M m, S) L" q& t9 s q! n
/* Start the clocks */: c% u Z E0 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. L2 s+ _1 F% \3 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) J' B4 r7 e" q3 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) n O+ N9 d3 N+ N3 f
EDMA3_TRIG_MODE_EVENT);" F/ g7 u) i5 D' \( e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, Q! h# @/ T8 o1 Q% `4 p" w- u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" u& A2 u2 F* zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 F6 B7 }7 V% h8 q+ Z& j/ K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 U4 @! F: V! ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ F3 z8 d$ B+ _$ n5 O6 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: O" h' Z+ N# F5 k9 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- i1 N6 Q+ }1 `
} % K" Z$ N1 l. F, h: t
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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