MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
$ v* p3 C; v6 K  ]- ^input mcasp_ahclkx,
, [, D& h+ @0 x+ J" einput mcasp_aclkx,
input axr0,

! s3 C* y; f3 w4 ]  ]3 @' Poutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
; n) a, B+ J( ?( A- Q+ Routput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

* H' [0 |/ c7 d. N0 A: A; e2 V

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

* e  e4 u! z: o& x( `# P3 ^( k* P/ w

static void McASPI2SConfigure(void)
! y* r' p+ V1 }{
' [5 y5 C: x* J6 @1 [: ^- }6 rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
  H2 B8 X+ n. ?( q. V8 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 _! Z/ X% [; m' QMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' ~+ b  ~) Y. ^! ?! O9 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' ~) h% z& k! J4 |, z. |- _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: q" i' `' j3 |# U3 c, RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
$ H0 H* S( v% Q: e! Y- kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 r( p5 K% e5 fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ j* c2 i- O% F6 ^4 N0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! u3 o  K& i; F( H$ W% yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) y4 S7 _/ G) Y9 b# L" N; W0x00, 0xFF);

5 {1 B) b* z* ^# d/* Enable synchronization of RX and TX sections */
; V' R, y( i, ^- m" B9 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ J: X4 V6 q' PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, n& {! e) X0 P5 D; aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
- t4 v2 c9 Q% t6 v( SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 B3 q- N. Q# R, B  U3 ?% X: ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
1 p5 }0 G6 f; [  X** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
% f4 G9 c- O% `. V*/
  I9 G3 a+ }3 I: |* x! ]* x! sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- J2 Y* w( t4 d  s6 B7 ?) \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ v$ s& i+ g5 N& v" T, k' [| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
! J- [" M: D0 c  ~5 eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( R7 u, k( o" N* f1 B| MCASP_TX_CLKFAIL
2 T7 {; \/ i; o6 l% [! G. o6 I| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# r* e+ B+ C4 q| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
+ i5 h6 c3 O! E- V| MCASP_RX_OVERRUN);
0 F; u$ x$ E4 ?  s' W}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
3 X: b9 i( Z1 K6 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 \" N: `. L/ Q3 oEDMA3_TRIG_MODE_EVENT);
* H% \: G4 x6 L- {+ r' LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 W; g$ A+ ?% pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ r4 Z* b9 D/ f- n! UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
* C( t3 n5 ~7 T4 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& b& E: w' M6 n# C; @4 j* oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 h! K& ?/ g  \7 @! Z0 V5 X& i- N) y}

4 l* B$ h5 E, K4 O: ~/ a" \' d

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

$ E: |7 G/ J8 P7 X- _; p5 T