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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- T; j: m0 {2 S uinput mcasp_ahclkx,
* \9 g$ z+ o: Q i1 `input mcasp_aclkx,/ f: [4 `- t7 G
input axr0,
" g( Z* G+ `0 X( O2 {" Y' K. ~
; c# k' ]( c5 R: ioutput mcasp_afsr,
. L+ P w l# f* O" moutput mcasp_ahclkr,
6 _6 P# i, ]' X* `+ X5 boutput mcasp_aclkr,2 L! j @$ H) q- F" H* X6 n4 ]
output axr1,7 T" p& u9 V# Z. P9 C
assign mcasp_afsr = mcasp_afsx;: A, P G# j$ b4 a
assign mcasp_aclkr = mcasp_aclkx;$ l v) D( k6 }( [1 \
assign mcasp_ahclkr = mcasp_ahclkx;
) W" O3 X6 G, Y9 m# s0 G& c/ c0 Dassign axr1 = axr0; 9 l0 X# T2 ?6 L, W! F( H5 e3 r
" t$ X( z8 r4 t2 o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" l5 R5 T9 z9 r' Y) [% fstatic void McASPI2SConfigure(void)
7 F& Z# l& _4 `# [{6 J/ _- T- {) A3 j7 B' ~4 W5 w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 ~ T( k: h2 \8 q' `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; S* d" p& u P+ ^4 |6 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% Q1 c- o% W+ N8 }) F4 l4 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ [$ |* d" ^" Q$ `6 X$ f2 M# T9 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 `. m( O' s |( m! _
MCASP_RX_MODE_DMA);/ l# n# R' W# z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 J: h0 l8 ^# R+ ^( x, i9 \, [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ t! A2 \" K1 t+ s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& O* f; \7 G' L- T! g9 CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); p4 k9 |$ v1 }( z) Y4 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* Z6 s: j3 x3 A! nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, _; C+ o" R4 F- ]/ j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: I! M! P2 [3 R# ~. c8 k* B
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* X7 y. o4 s# R- A# TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. p9 t. }. v( l0x00, 0xFF); /* configure the clock for transmitter */
5 H- b& e, n' e4 _3 tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: n. A2 Z! H+ X8 k$ S) |4 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- `5 {0 O$ T5 I, ^6 d- tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% _9 S1 C: r- G+ ]# c
0x00, 0xFF);
& q3 C, W% v% H. |5 Z2 L% p) L2 v0 Y7 @" y
/* Enable synchronization of RX and TX sections */ 1 y$ B* Y% z, x, M i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 e' p3 E3 D6 {, r/ oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 t! t3 e+ d, v* \McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ s' _5 W$ P# ~. ^1 V** Set the serializers, Currently only one serializer is set as
, q5 q- M+ U* h** transmitter and one serializer as receiver.+ n4 w S% V n/ i- K a
*/
$ h9 g% { y- w' Y* Q: w$ ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 D. ]7 f; \( ]7 ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: h- x6 ^/ j$ x @. P9 _) P+ O' p7 j- d** Configure the McASP pins
0 m j3 q$ o* I** Input - Frame Sync, Clock and Serializer Rx
6 R2 e$ ]6 V |** Output - Serializer Tx is connected to the input of the codec + o( p/ y' C D! i9 n0 O
*/
$ f( W* c7 @( n* ~% H' e5 N9 q! NMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 T* `6 F# ~1 S! Y7 n7 f6 iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% @, z& K8 R& z/ |# E/ Q4 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 k6 o$ l. ^8 n9 } V* R
| MCASP_PIN_ACLKX* R2 I, b( t. `) K
| MCASP_PIN_AHCLKX" \2 M0 E0 m; }" n7 r0 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// d$ m- F# m9 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 ]$ y/ h9 p5 ^! p" ]6 H; M, w
| MCASP_TX_CLKFAIL
$ B; m; _+ l/ W9 ?/ s- A$ j| MCASP_TX_SYNCERROR
T i' ^: k- u" k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: A1 ?: W& D9 B9 z3 ?% |0 n; u" z9 a| MCASP_RX_CLKFAIL2 {! @: k L) S+ A, c
| MCASP_RX_SYNCERROR
# f7 P& `5 }4 h, b7 m1 `| MCASP_RX_OVERRUN);( ]% a; K# e2 `( T
} static void I2SDataTxRxActivate(void). P, s4 d; `4 f
{% |+ N& h% ]6 Y5 S+ _ b$ i3 O q# J
/* Start the clocks */
! G; R# ?: K& c4 s: m" P) U* v- v9 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ n) `4 g1 [: y& L$ A8 i. M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: `+ y7 L( U0 j8 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& }% z- a: H. A% [8 J) a3 V
EDMA3_TRIG_MODE_EVENT);
! j5 _* R& ]* w% \( V0 D0 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ ~4 E: f9 ^& s' G( N4 HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! }( C) M" w- ]* ]' L1 u2 T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ p: a# Y6 ]: t) ^6 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ L8 t' N0 _6 H3 E/ y0 U0 a6 z# f1 Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 v& Z; n! @) H! u$ E* J& B3 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, x! i% [4 c, [, r/ c. O+ o$ }1 \, ^8 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 j- V# ]! }" g9 V" d. Q
}
* W7 w5 t& M" C! C* }1 J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. P% p, R7 S2 ]& M% w. w
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