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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, A3 w) j+ d3 I0 c9 g
input mcasp_ahclkx,
; J( a5 p' c3 k: Sinput mcasp_aclkx,
0 g6 g5 V# @: {% L3 ]2 U, ginput axr0,! W/ T* u" A# H- A1 i' V- K+ i
8 S2 F C3 Q3 N0 i) g, Routput mcasp_afsr,/ Z9 c! w8 @+ y* j3 P$ l6 e
output mcasp_ahclkr,- z. ^: e* s- q: ^4 a5 F
output mcasp_aclkr,
+ D3 m! I& \# I, q% i0 g7 j% Aoutput axr1,! E9 S& \. M0 o* T: ]/ |5 U
assign mcasp_afsr = mcasp_afsx;3 {: i2 M o# Q- P; P0 q
assign mcasp_aclkr = mcasp_aclkx;. M8 S2 M# Z; b2 [% D
assign mcasp_ahclkr = mcasp_ahclkx;
. r: ?3 O4 L; M U% b# e) Dassign axr1 = axr0; + K1 ~4 }/ j+ H7 v# p
8 V) {0 |4 ^* i0 P7 W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) D1 m) `2 D" m* G9 Ystatic void McASPI2SConfigure(void)
1 a7 C1 I" \5 B Z{
( z9 o2 q) ]5 k! UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" [, q- W& `! _' a! J" _; r8 }+ ?
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( a( Z# ?1 B! FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 f$ M- _4 N9 g+ Z( X8 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ n/ C$ x( i4 `3 [! `! M3 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. s% P$ e1 n( s- J1 X8 K0 f+ V
MCASP_RX_MODE_DMA);" q+ g8 @3 T1 k% R+ e1 ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 O, ]. t2 ?8 Y p& c# i5 zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; m( ^& y4 {7 D' T- N2 e4 U# F3 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " a- Y3 V' ^4 z. o5 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- I; @3 I: u y5 g4 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; m7 G$ |$ n2 H8 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 u$ X! v9 g. ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! [& r8 p& @1 U% F, M/ Z0 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% [* ^6 h6 k7 c( I1 J3 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# n1 Y m; d# y' f0x00, 0xFF); /* configure the clock for transmitter */
3 M5 r% K1 D" X- hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 g, ]7 ^; }5 G% k% ~* E8 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 L% N& [. k% u& y! MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; u7 _! u" ]0 X3 e! B0x00, 0xFF);2 z- o, H1 K" {' ~5 u) y
' U9 _) x' a2 q7 G9 _
/* Enable synchronization of RX and TX sections */
- T8 W, {3 L* q, z+ @6 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 d* |/ e9 y9 Z+ ^$ F' G5 Z! o/ Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- ?+ Z' G2 F( g, F& L z0 fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( a8 B' u3 W; x2 _; ^& Q c9 A
** Set the serializers, Currently only one serializer is set as
7 G$ b/ g* {3 b( M9 F** transmitter and one serializer as receiver." l t7 w ~ z: p
*/6 O& h& V& W9 k, z8 x- \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; V1 L& [" `1 F5 {, d" ~( ?1 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 B+ \/ O( o# V8 ?/ y! B. }
** Configure the McASP pins
0 i- m3 n$ H& ~7 u z p** Input - Frame Sync, Clock and Serializer Rx
8 O8 \2 K8 [& y** Output - Serializer Tx is connected to the input of the codec + e5 G5 j, U3 `
*/0 ]: B& {! o4 W; b+ u2 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& v* a5 p) n7 i8 _/ C- b! E& SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) \' h1 U& y' v8 h0 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) E% H1 m0 Q, k; a" `7 s
| MCASP_PIN_ACLKX3 A0 X k; L" g( }) B, x
| MCASP_PIN_AHCLKX5 |# r1 N0 c6 N& s! L$ G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ y( k* }- U$ j& F/ i" H# |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( ~" p8 W' r' |, g) H# ? k| MCASP_TX_CLKFAIL
, V5 A! B8 _+ g! Q2 [; B% K! z7 O| MCASP_TX_SYNCERROR
4 P5 F! E1 F q" l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 N" i1 x; w4 P- f8 ^| MCASP_RX_CLKFAIL
& E3 A( V7 M @; q/ [" g5 q5 i| MCASP_RX_SYNCERROR
+ S3 |( ^0 `7 p; ~| MCASP_RX_OVERRUN);" z1 B9 f' S6 @9 S8 d+ V- E9 q8 W
} static void I2SDataTxRxActivate(void)
9 J1 |; w. s' G0 |) a! f: @" }{6 [$ _. J9 v; O5 r& g# h) G p m+ i
/* Start the clocks */
, A' E( [4 t8 X3 L- Q/ a. EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- d, y5 H t' x- J9 |' u- r+ U3 EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( G% ]4 f% u: l/ l4 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 E* A4 [& g6 L7 Z3 E& j6 SEDMA3_TRIG_MODE_EVENT);% f, p3 g8 W" m* g8 C# o7 e# Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 L$ }7 \, Y; i, m9 m- d" j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& E7 j+ F2 s2 i" u" {- O' vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& P: D, N. F* Q5 R ?& H. FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ o3 g8 i9 C+ B+ v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ U3 {4 H$ g, M, O# U+ }: [% RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 o5 I2 d" e& {! e% ]0 x* X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! G) g. S: {, V4 w! t4 P& b6 j# J} ; d: A9 W/ j! ^5 d& e% e4 x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 W2 K& q: B9 ]% t# }
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