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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 L' Z" k) q! X# t8 q
input mcasp_ahclkx,6 N3 {, w9 p! q
input mcasp_aclkx,
/ a! E3 N% x4 m/ i: ] |0 iinput axr0,
- Z2 B. X/ `$ x% j9 s H( b- O9 |3 \9 l! \* M' V( }% B
output mcasp_afsr,' E, r+ ~& ]! T R
output mcasp_ahclkr,) I; P7 R/ t5 g7 p- N
output mcasp_aclkr,
! I w8 F6 F# y: W0 ioutput axr1,0 n% B0 f; a% e8 M* n& `1 L/ r4 N
assign mcasp_afsr = mcasp_afsx;
2 B: @3 A% |& ?) hassign mcasp_aclkr = mcasp_aclkx;3 K! p; u% }; c# d K; @2 N! t
assign mcasp_ahclkr = mcasp_ahclkx;
4 h% j8 a; W P7 V; p( R; nassign axr1 = axr0;
3 I8 s* w# L$ g2 O9 S9 S3 u5 y; Q* B8 k! j0 O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- O$ v% Y9 y y( O$ jstatic void McASPI2SConfigure(void)' L* U$ o/ S" u. z- [# @, m
{' r6 r b; o* C+ M1 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 ?- M4 O% y' \6 b$ dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 H8 u6 j. h" L- PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); t; D7 O& a$ @8 M% ^/ _6 c& n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 ^" {7 Q9 `4 U6 `" X0 }! C1 {
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 @; i# l, l) Z5 P( NMCASP_RX_MODE_DMA);
' U" V |! A4 \1 N; HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 k4 |+ x$ U$ M# h3 z) y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 R/ R1 _0 u( n# i+ R) }1 eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% n9 l+ W: Y* O, E- d$ `5 O4 v6 ~MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 {4 k9 X$ D7 r6 A8 s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % P( ?+ j7 l5 p# q6 | B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& _) o) Q* [* P9 Y* c: b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% o" ]: X$ K) w# ?; N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & C# ?; W/ @( [9 r5 q$ a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; [1 @% `5 `' w& v0x00, 0xFF); /* configure the clock for transmitter */2 r' \4 k$ o6 T8 y) L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 E5 i2 s K3 f+ |1 C, HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); f. |( `! X, ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 x$ k8 q5 z" C$ p; i% Y- U' j* d0x00, 0xFF);
& |! i" C* ^1 b5 j& q2 v7 H
" L$ n1 q2 M$ |. E/* Enable synchronization of RX and TX sections */
: K, z3 N" D! w5 y( [3 kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 v1 y7 v @' m) T* E5 `/ }# CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 a T L/ a8 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ s7 M% k. D' j: k1 C/ V; [" X
** Set the serializers, Currently only one serializer is set as! d1 J7 }2 g8 L/ ~' |$ U J
** transmitter and one serializer as receiver., ^6 |- v) M3 a
*/
# M* Y% X1 ]+ E! {7 a( XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 e) N9 i2 q( SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 h# s, m. o+ `3 v; d) {** Configure the McASP pins 3 [ D e8 w' g. a8 F) _
** Input - Frame Sync, Clock and Serializer Rx
* R; D/ U1 u4 B** Output - Serializer Tx is connected to the input of the codec # ` O& W$ @, V5 u
*/# K5 L* @+ @3 R& h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, Q" a! y0 _3 W1 y) h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; x1 w. \# X4 F) m( UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 j/ c$ h$ B; S| MCASP_PIN_ACLKX
! l s$ \" [6 m7 N4 R| MCASP_PIN_AHCLKX
/ P% M a1 |/ [# M2 b" X: m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 F; R: \# f) I& R- u$ x; bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 G! y2 C2 B) k+ u| MCASP_TX_CLKFAIL 3 I* \9 `* }7 P2 z! N
| MCASP_TX_SYNCERROR
/ s/ u0 _& Q7 F! B* N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 A: |* G2 C$ N" ^" w2 T
| MCASP_RX_CLKFAIL
/ K0 V; G; i+ }% u, S/ e| MCASP_RX_SYNCERROR 2 ?# ^/ r6 L' t
| MCASP_RX_OVERRUN);
% _0 A6 i! k6 C( G" l} static void I2SDataTxRxActivate(void)
4 h- L$ ]0 }" I9 i- V3 A{: j2 F w+ P' f) m: s' [+ M6 M( U
/* Start the clocks */
" g! N; ^( a5 F2 G4 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- |' P$ e$ q r0 a, z1 F. U- uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 v9 n- @9 O2 ? c; C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ e; m1 L& M. ?1 K! sEDMA3_TRIG_MODE_EVENT);5 C7 O' u5 f$ G: r/ i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % b- j& W6 T/ w- N9 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 J& D' @0 c! ^! N4 ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 K8 r0 {4 z$ |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// j5 e! L( m6 ]: @( ^8 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% }7 y$ U' H, W" w& P mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; v s1 W( {9 _* }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) N" v5 N7 d; l) m2 S$ A
}
2 ]0 ?$ ?' v, D& N* D$ l4 I8 D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . @6 _. j( K/ d1 M
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