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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 y2 i% |$ @ Y F- }" n. d
input mcasp_ahclkx,
1 u$ D* L3 R7 I, qinput mcasp_aclkx,
# r: e! w: P& s, R6 J+ T1 Minput axr0,
1 q+ O/ m4 I- Y0 c2 D$ N" G' f* L$ J: o$ N
output mcasp_afsr,# [( y! ]* A9 T4 J5 x; [
output mcasp_ahclkr,+ Q" ?( v' I0 w0 m4 m
output mcasp_aclkr,, d t [" {+ M+ d1 b. j
output axr1,) e# c. n" w% N2 [
assign mcasp_afsr = mcasp_afsx;
" R- l: g) K1 E* |0 A6 R$ Lassign mcasp_aclkr = mcasp_aclkx;
$ m& ~0 h2 K" D& t, Nassign mcasp_ahclkr = mcasp_ahclkx;: G! K! I' s, o+ U
assign axr1 = axr0;
% y( r+ j1 w- [8 U6 ]4 q2 p
1 c( n0 u G) U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. y U4 ^% c" _+ M9 P( j2 _# B8 i {static void McASPI2SConfigure(void)
) c5 q+ j v+ W+ E* {{7 W: y/ V! L U# G$ X" d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 E# k p- h/ Z- xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, w( q" _$ o; I; N* T( u) `; k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 A$ `2 \+ _1 O9 l( u- p+ _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 G9 ~) k# ]5 L+ GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" g; w. Q# ]$ eMCASP_RX_MODE_DMA);
# |9 g. G# w% E" e8 i" I* k( hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% J X, O+ q+ E3 @1 u4 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! |+ A+ `/ |1 z6 O5 gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 Y$ K: U3 o' l" X$ W3 }; [$ yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' X8 ^! |' o, A1 h3 ^& mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 }" p/ D+ ^: P" A+ r ?4 G! |* i2 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' S/ \6 F0 S" D$ B. Y, J4 w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! l& r4 D. Z( z! s0 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( W9 K7 `( m; r9 @7 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- Z7 ^+ ~% \* b+ P0x00, 0xFF); /* configure the clock for transmitter */
& X* {2 }: ?* U, `4 Y# B2 |* ?) lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 ?: q& H) h |" F) q# HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 s: D) V9 U+ c" a; \) a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 W7 O) O$ x0 _
0x00, 0xFF);* U! Z" @; ]3 `* C
4 \5 n D) `& {2 d1 `
/* Enable synchronization of RX and TX sections */ : {! r7 i" F: w+ K% k2 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" H/ o) W- L0 {7 |9 j q! g1 l. NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 Y% h; ]7 E2 c2 d3 H- ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 ?- F: s- y7 K9 d' d# E/ q, z4 U
** Set the serializers, Currently only one serializer is set as3 v: C, v, o, b" I. M- S
** transmitter and one serializer as receiver.
/ }8 }& D3 h1 ~2 M3 a7 p*/
, d. ] e$ [2 O0 O9 ~3 W& RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* m6 F& l# D5 A. v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 z _# N* H, ]9 E2 J" \2 v& F
** Configure the McASP pins 3 d8 O- g2 t o- ?# A/ ?
** Input - Frame Sync, Clock and Serializer Rx
7 k3 n7 F: q7 i- j' D** Output - Serializer Tx is connected to the input of the codec I$ g! O, ?" b* D/ j5 h2 Q$ x' K
*/5 h5 s {4 A# i' s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 [; ^7 c* }& B2 K, e: C h( b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: O9 b8 R' F, G8 D( DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' l8 t* L% f: m5 ^5 \- S| MCASP_PIN_ACLKX# |5 j& _, _% b: ]/ ~ K( t4 z
| MCASP_PIN_AHCLKX
, h2 i7 l+ \3 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ]4 _+ m; R% l5 L! d% f Z0 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 I7 Z( \: B1 s| MCASP_TX_CLKFAIL
9 k9 _! g; u, t( } u2 s| MCASP_TX_SYNCERROR9 i& `- G! \4 z7 l" i: t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 [1 ^2 g. ]' q* i" m3 h
| MCASP_RX_CLKFAIL
# J& Y0 t+ M7 X) Y% j8 k. K% _" v| MCASP_RX_SYNCERROR
4 H4 M' G% L% ?, O| MCASP_RX_OVERRUN);
* m* R/ u0 {$ q) x} static void I2SDataTxRxActivate(void)
8 T) d( k4 \; p{" P9 g5 r4 v0 m
/* Start the clocks *// t) W) r& _6 s& O4 h4 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& M. D1 Z5 _/ b! f4 w8 Z# G4 hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 ?- |- Q% b9 m% ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. u% K& n. |% S3 w! Y6 ~EDMA3_TRIG_MODE_EVENT);
$ G% w3 |$ H8 M! y$ _! sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ B& c M/ J' Q& R r( ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" d ^2 N) D @+ rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 C# [* q; x6 d; AMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; K+ J+ |2 d( M0 |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, g/ t* H8 m% u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ t# \& ~* `2 s/ U7 o1 P. |7 t# j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 Q% B% k4 Y% Z6 @6 `8 K} # V7 |. W3 ^" Z, [- l8 Q _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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