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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* v" G# @' ^- H1 g0 M( finput mcasp_ahclkx,; ]% r1 y# X. c H
input mcasp_aclkx,8 L' I0 D, L' m9 `/ r
input axr0,
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, M& [& l$ F- X; L0 Uoutput mcasp_afsr,
: k$ A9 m& n" v5 Uoutput mcasp_ahclkr,
! R) R9 {5 n9 H0 ^3 \output mcasp_aclkr,. N+ I7 ~: K6 s9 v; I( `) m
output axr1,
8 G s- ~- `! ` assign mcasp_afsr = mcasp_afsx;
4 `% X" M. c* |# d$ Tassign mcasp_aclkr = mcasp_aclkx;2 h# n" f' w9 h( m7 _6 m( S4 q
assign mcasp_ahclkr = mcasp_ahclkx;+ j2 b0 @1 n K9 u. [$ ^$ h
assign axr1 = axr0; $ n0 m( W/ X9 v3 X: T. B0 i/ M
9 t. l8 f5 u* `- l/ M7 u9 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ L. _8 Z6 ?9 [1 b. _* X
static void McASPI2SConfigure(void)/ D# F9 t/ ~- F/ T$ T# Z
{% d& a2 H# q! v8 C1 k/ Z% Z4 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. m: d4 E' ^& L- l9 l! cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* C1 ?* B2 H3 I5 W! jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 E, [% R* C, G4 q l5 e1 o- aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- C$ t7 b! s! D( t& ?# i9 j+ IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' ~* Y6 r& g7 U% x7 Z9 u
MCASP_RX_MODE_DMA); \; F2 R& U9 Q2 B/ ]% J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ p) B) L0 z6 G/ N1 `8 pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- V8 \% \9 }5 a0 M4 C HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / i, D& N" h" ~4 I3 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; R* D( Y9 w0 J+ ^" y& e d5 v% oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 A, k" A3 V/ l! S9 W% ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( H, ~- ]1 ~4 F ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. \. ~0 D. v0 w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . G9 r9 n6 B8 o/ t8 y4 g6 i& Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 y& t K1 ]/ {6 J8 T0x00, 0xFF); /* configure the clock for transmitter */. C" Y/ Q+ R2 q% Y. y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' X* g8 l/ `$ _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& S! l+ S- m4 W: S+ }" _) s3 CMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, l/ U6 ~# {1 q0 s9 _: w0x00, 0xFF);1 w$ H% G0 c+ R! @3 b& T$ v, e2 i
; ]' w, W& _# n2 r7 H' g) m
/* Enable synchronization of RX and TX sections */
4 J! v' e5 A& pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% \" Y0 q2 e5 Y$ m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& Y4 [6 Q, y' `& l5 R2 dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( s' X$ I4 r) ^2 p2 b6 `** Set the serializers, Currently only one serializer is set as
, M1 F$ e$ z' k** transmitter and one serializer as receiver.8 U2 Q& X( p9 i- b$ Q, F F
*/
8 F+ M2 I$ W% p6 b' b+ BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ N, B7 l o! O& N1 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) G8 S; x( ^/ B& J; F. N** Configure the McASP pins * k) [, \7 Z& J% A
** Input - Frame Sync, Clock and Serializer Rx6 v9 L& h* o, B' W7 H8 ~* Q
** Output - Serializer Tx is connected to the input of the codec
" H; d. Y' A: O6 n9 I/ O*/
' Q2 l2 I% e8 D9 }6 M# |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 M( t) V2 u3 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ^# p v6 b. h6 z3 N+ B1 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 |' z; W, m8 }5 T9 A| MCASP_PIN_ACLKX
~8 K2 V2 M( H1 c| MCASP_PIN_AHCLKX
% r& j+ R4 N' Z% p5 B; M' w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
^' d; m3 a# n/ h7 m. ?2 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& X" x: k! c8 I# t* [| MCASP_TX_CLKFAIL / g6 s+ g4 k+ f2 A! A
| MCASP_TX_SYNCERROR5 U) f: I! o, n+ w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * n2 ~& W" \2 p2 n0 Z
| MCASP_RX_CLKFAIL
+ x' H- f9 n5 r2 ~& ]| MCASP_RX_SYNCERROR
: ]6 t# Z& p4 G2 d% C" D| MCASP_RX_OVERRUN); R; _" i! g2 X* ] ?( V
} static void I2SDataTxRxActivate(void)6 d' A, [+ H8 P5 z6 ], L7 F2 h
{
2 e3 C8 n3 `3 Y4 e/* Start the clocks */
! r/ T* `+ B1 c7 k8 DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ m; v/ f3 H# y& |; ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; d1 f9 D) u; c2 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 f% J7 A/ u6 M
EDMA3_TRIG_MODE_EVENT);
1 J5 u$ Z6 K0 r+ @' kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! o0 a! U, j9 q0 [! K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; R8 e( P' R$ YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- r3 u) a% z' B( }# q$ u% h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 V, x% g, G9 g8 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 ?# O r' _9 f* ~1 i L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: P4 O, }- Y( iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; Y- E; I- r; v C: z0 H0 ^} - e8 c/ d- Y& P% Z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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