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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- W. |# p! A# oinput mcasp_ahclkx,
; N. I6 R* o* q Sinput mcasp_aclkx,
4 Q" ~7 R; Y1 \' ]input axr0,
, `& H" |1 F1 N) }$ O
* h, w7 i1 W q$ H) w' W3 Q* X/ youtput mcasp_afsr,' O/ D; y+ K* x# S9 V: R. x
output mcasp_ahclkr,/ y. q N e5 n8 X4 Z1 c9 H' t3 C
output mcasp_aclkr,
8 q& d; ]3 x" ?; Eoutput axr1,9 k5 @/ l, T# v7 G/ v7 H9 M R
assign mcasp_afsr = mcasp_afsx;
% f1 G8 b7 F7 ~assign mcasp_aclkr = mcasp_aclkx;! `" |* B ?) X- B
assign mcasp_ahclkr = mcasp_ahclkx;
: ?" B4 |7 j6 B3 G1 E7 ^1 Y% Oassign axr1 = axr0;
8 x) S4 J' h& _: o7 [3 r
. T* h2 A7 s. e/ t8 m0 |# W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 N3 Z# o( h1 H$ z f5 R
static void McASPI2SConfigure(void)
; C4 F! C$ m }& u0 Y$ X{: C" M; V& ^ @/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) N" @) i F& N5 A9 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# Q, ?1 [2 Q7 k% `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 g) z) |" e5 N# {% M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: q& o& \) r; A% U& v6 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" H8 |+ q/ t: eMCASP_RX_MODE_DMA);
+ M# G7 ]. s9 {- b" T0 _- o& b8 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 P' b1 J# R' `. h' |( A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 I6 s& Z. g# C# l& k, M" {- k7 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . y3 L4 ]$ H" s$ t% ^8 N' S5 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 m T) R( W$ |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + P3 O# X$ Q' {: U+ F$ R }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* u& y2 \, e- m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; B$ O. _. ]+ G, ?9 j# UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 Y- g4 N3 z b2 U1 Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% D0 F$ m* F' H
0x00, 0xFF); /* configure the clock for transmitter */0 m: \: T" Q$ Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 D! l: _. C0 p% w$ O) ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 D. J: }/ D/ g- UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ @$ D3 Q) l: S$ ]2 t
0x00, 0xFF);. o* c8 h$ T5 j/ J0 ^ V$ M2 H* @, }
3 ?" Z( Y. d3 w7 F1 r$ A. \/* Enable synchronization of RX and TX sections */ 8 n1 E- G; n. Z) u- T5 ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ E a: q9 ]/ N* B5 H! q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); A: A. |6 [7 p4 K* @, A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' c* {; [% \3 e. C** Set the serializers, Currently only one serializer is set as' s; D4 x5 R3 V& q) U
** transmitter and one serializer as receiver.- m/ y6 Y. k0 B: }' D) [
*/
7 d+ ]. N8 s4 |& v, ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( U! Y0 I( Z) ~0 N- FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ w* U1 i( A. C1 v
** Configure the McASP pins , T8 \' k4 ?. U5 S/ }. L- m/ F
** Input - Frame Sync, Clock and Serializer Rx
/ d0 s) [ n$ c* q- u; ]** Output - Serializer Tx is connected to the input of the codec : \2 |4 {, G5 f F* n9 i2 M+ j
*/1 E0 E+ C2 s; s! D; P$ D& L0 N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' y: ^6 t- c9 a7 u3 K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. b$ a' c: H4 A" n: [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; L8 P7 B4 u" l/ N
| MCASP_PIN_ACLKX
' O9 U7 Y$ K5 w' L| MCASP_PIN_AHCLKX
" W$ _+ s u! W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) M4 f9 b2 w+ z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ H' W2 u. i' i( w0 `9 z| MCASP_TX_CLKFAIL
/ R: J; i# Q, w/ f# A4 ^7 C| MCASP_TX_SYNCERROR) A0 {1 L- b. I O
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. k7 V* I# S2 K \9 _2 W| MCASP_RX_CLKFAIL/ W! ?3 `/ X8 M2 Q$ D
| MCASP_RX_SYNCERROR . a+ k0 V Q5 a% }* L( q; L: I, `
| MCASP_RX_OVERRUN);$ T2 y' b, P/ ^" a3 k6 ~7 k! u8 K) D9 X
} static void I2SDataTxRxActivate(void)8 e3 f2 F [8 E1 N
{
! s. _3 n7 h& ?6 K1 O/* Start the clocks */
( W, P" `$ \$ T3 d' e! w9 B2 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! Q V! s& O1 R, Q* T$ HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 Q& D, R6 f ^2 W. {" D4 t5 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 x# O. l6 k! x/ {: ]4 Q0 W M6 XEDMA3_TRIG_MODE_EVENT);
$ Q4 X! {" \) Q6 D* @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * O: o `2 i0 U' f2 q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. ]1 e- b2 x3 a `0 R0 l: ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& |: }, c! r4 W: d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& O5 U5 q1 z+ @, W( m" y5 O; Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
a4 \8 J( G' O# b4 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);: n2 J" Z" m4 O7 y+ u% v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 N% U" ]7 h6 t' }) h} 6 l, q0 Q* W( r% I/ Q: ~9 I+ o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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