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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( p0 v, n3 E7 x1 I( d- W& `6 l4 [input mcasp_ahclkx,
0 b' z' T, ? u+ A N$ C' \input mcasp_aclkx,
$ T& I7 a7 I& Rinput axr0,
. G0 U# E+ B6 }7 @# ~4 v( h$ S8 d1 e" W% {
output mcasp_afsr,/ d' u: S: }5 D5 G- H4 t5 ^: |
output mcasp_ahclkr,
6 V x* E/ U; Z1 b: a! Voutput mcasp_aclkr,# s$ C9 f$ H! S6 | \( \, |3 F
output axr1," Y$ {- E0 n' v# R* m
assign mcasp_afsr = mcasp_afsx;7 X5 @6 Q9 e6 w1 y# z1 i: \
assign mcasp_aclkr = mcasp_aclkx;" A# F' J' F2 F# W
assign mcasp_ahclkr = mcasp_ahclkx;; I% @1 ~2 B$ l6 ^
assign axr1 = axr0;
3 k) r( R% s0 O# y2 |+ I- ] Y; q5 ]+ S- S) d6 m9 y- h% U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 {! r( v! }1 d5 Z! w& K
static void McASPI2SConfigure(void)
) g1 ^& Y, _( [) {, V5 J{
8 y8 X5 Q' A. v9 M4 K' N$ X% z! WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 r8 L" Q4 |+ o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- J" W( F/ x) i; z7 P2 g$ P& cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 ]0 p0 o: K6 H/ mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 B1 @+ }3 x" R, r+ ~) A7 }8 N0 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% r5 B# r/ y; U. E2 c- ~2 V' u
MCASP_RX_MODE_DMA);$ {6 Q9 T$ @) V! l; n* i' ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& r1 I! V' P( W" T$ @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- V% ~; U# ~) \. H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 A9 b) J/ J/ h5 M: X3 }( @1 ? GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! G- {, s1 U% n6 ?$ zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ K \+ C# s2 ^( ~3 sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 \* B) G( d, O$ l7 g y3 ^; c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 S( E' l5 Y9 V1 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) }& Q3 d7 a) n- Z1 b9 P7 C8 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; M1 [) r1 O0 ]% S i
0x00, 0xFF); /* configure the clock for transmitter */
' w3 `& S1 x! ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- B3 S- ~- a/ k, a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 P5 c! E: M% {: A/ A
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# @+ w0 r8 n7 {+ o8 w( G0x00, 0xFF);+ {/ i2 v# t6 h, ], z. P" Q# K4 F
2 L. L6 b( [/ n8 p5 L/* Enable synchronization of RX and TX sections */ ) S$ h5 L; S. k, U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ r. }9 Y9 v) t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 O+ _( h2 g' i+ z7 J$ W: hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 A+ E0 t& i$ W' U( i** Set the serializers, Currently only one serializer is set as
7 L- a, g9 E8 R$ h. j% O' d- g! e** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ d+ ~7 o6 ~# Q' v. v2 WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. B) p: h4 S( x* F
** Configure the McASP pins
R `8 F( l7 N" V5 J2 T# P( n/ N** Input - Frame Sync, Clock and Serializer Rx
: `) a1 q) m( x B' x7 R: `( Y2 v** Output - Serializer Tx is connected to the input of the codec
) E2 [( Q! o) G) z2 Q! v4 y*/
, k- p7 `# h9 B! XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# a* i; H& M# g- Q' t5 L) j/ t
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# U' _+ B2 g% g, D7 G% A7 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
E3 V, x) V- D, B+ ]& i6 j| MCASP_PIN_ACLKX: c. t Q' b+ S) c) s6 a- G& k
| MCASP_PIN_AHCLKX
8 N, Y' v- j, p2 D8 ~8 f* E" z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. v/ N B: H" J7 s( N* R1 v, T; gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( a. u. S5 L W2 w1 t. A6 q3 S
| MCASP_TX_CLKFAIL
3 B- B u" c% w| MCASP_TX_SYNCERROR
% H) O, [6 L& I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % M* @3 T" r- |) |' Q+ S
| MCASP_RX_CLKFAIL) i9 B. T& V, A+ s ]8 V
| MCASP_RX_SYNCERROR
1 _4 L: X# i# m8 q| MCASP_RX_OVERRUN);( z2 r5 l! h$ B& q: T
} static void I2SDataTxRxActivate(void) H$ ~6 K1 s9 T0 b/ \- }
{
# U6 q$ p& U7 J! }/* Start the clocks */! I( x" k2 E2 b" y- I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( b6 E$ {) C9 N3 V& t' GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& k% ^* H' k. X* i; mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' |- v0 j# S. P
EDMA3_TRIG_MODE_EVENT);+ H1 K: D- X1 g% y+ p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 W& N$ U; F n* N& NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! C4 Y% A! ?3 } ?, b% Y+ AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* a, y! e) @5 v; ?& SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" P# D: X7 [( O" Y3 N
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 U, n6 ^3 T8 P/ n9 C) pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 s8 @# C8 @6 b- C8 I3 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ I. t( g9 k5 C2 S# F, h( A. P
} " L7 s! t, }& [- ?& P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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