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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ p' L4 ?) t, W U7 t( m) @/ i& e
input mcasp_ahclkx,
+ n* K5 h8 n- k$ xinput mcasp_aclkx,: M+ r# X- t3 M# G0 I
input axr0,9 d( o& F! v6 M* b4 W7 u; }' Q: t
0 W' f$ ?& v- C5 n3 W3 p$ {6 L
output mcasp_afsr,7 p; a( e8 }# N5 R2 W8 @% H
output mcasp_ahclkr,! x# E" y" o. W* v. B
output mcasp_aclkr,! {, y! X2 Z+ D. U4 E
output axr1,# B/ w, n. o f% Q* V( e5 l
assign mcasp_afsr = mcasp_afsx;# B* ~- u; v0 T" ]4 z+ Z
assign mcasp_aclkr = mcasp_aclkx;
+ A/ e' Y0 Y$ ?assign mcasp_ahclkr = mcasp_ahclkx;
2 T+ r4 V( S& @* o( }9 a. Jassign axr1 = axr0;
, C0 Y( @4 R1 m4 t8 o# s6 v0 [7 Y k! B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; m* g* O% B3 v- N/ ~
static void McASPI2SConfigure(void)
* |& c9 [, P$ O# S% ~9 u{9 k$ e) {! `. Y: i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' M! ~0 s' Y& d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 ?) x5 w# J8 {2 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ \% o T; T* L2 p! zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 c4 w" L- f% M8 Z3 x2 ?& AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 x4 I5 j1 x1 y
MCASP_RX_MODE_DMA);- K5 P4 ?3 X2 q4 @; T& R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 @- S4 q- D( K! s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ e" W) Y- A7 O# t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# _$ }9 A$ a' S) s# |' ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' k3 w" U2 G0 Q: K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
L$ o, u) ]1 {1 i3 _+ TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 K) W$ _2 f' [1 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 r4 t; |, r: b3 @+ y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); g+ n. l, v& P9 u, J, E* W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ l9 d6 H# N& v& y8 D# Z9 ]+ e0x00, 0xFF); /* configure the clock for transmitter */
' _9 w! k+ Z8 ?! Y$ ?9 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ R o+ g/ K* r( ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 `+ g' V7 o( A' z# d+ Q1 P& HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, v2 t4 ]$ V1 Y2 Q. z/ z0x00, 0xFF);
0 X! c# i% U; V1 S6 [4 Z1 c
( k1 y- U* _) Z5 x6 Z9 Z) f" \/* Enable synchronization of RX and TX sections */
7 X7 \. O1 @, t; u% H" J! ~) a4 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, V" Z/ J: N& t* D; ~8 F- AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 g8 J$ j3 E l# K9 n; m9 ~: a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# C" o) i) @7 D** Set the serializers, Currently only one serializer is set as: x0 V2 \3 J P
** transmitter and one serializer as receiver.
4 i) Y% W3 ^0 P+ I*/
' D8 Z0 R% Q0 y8 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) D3 c2 f- U9 A* c- E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' N D$ W: D5 G1 i; d% p5 F** Configure the McASP pins
& k) ~, _# M* h- x8 N** Input - Frame Sync, Clock and Serializer Rx
* V% Z$ d$ |& k% Q** Output - Serializer Tx is connected to the input of the codec - r8 q# O2 G" l. W
*/3 v2 T, ^) J0 W! m7 R1 [$ P+ ?6 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) e. ^- o) }0 g# C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" k8 z. ~0 L7 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ X+ Y- |6 d2 `2 T
| MCASP_PIN_ACLKX+ J" S7 K* ]1 P
| MCASP_PIN_AHCLKX
3 c) @3 c4 z3 k% e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 ^+ X: t D! B7 @
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 n, r- f3 c! B; n& [% Q
| MCASP_TX_CLKFAIL
( l, u# a [# u! r9 p' b: k| MCASP_TX_SYNCERROR
6 |7 l3 B6 G+ v4 L+ i# A1 X" n0 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# J5 q. w9 }" `$ m4 O- J| MCASP_RX_CLKFAIL: x7 }5 B2 S* a2 h
| MCASP_RX_SYNCERROR . a, ~% M, y) {) r7 U
| MCASP_RX_OVERRUN);% h; U }% w6 z, o* v8 c3 G. V
} static void I2SDataTxRxActivate(void)
) f5 e8 x9 [# @# n' P{4 `; W- ]+ V2 f |
/* Start the clocks */
) X$ [4 E6 B# R3 ~" m/ P5 Z; OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ t0 X9 N; ~3 ]# J: ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// p% |9 U" l8 y2 S# N5 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# D! [# F+ n( m T; UEDMA3_TRIG_MODE_EVENT);
4 M2 ?4 G* X0 D$ M/ A3 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . P$ \9 J6 w# d/ f7 I' ~! g0 j- p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& E0 k% f# f8 y, c/ K# HMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 S Y6 i4 {& M" D& lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 ?/ K( j: C" u0 Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% D2 r1 j a' m, @ G& I5 O( B, c; c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 k/ A+ S. [$ b* `0 j0 c3 ^9 Z& s$ r" J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 Q, n$ O5 [/ G0 o1 v, n}
: J) ]/ c6 G0 U7 k7 h+ O! K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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