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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, S. @* e: R- u( [ F' u I' s
input mcasp_ahclkx,
7 W3 O# H% C* d0 {input mcasp_aclkx,2 |; M% w7 M# t c9 q, j$ m& m% l
input axr0,/ r' A9 y+ n% x' _6 l
" q9 Y' I. f7 p* V1 a+ f: g& Doutput mcasp_afsr,1 m) G+ X2 s( U! M7 \
output mcasp_ahclkr,
! L. ^6 l; G" Y+ Loutput mcasp_aclkr,/ i" ~" G: U- o. ?: f
output axr1,
' f5 Y: p. r9 v. Q% E7 g assign mcasp_afsr = mcasp_afsx;4 K& e) C- h4 ^' D
assign mcasp_aclkr = mcasp_aclkx;2 m+ S8 V' F S! W4 y( N1 I
assign mcasp_ahclkr = mcasp_ahclkx;" [# r. X' \6 l) Y1 H7 E) c
assign axr1 = axr0; ! C: I" M+ v+ c: P
$ X$ u% b! X Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 O4 d, ?( l/ N8 C2 [! N& g8 Xstatic void McASPI2SConfigure(void)
8 m* I" A, Z( M, U9 ^ @{8 {& N' r# B0 G( u3 X7 U# w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ^) A( F& u; g2 _* j1 H$ D# c& w4 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- ~& Y2 u" U5 a1 o3 ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ q, V" W6 D" t) F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& i! z8 E# I- U4 U/ [1 E$ wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 Q* F5 F M8 z+ F
MCASP_RX_MODE_DMA);" O6 e* ^' G& s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% \1 X. k% m! B" H2 g6 p; b+ b' J/ yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& C2 m4 @- x* b, ?, F9 b eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 Q B& q; e8 R9 w0 P1 `7 d: iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: D$ ~% I7 p# p" w& R5 s) Z; YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' v4 L4 z8 z( A% d/ b Z1 NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' b' f) h# s% c3 p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 i% W1 ], W- _* pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" X: n& m$ R( _. c3 G& G' OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 D4 ?6 a. C; S
0x00, 0xFF); /* configure the clock for transmitter */
- a, ~) [ D5 O5 a. kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- E6 R: ]1 U& T6 h3 P9 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- {; y, S: S0 L' DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 M! M7 c4 G) f2 ~ z
0x00, 0xFF);
0 n2 U3 y# i7 @; k, c3 ]* n& C9 B+ t$ g0 I* p
/* Enable synchronization of RX and TX sections */
* u1 @; k8 H1 e7 w( VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ J. j6 {" R2 Z$ D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 N( P: k: V: Z+ g" d8 X$ M! uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; p8 R: V* @$ t! W" E+ O& Q' T9 @
** Set the serializers, Currently only one serializer is set as
9 n+ O4 U# v I$ Y) u8 U** transmitter and one serializer as receiver.5 A% z- m6 A' L% |
*/! F0 h1 k+ G$ D# M* z' I; z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, [# c/ i l1 W w8 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" }: |" C% G: i# w7 T9 x) `** Configure the McASP pins
( a5 s s- F( ]** Input - Frame Sync, Clock and Serializer Rx
% t. y$ c8 K: R h( Y& J$ l7 S# x** Output - Serializer Tx is connected to the input of the codec 3 @6 K( @% }- w( p& t
*/
$ t4 Q3 s8 _* }# D* ?& BMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ v- [' q* ^) J Z: w7 p! MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% ^4 L( D. {+ S, L' T. g: h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 \8 i+ y3 b% v, b2 ]& K! p| MCASP_PIN_ACLKX
8 Q( r) _# f6 B| MCASP_PIN_AHCLKX
( K, D5 l/ \% I' g. Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 Z* G2 m3 c! y" S& G3 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 m; l" n( g# _0 x| MCASP_TX_CLKFAIL . I* G4 O# f9 q. A0 s! Z
| MCASP_TX_SYNCERROR7 ^+ \9 j& D0 ~' }6 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
D* v" k# C b% t- @" T& B| MCASP_RX_CLKFAIL. L3 ?5 q% Y& v
| MCASP_RX_SYNCERROR
) a$ @$ h8 a4 C6 B9 v, M3 {| MCASP_RX_OVERRUN);
% C+ E2 t4 z* g; u( |' {7 F9 @} static void I2SDataTxRxActivate(void)
! e1 I# G% C& e" j/ l0 f{1 `! Z. a( }: T# E; [0 E
/* Start the clocks */
0 g' H9 q0 F) z0 h9 y" m: ^4 j: V# UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# r5 u; G5 I6 b" z# P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// l/ n+ U9 _* n, C/ y. k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
^3 r; Y1 h9 o* k4 A" p: |) l9 ~EDMA3_TRIG_MODE_EVENT);
% _$ \% \$ X" s/ sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , e! m1 ^8 B- _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 j2 l4 _( [3 s4 _/ W& D' m$ O' Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ i6 U; `; p9 }9 E! [ |* gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 a! {# u9 ?2 a8 F% R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ H3 N2 a$ `/ k8 g" G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- G0 p. R S: Q4 w- p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( f- A0 S8 U. x: q) r}
* J* y4 A% ~+ m$ S2 w* f" Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . Y, o7 w) N, q( I
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