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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( w" m* A6 j2 Y- M2 M
input mcasp_ahclkx,
2 G6 C8 N5 Z7 s6 f9 oinput mcasp_aclkx,
4 a* i1 L7 v/ B# \: R0 Z, t% Minput axr0,
2 X% W2 I/ }, ^9 R0 @
- Q! U1 q- F. n6 n7 boutput mcasp_afsr," {3 z1 x" e9 N! y! l
output mcasp_ahclkr,% e% ^: ^ {5 Y6 h" [# Y
output mcasp_aclkr,
9 M7 f* K4 h: f6 _- ]! Xoutput axr1,
% S. W0 Z0 k0 g assign mcasp_afsr = mcasp_afsx;
t6 k" F% d8 k& Y8 G7 M/ zassign mcasp_aclkr = mcasp_aclkx;2 v9 Z& Q0 m2 e
assign mcasp_ahclkr = mcasp_ahclkx;
7 X) o: s. h. _: P( N4 wassign axr1 = axr0; # _+ v1 }+ c( d: y4 O9 r
. [. o7 }( H' Y' ?% \5 W+ g! J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 Y' o$ n5 {3 C |0 z a dstatic void McASPI2SConfigure(void)9 K- ^/ t6 Z1 j
{
9 w8 s. D5 D5 N0 s$ a& sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( g: Y9 R j& ?1 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" n- q! R4 L) E, d+ @1 a: Q( y# D- C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 w, F6 G0 P! s% k; G- ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- t1 d7 @/ [) Y7 T: E; M3 N7 v4 \% K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 e- K- S, I6 Q% }8 l- C% r
MCASP_RX_MODE_DMA);$ J; _& @1 U9 x3 n2 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ^* l0 a$ O! r. ]8 _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- Q* G2 E: A4 y+ w |& a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / T9 v/ K D3 L5 P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 X3 l6 t: q. a8 ? W! {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ L9 s3 M1 I6 M! F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- K% w# S4 u4 J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 K, h L3 a# ^ M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 x- o2 e) _5 L) a' ~0 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 h4 g4 \6 N2 K! ]- N3 x# C0x00, 0xFF); /* configure the clock for transmitter */* g; M) Q7 m# G" k4 ~( B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 o. z$ c% q* I( j0 K; t$ ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ t' [/ G4 i# r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, j7 r: I" \% U( L; G
0x00, 0xFF);
$ S' Q, t$ |5 E! L0 ]% r u1 m
. c/ {0 G$ J! S& ^5 d/* Enable synchronization of RX and TX sections */
8 n" e3 s0 e3 n2 l( ~2 B! SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 M9 }. b9 ?8 U8 l+ N2 y+ }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ o8 c1 h- T3 K$ }McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* s% d$ m1 a& d** Set the serializers, Currently only one serializer is set as
* u/ Z5 x. r6 @9 }; s: H** transmitter and one serializer as receiver.- N* | Y- G! Z* v4 Y
*/
; d h! d n- NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 h; M7 `+ A% @! M6 \$ Q# v% U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ o" O' `! M$ ` t8 V( c
** Configure the McASP pins
) t' d( B$ K1 k5 \: N** Input - Frame Sync, Clock and Serializer Rx! Q' x3 v. {- n( W6 p& r
** Output - Serializer Tx is connected to the input of the codec
' p, M0 E' W* \# w/ O*/5 p, T' |5 U; G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; S0 P$ T% y1 {' H/ b; v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 }; }1 d6 f1 X z9 Z( l' ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, \$ H) ~ t( l% f6 V2 p: s6 x| MCASP_PIN_ACLKX
2 q! e7 v5 |" L" i& J- U5 N| MCASP_PIN_AHCLKX
% g* c: u1 i# P/ l| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- U$ E% F8 D4 Z- yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) N+ Q4 g3 c: k0 J! z
| MCASP_TX_CLKFAIL
. i+ o* f3 ^- j: v* `! G. d| MCASP_TX_SYNCERROR
1 Z9 z& @, Z4 ?. {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # ]& a8 B8 M5 V* W( v$ i% z
| MCASP_RX_CLKFAIL
; B! A/ S* N3 a( q" E| MCASP_RX_SYNCERROR
/ f/ y& u& j P% m| MCASP_RX_OVERRUN);
( V5 b( O3 Y" ] V} static void I2SDataTxRxActivate(void)
# z0 o; g! p" {+ H& o# M) i{, i, {6 H j0 ]: C. X
/* Start the clocks */7 R+ i% x- b* ?8 T7 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ? X7 x3 u6 q R4 V9 m- m O# p4 \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, W J7 |0 m& x! ?( ]* j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 g' Z; ~4 G! O4 D' `4 b1 bEDMA3_TRIG_MODE_EVENT);
) j* B1 N) O! I2 ?+ F, p% ?2 r* aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; j" z% n) `1 a8 z3 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% Y) Q( c2 |7 ^$ eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 b' t: _. d$ T3 O- o) Q- C8 s! @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ i2 u/ `2 r: _# V/ F2 Q( L/ V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% T) b! E+ o" _6 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' M- }& ~ }! ]! _McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# J& z& I* ~3 i+ H}
- q- Y1 L+ J9 _ Y' Q9 }9 u' w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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