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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 q! ?$ X: u J3 p/ [input mcasp_ahclkx,
* X8 s, R% Q9 Q% r/ k3 f0 R" Binput mcasp_aclkx,0 J. H; V' Q" M
input axr0,
2 {4 f" \& q2 F* f) C
5 }' Q' P1 A: W" _ n Xoutput mcasp_afsr, I" z' J% X7 j% A
output mcasp_ahclkr,2 f7 D1 L3 x; o1 G p
output mcasp_aclkr,
! h2 X3 q" f; [* M$ [8 Qoutput axr1,
4 _+ d" S) {8 N assign mcasp_afsr = mcasp_afsx;2 {. D1 _, V* c: |* y7 L
assign mcasp_aclkr = mcasp_aclkx;( @, a! B- P! `) W! |1 M7 \
assign mcasp_ahclkr = mcasp_ahclkx;
) p8 s3 w5 Y) w9 D! u' O9 ?. R6 fassign axr1 = axr0; 0 Y d/ p8 T1 U2 ]3 J
: [0 {- G! p: n+ {+ x6 D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / `7 w j- v3 [; H: M+ {
static void McASPI2SConfigure(void)4 @" A! M2 \8 R5 h! H7 C
{
/ H1 U5 e Z M" VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" `( p8 A% I1 T# L5 j* m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. z/ E# e& w/ Q' i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& m/ U0 N3 y7 |- S) _5 E/ Q$ y% CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* F3 \# f! V D1 K. L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! Q) J& l+ ?( O$ p; l# k+ eMCASP_RX_MODE_DMA);
# A9 w# f: A2 s4 c. kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 r* {6 m$ Q) _( P. {& x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) l# `. M7 _+ I2 YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) _3 X* C' ?6 d3 ]8 E7 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, V/ ]+ y- j; o) S i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 R$ f/ x/ x+ k' F5 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& @) |. A/ |* |5 S5 x: B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
\: ^: z6 v4 a# JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ ^! H" G( E$ z T& iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! n7 w1 {$ u! k4 I7 z! H# u0x00, 0xFF); /* configure the clock for transmitter */
8 K+ f- p& D) Y- oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ K) }0 @8 M6 x+ z: i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ [, K/ K) Q* ^# y5 F, [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 g4 \% S z" W9 ]$ m, a0 d0x00, 0xFF);
, _& {' q# E: F) n! J( x9 k
- B" V2 e. o/ q) X/* Enable synchronization of RX and TX sections */
# A+ f5 W" W \6 MMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// Y% O" c$ \- ~% W! p- R; F, m% s8 k/ g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 k$ e. P& U% b p# PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** F+ I0 ~% ^2 D2 a4 a8 l* v
** Set the serializers, Currently only one serializer is set as2 w8 H5 R+ y$ Z; E' I; e: C
** transmitter and one serializer as receiver.) t, }0 U# N4 B8 |
*/9 T! e. m! V9 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 y/ Q. l# g* l; d4 c: A9 x+ OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ k g. R* E$ q1 ]** Configure the McASP pins
, W; A8 E" r8 l** Input - Frame Sync, Clock and Serializer Rx- `" Y% Q. P$ a$ u7 i! N. R
** Output - Serializer Tx is connected to the input of the codec
* j* u2 K3 S, z, U: w*/( _0 k0 v* V' k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% G2 v1 B' |% q: T7 ^- i: v! [* c& z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( {- s7 X8 n a9 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, k) O! {( ?( V k3 Q N| MCASP_PIN_ACLKX
: B( Z7 M$ O( C R| MCASP_PIN_AHCLKX; z8 [/ C* K; ^( A' ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 D8 {5 i" E: N8 M7 J9 x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 B% f& l9 J p, y# b H
| MCASP_TX_CLKFAIL
" r4 D* C0 m3 U4 w3 K, ^2 Z| MCASP_TX_SYNCERROR/ p6 q% s7 ^1 ]$ f# \7 @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
L" I1 O9 p- h' E6 ^0 O| MCASP_RX_CLKFAIL
t( F' z, Z6 \| MCASP_RX_SYNCERROR ) [+ T/ ~6 q3 ~4 R3 {
| MCASP_RX_OVERRUN);, M) k6 U- e- ?* N6 L
} static void I2SDataTxRxActivate(void)
) R8 j5 e. a9 w( ?* {3 E) R{+ ^! e- M- k4 h- P( p7 F% D. W( [
/* Start the clocks */
0 e( G5 I: W& Z! L: DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
s7 Y" ]& q3 d+ [% w3 d9 @: v" dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ^% s6 `+ b0 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ L# ]! L( t) P* L- ? ]
EDMA3_TRIG_MODE_EVENT);% t& x* G, Z/ g$ B+ `' U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! c2 E! r3 g$ y B8 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ ^$ i0 O! o6 z' g9 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: }0 D* m( E( R9 {! ~* ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) h: R# o; ~3 g) e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) b: {+ z# i3 E: [3 f, \' i( HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. u4 |2 I" `1 kMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ L) u* }9 H' ?* ~4 P: d2 x3 Q
} & w* A9 i& L8 k' m( O: g) [( o9 J* J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
* z: `1 {; |, k, E: @; `1 U: p' c; U% H |