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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 w- h$ w+ b( Z! N( q8 K7 R
input mcasp_ahclkx,& A( x1 |: m+ i. a
input mcasp_aclkx,4 N* l2 ~1 N* C7 ~
input axr0,
6 q N% {, w- Y4 a$ G4 x- [, A4 m2 F/ S
output mcasp_afsr,
0 t. I- ^2 U0 Noutput mcasp_ahclkr, r8 n/ ?: A5 n* S4 I
output mcasp_aclkr,
2 z& w X# X& W! T6 f9 joutput axr1,
+ Z$ L8 G8 J9 a$ Z% [9 F3 ?3 ` assign mcasp_afsr = mcasp_afsx;
) P4 G" l3 J nassign mcasp_aclkr = mcasp_aclkx;7 F9 w, J0 T8 W+ V( ]
assign mcasp_ahclkr = mcasp_ahclkx;
5 O$ W, K2 [) I) sassign axr1 = axr0; 8 N( O" {5 m% \
3 F" ~+ v# V3 x# l+ b8 n _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 o k$ ?+ Y' B
static void McASPI2SConfigure(void)( ~' B2 p" B2 `5 J9 j O4 {
{
$ g. z8 s5 M2 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! H1 R. L/ V2 T& }# rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 X; H$ l8 }. ^, bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 S. u( M* t3 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 z( L1 I/ ?0 d x' p+ JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 P1 Y5 V7 K: A _: {, ?, C
MCASP_RX_MODE_DMA);
/ A, w4 [+ W) v7 {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# I" r# w$ l% k) u( NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 A O5 `$ e/ A N& L, U4 d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 _" \0 v) V" R1 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- |6 R$ z3 K8 _+ N' Q( c: R5 m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 [% x$ n' H B7 Z1 S, S% R' y) }, ^/ OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; o9 Y+ e5 ~0 Y! {( n$ }" U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) ~% r% J3 q [+ |# {8 e) Z% m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 V2 ~: o2 ?" G8 N& h; s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* I$ U/ @1 V- D3 N2 q( ~0x00, 0xFF); /* configure the clock for transmitter */5 W; V" W: s7 t2 S& j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 O" |) z: n Y& h( ]. @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 s! T& z/ a7 i& v; V2 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 y9 Z3 ?) M5 l+ _7 y% K ^! G
0x00, 0xFF);
7 C) f4 T" j' [. s$ @
9 f$ e F9 b7 |! d/* Enable synchronization of RX and TX sections */ 3 x* Q; j9 C6 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- ^3 Y2 \1 C3 ]; d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 D& T s0 f0 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ ~8 r5 P2 j3 c5 y$ o' G Q** Set the serializers, Currently only one serializer is set as0 c a* _- L9 i6 g; i3 }
** transmitter and one serializer as receiver.7 g) ?' t2 z( j% v
*/
6 X; ~7 E2 L% w4 [$ MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' G) @3 U6 d) r' v/ m& o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! c+ m, [1 c) I+ r1 W! l+ f2 e6 u** Configure the McASP pins , a [% Z$ b2 C$ d
** Input - Frame Sync, Clock and Serializer Rx- j; F- ]7 O& H6 G! H, m
** Output - Serializer Tx is connected to the input of the codec 8 s% F0 X, K6 W- N
*/
$ F+ o C5 f2 r" bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: G8 Z- j4 c+ K6 t' MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! s+ d2 [3 p% vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. A4 o; F. J* |9 }' P* U| MCASP_PIN_ACLKX
; I' m) Y- X; n/ k2 O4 a; J3 @| MCASP_PIN_AHCLKX; Y. J4 N1 K4 Q$ U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// r% R+ B" O+ T. d% f; j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 m _7 K$ v+ [/ K| MCASP_TX_CLKFAIL 2 s. s2 s" s, e+ l) z
| MCASP_TX_SYNCERROR' F# c9 l1 N1 c/ d9 R! a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% N8 u4 ^; P* || MCASP_RX_CLKFAIL
- Q G! E% D; Z& Y2 W| MCASP_RX_SYNCERROR ) y& C8 } r0 X) y+ z- B
| MCASP_RX_OVERRUN);
6 Y+ s$ [4 w* |# ~} static void I2SDataTxRxActivate(void)
, d# I5 `8 w# I% r4 \9 n{
, W3 U! g' v- _) u7 D8 w% {. h- |/* Start the clocks */
. F1 }# V) |7 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 ^% |0 t' p3 L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' f2 L; x! E7 X5 E k! Y8 d8 R9 k6 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ F$ E0 _7 z$ H3 y# i# F$ ZEDMA3_TRIG_MODE_EVENT);
" T; d( A+ i2 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . L! e' V1 J1 `& f+ _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 R1 E2 f2 ~6 }* b1 t0 m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 k& Q' x. [4 y: W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: B8 X* q h" ~3 E& t2 Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, h: a( p, V4 oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% L5 e9 a$ ]$ u- t/ _5 Y9 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% Z9 a5 |( X$ ?! ?}
4 D- _- o' b8 T2 L* B& z( E/ e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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