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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. z6 T( v& H8 vinput mcasp_ahclkx,
9 @2 |9 o4 x6 \) n. finput mcasp_aclkx,% q. } a7 `3 C' X9 n; q; I
input axr0,! v) ]5 [: R) b( z
# Y; s2 S j$ |1 z/ |" R6 _output mcasp_afsr,) f: F# L7 a8 B, z2 L, u
output mcasp_ahclkr,; B1 C8 `' d. P( G! ^: O/ V; b
output mcasp_aclkr,2 |4 L4 k6 ?5 k
output axr1,
1 E- R0 {3 g, c/ o" ` assign mcasp_afsr = mcasp_afsx;$ D, m; k. Q# E* ^# Y& o
assign mcasp_aclkr = mcasp_aclkx;( ~6 Z, m6 e+ S P( v
assign mcasp_ahclkr = mcasp_ahclkx;
0 U4 l3 S( O" `; yassign axr1 = axr0;
p5 \2 l+ A) r% c6 t% @6 N% j
7 w7 a# R" b% m" S/ R% @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ U" R6 g1 X1 A$ B4 F7 Gstatic void McASPI2SConfigure(void). l' ^6 j. Z( m8 K- _
{
0 e n% h0 l1 ^$ E# M: i- kMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 ~% q9 H6 n3 I3 @5 I Q5 @% n, b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ ?1 I$ \% w5 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% Z0 a% c2 j& m" B5 F1 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 E% k5 K6 t2 {) O9 A" f- Y% @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. a( k& D, Q) R y1 Z# z6 HMCASP_RX_MODE_DMA);
/ }' `8 E. d) j: U- C2 AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( H- C1 A" |& j" A# O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 X. O$ Q0 d% w/ @$ y" ?' i/ VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' F+ w+ m( [1 {% F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 h$ w1 ~4 o2 ?. d2 m1 Y& G
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & y' ^, p/ I% q; n& n: b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 ?, n, _+ {. b$ xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& T/ c# m- Q" l i# u2 j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' @" y. B( o9 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! m; D, y. E1 C" S+ \
0x00, 0xFF); /* configure the clock for transmitter */4 X/ u8 b; i( _! S# \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 Y+ G9 o% G0 j% j3 K6 N9 S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) {6 B, B7 O6 S3 l/ m8 D6 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 h" F+ D- V; X0 \
0x00, 0xFF);
: D9 \& q; v8 K3 G0 x5 t4 q4 y
/* Enable synchronization of RX and TX sections */
6 Y n, q; A p# U: fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 V6 ]! r! E8 j# L) aMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 h) Q1 K0 Z9 k, q9 j" jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- J4 R( X. m' U/ Y9 a
** Set the serializers, Currently only one serializer is set as
1 Y( X- ~) I" j( i; `4 x/ m' s** transmitter and one serializer as receiver.
) U: X A% Y- L3 ?*/
, S/ o* U7 n* [1 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: \; g# u% s( D; ] rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 X4 {+ |- q1 y, P, m; r/ T
** Configure the McASP pins
S5 d$ h' n) O" T** Input - Frame Sync, Clock and Serializer Rx
l" |8 |2 V: c b** Output - Serializer Tx is connected to the input of the codec
2 i) b9 M5 ?7 ?3 e/ T& ?7 j5 `( R*/0 K0 w5 p8 T, V8 |, m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ A: V2 Y# ]) Y6 A5 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) l! g1 m5 S% ^+ ^9 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' g9 M% {" d* V| MCASP_PIN_ACLKX
N3 h) `7 K2 q B2 U- l# g| MCASP_PIN_AHCLKX
, ^; b G$ Z8 }* N7 @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% L& H- D+ p0 E5 L c$ wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: f! F/ L1 J+ E, J$ G| MCASP_TX_CLKFAIL
/ C* |0 U+ m0 z$ z, w| MCASP_TX_SYNCERROR1 F. o- @# `% _7 @: R3 s" ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 q3 N+ E/ f: t, w; T| MCASP_RX_CLKFAIL( E+ @- p3 q' l9 R8 p3 m- p: N( u
| MCASP_RX_SYNCERROR 6 R n( N/ T; d# l! H! F1 \& s
| MCASP_RX_OVERRUN);; z2 q" n) I' I& S* ?1 f8 W
} static void I2SDataTxRxActivate(void)
H. m" v" t# k; \8 p{
$ D6 G, r+ _+ L/* Start the clocks */5 r8 S$ {$ w6 R# O$ @. v4 {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 `8 H6 G( X# S: [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ g& z9 g7 ^2 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- \, ?) Q3 {% [6 S
EDMA3_TRIG_MODE_EVENT);
! S- N& T* W0 i. f/ S4 }# c1 a6 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 h" h6 x, `- r) W2 P* V a4 t' S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# \9 ?( I; z: B. _7 }4 M- {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& E( I+ I1 E, b, S9 F6 X1 e3 [& u+ [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( @* s. E) R; H9 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 R5 I* B, R9 R7 j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 c# L! \% m. r4 B
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 t' ~1 i- C1 |4 C; c5 v
} 6 f( T, R" \+ u+ a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 }( K; e1 i/ u4 b# H3 K6 E
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