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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* {9 G3 z( z9 x( T
input mcasp_ahclkx,
) a" F3 T0 k4 H% e. V0 F( {input mcasp_aclkx,
9 e3 P% T. l0 Hinput axr0,: ~8 I. X/ R4 G( h
; x. p. u# U0 X2 xoutput mcasp_afsr,
% {( q2 J+ O) n, h! i1 {) Goutput mcasp_ahclkr,2 D5 ~* R, u) G0 k! `9 l' X
output mcasp_aclkr,0 ?0 |# w3 v8 U2 o* }& d+ j% V
output axr1,
5 W1 o+ H/ k$ C assign mcasp_afsr = mcasp_afsx;
' \2 W, ~0 }$ e0 `: e1 X" iassign mcasp_aclkr = mcasp_aclkx;) s. ^& H& Z6 e$ h1 [6 m
assign mcasp_ahclkr = mcasp_ahclkx;
5 K- O. Q" a0 U8 g5 f$ p ~assign axr1 = axr0; ! ~6 l( ]& I8 \/ [! ~0 v
. m" X8 Y" V0 r) K6 v" H& l/ d& ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 c5 p8 [4 v: _2 v/ W5 Ystatic void McASPI2SConfigure(void)
' m1 w. v6 w( }; ~6 [5 {{3 }" O$ {# |9 M1 t* q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; n D7 x/ O+ H+ \1 R X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) N( X0 n6 y0 l0 B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: E/ U b7 S2 y! q1 u$ n1 X b0 k; K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ S, n+ o9 A4 m: nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 L4 k8 |; q& |4 M2 e
MCASP_RX_MODE_DMA);6 w3 }: q6 Y9 y7 {3 h Y1 Q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" G9 @0 D- f& C8 Y* y3 k# {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ U ?6 B# S0 P) T; ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" G2 K( D) C) q# _1 j4 t [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); Y- z+ G+ H3 Z$ F7 h, ]; T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# Y1 {" }9 k8 V% p( n& h8 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 U+ S0 m8 V1 _& L' f U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* X: P! G9 {' C* c% ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( `& |, m& o; S% h1 y3 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ k; o L; F- f) O/ I% D0x00, 0xFF); /* configure the clock for transmitter */
. ^" U/ i; S' B2 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 t! | J" O# {; I, o; M5 m+ SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# J8 x- i, P8 O% f9 B8 ]& vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# g1 ]4 ]- z7 ^$ f; V# D0x00, 0xFF);9 ?4 i6 H+ ?* W3 l
4 D5 g! k" ^2 w/ t6 N" C# @- s8 X3 M
/* Enable synchronization of RX and TX sections */
" ^, J1 j* r7 J7 d$ y( I- {" LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 H; r. d; i% \$ b7 FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 d( [9 [6 e+ O. x5 V2 k1 }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 t* A0 A( r7 k4 X2 e5 ^' `
** Set the serializers, Currently only one serializer is set as0 _* f& v0 R9 x& A
** transmitter and one serializer as receiver.
" e6 b( X) M% v*/
8 Q- s" f* V$ VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& L& N O) F0 H$ x+ M! O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) A+ K. P( B1 b% {
** Configure the McASP pins
5 E6 W) `, D0 W* G7 K2 P8 x1 _** Input - Frame Sync, Clock and Serializer Rx
; B! D- H, v9 N. x) E% \** Output - Serializer Tx is connected to the input of the codec ) X6 ?; U8 J) V' W- j3 m
*/
0 x: P+ D% I0 d& _5 U' k7 t0 Q; q9 GMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 T8 B2 V$ E) l; ^# t/ V, \( {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 E+ Y8 R- t8 i4 x" U1 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, l) J! F# o: @' a; r- }3 X& A$ j
| MCASP_PIN_ACLKX% x+ S' ^) y2 u* S
| MCASP_PIN_AHCLKX
* P* ^+ x# ?4 m: r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 a8 ^! I c: YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 ^4 B) t0 V( q
| MCASP_TX_CLKFAIL
% E, C$ T/ N) D4 ~| MCASP_TX_SYNCERROR
2 d+ Y7 F7 J, J, J. j! r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* |2 z" K# \# t1 g7 E1 n| MCASP_RX_CLKFAIL
# u9 j. P, \4 A/ V| MCASP_RX_SYNCERROR 2 f2 B% N2 [1 V, n, g5 l
| MCASP_RX_OVERRUN);6 j7 D1 Q8 ^' y+ W6 C! E& c$ s
} static void I2SDataTxRxActivate(void)6 n' W, A+ ~* S( ]6 G* P
{
% k1 L8 |4 ^$ f0 ^+ |1 T/* Start the clocks */
, U! R! [% l. T' [McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 ?' F$ H5 Y4 f: i" h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ P& i9 b4 ]& g' W0 m2 X+ m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ `1 w$ c. E: k/ x6 K
EDMA3_TRIG_MODE_EVENT);
" R$ p Z# R% B- S2 x2 k! I4 x! {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 W# W7 h7 K$ e+ M# r/ ?6 eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 s7 N! I$ T L2 P) qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) `8 U& {- ^/ Q' I3 p- I4 M" j
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. v; t) Z% A9 g1 @2 U9 X- L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 Q- L/ G$ r. r- V1 G6 Y5 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( ]9 D- x K/ {6 o* V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 E3 A, X6 b l* u5 T% }: I) l} 7 [3 J8 V. a* e2 e& C* s0 ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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