|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 C5 C; e- B7 \' Einput mcasp_ahclkx,3 G; h5 z& a. d1 W& A9 [0 x
input mcasp_aclkx,
# f+ p+ Z- t+ h* p; Winput axr0,
K, [7 i, W8 C' i# D: g
, B8 s% G3 \* N- Coutput mcasp_afsr,% Y7 A: A& T2 t' L; R4 T2 _6 a+ X& j
output mcasp_ahclkr,
& Y& R# @5 k* }# }- v- T- moutput mcasp_aclkr,5 H7 l+ J; `1 s8 L% d
output axr1,
7 N( Z! S6 f- ?7 r/ N1 R$ L assign mcasp_afsr = mcasp_afsx;2 [- L. \, O g
assign mcasp_aclkr = mcasp_aclkx;
( h0 ^' Q! Y8 p H6 M- z7 W# X3 Wassign mcasp_ahclkr = mcasp_ahclkx;
; q# `! v9 z9 ]' f/ b6 K6 i. Vassign axr1 = axr0; 0 Z5 h* {% R; U* I3 R* O) z1 M2 p
* E6 y- [! W1 r) G# i9 W( O8 Z8 d$ ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) a* ^* D1 n( X0 P; H5 Q6 i
static void McASPI2SConfigure(void): \( e& {5 U2 ?- u; N. _
{* }; Z% v* Z! h2 x; P r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# u( X' ~' @' g/ y7 FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! R# \/ C; Q7 N5 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( n2 Y4 \ r% [; p0 z* s3 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# `, B1 u( s9 }8 I1 }& K* F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* f) [. e a6 L! P. N0 ?
MCASP_RX_MODE_DMA);
) G" J" n* ~' s$ qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) q& _% `1 Q6 M' K2 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, a, D# G" k: I2 L/ ^4 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! v: M _' {3 s1 ]- P8 [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- b R( s6 D& k+ ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
^$ I& @3 H1 o& ]% bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ s' ]1 }- J/ P ^" \1 I" U9 n. HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- j" I. Q* `( I
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 K0 t: `$ |+ S5 v$ D P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% C+ g, k6 }6 Z. B7 R( }# Y
0x00, 0xFF); /* configure the clock for transmitter */
: O9 u9 i" d& y u( m$ p; HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% X$ |# l! @0 {2 B" q' T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 W5 a9 k; Q4 |+ } K: BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ x- H" @- n$ g, n ]- g! o, T0x00, 0xFF);
* l* {! m) j1 b9 A. k) _+ }* W" k* e1 E3 t: B7 ~
/* Enable synchronization of RX and TX sections */
0 V3 Q Q" i3 EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 a! d |& O, t& xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ Z5 t3 P- S5 EMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ Y+ c( f# A, t' v+ M: S
** Set the serializers, Currently only one serializer is set as
! O; b4 B# ?$ F** transmitter and one serializer as receiver.( H, }- X3 Y C- j& }( b, V8 B' {
*/
4 v/ { a, k; hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ L+ ~) D! @5 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 w. H2 H Y3 `5 z* p: r** Configure the McASP pins 3 L. S$ ^$ y6 G2 M6 G( |
** Input - Frame Sync, Clock and Serializer Rx3 M l, ^6 V5 ]/ z- M
** Output - Serializer Tx is connected to the input of the codec
8 e; a. G! V0 ?- n9 i& ~*/. N) X, }. P/ D4 ]1 ?7 r
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 C% p; V# f$ K9 ^6 Y9 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- w# V' n F1 j+ }! f6 r, Y$ j- m6 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- g: x! l" ^. m4 g# R% N; B| MCASP_PIN_ACLKX5 {: X0 h& t( H3 w2 y3 p5 P2 S
| MCASP_PIN_AHCLKX4 w+ H. ^0 Q9 K/ X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' R/ {9 M3 V! ^* gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ J- ]" d' R. ~$ Z| MCASP_TX_CLKFAIL
7 }+ _2 i* x7 Y/ P4 q| MCASP_TX_SYNCERROR
+ L! i. o0 g0 J5 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 l. E0 L, {9 a0 }9 h& K
| MCASP_RX_CLKFAIL/ f# a6 J/ K* @4 ~
| MCASP_RX_SYNCERROR
4 @1 I* q! t, g. a9 N5 |" \| MCASP_RX_OVERRUN);
u' v. V5 ]! M8 d: g4 w9 Q} static void I2SDataTxRxActivate(void)
' P$ b; s Q( o* A+ n! |) {{% r+ a2 {3 g: j. [% ^3 y& k9 O9 _
/* Start the clocks */
: F1 B6 q+ o/ a) B# @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 C) `1 p6 A' Y" D! [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* @; Z2 q$ @/ _) \, ^7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 m, I5 O5 u& n4 ]4 w# r
EDMA3_TRIG_MODE_EVENT);
* a# G j4 T, C4 y. `( KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; m& a( S; O( A0 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 K% Y& T4 ]+ J2 F8 c {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 H4 g' b" p4 aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 \! y, J ^! C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! `& \3 T# {/ U; u `; M0 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ ~# r2 N1 w3 A' K% i$ e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! m5 V& ^# o6 D}
% |0 w K; D/ ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , H5 c% O: {: e7 p3 o8 p. w
|