|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. L! p& l; R0 C+ ?0 \input mcasp_ahclkx,
$ ?- S2 F; x$ j& I# m2 ~$ v: i. ainput mcasp_aclkx,0 q+ u: W, m0 R$ b
input axr0,( @- w8 E. i* X$ k) r' A& p
. f! |# e# p! { Z1 J
output mcasp_afsr,, V4 `+ w. [! L
output mcasp_ahclkr,
% h: Q P. |1 loutput mcasp_aclkr,# `4 X; b* `8 P$ N" P
output axr1,' k- N; S2 t/ {* p! x. D7 Z
assign mcasp_afsr = mcasp_afsx;
( ^$ a- K" M6 Y! Q# d9 q9 bassign mcasp_aclkr = mcasp_aclkx;3 A: z+ O6 @4 ?9 e' `8 S9 B
assign mcasp_ahclkr = mcasp_ahclkx;: Q& q6 S& r& b. n3 x5 n
assign axr1 = axr0;
' |6 [9 Z8 e5 u- E" t) D6 t3 ~% b; o8 O; v I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 D4 N- t, E" f3 ]% [2 j6 o
static void McASPI2SConfigure(void)
$ J5 M% y% z7 C+ j5 v{$ v8 p1 T( D1 p: I& s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 C: S0 Y3 O. g9 h+ N* z, ~6 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: Q8 T; R7 a7 `" |+ O; _1 t1 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ K% f7 ^& u N& w3 f1 F3 P9 q- K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' Y ~. m$ A, X) S" ^! K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 w3 L/ K7 O8 K t* z# k0 B1 Y) kMCASP_RX_MODE_DMA);; c1 G2 U% D( W" s* t2 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, d3 {+ B! E% L9 R% r& Q' }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, ]/ {; n+ N2 g5 `; r4 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% X( e% q5 A# `" S$ b: ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ B- Y7 r+ _& p7 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 l% Q, P5 ]) F& _' G: d$ BMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 V: W) j* x% F7 i- n) NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 [( i% B, h8 n4 }; n, `' L5 `8 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) V$ Z: q; q! {, WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( D; _! S4 f) ~' ^7 s
0x00, 0xFF); /* configure the clock for transmitter */
" z9 m; y2 ]/ Q, o* U; QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( i+ v0 m, ?! P3 {7 M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ L3 t; M5 S9 e ^8 t7 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* N! p2 E5 R) s$ a, A4 ^( y0x00, 0xFF);# I. p( m1 O$ C" P) @
8 i# c+ `4 g b0 G
/* Enable synchronization of RX and TX sections */ 1 K" b$ v/ H* W$ \# l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ N* X% b; |4 A2 ?- U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- z/ F! U1 Z8 A; B; n) iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ G6 h) \. z: I2 F0 X
** Set the serializers, Currently only one serializer is set as
9 K0 Z- Q. Y3 \+ H% j1 F$ }; N* G** transmitter and one serializer as receiver.
9 C( w7 ]8 F; g! G9 V6 v. v. x*/
7 c: e Q) i" l% ^. mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* m# q( U+ t% f) ^9 x% v. aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* @/ l! m" z5 E; X' m$ N; _0 P** Configure the McASP pins ' @" S3 g- ?5 ] D
** Input - Frame Sync, Clock and Serializer Rx
2 `; Q4 h0 _6 G& f' S** Output - Serializer Tx is connected to the input of the codec # y0 l) Q, H2 Y9 E+ `
*/( F6 {6 |. R( X( C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' N/ x; s. P0 X9 F8 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" e8 @6 `' f$ w! [/ k8 g5 g5 o4 x) }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 n$ w8 i2 G. K2 C1 z
| MCASP_PIN_ACLKX5 _% F( ?8 @4 ?, e6 X
| MCASP_PIN_AHCLKX8 S: O9 v! X3 m8 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; a# D: ]! \$ w, l2 W. ~: s# t* F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ ^1 x0 B# `/ D; @9 s5 u1 l# X| MCASP_TX_CLKFAIL
6 g, Y y6 h2 |: `| MCASP_TX_SYNCERROR
$ T( y( _: P! [, y! O: N0 Q5 b$ y% ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) e1 E& f8 ]( R; n# Z| MCASP_RX_CLKFAIL
8 g/ V0 o' A5 M" R| MCASP_RX_SYNCERROR
- C+ T7 w- J3 M. j4 k. L. A/ s| MCASP_RX_OVERRUN);, I6 @, ~- G" `
} static void I2SDataTxRxActivate(void)
: ]# i$ c. g9 ]/ [{
. w+ J- Q2 t9 }) P3 F- w( l: `" I/* Start the clocks */
( A% f, p" T# j& B8 ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 U7 g9 A- Q. h" `" m" A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 S6 H6 A4 i+ t" H- Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' h8 q- B, \ N% j \
EDMA3_TRIG_MODE_EVENT);% P/ K! M+ E( l* S$ v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; `5 F& V. x5 ^* I6 _ z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ }. b$ ]% c* m* o" O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& ^, Q+ d- t4 s9 W1 c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" U. H7 U9 N! x' `5 e# qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ ]* b7 G1 ?0 @& S5 q# B
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" l: S& a/ `- m3 K! L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 S. q( \* S# n7 [}
' x0 G+ N) s5 P* B& X5 D q r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 a% T' B9 b) [" f |