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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. O! Y8 ?! e# T* W
input mcasp_ahclkx,
$ {* J+ g( E# ^; Finput mcasp_aclkx,( i+ r4 T3 R1 A# x, V6 {0 ~/ ?2 a
input axr0,
. e1 `( ~* X+ R5 I0 W. P2 S. N. b$ z- K5 e* e/ h5 K
output mcasp_afsr,# K- }! V" C C4 c3 ^/ e
output mcasp_ahclkr,/ c, T6 j2 @* d5 K4 ?# T" L
output mcasp_aclkr,; B7 g! Z( V' E: D
output axr1,6 L/ U9 q r; s; f" Q
assign mcasp_afsr = mcasp_afsx;: c, q: @- e) G! R; n. Q1 B
assign mcasp_aclkr = mcasp_aclkx;
+ z; K- `5 v5 M) R+ u5 passign mcasp_ahclkr = mcasp_ahclkx;
1 D; w- j* \" h# n. Zassign axr1 = axr0; $ l; K, p! v, i! F* F; C2 x, H3 G
' N8 D% l6 p- c& l/ B' q' y* E i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 }( v. }, I$ cstatic void McASPI2SConfigure(void)
) K$ s: Y- s5 m* Z{
8 E. s5 b/ x9 A( Z n9 TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' v: M% d, ~2 v- G# xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ r) ~" v- P( qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 d8 f# R$ F( q, s' g/ W6 d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 S9 L" X9 Y# I! X2 B6 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ H" @: N$ `8 o2 U& F: _MCASP_RX_MODE_DMA);) f" a( z9 V2 ~+ Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# G- C, N' Z" D& I! fMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 ^/ A' n% Y, C/ C% w) C2 G7 V0 k4 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; u# u, [& u, B7 b7 g' t) M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, t; z) Y( ]1 D) q7 R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 ^* V3 `( w! k5 M. I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! i, q4 U# }: c% _7 DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. {' H( q2 z2 D% M4 T% m+ FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* a% r) ~) P+ t: \) b( nMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 t. q5 \. u- c
0x00, 0xFF); /* configure the clock for transmitter *// H4 m( ~5 k/ Z0 L' ]/ a! j* u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* {1 t, Q! w& s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) f$ j4 D1 ]; v; p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 p2 z" V8 w) p$ Z- A8 r8 h. n o
0x00, 0xFF);
, L( e& l* |% N, E( C5 ?
* h% h/ W" s M1 b/* Enable synchronization of RX and TX sections */ 1 Q2 s* ^% B5 F8 P. s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% O+ Z; E( U* k6 l* Z) N% M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 }9 M8 w1 W" {- G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- p# [' Q |+ h s6 n% z2 i \** Set the serializers, Currently only one serializer is set as( s; k" u, G U" ]' n
** transmitter and one serializer as receiver.; n* K( b, F, V# v8 k
*/- f# R `( J% j; A0 m! h2 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 B% `0 e @- {5 _: ]5 @: d8 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; E$ y! k8 X. S6 |8 V** Configure the McASP pins + o. F2 {% I6 G0 o# l6 k1 D
** Input - Frame Sync, Clock and Serializer Rx8 k: T p8 I$ R+ O7 w! U8 X" S2 o
** Output - Serializer Tx is connected to the input of the codec
* V }: t- A5 Z% z/ E2 p, R3 ]9 L*/
8 a/ T" d" ~ X2 Q4 r; Q QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% g) z$ W7 F: H3 y' j/ ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 v' B4 B0 U$ G8 Y- b1 W* z& h [' X7 D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 P Q q, W! A1 W3 l| MCASP_PIN_ACLKX
6 K7 ^. q% O( ] |1 L- @9 v6 P% N! [| MCASP_PIN_AHCLKX/ K& D" U2 m9 y% G, K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 B' g; l$ I) ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: d N; e4 d u! p1 T| MCASP_TX_CLKFAIL
% ~( C. p& J6 U2 [6 E a; e| MCASP_TX_SYNCERROR" i9 _% E/ L! A0 D4 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
K( {: F) f& Q" }2 B& U6 e; q| MCASP_RX_CLKFAIL' d# T$ u' d# t% F, C0 e; v
| MCASP_RX_SYNCERROR
0 t7 w- }! E3 P| MCASP_RX_OVERRUN);
f' _- k' S [0 ]8 H0 z/ W} static void I2SDataTxRxActivate(void)1 g. [0 T3 S K+ ^/ y5 Z
{
+ Y1 q+ H0 i7 S% K* C! o, q/* Start the clocks */
9 z$ L+ J6 I2 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' ~. ^( g z, r" X: d8 W# _: i, V& a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 g6 w: Q- r1 ]6 C5 e+ x) M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 T2 |8 `5 X. a' U0 B9 ~EDMA3_TRIG_MODE_EVENT);. Z9 U. f7 A; C- @: b1 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, H4 a6 K) T# E, v$ D
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 s/ [" k8 }& p. GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& h2 B) o4 p; n+ C# V+ L. m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: N6 k# Y5 E! I4 m2 {$ Z, {. |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% Z& b/ {" b+ ]7 \ H! G$ N+ ~ XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" \! R c' L @6 L C$ q! T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: W$ N8 M' ^% M
}
1 b, R8 m/ [9 r5 T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 x8 s; S" O4 T# H) y7 m0 `; V, W
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