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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 D1 e7 d) g0 P9 h! L6 [input mcasp_ahclkx,
" E# N n- S1 _8 m6 _+ c! n, }% a; Y$ finput mcasp_aclkx,. Q1 v$ W3 Q5 J4 A
input axr0,
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output mcasp_afsr,
2 D+ c( t5 F& routput mcasp_ahclkr,
; X# I" c: R. P1 W( @5 P1 zoutput mcasp_aclkr,) B; X) N8 S3 w
output axr1,6 \5 g; i% j" v3 t
assign mcasp_afsr = mcasp_afsx;- x. N" X" h0 `
assign mcasp_aclkr = mcasp_aclkx;
- R0 A0 W4 W! z# H5 Cassign mcasp_ahclkr = mcasp_ahclkx;
l4 ~, {. z6 ^assign axr1 = axr0;
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0 H+ V+ k* s; C' c7 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & F6 z4 a" T/ G% D/ s( q
static void McASPI2SConfigure(void)1 O j' O- H7 V' a: c
{
& [7 M5 a& L/ `( h' F$ o) T. O, CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ~' K- o" A5 ^! gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' K, a8 M/ p; P4 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' F0 ]. n" q; a) | L% wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. h9 T+ s& x) e6 X3 a1 F% \$ @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: d) Y9 _, A7 \8 b+ J5 d3 WMCASP_RX_MODE_DMA);
. q) S* ?: Z j4 k2 dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," T3 N7 ]: V8 x+ A% V; F. M7 x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 S7 M- k& f/ D+ `$ rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% T, }4 P! ^$ Q% ? D$ iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); d# r: P: p' j- i' j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * ~0 M4 b) O7 _+ w) O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 O$ w6 Z2 z8 t: uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 g0 A! v" a, ?5 E1 Z0 iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # @ J6 A# S w' U4 |( w3 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 y! J* {9 ` _( T& k0 p0x00, 0xFF); /* configure the clock for transmitter */
$ E' m. \2 B$ `7 g, u$ r* \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 L0 Q6 d- p; m) b; n. q# GMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , d- n" _& k" m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 T* T. t9 T- ~& U2 _. P
0x00, 0xFF);
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4 y I$ U: ]3 v1 |$ N/* Enable synchronization of RX and TX sections */ 1 K/ ?! J3 K5 Y; h$ g! ~/ I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, F2 }) }+ l1 W, p* m( o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 x- _4 B" V+ o) I, S# d1 t6 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- ?- P+ y! c1 e: l1 _) o V
** Set the serializers, Currently only one serializer is set as
8 n0 X q( V, R" x! C' P** transmitter and one serializer as receiver.* H' U1 B. e* n3 X
*/
9 Z7 R; \( \0 h' v/ x, Y' MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. N$ p7 l2 {0 F7 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
2 N2 F" ^8 n, @: b- h** Configure the McASP pins $ x* o( q V" m: n
** Input - Frame Sync, Clock and Serializer Rx
- l& t" n' j& h* _** Output - Serializer Tx is connected to the input of the codec
; C4 S! b& X9 M' D*/( I! v V+ }/ E. k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 s& \9 T; {5 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 D& j+ t1 N# \8 {3 R* ]# y- ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( n o2 S R7 D- [" e9 {/ H. u$ n$ @
| MCASP_PIN_ACLKX
) u8 K' G# Z( u| MCASP_PIN_AHCLKX$ v, h5 `6 a) Q; n9 E. b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 f/ O Q' e: g% rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ s0 Y3 J/ e+ F% Q! q/ j| MCASP_TX_CLKFAIL
- b' X% _0 n8 e! \+ u# M4 {6 \+ c| MCASP_TX_SYNCERROR8 N1 k6 `2 j [2 z0 ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & }2 _9 c% m, p% }
| MCASP_RX_CLKFAIL
" S5 L& x8 u( E. Q5 H| MCASP_RX_SYNCERROR
* `; ^/ b$ j. C| MCASP_RX_OVERRUN);
1 ~% r" `, ^0 C- B1 O% L6 Q} static void I2SDataTxRxActivate(void)
( P' X! w: l; ]2 Z; j# g{1 B9 X! ~% O& ?; Z0 A! E
/* Start the clocks */
9 ]1 \( Q+ X* \2 V% R, u6 Y: tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 X/ o3 f- j$ W9 h m* b' FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// h6 R9 S; t" f$ W' l; u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; H5 f6 Z4 C8 M5 Y ] I
EDMA3_TRIG_MODE_EVENT);
; r% ~. J/ {9 c/ W- a5 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 F( U& v8 U9 Z! `% q9 d- ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. [4 @0 l$ P) a% ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 u# B! h. L% x3 T$ n5 ?2 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ X! p5 P7 W/ D9 c4 \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' e! d; z$ p3 C1 O- u" A* KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ k) r0 x& E% x3 ?$ p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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& N2 B$ x. ~& G4 S, c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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