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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( @8 [% m9 {# n: _- \input mcasp_ahclkx,! f6 x! M2 ^% j
input mcasp_aclkx,6 q" ?7 J+ a$ y" ]9 g
input axr0,# I0 |' r! q! W9 g
5 `9 o+ M3 {- o% v. Q1 U( w0 woutput mcasp_afsr,
, {& N, k6 t3 p+ a. b, koutput mcasp_ahclkr,
9 {- J4 A Y; k: ioutput mcasp_aclkr,- M2 {2 f2 l6 {1 k( S
output axr1,
8 ~6 B6 D; Z4 f! {* }- C. m1 } assign mcasp_afsr = mcasp_afsx;
0 @% f: M+ i) R( x3 s! K8 tassign mcasp_aclkr = mcasp_aclkx;
9 K3 L4 T% ^* x) R6 fassign mcasp_ahclkr = mcasp_ahclkx;
% k* V1 ~& u I* o1 F, d1 L- Tassign axr1 = axr0; ' }- e* j% [$ H- ?0 L$ _+ D
+ `: \" i, S, P- Y+ W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! [# q' }/ p, T* \* \" n/ o# m3 U
static void McASPI2SConfigure(void)
0 z$ Z5 u, g% c N{
, o0 m2 w# K- K: }* u. |, ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ B, [/ C% [1 hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" d, j7 c& C' B D: x: s/ g3 \- gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 D$ m5 B7 r! I2 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; \* E; z2 ~3 m6 h XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 k) P# K2 c" W, h1 T! N
MCASP_RX_MODE_DMA);6 T4 j2 L9 G" M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Y3 R8 Q; {2 Y* L" f2 P; V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- b4 W0 X" w) \9 Q" M! E
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 p. J- e3 ^/ |5 p, UMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ g7 p$ r$ m' ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! P4 @3 z) z. M/ v+ ~# u+ f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! p5 a$ f4 d9 p5 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' U# d/ m" M3 k& ^% A- c8 o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 C' J3 B+ t& ?- C8 E' \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( [, S3 Q3 Z% K% J# L- n
0x00, 0xFF); /* configure the clock for transmitter */% |* V* H7 L' ]! M0 r7 L" a% ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 K! _; @! V2 n/ u" d- D5 Q- ]8 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 a/ A- A0 g' B* MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 F) w) @3 J- r0x00, 0xFF);8 w" I! U$ b7 }1 a% {1 v% S; T- b
9 E8 W8 i) L9 v# L
/* Enable synchronization of RX and TX sections */ 7 a" Q1 f6 [$ H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( A2 S# q6 A' Q. H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( n( T6 W& O& J4 O; u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; Q( R' M2 n0 }7 E0 n
** Set the serializers, Currently only one serializer is set as( @; e" n, i& h8 Y" n) b& x
** transmitter and one serializer as receiver.) _+ i7 z) ~- R+ E( j) z
*/
! `( H: r" u" E; {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. T. M5 H% N# I8 h0 o/ |" _* eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' M" [7 J8 q8 X( \: e7 K3 a** Configure the McASP pins + r& u4 l1 X, E7 h
** Input - Frame Sync, Clock and Serializer Rx: _* e3 n- N% X/ @6 f1 B% k
** Output - Serializer Tx is connected to the input of the codec
7 r: }' A0 ? @, p% ?*/
/ }; P& B0 g3 i. s" C$ I, x, @( tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) E0 W& c- N4 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* b( B: l; Y" K- [ \& eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 `! O0 A: R( t
| MCASP_PIN_ACLKX
( t6 O1 `) L7 k$ p# `& X| MCASP_PIN_AHCLKX7 J$ L4 g2 L* I/ Q7 ^9 {: i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- w% B# W% Z8 ~1 n! cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, N! P9 B( Y" x( ^| MCASP_TX_CLKFAIL $ g$ X: j1 r' S7 z( j0 \. `8 y) G6 I
| MCASP_TX_SYNCERROR
8 C& w& s! r2 p9 h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 ]6 M8 k# W# o# G1 K8 `4 i| MCASP_RX_CLKFAIL
+ P1 x4 i' [: j. p4 w& _+ }. || MCASP_RX_SYNCERROR
6 n3 m. A# ?6 U& _, h! ~, L| MCASP_RX_OVERRUN);
+ f" _" w6 J1 H; u5 p/ V7 r} static void I2SDataTxRxActivate(void)1 c8 U0 ]; P; ^; y
{. K1 z v- [+ x# J: g, ^/ D
/* Start the clocks */5 |+ A; C1 p, J2 z9 Y. A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# `3 N1 v9 y8 \' u8 K, w6 I4 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; y8 L7 K* O/ S: }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! g( y) S5 V' m5 r# S' B
EDMA3_TRIG_MODE_EVENT);
! \3 x0 T0 e u1 D# O5 ]9 AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 P" C& @4 ], [, AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 B# v& p, e5 ? g. G# c( z7 BMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 ? W. P& ]+ i1 q' V! o% F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" Q; p9 }% M$ Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 N+ B5 r( _, ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. d& t: k9 t" ~2 p3 WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; |3 @" Z5 t6 i} 2 o, T& j+ z3 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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