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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ r0 g8 K& o( N& ^
input mcasp_ahclkx,$ B$ w" g. l6 s/ }
input mcasp_aclkx,
* |* E/ L0 i3 o3 W7 kinput axr0,
% g7 }3 c0 x7 G' z- o0 w7 h* F# _4 x0 V1 H3 a+ u
output mcasp_afsr,
8 p" P& V: V% d- J' Routput mcasp_ahclkr,
: \* C* o1 x5 I9 x# M. V+ H( {1 youtput mcasp_aclkr,6 Y0 F/ [- O8 ]+ z7 M
output axr1,& D. v, h% x+ k3 }/ b# R( i' f
assign mcasp_afsr = mcasp_afsx;( d2 X6 K3 c- d4 T8 a9 ?
assign mcasp_aclkr = mcasp_aclkx;
5 u* B2 r. L; R# {+ Yassign mcasp_ahclkr = mcasp_ahclkx;
, y4 r4 I1 a" G3 Iassign axr1 = axr0;
# q5 q( L. K* B' V) M
. J5 ~# S% ]8 {0 Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' o# i' z* e4 f7 e$ B( @1 bstatic void McASPI2SConfigure(void)* G0 o5 {0 H% B) ^1 C
{
d4 K" S, q- B8 | nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* Z" \* I) Q4 J Y2 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 s# E7 U, E) p1 ^. yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 a1 {. I0 a' A# m7 `9 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 a- x: [' _. C' v7 l4 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 b6 E% |0 ~1 V" Q# W! a9 j4 V) C- {MCASP_RX_MODE_DMA);
2 M9 X) D5 M1 c l# u" _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) S! {+ N* \. T2 R: K. sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% M5 @+ N6 @7 k! h; ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. {& O1 w [7 fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 _ g5 l& p+ X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: T/ ?3 ~; q- Y1 mMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ \- N y% H% C: O& x% q8 b( E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
g! l0 U8 V9 W( v! sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' J( O' ~$ k+ [2 e" v4 J9 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 ~( z. i$ B4 o( s* |0 @1 ^0x00, 0xFF); /* configure the clock for transmitter */
5 w$ |, H r$ I8 }0 wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* H" W3 G4 h1 o9 ?6 A9 g! g, l- B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 J4 Z7 t$ i' N' K" s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: z' G# |$ q* K2 T& z
0x00, 0xFF);$ a8 a4 w4 l2 _/ n$ d, J
6 Y1 z& d# G4 q Y! y: u6 V3 r
/* Enable synchronization of RX and TX sections */
" V# ?/ J4 N: d0 O# XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 X$ P* i2 Q6 }, G) x" V/ o" `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ P R+ Q' |1 H- Y" D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 _& P" o" ~- n# z
** Set the serializers, Currently only one serializer is set as
" w, q. @( ^$ S7 o! k2 r** transmitter and one serializer as receiver.
T; j# Z4 T/ ]. F*/
3 W+ [; v1 G' J, hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. h$ ` K/ b F W9 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ ^ H; Z1 }" @& g. ]** Configure the McASP pins
5 C/ A* d5 F1 h( P- T3 H: S** Input - Frame Sync, Clock and Serializer Rx, ^/ S$ q; e8 \- K) f
** Output - Serializer Tx is connected to the input of the codec % S! n' R* h1 d4 q
*/
2 s1 P; ~( z \! RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) |: C9 ?* @$ Y( C6 U9 M# Q. `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 r9 r3 b+ L1 C/ n; f/ J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# D- g; S1 G7 ?& M: ]( R3 M9 v
| MCASP_PIN_ACLKX- o6 I" C" i0 g0 V+ g
| MCASP_PIN_AHCLKX, g% E: o1 n- M, c& U( r& ^+ g4 @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 ]- T. b/ N$ C# R. i( e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: D, }. I* f" m6 L2 Y% L |5 A| MCASP_TX_CLKFAIL
% ~" u0 z% E9 D; ?. ^| MCASP_TX_SYNCERROR1 s0 t: t/ W8 }& g# c+ I) V! G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; D2 G4 W0 L+ | ~" A) n3 b| MCASP_RX_CLKFAIL
" M0 _3 L$ c- |& u" k* U. R' G| MCASP_RX_SYNCERROR
% X8 D' v% v6 i) P! w7 P( || MCASP_RX_OVERRUN);: B0 o" Y- q- k: f7 B/ e
} static void I2SDataTxRxActivate(void)" y, u; S* s: a2 P! y
{
2 v1 L+ O9 b! B# I! [' `. g- q/* Start the clocks */- C/ E( }/ P1 F8 y6 p. N$ \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 o2 x' w B- dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' t' s) e* o) z) {# ?' _) _& J& b7 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- i0 N# P# T( f& D2 z2 mEDMA3_TRIG_MODE_EVENT);
" E( Y p& K: u' ^8 d2 I9 U" @1 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 B8 j! q0 G5 _: j. I% z& MEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! a1 M3 F# ^8 k2 q# _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); _8 G% r- f" r- X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 _1 i1 ~1 d. _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! D% a. j; u5 L8 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% E4 C# I. n2 o2 C, ]* H4 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: T5 Y- }6 E2 {5 H: s/ s
}
5 D# c" l" N1 Q! J7 z" |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . }% e7 Q$ [" Y6 J/ t7 N
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