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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- r' Y1 l1 @$ \/ J7 ginput mcasp_ahclkx,
% r' m. D; T. i& f) e* W8 yinput mcasp_aclkx,4 [$ Q2 N0 Y# F7 z5 D
input axr0,
! { h5 Q9 o# j- }
; f K4 U3 q' \- Z- @% xoutput mcasp_afsr,
7 e0 d! ?/ r% Houtput mcasp_ahclkr,
; D( H, F% @$ ]2 G) N: ?7 woutput mcasp_aclkr,1 q4 A q" x/ _$ Z9 U/ c
output axr1,
4 b: A1 I& @$ O6 g- R assign mcasp_afsr = mcasp_afsx;; M5 P( G% x3 G" H$ D4 j: W
assign mcasp_aclkr = mcasp_aclkx;: Q- O6 u, i2 @5 p. R1 J% S1 F
assign mcasp_ahclkr = mcasp_ahclkx;; g0 b- j* ^" Z( B- U/ W
assign axr1 = axr0;
# ~; S! L& M# x$ |% s0 F2 V% E
4 F, c" Y# T5 h+ M, j9 I4 B在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " @' P V0 G' i; k: b' i
static void McASPI2SConfigure(void)' @! ?+ p, @! T2 x0 N$ C% X8 A
{5 s# y7 i7 S( G- i% @) ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 h1 s# T/ H7 `3 p# _8 h/ P7 Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, v9 P6 g9 B+ A" }0 g- oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ Y5 P# p e- T! W7 q1 p! oMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 K( K& P. g! |0 F( o! EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 f( E0 { ?/ B, n( c rMCASP_RX_MODE_DMA);* C' _7 }$ ]% O2 v; [# m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; f, F) m- M6 o# h; M( p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 W3 W5 X% B9 L/ _1 d+ O x8 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 W7 G6 u' V, ^, `$ FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# q7 f9 |: J- _! S9 p0 k; J: q9 `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 S1 X* r: Q; l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- ~8 ]9 ] D4 g4 z& X! Y7 X RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& Y3 b& h, B1 K1 r8 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 {8 Q" j, z5 U) AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( x9 a$ _" `4 V0x00, 0xFF); /* configure the clock for transmitter */
' k3 z1 d" q' VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 d" P- g2 r8 Y. yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' e5 i6 b% _ G5 M# @/ M# p) A9 H" FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 e8 d+ A6 t" t
0x00, 0xFF);2 J3 l* m6 W# @# a( t
& c! [" l$ R s8 b/* Enable synchronization of RX and TX sections */
- ^& \- W3 X# Z, s4 i- ^4 [, J; yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. c6 a3 r2 t3 u4 r( r; `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' i9 U1 D5 K; e, r) ?. ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 S9 q# }4 P' O8 n; D
** Set the serializers, Currently only one serializer is set as
+ L4 Y5 Z& y5 K0 n. ~5 H$ x** transmitter and one serializer as receiver.) i1 `: u. ^1 A/ o' o
*/
2 {- D8 F: y& zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' L; K6 ~% b) B( m0 q# r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ y* k! B4 d- O, a( ], t+ ^1 B8 ?, N
** Configure the McASP pins 8 L- m8 D z! I/ Q* `( Y
** Input - Frame Sync, Clock and Serializer Rx& G/ P, V; ? y
** Output - Serializer Tx is connected to the input of the codec , [+ O% s! H8 L
*/6 |8 b9 k# o) o' R: j: x! Q! v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' M6 d; _( b) U6 \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
S6 b( W8 `6 w* _& d; @* `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 ]" L" [7 ~9 ~$ T) a2 y| MCASP_PIN_ACLKX4 l# ]' d3 B5 s+ j
| MCASP_PIN_AHCLKX
1 h9 J% S) V! X$ }" H1 E0 e$ || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' M0 ~) \5 }* M" k7 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 {# [+ T) X5 u
| MCASP_TX_CLKFAIL 6 \1 v y, z3 C7 @
| MCASP_TX_SYNCERROR+ ?4 {$ B% X" B$ t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + \% ]2 ]# r8 d% N3 ?9 |
| MCASP_RX_CLKFAIL
; o( Z! A. ^: E| MCASP_RX_SYNCERROR
/ z5 n% L' j& R| MCASP_RX_OVERRUN);
* M5 ~5 Q" j! A+ ~# I7 x: O7 p} static void I2SDataTxRxActivate(void)2 n& a! G' `6 K+ o
{8 o! O. J7 _2 x( T
/* Start the clocks */3 c" o0 q! _. C, O' R, K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. o0 m' |5 |, F I- T! Q& G) W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# c8 h2 |" }: hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& P3 c* M7 J1 CEDMA3_TRIG_MODE_EVENT);# V# v) a1 P$ J+ {$ D+ S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! T }, T# F5 E4 n- mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. ~ H4 g& x# G! _8 V9 V" IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ \, {: O; N3 A, RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 {8 R' |& ]! Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: s4 g$ ^' `4 H S5 h/ C' D7 s w J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 o4 }* G# m9 C9 H& \; M* z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; R8 e. F, d7 f6 S. |}
% k! Q- T, h* F5 K. l, X1 O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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