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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 f3 D& N" b" x8 S; [" Vinput mcasp_ahclkx,
+ K* O$ ^2 }" J6 @: \input mcasp_aclkx,
; z$ _. n2 g9 B8 Yinput axr0,! f) N; X. O2 G
0 Z: K: Q1 o% \3 [output mcasp_afsr,& |4 C( S; Q% `" j
output mcasp_ahclkr,
% P( z. z, f- u- H" \$ J7 Z0 @- _; I) boutput mcasp_aclkr,+ g5 i7 d. E; f1 P5 a: o* w
output axr1,' r) ?# m/ Q( M) V5 p X
assign mcasp_afsr = mcasp_afsx;. J$ B) B( R+ K7 x* Q* c/ E
assign mcasp_aclkr = mcasp_aclkx;
8 C# r8 f' Z: Z) x# ~' [assign mcasp_ahclkr = mcasp_ahclkx;: b. O0 o" u+ S
assign axr1 = axr0; ! x( H3 }8 R% M7 Y/ `6 L. E3 M
& h* @; j+ ^2 {) d" K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 p, j2 ~# Q! d2 R* Estatic void McASPI2SConfigure(void)
& h( i" `( b# \; D1 f. [{
4 W8 r2 x9 A" N& jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 |$ A( g4 J5 a! U# i) J- W% _4 u/ jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ |; w% L% j2 v: D% x& Y: h1 gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); X' }" S% K7 E! m! T5 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( `1 Y( K! T* a+ O8 U# L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 z6 s# T/ `' @3 Q
MCASP_RX_MODE_DMA);6 H! J. z/ Z/ K. a* _; L f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* t+ K7 d8 D: ?4 H0 j& [ ^ T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& f( J. G4 Q6 n5 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 [/ o" S: L& U5 e. |, vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ T0 f* V: j e4 [5 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 e6 i7 l; l+ I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 M: D/ l4 Z4 B" v' r8 g2 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( }! H: W! A% i2 x- `' l7 U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # |/ T' K5 M6 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," b, ~/ z$ b% g: e9 z( l
0x00, 0xFF); /* configure the clock for transmitter */
- Z( F8 F& C6 N3 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, ?# F4 E h2 N; K2 Z- J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 T( d2 ?% m! X+ p6 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 M- z9 U5 T% H$ w m+ i
0x00, 0xFF);
1 C( B1 f% {9 Y) A/ M( H
1 r7 N7 g, z( ^2 N- c/* Enable synchronization of RX and TX sections */ 5 y. ]0 l3 o. Y9 T2 ~2 J1 M
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 T0 y$ b3 h6 d; S/ I( m/ D" P* I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* G: w# v# M- D: bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 z A1 b" w6 a; d" M5 ?; B** Set the serializers, Currently only one serializer is set as" t4 U3 q0 j* c6 H( ]
** transmitter and one serializer as receiver.
5 n7 G! h W+ o' @5 c: j! V: [3 L*/7 k( {& w9 T. A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 c8 @6 `" P( k& m6 ^ q" b0 y5 K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# U1 q& n' M; M% M; W3 g** Configure the McASP pins ! N$ @6 U+ ]$ |: ~7 v1 _2 f
** Input - Frame Sync, Clock and Serializer Rx
+ Q+ N: u2 q% l# {** Output - Serializer Tx is connected to the input of the codec
+ ?! d7 v; r+ _6 @, F% _3 q; O*/. B, t7 {3 g* ?& q1 u( G) Q% \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. \# {; o7 x" F, r6 s3 }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" N0 L4 D( Q* P7 t5 Y9 c) i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ }- ~9 l$ D# K) r. u3 v, U
| MCASP_PIN_ACLKX
- w" I8 V& e! i9 }| MCASP_PIN_AHCLKX
6 r% J9 o' b& q; Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ]! k6 _( K# m1 @7 `( oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ k3 H) `9 `( n7 _8 R+ M$ V* Q
| MCASP_TX_CLKFAIL
" C7 Y; } @- b J6 l1 A8 Z" M| MCASP_TX_SYNCERROR9 |$ \) C/ k# @( o! @% {
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- h7 H9 O5 }, {9 W! `| MCASP_RX_CLKFAIL
1 d ]3 T6 t' F3 G; |- k/ \3 J: R, x| MCASP_RX_SYNCERROR $ |3 ]! u, z1 n' T) g
| MCASP_RX_OVERRUN);
3 D) V- o5 s) Y$ w7 f, y$ C6 q} static void I2SDataTxRxActivate(void)
6 K+ Y- J0 f& z+ I{2 v$ c' }, {/ _
/* Start the clocks */
) v, j6 y' q9 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( |5 N5 E- }) m4 L- E( M: T {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( `& |, d+ s' u, S1 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& ^8 ~% N; a2 s! D) ?
EDMA3_TRIG_MODE_EVENT);
+ c2 X) D& q# REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 l+ v- M# @! b, {" u, c) O1 |% |" N' y' j8 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. o% u- K9 o6 f8 K2 @" T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 c" V6 {2 K) Q# V5 C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 g* K. E% `9 y/ H3 W) b. \ H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, z& R( S, }" kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); L: W5 D% ~% b; \# p" x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ @/ p+ F* h3 t9 [
} / ~6 C3 B, Z) B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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