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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! e5 O* h ~' x( g7 Z3 h9 D$ binput mcasp_ahclkx,
% T1 C) ~* X$ A1 r$ }input mcasp_aclkx," ~# M9 p9 @7 [2 @/ c
input axr0,! L$ l0 d& }8 X3 O
- t, J0 f2 e& B4 z+ }+ a8 soutput mcasp_afsr,
# C* o" \9 e# a; K5 w. ooutput mcasp_ahclkr,0 c3 k! T! O9 t& y* M( {
output mcasp_aclkr," ?. ^- S, j9 _8 T
output axr1,0 g% E& R3 a# b
assign mcasp_afsr = mcasp_afsx;) ?- A9 |" e+ a* H( \5 M; G. w
assign mcasp_aclkr = mcasp_aclkx;
" l% S$ Q- o0 _ u0 |2 cassign mcasp_ahclkr = mcasp_ahclkx;
: y ]2 K8 q# F2 z# R- Lassign axr1 = axr0; & t6 j3 E' J' ?( X" I h
7 m. x6 f) ^8 u8 r! r, a5 l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: s: z: Y/ b5 [! m: R5 m3 L3 ]static void McASPI2SConfigure(void)
4 a* B$ [8 F, q1 }{
8 k: J% ~! y* u9 k' l# \% @9 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ |5 k( p* X1 x! m9 T& aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' u, Z0 N$ V1 A9 N! `$ W8 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ n8 r9 a6 O3 I5 l8 f. C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' S) R) P) A) r, Z' h4 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: {( T* ~5 d8 q; }MCASP_RX_MODE_DMA); ], I5 E0 c2 b/ z# F/ E! L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ w8 t( v3 @" g, z% V6 a8 o4 jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* v$ |( [9 R& y$ Q* K7 w$ gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ r5 s4 i. v+ N
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 j \% M+ h. L6 s3 Z6 U" Z8 FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % ~ s w& G. Q- i8 `$ r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: L8 I4 y& C. |/ h! b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: x$ R# y, C& G* A1 k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 @# X* P$ ]7 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; K! ^; P& `" U- [) F0x00, 0xFF); /* configure the clock for transmitter */
! [! ~1 ^2 _5 w$ ]7 ]# gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
Z6 j6 W1 P: w2 L$ [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 t3 ~% u8 b: Q" y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ d& w- ]0 m* i/ r9 P0x00, 0xFF);
) j& V2 E: M1 ~( o6 c& g3 _# O2 W% S! t
/* Enable synchronization of RX and TX sections */ $ g# B! _: n# _- k! H, ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ Q. S/ W3 r9 Y. ~; p) @7 g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 P% I$ S+ Z+ F/ v% S, h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: P2 P5 Y4 q; F6 r+ w/ t4 X$ ~1 |
** Set the serializers, Currently only one serializer is set as
3 K& ?' G Z; ^& d f** transmitter and one serializer as receiver.
4 I4 r! J3 q7 g3 t8 m# S+ Y*/) \5 f* d' [- x8 O7 I' V/ H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ h- D/ ^1 G+ G6 n" _9 x- u) KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* U( k* N/ O2 i; A N# ~8 f. K** Configure the McASP pins i; P# {& [# `" O/ m1 i
** Input - Frame Sync, Clock and Serializer Rx
5 I2 k( E' I! w) y& U** Output - Serializer Tx is connected to the input of the codec # G6 P! Z$ g/ T. C! q# g x
*/
1 _: C8 m1 F+ b5 P* r2 C6 C" @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; k6 y1 M; f: _. fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( n* [; E3 m: w5 T4 s$ @( a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: l" W/ \$ n h/ Z
| MCASP_PIN_ACLKX
" j9 u4 o+ u$ P5 e6 |0 H| MCASP_PIN_AHCLKX
- ^! t P) ^2 [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 C5 S) v5 ]! P. F* XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) ^! a$ S7 L% w1 ~. R' k% ~( z
| MCASP_TX_CLKFAIL " q8 S7 P/ C; e2 S0 t
| MCASP_TX_SYNCERROR
8 S+ p0 L/ l' X8 l* Z, j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% X m0 K/ a, J$ h0 K| MCASP_RX_CLKFAIL
- s! \8 S; m4 }5 v% R3 ^, N6 \| MCASP_RX_SYNCERROR " ]' A; F- i v# S e+ i
| MCASP_RX_OVERRUN);
' P( r0 G6 H& k" e2 k} static void I2SDataTxRxActivate(void)
* w0 _& q2 `4 S2 m{9 d. ]+ i$ J5 i: f+ `+ e
/* Start the clocks */
8 J/ r; j1 D: X- h; e% `3 b* gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- I. r5 E$ Y9 U: r, c% a; IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
C; X7 D4 U4 X9 ~4 {3 i. eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 w/ {7 C. ^/ Q) v
EDMA3_TRIG_MODE_EVENT);
( c( _5 `2 r: nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% ]* B3 E7 J4 u6 H& [, ?! ZEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 C( n9 {/ \) W* a Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 F( t! I) ?- P/ S( x8 h1 R+ b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% e5 i! |7 A1 i5 \) S# f$ Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# {; T7 A2 W8 v2 k, iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ R& D: f! t6 M$ X" J; H( K6 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ P# n ~. b+ \# N* y1 E" S3 j
} # t: g' @6 J5 B. z% K2 j' q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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