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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, I5 r5 t8 T, s1 U0 j q' W
input mcasp_ahclkx,6 J# d7 J ^: b- n, V; X
input mcasp_aclkx,
& K9 B+ q X& B# o) uinput axr0,/ r/ q* M2 j7 j
k6 I# i) _& e4 w: q. `: j
output mcasp_afsr,
$ I$ G% C3 Q) e8 J' ?& aoutput mcasp_ahclkr,
9 j( a% R" G( W) X: Coutput mcasp_aclkr,3 G) ]' B! M+ E" w+ U4 c; J; o
output axr1,
" a/ j" D d* | assign mcasp_afsr = mcasp_afsx;
8 s5 @8 Z- ?6 Y; rassign mcasp_aclkr = mcasp_aclkx;4 a- }! O& Y) W- N+ o8 n) d
assign mcasp_ahclkr = mcasp_ahclkx;
$ ^9 F8 q# z3 F: p# m, `assign axr1 = axr0;
0 T; u" s3 @6 g- n# V0 ]4 G0 X! R9 Z6 z- F, D' _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: C& U+ H2 }! _5 F7 l6 lstatic void McASPI2SConfigure(void)
4 s m/ b' {+ ~; n7 k( c" J{
( ~0 U t: G6 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; t) B2 J5 {0 J, f- `( ~" tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ J& d& ?6 H/ cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 q% p1 f) T+ b/ M: h" H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, f+ y0 V0 B& v8 ^8 dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 |( ]( I* r u1 s, C3 Z2 q
MCASP_RX_MODE_DMA);8 r7 {/ V; P' e6 o' d. I; R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) h5 j* @: c3 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 j2 r5 \; B3 U8 [& M& A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 r* Y' P* g: T0 b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ P1 D- L" U% `, R6 Q, qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * Y$ N- E- G' c/ s3 a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 ]2 c& b1 c& c4 K. Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 A5 \- q2 c) ~5 D, I6 N( z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- k( K" N6 N, Y- ]. MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 Q2 b: \2 R9 ?5 r; Z' m
0x00, 0xFF); /* configure the clock for transmitter */
" N O$ K1 n" d( k. qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 \% c, c4 l* [4 R. u1 @4 d4 f y$ ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 B" G( k. m9 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. a8 k0 C, p. [0x00, 0xFF);
& ^5 i' v1 `& R( z9 c! c* T* J Z- i8 }! ^, h# e1 V* f
/* Enable synchronization of RX and TX sections */ 3 z# B* K+ o( l0 o6 I) n% v8 s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 s! x/ g& p; u
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% u1 t3 H. I3 H; ?' o7 h3 Y1 sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 J- S8 b. f7 S! F- E4 l. K** Set the serializers, Currently only one serializer is set as
. u! k* P' p) H; G5 G% Z1 z** transmitter and one serializer as receiver.
{" ?8 V4 z6 E*/. ~, s; P4 P$ n+ O' F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ L n! O6 C; {& s
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& B5 M8 P. X: t2 D: ?1 ?1 n0 y: G) L** Configure the McASP pins
$ _4 ^4 _) E' x5 T** Input - Frame Sync, Clock and Serializer Rx" ~( L0 o z- `0 I8 Y* t( _
** Output - Serializer Tx is connected to the input of the codec
9 L A: S8 e ]" U*/8 Q0 l6 s0 D: T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 P5 y( B% [9 B1 Y5 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: ~. ]) q5 X. ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# B) {' o( I/ ` j% M* k
| MCASP_PIN_ACLKX( h# B9 ` _9 n8 `4 X
| MCASP_PIN_AHCLKX4 R1 d3 V# @; ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 i: H- Y5 D/ M* C/ M4 w- N: U: ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR U& i/ a5 u4 f, W, |
| MCASP_TX_CLKFAIL
' c" d* l. l, Y| MCASP_TX_SYNCERROR: [0 C/ Y0 o2 C9 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) y( u: B8 r- h0 S0 V5 {0 M- `| MCASP_RX_CLKFAIL4 Y% C: N0 e, }2 q
| MCASP_RX_SYNCERROR
# o/ ~- E0 D: \) k) T| MCASP_RX_OVERRUN);' v1 `9 i+ ]( w7 H
} static void I2SDataTxRxActivate(void)
( F8 s' B0 x4 H2 o; W{
. d/ Y* b+ u9 V; M- d/* Start the clocks */
% P% D, m+ k% V0 M0 ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 l' D9 b9 q9 e0 m- ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' N* F; U* K) @6 l2 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& ]+ Z6 ?9 K- ^, h0 g* bEDMA3_TRIG_MODE_EVENT);
6 }8 h- B. @9 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " z) k1 j; W9 l8 u* _0 I4 A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. A0 ^/ q" H6 F& J N r* U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
9 C# k0 ~( |3 A: iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: x$ \4 ~& r* U$ K! w5 g) p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 {* g6 t9 y1 _) V: X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 u* c5 m9 c d- qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" t6 W& s9 D. X2 l, r}
( i6 b" C" G1 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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