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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' F/ H2 q. ~* [5 K% sinput mcasp_ahclkx, J! l, U; d2 ~3 \
input mcasp_aclkx,- d: Z. v3 T( f% A z: C( j
input axr0,
$ K8 D; s+ z B2 e& u
# ]$ J q8 r6 G% u7 \8 p# \4 F" Poutput mcasp_afsr,/ Y2 {- R. m' G( |5 [
output mcasp_ahclkr,9 d! A, x# @6 w6 o
output mcasp_aclkr,5 }0 B7 y8 {, M% _4 K* r0 X
output axr1,
" E W2 ]4 u4 G, f8 k* R assign mcasp_afsr = mcasp_afsx;$ M M4 M8 {% k3 |+ R' k5 B+ ]
assign mcasp_aclkr = mcasp_aclkx;
5 D2 L! D8 Y; R- q. G% S0 w/ ]assign mcasp_ahclkr = mcasp_ahclkx;% D$ u, F" M. u1 O* i: U9 u& y
assign axr1 = axr0; % X" D* U7 u6 d" e8 t* O
5 Y( o/ R% W3 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * L3 F8 T9 G0 x/ \: P7 r5 d- i
static void McASPI2SConfigure(void)
" c( f' |. J2 O& c; b& O{+ V; O g8 w) _' j2 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. J0 U( f. M4 Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) }# M# z# S8 P1 \4 }& vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 a& e0 Z$ r8 p" Y7 w5 m$ fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 G/ H2 A6 ^$ R4 n) u$ l- ~7 A: b; l6 \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 G9 l% O; i, G' G
MCASP_RX_MODE_DMA);) c8 ^- O! w4 g" m: R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 B: Q0 I# r0 |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: j2 Y; B/ i. M+ u" q; g( k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# ^9 k2 X/ B% L- H) vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 ]7 l" ?9 y. Z% e. W% J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, A3 T+ D2 b& z2 ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' Q3 @: @5 i+ o# T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. R n- O2 G) X4 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 [9 N9 p- m8 {: | N" AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# W6 _% `) c2 O8 E0x00, 0xFF); /* configure the clock for transmitter */
7 V: n8 f* O8 V. j2 w1 U; _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 d, g; n3 ?# o; tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : G& ?2 f S _/ `1 [( `. F7 d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( x. M" @( w: s5 w
0x00, 0xFF);
* C2 @% t, V9 V5 E8 ~2 |0 E
6 z3 R. S9 v, F h0 ~- F/* Enable synchronization of RX and TX sections */
5 y3 m" \4 P8 |2 [" m0 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 A; U& e- G6 C8 G7 X- xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 R& i# g* n4 W2 M1 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( ?- ^) a9 Q4 p. O/ O( s, n! J; J/ C** Set the serializers, Currently only one serializer is set as
3 W+ R4 ?% C' w7 p** transmitter and one serializer as receiver.
2 p) H2 P! e$ N% {8 ^6 H*/
. F8 d- m) h; ?, O) xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" x; i! N4 o# i3 ~# A( O( ~) d; Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 o t: o4 _0 w: R** Configure the McASP pins
7 u4 F: A4 F% ?9 I** Input - Frame Sync, Clock and Serializer Rx) V! {$ F- J( y# B4 d9 u
** Output - Serializer Tx is connected to the input of the codec
$ x- t% k% x, r* W' v) G1 S$ [*/+ I4 f/ W8 i$ d. A$ Z; Y! H/ `: ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# z* S; D7 o( }) M$ pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* p& d% p4 N: |" J# mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 W8 O' x1 {7 t, L
| MCASP_PIN_ACLKX
. x* |* v, |! p( B5 o| MCASP_PIN_AHCLKX
0 i! Z) X6 A; q. x+ K, j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 E6 W- Z6 {; w+ q6 S6 a( M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 N4 y0 k8 c" x6 f: b4 l, K| MCASP_TX_CLKFAIL
4 D5 _2 V9 a" G' v$ D0 V7 E' `| MCASP_TX_SYNCERROR
. A0 S. y+ r' g$ D, k! C/ a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 f; |! U: Y0 j1 b9 I| MCASP_RX_CLKFAIL+ F0 M7 ~6 H) M% ^0 a' e4 ?: U
| MCASP_RX_SYNCERROR
+ j+ Z: H5 Y; H* U7 q* M! N| MCASP_RX_OVERRUN);
( [& m0 l1 b( O+ M, ]' S$ q; d2 d} static void I2SDataTxRxActivate(void)
, d! _" _$ ^! \3 {3 _. x% x" S{
% g$ A& X8 n9 q/* Start the clocks */
% G Y: i: S# e+ d" y& }$ wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 w8 f" K, U1 m& b% g K8 vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 I! J3 q! M) N) i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 Z2 a' H% e8 c" u# N L& nEDMA3_TRIG_MODE_EVENT);
* x4 P: \! {, U0 P: z& V, E, z9 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, ~5 Y8 F- A! }( t4 @7 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; A8 h- P% M7 g" T) v% h) lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, }* D' y' P0 g$ N9 o( y% h# b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! @2 @9 \( T5 S( u4 o' u, T6 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& @- A7 {/ h/ ^6 _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% c% h# `+ Z `# N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- V9 o) ^: m) s
} , k7 o/ { V9 m5 N8 {3 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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