MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

output mcasp_afsr,
; M& n9 J! W" A3 t- {% I1 t4 \0 \output mcasp_ahclkr,
  c2 `$ i. f* y7 d3 D9 g6 {3 v/ xoutput mcasp_aclkr,
  m9 ^1 o' r: g( \: }8 C- {output axr1,

assign mcasp_afsr = mcasp_afsx;
$ F0 Q* H' C! ?6 n/ k* }. kassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
  v- I5 `; M" _; X9 h" _/ M/ G) \& Gassign axr1 = axr0;

: y. G) m" [% m, T2 J  @

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

3 T4 t" ~8 `. K0 d* e! T. m

static void McASPI2SConfigure(void)
/ q  f# G4 u$ _9 w{
( S6 O6 _0 t* t1 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
" E$ Q2 ~) S, [, h6 y' _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" K1 f2 z& I8 ]" `" i- V0 D/ HMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 ^9 z8 r1 F: a( b- F) c$ zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
+ L3 P: n' m3 |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 X, \* K5 X1 P2 `5 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ T5 a. j+ G' N, ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: Z# s- o1 G2 K0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 B5 {1 R: @- V: w5 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: k4 u. N' o8 ?( s8 O0x00, 0xFF);
* t4 }: t  `5 l3 G
/* Enable synchronization of RX and TX sections */
5 g+ N$ C% ?* aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
% Q  I+ Y4 z) E, Y& jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 Y7 y2 ?- m; w9 CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
: r' _& w1 s" ]+ a% E% j*/
3 V4 C7 u# y0 K0 m& rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 ]- w: I1 o" E2 O0 O: hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
% v+ Q' w7 j5 D  w" c/ _- n** Configure the McASP pins
) Q# v. S2 z* F** Input - Frame Sync, Clock and Serializer Rx
8 u5 M* y5 k+ C! }** Output - Serializer Tx is connected to the input of the codec
*/
0 [8 V& g2 l. ^4 S0 W0 Y- T3 Q9 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
3 ^4 q* B! r: M* d0 B| MCASP_PIN_AHCLKX
% z9 q# O9 T* D' ~4 `  J! H2 N| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ e6 Z) D0 c6 W8 V7 S| MCASP_TX_CLKFAIL
4 T/ Z1 e2 l- W. E, h6 b' Y| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
$ e" |0 k: K9 K+ f" A8 V| MCASP_RX_SYNCERROR
' H/ J1 `# F/ q' q. M8 @4 T% g; P| MCASP_RX_OVERRUN);
1 z6 f4 G: x' W4 X) s; f3 p2 e! ]2 M}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
8 T2 j3 X4 N" I& X1 _) gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) j7 T5 a, O* o3 i$ h+ w( p" ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
- h6 ?, ?  c6 O" F0 S# {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ v3 e% {( |; a6 F" y" zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
% W. J: S# J6 u. c6 h( Q4 s$ jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
' ?. h. G6 ?1 q/ N* mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 [' G& t% [9 l3 Y3 |' ]+ p# N}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.