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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% Q0 L5 r6 V W' T! J3 I
input mcasp_ahclkx,
2 Q. g4 k- h: K! f1 n+ O2 G0 J$ ninput mcasp_aclkx,
9 s% j- h( }9 g. i7 ^$ \9 rinput axr0,/ u& {& Y( p+ }3 x, |% @
, q3 E3 u- d& h, D( Houtput mcasp_afsr,, B, A% J# v( j, h8 ~( [7 R
output mcasp_ahclkr,! G2 A% u5 q$ d+ {; k
output mcasp_aclkr,& \4 X) O% t3 V1 y& H: }( E- n3 T6 d
output axr1,3 V5 `" t0 z1 @8 M
assign mcasp_afsr = mcasp_afsx;
& i$ }1 T" x+ d+ [assign mcasp_aclkr = mcasp_aclkx;, N1 D! C+ J+ q
assign mcasp_ahclkr = mcasp_ahclkx;( U g" ~- e' k# X. r1 V
assign axr1 = axr0; 9 ^6 B& ~* T; \& _
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 g4 v' Y8 E* U0 n0 J. {
static void McASPI2SConfigure(void)4 ~. B# p/ k' {' h
{0 e' L0 i' e' P
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# D5 V% z3 f& T' r6 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 I8 ]) Q/ n' P. U' q( S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& S$ s7 K D( i8 J) q0 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 w1 S; W* ?+ M( _: ]( B/ J0 `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 ?& N/ T3 \% U" J! X$ n
MCASP_RX_MODE_DMA);# O5 o" h: q$ i @: q9 I6 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! f6 @+ F) q7 }: l3 \$ O( [0 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* X: n& g# }$ q7 Y, y# u) C: HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( V% a2 {# }; O4 T6 i; W. j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 G% n0 B2 {- G, e1 w) J+ }& Y( R3 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 F( J# d# m8 e2 S$ e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 A) P% q1 ]/ V
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- l; Q6 o7 g4 B- h4 vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 y/ w3 P) c$ |, X9 `! y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( f. u( n" D! |0x00, 0xFF); /* configure the clock for transmitter */
. M( I& P6 n: \4 ~! cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& V7 t' b7 T2 x" tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # c. W7 I, n) x/ N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! a5 c4 {+ ~; ]0 j) i9 p
0x00, 0xFF);
5 h+ u/ A L2 z0 h0 H( v; R z' F! M/ u- I6 m' @
/* Enable synchronization of RX and TX sections */ % Y7 V. f; N, X! p1 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* m. } R& y( p! l: g! S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& r3 Q6 l9 ~0 X' M) T7 R3 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** V5 f2 ]4 g4 S* R8 F* i4 T( m
** Set the serializers, Currently only one serializer is set as
6 N. P# m6 S. V& }$ L6 Y1 |** transmitter and one serializer as receiver.
/ b# x: Q1 @" T4 s# [' _' q0 X3 E*/+ Z9 x+ d1 k' _+ o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# t4 F- n( X6 }# O, _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 {* D3 h: _" |/ I9 T5 X2 C" u" H
** Configure the McASP pins
" W' u( o# H' E W' B5 M3 ^; N4 D** Input - Frame Sync, Clock and Serializer Rx
+ ^8 N% n8 E0 |, v. D7 c! o9 X; I** Output - Serializer Tx is connected to the input of the codec
' y3 g8 c3 R5 e: o*/3 f3 o8 [# [) I% z5 e2 M5 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& |+ ]3 h9 y! F1 e0 I3 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! m2 g$ @ |" F: _2 Z) i7 z) V) LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! n( q4 ^$ M, X P5 M4 H
| MCASP_PIN_ACLKX1 f/ Y* ^% @3 W5 b9 c2 u
| MCASP_PIN_AHCLKX
+ p& W m, h" z3 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) H- u5 y) q) G+ z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 V: t3 h0 {# [$ p| MCASP_TX_CLKFAIL
* u8 N6 }* G. }$ _3 I0 S| MCASP_TX_SYNCERROR2 Y6 r( l5 z8 m% e7 m2 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ o/ X/ _6 Q0 \: ?, C2 V& z
| MCASP_RX_CLKFAIL
( \5 I6 [9 P( X% o$ _% ^| MCASP_RX_SYNCERROR . n, @9 g" l4 O& i$ j* B& f$ W
| MCASP_RX_OVERRUN);
# t t4 s. `; V, @ b} static void I2SDataTxRxActivate(void)% M- @% n! m% z* s& k4 p% \; M, Y
{
" j; M0 O# i7 `! W! F/* Start the clocks */
7 S9 P9 N+ K WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% \( @* c5 G! I& pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- N+ r% m# B! REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; c U2 u2 Y9 z( d& n u
EDMA3_TRIG_MODE_EVENT);- \0 a1 [% K: }" }6 z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! i9 F1 U, D* d& B; s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) v. }7 r( h' V1 _" VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ B/ W% O9 N2 k1 L fMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ `4 K" E4 z! i: o; O& ^1 P0 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// Z8 E7 ?% j {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, \' f5 L6 ]7 ?. L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ~ g/ Q- w6 d+ |
} / @/ u O: J2 k9 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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