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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 j7 P: X" T2 ~input mcasp_ahclkx,
+ q* d& `% b$ H4 ^9 Hinput mcasp_aclkx,
" @% @5 f2 j# A, J, [input axr0,
! b; S# U* Z/ I( e/ p
2 N& m% d: P$ [3 }$ Goutput mcasp_afsr,
, Y, U* f" {2 | [output mcasp_ahclkr, N' P( d1 q: u
output mcasp_aclkr,' _4 {" a4 y4 U% C+ s& Z* f' P- j
output axr1,) s+ |6 {& s1 ~! d; e" P8 B
assign mcasp_afsr = mcasp_afsx;9 H0 }' c8 c! q+ u& v9 N7 P
assign mcasp_aclkr = mcasp_aclkx;/ W4 E3 b: I. d5 u! R' S
assign mcasp_ahclkr = mcasp_ahclkx;
7 @" g! z% l% X5 q8 V5 r' Dassign axr1 = axr0; 4 G# `" F* H X0 a+ m6 s7 e; J
6 R3 }$ R, T0 J. ~! u- Y ?" s在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) ?5 o( z) |4 N- ]$ a, w `/ Sstatic void McASPI2SConfigure(void)
& ?( l; n6 \+ V0 j{; [" }: }' C+ Y' w# m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ b. o0 j7 |2 u6 N C, |1 R2 KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; N0 U3 B8 K/ v( P G4 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: P) t) A. I6 i/ p% D! Y rMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 l# I1 G0 i/ J, d2 XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ T1 M1 Z. O& h8 e+ x, b
MCASP_RX_MODE_DMA);* R7 o5 R; R, }! U+ q! ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 u2 [' J/ t0 A- m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 L$ O$ a( [& c. X! t7 s$ j
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' j9 p# y1 g* [4 Z6 K/ ?$ j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' E- ?$ C+ N) Y" ~ `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : K- \3 [) t# O6 c+ j7 W v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( r+ J ?9 v8 u2 B1 C4 d$ [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 L7 s6 x8 o( [ w2 [0 IMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 N) |. V0 k) _# LMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' X3 Q% w4 d0 U5 Q+ k0x00, 0xFF); /* configure the clock for transmitter */( A; T* U# q! `- V& g* F% a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ]8 N' R4 ~3 p0 H6 {* S- S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 e3 \% w$ y- ~, U9 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 G6 _. C, e1 m* i$ k* y& t
0x00, 0xFF);3 w9 y& u/ d' [& a# @" x
& Y2 l$ P5 F. x* a# L/* Enable synchronization of RX and TX sections */
a5 k1 ?4 m! S/ m+ }$ H1 xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 X& }: Y. G! E# t* I$ h' @# Z, w& GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ P( l/ F- X- d) x0 E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- R- `& A4 ^& G( Z# W8 D
** Set the serializers, Currently only one serializer is set as
& r/ c, j% ?& _0 S** transmitter and one serializer as receiver.+ L. l( Q% @1 X$ g2 N U; l
*/
4 b, Z. E- d$ `: _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& H+ O, n; D# ?6 @
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 _7 G4 s" o( l' _/ S9 m9 y** Configure the McASP pins
D0 s Z8 F# R* ^5 G. k4 W** Input - Frame Sync, Clock and Serializer Rx
1 D" `: h6 u( [; I5 v** Output - Serializer Tx is connected to the input of the codec : X% ]9 S( K3 \) E
*/
/ w [: q: h' X! O. S1 iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 w- N6 ]- n% D7 \; EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% B! q( @- C0 Z- k' i- K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ W- J: `+ r, B$ k| MCASP_PIN_ACLKX H* Y2 F* w4 r2 H
| MCASP_PIN_AHCLKX
% b, k9 q7 m7 x+ r) n( o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 G, o$ k! e4 Q" M: b/ t$ {& xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 z. C( e/ u1 e; N. `& ?" \
| MCASP_TX_CLKFAIL
, v; e/ D+ f5 D, n' `| MCASP_TX_SYNCERROR
$ } X' Q' ?' x M" i9 \- M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) A, `: M, P0 w| MCASP_RX_CLKFAIL3 x3 G1 M* J. L' ]- Y0 S
| MCASP_RX_SYNCERROR # K6 _, k) b% E
| MCASP_RX_OVERRUN);% j( ~0 k0 z4 P1 d
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */9 _* E5 N/ H+ V/ E: q# M7 J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 {! ~# Z% z/ J1 c# D# m; l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; o( n; n& g4 a) `7 e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; u2 P* y7 a8 D8 |6 {) GEDMA3_TRIG_MODE_EVENT);' d& m4 J1 r6 O! i2 ^# K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# P# b2 Y ]* x" K, u N f1 M8 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& @/ B; C! c1 J2 P! L8 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( s* E" Z. e% \: ]% T3 h4 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ G6 @0 f6 u2 F# y5 v! x, m; I& L- _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; T1 m P. I) ]0 N2 Y( C0 h {2 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: O) ^& L9 c+ ^& g2 ~, u5 N: F3 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
b7 h9 @0 n+ b! _}
$ I9 M- m: k5 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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