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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 |5 i6 h1 a; t' _: l9 m6 t
input mcasp_ahclkx, L8 u2 v7 M/ f" K5 L8 a
input mcasp_aclkx,
, |3 [& y4 @* Finput axr0,) g# r; s. W* g* c# e3 Q! w* t
9 f, C8 C7 ?- [# }. V! w
output mcasp_afsr,
8 F4 t/ E7 x, j! c# M B4 }" Houtput mcasp_ahclkr,
! K a) c% L% h* z: V Uoutput mcasp_aclkr,
: C4 Q/ p5 i' u( uoutput axr1,1 k+ A+ X8 @- g
assign mcasp_afsr = mcasp_afsx;% B. _ r, j+ u$ N7 `2 X
assign mcasp_aclkr = mcasp_aclkx;
3 z# q2 r7 X/ x H/ Massign mcasp_ahclkr = mcasp_ahclkx;
/ G" m8 v' u [& cassign axr1 = axr0; 5 t6 T8 d; ?% R! `, t
+ [+ m( z s+ r! S# h( K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( N0 L% Z5 ?: e- Y* W# U/ l! i6 z. R
static void McASPI2SConfigure(void)6 v: \2 Z8 x' V4 \2 R" [3 ]
{
$ o H) m9 `0 g& \. Y( U [McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 L, @; n% G) d+ Z, _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 F0 ^( N" p7 F& ?6 u
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 |, K% g& @+ I& g0 v9 l0 J* i
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" W* Z+ x& A9 v: W$ c6 B' R& h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% \! I9 P+ t8 C$ e8 F* w7 Y1 k4 fMCASP_RX_MODE_DMA);* Q; `' O) A1 X2 X; X7 @7 z' K; n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' M5 o, ^7 W3 T$ X" V5 l4 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
d3 U" _% L* e7 \8 ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% S1 H. Y2 c- v( fMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( |. t# S: t4 s. F) l) [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / z3 f0 l9 r5 y* K6 ?" h% g e6 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* z7 q2 r! V! Q! N; h n/ w* E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* _) M. C) e0 W. J& `: vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& A7 r8 P7 l9 H# l, G: \- [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" U( d8 N: ?# j0x00, 0xFF); /* configure the clock for transmitter */+ t2 d7 q4 `; ^7 ]4 }6 `1 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" @' @9 v: w: E3 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* q4 w/ F5 S( F3 \McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& R& g1 @- T$ t: G& |
0x00, 0xFF);
6 X I+ o4 c8 R1 f' z6 Q5 k1 W
; Q, M% K: P, D' k/* Enable synchronization of RX and TX sections */ / y6 ?4 O% P$ u3 z& ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 { i- N3 h A% W; XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! O: y. a! [/ K% {/ FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; @/ e3 @1 w6 [' S** Set the serializers, Currently only one serializer is set as
' s: w! @0 {8 I0 V/ h! \/ f** transmitter and one serializer as receiver.* ]/ ?/ N( Z3 j* a* |0 h9 v
*/
3 v3 `: Y3 b2 m4 _( \; i7 ~# W5 m$ W' E4 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 `/ r7 o/ G ?3 n! }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 c$ }# W" q+ v+ _$ x3 F& Q* s
** Configure the McASP pins
8 |' R! B. Y9 w* b' l** Input - Frame Sync, Clock and Serializer Rx
1 I' Q6 M0 t" t' q3 R% p** Output - Serializer Tx is connected to the input of the codec
1 o0 Y0 W2 n# U+ e3 D3 ^*/0 U5 A6 Z: g$ ~ p& W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, D6 q& ^) z: \" [2 n- U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 c! F0 ]2 c: `+ ~7 v: ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 }+ y( D3 c/ S/ l7 M| MCASP_PIN_ACLKX
9 m. B# L& K7 q- p* f| MCASP_PIN_AHCLKX, a8 m5 @3 f7 _$ E! t4 D1 {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, N! v9 u# Z6 ^1 @7 h* t% X9 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- S, ]* g9 N/ m& s' [' k% \| MCASP_TX_CLKFAIL 9 r% `; h% H) P* k& ]
| MCASP_TX_SYNCERROR
1 _" S. I$ l. \# O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 h% Y0 f O7 {, l
| MCASP_RX_CLKFAIL
- u2 X: E. x" M" w1 h& ^ l| MCASP_RX_SYNCERROR ; s8 E) J5 _" Y. u( X8 p7 @ ]0 Y
| MCASP_RX_OVERRUN);
) v0 @! d! ~" `' c, m7 N- d3 ^} static void I2SDataTxRxActivate(void)" i' [# }) r. B( s- [
{
* ?: {3 l6 U7 t# |% V5 ^0 V/* Start the clocks */3 A2 y8 W& Q; m$ D) ]2 L8 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; p1 t! R! |" N+ G: P( G5 K1 v3 v# NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: N; O5 s$ z: ]! XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! E2 g5 h! l, j5 V- z6 cEDMA3_TRIG_MODE_EVENT);
$ Z" K A+ X4 t3 v C, _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
2 {0 `/ m+ c9 n* |2 X r2 w- AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 l6 f+ E% [! ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' u3 r, r) y, `2 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 Q& J9 U& |1 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ O: E( i; b; u0 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" I# c1 e; c6 m1 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 [# {- f5 v) C; R! l
} ! w3 [# G# r' b8 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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