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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. Y- A; P% p/ B6 j; }' Winput mcasp_ahclkx,
* W% [2 |6 X0 [0 L' E& n% Iinput mcasp_aclkx,, r* F5 ]2 \* x4 C( A( x2 W
input axr0,4 C- a4 ]" n, \6 o- D$ [' N
6 Q9 c0 C( |# o( e Q
output mcasp_afsr,7 M5 Z4 g0 O! \
output mcasp_ahclkr,
8 g- U! y# ?0 u0 B- A$ ^8 noutput mcasp_aclkr,
# b, O) L6 [8 Q# e, ?$ s) Z9 M! Woutput axr1,
8 _6 I& Z# W& K: H' v( W. }- M assign mcasp_afsr = mcasp_afsx;
& n7 b" k4 B7 T- S+ c, r% `assign mcasp_aclkr = mcasp_aclkx;
& P+ _* ?3 d2 t0 _( passign mcasp_ahclkr = mcasp_ahclkx;' l" I4 i& g( [0 T: a( d3 P$ G
assign axr1 = axr0; 0 i5 u! O. ?0 L
; D3 z& k" | L! {( m- C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: W2 C8 |( }& `; A5 dstatic void McASPI2SConfigure(void)# i6 K, g% v: S1 k2 f: g4 _
{
, K2 O1 [( y) H2 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);: c, ~- q7 H! @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% T% |: T& J6 b+ j& x" sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ O+ m( L+ V1 Y' \4 N) ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& |* `+ I& _2 A/ c+ ]; k# j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( H2 f! K, d8 \+ l" k- m
MCASP_RX_MODE_DMA);
" v6 ]5 N6 F0 R0 G+ `. BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 W3 h9 H g: IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( |7 a, h u) Z# f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) t9 ]. b- k7 m3 ?2 X5 }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ e9 i2 J4 |2 i I) K+ z8 ?; ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 e0 y0 ]4 b1 Z7 n* ]# Z
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 q0 h- D8 l5 ]$ [9 y9 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
D2 F# q# K* x1 N, N7 w* MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 W: u3 P, b/ I6 u) w8 P. D% G9 ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 n6 m* ^# i0 w: [/ G
0x00, 0xFF); /* configure the clock for transmitter */% [" x) C, A- `# b4 T+ T* I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" P. O) x7 O* `9 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 ^5 }+ b- K' _. i- `; d1 A$ l! zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& p- z- ]( `$ H* Y) G! a0 a0x00, 0xFF);
' D, s8 ~, J" y5 Q- `5 B: g7 j
/ W9 A$ M+ ~7 \/* Enable synchronization of RX and TX sections */ " M1 U2 X7 U% _5 @; h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; Z2 V/ D3 t6 v7 w' h8 K+ ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* \/ o1 O. R" t3 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 m3 ]8 E- D+ s* _4 N
** Set the serializers, Currently only one serializer is set as( ^0 N+ \+ B) ^/ h9 j
** transmitter and one serializer as receiver.5 _3 ^9 `2 i* V' _- W6 N
*/' G' Y5 a$ h. z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ e' y* l) G6 U1 D# P* @8 s6 D- Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 X7 q; p8 y1 l: E9 V** Configure the McASP pins
; m0 E6 K% R$ D- i3 N** Input - Frame Sync, Clock and Serializer Rx) N, U7 c; R* {7 D' K" q8 y
** Output - Serializer Tx is connected to the input of the codec 1 ]$ ~3 n0 b2 ?- Y+ x
*/$ V) T& N( o! n1 l7 F" U1 J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 k5 T! B# B6 B- a4 E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 s8 f: \/ ]' ?) C; @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 C9 i' u+ G8 D o+ v; f
| MCASP_PIN_ACLKX( G5 H0 G& R/ U& B3 h8 ^% ] u9 j
| MCASP_PIN_AHCLKX
; D( K. S. K( G5 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& |: Q2 e' i. i: y( O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ e, k2 H8 \: A( r
| MCASP_TX_CLKFAIL 1 q' D/ U' d5 @$ |' D$ N8 c4 a3 U. y
| MCASP_TX_SYNCERROR
0 X' x; ?( S% d0 W6 i( k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR H% T+ U. P# L/ {, x
| MCASP_RX_CLKFAIL
6 J! h S9 S( }* |4 l: Z9 z| MCASP_RX_SYNCERROR - ?. U( _ W- g
| MCASP_RX_OVERRUN);- S3 @ W: h+ s& m1 O7 L: H
} static void I2SDataTxRxActivate(void)
) B K E- e* ~$ t+ |+ C{
- b9 L6 `# P+ Y; [5 } s0 e/* Start the clocks */
/ n9 |" D7 x1 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 p* c3 R) K! dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 ]/ Q6 G& g4 w- N0 r4 C. L+ \* b @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 u- V; K, @( G& TEDMA3_TRIG_MODE_EVENT);$ S4 @8 ~/ M" f' r, O, H1 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 _4 l4 P- h9 w4 ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; S c4 @" Y7 {! v: d- ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& y$ n8 D) R1 k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, M0 w3 U( F6 }2 {5 w+ X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) o1 a# k# F2 ]; @5 |/ U3 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* n* i' e; }8 q; o4 o# O+ mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& ~+ y' @: j% ? Z4 ]5 A}
! @: Q- @! G( h- A# R h0 K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! g; }1 W1 N9 _
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