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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: Y/ O: d5 @: D* Q; ~/ Z( r$ pinput mcasp_ahclkx,
; u& F3 h9 {+ X u! cinput mcasp_aclkx,
% e( Y; R6 S: m) linput axr0,, r0 l5 Y. e& J0 i# f% U. z
, `8 \3 c0 H! H
output mcasp_afsr,) g0 \6 S( q# @' R7 G2 s ~
output mcasp_ahclkr,! H+ ?, a% Z6 P6 _0 \
output mcasp_aclkr,
6 i2 Z2 K( S7 }# e6 |output axr1,5 \) a* C; I0 ~6 K2 o+ _2 g- m& y0 r
assign mcasp_afsr = mcasp_afsx;: o; c/ X$ x0 C( z/ G% N- C
assign mcasp_aclkr = mcasp_aclkx;4 T4 S, u! @2 r
assign mcasp_ahclkr = mcasp_ahclkx;* A0 T- K; B. |
assign axr1 = axr0;
& |- V; e/ {- \6 T( r6 r7 ~( I
* i4 { q+ D7 J x8 Y9 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + q$ H" L4 l1 L8 \0 _$ Y2 U
static void McASPI2SConfigure(void)
& q# g* q$ ` Z1 Z! h2 C# I{. @3 m* r |+ S& N* x$ u/ o! O7 a$ s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' K0 A0 w F! ~3 K E7 m* K( mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 ^, H& S3 j0 U4 c) d" u9 a8 D: u1 |0 Z! C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- p4 G, L2 b, y7 m( w+ u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ v( z2 F1 z' B0 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 q; N; J/ C8 f
MCASP_RX_MODE_DMA);
, B6 ?0 d, _4 x9 }' IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, v/ f4 _# M9 {/ B7 o% ~; AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: M. Y/ a4 k3 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; s2 E* G+ F% q. P! QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ N, A" U! h1 p1 O0 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, K$ } J( `5 b9 A7 O- m" X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 w% K5 E* U0 }/ ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 }5 ~3 n$ n: R* C$ @6 h5 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, S8 N5 B! Y; l( q2 B" wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% ?4 c0 ~" T# A5 x( A y
0x00, 0xFF); /* configure the clock for transmitter */
1 ?: U* }& r8 k9 S. EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& i |8 v5 }: Y& x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 A2 U3 a0 R a. {
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, h5 L N6 ]5 V, f
0x00, 0xFF);
9 Q* C: _7 |# B( a( g- N" ?$ Y# L* a1 ?# |+ o% Q
/* Enable synchronization of RX and TX sections */ * p; h4 d3 q; W; y( A' s) d7 y' D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- A$ c# I" r, R- P8 R" uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( z5 j4 x" w+ C" bMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 o ^2 t! T/ l2 ?1 f9 h
** Set the serializers, Currently only one serializer is set as' Q& t( \9 Z# O3 B, [/ M N! d& o
** transmitter and one serializer as receiver.
- |, B+ z* A# k z; p*/9 X2 P% w l. l8 S, P: {4 Q3 j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) ^3 `9 c' r. P j \2 q: K6 A) AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, |8 u# x% R; u# a# b" v** Configure the McASP pins x I0 b) h0 z1 l6 U) R
** Input - Frame Sync, Clock and Serializer Rx
K6 h1 v5 D0 H! n9 e! [. D$ d** Output - Serializer Tx is connected to the input of the codec
/ A9 A4 F# M4 f% d$ {& x*/5 R- I' K8 ~- B6 P9 p# P$ d
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, M( R; l+ B* I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* i2 ~9 s/ w( |9 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 E( b9 `' r+ u9 n| MCASP_PIN_ACLKX# G3 O! C2 v. M$ B, b
| MCASP_PIN_AHCLKX
9 i" q1 V3 b( n& m+ v' Q/ @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 j2 e5 p' P" a0 Y7 XMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! M S5 m" r% w
| MCASP_TX_CLKFAIL / `+ n2 O2 h& d5 }" ?+ v' a+ [5 u6 f
| MCASP_TX_SYNCERROR
$ n% \9 F# w( {; U# B9 \9 F! ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 c% y8 L8 j8 s T| MCASP_RX_CLKFAIL' s' T6 z; r* Y/ N
| MCASP_RX_SYNCERROR
: @1 P D- V D& p5 h) I0 z| MCASP_RX_OVERRUN);
4 G; F3 l' d! e7 y2 F} static void I2SDataTxRxActivate(void)6 |1 b! d, I4 b1 s
{
/ g4 Z& y) v' M* x/* Start the clocks */
$ k8 o! _9 X+ KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ u' b$ C. ^3 l( L4 W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ r8 B1 `. ~, q* V$ S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 Y$ V- R% \( O& k2 R) w! F2 ZEDMA3_TRIG_MODE_EVENT);
# y9 X3 K1 J$ W0 y2 g0 p7 \2 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. f: c* O0 ]0 A6 J- l0 d0 u2 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; P; t$ p( n6 r3 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 a/ O7 V/ v& Q- M! u+ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 r. P. Y. b) p- L8 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. j* \$ k5 P( ?9 m h( M# s' bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ U) g! e$ j+ _& E' F4 RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 P- J. L- e Y# @/ d5 A8 o
}
7 _& V& ~5 A3 n/ m& @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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