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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! r5 N/ K" R$ w
input mcasp_ahclkx, a0 Z1 `$ }7 u
input mcasp_aclkx, w9 z5 O: w7 O* Q3 g
input axr0,+ [" y- n% W; ~
7 \0 g* t, V4 X3 l" y7 Boutput mcasp_afsr,
0 V7 j; A6 U n4 V+ ~5 Doutput mcasp_ahclkr,3 l1 R" K/ z/ J7 t8 x$ b
output mcasp_aclkr,0 V+ j. v& K- F+ }
output axr1,2 t4 F" M% |0 F5 a3 b/ m
assign mcasp_afsr = mcasp_afsx;
. P- d& Y2 q- ~2 t0 R5 _assign mcasp_aclkr = mcasp_aclkx;# c; T( _" I( n
assign mcasp_ahclkr = mcasp_ahclkx;" a& K% ]! k) I* _
assign axr1 = axr0;
. K9 t0 J, O4 h- E2 X* d" x% J& _! z& i, u$ t: x+ o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& t3 S6 X" o. f4 n3 t6 mstatic void McASPI2SConfigure(void)/ w& p$ Y4 F3 q
{
9 G" p) U$ |; q! NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% \5 T6 D2 \. q( ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 l) u3 D' N8 g. p& J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, F# N8 E. F, o; Z; N8 i2 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ U y$ k" {# Q5 r3 _
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# V5 Y9 v5 W2 N4 h7 \; H6 i- U
MCASP_RX_MODE_DMA);( {- [, t; t# r) }0 T. F% k% k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ E: p* N8 L @# Z( ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 }0 ?: T& W: s! x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 e6 ^" [* r$ k* d/ n( w$ S" ?+ rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" | h1 d9 O }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 W. x$ x! C$ M9 v# k; J M% P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ e n6 t M, {7 p- dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 I) l; R' y, b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- `5 Z! ? y2 JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) y8 ~& F2 c5 e9 Q! o8 M3 b2 M
0x00, 0xFF); /* configure the clock for transmitter */0 Z( V6 x4 W# n' b5 J. D- r& ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 S6 S% c6 q, M( h, \9 S( D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% g) m, b8 I7 r4 v/ {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! \" W+ R# k" z& B# S/ c- O4 v& O0x00, 0xFF);
2 i/ i! J! ^$ B! [0 ]5 [- c3 A8 Q6 g, R/ F* }7 b2 ?) Q8 c/ @
/* Enable synchronization of RX and TX sections */ 1 V4 s5 o4 D! P5 a5 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# Z9 J" d0 P( J" e2 G T. f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- b' \+ X5 L& T7 i3 C, CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** n6 ?5 @* p7 X" X D
** Set the serializers, Currently only one serializer is set as
( v" R* o; o) n" F** transmitter and one serializer as receiver. \0 ~2 {1 J- G# Q& z
*/
% Z2 h; z0 I" M$ H3 c, b* g8 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 i% r( U# h2 h5 e. F) cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( M; M- M9 e* Q
** Configure the McASP pins
( V% t2 p1 ?: q- W** Input - Frame Sync, Clock and Serializer Rx9 J/ d5 ]2 h: ]
** Output - Serializer Tx is connected to the input of the codec
7 _* Z: X9 @" E+ _ u*/% b$ w' B' z) M2 m; f( f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' \9 j% a% Z4 Y2 s+ a+ l) mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 p# D4 g% [" v6 b% J5 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( r! f8 R( z8 b) r+ m9 a| MCASP_PIN_ACLKX
( I) |: N) j+ b2 i+ f+ q, b2 p| MCASP_PIN_AHCLKX# L" ~7 k) f; \: m6 n6 e3 x
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
D5 @- `: ^9 n1 E- l1 mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) l; |) ?8 |. ^# [" A: T1 S| MCASP_TX_CLKFAIL , y- ^4 N# h, x7 z% ^5 d$ D
| MCASP_TX_SYNCERROR
/ u7 \1 `9 z$ U6 q! ]' v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , V+ {( O; s) f9 r- r
| MCASP_RX_CLKFAIL, A: o4 Z$ o, c$ m9 a' P% L+ u
| MCASP_RX_SYNCERROR 1 o, |/ i! i) n! h6 h0 \1 N5 m8 A
| MCASP_RX_OVERRUN);
0 e/ y5 M- c9 j' ?} static void I2SDataTxRxActivate(void)
7 X! u- w6 M& |* x5 X, Y{ S7 f$ X$ w# N# V0 P' @, h4 P
/* Start the clocks */
- Z U+ ~; p. G0 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# ], o: T g# _7 D( O4 h6 H* w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& b, o+ ~) e; y1 t# y1 }: j. N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& h A1 t2 E8 u* LEDMA3_TRIG_MODE_EVENT);2 A" b1 C, x- P& ^( [" [% j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . K+ _0 \4 |, N* p: N r, k/ t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; ^ G: G# V, K" ]* ~+ vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 C7 ]4 P8 N# jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" {; w h, x# i5 }. u* a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 h% o; |; i* U* A2 L$ Y: b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 r6 _+ d3 C& `; U% ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 G1 b: B. F7 B' z" V& C! [
} " a7 y- O0 _# A1 C {/ W. e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 N8 P0 {5 @' ~5 ?$ o1 I! r6 W
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