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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 |& R& A0 m# Xinput mcasp_ahclkx,: m# `4 }9 r6 u
input mcasp_aclkx,( }9 {0 F: p$ F- `
input axr0,
- t! H- y3 }3 l% F0 w3 R/ |* D D! s: w, ^( f* M) x% P( A/ V
output mcasp_afsr,
R' r& w+ w" E# F7 n7 `( W$ qoutput mcasp_ahclkr,2 ~" `; }. h D
output mcasp_aclkr,
@+ G" M) T- ^5 K r! Routput axr1, g X8 @. c% s0 n2 k5 j- E
assign mcasp_afsr = mcasp_afsx;6 j# e! t8 f* m9 p; J
assign mcasp_aclkr = mcasp_aclkx;
/ [0 u, L" n3 |assign mcasp_ahclkr = mcasp_ahclkx;' H4 e. W2 N0 n
assign axr1 = axr0; 4 U! }- a5 M! R/ J
7 G q& y+ ]& ?7 a" ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( ? F" ?1 M+ m, h. k: ^1 ystatic void McASPI2SConfigure(void). U' B1 c8 |( `5 Z& V
{: ]' y' K0 A, V: i# {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 B2 c8 w- I0 a1 j( ?+ ~( L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( M) V+ s% R: l1 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 l0 d, L( {% _. a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& l* L# k1 d, b1 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 @1 f3 u: \% BMCASP_RX_MODE_DMA);
. t( ^) X8 a; t+ a9 a! LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# I- F# T a( I' y8 J; O$ ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* L" p" Q6 @; f3 {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 e$ X" |; `# }0 z# G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); l) i8 U, m4 r ~; r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; `1 C! y4 ? T; y$ DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" `; l, f8 W/ E4 X5 n. s- xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 f' X3 s- \( T) ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * C, W2 p: r b) k4 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; B3 i/ i/ i# Y$ [' E$ P) H
0x00, 0xFF); /* configure the clock for transmitter */
2 U; l! }7 M: p. y! T1 g3 G8 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! W6 c/ ^, \, `6 R/ i" TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( z; I, y% \% ?: W: j* Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 {# s* [" O6 g9 \* o8 H$ {/ K0x00, 0xFF);! ], I$ z. n2 f0 {; t+ G0 W
; r% e% C8 o7 y$ w# V5 O
/* Enable synchronization of RX and TX sections */ 0 h( f5 u9 t! ~8 E7 k" {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' y5 w n9 U1 n( s% i* XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' U* [3 e4 x9 V& _ O! ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 h$ @% V) e# R
** Set the serializers, Currently only one serializer is set as! s! o/ |( F/ J: S5 L! c
** transmitter and one serializer as receiver. V, u- ?/ [" |0 P* }
*/$ {( F D: d5 ]$ A" l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 f1 C" I' n, o$ j/ \4 `" O/ YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; H/ p2 z) s: e) q0 E
** Configure the McASP pins 5 _8 W/ E, Z9 e e4 Q1 O% F+ ~
** Input - Frame Sync, Clock and Serializer Rx
) X6 Z& J# l7 z# l** Output - Serializer Tx is connected to the input of the codec . u; A% l4 \3 a7 e1 Y& t1 L8 X- L
*/4 h; y; d1 i" n$ ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ j! |! G( \1 B: u4 oMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 s/ e& b* |# M6 k d7 M. JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ D& q/ X$ m& V* C2 j M
| MCASP_PIN_ACLKX
2 @3 z" S' r! F: ?4 a1 y( B| MCASP_PIN_AHCLKX6 T c+ X P7 ^+ ?9 B) \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 s2 Y) |; `1 i# ~5 Z! x2 hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' k% S' Q' O4 J8 n T
| MCASP_TX_CLKFAIL ! ?0 ~9 Q; j, c* I) r
| MCASP_TX_SYNCERROR
; ~8 y7 U$ \9 K- m5 R: W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 O8 I; O8 b; S) y
| MCASP_RX_CLKFAIL
4 Q4 e7 ]! P5 g" L, J. V6 W" [5 J| MCASP_RX_SYNCERROR
4 V7 u c7 O1 q" @9 y| MCASP_RX_OVERRUN);
* J+ I* u5 C+ G) h} static void I2SDataTxRxActivate(void)3 ?( z8 W7 N4 D/ L A& [* G
{: w% [% s2 f& c2 j' d/ a$ r$ a2 {! r, R
/* Start the clocks */: M k: I/ R7 d3 R9 i: u, V/ u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, H0 X; c: o3 {9 J( r; a& qMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ u( k3 F1 t" Y5 D; u2 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," U+ t% J, G$ |! ~3 Q3 p4 l) ?
EDMA3_TRIG_MODE_EVENT);
1 G6 Y% ^* {4 Y9 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ F( m# k2 f' s: E# QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( q8 \- q3 C; _/ ?( ~0 z# Q& O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 t( e! c/ Q3 R T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* V6 \0 n2 ~' J3 @2 J% r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 [$ Z/ E0 M* V) qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. z, ?( e+ G. a% v) [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 T0 x4 {% o6 N6 M% ^1 d& h
}
3 X' w3 h9 z! e2 K! a6 N1 p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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