|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ s+ G. {7 @. H4 v3 z. l/ B, |! I" E
input mcasp_ahclkx,
+ Q: |" v# A C9 g" B3 xinput mcasp_aclkx,
' d7 P- w) e2 B9 c, _input axr0,8 `# T. g# w4 m& J% G5 ]- a% m6 ^
$ i }5 _ o9 g: g f
output mcasp_afsr,
9 u W. `; ~$ A5 T+ K u8 C& Y" Foutput mcasp_ahclkr,/ v% O/ Y, R: l& f
output mcasp_aclkr,
n _4 K' Y) [# w4 J* ?output axr1,
3 g, G9 Z7 q/ O2 Q ]" l% @ assign mcasp_afsr = mcasp_afsx;
5 p0 `3 d* W( `( y" T2 Jassign mcasp_aclkr = mcasp_aclkx;2 ]' Q1 |% @) j0 l t+ j$ V) e* B
assign mcasp_ahclkr = mcasp_ahclkx;
* Y% ~9 u& c7 u- X: y' Dassign axr1 = axr0; " ^1 U b8 Q3 v
. g- ~, \; t( V# ?. y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 W, C7 c t# I: C* q
static void McASPI2SConfigure(void)/ H% d4 Y _3 z7 V
{
, x& y) u8 P3 @: C- VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, V* k2 d7 F% F. \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ N1 j5 ^, I2 A6 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) |0 J7 g/ s' X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 k( I: \7 p0 S ^+ x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: T- z+ l7 }7 G8 FMCASP_RX_MODE_DMA);: s, `. {% w6 e6 I7 J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," C5 T! E8 R) \7 C1 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 ^) Y% @ P$ f+ M3 G' T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 i& q6 A& I9 A: ~3 O5 M |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( p0 w7 S! c) G. {$ bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) C- A" T4 p) D4 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# K8 S# B) e1 B& ?9 s' m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 r T% s j" c3 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# |9 v: k. y/ {, CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! \- e" v9 `! o0x00, 0xFF); /* configure the clock for transmitter */. K' Y/ k2 \5 r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 y) p9 t h7 e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' c% ~2 s. T; b; Z- iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( x' e0 K" U# P9 R
0x00, 0xFF);
0 r7 d2 i4 {" X
1 S7 ?4 i. k. G( n! v2 K% y# ?5 j; M! W/* Enable synchronization of RX and TX sections */
2 I' u3 q+ I y0 E# }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 r# c6 X8 h9 b/ y* I& D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; \- O! l# ?) |0 w9 ^: mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ w# M, P3 _( Q** Set the serializers, Currently only one serializer is set as
, r$ P4 O) o* w** transmitter and one serializer as receiver.
3 w2 Q& m( [3 ?2 w7 G# P*/( k9 `. [/ g$ h6 C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: p% p6 Y1 r; ~9 d" iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, ^" p' i- b- t6 d: W% L
** Configure the McASP pins
; H B; C, U+ ] I2 h** Input - Frame Sync, Clock and Serializer Rx
$ g0 A; A; p( q** Output - Serializer Tx is connected to the input of the codec 3 O7 r6 `, T9 q6 o
*/) K4 _" e; x! f) Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 T7 E" j+ u7 t `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, f9 L6 k( `1 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 _; ~, Y+ U g0 e| MCASP_PIN_ACLKX8 o K# [3 ~3 Q. ?
| MCASP_PIN_AHCLKX
5 `0 f1 }$ v* f" y: b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* {9 j2 [" T2 m. dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 ^& G& o3 i. j# D) U' @2 u9 j& L
| MCASP_TX_CLKFAIL ' z% {2 F1 y2 Z! N
| MCASP_TX_SYNCERROR0 S( t# |& `4 b" I; p
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 E5 u- s+ P) i# e g' {
| MCASP_RX_CLKFAIL$ Q; N: O9 B2 |; R" R
| MCASP_RX_SYNCERROR ( G5 J, U; C V+ n" }+ |
| MCASP_RX_OVERRUN);+ A$ n/ [! v% W* G6 k7 ]1 y, h2 j
} static void I2SDataTxRxActivate(void)% G) j# e- x' r* T
{
. J- m9 n1 o0 w* r" i, H/* Start the clocks */
' G0 s! X1 N. s! `) JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 F5 Z) h- U+ [" d4 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ R; e( G y) R/ n1 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, R4 K- y: y( \4 K
EDMA3_TRIG_MODE_EVENT);
% |( o; Z/ k. H0 J% AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 F6 Q$ d. R. F9 A2 I
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ S$ u0 x% N w/ u2 v5 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- |1 T5 k2 E# O. J
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, t( l* T `0 R5 m) V0 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( i! Q* P' }/ hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ z6 P, K9 t* A/ |; o$ s' Y; bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- Y9 F- o' P4 f8 i5 a# H
} $ j- m3 t ?/ S% ]- h5 }' F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 T7 W" o; |* u9 Z/ J0 W |