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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' D+ L) c v9 W* o R
input mcasp_ahclkx,- P% ~: O7 Z& ]( @5 O2 E- q
input mcasp_aclkx,4 I6 T" N9 C: ]$ n! F' S! L
input axr0,$ C3 c( K8 U4 [2 G* i* v; S5 U" \
( v4 e3 G& b- \output mcasp_afsr,% i# U, G. C" t& |) X+ U6 w$ L
output mcasp_ahclkr,
) @, z& F( H7 [6 u- y6 A! Coutput mcasp_aclkr,0 d, V' i, N) @3 p
output axr1,3 T. ~3 q0 J i0 N- L. k
assign mcasp_afsr = mcasp_afsx;
3 p" h' f5 u9 V4 @1 h7 [5 `2 Xassign mcasp_aclkr = mcasp_aclkx;
$ X/ g6 U& O l" F# }+ h& Iassign mcasp_ahclkr = mcasp_ahclkx;0 T+ R2 M% [. N; r
assign axr1 = axr0; / U+ ?" H' M( h
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) s5 v( j! v' ]7 ~6 S
static void McASPI2SConfigure(void)
* O0 v- S: ]5 P{
8 s$ p0 ?+ q% z) W/ ^. D4 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' ?7 X1 n2 u, D9 O2 i: OMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 H9 O1 O" h7 H8 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; V+ {& @# P! g2 q9 B3 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 v) M- |; J! J$ CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! v5 e7 B8 u3 v- q, KMCASP_RX_MODE_DMA);0 A( B% _6 _) ~2 ?3 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' M! U& Z- {& F3 s- g# rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 e2 `) C4 T0 Q" HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 `3 S$ Z5 D0 G# l/ r7 U QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( w: \6 ?- x/ S YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) c# ~3 ~: T" o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& ~6 d& [5 a* D9 y0 U, o, ] T3 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" c1 H5 u& I' W8 t7 g* z9 @& [1 Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 I( H5 H* t% o- L1 p# J+ u5 b/ v( mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
?+ K% H1 e& E* E$ C- h( [, X6 y0x00, 0xFF); /* configure the clock for transmitter */
) [$ h) }- T a0 _9 u+ ~( x/ @& lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; p& n& ?, R$ b9 ^% } d- D9 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , c) Q7 ~4 T7 N4 b, Q3 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ \+ r9 ^& X- }9 W$ Q# D0x00, 0xFF);. s* Y5 a$ l8 H5 i4 J$ a {$ d6 N
/ \& t1 L% w/ P. J9 d
/* Enable synchronization of RX and TX sections */ 1 d! t5 B4 h# O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 a2 H+ _$ X$ \McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ {$ S/ j6 D/ O/ d" zMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; X7 _6 O2 c2 J3 [
** Set the serializers, Currently only one serializer is set as7 `* b0 f/ L/ I3 k* |
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 l/ R6 o( J6 I! SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& V5 L$ b7 F# O S) Y$ P3 y** Configure the McASP pins - r& U& o9 [7 i, R+ Z! u p
** Input - Frame Sync, Clock and Serializer Rx
+ w' |# z W) E8 H2 n** Output - Serializer Tx is connected to the input of the codec , h y& c' T& I) l5 _
*/
, w: v, y/ n6 w/ [6 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 V) M. x2 N( m5 K* x" p% T& a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 ~& X9 ]- F" _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ }1 }+ L3 T [. D7 t3 b| MCASP_PIN_ACLKX
, i4 ~. J3 g( j1 R+ F4 O| MCASP_PIN_AHCLKX, u3 y; p1 W% F+ f- [5 r% F' l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! m) h1 H6 ^/ mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; U6 t1 \0 R( R
| MCASP_TX_CLKFAIL
9 D6 a" U- ]9 ~' z| MCASP_TX_SYNCERROR
8 ]7 h' L* h2 L6 v; U" ]: S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . k! E9 y+ k. ? N1 t0 X7 L! @
| MCASP_RX_CLKFAIL% T% @% E1 v( i5 A; i! `1 [3 k
| MCASP_RX_SYNCERROR 3 L$ x' }( z( a
| MCASP_RX_OVERRUN);
4 a! b% v# ?- h$ B5 E3 Y} static void I2SDataTxRxActivate(void)+ _) d/ p; W4 c7 o0 q# I
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/* Start the clocks */. ]2 @) t! x+ `9 |1 w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( D; ]5 ]* v: |$ p" o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: I4 r( _$ g3 J* |6 a- ?3 J' f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ X1 e F1 |- W0 p2 uEDMA3_TRIG_MODE_EVENT);$ v* C' a$ E9 ]4 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % @# A& v; a. r( _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ C; R; e! F' Z! ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ D. @5 e+ M; XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ V1 _6 s& _4 G# P6 ~: p" [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ s: q9 J3 h8 [! nMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( ~8 z7 l7 ]; @" l6 l
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' x6 N; X9 c) k @
} " P- E' C3 `5 f7 ?7 f# v) c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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