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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% h9 Q$ |: q; o# ]input mcasp_ahclkx,# P" a) ~# A+ Z' F/ Q
input mcasp_aclkx,
, h' V- d! I, l7 pinput axr0,
4 h! _% H& n: ` z( u" _& K+ Q" @$ w( v
output mcasp_afsr,
" f7 Y' X6 Y+ r3 z5 Aoutput mcasp_ahclkr,
: E' `) q4 |$ ~. n- i+ ^$ e2 coutput mcasp_aclkr,
- T. a4 Q; t" Coutput axr1,
/ T- h: g2 Z: a y7 e assign mcasp_afsr = mcasp_afsx;
0 C3 J$ ~1 K0 z' K) Fassign mcasp_aclkr = mcasp_aclkx;% X6 Z* R7 n8 y. n" x$ u2 Y/ m
assign mcasp_ahclkr = mcasp_ahclkx;: t/ i+ t4 a F+ a" S( k9 d
assign axr1 = axr0; & H4 M7 g: N7 c5 L1 m# X
H- k6 l9 e& @2 U A6 d" Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 r3 {4 J& z# [! `4 z' p% N8 U
static void McASPI2SConfigure(void)8 i% S$ J# i8 B! o8 N o
{
" @9 h& S0 I/ D7 A3 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 u, I1 I! p( e5 {& eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- Z7 s' S+ I- o& K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 z* r8 ]4 k7 P4 P6 ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( Q8 H: {* r% v& P; x" i/ q/ l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* w' k' i+ [0 z' a
MCASP_RX_MODE_DMA);7 @ ~; n/ j" v# ^) K- m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 O2 Q' V6 w1 K$ [% O" z4 B2 I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! I7 U* e0 Q' P2 y0 c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ ~ p6 G# |: v2 E0 T# N- w, q3 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ K4 {9 \* ^/ |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, G4 [2 w- E$ V1 P; IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- J4 x, G# A+ X0 M& y' f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* O, T0 O" C4 K5 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : W& M8 [6 T! U: y5 z1 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# R" R5 r2 t9 c9 g1 f+ b# O0x00, 0xFF); /* configure the clock for transmitter */
: a% R3 G! r! W# ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
@6 @! U* N9 z2 e. _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 N3 t+ g/ U4 r4 g! A- z, e$ MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 m$ C2 w3 t* j3 m$ W; o0x00, 0xFF);9 c" S! b3 j$ C0 F, O
6 N2 G$ N' i2 L4 H4 U
/* Enable synchronization of RX and TX sections */ & E# f+ y! u0 U
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, c2 U3 |' H* ~# ^+ E$ N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ T$ T/ K* x/ p0 J S) ]! [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( N3 Y8 W! h( b' }$ `4 |
** Set the serializers, Currently only one serializer is set as
2 B5 a# ^! J5 \** transmitter and one serializer as receiver.0 g$ q3 m0 I* ^- \8 n
*/$ @5 _" E- U1 R5 g- Q9 K! p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! w' d7 G, K8 UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, R% Z6 u" A6 n6 y8 Z8 v/ [** Configure the McASP pins R; ~- w* o$ T' ~! o3 k
** Input - Frame Sync, Clock and Serializer Rx4 s, E) {# l1 I2 P
** Output - Serializer Tx is connected to the input of the codec # v9 s- J+ ^$ _ K" R' Y
*/0 w! a# p; ^* F1 B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# P8 \9 q% D6 M1 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: }' v- h! _. jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 p* M% o9 G/ D! g3 R% h
| MCASP_PIN_ACLKX9 w2 e$ k1 }6 x: ~
| MCASP_PIN_AHCLKX
; V/ L. `+ X, B: b2 f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 u2 U: _* y1 T8 j: w' B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 m7 h2 @4 L3 o# M5 f
| MCASP_TX_CLKFAIL - z7 H; n/ \( T8 Z& _4 Q+ ~
| MCASP_TX_SYNCERROR
. K f; Z; d% Q5 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% {4 M0 s0 J9 l9 S( l2 y| MCASP_RX_CLKFAIL5 [0 P1 j/ p$ k& L
| MCASP_RX_SYNCERROR 0 p0 U `5 P& f3 t/ F9 X. \
| MCASP_RX_OVERRUN);- @/ e" }( @7 h% ?2 ]4 N
} static void I2SDataTxRxActivate(void)
- L0 E; l1 @5 }$ B{* v; @2 T. e& H: u$ Q% i5 g* \
/* Start the clocks */: h3 ^; s4 A. c3 S1 U# D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
z+ a& y* c) {/ \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ Z0 |6 a7 e5 H/ S% }1 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 p" O) N8 Z5 Q" r+ FEDMA3_TRIG_MODE_EVENT);7 B$ ^" Z$ m. o: _& a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 s3 c8 J1 M6 Y1 Q4 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 m2 o( a& e: ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- f2 I4 ?+ P# n2 P/ o/ `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) ~8 J- l# u% v3 Y. e; f! Q' f5 @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 J }9 D; K- ]/ XMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. c) A7 C' K4 K; H$ u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 N, x& I$ A" p% M: Z/ G0 V
}
& g9 x' U7 f: n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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