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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* ]+ W; {3 _$ f4 _* O% f. f# G" U$ W
input mcasp_ahclkx," e4 ~6 O8 B9 {" I# w8 z) S( e
input mcasp_aclkx,# C: I. W4 l& h3 H/ s, n
input axr0,2 z7 b* ^1 F5 v
( t9 Z9 k b s! T6 D9 y# J' {output mcasp_afsr,
% f2 t* J* B5 ~1 f" l+ N% D( |output mcasp_ahclkr,
7 N8 t, |1 m8 I& goutput mcasp_aclkr,
: k# E# f" a3 [( @: Boutput axr1,3 {6 w% @% E) R
assign mcasp_afsr = mcasp_afsx;
6 u( K; J4 [- J$ ?, F3 r- \6 D8 j6 Rassign mcasp_aclkr = mcasp_aclkx;$ R# l' V2 n" A1 S+ |
assign mcasp_ahclkr = mcasp_ahclkx;3 N) _1 I: g0 x0 w9 e% G4 [$ R
assign axr1 = axr0;
6 e% }; i/ p* U" r
# U) m, f( |, H" Y) g4 \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' J9 @6 Y$ E* c4 l( _( P# i# Wstatic void McASPI2SConfigure(void)
9 W' t( O D( w, |5 t0 I9 B) N- n( a" e{: U# P$ [; ]* B$ |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 T# q7 @, J, H' ?- {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- T$ c( ? ^: `3 Y3 _# C9 GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. F& y. B8 X( j- q VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 T2 i( a% b' g% ^6 l+ ~7 P3 r: \1 _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' f- |- y$ F% S3 T1 R: z( g
MCASP_RX_MODE_DMA);
( Z/ D. y2 h: u/ Y0 j# p' c( K2 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. t+ r5 T6 e/ X: T" y% zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 X, G' d5 `; w% G+ o) \- u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
y; } d4 x6 D" M& {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 A- O2 Z$ z8 s7 B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . l& [; v+ e* Q; ?: q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 g7 h) N" I3 t$ {3 ~. _& WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! [* E7 \3 L, h' dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' d1 y$ z( o) e: b& SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 x0 x2 w1 e5 D8 U7 O0 T' r0x00, 0xFF); /* configure the clock for transmitter */
( K1 K; S1 q4 t" `2 ]/ EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 ~7 p8 F- ]& |: z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 J% Q% L' A: X" a& Q" RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 @1 } {; C. [# n8 y0x00, 0xFF); d; G# ^) U! q' o1 z8 ~. c
3 V6 \, L( u% a9 i" t/* Enable synchronization of RX and TX sections */ ! P* T$ x6 l0 u8 j. F# s, T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 w$ ?4 n; \) u& s/ y) L$ h1 m& M! ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 p2 W# s! L4 X; o [% y5 T% OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 b B9 O; K- t. |** Set the serializers, Currently only one serializer is set as5 u5 T2 X& u8 L5 B- \7 j
** transmitter and one serializer as receiver./ c; b$ g4 n6 n; N7 B
*/$ W9 r" A; z9 l+ L# p8 m6 P0 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' u( o8 d ~ m% s$ K
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 S# }- x1 k# |* l$ G( s+ d** Configure the McASP pins . ]5 b7 }8 N' h. V% }9 _9 U% z
** Input - Frame Sync, Clock and Serializer Rx
0 `! t' x" ^* c8 W** Output - Serializer Tx is connected to the input of the codec : R, O8 j1 u8 a s7 H9 u
*/
( G% _1 J$ ~" {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- q3 z7 u9 q$ W+ }: k- x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. [- T4 K# E( \' K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 S ] X n4 \| MCASP_PIN_ACLKX
; `6 ^- A2 S: s o& b' c% D) D| MCASP_PIN_AHCLKX4 P5 Z1 I$ M9 `0 R% P
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ s/ @- F& z8 {; x% a8 y, I0 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 K, j$ B! R" _1 ^ s; X| MCASP_TX_CLKFAIL
$ S1 V; D* T5 E5 P7 y/ k- R; [1 m| MCASP_TX_SYNCERROR+ D5 C0 ^: e5 N5 ]0 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / M& E+ M0 W- V _ i, Q
| MCASP_RX_CLKFAIL* |* P' o, L c" I, c" n1 f
| MCASP_RX_SYNCERROR A/ _$ q/ T! O& I+ w7 i" F( C
| MCASP_RX_OVERRUN);
$ H5 b. _: N' S- T: w} static void I2SDataTxRxActivate(void)
1 S9 z" E; l3 T2 F1 i! u) b/ J{
" ~3 G2 h$ S! D% _% W. Q; H6 b/* Start the clocks */
, ~/ U/ c. T4 e: V& lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ `8 E% r+ g" a& n6 UMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 ~* D. J1 t( O7 x" {. R' O {: ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' u& {8 |7 k3 y# Z" h7 CEDMA3_TRIG_MODE_EVENT);* I0 o) ~1 `: b3 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ g$ M8 M: X+ M) a) ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// F. z. M& J8 x3 D1 z, }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 r# p. a7 C( `8 v+ f% H" WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 c- v, a& F- L! V, _6 vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% M6 @% X C! gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: _% Z- r2 f0 [, s; C: a& T& yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' d/ Z3 F4 ~ z N! k, r" }, X} $ j* W& V) E3 R3 S8 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 z* U3 S2 B7 J
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