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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 L* S, }+ O7 N" ^input mcasp_ahclkx,
( Y" b& W# N4 m" H4 c7 c) X% Vinput mcasp_aclkx,) O0 Z! a2 _8 Y# d
input axr0,# ]4 U! H' l5 @4 U; m/ H
2 @; y( H! V1 V/ v1 A
output mcasp_afsr,
3 O1 q0 J2 u! W, V: Aoutput mcasp_ahclkr,
# f8 e% @, I2 V! `3 v9 c- q5 }output mcasp_aclkr,+ X. s& X& O5 r, m. O* y# p5 o
output axr1,
5 g& y. m+ A0 E+ L1 P8 s assign mcasp_afsr = mcasp_afsx;
* Y/ o/ h9 S5 K) R1 |+ u/ uassign mcasp_aclkr = mcasp_aclkx;* x5 L% B3 G ]/ ~. x
assign mcasp_ahclkr = mcasp_ahclkx;- G+ F' v3 }6 Y* V( q5 j
assign axr1 = axr0;
' k* o2 M% _& G+ H
9 h8 ^( A+ U# m在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 z W/ v/ M3 U) \3 z- r8 x5 _
static void McASPI2SConfigure(void)/ J0 ?% l" x- S% ?
{3 i2 V7 J1 ^& [8 |5 y, N+ S4 j! [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" l c0 N3 K# kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, |& K' ?: f! sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ~" r4 F, p. _5 V' b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" p1 A- o" ]8 n9 }: O& w% n5 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) ~" `! P6 v- V0 F7 S% MMCASP_RX_MODE_DMA);
. l% c# E; V$ @0 x/ A7 t+ o" ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: H' Z# a0 h6 C* XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: o M; u3 D5 a* j& H u# MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 ~( I- M# v; F& N$ f. }; C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* ^0 S2 K6 T0 n; f% C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 C6 [ o) J/ v0 J- o! ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* I: J" f, q1 j# y" VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% g* A: E8 a% F* O1 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 Y; b5 s# n# b2 T. O* ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ K9 w% `2 }* f0x00, 0xFF); /* configure the clock for transmitter */
, z2 J( u$ V3 W' o7 @' _6 jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 C2 ]! W- Y& q& d: x* oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 c; y3 k& M! k( ] B$ ]7 E& k' _2 d1 [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 z" K$ H3 d) v, r6 O# V. S
0x00, 0xFF);& B3 |6 Q8 x7 n0 M$ }
- Y) p# W: J) _, D/ T+ W
/* Enable synchronization of RX and TX sections */ . c7 D: Y) L! G/ Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: p* u# ~" u' S# h( Y6 F( j$ v- OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: k+ D3 A2 K, M$ ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( X0 C( {7 K* i1 @** Set the serializers, Currently only one serializer is set as
9 q, _9 b( S3 K, x; b% d# H/ n** transmitter and one serializer as receiver.
6 m% ~" j. i5 H) z4 ^*/
7 e6 ~& h3 R" {! {% J- UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ R0 J1 Y) p* @2 i, m. s8 c$ z% L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 B8 D/ g8 e; I) G% F. ]
** Configure the McASP pins
O; ]1 K& Q2 j9 N; U7 ]** Input - Frame Sync, Clock and Serializer Rx! T% { b& b4 l( T! p
** Output - Serializer Tx is connected to the input of the codec 6 @, P5 }) V) L9 S0 O
*/
7 x2 Z; i) j- }; X) U7 Z* DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% h4 f c0 L/ r7 e" H2 b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 e/ o8 ~) Y/ c$ V3 M$ N! f D6 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 I$ b7 {. k* R' u* |) M| MCASP_PIN_ACLKX/ W1 f. }: [/ Z( t; M: J+ U
| MCASP_PIN_AHCLKX! n" C' I( p) K N3 T. [. e% y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ z$ m7 W: F4 u& g. N6 l( O8 K) bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * d. t$ V+ N$ ]' c c7 f; r
| MCASP_TX_CLKFAIL 3 V- Y5 D# _1 W S# f3 W
| MCASP_TX_SYNCERROR
0 K, Q4 ~2 L- E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 }) a; O, R% l" K Z| MCASP_RX_CLKFAIL$ {, z/ Q8 W8 v& b: k2 g
| MCASP_RX_SYNCERROR $ p4 h5 A. J6 M( t
| MCASP_RX_OVERRUN);
/ S; G* Z" c+ W& n' e* a2 o0 p4 g( e( b} static void I2SDataTxRxActivate(void), C: u; ?, _- d/ |
{
# E5 P P" m, L: k# p( K% m8 ? N/* Start the clocks */! z$ D5 U% u) I4 i3 [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! r# k* T. Q, ?& K
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- m0 ]" ^/ Q* F% A2 ~. Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 t5 s" J6 `4 v6 w- J9 q, xEDMA3_TRIG_MODE_EVENT);
. F4 y/ n+ j5 z6 ?" y% \; w2 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, W2 B T/ y$ _2 z8 F# N& ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. T0 l# C7 G& j! s7 r# ?; J+ k+ JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" t/ L' ]# M0 p& k1 y, i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% d; e( ?& i4 ^) z8 E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 g- k; R* [( U0 ?9 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) c4 n* b, Z9 \) h3 T2 F0 ^! q$ L2 PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 ~# Y0 N% i/ \' Y: Z. J1 }} + ]" {5 v9 x" {; Z" E. d- ~* r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 j' ]/ f- ]2 D6 A- ?- j
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