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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 \# E% x: S% v: D# |
input mcasp_ahclkx,
! P& T2 B% M5 C! }% O7 C0 @. Cinput mcasp_aclkx,) n0 }3 a3 q( @9 V1 c2 {
input axr0,+ ?9 W+ j$ }2 ?: v+ R+ u' a3 X) [
' F& z& ?+ _4 ~& \) t
output mcasp_afsr,1 U7 w6 C- s! {- f
output mcasp_ahclkr,
p/ l& ~- u' x- moutput mcasp_aclkr, z3 ?" s& N. l" U I
output axr1,* j' ]+ J8 y H4 g3 N
assign mcasp_afsr = mcasp_afsx;
( w* M; L3 O! W+ J" Tassign mcasp_aclkr = mcasp_aclkx;: n) r, J0 _- J: R4 F5 G: N# x
assign mcasp_ahclkr = mcasp_ahclkx;; o$ ?0 }1 m2 x5 t9 [3 p+ K! h, J3 W' J
assign axr1 = axr0; - x! D# @( c/ l% |$ E
* K1 a! i9 W" Q# [ q. @9 W- G8 t5 B: K" c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
$ a: V! V) S6 V astatic void McASPI2SConfigure(void)" d* W5 E; [ r+ o, r1 o* ~
{& x: ~. G* |8 v! K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 D; T: `( E3 M* [5 i/ K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ E, b4 F- a* ^' L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 q# ^" l+ N) I3 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- Z; s8 B# n5 B; p a
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- \ n+ z$ C2 x
MCASP_RX_MODE_DMA);+ i0 |$ V! K* x& {
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 i2 s' D l' P a/ |. k- kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" V' e7 i& f% E2 w4 _* EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' |6 o/ } U( F v) N E5 R+ bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 x' R# C7 a9 [& ?$ f$ x V
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( U' u$ b. Z! Z# Q6 A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& H) |: L% ]/ `) P( VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. Y. Y* C. `+ }McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " r2 X: i9 a& L; M
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ c* I$ _0 v" `3 S8 [9 Y* y0x00, 0xFF); /* configure the clock for transmitter */% X( s/ t) P @) t1 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 _' B! E' B$ C$ ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! u3 d# @' h' z& G9 c0 n, ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 B8 n7 }7 ]6 @6 M; {! n2 O; \0x00, 0xFF);
' V* j+ h3 ^- S/ l/ t5 I/ D7 Q
8 c( m, a' G2 D6 Z/* Enable synchronization of RX and TX sections */ 6 }4 v; u6 l, ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, \" T5 c$ m* N8 _. NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* w: @$ b: i, A7 p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. X5 c+ |% q7 g/ g: P$ O
** Set the serializers, Currently only one serializer is set as- X! n# L- [4 d; {
** transmitter and one serializer as receiver.
$ E7 v. H3 P- ~% J; h*/
. e5 _6 y9 }$ O7 I2 K* {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" l3 O5 I" Z4 }; i* m$ a" fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 Y/ K+ m$ ?6 |" N) w) M
** Configure the McASP pins
8 R# z( L* l5 _/ l$ U3 ?% O** Input - Frame Sync, Clock and Serializer Rx
$ z7 y) C- U y3 N8 ]; T** Output - Serializer Tx is connected to the input of the codec 4 D3 @( F% v: c
*/* L3 a# g3 H' \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# T6 Y6 D! \! s+ v! u0 c( n& h0 V
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ e# P5 G8 n+ c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# V- l& p4 Y F* z! X* J/ l
| MCASP_PIN_ACLKX. I; [; N3 e! i1 A+ w
| MCASP_PIN_AHCLKX
0 q6 n, u# v; X0 c$ O| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* C7 O: q( f' n }9 PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. R5 q0 H/ I& Y' }| MCASP_TX_CLKFAIL + L' [& {! O' e8 \1 v0 [
| MCASP_TX_SYNCERROR
. q2 ?! u7 l2 d, }% L$ I| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR K4 L1 [: F/ M7 ~6 E. k. R, p. K
| MCASP_RX_CLKFAIL
) X; C5 V! F. s| MCASP_RX_SYNCERROR ( `1 {/ J% J6 O- S
| MCASP_RX_OVERRUN);) a" Z" }& k9 G; C' _
} static void I2SDataTxRxActivate(void): x0 R3 _9 T6 T5 ?* g& E& }
{
* X6 E8 ]! p9 w1 f/* Start the clocks */; K) r! k; N- I5 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 j k# k# l1 X- OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; ?+ G( k0 |4 G+ o0 \( e' A# L0 [, DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 H% I5 M9 B+ G4 r/ _
EDMA3_TRIG_MODE_EVENT);/ R6 N, F5 F# ~; \' l* e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 X @: m5 C w+ A1 U' R$ p rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, i) v6 @5 n: p' c* H5 @( N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' z& J q4 C& o% D3 o% V' |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' d8 t8 z7 m: Z; o0 q1 s9 |" hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 V6 m% D1 m* r) K3 @$ YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' `0 K, _& ?. N+ OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ s' K' ~: i% w7 E8 z3 v9 A} 3 @$ O. \' I* ^+ K% d, U; D5 T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , F* F8 X5 U- m, g9 b2 Y, G
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