MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
; P3 X+ v! P% Jinput mcasp_ahclkx,
8 w' E; U; s% Uinput mcasp_aclkx,
* H" Y+ {; J. Kinput axr0,

output mcasp_afsr,
( ]8 u8 u8 a  u1 ioutput mcasp_ahclkr,
output mcasp_aclkr,
3 A" E- d9 C+ foutput axr1,
% @0 ~' Q9 Q( s1 _

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
; j& o% B; A5 j  \assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

& l% Z; k* m: u

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

$ M7 |* o; P: J: |3 q0 l

static void McASPI2SConfigure(void)
5 U: g  e; @) ?( w% Z{
. C1 X' e; t- A/ ~; b7 N, \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
/ o- R& I( g/ F! d. UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 N* J% E  W! hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 h# m/ G+ [1 y* K, l% I" g6 [# DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- y) c( `8 F4 n6 ]# DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 i# P* P  @& XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
8 }2 b6 ?1 Z" ]- |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) a+ Y; U7 {! i) \. [% jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 x4 T+ }& d- dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
! R& `. F: f& M& m, B2 c/ K! U
- v* v+ A) t% `/ t2 E! K$ q# ^: |' I/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; a( o1 s9 y& e8 e0 h" KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 b8 I) y( @: w% J8 gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
7 |# V% v+ }  ]) O% N/ D7 Z** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
' Q) Z) S& `  @0 c3 j8 _** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
' u/ u% \; Y7 x8 o! n*/
5 f, C. w2 d( ^) V# WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 Y: R' l0 g) b- C5 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; D+ |$ l& L2 q8 G; |0 f| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 ~2 a% {' k. P0 W* O7 Q% S2 w3 Y; P| MCASP_TX_CLKFAIL
6 E2 G5 c' {4 J  J. o6 M| MCASP_TX_SYNCERROR
+ P; K3 `2 d6 ?& U, b! L& m| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
/ u$ ]" _# q/ e+ o| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
# {/ r4 L$ F% Z}

static void I2SDataTxRxActivate(void)
/ i8 T' O( E$ R1 P5 r{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 K" p% T) ?9 G. `McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 X; R- F8 H* S) f4 lEDMA3_TRIG_MODE_EVENT);
# O4 Z, d% y$ C* ^5 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, A: t: j( q+ S# }8 v9 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
; B) R* r# c* d) P7 d% YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, K3 E5 K6 ]4 B* l6 x* K3 DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% R% Y2 w" o! s2 K3 C$ `}

1 x1 @1 C" g1 }7 U

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.