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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# q( o8 Q6 m- g- z" G* N- o' ginput mcasp_ahclkx,
% a+ J2 ^3 b( u L4 kinput mcasp_aclkx,5 n5 ?& B$ J0 @
input axr0,
% f# h/ Y+ z/ |( @0 ]; j T0 R' j; M! d1 n" J' n% p
output mcasp_afsr,! T- U! N3 N& @
output mcasp_ahclkr,8 ]2 z$ y& B) O6 H
output mcasp_aclkr,
/ D' O; A. R: [+ Toutput axr1,
) Q5 h4 g8 N/ s F, | assign mcasp_afsr = mcasp_afsx;, u0 z7 X2 t. |+ L, p
assign mcasp_aclkr = mcasp_aclkx;7 s) H. Q' f. D% C: S K
assign mcasp_ahclkr = mcasp_ahclkx;. E$ j0 I G; w1 x
assign axr1 = axr0;
; J- H% n, O2 P( d- Z
( F6 V1 G5 _% X9 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: ~( V4 R4 N; E: _- o+ a' }static void McASPI2SConfigure(void)
3 U6 d( I( F& U2 j. x# v{
8 R4 U. J# F" V8 _( `: B. fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" w) W. Q7 n& ]# u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 @: Z% {9 B2 }8 p7 S9 g, N
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* B3 w* ^ P, Z% G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 {1 H% R: i+ W" t3 |! WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ ~+ q5 m- g5 n( f
MCASP_RX_MODE_DMA);4 T& |) c% J A2 W; d6 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 f. L! |( _. x. `6 p8 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( v: B! q# T! h9 A% H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / \ b1 i y. |/ I' Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- `! M* f: [7 P( ~& u# h/ @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) @+ I5 d h5 N7 ]4 h8 K0 Q0 u
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 H9 d% A2 Z9 C& ~% y7 k$ L+ n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& G n) ^3 X* j& z. R0 K% Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: o: \$ `- c) D6 n2 `) u& l* \: oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- g, n$ X+ W! {. o( Y; V0x00, 0xFF); /* configure the clock for transmitter */9 q0 q* _' ? H6 I! m. V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" r1 h7 y$ F+ k+ j3 x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / i- z; l2 Q7 H8 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 }; b1 `2 |0 H" Y" s# ?0x00, 0xFF);
* @- j5 g+ x) t! T4 u# c. V# z# I& J. `9 ?9 t& k* z, z- z$ S; c
/* Enable synchronization of RX and TX sections */
$ h {3 m) L2 R" X( L! p0 }4 ~) RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; i. U% u4 S' ~ }. t* KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" G# U$ {& a( K% D) KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! G) s3 ~$ | E1 z+ _, Y
** Set the serializers, Currently only one serializer is set as m* t, E' a0 c* I4 Y
** transmitter and one serializer as receiver.7 h; e5 r A! N+ r& O
*/
: C& \' {1 h' K4 c9 t$ s4 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 D; p# F3 P5 f; \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ K6 q0 Z# `: v5 m! y4 k0 |** Configure the McASP pins ) h+ D- k' W- j- @: b7 I0 B0 z) s$ x
** Input - Frame Sync, Clock and Serializer Rx
$ }5 m8 W& ~' r# g' J** Output - Serializer Tx is connected to the input of the codec
6 o- [ O; S2 D( ]2 v p*/& R* ]# `( ^1 p& r- L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* v: H s0 s& `5 X" A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; U& d0 i7 X: e: ^0 q" F. k& Z& A BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' |" H0 V; g3 v' J# l1 [ i| MCASP_PIN_ACLKX5 H6 N' ]5 {: z5 a' E, |. t
| MCASP_PIN_AHCLKX
7 A& D) z C, H/ O. S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: C8 q1 l. }; K( b% `* E/ L+ r5 g1 ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
J s$ W2 m" f. M- T| MCASP_TX_CLKFAIL
. H& g6 S# w9 J5 H| MCASP_TX_SYNCERROR0 V" m- c" J0 \- ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * @8 ?; m' [" W5 [. j
| MCASP_RX_CLKFAIL
, g, |. p# y2 m/ p" |/ g# A| MCASP_RX_SYNCERROR
& y c- _- G' }! m| MCASP_RX_OVERRUN);. N, m+ y+ e( t/ {* Q0 Y
} static void I2SDataTxRxActivate(void)
$ ~3 q6 E! W7 x0 R1 v{' d$ D- U8 l. p [
/* Start the clocks */
+ z, j' a( [- r3 M6 T5 gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, h+ e" o8 p' k5 X( M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 j1 l- K# n6 G4 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 V- V, ` B7 c# a' I D8 QEDMA3_TRIG_MODE_EVENT); u3 l- s$ W" v& h/ |" M2 c- v# N$ x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 l" z. q. _8 x5 C# ~0 W, V- t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( w) ~4 ~; M/ K' a# m, a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) E/ ?5 Q1 g! X+ G$ ]" HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 X5 w" j; L; T2 c1 |1 ^4 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 G8 O/ D5 F, |# _, V4 L* \! UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# G; t/ p0 O/ C' t/ ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( i; O3 d; C& v8 m% e1 ~}
4 H ^& I" B5 [$ I7 P, H$ R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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