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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) f" ?- _) j8 b0 M
input mcasp_ahclkx,' Q+ a/ W1 |0 K& U/ k8 s/ o
input mcasp_aclkx,* @4 f9 b9 f# I( }3 S
input axr0,
, L0 [! E0 P6 @. a% ?
5 c9 h5 L+ ]# W8 Koutput mcasp_afsr,# ` k" h$ c9 d$ {5 Y% n n& w
output mcasp_ahclkr,
# E+ `( y% {+ P3 f; ~7 s0 m6 ^: Soutput mcasp_aclkr,
% k! t& \/ m; x( ]2 E' eoutput axr1,
) D& M# Q' F$ ^1 Z assign mcasp_afsr = mcasp_afsx;
$ O- }8 R- o# d" W) xassign mcasp_aclkr = mcasp_aclkx;1 b' C( t5 K4 L3 |/ Y T: P' h! m
assign mcasp_ahclkr = mcasp_ahclkx;
- m- D: z& ~& @% Z4 |1 J: h9 D- Gassign axr1 = axr0;
}; Y9 k6 {! x' J) `: [0 Z; c! ?) a6 {$ _' o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' g4 G0 M. I4 c: B( d7 Dstatic void McASPI2SConfigure(void)& ]+ C0 m: J. P( H& N0 k, a
{
, ^, @& [3 S$ g8 J6 L* ?4 ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);. n% Z0 m) a( I8 v% S# O2 `8 P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; {# K* `! L7 B/ R; k4 }: h! NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ B! ?$ z" w0 T5 {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* _' V; s: p3 ?; L/ N8 J( m7 B6 P1 yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* o# j: j: o+ g/ ]8 Q) x6 R
MCASP_RX_MODE_DMA);
6 k0 Z; G* \$ H* h; |" J; ]8 o, ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% s: y5 |! {! p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 z) P D% K7 f( A8 oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . S: a% f! q; g O& V6 j
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, U6 n! V j% w+ e- j' |0 C8 bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 R. |; r, i( _9 F ^* K# OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( Q, Z4 k% z* ]* i+ PMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' l6 i" i3 K. wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 H8 v/ b4 f* h' ~2 H4 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ {/ Z7 \2 Z2 c* [* W0x00, 0xFF); /* configure the clock for transmitter */
/ O6 v. R' i. x- p# r/ `$ jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 ]/ O" Q F% ~9 d- jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 j6 j! |5 a0 ?! w9 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: A% o( v" D; h- d" R0x00, 0xFF);
0 L: E, }1 X2 `$ m; a; T7 ^: g8 ]+ G+ i" q
/* Enable synchronization of RX and TX sections */
( n/ m2 s5 \" x! r) k) Z! [' AMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ X0 H( s9 E, H8 R* D; @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- N% _+ T1 l: x. M* I f% OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ U2 r7 [) n( i! O2 H/ C9 N** Set the serializers, Currently only one serializer is set as: E; U1 c6 ?9 P8 h; L
** transmitter and one serializer as receiver." g" F2 a" \7 h3 p. x Q: Y
*/5 {! l$ C9 H; V: j4 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' k/ a; i7 j h8 X0 A
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 B' B% x$ y0 J& [1 h
** Configure the McASP pins
# f1 ~) J. n! U; F** Input - Frame Sync, Clock and Serializer Rx
# k) A. `$ L4 P1 ~" Z** Output - Serializer Tx is connected to the input of the codec
( N2 ] r+ f: }( o! v+ u*/
3 r' C/ F5 z8 I* Z1 ]' |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( d9 ~& ~" t& @3 o: h6 I5 eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% {& S2 L: `: A( lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ B$ D9 o% s2 e$ \0 y| MCASP_PIN_ACLKX
- B& h( U7 J3 i/ c* l| MCASP_PIN_AHCLKX
2 [+ O% M' }! l* p! a5 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& S9 u3 N, I3 w7 _7 t
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- m" r& ^3 x5 V I/ c- d9 B| MCASP_TX_CLKFAIL
) `7 D! Z! z% ^/ Q| MCASP_TX_SYNCERROR) T! Z4 j0 S$ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * l# v) c% \+ W: b4 Q$ U
| MCASP_RX_CLKFAIL
$ Z( i6 l( r" c4 V" T% Q. B$ E; T| MCASP_RX_SYNCERROR a- ~! p; ]( l; E7 D* L9 z$ Z: E
| MCASP_RX_OVERRUN);
o5 }' _7 P. E0 @} static void I2SDataTxRxActivate(void)
" Q9 f& T% E' C{- ]6 [( O" e, `5 p
/* Start the clocks */; Z( g% D3 E: W }8 k/ V( c* B' z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- e; C6 j H6 Q# SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 }' X w6 N: E z, x* eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 _. V# [" Y4 e% t6 xEDMA3_TRIG_MODE_EVENT);
* U! c. I* }% E, Q& F6 @' PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) p" c B0 P/ E7 F2 j \6 O1 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 L( a: E0 L" d E5 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ J# }& {9 x4 D3 {7 M/ w6 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 u3 r9 Z7 B! t4 s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ h% h b1 Z% vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ i% M1 q. a/ PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 O* Y# f" h3 t) @) f* Z' U) d1 |}
+ X( Q) [( W7 K/ R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & O) t. f- i9 k1 ]4 `7 k
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