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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 @5 m' _2 D/ cinput mcasp_ahclkx,1 i4 B& f: Q" |* {
input mcasp_aclkx,
: T. G8 ? b5 w7 Y4 _input axr0,
6 U# [9 F$ \$ B/ }" o! Q6 l4 p+ w. t: F6 C4 K! {2 K
output mcasp_afsr,
5 J: ^4 R2 E9 k$ T! Uoutput mcasp_ahclkr,# l5 X' \/ n0 ~+ }. R+ \
output mcasp_aclkr,5 C7 x: V4 s8 R8 j% i
output axr1,7 J+ l C4 x8 \' i; C
assign mcasp_afsr = mcasp_afsx;
$ U# T1 Z3 P. c9 w% M; z4 B1 Bassign mcasp_aclkr = mcasp_aclkx;
X0 P) g+ N& {! [, Y+ tassign mcasp_ahclkr = mcasp_ahclkx;" y. u) H9 n3 o
assign axr1 = axr0;
0 f% X! F, A2 B, d- D3 @
; s; c$ f- [( k- r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 @2 F: }/ H9 C! N' ~. J+ g
static void McASPI2SConfigure(void)
# |: d$ f- D9 M" v{ C; p4 R! R& F' O1 {6 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' U+ z# l0 h o& R4 @" k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' u7 {1 m! g" Y! Z" RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& L$ [4 v7 O* M3 T" Y! ]- \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 v6 O# [1 A+ AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. j1 q) o' _6 X3 X' g, p- B0 fMCASP_RX_MODE_DMA);
2 ~# i9 |; m# G: YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' X; Z1 R/ W6 x, z, C0 f
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) _2 o+ Y+ v7 d+ z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 _6 X% a2 u# SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, |' x, t4 I$ Y, o6 VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& X3 w. [' B( C, ?6 _0 @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ Z; ]8 v; l- v$ a& z# ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# [. e$ o- Y5 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 ?, n' h1 i; O. G N& n- ]1 \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 r7 {( F; E; z* U. t
0x00, 0xFF); /* configure the clock for transmitter */+ D( i7 t Y& f j* i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) c' N/ q: G ~- HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ p, D$ a) ~0 S& ^; x4 h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ a6 \) j& q: F7 q0 d9 z- I
0x00, 0xFF);
+ F7 q- S6 Y" V7 T
( P5 k8 T: w) h' W. g( Q/* Enable synchronization of RX and TX sections */
2 i, V/ b6 `7 k! l# k: CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 B. `! C) p$ |5 Y {* m0 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, C! q6 F+ T9 h5 M* gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 u' E; W5 O9 |4 [" d4 n** Set the serializers, Currently only one serializer is set as9 y( _( Q9 Z# Q$ c, M, E% l7 g
** transmitter and one serializer as receiver.. @% K/ G8 P0 T6 V2 b5 d; S
*/8 h# G0 E# R! J1 i: w! I( ~) a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 E# R# o0 ?/ b; F1 ]. uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! B! y" M; O3 J# a+ V* ]** Configure the McASP pins : O2 V' r+ r& A! s3 U5 v& z
** Input - Frame Sync, Clock and Serializer Rx
7 f$ O7 O9 z9 K$ J. J** Output - Serializer Tx is connected to the input of the codec
4 _! o- e- g1 A) J% E*/- x( b3 J) N& s7 C6 V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" s/ K" ]6 ^; @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ c8 A3 ?' e; Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 j* p6 h' T+ S% b
| MCASP_PIN_ACLKX
7 ]6 `* q5 w/ g$ g" z5 D: c| MCASP_PIN_AHCLKX
$ X) M L4 W7 H4 d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- X" k: C9 k8 X+ [9 P3 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - |. w1 J; t2 g+ @ r) j
| MCASP_TX_CLKFAIL 6 v! `+ d; e3 T( Q9 G
| MCASP_TX_SYNCERROR
. u! [3 o% p% V3 W+ J2 Y. `9 N; i6 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% @ c8 K' [" `8 y2 G/ [| MCASP_RX_CLKFAIL ^9 b6 E7 Q: D4 d; J
| MCASP_RX_SYNCERROR
% L' w! J/ t8 c, R! P2 ?* Q| MCASP_RX_OVERRUN);
" F2 Z8 p" z* r- c, y} static void I2SDataTxRxActivate(void)( J* \$ @" U }* z
{
3 p7 b0 G( a' [5 x2 R5 T/* Start the clocks */# [: P8 M( G( [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; @ k G# I2 C- s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' [! [/ Z' s3 ?. NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& L9 |: g% b+ M1 S
EDMA3_TRIG_MODE_EVENT);
5 b6 k7 Q6 W* ?3 T+ REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % S ~3 q* E; W" ]5 _% z6 B' x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& I% M0 [; h" k9 XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 u( k, o. c3 a! M2 ~! @McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 [" \. L2 D6 t: |. I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 ~4 A) s6 O# mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 `& f& d& `' B' `, J$ k) V. k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' y+ e+ F8 [# c+ ^, N% \# {
} 0 b3 r& B, }; E- e/ }( ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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