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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; m) z, a2 D3 K" l! a2 F* Yinput mcasp_ahclkx,, B# A( n) w" F6 s/ b
input mcasp_aclkx,
- \3 W( V* |2 s9 I N" e# `input axr0,
. p. V+ Y! x" Y; ~4 C# I8 O e' D6 [; o8 Z9 s h
output mcasp_afsr,
Y/ J, J/ Z$ L! D' V% J! q2 Loutput mcasp_ahclkr,7 u l" x% I0 O/ m" K
output mcasp_aclkr,
# _" D% ^/ U5 _* ~" K) Voutput axr1,0 T1 C" ~; H0 w# |
assign mcasp_afsr = mcasp_afsx;
2 m# ^( I4 o1 z( I# S) Y/ Sassign mcasp_aclkr = mcasp_aclkx;
0 w1 d, ?8 `; t5 e/ F* F t- i! _assign mcasp_ahclkr = mcasp_ahclkx;
" b p0 I' ^: g9 H- r Q+ aassign axr1 = axr0;
& O% Y. Q# u) ]6 }
5 y" z0 I: a; m( ~+ M) l& G9 w+ M( C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& S7 d+ I- K2 Z# o- Pstatic void McASPI2SConfigure(void)# S" Z K9 h/ w; _: N
{1 p3 Z' P) T d. s. x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 X1 W/ Q/ O7 m; P, P6 r0 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( ?$ W$ x9 G2 ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 k7 N, X, X6 }9 p- o4 w. hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' k# A2 G/ S& N! K# H5 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 O. {& Z) y: ^! s5 K
MCASP_RX_MODE_DMA);" m9 P" J# z6 t' k- L4 F' T2 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ G& c& ^1 g4 A$ H9 vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// {9 J/ u: p& Q8 s7 W( I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; U2 `) g8 m7 j9 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# }: Z8 Y- O8 z! u2 O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * L8 K) Z c4 _' p; ?+ t7 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 {. G( \) s2 l5 f; ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% A6 r# |' O! k" q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( t) v- ]5 L4 L: O$ A4 D: w, d9 ]9 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 \/ U( G7 p! A) p. ?0x00, 0xFF); /* configure the clock for transmitter */7 b. x6 a$ ^$ v( T( H+ g# p7 p7 }' Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 G" x( W' R/ X: mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 V+ h M5 G$ X/ _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) E1 E% ^1 h2 G1 j* r) P5 ^" a( L0x00, 0xFF);
! ?' k2 [' n0 @; B+ F R$ |& Q
# R9 z D/ {+ R, X/* Enable synchronization of RX and TX sections */ 9 ^; a" D+ ~# }) ]5 y8 r
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 y% R; x9 P/ z" v9 }6 p! w; U1 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ n* ~0 D; z" J4 c+ V1 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: F6 P7 K" I" S% B/ q% `" o** Set the serializers, Currently only one serializer is set as I, |" ?! o# X
** transmitter and one serializer as receiver.
: [& H9 N8 o" g+ t0 n( I2 @" Q' ^*/( R0 o# a- Z" g! m0 k. a1 ]9 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 ?) [2 Z. N; q& e. u: f- h- oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ T4 S9 y* ?) b( Z
** Configure the McASP pins
# n" \9 X0 X1 e7 y" Z** Input - Frame Sync, Clock and Serializer Rx
2 S* q# |) @+ ]7 d- j** Output - Serializer Tx is connected to the input of the codec
1 ^: w, d* e2 I+ D4 n+ D+ V& K# M*/
. \0 G& a2 f# o# I! r; s- i3 v9 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: G; g) h0 ?& y8 \) \0 D# I8 v) ], V" a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ J d4 b7 Q7 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% q! {9 p# V4 j7 A! P
| MCASP_PIN_ACLKX
0 V- ]2 D2 J0 C/ F) q! }! x| MCASP_PIN_AHCLKX
) i$ P! M5 P/ g1 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: E i* |1 i9 L9 M: Y3 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; K$ d9 }- p6 J( [3 A- w0 [7 [" O4 I
| MCASP_TX_CLKFAIL
6 B1 h2 h8 d" W. U! u" D| MCASP_TX_SYNCERROR
1 |9 a+ Y( C, b1 e0 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR |4 t1 H7 z+ m& w: k
| MCASP_RX_CLKFAIL/ V% H* S a: T# g5 Z
| MCASP_RX_SYNCERROR * [8 ?1 `; j+ m# t
| MCASP_RX_OVERRUN);
" t1 r, t0 t8 {4 J. W} static void I2SDataTxRxActivate(void)
8 S' i f6 K. Y: K{1 t6 v- N& G/ I6 z0 n) d9 r
/* Start the clocks */
) b% A4 }; D {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ J c' f5 L: N' DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" v- U- R5 `5 A8 n2 X( ?& u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 }8 e% t. }& A" {& i, Z4 BEDMA3_TRIG_MODE_EVENT);
! G B+ }2 ]* KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 R9 ~- L5 m+ I# N) z0 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 p* @- W; _, v( h% ~& m- sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* [9 w. b3 ^/ y9 N$ s3 e* R% U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ y1 Q4 b+ Q2 C0 U, G* a) i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# ~$ S. |6 k2 Y& j+ o0 J0 t. o6 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ \. c* W8 q# n/ K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 m2 L. G1 i" X}
* G. E4 X' L' [, {" ^+ G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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