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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 f6 H- ]9 x7 f
input mcasp_ahclkx,
7 B- Y, O2 u# z) `5 _input mcasp_aclkx,
+ C+ g4 \4 S$ t1 }1 z }input axr0,
, V# k( ^, D) x, ?* y) X4 c7 p( d: [$ ~( O8 r' J' B, k
output mcasp_afsr,% n7 [: P! k7 B- g, M: T
output mcasp_ahclkr,2 D+ s8 a9 j" G9 g& k
output mcasp_aclkr,# u" O6 G) ?6 Y1 X
output axr1,3 B/ a: \0 S+ M( E% c
assign mcasp_afsr = mcasp_afsx;5 w$ \, Z' I; K6 N2 k
assign mcasp_aclkr = mcasp_aclkx;
/ Y! ~8 Z* _# _- R4 f/ H( u# |/ Gassign mcasp_ahclkr = mcasp_ahclkx;
( E6 o0 \/ B8 @" t+ S1 uassign axr1 = axr0; T+ f6 d- k. O+ i' K) ~* Z1 e, u: t
8 A8 |; ] x/ y) U& m+ q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 z9 e5 X6 X4 @) b+ Mstatic void McASPI2SConfigure(void)" a2 [( k* J) [! W2 k* D- n
{
) v w/ \! i p9 U2 `McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 o0 I: ]$ q, W* K$ O9 ^1 @ e" y+ sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 Z3 O8 [7 J IMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& V5 p) Z5 h$ Z" T6 M, G; M! ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: S! j# X1 y' }! E* x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* O: b9 g1 x( z& B
MCASP_RX_MODE_DMA);
8 Z- Q! f: G; K' H6 HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 E% p, _$ e) ^' S- hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 O5 E$ g& e# `! W) \9 A2 cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) A% ^8 c0 I* S& s$ sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 V; G9 M5 Y6 b5 `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 D; l' w, q& O! U3 H0 G3 g B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 k2 Z# I9 z$ _$ o' f" Y, ?2 CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 e+ }5 l. p" V# l, i: j. [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % c9 q/ I! j# X7 N; r% {% ?5 D1 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 E, Y/ Y# z2 \0 D C L2 n0x00, 0xFF); /* configure the clock for transmitter */
, ?, Z5 D" [3 c& I+ nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! o9 J$ G0 @; _# m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , O. K; q# t) `. t$ e/ |" [
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
: T; l, i& l7 m! o2 Z, v0x00, 0xFF);
6 `2 j8 |# i1 {) H' m/ m
3 A/ g5 }8 ~0 G3 b/* Enable synchronization of RX and TX sections */ 4 A9 ]+ \& p$ S' }+ i+ `6 O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! Y2 r: c4 R% w8 O1 r" U& o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ c" d; i+ F) J
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* E% a* q1 D& L E- E
** Set the serializers, Currently only one serializer is set as8 n+ h! j. Z* z9 E( Z/ X! ?' g
** transmitter and one serializer as receiver.4 K1 O6 t2 n& [ t1 s6 L- @+ r
*/) U; i, ^" A1 F' B$ i8 d, U3 \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ Q, Q( G5 j& h! S* @) Q6 i! X; LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** }8 Y$ S$ p8 L% t. |
** Configure the McASP pins / A2 A9 k+ V' d8 ]4 k
** Input - Frame Sync, Clock and Serializer Rx5 e" N/ ~7 D0 Q6 q6 D
** Output - Serializer Tx is connected to the input of the codec 4 a# v4 ]$ t' v
*/
; b6 G" J: H O; Y8 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" q- ^( l8 u* U" c0 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# }$ c% K0 p1 r$ H$ S% l. Q3 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! d: S# g$ _) _3 V7 R
| MCASP_PIN_ACLKX
! d" L% D, Y# P( f| MCASP_PIN_AHCLKX
" _& _0 j: z! | k/ @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 M( `* _. ^9 e& eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- w/ l% d. o6 T/ a& W% d! B| MCASP_TX_CLKFAIL . n* K0 Q, ~/ ^, Q2 b* V
| MCASP_TX_SYNCERROR' ^, K9 p; B$ S+ w1 R& Y' U' i- S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 U, C# Y6 M: o5 w0 `0 b
| MCASP_RX_CLKFAIL
! A6 F; ^+ ]2 _5 {| MCASP_RX_SYNCERROR - G% C5 \7 B8 }: p$ L0 X
| MCASP_RX_OVERRUN);% F+ x& j7 k( K8 N! l9 r* b( {& o2 D9 d
} static void I2SDataTxRxActivate(void); t$ M2 N o9 U
{
% p; Y' b) L( d+ V/ |. s/* Start the clocks */
) S; N! q# d+ ]/ p: X7 Q. A+ XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: ~, c0 Z z* c& J0 E I" K% QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ r4 C# F3 Z, F! {7 Z- W5 Y# M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 v9 z% B0 m* HEDMA3_TRIG_MODE_EVENT);+ }& ~- P$ u' w/ c- m* A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # f' A& I' {3 |; `' T+ B+ T9 d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% J; A5 l6 X- K) o( W. {: v4 DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' N. Q7 P6 v# ]7 b- s+ zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 j' g* F" `- u& K# n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: u& m$ @- [5 d/ J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( P& J4 q/ G3 u7 t' b( R, _% Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 Z4 R7 i: j* y/ `
}
( N9 X3 ^& S1 ?; K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
/ b) [# r! I9 Y* k, r- G! M( B* t8 m$ U+ F |