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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ V2 Z8 G& L0 K
input mcasp_ahclkx,
& l8 N' }" x' u& winput mcasp_aclkx, C; T2 U; E" i
input axr0,5 O F3 v3 z( R
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output mcasp_afsr,
9 \0 n2 l+ x9 S9 d3 }" z, i3 Toutput mcasp_ahclkr,
5 N3 ^2 V- R' d9 u0 poutput mcasp_aclkr,
1 r* ~( b/ l1 R5 F- noutput axr1,
* `; i; \' N0 S* h assign mcasp_afsr = mcasp_afsx;
' s$ I/ S8 J, @3 Tassign mcasp_aclkr = mcasp_aclkx;, W( G7 X; I8 D! u$ o' t. C) E1 z
assign mcasp_ahclkr = mcasp_ahclkx;3 G/ B% }7 r C/ ^. H
assign axr1 = axr0;
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* ?, C+ V9 G1 F在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' x J2 c" G, T9 `static void McASPI2SConfigure(void)0 W! S7 f4 `) Q, X4 ~
{
6 Z2 }1 B5 h: n1 V& Z9 @5 ?% z- Z7 CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 I7 V6 b) u( J& I* R8 K3 [$ \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& t8 l9 F4 |- v# l( ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; h! z8 ?: z& \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 A5 s; a! a5 V; R) d( p! Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( J; e f" b$ ~ l% j& E) `7 vMCASP_RX_MODE_DMA);
. K `1 D% A U$ ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 b" }7 i8 T% `# n) CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 ]5 N+ w H, T* l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( W& B( N( @7 U( M1 Z% E/ i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 \, ~( ]6 [9 I; lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 T6 W! Y, _+ Q* `4 L* ]: LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' T4 H ~4 f* Y, \: e7 d$ r0 M+ o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; L2 j# T x( \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 R8 \, e4 ~0 M7 W) hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 T/ t( K$ v8 p" n# y* y/ S
0x00, 0xFF); /* configure the clock for transmitter */: A$ _* n. Q6 W! Q# z3 \# [' p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 g( M5 z: e% i2 k% U {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
G! D' s1 Q3 n8 o% ?& ~" J. RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 c) ]3 R3 y) @ x5 h4 f
0x00, 0xFF);
# S' L! p* q+ A& E- B6 O
1 D. z& o n3 n& G/* Enable synchronization of RX and TX sections */ - U8 R6 I2 Q/ @. f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' i( j7 z4 n, F+ nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 L# z2 {% H+ g3 p( _; T3 z! o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) r. t+ p: D/ M P: Q, B _# |** Set the serializers, Currently only one serializer is set as/ p& l4 ~# o- T- z1 |) x
** transmitter and one serializer as receiver.& U1 E) h @ }8 x" i
*/
0 z) {. ~7 j. H4 r) o4 N" o2 N5 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 R. h6 o( T! x1 SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** ~7 L+ b/ c; ]# S
** Configure the McASP pins w3 s0 B( `& ]) F
** Input - Frame Sync, Clock and Serializer Rx4 n' g& R. n$ ?( m# e9 v0 U3 o
** Output - Serializer Tx is connected to the input of the codec
; b7 X' _3 f4 }/ _$ J$ |: y*/9 q$ ?% ]& K) j- o X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); J/ S6 _1 t( r" A% I P. {7 e4 R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 w6 R( Y% I$ ]' b/ T* [5 c7 ]+ D% ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) m5 l6 [- E8 {- ?. q, }3 I9 H
| MCASP_PIN_ACLKX
, d% z, v$ |3 T6 B4 i) l( X| MCASP_PIN_AHCLKX6 e$ C1 Z3 v* d0 I9 F# @; n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
| H$ | K& o2 kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & N" ^/ k, }, K) S. F3 B& H
| MCASP_TX_CLKFAIL ! V |5 Y" P5 k/ R
| MCASP_TX_SYNCERROR
: L- O$ z: L0 @, s. i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# W: q% ?9 p& s| MCASP_RX_CLKFAIL4 ?/ d- _$ V) W$ M
| MCASP_RX_SYNCERROR 7 P- n; x0 b+ A
| MCASP_RX_OVERRUN);
- i6 p4 U5 B1 A} static void I2SDataTxRxActivate(void)
+ \, r. D7 w* S{
" i r. [: x8 |- L: f0 d' x/* Start the clocks */
2 [6 i8 {/ Q2 h2 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 m% R& W( a, w+ W( x0 ^. R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# l; B; ^7 M/ K! I: y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 {* X g$ y. J- p! h& p( u1 l1 a
EDMA3_TRIG_MODE_EVENT);
. t+ E/ | j$ R6 o, yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - D3 w; O4 T9 D8 g$ |' t2 ?, m2 D m; n; K) j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' C) |2 C) a; ^1 n2 x) l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' Q# v6 P5 u5 E" y# N( J$ v' X$ u
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 V4 {+ h, l7 C! s+ U# x1 [while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, ~7 ^3 T3 K# tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 m1 A# M3 m3 s1 h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; b, e. v. z2 r$ y: _, ~}
2 h; w* \; H# L# E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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