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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ p3 z1 ]$ j4 cinput mcasp_ahclkx,
- X: p( T- ~( r3 W" n( jinput mcasp_aclkx,: n4 H3 R+ `8 D K2 Z
input axr0,7 o* ^' F! }( H7 g, {( ^" r& x+ F9 v
' _7 p' X( o U" a9 O2 Q/ Xoutput mcasp_afsr,
5 L7 ]! B% Z# n; s1 R# W4 P boutput mcasp_ahclkr,
1 [5 G2 E6 @' y& \+ J" _output mcasp_aclkr,
. k3 A3 l- b0 S9 i1 o( v# Routput axr1,9 k. y, f5 k' {: Y1 J8 x
assign mcasp_afsr = mcasp_afsx;0 H1 a" L$ {, L6 M
assign mcasp_aclkr = mcasp_aclkx;
' l: S/ q8 H# F) M2 E; F, H% kassign mcasp_ahclkr = mcasp_ahclkx;
& C7 y: z' |& E- `, i( Wassign axr1 = axr0;
+ \1 [! H$ t1 c# X! h" Y
/ \& f* |7 [% \1 Z. D2 S& g7 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 E: a# C/ a6 @
static void McASPI2SConfigure(void), b1 L9 z! x5 V0 ~6 @
{ }+ s1 Q2 N. A( h. [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ r5 R- m0 H; v V [* ?4 D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- N0 m7 p N2 B+ ^# u) iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ [, J# ?6 U! F& ^% HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! }* t( }5 x: Z. _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, f) ~8 [& b( C' W
MCASP_RX_MODE_DMA);. \; F( l6 _) x* ^2 a1 q/ f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" g# p* J7 d9 D- ]4 r* l5 R$ yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; s: C7 L# k$ g) b: e: k9 C5 Y& CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , t% Q$ @( r( I i6 P) I' s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- R! T1 N2 h9 |) `* T% \# qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 n3 v9 S& ?, X, `9 IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' K& r- [$ q% t1 |- m7 s8 p2 z JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% x' h1 H/ G$ \3 K1 M ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 h- H* G& ?# bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) l3 p6 K! H: }2 v. `9 N3 o- @0x00, 0xFF); /* configure the clock for transmitter */
+ _) e" R# |2 c% I" Z# B) o2 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% f; D6 Q" y0 e6 u# F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 z6 H8 `9 x% n) b. uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, q2 R( {) i# k9 a! P. i' [0x00, 0xFF);
. S/ u& E7 Z, G( L( T' \ C
* X$ S. n; f3 w/ |/* Enable synchronization of RX and TX sections */ 9 Q9 |% w% l7 n6 u! [- a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' p; ?: i+ B+ S5 n. F$ N4 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 B/ c3 o3 r g* M* K4 P+ TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: b0 ~8 }3 ]- E5 }# N** Set the serializers, Currently only one serializer is set as
' Q0 v& {! O" ~+ @( l** transmitter and one serializer as receiver.
* e2 l8 I! l4 s( q/ Q*/4 `6 s @$ Y/ T* z( Y9 \5 a6 w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& i) [1 k- w2 j' p2 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# f! R4 q) _* C. K* y- J** Configure the McASP pins - j* W* u$ d, o
** Input - Frame Sync, Clock and Serializer Rx% {. d F9 f$ l! i/ ]
** Output - Serializer Tx is connected to the input of the codec & p, y V- n) Y; I' Q+ ^- ~! c) w @
*/
- r# r; k8 W* H+ tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- l2 }/ @ v4 U* C1 A, lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& Z7 [2 b, ?1 z: N# ?* X+ J0 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 Z" N& S; x4 R: k/ d' I
| MCASP_PIN_ACLKX
' y0 |2 z, @# F: `5 i; W| MCASP_PIN_AHCLKX M9 ^) Y$ d3 j' y, J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, Y" v8 k: f# I u+ r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- q) d$ m) u' h+ O5 h2 X2 }9 ]$ Z& e| MCASP_TX_CLKFAIL
' Q/ T6 p G- f5 {- c. K| MCASP_TX_SYNCERROR1 C4 A' ]9 F+ g0 n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, B" x9 ~& K4 y, K| MCASP_RX_CLKFAIL
* {' f) {: y+ `% Z7 H| MCASP_RX_SYNCERROR 7 x) Z2 Q1 L- v, T- |- N+ l6 ^
| MCASP_RX_OVERRUN);+ @2 o2 U. Y: r: `
} static void I2SDataTxRxActivate(void)
3 ^' Q" A) ~" ^( K+ P w& r# ]{
# J8 z7 L7 m+ U& j, M l) {$ r1 }/* Start the clocks */
% {" O& I: {9 [5 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) t% a2 g" }$ l* ^" G2 V1 ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ d1 O1 P* x5 K, r) cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- A& P' ?- x7 K1 D8 T& _EDMA3_TRIG_MODE_EVENT);
6 @/ a8 M; n' f7 \9 H% PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : D. X% `9 t/ }7 S& r
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 i, G% c2 O. i' F! x2 ?: \/ O. [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 m6 T' R( M, NMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 y1 ` `8 @% Z7 b+ N! i; Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' q! k. z6 z8 zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, d8 e: M8 y" K; x4 l/ M& W ]; gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 O" m& L9 r- a9 v# S; W& n} 5 ^; x$ g9 X0 R) `) j( U2 `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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