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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: x( K# E$ H; F1 [input mcasp_ahclkx,
6 K% n' `9 F. S1 I2 h0 y5 i' E5 G+ rinput mcasp_aclkx,
- A+ I! q n3 g( y9 f/ V& _9 iinput axr0,
s. ^2 w$ H, n+ n
) R5 n1 J9 ]# P2 F/ \( B4 Noutput mcasp_afsr,3 c0 V' R* a4 W4 O: Y/ ^; h/ ]% p! r
output mcasp_ahclkr,
( F4 [( p+ M/ j! a* ]9 S1 moutput mcasp_aclkr,
7 C3 }+ C. {" O5 A& V: |- B% houtput axr1,
/ k o [& j( |; m( j r assign mcasp_afsr = mcasp_afsx;, X& Z' J e9 i; V; |( B. h5 V# u
assign mcasp_aclkr = mcasp_aclkx;6 S0 ^# ^5 V8 f% D# ]+ R
assign mcasp_ahclkr = mcasp_ahclkx;$ F: ?. [1 g% R
assign axr1 = axr0; # x1 I; ^0 E, N- I' v `' j# ]- y
% k7 ~- G Z- I3 w- }$ b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 S+ H: j0 Q1 s2 lstatic void McASPI2SConfigure(void)
) {( T4 j8 K q) T- \# \/ h{8 M+ N. V/ n& S, g( w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 k1 O/ C& [( g1 S- f3 s# W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& z8 N( [' y' E9 n% X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 b/ T7 y# p% ^; h. L3 Y* b2 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 P7 I' S2 H' a8 W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* S( C. [ ?& b# _4 CMCASP_RX_MODE_DMA);
; U, X: L- H% a: x3 X6 W7 k- {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; K9 r x5 M! G- k3 cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 F+ K6 l9 E% q! G: K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ y# h1 y. ~) v; RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 d4 M- e/ e1 b+ OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 _) g- O, d) k) g" k2 k) J" r uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ p, S2 C. b! X& K; {McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! ]* ~4 Z3 T/ Z/ f5 j9 }/ f6 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) U4 `; j! Q; z( oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* e1 H3 b# e3 s& C/ Z- J3 S: {
0x00, 0xFF); /* configure the clock for transmitter */
3 z5 n1 [4 w) O0 ^' r3 v$ l) J+ |' zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; w8 c: l( z& C2 V, o! A4 q3 sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' E7 J: A4 n0 _8 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. ?: T$ B) h! ?/ |7 j7 E" Q( I0x00, 0xFF);6 f" F( r% E( o7 D% a7 E# U
& d. D" ~% ~' W
/* Enable synchronization of RX and TX sections */
; U; }- Y: r2 Z( d1 L" z6 ]: u$ x3 zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 o4 R4 O& ]. r: x7 L& d4 rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ w6 i, y6 X6 F4 f) ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 T: v5 ]- L5 r2 \
** Set the serializers, Currently only one serializer is set as# X# @' h3 u( B3 E' N" ^
** transmitter and one serializer as receiver.
3 S4 u7 a# t0 Z& h/ x( w2 w*/
A1 ~6 _& g6 r( XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, R5 {1 r# j/ r! {' I ?2 `
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ {0 A# u [) x# Z% D/ ~, `: _/ D** Configure the McASP pins
& v! ^* r. Y. E4 e! e8 U** Input - Frame Sync, Clock and Serializer Rx, C5 e4 Q O) j
** Output - Serializer Tx is connected to the input of the codec
+ R# ^4 H. W& L( f# g*/* D7 T" r# l4 v9 u: ]2 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 A/ ~7 `* q( H+ y9 d- R, VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 _9 C! g1 L9 L- S J& wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- J% o3 \* e3 s& l) b. [, d1 j* ^
| MCASP_PIN_ACLKX+ m1 h6 q% U& a0 v5 ~) \) T
| MCASP_PIN_AHCLKX1 X+ I& I0 s5 X' ^) G% R `9 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 _9 B$ n( G( l s5 M7 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 |3 H7 a) {3 b! i| MCASP_TX_CLKFAIL
, w# i! A- s9 N C6 `6 N| MCASP_TX_SYNCERROR
, M: ^9 `2 z/ c [. z5 G: l/ G( \2 _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 _" |% Q3 S: i2 f
| MCASP_RX_CLKFAIL& X/ y6 Z7 Y8 {6 K; m
| MCASP_RX_SYNCERROR
5 ]4 D5 m* y8 C& v) m2 k| MCASP_RX_OVERRUN);
$ O; ^5 ^2 e; i' N6 Z5 i s. I} static void I2SDataTxRxActivate(void)
% Q% x) }5 i- n5 q9 s* f! t{
% ~# r- L" A! ^+ T/* Start the clocks */
% U) H) }, T, A! Z( ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: t4 J+ D3 m" }3 M% Z, V$ t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" c1 e' ?! ~: ]: g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. D/ a, H+ v4 |" p% P' r8 S/ o
EDMA3_TRIG_MODE_EVENT);0 |5 Q# z/ {: g# @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 U( r# U' f' D, f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ j3 H3 {5 ?& A. d- I" `* ^! O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 t+ F& y- r3 {$ `# h6 r/ {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" ]& e1 B4 S% ?( O9 R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- r% {+ z7 f Q% U1 J8 [$ O. W5 RMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" [. E( o1 v3 c: g$ y4 C, V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 c7 a# h* I, N}
/ n$ }3 h& h: l/ Y+ l( l" J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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