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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 C% J6 m" H+ C* K
input mcasp_ahclkx,
- |9 l8 s+ N/ y% h2 F( Winput mcasp_aclkx,
& e W: `/ N0 V# P8 o9 e! {. Cinput axr0,
2 x% d4 F: h$ c; o* J
) P% B4 T/ Q4 Q# `output mcasp_afsr,
$ D" } o) E1 c3 F, t0 K: Q0 {" A' Doutput mcasp_ahclkr,3 f; z3 F0 d; J% p4 W2 o
output mcasp_aclkr,
5 @! A$ U- m# {7 Y9 D5 b6 {output axr1," h9 F2 ~& `+ E
assign mcasp_afsr = mcasp_afsx;
/ F) g: ~% ^3 S$ ~$ I! A& K) fassign mcasp_aclkr = mcasp_aclkx;
& t# q0 \$ \; t- h2 b# U0 N) gassign mcasp_ahclkr = mcasp_ahclkx;
% k, F1 b. C) A2 P8 |assign axr1 = axr0;
# P; v: j' q1 X( D4 p( }" u
8 `0 W/ w% ]' ~* q, W$ E$ `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 B" Q9 }4 j/ }8 Nstatic void McASPI2SConfigure(void)
5 p% W7 d, P3 b7 h: E* \{' i K- g" ]* ]- s& S6 {8 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% a g+ O" C$ k6 q) ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- |8 a, L& B+ }3 n
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& l4 Z8 {+ b% ~6 v. r, `9 {8 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! I" C2 C* C! {) @0 A) @" `3 m- R' c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 t1 i0 W+ `* m: z# fMCASP_RX_MODE_DMA);8 h( b9 v, o* ~, `, q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: i9 l6 t. Z0 L. n8 k/ yMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 _8 N2 T) [/ F7 F1 `7 b& k [0 {' D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - |/ X& u/ d+ z- G1 P) ]- S+ V: ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! l- ^+ Q) z: q t& Z5 N2 t( B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 h }# e( x) F3 ], x( E8 R8 `# JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 g# a4 W% ?7 mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# b( x) _5 Z. w8 Z4 K0 O+ l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . f5 x- Z) q) {! j5 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% ]' d" ]2 N% P q( k, Q3 u4 h
0x00, 0xFF); /* configure the clock for transmitter */
8 N+ t$ S4 J$ T, o I: i pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); D* r: x2 @& {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & T) d) y/ z' j
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: q5 e. H7 J. p1 h7 }: U f
0x00, 0xFF);# H) o* M* |- {) p
) V3 o/ n! [9 r( D( q, V/* Enable synchronization of RX and TX sections */ 6 X: z, F5 h" a; w `# `" t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 r' P5 j6 B0 V3 d/ ]5 E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 f" @' c) ~" s% K% G6 v. u( I* sMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: V! ]2 p( o; P& v$ k' L& K# ?** Set the serializers, Currently only one serializer is set as
% S: n2 h1 A8 P4 G4 Q** transmitter and one serializer as receiver.8 Y% k" a- G. a7 H; O
*/
8 i! V4 I0 `" e9 g. l$ aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: |- Z' ^" g3 \! R3 p: B ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ N R9 P. }/ @8 ~6 ?. e** Configure the McASP pins ! w+ p' |5 O- Q" t3 u9 s
** Input - Frame Sync, Clock and Serializer Rx
D3 U% m) R4 d; Y6 N** Output - Serializer Tx is connected to the input of the codec / t7 D0 Z# _& \& Z7 K' s/ P- A
*/
- [' n1 n' e( C, _8 g( H, jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 S7 i3 ]5 N4 m" DMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); I& c" t; F* ?# E+ d |2 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* D2 {2 z7 w" P& s' [
| MCASP_PIN_ACLKX
) _! h5 L% y( [' o( ^| MCASP_PIN_AHCLKX
0 w; {0 Z; j E( G" a, }: || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* Q$ @: n0 L. bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* j& x. ^7 R9 f- ~: f1 l| MCASP_TX_CLKFAIL ' U; a+ K8 u+ }$ h/ X3 ~3 }# G ^4 z
| MCASP_TX_SYNCERROR( h e, ~+ {7 O( j6 f2 b8 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + b5 Y: _! |8 {$ J; E
| MCASP_RX_CLKFAIL3 `: l6 R" W0 A8 K
| MCASP_RX_SYNCERROR 4 m' b8 x8 D& z8 r8 R; ]
| MCASP_RX_OVERRUN);
% q% Q7 M: ^: [; q* s} static void I2SDataTxRxActivate(void)
9 U3 @, u7 W& r' I6 Q; o+ @8 R- P7 J- i{
2 B; `0 i, M! t8 b( I/* Start the clocks */
2 {1 W- @! H$ X X# h% pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 b( ]6 D9 x0 x3 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
|" Q2 ~" w \2 `4 I% LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- c- T+ p8 M1 l+ c
EDMA3_TRIG_MODE_EVENT);
2 _! ^6 B; |) \ [$ c0 CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / l6 w) |5 G, `# k, A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! j9 v8 s& Y" c# Z, o" C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 V, u" m6 E/ F& Y0 f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) d. ~6 u% i; ?1 @9 c. V: {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, ^$ p Q/ D& \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, w7 I$ r4 z& ~+ Z8 m4 R( N, c0 p1 `, ?& OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 L5 T) J8 b/ _) [} ) E( d0 V2 w- M' a( V2 ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 d) L* ^! u. N: G' ~6 D |