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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 y) g4 F5 D4 L% }, ~* z/ P$ ]3 Y9 ?input mcasp_ahclkx,
3 J; Y4 u1 p9 h5 sinput mcasp_aclkx,: s! x4 ~ ]$ T7 y. K
input axr0,
" ]( I1 G# q7 X$ ]$ s! y
0 N5 t& r8 n* ]* C$ Voutput mcasp_afsr," j4 E! K; Q/ Y( L+ p G- X
output mcasp_ahclkr,
6 [ X' n0 L& n! Joutput mcasp_aclkr,# t/ h0 i5 a; F$ v% |
output axr1,
, w: N! a# \8 | N9 N% B# c' y. C! u assign mcasp_afsr = mcasp_afsx;' @1 v! x) {" _- |0 U( i
assign mcasp_aclkr = mcasp_aclkx;4 I$ w, @& i. I# ?$ ?. }/ M+ y
assign mcasp_ahclkr = mcasp_ahclkx; h# W1 ` A% G
assign axr1 = axr0; ' V5 ~- D$ P& Y: |, Y
( M1 G! T- S4 s/ U2 w- f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 j8 {+ c! M+ ^# e, bstatic void McASPI2SConfigure(void)' D2 z6 @, S; L. k0 O5 |1 _# X8 S
{9 t$ x3 v: i; v2 I. M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ D# j0 t) v: f: ]" i
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& J+ j+ j5 ]. f6 @2 W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 p8 Q! E% z5 j6 Z+ V6 f- fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. ? W) @9 n' E# I' HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 r s; s3 S, Y4 t7 X0 r% K% {1 g& z
MCASP_RX_MODE_DMA);6 K) Z4 P+ q& ], B' b% n& B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- `3 ]) s3 W- i! w; k' N- F$ u" sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! E3 }2 M: s: W: O: W1 D! q9 I4 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* J. B+ C1 j# }/ y3 q/ wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( z- w- k% e* a. z1 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 @+ F) p ^: p; q# RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 W3 `3 u. k+ ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. n+ _0 e3 G% O. t6 b9 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 B1 C$ k4 X, q' A: Y' N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 O/ M9 r; M# N4 f% p
0x00, 0xFF); /* configure the clock for transmitter */
7 o/ R5 g4 @6 ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); |0 \+ o6 ]# k. `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 w6 y4 ], H1 V& y4 J# F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ z% O: v3 G6 R" F, ]
0x00, 0xFF);
$ o, \% |: ]: |8 g$ R, N+ Y* M6 E( e# \: f
/* Enable synchronization of RX and TX sections */
' E: Y. M! Z' R4 Q) b1 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* p, C% j# Y8 k) P- _* v( eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& d# ~/ F" {6 A$ F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 r f8 ]" @& Z: h
** Set the serializers, Currently only one serializer is set as# ~! U% o& E5 |7 C6 H+ [$ d$ t
** transmitter and one serializer as receiver.
8 i2 S+ F7 F/ j8 B4 n*/
* Q* n7 T- i9 T) H8 q: \7 G$ ~8 ?1 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 s4 u3 u( `# W5 U4 y/ iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( ^5 I& Y W$ E% t5 t** Configure the McASP pins ' O6 I7 {9 H) I2 X h, P
** Input - Frame Sync, Clock and Serializer Rx7 m0 K" |9 ^- C# f: q8 f0 P7 Y; f! F
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ o: C( H6 |$ Z# R! rMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ K. l) B8 s- U) ]. x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. k0 x% \7 F# E+ U u" R| MCASP_PIN_ACLKX2 ~. O9 V! E" E1 q A
| MCASP_PIN_AHCLKX1 a! |! z2 E% X; ]' y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 j. d H2 ?6 v1 S0 `5 h1 a6 H }5 Q1 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR e5 ^ L; \' N$ D5 ]
| MCASP_TX_CLKFAIL
, J4 j, }5 U8 y3 j, E| MCASP_TX_SYNCERROR
- e! `/ r/ N/ `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - }7 S. n3 \8 N, ?1 H$ U/ N
| MCASP_RX_CLKFAIL( W. L' b5 R2 d+ x6 X. v
| MCASP_RX_SYNCERROR , d+ i2 ^; ?& h7 O
| MCASP_RX_OVERRUN);1 m A2 ]. b* ^. f, d
} static void I2SDataTxRxActivate(void)
U2 r4 o1 d" ^, n; M( y& s. p{- r$ H' w8 O! u4 c
/* Start the clocks */
+ {# O/ z/ D/ XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ T( E; R1 `3 |6 n" {7 o! |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) }. A3 t. y6 `8 _$ h% _& j' f6 C5 j* j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ s) y7 i5 N P; a$ g
EDMA3_TRIG_MODE_EVENT);
; W; c$ |" l) Q* g) Q) L, BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) B: P5 B/ [7 y6 {9 e( Z- J, e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
t0 j. V- |- q. w0 G: WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 ^3 a0 Z: i x& B1 N8 _7 [9 b' D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- |$ G4 }7 a9 z4 w, x9 B: F$ @! s7 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! g: r1 {% s" o9 H5 G& L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 l( ] x9 w5 @, V0 [% [; h* g" S. \- z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ P" F: b& L( W% N& I3 T2 {
}
6 J% K. ~* c) k' ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % ^, K# V K( @5 R$ j
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