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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," t% x& ~& q3 I5 i+ D. p
input mcasp_ahclkx,
" B# U+ } H1 e) J% j( j/ u5 qinput mcasp_aclkx,
" @' c9 `5 \1 @9 J' L9 F3 [input axr0,6 [% W1 D3 G6 M3 I9 p
/ d$ @. P/ X; \0 V+ Q
output mcasp_afsr,1 S8 H/ [0 i5 D4 ~2 A4 q( C
output mcasp_ahclkr,
3 n8 H' ?* X( \$ l5 U5 M* M2 Boutput mcasp_aclkr,4 m' n; k0 m5 L2 A/ L" U. Z
output axr1,% u/ M. u) N& F; Z% I; K. g
assign mcasp_afsr = mcasp_afsx;4 ~+ O* ^6 f1 \7 V- W
assign mcasp_aclkr = mcasp_aclkx;
3 k( _4 }9 X: a' ^' N$ V! [assign mcasp_ahclkr = mcasp_ahclkx;
9 j7 l$ J8 p9 \4 _% R, j. U- d/ @( dassign axr1 = axr0;
4 F) t- m; Y7 S6 r8 ~/ a7 `- u+ t6 _' R$ c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 S' P P, k2 H. h& n9 G0 K
static void McASPI2SConfigure(void)) V5 Y# d3 Z4 K$ [
{
7 H2 ]. O0 A$ r+ y* B0 wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
, q3 x9 @& w8 \0 M. YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// ?5 `3 Q, S2 C5 ?+ K+ S5 ~0 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% ^* O3 H- D- N2 G* s. VMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
V- E2 ?/ X. `! {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 x+ g) K. n# D8 t3 GMCASP_RX_MODE_DMA);9 Y D2 s) a) n5 Q) L C/ L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- C; t5 m; v( `* CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ l4 U. M' Z9 w" m4 M1 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ d+ y, U8 C5 r0 p( N$ mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# h$ v( k, q4 b, H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 K7 @$ x* \4 L, e# a% G4 r- G) }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& f: r3 B6 k$ {9 J4 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, u9 R o e0 G6 ]* u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / s- Y' O0 \1 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' j' [5 _# ^+ S1 }2 W7 O" [0x00, 0xFF); /* configure the clock for transmitter */; G$ H5 u( ~8 ^/ Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. U4 @1 X! E7 D- W7 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 D" K4 s9 n/ E$ J- s4 P# @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, F- ^* ? I/ l! e2 @
0x00, 0xFF);- C2 Z4 w! V9 N$ e/ m. P
# y- W& i3 p6 J r/* Enable synchronization of RX and TX sections */ ! o' } _* V9 e2 k3 Y2 s- L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 E+ h$ |; K) r% v/ G% g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' k( u; }7 L' UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 {+ Y, D5 O. b$ z8 k
** Set the serializers, Currently only one serializer is set as
' D. ~( ]* T' O9 c/ A' l' r** transmitter and one serializer as receiver.
- @ z. t, [. L- S7 w- b" \*/, ?1 g) O" ~: V! S( `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, J( K, V$ D5 W) Y% ?
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 O% @' @$ ^2 k
** Configure the McASP pins
' g% @/ o; H; m: s9 h3 W; j. m** Input - Frame Sync, Clock and Serializer Rx
+ h7 m: `: l p3 B! W( A** Output - Serializer Tx is connected to the input of the codec
# H7 G w- Z) z/ B* ^*/3 v: \( [5 e( D- Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# w" K2 Q+ c* p6 w8 \McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* a9 E# g0 Z+ [# C6 OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 T, `9 ?! t2 I* P7 {0 ^# i| MCASP_PIN_ACLKX
$ X8 P* E/ E+ a7 i( J6 P7 @5 z% d| MCASP_PIN_AHCLKX
# {! b. q3 A' {5 m* m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 P1 E* t2 f$ E( [) s; FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' _& O: \/ C9 S
| MCASP_TX_CLKFAIL
% _3 o% x( x% s1 v8 [; I7 I| MCASP_TX_SYNCERROR5 Z$ @5 W: J2 B3 m4 w0 l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 L# X; v6 g9 O) W; K/ {. @5 V [
| MCASP_RX_CLKFAIL6 o+ d* d, [2 Q) o8 u: V2 l3 ^3 c
| MCASP_RX_SYNCERROR 8 F8 J* O" t& i( x, h0 L
| MCASP_RX_OVERRUN);
) w# n/ e& o! |! i7 {& }} static void I2SDataTxRxActivate(void)1 t u6 |6 i! m& O/ r% E" j
{& \' E7 C1 n: ~1 t1 R; ?9 G" E! J
/* Start the clocks */
7 C& t/ g& Q0 `. r, rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 r+ _. J0 X5 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( _' L; u# Y! A% ?' mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, t( P* f. ~" X J9 _- ^6 V
EDMA3_TRIG_MODE_EVENT);, c- Q) b e# X! k- ?! w3 Q7 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! v, Y% }% |- d3 N F, A( R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 u* S: O5 b M8 h( @) v B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; y0 {9 O% ?2 u# B: d5 x, O. W6 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 ?* h: ]/ p* T, dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 I& t+ T$ M- h" L2 k# BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 _& G9 ~. v5 L& k* C% A4 p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, a! D$ j0 E8 O# L0 K
}
2 s }! s2 w9 w' e% o( Y5 B6 j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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