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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ T0 O$ c/ q% u# N' T2 S
input mcasp_ahclkx,
- A( t, h* [$ W& O0 Yinput mcasp_aclkx,% A& B- d3 S: d
input axr0,
; K+ R5 K, a! b( N' M
" i" w, a# c7 ?1 Toutput mcasp_afsr,
( N) f: J* `4 r+ houtput mcasp_ahclkr,
3 A E0 C5 z2 Uoutput mcasp_aclkr,
1 D3 }- l" V; o* ]3 [9 C! A6 xoutput axr1,+ [/ @5 C9 i4 `4 B: Z/ M7 l/ p
assign mcasp_afsr = mcasp_afsx;
* ` {- y' L* U' `assign mcasp_aclkr = mcasp_aclkx;4 i, h/ y) } q7 ?1 q
assign mcasp_ahclkr = mcasp_ahclkx;
" V# p* y1 k. G+ W/ Passign axr1 = axr0; # h: l1 F1 @' o! N& s8 n
6 `2 X8 J2 n& {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( j: ]( u* j" A$ \( q3 j! L
static void McASPI2SConfigure(void)# y+ p& s% E! Z4 K( E H
{
$ ?+ q; P @& n* ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 k' P/ E" B+ ?1 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 U V* p! F3 p5 K4 \5 L* z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" }$ `3 r0 A: [& e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" N' t7 ?* D- j8 m1 g8 z" t* K; EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' t1 K/ y: o3 W# @9 K! `
MCASP_RX_MODE_DMA);$ O) f3 }8 Y1 G: c. x$ F+ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ]3 H& G& T. o- j. x* \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# D$ U t- g) Q% m+ s0 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . o* V! Y- p9 f" c2 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 c1 y8 s$ ]8 s' p7 d* i. m7 Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' n5 V `/ O& o. X8 k& l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ^, m5 @, M& P4 U6 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' _& d) V! n: l3 c4 p" oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Z& E# |8 y# v* n" H! k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 w2 q9 c8 H7 T) @5 J8 t6 ~' u9 C
0x00, 0xFF); /* configure the clock for transmitter */
2 ?1 \" A% f. q+ uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, v0 e3 ^( v( N7 i3 N3 Z' bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; t# l: w9 b; O- Y- l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 E5 V% I5 k6 \8 `
0x00, 0xFF);
( P: F) \0 l3 r0 c3 z
* _% m3 ?+ G. X) [+ V7 @/* Enable synchronization of RX and TX sections */
+ d! ], O: \ l9 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 {# P9 a! ]* l- m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 f7 t& j8 U# [7 \: DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# ]; l7 p: ^ M* Q# C
** Set the serializers, Currently only one serializer is set as
v# S; ^) J' ?** transmitter and one serializer as receiver.
3 S) F5 \. [9 \/ }9 ~0 s( ?* _*/
5 X7 K$ d! u( uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: U8 V7 B+ o4 z& o9 I; t! E% SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 S% _3 E: L# S- U# @** Configure the McASP pins ; ?7 h$ j4 M6 c
** Input - Frame Sync, Clock and Serializer Rx
3 {5 G6 ?8 a( P' [** Output - Serializer Tx is connected to the input of the codec
: B9 d7 I/ Z) O) ~/ e5 ]+ ?*/
# V' Y. e# G1 t7 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- `8 j4 Z/ t) q, R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: f: f6 z) [" {/ B0 A0 j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( g- T+ `* ]& o& N$ J6 c. h
| MCASP_PIN_ACLKX: _8 g7 r i+ R0 j) v& `9 o6 S
| MCASP_PIN_AHCLKX
, A: R! t# Y0 h7 f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 L9 c. T I+ W0 G% T z. J3 cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : b+ }) X. {" A3 V) `+ H& U0 T
| MCASP_TX_CLKFAIL & R6 k$ _, N; ?9 R$ ^( L7 M
| MCASP_TX_SYNCERROR
1 o# B8 A+ H1 C2 g4 q/ m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' O! E' ^" @5 f3 u) Q* U! o, W& L9 ?| MCASP_RX_CLKFAIL( m; B1 J0 U8 W1 q* H( D
| MCASP_RX_SYNCERROR + M t% k; d7 I* O, t' j
| MCASP_RX_OVERRUN);
! g& L4 [5 @% t; n% X} static void I2SDataTxRxActivate(void)2 w! H( t: f. z! k) _* W( C) M
{* A9 Q7 b; n$ S0 X6 m2 x* I9 t9 t
/* Start the clocks */6 C2 h% E9 `+ B- |1 ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* s$ q$ w* \4 o; T& H) t2 ?% C5 cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. `4 V: S# }2 P8 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ V( E2 g+ c3 i H( H) _, REDMA3_TRIG_MODE_EVENT);
( ^' Y4 f/ v! x NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' B% I3 Y6 I5 V LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: K0 | L" S" O* i% S' RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 U8 p1 E U& X0 qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 r+ Z& R5 [4 F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ ~7 K% e( t2 E* V" P7 w5 X5 I! y6 dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& d7 p+ i" m1 X! H8 G$ E, J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- s( k4 N7 Z. h2 ?}
6 u9 J0 m3 b1 a. T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / @4 w% N; H8 X8 m
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