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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" v/ s1 Z# i R) G0 X' N" B8 m1 Tinput mcasp_ahclkx,3 e( J3 c t1 m
input mcasp_aclkx,+ W2 G' A7 t, s8 ^, Z' {- I6 J1 k2 u3 _
input axr0,, n3 R ?, {" x8 t8 n
. x# M2 R0 y2 g: o( s
output mcasp_afsr,; y) I* y0 K- v! |7 I" s6 I: E0 _, W
output mcasp_ahclkr,
3 b9 w9 m" N: n* V0 c( Doutput mcasp_aclkr, P+ i6 E T: E3 r8 B9 d
output axr1,0 ^/ Z) y, t7 p. k% u& s
assign mcasp_afsr = mcasp_afsx;' a& C) ~1 }( ^% b* ?
assign mcasp_aclkr = mcasp_aclkx;
. g1 M/ f8 m7 c: eassign mcasp_ahclkr = mcasp_ahclkx;0 g! L. K8 V2 Q# w8 D( H
assign axr1 = axr0;
7 J u2 z4 z8 u+ p# z$ A# f1 x) `- j% W" _# d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! `4 P$ {7 t$ ^7 \" f |static void McASPI2SConfigure(void)" z; x* a2 b& F; R
{
( _8 x5 M( q! T* j2 Q% ?9 e" |McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, l; e4 `$ k7 l$ ^& { ]4 ]4 C, TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: \" @) k4 G; H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# [$ i6 r; F1 v6 }+ t. ^* [- O& u/ NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 p$ [) t' U [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% N' `; K" @5 @) Z
MCASP_RX_MODE_DMA);
/ @: L% [! {' C4 \1 \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* p& y1 n- O& e0 RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) l9 v. @0 L$ o+ D4 J% v' LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 X- Q- _8 t) N, W& \: i+ QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ |2 @5 n# {& _- L# ?0 I. t4 C9 L( S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 \3 `8 ~7 K$ l9 V4 v2 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" _* Z; A2 x- I {2 m8 V6 {; j) N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 k7 |7 T# I7 L7 y. I8 W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 |, L$ n1 S! B X9 ?7 N$ z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# z4 j; \8 N/ Q7 l t6 y0x00, 0xFF); /* configure the clock for transmitter */9 | s2 N! K# v& ~: V! D0 ^1 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ Q- _8 Y/ a/ @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( _" `+ c/ J/ F& a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ j# ?, ^4 A! |# l# [" v7 E0x00, 0xFF);
% j8 M6 p: q$ r. ~% j5 ]0 x3 ~& W! n9 ~; e
/* Enable synchronization of RX and TX sections */ - J# Z* U, u5 z- A- b; ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, Q' G! q( J7 o' Y [3 `! W* w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 I! m4 [- `9 t- [' Y$ a! r: dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 O7 Y( T3 E% |' B** Set the serializers, Currently only one serializer is set as
2 u x/ S% a9 h# G& |** transmitter and one serializer as receiver.
6 z2 V, l. p7 g*/" n: j# b- m; n, V6 R1 ?" k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 b2 Y$ s" f' R9 p" r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' n+ E/ O2 Z5 {
** Configure the McASP pins
) X8 r4 A3 L& h! c- G: F: k** Input - Frame Sync, Clock and Serializer Rx1 @# n& }- K* |& L% `
** Output - Serializer Tx is connected to the input of the codec
+ L* }% P0 g" S C*/
3 Z; [1 C, {* z4 c% f, p* zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: F; Q/ @$ {. Y" f. o* G& ^# i- q0 LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: ]8 b, k3 o+ a" v1 H+ b9 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ @3 Z4 S8 \) K1 G2 Q$ W2 X| MCASP_PIN_ACLKX
# s- p) C, `7 z+ x( s0 R% Y9 C| MCASP_PIN_AHCLKX5 V1 s$ p: b; q5 e! \- V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" M: s7 `4 B- u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 \1 W, W; Y! P8 E7 o8 P+ `9 e- W3 @
| MCASP_TX_CLKFAIL - W/ P& k$ b& a/ j
| MCASP_TX_SYNCERROR) ]$ O" ]5 x2 L$ ^
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ ?1 H" Z$ M$ x% i$ s# R| MCASP_RX_CLKFAIL
& F0 \3 T! u* x: J1 I7 w| MCASP_RX_SYNCERROR + x0 _ Y% U& q7 ~7 f
| MCASP_RX_OVERRUN);
7 i6 A1 D! z6 Q} static void I2SDataTxRxActivate(void)6 {& Y# v1 X0 D" ~1 F% Y
{
0 a* ?8 ]6 Y. B) E- V+ C/* Start the clocks */- i! H4 i3 o* `# F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ H- m& D2 J: ?0 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 F0 E- y6 X! U+ ]: s+ V6 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 g- I; z9 z1 g) Z6 }* U
EDMA3_TRIG_MODE_EVENT);
" }4 o/ u% X' ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 D, i) ^# e/ s! zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& ` T7 N: N2 [6 K+ iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ j. @, F/ }# o J# t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! [4 O6 |" ~0 f1 M8 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) a; f% t8 B! S5 j9 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) `& C. N0 S- h9 c" E0 g# W- BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: ]( z$ k0 x k. F- Q+ W: ]
}
6 _: P) e9 n1 M: T( T9 B/ d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # a8 f4 s1 h9 n; r# ?8 r
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