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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# c+ F' D+ F! Y" k) K/ ]1 w
input mcasp_ahclkx,
% U8 L1 K5 K& I8 l Pinput mcasp_aclkx,/ g/ u, E4 m2 [. z# b& N) n7 \; L% e
input axr0,- d+ y/ W2 P' c% _* A1 F
4 i6 H2 s( C$ D& Q8 k9 Qoutput mcasp_afsr,; F+ k9 s Z% d
output mcasp_ahclkr,; K; O6 N9 M9 Y) a# H0 _
output mcasp_aclkr,# k* ~ h/ g$ i; {& x' m3 u1 p0 E
output axr1,3 `; L5 h# ~1 o
assign mcasp_afsr = mcasp_afsx;
d( K. Y3 u% C* Z+ G# t; Kassign mcasp_aclkr = mcasp_aclkx;' h; ]1 [% x3 Y5 y6 k
assign mcasp_ahclkr = mcasp_ahclkx;
/ y/ ~; y( Z8 l/ [0 }- `assign axr1 = axr0;
3 p; k% e+ y0 u9 N8 Q5 e. D5 q/ n
3 z2 U' u+ ]- b2 L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# y" b( A B2 P2 Z3 ~static void McASPI2SConfigure(void)
. R% I1 Q0 ? E, g% G( J{
% Z; p _9 G* oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ Q; l4 X! }$ o( i! jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. U3 i- X) t0 [+ {! GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" Z* ]! u6 [' qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! B6 z: P, x9 ^9 L2 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- p( y3 _0 f: Y" }) @) p( R" lMCASP_RX_MODE_DMA);
9 |' m' k" |# M& AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," b; S# o6 r1 P$ ]$ G, l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( P5 _! `2 `+ ?3 z5 ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 C! n' d5 g6 W3 P; J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) L# _# |. D! L1 Z; u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
?: F& ~1 l+ k0 J1 t/ Z# J, uMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( t& i( e+ T! _% B- s8 t1 J7 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 T4 N4 B- Z6 ~/ `) F MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ ~* x' Y" _" V. L' O9 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' w# f5 J9 K8 T! G% X, n% C& p
0x00, 0xFF); /* configure the clock for transmitter */! f7 Q, K, ~6 w$ u! p! G& C
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( f3 E. G- g! B, vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 g5 |5 I4 f: m% K( k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ e+ P0 }7 w- ]8 a% L9 G a+ l* Y8 G0x00, 0xFF);' u# x+ l# V0 C: \
# u% ]* _8 ]5 R! F4 O# Z+ F
/* Enable synchronization of RX and TX sections */ ; a: d% p1 b1 ^, \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 }% F% F% U6 s0 w R8 U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, R' @8 w$ w% O( ~% e9 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& X) H' D; }. c! l) Z** Set the serializers, Currently only one serializer is set as
; \7 Q; R" _! Z- l/ i4 o* |** transmitter and one serializer as receiver.1 f y$ A3 p: `0 `# |0 o+ _
*/
) i+ b; S( w1 @" }4 T% k( SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- X" g6 H. J" p, m W) @. U; aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 d8 c" }( c. }0 o** Configure the McASP pins 5 @* a3 X% V C
** Input - Frame Sync, Clock and Serializer Rx* k4 Y$ J! }, ^6 N; x: S
** Output - Serializer Tx is connected to the input of the codec
! Y2 `* T0 l0 s9 @; E0 f: [! b*/& \1 W0 t- n5 N* w5 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# |* L$ ]; O5 |# a* T' H1 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 k& W# {) J- L& \+ H1 sMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: E0 ]! W5 ^6 X! B| MCASP_PIN_ACLKX
( A2 x1 Q4 [% ^& f| MCASP_PIN_AHCLKX: L- ~# J# J [: I( {0 S4 L
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 {: x( a5 `5 f7 t4 ^ A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 A( O" n, f6 B% J" O+ O- P a; f
| MCASP_TX_CLKFAIL
! q9 t- W# y! x" Q: H5 \| MCASP_TX_SYNCERROR
; Z5 W4 \5 R1 ]6 _; C4 }+ H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 @: M* R( V2 Q/ _+ H
| MCASP_RX_CLKFAIL
; T$ G+ D* l7 w# l5 m| MCASP_RX_SYNCERROR % w( ^7 D2 C4 ^2 `. D$ ?
| MCASP_RX_OVERRUN);
) o/ b2 p" b2 N' T3 r K* A} static void I2SDataTxRxActivate(void)3 W* K$ \7 _0 y; T2 ]0 u. t6 j
{
% Z- J! H' ]! Y- T- Y3 k/* Start the clocks */
( \3 j8 i8 Y* O- ^9 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* z7 Y [' d. M5 ^3 T( d/ [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* s- v% f! B' a `( F* B3 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 k) {8 Z' ]/ h4 W$ fEDMA3_TRIG_MODE_EVENT);
& m7 { B7 C' XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 A5 M2 T2 n% G; O) |9 q$ F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* [- H# T: l: l% H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) C/ V. X2 n" u+ b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 `- E# v i" {) G' m" |while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& k3 |% U( x, I
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. M0 J, ~6 u2 @: ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 q) W* I1 {9 \4 ]' h0 Q& [( W! R0 G
} 4 A- d" A' S0 S: J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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