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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 i4 D/ s4 S( j( a: f
input mcasp_ahclkx,
. x7 z8 d5 `! O2 t9 zinput mcasp_aclkx,
( y+ r1 O6 `4 W) ^7 Z- o; ^! Pinput axr0,
4 m; D1 G9 X! }! h$ D0 B! p3 _& f1 B% C" V9 k
output mcasp_afsr,
& [: ?6 T8 z" ~" P6 W7 `$ O2 L: eoutput mcasp_ahclkr,+ [$ d: ?3 ?& g* W. l. u% E
output mcasp_aclkr,8 @+ Y! t* T' I s* b
output axr1,% q2 f! j; i9 F+ u3 a: f+ ^2 l
assign mcasp_afsr = mcasp_afsx; b( W8 _. h1 z0 F
assign mcasp_aclkr = mcasp_aclkx;7 A/ P$ T: p. [4 S. _2 X
assign mcasp_ahclkr = mcasp_ahclkx;3 X0 Y' w7 l7 t
assign axr1 = axr0;
% f; t$ O4 U% z8 H+ F# h3 R2 W- { z% U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 D3 L, [ U0 Z% tstatic void McASPI2SConfigure(void), h" O' G; T& R
{# e/ q4 b, t- E ~6 R5 z! i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 |. X$ y8 X4 k" o, D( z X9 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 S* E- k$ Y. VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 h' m2 H5 S: e) Z3 HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! I; w$ }' D# r0 _& ^) dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 M' z1 z- Q% C" x/ MMCASP_RX_MODE_DMA);) e% J/ P S2 c3 u3 Q4 r9 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 w* [4 |( e( r& o( @& DMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* c0 ~# S& O+ ]. i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " ]0 L i+ r) n4 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ R# r2 _3 h: P6 v4 |8 y. W$ s' QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: ~. q6 e$ b) z, T3 A9 w- oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* ]$ T( q, @" T* k) E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 b! }% C5 U7 e+ `, p2 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& V- S' m/ c8 ~0 ~. T; QMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! a" w$ j4 K# @- \0x00, 0xFF); /* configure the clock for transmitter */
* P! R8 e7 ~: p! k2 W$ LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" A K P% B4 U$ t+ L1 `
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; u+ T9 w2 B$ a. X( `6 u3 M! g% T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, U O( U- v7 s8 B4 e0x00, 0xFF); Y. U, [$ }4 F+ f# F9 ]; A
# t, x4 a7 ~: d2 K3 t2 J* t
/* Enable synchronization of RX and TX sections */
/ [5 x0 c) ^4 C: H$ j" _& W- JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- P% ]7 i2 J: Q1 r- H$ T( ?! P1 nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 M4 V) m3 n4 U+ Y; G9 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 F+ p" @6 ~& K
** Set the serializers, Currently only one serializer is set as
" z) }0 u/ {, |3 g6 v" [5 }** transmitter and one serializer as receiver.
+ B/ ?* @7 G3 y" C0 b*/
: u, @" D2 V8 U, R% m& `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! i. O5 L8 g' D9 d0 ^% N4 e( A1 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: g' t# T F9 ^& y$ A+ P' ]** Configure the McASP pins
. L3 H/ F e& O" y4 Z. c ^** Input - Frame Sync, Clock and Serializer Rx& R* T# G8 I$ |) V+ c
** Output - Serializer Tx is connected to the input of the codec
/ Q. j7 B+ s9 z*/; S6 [& Q2 r [+ o2 R# H0 P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: Z; k; m& F, H+ G7 _0 J) X5 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
K) ~/ J9 l, Y; o: R- E+ rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 o$ u/ |, j8 \8 |
| MCASP_PIN_ACLKX4 v- [3 W$ R, `/ P
| MCASP_PIN_AHCLKX1 W; X, \$ {2 N6 N+ c, D" v# J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( o+ r# P& D" r6 b8 i" I4 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) L; p9 b3 y3 K" Q! J. m6 ]' E| MCASP_TX_CLKFAIL % i' v: S; A& Y! m- U& k
| MCASP_TX_SYNCERROR8 f# M) L, G# C' \. h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 b& G& z5 I6 R9 i0 L0 t* d
| MCASP_RX_CLKFAIL" ]& Y% A# `% c
| MCASP_RX_SYNCERROR 5 t( N$ Y7 J2 i
| MCASP_RX_OVERRUN);1 h* _- j" D0 ~: i
} static void I2SDataTxRxActivate(void)- v- W' ~7 \# i" E# w4 v
{
6 Y, h* w% H) E# j5 T1 l/* Start the clocks */
- U; x2 l3 I# K6 I/ R6 X4 BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, T& y! k# }: O) X( L: i# x' e& I9 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" E, }9 F( f! m% @, MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( Z" m/ H$ `' U# ?
EDMA3_TRIG_MODE_EVENT);5 Q* n# N1 b: z2 j" m( g" T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 m( o7 B) E. {% l4 @& ]. EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 A4 t/ ]2 H( B- Q+ oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ i# v0 ^2 O) S& E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. P) h/ O; K/ l+ _& owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ t2 M, q; }( ]3 `4 `# u% |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# ]: [! w1 W( M: N- ?& ?% QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ z' A) V4 j5 ~) n+ d; h& u
} 0 A- i# t0 {% n H& I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 O+ E7 x$ V7 \; ~1 Q& ]
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