|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 v( b: [3 J, e. }, a
input mcasp_ahclkx,% u" h2 N }! \. ]; X# G; u- A: a& [
input mcasp_aclkx,
2 ?$ h" i p, W1 I; `" A/ {, A* q) tinput axr0,/ e/ G) K5 M0 B6 S. Z+ g4 b0 O# c
2 w$ Z+ \( x$ F# j7 m7 B+ Goutput mcasp_afsr,9 J2 C9 Y8 Y, M, I
output mcasp_ahclkr,: S( E4 \1 ~; u* k. o ^. @
output mcasp_aclkr,8 _3 Q5 y" _5 X2 G
output axr1,: f+ ~3 z; r0 t0 d8 l9 {2 G Q3 }5 t
assign mcasp_afsr = mcasp_afsx;
) v# l) `/ n: _ Q# v" y; Sassign mcasp_aclkr = mcasp_aclkx;
* Y& o* a) p$ u: u( E% r! g. h5 Xassign mcasp_ahclkr = mcasp_ahclkx;1 ^9 U8 }0 ]9 e; A2 k/ \- T
assign axr1 = axr0;
( Q- n# @+ X8 M6 g# Z% f+ @, Q* o$ G j" z( ^$ Y- ]+ I" y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 ~8 g: |6 u. S
static void McASPI2SConfigure(void), t. b5 ~8 |" t; R0 W
{
8 Z! h0 |2 q' v* @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! h5 S( d& ~# D9 NMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# ]& f, ~1 U! W$ FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' G' ]: S2 ]$ _* YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 ?7 f: y# Y7 d# x9 L0 d! ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) U4 _8 v9 X' p4 K1 x4 ~8 A
MCASP_RX_MODE_DMA);
$ I) ]# U; [5 PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- T. H+ n- e& y' {9 t# j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. A4 K" l0 v" _( j6 K8 v$ K9 w4 ^* d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! E& K/ ]! ]) t# j8 p( y0 |$ EMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' |0 i9 E8 L b' l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : H% q9 V8 E. p9 `: ? h! g
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( z* `/ U# ]) p& t: C: z; D5 Y0 OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 z, L( p3 r. b; |6 H) P9 p, \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & g A- W* q9 q+ c8 }0 S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' ]7 G! r% M5 [' M6 H
0x00, 0xFF); /* configure the clock for transmitter */
- L5 I# j2 x4 u( ^# @% PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& u/ Y" K) p3 ^4 w1 h. OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 j1 L) [4 o" t9 K. ]4 o lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, S, X {/ P5 h0x00, 0xFF);
- w( Q- i% J, v" f! f; U3 P) A
& R4 P6 X9 j1 `- E2 g) P0 }/ C/* Enable synchronization of RX and TX sections */
% a: a4 h" r c7 S5 A& ^2 bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 O; H! o7 p1 [: {6 c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( r d% f5 p1 d0 `$ NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ i9 n0 {5 z# ~' Z: V1 B
** Set the serializers, Currently only one serializer is set as
% f1 B/ Q' \0 c# r. _6 `, l! j** transmitter and one serializer as receiver.
+ c$ n2 d1 e, |9 f. Q& @) n9 F$ T*/ \9 p+ [5 J* N. X T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 l" T/ P6 N: r1 ^' o, C; p
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 j1 p4 d' F- y8 @
** Configure the McASP pins
. u4 x6 Q! a4 W1 k" t0 V6 r** Input - Frame Sync, Clock and Serializer Rx
g2 I8 W1 F! Q7 }% m+ q4 Y& ^7 x** Output - Serializer Tx is connected to the input of the codec 9 `4 K, |! o" A- ~6 W" b/ t. C1 g5 [
*/4 u" E2 \' N G7 w+ W) T8 D0 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ Y: Q8 l4 ~- Q0 _0 j3 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: n' r! f, |, l I9 ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- |: y4 p/ b, E: D. ~( y| MCASP_PIN_ACLKX
0 M* ^$ v; z5 P( U* Q7 F ? @| MCASP_PIN_AHCLKX
+ l0 p! R: P% v: h$ Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, ?' A1 |+ A- FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 \" F4 o+ `2 O4 P' R$ ?7 |1 N, S| MCASP_TX_CLKFAIL 6 r3 R2 x% T1 T' P8 I! q1 J* B
| MCASP_TX_SYNCERROR) B c1 e, ^" z0 D1 d! B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 H! q' K0 R( |7 q: ~$ z3 W% r| MCASP_RX_CLKFAIL9 r% o2 N! ?$ a. S$ p; I# r, O
| MCASP_RX_SYNCERROR
" i* Y; l* f# n% g" A$ F| MCASP_RX_OVERRUN);* Q5 H4 U% n6 P5 ]; i- K
} static void I2SDataTxRxActivate(void)3 q/ I, z3 ^, ^0 L
{
' R4 g, Y" S a7 `- O( m/* Start the clocks */1 J* h, x1 t" p/ j t5 x* o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) I z' D N6 g8 w4 eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 [; A8 [8 G) n. @* H; J4 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 ^# d! ^9 c5 E) `+ FEDMA3_TRIG_MODE_EVENT);
1 ~2 E: |- O$ g, y& dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' U n/ }0 ]; K9 H- h4 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 B/ S, a: K0 z) d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ ?0 q4 U! r- k; l9 G" u' }$ qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 x1 y$ |/ `. m/ \9 B
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' Z8 Q9 A, d4 ^+ `1 n' {1 X) @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. h6 K8 g) d! F+ {0 }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, ]" Y* I9 S' p5 [} 6 `- L5 r! r4 [# v3 \& O9 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
' W& R) V& I7 F4 z1 f |