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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 x! M0 M/ }4 B
input mcasp_ahclkx,
' n5 J- i6 h5 d3 `7 Z) Cinput mcasp_aclkx,% M) R0 x0 @& e4 r' D
input axr0,: G) V R" Y9 g. F9 T" I
" L/ k+ n! o2 m# J( g7 ]# p2 E
output mcasp_afsr,4 C$ X( I3 T$ K8 ?
output mcasp_ahclkr,9 [; Q3 A1 J$ T9 o% K" q
output mcasp_aclkr,
: u/ h" s( B, W1 Xoutput axr1,& e5 R: [/ ]7 z* J& J5 h# `2 |
assign mcasp_afsr = mcasp_afsx;1 g9 A4 W3 b( w2 Y7 L. K
assign mcasp_aclkr = mcasp_aclkx;9 {, i @& }! [0 i8 S
assign mcasp_ahclkr = mcasp_ahclkx;
2 F) U3 e& D H7 z/ w: O, Z0 sassign axr1 = axr0; + \" o- Q$ }. s( P( r7 L3 D
0 U9 u4 n6 {" }" ]! M2 a0 h c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , _' }7 s3 N$ P. ?3 Y. S6 R
static void McASPI2SConfigure(void)
4 S, _1 V% d/ z# C; X{
" `% z j8 R' s+ wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* g. d. Q0 l( q- I+ ]4 X4 Q* l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 _: C+ G6 c I: G! qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 F( h. J+ }# c" w$ @: N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( ^# n8 @; d5 d d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* Z% ?* i$ q2 X' {
MCASP_RX_MODE_DMA);
% p: X- w- p- u( ?2 j; zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* C* J" e1 [4 ~, `; s. Q( o jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ A' h C2 X* H0 {8 ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 c+ ~6 S ?) ]; r7 b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* \6 d1 y0 \; j* j7 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 @2 ^* f6 x" ]' h6 |: u) F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* M( i- Y; }: |& e; X- F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ q1 e* e2 c H0 e! M. K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' V( b6 J- x+ D1 C/ h9 ~" l. {6 F/ v* Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 m6 K) T6 `3 [" }# ^. S3 v" b. I' E
0x00, 0xFF); /* configure the clock for transmitter */
; x5 z. s( e* d) I; e8 EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. O0 [" f/ M" S1 g0 e# o* xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 X* Q& c' V$ F u, ]( ~' U& t1 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' h" N+ N$ S0 o; ?! r0x00, 0xFF);0 T* ~& R6 d6 |4 b8 d- H9 ]
+ U: f" _/ v% O0 p% E5 I$ s0 o
/* Enable synchronization of RX and TX sections */
) b$ J4 i6 Y5 Y" Q# P3 p( d- g$ zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" l! f" W& s% KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 Y/ r) I, x. Z1 c6 L: I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 ~6 i& S& W5 Y i
** Set the serializers, Currently only one serializer is set as) |, b) S/ q+ y4 ] _( T
** transmitter and one serializer as receiver.
$ K- a4 T; j- n4 K*/
2 x% B" {0 ~; {- Z8 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# S0 ]" w; i! m# V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! L& K0 j% A$ J' Y0 L, m
** Configure the McASP pins
" F4 p( G# Q# _; I** Input - Frame Sync, Clock and Serializer Rx C$ h8 S4 A2 A! |
** Output - Serializer Tx is connected to the input of the codec , F- _4 }3 q: h) K7 E s3 b- P
*/4 Z+ h' W- t7 e1 B, q% i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ C8 J/ e* `; X' Q2 ~$ Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% J( ~; v: O7 [! ^( ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 J8 U1 Z: n9 y1 @! y
| MCASP_PIN_ACLKX
6 L. s+ W; L1 C| MCASP_PIN_AHCLKX
& _) }9 z8 K3 F5 f) h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 w! }$ t+ _, x0 m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
X1 z/ l& o5 T9 [7 o| MCASP_TX_CLKFAIL 8 b8 \$ P: N$ u; {; z
| MCASP_TX_SYNCERROR
9 R4 U( Q1 y# y/ x! X$ h' l3 s( c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 z" G( H: K6 a4 m" w5 ?+ d# |/ `
| MCASP_RX_CLKFAIL
% f& d# l, g M| MCASP_RX_SYNCERROR 6 ~+ E/ V: P! s8 t1 _
| MCASP_RX_OVERRUN);+ K- m; ^8 a' N$ @- v) O
} static void I2SDataTxRxActivate(void)* x7 |; N1 P/ r+ W3 L
{
- b! b f9 m% y1 r2 Z3 n! q" f1 }/* Start the clocks */
5 E) n2 N) V$ s z% MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, e2 ~6 w8 w7 D( _2 p( {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 V3 G2 Y' r* ^/ t9 g, oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 j! }9 O0 G6 EEDMA3_TRIG_MODE_EVENT);* Y# m: i/ _$ d. |& d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 F/ g: ?; f+ S5 q* C' Q4 tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" n: s/ C. t& n+ |+ KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! K6 H( l$ L" H8 x# t% z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 A: ?7 \, z& i& t7 J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 G1 q! ~& `4 P w. @7 GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 F! K1 O) _' ?- @: t: Y/ DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ ^9 _9 g" ]8 ~7 G, l} % y& A$ P0 `" |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 ^; n5 Q; x) W1 v u |