|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* R1 H) t' k u" D c
input mcasp_ahclkx,
+ u: a9 O: D: R7 i" _input mcasp_aclkx,1 k# X4 a+ Z$ N; ]/ b# p
input axr0,5 U9 F' e1 F1 m
' s. t7 ^. r! L8 a: M( g
output mcasp_afsr,6 c* i& r) X% o' s/ n1 l! c
output mcasp_ahclkr,$ ]. t' s/ n/ E* D) \
output mcasp_aclkr,; y' b4 L1 P+ H& P7 W5 c: ^3 ]
output axr1,$ z/ T8 y) R) ^1 ~5 M) C0 \5 H
assign mcasp_afsr = mcasp_afsx;
% g+ v6 g# p1 D4 passign mcasp_aclkr = mcasp_aclkx;
9 F, y0 v$ w5 G. N" j! jassign mcasp_ahclkr = mcasp_ahclkx;
- Q/ z* j+ E8 Y$ Eassign axr1 = axr0; 9 K# z* \$ B/ ]- ?( h) l
4 I' M) v( @8 ] P' N1 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 t0 f0 w# ~8 J; d. P! S7 v4 D3 Nstatic void McASPI2SConfigure(void)
( S7 H* _' W P/ H{5 C; ]7 W5 ^: \- F& l* @& K) V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 I( B2 P* J% E/ a% U4 Z% ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 _$ d' I4 q5 F1 I9 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 \4 ]; U) Q6 T$ y( v5 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* F6 Q+ v3 T. a1 G k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: k5 e0 z# L9 k9 j2 G5 j
MCASP_RX_MODE_DMA);
% P. ?/ B4 Y$ ]# E( v0 A V5 CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! M4 c( V1 l4 p0 g9 a3 S: |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 C7 y4 V* ?) D8 ^- Y: M# `# v, s8 i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 C- T" R! X2 L! V' P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 h( J$ R1 n# ]( X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 k0 n$ Y, W9 ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ v M# G# l5 `( `9 H7 u* uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 {$ ^1 U% A' HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # S' L Z# y% k% y/ `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 i# T- ?- i3 c. h; F' A# n, \) |
0x00, 0xFF); /* configure the clock for transmitter */& ?/ p- q/ i8 `0 r* `6 u& p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% G$ a% k; g) eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 `, P7 s) z( ^! X" nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. L& o _7 c9 i" g2 ?5 m/ D m( q/ g0x00, 0xFF);; o5 q8 o' r6 Q' R% D
% {1 Q- [0 ]1 R) W0 D8 N+ C
/* Enable synchronization of RX and TX sections */ * J7 M; |7 X: \% N1 E" ]( Y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" v6 i O) @1 ~. C4 O' Z: V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ I# P2 P$ u. r5 }; Q: T7 K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) t4 T. l" I7 @5 C# |( [
** Set the serializers, Currently only one serializer is set as
5 f4 Z* k2 V5 o v# w' Y! O** transmitter and one serializer as receiver., ?* h, u% K, r' _, b
*/% x6 _' g; p9 ^: }: C( N- m5 s) ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% y b+ a' e; y: U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 \1 o' d0 }+ W( w" ^6 P5 @
** Configure the McASP pins : {- J4 A* a1 n3 }
** Input - Frame Sync, Clock and Serializer Rx9 h \9 f/ H+ O3 b% E0 z- F
** Output - Serializer Tx is connected to the input of the codec / i6 S2 N! @& k& U. N
*/5 n/ I4 M$ }8 j9 ~5 ?, d" W1 W `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 l5 |- s4 R( Y2 a# M0 e/ J* iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 v9 k7 { M; f$ h; YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- e5 _- d7 A$ U/ t9 G* ~; d
| MCASP_PIN_ACLKX0 N( I! v8 x% C5 ^
| MCASP_PIN_AHCLKX
& I( F- d: @% Z) {5 `' h/ K6 R: Z9 ^| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
M. u% h+ c' |/ \7 |+ Q q5 wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' j7 E/ Q) K, C- e+ x
| MCASP_TX_CLKFAIL
" ^" A8 e6 P! Z m: s| MCASP_TX_SYNCERROR
: z _. z! B; c) z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! U8 e) F: k0 x8 Q
| MCASP_RX_CLKFAIL, c) w' y& |/ ?3 k% K
| MCASP_RX_SYNCERROR
/ z5 S/ A6 N2 c: Q| MCASP_RX_OVERRUN);/ D* n6 ? A+ @1 F
} static void I2SDataTxRxActivate(void)
: Q6 ? F( g6 z' U! a5 |- {{
' }+ o% d1 l1 g' m- r4 o' |/* Start the clocks */* z/ b: ^9 r0 H& U3 Z1 w# ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 b3 c4 m0 @6 |6 m" @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( i- e! q' s; D6 F8 }) [ p3 I0 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 T7 z4 T6 F5 f1 A
EDMA3_TRIG_MODE_EVENT);( H5 \( o) g0 H9 E1 d, L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . H1 r; o# A8 a% l4 k% y" V4 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// w: h' H* `7 r4 T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( U) I' }, h$ JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 e7 O4 o' u9 Q6 i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! k+ y' r3 e4 I3 `, I ^& r7 aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 \( M$ `, S# Q9 eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 D; M- J' K( D2 V" \. \7 i- e
}
" I1 F3 B& [7 f! F5 d+ l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 s4 [ \. \" L |