MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
9 o) k, D. o) W) sinput mcasp_ahclkx,
, K# j. M8 z6 P: ainput mcasp_aclkx,
/ y( @  c' F6 P4 U/ Uinput axr0,
! M7 E% `) |9 [+ `0 ~8 ]# @' D( d
output mcasp_afsr,
output mcasp_ahclkr,
0 g* T& K2 I6 C1 f) G# ]output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
! c: F2 ?5 {* fassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
3 f. T9 ^" r5 q. p$ ^1 R) Aassign axr1 = axr0;

) O3 a) T5 Y5 t$ E4 x1 R

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
$ H% Q- T6 X$ {! W7 y4 t{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ j2 m1 |0 o/ s0 j6 s: wMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- D( F5 a" m. J1 `7 L2 AMCASP_RX_MODE_DMA);
  l3 C* \1 d( T( x# NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ J, ]" E2 {. a" Z' ^* c( kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' W, z0 r; w# d- a1 A$ `! p7 uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 M4 W$ T9 x. \3 g6 F: qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
4 `; ?9 \; u' YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% K/ w  Y* A4 W; ^( R$ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 z( W; x7 q9 p0x00, 0xFF);

/* configure the clock for transmitter */
0 S; ]. ]3 ^% s- o( q' a, GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 h) A7 t' l5 x) ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# W0 }# E% H6 K7 \1 AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
1 a. U9 c" u. e$ \" e& Q
/* Enable synchronization of RX and TX sections */
/ o* X  |' U3 r1 S+ U2 RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
  h; u; v+ I7 V: O' \*/
% ^4 M! V/ w* HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" P" C( h+ t  E* fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
. G3 |3 ]: e) F/ {/ y** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
& o$ w- n0 R% |' [7 ^** Output - Serializer Tx is connected to the input of the codec
. l4 c4 P" {" e- o; P5 t6 y*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" _. u+ P: X  s8 t* T, pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
% x: ?. A+ J% e2 D9 H| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 B' _% `  k) S; z. q# q) W; o8 W& j% w| MCASP_TX_CLKFAIL
  U3 M) P7 x  t| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
5 N3 ^: ^+ F+ t% [7 Z| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
$ g5 X$ i9 X3 z! J4 p( [- ^{
; z  `$ U/ G3 b) h/* Start the clocks */
2 E' o! R2 S" [" ^8 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; H, R7 i8 W6 n" O. w" ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; |7 {) k6 g+ B; G! H2 a6 i: {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
, ^) v2 d7 H, p# m' A. x' swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
1 u8 r: J  M2 y- x6 M7 _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 l" x9 [1 N$ S% cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 w* B2 v9 q9 H% N( l% c}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.