|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* C h& A. {7 _. B3 q8 H" g
input mcasp_ahclkx,4 O, D. U. Q: ]5 j
input mcasp_aclkx,
" U; O! s) G2 y6 K9 Finput axr0,
3 w* `" ^: w8 {6 m! \% T5 @! D R) e" P9 A/ ~. } M, P3 {* {
output mcasp_afsr,- Y$ U) f" R9 h0 {
output mcasp_ahclkr,
1 G1 M3 v0 ~4 u# l; Xoutput mcasp_aclkr,7 ?. j$ ]8 \- S- a, J& Z0 U
output axr1,4 q9 x( E) Z% j' N
assign mcasp_afsr = mcasp_afsx;* _+ e3 Q$ w u. S3 ~
assign mcasp_aclkr = mcasp_aclkx;9 n1 w1 B0 p5 d2 G. V
assign mcasp_ahclkr = mcasp_ahclkx;, q v& B. i; z8 N
assign axr1 = axr0;
, m; g" P0 u3 `% z- g: s
9 O) _7 Q1 I! ^" \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! w5 {8 j) F2 |' g
static void McASPI2SConfigure(void); `% N) ?% ]4 x# k
{3 ^( a" F0 V _5 |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 `' r: _& o% B6 V& k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( v, l Q8 K+ m& C2 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; Z7 Y w8 a# b! d: pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 a& [, N9 U4 _6 i5 r- A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# U5 O1 U, m) ^4 m- @6 x$ }
MCASP_RX_MODE_DMA);) C' z, r x' x* J7 w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# e% j9 L+ k0 R0 J9 [* \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 \0 r3 {( O9 o1 X5 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 ^/ {" Z& t( A& sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 l: @5 p' X: ?' S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" A2 W8 n" u4 m# U% H2 q/ P$ ^1 ^9 vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* e6 D9 j0 X7 e$ S J" {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 o# u% u. M$ Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( [" u' X$ q" @6 [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; _, |$ i) J, \" Q0x00, 0xFF); /* configure the clock for transmitter */
7 J+ r2 K7 D9 N3 v- I5 v# rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! Z: b( K9 Z: v2 Q7 ?& d: d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* t! {( g& z: S+ O- H+ `: mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( a& h; P3 t* R: H/ j* j
0x00, 0xFF);6 \, v* l: h% X% P. ^8 I: f
2 G1 |/ O& D; T8 `
/* Enable synchronization of RX and TX sections */ 4 i8 }2 o1 l+ M _; [' }, [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 d+ r h& U5 uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 g4 v" W4 X" n' _& R" ?, Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 \! T3 L0 R# x4 r3 O** Set the serializers, Currently only one serializer is set as1 J8 Y# B$ E, f( J) o. m- S- |
** transmitter and one serializer as receiver.
: p8 G% d! V3 L: U9 t; {*/
5 |: n, e" f4 [McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ N; K: ^2 b- x! ?6 W; e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, M3 N- ~! i% d5 u* r2 H0 d** Configure the McASP pins
) c4 b+ Q- S6 w `** Input - Frame Sync, Clock and Serializer Rx
) O+ Z/ A3 b( o** Output - Serializer Tx is connected to the input of the codec
3 M4 M: M0 e6 g# f' o1 v*/
) C2 x+ \# z% j& y3 @/ C% ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% w) g, }2 v, ^/ }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 e5 m, A7 Z. a3 L p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ A( @7 v! |, z/ J! ^5 W
| MCASP_PIN_ACLKX
* j! M ?: l3 J9 `3 |- || MCASP_PIN_AHCLKX9 T; i6 n: L) N2 h% w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 h; g* o: A2 T2 _0 _# h! c/ ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. s0 q6 w1 y3 U| MCASP_TX_CLKFAIL
' L- L3 }+ d* `$ H) M6 X| MCASP_TX_SYNCERROR* D' } N9 k! y! x% n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # p6 [$ L2 p2 V3 x. G) G
| MCASP_RX_CLKFAIL8 ~& V' B0 m: U; a! O- c' W9 o: r
| MCASP_RX_SYNCERROR ( I" _4 J: P. ^4 p3 |: M
| MCASP_RX_OVERRUN);
$ i7 u: m0 W* n3 r! l} static void I2SDataTxRxActivate(void)
0 x6 e. v( c9 z) {$ {9 q{
9 [, p* P1 Q- P" x/* Start the clocks */
8 E) w6 l( G+ S. aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" d# v6 B3 F3 ~. zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% @9 s1 U9 E& j/ a0 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 A8 i" F, M& {6 ~EDMA3_TRIG_MODE_EVENT);
- C% d* [% ^. ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * Y3 H* {4 D. \
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 U' u+ ?+ J+ N6 D9 c% c8 {2 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" A# s7 y9 S$ l7 D. L4 a4 `+ KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! @9 F" a9 a5 G7 m9 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) n0 m! Z' H3 B# q( Q# a, n6 UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# {1 Y! q. Z \4 v/ @5 u& K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& p r- a; c* `' b! d} ! @) _' y% q1 @3 X0 }! r. @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; l! n$ ?4 t7 P0 E |