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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# {2 H5 p9 A. }
input mcasp_ahclkx,5 ^. F& g% o" O2 ^* Y4 v- G
input mcasp_aclkx,6 B* J |5 C8 s4 V- e( {1 |
input axr0,& A/ j; u8 y3 @# }/ j
6 \6 t5 G: v" o u8 Q5 Toutput mcasp_afsr,
0 u8 \* F7 m( s+ N7 ]( v) s) Eoutput mcasp_ahclkr,
, p7 E8 ~8 O2 ^6 p* w4 Qoutput mcasp_aclkr,. e) o0 s! e4 V. I, l$ I+ U- ~
output axr1,
! a- g% ]. G2 E assign mcasp_afsr = mcasp_afsx;
* g5 v# N" ~) H, C% w" jassign mcasp_aclkr = mcasp_aclkx;& K5 h K8 [+ G; ?. W( I
assign mcasp_ahclkr = mcasp_ahclkx;, u) B. O6 F. Y/ K
assign axr1 = axr0;
4 W Y3 j* g6 C$ h
. k$ E4 Y1 L1 K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" K& a6 W" R1 |! E( A. n Ustatic void McASPI2SConfigure(void): G5 g. E8 ~$ S9 M- T( W% M
{
) x+ k, J7 m5 M+ W/ BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ ?6 ?! B( ?- v6 P/ I I& qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; E& j! X! w# L! n: WMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% B& L. ?8 f5 ^4 d( b2 t2 _, r( \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* L$ f5 P1 D8 w# S+ P' b7 g7 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 I) E0 y3 A( K3 H
MCASP_RX_MODE_DMA);
" \; o1 z7 t$ g7 R2 T: ^4 }& `McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, @# x3 ^) H. t1 V W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# w3 {6 v2 ^0 D9 x$ Q4 }McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( ^4 ?9 T9 T4 R4 ^4 R1 e" _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! P) g C { z# R6 z+ j6 t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' m0 }! p2 \, n1 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 @0 ]% D% a/ f$ WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% H+ N& n% S* K' w& W1 p/ J1 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ ~. p0 {/ q* A$ XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 E: M1 x8 S' S4 r1 H9 F% P
0x00, 0xFF); /* configure the clock for transmitter */, r. B5 ?2 q2 X# v( ~/ y# v* i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& B# Y. j+ e- }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! i- s8 n, d8 ~2 AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 \9 b# f+ ^- D0x00, 0xFF);
8 e7 \1 p c5 p0 }6 N( V8 T8 j7 m, K7 b: l/ I' G1 u3 X, z
/* Enable synchronization of RX and TX sections */
; I# d" Q$ l. _0 X6 D4 a! P- S$ aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// u' s/ f+ G$ Q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. `2 G: R, g1 m! ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; m7 M5 s2 W1 L- b* k** Set the serializers, Currently only one serializer is set as3 O, q& o4 w- l* a( b% R
** transmitter and one serializer as receiver.
1 a1 R8 D" ]% ]*/1 O6 |5 u7 @/ D" {& ]. W4 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 J& f, R5 f' d; B+ NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* e! `* p* r, E** Configure the McASP pins $ B/ F0 @! g6 j% j p: U
** Input - Frame Sync, Clock and Serializer Rx
, K4 z2 a& |1 o9 P& J, A* o, ]** Output - Serializer Tx is connected to the input of the codec + w( r/ ^3 }; B% V8 S
*/. X+ Y- S- @: n' m7 u, t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 J1 j. m. y- K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; m& Q% |! a5 N6 n0 C" |/ A, g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 [! V" l0 z X4 G- ^| MCASP_PIN_ACLKX
3 {3 z, {" G- O! h| MCASP_PIN_AHCLKX. r4 [$ j' F$ t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! V' X, Y F0 j% Z4 zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: t4 W" J, [) P$ e/ g| MCASP_TX_CLKFAIL
: U; D2 I E" V; n. ]3 v% Y/ P% C| MCASP_TX_SYNCERROR! v) s, G$ X3 ?+ E" @/ [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / H! c2 A; [& U( R: M L$ Y
| MCASP_RX_CLKFAIL; Z! K" |1 }' {* Y" J7 d7 h8 y
| MCASP_RX_SYNCERROR
+ ?. X! V5 A2 Y4 {$ n2 X6 a| MCASP_RX_OVERRUN);
* P4 x9 i$ |' F" w$ ]' G0 W} static void I2SDataTxRxActivate(void)& |& ], D% D8 L+ I* n* K! `
{
4 @) I, s2 x9 i1 d3 }$ o, }/* Start the clocks */
0 \ F0 o1 B f& W _McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" _9 _2 c6 [2 M+ C2 l9 RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 [: y. p, H9 ^) ^' ^! C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. r; ~# f3 w! s) |4 z, m, oEDMA3_TRIG_MODE_EVENT);4 c) f) h0 z2 n8 |# P: [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 n( h8 b3 Q1 y* {' R
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& c a" Q! Z; D+ cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; P& Z2 \; d3 nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 I5 \/ p1 W6 o9 q" C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* `" C6 |. f! W5 yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);# H0 [& t8 X: i' c& s( N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' n% I1 n5 ?1 [/ C}
% R; [$ ^7 u0 p' A0 G% f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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