MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
- s3 Q  j; m' V" }$ R7 [5 E! _input mcasp_ahclkx,
7 b6 N0 h% s+ e: D, {input mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
- M* t- y1 W' Y& [7 a4 Aoutput axr1,
* C/ R. y  N' D- }% ]

assign mcasp_afsr = mcasp_afsx;
- r6 W% B' b6 ^3 |assign mcasp_aclkr = mcasp_aclkx;
; V  B* m! Z- P- _3 dassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. {) c3 e" s; }9 V1 U7 U! y$ L

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 N5 j4 U4 X' D1 N% pMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) t" b6 g! n: WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ F$ x7 X$ ^% I2 r0 A0 P$ ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 M* w; i7 [2 D5 X8 m: Z4 WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- L9 _2 n  B' `; y! TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) E/ d3 E' T) k  y; p0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' Z. H/ B. o( s$ V; I8 B' [, P6 wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! ]  \( o* l4 y% mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
, A+ {6 m2 c" A1 eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) {. \$ n3 ~+ \2 m& w& X5 PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
' }8 u  w4 ?8 k* c9 T2 Y2 M** transmitter and one serializer as receiver.
8 i" B: p. I2 s8 k*/
1 ^! C4 ?$ K( X2 Q# `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 t  g+ q( a! ^' F' [# JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
1 F( }& }2 B/ g+ h3 X# [( ^** Input - Frame Sync, Clock and Serializer Rx
) Q% s0 I6 H% H! f5 X9 \, K** Output - Serializer Tx is connected to the input of the codec
& }. K3 T- K5 X# U0 X- a5 G- u; p% E*/
5 [) d! K3 Q1 z  ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ }. e# p/ s1 ?* {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
# n4 x0 g9 Z3 Z; d6 Z2 E8 y+ |8 F| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 q8 e% F2 J5 h8 s7 C2 V| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
6 T/ l  F. ~9 {, Z7 V; b| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; `" p) O: T( f# H9 k| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
5 j$ W9 ~; G) Q2 }5 b6 D0 p" P7 g  a; g# b| MCASP_RX_OVERRUN);
: e" \2 Y5 V5 V: ~9 C}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
2 E( _3 }3 O1 ?' [5 pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 ], G- ]) }7 m1 L1 ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! @% `1 V6 c1 rEDMA3_TRIG_MODE_EVENT);
, N# S8 D7 k: z4 H3 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& \* I% ~0 m( j) v9 O6 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 A9 t' r0 C8 {7 DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' @; w! J8 p& [' W( _) mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ z. Y" Y9 ^/ U9 P}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

2 ]1 M5 b' H3 O