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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 h% A% a' y9 K" Q$ U2 |$ C; G
input mcasp_ahclkx,
: O* y: w, e2 s/ Q+ q Dinput mcasp_aclkx, |; }, q6 J4 e* K4 o- K
input axr0,+ i- H b/ O" f4 ^0 G" y2 M' m/ @
4 g. s' w1 Q3 E( S. c3 g2 j
output mcasp_afsr,
" T5 W- F Y: m8 joutput mcasp_ahclkr,
3 j3 {+ c" ?8 T( d9 ]6 Goutput mcasp_aclkr,
8 a M, ~/ O8 H+ c% M* g6 woutput axr1,# S4 V, X: {$ p5 i+ f
assign mcasp_afsr = mcasp_afsx;- h g7 O* ^8 h6 A* I+ _' _
assign mcasp_aclkr = mcasp_aclkx;. H4 i: T' _& j* G% [
assign mcasp_ahclkr = mcasp_ahclkx;
$ g* l8 q# `- F& d; l1 G2 \0 H uassign axr1 = axr0; . S% w( u% V" N+ G5 G* M* n2 g
3 S: [, [+ V8 o! s6 c0 e0 T4 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 _9 B7 n6 {3 \, V2 Jstatic void McASPI2SConfigure(void)' x" o% k5 b5 s3 ^' c0 G) v
{! d- o1 [/ s$ `' i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
U0 V# c' s" LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 w2 ^' T; k2 Y% ?McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- b( b* `* X6 Q. ~2 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 V: R B0 w. j! A, |) O8 p% Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 I) b7 v3 h: o
MCASP_RX_MODE_DMA);
8 u0 ~0 Q. z" Q2 O2 M' Y a5 T0 TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) B- z8 b" j7 @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- h, b, G. ^+ e! d2 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; V$ ?2 L5 a x3 x& \7 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 H% t, ]/ x" \/ XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " e: B$ B) u9 ?3 o$ z8 }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ ^& R" Z$ q4 |4 v' B, c2 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 a/ Z; ^* q4 [: ?, @- c- |) m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; j* b+ h2 H+ ?( p+ M: k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. E1 R; y, ~4 ?. S2 S/ s: R0x00, 0xFF); /* configure the clock for transmitter */
& x9 m) t, z3 yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. B, @/ C% F) V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- E: Y4 d/ Q D2 E1 \2 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ j6 I6 g7 ]& ^( w2 h/ C. o1 `
0x00, 0xFF);; J0 J! B' h r
. h) B" ?: q2 D: T, Y6 D8 q" Z/* Enable synchronization of RX and TX sections */
3 j2 l9 ~9 i' J9 `: q, v) EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 Z) w7 k( u+ d% rMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. `( o8 K# n' p3 T! ?: X+ U: R/ M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( T9 h5 \% \, q$ X. O9 ?8 w% V. o
** Set the serializers, Currently only one serializer is set as
1 s( X& ]& N; N5 d- c6 W* M4 e# i& n** transmitter and one serializer as receiver.
" F, G. a/ y2 M8 c5 k+ o+ X*/
. `) K9 r% k D: n1 }* O7 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# v* _; V% N, d' q: Y. [: y" BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! n$ z3 _5 K% o. r; F** Configure the McASP pins
7 ^' U* [" O3 x! O) \; R" b** Input - Frame Sync, Clock and Serializer Rx0 ?7 Y# K, y, o' J
** Output - Serializer Tx is connected to the input of the codec , O, [. C8 `. J w
*/
& x% z/ q5 M m7 d1 A# h hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! J) k/ d( M! a: F8 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 |( `2 v3 T$ x4 r. P* R5 R1 JMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 v0 f# Z/ f- F( ]4 a; L0 h| MCASP_PIN_ACLKX9 k6 a. y' V/ m0 `6 C1 p, {1 X) [
| MCASP_PIN_AHCLKX) w. C) @8 Q; K/ m/ W }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, L" B: F0 a# y1 _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ a& [+ _9 J7 Z4 y8 g1 I| MCASP_TX_CLKFAIL
5 h8 Y1 a# A. ?5 M# \| MCASP_TX_SYNCERROR) C5 j* x& s' M n7 m3 z3 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" a5 r u0 B& X7 C1 G! h$ `" k! n$ R| MCASP_RX_CLKFAIL& o/ p1 O: o$ U" ~! V; z! t( T
| MCASP_RX_SYNCERROR + G7 r% J) J) w, a
| MCASP_RX_OVERRUN);
1 i# f, D m/ y} static void I2SDataTxRxActivate(void)
+ i6 z- Z. j. @( O! {# C{
2 n9 k( ?0 ~2 i) X3 t3 z! p/* Start the clocks */0 j$ H; \, D5 h+ Y3 L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 F9 R' d0 w p$ s! q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ A6 o0 {$ k/ P+ F0 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& \4 T! U! L2 ~! P: @& e) v) M$ E, R
EDMA3_TRIG_MODE_EVENT);
9 z0 q9 ^$ ?: ?3 J: f% G6 k6 W9 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
i: K. {7 a0 ~& n( CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: |! w4 `- S/ S2 K' R0 o# q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* W% b5 c2 U4 R6 W( x: _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ P* z) f: E% s5 G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 F' y3 v4 b' Q) a0 m7 T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; [/ \: t3 H# j3 a+ v3 g' zMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 m3 @. h- l7 S! c4 `
} 7 Q$ P; S; k0 ?8 d1 O/ v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " n6 z- }( ?/ J8 D: ?0 i% ~1 n
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