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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ q/ a% Y% I, a) T% A1 B6 r; I5 k
input mcasp_ahclkx,
/ a3 c: e6 ^ l$ k0 K0 A/ ?input mcasp_aclkx,
4 n& [/ s+ O! f0 |- y9 rinput axr0,
6 y& Z' V4 h- U7 c1 K% v1 L% a! i4 J C- ]
output mcasp_afsr,$ x+ F% d6 `0 x% d- V: L. u
output mcasp_ahclkr,8 D* _# e6 v; w* d- O5 u9 T
output mcasp_aclkr,% B+ h) z7 D$ h Z. k: c6 u# n$ U
output axr1,
% c" G4 @" b. T e$ [ assign mcasp_afsr = mcasp_afsx;$ D* y1 j; m+ s& A9 Y8 t. c3 K
assign mcasp_aclkr = mcasp_aclkx;4 n1 _+ g# s0 w9 k9 K* G& F
assign mcasp_ahclkr = mcasp_ahclkx;4 R6 E) n2 w( D1 g0 o$ i
assign axr1 = axr0; 4 h: k% w7 b* z
6 q. E$ e3 X2 B2 m4 A R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 R, I* K; @; F+ b3 e9 `. {' [static void McASPI2SConfigure(void)
! N! v+ g' q! `" i9 c9 V6 [8 k{
) g( h7 P: W- ~, F- r- E* NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( R l. O6 O' d4 p- F; M0 I; ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 A" v/ ]% ?8 J4 C% v0 N, D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 h6 @8 b- ^$ v" Q; S2 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 N0 D) P! H% h5 `2 O' K& Q, x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: E! \" b5 o0 [MCASP_RX_MODE_DMA);
0 s9 n2 W2 P+ F: ?: m* ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# q( {3 m+ r# n" j e" ~" _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* ^/ ?8 V0 U- I, xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% N. b$ _2 O/ B! x# ?4 o* i- qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% o# G6 P1 Z2 O( i' jMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! Z: a* q6 l: ^4 |# YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
w; S8 Y# [6 I/ W' eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 u, I; P9 y. g5 ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 q6 q/ [1 A$ R; P" l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 H" z: `' W/ X3 }: f& ~0x00, 0xFF); /* configure the clock for transmitter */* y8 H! X+ s3 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; U; d9 C+ t4 S1 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . [+ E4 h! R( s! W/ a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 F1 g( a$ O. z; O8 `4 {+ k
0x00, 0xFF);& ^) J W l6 O" o4 n8 ]0 R0 v
- ^! K6 U% [9 v# G0 T- R9 M/* Enable synchronization of RX and TX sections */ ' l E+ }+ k, J7 E/ {3 ]: u2 B0 g L' o. O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. ~8 ~/ g7 O3 w9 m; M* \; M! `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 E. N3 u2 S, V% ^' WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" N7 H2 C& d7 G& k2 H* }
** Set the serializers, Currently only one serializer is set as5 U" N2 v! @" S1 Y
** transmitter and one serializer as receiver.
: G/ e$ \$ Q) d3 C. s*/
' W( |8 Y2 S+ e5 B6 n* s% |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* }( l& m/ B- J3 A8 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" g- d; o+ X8 O' U( n+ J
** Configure the McASP pins
+ T, v; F% l1 I3 S( {5 @7 u- f2 F** Input - Frame Sync, Clock and Serializer Rx% q7 M/ _) b: G6 ?, g" m' L5 P
** Output - Serializer Tx is connected to the input of the codec
w' g& H7 }, A5 }; P+ q5 [. e*/
9 o! ]0 w1 R$ b5 M y( ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ s6 M: d: k) M. f3 ]: A$ n9 n+ U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ O; A( s% Q# V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ V: d: ~8 o6 W& Y9 X8 E1 n
| MCASP_PIN_ACLKX2 j$ C% Q. P# Y* f
| MCASP_PIN_AHCLKX
, z6 ?2 f3 W: H$ M- U& X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' K$ U# H1 l6 BMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % D7 u& T3 Z* l
| MCASP_TX_CLKFAIL
$ h+ l7 X8 ^( T$ || MCASP_TX_SYNCERROR
: @; d; _0 ^6 U. L| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) _) `( [$ G* O| MCASP_RX_CLKFAIL, X8 L: R; |4 x* J- j3 G+ L- p
| MCASP_RX_SYNCERROR
& x' E6 i9 S& Z3 o; D% q| MCASP_RX_OVERRUN);7 Q/ b' ]- _' Y) i2 `
} static void I2SDataTxRxActivate(void)
6 q, h8 \+ G( D0 x{
3 @( ]* R# w# w% v- `/* Start the clocks */
" x; p: C* g# r5 F3 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 u; _: Q6 O+ E3 K6 c4 {# NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 X% Q6 r: h2 f$ |9 @+ s" p8 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( g X* f V; G3 d' O' z& ^1 gEDMA3_TRIG_MODE_EVENT);! D5 o* L+ I! u% e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 H& {! s' g& J8 m6 e( m. W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, V- |5 y/ @) i' k3 x/ y$ `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# O; g4 P7 U+ H M0 C8 F. y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 L* Q5 s1 R k3 Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% a1 ^( }+ K3 m0 R+ m; V. v
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 O. M( f+ k: f( s1 d( hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ T7 L: Z+ k& Y; r7 I; W9 q& p" V9 i}
$ Z, m$ D: t. |2 Q3 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 W$ v/ _4 l1 b8 K
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