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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) M8 { C. z7 Z# |2 F
input mcasp_ahclkx,
! G$ Y9 h' b& Y2 X; L$ Y: N5 l7 qinput mcasp_aclkx,- c& Q- D9 q% r! y/ i L) r
input axr0,
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output mcasp_afsr,
, H+ e* X9 C4 boutput mcasp_ahclkr,9 W9 y+ j$ S# \8 f }
output mcasp_aclkr,6 v0 [# A* w& D- E4 f5 g% {" l
output axr1,
! ~3 @7 u F8 B0 k$ ~# h/ m+ p assign mcasp_afsr = mcasp_afsx;
% X- ~( _* b# W2 i3 @assign mcasp_aclkr = mcasp_aclkx;7 c6 B' i' S8 v5 D4 P. f
assign mcasp_ahclkr = mcasp_ahclkx;
! [+ U5 M' Q# Y9 `2 Passign axr1 = axr0; & h( |! U8 W& h+ T V
3 y$ K4 f" y& h: @5 X6 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! n! d$ y/ C8 y9 H: C; s" h7 s. Hstatic void McASPI2SConfigure(void)
) i' Q- H! b) W{3 L0 O9 f, ~$ C% D( _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& G8 r$ c( h7 k1 j/ r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 ?* K8 i; [. { K" R$ F1 r2 r( L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 K8 t c* K V/ i6 p" L' p3 b; Y) G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" R1 C* C* b9 |% fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! c/ i% E% E' V" XMCASP_RX_MODE_DMA);
$ Z; J- J3 p) U# y0 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 `% L9 ^( K5 V: k% ~9 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ W/ |/ ^: n |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! [/ I9 I* }! m! ^& `+ v- T
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) z$ b9 O1 v8 [5 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! E) h- J9 F9 O9 ^! ^) e1 o0 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" y& u* ^* |. ^# ~# G) r( GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" o2 z( l, n! Z j, {& w- GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 f" t H5 X% H. F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) T- k7 ~0 V! h5 X; ]" }
0x00, 0xFF); /* configure the clock for transmitter */
3 f7 w' |- I/ o) K8 ^( B. H6 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' }, }. a6 h/ H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & ?0 X; ` o u5 D, E& L5 q; _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 D; a: C( ?: Z4 H) @
0x00, 0xFF);
, s. W" P" y# Y2 @6 m& B7 O+ y# d, Q% _$ R8 E
/* Enable synchronization of RX and TX sections */
$ l8 X! e% B! CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! V1 i0 J9 G: {8 L/ A$ @, BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 G6 B6 g) M- M6 D q/ @2 i. rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. D, L( a2 l0 A3 i** Set the serializers, Currently only one serializer is set as
5 g3 z) h! u* U6 S. w3 T** transmitter and one serializer as receiver./ r; {4 r8 `+ }4 M# ^ s
*/" E. g. C+ L* ? g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' N2 _# E! Q9 }: C; A& I1 U( w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* I5 z7 k; m/ U( {' {* Z1 i! u** Configure the McASP pins ! z [ o, F: s: B5 F; `9 t. v0 d
** Input - Frame Sync, Clock and Serializer Rx
- \& N7 p0 q$ \6 V7 s' t9 n+ i* L** Output - Serializer Tx is connected to the input of the codec
. t$ t6 i0 B3 p e1 E! A*/, M" q4 q4 `0 m" r; e$ X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 b0 E3 S! x# f! V9 C8 X1 i4 I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. o- e/ n) s6 D8 f/ ^5 vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& E/ e2 S* j B( w( z, P( ?7 s
| MCASP_PIN_ACLKX
* U$ z' f m6 u1 `9 v! O| MCASP_PIN_AHCLKX- S- P" J. c! q+ w6 ?6 v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 E- p. l3 h* C) OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- W- L* L% ?4 D| MCASP_TX_CLKFAIL
, u. Q: X: `" [ @| MCASP_TX_SYNCERROR
2 r: D9 U+ v- T6 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 g4 l7 y: ^% r8 h4 a/ e7 J| MCASP_RX_CLKFAIL
2 ^" N# K* i. }| MCASP_RX_SYNCERROR 0 _9 _5 ]1 A: p
| MCASP_RX_OVERRUN);
+ L% q; Z+ g1 y} static void I2SDataTxRxActivate(void)6 f8 {, X# C/ I3 o# K
{
2 V' \( t0 y7 e* W" I/* Start the clocks */8 ~+ T5 A7 }" y; ~! y. w0 G5 e& I7 [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); ?, y# W, M: y4 A7 f' I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ O! Y+ c& x, j' v; l% q: J$ jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ^' T5 s% M' e' Z; ^9 h _
EDMA3_TRIG_MODE_EVENT);1 x0 H! m9 V2 c4 A* j5 B; r* X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 w; f3 c: p% `8 T; l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( p' @+ u8 s, i9 F' N) PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" j' }* g. X( _4 J' e! U8 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 [ G- Y7 ]0 n! U. q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 J/ d6 e! T& |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 ?3 w) ?! W" J5 v1 Y6 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 c/ L3 t6 `1 Q} ! J+ e5 }' b7 M1 K' K, D8 j' r7 V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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