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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& m8 s. w# c7 E- rinput mcasp_ahclkx,0 C Q) v0 ?" Q: u8 X* r G- p
input mcasp_aclkx,
8 \; H9 z) F0 b! f z$ yinput axr0,( ]7 e; a6 R# X/ S+ j8 }' F
- B8 |0 b4 l. F, ^& voutput mcasp_afsr,6 h* t0 R* D I9 z, ?( Z
output mcasp_ahclkr,) G9 _8 t- M4 @# W- H
output mcasp_aclkr,
2 B9 N; X2 d& n$ J [) l p& Youtput axr1,- z9 H) D7 M( B% G% a
assign mcasp_afsr = mcasp_afsx;
5 b, }2 x4 a) q! M- Q/ [+ jassign mcasp_aclkr = mcasp_aclkx;
4 w! Y# a1 |* w, y0 Oassign mcasp_ahclkr = mcasp_ahclkx;" r$ s# U' g8 l: J& t1 e/ t
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + ^, |# j+ }" |6 n
static void McASPI2SConfigure(void)
, J( v+ P* I6 ], d+ q$ R& ~, c& J1 u{! C- E( X3 j% L- R& D3 ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, ]; [/ d& F$ Z6 n- j" h5 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( V( \; u- h+ ]$ e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# g- ?0 z& K: R% Q6 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% A, c' \, c4 i, [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, J3 x3 B- w3 u) @9 AMCASP_RX_MODE_DMA);' K5 N; v3 c' f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 J- M# S$ K7 [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 E% a- v$ o1 ~1 x# Y6 B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + i! ]. C, k7 G, r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ d w& T8 x. ?* @ |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 R( B( [; r/ r9 s* ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- Q1 j" ^+ Z. H/ b( j$ h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 {2 A. d) b6 PMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); J1 ?! j: c d! N. y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 g+ r$ P5 d3 J: N* I$ R
0x00, 0xFF); /* configure the clock for transmitter */: e& Z( I8 K! J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 O0 r6 \% x& C1 ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 m; M1 m! p \: a8 Q4 j. tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% z1 |! Z+ _/ z0x00, 0xFF);! R' ?1 S& t9 Y+ O7 @+ M( S) c
: z' `8 f6 ^: W k: f$ Z& |% d/* Enable synchronization of RX and TX sections */ * \% U+ _$ @4 [+ y5 k$ W. ~% m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 m3 r+ R/ v6 U" V: m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# K+ e; J d. z- |& F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; e; \2 U& G0 F# j% P' _- s) [
** Set the serializers, Currently only one serializer is set as
$ g0 R2 c' \9 \' N* @" F** transmitter and one serializer as receiver.( c" _2 X4 }. @) n2 f( L1 ?5 m0 O% }( ~
*/
4 o, l/ Z9 a* B* g: V9 cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 C; M9 |6 G8 A6 fMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. |0 u, v5 q1 S. t4 g1 G$ L( I** Configure the McASP pins : d9 f6 L& G' e0 V0 c
** Input - Frame Sync, Clock and Serializer Rx; W1 e" k2 U$ j
** Output - Serializer Tx is connected to the input of the codec 8 O6 n; x- r' b; a* Q0 l7 ~
*/
, N5 }: ~* S- g* @/ P* u' JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 W) s& {7 Y1 E* ?1 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( @/ Z# K5 y8 z$ P* r% R. C; S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 g8 M# O5 S0 h6 Z0 a2 v8 ~
| MCASP_PIN_ACLKX
& s7 W# D+ i% b4 p| MCASP_PIN_AHCLKX
: e8 t. O* S- g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( h% I: T& l9 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" z) r( N: O/ k+ S| MCASP_TX_CLKFAIL # O3 T. r( l+ {8 h
| MCASP_TX_SYNCERROR6 S* R/ @2 l+ r; J. L/ X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % a; i N- }; u
| MCASP_RX_CLKFAIL
5 T7 _- L- Y4 g7 M* u. c! @| MCASP_RX_SYNCERROR 4 F. z# d' a: e, |8 H) @0 i2 P
| MCASP_RX_OVERRUN);4 D# c! [: ?/ a9 g8 E
} static void I2SDataTxRxActivate(void)
4 u0 W) y/ Q) [4 x{6 n. A: T2 g$ K; \ M
/* Start the clocks */1 b$ }2 W4 s0 H% P$ b; [: B" n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( e4 @4 g; H0 v0 S* Y; o& p5 _
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' a7 d. x8 K# R% f& w. Q& M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 G9 K; X8 H: h0 F1 n: K# u$ N) x" dEDMA3_TRIG_MODE_EVENT);# Y a& I9 W( b9 R% Q0 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" s3 _( n% ^& b* R' G* r1 p S) ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' s3 p; W) ^7 l- w3 r: N2 h# Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# |3 P: Q0 ?% aMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' V' |$ |4 E& ^! {4 Y* kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 x9 K" U* N1 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* E! s% H1 F( Q& } h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
b$ c6 e0 g9 P}
0 }, S, G& w% F, ?% J" }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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