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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. Q( R. e. U! w3 D; w+ Rinput mcasp_ahclkx,* s% e3 m# y# {5 C! b* a
input mcasp_aclkx,; D& t7 z' |& w% j8 }3 c: _6 Z
input axr0,1 Z4 x P3 R2 t! t) W1 H$ |' J# h3 x
) ~/ h- f9 D m: y Toutput mcasp_afsr,
6 M# V1 T' M0 e3 ^, Eoutput mcasp_ahclkr,0 a# k, r. u# q1 N/ U- p
output mcasp_aclkr,
' p. ?0 f* b3 E' r$ loutput axr1,
1 ~2 p8 U% b3 e# y- I0 U assign mcasp_afsr = mcasp_afsx;9 [7 N! A2 P' j0 s: O1 X4 W
assign mcasp_aclkr = mcasp_aclkx;4 \5 H7 S7 }7 i, K4 f7 i1 l
assign mcasp_ahclkr = mcasp_ahclkx;, N- G: C* `5 k; z5 M: j z5 Y+ B$ D3 F
assign axr1 = axr0; " c9 C6 E! ?$ e4 E. b3 _
# L! h' [ M: u' N! {! A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 Q: M: e% P {
static void McASPI2SConfigure(void)9 c3 l. x& G/ \8 N2 w- d
{! e5 J! g6 V! s2 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);, }( Z! L* X- d! f3 y3 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& i0 @3 a+ m- U! L3 CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ Y' f% {( I4 u7 w; C/ S0 Q7 r+ aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 X4 p# ^, K$ j8 g5 `3 G2 j- b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 \& l4 P; I, }7 }" A* W* V
MCASP_RX_MODE_DMA);
2 Z9 q9 B1 r3 r/ s* e% GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 s6 r( B. W# y% e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) N: X- n2 J5 o! n# q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. w& a# F, e1 v% YMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 i+ b/ g9 {. _- I) Z5 c5 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 \6 }8 {% q$ b+ @9 v' g& I) |$ X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 X! q1 e6 C3 l4 v2 R; W9 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 @ `( }% @% r' G# Z( {2 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ _$ h% a, v+ P1 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& u6 t: ~: h, Y3 X( T7 V1 h5 U( ~
0x00, 0xFF); /* configure the clock for transmitter */7 z$ U" F1 q& S4 V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: o# G0 _ K, M# T) t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , c0 R% S, H: i. L" q* ]- ^' O) w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% S W2 |* h2 M0x00, 0xFF);
: q/ \2 ?* i# }! D- `1 k- f% C# l/ c7 S1 o3 B5 E+ \
/* Enable synchronization of RX and TX sections */ " |* n) i* q% x; ^0 T: I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ J: J. z! }( Z; {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: j1 [' z% S* K7 H5 ]4 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 ]/ C3 Z' f$ S3 h2 o p** Set the serializers, Currently only one serializer is set as
2 j+ B8 h) ~/ N/ t4 [- |: ^* W' o** transmitter and one serializer as receiver.6 R2 D+ j$ a( A" f/ B
*/
0 d* Z, J, Q- Y' r lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* \( P6 v$ K' F, ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 A8 G; D; Y* d- f. V+ U/ Y4 g
** Configure the McASP pins & g0 G6 b4 J; _# G; e
** Input - Frame Sync, Clock and Serializer Rx
' l ^- }% ^6 y V** Output - Serializer Tx is connected to the input of the codec . ?: `1 W" g, K9 G$ f, f
*/5 t u+ |. o$ U
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! ^ D: |% i" N. o7 E9 |" ~3 bMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 s ~) \0 N9 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. F2 A. P2 j. I| MCASP_PIN_ACLKX
5 p' M. m% \6 T& j3 S2 N| MCASP_PIN_AHCLKX# e, H# s3 p9 ]" [; w3 S5 d5 J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& D4 [8 i/ k4 ^$ h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& v/ ~) y$ q- G% q" x: m0 {$ C9 |, ?| MCASP_TX_CLKFAIL
U/ L5 X' R( W, }& y7 B8 E, S, `- ~| MCASP_TX_SYNCERROR& U( M7 R( E8 h8 O- c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ X; j3 h A' G; M" d( E1 E/ M% H| MCASP_RX_CLKFAIL
' A- O. W. x' {0 ^; S| MCASP_RX_SYNCERROR
( N3 j* \+ G! m| MCASP_RX_OVERRUN);) c z* P: C0 D6 M' c
} static void I2SDataTxRxActivate(void)5 k: \2 k; l" Z8 v5 L$ m' l
{. v2 @% Z1 r7 Z* U3 |5 @
/* Start the clocks */4 ~9 f4 T9 x7 [- B2 z" ^& |" s, ^
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ i8 l0 j" S4 w2 l8 YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 T; O7 [, H. a( o0 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ N, N4 [6 y5 c4 ]
EDMA3_TRIG_MODE_EVENT);
. `' q/ Q4 y; d" BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 w; n0 r( L. A+ _0 t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" G. g5 K- O9 X0 R$ X( e* ?" B& R; d
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% j- d! I7 K5 g1 ~2 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& G1 a* I- j- e. ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! l8 R" {: P1 J" R5 R& @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) V( Q! f' Q8 O* a; c) @, \- s1 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- d. W m0 f V0 G& A* B/ o3 q
} 8 Y w1 `' A! y5 o m- P$ V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 i3 {/ N# \/ ~+ e2 C$ P
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