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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 W7 \4 R1 g6 |# U7 t, y& Pinput mcasp_ahclkx,
$ N- H" c. C% U O1 Q9 ^input mcasp_aclkx,) Z) Z r4 t! W/ G9 }
input axr0,$ k6 c0 Y9 Q0 q6 U! V
2 \4 k5 W+ w, S' ]8 Z0 U; Q4 b# r
output mcasp_afsr,8 M4 f% g- M- [" _- R5 D8 L
output mcasp_ahclkr,* g5 [. x, \6 [0 ^# Y
output mcasp_aclkr,# B. O: v7 c+ A3 q5 s: n! M
output axr1,
7 x) \/ G& X% q$ m( L l+ p8 P assign mcasp_afsr = mcasp_afsx;
& m5 P# d) D- o8 V$ Z9 }0 R: I& iassign mcasp_aclkr = mcasp_aclkx;
^, [+ e/ i [$ dassign mcasp_ahclkr = mcasp_ahclkx;& [2 m/ g8 M Q& G9 I% ^; Q7 e( f
assign axr1 = axr0;
- s9 C; @& \. A) \3 X, c
! V; i$ W3 p8 U! d, r& O& I* \+ Z- d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% u. F( f9 z2 O) ?static void McASPI2SConfigure(void)9 R" A0 d- }' q/ L( N
{
4 U* P8 S* L( f1 OMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* X9 W# ?% Z' a( [3 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& v7 l s/ v9 T9 I" y7 a6 {1 jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& h& q6 o* ~& \$ c* _4 @ U. MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# q. g# o! z# z U' SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# u7 k& Q: d+ h
MCASP_RX_MODE_DMA);# q3 }( S' y- w* r, D1 b& f. n5 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) h7 b' Z1 B, u3 L7 {( U* a/ \3 P Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 B( K* g. J2 J) I% `6 N) OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, h" J0 p- B z% M/ G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" {6 c; g) S; b1 s/ ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' X+ J' h/ \8 e5 F+ h, k8 T& vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* L; ^4 h, i. G7 |# [0 Q5 R, o# mMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 c% u, G$ B: q/ F2 O9 r* CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, z- f- Y% j( s9 k+ dMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 q) s! [: S6 |0x00, 0xFF); /* configure the clock for transmitter */5 r Q8 W) j8 {; n4 c2 J+ r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 u0 T+ }) R& c: l( T6 aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); d' n9 i% O' C& c& S0 J$ S7 q" @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) J6 @. o: z2 Z& Q% J- v1 t+ G( `
0x00, 0xFF);' e; v" M" q2 t6 t' ^9 h! t# W
. f9 f5 j4 m: b; A+ D
/* Enable synchronization of RX and TX sections */
% o6 d+ L/ o: u. f! m( o2 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ q, q, l3 Z0 }0 [5 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ B4 M! K( C) x+ M. r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( D9 z) k4 Y( Q6 {
** Set the serializers, Currently only one serializer is set as
0 j+ o; j/ c; D: H3 A** transmitter and one serializer as receiver./ O& H3 E) U! r; h
*/6 k- I. l, B$ T# V# o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: s" k! K, ~3 ^% [# OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 ]' _# z* L6 ]7 L7 |- C** Configure the McASP pins
3 D2 z: }; I$ _' X# i2 A** Input - Frame Sync, Clock and Serializer Rx
8 e% d5 R( X Y** Output - Serializer Tx is connected to the input of the codec
, R6 }' p! k6 C1 \. D8 b*/
}4 t! V/ s3 ] i g. G3 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. y/ y& s# k$ \3 ]7 ?9 ~0 xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# S) k3 T3 w/ N2 M$ jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 X/ _5 @1 j/ @/ G a& {+ N
| MCASP_PIN_ACLKX
4 {$ t5 b' v" Q| MCASP_PIN_AHCLKX
- f, l$ A! f8 c: O* D, L2 g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* P3 u! ?5 U; z+ O6 D- }0 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 f Z% d" Q' r| MCASP_TX_CLKFAIL
9 K4 ]3 Z. y5 ^/ D| MCASP_TX_SYNCERROR
3 b! g9 N5 M( I q# ?$ N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 R& k/ h) J7 y+ g* c$ I/ y/ i& b| MCASP_RX_CLKFAIL
2 T: l( `7 N5 s; z3 I1 H3 S| MCASP_RX_SYNCERROR - b0 j( H9 \6 B
| MCASP_RX_OVERRUN);
9 u3 K; x- I5 G2 \" H5 H# d} static void I2SDataTxRxActivate(void)
8 b+ j" `& l( r R' K2 {& o{
% m: B/ ?$ `3 _8 ~) q8 m$ J/* Start the clocks */
c) W- B" N) x% hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 l% q' J8 J: H7 l# m5 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 P5 N+ h( H( a# V7 y, KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 |4 d% ] Z3 ]9 m5 Q% u# s% T
EDMA3_TRIG_MODE_EVENT);
- U2 N5 K r* d: a# x) ~( e% ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 K- M+ ?( K2 e7 Y' I' e4 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% @3 r6 i g( T+ P3 o0 S1 D/ X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) a8 z: S2 e4 l+ R8 g7 v t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% S' X. E I# M- X) Z' z$ ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( L$ a1 {6 N2 d, X' ~4 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);& f! w% x3 Q4 r, L0 f4 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 }, m# s* ~* j; [2 M* A; `} ( x2 g. v T4 `8 q8 q( `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 \7 j% a, a& U0 [* U% n9 l* X
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