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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 [9 d2 j9 Z- M5 N" j, n
input mcasp_ahclkx,7 I# J4 I. c- A6 J
input mcasp_aclkx, f! o5 ^ d* v1 \
input axr0,
& X6 K! j2 `7 s5 |* h: i( X, A/ ^/ h7 v+ J# k0 n* L6 n5 f
output mcasp_afsr,
) q5 u% u' Y' E( t! q# o8 @+ Goutput mcasp_ahclkr,
9 L) V/ E- V$ A- G5 K$ V) Koutput mcasp_aclkr,
1 S( E' j; Q4 P/ B! S: J5 T. Ioutput axr1,! w3 v1 H) z1 ~3 c+ j0 i0 w
assign mcasp_afsr = mcasp_afsx;- k8 ^$ v r3 k% l" x
assign mcasp_aclkr = mcasp_aclkx;# ?" l" w" C7 s
assign mcasp_ahclkr = mcasp_ahclkx;4 D8 z5 N* l D6 I+ a; o
assign axr1 = axr0;
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( M: B8 t x8 T7 E/ p/ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + T1 C D' y( g/ Y; z
static void McASPI2SConfigure(void)
3 p( q- \* s% i7 T{6 I# s6 `1 c# w& {4 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ V/ D6 d$ m( v4 t- QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' J9 `6 C- c, i9 E8 Q1 H; F6 K1 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 G" d2 c/ N9 G5 ?# F' m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% t7 G0 @1 o" W; i$ }0 C# I9 A$ N9 P+ c
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, i& _9 Q o+ g/ \MCASP_RX_MODE_DMA); @% C1 z' w4 j. f% y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( T5 x7 K! S" ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 Q0 ^1 N; I. z2 H5 ?9 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - E8 V6 m6 I5 F) w9 I8 \' J& D6 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 d& e! F9 I+ ]" d8 ^: Y+ [0 u; w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ _4 i: T1 z" N% a5 \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 [, z* {4 n8 ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ y: @- n0 a% P7 e3 n4 M/ VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! h. D, k) j9 G6 N; v2 y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 v8 S( K4 F! x4 t' I# F$ d! b5 s. q
0x00, 0xFF); /* configure the clock for transmitter */
' V. r: q4 E( W# ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, o2 X+ u: s1 b, t+ s: a+ ]7 G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + ?9 H9 @4 @8 p$ K/ k/ }0 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) W, a' d1 Q* t2 x
0x00, 0xFF);
" ]4 ?% S9 S6 l' w& t& f. l7 E8 j+ C: F+ M7 K5 H! s2 E6 N
/* Enable synchronization of RX and TX sections */
; ^4 h1 V6 c4 e' C0 i. K: DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( @& e7 e3 b6 r+ ]1 j! ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# j) \+ j+ E! t/ Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: Q8 A1 y2 d' Z; D4 _
** Set the serializers, Currently only one serializer is set as
1 D0 X' `! h( @4 I" q** transmitter and one serializer as receiver.' ?. t. y* c9 P) C0 U
*/" h8 S! A! n X# k1 x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 `2 w! b/ p: b( ~" Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 f2 I3 m4 e) o, Q** Configure the McASP pins
* W: D7 I4 I' X- V, h- @** Input - Frame Sync, Clock and Serializer Rx& Q/ Y5 D4 C" l+ y9 o
** Output - Serializer Tx is connected to the input of the codec s# I+ f+ y% i5 E5 L
*/
5 m3 I7 M* i# Q" ~5 Z5 G9 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; h1 g5 i! R R8 ~" B, m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% n7 x8 J9 K! ]4 W8 O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" S& Z( P" y/ Q| MCASP_PIN_ACLKX. U3 j! H( o( g* L& W6 ~3 C3 e( k( Q! r
| MCASP_PIN_AHCLKX( E7 u* }* D7 V- I, g8 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 u/ X+ x& [8 ], n7 @$ n) b" |( `2 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
y2 a+ a2 D) L| MCASP_TX_CLKFAIL 6 d* V( S6 y5 s1 |% l' D+ a
| MCASP_TX_SYNCERROR
( S9 G' |* I2 E6 \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 O" u8 s$ v) [6 B* f5 S
| MCASP_RX_CLKFAIL
. X+ b- U; Y; S' P7 m$ i- j( U" j| MCASP_RX_SYNCERROR 0 s5 X& r% L! G4 Q& Q! x
| MCASP_RX_OVERRUN);
: w/ X7 Z" K3 q( j: t} static void I2SDataTxRxActivate(void)( J3 _ {( a+ I8 z) ^9 N
{
; U/ g7 l* f" \/* Start the clocks */
. f* @- P) o* vMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" o9 d, P' V% T C: I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ [5 ]# C$ E. f& ^ ^! ]% GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" b% s( h0 L/ Y/ G; t! h# IEDMA3_TRIG_MODE_EVENT);; l/ X$ w6 Y6 m' {: c+ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* _' Q9 u) }6 P3 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 v5 U) V. M" m+ h) {8 ~' k' DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# P3 E" H( W. ^& ?, {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' C9 V9 \& I, p5 j( q! e* X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 Q, i* ]1 e* a1 o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 {5 g6 L' o1 }+ W( l7 t
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: ?& n# ~4 h$ P9 H7 r
} + |' a# L4 k) R8 f1 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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