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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- j8 l0 e% a* o- Tinput mcasp_ahclkx,
. { y: |3 {1 e8 iinput mcasp_aclkx,
9 }+ s8 ^/ j$ Sinput axr0,
4 M' u. r" o a) {& A) h
. K5 H- X8 A) joutput mcasp_afsr,
" J) |. S* \1 P% C( |9 Boutput mcasp_ahclkr,
) n! d1 |+ F1 @/ |; f2 O: Coutput mcasp_aclkr,
, e% m- }5 v' C7 ^! j4 e" q% }- P4 _output axr1,
: K3 }; [5 @: p% x4 F9 o0 N assign mcasp_afsr = mcasp_afsx;
# B( d' W& Q- X8 Q+ X( I. Uassign mcasp_aclkr = mcasp_aclkx;/ R! K% i2 i$ t; h& \0 H
assign mcasp_ahclkr = mcasp_ahclkx;
# m0 X/ H: [, f' V! L) z1 {8 eassign axr1 = axr0;
, o5 {0 p, B) U8 G7 g% g* k# F) I1 i- o) Y0 g9 s% Q8 K2 S+ \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 i4 _( W* x/ \" E* X& qstatic void McASPI2SConfigure(void)
+ C) ?6 u; T) }; X5 K. q9 N{
2 d. C# E7 I6 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% l: ~5 f9 h. t) T7 p% n' A1 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" Q6 C/ ^0 G" J# u3 H! D! b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) L% Z) t' B4 o+ G2 }. CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: X! I7 ^+ P b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% Y6 i$ _4 C- w( a6 U; Z6 t
MCASP_RX_MODE_DMA);
* k5 k% f7 L1 w) O: ]9 m. L. fMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, u) R" ^; ]2 EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& D+ k. \* X; q$ dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 \% R- `& h3 a9 X2 I X9 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 y# E- ~9 v0 U. U/ oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ Y& i) ]" W; h* kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* t6 L! H7 e% t, {) X: bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ y# i0 _: J# F: N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ V% E r4 J7 z5 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 [/ \ f( j4 j0 `3 J+ J
0x00, 0xFF); /* configure the clock for transmitter */! b4 v, D" R; Y' O9 {: g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. h9 V! b8 R% c: N- ]6 y" i" {
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 O8 T4 p* c, F1 f9 w% m' vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 `0 P2 U, E9 z }1 K
0x00, 0xFF);
! ~3 d7 h" L% h" w O' g" X+ s% J( r- h7 U
/* Enable synchronization of RX and TX sections */
$ Z' U |7 Q- K9 b+ m& HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 _0 f$ Q/ U' n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 W. u3 v! v" l4 ^/ M4 V7 S7 {8 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ^+ h1 d$ a( ~7 \) g( H$ T4 Y- I
** Set the serializers, Currently only one serializer is set as
! }8 Q1 ]# N( h** transmitter and one serializer as receiver.
/ ~( ?0 _6 y4 A*/1 E. d+ }' e/ V6 [, T* B2 U$ ? m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 W) G4 [ `5 T, sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ Z l( i7 Z% s7 L** Configure the McASP pins 0 d/ Q) y! a% g8 ?( _, B
** Input - Frame Sync, Clock and Serializer Rx7 l5 E' G6 B1 Y: z# g
** Output - Serializer Tx is connected to the input of the codec 7 g1 Q4 u# X1 U; k( }
*/
, ~1 C: `7 y# h9 @- {0 ^: G% ^4 {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ K& _# T" g5 k( x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' B7 G, S" [6 k9 `8 Q' G2 Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* k# f6 P: a' V0 P7 P3 Q| MCASP_PIN_ACLKX
. V1 X- J) w" O5 ^* _| MCASP_PIN_AHCLKX0 ?8 E! X0 a2 {& K
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) I4 u$ h; W4 W. N$ {% e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ p) u4 l! P9 f1 h }3 q| MCASP_TX_CLKFAIL
" t$ m7 v d' ~9 g5 y| MCASP_TX_SYNCERROR
; E* u2 G9 k8 S( j7 z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 ~9 o9 q; |8 `+ ?4 a| MCASP_RX_CLKFAIL
, A. H7 V8 _2 W3 e- @2 U || MCASP_RX_SYNCERROR
& ]% @6 D3 {# K0 A- X9 T| MCASP_RX_OVERRUN);+ y% f3 n- t. J) K& P" S7 c" _" z
} static void I2SDataTxRxActivate(void)
; F+ X# i; m8 b# c e1 R% Z{
. X" f; y" L N2 Z4 _# |/* Start the clocks */2 b; h9 o# y7 j6 Y+ Z7 N4 n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, v% X7 c$ B R6 c& b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( O( I( G% y( W; w3 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 A( ` n, J" h5 y
EDMA3_TRIG_MODE_EVENT);
' ?# b$ l, v* I7 TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 t! f: A A& _. v8 o( q z. @* Y0 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; K/ F& D; `7 i$ L+ ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* J0 k( u% J% O/ q% L( |# I9 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' F4 T! p5 n. Z8 @+ W& dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: s$ B% W' d; j+ ]6 B& W9 J* OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 i$ s2 {. E: `8 F% I. bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 K* y8 j! ~5 e2 O" a- W}
. T$ v5 ]( X8 @: l0 ~" R4 ]" j* i. `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * L/ y: a) I# Z4 n: s7 S
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