|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 O- {+ }( E& b1 G
input mcasp_ahclkx,
- I3 w+ L m. R9 X0 k, ] `4 rinput mcasp_aclkx,
$ h Z! [: Y6 iinput axr0,
3 K- {; v B) a1 Q" M3 _) l) S7 e4 s/ Z6 E9 `2 A& w
output mcasp_afsr,
; {- F$ N* Z, J1 v6 y( A! h2 N Goutput mcasp_ahclkr,! G! c. O+ L( k* G# c# E$ b t, k* |
output mcasp_aclkr,$ p8 B# z9 o0 b, V
output axr1,
5 L9 n; X! M5 O assign mcasp_afsr = mcasp_afsx;
% }3 b3 _: t3 F# m1 J& y* B8 p% passign mcasp_aclkr = mcasp_aclkx;' z f; m9 a \# |0 j
assign mcasp_ahclkr = mcasp_ahclkx;
+ b& b! f2 c" U; E; X' Wassign axr1 = axr0;
' _8 |! E" E6 A) |) x& E7 o% D: k0 ~# g4 |* M* i, T% j/ q- s( q: @
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 F( v; p1 g4 \3 d5 S: m9 x
static void McASPI2SConfigure(void)) N. p0 a7 K) F9 [
{* G1 U/ B# j1 }& c5 y6 p2 t4 A
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 U4 t3 j/ v' ~) l! ?7 \ ~$ PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& s9 Z* a" ?0 C' l" D) X2 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 H3 p" J7 ] u5 h+ c3 o; j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# C, H1 i- [6 h$ O6 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 l: ~; o9 _% {" D/ U
MCASP_RX_MODE_DMA);! n1 f/ d! e* s- L a
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," P6 q `7 l4 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ v$ m; G" t! k4 s( `4 L, c0 XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 H5 S9 }3 q2 p; J: Q: j: mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 {6 S) e0 _% F, V @. k: Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. T. O8 A- V. z o2 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 q0 t. G' F2 x" x/ u; O* s& D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; m9 s8 F3 L! _* D! B8 H( \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 s$ @) E4 C7 c# k5 y0 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) E3 X2 E$ d" t6 O
0x00, 0xFF); /* configure the clock for transmitter */2 p% T2 t& Y( ]# `3 Y. [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 z7 p0 C7 b+ W1 W. L: HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 @- L+ M$ F1 V w2 q Q! V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, {, v, v# r* }2 ~
0x00, 0xFF);2 Y' y. z2 o- w5 G9 p( T3 K+ z$ U
: P0 P5 n A, m9 D5 X
/* Enable synchronization of RX and TX sections */
2 m3 r q. }3 f( e! p6 r+ S o6 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ v# S) P6 B" p8 X6 w7 a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- ?: L; a% V+ y" }* ?/ GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! b# _7 j. m) X2 G
** Set the serializers, Currently only one serializer is set as
Z3 D4 P7 v/ I7 Y: F8 h1 e2 }3 \** transmitter and one serializer as receiver.
8 n9 V y8 {- F4 M) m*/
! u3 g( k& A5 Y/ L1 yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 J& G! ? M. T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' ]- `1 r& ?9 N; ~
** Configure the McASP pins
4 r) c3 m2 ?' h' n" R. y0 }** Input - Frame Sync, Clock and Serializer Rx, \. ], z4 d+ M o! f4 L: j
** Output - Serializer Tx is connected to the input of the codec
3 {/ Q3 {5 m2 _*/
$ z+ _# q7 }3 }2 c0 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# `# M" G; Q' L2 C7 O, f3 hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* l# f7 I9 ^. o. I8 c" q; A8 [: Q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( Z1 s5 ^1 S. |* k- E* B| MCASP_PIN_ACLKX: v. ]6 h. q2 r( A9 ~/ c
| MCASP_PIN_AHCLKX+ E* `9 ?$ L$ r1 U1 b7 ?8 j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ ^- k, v3 K. s& m, l0 T0 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! Y, a0 ?3 x. V4 T7 f4 s- |8 o| MCASP_TX_CLKFAIL 3 A5 ~' z4 ? S: x' {5 s1 |
| MCASP_TX_SYNCERROR
, ?4 a. K! A! S% h, t2 I0 A; [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! m( V7 W; o7 O3 h/ z| MCASP_RX_CLKFAIL
' y! \% t H6 j, O6 B| MCASP_RX_SYNCERROR ; o# s0 L% s, l! T- m- x# g
| MCASP_RX_OVERRUN);0 f- f; q }, Y6 B+ Y
} static void I2SDataTxRxActivate(void)
5 c' S3 l; x& F# V0 e8 i6 }{8 w- J; k4 F4 S
/* Start the clocks */! B$ L! n3 |+ @4 `+ ]5 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 a! L& I5 W$ ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# u$ i* [8 U& b7 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- `1 C3 R$ }7 g; |% }" |EDMA3_TRIG_MODE_EVENT);
5 j7 g) q* q2 Q) J9 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, i2 T+ ~5 f6 F4 I: G3 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( r; E: E( x; \6 e& s/ W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% k+ W& F1 ?7 \( e3 v, ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, j* Y' S* r. _' Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; b" W- e) N5 B5 o# [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 G2 E* B# r( e! }7 ?; z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) V$ v) p" ^+ K( V9 B: z( x
} " I b# v, a+ Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; b& S. _, M# d |