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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 R/ o3 `/ u' l& \' g1 f" t( ~7 winput mcasp_ahclkx,: Q- P8 t1 M( f, f! V
input mcasp_aclkx,
# ^' r, h; V3 e p) \1 ]input axr0,: d1 P5 s& @! [
: T, D; L" ]" g+ }output mcasp_afsr,
8 x. `1 g1 K7 v5 y0 s" d, Q) M$ Y& \output mcasp_ahclkr,
5 O) P# p8 P7 v) e; Poutput mcasp_aclkr,5 p; a v! M1 E- O% ?" M7 O
output axr1,( U" A+ T2 g1 _
assign mcasp_afsr = mcasp_afsx;! O! }$ J( U9 b
assign mcasp_aclkr = mcasp_aclkx;! u3 ]* Y* P" g. u5 v. g' t
assign mcasp_ahclkr = mcasp_ahclkx;8 a/ g! y$ R/ h
assign axr1 = axr0; 0 `$ _8 N$ J! W& o* y
- e: x) }% r* H/ c) |! A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ \& ?# t3 ~ m: ]$ j6 C6 lstatic void McASPI2SConfigure(void)
/ a" F; q6 L* g2 y; }# N3 `{
9 U8 u+ M) J6 Y/ ~McASPRxReset(SOC_MCASP_0_CTRL_REGS);
p9 f0 O& M. F$ o4 QMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 K1 U+ V: @# z" xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 S0 k5 c: u! u! W2 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 g/ S# \8 E3 s# k5 SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. R. s0 n/ F# w5 ] u5 Z$ `/ H3 E
MCASP_RX_MODE_DMA);3 F8 u& o1 G9 R% n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 `8 ]4 \0 K+ aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( i/ Q- t& j, N* W$ V4 G3 l) k% y) zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
G; E9 V7 `( l- r1 N8 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 | V' U6 H+ t5 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' w! { a e: p& H) M wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 K3 [ I- p7 |, [) LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' X+ y" A" l! V1 Q8 D* y. O( mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 }- k& O/ w9 s f( ]' Z. l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 q0 {5 {+ S' v, ?
0x00, 0xFF); /* configure the clock for transmitter */
% |+ M* N" d/ h/ BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( Z: Q" E8 i: d; Y& V! J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 t7 y" ], i K% ^! B+ i+ }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 c& U7 b& M" s3 @. m0x00, 0xFF);( }& x( l5 M; ^7 Y
' r0 c+ b! |2 t3 L% i* ?/* Enable synchronization of RX and TX sections */
. f h+ H1 ]7 Z* E) `9 i: d- jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 i% }' G3 P, n4 F8 i, ` VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# B1 N& H" h4 i% Z7 `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ x4 {2 \$ G5 `! y* {** Set the serializers, Currently only one serializer is set as
, S7 \" D3 N( h' a j; w8 i** transmitter and one serializer as receiver.
/ ~0 c, l2 d( K/ h g( ~0 T, W0 |*/7 T& Q0 ~% H& y; ~1 g1 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- |) M1 [* E$ A( b4 OMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; E, Y! p. t; F0 o** Configure the McASP pins , F" @) i! ?5 e5 T9 e. C% q
** Input - Frame Sync, Clock and Serializer Rx' m" g! I& v4 k6 m
** Output - Serializer Tx is connected to the input of the codec
* z+ H0 q9 Y" u/ W- |# ?8 h*/+ L6 t+ u4 b5 v+ M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); D' v @/ }' Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ F3 R s3 ]# a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( V! Z/ a8 J4 U
| MCASP_PIN_ACLKX
/ X9 D8 o/ a o) _ u| MCASP_PIN_AHCLKX" Q4 @2 s1 I" Y' i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# z3 t$ f; ~; c2 h+ c4 G0 iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ {2 s/ K5 S. C* M8 I4 K ]) ^| MCASP_TX_CLKFAIL 4 W( z0 V5 B# @! Q, w; C
| MCASP_TX_SYNCERROR3 ? u' e8 e4 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 k9 l% ~ U) W
| MCASP_RX_CLKFAIL, r4 N5 C& v9 n
| MCASP_RX_SYNCERROR
0 d( g" u1 H$ A0 J9 T, r5 N& E| MCASP_RX_OVERRUN);7 W& m0 ]7 k/ E9 C
} static void I2SDataTxRxActivate(void)
0 u0 i+ S0 K; ]# o{- `+ e- G! G% v& g
/* Start the clocks */
2 S8 [! W4 X9 L3 \' O3 T) IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 `- q& s" [# J" {: @2 n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- j# q% {9 A9 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 ?( j0 K& _9 b
EDMA3_TRIG_MODE_EVENT);
& E E# x, q9 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! [7 M$ W2 i4 X0 S2 x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: p C9 c% b3 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# x% E- P. S( [/ W0 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: ^; m- ~0 a- K4 ~! {& p/ @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( k/ |5 o2 _( J4 {3 U5 g4 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 r" j- D K" k' \' j6 e4 ?
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 p6 c) e1 O- J1 L+ e
}
0 e! K+ D/ g+ k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 _0 Z$ o; L# }* U0 H, ?* D4 h |