|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# v0 k+ B p a) f6 [
input mcasp_ahclkx,: }( w% T9 s1 s- Y6 _, w" E
input mcasp_aclkx,# V; a4 |0 U8 W/ s5 z% @
input axr0,% I- D3 ?6 C0 @! U5 G% z. @3 K
* l( q% y5 b, z) F
output mcasp_afsr,
1 c* ?' E/ G$ z2 v* eoutput mcasp_ahclkr,
+ j3 y6 O% a# x6 O- b! p' g4 loutput mcasp_aclkr,, ~, k( a" R5 t& ?
output axr1,
& g9 k; S6 A3 S7 ]1 E assign mcasp_afsr = mcasp_afsx;+ ~9 ]. u9 N8 |, u7 ~
assign mcasp_aclkr = mcasp_aclkx;
. }) J2 z. l+ k5 P9 a# O4 {assign mcasp_ahclkr = mcasp_ahclkx;/ |9 F& D, X" z ^
assign axr1 = axr0; 1 t( g% j: b1 R6 N
2 {# V% I$ I, G) C& ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * c( h+ g% u* b0 a# R, i1 ?
static void McASPI2SConfigure(void)- F5 p- R, }; E h: L* b7 A' S3 A) t/ f
{" z* g4 E' j6 d/ S# z0 ^* _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 B. G+ ^; T6 p9 q8 X4 R* a2 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( r/ A5 G7 ]" |- i2 t" KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 U- K/ }( U9 k) |/ ^: _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 n: E4 ^4 N; E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' L0 Z5 W( {! v2 J, e6 y' mMCASP_RX_MODE_DMA);& X% \4 j4 N; @4 T7 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 |$ V/ V$ `4 X1 X& X2 W- rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 \" l$ S% f% YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" f4 y+ {! [6 z' {- zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ }8 k7 l3 X+ T( ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ @" ?- M1 T7 }2 s$ ? T. c' z. s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" V6 c2 b! y- P1 M7 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' n6 p- y5 U, M Q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # v7 D" L' K7 ^. K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 R% W( b5 k; Y2 j* E4 G3 x0x00, 0xFF); /* configure the clock for transmitter */: t9 b, ]% b1 \/ _& P; x6 {4 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) h4 k, q2 M4 c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 Q+ X# C6 o! Z3 d5 T* J$ o. S2 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) A- K1 b5 B; d. T: k2 E0x00, 0xFF);& a9 M( g4 a# {& V
: ?8 k& p' }8 [ N: S4 C) B/* Enable synchronization of RX and TX sections */ , ~& V( c7 l* F+ l3 S" C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, v- v( z* Q3 d5 H- V! OMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: w% w2 l# J7 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 e' s- D8 b; E5 F
** Set the serializers, Currently only one serializer is set as
; A6 l, F& C; V% |, ?** transmitter and one serializer as receiver.+ U% w J0 K! X0 `
*/
8 `: r* W0 o9 V' F; P8 h! `2 nMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! U3 M- Y& W+ Q( F a7 M" \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ r2 u; Z# |; z% @4 _4 \6 P; @ W
** Configure the McASP pins
, @; w5 `% F/ {: V+ J** Input - Frame Sync, Clock and Serializer Rx
+ Q9 f8 u" Z2 }3 I5 c9 v** Output - Serializer Tx is connected to the input of the codec / E. x/ m: b l( [+ i% ?
*/
/ s! v; q8 s* F- E' `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ J3 z/ I3 A) j: TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& ]; u! d" [5 N; U! BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ X4 S0 X9 t: f" q$ \| MCASP_PIN_ACLKX
6 R+ K" A+ ]2 b. I2 O( ^| MCASP_PIN_AHCLKX
" {4 z. g, v# a9 L1 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# X% K% f& D$ C6 o! }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * ]/ a" j( [/ v5 y" ~' v
| MCASP_TX_CLKFAIL n& Y3 X. e3 _7 x$ t* X
| MCASP_TX_SYNCERROR( _5 J6 w0 `! s. a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
4 J, U0 f$ H' ]| MCASP_RX_CLKFAIL9 k8 c* ^) Z. K) a5 ~9 o
| MCASP_RX_SYNCERROR
U1 {! v* {9 a7 G. ~, {| MCASP_RX_OVERRUN);( w P# q: c* V' M7 D3 r
} static void I2SDataTxRxActivate(void)& \/ h$ x/ i+ b6 o( v3 U# Y% t
{) d! n$ i- c% Y- f" z0 e9 h
/* Start the clocks */
* F$ a% j U7 r, Y# q2 J& E9 iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 b( m9 w- k9 W2 s. K! |( Y6 s9 _3 kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 Y e3 d1 [ HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ i* p, S+ H2 I) M7 m+ O$ YEDMA3_TRIG_MODE_EVENT);2 k# w* L" p$ n5 W" L9 f9 w# X8 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 ]* ~" y1 N, N8 D' ]7 AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
^8 m! I( Z/ v! C3 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; r# i1 r V6 V! F4 g& k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 p; [1 z# S" e4 E% l& i: x& Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# B& z8 G0 B9 ?6 f# a0 L: ~2 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" R3 Y( R! N' N2 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, r" e3 s$ _- b0 D7 @$ c, A
}
9 g+ x" D b/ x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
3 \( V% a, H3 h# w& o" Q7 a5 K* L |