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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 \- Y" }3 E5 d$ ^
input mcasp_ahclkx,
- Y# O' U9 a6 q' u! _input mcasp_aclkx,/ N* _1 H: I7 k7 Y+ |" K% _0 s
input axr0,; W1 i& a0 U9 \( d
L# x: r5 j6 t9 ]' Z# X
output mcasp_afsr,
4 _" @' h( H2 C. t( houtput mcasp_ahclkr,
$ n3 z4 p6 H4 ~# `3 }7 ooutput mcasp_aclkr,
( N# E7 w$ [3 e/ j7 l" s; {7 ^output axr1, O+ v: }" X( L# X
assign mcasp_afsr = mcasp_afsx;
& @$ l; l/ x. g5 y' d% E2 Y7 massign mcasp_aclkr = mcasp_aclkx;
! A; `" O! X, Q oassign mcasp_ahclkr = mcasp_ahclkx;! p9 o- r: N# R
assign axr1 = axr0; 7 r$ N, {( R: g% K
+ X1 B' v1 J, d! y! B/ S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 b4 w; V! p, S% c, a7 C/ Ostatic void McASPI2SConfigure(void)
7 H O/ e4 G# J2 k9 B$ J( G{
7 X2 t5 ?8 X$ O5 h# ~6 i' nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
* B' t* ]& p/ R. {7 @8 p2 ?" kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- Q, ]& f, u. _$ Q6 A9 }) ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 D. T+ M9 E. x c* w3 X$ ~8 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* z" ^4 ^5 O% x7 r% `5 s+ e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 u; J( v$ @. M% z% ]$ r) vMCASP_RX_MODE_DMA);
% t% O5 Z8 @" lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 O& |1 F& j" [4 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( U# D, q* c+ t7 B. a* ^1 D0 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , _% _' H& X! r+ o2 r0 [9 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; i: a3 N6 W; p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 X3 `, L G/ w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 e. z; i8 d- c) K# A/ @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: X7 d# l* Y% BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' |! }* r0 R+ l& m6 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. l/ m4 g5 }1 @3 u) ?
0x00, 0xFF); /* configure the clock for transmitter */
) a" C. a& y! m. W- yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: F! P! c6 F0 l. yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 O& g( M- n- L6 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) t3 G1 u4 o% [ O; i3 W
0x00, 0xFF);
7 L6 N% g, C& y9 J8 n9 n+ J
{# Z9 l h2 _2 X& ?/* Enable synchronization of RX and TX sections */
8 ?9 I$ Y/ _1 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 K6 ~9 q V$ H- mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' O) y6 c5 r) ~6 R: p& s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% O0 s1 N, N' S' V; m6 W** Set the serializers, Currently only one serializer is set as
: b3 J# I( U V6 C1 @** transmitter and one serializer as receiver.; p8 K& X. r" V _9 R2 ~
*/
" @: b& n$ h3 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" k7 v& }+ O# b# o6 ?, }8 TMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; T: b5 ?# p" W' O3 P$ {7 J; M
** Configure the McASP pins 0 T" S$ Q" G7 Q: b
** Input - Frame Sync, Clock and Serializer Rx! I7 w) X* F0 n. Q4 v4 l. y8 o
** Output - Serializer Tx is connected to the input of the codec
5 F o2 m! Z0 I6 f) }8 [' H*/
. K$ L% `4 N2 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. w5 `+ o& [# Y# f t6 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 u# y5 M' A1 g/ |; ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* t! Z1 Z. t2 ?* ^
| MCASP_PIN_ACLKX
2 t- o2 `% a Y0 n1 k, X- r* b| MCASP_PIN_AHCLKX* T `3 Q% |, A) A; g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 L# ]! D2 }* o8 QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & G$ i* g) }9 Y3 ?
| MCASP_TX_CLKFAIL 7 a+ r" X4 t' @
| MCASP_TX_SYNCERROR
! R# z9 Z: f: e; r4 s( U) X9 y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " |: O+ a3 K) {2 y' K' S$ v- L3 m
| MCASP_RX_CLKFAIL
6 V- A/ ^6 T m% {| MCASP_RX_SYNCERROR 4 c, I% _) k' Y( ]- p: K
| MCASP_RX_OVERRUN);
. s( y) r% \+ r. P+ [} static void I2SDataTxRxActivate(void)- f {3 j1 ]- x0 d+ f: a
{
Y3 n; r% Q1 O; `4 N7 w2 \- Q/* Start the clocks */
* R( m0 r" C) H% D2 K. iMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% x1 c; s! x1 l$ ZMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ l2 P/ m' G! YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! ~9 {8 @5 W8 V1 @& {/ x( fEDMA3_TRIG_MODE_EVENT);/ v* d8 A& r% Z7 b$ q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( y* E! M- ?( v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% V! X( U' u4 i% d T4 l) DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# J8 x, Z D; n2 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- V/ {9 n7 X: n" F. u9 C( S' Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( L% ]0 u( D+ b' Z" m4 q9 E/ i' DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 W3 Z5 l$ A. l! i0 O- L, ?( j% l& tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, c& X- T! X8 o, K
}
; ` x. n; \( h) s+ y" ^6 R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ Y% w! I4 e8 L6 Q* M- d
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