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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# n3 U) a& ^6 linput mcasp_ahclkx,5 J8 c) E# s3 A- ^" |2 V( s
input mcasp_aclkx,$ ?% x* S6 m7 y. k) y3 Q% c% t
input axr0,
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1 D, J9 M J8 s" V) n R3 D2 {output mcasp_afsr,, n2 y* Y; k4 R. i9 O* E+ z
output mcasp_ahclkr,
: I: v3 a9 f3 ]: Foutput mcasp_aclkr,
: U$ z+ s9 F4 Foutput axr1,
2 z/ M/ O) I& G# j+ ~5 | [5 J assign mcasp_afsr = mcasp_afsx;
6 n5 [# U `, ]7 E/ b; K5 Bassign mcasp_aclkr = mcasp_aclkx;5 N$ L3 A# \# N5 L7 ~. \
assign mcasp_ahclkr = mcasp_ahclkx;
% K* d5 Y) n7 N4 @0 z* qassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 A2 A7 X# e5 F
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- V/ ^* X1 q( N3 f( a) cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ w/ B( P9 o; aMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% I3 e) W7 t5 _, R- w0 ?+ JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" w3 T1 g2 z0 C( a, o1 C+ |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' v* m% W$ l, V% h* `% r4 x8 @5 d
MCASP_RX_MODE_DMA);& A" e" _8 O5 w% z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 E, _+ H8 W1 P' c: oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! N2 f& a' o& A$ {0 Q+ f* {( Q YMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
s$ O; P; ^1 e! h z4 g( X; GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 q' D h) O" ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" \ Y8 Y& k7 A6 o5 R/ j9 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# B5 P9 m% |1 B( s1 |: XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: H F4 ?5 g0 }3 f
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : ^# @- s& o3 o8 S3 p- Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 v( G& F7 Z; ^" F. {" E
0x00, 0xFF); /* configure the clock for transmitter */
8 ~" `) d H8 k( XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 c9 L" u1 S1 Y" `" [+ z0 A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, j0 D, m3 c/ t* @ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 g: ~! x0 l: c3 Z! ^$ w5 J
0x00, 0xFF);9 t$ W9 p# C$ p$ O7 @
7 R2 \( C/ T+ }/ W- u/* Enable synchronization of RX and TX sections */ # x: ? B# x' J- ^! k; z4 F! w7 z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ p- M: U6 D" t# c0 r( T! t( l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 ^7 `; H' @. `1 m: M- E8 Q$ C* O \$ fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: k8 s* T/ Y6 R: y** Set the serializers, Currently only one serializer is set as
. w/ _) s" Z: _** transmitter and one serializer as receiver./ w/ C% L) I, G$ Q
*/
4 D8 m& |2 S) f7 j* u! D+ `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ n0 [ W2 N8 M. W9 {
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 h& r, V# L( V5 |+ \** Configure the McASP pins 5 @2 u; T( S9 v2 O" z! O" z7 h
** Input - Frame Sync, Clock and Serializer Rx
$ t+ O8 \& `" \. P** Output - Serializer Tx is connected to the input of the codec 1 E2 ~/ ?. z& [. V. O1 I% v
*/' ?# P" D3 ~$ b1 ^4 V: `. ^- S! s2 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ W. L( E2 Q3 v. ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" K/ G& P5 V* hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! k$ f" b4 C! B
| MCASP_PIN_ACLKX
; a( ^1 V) f3 X# J| MCASP_PIN_AHCLKX/ W# s; u- B$ p1 G B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' V: l6 A0 N# K! _7 [& lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ H( e6 V' v" v& y! t: Z9 R| MCASP_TX_CLKFAIL 1 M8 O4 K3 Q5 v
| MCASP_TX_SYNCERROR
0 w4 N. M7 [3 I) D- q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 P" R$ \+ d, Z| MCASP_RX_CLKFAIL
7 _( S7 |; ?0 ?3 S- _| MCASP_RX_SYNCERROR 8 a* S5 A) I4 o/ \2 f' g7 i. `
| MCASP_RX_OVERRUN);7 I* l& ~0 }4 V" D( c; Z7 [0 Z/ n
} static void I2SDataTxRxActivate(void)5 h" V5 X, `0 q m' N2 G# {! i, L
{6 N; |1 H* ~# O/ @5 k. q; I1 g' _
/* Start the clocks */
, m( r5 z/ u, {6 O2 l3 d8 y" W# LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ H7 B( b( \6 j4 H4 V+ E6 z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, f1 J) i1 V* A! x" u- _8 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. N+ G% o; x( ?: j) O. a
EDMA3_TRIG_MODE_EVENT);
1 G* H' i6 S/ ` @2 s& D6 g& G6 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * Y8 O& @7 N' n0 p5 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. a& S6 D y t/ W! h: V3 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, o$ h* h) d7 H& M- G m3 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" L" |* Z) w: l7 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 w9 E" O1 @! n K; R2 n3 m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 q$ c6 d$ X0 I6 q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& n3 q D F) ^: O} / g4 T, r! U1 l8 d; z0 f# }0 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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