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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 y) w T( B0 J; b+ A G; B& ?" _6 xinput mcasp_ahclkx,, k. c! w. E |, k. e8 F) C
input mcasp_aclkx,
- r8 [/ P7 D! |input axr0,
3 ~ G# M. g# x4 \9 ]) I$ _3 G8 D- v T ^0 m/ t% Q
output mcasp_afsr,4 R; A. @* I% f8 Y# j: R! v2 A
output mcasp_ahclkr,& K% \) Q- x& u5 j0 m; h9 {
output mcasp_aclkr,
$ ~! G M9 o; K/ ~$ v9 Routput axr1,* w% q+ D N4 `* N8 D5 J8 o
assign mcasp_afsr = mcasp_afsx;7 ?3 r5 t2 K) Y E1 {! `
assign mcasp_aclkr = mcasp_aclkx;4 d- s) x( |4 t' A. w
assign mcasp_ahclkr = mcasp_ahclkx;
6 a0 K8 i9 `0 \5 f9 s2 zassign axr1 = axr0; 6 k- F8 A$ `4 z# W2 }
$ K, q" {0 k% V4 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, m; r0 x+ v* Cstatic void McASPI2SConfigure(void)" {: Y' {2 d1 L: b. H( g
{
O- ]5 j9 @ M; {2 \9 p1 E5 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 L A/ O3 \! L) l$ gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* [4 G) H+ `; B9 B4 P; M( @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" l& g. J; {0 p6 xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: V, F/ b) x' A/ n% H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' t, a$ Y/ M) ^$ HMCASP_RX_MODE_DMA);* ]2 K) Z( L& ^- Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, x' ]8 ~1 u' p. G$ a/ ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* [ R" L# s4 k3 [* D3 |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * h- Z$ R: O/ ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) f, Z! k) |4 O) b, OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! I1 C. r& B& G8 pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) X8 ]. A# K5 J, l. C6 u% w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ @ y. [# g; r5 G/ @/ j8 l8 H9 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 d) B3 c7 l- c- F8 w$ b+ W0 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& Q/ M' u. p2 ~0x00, 0xFF); /* configure the clock for transmitter */
0 S* j' {! |0 J# _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: b" Y# b& U1 R; d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % H) Y* W' q) g2 b! F' z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ }, r3 P) `2 P8 t0x00, 0xFF);
7 x9 S( q6 h8 U, ~# m2 r4 X7 u2 c( b( j
/* Enable synchronization of RX and TX sections */
s7 h% u1 w) tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* v5 n6 {, G, ~( _& r: E! pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
}. j" b) ]: `) s& |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 f5 Y) ]* ]% M! {/ z5 h** Set the serializers, Currently only one serializer is set as' _- _$ M8 T3 X w3 n
** transmitter and one serializer as receiver.' r2 Q+ P( m* W) I9 |: U
*/
0 w" I# k+ J' |/ C: u% SMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ l, b6 u' a! T, n: w2 B9 S" B* r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ L# S9 V( s l* }4 B** Configure the McASP pins
7 ^' T. N+ W& R( i** Input - Frame Sync, Clock and Serializer Rx5 @3 B& a9 X$ V: \" i+ f
** Output - Serializer Tx is connected to the input of the codec
7 N5 f: M- J1 s; V" E6 j" @4 n*/1 }( b% d, `: G" r) i% T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); _" K2 S* M' O( F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: P- l+ U: R" i! Y; h0 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; T: l& c5 Z, e3 Z| MCASP_PIN_ACLKX- P- w# l2 H8 ^; X O# S
| MCASP_PIN_AHCLKX a& W, Z5 B7 n6 n! o& k9 [" x& F6 U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 L9 i% G6 u X& `5 ~5 V" j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) D; L, E/ h5 q' J4 h# T! Z6 z
| MCASP_TX_CLKFAIL / `- h3 @/ Z, b) U6 z( i9 f$ f
| MCASP_TX_SYNCERROR
" B) c' |7 f1 F; x9 e& U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & x0 q/ o$ Y3 R3 ~! h% ~
| MCASP_RX_CLKFAIL
2 B+ I# }" v0 T! l( ~6 L| MCASP_RX_SYNCERROR ) {9 y+ ?* \: c; h% K4 o
| MCASP_RX_OVERRUN);0 z# ? U9 B8 n* H- L9 v
} static void I2SDataTxRxActivate(void) H% w/ F0 G5 e$ u9 A. y5 V
{
' Q+ V, L# f4 ]8 z: {3 U/* Start the clocks */
/ \' G, l% y$ EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: J1 z5 m; o h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// d8 Z" S( S3 |# X4 L3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. L2 K: ^, G- n1 ?EDMA3_TRIG_MODE_EVENT);1 A" G4 D2 K; H( q% X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) c+ P6 X8 r$ _5 _% \- V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 F0 b0 y1 z1 m) q% u8 YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ A* w0 P. d; S7 F$ ?. y0 S, m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) H. ?. d0 q1 H! j' K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 @8 j! L. e9 c, m' u1 u' oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- |, D- d/ ?$ M7 \% k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) T3 f" ?2 ~# h& \* ]. y} 7 ~& ]- ?! x4 G3 V3 j% j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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