|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* S5 z$ Y; g2 L5 Iinput mcasp_ahclkx,0 R3 `$ z A' ?6 U) V
input mcasp_aclkx,! T- m8 ?0 u5 R# d/ I( N1 n; [; }
input axr0,
4 P @7 l- [; M' K6 }8 v
8 Z1 e6 [# J' K3 l" Y$ A3 u# xoutput mcasp_afsr,, j/ H5 d/ |% c2 Q, ], Y
output mcasp_ahclkr,( D/ C' q/ \- ?8 U
output mcasp_aclkr,; U& Q3 a! ~ X" m* h7 A/ }1 g% V3 f
output axr1,0 y; o r' Y3 p: t& x
assign mcasp_afsr = mcasp_afsx;' k! F' C* f; U
assign mcasp_aclkr = mcasp_aclkx;( | T0 S2 m3 [, s' W3 i5 G
assign mcasp_ahclkr = mcasp_ahclkx;9 ^* _ z0 x! L# J9 H( C8 @
assign axr1 = axr0; $ T+ Z2 t* E, `3 }2 e2 y, x- n
0 ^& J( _% c( G, J+ I9 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 p/ b, X( G. l7 ?8 g- Estatic void McASPI2SConfigure(void)* ~: F3 W' r- d# V2 X- c; ?
{ {8 o. M. U! y; k, d& f7 q9 I* R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: I$ @$ h* ?( B0 b
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* Q; y$ ]& v6 i' F
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 z7 v" ?8 Q+ iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 k. ]5 _3 N; R- n+ B6 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," B9 e. L2 r" J
MCASP_RX_MODE_DMA);) i" N, A: }/ h0 G r1 e8 W; c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 G- L K8 H6 O& N% i( U( F: A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 y4 C D" |/ m) V6 K& q$ V
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- ^* i4 x' {3 @: ^, i5 x! rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 t6 q% u& h, s$ I4 Q8 rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; d7 K( e$ y7 F M& g& d& I+ vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ j4 r9 e! t- e+ I% [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. n) }. P1 `* {0 G( ZMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 k2 f/ ~6 ?' ~0 U$ M# h! lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% d. e! p( V& B y6 E0x00, 0xFF); /* configure the clock for transmitter */
5 c$ m4 q" F% i4 LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: Y' N8 g J$ t" O6 nMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# l- p0 P2 F" ?- ]8 `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 u& V- X4 I$ p4 r$ R# C1 c6 k
0x00, 0xFF);
2 Q1 ]: X" D8 ~0 w
+ H( r8 h: \4 }0 D/ i9 k# X/* Enable synchronization of RX and TX sections */ & _9 n4 r9 W8 e' d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 w0 ^3 p1 @/ [ ? w8 ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 N& d! E' ~; `9 l* H2 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; G1 g- {5 [0 i** Set the serializers, Currently only one serializer is set as+ t$ v7 ], _: k) @+ s: _
** transmitter and one serializer as receiver.
0 S5 Y* J- F a2 u" p; k' {2 `*/
1 i' `* c3 ]9 z& B, N/ KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 W% q+ G2 T8 G/ V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" |3 u- J- a6 ^4 u
** Configure the McASP pins + B% Q+ }+ D* D& L9 w+ K+ T
** Input - Frame Sync, Clock and Serializer Rx4 _5 R1 q4 h0 b: {& R7 G
** Output - Serializer Tx is connected to the input of the codec 8 w5 Y. a+ T" o6 h$ j6 T
*/8 L; b0 x1 s! W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' t, k8 f% ~" C0 |0 t* w( e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# q: @7 r( I6 Q2 R8 n; M9 k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 J! z6 T; a9 h) s2 v' b8 M3 ~
| MCASP_PIN_ACLKX5 D0 A* T/ g! r
| MCASP_PIN_AHCLKX
: x1 W0 i9 V; p+ d$ e7 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 L) a9 A% z" d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) f2 A& C: N k1 d
| MCASP_TX_CLKFAIL + K, |/ c, n, }
| MCASP_TX_SYNCERROR
' V4 I; ^6 y: @- g) F6 y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: A& s& j$ K& z& _. R| MCASP_RX_CLKFAIL
9 P2 Q; k0 C# v4 z! i1 E" n3 A| MCASP_RX_SYNCERROR - w! Q6 v" j* ~( L4 ^5 A
| MCASP_RX_OVERRUN);2 e3 H* p( [: @# d. a
} static void I2SDataTxRxActivate(void)
$ j+ t$ L- c4 r/ _{ U, P2 k( b% t: @' S9 K7 d
/* Start the clocks */
9 ?* D2 V9 m" g( I' z" P4 U9 W# ZMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 A+ r. l: x9 X5 [8 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
q/ q/ x) r/ J! _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% B; O9 f3 {+ e! B" a rEDMA3_TRIG_MODE_EVENT);
' n* A! [7 M+ V# e @. I* b9 k& P2 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ P- j: Q7 ?, P' v2 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 I. y( ^2 K8 e& IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 @, `: n# g1 p b+ ~3 I( K. sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 Z; J2 k& [: u* N" j1 r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ S# C/ \+ x# W; |* P6 G) UMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); [9 U0 X$ x1 u& X4 C }9 E: x- b' w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' F. Y: w- ?+ a} 0 S# m! V5 V2 G
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 ` \! _6 q! { t5 X1 { |