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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* ]- m# [" r R4 E; u7 h1 tinput mcasp_ahclkx,8 T, M! M9 r( g2 S( K7 y
input mcasp_aclkx,, w3 R6 c/ o: M$ b1 R8 P
input axr0,0 C2 k+ m% N$ f7 [6 x
0 g9 d, [4 \: q- _9 U7 e
output mcasp_afsr,. _3 u" V. p6 e* q; J
output mcasp_ahclkr,; H. C! E& m2 I. O: G
output mcasp_aclkr,1 H; @# c+ U( l! u0 L8 X0 z
output axr1,' i7 b& E. J. |9 Q" P3 t
assign mcasp_afsr = mcasp_afsx;. |6 g6 A c6 H) U- H4 t& T$ W
assign mcasp_aclkr = mcasp_aclkx;8 j$ B. K* t" K" t/ p3 k
assign mcasp_ahclkr = mcasp_ahclkx;) K7 ^ _8 A3 i7 w2 r
assign axr1 = axr0; 3 l E6 m8 h+ V$ d
* ~/ h9 {' X. _ {3 z( R0 t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ H+ C, |$ O5 {: M6 |2 e" K; }
static void McASPI2SConfigure(void)
. g2 |6 ?0 k' u3 m{
$ D3 y% J& z% J- _$ M3 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 d- G* G7 ^/ A2 D) v3 I2 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) e2 R8 q/ t( I+ mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; D1 ]' \ m+ q* zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# G0 z9 n3 o" t7 W3 M' XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 V3 n( r0 ~! j' P& Z& O
MCASP_RX_MODE_DMA);
& o5 F! P, G! `% R# i2 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 H, p8 Z6 \ E& R; ~, G9 E% d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 E+ d2 Z- I9 ?1 k8 r' CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 b. n: H5 N6 O' H- C+ ]' g0 A8 Z; @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 h* L, k; d: j8 B/ l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 |% [% m* X1 n2 C' i: pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ D9 ~6 Q3 d: t# z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 X2 `& t6 b2 D% M U2 M2 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 @' H. e5 G& b! a# F/ z( Q* p9 Y# tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ X+ I2 v c8 d3 U3 I0x00, 0xFF); /* configure the clock for transmitter */
$ p0 n& z' m3 k. G. yMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 K9 K9 Z$ v/ p9 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " m5 x9 m7 y- B9 c
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; V* z0 p. J% v. V0x00, 0xFF);9 t7 o/ P0 G. T. [2 U
4 C3 w% k- r `$ r
/* Enable synchronization of RX and TX sections */ 5 ^! R3 A6 X! r3 h5 P9 b3 C- S( [0 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' C ]0 k t# g7 [2 l+ k# g& `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. G t- |: |; Q6 S' J h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% @# [1 \ E1 \# F# K# F5 w7 G
** Set the serializers, Currently only one serializer is set as; H" }, s% Q/ @! C5 y+ I( m9 a
** transmitter and one serializer as receiver.4 D6 D: {: g6 j& C# Z
*/* F! m7 D3 k3 O
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ w: A2 l: S/ f: f6 ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 F+ h/ p, B6 a
** Configure the McASP pins . V: O$ T; z0 s
** Input - Frame Sync, Clock and Serializer Rx+ \# `% \( E/ h# F, `/ T
** Output - Serializer Tx is connected to the input of the codec 5 O/ T8 }( L7 k' l5 [0 Y- J
*/1 b( w( P) X0 s( B# E/ G4 G5 `) Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 j& R' w8 e1 W3 d) o, ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( y+ R8 p3 E% z1 a3 Q8 L+ K2 V; t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 }- g7 }" f7 \; T* r+ S| MCASP_PIN_ACLKX
9 a. y0 q2 v h! b| MCASP_PIN_AHCLKX
[$ I* g8 L8 S3 m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 V* o: }2 h0 d$ s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 W% v p- r* S
| MCASP_TX_CLKFAIL ! L- P. `4 q. e1 ]0 D
| MCASP_TX_SYNCERROR! |' Y( L4 g2 z0 H) Q! l: G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 s* B2 X' b$ Y
| MCASP_RX_CLKFAIL
+ X: c; b7 ] X) G& `# y. k1 Y! s| MCASP_RX_SYNCERROR ' l: t# Q( K, Z. p( x! p, V
| MCASP_RX_OVERRUN);+ T* H$ W& J' n* w; I# r; m, Y
} static void I2SDataTxRxActivate(void)
8 l, g& s3 C7 F: y- q; r, v2 O$ H{
4 h T3 W" X4 P' y/ N( A# z- `/* Start the clocks */$ K# S2 T8 W& d! Q# {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* e4 U8 H& F! K7 H3 A% ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% S$ o, f! B2 Y' UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," R# p1 b' P0 f! F! b
EDMA3_TRIG_MODE_EVENT);! }# ~4 `4 _8 x0 a3 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * y( f8 u% C, A% q0 `) x, F
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 B* L# ?+ V" r
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
z: {- B' U1 u" v' c, }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" ~: w% f/ y" [% H2 T5 D- Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ q$ e( U) i# p1 |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 U! Q: T4 X9 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) f0 Q& r( @' D( i% b' B
}
0 ~. r Y: b0 n L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # @/ f0 I# C% B( u4 ?
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