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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 P5 O% J5 {2 L+ c2 C0 q
input mcasp_ahclkx,7 U; I3 l/ V' r
input mcasp_aclkx,
7 M0 G& o5 V6 p) z: \input axr0,
5 Y; Z7 [8 k4 j0 D2 J/ n
) s" x8 e f7 R: Z7 t# n4 I( goutput mcasp_afsr, F0 ]! N p8 T* j7 w' z
output mcasp_ahclkr,! {$ Q: `3 R/ Y& G7 Y4 m7 V( ]
output mcasp_aclkr,
; q" P! k7 ?0 f7 W! woutput axr1,
/ D# D. R; c8 \) `! a assign mcasp_afsr = mcasp_afsx;# T- h5 O* [" V9 @0 O
assign mcasp_aclkr = mcasp_aclkx;
" v/ Q, L" w _8 J- t) iassign mcasp_ahclkr = mcasp_ahclkx;
1 z$ a9 Q' G& Xassign axr1 = axr0; 8 `) W `. m; b5 [0 H- W" U1 @9 Y
# W7 Q& J* s/ A4 O4 z; L1 w: I5 Q" g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ k& m9 I) U* N: V9 y2 R, cstatic void McASPI2SConfigure(void); T w2 L$ R! m( f/ q# m! ]
{; B- i. {1 v4 P5 S0 ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS); Y+ ?! }# \* R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 n' z% }4 }/ {5 c6 h; \: `6 p) C& N* }: @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, d, m9 G3 ^! L7 O4 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 z: A* W. I2 j5 i3 B5 l0 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, K* ~2 F! C1 v X }0 J) z: R( i
MCASP_RX_MODE_DMA);
, X" c1 y8 R2 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ h) R: o* c! H/ p1 m$ I- o
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* V) Z; B/ a# S/ g" i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; Z/ L [$ M, }2 R" _7 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* |) ], O' {9 S S9 I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / \. `; F: y! L. R* |! k& R) q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 |4 d! x+ j; xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% K6 ]$ z9 y4 L- p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ J, q# s% ^. N$ n" w. h1 R/ lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 K3 `! `1 A; X2 g+ q- G& v0x00, 0xFF); /* configure the clock for transmitter */
" N6 Y$ e5 T( kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 A7 b1 e7 z s+ A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); X' ^2 b: B) O. c% ~+ h
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ L0 G. y4 K( m4 O( E' B0x00, 0xFF);
, K- u t! p0 H0 d2 k/ V t% g
0 e$ I& u* w& ?" k! T j/ b7 G/* Enable synchronization of RX and TX sections */ 9 O' G+ m* k" a$ f7 y T+ A' ~
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% ]# A. B2 ]( i0 j9 f$ Q0 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 B2 A ?* |% V! `6 o: V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 l! E, r' F3 V% {1 H* E" Y** Set the serializers, Currently only one serializer is set as
8 i' v) G$ e+ e: a. v** transmitter and one serializer as receiver.0 X+ Y; A# _ W% A& u
*/
% U! b. H& ?: a5 r- M' DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ v; O; B N( E) UMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# H0 p1 Q$ G3 t% \; t, g9 W6 K. J** Configure the McASP pins
1 `% h) g! J: n: l) j** Input - Frame Sync, Clock and Serializer Rx2 O2 ]) g" n0 g E _1 ^
** Output - Serializer Tx is connected to the input of the codec
1 U V+ b, B+ P$ j*/
6 S: H7 t! D+ [& F, j! f, d; T t7 v0 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% ` S6 \, K1 s' S# m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- B! L2 ?" i* R! a$ j5 [* H# mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 G% z0 P7 c9 I! W/ I5 B" s| MCASP_PIN_ACLKX
/ S2 F9 E) u* O) n1 m: V: t| MCASP_PIN_AHCLKX- s5 s' F8 Y# k6 E5 Q3 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 q- Q8 J4 T, N }: ~+ s' N9 z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % H7 y' {9 @ t6 U F
| MCASP_TX_CLKFAIL
! ^" N4 y* i; U* V) d. V8 D! a| MCASP_TX_SYNCERROR
3 k! L: d4 G2 c; N+ R3 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " x1 O( V% L$ m
| MCASP_RX_CLKFAIL' d& K$ g6 O' r. H0 H: p% K
| MCASP_RX_SYNCERROR 3 n0 k5 ^" p5 q' U$ i9 f4 b5 Y
| MCASP_RX_OVERRUN);( s8 B; k4 g0 F( B
} static void I2SDataTxRxActivate(void)
- Q. G+ W5 a# A0 k- v/ l$ Q" o/ O" t{7 ~) I0 ~3 ]! k) V- r$ Q7 v# Q
/* Start the clocks */+ B d' H2 ?0 R) V7 u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: L: n! ?& r9 Y1 s% AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* D8 i( ]. H9 N4 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, t% r/ f1 ?2 A) [* o& f O; u+ K
EDMA3_TRIG_MODE_EVENT);
5 @7 U6 L) ~0 W2 b3 `! ^$ J% {+ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + C/ g" v, c( J& t# b6 M" r" {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& r8 E' N& j, f7 ?; A2 C$ T! aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. q R# j* m& f( ^ x( ?' W8 Q) qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& Y3 B, b; F8 S2 ~3 i6 _( g' ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* d5 h* R p7 w% P+ F6 D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);! |+ C2 B, G" I: n7 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ {) I# `* ^1 J8 c( @2 i$ n, O
}
$ ]( L l/ L! K' Y1 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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