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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 R- O4 S. [! S. T+ }input mcasp_ahclkx,/ g0 ]3 D# d- w2 W
input mcasp_aclkx,
& @' a1 ]$ y! n+ |4 `! h! Jinput axr0,) r9 _4 C8 X: \
7 {2 [ i/ H8 t* n4 Xoutput mcasp_afsr,
* |2 ^, o& y/ Youtput mcasp_ahclkr,3 h0 |, r6 K! e
output mcasp_aclkr,
1 z; b! U" n3 e& {. uoutput axr1,0 O x8 j; P) x
assign mcasp_afsr = mcasp_afsx;
+ o8 ~, k' l1 _) R1 B% A$ eassign mcasp_aclkr = mcasp_aclkx;; [0 u! _8 p; o1 P/ C4 F4 e1 |" O& s
assign mcasp_ahclkr = mcasp_ahclkx;
0 \0 A1 M2 x# A. n. g8 nassign axr1 = axr0; ) J, k! j! g' c' Q2 Y9 i
" x% _% b8 d6 v, _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. F% n* W8 r' H. j- a# xstatic void McASPI2SConfigure(void)
2 z6 t9 j9 H! P: y! o7 p2 I! q6 W{$ Q5 P( t" l0 h( E Y' T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& L. M" ^# { D+ o7 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% [6 S/ U2 z4 n5 i {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 |1 _# T) u) n) D AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. N0 g3 j; o9 Q u6 o! G" r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Z1 c- E T# p6 v; bMCASP_RX_MODE_DMA);
; | @" y7 l1 d# k# TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ E( c* C2 R/ a' F. l) dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ X2 w3 d( k- K3 q. J; f- A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 C _7 V/ u1 K+ y4 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 { S7 l" G, v: u# ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 F! }/ a. U. Q) W$ b# t/ i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* X# O% Z2 e2 g( r7 z1 u7 }7 D! `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 l5 |5 k7 F* p' c8 P- [- F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - w& ~3 P# B+ L4 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 ~1 K9 ]7 J$ w" a* f
0x00, 0xFF); /* configure the clock for transmitter */! X) \" C4 P% W% \. V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' {( }. z# T; W' eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, m# g3 r8 R% rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. F% L' U+ K8 T K
0x00, 0xFF);3 i( g/ [3 @$ J: j) D
9 J1 L4 ]! L9 a: D( A5 h" `& b
/* Enable synchronization of RX and TX sections */ , I! q8 z1 ~3 [6 p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 Z- @! ^. S7 h- @2 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& M {% k( x4 G0 |* J, K5 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 K7 c" c7 X2 V) h% F& G3 e
** Set the serializers, Currently only one serializer is set as& G$ q: Q- Z0 n2 k
** transmitter and one serializer as receiver.
# ~' h" x" h+ H1 w: w2 ?" f*/
6 H* c8 ^) G8 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. M, T& N. S# X) ~+ CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# A% E: w) g* F** Configure the McASP pins 4 V) b- O7 H4 \! F
** Input - Frame Sync, Clock and Serializer Rx
0 Y, a. W7 ~ v+ }8 P** Output - Serializer Tx is connected to the input of the codec
$ b" V3 p8 S/ L*/
- Z0 X. j9 W+ [3 q8 u9 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& q( L8 e/ C& D9 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) G% k( R& a1 ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 C" \( r/ K. C2 r6 I$ m
| MCASP_PIN_ACLKX! a& m( N: e& w- m: h# D
| MCASP_PIN_AHCLKX* P5 j T# `0 }; p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 M0 K3 H I1 a; }! }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # o! O5 n3 Q$ ^$ L9 ?
| MCASP_TX_CLKFAIL 2 @: c; \$ |1 X( k, p# T4 M% F
| MCASP_TX_SYNCERROR
0 m+ v* M- k; C8 q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' ]$ Z& i# |5 ~' u( t# Z, ^! C| MCASP_RX_CLKFAIL
9 [- U& K, X8 K0 h) T3 r$ \3 I5 y| MCASP_RX_SYNCERROR / l, B- w) e8 }% B' L2 `
| MCASP_RX_OVERRUN);
6 ]) e6 Y* R+ G' O5 R0 G' l6 v, C1 I} static void I2SDataTxRxActivate(void)+ ~2 }, V9 N! i+ s# \' v S
{
5 r) i3 D. q2 ^ V$ S% h/* Start the clocks */( i- C3 U. C+ h x' F" U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; x' ~! i# |1 @7 B+ S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( q" ?( J, N+ {" X+ Y7 z$ Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- e* ~& I+ _, A
EDMA3_TRIG_MODE_EVENT);
9 y% I7 r3 N, aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. V, K0 ~( p( Z$ H; R4 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% {& K- c: L1 h- \& ^
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 S& U. e" u& b! f) Y. W4 J- Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// V- Y/ t# G( G. c. @! A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 d0 k- a7 R/ M: B7 ~
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# i+ k$ O0 M7 I7 W5 |& V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# f( |' m: t; _( [, Y2 s} 0 y- z2 l; t! C: n: Q* a2 R% P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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