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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! z" f; A! [$ }3 S7 L
input mcasp_ahclkx,8 ^7 c% c9 o3 u% J0 C0 W; _* }
input mcasp_aclkx,
/ Z+ O- ?2 K/ K; Z# @8 sinput axr0,
6 _& y9 x6 C: ?+ _( v, T# o2 M' t) G3 r$ g
output mcasp_afsr,
. B% {3 \ S0 U3 f) koutput mcasp_ahclkr,: x6 a9 p+ u4 K* l4 v
output mcasp_aclkr,9 y' k, q' z7 Z+ G
output axr1,( i! J7 n# G" e. W) L, s0 G% N
assign mcasp_afsr = mcasp_afsx;
- L2 j2 q* k$ a% F' Eassign mcasp_aclkr = mcasp_aclkx;
4 Q$ ^6 G* P8 q r5 i8 i0 ]assign mcasp_ahclkr = mcasp_ahclkx;6 w) M9 x1 c1 X+ `0 V) \+ z) o# K2 g
assign axr1 = axr0;
' ]. m1 F# o. }( f8 P* o- B/ h3 F$ u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 J1 r$ T( C. H/ H: e U I4 z ]static void McASPI2SConfigure(void)% P& R z( o" \5 H+ K
{" J* G( m/ }* y6 c- A5 K
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( `4 t4 O* ]. y! u# ?$ {9 X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& J7 L/ q& p1 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: Z i, W! X" v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 w4 \; x+ j" c5 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& c2 O2 X; u4 t
MCASP_RX_MODE_DMA);( R# [7 |% i1 ~$ o2 Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- J' q% Z3 x; s! Q: ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( L2 l: K* g" {5 o+ @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 Y1 Y. n' C: X! t m! x, }% `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 I4 u) K' P0 W5 a3 z& [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 P( X; {* G' N% h5 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# m$ `# N7 E* [+ {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
Y9 y! Y2 B8 P* A+ O4 jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) {7 n" T0 {+ [- c! h* }2 g" i7 F9 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) i/ T4 \7 ], h! C6 u6 ~0x00, 0xFF); /* configure the clock for transmitter */
g( x3 D; @) y7 X3 J' S( PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 p; K' i c" J6 M% B, b1 _1 }) h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : x6 y& m' \7 R0 \5 g7 e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* o& x6 ]7 m6 G+ I$ @* g0x00, 0xFF);
/ t5 |! i& ]' V0 O& q$ k# ]( e
. i" w: V% C' M& T) j% d/* Enable synchronization of RX and TX sections */ , W# @3 p/ f' N% o, M' K% F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 Z0 C, S# t' ~) h6 H4 r, d1 FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: b1 M8 c x. s$ s- Q lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 [' C- t% L: F3 _8 I( x, E
** Set the serializers, Currently only one serializer is set as, k+ [( e; R L' h
** transmitter and one serializer as receiver.& i# N0 P2 [" r7 Q
*/
3 q; L( X# }$ T$ X! E3 M* j8 v( @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( a' F, g9 p( A/ u U/ QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 v: f# z! J( E- K! s% D$ r** Configure the McASP pins
" y+ p% b5 p2 G) P' B. A** Input - Frame Sync, Clock and Serializer Rx: F4 ?5 b! {7 U0 e. e" U' g
** Output - Serializer Tx is connected to the input of the codec
1 @; Z6 }9 q, v( S; z/ M2 n*/6 p1 n( B4 h3 o0 w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 U/ Y' k1 f1 Z2 C0 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 S0 _9 M! Z% H, q5 j; I: {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. d* s$ i& ]& w" ~; i4 S* K
| MCASP_PIN_ACLKX- Q2 w0 j3 q- D* q* Q
| MCASP_PIN_AHCLKX
0 h! y/ F2 ]! v) R) k; {| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! r* `! x; A% |" a( w! gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * y+ E% }. e' |( w
| MCASP_TX_CLKFAIL & \0 ~ F( e1 _3 V8 B8 [7 t, r
| MCASP_TX_SYNCERROR
# H, I* k: p7 j: _- }+ f& F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * l+ x" I3 S* B+ \& n* l7 \
| MCASP_RX_CLKFAIL% M7 U4 U: ~2 K/ Y- u
| MCASP_RX_SYNCERROR
' U0 N9 B! F0 F+ S| MCASP_RX_OVERRUN);
# ~+ x% {* E( T} static void I2SDataTxRxActivate(void)$ d# i5 T# h/ f: h5 H3 V; m9 P# l
{
1 t7 o8 r2 d7 K/* Start the clocks */
+ {4 n) c1 q% w ^* x8 j, ?4 `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 L4 u- }" {/ f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 y) B$ S# F" D& G1 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' W7 c8 x6 }$ R
EDMA3_TRIG_MODE_EVENT);
8 y- k' z- |4 ?9 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ b) I$ [# O% W& O- O% m% F3 w* h9 V# l8 }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) ~0 `& i& N$ v8 @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, I$ z. h' K4 S* ^$ ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, V: s) d% s, z |0 v6 D1 y* zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& L7 f2 g0 W5 q3 i" h8 e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 ~0 Z- O- `& i1 j7 S
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 |8 ` _: z }. f1 @! m
} Y+ @; a/ g( Y0 j8 \! }7 K' `- u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 @1 u5 C; u1 R: [
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