|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 q' f* G% f& T4 N: D* G! zinput mcasp_ahclkx,( u2 R6 H8 I1 i; Y }
input mcasp_aclkx,# o$ H; k! v+ z l, M D' C
input axr0,3 |" q. W5 |! n9 ^
* J# N. i9 m2 h" g9 youtput mcasp_afsr,% R6 L! r6 C' l5 ?3 }2 {: O; |2 o0 I
output mcasp_ahclkr,. d( ^8 _1 d2 A% ^/ i! G
output mcasp_aclkr,5 O. p; y2 Y+ f/ K
output axr1,
& ?4 w# {, r, Y& w assign mcasp_afsr = mcasp_afsx;# u+ \# C) A# F0 R& ~
assign mcasp_aclkr = mcasp_aclkx;
( e& S+ W2 k' ?- S% g# i* S5 Aassign mcasp_ahclkr = mcasp_ahclkx;; ^- M4 W: i: T7 V/ p$ S! c
assign axr1 = axr0;
# E5 q0 \/ j g6 q. h, \; Z! h* U! m" d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! v# B" j8 h5 Z3 Estatic void McASPI2SConfigure(void)
5 i) Y1 b- Z% Y& o{- ]7 ?7 Z' q _+ Y) s% v3 f4 c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; F1 w ^6 o& F4 w8 a+ LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& H, |& k' r# @% ?; W1 l; ]8 G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! }' ~7 Q5 i: ?6 \8 pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# C: t9 u7 X$ J# D) t; ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, |: l' D" B8 R. f1 iMCASP_RX_MODE_DMA);& G. W7 j2 E) d4 h' G. ]- y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! u: ?& {, n2 F! B x4 k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* [; e+ R) {& g8 rMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. s- v( T2 A. E+ j( M, yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& p0 b( G( O1 U4 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 ?: A0 A5 B6 _ ?6 c2 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, ]0 X: T4 _9 i; s8 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" t7 [9 a9 c; T; ~( E/ ?3 @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 | ^% o# @. v* E5 {4 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 h- B; L9 X& o
0x00, 0xFF); /* configure the clock for transmitter */
5 f" G! g$ F# V8 n6 xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 v& E% ]; r1 C7 h6 x& O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 m* B( i9 R4 j0 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. S) _8 v; L! A4 p. D+ W1 J0x00, 0xFF);' f' H( o. n9 {4 X
+ v* E) A3 ?1 L+ O/* Enable synchronization of RX and TX sections */ ; _# s: \/ r9 T" [% s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 c6 \0 J2 i: d/ P: @* XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Q7 j: A4 b& X8 C8 G8 O$ ?- v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ F# g0 G& |5 n- L5 ~3 K+ s2 G
** Set the serializers, Currently only one serializer is set as
: Q _6 \; K- e3 `7 b, ~** transmitter and one serializer as receiver.
: x( t3 `' @- {( Y) @*/
2 Q8 z& }3 N- ~. DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& D+ R3 S5 P6 Q$ ]& D% LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 f- _ P. M9 V* {5 M
** Configure the McASP pins
6 p" L; T. r/ a- F** Input - Frame Sync, Clock and Serializer Rx/ w7 V' O1 D# C$ L7 h! k
** Output - Serializer Tx is connected to the input of the codec 7 F& J! U) ]- u) r
*/
6 V0 h* w7 i" G" j; cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! ~% F0 Y3 F6 J& V2 p& V: w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 b `$ J+ L$ a e y) h+ q; H4 eMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, v5 `3 ~+ D. Z H' M0 B
| MCASP_PIN_ACLKX5 E" M9 o1 q; _2 u1 m" v
| MCASP_PIN_AHCLKX. W4 `! |2 M" C! p. E; z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# X p' I0 v& n7 @: {1 ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% M5 c% p) m1 T$ \| MCASP_TX_CLKFAIL 0 e4 B! Q B$ q0 T: b, S
| MCASP_TX_SYNCERROR
" g4 q2 e% m# u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 R9 ?3 f! l+ s; o! ^ A) S! x
| MCASP_RX_CLKFAIL
T6 i) ~+ @. P7 d+ _! J| MCASP_RX_SYNCERROR 0 t# _( B/ e) k' c& m
| MCASP_RX_OVERRUN);4 a4 N$ ^% Q: t& M p
} static void I2SDataTxRxActivate(void)6 v( ?" K# w! Y: m5 v! E: W
{; w9 }9 [, K( J" {6 W
/* Start the clocks */
4 W9 |9 r7 r% [. KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 u6 C0 N7 u2 P& P" r6 X: nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! g7 {$ d, Z/ T! b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ }) \- X3 K# w! d! s# vEDMA3_TRIG_MODE_EVENT);
2 O. R+ y7 u) l* q3 X- I8 f1 zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & r9 U1 S7 l" K! Q# D8 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% f$ v9 K. U7 n- A8 tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! y b& H+ `5 |7 [- KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 k$ M) F% V$ Y; p: F3 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 @ p& u( Q7 k; M( l$ f$ oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 ]6 K9 k) E. l ?1 @! o5 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: y$ X" z2 f. R}
$ U( O/ t5 v# \+ V1 v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
% g% g; C$ q4 |' B4 k |