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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 U( t5 |( f% h' @
input mcasp_ahclkx,- Z3 J& [1 J M
input mcasp_aclkx,
3 L$ G! u/ \$ S6 p: C9 v4 G; M Oinput axr0,2 M. L, _/ ~( h" Q9 p, o
. E/ `6 I* a! v: L3 f7 E2 X, v
output mcasp_afsr,; @4 c( N% }9 Z, c$ D5 d
output mcasp_ahclkr,! ]. _) `9 r4 }3 I5 N+ a4 q' N) G
output mcasp_aclkr,
: ^& s0 L; B( G2 M% b d- Joutput axr1,3 _8 m$ D8 X- o" C0 P/ i. w( ^
assign mcasp_afsr = mcasp_afsx;* m) h+ x5 [4 b4 @
assign mcasp_aclkr = mcasp_aclkx;
9 r% ^# t( e$ W6 e- t( }7 w- Fassign mcasp_ahclkr = mcasp_ahclkx;: s( k/ r/ H1 }' ~' X0 k) v- v
assign axr1 = axr0; ) R D+ r& o3 z7 I, Z
( l; H: {& h& v* k# |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & {! a G' R2 ^$ S, w8 w2 T3 ]
static void McASPI2SConfigure(void)
" M- h2 r7 K, S4 o; U: B% Q& w{5 c n& ^1 G/ U, q8 Y5 C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 u2 T6 k- I* Z, E i* U" [9 j0 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 v1 `' \; v3 J, i7 F& _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, N0 }7 z& B5 p0 y3 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ Y( q5 ^: X. R0 [3 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ Y& i6 t S+ i) ~! J
MCASP_RX_MODE_DMA);
, a# k d) g2 o0 D1 a- X8 y( w2 xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# U( u$ D: @1 W4 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
R5 ?. V7 M# c1 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / L! K9 m( Q+ x7 h# x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% c5 f# W8 r) ?" x
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 Z i) u+ j4 @) D. J( m7 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 N6 J2 K# F, ~. t s! V- u8 bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 [4 L) |. D2 @* W% iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 L. E: i7 _8 E7 \7 E6 d+ z$ q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 z8 t. Z/ `+ z- A" G
0x00, 0xFF); /* configure the clock for transmitter */3 p2 r, O% H, U& \& x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ n/ X6 z2 t& W4 C& r7 Y+ ~3 P, D" ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' K# j0 h; z- L" u) p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) [9 M( u0 t5 Y: }0x00, 0xFF);0 |7 O0 h- _3 ]2 d' h$ Z2 V$ `( U6 P
& q4 S+ C( Y g7 U7 Q) [/* Enable synchronization of RX and TX sections */ ! z, d. I1 ^3 O3 i! E0 Q+ e+ w4 f# ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; z/ u/ L [( _, D( l9 NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: a% C( }5 k) `- xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 R* w* V4 o% ~. Z0 |/ ^5 ^** Set the serializers, Currently only one serializer is set as
8 `2 I' Z3 j5 u7 ^** transmitter and one serializer as receiver.6 w5 Q) {( k! A+ x% s, E5 ^- d
*/5 d1 ~; K" e3 P q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 i- e" y- @7 e D# ]5 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 ?1 @: x3 ^3 G! _. B; u0 [( i** Configure the McASP pins
* _/ t+ p, u! o/ h** Input - Frame Sync, Clock and Serializer Rx3 ~$ K8 F; ~6 V5 \
** Output - Serializer Tx is connected to the input of the codec
1 W) P5 U8 ~/ Q4 G _( w*/
" Y) Y; w$ U. x* X. Y- RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 A( g2 Y2 L7 k5 k, Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# N( B. {" K* }: z$ p! |+ FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# C" W! `- y2 X& _& n1 f. ]0 r| MCASP_PIN_ACLKX5 I. X& H9 G. X1 x- I
| MCASP_PIN_AHCLKX
8 z2 ?2 U. H; J+ r: d( v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 I9 P$ Y) d0 e9 y. u/ w+ {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 C) T; X" C+ T| MCASP_TX_CLKFAIL
2 X# D6 L+ N S| MCASP_TX_SYNCERROR
9 c( U I* d* V$ c9 C! W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR N* D- F) u0 [/ J ?
| MCASP_RX_CLKFAIL
) o, o8 [! v, s; s( H6 o. X| MCASP_RX_SYNCERROR & L; K) ? ?/ j5 `7 X
| MCASP_RX_OVERRUN);
( e+ Z3 ~+ J0 X3 f r: u2 q) }} static void I2SDataTxRxActivate(void)5 M; t/ t; h5 H/ w* o/ L& P3 L! q
{
9 m" C7 N3 g" w& W7 b/* Start the clocks */
9 G, O8 h7 e% S" p0 JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& }; {/ r9 t7 h L+ `* c. B3 G+ w( KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- c7 ~ k" p' F n wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 l) |# D7 F* B
EDMA3_TRIG_MODE_EVENT);
4 b8 P1 h" G' i1 c' ~# R, gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& s/ C$ ~3 @! T6 i. c' tEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ i: P( W1 }* [1 R' f& D4 k9 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& M; A L/ M- L& K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- p( u' \: N J8 D* H* cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 F+ Z7 V$ U9 s9 W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); J0 S% L2 Y! H) Y. \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ h$ b+ Q: R4 ~ F; {! b+ \
} ( r' K; N# n& |: c! ^, X& ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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