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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 C# y% Y0 S& d- Q$ t5 B# R: ^4 d8 Iinput mcasp_ahclkx,
' h- p) N! m' ^* k7 s3 O& Minput mcasp_aclkx,. H3 h3 ]' F( L' S# k+ i
input axr0,2 X" o4 Z5 ~$ O8 i5 T
- V( p+ Y/ u% H, T4 P0 ^output mcasp_afsr,
, J2 X; r9 X9 l0 L6 voutput mcasp_ahclkr,1 n. b3 z' l) L- M1 I5 f
output mcasp_aclkr,- L, ^4 a: V- g% r7 j$ _' N
output axr1,! _/ b2 S+ T6 {) Q! r
assign mcasp_afsr = mcasp_afsx;
" J& q; e' v6 q& yassign mcasp_aclkr = mcasp_aclkx;0 Y2 R4 Q$ z& T
assign mcasp_ahclkr = mcasp_ahclkx;
, y6 K9 \/ ~& Q9 \7 Lassign axr1 = axr0; 8 {! k$ E% g- M4 U
$ R4 d) Q2 z9 u. O1 G9 @/ ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . l& A; i$ r) s
static void McASPI2SConfigure(void)) i( P2 x7 l) D% g' B, H! F7 s2 u \5 K
{
9 p/ N5 o4 y; H+ i- tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 r. y, B% y+ g m* rMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' ]1 {7 R7 x `- c' c% a, ^+ dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. _% Y& u. @1 J$ }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; o! y- \) t( |1 a# N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, \# Z: ^2 B& d
MCASP_RX_MODE_DMA);
7 L3 N( X; X5 q' V, jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 e! l" \7 l/ o, `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ W9 S% m8 I( `; p/ k" P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' j5 e- l9 L$ b6 Y2 u3 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! l# X% f7 ]5 L! O& D. t8 FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% ?! ] z# b3 e# y: YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 c3 D( O7 d: B! ?4 H7 c. {: _0 u2 ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( K% I9 ^8 O3 ~& D c9 y. ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 C5 _- l+ C9 h+ D( C/ _. GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ T) x& W( n; R4 ]; y& C8 I
0x00, 0xFF); /* configure the clock for transmitter */+ z+ n6 {7 ?6 u' s* j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 v, i7 [, o, W/ o |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 _4 s( G4 W! p/ ^2 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& N) ?& o* R* l0x00, 0xFF);, S$ l$ Q4 q a& ^6 A2 C
/ y& U4 z& i' b c; O8 d/* Enable synchronization of RX and TX sections */ ) z2 |7 G4 L1 G8 r) S) ~* N$ z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 Q8 p7 h7 M; w- d$ p1 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 J# g+ P- n- t0 Y+ y" W9 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ [8 W& B+ X; G/ ~
** Set the serializers, Currently only one serializer is set as
& y3 o9 |* k3 q6 J9 K** transmitter and one serializer as receiver.
) I/ s: }1 m6 p*/- _3 ]0 _0 M% i& Q! t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' j- Z' ], ]2 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; S1 d/ x5 v* E4 S/ y' s
** Configure the McASP pins
$ L6 G1 D+ R& W# r** Input - Frame Sync, Clock and Serializer Rx
/ O- x7 B" Z( @% P2 t- c8 k% j8 g. s** Output - Serializer Tx is connected to the input of the codec
* e- }0 d( e( {) ]% A/ ~8 D*/1 i" C$ G2 D1 B- f% n' y0 s" o# ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 |* m+ g7 G7 X8 Q$ w. ]( r6 _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 a9 |# s7 r C6 J X6 R& U) ?( L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# B, s7 y: u* e3 y7 z6 F2 x| MCASP_PIN_ACLKX
; @% l1 S* e. h| MCASP_PIN_AHCLKX
9 O* E8 i8 O( ?0 L7 ]( ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 d7 J" [3 q5 g2 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ n+ @3 d J3 Q; b) j% j i4 ^
| MCASP_TX_CLKFAIL
. W+ p) B2 b4 l S4 j| MCASP_TX_SYNCERROR+ }9 O7 ?1 m2 i& S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * }( u: B- j" u8 E: j" F' V
| MCASP_RX_CLKFAIL+ ]9 e) w& ?- s9 T
| MCASP_RX_SYNCERROR
* s- _0 j) X; u" B| MCASP_RX_OVERRUN);& |8 Z' B' Y( b; K( _4 I* Z
} static void I2SDataTxRxActivate(void)
3 C& m3 z& m$ d- b6 e{7 s7 g8 G- x8 R$ s
/* Start the clocks */( j, F5 V d; L8 {2 b1 B( X9 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 H2 L9 }9 m& O4 A) oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 u: Y2 O: ^# q8 `& h8 O+ gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% T! `; \% I! ~: r% P6 j. }
EDMA3_TRIG_MODE_EVENT);
! M; x6 u4 H( W0 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % q% }! ^- e( N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, B0 U% G# [0 _( [; t9 XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ D$ J ]% o$ m0 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; [& S1 K) F- [ l* ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 w. r a) @" ]1 y. ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 T- a; A1 |& t: t# Y9 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ D1 M! ^ Q5 @7 G}
P$ F7 D8 y. t3 J! t% V* R. ^/ N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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