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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 H5 u1 `0 q. I' S7 l0 Jinput mcasp_ahclkx,
' F0 b. _0 H( D- o$ Z3 W$ o$ \& iinput mcasp_aclkx,
. x) u- p$ j0 u+ linput axr0,' `) ]" N$ ~/ d1 v8 e8 g. P
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output mcasp_afsr,+ u! r) k& ~6 n1 ]5 K7 d; X
output mcasp_ahclkr,/ H1 c1 e2 B# g4 {
output mcasp_aclkr,! [8 R: T ?+ `+ v* q2 {
output axr1,
( R# E8 y- l6 |4 C) H: y+ p assign mcasp_afsr = mcasp_afsx;
) v. w. q, A2 V. d2 dassign mcasp_aclkr = mcasp_aclkx;
, {) N/ j7 w. o3 Q- s, A# s% sassign mcasp_ahclkr = mcasp_ahclkx;+ ^- w" l6 ]. A8 C( H
assign axr1 = axr0;
' z$ U5 I! K# |1 N9 D% y
- f3 F3 w$ D- [- X, K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - @8 w6 K+ v( r- Y
static void McASPI2SConfigure(void)
@% `$ i) v z( f: _4 A( R% v{
: k7 f) l& p0 ~9 }9 A* TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( @8 I/ \' J- h* u6 @+ TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; R) P: w3 m+ n1 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ u7 E0 Y3 _- D, _- C& ^! j3 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. n: S% }3 G7 ]; ~6 b' I# B4 Y/ CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 a5 Z z6 s, F5 `0 T1 G$ |) P5 {2 sMCASP_RX_MODE_DMA);- T t7 J% X3 g, p3 U3 X; @' m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 X5 g) P! J, T [) o9 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; @/ s% ~0 d, ~9 I# _- ?
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / r) i \# D( w8 X' ` H. U9 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! }/ Z$ `1 y6 o; [/ T9 m* tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 H8 v. c. ^. g: R7 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 Q3 D# t; {9 v+ x- LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; P" Z1 B7 T, p1 d! oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 `- S% [2 S* z) Z8 oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ g. o8 B. _. o* u6 f( h# `
0x00, 0xFF); /* configure the clock for transmitter */
9 L2 |3 b4 J7 l" R: D. m* }9 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ ^5 Q* q+ }9 z" V6 |* \% y$ j8 ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
O3 T4 q* L( U! f" f5 DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) L: c& ^2 E+ [- J: o) q0 {0x00, 0xFF);
7 }* R6 V+ Y( U7 k; x# c3 ^1 N1 Y' T
/* Enable synchronization of RX and TX sections */ ! Q2 j' j- R0 W# C8 {" o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, j4 U' N! Y7 O+ W0 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. f; n* ?7 J+ W; d6 G4 W! CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 C9 `4 Z; M- q1 |: i** Set the serializers, Currently only one serializer is set as
+ V" y7 F# \( O$ u4 M** transmitter and one serializer as receiver.: ^: M& s! ?; C) j
*/
8 p; O* t( j/ u* K5 B- I9 zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! ]% q; h6 j& V/ Y% R7 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 o" k7 [: D$ Y4 X: k* q4 k/ x
** Configure the McASP pins
* Z3 o p% A9 V/ T** Input - Frame Sync, Clock and Serializer Rx. Y1 K2 S, d- B" A; P5 {
** Output - Serializer Tx is connected to the input of the codec
) n3 H; g+ B; f+ [4 S1 f# w*/( Y) A& E& Z2 t/ V5 p: N; j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); P- d7 Q' L% N' d5 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! p1 A2 [/ A. o! z A- T- kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 C4 W7 P- J: Z1 i/ Y+ D: n| MCASP_PIN_ACLKX
4 I) v. x0 W5 v! m| MCASP_PIN_AHCLKX
$ |5 V/ n( D1 w( e5 Q+ T* a- B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) L- n$ w' G; b6 \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, X# _. Q2 k( ]; p, n! N1 V, M/ m| MCASP_TX_CLKFAIL
5 Z( n/ W( W/ ~| MCASP_TX_SYNCERROR
. G6 h+ R8 D2 X; D9 e4 @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 M% I0 _2 o2 g7 b! f
| MCASP_RX_CLKFAIL
" u9 V _( A# R$ V- o* t| MCASP_RX_SYNCERROR
% u s9 Z, }: K7 d# q| MCASP_RX_OVERRUN);
5 t8 W% M" g* T F. H% `( v' P} static void I2SDataTxRxActivate(void)
8 P5 k# T% n; L( Z) g: F6 r{: s! g% ]% i& W2 i) A% q( S( s9 n5 a
/* Start the clocks */
|' |. ~& o. \* z- R1 Z- zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 h* l, b/ X2 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 X$ ~% \3 F7 m1 `* o) V( U; HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 U& h0 k# D$ g1 ~
EDMA3_TRIG_MODE_EVENT);
$ Y' Z& \+ S% Y, ?+ G- m7 l4 {+ sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* t5 G# ?' A" _2 Z* N, ^5 h9 H: wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& d; V( p; s J/ G! EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; b6 I# `4 E7 ], C
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 P8 z) o3 ^" I: C$ [5 X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 V/ ]1 ?, M" {( `: e* H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% m+ U! i q. x& ~$ u( |2 d8 F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% e2 u& R: k% U: M9 S
} + Q3 N& y) r2 F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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