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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 I5 E0 Y, A7 p& a$ y6 o
input mcasp_ahclkx,) `5 a, v6 G( Z5 }7 ~
input mcasp_aclkx,
/ ~: W/ Z1 [, t6 F g% P! {& e( Minput axr0,9 q( [$ T8 Q: k3 M9 y+ U9 d
2 z( @, q- T5 woutput mcasp_afsr,) v6 m* `: w. t; t5 E' S6 B
output mcasp_ahclkr,
8 W% v0 w+ R- N. `: A* Youtput mcasp_aclkr,
0 t. r" S2 E+ soutput axr1,- r3 s( l- v, e4 n6 u3 \) l
assign mcasp_afsr = mcasp_afsx;. F$ b. z' A. E! j! R/ R0 }5 r
assign mcasp_aclkr = mcasp_aclkx;! \" D, j0 A6 S5 }( R* t
assign mcasp_ahclkr = mcasp_ahclkx;; w! }0 j4 B+ P( L, q+ u7 ?
assign axr1 = axr0;
: E2 m! A- x j! q* N! N" @1 N: R/ Z! g& V0 k5 q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 ]* L, O; T0 A+ {; L |static void McASPI2SConfigure(void): c- P7 H, l, ^ @
{( _ x8 f, S7 ~" Z0 D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' n% j! B0 I& d/ G0 GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% |) c9 _, Y" j( \3 [7 x6 b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ M. M, s) O0 X' O8 G- V, A& _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ N. z* W! f( {( ^, XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, X9 A' n% L T0 N
MCASP_RX_MODE_DMA);2 v: t% f7 \, k* k: }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. h* T( w4 O ^9 A# @. a+ @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 {8 A" r) [3 p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 z; ]& d8 _) e9 K3 e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 o6 R& p+ F1 vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- _# F* T0 t; T) t% V1 s& k5 CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, w0 D4 e5 W9 W. w( YMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) X) c% i4 f6 q$ Y9 E w2 J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 _% ~+ S/ Z% [7 {! i& t* ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& v7 U& k: C0 D4 Q) @7 L# d0x00, 0xFF); /* configure the clock for transmitter */
8 K8 @( v: h% ~ O( tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- C5 R- o: K6 o. U0 ]# V/ |; HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ k8 u( ~5 s6 g' T$ L4 O% cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 ^2 a/ k. y3 s$ h0x00, 0xFF);
1 X6 X5 ~4 s# o* ^& w& O
: A* K6 R; J# ]. t/* Enable synchronization of RX and TX sections */
' h1 a) H% H& o* x$ g) rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 X9 j; a* ]! {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! w d8 F! ^( k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" D2 F8 r, Q( {. P8 ]** Set the serializers, Currently only one serializer is set as' z+ f) R4 Q+ R
** transmitter and one serializer as receiver., c( ]! u. R! R& D3 O
*/
; `; C9 V, d! U) rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); a1 y$ f7 b4 v3 O9 N3 R' b' D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 q/ _! h+ v3 Q. k! H, r: K) W
** Configure the McASP pins 3 [1 J2 s; W( e7 t+ l" @( {$ L
** Input - Frame Sync, Clock and Serializer Rx$ J: ?1 v8 R: A* V- a* b
** Output - Serializer Tx is connected to the input of the codec ' G6 z# C& |: u% a+ c
*/1 {* l& X% k5 m2 o" g2 H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. e/ b1 @1 O( N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 Y, \( _- H- `, W7 [- i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% L# _4 g4 B* I% k
| MCASP_PIN_ACLKX
* @$ H( g1 @# B0 p| MCASP_PIN_AHCLKX$ P5 A( f. P6 f0 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 f9 _- x+ X7 n. {. r9 b6 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 b8 a0 _- O/ U N, Q) H7 S% c3 B
| MCASP_TX_CLKFAIL
$ X; J; F* e/ X+ f3 Z p| MCASP_TX_SYNCERROR2 A% c9 k! B. _* E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 j- d' j1 g e. A/ I [
| MCASP_RX_CLKFAIL8 \/ d( C% E* x! _ c
| MCASP_RX_SYNCERROR
! z g. @5 q1 s2 Y0 T| MCASP_RX_OVERRUN);
4 B5 k5 D* c4 i} static void I2SDataTxRxActivate(void)
2 k* q- Q4 j9 A& D{0 i, E1 y+ t% @5 ^" G+ \/ ~! I
/* Start the clocks */
" o+ \# U7 s" G: eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: m7 e! d6 K/ u7 ?6 J# s6 L) X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. z4 ~/ X2 H. X! k' F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, u2 R4 Q& Q Q5 @, a" ]! N" K0 l
EDMA3_TRIG_MODE_EVENT);( V) i4 k- k F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , J& L6 U4 j" P0 s) V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 N( z. y B- u& lMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 z3 c7 E5 `* f3 |" t7 C( SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ m5 v- q, z) q3 D# Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ ~: \0 [ b+ i
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" h: i% `. ?8 | h% R- M2 i/ K" Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: O7 k5 \6 D9 [4 Y} $ i$ y1 E0 L& }/ k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; ~8 S/ `% L4 J8 L _
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