|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& j7 k% c# l- `% U2 S. J0 dinput mcasp_ahclkx,
! O/ H( [8 s9 z1 ]# A! b+ }input mcasp_aclkx,; a4 [9 e& h% H' m1 _8 M5 R
input axr0,% D M& ~# a, I# r5 ~
7 G7 s- m+ L0 O
output mcasp_afsr,0 B. C) s3 x/ ?- C, ?" ^
output mcasp_ahclkr,/ k: N! U1 c n0 o4 p
output mcasp_aclkr,6 J* |; i/ _7 I( a; l) ?
output axr1,
- M4 S* a& U, E) `) w% P. c assign mcasp_afsr = mcasp_afsx;' E) _& P/ ]- Y' ?# ~# R
assign mcasp_aclkr = mcasp_aclkx;* H0 c! J2 F& @ d3 }5 B9 E. O
assign mcasp_ahclkr = mcasp_ahclkx;
4 F( r( g0 @1 l4 |1 @* R1 Yassign axr1 = axr0;
( v) X a+ @3 Y" K# Y& x% I; \, b& ^% T" O6 X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 W( ]" [& m- {: B8 G$ V5 O
static void McASPI2SConfigure(void)
1 n6 B" ?1 r: x{" L( j0 y* D3 h0 [. `$ W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* k1 F( T" v, J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- J; X1 Z m/ d; ?1 k: Y }8 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, U+ x: x, H/ h8 i5 CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& W: u& C: k- l+ U0 IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; t3 e+ ?: i7 O/ J1 i% \3 QMCASP_RX_MODE_DMA);* x8 y& }- }# D0 {. h2 d+ K0 d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ z% j" Q4 r" I& A8 X, EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' e6 A ?( n9 } d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , Q* w4 o$ R. _( `7 q9 s& f2 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 ^/ A5 t* R" H: ]# E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 \& b' P/ R0 fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 q# C' E& x9 a" FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* Q" ]/ A7 Q! c7 j& W* \2 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' E) I7 L. d9 s+ z6 W0 U! IMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," H7 D% A2 L" X6 |% W
0x00, 0xFF); /* configure the clock for transmitter */# I2 I/ n$ |$ `1 c, Q6 L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) L6 W: Q* h! Z+ t: O, yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) i; x `7 X& \1 d( Y! _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, F6 c1 A. q3 N; t! P- E1 k3 q v0x00, 0xFF);, q& Q( p: T, H
9 M* v- d7 y! T8 W5 X- z# n/* Enable synchronization of RX and TX sections */ ( w) R( J* ~+ {0 `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 R" o: `! F% J. r4 M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 X% P) |' c0 H3 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& F: e1 f. u: z. H9 i- J; G9 i** Set the serializers, Currently only one serializer is set as
* z I9 t! I1 S; g** transmitter and one serializer as receiver.( b y' a$ y7 _ @) K$ c+ R
*/
6 Y: F k0 ?' T* h/ C( f2 HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 v; q) O6 d7 ^0 t0 i/ v3 H
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ C" e( [9 W0 k7 R** Configure the McASP pins , }( S. V2 {, r. c: k/ s
** Input - Frame Sync, Clock and Serializer Rx
2 b: U8 o4 K& L5 I. j0 ]** Output - Serializer Tx is connected to the input of the codec
% G5 S. `1 Z, k' V$ m*/9 c' \* m8 I6 J3 J! C* D! J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 N8 Y7 m, e' M. s; v; p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) w. V( f# d& h+ J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 Q3 k1 P2 f" h+ W; u5 l
| MCASP_PIN_ACLKX
! {! j; w; P( E" ?+ @# q" s6 `| MCASP_PIN_AHCLKX4 j0 @: C& [" v9 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: n% A; w9 D2 C0 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " d6 S$ a6 v* A1 J1 _/ Q* L( [
| MCASP_TX_CLKFAIL
" c, a/ [! R( N5 P# o7 _, f- j| MCASP_TX_SYNCERROR
! o4 a* i# I- d$ [& I% @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- ]0 j+ b6 \: W1 c6 e| MCASP_RX_CLKFAIL
7 S9 z; H1 b$ c4 v7 K| MCASP_RX_SYNCERROR
( f& ?1 Z6 `& a& [+ }; d# c7 o| MCASP_RX_OVERRUN);
6 O" M8 j; z# D} static void I2SDataTxRxActivate(void)6 Q+ Z- ?5 _# H6 j/ S# R
{
& h% E/ b/ L) w1 x& K- v/* Start the clocks */; _+ o L( S$ `2 ~2 F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) b( `! ~: y' ~( bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- @2 I' S0 X6 D3 k f6 F( L" t3 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 e: L7 ?, x5 X6 o8 o" [5 XEDMA3_TRIG_MODE_EVENT);
0 E$ h. W- `* P! w1 C) y# DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ O1 t. G! J; L$ a& e& j- \# [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 N* d. `/ z; q" aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: Q5 n/ C7 r# h1 f" n: v. h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ P) o: j; r4 \; P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' m6 [: b }2 [) b7 X6 L: X
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; _* e; M* ?$ a4 B* oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% ~4 K- q7 k! \& T}
% |8 e/ t. q! K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
, n+ y7 r% `) Q* I: a7 } |