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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& M* i9 }! U) u- n8 O
input mcasp_ahclkx,
# B4 q( b% F5 U9 `% kinput mcasp_aclkx,) |. x/ M2 }) g6 E N
input axr0,
, Y( J7 J1 m" \" o3 |5 j I* m, a- ~
output mcasp_afsr,
7 p" O6 s' h9 V# _3 toutput mcasp_ahclkr,5 a3 @; {3 b" b; r) e
output mcasp_aclkr,
, T, @1 w; P* C" N' eoutput axr1,
! H4 n4 G- e* k2 C( X1 s assign mcasp_afsr = mcasp_afsx;5 j& H/ P6 D$ K2 C% B6 V
assign mcasp_aclkr = mcasp_aclkx;
- ]% H9 w# t9 L R6 |assign mcasp_ahclkr = mcasp_ahclkx;* g3 W) ~) ] q+ Z$ n* `( O* g
assign axr1 = axr0;
* Z3 M' e! q: g' i! n! P/ K7 r
; o+ ~ S9 T; ^! ^+ X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " t5 R8 q, n1 O3 ~6 Q4 _
static void McASPI2SConfigure(void). a' D, D6 A$ d4 I
{
6 _8 `3 H: q. z2 @4 BMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 R; y1 c! I, Y% X+ vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 t6 Z \4 R) T$ [ y9 Y+ e/ bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& [ Q) J1 n3 {" {2 p" @$ A# _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& A/ j+ y' _9 w" j$ s v Z8 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( O! j" L f" V" N
MCASP_RX_MODE_DMA);
% l2 C3 h0 C% t- i G1 }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ c5 i8 Q* K( ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 \& h% H1 F' y( b, LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 @# R- L+ Q4 o+ W6 Y) uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ _4 n9 ?0 M2 b. ]! e8 YMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & |& A/ [: {5 y" F' N4 y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 X# P0 j' [. t, U9 L$ \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ a1 ?- K5 c$ K! G7 |# f: S: p' `; hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + C9 |! O2 s9 ^ g1 ^0 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 k# p6 `) q5 ?% d, Q( i' ^0 U
0x00, 0xFF); /* configure the clock for transmitter */2 M ?3 T+ l5 f( |/ [ [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ @: o1 H2 J v: @" s6 Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- m" m* ^2 }# ~ a! gMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 M5 h& F. I* d3 s8 \9 \0 y% {4 w
0x00, 0xFF);
/ ~1 M4 ]: J5 ~8 O$ c& _* F9 g7 [" \8 B; s5 A Y, M6 k
/* Enable synchronization of RX and TX sections */
% \1 X0 O0 N4 q! O YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 b _- h" {, e" f# T* y5 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: N' @- G- f# X2 L- g ~1 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 a2 I$ r' M9 m, Z6 h+ R** Set the serializers, Currently only one serializer is set as! z) b$ h v! k9 W
** transmitter and one serializer as receiver.
~% l& L# \$ i, r*/
1 N# q7 |5 e( C) kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 [1 T) w% g% T1 E$ ]. z- o- @* p: P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* h( g2 M3 y1 v7 |" j' R** Configure the McASP pins
$ X) D6 N3 g; Y. U% o" `: f% Y** Input - Frame Sync, Clock and Serializer Rx8 G1 O/ j$ Y! {: r) \% ~& j7 H* C
** Output - Serializer Tx is connected to the input of the codec " K. [% Z( f. Q7 M, b6 k6 t' [8 ~
*/
# n/ `, |4 o2 h: p1 e) wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 n% B1 c# _9 N1 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ p+ J9 H1 `7 ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- R t$ U; T# Z! C! f" f6 V7 _
| MCASP_PIN_ACLKX
+ Z" a; ^+ F& ~) Q9 q) b7 i| MCASP_PIN_AHCLKX9 i2 J* u5 p6 K3 |" z' U, b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, I- M$ ]: r3 G+ w) fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! N! ^# P, G6 k3 D8 j6 @' x& I| MCASP_TX_CLKFAIL
9 W6 n3 D( \# j3 r# ~| MCASP_TX_SYNCERROR
/ [" m- ]% }0 V% U1 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, t7 h2 [5 M: n9 l| MCASP_RX_CLKFAIL
2 Y/ o6 i6 R/ Z& Y1 m& a" s| MCASP_RX_SYNCERROR + f3 Y# i! M, y4 e
| MCASP_RX_OVERRUN);9 Q% s7 s$ W4 c: Y
} static void I2SDataTxRxActivate(void)
9 N4 D0 b; R3 j w; R: o( I{$ |- ^/ r1 C' X. I; n- q
/* Start the clocks */
/ e2 m7 s2 W( k0 r: OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% @4 D4 ]0 ^3 R0 J+ N* F: k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 {) q! b1 \6 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ N0 y$ k& z3 p, K
EDMA3_TRIG_MODE_EVENT);; `$ z }4 h! A7 }- o P# T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . T& B& }* E, {8 ?( n, Q* r0 e2 \" m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- x4 j( v7 Z( [; ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 `) {3 S7 j3 j- z6 S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: r, `# Y( Q% V: l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- @/ V$ _' r: \* _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" A( G& F" }3 b) q- rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' Y7 D* y% G x( F4 r) ~. E
}
# K: D$ v! N* e& ^+ Y7 o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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