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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 D U0 r8 o) l6 r
input mcasp_ahclkx,
3 y: q3 H5 i) B) ninput mcasp_aclkx,
5 Q6 A4 R4 H J& O- L, H7 Jinput axr0,' q+ y. v: n! V0 Y8 L
1 ? A; a( |& S- B1 e/ p8 routput mcasp_afsr,, [1 k' d0 O% X% r8 o$ u
output mcasp_ahclkr,+ y3 v. Q, H, l& B0 v% D) l0 s
output mcasp_aclkr,
9 G( g, M( L- J3 p5 ~output axr1,: c1 u4 h+ r9 ?& X
assign mcasp_afsr = mcasp_afsx;+ d, t: S+ X) Q+ B7 F
assign mcasp_aclkr = mcasp_aclkx;% O. z5 k0 m [
assign mcasp_ahclkr = mcasp_ahclkx;8 M3 b4 y: ^( t; K" U0 H1 Y' r
assign axr1 = axr0;
. N6 z6 @5 G9 ?. Q+ c
$ V7 y* g' O5 m* E" a: L/ V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 O: L1 x! m* x/ s* ]2 g4 L( Q
static void McASPI2SConfigure(void)3 j1 f4 p9 G; g* [6 v! \2 x
{( B8 H+ X) C0 B- v6 A$ J2 d; t4 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 X8 Z; }3 b: S5 F v$ p3 N5 ?6 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 j# Z0 x O( w* s( w5 I& q- E2 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 |. `0 r; E' K1 R3 U; P3 {5 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) W4 S: G0 X# ]4 y9 g9 ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," C. T1 B; r/ w# B* q% f! @4 v/ ^
MCASP_RX_MODE_DMA);5 e w" g$ _" A3 g$ r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# y' o0 e# O2 D2 w6 l8 [7 l/ {1 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 @7 `7 V8 m) v* {" b" n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 j }6 s: O: J4 e' p7 p1 {7 RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% z7 v- a) N" W* sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 ^6 h- e! r5 o* ?/ l U/ O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, a; V9 ], J: T. `9 U9 s7 @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ L6 E; D. j1 ]" W3 o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ~ X+ X/ n) y2 B+ l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
o, R3 ?; J, D* R* x9 V# h3 U0x00, 0xFF); /* configure the clock for transmitter */
* W% W9 E7 u& ^' ]* ~0 F: j6 hMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& ^7 D7 p$ k! _& }- C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- |5 j& c# c4 l# T$ KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% t$ `. f" |' H% E, e* E$ @2 N* y
0x00, 0xFF);
) ]* K J' W# F! M0 L& A+ `7 M" x, I3 z) k, y
/* Enable synchronization of RX and TX sections */
, }7 T0 M& D) T9 fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' q4 x5 \4 n& {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 n* k) l$ m+ c! e' jMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 x( g5 X X8 o1 F) e a7 @, j
** Set the serializers, Currently only one serializer is set as- I/ O9 |+ o* n1 m2 F& a
** transmitter and one serializer as receiver.
, T: D g/ ^( P+ E) D*/
3 i& [2 r& q4 X+ s: K+ N0 y! EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 e* l3 Z) ~$ v$ ?5 ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: {0 }& ?5 x- F0 u8 B6 u2 f** Configure the McASP pins
# D5 D* ?6 \+ M W** Input - Frame Sync, Clock and Serializer Rx
+ r) p/ r4 @& G5 S** Output - Serializer Tx is connected to the input of the codec 4 C- [7 T6 U }" e
*/1 Q/ A+ R9 W0 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
l8 h0 _) i" ]" s7 L7 aMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( X# ]. R% X1 J) ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 ]* e9 r) q# h0 l
| MCASP_PIN_ACLKX& `1 i8 k7 g& b
| MCASP_PIN_AHCLKX
0 O2 H4 F( \7 l7 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 \' K& g& r9 e6 I1 r6 o' B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 g$ h) m+ K( W. J. i* D ^4 q( V| MCASP_TX_CLKFAIL 1 O5 k1 w$ T4 g- p e. M
| MCASP_TX_SYNCERROR
0 z9 v# n8 i" k* O$ [0 U* K: t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& V/ H1 i6 g7 H2 P| MCASP_RX_CLKFAIL9 ^. l+ ~1 i' I. S
| MCASP_RX_SYNCERROR - P. v; C M, X0 N8 `* h
| MCASP_RX_OVERRUN);
5 ~# k) V1 B9 i6 D} static void I2SDataTxRxActivate(void)
/ ]8 \% Y' r. d u" V1 D, u{
/ S; p3 d8 W! Q$ t% W! N- t/* Start the clocks */
2 b% \( \/ V# R0 H8 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 j( d+ \ `. j' HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 e2 v1 V( q# b) E4 x3 Q$ {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 ]& Y! q) g) m) M2 c) X
EDMA3_TRIG_MODE_EVENT); y: \: e' ^( A9 x# n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& q3 q9 B, F* a) rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 ~" r4 m& P" T2 IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# w7 o0 h0 ~: w- {+ e: pMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 B( y6 F4 c% {; vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( f% _+ N$ C. x3 qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 q/ p, ?4 E4 {8 H; |7 f, O! L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 Z7 ?9 `9 E3 X4 q$ t6 r+ B* w
} 2 P+ E S: ^8 y& q+ l$ K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 c) M3 a, D2 a, V- o; k
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