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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ C |0 q& y) c. @, o6 w) Q; r: A
input mcasp_ahclkx,
4 d* A$ I/ ?' Tinput mcasp_aclkx,
+ Q f: t# A& X* Y* p) V: Linput axr0,
7 M6 h1 ?4 J, y3 X& n& ~- G* Z2 B- }$ w# w$ F# X5 @! C
output mcasp_afsr,
$ W% d& R# R! eoutput mcasp_ahclkr, y( E: Q6 z; \& v) X- ?1 Y
output mcasp_aclkr,
1 ?1 c8 y! q* g+ M, l: Poutput axr1,8 F1 X% I# F$ J& V
assign mcasp_afsr = mcasp_afsx;
4 ~* y9 g: N0 H, R/ Oassign mcasp_aclkr = mcasp_aclkx;) E @& b: \; Y4 i* g; ?
assign mcasp_ahclkr = mcasp_ahclkx;
2 o8 K' `) M1 I% Eassign axr1 = axr0;
0 H5 h1 V, D6 n1 I9 @- ]; [% `& @
/ C; S' p7 n# ^7 Y6 |1 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ f3 G( g2 N" A9 ]5 Qstatic void McASPI2SConfigure(void)
: d' e" H1 }6 Y8 Y{: O. t( \8 t* N0 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( p3 u" t- t- D9 m/ wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ D1 i# }, M3 h% Z' w7 ~/ t, r) ^, \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); A4 |- P/ [- _( ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 s6 I) V4 S9 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 p4 ^4 V1 ]' f+ R1 L2 W TMCASP_RX_MODE_DMA);# d- P; D6 i0 \0 J2 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 x" r+ q" y1 g* x1 U3 e, Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 {( d( x" [3 j- d8 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 t' o7 E, e9 d3 g0 m' {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 x# D( q0 }5 D( yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 k& |( ?: ]2 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! Q1 N9 ^; z: A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* |. ?# S' k* o3 ]) {; mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , O6 p8 \# q( m5 G7 A7 i* o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," }' r+ Y% H2 u# t* ~
0x00, 0xFF); /* configure the clock for transmitter */
4 G+ E5 u1 ?6 t3 {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 i% Q! [- F- H$ {+ N0 SMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : b3 ~1 b$ B0 i/ T/ [- P6 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( t D; F- X: d! p) K6 G0x00, 0xFF); F9 W) `: N/ v$ V
6 `, d7 {: _8 n3 {) l
/* Enable synchronization of RX and TX sections */
4 W: J& }7 G3 e* xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 E, _9 U! [7 e9 Q( p0 r5 N" k! LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ F" p, z# T5 R, X- yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' m% q: N, \, b1 e0 C+ x** Set the serializers, Currently only one serializer is set as+ M- `7 t1 R5 \7 d; q
** transmitter and one serializer as receiver. z1 j& ?+ s L2 d+ j
*/- H; q1 t$ o/ K* N3 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 l0 W1 M+ D* m" eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; a H$ T8 i9 d/ D2 w** Configure the McASP pins " Z5 A) }% a* [) K/ y; b" H" f. i
** Input - Frame Sync, Clock and Serializer Rx; t( R4 R! V G; s+ O5 L
** Output - Serializer Tx is connected to the input of the codec
6 Y# k/ z. C3 a! p9 N*/3 c6 _+ a+ n5 r, j: {9 i6 W% S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: h* p3 q$ [3 D O3 A' _$ VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ S: m# k. a9 Q5 A% a D" n' w* v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, f5 F' H% ]% A4 a F4 ]
| MCASP_PIN_ACLKX( S: {" j' \* C3 {
| MCASP_PIN_AHCLKX
* M- a4 v5 [2 X [| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 @- n( Z4 ]% W6 u- qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. S7 f6 S8 S. ]| MCASP_TX_CLKFAIL 0 a$ A! @* T- {! o8 u! i s) b5 a
| MCASP_TX_SYNCERROR; \; _# @4 k$ ?; V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ W% i) P" m' [| MCASP_RX_CLKFAIL6 d$ S* H& P; ~' ]- O* H9 f
| MCASP_RX_SYNCERROR 1 R% j* S. R- a; \ J
| MCASP_RX_OVERRUN);
8 K2 _( Q, M+ `' Y1 U S6 G8 x0 D} static void I2SDataTxRxActivate(void)
' O9 T( J1 @0 l; s( I4 p{
( F4 o! s$ ~9 a% z. q/ n# ^; q: v/* Start the clocks */. W$ a- K1 S+ P) j5 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& i' v4 g/ |( V& @6 T, OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 v6 F& Y+ k2 x+ h- s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 G/ `) m2 K, r% z, [, P( x$ U) sEDMA3_TRIG_MODE_EVENT);* }' v8 v: ^) E7 W& b1 Q) _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! U$ D& l7 V2 g& A8 [' n% lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 o$ [" ]) v0 D' P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 r9 Q; f( E* t/ v! ~" X1 N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 R. U" l) |' ?8 _' h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# R0 r7 ]" C9 U% gMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, V4 b [9 w ~# M6 `$ ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 k) ` G7 a0 }* q+ T1 ] n
}
`1 H* `' p- z! |: n( n7 g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * r7 j- P1 K" g& c5 n" U
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