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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& D% ~& { v0 \0 Y
input mcasp_ahclkx,
, H/ V! ^4 h# Q( b" ~3 b1 ?% Uinput mcasp_aclkx,
# n, _1 O+ g3 W0 f' q1 Q' p W2 g7 Ginput axr0,7 V) V/ Q2 x2 G: y
# i- O5 C8 U- x8 I
output mcasp_afsr,: y. c# a( `* S6 _0 h
output mcasp_ahclkr,
8 T. S3 n% E6 |* ~" ioutput mcasp_aclkr,
( M# B/ m7 I4 I! G d! g4 houtput axr1,6 H; p: O. F% ]; \8 ]& F) S9 ]
assign mcasp_afsr = mcasp_afsx;
, z% ^# ]- g) ~4 N! V. Gassign mcasp_aclkr = mcasp_aclkx;
1 J" l$ b, w* r# w6 o/ B3 A" {! Zassign mcasp_ahclkr = mcasp_ahclkx;
+ d: D0 o5 J$ P' H3 V; i& Y9 L& e9 N3 {assign axr1 = axr0; 7 I0 m; M8 L4 g
& Y% g7 N6 d, j! Q& @0 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 @1 L/ P" l& k) J9 I& Z& e& p
static void McASPI2SConfigure(void)
- P9 U# Y2 z$ e{: F4 }0 T8 m# E" w' o* g- o* W O% e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* ?& }2 ^ m. i) I k; PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ W4 V( J, p ?9 }+ i3 m# Y1 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ y7 `" m: U5 y4 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, _* i8 {8 \3 q3 |. IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 C/ X3 e9 G. o) k6 T/ W
MCASP_RX_MODE_DMA);
+ l! j& g/ M$ {& z3 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( h* e. g l: M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ ?( a( H7 C8 v2 O7 S* Q7 H8 s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( }( I% U* c. i0 r! G8 q7 n8 h. t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. r( r; I2 ?3 D& n/ a8 p" C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 J' M9 y5 ]/ ^' W" fMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& E) C! s! z1 l2 ~$ WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' F3 e5 g+ u0 d* d. u4 B+ K4 tMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - o- T* z6 y& ?/ u' [2 o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' Q9 d' |7 ^, w
0x00, 0xFF); /* configure the clock for transmitter */0 |9 b; f9 R7 t2 h i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- a, |7 K' t+ @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( {+ @( A' `. a0 a+ |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) R) f; b3 P' U, k, U: ^* n( J( o5 c
0x00, 0xFF);5 g" H2 y+ d0 G& Z4 {" ~
2 n! c: o5 k1 d/ o9 n0 J/* Enable synchronization of RX and TX sections */ 4 n! r' c6 N( P& @4 \. l. F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 C9 s0 b0 y* c2 yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; p% I, M( _6 H# i* LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ k5 _+ H8 @) S# }2 }8 l) y** Set the serializers, Currently only one serializer is set as! k/ G V7 U `* _. c
** transmitter and one serializer as receiver./ Z; ]5 X0 @7 ~* ?/ w) ^/ m
*/
# w3 K! {/ |) T3 kMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ ~. c3 t5 s. s: c% K Q% [+ f( Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 N! Z" o8 _7 m0 L2 r6 _** Configure the McASP pins % S5 ^) r8 G- Q1 q# V" Q! g- [" H
** Input - Frame Sync, Clock and Serializer Rx1 [ J0 h4 X7 O: Y' l; a" O
** Output - Serializer Tx is connected to the input of the codec
# m- J& ^, h# |2 q% |. I& D*/
+ Y: e0 R6 p6 V$ L& mMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. u: A2 i1 l9 G! a7 j9 RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# Q- V: q4 T" [0 I# OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) O" J$ f5 Z2 @/ i6 h( `/ |# @| MCASP_PIN_ACLKX9 H% d8 v6 \4 k/ M: S2 f# Z) Z7 r
| MCASP_PIN_AHCLKX
3 Q/ N7 }# Q: C9 Q6 w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, h) r- k# f; w5 M
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 j4 J3 S! G$ ~4 \1 R) a R
| MCASP_TX_CLKFAIL
8 B" t$ `( n9 _/ a" x+ J; ?; x) U' z| MCASP_TX_SYNCERROR2 ?" s( w# s3 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 P, t3 u, Y- n8 ?
| MCASP_RX_CLKFAIL& A+ Q# [9 B3 x5 X/ w9 M4 T
| MCASP_RX_SYNCERROR
3 q/ g% _8 }: l5 S( C, n, M, j| MCASP_RX_OVERRUN);9 g' ^4 N, E: M0 s1 }- U
} static void I2SDataTxRxActivate(void) j5 E& }3 X8 s2 o' D
{
9 K A$ W6 ^' h: E m6 [( q8 h4 I/* Start the clocks */
6 J# S; v& Y! s) q/ f% x1 L8 @, rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. C# n; k) ?+ h8 L# E5 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" @( d- r* l! M. Y) k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ W7 v. y1 k4 ~% f
EDMA3_TRIG_MODE_EVENT);
" [1 B1 q) d$ V/ ^; l+ h$ @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ _& `6 c# s5 p7 V; N' yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( k$ m/ g; ?+ ?+ B4 h; o$ yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- z: S }- p1 ^3 q- DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 T" g( {5 B5 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* P: V; l( W X# T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- p, x8 Y8 [; [) C6 b3 ~# }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' \2 I; P! o0 f- z}
( i& F) t! o I) J% b2 M. q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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