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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ D" K4 c" E0 F8 Q9 N4 Jinput mcasp_ahclkx,
' x$ [8 b4 m; T. m$ V: H- yinput mcasp_aclkx,
+ D4 P5 P+ j5 ]2 a; h! {& |input axr0,5 u# m4 t# d0 L$ g, Z" [! m
: ]; ^, e- d, W# a$ r2 A$ H
output mcasp_afsr,
! [' {, c/ C: d# D& Q5 w4 n$ Woutput mcasp_ahclkr,3 E' [% Z# `2 d5 j; O: m% e
output mcasp_aclkr,/ E6 A# V! J# A: R
output axr1,
2 N! p) H# s1 ^; g: w8 K! p3 O2 @ assign mcasp_afsr = mcasp_afsx;
$ `- ]# ^0 j6 Y; I: x6 i; Rassign mcasp_aclkr = mcasp_aclkx;: b# m0 L* ~, Q, S' v
assign mcasp_ahclkr = mcasp_ahclkx;
3 D, c! H: z6 Nassign axr1 = axr0;
. Z. x& K. V* r2 ]) _3 T6 L4 D$ v, d
# Q8 K: D [# S3 I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 {# _1 ^# T0 t/ m
static void McASPI2SConfigure(void)8 P- N" S6 w# Z6 C" V3 ^
{1 `* \" f+ F, p% {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 E. p5 ?; }/ z- dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, K6 K! u* B# | k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 v* _/ S0 [% Z% y- p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! O& [1 _' |9 |! V* a' J! }( RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, }: @6 V# K' e+ L7 ^$ }
MCASP_RX_MODE_DMA);
4 Y& k1 F+ e6 [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 ~* W! [7 e; u. Q7 \1 r; S; @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; p+ h O' V( C# w: \2 o, ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# m- M/ q8 ~! q7 M6 v) |& @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, T' R* E0 d/ b; o5 \, n% x$ ?; W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; p3 ~ V/ m D% QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' c9 C# j3 c- s# D9 o5 X2 w; b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ a5 A* C) h: h9 b; e, C T' |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 b" l2 E6 C, R( T% j. J- z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, u+ o/ [* I9 h2 _" t0x00, 0xFF); /* configure the clock for transmitter */3 w; p( Z! T' C( {
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) L P% d/ s1 D7 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ P5 `0 a8 a3 T# ]" d6 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' k! D3 r) s4 `# b+ C# n. ~2 a
0x00, 0xFF);# d. t( k1 }. D" B/ k5 u0 m
2 I7 _3 C+ M, z; v( h0 r Q T
/* Enable synchronization of RX and TX sections */
: W6 ]. W* @/ G" B1 p7 \ n0 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ B9 k% s' U5 k7 x$ dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, g- f. o+ B' f+ j. U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 N. t: K/ D0 H( \. C/ [0 o
** Set the serializers, Currently only one serializer is set as
) f! v9 \# F$ B. J4 R# A F0 Y** transmitter and one serializer as receiver.
) n, u& W+ `+ [: s& l0 P*/8 L+ G6 z! }) _$ ?& T- `, x! }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 [8 y+ S" `' M2 z* nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* F, E0 d; i; p5 j
** Configure the McASP pins
' b. X' D3 u. D/ s) d% |2 D- R) x** Input - Frame Sync, Clock and Serializer Rx
2 W. Z' C3 Y* m9 R( [. Q** Output - Serializer Tx is connected to the input of the codec - T$ |0 B: Q0 {% O; u9 S; E
*/
, e4 x( I! G2 h9 r8 cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. [- d; l$ \. p4 t3 ?' I! hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; }& G' O! _$ r0 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* D) ?' c. V- @& l# V1 \& t
| MCASP_PIN_ACLKX9 l+ A. V/ ]9 Z! J ^: Z& @8 z
| MCASP_PIN_AHCLKX8 }" ~# T4 h) i% i8 _( a) a
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' x4 f5 k1 C3 z0 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 y X$ h6 Z0 B. e9 p2 W| MCASP_TX_CLKFAIL . a& \9 u" c6 W$ R* Q
| MCASP_TX_SYNCERROR( s: Z! n1 S6 X6 _( c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % M. G2 t' J) L/ ^: y
| MCASP_RX_CLKFAIL+ ?: e% H, A" t/ p* T* O" C' _
| MCASP_RX_SYNCERROR ; T1 |9 f+ F% |7 n/ J
| MCASP_RX_OVERRUN);
) Q0 A% ~* B% M* H3 J* h, ^$ \% i3 |5 e} static void I2SDataTxRxActivate(void)6 m& L6 H2 E" u! P1 R, L* l7 N
{
4 P5 q# ~6 ^1 g: D/* Start the clocks */. A+ e$ Y" h e$ R0 W8 u( I1 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' Y, N0 r5 T! U1 P% `& R* ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( P$ a l2 G% H, ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 h" h& s) z2 q9 O) r9 S
EDMA3_TRIG_MODE_EVENT);+ E1 v( X i6 g [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* I" B' w: J) VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ q, W3 y6 H# _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 V, j( i' T7 D3 |: D( yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& a. }5 W( [5 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, e. c1 ]$ |- ~4 X0 h+ AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; v4 M# D6 R+ _% ?- BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ e0 h* P+ Z4 q1 m8 Y} 4 ^+ _+ E% H( [; ?* ^
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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