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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( P$ ?) V' }- e! ]- Y# t# q" Rinput mcasp_ahclkx,
3 e7 M4 w R- I( s% o2 G; Minput mcasp_aclkx,- _$ K- N7 A( @: v# p X$ e0 Q
input axr0," W/ J; n1 A% g! [$ K9 W
" B$ ^# |6 P8 l; I( B2 }output mcasp_afsr,
$ h4 U) n5 l- l' O, Zoutput mcasp_ahclkr,
( ^" p9 F: X, A6 v* p# noutput mcasp_aclkr,
+ {8 C& K* }3 P' @' Houtput axr1,% C0 y# g; B# n) J7 o' j1 U
assign mcasp_afsr = mcasp_afsx;
) q0 e+ V- n! y7 [" ~5 g! iassign mcasp_aclkr = mcasp_aclkx;( \% t; Z' C+ R `
assign mcasp_ahclkr = mcasp_ahclkx;
% ]2 K9 k2 D( y) eassign axr1 = axr0;
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7 d+ K: h+ a9 h1 T! d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ B' c; k; s1 z I; i8 Nstatic void McASPI2SConfigure(void)" T8 m4 s& Y) g0 V+ Z
{
& O' P5 f7 D% T0 m8 o2 r% bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 A6 E5 I. t- n: u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ ~+ j2 |6 Y2 C" b. jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! E3 c. ?% t# _. J; \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" I8 \0 g2 w) ~, m8 t+ C5 u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# e v, E4 y( l" ?6 j3 @% M4 hMCASP_RX_MODE_DMA);
6 p2 p7 e# |1 o6 b9 P( C9 j; d+ pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- S) W/ H9 {0 v& B7 h( N- u$ ?+ `. sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! i5 K. ^. y# ?) n. d8 |) v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 1 M( V. i. l& [- F8 R/ a+ |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ k4 k5 {* ?6 z$ h9 T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. I. Q4 c) }% J# w* X2 p1 HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 E' F5 Y7 q) x8 U5 [; y# [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' }$ R: X3 P( w- d7 t& eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, P6 s3 R) m6 `) ?2 fMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ G1 I9 M' Z6 d4 K0x00, 0xFF); /* configure the clock for transmitter */, U3 ~, V3 W2 f# `8 u! x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 s+ j7 g( d5 o3 \" @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% g7 ?& J5 H/ `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, K: Z3 y$ E S' F6 R+ j a: k0x00, 0xFF);6 s4 u6 b/ W$ i5 X4 P
. l; {0 n1 R# |. T/* Enable synchronization of RX and TX sections */ + H8 u8 _- j6 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( g9 q5 F6 c8 _. b6 @/ FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% a* w6 t }: o+ B9 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" e3 t. E) k5 P+ ?+ n+ o** Set the serializers, Currently only one serializer is set as: e6 l( R. T. S) S, F
** transmitter and one serializer as receiver., L" l; T9 k0 O5 G. L2 J' i
*/" i4 z! L- c o9 N" {: t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
B' m: m, P h9 g0 ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* P, [; \" q o" k7 K** Configure the McASP pins
$ C- D* H, o2 w** Input - Frame Sync, Clock and Serializer Rx
7 O( C8 J1 h. i/ v, p! t+ N; o, |** Output - Serializer Tx is connected to the input of the codec 0 n# S, A7 y2 ~' B6 p
*/
: e% Y( ?) Y: TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 k2 V9 T% e1 m$ p z! g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( d! Y& J8 Y& I6 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; D6 @0 Y: h' K
| MCASP_PIN_ACLKX' r5 [) a, {) J
| MCASP_PIN_AHCLKX) Y4 `6 [* c3 \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, N6 v- g. M6 e6 B6 G K1 w' V( dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * P0 r/ R1 \% F2 F, v o( C7 z. e
| MCASP_TX_CLKFAIL 3 L' F/ b2 a' o3 u$ u
| MCASP_TX_SYNCERROR
- S$ o" I0 u$ ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 N" B! i3 c2 O/ {| MCASP_RX_CLKFAIL; K7 p$ B) w5 O+ L7 i3 k
| MCASP_RX_SYNCERROR
2 k3 ?1 _+ D# r1 k/ m5 Y! G| MCASP_RX_OVERRUN);% l0 z; w8 d6 h1 y7 o! _
} static void I2SDataTxRxActivate(void)
4 ]6 |; G9 W+ m- m1 K8 H: A{& T4 A& V8 o) q$ t! q$ T! C
/* Start the clocks */
, Q! s2 _$ v6 KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 V5 X# D2 b) E/ R# A6 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: X0 R/ J) e$ i6 qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 E6 n* S6 N7 ^, Z/ w" |
EDMA3_TRIG_MODE_EVENT);: a8 H8 x3 D2 o9 R: U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" Z3 j6 K+ _5 O e' H3 WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( ]& _2 d# _' I( Y' a4 G6 h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; v+ D0 \& S% ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 k! G8 j, M) u, ?: _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 d3 A* }3 I' w# V* V% `1 M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 A& f. f' |8 P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! e; b* g* v f
} 9 t' G- ?9 t b C# O: [0 ~' q; C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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