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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* \2 w) N+ q) x9 ?input mcasp_ahclkx,
- L- i& s$ Z4 ^: l f& j& iinput mcasp_aclkx,
0 j8 V' o3 \. a/ F- y# f8 [# Finput axr0,. t8 W. A4 Y: g8 W0 i& T
, c+ Y' n3 g8 c2 E" r1 a
output mcasp_afsr," E- d4 r* E1 m7 Q9 T8 o) G5 p0 w
output mcasp_ahclkr,
8 J% `2 x9 I. O8 z# G+ D' M/ Qoutput mcasp_aclkr,9 ]4 V3 O5 N" g5 w( `/ Q
output axr1,
& P, e' m/ E6 h) |& [ assign mcasp_afsr = mcasp_afsx;" u+ C; S$ A3 v# q
assign mcasp_aclkr = mcasp_aclkx;1 ~2 E3 N2 M: s6 R% k$ N
assign mcasp_ahclkr = mcasp_ahclkx;
5 A8 A7 }8 M0 U) iassign axr1 = axr0; & G0 p% N4 N, K. T2 x
% d: ?0 M! Y2 r, ?. h3 R: a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 X& Y8 G% [& ^ G ?static void McASPI2SConfigure(void)! i7 i- W/ ?- Y# ^! R
{
+ X& `. W! m1 p# JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ F- X3 E% G* i) t, `, x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# u: y& s( e7 l* T( |. {- c9 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 ~! K1 l* M+ M! G; x8 u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 b- \$ y) e, j3 g! ~. O: u4 m) AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 K4 Q% p$ r( K2 K7 m* m% U
MCASP_RX_MODE_DMA);( X. f$ U0 f9 k8 G1 M
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, S" B. m/ T2 q; U4 H& B2 G. k1 }# b3 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 j5 y3 ?# [+ P4 e( QMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . u5 _& t. a S4 x. B) m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# Y( W( D2 Z8 U8 ~1 s! ]1 L( u
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 m; R4 o- ?. a, O$ a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 Q1 I% r f: NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# E" `* L# ~0 [) @8 I/ A% MMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- }7 r3 \3 p; ?- f+ z$ BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 c- Q6 z/ Z; m) l5 \* Q% u. K
0x00, 0xFF); /* configure the clock for transmitter */
5 K. P# L6 F7 M: s8 S" iMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- U' \' y. X: F: Y) s" ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ U8 C; K8 ~% l9 g5 E- cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* m* J4 M, ^& L* T8 Q% @ P1 I0x00, 0xFF);- {: z: a! z/ U" {
" [+ A/ E5 n4 S4 C7 B/* Enable synchronization of RX and TX sections */
7 Q2 K! M, @7 R/ b- I6 K- V* c2 {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ K3 W6 u2 |0 k. [" n, V mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% o& V! }9 o8 i# p* |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: z: l' b; Q/ {; Z4 ]' R* d
** Set the serializers, Currently only one serializer is set as
4 f+ F7 T, e$ ^' q** transmitter and one serializer as receiver.
, Z; n- d- P0 E' V) P*/
4 b4 r( s0 p zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 D# N- {# o# E3 _4 z( xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! S( C" `! c9 d0 i2 g
** Configure the McASP pins 5 v% I$ f `- ~
** Input - Frame Sync, Clock and Serializer Rx/ s: j7 C; |4 S' B. y
** Output - Serializer Tx is connected to the input of the codec 6 t, f8 g2 l' k( ^7 p3 S. }$ k
*/
: w0 ]! E: q5 s- D# V1 n3 SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: U( h: D; Y6 H( XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* Q/ W# M% J8 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. ` D) G. G) V. w) m& c| MCASP_PIN_ACLKX/ d0 z: @; U$ m, p1 S; w
| MCASP_PIN_AHCLKX# r" V/ x+ e, V2 l# q" E% h( k: c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 V% K, q7 S0 `# Z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 j. c0 W1 f% G6 B1 c/ C3 s- }6 l| MCASP_TX_CLKFAIL ' L6 {$ U6 }9 Z& \6 I
| MCASP_TX_SYNCERROR
4 b) t* v s1 @3 g& S/ P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # A5 P3 D, B- {; `9 U+ }
| MCASP_RX_CLKFAIL
( R9 a% [' ?, [( M% V- h| MCASP_RX_SYNCERROR
- U$ x: z- n( |3 f; Z| MCASP_RX_OVERRUN);* ^* W4 e D# i6 P Y
} static void I2SDataTxRxActivate(void)3 k) f( V6 C: @4 C% E* u
{" o) S% m" d2 ^( \, C
/* Start the clocks */7 k t0 {# U, X) }9 x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ F+ f/ D7 \4 X$ R, H/ f5 }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" D) f+ ^, v0 x! QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 F+ I# B5 _( O8 }& w7 J
EDMA3_TRIG_MODE_EVENT);/ N& S/ ~; j4 ]6 E1 n: j% H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : U( e; [$ y8 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& H. z9 a, @" ]9 T. X6 T. {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 k! p( N2 |0 R) _6 |+ I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% n$ n6 ^. p9 b( F6 H: Z5 n1 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ T. J, I. U+ k6 g% J1 f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 y4 j/ s! z# I) r# S- u5 h+ Z# ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 I$ n5 C2 u2 G4 X6 d0 [9 t
}
4 X% y0 s9 N2 r' I6 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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