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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# U o) ^) Y) U- tinput mcasp_ahclkx,
, E# j0 T$ R* a5 y! J2 Oinput mcasp_aclkx,
6 B( @, g8 C. {, d- dinput axr0,8 n8 V: P- [) ^6 V" }7 H; ?
7 d2 H1 M* @4 h0 Joutput mcasp_afsr,
; f8 A6 q2 |4 d% h: D4 x% H6 youtput mcasp_ahclkr,1 \. q/ L$ ^# n3 b2 a, \$ K
output mcasp_aclkr,
& w: p1 [/ m: F9 h7 @$ routput axr1,
1 {% p/ U- F- s- @! m! _6 y' I assign mcasp_afsr = mcasp_afsx;
: J, l; Q g. N5 qassign mcasp_aclkr = mcasp_aclkx;
' ~) U, @7 W/ ^1 c# n, |assign mcasp_ahclkr = mcasp_ahclkx;
9 t& D5 ]& s& _( G; C& V! Vassign axr1 = axr0;
3 n) v. B/ F2 o/ j6 A6 U3 G: R4 D
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ ^1 S7 A. d. ]1 O
static void McASPI2SConfigure(void)
' j% w: _, w' v$ e! i# P1 a{ k5 |- |+ H# K, ~- c* F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 T6 R/ A, V5 k; Z$ G, U$ r
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- O5 X" p. W+ a; n) }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 j6 y) Y" P5 b- H6 t3 @2 K5 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( Y. w7 C0 m+ g& xMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 f% n7 {* ]! f, a' ~MCASP_RX_MODE_DMA);
; S$ p, b, v8 n) UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* v( `# b1 E- y/ K8 w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 s, U0 U) L) L- J5 H3 Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % U- K0 v! ~; J7 c6 E, y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. |+ l" Z6 _% O1 ?& d; f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! H \# [* v/ eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 ^# G7 \- F; q" v- W E3 Y+ NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; u5 K3 z* J4 v, B- qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); l: B9 p; B" F; T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 m4 W; y5 R! L7 b, S0x00, 0xFF); /* configure the clock for transmitter */
" B& A0 f! [$ b% E9 XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* [' y8 V% H! S; n' ]! v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 ]' t9 a1 h0 K5 N0 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( B0 P% W! r. e8 S6 L" q0x00, 0xFF);
( K2 n* o0 Y, D; c) F" {5 B6 T+ Z C
/* Enable synchronization of RX and TX sections */ / Q0 s& o( V) J& d+ d/ m( a$ ]6 A( y1 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 ?" ^8 C' q! R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# ~6 K4 R/ J3 z# k; `+ ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 t2 M- R* J0 ^0 i% Z/ h) X; M** Set the serializers, Currently only one serializer is set as5 d9 _1 V( b' y6 h; ~6 }+ n
** transmitter and one serializer as receiver., W/ e! v- b. S& d" A6 p
*/
* }' f, t% ` M" Z, CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 f2 A; S4 Y3 p, E) h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 J% |0 H" k: O8 n; k4 i** Configure the McASP pins # j; c8 R$ U" {, }' u9 I$ w
** Input - Frame Sync, Clock and Serializer Rx
9 Q4 D6 K8 F. U** Output - Serializer Tx is connected to the input of the codec - q$ L6 @8 F: E. u2 _* B
*/* Q; R7 [+ T6 h6 S+ [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 m, g; c6 A! d* G, p' m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 ^! F5 X1 \! _' [. r$ Y7 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% M; R8 c5 O$ r! q, O) T, l| MCASP_PIN_ACLKX
) g m. H3 Q7 {| MCASP_PIN_AHCLKX+ n5 u& B9 K5 R7 }# q. O. d! D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 t. r/ s5 X9 V7 }2 A7 t, AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % ~# u- i! B, Q. e: X6 A
| MCASP_TX_CLKFAIL 0 I9 U* L) E' F3 [ u6 S
| MCASP_TX_SYNCERROR6 Z2 n" E! z; |! O M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR J7 k, ~, M1 y/ \7 G1 K
| MCASP_RX_CLKFAIL
+ x6 P. [6 A7 ~0 c4 x| MCASP_RX_SYNCERROR 6 o- Y, l! p$ C" D" `
| MCASP_RX_OVERRUN);
: A7 m5 N. j* I7 H* I- p} static void I2SDataTxRxActivate(void), P% I5 p H" F; P& |
{* T+ r0 o" P9 d! x% }
/* Start the clocks */! |1 J7 q' y) s3 r7 {( s4 g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% J2 s# O: \! M% T- r$ SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- h! i/ W. f. I3 i7 m6 ]# p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% y! ]8 R3 Y8 e2 G$ v4 F
EDMA3_TRIG_MODE_EVENT);* ]1 w' q; j" x' N6 y, G2 _% J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 W1 y7 x9 D6 i: x" S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' ]. z# x9 C1 L5 N3 g4 qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 d! O9 s8 t8 z! `% X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# J0 S1 x8 h9 r( r2 F* _! a; pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! R" e3 o$ E+ \$ W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 T7 q# R* D7 `# P. p
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 g* T: k3 Z3 t/ j}
) P7 l, s$ M8 A8 }& \+ A! H3 Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 r1 l; y" U' l, g, ?, f' W
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