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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 \/ A0 v. O: V* X/ u3 ?7 {
input mcasp_ahclkx,3 l- o& V2 C7 X, _4 C, @
input mcasp_aclkx,2 l& |* P8 l: }3 D' x2 e( Y
input axr0,% ?1 v$ V! x5 n- V3 M3 v! ~4 O
; H( k- C. F) u3 E+ [; u5 t2 V0 Houtput mcasp_afsr,) |; Z5 Z( Y: S" r7 t5 B
output mcasp_ahclkr,( l" d& O% O6 P0 ?
output mcasp_aclkr,
" T/ G# p) Q& j7 J+ }, d4 ?output axr1,* s+ W- W' P# J# S& M0 f
assign mcasp_afsr = mcasp_afsx;
$ y- s- b1 J* H2 y7 B2 W* uassign mcasp_aclkr = mcasp_aclkx;
1 P2 g3 ^# s) V/ F' d* cassign mcasp_ahclkr = mcasp_ahclkx;
* H9 h" P, g' n4 Oassign axr1 = axr0;
. ^9 V9 H& p0 T, r8 }8 P
A/ c: w( A" U% D- ^4 C% R" h% N3 c: p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 J% r- ?! e% Z! A/ Y, t. T( u/ Z Lstatic void McASPI2SConfigure(void)
- G7 P% \* ^- w, O* [{6 ~1 \; w+ b2 n( o: ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. w' {: t9 d! f3 C* x0 z/ BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& L3 C+ a7 C. G7 G/ u1 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 G! _: u7 q9 C& c7 ?6 y) WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! i5 K E- p2 \+ P, c7 N6 u' NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 v) _* A& Q( G; f; g, _
MCASP_RX_MODE_DMA);$ S3 |; [& O) O6 O) r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' u8 K! A) ~$ O/ i% \& dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. G3 r; v: G4 A* P8 W" U; w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 m4 V/ I, F* l' D/ SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ?9 j( w" V: J. s8 e9 A! M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " w/ ~. W. @4 c4 u+ D$ a( Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 j% K! n( U2 ^2 U6 a7 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* k0 Z \; ?' W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( A/ V1 i% B, K; JMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 ]! p+ X* _7 E0 V! l
0x00, 0xFF); /* configure the clock for transmitter */0 z! T F% C1 F: F! g# T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# O/ P( c4 T, B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' }) v+ P ]( M7 \- U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# [. V( w- {$ E% b; R# J5 c0x00, 0xFF);. Z. A$ j, Q% t+ z/ c( y9 G
! j; J; i' m" l- |' a8 N
/* Enable synchronization of RX and TX sections */ + ?0 ~: t8 T1 |7 W K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
L7 }' Q7 C8 V x1 k" N bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# q7 ~3 C* B0 R! q9 o4 ] o( U2 S, t. CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 E" x/ ]1 T' A; [* F( m8 ~6 i; P
** Set the serializers, Currently only one serializer is set as
9 S% n) I. J: k# [$ ~5 b** transmitter and one serializer as receiver.+ [8 i: }0 _' J6 J. j S! L
*/: z# u L% ]" U8 U5 J1 j" R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' K8 G; w5 H+ W3 @& jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 }3 s- Q( G% ~: j6 [8 W% O+ }! w** Configure the McASP pins 7 \! ^' c6 u N# h( ^: l3 Y
** Input - Frame Sync, Clock and Serializer Rx
2 h9 ?5 K! y1 m0 {, }; s** Output - Serializer Tx is connected to the input of the codec
2 k& c* f" @. s4 D*/
/ W6 g+ I; f8 M1 ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. ]" d. x6 s7 Y" l& y" O6 L E: U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, L6 I) s0 n$ p' m2 N% E7 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 q9 E/ _, b* l2 C- Z0 o- n
| MCASP_PIN_ACLKX) [6 g1 e$ q- D
| MCASP_PIN_AHCLKX
7 K9 V1 e5 C& E- d3 j" f7 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) S# c! Q+ [ n- e" n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% M5 j- I) y e1 E+ J| MCASP_TX_CLKFAIL ( Y' _3 E! Y* M4 y0 u4 ?3 U' m0 ]" Z
| MCASP_TX_SYNCERROR
2 I' O) h3 _% w. G q( ~| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& Q- |/ `9 E) [3 c6 O" L9 D; ?7 f| MCASP_RX_CLKFAIL# B' M: I. g B$ {, ?; s- ?0 o0 t
| MCASP_RX_SYNCERROR
; O; V1 v. X; f| MCASP_RX_OVERRUN);
" p0 H, u; ?; S$ F5 B& G} static void I2SDataTxRxActivate(void)
" O! @$ K M4 X* t2 q{, m5 q1 u0 Z h: y, Z" N" z
/* Start the clocks */2 o4 h7 X: A0 J4 [; I; D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ B6 z( D* J# }( }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- p, e) v3 v; Z! x' o, U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. q/ j4 v; a% W$ W3 d# E
EDMA3_TRIG_MODE_EVENT);; H6 A" o0 G1 r. z4 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 P i1 U0 S, g: G9 JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. L9 w/ ?' }% g! O" u P# fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 U# W, q; c/ n9 A. I) ?+ W2 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 X2 f, T( N, a |; T- x$ ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( e: l& Q& H% Z) S5 v1 _. a1 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( m& r O$ N/ s o4 a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* ~7 [ S: E4 Y | K( D} ' l/ t" }6 [" B, N8 }" m* M# r3 r2 m
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . b o- J3 q& T$ \3 w6 C
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