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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 q! A. u! d6 ^5 D0 \" G9 r. einput mcasp_ahclkx,
$ p! B0 q% o. H. G5 b% X' vinput mcasp_aclkx,0 c. I" ]- T3 f* p2 d7 B3 Y
input axr0,0 x N' F9 f8 [8 u* a$ @
0 K6 ?( N+ Q) _" u
output mcasp_afsr,- {& L! q# x" W
output mcasp_ahclkr,
' V& v, n( h4 Y% T5 poutput mcasp_aclkr,
! ]9 {' v, |, O/ Poutput axr1,1 e! O/ p" H& A9 h+ W
assign mcasp_afsr = mcasp_afsx;
8 t# M$ M/ Z$ ^5 m' Aassign mcasp_aclkr = mcasp_aclkx;& n6 b# m* h% i3 Y' f4 f' M7 M2 t/ m
assign mcasp_ahclkr = mcasp_ahclkx;
. Z% x! x5 L4 Z6 e! r& D) bassign axr1 = axr0; " J9 J( y& b8 A6 W: O
1 I5 y6 p/ U$ R1 k4 e, F' o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & E3 s$ }' F) M% Y* U) y2 A9 ^$ D
static void McASPI2SConfigure(void) b/ c. ]- i5 _) f7 q
{
- d" r1 }, I$ z7 e: T9 O+ mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) r7 z# y: ^0 ]1 v9 I7 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 B8 O, ]& f7 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' |( a# L4 `. e& J/ zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ a n0 [. M$ J& b2 l' H3 L- _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ i; k B H: J' X+ x9 g& ^* N: NMCASP_RX_MODE_DMA);* y8 N6 b. H/ |; y, N0 ~4 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ `: _+ J, `+ i$ S* ~* o8 X$ U- U1 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% n% l/ J) |: P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; V& D8 D e( yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 n7 K; C" G+ j6 C ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 ?$ M" W w7 C* o, k
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' P; B% L( O4 x) P% E; E3 Z1 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: ?' T- _+ z9 F' QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( d& L/ F/ G5 s7 [9 ~% t% |8 GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 o7 [9 p' l E+ h* W4 @1 D1 w
0x00, 0xFF); /* configure the clock for transmitter */
, f$ X7 {2 Y7 l; q0 s: T1 fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, n+ f4 i B! D% `( c) \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) q- @1 F, p& s4 R# ]- D. ?" bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," m. H7 p5 l9 t: `
0x00, 0xFF);" L2 p. I7 s! n9 R
* l! F! Z. k4 G- N! I/* Enable synchronization of RX and TX sections */
x& W7 M6 Q0 H' j' P, OMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ G& \- P! x0 Z5 l( v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
d! M( @% F# b: PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 v, b* ~2 H/ G3 ^" i: W- a
** Set the serializers, Currently only one serializer is set as0 z, {* f; S: o
** transmitter and one serializer as receiver.+ ~8 x- h* F( i" X$ r
*/, v, p/ b/ g7 c3 X/ Q" v) {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" I8 b. @. C3 [4 ^4 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 I0 E) b( M) S5 y
** Configure the McASP pins
% o' `: q$ {: R" O3 E** Input - Frame Sync, Clock and Serializer Rx
6 Q) z* ~% P: \6 P** Output - Serializer Tx is connected to the input of the codec
7 D" G g/ N; W2 k5 c*/- I. Q; L" C4 d6 c# P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- j( G" n( ^( r0 CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 h8 z, g8 N- pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( x) ]( x6 _2 K1 V$ [' ?| MCASP_PIN_ACLKX ?( _4 j) A5 `* u5 ~; A/ o
| MCASP_PIN_AHCLKX
/ Z; c( |/ Y4 M) y4 E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 B# U. v5 l! }5 N. AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 O# S8 d# E, e- D2 e
| MCASP_TX_CLKFAIL 8 T4 z. _) i/ ], F2 C5 g& M
| MCASP_TX_SYNCERROR
# ?+ l& H0 @4 g5 p$ s. Z5 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 A6 V6 s+ J7 S( f2 i1 c| MCASP_RX_CLKFAIL
8 ?. H4 e6 K. K9 c| MCASP_RX_SYNCERROR 3 c7 [7 }& y3 W
| MCASP_RX_OVERRUN);8 z. \6 m4 r) V: h4 s
} static void I2SDataTxRxActivate(void)
' y/ Y0 [( |. y2 Z{3 n8 z, U1 N) }. R, P/ E
/* Start the clocks */
8 n/ s4 r' S" m3 Q8 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 N& C, t# s" K# h7 R: dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# R: n$ p/ `1 l+ L" c6 r8 {* |/ V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; M; w: T- m% @. k) X8 U( {
EDMA3_TRIG_MODE_EVENT);
& |( n8 ~* l6 v. a! X! jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 E: N* k: z) c0 u& @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 Z8 ^2 i K6 Y7 U9 O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' V4 ~2 j9 K4 r& K9 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 b+ J% T4 t) b* M; W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& V4 ~. z: O1 r) g# mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, v6 h3 s' h- q/ [' Y* e3 [2 _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! `& F$ F2 I; n+ @
} * w! h2 o9 |9 t* I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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