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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# i# f0 z2 D$ o3 D& V2 h4 S
input mcasp_ahclkx,
I: Q9 i9 M- ^8 G5 P7 b5 V: h) finput mcasp_aclkx,
7 k' D* ^( l$ a. Q; g' H( v- Zinput axr0,2 y( Q/ N9 Y, A# d, J
1 y6 W' f: e$ m# h% t( n) S
output mcasp_afsr,
) f/ B0 q2 T( [. |0 e; _0 poutput mcasp_ahclkr,
+ y n! g% B& C, F% ~output mcasp_aclkr,
1 P& U& ^( h! h2 Koutput axr1,+ S% ^% D/ U" A: _
assign mcasp_afsr = mcasp_afsx;
2 b; g. g6 u0 `! f; _assign mcasp_aclkr = mcasp_aclkx;
2 C- `" x2 H3 ^: _4 n# dassign mcasp_ahclkr = mcasp_ahclkx;( I, p: r/ Y# G& U
assign axr1 = axr0; : b/ Z% W; g* j- h) J3 r! k
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % C1 r) a1 N+ p) s9 }- L4 o* i
static void McASPI2SConfigure(void)+ Y. B0 \6 R) m" Q8 s8 P! U) H" ?4 m
{0 j& t( [; i- @7 [" y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" @- [9 v9 X% t2 x" p/ G4 X# Q3 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; q2 C: I; L; T" |; x9 H8 ~# r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 v/ O( I9 K& i' H, UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
{6 B4 h, k# a: qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ ]' n& o- q: i: ?. DMCASP_RX_MODE_DMA);) b+ v# X1 J8 _3 j3 j
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 {! @4 m) s. K3 [7 a. _; `, ? {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 i; B* p% ~' |3 u# k( _/ e T
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 U j4 V6 X7 K- { Q) K1 k8 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 J4 G* q& r5 K4 F3 Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: h# ^ D4 U9 i2 Y! a eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' m/ y; @3 T# ]/ z! M; zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& K# k# \7 o9 v% I0 Y* GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' a: Q e7 \$ d; ~, c" c1 h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 i/ i+ u( d" n1 {" ^; f( f
0x00, 0xFF); /* configure the clock for transmitter */
+ C$ `$ q" Y- L# D5 m7 U" [: P4 AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 w3 l8 d' C! t6 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 W% b0 O ~8 o) p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ [3 j) P3 j) t: d: Z2 ` C
0x00, 0xFF);4 z0 `5 a+ _! G& s$ y7 f
5 x, K" x' k/ |
/* Enable synchronization of RX and TX sections */ ' h5 D- F6 y$ Q' @1 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 D* a6 ]5 D! A6 o r5 b9 d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 a! b+ @! `% q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 M# i; T9 C8 p" Q
** Set the serializers, Currently only one serializer is set as0 _+ E8 L" p, _6 ?
** transmitter and one serializer as receiver.) t5 w* y* f6 i' n$ A3 i* Z
*/
: j3 |# J# j( O; ^- ^6 Z2 }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 }" b9 d2 @8 P$ z, T4 mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 c9 m2 F5 W' b7 Y. Z( B0 s( t+ ]# p** Configure the McASP pins
$ |6 ^# k( _# y8 H# h- w0 d, P1 ?** Input - Frame Sync, Clock and Serializer Rx/ T( j3 L. ]/ r5 L
** Output - Serializer Tx is connected to the input of the codec 0 }7 T9 `* Y% o, O4 i
*/; ~' m" g1 `. E3 J4 a2 O9 j- H2 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! T) R; y8 c+ p7 }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); Z- c2 |: e4 y9 [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: c; Z6 ^6 ~# |+ Z" c
| MCASP_PIN_ACLKX
$ z6 B, |# V% M% H| MCASP_PIN_AHCLKX! V: s! i( Z6 I6 M( T, L9 l s1 G9 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 W% x* d, X) p4 g! }! Z) |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 X8 C) Y, R7 C# _4 t
| MCASP_TX_CLKFAIL
8 p: \0 ]; H. |! U| MCASP_TX_SYNCERROR
' L( x6 Y, p6 m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 d# b: W# E- F/ r: u y& h" N
| MCASP_RX_CLKFAIL/ X. ?/ X" a2 H9 A+ @
| MCASP_RX_SYNCERROR , O# p4 Q* J! q- t( w
| MCASP_RX_OVERRUN);. t6 b7 H4 ?, `( ^+ t
} static void I2SDataTxRxActivate(void)6 ?0 L- |9 @0 I* M f$ N# O7 I
{2 W% M$ i+ ` y; }- N3 X0 C8 `
/* Start the clocks */
4 n: n3 n8 v& kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- l4 i$ L6 \0 tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; d; |5 l* J% j- u8 b2 d* Y( k9 `/ m% e
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' e M9 e; b1 x' fEDMA3_TRIG_MODE_EVENT);
1 `6 c# m6 S0 t' }( |& b4 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
Q. ^$ ?2 d( W* KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: [6 {' `$ W: k+ \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); B: a; i/ r3 ]( @8 ^& e8 D: A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 v! n8 e, n7 b2 {/ q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 V# K8 x, X7 N% |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. j, p( T- h F9 m3 ?) A3 ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 a8 J7 z) A# Y& q! [5 E; o* Q
} / q. ?8 y; w K9 _; W9 `' f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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