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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' l5 ?4 i$ j1 ?. y5 l' F; T9 R0 g9 h& pinput mcasp_ahclkx,+ z9 z8 ]* {% a& Z9 S' X8 U0 H- I
input mcasp_aclkx,. }: }* R" S& P! o/ `
input axr0,7 {) f* l: @3 _; i. `# Q& ^
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output mcasp_afsr,
& E9 o7 s, A9 v4 \3 Qoutput mcasp_ahclkr,
0 w/ C) W- O l) p6 loutput mcasp_aclkr,
& R. W9 i3 Z/ Z9 u/ Q7 Z$ Foutput axr1,, |" a5 Y" o0 I' L; Y8 y
assign mcasp_afsr = mcasp_afsx;
! ~' C9 @! d2 |assign mcasp_aclkr = mcasp_aclkx;
+ V1 n( S- E9 H; [( A. o; Passign mcasp_ahclkr = mcasp_ahclkx;
" z; w8 V I4 E0 X- \1 c+ @) xassign axr1 = axr0; * u; m: d' ^+ Z4 L+ i9 d
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 f# s+ X I- Z1 ?( l
static void McASPI2SConfigure(void)
) Q! i8 p9 A3 Z{
4 o. P3 S, b% Y* N) t0 O/ {$ RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( C* n* r; h1 C9 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ B1 x$ k4 F1 V( JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 j% D, F f& _) Z% NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
F3 b1 y1 g1 w: G7 ]McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ J, y4 s; q' B2 q) R. G, HMCASP_RX_MODE_DMA);) B' f2 E# Y9 |/ Y4 I T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* V; W0 H7 j! v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& Y; _8 B7 o: c& O7 \3 q- [' cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: ~1 V% S% M. F2 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# F! a6 B2 V( z5 a, m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . c2 p5 b5 {; Q- t0 V7 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- \. G) G8 f6 W$ RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. y- w' j8 o: g/ k0 s3 NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ J" k' L' ?- F1 N& f. X( g# z9 ? }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" E3 F1 O6 L2 j. a3 J0x00, 0xFF); /* configure the clock for transmitter */
/ \" D$ U; K/ a" w. L" d2 A' s7 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& [& `0 |$ E% U. ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ A7 j1 l4 t/ Q/ yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 j/ m5 c3 Z! A6 Z1 y1 r$ L
0x00, 0xFF);
0 p4 ~' J5 N/ R. p; C% `* `5 j
/* Enable synchronization of RX and TX sections */
6 z" R' q7 V9 r7 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% E2 C. F8 M8 G2 I
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& ?, v0 F- n2 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* o" L) {1 d+ t' q7 S# Q' I# f8 Y** Set the serializers, Currently only one serializer is set as3 s5 a Z8 a/ W) T
** transmitter and one serializer as receiver.
g; C" T4 G/ X2 E4 v*/
$ K' I. v2 T9 c+ b E, vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% V2 y6 u( g" X, W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ X0 Q. v- X5 m: @" B+ d3 O** Configure the McASP pins
' W3 r" y2 ^1 V) D/ ^$ Y** Input - Frame Sync, Clock and Serializer Rx
& C1 I% T3 N# `! q# G9 t: q** Output - Serializer Tx is connected to the input of the codec
; A! i/ W+ ^7 ?- W5 A# ]/ e: g*/
/ @5 _% U- N- L$ A5 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& R: a1 N2 x4 y* zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); Q" h1 g, f+ Y& {( p) |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
L" t& }. B& G; O0 s| MCASP_PIN_ACLKX
, |0 b, y4 y& a4 J| MCASP_PIN_AHCLKX9 f" [% Y* @* p8 q0 ^% ~$ G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 P$ ~7 {7 f5 R: S% n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' q' j6 m, t4 x2 i A
| MCASP_TX_CLKFAIL : q( z2 G2 q" t4 @ h8 e
| MCASP_TX_SYNCERROR! Y7 G+ @- t2 a2 [) }4 D/ C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 h" H9 K1 l/ N# R; q$ N| MCASP_RX_CLKFAIL
2 B7 p8 S; Q: ]( i9 w5 [; w| MCASP_RX_SYNCERROR
8 Q6 u8 {2 H: @1 ?% o7 i| MCASP_RX_OVERRUN); {) q/ U* T. n& K5 v4 p1 l# @( P) ^/ v
} static void I2SDataTxRxActivate(void)8 j. }' h5 Y0 v4 ? V
{
/ N0 {/ _! E3 i3 v' _/* Start the clocks */4 [4 X( |& x0 {9 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. z8 n/ q# k+ V* T/ y: N( ?! ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' k( L/ `% W Z. N; Y' I8 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, y# H: U- s* p, R1 T( g+ |1 y
EDMA3_TRIG_MODE_EVENT);
/ R" ^7 b' m7 N+ N4 EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 G1 Q8 a5 W" O6 ~' T/ O$ bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 I2 c) K; d% iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ S1 P" L: c8 Q* N) d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& y3 w, f0 c6 f, I6 s5 t+ lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ k# E. B; ]- Z) R1 u6 ?# |$ O5 c6 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, W) K/ e4 `1 W5 }+ p4 }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 V9 S2 l% h! t& y/ W: }# u8 Z* F: C}
% b, N. f3 S+ o0 e5 ?. z/ O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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