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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, J5 z1 Q9 ?3 ]6 I% _
input mcasp_ahclkx,& @: U5 g2 W% r* K# d
input mcasp_aclkx,. S { ]' t6 X- x) {: D
input axr0,% y& b! J, \/ }
" ^; l2 H/ Z2 Y: d* q$ u
output mcasp_afsr,4 A/ \2 P$ t# K4 Y
output mcasp_ahclkr,
4 j9 m- n8 r, eoutput mcasp_aclkr,$ ^+ \% U8 v @: O+ M
output axr1,2 h: D) f1 S) X$ H2 R1 s) a1 p
assign mcasp_afsr = mcasp_afsx;8 v, x6 i. W& C7 x
assign mcasp_aclkr = mcasp_aclkx;
& D. M4 U8 v/ m2 ]! K$ a# cassign mcasp_ahclkr = mcasp_ahclkx;3 o) c( o( p' J+ V3 \/ z# }
assign axr1 = axr0; + d x3 }( B# g+ k
0 [2 R1 V+ I q; ~2 x: o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* Y- R' I# e: r6 R' u/ Qstatic void McASPI2SConfigure(void)1 X1 z" e* k; w
{
7 _ q X) ?. j$ V' R0 nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; r/ {9 b# H( y" ?# {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 P/ \, o; r1 E9 T3 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( U+ S4 ^3 q5 P, M" EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 C9 R1 H3 F7 z2 YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ]# G; C3 P5 ?0 P6 S3 fMCASP_RX_MODE_DMA); b* |4 G+ c) M$ o" A3 k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& U/ [2 j9 k; ` G! SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 I/ A8 }& ?. G B( I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) X( X$ r; g$ M) c. P1 L. l9 W
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 v' \+ N+ U* Z8 L( d" L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- Y% q% Z* D0 K( VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% I0 u- q' k$ x& Z# R$ Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 `0 \* y& D6 P& Y5 Q+ [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 I0 ? r+ [6 J2 O6 P" e; w" f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 H3 b; y& q* T) w, k6 B1 u
0x00, 0xFF); /* configure the clock for transmitter */
; `6 M: [5 o- E s8 r! Z9 vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 N7 ^2 v* G5 e- q6 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" R7 `1 C" v0 _4 Y" @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& g: n4 l, N; W1 ~& z8 e5 P
0x00, 0xFF);7 I; s; z C' s, v8 q* J
3 s7 \( e5 I8 z) I
/* Enable synchronization of RX and TX sections */
& w `- n8 B4 Y1 D6 {& W# zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 |: o9 m) T0 B8 {6 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" S8 B V( `0 s" k3 ^. @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 U0 c! ^* Y, i9 F
** Set the serializers, Currently only one serializer is set as
# j: O& u% q+ P- Z0 W8 E, r** transmitter and one serializer as receiver. L- H0 J- R% S, X/ ~6 _+ ^
*/* S3 d; Q6 F7 m" t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 W+ l: L7 T2 |5 l8 F s- T' \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( w0 B0 [+ N9 p: ^* G( B- L** Configure the McASP pins / ~1 B i& ~$ g+ g
** Input - Frame Sync, Clock and Serializer Rx
( d7 h+ V, }$ j** Output - Serializer Tx is connected to the input of the codec [/ i! b; R& W4 a( g! c
*/
; J6 p# W/ j rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); h1 k$ U: Q$ J6 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 Y$ S& G) O' l' v! _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 H+ f; V5 O5 j) Z1 e| MCASP_PIN_ACLKX
5 K! g6 [+ b, \" R; T1 E7 j| MCASP_PIN_AHCLKX
" Y6 W+ D0 o4 B8 O2 X/ A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* O& r3 v q: ]+ v5 ?9 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% R; w+ I! i% H8 X% D8 K| MCASP_TX_CLKFAIL
; Z9 \- z( r' G| MCASP_TX_SYNCERROR* e. G4 H2 X9 U5 t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * u, l" z- o" Q& C! E3 p
| MCASP_RX_CLKFAIL' i# p. J# }0 f I, J/ L
| MCASP_RX_SYNCERROR # d8 r9 f+ {2 @
| MCASP_RX_OVERRUN);7 N% E; t! N- Y8 C$ @' f' O
} static void I2SDataTxRxActivate(void)1 Z/ H: W" I5 j4 X0 w5 V- R
{
& B( M5 u. Z4 Z' ~' U+ t1 |/* Start the clocks */( l; L) X! n1 T2 A1 J- W; z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 {7 L3 O3 \- X3 Q$ e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' j: T* W: b5 H% N. r3 [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# T$ ~ U1 r6 m- JEDMA3_TRIG_MODE_EVENT);
% n6 P, e) M* v; f/ k, a- wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, E% V: Z) N" i @; a0 j* n8 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ }% d( `% ?8 S- A, M" S0 ]
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 p& v, S* d, `/ L) ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 Y) K6 g! b0 }$ zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ `" E1 r: O! ~; f% o; [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- ^7 D% n9 t6 D5 P* T& D k9 K8 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ m" w& s5 S# Y5 @2 I c} * v6 i, k1 C5 J+ n/ s$ w; P) g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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