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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% h, \: B' W/ P6 x* k, Rinput mcasp_ahclkx,5 s' ^. d7 y) ^; P: j% j
input mcasp_aclkx,5 ]6 n2 |1 x0 {( O' n1 @
input axr0,4 K& U' a5 `) s
+ Z! H4 x, S7 |9 N7 h
output mcasp_afsr,
( P# T. p" m @5 youtput mcasp_ahclkr,
2 h o* |: H% M' m) Ioutput mcasp_aclkr,
3 {- r) f" B+ j0 h; {) \- qoutput axr1,7 Y! O W, v9 i! f2 T
assign mcasp_afsr = mcasp_afsx;
" `1 H; Y1 P- ~$ fassign mcasp_aclkr = mcasp_aclkx;
& B7 {; J, [* ^! a7 a3 q, lassign mcasp_ahclkr = mcasp_ahclkx;
# x# ?+ c! c( T; {3 massign axr1 = axr0; ' E5 ^) k& I, {4 u5 K8 O- H
: j% @( W! b$ o4 p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 * g/ D+ U, v5 P% U9 E
static void McASPI2SConfigure(void)
3 n( L+ v2 y4 N- }7 J6 ^( I% z4 L7 B2 r: ^{
( [4 t$ L( ~7 C# \$ R2 @McASPRxReset(SOC_MCASP_0_CTRL_REGS);( S- O! }8 Z+ b* f0 l( b- [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 s; O# W% \4 b9 dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" [. ^5 c" Q% }. N$ f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" U* X' h1 R" p* v$ _- a# Z7 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ u) G! l* T o# TMCASP_RX_MODE_DMA);
0 G1 L( t: F, FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ L6 b ~7 Q- z% O& w, G- dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% e+ F. s. u5 i4 r( E" TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' {* {! O5 I: O, t8 O
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* ~" ^4 E5 `. \$ N$ v3 W2 tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / R$ \+ F ?' D' a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 }- U3 W- E% b- d f# p6 {9 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% ~, z8 J5 d# n1 s6 e# bMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + ~" p- X% z c5 q" ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
n/ R9 g, o* [; A" O( _* @0x00, 0xFF); /* configure the clock for transmitter */
9 t* j/ v% O/ GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ t* P" S: ]2 o2 xMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . d& q& s7 L9 C9 j- L; V. C
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 g" w& G x% z9 |1 P
0x00, 0xFF);6 Q) o) ?& Z1 P) P1 W# c
% J% G% G Q2 Y8 S0 v. h
/* Enable synchronization of RX and TX sections */
* U9 I. A( B3 y9 J {4 H- h+ k# z3 _ gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 j) [: v, S. F) c4 ^% I/ }9 X( C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 ~7 m) Y& [9 {& V6 b6 H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 {* @$ |$ o! G& N: B# f
** Set the serializers, Currently only one serializer is set as
) L& E* W( _3 O' s; {& J1 F! v& {** transmitter and one serializer as receiver.( F, x" e8 ` X
*/
8 W+ F: G5 Z% b" o+ ~9 _7 I# oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! p+ f, c Y' gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) M1 j5 p1 N. ~3 i) B0 J5 u: t6 d) s8 T** Configure the McASP pins
6 m T, b! J8 i" k) I** Input - Frame Sync, Clock and Serializer Rx/ T% h: W# C0 ]4 ]- ^$ a
** Output - Serializer Tx is connected to the input of the codec % H5 u: K; a7 Q1 {" E& c
*/% g, h0 }5 o! [: U2 V- {4 ?" {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 z- N/ O1 |7 F4 `- n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- u4 ~8 C. f) p, _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, k+ n7 u' P7 V) ?- o$ Y. M) l
| MCASP_PIN_ACLKX9 F1 F. Z. z& _. b
| MCASP_PIN_AHCLKX
( ]" i) I& |' [$ a# B4 _/ S- S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! r5 `6 u+ b; e! r- H& UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) |9 h1 ~% ?) `$ R, @/ _/ i
| MCASP_TX_CLKFAIL
' y, W1 {9 x- r1 ?: y1 G| MCASP_TX_SYNCERROR
& }1 p" k; ^0 r% L+ M f" Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # w, X3 Y) g8 f2 t4 _6 f$ I c
| MCASP_RX_CLKFAIL# T" C( K( a4 E4 Z4 G) R) ~ n
| MCASP_RX_SYNCERROR
# o# l0 B3 |$ P- ~| MCASP_RX_OVERRUN);
( R: c; l, M: ^( j} static void I2SDataTxRxActivate(void). o. y% q' @. o
{. \, e% I4 R- r* ^: {
/* Start the clocks */
1 @ Y; K5 f0 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- D, I, y' h* g/ G! U! l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* G. ?+ F j7 p: L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," e9 k0 V9 k. i+ o8 |
EDMA3_TRIG_MODE_EVENT);4 e1 u: b A. Z' n! h/ |2 O6 d: N6 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 F% W: R* j) ^6 }$ oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& |9 a* n/ i0 i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 h/ p: i! V. c/ c' M. DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ ?( P0 b( K3 jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 d: p6 n5 r. E, S2 z, JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 y$ A$ o* o1 u8 i5 y" i4 }+ t- B* O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! L; w3 N8 \ R% i+ w
}
* O9 @: \- S& R) P* z' I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , J. J1 ^( R- s
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