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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 C" g' N: Y9 o- x, n0 Finput mcasp_ahclkx,
$ E+ T+ ]/ T, ]2 `' Iinput mcasp_aclkx,( [8 X1 }: ]* g' S% d8 K
input axr0,
1 W0 P3 r% `* a$ O7 \ V: E/ N4 M' e# Y
output mcasp_afsr,$ ~5 _! [1 k1 T: y$ _! V
output mcasp_ahclkr,0 e- R" `- o! K
output mcasp_aclkr,8 g, ]+ Y' e |4 w; F1 Z* d" }# f
output axr1,
& J! s& g1 S7 ~/ g3 |% m assign mcasp_afsr = mcasp_afsx;0 A7 J6 e7 Z7 H5 V8 `: V
assign mcasp_aclkr = mcasp_aclkx;
/ W. q9 H9 y3 D. R, Oassign mcasp_ahclkr = mcasp_ahclkx;
' i& N5 O; K" ]3 B2 N2 Qassign axr1 = axr0; 3 i! s |8 C1 X$ S6 i9 |/ C
$ _2 o3 S. X$ A( H6 s7 t; i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - N4 D( J1 n3 D7 _6 d4 f1 H
static void McASPI2SConfigure(void)
6 z5 Y& F( o% c3 T& a4 i4 E7 y( ]{) b8 F- r( ?) A1 f# {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);# X. Q8 O/ C1 |* ]& t4 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; c0 l! D# {. E, E, c7 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
?6 h. |1 W ?' pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- H, a. m7 e9 r% }6 M& ~* T4 w) YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 Q: v. N$ v( s* }8 B1 j7 sMCASP_RX_MODE_DMA);
& ^1 r( d" c9 o3 }( C* I% sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- P) l, Q1 a. A# N) x( S- Q3 z! k$ oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 T0 F$ f! r k N2 V$ qMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 \8 e( k+ r; m6 h3 \5 v1 p" G7 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 L8 Q" S5 n) D0 U9 LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! R) N1 L( _5 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% h1 J# t0 S8 }( b6 A/ m: Q% T( MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( R: G$ y' y$ Q7 \/ S! ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " o0 R3 V5 x$ G4 ]9 @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: P1 M! G( R9 T7 |; J0x00, 0xFF); /* configure the clock for transmitter */
7 a5 F& S5 p, w9 X$ z; P* OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 Z4 s' m w$ tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 ^0 q& T+ ? Q# g/ f$ U a9 J
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," ?& q% u7 Z( `0 t/ G
0x00, 0xFF);
# l5 U H' j, I
/ u' h9 m, N- q/* Enable synchronization of RX and TX sections */ ]. T" D1 N$ D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 f+ O$ n! E! F+ ]9 [& i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 |0 g5 e% x9 y, L/ ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' E4 e* K# q3 s( ^
** Set the serializers, Currently only one serializer is set as
# J3 j' r5 l) X" |9 P) @6 h** transmitter and one serializer as receiver.
- s7 y/ B5 C) S8 |; X- w*/
; o$ g5 n, w, n2 tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# X g% |5 |! j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* R6 g9 J1 t, g+ B/ W
** Configure the McASP pins
/ c. f; m; V* [5 ^** Input - Frame Sync, Clock and Serializer Rx, B6 h5 c4 J& k9 _
** Output - Serializer Tx is connected to the input of the codec
) U" r$ @( _$ F- V1 M G D*/
( ]" R9 N/ F. v0 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ x& Y) T. G) ^) F; E5 H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& t6 Q* i6 N6 N0 @) |1 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 V6 ~( q) E3 c u6 e| MCASP_PIN_ACLKX
2 [6 L5 v, O q1 h$ ]. @ q| MCASP_PIN_AHCLKX
; }" w0 |( v2 q6 Z% p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 G' o4 R2 \4 N3 x5 Y t5 {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! E+ S. l" S. k6 b# O| MCASP_TX_CLKFAIL
$ e: [' D' D4 @) Z$ ?) Q| MCASP_TX_SYNCERROR
4 u) D! [$ M3 f9 u) ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : U9 O' m7 ]. q$ P5 V9 i0 X5 b# s
| MCASP_RX_CLKFAIL
" C/ u1 [5 K/ c. [; e| MCASP_RX_SYNCERROR
/ W8 B* u" P1 K# S| MCASP_RX_OVERRUN);+ o1 a9 o i0 [/ Y# t$ {# v
} static void I2SDataTxRxActivate(void)
0 m, x' Z: x3 N{" l( ^; T, Y( q, s
/* Start the clocks */
9 k0 `9 p$ O* j2 B$ OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 t, M7 Q: b& Y- o4 v4 }! |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// U" m. z, S' @/ r% o& M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 S1 _0 L7 H, D1 [3 c, I! y
EDMA3_TRIG_MODE_EVENT); P1 v! Y; Q; c6 K# }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , L9 ]! k9 C8 D: C7 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( G3 I) b& Q# C! |! W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 |, n, r( m6 q) y7 ]- |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 Z$ ]3 F' z: e+ m) y( z0 ]
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) Q, E, {6 U0 R/ U( O, m6 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- N$ e1 j6 j7 |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# U: v W1 z% o/ M u) }. o5 S
} $ [+ N% y) E( C( X! j4 R( J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 \ j- K3 v8 |9 h$ c% ?
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