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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# J* Q/ M% n* r9 o U! X
input mcasp_ahclkx,- u% G+ X0 f" Q
input mcasp_aclkx,
2 r( \: F L6 U O9 I; K7 q* V5 |$ ^input axr0,
+ }. e+ k9 T4 _: w0 l2 l
- o, x6 |! x5 }output mcasp_afsr,* g' n' Y$ v; f8 P
output mcasp_ahclkr,) j; j. L& c+ E- c
output mcasp_aclkr,
# x- L" D- e9 x0 U7 toutput axr1, J; |7 D% `7 W6 a
assign mcasp_afsr = mcasp_afsx;7 U2 u8 Z- J8 _5 t8 p
assign mcasp_aclkr = mcasp_aclkx;' [' p# A9 e( ?$ u8 C
assign mcasp_ahclkr = mcasp_ahclkx;
# r) e+ M. ?/ bassign axr1 = axr0; ; s% P ?& z1 h7 x
$ d4 {' r C4 p! {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 x: e3 r5 f9 \2 ^7 d1 p
static void McASPI2SConfigure(void)% H. b( _7 M& k, }+ M/ R/ y
{
; t+ V/ l3 T' Q' y# WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 V" |* ^0 T* H2 M8 R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 H9 O* E/ M% w' F0 b$ ]8 N# v; i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* l) {+ `7 q7 F! ], k% vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& D2 E( t. W' L3 k+ U8 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," ]0 l& W8 z; c# }2 s
MCASP_RX_MODE_DMA);
! `% e* x7 y2 l6 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 C1 q% X- L5 E2 M L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ ~( T9 f( `3 j' p( Z$ _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; S3 A( Z- n: |& CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 N% c9 w, y. v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' a8 }& Z- M2 o( e& ^) p3 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 H3 j" ]) H7 Q; R) j; DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) o. P( D' C4 V! B9 ] f. K9 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); u6 ?& r+ B1 G* ?; C% @2 p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 E0 ~5 V) x0 I0x00, 0xFF); /* configure the clock for transmitter */
' Q2 j: n7 C4 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- Q0 G1 e( l2 Z6 B0 O, KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 }. a8 [4 ^( M: @: U+ z) u5 D! N5 F
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- m% M! w/ M8 \, v7 w
0x00, 0xFF);0 c, j3 t2 G6 v* M3 \
8 [2 f, w' ?+ ]' J6 h/* Enable synchronization of RX and TX sections */
8 b( Z$ k/ n8 D0 s" Q1 x- t0 F, FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. R& S X% M$ ?, l3 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 W5 X+ s: Q, w2 xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" l7 O3 t' d: z! E b
** Set the serializers, Currently only one serializer is set as% [( B) N" I( F4 O
** transmitter and one serializer as receiver.
) s! `) V$ a2 w8 f$ P/ v*/
2 s v) G8 ^# U3 bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ Q# U+ D% f; o8 tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 d4 X e2 n- N6 R
** Configure the McASP pins 0 X" q. T7 v, _7 b9 o9 U' e
** Input - Frame Sync, Clock and Serializer Rx
- ~( s0 k, N: w* p9 `( D** Output - Serializer Tx is connected to the input of the codec
+ n* B- i& C' v4 Y/ H* U8 b*/" R5 ^- L" f$ w1 i. T' a2 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! h- u) {$ a( X6 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 M" ?8 r' u, V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" p4 g1 c4 X0 S6 x7 o| MCASP_PIN_ACLKX \1 x7 h; H$ ~: h" }
| MCASP_PIN_AHCLKX
& y; n, ^! T6 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) ]$ w" k. Z. DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ^: n4 w& c, K6 d; x! p
| MCASP_TX_CLKFAIL ; z+ F) M9 q+ P( r
| MCASP_TX_SYNCERROR
/ ^8 x- n6 G" I9 J6 |1 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# F2 h( k* t# f! S: o- {: \& V3 P| MCASP_RX_CLKFAIL
4 U) A& _8 {. U. B| MCASP_RX_SYNCERROR
r4 k: ?$ O i; m' b" W| MCASP_RX_OVERRUN);
8 b6 `' S6 d& ~+ x7 G} static void I2SDataTxRxActivate(void)
1 [6 A J) B/ T$ [{4 P& {# Y( j3 I. q) i
/* Start the clocks */- i0 ~+ t" b4 s% X4 J7 g5 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& s% G1 r2 v2 x7 T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& @% q' k2 I, w5 D; l n, ^( |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& u D4 ?* ^. F# ^( n4 V( h. _7 nEDMA3_TRIG_MODE_EVENT);+ r- l) l* N# x( a- a" l0 ~4 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! z" _! ]& ^) l, o4 _2 e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& z7 C% T8 Z, t* K! a, GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ J/ d$ ]9 R( nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 t1 ^6 J4 M, r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! k! S1 Q, F! f, w9 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 C9 F' O" P% w8 Z( h# }% }9 Q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 c$ O5 M2 |) O3 t1 X" B
}
. {; C. d+ X) o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . O9 Q- i6 ]4 v1 `! J
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