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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ `" I3 O2 p4 {# R+ ~input mcasp_ahclkx,
6 A8 V4 I7 |$ winput mcasp_aclkx,1 a; A3 \" L, D3 h; g& H5 s5 R" @
input axr0,* Q1 a4 }% ^) {( F L" z# F
, V7 B& t. I4 g9 I7 A/ poutput mcasp_afsr,
5 Y5 r0 S) c& V$ p/ t1 Y- Joutput mcasp_ahclkr,
/ v' q V1 \# \; Voutput mcasp_aclkr,6 q4 a: T" j& M. x) D9 j- b
output axr1,
2 ?3 P+ D+ N% C' o( Z assign mcasp_afsr = mcasp_afsx;4 D7 e: N8 J' j4 Q
assign mcasp_aclkr = mcasp_aclkx;
# x: Q: c0 A+ D1 M7 V$ P8 f1 _assign mcasp_ahclkr = mcasp_ahclkx;" a( ~: l2 j: }! E! L! {
assign axr1 = axr0; 9 A% j1 C2 H2 @7 y! G T, d$ ]
- L, y* ]9 i3 |+ f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / P$ W e) C6 L% t" j. D4 ?4 X
static void McASPI2SConfigure(void)* ]! i% X3 y( K. ^+ C# {- z! q
{) Q6 E+ I6 A# b. J$ r3 I; X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 U- @4 w7 ]2 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: _# ~, ^! S5 S8 F8 X
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 j6 U2 f* M' R5 N: {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; v9 V/ P6 b$ r* q2 P) g& O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. n/ l4 x/ w- W& Y: [% y
MCASP_RX_MODE_DMA);; l0 h# ^$ q+ o# N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 z- i Q9 p, u: A" r8 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ H6 `& E4 ^" M3 p0 h8 k. T- xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + Y% w+ W: B, l3 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 w* l' g$ o8 V$ P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 b/ q& |( k6 O, j0 v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 J; _! F: C4 |6 `0 K* U9 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 Y" S; n8 o" n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % z9 i9 G2 f; u! r3 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 O" i5 {9 D D' P0x00, 0xFF); /* configure the clock for transmitter */
; ]5 b7 _0 m U& {" |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" N9 S9 M. o' B8 [+ B4 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 J( N" g9 N, F2 d% ?$ B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 Y2 _8 W& K6 l! K1 U3 \6 k7 y- }0x00, 0xFF);
# B- w% Q0 ^& x5 w0 R5 x. E
( n e9 F! b$ b" V" S/* Enable synchronization of RX and TX sections */
2 c$ O) g2 V5 ^6 g6 K) d6 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 M+ Q8 f( x3 r8 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( n$ v( d/ G) T* B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% h: e" F* b$ ^
** Set the serializers, Currently only one serializer is set as8 J' Y" ` A8 E
** transmitter and one serializer as receiver.& O/ j! c# H- h6 K
*/
. m* {9 c9 _. O* M+ U$ cMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 f1 m6 v1 x% n) R# w: GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* W+ w, y C1 N# x9 H5 k; s2 T** Configure the McASP pins
0 V0 j: x9 p# {5 Q7 h** Input - Frame Sync, Clock and Serializer Rx# ]) A6 d: q6 ]. S
** Output - Serializer Tx is connected to the input of the codec
; T: O# M* _6 n*/
$ ^) D$ C2 p! n1 l+ t5 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 L: F x5 `" w' R8 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* W: k: U, G; QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( d8 ?+ H0 m! n$ p4 g6 v k| MCASP_PIN_ACLKX
( h' S: ~( C. v| MCASP_PIN_AHCLKX8 n: k5 L- c% u; w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* [+ t& _0 B! n. P% g9 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
P7 b+ f4 ?5 v5 `| MCASP_TX_CLKFAIL 9 W' ^ [% a2 r$ l2 k& j6 j* o
| MCASP_TX_SYNCERROR
# F3 W/ Z+ U/ m& Q% t7 R0 b1 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 r# [) G2 ?; N5 m| MCASP_RX_CLKFAIL
* h/ O) ]1 R" ~. l( ` l( || MCASP_RX_SYNCERROR
- Z5 T6 w) ^6 J* p- a2 c- _| MCASP_RX_OVERRUN);- N- |8 |, ^% d4 w$ p4 I! Y
} static void I2SDataTxRxActivate(void)
1 k5 g4 m0 \! I' @ u) i{2 z; V0 M6 X% N- [& d
/* Start the clocks */
7 T& h# k" Y1 H: c- RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( m4 |8 S$ @/ S, _: W! ^% a% E0 S3 D' [, tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; W2 I% F- W& L; X3 X- r; \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ x, c1 n+ C h8 Q0 o* _3 E
EDMA3_TRIG_MODE_EVENT);' f; l! @; r0 ?) z' [6 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; h0 x. |# `( H. eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& ~+ i5 }) \- K# Y- d/ v6 m# h
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 c3 j. k( S5 d8 N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 d( e9 [0 a- L+ U' dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* ]- y7 K- ?5 ]% `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 V0 M! h: L' W# c5 i3 {, ]( M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, u t3 U3 |6 X1 d7 ~! C} ! h& U, f. p; T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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