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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ ]9 @ W# B, D, ]( i
input mcasp_ahclkx,& i9 W# v. i, p+ t2 H4 \1 i0 y7 i: @
input mcasp_aclkx,9 \0 E7 S, c5 o8 D
input axr0,
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8 N5 @- q, r `8 Y+ Y4 ?3 b! D. youtput mcasp_afsr,6 O! N7 M3 F# l8 k4 L$ e
output mcasp_ahclkr,
( ]( p) f" t/ C# soutput mcasp_aclkr,: |3 B! B) a* U$ P4 a$ e
output axr1,, F' _# [( S8 u6 g4 D2 _% L0 q
assign mcasp_afsr = mcasp_afsx;
3 `% K/ Z! g5 o0 Gassign mcasp_aclkr = mcasp_aclkx;
$ i( c, \4 C! d' g4 kassign mcasp_ahclkr = mcasp_ahclkx;& V" Y' L) v3 r# M9 R/ N
assign axr1 = axr0; 9 l) d9 y$ I& k' {
% y% x; M+ i6 a0 p `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 {" a! O' ?% A% Gstatic void McASPI2SConfigure(void)1 _! S# H7 f- i3 {/ [
{- j, C% J6 S: B$ s# v w0 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' S3 \( I1 Y3 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' u' H5 W0 \ r: I* e& ^, ^! cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( t) ~0 z; I8 N1 E7 o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 T4 a. A1 Y5 @( k* r/ r1 o' e: [2 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; r% h/ d8 W# y& I* ]+ t5 `MCASP_RX_MODE_DMA);
2 o: z/ s. i) Y: F! q. K* t; XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" T* q0 j! H* D# G; p0 ]% KMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ~% y8 `3 X8 P: t" u# ?/ k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 Y$ U# b: h& E% @( a+ P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% t; H, F$ Z3 V4 Q, a1 x! _- p& I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - c: Z0 E* s+ p- t1 r4 e: |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ ]) f* g0 m, N# V" Z4 y$ ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, A1 N. Y: l+ G4 E; Q( u0 J. VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, H w4 ~/ ?8 [$ z9 n1 \( pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) T) y% Z+ _9 b
0x00, 0xFF); /* configure the clock for transmitter */
/ a8 z/ v' ~. g1 A- ]" H5 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ Y5 `# K" [) i" Z: lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); }3 c. |) c/ ~3 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ a) x$ Z+ Q5 T+ n; L- |0x00, 0xFF);% }1 d) J) | o% k0 f
: @3 h/ H. w/ X6 `$ m/* Enable synchronization of RX and TX sections */ - a g5 z* B8 T# j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 z- v. ?" o9 ]; X# h* n: K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 ]/ z$ A2 `: w7 c( t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 ^: r2 b5 w) z. s4 b** Set the serializers, Currently only one serializer is set as U) n6 Y8 W6 q5 K
** transmitter and one serializer as receiver.
/ _' a9 B/ r9 k$ H+ q9 Q*/
: _3 N& B7 C3 l' ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 o' ^6 e; r; m7 k2 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 ~% `) A% M) c3 n) o9 s
** Configure the McASP pins
, w1 R+ A9 z8 z' \' c** Input - Frame Sync, Clock and Serializer Rx
3 F2 b$ F& j! k2 G** Output - Serializer Tx is connected to the input of the codec
' n' j! _4 C# w E; D7 I*/
5 ^' m( E. o; {* _: FMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) X1 m2 l' j/ d+ _6 q& |9 F* K
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) W, Z, I7 c2 C( Z7 P7 T& \- d/ nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" S2 ? g8 q; s* ~2 r$ a# q# Z
| MCASP_PIN_ACLKX
( S4 ?; K0 o/ }| MCASP_PIN_AHCLKX
! d! k/ n# q. Z' w$ D, i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 C! m6 N2 W0 m0 c! O/ P3 }McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 H8 U \$ d" e1 Y8 S! Y8 h0 t
| MCASP_TX_CLKFAIL
0 }4 g9 [+ ~* }" h7 t5 v| MCASP_TX_SYNCERROR7 [) X! U6 v: ~5 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 G" [# e/ ?' s# q7 F! Z. X, Y* w! x| MCASP_RX_CLKFAIL
( Q: {( K7 Y! u8 h4 {8 i0 y| MCASP_RX_SYNCERROR
1 ~" S; i m0 Z| MCASP_RX_OVERRUN);* Y" H0 o( `& G1 c) N/ ^
} static void I2SDataTxRxActivate(void). C9 o' z- [! \% ]: O; ]/ i- }
{
: T. Z( ?# I3 g: e# G* f/* Start the clocks */' c; a# R1 a4 N! w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 S! ]5 ~; C" m3 I. J, y$ c9 r5 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# g5 n) n9 M. C6 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' G4 x/ R( c7 }
EDMA3_TRIG_MODE_EVENT);
7 B+ r0 X: l6 W" mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 {3 f% Q( |- QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 S+ [; s1 K ^! |. g* ]0 i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. b U: K' K# A0 R! Z0 }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 M- z$ `/ ?' a" ?: W' X- w% ]% q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& }$ q# z: Y u$ k) VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ F$ X& D1 u' f% p7 xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 d5 C9 |8 b0 z& V" W
}
. _. T: J* k j9 A" I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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