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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ C6 U) w+ C9 v
input mcasp_ahclkx,% I$ p$ o% l9 r- z" G
input mcasp_aclkx,
' n+ k4 X6 k7 tinput axr0,1 a' Q6 ^7 y; |! m+ g2 ?7 C
, x3 J1 Q. u! L9 N
output mcasp_afsr,+ b, r; x- {* [4 L! ~
output mcasp_ahclkr,
: L5 p; e" L! h/ j! k- }output mcasp_aclkr,+ O/ d. C, O7 l) T( ~' a
output axr1,, O4 U7 H4 e( C* O! h/ J. ]
assign mcasp_afsr = mcasp_afsx;& h% V. o0 j; C
assign mcasp_aclkr = mcasp_aclkx;! J2 d0 ~2 V2 i: @% H; k$ T
assign mcasp_ahclkr = mcasp_ahclkx;
8 `. e' f3 Q$ A8 B3 Cassign axr1 = axr0;
% A* e5 \& ?6 c( S1 C9 f/ Z& q: l5 n/ [0 @) a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 Z' v) B: b7 M5 u& z, c: @; G, R
static void McASPI2SConfigure(void)
" c0 U+ I0 b( i& C- i7 s b2 s: S{# o; L' n4 z' X+ e7 q5 c- d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ J) s. K3 a9 a2 [$ XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
L$ G9 n6 K, V( \! jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* k" c6 T3 R7 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 c% P0 X1 D. o0 P9 T2 `5 r, |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," w; V1 l, U. D& ]
MCASP_RX_MODE_DMA);
# L6 c' ?' p' ?* t) wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 |( p: b3 u3 @7 K$ D! x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( U" a, ?8 y1 h1 V! a6 t- fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 `2 P+ J" L( K, B$ b+ L# M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 L2 m' Y$ C1 s; Z, y: H/ VMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 |8 r" ^8 |* p0 l) ^) `4 ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- L& [' d8 y$ Z. r: [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 g- O& u+ y! V/ T4 H7 D( wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; d1 v9 N0 M% DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% H& R, N4 O- D5 E/ l
0x00, 0xFF); /* configure the clock for transmitter */) [2 M; ?) Y/ O! l; H. X1 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- _5 {. S1 |; w1 K6 N, U X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : P3 _( L7 }: p H2 {! j1 T
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 D. R% z3 a' q; P+ n% C
0x00, 0xFF);- Z( d! @ g# |0 y$ d+ f
- w6 h6 c! j/ S, f" s# i
/* Enable synchronization of RX and TX sections */
: g0 z# D! } g2 t5 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 T4 S) E+ k* @6 b4 `8 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# u# x$ m9 d1 K9 F8 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 E5 b& G3 G) z5 L/ p** Set the serializers, Currently only one serializer is set as
: [" e' c+ |; f' r** transmitter and one serializer as receiver. K( K$ N! ~# C9 u
*/
0 \- C9 c( `4 |* O4 _2 p3 hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- V4 {( G0 N5 F {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' K. { B F# S0 a
** Configure the McASP pins 4 N9 h3 O! \1 W2 Z7 T
** Input - Frame Sync, Clock and Serializer Rx1 m, I$ h. z0 Z/ X$ P
** Output - Serializer Tx is connected to the input of the codec ) i, y' J7 P+ B6 M$ M( R
*/6 J: o9 \, R3 [& N6 S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 @) k+ ~) a; H: ]8 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# r, s$ R! t# H5 f5 _3 M% mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 ?3 b6 T4 d5 ~) t$ `| MCASP_PIN_ACLKX
1 x6 i1 j) K& l) o1 i# {| MCASP_PIN_AHCLKX( x* V: ^ Q6 j* e# d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 E; I9 }2 K8 z7 w3 L5 HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : ~( X0 S, f- v, n3 [ P
| MCASP_TX_CLKFAIL 1 S0 W! `# ^, ^7 ~2 ~& h0 U
| MCASP_TX_SYNCERROR
! V, U! W; Q# N# `. C4 V) u- z) t5 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ V2 |1 i0 x# N( K7 E' E| MCASP_RX_CLKFAIL
( d# c5 @/ \( p6 q. m. ]: S: C| MCASP_RX_SYNCERROR , \/ T% M4 [2 A( \: i* g, B
| MCASP_RX_OVERRUN);
$ a% `( u- Q% F& S4 Z0 l& N' u# F2 X& d} static void I2SDataTxRxActivate(void)5 h' }8 c" G5 t* V: b1 ?, h% y
{5 T: {. ]; ^% h: ^3 N8 e5 k* i
/* Start the clocks */ [) w4 }! G4 f) {8 I4 G4 U Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* i: n- l0 Z6 i7 l5 U( ]8 U# MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// l2 z! o: [0 [( W. G- w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 l/ c( E- c! H$ D3 {: n) r2 N/ ?
EDMA3_TRIG_MODE_EVENT);
( n e! @+ j1 j9 r9 r" k4 y" kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) c! ~+ e; x! |+ `4 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 h4 _' G+ E9 V) j# iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, Z8 Z& ~0 f9 g P! \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* z1 g5 C6 a3 z" V! l* `$ D; E/ Twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 V/ o+ D& d+ V8 ?' k2 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 _3 P8 g, ~; E' |! J1 t0 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 {9 \, ~8 `, C" C6 m% x
}
6 H- p, U$ y* O' d0 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 @% w; m' C6 u6 q2 Y( G
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