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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! ~& b* P4 J8 l+ k1 A6 ainput mcasp_ahclkx,
" L3 Y( w+ y0 x( ginput mcasp_aclkx,2 ~9 \ x& x6 j: m* D
input axr0,4 m `0 Q- T: h) o* h" }
# s( m3 I; \. B4 o" W# `output mcasp_afsr,
7 L0 i) H2 ]+ J1 a. r7 V0 m" Z9 woutput mcasp_ahclkr,
& K' O5 y! L7 w. Aoutput mcasp_aclkr,
% A8 z l# `) K; H; _- G3 ~) Zoutput axr1,. Y+ B' s' F+ r. d! v; z( B6 o
assign mcasp_afsr = mcasp_afsx;8 a- q# _) E8 w7 ]7 Z7 K
assign mcasp_aclkr = mcasp_aclkx;
1 {# h9 A5 ]' z+ M- W* g/ D/ uassign mcasp_ahclkr = mcasp_ahclkx;
f! x: z0 X8 U D8 Rassign axr1 = axr0;
& X( Q* {8 o0 N! q0 d' T4 s1 T2 k1 L1 M6 ~& G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- l+ W' _8 [& kstatic void McASPI2SConfigure(void)6 r: E/ A9 u* Q) s6 J. i
{
- ~2 P; k1 x5 {) W6 n/ XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 K4 a% ~, G; e- o* T" @5 J& aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 p. T3 h& P1 E& f# m8 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 X( \2 E8 t9 h: GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ m) d8 l, I# g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- {1 k* @- n" U( H
MCASP_RX_MODE_DMA);
; f9 g5 X; l; Y6 Y. yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 h! h2 D0 \4 |( q8 l: U: `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) E* l0 q! Y" N% W0 d& @, WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . J q4 k; D% W" M. [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: L3 u* k0 u9 ]- uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 V& R& Q( { w gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# n% m3 u) K0 O2 j$ Q% d+ @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ ^0 H; L. B5 ^, b: {3 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( D) b) t5 t1 d7 t8 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" g! i; K; n; N; G0 x& Y9 ~; l0x00, 0xFF); /* configure the clock for transmitter */! R: F. w0 q( l8 C# [% r: z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' }" z3 D1 n1 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ C# ~* K& U" V" p& SMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, |/ q) ?- H& }* j p# [- @
0x00, 0xFF);
6 q1 I2 h5 b+ d" R: {
8 Z5 y( t3 K1 L# b, [/* Enable synchronization of RX and TX sections */ 0 C, U6 ^7 k' N: r" M, q, k9 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 p: a, x# h4 W5 v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
D% j7 I% q- CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 f0 Z: z0 t$ x1 |** Set the serializers, Currently only one serializer is set as
; r) P- A* D; Q$ \- N& b! X% d$ V** transmitter and one serializer as receiver.
: C$ { [& c) G5 y/ ~*/
t; b9 `, F! e/ l% sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ b/ i2 d7 c ] `0 P! t) ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 i1 K |. o* B
** Configure the McASP pins
! g( s$ q$ R5 M5 K' u1 \** Input - Frame Sync, Clock and Serializer Rx
% _- g d. M. l. _ A** Output - Serializer Tx is connected to the input of the codec 9 Z6 J J* M1 h7 u$ t
*/# A0 \0 m% x& k/ T, j" o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% g& G: M0 |% l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 Q4 r( D9 g9 B) }, V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ k1 e# i5 `: u% @| MCASP_PIN_ACLKX
- c1 `( Z. A* g& p7 B- L' Y: j7 d| MCASP_PIN_AHCLKX
# x. @- k2 N+ A6 K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// Y3 Q+ W- I5 L7 U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& Z1 u' @4 J+ Y, X$ C- x4 f| MCASP_TX_CLKFAIL ; p; B* K1 d# O5 ?3 P( W. R& e
| MCASP_TX_SYNCERROR6 X8 @- K8 J0 K( u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 n6 ~% Y e t/ t/ u6 C& f0 O| MCASP_RX_CLKFAIL
& h z( w/ l9 g5 V| MCASP_RX_SYNCERROR
4 b' Z4 x; t4 M: e! b/ h3 D| MCASP_RX_OVERRUN);+ }/ @4 e( m$ j C& g! j5 ?+ n# n2 _7 r3 g
} static void I2SDataTxRxActivate(void)5 r0 ^" P/ g$ I$ X) E" P
{, \ s; S6 ]1 p7 j0 a
/* Start the clocks */
/ ?, j# _& w7 _8 c- wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 {. H) y3 u" M/ B1 R. h$ a4 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 E: v4 l$ r, [6 @2 D' |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 }# h6 J8 M, J6 Z. JEDMA3_TRIG_MODE_EVENT);0 ` l4 j5 f6 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; z4 n" L( c! I( ~9 _! B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( [% D$ z( d3 d) s: n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 M. l7 ~4 }# q R, k, \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 u d* F8 l" p* M. f
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* a3 i7 |; O2 ?+ m1 E ~7 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; B4 \7 {% V$ W* }3 q r7 f$ \& i9 u8 f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 Z! }1 Y3 _% I4 J: y: J} 8 C- y- Y3 X/ w- L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
+ x6 J: P5 Y! a1 t |