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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% ~# o+ \1 q, Y- N1 u
input mcasp_ahclkx,
, ]. Y3 F' l- F& r. p0 w% O3 e& I/ [input mcasp_aclkx,
9 _$ D6 P3 e) T* F9 q- einput axr0," G u8 i9 M! A7 n
9 Z- W, a o4 R/ G6 ], {4 Toutput mcasp_afsr,, L- C1 a3 e# S2 O% ~
output mcasp_ahclkr,
' f0 v. `; w( m" D/ @output mcasp_aclkr,6 e% P# d) y9 H+ J+ W. d! ]
output axr1,
( z. } R, N2 K. q- g) A1 l: K assign mcasp_afsr = mcasp_afsx;
4 y8 I+ N2 t% @+ i* V1 nassign mcasp_aclkr = mcasp_aclkx;
& o" O4 n: i; A l- f+ c9 Q% fassign mcasp_ahclkr = mcasp_ahclkx;/ Y9 I8 u+ N8 C+ N6 h! ~
assign axr1 = axr0;
5 A: \$ ^: Q- d6 k# j' f: K
8 J8 }* t& K3 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 u y" }% D! F; R# W ?+ Istatic void McASPI2SConfigure(void)
2 R+ I! r& ~, d{ S8 a) E. Y) K3 E2 D! A8 K6 S* v0 S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: o; ~7 v7 s( ]. \. C2 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ `' c2 o, I! \% S' j1 G% \4 B4 LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, Z* Y' y. r/ d0 g* S7 G, r
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, s2 l( p6 H2 {0 S) c, B0 n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& J, T1 T) H6 \* d3 n H! {5 w2 [
MCASP_RX_MODE_DMA);/ J' S: r% o, p# e P" ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 E' B( K% |$ V! R0 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 X8 R( \5 Z a4 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' W2 C/ a5 K0 W8 q; ^$ j/ d' p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" ]( o4 R& I7 X8 u' a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . w9 j7 S, \* |4 ?4 V& V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 b, o& q& u1 {5 S' r: p* X, k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" N. Z5 X$ Z3 E) Z- v# h3 m# J- N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , ^) [/ w' ?3 B% G) U# R# P1 m1 Z# B1 P* |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: R: ^ ~9 t9 E- ?5 m, n* ^
0x00, 0xFF); /* configure the clock for transmitter */
1 I6 Q3 v& f8 y" s4 ~- H( x$ C( AMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. S- h/ }. Y" I/ i. ?1 r; i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 K$ {& \* L8 ], ]; z/ AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* }5 p' b" U! C# O$ w! d- W( t: e$ {
0x00, 0xFF);
! Q& }0 a, [2 r L, _! l* U* H2 ]( K5 d$ f
/* Enable synchronization of RX and TX sections */ ! }* u6 ^+ Y2 ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- |: f( D% E$ i* E. A" d4 lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ u6 `4 A! c/ H* ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 a0 f& y' V8 U
** Set the serializers, Currently only one serializer is set as' r$ z) R1 j+ K6 x
** transmitter and one serializer as receiver.( P* Q2 g2 X7 |
*/" T" b6 W/ V, ^/ J: ]( K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 C6 M: y2 y R2 u- O/ O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 G1 [- |1 N& n' v" Z% Q5 ~5 V5 B0 Q** Configure the McASP pins ! d( [" i; V; c( _9 s6 B. d
** Input - Frame Sync, Clock and Serializer Rx5 N7 R! j6 i$ L. x. l
** Output - Serializer Tx is connected to the input of the codec 7 B0 V0 x6 o; T2 o; \
*/2 l$ z0 _" f: T0 J Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 C- ^' w4 y3 f0 T; A" P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 q$ O6 U7 W/ L* |. L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- l) Q' _6 g6 h+ j8 R| MCASP_PIN_ACLKX
4 r% Y; B+ i& f: d& C( ^! Z; E6 ~- r| MCASP_PIN_AHCLKX. A Q' A( @; W: I. Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 F! S0 `) X7 z% g" Z( oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; i' ?# i- L0 E
| MCASP_TX_CLKFAIL
3 N) r$ B7 W6 q- V3 [| MCASP_TX_SYNCERROR0 t+ Z& [( m; j) B$ j5 k/ u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! o, ]# V- f7 V' l
| MCASP_RX_CLKFAIL
6 D* Z) Y. Y( N8 k4 j2 X: y| MCASP_RX_SYNCERROR
/ s6 Y! F- Q: g) V, \| MCASP_RX_OVERRUN);$ L+ b/ d6 J9 E* x6 L" P
} static void I2SDataTxRxActivate(void)
; u. b W) N7 D/ M{# {) d! L, }$ V" N5 h
/* Start the clocks */) o0 P& W3 |* V. D& q$ H! N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! \# x, k" j/ r) X3 M0 o3 z+ e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ t9 z) O' T+ s$ [( OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, |" t) m& m& v& M3 @
EDMA3_TRIG_MODE_EVENT);& K/ C H4 |4 ?% d1 L* z8 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & S; W. w" \( S0 c8 d; d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ h) \! y6 e( e- G; ~% I2 t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 \. f+ U+ H7 q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( p$ _& ~: `9 j- e! q0 O, Fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- y" N6 s! ?2 G# f+ h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); A0 n1 y- w2 _$ d$ ], ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 A3 H7 h1 N0 H R" Z1 f
}
6 O2 P {+ K8 |; [+ A8 M; X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 r* }& s6 v7 P o) O6 M1 ^ G. N+ q W- b
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