MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
' L3 i1 R9 W9 O' Pinput mcasp_ahclkx,
input mcasp_aclkx,
( r5 ~0 a( @$ m' B( M4 }input axr0,

+ l" A: }0 \$ M& K  qoutput mcasp_afsr,
output mcasp_ahclkr,
5 ], X9 @: l. a9 D$ |output mcasp_aclkr,
output axr1,
) H$ c: R- D# l. `- O

assign mcasp_afsr = mcasp_afsx;
- }% o7 \5 Q# k/ Passign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

' u3 y6 B+ i" ^4 ^. I- G
* \* Q6 z# y! Z( Z0 h

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

! L+ w3 V" ^  b; \

static void McASPI2SConfigure(void)
{
' q( O: D0 _% I; _1 A; J$ @McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* j3 H" S! y; [McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
+ R. o0 t4 P/ oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
  x2 J. X4 t" u9 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# U( N1 ?# B9 LMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 A5 o5 l2 O8 k5 y' A1 c8 E4 _+ Z: LMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* P5 p) @9 A% F/ n  i9 S7 w- C. oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, _' L" Y8 n0 J8 e3 }1 A. J4 |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ U1 w* i) i" |2 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" y" T0 {, ^) p3 S. l8 A7 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
( B4 A' }7 q* r, g) X( L9 K' o6 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. C; z9 u& b# ~# rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 b/ H/ S8 v! g9 x* aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% A) ?; M) I& G2 M0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, k& K2 }5 |$ O# \/ YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! `8 ?" l7 Q) p: {! s2 r8 A1 x! Q& aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
4 g. T6 f5 _: `5 d% f& F$ g! [6 u/ _! a
/* Enable synchronization of RX and TX sections */
2 j) v, y6 k1 }: C4 f$ L9 i* gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 E; x6 B  R. x" ~3 h6 C3 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
- H, u1 ~- l+ k9 T* d** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
; W! \7 [. Q' k: Y% K2 e" a** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
/ _8 s% v9 I8 u  F# x| MCASP_TX_SYNCERROR
4 z8 M: _: w& P% V- g8 x- L( A8 Q0 Q| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 @0 d% s/ `6 @* N; w+ y| MCASP_RX_CLKFAIL
6 n7 i6 q3 r! @$ h2 l: X$ V6 o+ T| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
0 a  d# M1 P  @{
" S0 Y: t# N, {4 ~/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 `# b2 v2 \* J% p$ N  cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ~6 M! P1 m4 ^8 ]$ s$ d& o/ uEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
( @* q+ g8 S: T5 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
0 j; v* A" k9 D/ M" Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' I) \, }8 u' h3 l: ^" I4 h& QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.