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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' H8 x3 Z- ?, i: N
input mcasp_ahclkx,
, _3 O7 n9 m9 R* \# Q6 j8 |input mcasp_aclkx,' Y& Y! g/ W( K5 l
input axr0,
) ? W2 w; Z1 ^4 _8 A2 r7 f5 Q" i' @, }8 S, o0 h' }4 i o! r
output mcasp_afsr,6 O/ l5 ~6 P- R
output mcasp_ahclkr,
2 ^; r3 y: K3 Doutput mcasp_aclkr,% m1 P: p& m- w" D7 |8 ?
output axr1, |; L0 }3 i* f; O/ ?; K) N& M
assign mcasp_afsr = mcasp_afsx;3 H/ L+ I J3 \/ b5 v- l, g
assign mcasp_aclkr = mcasp_aclkx;9 Z! S0 A. f* h8 x6 W. W0 T
assign mcasp_ahclkr = mcasp_ahclkx;
" y/ v7 z1 D0 C! Y6 l/ O Y2 s( Vassign axr1 = axr0;
. N& B. H; u! P+ g% n. z7 [5 ?0 W: y7 E9 a% g3 C7 j0 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 i0 w# G* \' Z6 I# b, \$ b* G
static void McASPI2SConfigure(void)! D5 o7 ?2 M D3 x* ?
{
! w D/ W, P7 d k, x9 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 f" K3 S# y: F# B j e O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" V' i, I( @2 k) O; Z5 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% j6 W0 u+ Q! {, ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' \+ A$ S. ?8 A- \4 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," f, l. ]: }. X% {0 [' z
MCASP_RX_MODE_DMA);
~8 h% W2 S4 _+ X* {; ]McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* @8 L0 t% R( a- ?5 e- w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ W9 ~7 H" F* l4 ~1 C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - a/ f3 |) X" K( |1 N9 C1 ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 t* w: A3 y' M8 i" T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 d4 G1 H! _/ {: \ KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. v' `) m1 S" o# n* qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ L( M% I2 L2 h# O. o3 _" A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " g0 q$ g$ s; A' |# L+ I2 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ R$ h& `1 s$ q3 i0 t( C
0x00, 0xFF); /* configure the clock for transmitter */
8 N" M% G l: r0 c( g- Y; G. W1 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. \! \( U! g* v: n4 E2 g% [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 s: [$ a' |8 y. G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ {! j! z& d% j* H8 m' K: j8 H
0x00, 0xFF);4 H. }! w2 s/ h- k+ f5 ~
0 B1 |% D, M. T' f6 S$ c% I/* Enable synchronization of RX and TX sections */
/ [4 J7 G! A, L6 ^5 D5 N! QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, k3 A+ z% D: W& b$ _. J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ ^$ ?$ K$ U6 i. P& ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 F2 H6 S* K, k** Set the serializers, Currently only one serializer is set as/ t! m8 E6 j6 `
** transmitter and one serializer as receiver., i0 v7 Y- c. ^* U" P
*/4 [6 G; J* u+ V' A0 r$ t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 W1 S, I% G4 t1 a+ H$ P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 k l4 W3 X* g
** Configure the McASP pins " B/ U& k+ ?+ I. H, b$ j7 H4 h
** Input - Frame Sync, Clock and Serializer Rx
6 o% |( d0 a/ B) C1 o** Output - Serializer Tx is connected to the input of the codec ; W( v. ?+ w2 J0 }
*/
( y$ S) o4 H: \: z6 [/ ]: d" K$ c3 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; ]- n& A& V1 e8 F5 R. m7 w( \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 \, J7 Z+ D4 ~; T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& L" M; \5 `) K| MCASP_PIN_ACLKX& F0 y: x& \5 q9 ]
| MCASP_PIN_AHCLKX
4 o/ W) H6 M0 H! k1 W1 U3 B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 }3 I: U; e! J7 u( A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . s0 q/ l9 D% G4 M: D; g
| MCASP_TX_CLKFAIL ! O( `3 j0 x3 @& G. ? a' [/ T* r
| MCASP_TX_SYNCERROR
* u9 A+ }+ p% k! T7 Y# m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: }* R: p4 z" p| MCASP_RX_CLKFAIL
, r Z0 w9 {- [: e; W| MCASP_RX_SYNCERROR
3 d, \; O# l0 e: B. d% p| MCASP_RX_OVERRUN);
, b" ~ {7 m, v} static void I2SDataTxRxActivate(void)
8 O7 c8 G$ ?. o- o{
# @1 s" B: ]' b+ Z/ j/* Start the clocks */
% r- X" j( N+ H, p! eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 Z0 Q' ^/ R QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# g6 Y& G# m4 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* e& f+ s, E* w: Q' p
EDMA3_TRIG_MODE_EVENT);
2 g& ]( l4 B. {) BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 Q# K: V% o# ~, i7 vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: W: Y; x J% i* dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% h2 G5 r! `" K- e* u0 p! u' cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( R" I6 |" `; ~; Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; p% N) l+ e$ x! @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 p4 ^1 N- t+ n( BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 r) t+ P3 \) l
}
4 N, e9 j5 V- D& L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 f# j# j2 e/ k5 _3 ]/ Z$ B
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