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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' Z [" s3 p% ]7 |1 P
input mcasp_ahclkx,+ g: d% P$ l1 w, ]+ m
input mcasp_aclkx,
. l+ ]0 O! X, p& ^$ {5 F( [ M: t0 ?input axr0,
4 K4 t) q( W" \3 H) j7 x
& A' L, x' R6 R- I" a5 Moutput mcasp_afsr,
: B) g4 y% j2 E$ h. F" Qoutput mcasp_ahclkr,1 z9 Z$ B. W1 S# l: z! D/ e
output mcasp_aclkr,) Q9 D3 X: w6 O/ t: ], N6 {
output axr1,
+ ^. l7 {" @2 g1 ` assign mcasp_afsr = mcasp_afsx;% g j0 E" y M& X% J# m
assign mcasp_aclkr = mcasp_aclkx;! V( N. g0 Z. Q- P5 o
assign mcasp_ahclkr = mcasp_ahclkx;
5 p5 i- l7 O+ e1 nassign axr1 = axr0; 9 Q! Q5 v/ O% @, J* J: g6 a
% M f" w9 r- R, |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 D9 L/ U e5 {9 I: \- a% Estatic void McASPI2SConfigure(void)! @7 \' ^3 g+ A& x D( r2 h# ]* ~
{! K) K( p" b: U1 Y% T, F/ b. n# B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ \' H1 Z& |; K0 W% D; }0 {' t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! |: k& G3 I9 C, mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 k5 Q( G+ R4 y" d
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// B# C _4 Q' n/ `. J6 M6 \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( P V" e6 q b8 e: h; e
MCASP_RX_MODE_DMA);. L8 x& k* j+ ~" C/ E! J( _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* b$ k0 {6 l" W0 m2 G7 u: C m; u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 N" I: {( `9 m3 W8 {1 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 {$ m, M, z. a: I1 ~
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 N1 ` S! L SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 r( [8 o% O( d- rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% R6 z3 s; h7 ^- B D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& j, k3 N5 W& a# M% _McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ W* s" Z' \" Y, M) XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ P) L8 \; o* ] K" b- n4 s: r
0x00, 0xFF); /* configure the clock for transmitter */
; `# `. t; T7 d$ KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 `4 F/ K$ E0 V4 JMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 Y1 D* a" g7 G0 A A6 L0 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 u7 w6 C5 R2 t K& n, Z
0x00, 0xFF);
/ D" ?+ c+ ~5 n4 j. w9 l. r6 o* @6 p
: M+ B$ z0 P: [7 c! q% u' Z/* Enable synchronization of RX and TX sections */ $ {- E* x% l1 q+ P5 o1 n; A( u/ E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 I3 ^* C+ D! `# p8 R( z- AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" g: y- ]+ W! _$ h. o& `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 {6 P3 `/ v6 _
** Set the serializers, Currently only one serializer is set as. M4 j& h+ E1 C0 Q9 L4 [
** transmitter and one serializer as receiver.
# j; L* l+ ~$ ?5 b% v*/
* b; n1 D" s; Q* |! CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 z) ]# P" p0 e' l, EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
?/ d1 U, L: C% |$ H7 h** Configure the McASP pins
8 n" g% o" ~' d4 l! ~. {** Input - Frame Sync, Clock and Serializer Rx
0 ]7 S! S7 ^. D' W- A2 u6 [( K** Output - Serializer Tx is connected to the input of the codec 2 u' S1 z( ^5 x3 `
*/
+ M6 k j# `3 J' i8 b4 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 u. e7 Z' u/ n7 u2 yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# ?; C) M' A8 q! L% `4 o( D! PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. L, j7 D# P6 ~) s. _
| MCASP_PIN_ACLKX
' F: v" ~$ H" q- y7 C| MCASP_PIN_AHCLKX
# c8 b/ n5 l: Z: F) u3 h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' X. w# h$ P0 F5 W1 b+ L' z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. g1 C' x4 x A. l2 L0 @| MCASP_TX_CLKFAIL
% p* D8 B; g- s* L! [( ]| MCASP_TX_SYNCERROR
, O1 w% J/ E' M+ O: r, e+ j/ M| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 x* m9 A6 v- O9 ~( r) B% W5 h- t- J| MCASP_RX_CLKFAIL; C" Z7 \ U& {, l
| MCASP_RX_SYNCERROR
& o, p5 n3 ]: w% k% g| MCASP_RX_OVERRUN);
2 h$ i7 A1 `1 t! a1 T} static void I2SDataTxRxActivate(void)$ \' _4 x0 j8 I/ B* @& X8 b
{1 |9 Q# ^1 T2 B" u( M
/* Start the clocks */4 E1 ^2 C& y1 Q3 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) B& e0 K/ @+ d% e ^3 |1 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( W T% a9 j6 L6 X$ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ]' ?# C7 I1 N& J1 G, u9 OEDMA3_TRIG_MODE_EVENT);' n6 [. L: h: H) J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 O4 b% v: \! n V/ r4 |
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 z( ?& @/ l/ O- Y" T9 D2 \4 `6 E( i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 s7 J o4 v; J% K* ]8 HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 n$ W! ]1 G' O4 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 Y7 n& v7 J* CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& p* _# w! K4 {& A. s1 e) f* I! \1 bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 m( j% y0 d* C/ n# @
}
& b% K0 C8 {7 K! i5 v0 A K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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