|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ ^9 j$ _4 o4 U& ?
input mcasp_ahclkx,
* m, @& D" g. T% U( rinput mcasp_aclkx," i5 [0 k+ L) X' D% P3 U2 p
input axr0,0 t, t1 X% k4 G" a6 E1 p' x
* I1 v) b& l2 L6 v, i" J% m+ houtput mcasp_afsr,' d) H$ u: i5 M. K0 s
output mcasp_ahclkr,
6 t y: o/ r9 D- N( b9 foutput mcasp_aclkr,8 u) t8 \; m( R& ^1 K% L* r3 f0 U
output axr1,+ U9 j6 O5 D% u- J: c {
assign mcasp_afsr = mcasp_afsx;+ V& f" D9 u" G& m6 Q; }
assign mcasp_aclkr = mcasp_aclkx;' K- J" e5 I6 P u; f9 }! a! D
assign mcasp_ahclkr = mcasp_ahclkx;/ m8 p- P' G% a1 a( p
assign axr1 = axr0;
7 j. u$ {% ~ O ?( W+ n
w: o& c7 h7 V- y* a `" Q( C; h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 R9 {" H) R: r. |0 U0 Rstatic void McASPI2SConfigure(void)
( {' z' o" R ] U. m* t5 P{
& J }. u, c8 N$ vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: m& {' }' G7 i1 \8 y0 A9 h: S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% s. c4 F: j' W+ t4 B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 p2 j3 j- d4 x' x$ m1 vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ i$ m7 b* d. w- J5 x6 ]; Z! ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ y/ _; [' X- |MCASP_RX_MODE_DMA);
+ x' l; w& v9 t; v& T2 V- FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 o8 K# i% P0 ]' jMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 I* h# o. [! Y" K' pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 j# Q6 ^' Z% r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 \3 ^7 ]9 ^* \, B# CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # R3 ~% g( E7 ]+ g! l' C; `8 X0 K3 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. G7 F3 }! E/ m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. C6 J; k# s. e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # a" ]5 Y1 B& E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 t9 N i9 n" _+ |
0x00, 0xFF); /* configure the clock for transmitter */6 z. {% F% A& R* X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: g+ r) J7 c; ~: z/ q+ VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & a: o! J* A8 }' p- N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) `/ |% k( b& a8 x0 I
0x00, 0xFF);
R ~. E* v+ U+ o& @ G$ s5 A8 t" Q9 ^
/* Enable synchronization of RX and TX sections */ q/ u e. D: e2 Z8 V3 N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* ?, ~; o [0 S1 f( LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% w3 q3 |7 N! \% e7 N, z0 hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 d8 G1 G( Z0 S# E4 v' T* q** Set the serializers, Currently only one serializer is set as8 F* `1 z' k2 y( n! K j
** transmitter and one serializer as receiver.2 G8 f! e n, l- w: `) P" _
*/9 m& y$ \( [( F. A! U! e2 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" @ _/ o" V S2 Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ b( i' @( _$ o) ~7 e- V% c+ a* B8 ~** Configure the McASP pins
3 E* n) P m$ W' o** Input - Frame Sync, Clock and Serializer Rx* ^* P9 {0 s# S# r& o/ J
** Output - Serializer Tx is connected to the input of the codec
5 r* @. W( I& Q% J' P: K*/
c: c5 W' i, d; F& I4 t8 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ V- h7 p# N: h7 f9 e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
4 X% d# b0 @6 ?5 s% M; ], u' n5 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 _3 B) O9 q) d7 T2 T| MCASP_PIN_ACLKX( k1 z, p: p2 ~% i3 k
| MCASP_PIN_AHCLKX
9 z3 ] @8 y( x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 d; W+ P& M8 r0 d' oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 ]! ^6 `2 _6 S$ c) A5 ?
| MCASP_TX_CLKFAIL , ^' q9 D1 r$ Z, n( V* A8 _
| MCASP_TX_SYNCERROR' F5 k: {5 N9 C. ^- N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / ^6 [) t* Y3 E7 _) A
| MCASP_RX_CLKFAIL8 G% u! c: d- d7 k/ c' A/ S5 P
| MCASP_RX_SYNCERROR " N, |2 x5 @7 ^5 `% H
| MCASP_RX_OVERRUN);$ R( o- d% }6 y) Z
} static void I2SDataTxRxActivate(void)
6 v* T- R9 a" E2 P9 P7 x2 ^{. D1 t) q5 m" J& v
/* Start the clocks */( B5 [: V* \# A, t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Y4 b$ A; U. M* K1 ~' GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! E" _! P3 S1 G( o/ h- X( WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ Y( n, H$ g! P2 \EDMA3_TRIG_MODE_EVENT);
' t7 c# l9 O, w, N9 V% |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' A7 i8 _' d4 @1 D7 D* @! iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 m- u& _3 `; p. o1 _9 U" x5 {1 W, RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" A5 D W) v7 E) |6 f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 `' x) R, z0 Z5 W' B$ y0 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 T! T% C" @3 rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, w4 M8 ^+ j) l6 d! H0 P/ i+ z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ b8 E: e2 B# {9 l
}
q& s! m$ Q: H- @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 `" @# b: x% ^/ q: u9 Q |