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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' j3 X2 X( ~/ L
input mcasp_ahclkx,! R7 \! n6 f+ J9 R7 N. e
input mcasp_aclkx,9 ?# M5 a! \% A/ A
input axr0,# z9 i7 Y ~% ^% n* ^
! o1 A& Z* v, I! x( ?output mcasp_afsr,; }5 B+ ~8 m# S4 U
output mcasp_ahclkr,9 {9 C8 ? q& @/ B$ _
output mcasp_aclkr,
- T _- N1 V- K7 P8 p3 ^- u/ Joutput axr1,2 [3 T8 N* B9 t7 b+ N0 E
assign mcasp_afsr = mcasp_afsx;% r% R% Z5 D* p# a+ o
assign mcasp_aclkr = mcasp_aclkx;3 T4 ~! H5 k1 u& i5 b: O1 v
assign mcasp_ahclkr = mcasp_ahclkx;
; T3 v' z7 I# `% M' }: L# u2 vassign axr1 = axr0;
1 \! l# R7 ]" J7 }! _" W) P! K& Z: x4 a) B7 t- ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 i0 m" `: I3 fstatic void McASPI2SConfigure(void); M- j N3 v+ k6 J d
{6 N4 l; \! @6 t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" j- z, n$ w& S2 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 X! J" F B2 e D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 Q; L: i, R# K& b- t' J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) ^& m, M5 z( B* Y4 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ^) R" D$ q* {6 w1 Y- S ]MCASP_RX_MODE_DMA);
2 y$ s4 y" d$ e1 z' IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* A7 M7 C* _1 _& pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! }1 c0 a8 m& `, M! F0 Z+ q3 @; f4 ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " A8 M" Z2 O$ Z/ h ]- `. _0 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( |- s7 c" Z# Z" _+ [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 @* s& |6 k0 S yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. B+ z( J6 b$ P& Q, }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ x# u# u& u0 E' ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* D6 i; P% b! N; N3 RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," ~9 J) ?! [2 S# Q8 l9 n
0x00, 0xFF); /* configure the clock for transmitter */
9 F6 L% R A! s$ T6 ?& u1 k' U' s& [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. Z8 n: I+ x: s8 C9 {3 n- m! W; BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / n0 z- C1 W, M' y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 W; V3 y6 G' x) S& |- g3 Z
0x00, 0xFF);/ }; ~- N$ T8 N% b- p4 G
6 A: p; m4 i A9 b
/* Enable synchronization of RX and TX sections */
5 `, n0 |/ H' I2 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: t0 K% s+ j7 ?- I' NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 h5 t1 `/ q9 ]/ A$ F& ?6 H9 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 e4 L! C: f/ H( Q0 h7 T4 o# i5 l
** Set the serializers, Currently only one serializer is set as W: g$ H4 V2 J9 N i
** transmitter and one serializer as receiver.
3 F$ |' ?2 h" m, z8 V/ `*/; O& C7 l/ D2 v( _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 [& n" ^$ n* p5 K6 E9 Q- s/ d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 q5 Y: L R1 s6 S3 J
** Configure the McASP pins
. E8 X. c/ B# h6 h** Input - Frame Sync, Clock and Serializer Rx
# e+ O2 h' E( k' F** Output - Serializer Tx is connected to the input of the codec 3 M) ~! e7 O5 n9 S: j5 D
*/
4 Z. v/ M: b2 J: D: IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); ]) h0 Q. R* ^" p4 o. k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: @* e, N, O) C$ V; v b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 K$ S, ?9 y$ ?3 N1 {
| MCASP_PIN_ACLKX
) g5 q' W; t0 `| MCASP_PIN_AHCLKX- v$ j$ @0 w' f# j* |1 e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* [0 i3 G2 z* @" ^) MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 L# m) @6 ?( o' L/ a. [) K
| MCASP_TX_CLKFAIL 5 M9 V5 {+ P! q
| MCASP_TX_SYNCERROR
% E- _7 p, z" V; M& b7 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) y% p' x: F* ~" i% S: l. g1 w( R| MCASP_RX_CLKFAIL
' n( L) X$ l; S, q; O% l, M| MCASP_RX_SYNCERROR 5 H7 I& }# K& b7 ~& L" u6 L/ n
| MCASP_RX_OVERRUN);, c; `' _1 I: g- c: j$ L6 n
} static void I2SDataTxRxActivate(void)( [! O) H' s5 K% K
{
* X9 V5 n4 J) K& b: r/* Start the clocks */5 i6 ~) P' j. b. B6 A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 S, Q- c4 I( S& z0 o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 x7 ~0 s, O) H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 R) k: C4 f) R- REDMA3_TRIG_MODE_EVENT);! H# a) }( y9 F$ Y4 U% U% W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; Y: c1 _! b3 s- }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 c' b3 w2 T/ k) l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* S0 f/ m4 }. m. f+ Q. W# W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 A" U( A7 {9 mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( l# n6 p! |- O" l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! A O% q/ T5 N4 V i. b$ k. aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);* n# f# C2 Y/ k Z. } P
} 9 z/ A7 Q# s X+ }) t- ]& N5 g, c3 n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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