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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 d: q5 ]! P& d
input mcasp_ahclkx,( o. h( M* \: t8 [- @1 r% ]
input mcasp_aclkx,
2 G3 j- r$ i6 u% Z( y# A Kinput axr0,
% h3 K+ p9 p, @3 O- u; H% i) P' [9 [; L8 E
output mcasp_afsr,
$ P3 }7 Y1 S, H$ N3 {# H7 voutput mcasp_ahclkr,# e, M \/ E& J$ V
output mcasp_aclkr,/ i: n7 z( G0 V+ M" O
output axr1,3 z+ E" j3 n& @& X" l, r: `/ M! E
assign mcasp_afsr = mcasp_afsx;
) @# P) _* x" \. Bassign mcasp_aclkr = mcasp_aclkx;
! c6 h' p; w" l# Y8 t7 F! V! Gassign mcasp_ahclkr = mcasp_ahclkx;
. h D$ K) D, I; G' ?assign axr1 = axr0;
6 {9 v0 ^' G1 J/ J
2 s' h" a5 W# E! z2 H( G7 d' M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) T7 c# b. B$ ~" o3 }+ }( Hstatic void McASPI2SConfigure(void): L) y* F7 J* X, E4 J# [4 h
{
# I* K* i5 a/ s# g8 j6 }, bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; a1 @( X9 Q2 E8 W; n! ~4 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- i/ n$ Z5 ?% K* x+ YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) c/ `& H! y+ i1 u, X0 c1 S+ SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ y3 c! D2 j) h, y/ I- x* ~" T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& L# A, A( s* p" {8 c9 s
MCASP_RX_MODE_DMA);5 u$ J2 O$ t. N* f! Z" |" }3 e
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! V" q& F/ y6 _: k' T6 l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& O' U' Z! U" [& S3 G) Z- vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " s3 {8 \, ]/ U6 }$ Q) R) c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 u: A! U$ G! t; GMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' Q+ V& x' W: F, GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# A0 o9 ]% N/ G- \/ l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ [! X8 k/ X/ n- E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & J$ g8 D$ [( D0 x' \
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* p" T: _2 R! k' d: W9 ~
0x00, 0xFF); /* configure the clock for transmitter */( M, Z3 b2 g& y, ]3 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) g0 C. Z$ D1 d- v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 |1 u( i: n3 m! |; x$ m; K7 ?% T0 [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; P; C9 \" {, M
0x00, 0xFF);
3 Y% _! Q# H9 H
' I/ d- J! M4 n; u& \0 @) N$ F! _/* Enable synchronization of RX and TX sections */ . D; [ s; a) Y- c4 I9 a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( I% ?% c) ]" D3 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 v: F8 j' w8 j/ \! @1 Y' X& E6 AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( s: `8 ]) c+ j: Y( F, o# x** Set the serializers, Currently only one serializer is set as J) y7 i. k% U9 G8 `" U1 ~* [
** transmitter and one serializer as receiver.
2 _, O! I$ o5 A3 _: l* Y*/1 ?8 {( k1 d% q/ x# P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 B' D- @# B; ? bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ `+ |+ e4 K: ^+ |** Configure the McASP pins
0 m- d) ~/ q+ k- C, L" m1 g** Input - Frame Sync, Clock and Serializer Rx
5 }/ ?/ a- c4 F, U9 A** Output - Serializer Tx is connected to the input of the codec $ _8 F* d3 q4 B. a
*/
0 Y5 y# H0 i5 n- E! MMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 ]: X" H, R4 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
H) e2 i5 I4 nMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- D3 a4 o+ O( }& K
| MCASP_PIN_ACLKX5 p0 V9 G4 `" z0 P! H9 d
| MCASP_PIN_AHCLKX% o1 H8 M+ e( d& @& J0 Z, @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) _7 h6 F) J( R
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 `' e% {7 Q# G| MCASP_TX_CLKFAIL
4 q! `8 k: A! d r| MCASP_TX_SYNCERROR
- x4 V3 [, f2 q# r6 x6 L( K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
Q% t2 n, `5 ]$ H% L3 t| MCASP_RX_CLKFAIL
* U) Y) Q S8 L| MCASP_RX_SYNCERROR * Y# K" T; Q6 ^' }1 ^( {
| MCASP_RX_OVERRUN);
" n2 }& O5 q9 W" c$ U. O5 G} static void I2SDataTxRxActivate(void)8 }. p& i, O8 S4 t, D
{1 ]: U( T+ ~) C' E# x3 M
/* Start the clocks */' h1 f) @ `+ `$ H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 x a3 D; M' {+ i' }McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ F7 u2 ?3 _9 }' C2 S5 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 y0 l' Q$ {$ A8 P V' }
EDMA3_TRIG_MODE_EVENT);: {3 g% E9 \. j. @: ?' u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - _+ N! W/ k) T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ ?7 v2 p; _' V' s% ^" d) W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ T% c+ P3 ]2 w% Z6 c* R K0 K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 o/ ?2 [# S/ @1 E, p/ ?9 @* _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; F# G% n" i% u# g- j( _ D" W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ n* P5 t% ^* t7 @7 \8 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 W% w* ?6 t8 {2 v# b. }* M} 0 r3 a. F1 k- a9 W8 \7 [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; N" `, l. b% g$ Z% L
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