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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, u9 ?# H/ o! q Vinput mcasp_ahclkx,
5 d$ Y- [6 {2 i* ~8 f$ t' cinput mcasp_aclkx,
8 w$ A/ I% j8 J) H. zinput axr0,
( }! F2 ]* f0 R( D* P8 y% O) V3 B" h3 u' t# m$ S" c; w, m. z8 e& e9 q8 Q
output mcasp_afsr,+ v( w$ Z; p& F0 d; @. I
output mcasp_ahclkr,
$ u1 F8 M# f5 ]" \% O" Coutput mcasp_aclkr,
* J2 G1 E, [% @( Z+ W* woutput axr1,4 G) d/ H7 E( L& c
assign mcasp_afsr = mcasp_afsx;% X: q4 b. f" Y) u% K" f* w
assign mcasp_aclkr = mcasp_aclkx;
4 I- O( q) p( H2 D( sassign mcasp_ahclkr = mcasp_ahclkx;
' b9 G% Q: S. W8 A! cassign axr1 = axr0; 3 m) z! p3 R+ B( {0 Q+ {5 \3 i
% C* t% T9 z' ]1 k% U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; v: ~2 r# W! e3 g! E* L% kstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! t0 ~. \6 y8 }9 x5 ]7 F: sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; g$ W- q. R/ dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 o+ P- c4 ? n1 Q$ hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 f$ o; t0 t3 {9 `% T+ c) }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; K$ a, y# Z! A: _! H- t) @2 O
MCASP_RX_MODE_DMA);
: c% Y. O* X; z* PMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
_( e; }, B7 o: p/ O, ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* Z6 R+ i* u2 D5 q. ?- H" @5 [# XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( X7 b8 F+ D- ^, Y, e/ tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 t9 }" z/ l/ G# [9 j2 [* N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ s1 J/ W' i9 o' |7 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% U3 g# r: w9 W3 d( ?- ?& p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ f/ H) O% {3 Z: X- B+ Y. ?/ q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 g0 L, ?7 N* K, b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 J7 S ^1 @3 ?. k$ W5 I" c2 X
0x00, 0xFF); /* configure the clock for transmitter */
9 A/ R: p, P4 Q! P. _. s: P3 UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 i7 ~+ _, e; wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / y g5 v% H. k! |; L* I* a* m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 e o# R4 r) J: o, d5 ]6 X6 h u0x00, 0xFF);
! O4 m& R& p: G. e% ^6 x# T
5 S) _- o! a- J2 f: B# Y/ u/* Enable synchronization of RX and TX sections */ - l! B+ g( t, G+ b- k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) T H5 V) l& w# v( R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# E3 w+ O0 h; [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; B. B$ q+ F- @1 ]7 ]** Set the serializers, Currently only one serializer is set as3 i# n7 B h+ J Q; l
** transmitter and one serializer as receiver.
2 M( Y; J0 k7 N% S$ y! m*/4 L& G) F6 O* s1 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# `' X# z% }. s1 J
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 a' m F8 h8 J8 O# H** Configure the McASP pins
/ d6 J% U5 g! Y# }4 U9 c** Input - Frame Sync, Clock and Serializer Rx
# P6 z3 M/ z6 N** Output - Serializer Tx is connected to the input of the codec
b0 M6 k+ N! v! D( F*/
* s" ^" o+ d( _, ]/ I/ I+ RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* L" ]/ h2 c2 {3 N5 y) J! p( Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" g9 W" s C- e. p0 k# V2 s0 O) DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. X4 `4 H' P7 g2 z9 m) L
| MCASP_PIN_ACLKX7 G& c+ J, Y+ ~. |
| MCASP_PIN_AHCLKX
1 G3 B4 a- } `& u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 x! C9 i$ t5 ^0 o6 |6 n/ QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' q3 \3 _! L+ v' [; ~$ \# R
| MCASP_TX_CLKFAIL 9 [& P( L& b5 B% e- r8 U4 F5 D4 x4 j
| MCASP_TX_SYNCERROR
! y7 h- m/ {6 }" |. }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 N0 B5 g z7 m! b6 V. g* W9 B| MCASP_RX_CLKFAIL' B* p+ ^ o! |- ^
| MCASP_RX_SYNCERROR : D' v- V2 M( A$ V
| MCASP_RX_OVERRUN); _6 |; U) u/ b5 R8 B9 ~
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */3 X( o* T5 I/ d8 Q$ b( l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 O6 b5 L1 D6 J4 N7 t8 QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// @2 O1 [2 T% i1 U8 L$ k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 G- P: W2 x* ]. D; k1 ^6 MEDMA3_TRIG_MODE_EVENT);6 k/ U# \6 m/ \7 g* z, A7 p& I! Y+ A& J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* g# J' Y# R0 [' i) s9 Q @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( L, G e$ s# P E v
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 U+ V2 s8 _* R; q i2 ]5 G1 M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; K; x) w. z: E$ zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 F5 u2 I/ Z# v) b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& I' d0 |) B" _# ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # W7 |5 J+ Z; v. n
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