MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
, o9 G: q' v7 M* @: g" }- pinput mcasp_ahclkx,
- I( ~9 T5 A+ O: uinput mcasp_aclkx,
. J$ d/ V0 Q, ~6 W, ainput axr0,

output mcasp_afsr,
# I: O/ K$ Z! Routput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
7 w# [0 S( e. y) |5 I; }

assign mcasp_afsr = mcasp_afsx;
& _: r, q) K' g: R1 ^assign mcasp_aclkr = mcasp_aclkx;
" T; S5 u1 z, d1 ?( }3 Kassign mcasp_ahclkr = mcasp_ahclkx;
! B& C2 b" K- I/ l+ @assign axr1 = axr0;

! a; m/ A. K! P4 c

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

( j4 {, U1 w+ ?

static void McASPI2SConfigure(void)
{
$ U9 j9 I) {( F" LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
, U( a. N0 y5 [- a, |' ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: z# g  ]7 p* JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
1 b; C/ B" Y6 J- A3 [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 |/ n  L+ F" ~1 @9 X! cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 @+ n+ Q: V9 _6 \9 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 V9 y3 b8 e4 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 I" e) ^/ J% i5 T: x- Q0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; F# }6 j: ^3 w! Z; Z; S& Y& s) C2 |0x00, 0xFF);
3 K6 I4 ~% A- ]# M2 b0 m& V
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" K% u- h9 {0 aMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
' l) i3 r8 H* B. g& \# h7 |** transmitter and one serializer as receiver.
8 J$ S7 T5 O0 `" N7 ?/ T*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
8 y, ~$ A3 s3 g*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 r% Z3 I/ X$ P. r" U4 n| MCASP_PIN_ACLKX
) p: `' U0 x+ |0 P# X| MCASP_PIN_AHCLKX
! W+ l: k, x; l. H  M- H! X! o  I| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
) r% E% x+ G! j! N| MCASP_TX_SYNCERROR
/ J9 @8 `( U$ N& {$ _( T| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( {, k( k$ A0 o| MCASP_RX_CLKFAIL
3 K5 \1 U: Q7 f! P0 y| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
' _3 [& c" w( e# j# [{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ U7 w2 F8 E% \% n" GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
5 M! ?- R6 s9 B8 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
* a- ~- j+ }  ~' D0 Z! E6 g- A* ]" \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
8 Q% b/ L" w, m+ aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# j' ?+ C0 J  p+ ?3 ]6 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
0 c) W$ S2 m0 N. m$ N5 h2 [4 Y8 kMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 s- ^6 I+ i# l: F7 o3 c; \% p}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

5 J, H5 d- t9 [/ C; a