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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( v$ D! p, |& }, }/ u8 i) Q! f
input mcasp_ahclkx,1 V9 l. N* w/ f; E7 T( o
input mcasp_aclkx,( ~. l* v A: x) C5 m+ t* x
input axr0,
6 c! G% n) _$ m/ y! \
2 g/ F1 k, d5 F/ \' z+ i& W* woutput mcasp_afsr,2 F7 j- z5 t8 x5 t
output mcasp_ahclkr,
& \1 ^7 v+ j6 r$ Q2 n( i5 Z {0 }output mcasp_aclkr,
) P1 n, A, |$ \" L* w: X/ Woutput axr1,
( e3 B% B1 y5 p4 V assign mcasp_afsr = mcasp_afsx;) G6 S8 M" g5 \! x* e
assign mcasp_aclkr = mcasp_aclkx;
7 @! U _- R7 oassign mcasp_ahclkr = mcasp_ahclkx;
% Q) A9 O0 c' x! r5 I% V' Y$ @assign axr1 = axr0;
& _. k1 ~1 ?8 B P& H3 z) @6 N1 q8 w/ X# V0 _+ a7 V! e: y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: M, _" `% E- }! G) I) U) ~1 f! P0 r- wstatic void McASPI2SConfigure(void)
/ z$ J4 R$ L. c{
; [7 w! r: n2 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS); l# F+ R# o. ?4 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. _# }, {4 ]9 D1 e# E5 }/ l5 kMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ O L: K# K O# a MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# r( Y9 L6 w9 PMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; q9 c# { K- Q! P4 DMCASP_RX_MODE_DMA);
) f9 E5 A! x! |' v4 KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 z& r% Z: R5 T5 X1 V! p! @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ ]% m1 M' l9 b* ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 p5 F5 e: K2 o6 \% B* XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ F' A: z' k4 L% r! `McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 T! R, V+ e2 ~- e& J! ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ^7 h( L+ ~6 `0 I1 q! g4 iMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 R$ J3 o) n1 u6 N& d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
p+ H! Y: H1 ~# D {$ pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" E9 L# }8 H8 S$ U: O" A3 S' O2 I0x00, 0xFF); /* configure the clock for transmitter */" t. @1 s7 B7 H, |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) J1 A% }) {, Y) b7 Q* v2 ]0 v) wMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, C8 G! b9 B6 M; Q, ]& T _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 U8 e2 n* G( U) w
0x00, 0xFF);
- Q; l5 n2 ?9 ~3 m, j2 E; O+ S& _; D) e- T
/* Enable synchronization of RX and TX sections */ # k [( r! }1 A) `. \% Z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 X1 V2 A) e! xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# c; O8 J5 {3 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 k& T0 G8 p9 e$ V" C4 z2 M** Set the serializers, Currently only one serializer is set as
7 `. E+ `* z `) I** transmitter and one serializer as receiver.
2 T0 m; _8 Y4 C# r' N9 E*/3 V4 A* {6 F- b; V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& V! |% f" V0 p" k" \, _: v. D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) Z/ I& l( ?+ x3 v" a1 {! H** Configure the McASP pins 5 `, I% A2 X' R2 V( ]
** Input - Frame Sync, Clock and Serializer Rx. x. l; u" P$ L. T
** Output - Serializer Tx is connected to the input of the codec
; F- J6 R2 Z* C8 B) A*/
; T6 f; r |" c" y+ E: TMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ R+ q) |) n, ~0 m( q* Q. w
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 X) J& B; ?2 b/ h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, B! E4 t' i' R8 j# Q) o! R- ]| MCASP_PIN_ACLKX
1 U# p$ [$ T; D$ w1 u| MCASP_PIN_AHCLKX, p5 J) D8 E! S# }, L3 n8 y1 f' i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 z; n2 R) |9 b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 Q' b% U n* D" o| MCASP_TX_CLKFAIL " y/ V* }0 s$ \6 `
| MCASP_TX_SYNCERROR5 M7 V+ G( o. Z) _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 q+ x8 _2 i7 f5 `4 N2 w4 O| MCASP_RX_CLKFAIL
, S3 x+ L# @; K% [* o' o" f| MCASP_RX_SYNCERROR
6 }: z. Z, U9 R ]5 Z0 p1 o: S| MCASP_RX_OVERRUN);
4 f2 o) ~! M$ \. P0 j} static void I2SDataTxRxActivate(void); i# G' `1 R& p# n4 x( C; E7 d
{$ K$ k; c3 Y3 u* K
/* Start the clocks */
- X4 T8 w+ K4 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 {9 o4 O f& q5 \4 z* GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 ?0 X: W {8 m. m3 I% o0 ?- W. N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, Z# j# R+ Y3 R7 X
EDMA3_TRIG_MODE_EVENT);5 ^& r7 ^& _/ o& S, W1 N% S, x% j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & Q6 X7 z3 J: X+ b6 ]" G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* m$ u- D! F. M5 e3 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% A9 c1 u% ]- b; X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
c7 C/ |! g; ~: U1 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ p- b/ e9 V/ R: e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; K( p, H- {. `1 X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 N8 q* }* l$ B}
/ T1 e1 v' a/ Y: Q1 M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 B" A5 w+ Q* K& s) U/ ^
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