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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 u2 [$ c- u8 A: y6 n: M
input mcasp_ahclkx,* @5 C h s; ^7 t3 r+ `' b
input mcasp_aclkx,
- P" G% ~5 D( E1 p; J% rinput axr0," V) [% L; L) Q
2 E5 O' N* _* a, y4 ~ z( C, Q7 o
output mcasp_afsr,& R+ k* v: g0 ~2 q
output mcasp_ahclkr,
+ Q/ j1 C1 y7 }$ youtput mcasp_aclkr,
" v+ D) s: d! q6 woutput axr1,
3 l& |" Z2 }, ?0 J m/ g assign mcasp_afsr = mcasp_afsx;# z7 C2 _" t0 \
assign mcasp_aclkr = mcasp_aclkx;
& U4 F7 A3 p' ?; R9 jassign mcasp_ahclkr = mcasp_ahclkx;
; B0 F% \1 l+ V% e2 Gassign axr1 = axr0; + k# b, t* W% g4 [2 y
- l& H6 g. N# V在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 v3 Z5 b* G2 |* a3 M9 ]static void McASPI2SConfigure(void)
( U- a! Y0 e9 T* V$ _; {: J{
6 b6 X8 S- G! Y' a6 k( XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: V' {" a" Q5 Q4 Y6 v; r; f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" r) y0 r9 t4 }7 m* q* u7 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% v4 X- c: @: K# E% M1 r0 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 C2 R. r: v& V2 }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; ]7 F1 |7 E' J7 d/ A* r7 KMCASP_RX_MODE_DMA);
, j* s* l h* b: |3 iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% f1 G+ t1 F0 x' N* n: o8 D5 a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 w: u! d) z- \' DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 z. Z+ d" E0 M* l( w5 x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 b7 I: Z: P: n8 V4 ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. S% [2 X/ Y" yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% V: F5 @" ]- J0 w# L7 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) t" C% ?9 x$ m$ {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. K1 d. X, J( a; H) |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 o& D* ]' x& f4 L0x00, 0xFF); /* configure the clock for transmitter */
0 Q8 p, _1 o9 \0 Z- U" {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& K, p* p$ k: J8 H) EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- W+ i% o u' o5 e0 S' L) \7 @" ^9 EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 `! n, v+ j! A: _
0x00, 0xFF);) [/ ~' I" f8 [) f
. i2 I; i- e* q1 c2 I& V# h/* Enable synchronization of RX and TX sections */ ; Z/ l- W* H) U$ b! _, W" s4 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! X- }/ l# h" o( `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ r# _; ~4 e7 \ l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 ^6 c1 @9 r* \8 E5 \
** Set the serializers, Currently only one serializer is set as( s# {; ^" H8 A6 `
** transmitter and one serializer as receiver.
" W# w! `4 m" J. }, l*/
1 _9 x7 G p+ a4 o% \! V% EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 P0 [2 b3 [& Z8 N- X' AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 t) C. u6 G. j4 D8 [
** Configure the McASP pins
3 d: R7 S. C# `; H' m6 k** Input - Frame Sync, Clock and Serializer Rx
$ e& ]. @* U1 a5 z6 K6 I. {3 d** Output - Serializer Tx is connected to the input of the codec - o" G9 `1 Z& R& u/ n
*/
_" s9 E7 }1 H6 b3 \/ m( ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 K: |/ d3 @+ n$ r" H3 V* iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) D! ^+ B" L; }1 d4 Y i5 X5 lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. u: }0 O$ d, a1 Y# _. N( }
| MCASP_PIN_ACLKX: F5 g* A. V# S1 Y" Q6 E) Y6 Z: r
| MCASP_PIN_AHCLKX
2 [, ~% J% d; n% P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" w& b) | \& p% ~- f2 U. ?1 M! hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / c/ w1 p8 C$ M' W- C
| MCASP_TX_CLKFAIL 4 M2 Y+ ^. o7 D
| MCASP_TX_SYNCERROR. \. U6 |& S1 k3 p1 |+ y6 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 W- R: Z! Y3 m6 t% v| MCASP_RX_CLKFAIL
( h4 i- N# A& U4 t| MCASP_RX_SYNCERROR " O# |( u: [+ a- i' W' Z- z
| MCASP_RX_OVERRUN);$ d- Q* e3 }: a# _0 Q" d
} static void I2SDataTxRxActivate(void)
- C* B9 x) t: K0 ^{# a- I5 D4 w# q9 J
/* Start the clocks */' n$ A1 g' ?6 n/ m3 W5 z% M& O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( I0 j' A; K! e: B$ V+ ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, G$ u9 {9 r# u8 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 B. P( A a" Y& J$ j2 K
EDMA3_TRIG_MODE_EVENT);
6 R4 a7 `& l, uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / [! \6 i6 S: k' r r- g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# C. h1 h: ~* [ }6 @+ n% |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 A" v& L/ G# q6 ?3 |; l! PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. j, E9 j( T! f2 ^. V4 x" v3 h, O
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 L% u# \( t8 }
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ G) Z; `2 O0 a! o% o) y, d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' k3 S+ P8 Q* `/ n: X9 C}
* k7 a7 y7 T) G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * K) C9 w& ^' T8 w. z( N
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