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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 R8 g0 G: Z! X/ X: Minput mcasp_ahclkx,4 J# A+ Z: [" x9 j3 B9 c% u
input mcasp_aclkx,. C$ M1 {5 k: y x$ y6 D# @3 M
input axr0,
& r6 C- f" U% u! A' f- |1 ` b
: p4 u/ G" O. w/ S2 w% Z9 aoutput mcasp_afsr,- D% C$ y) W$ r6 K' \- u8 O% _
output mcasp_ahclkr,
5 L/ k o8 l6 P/ s4 g+ w7 T' q, Joutput mcasp_aclkr,7 }8 r- B% T+ V
output axr1,
( B* K& r& p, [6 ?0 r assign mcasp_afsr = mcasp_afsx;0 z7 q$ G% {) f. v- m$ I" l
assign mcasp_aclkr = mcasp_aclkx;
$ m. A/ s4 u+ s W! M1 J' ~8 yassign mcasp_ahclkr = mcasp_ahclkx;$ i9 F) Y" j3 r
assign axr1 = axr0; % K) b5 E; I" {! |& g, J' r! z& B
! x- Z4 w6 w! T( R) }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" O) K( x6 _/ ]% ^- @+ [1 I. cstatic void McASPI2SConfigure(void)7 y( f6 C. Z N4 E1 P
{
( }( P$ G) f8 JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 m7 A& V' q/ u% W) LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 x4 C& E4 `7 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' A0 \% U$ r9 k8 F- |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! g1 ]& B2 @; Q7 H2 ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! L! Z' ] N+ a- q; [ |MCASP_RX_MODE_DMA);. C) g( h1 ^9 k- @2 A w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ f7 j3 z% H: ^3 v _9 r0 m- h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ B5 F ?2 U* v# [6 [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 _. Q6 | E+ \4 d1 k8 f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 n# N1 S% q3 r( EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 ^ v) Z5 c; H6 P/ }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* V2 q" p' f$ `' M1 R4 D. fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. {3 \# i4 F( ?. b4 b' H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ u, L( q8 h1 w* T: p* F/ o% E' }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 B+ w' D- l+ g2 a0x00, 0xFF); /* configure the clock for transmitter */
$ D* P$ s$ n; YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) R7 W2 n$ G; Q4 H5 V! }$ }) f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 ]0 y4 j& |$ ^# i% {. GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 Z0 [3 s, m6 \7 e
0x00, 0xFF);& G( I7 B; f# ]: U+ p. I% G: f
8 }) q# w4 ]6 V# k3 B; b- K8 w
/* Enable synchronization of RX and TX sections */
$ }/ y" i) ?! G2 fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 H. c& c* I9 p0 u6 L, s' BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) G( A8 c: j4 D8 x4 L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! f6 a: v; x! J0 Y3 O** Set the serializers, Currently only one serializer is set as
: i: M6 x/ |4 l& R2 ? a** transmitter and one serializer as receiver.
6 ~! N# f& e2 \, y- A* k( Y! h9 z*/
0 _- ?% L4 h8 [2 RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ V0 a. c: c1 R2 F) G. bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ _6 e: }, X1 r& g; K* k
** Configure the McASP pins ) d# [: P$ y9 |8 ]
** Input - Frame Sync, Clock and Serializer Rx
# H* n; j# b/ f" Q q0 l3 d5 V** Output - Serializer Tx is connected to the input of the codec ) A1 U4 F$ Q* Q$ d
*/
. {0 s2 a* o) M0 E- oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 S( X8 _* y5 \0 F x4 G6 hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); B; l/ ?. z; k5 ]
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! V0 d* H3 s! [" k/ ^| MCASP_PIN_ACLKX u0 G: [( |8 C; v
| MCASP_PIN_AHCLKX+ E8 _4 r- |# j# n* Q8 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& O1 t8 N) n: |; z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % [* o1 |* a) g4 ^" Y6 ]
| MCASP_TX_CLKFAIL
5 @2 {! \+ b& E; o6 g/ a| MCASP_TX_SYNCERROR
; ^! ^0 g5 u% n8 |7 h| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 O$ M; a& Z7 f' _) H& m: k
| MCASP_RX_CLKFAIL
# [6 a+ c0 t: i* I S4 h* _| MCASP_RX_SYNCERROR " I! N) _# B5 z U5 {0 r! R4 C8 J
| MCASP_RX_OVERRUN);8 _ [: a. u+ Y! q$ n
} static void I2SDataTxRxActivate(void)
7 ^! t3 ?' U: l# P/ L! W$ U+ n{0 F0 p6 l5 M I% P8 v7 x
/* Start the clocks */9 V, r, h' y! [: W/ ~; `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- D7 \9 o- l, f- A$ K" G+ J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 |+ Z0 G, P4 n8 s5 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% d8 W3 E. Y4 V+ Q2 i1 m
EDMA3_TRIG_MODE_EVENT);1 h" B8 ^& S; t6 b& [5 q9 x( d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 P, y- v" D1 Y# ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: M6 R* ]% C# z4 R) @
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! j: x1 n) |2 P: T/ y3 b) {2 R7 O0 JMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( b# J5 }+ o1 O4 A
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 ~* D: p/ v! Q5 Y# ~0 w4 R0 r: `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! C2 N# Y6 U9 b4 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
L: N1 g+ ]+ |4 n# t! L/ Q} ; T: R& T) s2 K# Q" e R0 }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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