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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; k0 d6 r- w/ h' }input mcasp_ahclkx,
7 i% [ z) d. X, E2 X: e1 H* i' Zinput mcasp_aclkx,
* z; S3 Z+ i ~8 `! A; g( iinput axr0,
. t9 ?/ H! q0 @4 ?+ q( j9 r2 K2 ~0 ~* [. B3 O& p
output mcasp_afsr,. O: E8 Q8 B' M2 [
output mcasp_ahclkr,) E: `: }8 g9 ?5 k* @
output mcasp_aclkr,9 z! F& z- }5 m+ e
output axr1,3 S. U! n5 d- s5 A h+ e6 J2 _
assign mcasp_afsr = mcasp_afsx;
" [1 Y+ `% k1 K( x, sassign mcasp_aclkr = mcasp_aclkx;! f* |5 v r" u
assign mcasp_ahclkr = mcasp_ahclkx;2 J0 W. }6 P, }1 F6 J/ H
assign axr1 = axr0;
: l2 g9 n( o0 t$ e' K9 E
) V1 F- R4 m; ^1 {0 |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( l. x9 u+ a) n4 }
static void McASPI2SConfigure(void)
0 P3 ~8 h* W7 l{
2 s5 G5 Y! Q& p2 J& v& n5 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 F4 n* y9 G: U4 |' \1 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# K2 T' U- k9 O5 b; y" O. Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 @& _4 Z+ E9 z5 J( p, H% }9 Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. T* p% F" m/ l. r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' u' n5 G' {2 l! r) K( T3 n
MCASP_RX_MODE_DMA);5 C; l4 \7 F& e1 H) ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ X; K$ @4 J u! gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" z {0 b) e( I2 K1 ^7 E% ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" \4 }+ o: |, r4 B, yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: G1 v. C5 c0 y! Y9 F7 h0 \4 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 ^7 k4 @5 `3 q. C$ B u/ L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 A" |. @% [6 r2 u3 e( y0 `( NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ h' |* S% f; {$ D: p( i& g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' o B7 a4 P) Z/ G
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- w& _, S$ b# e$ U& B& F0x00, 0xFF); /* configure the clock for transmitter */ v$ n* n: }' [9 H9 H9 g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 K' A" T+ T2 I" c& |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , d1 Y0 o2 K* O; a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% W I1 e% K% A1 _3 K, t# r$ S
0x00, 0xFF);& k3 R# B( ?* b. Y
4 d5 K% s7 E, X% D8 v8 p/ g/* Enable synchronization of RX and TX sections */ 6 p5 p0 z& O) F2 i+ b$ B0 a* V8 T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ t/ x5 W, E) i/ K. HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* y3 w2 E( S$ q' q& O/ n. q6 t) `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 N7 x9 `1 z) e; i
** Set the serializers, Currently only one serializer is set as; S2 `8 [. k9 d& _+ H
** transmitter and one serializer as receiver.
& `& {3 R! Z4 r*/4 T: n7 |/ J) y9 t! m
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
I0 C, T: F5 K# eMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' P6 a$ X9 G. h/ _4 V! f. g
** Configure the McASP pins p3 V6 u+ x# V6 l' g
** Input - Frame Sync, Clock and Serializer Rx
4 ] w) L5 Z" }+ M** Output - Serializer Tx is connected to the input of the codec
' L$ h1 L/ r) ]1 ~*/
' T8 y3 @% t3 A; m2 m" S7 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: W% a5 ~2 @6 U+ T0 @( z- r9 [; zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! e \ `; q; w( {' `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( c! F0 D! l2 Q& h+ b x
| MCASP_PIN_ACLKX8 Z! x) H9 u i" S" r* i
| MCASP_PIN_AHCLKX5 r% N! l$ U; J# k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 q! e& g/ N7 s! e1 A* d5 }7 HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 ]2 I" K! [0 ]2 R
| MCASP_TX_CLKFAIL
8 y* N' i9 \1 a; E/ M| MCASP_TX_SYNCERROR
- G# |" \9 Q/ Y( B P& h5 u| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 l! b1 C# Q( K" y% s# a7 P
| MCASP_RX_CLKFAIL5 P" j' |: G) V. T+ B2 s
| MCASP_RX_SYNCERROR
4 \6 _ D9 p# N+ [3 J| MCASP_RX_OVERRUN);
: L* u( L9 N1 ~} static void I2SDataTxRxActivate(void)- Z. I) r& {6 ?+ [6 r
{
9 K/ h8 ~5 V( g$ D/* Start the clocks */& t; [ A" A) \1 B r9 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ a" ^+ O: _" ]. l8 n
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& R: |6 \& P+ d' ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ s) {8 l" M2 M9 i9 x6 e, aEDMA3_TRIG_MODE_EVENT);: B8 T# X! Z9 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! @/ J( \% ]: W# _. _) OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: p) B: e- B& I0 B% A) \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ o$ ?/ {5 P: ]4 xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 c, Q8 S8 m9 p4 o; |# B: d& pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: s2 y3 t- y+ l) \5 NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
l1 O& ?# S# z# @/ F! A& m7 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); {8 P2 r! t3 A! T
}
8 w1 E! N: \& ~ F0 s, I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : h. u Z$ G9 ?; e m. D, C
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