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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" o* s4 W9 ]. N5 }input mcasp_ahclkx,
0 j9 V/ }) R ?% Z) Xinput mcasp_aclkx,* K/ {" N. ?/ o- r! R9 W
input axr0,
. S$ B% H/ K# G+ F/ `6 y* _& f+ [" B* T% a4 b
output mcasp_afsr,
! g1 v ^8 g5 k8 u6 R% t* @; R0 koutput mcasp_ahclkr,# H$ `# q* m% C
output mcasp_aclkr,& h: b' i6 A/ D& Y* } ]9 [
output axr1,
( B0 _) L% K* T+ J9 D) N! n1 r assign mcasp_afsr = mcasp_afsx;
# r" l S3 x3 a, Vassign mcasp_aclkr = mcasp_aclkx;# ?: t! Z- C1 f" k
assign mcasp_ahclkr = mcasp_ahclkx;
, K9 y9 c# H+ J" hassign axr1 = axr0;
' Q* ^( e9 ]+ U" @& F# J: f6 u: \. ^2 ` X( O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# m0 G* D# b6 A& _static void McASPI2SConfigure(void)
( Q t% E1 z% C& `( c) d( m4 e; Y{
1 J) }; C, {4 q! Y* iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Z$ T. Y3 H- ]8 C8 `1 ?) J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 ]3 l* P2 J( N- G. e- s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
^# q& l/ c) o+ tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' {( K% g* W; F6 S( MMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 v/ l% s: h7 f* M: ~& b2 }0 G
MCASP_RX_MODE_DMA);
/ V9 M" X$ c* X8 ~9 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# S5 ^! o9 s0 P1 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% k' I( g7 Y: Q3 l9 f, m4 N( JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* J% q- {0 k4 N6 e& mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 Z4 v( i" U' w& r2 A8 R2 NMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 I- I, O. |) HMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 Z5 `( s8 ?! ~, q' n; I% UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 E4 ^- d& r5 \$ WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : w% v0 D7 y7 d$ p% V+ {6 e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. a+ \! j9 `) E! q5 e. J0x00, 0xFF); /* configure the clock for transmitter */: z. G) D( C8 J; M- c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 r3 u; j: `- x" W! OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 i1 w2 l% B& X/ l/ k0 n k0 i0 v: YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," _( S2 N' x/ z; x3 A
0x00, 0xFF);
! S+ y3 a$ k c5 I
2 ?8 k5 e: v# R$ K/* Enable synchronization of RX and TX sections */ 6 u f6 c+ I3 u& l# g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! ~9 a8 N o9 Y; LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 z; ]+ U Y7 {4 x8 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' C8 V5 z6 d O' G# \( E4 C** Set the serializers, Currently only one serializer is set as
: R9 V# m1 T) M; M: A8 }** transmitter and one serializer as receiver.$ S" w0 S7 G5 O
*/" Y1 W4 m: u- {2 L( z0 J; ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! Z- j: c' _: z8 s( u$ P0 M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! q2 X$ p) u: D$ Z$ \ w** Configure the McASP pins
+ Q- k6 f, I5 \- X$ a- }** Input - Frame Sync, Clock and Serializer Rx# ?, }- O. `, Q! w6 u# D% c4 M# ?
** Output - Serializer Tx is connected to the input of the codec / ^8 W$ P5 p. e- y
*/
# U) [( D% i! O# t5 A' nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 Z7 H* I. W9 G) c3 P: f5 ~+ @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; c2 Z( I* i) D; S) [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) D' f% x( ~2 t* g| MCASP_PIN_ACLKX
$ {+ Q- q& q, E| MCASP_PIN_AHCLKX
1 M/ g, P. p" H, x! M/ i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' e" W5 u6 z- P# m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # @- q. q) ?" \6 @; o A
| MCASP_TX_CLKFAIL
* B+ R& [7 I& b6 I| MCASP_TX_SYNCERROR
w2 L& {2 c1 Z, h. |( _| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - h) @0 S& f5 ]! A+ z
| MCASP_RX_CLKFAIL0 u! V# T3 c- m5 q2 \5 f
| MCASP_RX_SYNCERROR
7 W, i: `9 Q$ y9 F+ M- g% E1 a| MCASP_RX_OVERRUN);& c; q4 Q1 C$ ~/ l8 `4 Y2 b
} static void I2SDataTxRxActivate(void)
% z5 p. R% c, e0 t/ W$ \8 F{
- z1 Z8 L( X- h O7 t/* Start the clocks */6 e+ n9 r" E! q: h0 _7 U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( a0 F4 S) [0 }* P: L& p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! F- |; A, k" n( MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 [* W! w6 ~' aEDMA3_TRIG_MODE_EVENT); H6 U5 y3 z" P' Q3 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * M. R, o# ?1 ~" Q2 X6 e S" U8 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ U8 G) G; b- y, p5 u; _6 A" i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 l9 [/ m5 a* ]7 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 }( b5 b( n6 J4 N4 h+ }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; @# y' t& c$ T4 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- u- {7 R0 j# Q: `1 YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! M' m: r4 b6 ]9 i( U/ U
}
% p/ i. g/ q4 Y' l, u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ~9 n- X8 G. ~* i
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