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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 w7 }! k$ d- v2 f; _
input mcasp_ahclkx,9 D: s; O' X& H' B) ?' P! a& M
input mcasp_aclkx,& v- g" A. V! L, S' n
input axr0,; K1 d; Q# V/ _6 }/ Z4 m
) `. O6 O8 P! l: ioutput mcasp_afsr,; o& h: }% Z( r2 `' L% _
output mcasp_ahclkr,
5 X% H) z f; q" y' G' Woutput mcasp_aclkr,
5 ^% e+ V( I7 c: g1 v* @output axr1,
6 U6 s- _" v$ h! H: e assign mcasp_afsr = mcasp_afsx;
% `/ B# l- L: O& j4 F$ yassign mcasp_aclkr = mcasp_aclkx;* O( H, j! r6 H5 S0 C6 v" Q6 j
assign mcasp_ahclkr = mcasp_ahclkx;
4 O/ ?% t% m' uassign axr1 = axr0;
3 _# x& t7 x! r) `# l, o% b. G
6 {% W& Z) y( E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% P+ E+ Q1 z. L, p3 a# [. {static void McASPI2SConfigure(void)3 F3 O1 p+ |; q6 J
{ S# l' m, p) ]8 {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& O6 v' y& o# Q/ z) {( I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: t" b* Q# H( r# G
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ X: b# Y0 B% |% M0 @# IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ B n/ i$ R/ W8 r5 ^$ \
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% V( @7 f; u( ]% }MCASP_RX_MODE_DMA);: d6 v. l# h6 \+ `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 c$ U/ R: R) v1 u- |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" C$ d3 z! d" h/ zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: X7 y k0 B7 y- P! C% f/ FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 ]5 s1 W) e. q; E1 N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 D. D, J- H, ?& B3 j% q0 Q: |0 S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* b& t) `, b8 P% Z+ x h& jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 |! q( K7 Z) `: cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ {9 J, Y4 y' d) t5 Y- uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& ], |+ ~$ A/ E0 e8 z8 s6 J0x00, 0xFF); /* configure the clock for transmitter */
a& a5 q9 }; [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" f5 d- y8 l8 W- v" Y8 _6 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ m5 {- y/ C: F# d9 n! F& x9 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 t9 e. C/ t. A! {: m7 q/ B! J0x00, 0xFF);
T! V5 @4 h5 n' P( _2 N
q/ w2 W! \# D$ O/* Enable synchronization of RX and TX sections */
# Q( q s. z4 z9 XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 V6 A8 F+ x( Y9 `1 Z( QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 S! }, A; W3 n+ L% D& WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" Y6 {$ e- `8 u% r' S2 v$ A
** Set the serializers, Currently only one serializer is set as
) m. c7 H9 y* t C6 Y8 N** transmitter and one serializer as receiver.' }0 h2 u2 z1 \
*/
! J' P0 D% z4 x9 EMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ K" C0 X5 U8 J) p8 B: M3 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 j3 n4 f- X( X) O7 Z
** Configure the McASP pins
`& B6 l7 H" m! @3 Z; p** Input - Frame Sync, Clock and Serializer Rx
8 O7 z) ?8 G2 k$ L) N8 [** Output - Serializer Tx is connected to the input of the codec
; M) H* ?$ W" I+ T9 U$ y*/
) P! t$ |9 n+ `6 N7 I6 @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 @. k d: J, tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- G* m' H# L' m" N% iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( r4 a8 t7 b/ e+ e
| MCASP_PIN_ACLKX
7 R6 }% ?. K- I7 w| MCASP_PIN_AHCLKX
7 h$ U3 e# S' `( e* N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* g8 L1 Q2 I0 t3 ~0 SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 u2 M( e+ X+ O3 U# E| MCASP_TX_CLKFAIL
: O' A1 Y7 K4 H' G. ^3 d; N| MCASP_TX_SYNCERROR1 @1 \$ {' f$ f# d' H$ i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
v& J: z" x9 K1 F6 C4 T# n| MCASP_RX_CLKFAIL
9 w! @# d& ~% B+ x, T3 ?0 k% [: y& J| MCASP_RX_SYNCERROR 5 q8 Z8 `9 ^+ L, S9 P; u9 R
| MCASP_RX_OVERRUN);; S( k! h y/ H" F+ u/ x9 Y/ y
} static void I2SDataTxRxActivate(void)
w; B! B9 y% O2 Y$ H( C{9 O& ~" w8 s9 h/ i9 ~2 C" b
/* Start the clocks */
0 r% R7 e I1 e/ F, |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" @6 O/ h) D/ ?0 Z7 A# G: a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 [6 \+ p; x$ R+ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. R+ D% ]+ q* z; T) f
EDMA3_TRIG_MODE_EVENT);
S: v4 X) q9 I" WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, P r" o( G; s a8 m0 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, P' e. O4 }+ c4 n! a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 \# l7 G) T# w+ g A) _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 C- _" Z m3 N" ~" U
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- @* L7 ^; [& |% O @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: l" o( |) w& ?& G2 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 @6 V4 [; F9 H
}
+ F6 ^: N% T3 p0 v2 g" N1 U* l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + I' `$ O# C9 t+ ]2 i: f# N
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