|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 @; [8 o3 u) x0 C: }input mcasp_ahclkx,
" t7 }* p- p$ ^input mcasp_aclkx,
; ?$ D2 \' J2 s$ o1 binput axr0,
# w% C p8 h# W, @* ?6 h* r
! ~' Z; }1 E' ]! { B. B( @3 |! Toutput mcasp_afsr,
0 X Y. V) p; W* voutput mcasp_ahclkr,4 U8 k( Q: U5 Z$ l1 n, k+ I
output mcasp_aclkr,, A* b$ d/ \2 m- q
output axr1,
7 v6 \4 g! B6 S8 G& J) c assign mcasp_afsr = mcasp_afsx;
4 n9 H! ^ J" |assign mcasp_aclkr = mcasp_aclkx;0 |. n7 X" D9 q
assign mcasp_ahclkr = mcasp_ahclkx;
' T5 L$ w, w w0 y7 f4 `' W$ passign axr1 = axr0;
5 ?) w& n3 Z) E/ F+ y" l+ e7 O
; _3 X3 K( u5 Y- J' E8 q+ h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % M) U& A) ?# ~7 C" @2 t* u g c
static void McASPI2SConfigure(void)$ @% `4 W' P- ]) @
{4 P8 I0 x; D R# ^5 c4 r' i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 p6 A- c/ A$ D( M8 g) \. [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 J0 a1 u, f7 ^' f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 U" r' E4 o: A8 |) m: _, lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 y4 k( o* M! p3 C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! _/ k1 F6 z: B' H2 y% d
MCASP_RX_MODE_DMA);
: d+ u4 w$ z% h4 [: {/ m2 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 X0 o+ I0 V+ R9 h4 f6 h# ]% M3 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 j: k w3 `- H& _8 ?! s$ }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& U$ {5 R+ a% d+ [$ x7 p8 E% rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( F# E: D+ S0 U, y1 m) B2 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( H2 i7 \* T9 |, W. h6 j: W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ x% o' X7 J) ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& Q. @ h; O: ?, V- u/ W# iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! v/ y: ]! |* c! j! X% X0 K" u8 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# P+ O- U& p2 A) D: p# A" X
0x00, 0xFF); /* configure the clock for transmitter */: w8 a9 f6 _7 q' o: d, e, C6 |% ]* v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% g. N. c( I' _8 H1 L1 YMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " m+ }. v8 [! J: q: F2 u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 y( T. n* @9 |% _0x00, 0xFF);5 m! w; M8 ^0 p- a6 D8 `5 O" X
* N% ]& c% V: K8 J9 Z3 v6 U/* Enable synchronization of RX and TX sections */
9 `4 }( l: I( V+ H5 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( p# X& I% d$ k" f4 k9 @7 d( MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' y0 n. R6 y% j& L0 I
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 g5 q; T4 B X** Set the serializers, Currently only one serializer is set as
|! M4 M. r7 e2 F& I/ c8 Q1 e% X) ]** transmitter and one serializer as receiver.
) t7 M ]% O2 A# P% Q' r g*/6 M3 c9 L, z4 S$ |' c# d+ T5 {8 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 j( ]9 [$ ^3 o5 m, h. p6 R0 J$ A5 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) k" ^- s: i% e6 y# y. V% H
** Configure the McASP pins
T( z, b; l* J, r3 D, T: b2 p** Input - Frame Sync, Clock and Serializer Rx8 C# p% n$ k7 q( B* C$ G; ^
** Output - Serializer Tx is connected to the input of the codec 2 B& _5 ]/ [1 B7 V( `
*/7 V0 ]7 F) V6 D. b' z3 y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); A8 t" x( D7 \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 a* t4 I2 t ^1 }' F" B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 {- c) N1 m$ O9 j4 K$ Y| MCASP_PIN_ACLKX% v" R: x% g) z
| MCASP_PIN_AHCLKX6 n% Q6 @3 F2 G8 b# D! A1 ]% z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, r+ R: S* W9 }7 j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 t2 N1 h+ c: i. ~+ }$ k; Q
| MCASP_TX_CLKFAIL
* c4 q9 n/ W( Z# || MCASP_TX_SYNCERROR7 r2 x* i/ M0 F- W! O& ^$ E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
e# D4 h, m( W" y5 o| MCASP_RX_CLKFAIL O+ N9 I( A) T2 ?
| MCASP_RX_SYNCERROR
8 V. g0 Y* }9 @8 U/ ^( `% k- w& }: s| MCASP_RX_OVERRUN);$ J y, |3 m% G1 e; C! y
} static void I2SDataTxRxActivate(void)$ }+ X1 E7 a/ V3 p
{
4 h7 O0 I$ A6 o6 i; q( N1 O2 r/* Start the clocks */
: z+ F: J) w& q7 H. P2 H5 a" h) h; tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 d& @/ E- O7 Y5 v- ^! JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) k0 D' e: K+ J+ N9 u. T8 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# \* X. @# D* B* Y/ `3 r* ^
EDMA3_TRIG_MODE_EVENT);
& _7 w7 i5 p) t, ]7 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * ?& V1 W" {" C' }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 o- g3 X- x, @3 y. d" w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ B2 K- \ N4 r1 r+ c- u, y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ t/ Y# s6 e3 F2 `4 S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 b9 u; e6 a2 L+ |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 W' w# W- ~/ T& p+ ^! E8 x: vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 o/ M: X" d/ r! a( S( I1 w* Q
}
2 o2 O4 b9 ]0 v) [; M) x% J请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
E6 ]$ d5 q8 z3 B |