MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
8 T% ^6 Q5 C, n4 |% ^input mcasp_aclkx,
, Y/ d) x- M& ainput axr0,
8 _, l$ W4 }, W- }2 C: ^$ w5 {
' l* D9 _! e5 S0 Q4 |# R1 houtput mcasp_afsr,
& ?. {: S7 n; }' Q( Z" }! Youtput mcasp_ahclkr,
6 i) A8 J6 I+ v3 u, L0 Aoutput mcasp_aclkr,
! m% b! F( {8 {+ z5 doutput axr1,
; @8 w; }) H6 Z" N

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
1 i* `8 o5 U  j% Dassign mcasp_ahclkr = mcasp_ahclkx;
$ z1 _( P# Y$ T2 ]2 F- H) e  M! {assign axr1 = axr0;

3 V9 d; H. e& C3 ?

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

6 ^& u7 V, R2 ], e- S+ B

static void McASPI2SConfigure(void)
# \; M; T4 g7 s4 O: _- d- m8 N{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 M3 n1 Z7 H% ], gMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
# r  z8 o5 y. o8 w) D" @7 eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
+ i; U/ l0 M) D% oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' Y) Z3 l/ X; f  v9 |& p! vMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 O. D: r: b8 j* p* z. u. WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 l. `& V+ p7 m& l! |4 c+ E, ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# L! y0 p+ d2 }# w- n, [( F+ G( m1 jMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 f* j6 N' a0 A9 q! u) ]6 `* WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% y- C1 z  q4 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ v2 ^6 t3 O  U% q! m3 G7 U0x00, 0xFF);

/* configure the clock for transmitter */
: Q$ [* Q6 h$ V) m+ y4 c5 x4 KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) x8 E- q, s) O% X) y3 FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

; c& ]6 Q8 A( z: V! b/* Enable synchronization of RX and TX sections */
& ~$ z/ _5 y7 D0 \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 H. s" q1 w8 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
, ?, X& q1 y  V* K- n+ m** transmitter and one serializer as receiver.
*/
* N1 ]3 ?4 A* l, T, d) g4 h4 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
! d' r7 i$ U0 }# K1 x** Output - Serializer Tx is connected to the input of the codec
4 L5 d1 I7 O; F5 k- C*/
7 T1 D: C6 l% Q; M4 uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 ^, s' S& l1 {- tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 \  W7 A7 }; C6 c) B$ Q6 s% d| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
9 }3 K# F0 `6 d2 f( d5 g1 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
  `9 {# m& g0 T/ _  r$ f1 L| MCASP_TX_CLKFAIL
0 S" u( l- z- E" R1 v9 r# v| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# o* T0 E5 Y+ w6 d| MCASP_RX_CLKFAIL
0 {  V! S9 c2 A" Z| MCASP_RX_SYNCERROR
+ ?, Z) s' z- k# H| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
5 Q+ ~+ ^' w6 V. K{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  Q5 N- d: b. f" F7 W1 [" cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
, \; J" t0 \+ k+ B5 NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% d: A; V& D8 [! w" F3 P# C& T2 UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 ?: A4 I/ d, FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
6 ^5 }. R- C$ e3 ?6 l0 Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
7 y9 y: G1 v' Z% }; pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" ~( m: k2 M% D" @% N0 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# ]' @6 n! t( U+ |: h}

3 G7 i8 [" W9 H7 M

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.