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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( c D6 D+ ~5 M; c! n
input mcasp_ahclkx,0 k6 A: O) c& k; e8 L# [4 e
input mcasp_aclkx,4 O" p* c! G( L7 u% T% D" |
input axr0,
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output mcasp_afsr,6 m: j. h, q; B5 G d5 `& K& M
output mcasp_ahclkr," n& A r* O8 A1 {/ x- N0 B
output mcasp_aclkr,
, q$ M+ `( R. p5 v7 Loutput axr1,: k, Z* L4 C4 n6 U4 K
assign mcasp_afsr = mcasp_afsx;/ t9 S- f2 |" B: D0 Y
assign mcasp_aclkr = mcasp_aclkx;) ~9 l3 G$ h% _) H7 E& _
assign mcasp_ahclkr = mcasp_ahclkx;
0 M8 `; l# U" @# h8 L9 ]& e- p# Massign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! L! b0 p, X. E2 Y5 Hstatic void McASPI2SConfigure(void)2 @. T8 J. J+ Y4 z& k p
{9 @% i/ Q4 _" q$ w5 i# c! Q' l& M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- m2 j. Q& B) @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: ?1 j% o/ V6 o! K; C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: G" X' A! ~, N/ K* GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- ~& ^. @/ O. D$ t5 z) ?. I9 O! lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 Y2 r: M) P" }. c3 C' n: V& B- ]- QMCASP_RX_MODE_DMA);$ `. \# o' d, a! u6 U! A, I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& z; [/ @7 |! ^6 y/ ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# q3 t: c5 B ^7 X- g/ ]( W$ S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / {6 B$ Z" X. x0 Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 X& b& W3 k! l% k4 E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * o, K$ X) ^6 C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* o# W1 m& E/ f" M f. O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 `; H, v* h. x- X4 e7 `1 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * u& A3 P. o6 s# d0 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ d' y ~' i( K
0x00, 0xFF); /* configure the clock for transmitter */* Y; }4 i9 X/ p9 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 m6 O- w: k# H! q/ v6 c) A' X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ _* C- D6 X! b: N# ?2 H( bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 j% `% ~: w% S* u; Y% P4 R0x00, 0xFF);
3 F- ~* d& a5 z/ z0 @# s
+ a$ C9 e+ D7 O/* Enable synchronization of RX and TX sections */ 6 [5 c. i* P7 r8 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: L; f& q. I/ Q, EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; I' c3 X! F0 m# ~+ n& `* E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# e9 w1 N* [, ~( F6 d) C# a
** Set the serializers, Currently only one serializer is set as
, W) }; e" D7 ~8 v; s6 K** transmitter and one serializer as receiver.
$ G. z$ a9 ?8 H7 Z/ `( c) D0 S% Q*/
- y7 E6 r ?3 T6 p8 m9 r" p3 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 i/ e; g N6 ]4 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 D, q$ b6 I2 S4 ?5 K
** Configure the McASP pins
* z( I8 @/ n N3 m7 [** Input - Frame Sync, Clock and Serializer Rx
* {6 f) V6 v$ d% |; Z( z: _4 X** Output - Serializer Tx is connected to the input of the codec
' R7 i. d# h! g) V; K: x' l*/% D+ g# @# N, \& j0 R3 u8 s) B& B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) k$ ^6 p1 L/ w) [3 L, A' JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# c8 ^* o# ^% O2 a" J
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( R! L4 x4 U M5 L
| MCASP_PIN_ACLKX
" G) P: l( E. V0 K| MCASP_PIN_AHCLKX3 a1 o, n" S) q; \ \7 ?1 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% @# W0 M! m. r: V' f0 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! S2 c' g( E2 {! _/ p7 || MCASP_TX_CLKFAIL
5 k" ]* G+ J2 `* i' q7 W| MCASP_TX_SYNCERROR& x E: ` I5 W2 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % q' d& V# Z" [1 P8 R/ l9 }
| MCASP_RX_CLKFAIL+ N6 q8 O0 r4 O0 e C L$ s3 t
| MCASP_RX_SYNCERROR % P# r S, Q# Z& x
| MCASP_RX_OVERRUN);
M" a8 d+ n, u9 o} static void I2SDataTxRxActivate(void)+ A6 ~. P$ O1 V# s3 k
{
* J+ L* R4 G; H& S- k: K2 C/* Start the clocks */) v9 Y" J* Z, J% ^2 }) p7 ~ `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ U2 Q- }0 _+ p" {9 H" j. K$ NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 h) [+ g) Y" z. ?4 i7 S" s3 C9 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 r7 ?8 J3 R- b) iEDMA3_TRIG_MODE_EVENT);
9 k- Q/ R: f! B- A5 A6 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 Z X# l5 e" @, [3 O6 Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; }8 B8 j+ v; P) z, z$ F* F6 }" aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 x" ^) M0 g; |" s) ^( {9 VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 i/ V a5 g T6 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. }7 Y2 J" i4 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 k1 [0 y8 x* r/ Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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