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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 E0 A7 j, a6 c. @* Z" m; ]2 winput mcasp_ahclkx,& T- x. o! A7 M, \* e7 K$ L% n- w
input mcasp_aclkx,2 _2 \0 U) d6 o* `; R) W
input axr0,3 h" Z* D6 {- F
1 i9 m" Y1 Y% o8 o
output mcasp_afsr,
" x5 M/ p+ @( W/ C5 q% Foutput mcasp_ahclkr,) {' }' i* q; C$ L, R! ?! P1 y
output mcasp_aclkr,' i4 w, p: J; N J) K& s+ N+ ~* y
output axr1,
; N! s- w$ A5 y assign mcasp_afsr = mcasp_afsx;
+ N9 L* M3 g; z: {( m% aassign mcasp_aclkr = mcasp_aclkx;/ f/ m; e2 `* d( e
assign mcasp_ahclkr = mcasp_ahclkx;
9 z$ S+ ~( E3 G0 Xassign axr1 = axr0; + j* a* Z7 l7 ?, ]2 n: {: g
+ M- g* b) v4 Q7 T3 G7 U在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 j2 C4 s8 t# A& `. Q) V
static void McASPI2SConfigure(void)- D N' z( d5 O. o2 ]2 N+ t
{
6 `8 u4 H# u0 `# w# nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! c* P% }* h# R: g2 F) k2 ~5 c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 m9 d& e; C8 @3 ]3 D; |# i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
N% R& T8 | v. c) ] z+ f% KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) |3 W, S( b ^* a- i8 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ S! E& u/ Y. p' k( eMCASP_RX_MODE_DMA);
3 C3 V( ^" q' b& _- h% S- hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# |6 u1 m; c& m# tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& w: ]7 Y0 q, a2 P- {$ u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# k) K- o0 j1 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' F% f+ ^/ ^2 H" A* f) }$ L$ CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( C- W1 D- k5 l5 \1 q3 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 U1 C$ G- J4 s% ]& LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! f7 a, }9 E7 n) }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . V% z! y. S) x! W _5 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. |5 |9 R4 j3 J0x00, 0xFF); /* configure the clock for transmitter *// V( F5 t6 f. _# F U3 r3 _: _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 ]7 O; _6 b: u" F CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 @& Y7 @1 C6 T- u
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- f! [1 N, y% G0x00, 0xFF);8 t+ t) n* O: B# E1 K# e- a) j
8 M. v- W3 x0 X& d/ d' {! v
/* Enable synchronization of RX and TX sections */ # \$ |1 I/ ^8 k. F8 ~$ ^
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" W+ r3 _+ `2 z0 A: K3 r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: d4 h+ P6 a* |: ?% }6 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* q" e' L9 H- i2 M, `** Set the serializers, Currently only one serializer is set as' W$ h, n2 A* Q: d4 W
** transmitter and one serializer as receiver. @$ N7 P' E. y- t, Y6 |4 W4 Q: a
*/
7 z. V0 @+ B, J# T1 i+ Z# GMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); u4 V, ~. V. }6 ~6 e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: J. h( O1 D& H0 A$ J3 y) [** Configure the McASP pins
6 {- |8 z9 f& C9 E4 f( Y! S. w** Input - Frame Sync, Clock and Serializer Rx1 s8 r* i0 Y9 c4 N3 |
** Output - Serializer Tx is connected to the input of the codec : F* ]7 U7 E3 l0 _+ S
*/' X& A% B3 K7 c7 c# s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; B0 [+ `/ E( Y& x8 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 ?4 [. A3 d+ m0 v% l$ L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 d( Z6 b% ?: c" t% H
| MCASP_PIN_ACLKX' ]: b* l" q$ D% D0 p" p
| MCASP_PIN_AHCLKX
1 y9 O+ ~ S- E( B7 m/ D: G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 \/ R# C( B+ [1 w0 w" c% |3 M' u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 R! J6 w/ E; |, a& Q6 s1 H5 q% H
| MCASP_TX_CLKFAIL d5 i) r" ]' {; L9 j( I2 U: b
| MCASP_TX_SYNCERROR1 N$ F( V6 b: H7 j' ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! d. c+ P& |5 m+ D" b$ m
| MCASP_RX_CLKFAIL
4 B$ X7 R& V* [" q9 y) j2 Z5 W| MCASP_RX_SYNCERROR
) L Y6 S/ U7 l5 C" ^+ F# `7 I| MCASP_RX_OVERRUN);) g' A5 m( f8 G% J
} static void I2SDataTxRxActivate(void)
% O5 c5 u+ Y3 C' \: _; g0 f{8 |8 r# x0 s/ Q- V% M
/* Start the clocks */
w/ \% `1 B" o8 f* u: RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! y* w* g, r; u" j5 A/ N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 C( w( q2 j; B, y% t& C( t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 C s; F7 i1 f
EDMA3_TRIG_MODE_EVENT);
1 f# o7 d P7 L1 R2 y6 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' f% h% y; y) I( T( v2 a; n, N9 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 C- p8 L3 V- T0 y: c0 n& m2 j7 OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 X9 e* z! E" R$ F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// t, B! T; L! \1 ?4 c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# X! d5 j, x% C7 [- f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' e+ {2 {) a* K( M7 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ F& I, ~! e6 G' o
} + ^6 @% R ?" h2 r& t3 D1 ?8 I5 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 K4 j/ m; S9 |7 w/ A- g8 r2 i
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