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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' V; n5 F9 A" k# q& h. y: x
input mcasp_ahclkx,9 l! m: k* l) D+ D
input mcasp_aclkx,- ?- y* E5 y, N: H
input axr0,
4 H% y4 z, |. B; t; k: C3 X; o! G
& q& D+ Q. ]8 o5 T* s- G# }output mcasp_afsr,
( l4 Q! L @3 k% w$ e Goutput mcasp_ahclkr, i" ?: U0 s# y Y; @
output mcasp_aclkr,1 r: d1 ]0 ~1 w' A L2 w( x8 F
output axr1,3 v& I) j! S' w/ a& T3 b# S1 h
assign mcasp_afsr = mcasp_afsx;
3 \3 _: \, Z! Q: s3 Hassign mcasp_aclkr = mcasp_aclkx;
3 `, a6 ]" r+ n9 V- Dassign mcasp_ahclkr = mcasp_ahclkx;1 j; w, C* B' _: \1 M/ s
assign axr1 = axr0; ; @0 Y1 C$ x1 X' @+ k( z3 B9 j0 w
8 o% P1 a2 v" N5 z1 {% h
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . D2 q" B- B( P3 u, w ?4 T
static void McASPI2SConfigure(void)
1 O$ x0 u" a/ p( K! M{
5 G$ f+ y8 N' R7 o7 F2 E; HMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 b0 |, G5 E E7 n1 g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" {0 }; w/ }: p0 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: X0 G. c4 }0 r6 B* J/ \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ F; ]! c2 _4 L( k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# O W. ]% g1 P/ p+ |
MCASP_RX_MODE_DMA);
+ q. z. b. u$ u! {7 m4 U! M6 t& i/ VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 o. ?# c$ M5 q5 [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& \& |& f6 H1 R( D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 Y8 \0 E* ^; X! Z- y; ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; r4 e& ^( Q) b# n* c
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" W5 Y+ \. P" p: t2 }4 Y- I) I% q! }MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ l r1 |4 L1 G3 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 V" j( X) O" P6 J _" _. ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: o3 @) P! k6 M2 r( X7 TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 T n7 J8 ]+ _4 P7 r0x00, 0xFF); /* configure the clock for transmitter */
6 G' H: ?* |7 B8 O& s* JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 k/ H: L3 T [* F& O6 V! ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / ^8 C" i$ E3 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 R: C& H# G( y" a( ~0x00, 0xFF);
& {4 A$ F3 f& k1 D% B
* b) W2 d' _5 h6 i& j/* Enable synchronization of RX and TX sections */ , y4 X( w( h, _# b9 A
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- k$ ?8 J1 S* E/ mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 m1 R% i4 W4 j, s& o& h3 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 \# z8 r2 J+ V- X
** Set the serializers, Currently only one serializer is set as
( m$ r! a+ ^4 }- {0 z4 {. a** transmitter and one serializer as receiver.
1 ^' G5 H# T u1 r- R& F*/
; H6 M; T0 u. R7 D3 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ P* o1 J6 }4 w C) ^! xMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 U( N; ]; W8 B& y1 N8 U! A
** Configure the McASP pins
2 ~& @- s) x% S' N0 i3 Z z; k% x** Input - Frame Sync, Clock and Serializer Rx
/ y) ~; O- M. M% `# H R) E9 b. _** Output - Serializer Tx is connected to the input of the codec 4 w, S6 c6 U# ]0 O; d& B8 m
*/! B% I4 P r: o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 b* H: ~! N7 y QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- O' N1 ]9 h% w6 H* A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 q2 K! D' e0 j% s" E9 H- A
| MCASP_PIN_ACLKX
( h& ]( ?* ]% J( y6 K1 C| MCASP_PIN_AHCLKX+ u: r* J W; ^7 _" L7 u
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% }9 b# D4 A" LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # I* o& c3 B; @; [7 T. n0 u# l
| MCASP_TX_CLKFAIL ( _0 n1 m: U& r+ k& t0 x
| MCASP_TX_SYNCERROR
5 `1 B8 h8 u" n- Y$ }7 a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : m% O3 h$ }. |. `% C& B
| MCASP_RX_CLKFAIL! @7 Q5 ?4 o1 }% `3 b
| MCASP_RX_SYNCERROR 4 \$ a+ z5 R# Q
| MCASP_RX_OVERRUN);* F% \+ ?2 B9 @6 x# Q' F+ D
} static void I2SDataTxRxActivate(void)
+ z8 ~ s3 O7 w- e- I! G: k. d{: I! q+ O; l" g( }9 P% Y6 w* H; t
/* Start the clocks */
, d: r7 m% t) q: i4 o. TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 H; p2 M3 i6 `5 h( G. PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* {" v2 K$ G; B2 I5 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: U) J w8 b7 }9 ?EDMA3_TRIG_MODE_EVENT);
) m! q8 C- z6 p* C+ L' CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! [$ p5 a% E8 b, nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) h# ~$ e7 K+ @+ R( \0 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) W. E1 `4 ^" ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ }, `$ y, Y/ n' ]) C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% }# V3 p: u% Q1 ^% ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 {: ?; x. A( v( B; R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) I* h% n5 k9 G# f* G- F
}
+ W- [( _. e5 R* ~" j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % r7 Q2 C- X/ U: t: O3 t2 I9 Z9 ?3 m
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