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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* G* T J3 t0 y j, F: cinput mcasp_ahclkx,+ v! ~- _1 W, n4 j9 g; p4 w
input mcasp_aclkx,
) @3 r' f5 [( T$ K. `3 |input axr0,
% I5 P+ T9 V3 Y$ N( ~5 N; L) B% D7 h- j' k- J2 N
output mcasp_afsr,
, c: [$ B7 s" v9 loutput mcasp_ahclkr,
6 r1 ] l; C9 W! j: n+ voutput mcasp_aclkr,7 c5 K, S$ Z. l) N+ _3 z8 Z! f3 `
output axr1," d' J( H: _, u- L' D
assign mcasp_afsr = mcasp_afsx;
" {9 V! u8 d2 E4 U. b/ Iassign mcasp_aclkr = mcasp_aclkx;
& k" Z8 D, Z {9 u Uassign mcasp_ahclkr = mcasp_ahclkx;
+ b7 C- v+ z# D. d" P+ V% Jassign axr1 = axr0;
" j/ s' o4 o. W& @* o ]
8 F9 ^+ n2 J' h0 x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" ~+ r- @3 L1 d4 v3 d0 qstatic void McASPI2SConfigure(void)9 p2 W1 \* C; J6 x/ }6 b
{% l. Q& k* Y: A) D: ]4 E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! e- H z; {, G$ M5 {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. F* z- h1 {4 `. O4 O! rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 C9 c6 x, y# A/ u4 w$ O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ r; P# f) I9 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# f& A3 \2 p: E z4 M( yMCASP_RX_MODE_DMA);2 g, H9 z; h7 O8 O. q9 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 O1 L! L" b$ X6 X# z/ P7 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 ~( W6 W `+ H- }( D2 b7 d+ h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 R; z/ q/ t2 OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# ]- ?$ j! j6 u+ ]5 ^& G( c/ F# k' b5 KMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ }% ~* [! d" h: E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 a$ X9 R: A' g, E. m) x# UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. v& d; _' [0 e$ s6 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : f! k8 V& {; P
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) h+ [; [( L' E7 \$ M
0x00, 0xFF); /* configure the clock for transmitter */
/ \. `* X& ^# JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. M% w+ ^) D$ O3 X% A0 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: m+ ^2 \! {$ p2 A9 WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( [* Z6 K& e. \$ Y7 n F
0x00, 0xFF);
/ \5 [* n/ k0 y% c
. X3 A4 ^; r8 u }/* Enable synchronization of RX and TX sections */
7 e2 Y+ {( V- u L3 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- y. V' @6 z1 R, T" O2 N' T$ vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 K% V) E/ ^" f+ T* n, Z# @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( ?" m3 N) T) L1 v** Set the serializers, Currently only one serializer is set as& c0 G% V! }" ?6 G9 `
** transmitter and one serializer as receiver.! q' Z! ]2 y, J' |5 q, N
*/
8 d9 F( Y1 D! W# o$ p+ I1 WMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& m. D" D7 ~4 @1 AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' V1 O) O. | V% ~9 m: i( _( G** Configure the McASP pins
0 V# g! c. E7 W& @# g** Input - Frame Sync, Clock and Serializer Rx
! C5 q) F: b3 f** Output - Serializer Tx is connected to the input of the codec 1 Z% I4 j0 O6 h" F4 i
*/
' x3 w5 C) a1 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 ?% {- [+ m+ j1 e4 V, V ?6 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 i* H& ?; `+ p3 e5 ]/ `) n
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 k/ z7 ]1 V$ O: H0 M8 \
| MCASP_PIN_ACLKX
$ ^: _' R, a5 u3 B* P5 x: i6 m| MCASP_PIN_AHCLKX |* i t8 q3 d( K9 ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 Z2 g/ [( J, k' |4 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + R* A, N7 t5 K8 @ o9 j9 P# G* E
| MCASP_TX_CLKFAIL
+ k4 i; N& o7 p7 o5 T: H4 G| MCASP_TX_SYNCERROR9 |9 P$ e& i6 Z) m$ T% H1 Q0 S9 y0 Q% [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 Y5 g6 _5 t3 |6 j. K
| MCASP_RX_CLKFAIL
0 F/ m. z( f& z( N+ D) L2 j3 }| MCASP_RX_SYNCERROR
* F. L" v, {9 k2 u! s" s( u9 b% X0 \8 K| MCASP_RX_OVERRUN);# q+ Z, b5 R6 L4 W2 R5 i
} static void I2SDataTxRxActivate(void)" |; i, ?# g# z0 f7 _3 _
{
( a- q: S K4 `* Q) r: v" ~/* Start the clocks */
. m6 h0 }) _5 G* ?/ B jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) F, a: D- F1 _, Z8 U& A( [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
* b9 y5 _! Z( ?+ e+ v. j& M/ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 T; e' P: \. K' u) qEDMA3_TRIG_MODE_EVENT);: _* n9 `" I3 [/ `- a5 f! G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ?7 \* A( o5 {4 N& VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
D1 l+ i% L, ^; LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 e) a; k( S/ m( c3 x% Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ I! ?. f' r& q" ?$ A1 lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 v" j$ H# A% J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& {7 A" u8 | y1 p* f- ^0 m. t5 o) HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}# k5 @ C" y} ; |/ `* E) M. `& a0 e) j% \# g9 `
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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