MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
7 r6 F0 G; M% Zinput mcasp_aclkx,
- Y7 u! B  `# o, Cinput axr0,

output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
/ i+ a# Z7 T1 D5 L# doutput axr1,

assign mcasp_afsr = mcasp_afsx;
" Z' t4 w1 p# R  C2 x6 C# X3 K, oassign mcasp_aclkr = mcasp_aclkx;
3 A2 S# E8 F5 \4 k& K# rassign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

. d- }: Z/ i, z% d
8 B- M3 g' G! ?) A

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

' ^; {8 Y# J1 R$ S+ S

static void McASPI2SConfigure(void)
1 p2 H! p' N. s2 N9 a{
9 S- `3 ^% @3 k8 ~& E& F( K0 e6 g- xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
5 i1 A) U7 Z6 V! `6 zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% P7 }7 Q3 ^+ X% ?% v4 `! Y+ ]MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% M$ q8 O. m6 k9 FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ n1 P% y8 Y" }# m# CMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
  |4 ]; V  j% `3 |4 TMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- O- O3 ^# N! B7 O: O# _+ u) ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) n  [% K! T9 ~' }( _3 E# u) r0x00, 0xFF);

/* configure the clock for transmitter */
/ g9 l' Y0 \; B* cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 a% C% |! W# O/ h5 W7 M: AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
4 F% t; w+ N7 \# T/ D% h1 e9 a
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
( m4 X2 P0 |# `) `** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% b6 ^9 `  B6 x: l  G+ B* |, tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
0 V2 }7 k( n$ h** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
# q- N5 K+ p; u*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
8 h" |4 }6 {* Q  M| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
3 v) V! ], m  h2 K* Z$ {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
* [2 m7 _9 e8 E# G% A9 s1 N- x# p| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
. I. l5 v/ U4 G| MCASP_RX_SYNCERROR
4 i: l$ B3 V% X& [8 V$ ]) L| MCASP_RX_OVERRUN);
4 D" O/ O6 }! Y' a}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
; S$ Z0 k1 V, l. J4 n' O. NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 {+ U. N: a# L2 C( rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
6 b9 M  o6 J- i$ \' p& QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
3 _! h0 M7 m7 P" B+ u1 F9 B9 B( hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ y0 V: p% F( ^4 [) HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
  ^  x& |4 S1 S6 A: O}

3 r& }* Z1 R, `# g* w/ B

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.