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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% S2 m9 u5 o9 yinput mcasp_ahclkx,4 V7 ?9 G! n. o0 f
input mcasp_aclkx,( G1 _9 O* h/ g9 a$ Y, g q; w
input axr0,
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output mcasp_afsr,
1 ^. W0 \" b1 D7 t3 J6 e4 ~" z. boutput mcasp_ahclkr,: L0 V% l% ]% `2 O6 ?/ V& r
output mcasp_aclkr,
# s- j, b% X. w6 m* joutput axr1,) D( n: z$ R6 H; w* H, }; G3 V
assign mcasp_afsr = mcasp_afsx;3 `: o" F! e9 g. ]5 @; L
assign mcasp_aclkr = mcasp_aclkx;- e q" Q c$ @( s- n: l- q7 W4 _/ H
assign mcasp_ahclkr = mcasp_ahclkx;
d6 Z3 t- [9 _$ f- Eassign axr1 = axr0; " [/ M; j* q- z" Y+ N
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 L2 M: C( g( G& p* l
static void McASPI2SConfigure(void). |9 u3 [5 J# U0 w
{
% @# O; P" L5 n9 iMcASPRxReset(SOC_MCASP_0_CTRL_REGS);4 p; G, H2 m+ T+ V w* E z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 a5 r; }: e' P8 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ ~* C; J4 e9 ~, TMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% S- c' m+ f% _: y6 ^9 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ F# k; t: f* @* ]: H. ?MCASP_RX_MODE_DMA);
* g9 v& ~1 y: x0 R- ]* OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ j8 F: M$ x# P! H$ q" VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( l" N6 t* Y! wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* m; o& n7 b. d. \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 X# V4 [9 B8 t# G2 `8 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 Y" K- \5 l2 R4 i' K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' R7 r1 o, g/ \4 f, ~9 kMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% L, K. x/ |/ Y7 b0 e. VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
i+ M6 V) P4 M9 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 X& D. Z) Q7 |+ ?( f" m% f" u
0x00, 0xFF); /* configure the clock for transmitter */
8 s/ f8 H+ b% F7 z; {- m6 rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 w: {# z3 K" A4 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" a: A# p- H' @% L+ qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! v* ]6 X8 Z: W
0x00, 0xFF);- Q/ E' X8 J, c6 T1 D
! z: h0 j L# `" G, Y/* Enable synchronization of RX and TX sections */ 3 V4 g8 f3 U" I9 }) c) c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 A5 |% \1 x% F. @7 t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 f' D' Q& w$ R' `3 d4 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** U/ y' t; e$ E: T4 u% \7 y- Z
** Set the serializers, Currently only one serializer is set as7 V. |! ~4 G2 J
** transmitter and one serializer as receiver.; r" N* X5 ]# `4 y( R- [6 p
*/
5 o+ Q W" J, v. o7 S+ @. ?) A$ CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 Q. K2 z4 j- V: o9 O# e7 g
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; A$ w( w, h# b& ^( z7 B
** Configure the McASP pins * m2 @$ A6 c! p1 _$ h
** Input - Frame Sync, Clock and Serializer Rx9 {* |6 K; E. e% M7 W
** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) R* A' w( P3 B o/ c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 o7 w7 J4 ^9 c) ~( F7 d; pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ l9 H* c' @6 V9 _| MCASP_PIN_ACLKX
7 X5 u! A8 ~: d4 t; o/ ^# I| MCASP_PIN_AHCLKX
, a" w: |) w: ]5 E8 v- W9 M8 f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' _- d e- \0 F' x
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
U# E' [) O: n% F0 W3 T" \7 r2 F| MCASP_TX_CLKFAIL 0 s$ q5 X0 ^' A/ }: ?" H
| MCASP_TX_SYNCERROR/ I1 k3 f& Q3 p, r, m' f+ E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. k, }+ S$ N# E- W! Y; h| MCASP_RX_CLKFAIL
?% t6 w/ S5 \| MCASP_RX_SYNCERROR # y! n6 H- k: G& p
| MCASP_RX_OVERRUN);9 a2 n# L, _# H! m8 I0 L
} static void I2SDataTxRxActivate(void)* Z2 r( I/ ^5 o! g
{0 o. m l6 f2 Q5 C* ]
/* Start the clocks */, b$ {9 E" _( m& h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ @6 I" \ {; B3 B, n2 X
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 ?: s9 c- p, _0 e* L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* d1 l- B. r4 E4 j# x" l
EDMA3_TRIG_MODE_EVENT);% L# e: P8 v1 c3 K: F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " h* X& y5 Z' T! I* ] O$ j1 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: K- o6 B( C* ~9 LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( r% D" K; g3 ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; R, ]% g2 f- H5 ]+ Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 |; q) T' I7 Z- X) zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 s( O$ G( y! f1 K4 a3 E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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