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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) ~9 F t: p8 N
input mcasp_ahclkx,* J! q* q+ Y! o* R3 b
input mcasp_aclkx,
) W! a5 x' c$ r8 D: `input axr0,
1 R! S+ R S+ N z2 l! `, w9 U% W; |! j
output mcasp_afsr,
. L9 [7 n2 r( K: L/ Woutput mcasp_ahclkr,4 w n2 u/ o4 u8 z9 D6 x
output mcasp_aclkr,
4 B* D! Y- x1 @3 \! K) ~output axr1,
1 f+ Q4 a0 R- d' T! v assign mcasp_afsr = mcasp_afsx;7 e1 t6 C3 ?1 M$ g% c
assign mcasp_aclkr = mcasp_aclkx;
7 D1 }4 m+ n, n- w1 ^1 Xassign mcasp_ahclkr = mcasp_ahclkx;3 C9 J2 [6 |9 Z" A1 E
assign axr1 = axr0; " ]4 l& @! h' ]! N2 K
' f, |' w; a' y( k4 M& w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; \4 x5 T# C3 d8 ?1 P5 \3 t0 w0 F
static void McASPI2SConfigure(void)
. n$ Y& j% d7 B{: `: S& c6 R& k1 s0 Q% \, ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" B! m: M$ c0 ^1 F) b5 m9 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% l4 N( I7 R! e- w+ X- d( s* g4 d
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 C+ s$ B7 x! r5 _5 R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 N: R4 q. P! D: q5 \McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* b: u3 U; c2 m& _
MCASP_RX_MODE_DMA);
& }0 s1 L2 q+ lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 a4 a2 r* f3 H b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" T) R% s2 C4 f, k3 T/ G, Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / U) a" x1 E% ?' z0 p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ Q" A% D5 P4 A: Q0 c0 |& O) B0 ?" mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , n3 V) m7 |8 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) `4 }! V' a7 [5 S) ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 \* S% M1 s9 Z8 J0 q- r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' A* N; b% W. @2 A' N7 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; j9 n7 h& I, H' _" |# I! S, I$ a0x00, 0xFF); /* configure the clock for transmitter */3 D' X S0 p- w; G. f3 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 a$ T7 E/ `6 g9 X8 J$ g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 B2 e& x# A, t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ E) p, ^) W5 e6 w' N6 I
0x00, 0xFF);
! q, X# v2 h* ~( x& D1 s
* Y# S' P4 E. G# v+ j) `3 r* ^/* Enable synchronization of RX and TX sections */
6 E$ X0 D* n* B0 S7 I5 yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ l5 p. S8 _7 X4 i3 [6 L* e& }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 ^+ H' X: g$ D8 g$ x
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 C# R' g. [8 p; K) a3 A6 l* Q( v** Set the serializers, Currently only one serializer is set as
$ t: S1 b! d) o% f& x** transmitter and one serializer as receiver.( |" L8 M( M2 r! d- U9 |% F7 `
*/
t' W( m5 n% I; ]3 _9 X" OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% S; g k+ }2 r; JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 E' i6 w' ], T$ q! G$ n3 F' m' O** Configure the McASP pins & a3 ], _; e3 b
** Input - Frame Sync, Clock and Serializer Rx: n3 e! ~/ `' [6 A* `! G$ i6 x
** Output - Serializer Tx is connected to the input of the codec
! K# J5 i" z/ w3 ]" N! Z- T*/
- q4 z3 c3 F, e7 _) l, y3 i5 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ b/ s( I( }, l. a) Q" PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 b7 i5 {+ e& k- }- m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ `% p5 V. u5 _: b* L; c- Z| MCASP_PIN_ACLKX
- q. }4 f+ i Q1 ^+ P6 x| MCASP_PIN_AHCLKX
6 |7 ~. b( z+ e; o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# w1 K9 {0 E/ c8 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 ` K) m* B, c8 j| MCASP_TX_CLKFAIL
$ ]4 _8 T0 z4 y9 M+ K6 b| MCASP_TX_SYNCERROR8 l9 \* O* D y' l* Y, t+ G' t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ x. T" j7 Q9 ]5 ?
| MCASP_RX_CLKFAIL5 x' F2 x5 r- V. @. w; Q6 E
| MCASP_RX_SYNCERROR 4 h( V+ ?2 b8 }) r# K# U
| MCASP_RX_OVERRUN);
0 Q; n' d2 ]8 I/ `3 v( G4 q" D3 ~} static void I2SDataTxRxActivate(void) d K/ P- @8 A, Y7 w: W7 P3 m
{
" n0 E0 d% \/ ?/* Start the clocks */3 Z/ i8 l1 ^" s! M, ]2 C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 J3 P9 h6 A& V: t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 }5 p# g; ^. G4 T ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 D* n% @6 Z- q4 Y
EDMA3_TRIG_MODE_EVENT);
0 ~3 }6 ` l3 q7 ^! w. J% H3 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ p, y1 `: ?; N4 u [* Q2 p: B, eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) w! T8 T+ M4 X5 r% \/ d$ d5 W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& j9 p( o Z$ v; ]% l! z G& k! b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! |* a7 I5 E* `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: {2 N: q- Y7 J) g: Y4 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. d2 G, K; }7 N. i" f! H/ JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! f9 J0 p) z v+ j}
- z1 ]' o- R+ v) z/ o6 c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 b- J) Z- X, ^/ ~5 Y
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