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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ P; Q' B6 }4 U8 s7 x7 zinput mcasp_ahclkx,# N4 y/ j A1 p4 V* ]
input mcasp_aclkx,
' p" o6 Z* @2 L% j4 |: L xinput axr0,
# Z& I% R& E e9 ?( K l: }* H" [$ R6 ?, B4 G( g+ M. j
output mcasp_afsr,
/ s' z1 w1 a! A; Z3 d0 poutput mcasp_ahclkr,
, K0 m8 a! Z" |output mcasp_aclkr," }: Z) t1 s+ V8 x; K# h
output axr1,$ o7 t# }% B, g" X& {
assign mcasp_afsr = mcasp_afsx;
; M8 `6 s- ]3 q n; f# C% hassign mcasp_aclkr = mcasp_aclkx;
0 \$ o+ e; Z. N$ j% N, Qassign mcasp_ahclkr = mcasp_ahclkx;% l" M" a" H0 w3 m
assign axr1 = axr0;
. C, F% C; J0 s
9 D* e0 u" }+ t2 r: z8 A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " t# v7 W) U! e. v. g
static void McASPI2SConfigure(void)" j! z- [# m6 d( e' r
{2 |2 W) v+ I$ S' U( D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- K7 B' j! Z" y7 L) XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 Q q9 D- {" O$ I" c. |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 @' V( D5 U) T8 C3 P9 y1 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ r: Y$ P# r5 M* C: o& | j j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ O0 J, t8 C3 {9 Q- ]) t bMCASP_RX_MODE_DMA);2 D, \/ p0 L7 Y7 [' L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 O& \+ j( a* _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 w$ ]2 j; x6 R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 M* W% p( p6 a$ ?+ d* n. qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ L8 V: g) D: F# g5 E5 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 {) E. ]: T3 j3 ^3 w6 A0 o2 s' _) ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 j, E, ~+ A: E: k% t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- p& |8 i3 {9 ?$ m5 p6 F+ ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 r* F5 B5 [5 _& |6 u- rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& c- M* h- m: X; x( t+ j6 r
0x00, 0xFF); /* configure the clock for transmitter */9 h5 |* B8 X' O3 K2 F7 p0 k6 U
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ }, T2 ^' o. T: y8 t1 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) t8 a" w9 ], V8 R( VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, [6 F4 P2 A% m$ [. \, d0x00, 0xFF);" E6 u% j* J- w& i) I# A2 y
% ~9 [/ R f* {
/* Enable synchronization of RX and TX sections */
' U+ ^5 |) x+ I1 r; S2 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 x+ {+ j0 V( ^( R% \7 K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 {& V% ], v" l# oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 q0 @4 V, b/ f7 Q+ ~
** Set the serializers, Currently only one serializer is set as
' q& J/ c( }$ T** transmitter and one serializer as receiver.
: }3 i9 M% U- b! F*/ B1 C5 c, H: q6 ?! _6 o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" B- O- P/ f7 W" [, P8 q! b( |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. }- G. K6 [. a: I0 `; M
** Configure the McASP pins , R, S; i" x8 e' `4 n; m# I: n( C; M
** Input - Frame Sync, Clock and Serializer Rx
# Y: A4 e. p8 I8 k) c** Output - Serializer Tx is connected to the input of the codec
5 Y$ X4 z5 S$ \. L*/( z; l8 B5 c! [3 @0 ^! h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) I3 |, Q# Q) ]4 q& c, t6 S. e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ t# O% Y( F" _0 e; ^$ w; mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" q2 R: ?! O. l3 ?1 J' O* y
| MCASP_PIN_ACLKX
; B; t( X- n. {| MCASP_PIN_AHCLKX: ~( c" y# _1 G# i6 T/ o2 H: \; ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 X: r4 p$ m# `2 i; y. W
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' Q3 o7 ^$ R% q| MCASP_TX_CLKFAIL ! I& F2 z0 U3 [0 P4 C) E b; v
| MCASP_TX_SYNCERROR
5 a4 ?, @$ F5 w _: e9 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& d2 L3 N, R# D5 B* R/ b8 j| MCASP_RX_CLKFAIL! B* |' ~9 K5 \% H2 J! P
| MCASP_RX_SYNCERROR / z# b$ S& }3 R# D
| MCASP_RX_OVERRUN);
2 L5 g, {( }2 K9 _* ?2 Q} static void I2SDataTxRxActivate(void)) @5 ~' J5 D5 }7 R; C
{
2 E6 a, e R9 G8 A. c; q/* Start the clocks */
! Q A; ]* f; i# @ U% XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# Q! {3 w4 Z- o, ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' W6 L) X1 g1 d3 s4 E* }8 HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, Y! I8 e& v5 o2 y4 I) M4 }
EDMA3_TRIG_MODE_EVENT);( d9 K' B2 P" e; X. e% \) Q# K% O5 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* v! ~& L# w# Q7 ?1 q. AEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 u- g2 T5 K% e, q; sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 H# y' a- a, z- S# j& C0 U: m5 yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 h, O$ b0 S- ?+ G2 s2 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 S% m8 ^6 L0 J3 B2 OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; h! k6 @5 j1 V9 e3 o* L1 V0 ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}* U7 H. l! s2 U+ T$ G' l6 s+ F} ^+ M0 K# Y& E4 I% F# v& ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 s% v; k! l; w2 y6 ?
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