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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- I% W; N8 a6 Ainput mcasp_ahclkx,
6 r9 }2 C0 Z. Y! pinput mcasp_aclkx,
9 n o% y7 _4 ^input axr0,
5 n4 }( c! h) s( D; J
: g, ?* t4 ]# T+ P5 G2 Q- \output mcasp_afsr,
. a/ V8 m: B& g' V9 Foutput mcasp_ahclkr,
! ^ F/ p- l' g/ }8 X9 Zoutput mcasp_aclkr,
, k4 j, r/ w! n6 Q4 t- ^output axr1,+ a+ k8 D7 V5 J0 l. z2 i) s. D; N
assign mcasp_afsr = mcasp_afsx;9 h9 X9 [& `$ [# m0 |1 i
assign mcasp_aclkr = mcasp_aclkx;7 {+ g: H; t9 R* D
assign mcasp_ahclkr = mcasp_ahclkx;
5 g W; c; m5 y; H H. A. U; e3 oassign axr1 = axr0; : g* o9 k3 q3 J) w" r- T# _% R; N
+ o2 w6 S" m) W1 i. l, \: V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " j0 h. u$ r0 e7 m& H
static void McASPI2SConfigure(void)
# f. m. g9 U4 g* H" c{
' p7 `4 V/ j- M0 P" UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" \$ m. P! o8 S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 o" T9 W2 Q8 E3 g7 L6 j; \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# n: g3 i, a+ X# NMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* }: p9 E8 a i, ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ a" N I& Y7 l% H) z
MCASP_RX_MODE_DMA);
$ V$ x* U7 a3 M; w. n$ I/ u* x( r' gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& l( u0 o/ K) h7 A) a: eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; K/ y) _1 Q& G2 JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' x% k- m! M* x& |6 L6 jMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 f3 u; k# P6 q! d+ P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 @$ _0 C* f( c2 @+ u& X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- o3 f5 X# z& ^0 v
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 d6 U" X7 R9 o4 {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 N& [; H ?" m3 F/ ~7 ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- \9 m0 d# Q2 F0x00, 0xFF); /* configure the clock for transmitter *// K+ p6 C& o! J. _8 `0 h# p5 |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ d+ Y. _1 }# lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( t+ }3 w6 S- i; K, ?) }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; h* |, [% z! ]. K+ o/ \0 q: W3 U0x00, 0xFF);
1 t2 ?- P; ^) s% V( H1 b& l
& {6 g! q; s. \/ a) J, O2 @/* Enable synchronization of RX and TX sections */
+ J; O4 H/ X% S* Y! TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 C/ i5 y3 i9 E; S1 xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" [# `, @$ C/ \' e& z, E0 ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' h: F0 ]6 u: i/ t** Set the serializers, Currently only one serializer is set as Z' i% E. t ]
** transmitter and one serializer as receiver.$ U& ~* w, k& H% P) `4 |4 r
*/+ {7 K% @2 ?' f- O$ Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 M# o) G* Q8 C: j* qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ F! \7 v* G9 h& J5 g0 _
** Configure the McASP pins
8 r R# {& x- Q# \) l& s( X5 z** Input - Frame Sync, Clock and Serializer Rx) f0 X( B3 c! p1 T
** Output - Serializer Tx is connected to the input of the codec
6 w5 U# m* r/ a*/' [! @& ~! M9 b# n. C, w6 G" @3 I; o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% C1 a; G) { ^5 G8 F- \; W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 Q6 y) L7 H/ \8 Z6 U: g
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 G. f G4 C5 ?| MCASP_PIN_ACLKX
4 ~# L' H5 y. B7 @| MCASP_PIN_AHCLKX
! U, V9 u: \2 ^. Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. F7 A) M( U9 R% G6 d7 B% Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # \2 I& p5 l1 d7 Q- z
| MCASP_TX_CLKFAIL & }7 l0 M$ q9 a* x
| MCASP_TX_SYNCERROR: ~0 Q! H2 T: b/ @* V- W3 u A" U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ i3 S' r7 E4 V- E3 B) ^: ?| MCASP_RX_CLKFAIL
+ C$ Z ?! w, L& @; g2 V| MCASP_RX_SYNCERROR
( w9 |# }- y& M! M- M2 _ x% r$ Q| MCASP_RX_OVERRUN);- s7 [+ p2 V/ L+ q0 O; Q
} static void I2SDataTxRxActivate(void)+ S8 C6 ]( H. Y$ Y
{
3 w! f, S; o4 W' P- p- R6 z/* Start the clocks */
5 H2 m( ~2 Z- A) f$ j1 M7 E. MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) [) S! n$ V' C8 R; W% GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: h& c' @3 }0 B! N7 E* b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 b3 O( e+ D) tEDMA3_TRIG_MODE_EVENT);( @3 A8 G1 K: _9 d6 n4 H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# f7 x$ i' M6 I: TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 \, [; l9 y8 f7 N3 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 K6 j* r3 ]9 S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. b, R: O5 M* d3 y- M2 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: q/ W2 S$ m: v! N6 S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ |2 W* t8 @) G$ u+ O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 t! z( L8 g0 q% K
}
; L% w. q0 n: A' z- e. _* c请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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