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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
o! H3 ]& }) G' q8 P( e3 ^input mcasp_ahclkx,
+ x% u& M6 b0 b/ w/ ainput mcasp_aclkx,
& u" O1 v5 [1 K" W* D7 l+ X o6 U3 m& _input axr0,. r5 r# e+ P1 A# p- t
" y3 C- O! Z$ c9 U& e6 ~
output mcasp_afsr,* y U; Y; A, _% v
output mcasp_ahclkr," Y/ k4 a; h5 m. h1 I% x9 G
output mcasp_aclkr,
5 L, n! _+ g+ ^9 Z8 C% _output axr1,
3 t6 r6 G+ u8 W1 Z; K assign mcasp_afsr = mcasp_afsx;
! _) ?! T. x- C7 `3 G9 Lassign mcasp_aclkr = mcasp_aclkx;
( L( J" D; \/ {9 {" Uassign mcasp_ahclkr = mcasp_ahclkx;
: r0 K2 r7 ]8 I2 m% k1 O; aassign axr1 = axr0; ' I1 m! `! Q7 H
" C! C7 h2 Q/ S7 I: M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- v3 P- W6 a# [; ystatic void McASPI2SConfigure(void)2 K2 K0 b u/ M& d
{
0 K3 d, A$ _: QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) y. A9 d% D; m( I! a! o4 f8 T% v& f# ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 o, A0 S+ x! X$ p ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% S3 `( s9 e7 s+ O8 ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. c' j9 |8 ]% A2 \3 T$ _3 L8 A$ TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) T2 l1 j; [5 }2 W7 H3 T# ]9 }
MCASP_RX_MODE_DMA);
, o# p) Z" a" G6 u. U6 u2 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, L# g A# y# `: {. J4 U9 d4 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 T& |. |# b& g. K! q7 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / x9 }2 ~$ G! d$ v+ j% f7 v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" f* J/ c- A7 v* U/ _McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 T/ }( r8 m$ q- ?
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) I7 Z) g7 x) n$ A/ a) z+ w+ e9 _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ ]% ~6 |% U' s* M* i+ l6 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 u- w. K1 ~9 R& X6 Z `) @& Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) @; [. O9 p2 d9 Z$ ?; e0x00, 0xFF); /* configure the clock for transmitter */
/ Q/ S8 T# I6 n7 `6 X" ^4 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 q0 a/ C2 ] p* bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 b4 A0 t S" w3 b$ Z0 j" W+ _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0 @2 Q# v, S$ j: P3 Z7 ^0x00, 0xFF); k. S5 @1 _* L$ ~& _
/ o" x" y) a; h/ Q' | D/* Enable synchronization of RX and TX sections */
7 [8 U. a( r( ?3 {3 j- A0 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* p% Z) g0 A0 _+ h1 g6 ?; l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ C" {9 Z& O/ ?6 ?7 [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 m$ f* [# c1 f7 V** Set the serializers, Currently only one serializer is set as
! }0 d7 X5 S; t7 X! g6 @** transmitter and one serializer as receiver.
6 [& h- j' |* M( |' i*/% d9 Q2 w/ s& w% c2 I0 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ z7 w# }' ]9 {7 t3 {, y( K z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 U! i( p# n3 h8 d0 }** Configure the McASP pins
: F* E+ |% G) U- ]9 s& @8 E" ~& g9 }+ L; j** Input - Frame Sync, Clock and Serializer Rx9 l1 D. R3 M3 y- k
** Output - Serializer Tx is connected to the input of the codec
) X8 R# ?0 q2 u2 e*/
/ E# E' V. U1 J: p7 V4 L" fMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! `% h+ \2 q/ m3 H% G9 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ E3 R: g7 a2 m6 S* [' k- x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: G7 f! p" n$ x/ \7 Y) C" Y| MCASP_PIN_ACLKX
% j; l% Q5 ~- D$ b$ ]( w| MCASP_PIN_AHCLKX
$ o% Q) W! ^1 l6 g& y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" c1 S$ p" p( X0 e. k3 K5 K) |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( b1 A; T) x# p. C2 i Z+ X| MCASP_TX_CLKFAIL / h- j* z h' C1 p; D d g+ k
| MCASP_TX_SYNCERROR* m4 J; W w8 i$ z) q O' l# i4 T- e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 m- P6 x; I6 A! W- [0 [9 A| MCASP_RX_CLKFAIL1 `: }4 [1 c' a& J- g
| MCASP_RX_SYNCERROR
) n( W0 x% j4 w" J. u| MCASP_RX_OVERRUN);6 U o8 G) I4 [" z1 |4 ~
} static void I2SDataTxRxActivate(void), T4 F8 Q/ @( m+ i. l
{
5 y5 z+ e8 m) b1 L! g/* Start the clocks */
5 L1 ?7 c" Q+ H. _: tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: W8 P/ {' ?+ C$ B: ]7 Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: S) n) z! ^1 v* x4 ~, w4 |- j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) e# U/ ~& `/ z8 d8 H/ FEDMA3_TRIG_MODE_EVENT);3 h7 }- I9 S! I2 S( B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! s _* M% ^- c7 k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% |7 g- _$ A- q0 p; Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 E* y6 D2 F) A4 l& }9 p6 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. j) e. h. }* ]. N6 E) _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ G; S% e! I& X, o# H5 u) O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: D' U( ]. ], S0 @/ x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ O+ `: I, r" I% f} 9 |2 Y7 H* G# Q: C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 }; I6 {* |0 o$ q1 O
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