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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 W2 U; @3 x( j8 Dinput mcasp_ahclkx,
0 i) h4 h, E4 @+ C3 W; ~input mcasp_aclkx,
' K I( ^3 C; V5 z# F7 Iinput axr0,
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, e5 d5 x) _) u. m7 ^output mcasp_afsr,4 q4 Y3 C: U* e$ |; L0 }8 b5 s
output mcasp_ahclkr,
3 Z/ ` ?, O8 z, }output mcasp_aclkr, c" }+ _% N# P
output axr1,7 V. C0 H; O# |( i
assign mcasp_afsr = mcasp_afsx;
s3 F" Z3 f* C+ Passign mcasp_aclkr = mcasp_aclkx;
4 j, }, S# ^; G1 _assign mcasp_ahclkr = mcasp_ahclkx;- u7 x. o3 @( d4 p: J
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " Z: \% e4 q4 w9 r. x' s* d9 v
static void McASPI2SConfigure(void)5 i+ f6 j. [0 I2 {
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 ? L3 U; W. c& z% b+ c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 H! _- d9 }! O% g }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* D ~$ U/ y8 n7 s' o, T) g ~8 W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- ~8 j& N J$ Z4 {% L- B7 E! q4 O
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 H# [; K3 u! S4 u* k0 P3 ]" o
MCASP_RX_MODE_DMA);
+ ?% L9 l w' L* YMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ M: U8 H G) [, `% r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, Z8 C4 r. H. Q: P! \, n4 yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 M; X% U0 ?* {7 N: ^- [' W+ h
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* U- P( W3 p2 M0 p- b' xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% {# I% q& M/ n7 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( O. j$ g' w7 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
i% t6 n! x l9 Y' f; NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . K x4 x# a$ ]3 z5 Y& J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' x, K- g$ A# n8 S4 c) Z8 h) Z% F0x00, 0xFF); /* configure the clock for transmitter */
" {$ E: S" }; W* Q9 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, |* q9 I; Z5 c. P& n5 |( MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 q6 k* t4 u0 Y- l* xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% ^( [+ _& w) @" y% U4 Z% H; b- Z; A
0x00, 0xFF);. F3 j9 J* @' k, V: ^
+ o# \, e% @3 q/* Enable synchronization of RX and TX sections */ + ?* Z9 w& ]$ I F# o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" t x2 t$ N' }1 c/ C( ~+ k( {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 @' C# J' E5 N6 k
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 o- t6 E0 y+ S( v9 H1 d
** Set the serializers, Currently only one serializer is set as
, O7 h& \" R7 `! T- E7 ?! |( \** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 t6 \! N" |& ~% wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: {0 i* F$ w5 Z) O2 T** Configure the McASP pins
2 m( o" _& l3 I) J M( e. E** Input - Frame Sync, Clock and Serializer Rx
}7 |/ ?# W6 N** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& ]* q3 p, E' {8 `/ X0 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ v* b e2 b0 T" s: j9 oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
`4 |. |5 }3 m- o| MCASP_PIN_ACLKX* n, p- J* |, i$ p4 s% q
| MCASP_PIN_AHCLKX1 Z' }3 E6 d3 Y8 A5 I% T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' H7 M8 F) ^" U' U. v [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " \! |" |8 ^7 H
| MCASP_TX_CLKFAIL
3 l+ f, X! [+ V1 @+ u3 _" ?) a| MCASP_TX_SYNCERROR
1 f# V; Z" `, ?6 y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" Z; a* F |, x| MCASP_RX_CLKFAIL
9 x+ {) X( ~& m| MCASP_RX_SYNCERROR _, C( l z5 m' W' B
| MCASP_RX_OVERRUN);3 e+ `& t2 p" t7 o( g: g
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */( B2 n. q# m" E2 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 r' d1 \. f; Y; ]$ f( I# P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ Y( K4 U7 G# q0 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; T! k: c: T" H/ f3 R2 F
EDMA3_TRIG_MODE_EVENT);9 X1 s& s+ J7 g% m2 Q/ q3 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, O7 r0 V6 Z4 A" C& b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. T8 V" k# f% M: [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, r5 h! p7 U" H$ L8 z, p( w& l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. a# j% f5 c. x+ F. `, ]while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 \( H& s2 H. A4 x% i+ [ `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 U3 B7 [- ?* X$ GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" ^' j: g7 m& W/ @9 F}
: U1 L- F1 Y7 k& Q1 R( x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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