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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. _7 G- o8 u# A7 x) Iinput mcasp_ahclkx,0 F: r7 Z' y! D3 U6 Z5 I
input mcasp_aclkx,
; ]% l7 G2 S2 O$ s% b! V5 c( dinput axr0,
; d' v+ H. v9 u3 g! K
( c" e7 k; @% h8 c4 xoutput mcasp_afsr,
- _# r5 F i: W8 foutput mcasp_ahclkr,
7 D% v3 r2 ^/ `/ r$ |& i$ V. Routput mcasp_aclkr,: \/ Q1 A8 }# v& r' o
output axr1,& W5 G' p T; l$ Y- Q
assign mcasp_afsr = mcasp_afsx;
( W% D, {9 f2 k' tassign mcasp_aclkr = mcasp_aclkx;
* Y+ [9 r/ ^8 i- A# P* bassign mcasp_ahclkr = mcasp_ahclkx;
: U* H4 c, y7 J9 ^5 ~( passign axr1 = axr0;
. S' V: N- O k, ~/ _" H4 s2 @: t! r4 J# D4 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) ]) n( L5 r, W$ X1 O. P+ V
static void McASPI2SConfigure(void)- a/ [. ~/ m: t) \8 D9 O! [6 B
{
, g8 M5 p# O# f* fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 Q! n- B! R# a! K/ {1 pMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// V8 D) ] r; j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" n8 V' Z4 y7 Y- DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# n! a" g/ `, l. ~2 ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ h0 u$ j' h: l2 ]
MCASP_RX_MODE_DMA);: }% g8 c* s( q. T' W. p. y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: d/ l5 J, h: [7 I% G, WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! c$ Q6 B; @' ~7 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) J9 l. I7 [/ w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 v l! K$ p0 U/ P! g$ p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 R* x. a9 j" A0 bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 f' S0 H' ~8 P @! u3 s: qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 ?' |8 V0 ?% \& X5 Y; V; J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& l+ u$ B3 l) n4 R7 `$ G3 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 b& C# _/ s! y& J* L
0x00, 0xFF); /* configure the clock for transmitter */
% x u( ~% v& D& ^ pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- Q* U) k& p: O! A3 u* `; k T- r4 o
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 c- q+ O. {" G, R( e5 f6 K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ z& ^! Z# J$ \, @. j7 H0x00, 0xFF);
! t, h# a5 i/ p) V6 ]$ B! ^6 r3 O( Q( P" e8 |' \
/* Enable synchronization of RX and TX sections */
3 U5 n/ |, s: D0 DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; B+ l; ^) Q! e/ n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 `9 [% r+ ]1 |3 d e, _' M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# b) m+ _* j2 O; }' }+ d0 Y- z
** Set the serializers, Currently only one serializer is set as4 J' H. W& u E" ]' d% m
** transmitter and one serializer as receiver.
" j6 P P9 X' G! D D*/
$ v+ h9 [+ |: i3 Y Y2 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 H6 y+ p6 e1 w: @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' q' k- M: A$ ]4 \) ~% e: {4 _: T! w** Configure the McASP pins
) a' B9 v6 I! x$ W, p, x** Input - Frame Sync, Clock and Serializer Rx3 S+ ~2 V7 L# T+ Y) v& ]8 M
** Output - Serializer Tx is connected to the input of the codec
2 k7 L) A1 O5 t8 E2 d, p6 C4 h' H*/: U% Q. |5 _3 d) j/ J- r6 E1 k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 N, P2 J V, f, S+ \/ [0 hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 t/ [& x% A7 [! j$ [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 z5 T; O: v8 R8 d8 v
| MCASP_PIN_ACLKX e" s) N t, k, M% K
| MCASP_PIN_AHCLKX% I/ x0 [2 a2 {! o* ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" R4 M7 A1 S ~* d, SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 i4 w3 z/ o; R
| MCASP_TX_CLKFAIL
* b% q, S# I8 ^9 v! N| MCASP_TX_SYNCERROR
5 h6 S* @: ~; G& C. ]. k* q& O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# N1 S3 c( P4 n7 h4 ]. D S| MCASP_RX_CLKFAIL5 ~7 h0 K$ P, T" ^, C, [ A9 ~
| MCASP_RX_SYNCERROR 2 e2 X+ ]3 }1 y7 s4 O; P
| MCASP_RX_OVERRUN);) Y2 f4 F, B$ p* M
} static void I2SDataTxRxActivate(void)
5 c9 E! i* y' N. K; ^, m$ I9 E{
$ c2 v( K) l* J! o( f/* Start the clocks */
: p, {/ U8 Q$ H+ n6 w) DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. M# a) } l. i2 }2 l" @, x7 M) d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( X, s3 [1 I' F W1 o8 w/ @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. s( f) j0 c Z6 E
EDMA3_TRIG_MODE_EVENT);. F! D- p% C4 J4 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 {& L8 S; E0 c, n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" ^+ p7 g/ k$ ]) l# n/ j2 h& s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 S) H O" ?) L4 ~2 _5 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. v( U6 s3 g% mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 D( T9 y% t: s, h' M9 n( d' S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 K# O5 Q4 s& T4 ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 E9 p! W7 A9 G
} ( I( W7 a. b% d3 Y3 p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 ^% r/ G/ p" s+ u' y
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