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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 d) j# E% j ^1 w; B8 y& xinput mcasp_ahclkx,
* p$ a1 M- N2 U7 P2 J' Ninput mcasp_aclkx,1 p% g9 v/ u" {% K+ f; w5 @
input axr0,) R( B+ f* ?! L+ f- ?
! a; }% w3 Q( u# G
output mcasp_afsr,9 m& @9 S7 u) h- m; i8 v6 f
output mcasp_ahclkr,
- a$ j! i( N F# I8 s2 N& X$ routput mcasp_aclkr,
& R1 Y& T! B; e9 B% o8 _/ Aoutput axr1,
. X' z) e, i+ s3 v2 j6 I assign mcasp_afsr = mcasp_afsx;# T0 l) T( r& h0 U$ Z P
assign mcasp_aclkr = mcasp_aclkx;% @1 _1 y' t0 \/ d# G( T# n- G; g! W
assign mcasp_ahclkr = mcasp_ahclkx;
( K& X5 O! P& T7 h, bassign axr1 = axr0;
# ?) E o) i8 f, N( e
+ B2 C5 O5 O# p7 f: m' s! U6 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" c6 f: E7 S4 G2 T' `static void McASPI2SConfigure(void)
5 y" X( B, n. c1 p$ V# X; z3 l{5 M1 S+ h0 j+ m* w. c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: r0 d6 [3 C# Y* m( o- B8 a$ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! M& w2 q9 c$ ]4 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);9 r1 O$ H a K& {, ?! M3 z& n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) H( g' B0 T; A2 j: e9 \, {8 NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; K$ ?& q' B" B
MCASP_RX_MODE_DMA);
: {' V( H S: i/ y5 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. q* _2 K+ z+ }7 l. d+ l+ ]& q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 e5 t6 }% l+ d3 Q! P4 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - h% L( F" G( ?0 k" @. _7 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 S1 o4 {& e* a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 @+ e' R1 ?( [+ Y8 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, F% {. L0 X" t6 s* q! L, R P$ E! @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 u0 M0 k0 C1 E1 {: {. N$ ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); , S3 V, q" ?, m7 }1 Q8 F* D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 q0 Y: |$ |$ m, Q
0x00, 0xFF); /* configure the clock for transmitter */
7 k- C1 b& E* P& a: k9 r4 a. nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 s6 ^$ P* }* @0 t3 m" @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 K2 W0 b$ H' {- jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) I" ^+ T; u! p9 o0x00, 0xFF);
8 _( \+ u1 O9 [( M
0 i" M) q: y( V1 J8 Z$ O' U0 D8 P/* Enable synchronization of RX and TX sections */ - E n4 s2 T& S' j. \& t6 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. s+ K9 |: w. a. `1 k/ l( mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& @ S! Y( H* rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* |3 i4 @ M2 d5 } @** Set the serializers, Currently only one serializer is set as
! e5 _; q7 l9 H) _: L** transmitter and one serializer as receiver.
0 m' B" c5 J7 s1 y4 \% v; V+ m*/5 y$ M+ D) L% F% M2 ~* p7 n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 ?5 V N5 L) K3 D. F# o- |$ ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 y( J: b; s, D7 j. n5 b0 s. k
** Configure the McASP pins 9 s$ d4 s) \: q# |/ Z! [
** Input - Frame Sync, Clock and Serializer Rx
6 a4 X9 S/ B9 u2 g# L+ H6 S** Output - Serializer Tx is connected to the input of the codec
: Z5 f- g+ Q5 [! r3 M( R*/: s6 T8 R% ~2 X% Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 k `$ C% D/ @2 \1 U! ?- C" KMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% K& m/ r9 w& c7 _2 ?& UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* r( `% b" t" }6 q0 L| MCASP_PIN_ACLKX, J$ Z5 T5 f+ b* g+ U, {
| MCASP_PIN_AHCLKX
7 x: x- ~2 h! U% P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 ^. a+ J% |2 d0 t' KMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' V+ b9 ?/ a, H+ w8 i| MCASP_TX_CLKFAIL $ f+ U# \3 o* J# a4 R* o B
| MCASP_TX_SYNCERROR' v X/ s4 { n: b; \, w8 B" g
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; W% u* C5 } Z' G$ a| MCASP_RX_CLKFAIL/ o. {$ y3 I7 k
| MCASP_RX_SYNCERROR ( l4 U9 W% a4 i1 E& f
| MCASP_RX_OVERRUN);
M! Z2 z: M: O/ R8 K$ B0 ~} static void I2SDataTxRxActivate(void)
, ?3 [4 n- D( t; {{3 n7 c |# z) a! D/ ~
/* Start the clocks */' t! v) h4 p- S3 f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 B: R/ r; X; @+ E3 Y$ \6 Y) }2 B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( D! G6 `7 y3 R# m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( h1 k- Q9 x- P- i) iEDMA3_TRIG_MODE_EVENT);. e9 o% h+ D' i% v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ k3 \, W3 m0 ^4 B/ A' L; t7 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 W) X0 I$ {* N8 Z' T5 J3 B6 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; |4 ]& N& p! e5 y. w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: L9 d. o! \$ R2 n! t% u" R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. i& R6 k+ d0 J8 R0 q$ [" w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 Q b% v5 y# U3 j+ I; Y) ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 v8 P% o- `* X# w2 q5 W
} 4 c6 F7 z' K3 o; I7 U2 w3 ?8 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; t, w8 B4 h* a0 s% G
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