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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) q6 _$ a( k9 y8 s; s& I
input mcasp_ahclkx,5 v* T& {$ k: b/ M& r" j; k
input mcasp_aclkx,/ a1 {7 M- F9 l/ P4 C0 V
input axr0,
W3 B( h- Y0 d' E3 Q
7 y* Y! Q# b: J B0 ]output mcasp_afsr,
$ ]3 B {* G1 H" z8 Woutput mcasp_ahclkr,7 f7 S- d* S. C# g/ g4 G4 `: B9 P
output mcasp_aclkr,$ ~$ l9 x: I; k7 _
output axr1,
# m4 [; g4 `$ I: f4 _5 n assign mcasp_afsr = mcasp_afsx;
( V" i; L! s; z# P, Z; M% tassign mcasp_aclkr = mcasp_aclkx;) X1 |$ V* v5 E o: t/ I
assign mcasp_ahclkr = mcasp_ahclkx;4 M6 F: w% z' G. O
assign axr1 = axr0;
+ ~! U7 d. e8 d* H) f" s V/ T! H/ \3 j; x$ x# ^3 T3 R- Q4 \
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 P7 x! Y+ q# _! R. j6 ^5 n
static void McASPI2SConfigure(void)
4 G" ^4 @! W5 {4 k{
/ S" T% F+ N8 ~2 c& v5 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 Q8 P' j# @# [0 B* w; k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// Z: W! i7 `: p( w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* U( h( s0 N S6 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; A- R. i% Q/ s7 h6 p# F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 `; ~2 ^4 J7 Y% G" c& yMCASP_RX_MODE_DMA);
; {* k& _, V' w0 X; |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 \# Y- k) a/ v4 |% t! _+ T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 T0 t* }& F! n% J5 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% m. W0 J A% bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ g' ~+ v1 O; M$ T" M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 a: v' {) g2 H* _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 `, n+ `& r9 J0 U7 q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( \: J/ p6 G* ?; u# r! L1 H* g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " x5 R- d* A. I1 a# J! x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ F$ D, {6 N! G7 f1 b1 P0 E0x00, 0xFF); /* configure the clock for transmitter */
+ ?( O! A1 e" E& Y8 D% Z! l7 HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# y; I) p) i% G% |4 n2 J2 i& r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 c3 s1 @' c# ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, @8 h2 d% X8 {" J( e
0x00, 0xFF);3 r1 S" m L' ]
# n7 f5 I" K+ a( y7 b' g/* Enable synchronization of RX and TX sections */ . r8 R. I/ c5 {. p- p: ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
N; H/ p0 s3 O0 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. V, E- i: G. O( ^6 Y' v& NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- u9 C1 i7 x5 n. o% n1 K** Set the serializers, Currently only one serializer is set as; A. Z2 T6 ^- J' ]& |# o& ]
** transmitter and one serializer as receiver.
1 X2 D) Y; u3 c$ E s% ~# I*/
5 f5 h9 a: R9 l8 l: {- ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" V% g/ E1 r# ?5 F& e4 ^/ S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- C; V# W4 d; n. ?1 \0 q, G
** Configure the McASP pins U) c% w+ u ^6 M4 w- R: n- @
** Input - Frame Sync, Clock and Serializer Rx V5 x$ q* N# y5 f& s9 k3 ?4 Z/ P
** Output - Serializer Tx is connected to the input of the codec
6 X/ M" T# K( j0 {*/
5 w2 b2 G9 ]7 T N r7 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; F0 |7 e M U8 c) H2 y5 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" F' {3 R5 j, G9 C3 p7 |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 U9 U* {( n% z0 w
| MCASP_PIN_ACLKX+ a3 i$ E9 e/ X
| MCASP_PIN_AHCLKX
* y5 n3 ~$ a+ _* F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- \% ?( Y @; `; h: j( lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: o( H- `. E2 n4 y- ?| MCASP_TX_CLKFAIL 8 w4 F) _7 {+ l- C! b' v% S+ ?
| MCASP_TX_SYNCERROR" Y" z1 B0 R% [0 }* X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 r' E; [) n, z4 S2 f
| MCASP_RX_CLKFAIL
) ~: K9 F/ t! ]$ m4 X| MCASP_RX_SYNCERROR
& I% g0 B ]0 }! g! t| MCASP_RX_OVERRUN);
5 q/ F8 Q1 ?0 E7 U+ O* W( n& e! t7 B& I} static void I2SDataTxRxActivate(void)" c+ |/ b% U* n/ {, a
{3 J5 w( z2 p$ l" D
/* Start the clocks */
7 y# A W; s6 @/ ~% FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 b& |+ x0 V7 s' c4 }6 E0 b; r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 M6 R3 `( G6 {( u3 @, S. {0 }. XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 m, H: d6 C& f+ \0 s/ _; eEDMA3_TRIG_MODE_EVENT);) C' ~/ T! r2 @ Q0 w' h5 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ K3 n* k# f" _% x6 }$ S% Y8 Q1 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. ^! O" ]0 l6 e# E3 z/ Z0 g/ M% H$ c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- f s$ v. ]7 _9 {! RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ Z7 z/ D& S: ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) W8 K2 ]7 ]$ h* N F! vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ W% e% `! l2 L' Q# K! x/ V9 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 P# H8 G* T5 Z2 `) _( u2 u" ?
}
- z5 g/ W8 f( S5 L4 s& _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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