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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ L# M7 {( h! l2 V6 x8 Ninput mcasp_ahclkx,3 H5 W6 p; a. j f5 o! ` V
input mcasp_aclkx," m% e0 V) M, b; l2 ^3 p I3 s+ j
input axr0,
, S4 c; f3 Y8 H! [
1 Q2 k" }' f- f1 woutput mcasp_afsr, z/ I' g5 S0 [! H# ^7 g
output mcasp_ahclkr,, V; t7 R9 [, i
output mcasp_aclkr,
$ b! Z/ @9 b1 H/ t3 Y0 ioutput axr1,
& @7 n3 |" Q( z1 O2 F4 _0 W( @# `& d! c assign mcasp_afsr = mcasp_afsx;
L- e1 J# \1 {% m" u; G$ ]1 yassign mcasp_aclkr = mcasp_aclkx;
' y6 N0 p0 G, }/ l1 o# Sassign mcasp_ahclkr = mcasp_ahclkx;
/ V% u, J! \1 H0 x9 massign axr1 = axr0;
5 U* H3 h( o# V; ?+ L; o& k4 ~, G* p( m6 W" q& Q; m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 l3 x& V) G: Y: e$ cstatic void McASPI2SConfigure(void)$ S* s9 s3 J' Q, P4 {8 {
{% R: B- l0 d8 |+ z, J" H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; Z4 ~8 ^4 V2 e9 c, tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 h! B$ h% r* i8 `, J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ F+ C; w7 x2 {% J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# u+ m1 o$ J4 K6 z \' C
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," h. m* }( o# Y/ u5 p4 [
MCASP_RX_MODE_DMA);
9 [) h+ j3 d9 _0 UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ]' T! d. r# [3 ^% K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. C+ \+ ^; \3 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , Y- ^7 |5 L" I! Y$ {0 U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. J$ ~: j0 G% {' ^
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& |# i+ ^: G4 L7 M/ q" J* G% {" d4 ]) g+ hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 ]! @2 c" E' h- @9 i1 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
B! U7 h9 v. u5 m0 DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + }/ n F( D# ~9 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; A5 ?5 |' V) Y8 k* d0x00, 0xFF); /* configure the clock for transmitter */9 _% a3 R. v7 i, U) B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* q( K% ]2 w: K7 x9 H" E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 f5 K) x0 }; c N( M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ J5 B% r$ t: p) v9 g0x00, 0xFF);
9 H+ t9 c4 P4 r5 ? G" @
7 \) ]* a4 i+ J% V9 S' [/ K/* Enable synchronization of RX and TX sections */
$ @" Q5 N7 h7 B9 p. a% [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; A6 T2 h" ^7 e/ @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
N* X' O: \) K: i6 K3 PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 [ d$ i$ C! E# ~** Set the serializers, Currently only one serializer is set as
5 g2 ^4 d# C: k& P; m* |. Y$ Q3 i** transmitter and one serializer as receiver.
9 G6 j* k& m W- H% r*/: u" }/ M, l7 Q! R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 V2 ^! u3 L' r1 z4 N& T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ x( i" q) g# F8 l5 ~** Configure the McASP pins / p; B. o. A) M# N2 F J
** Input - Frame Sync, Clock and Serializer Rx
" i! t" t* o1 ^% T; r" H0 t* q** Output - Serializer Tx is connected to the input of the codec
* b1 w8 J4 H5 O( ^( R5 l) e; h*/
# h6 g2 Z4 j; J' F2 A3 q$ uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 A* y% {* w$ W6 S- b4 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' n+ K, y& J3 zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 l' U7 [) N; L4 m8 H: o
| MCASP_PIN_ACLKX
$ A7 u- l$ W0 \; p& L" S$ N6 P| MCASP_PIN_AHCLKX
R/ c. _7 _ o| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, b# a Y5 A9 F- q# U0 WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 p' Y4 p9 m3 z1 i1 g+ m| MCASP_TX_CLKFAIL
5 m/ f& o, O8 o| MCASP_TX_SYNCERROR
& f! b- Y* f& G' g; X2 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * {) ~! ~0 ^% h& z3 d- E p
| MCASP_RX_CLKFAIL
7 n. x+ e, k7 [; o4 v: ?6 I8 \| MCASP_RX_SYNCERROR
; X1 i/ R2 j* Y5 @| MCASP_RX_OVERRUN);0 W% W/ y/ E5 F4 _, p5 X
} static void I2SDataTxRxActivate(void); P6 m/ |2 o9 y
{ k. Q7 S- O6 G" a$ c3 M* n
/* Start the clocks *// s# s q$ H: U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! M1 [1 Q) M8 I% A9 JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- b6 m) j, ]/ D5 F5 I# D8 C, `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 X, d" i9 [; B T- P7 l
EDMA3_TRIG_MODE_EVENT);) @% ~# G8 H; _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) ~0 P$ \7 ~! K! `& QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! B2 y) n+ D6 e0 |% L3 G
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# a( X* A$ x2 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 I5 X; u' r6 P. |0 |" B* y5 q+ R0 q$ Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ e: O- d: i) Q. ~, i/ u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 n% M# h: F/ _2 ?% X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& u- `1 K7 m Q% ?} & L2 `4 i3 I3 _; O* Y' } _) h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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