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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ m4 I8 F$ x5 L+ iinput mcasp_ahclkx,
2 K5 x" v3 M! Iinput mcasp_aclkx,( n1 ?' ]$ D! {, W+ x
input axr0,
5 u" @# q6 w% Y6 [9 T4 A/ t3 c& w4 F9 n2 D- P& l6 {, ~
output mcasp_afsr,$ A2 |- I1 {$ x$ k' Q; T
output mcasp_ahclkr,3 F! x9 r6 D6 S
output mcasp_aclkr,
6 J, T, X- l7 G! u$ ^output axr1,
) `8 e! Z# v7 q3 F+ I! M assign mcasp_afsr = mcasp_afsx;
0 r& i, W! Y* P- g- C+ _- P: J: _" Lassign mcasp_aclkr = mcasp_aclkx;
# d5 b- X" L _) {" xassign mcasp_ahclkr = mcasp_ahclkx;
" m$ f& y$ N- H. [assign axr1 = axr0;
' z+ E n- P1 f# o' |$ B0 z1 t) y- ]& `: C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; T* M4 X- s! l6 X! hstatic void McASPI2SConfigure(void)7 s) g }6 `2 d& g1 P
{# X8 ?% c8 |- J# a0 h& D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* U. A: T" E; h+ r# jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. [3 y5 v, a7 Y, y2 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 Q* H; r% b2 I; BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 V7 M) _1 L" M6 h+ b) X- l4 cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 v! h: n% u1 U2 b7 F, y- mMCASP_RX_MODE_DMA);9 d' p4 u! i8 d$ }2 ~. K; |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 }% B6 _. g7 `8 T3 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 c( ?' y! `& p i! c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 P8 G9 [0 U% |6 a7 F
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ A* j- {6 O0 _" t* i( Q0 p& aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
V) g; }& {7 E: ]- x) SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 U; \0 ?6 t4 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, I, }4 @ B9 b, S, C( vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 @! q1 p9 e4 \$ s: I% bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' n; T; ?* \. I. V7 e0x00, 0xFF); /* configure the clock for transmitter */
8 E4 [3 |7 H. [' I8 W2 N5 S+ c% YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) @* z" l+ i P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 C5 J: U8 ?0 r8 t( k* x5 _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. y5 o2 r& t$ Y8 X) B5 R
0x00, 0xFF);2 W2 c4 W" G- k; E* p3 ~* |
; | \% C B4 H/ ]
/* Enable synchronization of RX and TX sections */ 5 s! |! h1 ]8 D2 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 @' e, c3 H3 f0 J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 x) j7 t9 f0 v2 u: P0 l4 Q2 |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& J& b' P3 H; Q( U' V** Set the serializers, Currently only one serializer is set as
0 j% V) y; }8 [) Z I/ z** transmitter and one serializer as receiver.. I8 u1 v. q3 o! L
*/3 w' j+ a9 N) m& V4 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) J; P8 p6 H7 h8 p0 q8 |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 _* b8 q# D1 W4 n' {
** Configure the McASP pins i+ x) t2 Q, R6 q& L5 ?0 U
** Input - Frame Sync, Clock and Serializer Rx! P, E: t* W- n, |# Q2 R
** Output - Serializer Tx is connected to the input of the codec ! V$ o; |6 f2 }) k, e: @
*/! ^# v* k8 _+ R* V! ^ }/ y5 V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 _5 f1 f9 h* Q; O; V8 X$ WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: R7 ^; u6 \; iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ b4 T3 ~6 H; W2 K2 e2 R+ `% P) T
| MCASP_PIN_ACLKX0 P/ o) a( h' V9 O. Y4 R7 }6 S
| MCASP_PIN_AHCLKX8 v9 c$ ]$ s' K$ B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! ^3 F5 |$ E% d( r) o# Y4 ]5 R8 GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 V( p O4 Y( u& {* D" l| MCASP_TX_CLKFAIL
) P+ t7 A8 ?$ L/ I- Z| MCASP_TX_SYNCERROR
6 {; Q* Z, g& D N| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& M( v' U' n3 Y| MCASP_RX_CLKFAIL
5 a; {4 W" T; I0 w| MCASP_RX_SYNCERROR : }6 }" _$ q% l9 n" i1 k5 O8 _
| MCASP_RX_OVERRUN);0 R, i6 c5 d3 H& ~6 v+ b8 w
} static void I2SDataTxRxActivate(void)
8 ^0 F( G* F& w& i# K1 `. b' w0 ^{, P3 }# j4 p- A9 }* a0 k
/* Start the clocks */
1 X8 a( u: ?& UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' w' V" k* `1 i$ G# a2 GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; ?5 z5 ~- Y5 X, g- K5 K p. S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, f2 F% a+ {3 |# P. U9 F4 k
EDMA3_TRIG_MODE_EVENT);* k8 q5 x! t+ i5 I5 [6 _9 D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 R+ B S: ]% R f) H/ rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 c3 R* w ]8 P+ W& H1 p* PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# D& ^, Q' J7 e7 l( OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 z( |9 P* I# I+ \ F. c" ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) k1 R6 k* Y9 Z3 F- k" AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 V& l% j; q5 O+ `* CMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: A; F6 P8 G: J b8 t+ b3 B4 q z}
: h( \6 [7 r- b. E$ j* O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / F. D* W, P1 M- x& e& q0 j' k
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