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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 z3 J8 T$ Q) r1 Y: j* Zinput mcasp_ahclkx,4 x' K/ G: Y2 L0 l9 C' _
input mcasp_aclkx,% C4 H8 W/ h2 t
input axr0,6 y3 l5 o5 c! m3 H
. ]: e1 q8 z9 P- i* c% M0 F
output mcasp_afsr,
" t4 o, s2 X4 c' u0 G9 v/ y, Zoutput mcasp_ahclkr,
8 `1 Z+ {' K0 Foutput mcasp_aclkr, [. M0 v, y, M( q
output axr1,
; n( l9 y) R) T; p5 f9 O. y assign mcasp_afsr = mcasp_afsx;2 n' b/ t, z4 v/ W# P4 l
assign mcasp_aclkr = mcasp_aclkx;. N8 I2 Z2 x! U- y( f
assign mcasp_ahclkr = mcasp_ahclkx;) j# s- g/ R1 V* K( m/ T* W ^9 q' Z: v
assign axr1 = axr0;
5 w! J( G! b4 R! v1 R, w
; X) _! z9 {$ A) H, W o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , u- f* U4 a9 d8 _% s$ F
static void McASPI2SConfigure(void)
1 k* X3 G* c# j{" c: q& ]( r7 ]) \% |. G7 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! O7 h: ~" f6 F+ V0 mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 J$ } r+ i" N4 u2 u0 K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! V$ z% j- J6 MMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 l2 C" k1 X9 L$ ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 o/ y( [6 y# u5 y& g4 B9 e+ |! H6 a
MCASP_RX_MODE_DMA);
( R. p9 W3 q/ z9 [- i. k7 y) aMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ d8 ^6 q: t3 g- R2 E* x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// N( |# U7 _% q3 x+ U" L6 \0 b
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# M2 j- |# X1 U9 i, @/ lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& G9 ~7 A2 z2 q- h
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 x5 ?2 A D; h8 b. H) j, P8 [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( @' s; J$ w* Y' B) H. `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ D, S7 J3 w! o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# z, g' Q' a/ SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 P) X3 H. u3 o/ t1 O# v& a0x00, 0xFF); /* configure the clock for transmitter */2 _5 y! W3 }$ G5 F7 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) Y( _- S' H! LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! r T, d7 g& p+ L9 h( M4 h3 A3 z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! H7 C$ X$ p( ]
0x00, 0xFF);
3 n# {: ]& C) \- z, M" G; d; \% }1 E- J& s5 J
/* Enable synchronization of RX and TX sections */ 9 L2 d! X+ }2 H9 a* C! {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 d# n6 b1 S+ |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 d; l) f1 k( B wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* h, o0 X0 T+ \, P
** Set the serializers, Currently only one serializer is set as
+ Q$ E) D: r9 r** transmitter and one serializer as receiver.
J* }. M5 ?- ~$ \! @( B& c4 U" r*/
. z+ ?4 [5 ]- i3 M$ Y! HMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 a' P% b) u/ W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** _% k4 t, a8 K j( M/ y* J( c" L) a8 s
** Configure the McASP pins * \# k! F4 A# N4 r$ j$ {: S
** Input - Frame Sync, Clock and Serializer Rx. h+ ~& q6 }% H4 l1 Z8 g% H
** Output - Serializer Tx is connected to the input of the codec $ _: I- w5 a5 _5 [ ?" E$ M
*/0 N8 D: e6 [6 Q$ q) v% A$ U( n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 f: v* A" d' @0 C' h7 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ v' l8 G4 N! oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: v* b3 F2 e Z: D5 c- p| MCASP_PIN_ACLKX
6 P2 I; S G% t0 I| MCASP_PIN_AHCLKX
' X5 Q- q& C& _- |) B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
2 H$ |4 I: p. ^; aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 D l0 A+ q# j% q/ w+ l: f| MCASP_TX_CLKFAIL
; O: w+ i- s$ y| MCASP_TX_SYNCERROR+ n: _& ~% I- l
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
F# w$ u( B- a! X+ G: C| MCASP_RX_CLKFAIL2 J1 F; |3 C7 Z1 T0 @% m
| MCASP_RX_SYNCERROR 3 E+ M. a- W1 p
| MCASP_RX_OVERRUN);
( a; s( n- J2 g1 \/ y' w9 l} static void I2SDataTxRxActivate(void)
2 J5 R' h8 s- c8 i! m- P{
% f0 |: a5 \5 A2 j; n# R. s' a8 M+ q/* Start the clocks */% O+ S- u- o3 t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 `4 ?4 G. O b3 B7 E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* T) }4 d8 a" X2 k0 S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 J% i( \6 e. aEDMA3_TRIG_MODE_EVENT);
+ E. @; [' B% C( t6 M5 ~1 Q( |/ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . M) U1 V# P8 ]' s9 e" @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* t0 B8 j) f/ T( a7 CMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* F' c" K! K0 [6 V, s0 F5 R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ q( ?# X4 m$ ]4 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 Z U* |# F' m @3 o/ D4 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) r8 O) ]* H2 h0 ?8 P
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 i" |; T$ B0 O) Z}
0 f" j( Y# ]$ y* e( d3 q' b% \请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 l1 ?, y4 f _! r
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