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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& y( h# y, }6 O# Q; G
input mcasp_ahclkx,$ C5 E. d9 a, [9 ~
input mcasp_aclkx,3 A9 v" h1 q* G$ ?) w7 A0 T
input axr0,
; J4 p4 W0 D( t+ w* @7 j
7 h' h! t; N* k/ v) @, R5 F8 ?output mcasp_afsr,
; v$ z+ R* n4 L% b% coutput mcasp_ahclkr,: r9 r$ u' Q3 o! _' W3 M
output mcasp_aclkr,1 Q) |- Z" \6 T. I5 K
output axr1,+ f0 t, m) i) M8 i/ S; o
assign mcasp_afsr = mcasp_afsx;& U! z* l/ ?) B4 ^3 s
assign mcasp_aclkr = mcasp_aclkx;
6 V7 I' u$ s) J) r8 I9 R/ }assign mcasp_ahclkr = mcasp_ahclkx;7 x% D$ R D; w$ j0 ?7 |* v2 ]) M8 o
assign axr1 = axr0;
! _( u" |( W, u% u/ ~0 R; l6 F( G# R' f" K) c+ o: t- I
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ j1 M* L W$ G9 x3 Estatic void McASPI2SConfigure(void)+ }3 z* K( C% o. k) [
{
$ ], ^5 I3 M8 m: U) WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; ^; j/ h ?' T$ `+ p* R7 g! M
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 N# S8 A: s2 A0 _1 Z* ~
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 F) w0 }$ R% M* b; z+ yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% z7 l3 F# Q1 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 }% V5 S* F) p. `, kMCASP_RX_MODE_DMA);6 q' t1 c7 l. g, n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* d0 U6 x- s1 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- \ Q2 x/ u- W/ MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' J: [. e/ Q* O% w u: ]/ v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 [! ^4 d: h4 X, d) {% R$ E/ d1 QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 X- Q" z( @! v0 o4 |+ H$ E& W3 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" g. k4 U* j6 K8 @) W! ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 h9 O0 }) \, u" ^* T8 A C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) x j* F0 o+ ~# FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% Y( }+ M- [ i4 A' k
0x00, 0xFF); /* configure the clock for transmitter */
5 y2 }8 R- s2 F' ~, q' ] {* TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 ~0 |2 E5 c( x- f' ~4 t+ M# }6 t4 z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / P. Y5 o2 H) k" `+ l/ q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 K5 g/ g# ?( V. N# }# }: t2 h0x00, 0xFF); i- L/ D. D. t, t
S H+ D0 O2 ~0 Y
/* Enable synchronization of RX and TX sections */
+ c% B# z$ y8 I+ y3 I8 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ d6 P: \: S- S; Q; L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 G& C5 [8 X5 G5 _- v: fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ |# e" B* d' t* n3 U** Set the serializers, Currently only one serializer is set as
4 `6 \0 }4 t8 p9 p3 v) t: v** transmitter and one serializer as receiver.
+ H( s$ |5 y# g i*/, I, B9 j3 B3 }# y) Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 H" E* R) s9 }: T% ]' E. V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ g5 p; b$ }, i; N+ v$ a$ k
** Configure the McASP pins
( K3 q. l' s/ `* Z7 S** Input - Frame Sync, Clock and Serializer Rx( |: l6 u7 j m
** Output - Serializer Tx is connected to the input of the codec ( v8 @- k* H* Y$ M5 l
*/2 d( |) E( S. X& i" o$ w; w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 R5 e1 f2 |! a" pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 U o# a5 B1 W: f' q* B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 v! v$ y# ^9 I$ t1 l$ y/ u| MCASP_PIN_ACLKX
+ R6 h5 [8 a2 s3 C; k5 ]/ }. {( P| MCASP_PIN_AHCLKX
/ Q9 j% x! T: t$ p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 V! L. G- E$ T) UMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
K7 x2 Y1 Y9 Z& l| MCASP_TX_CLKFAIL 4 B. F! }" ?& s8 V/ ]
| MCASP_TX_SYNCERROR
3 T+ A' ]4 s" U; v. [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " w* r- K$ X0 Q3 F/ M2 Q J& I v. g
| MCASP_RX_CLKFAIL& k! r; e) F4 g& a% f1 u
| MCASP_RX_SYNCERROR 1 a! T3 U$ x" z" w! p
| MCASP_RX_OVERRUN);
g# `7 R% d& a} static void I2SDataTxRxActivate(void)/ A, P% p; U1 Z" Y& C
{
' n& o0 k2 R6 c( ]3 E' G; t/ e/* Start the clocks */% b+ r K H/ w, o# R8 F# c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 f t( q) @( {+ h0 U' e* n0 @7 U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" d: z$ I2 L3 E- d9 D: xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* I, H, K4 G: x# D: v" a: p0 S0 t
EDMA3_TRIG_MODE_EVENT);
g* O: f$ v2 e1 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) Y' E& T- H$ x, e1 t% _& |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* J, f5 M0 A; Y5 r, V) B7 c' \/ I" TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
`' p9 S& D, v1 p1 T. @. ZMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; s2 O! L2 k9 L D+ v1 z, X! n. j1 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ e1 u( V- E: f6 V6 S1 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. C8 d! h" K$ S$ R; Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. J: y+ B+ A# A1 A; C* ]0 i
} # `' G! x2 ?1 y9 _+ X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( v3 j+ t9 M9 O) q$ W
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