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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ S! ~- l; I( dinput mcasp_ahclkx,, Y$ `: |; K% M% z$ q
input mcasp_aclkx,* |. u o5 u1 J% W! n
input axr0,
( S6 v7 U# f2 y( E h- P0 m' D
9 [% \% S6 W, `" i$ h+ ioutput mcasp_afsr,
( @( q6 q8 _; N* zoutput mcasp_ahclkr,
* P5 N9 `) P& f6 x' Doutput mcasp_aclkr,) K a- ~* G" U! Q
output axr1,! J. F; W5 i+ l
assign mcasp_afsr = mcasp_afsx;7 O, v+ k. o2 P5 v
assign mcasp_aclkr = mcasp_aclkx;
F, z& X, L, h& r ?2 U( dassign mcasp_ahclkr = mcasp_ahclkx;
$ a9 p* F8 v- K% H% u7 [/ p) F8 w: cassign axr1 = axr0; 2 C, j, a9 T! }, @
W8 |, E3 i* g$ x在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. b @: y! i( Kstatic void McASPI2SConfigure(void)' b- ?* r3 `8 c+ {; ]7 d5 N
{
' }, U1 d2 A) wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( d4 f0 X0 C3 d9 R; E s+ c- ~; sMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 E9 s1 H8 D L3 P" O: e3 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 {! m9 r' l" {1 r/ HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; x; f/ [+ Y7 K, eMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, ]" a2 f& {# e, V
MCASP_RX_MODE_DMA);0 V) N; e% C# e/ M3 T. \) ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. w2 r( C. N D3 T9 T2 Q! RMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 o2 w; y- N( ^9 DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 Q, H, O7 s/ }3 _4 |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" u$ |# ?3 ^+ Z7 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 u4 u3 ?2 ]; f# N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# P% i& @) Q5 H1 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
u. `6 X" K0 N, L0 q) YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % N. C7 s+ `+ b( i% w4 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: Y0 k* R6 S0 [# G2 u
0x00, 0xFF); /* configure the clock for transmitter */: m7 R/ s4 D5 B: W( n1 h# b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ o+ v0 K) N* p- ? o- h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! Z4 q; g0 D% U% F4 _6 X0 ~McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" I F/ W M* m8 @( L; z0x00, 0xFF);1 | b5 c* O$ [' P. z! ^7 j
3 M2 i$ t7 ~) R1 w4 A
/* Enable synchronization of RX and TX sections */
7 p, Y9 h# D/ bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: G' l" Q* c$ y# x2 O6 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 k! w4 v. r! I+ xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 u2 `) B" c( V- d. N* A3 v7 f** Set the serializers, Currently only one serializer is set as" r6 ^0 Q) A- L$ _! ^
** transmitter and one serializer as receiver.
" g) e; `8 M. c! y* m4 y8 b# B*/5 M; N& m k' c5 o. U: X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( R$ G, q, Z8 g7 x) b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( r8 M5 j }7 y. u& E( Z- r** Configure the McASP pins
% b# w7 l' `4 O& Q( \** Input - Frame Sync, Clock and Serializer Rx6 b! i1 y+ }1 e" E$ t) ]
** Output - Serializer Tx is connected to the input of the codec / D( g. ^6 d$ `7 {2 Z1 W
*/
1 k9 W1 F# T' c6 wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, U" m' ^& ~+ o, ?# L0 k9 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& U& ~) a3 B0 N" \, N0 y! EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 O/ F+ r& t5 L| MCASP_PIN_ACLKX) o* x# ]2 @$ ]' i1 |, h! W
| MCASP_PIN_AHCLKX1 f$ i# P4 G) n j$ A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 L; n( [% e) Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 T! E# ?" A& H; L! C| MCASP_TX_CLKFAIL * f ~% G6 q4 U5 I
| MCASP_TX_SYNCERROR6 a# m/ \' ?2 t$ Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + [/ W. E) U, T1 h/ {8 o
| MCASP_RX_CLKFAIL) b' A- G @! N$ Z* `
| MCASP_RX_SYNCERROR " b( L# T+ ^ I( u. l7 X/ B" l
| MCASP_RX_OVERRUN);
- Y+ E- y W+ R- z2 D% T* Y} static void I2SDataTxRxActivate(void)# o9 O) p) e+ y9 |) X
{
$ g/ E; q1 S( _ S8 n9 Y/* Start the clocks */4 F3 p. Y. Q/ c$ S7 | U/ B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 f }( E6 G) pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 M. Y7 q# T5 k) I; [+ QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" U9 O& }4 D% hEDMA3_TRIG_MODE_EVENT);- ]4 J3 D9 G8 |; O' {- q0 {1 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 X7 a% X* l7 P! M" I7 k0 b3 TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' {' K0 [3 [7 L- TMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( L# _6 N& V# dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
L$ I; q: P8 T+ V" p1 w1 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 b# B: y1 t4 p+ MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! i c& } b+ \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 F+ j7 n* y! b/ u( P: k* c4 p4 k}
8 |/ {* z' m9 d7 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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