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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& A# D% q% Q/ g9 d" a! z& E
input mcasp_ahclkx,- ?6 l6 ?, Y! D. A
input mcasp_aclkx,
% e9 s+ c: y" Y! L8 [( P' winput axr0,6 _ B1 j) r) {2 V
2 h. I/ m+ H) coutput mcasp_afsr,
F5 O2 o( F G" z; T" N3 a0 M2 f$ zoutput mcasp_ahclkr," D6 c3 F1 K/ d0 I/ T
output mcasp_aclkr,9 V, A3 m7 K" ]. q, r- |
output axr1,
+ D: P' Y6 E7 B* Q b assign mcasp_afsr = mcasp_afsx;
* `1 E1 [" _: l6 h# zassign mcasp_aclkr = mcasp_aclkx;: ]6 U; _( ~# B8 [& o; P6 y
assign mcasp_ahclkr = mcasp_ahclkx;
3 [# e% `* Q. E- s3 y) d- n; h3 _3 J& rassign axr1 = axr0;
. `" L3 _6 Q& j; I \2 Z8 M- W0 @# y6 o( j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 w3 C' z9 X8 m' N+ h0 ]1 J: l8 ^
static void McASPI2SConfigure(void)
- f9 M5 F4 N+ \7 E{
' V' n9 R- d2 i& JMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; ]% M# d9 N: p9 I5 @5 K
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- Y% r9 N# L3 {8 z n7 ~; r% CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& O8 l, m! V! o- V# d1 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! H. m! O y. |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: G$ T$ k% ~2 TMCASP_RX_MODE_DMA);4 D' P1 G6 ~: z" N; ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, f- k3 d7 v. m0 X
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ r( j5 d* B; k( O3 s2 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 p& q! `2 o6 k C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ @2 [- }9 {) Q9 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & L6 @# Q# M4 H' z1 w
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 M: D; r& r: b% x1 B" DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# G1 Y* \+ {6 L/ B, D( ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + | ^8 J! X+ f x, r# v ? D
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! \# s7 _0 l0 Q! E, f7 o( q0x00, 0xFF); /* configure the clock for transmitter */ I, g$ Z2 D/ p1 ]" n8 O- j8 D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 T. B/ q. k5 F1 H+ @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, b$ A% g9 p9 F8 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 d, z: T* V9 ]$ |" e
0x00, 0xFF);
3 A# M1 M1 O5 H0 C8 ?. Z. D* a$ V; \# O; l6 ^
/* Enable synchronization of RX and TX sections */ + V, c; H% |- ?! }: ?2 x5 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% @( k' }7 T" C" q1 C# IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 C# |. R4 z$ O1 N2 kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 p# ?# l& {6 K3 Q$ D** Set the serializers, Currently only one serializer is set as4 ]7 ~; j# z9 r+ L* Z, d
** transmitter and one serializer as receiver.$ o% j; C' b8 I# \& w' X
*/- A$ p3 E$ k2 y- l) j9 p5 P6 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; A: D+ E$ _. D( {4 G; aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. Y' \0 y4 O2 G, b3 V0 `** Configure the McASP pins 7 P% C$ L1 ~! m2 n( {
** Input - Frame Sync, Clock and Serializer Rx3 G+ j7 K1 E% f ?
** Output - Serializer Tx is connected to the input of the codec & k K: N" _% _2 M
*/
' u" D5 ^% D* i( [ ?/ eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% h. _3 B+ a1 B1 U% eMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# e( u! s$ I5 ~0 F! l0 ]8 [. G8 B2 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! y# {3 J% o2 J; ?
| MCASP_PIN_ACLKX
* m' W$ M& ^! u- x2 \+ T) A% L# x| MCASP_PIN_AHCLKX
' z( g0 F. u" A* z* _2 R| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 [0 K5 t( P* u5 t6 b0 |2 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( {4 C2 f2 i9 k1 ~% z
| MCASP_TX_CLKFAIL s( k6 T, p# W* \$ f
| MCASP_TX_SYNCERROR
m$ H Y* D4 _: y2 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 o; }* r0 M, {7 P
| MCASP_RX_CLKFAIL
* J/ T4 k' @0 h i8 Q0 {| MCASP_RX_SYNCERROR
" Y' Z0 c& n* C. `| MCASP_RX_OVERRUN);
6 X% r$ O6 E8 k/ ]$ K} static void I2SDataTxRxActivate(void)
- \$ b0 A+ f9 t; }# j8 F{" ]7 F) D5 T, H
/* Start the clocks */
) N& V. o. U# B* W. pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 @ O, y& r8 ? H- P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 D0 h/ O# Y+ D' V F) a1 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% o" F! a. o" K/ J. d- E
EDMA3_TRIG_MODE_EVENT);& z" F8 I9 D0 v1 C( B& C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - W* i* ]' A0 `& f+ M& T' p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. e: B3 Z# D1 H5 X$ N" a$ g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& L7 i; r5 s4 {* A- d$ {4 OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 R- R% d: H+ W, J3 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 v9 Q) g! ~( Z' t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 O2 W" S- D) TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 p5 |: c4 _ V) N$ ~& w
}
3 h& g1 [# y- s, _+ Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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