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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! Y' p# e( V9 _
input mcasp_ahclkx,
1 U9 i0 h5 E7 {! {8 G+ cinput mcasp_aclkx,. E! L1 y+ c w P2 X$ z
input axr0,
6 j# \4 T8 O% N, l: n1 s; U3 e: h7 P
output mcasp_afsr,) S2 H: @# H; t$ e
output mcasp_ahclkr,% R/ \4 a2 I3 m' t
output mcasp_aclkr,
: Z0 c& A4 p! ^output axr1,6 P+ Y- u( l1 Y
assign mcasp_afsr = mcasp_afsx;% J; K- m: u! h2 s& G' b
assign mcasp_aclkr = mcasp_aclkx;, H# E& M* I* C! {7 f
assign mcasp_ahclkr = mcasp_ahclkx;
: p( h. I' n+ p; \/ G; L+ gassign axr1 = axr0; 6 t9 @2 i3 c: y$ k
1 d$ J, l( W! a% e1 b3 X9 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% d4 l9 X b: v( ~6 \static void McASPI2SConfigure(void)5 B5 ?1 `; v* K9 {1 w
{
. ~3 H" R% F' t2 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- c1 Y" q& D2 h! C+ e$ k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 V# r$ s V" J3 D9 s! K
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; Q9 v- ~6 X# q# L3 v }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 k7 k; m2 p/ i; v0 N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. M( S m+ s/ y( w2 gMCASP_RX_MODE_DMA);$ \' o3 H( f4 Q1 p8 Q1 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# z9 K* O% T2 y7 c) {; s0 ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
S, h, ^+ T, _" TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 G: ]) ^: t2 D$ |3 F! d
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, ]$ E. S3 x1 s7 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 S/ g% \! T8 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 v, p7 b# D2 W* w, }; n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 |- r2 b$ Z) I) N( U% G- g8 e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); G6 l: { i v: K- K t+ J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% m6 d' P$ D. T2 o6 s0x00, 0xFF); /* configure the clock for transmitter */
! f% N* `2 s! t" n) G; rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; T' \) ]( d2 [1 v: m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( T. Y! Y2 M. G& G/ V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 }4 ?( N" v: a
0x00, 0xFF);& N; p; e, b% d! M
; k, R( } K2 a2 T
/* Enable synchronization of RX and TX sections */
; P+ ^( o% X+ \/ [6 h0 ]- gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! ]/ a3 e3 D v4 P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) l K5 B3 G. T( J$ G# q) h. XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ d: H: t0 P. d; Y, N3 V
** Set the serializers, Currently only one serializer is set as
3 J1 t# f) Y6 B! E* ]' s** transmitter and one serializer as receiver.
d/ f; d& v2 J6 x# _) I2 ?*/
6 }1 H! T8 l4 }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- {. {* g2 V( |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 { u, C5 [4 m) I$ }8 \. O A** Configure the McASP pins 6 ~, s5 F( z* |! U h n1 s% P
** Input - Frame Sync, Clock and Serializer Rx
; e, k; f I9 e, N( `** Output - Serializer Tx is connected to the input of the codec * R. C8 d- Y u8 l2 }+ f+ i" p
*/! ~: p4 [" t% r+ ?4 t9 x: Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 b5 Z7 D8 W# n3 u0 ]9 g6 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% G- w: I) f4 C; ~
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: @! t# D) d! l4 e$ i& s| MCASP_PIN_ACLKX5 |) c3 p% B3 Z% U- t
| MCASP_PIN_AHCLKX; m1 E' z" u2 L: K3 F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 o+ l' o0 H0 V" E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - _0 s$ s5 X7 m P) n' x6 a
| MCASP_TX_CLKFAIL
% c% G5 ~4 i8 H& C( I, m; G2 ~| MCASP_TX_SYNCERROR7 M# V# r$ I% I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& Q6 Q6 F7 v6 J( ?0 u5 w" l| MCASP_RX_CLKFAIL
1 L% h0 x5 t+ t1 _| MCASP_RX_SYNCERROR
0 |" n# H: H6 K3 e| MCASP_RX_OVERRUN);
& J& S& i0 Z3 f9 x} static void I2SDataTxRxActivate(void)
/ s& v4 K" v$ S, Y: b$ w1 g{
8 \; L- p! e6 a7 I" B/* Start the clocks */
' T& `5 [7 H( Z' @$ X4 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ a7 E5 B& I/ Y3 |. i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 i$ `. K' ~, v& tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 H, t" a) z4 n7 ]# A' u9 `( U4 OEDMA3_TRIG_MODE_EVENT);- K9 @# F c' M8 ^+ p& J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) i4 n0 A$ B8 F! Q) T% K' x/ K
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' ~& u3 T: O4 L4 S$ G6 W! w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) S+ H- X# m8 C% j7 m" d6 D
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; B c: [" B# b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 k Z" w2 ^% oMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 y& [$ L9 {: i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# I4 M2 f3 F$ m' t}
% P8 @! S7 M3 K# x Y {4 ]9 b) [1 F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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