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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 R& q h/ M; |/ x, n1 [ rinput mcasp_ahclkx,9 k% U9 `; N- W& l) W# V- D
input mcasp_aclkx,% P. c) h5 X2 e( E0 M* }
input axr0,
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( s1 C* ?% L7 I+ H) w( w' D" e, A2 _output mcasp_afsr,# ]' g+ @- z% d! G& f4 L! D
output mcasp_ahclkr,
; q/ c' o6 ]& aoutput mcasp_aclkr,
3 C5 }* O+ Z- l% T$ G) ooutput axr1,0 ?- f l# t8 A8 q1 i/ d# |
assign mcasp_afsr = mcasp_afsx;
- R, G/ p7 ^4 m* i4 u a, {/ Zassign mcasp_aclkr = mcasp_aclkx;
7 I* c0 w! d2 U/ E4 vassign mcasp_ahclkr = mcasp_ahclkx;$ O% ^3 r& ~. S2 ~0 r$ {# ]
assign axr1 = axr0;
1 u2 U8 s$ p) t$ L2 V: {% @0 i B1 |" ~! k( d' N$ m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 ~* B0 q$ `" j8 A4 \/ z* k
static void McASPI2SConfigure(void)& F- l2 a% {% B. v5 M
{
8 x* x( ^/ K$ g9 n$ F7 K; LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);+ D% t$ R+ r, D5 T6 o, j( [; ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ n. \) ]7 W' A" d) A, C1 O) LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ f! S+ n+ E8 X2 r- V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, J+ R. @) n! }5 J- @
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( V+ J. q. r# e! [1 s8 i7 R W
MCASP_RX_MODE_DMA);" }( @2 ~: ~1 o% C7 n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. A. O. a/ ]' v# c" t- r" Y. Y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: U6 m1 D: V6 Y, aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! `+ {5 O2 ]6 B. i* a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 H" t* ]/ J" e& |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - j4 c! E0 ~2 [8 _/ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 s3 j# Z3 p, N7 s+ K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) g, m( `1 R2 o9 P/ J9 m- u! {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : v5 T5 D6 s- e' W# \4 X- H; r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# {6 O* r- f5 L' X0x00, 0xFF); /* configure the clock for transmitter */0 x# m3 o; m [: U$ r; e8 v8 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 S. v) a% _/ W* K$ |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* _$ A% Z% u3 r( JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, K1 G- q7 j& t) w" O0x00, 0xFF);/ [4 X# r+ l. \0 \- v+ a+ O
: D1 @2 X7 W- Q2 `6 a4 _/* Enable synchronization of RX and TX sections */
0 P' k! B4 o" ]+ v7 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. X* t( v, E7 }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" u, k$ T+ X9 ?+ Q, h$ ~7 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) L& s6 T9 Z$ H0 T, i
** Set the serializers, Currently only one serializer is set as N7 J% N5 [$ |# ]- y' e! d
** transmitter and one serializer as receiver.
) f. v3 {8 v2 o" e0 f! u R0 D*/) G/ ?3 B% P. G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) T9 r- d6 q0 _# L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# y/ q1 S9 O% Y' l$ T/ x4 r$ \
** Configure the McASP pins / o' c$ j, Y- u
** Input - Frame Sync, Clock and Serializer Rx; M4 m3 M8 {1 e2 ? M" d: z) |
** Output - Serializer Tx is connected to the input of the codec
) f: }9 l1 h; ^( M% j*/
' n5 y) L1 l* n! f7 m; dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# n+ n% h' z/ V7 T9 p: v* R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: K5 j- F7 M$ ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 V6 B) t% v6 C| MCASP_PIN_ACLKX
/ ?- ~, f$ x& s| MCASP_PIN_AHCLKX
% G) x6 p+ a8 F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 a I8 ^$ F: [/ S; ]: [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 S4 @. N) P- ?5 ]3 H0 g4 ^| MCASP_TX_CLKFAIL ' T* i' J0 _" w& N, N8 r, V; a% h ?
| MCASP_TX_SYNCERROR
% q: i+ b% U, G- ?, Z& x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 D) q- s! Q2 Z. c' j. j| MCASP_RX_CLKFAIL
' j+ Q6 P0 V% k% F1 O+ F: L| MCASP_RX_SYNCERROR 2 L' ^% k' Q9 g( t6 C( w u
| MCASP_RX_OVERRUN);2 r. M9 T$ }7 M0 D- j' p. d) a4 W
} static void I2SDataTxRxActivate(void)+ ^, a( L- j- S- S7 @
{
# M6 n# u) |3 d/* Start the clocks */
2 R4 P9 r: Q1 g' ^- J+ z) KMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 n1 W) d$ z: _9 s6 C6 E; ?' V+ AMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
G. [& }# s jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 T R% O0 c Z( Q2 S' S( jEDMA3_TRIG_MODE_EVENT);
5 n2 V5 S. }/ s* HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' l$ }1 C( }1 Y1 i3 xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 Y1 H; I& g1 v/ C0 m3 ?McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 z- m K2 t: r8 F" t* t/ bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 G- Z" q; u" }8 y% W7 W! z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' [4 L' Y' F3 t3 x4 r6 V9 xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);( ?( e" R) K9 Z8 j( P% \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: s6 b' R% `. n- i+ }
}
& T5 H$ b/ z; b2 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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