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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 m8 D: O9 r% G1 Z0 v
input mcasp_ahclkx,
6 i, i+ N7 m# u$ P, M! @input mcasp_aclkx,$ r; T+ b9 ^& c5 I2 w- P4 F% O
input axr0,! y9 u8 x U6 B; b
* ?' |, ?- f& n" n, `0 Moutput mcasp_afsr,; M/ @: |6 C9 W, P9 }5 K
output mcasp_ahclkr,
0 d! D* O1 v/ _ }/ Youtput mcasp_aclkr,
* F' ]! o- S# w. joutput axr1,
; B d! z4 N, a1 Z3 E8 G3 x- M assign mcasp_afsr = mcasp_afsx;
9 d( e5 n- v7 D: u% _assign mcasp_aclkr = mcasp_aclkx;9 R) k4 C# ~; x% m# H
assign mcasp_ahclkr = mcasp_ahclkx;
* ]* e+ [" D/ k3 S1 _& J; L7 zassign axr1 = axr0; # `4 c9 n4 ?( C5 T3 x; C" N
# E" J! m# m( w6 g% ~7 q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 a& m$ o8 i6 p Tstatic void McASPI2SConfigure(void)6 e5 X2 d- e1 f0 p/ X( _4 b/ m) S+ G
{$ `5 U# Y5 H4 ^1 e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( S6 P( s; ]" U& @1 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ ]$ Q5 F- Y1 x2 K, l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 [7 c" X2 _( e, M" _2 jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 R0 ?5 ?& F2 x: P& Y- ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' I! k; M* P( n" k" E
MCASP_RX_MODE_DMA);! Y: V. v8 _2 Q ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 `; ^* f3 i( \; Y% Z: I6 {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 Z, a3 m( o7 m3 s: |* n h$ HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / q& g- f; \$ r; Q3 U$ A# c4 L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; o$ L) }5 ?7 M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 O- C2 v" Z1 M% I" AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, m$ ^/ m5 ?* E( WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: ~& R. h8 }3 l8 mMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
H F9 T8 m7 X7 e: q6 R3 q" c2 `& gMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ ~. K5 v4 }2 \2 V# _4 l; r
0x00, 0xFF); /* configure the clock for transmitter */
* q2 j/ F8 H4 ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
M' [4 g* {) O2 P2 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 ^4 \( c* ~: B; G- `* u$ Q' w* ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* o5 i- g0 D9 E" G3 H0x00, 0xFF);: {* x) @& a* V# v8 M
4 `6 m1 I; `6 y9 [, S* Y5 g
/* Enable synchronization of RX and TX sections */ f1 R, B4 b& p4 [5 D I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. k8 i; c! M) ^8 N4 ?7 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ X. Q# Z* A7 L4 O% k @3 i3 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 S/ S5 u, f; z- r) K
** Set the serializers, Currently only one serializer is set as
/ d) V) T1 o9 X: }" q' C** transmitter and one serializer as receiver.$ d; ~# V. [+ V! t. T! |- K. L
*/
" J+ r0 b* v; K- t( ?4 ~% o4 G. uMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: o/ P+ f* ^# I) v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** H8 P6 ?. B% d; f' _/ f
** Configure the McASP pins
4 A" S% @ |( O** Input - Frame Sync, Clock and Serializer Rx2 S3 r* l+ e8 J9 p/ e
** Output - Serializer Tx is connected to the input of the codec
% [; s5 ^- X; {: F*/
$ T# F1 B+ S& D. y1 H+ J# SMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 _- z' U! N+ i+ }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' X6 U& e! K# i+ l( f4 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 g. ^, ~1 P7 w+ e| MCASP_PIN_ACLKX' |; q( L4 L; G# r( \
| MCASP_PIN_AHCLKX
3 S" d, `) _4 s' z3 _5 i+ j2 X3 ?/ k* B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! P8 A" v' a5 C9 ?; R# bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 I) _. ~3 a1 d3 _3 e5 h- Y| MCASP_TX_CLKFAIL
. B: ?4 b) j% j4 }% Z( t| MCASP_TX_SYNCERROR
$ q1 z% {7 r; G7 R: V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 ]' z& ?. C1 k| MCASP_RX_CLKFAIL
* n2 r/ Y$ m8 S| MCASP_RX_SYNCERROR + P4 [$ V2 d( U3 f
| MCASP_RX_OVERRUN);
9 ? E! j7 ^; h) X! H0 d3 V} static void I2SDataTxRxActivate(void)6 W# c- X0 Y1 S/ A+ w/ s
{
( l" f7 V- n- T! F1 e/* Start the clocks */, p3 a L3 ]" w5 _% ^: {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 c; G! d ~7 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ \5 M; n9 U, y: |8 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" [5 v, N( B7 ]$ Q- K- a" ~EDMA3_TRIG_MODE_EVENT);
/ [* e4 [ P. j2 @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 R) i3 T+ M7 s& X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
+ ~ B7 S# h' b7 d$ ~; p. }McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 ?, ^* |5 @7 b( J" A1 x( @5 _5 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ B, ?) a( {' e' D6 j3 zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 m( q* ~. v; a- v1 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 ?8 `6 a& F/ \& e0 @. a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' ]. O( u1 |' p( J1 a}
: I% x1 ^- d; M' z# f3 k+ x( k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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