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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" q& M6 q1 p, c5 ? j& |input mcasp_ahclkx,
2 U2 s- T7 m6 e, s3 S8 I0 linput mcasp_aclkx," C% f6 ]5 R# X/ c5 R6 Z0 M: M3 @ M
input axr0,7 l8 o' \( n: W2 d1 K: l
" t' u i) P4 B4 W9 Y8 `; l$ \- G# M
output mcasp_afsr,
4 e0 s) V( K; P, W8 J2 Voutput mcasp_ahclkr,
1 ]5 A0 I, i- F; J$ j& moutput mcasp_aclkr,
- }/ H! [; M loutput axr1,
( x3 m- K$ j( `, p- {3 w8 T- a: g assign mcasp_afsr = mcasp_afsx;' ^8 L# C7 H2 m* X7 v
assign mcasp_aclkr = mcasp_aclkx;# {% E* i- @% w4 [9 n
assign mcasp_ahclkr = mcasp_ahclkx;
' ?7 r% x+ ]& x( @assign axr1 = axr0;
% h( p# N I7 w; N: l n5 W% H s2 Z+ ]! p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) X1 j& ~6 p8 y3 Jstatic void McASPI2SConfigure(void) C' n- S! ^' {/ A1 n( N
{' A8 p) n/ ?7 \! H" J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- l1 a" F& h b; l. MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ S6 ~2 g: |. n. k- U$ ^; V. OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 n. F5 r! [. Y& D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 T$ x" u8 o+ [4 ^6 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* G# b5 t. W. [- S' e- MMCASP_RX_MODE_DMA);
. T: u/ I0 Y4 Y- e- HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! A) l3 C! `% w1 T" J+ |
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& H# \, C Z0 @% E( ?8 {3 @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + | @6 `8 X* @5 ?6 h0 y& }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( P( K4 A* @' I8 I) `0 B+ s" QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % |5 e6 ]. ~0 F: ~$ I) c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- U' L5 x1 P. {2 a+ uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 X6 N i8 N# s# F( ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 o' G+ f% ?) B& f/ aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 R) `* _& j6 G: [# o+ F* G
0x00, 0xFF); /* configure the clock for transmitter */
4 L) c0 _( e) q+ B- f5 `; C8 |1 lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& S1 f4 C9 }5 b$ Z; U* Z& B4 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * m4 p! ]: \4 U9 X* \' M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ ~9 a* u4 m: Y0 N
0x00, 0xFF);- x$ }& C9 m. i. p
- y) ^& p E" E7 D% q# Q% l/* Enable synchronization of RX and TX sections */ - y/ m+ X, ?7 o& f- Z( s
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ T# P0 n" s3 y* [: A) NMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# e. n H# x0 v* |+ _# }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 t2 D6 L0 N8 V# ]" Y* U
** Set the serializers, Currently only one serializer is set as
7 u8 P6 d+ Y( q. z, C+ ^- T' P** transmitter and one serializer as receiver.
# `/ R) d( ]4 ^) e' d4 L) o*/9 v7 m, Z* b) W: ]. ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 ?' w( Y# _! b9 w) F+ F9 g# AMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) {7 i) h6 L+ M0 X** Configure the McASP pins
0 O) R$ i6 u. B; @** Input - Frame Sync, Clock and Serializer Rx
4 g9 I6 Y, i. q8 h* m/ p9 D** Output - Serializer Tx is connected to the input of the codec
7 d+ N: o, R0 A2 Z" [*/
, W+ Z/ y+ o0 T5 rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 F2 t! o" u: N# c" Z% Y0 L! k3 y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ A2 k. j7 y9 u' e; AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 }, ~/ c' g* F% k5 ]
| MCASP_PIN_ACLKX7 ?" D- M& ` n& |
| MCASP_PIN_AHCLKX) J4 X# W, J' m, I+ I+ E% }) A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ N# E! ~. N2 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" @ R7 \4 `4 D: V| MCASP_TX_CLKFAIL
6 `* u5 E( {/ |/ z0 H| MCASP_TX_SYNCERROR
) m# g4 F$ O$ I5 O A$ b: C/ O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! Z t% T% ]5 h0 X5 u& O& k: \| MCASP_RX_CLKFAIL
1 H# O; q7 C: q' R| MCASP_RX_SYNCERROR
+ ?4 ^: j$ w) z% F! z| MCASP_RX_OVERRUN);
) X& H% H, ?1 r0 {} static void I2SDataTxRxActivate(void)
2 U: f* y% m% g( q) D) d' I{7 J# b; i( r" z, I
/* Start the clocks */* w7 O2 t3 w2 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" |6 r- @* e9 b- Z ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& D1 {" C9 R1 u" bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 Y* ]8 d% i; U! v0 a2 vEDMA3_TRIG_MODE_EVENT);
. D: f; q. A* u1 P* d6 G0 L" IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 S& m3 Y0 g# y6 t6 EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// m& e- ^4 A3 i2 C; \+ }5 ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# q3 S+ q3 n/ ^ h hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 S2 e7 d$ d: H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ I& n( v; p; i- ~) mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 W( ~; ?0 i0 }. f2 AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 A, H a8 U; P
}
1 x8 @! X1 i$ L* y/ r8 B5 V% l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + z. ]% Y2 ]# M1 @7 [7 U
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