MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
9 B6 J# Y& i. pinput mcasp_ahclkx,
* ?. Y* B; R2 y# n* H- m" i+ tinput mcasp_aclkx,
7 ~; @9 P/ X5 k" C! J' o% W$ G( vinput axr0,

output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

' f( d! M6 O% e

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

' ~% G8 b/ ~# z! I+ {

static void McASPI2SConfigure(void)
( l( w1 f9 Q) _# d{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
7 ]$ C+ [8 f1 U# |; |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 h; R2 g/ o8 A8 iMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& B) l  I9 P4 _8 \MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) e0 X2 b" n6 b0 |& U# B" d' p8 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 ~* _- M! p% AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
/ m9 O2 s0 M0 k5 x+ M2 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
; N) l; s% D* [/ {  n) N' V6 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 _$ D  x' ?. yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
) U$ t: X* a0 o( U$ h6 fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
  j* }' Y- ?: c* F. Q% J, y6 a( q! `McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 c8 _5 _, M& d6 }/ J7 fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; O) F# f& j+ K0 p0x00, 0xFF);

& G; c' ?+ w- [! I4 t  d5 c/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ s8 w+ _- R! _1 U2 V( |' A8 ^( ~) ?McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 j2 _* _, Q) h2 M: I- \- cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
* V% u8 T! M" L! p6 H1 N** transmitter and one serializer as receiver.
9 m; E6 |' ~& f8 q) L  t$ J*/
6 U! u$ q9 V* R# k  ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
$ B# N. Q: q: {: J6 E7 B** Configure the McASP pins
: M' j- t, c# A. z* a** Input - Frame Sync, Clock and Serializer Rx
3 N" S8 B$ H3 V3 F** Output - Serializer Tx is connected to the input of the codec
# T& ~4 s' a- P/ E*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: R0 W/ \- f+ g3 f( L1 h; fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
+ l5 H1 ]- F( j| MCASP_TX_SYNCERROR
$ O6 K5 H7 Q( s3 R: W9 d6 z| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. y- `, M, ^6 M$ S6 T3 Y| MCASP_RX_CLKFAIL
5 u9 Q9 u8 |7 x2 M8 L| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
" H! A  n$ O3 L7 o6 Y{
* F$ A5 A# [( z1 E' I, P1 r9 d3 v/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  k( B9 G+ X& tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
2 g* @# D% Q7 x: {9 y% fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
2 D+ `, r4 ?: Y; j% p% ]& l. `& PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 L- R9 F7 G. N9 fEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
" ]$ ~+ N2 n8 N$ m% dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% g/ `0 |0 I: s& d4 j. I$ PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
, {! |0 p4 m1 a+ G+ F& h; g2 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" a" g5 B$ t8 {! C3 \+ @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# e8 P/ ^  b1 ^& I  G3 H% {}

" z. M' W9 S5 I' x/ J

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.