MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
, v1 j1 {* y$ Z- R8 kinput mcasp_aclkx,
  y5 T" }0 O" d5 C& B5 v, \! winput axr0,

output mcasp_afsr,
$ V/ V: E0 C% v* G( Toutput mcasp_ahclkr,
output mcasp_aclkr,
output axr1,
( l0 K8 K! [8 V8 i! @: w5 Z

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
* b8 Y* z4 u0 C$ \( _assign axr1 = axr0;

2 y  B6 w$ Z0 }: t

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

# P- k( I+ u0 y% B+ A/ s) n. e

static void McASPI2SConfigure(void)
- {- M3 R4 Q, Y2 p{
( E8 [4 F/ y) O6 c% K& Q9 b% hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 }1 t0 j0 a  b- n2 m2 K% tMCASP_RX_MODE_DMA);
5 k% ?! T2 ^, Q( ^) G0 G- Z& M/ KMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% k) A$ o! {8 d& AMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& X/ Q8 I' C( C% f6 ZMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
3 |2 Q' Z5 H/ u4 N8 xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 [; g; a& y9 F0 YMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" U/ A3 U( @* W/ n, V9 w7 z- A, RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 ~/ a# `+ C6 t" q0x00, 0xFF);

/* configure the clock for transmitter */
' ?" X7 e. _- o- b( h9 oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, z' g9 V. _* R1 |0x00, 0xFF);
' o! M- ?1 C8 r  `1 {
/* Enable synchronization of RX and TX sections */
. t) _% A" u% R( C/ ]8 N1 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
* t! ~" t5 X" C- n/ k- v2 bMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" |: v! C/ P- {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
& x* ]0 w* M& z( E** transmitter and one serializer as receiver.
5 T" g: A+ `- i. T*/
# q$ A, z2 a" m2 F) J) c/ fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( B$ U5 y6 r7 |% NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
8 K2 C5 l. N9 t" J* X$ _3 ~, P$ l** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
) @( z3 [- ~; x9 X9 v% kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 I' o' q8 \2 \* }4 J! V# \& QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' k7 V9 u! X. V" D/ N' x% b; uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
- v7 p) k4 V3 [& ~4 B| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
# m* m+ E" a. a! Y9 M7 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
# U! W, _6 L# Z+ }0 {' @' e| MCASP_TX_SYNCERROR
; h9 W# p: z" A1 _7 `) a$ N| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 j3 y9 I# A9 C# Q! f# b| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
. y" F# o. q# R( ~* }{
! n- s! R& |9 g/* Start the clocks */
. w) w& E$ T8 j3 mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 `" b: Y3 X9 ?% `+ xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
& N0 G, g) ?/ N9 W# _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 X. [* Q- B5 f% w" |4 Z& ~, M) gEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' H, n* Q- b3 @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
2 z* C7 y& Z8 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 A2 }0 s# D+ J+ oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) p1 b, }; [7 i* V( uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

( ], Z/ M) B( Q+ C$ ^5 N