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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! S2 |. S" H' a9 a7 Z6 }0 z9 L1 rinput mcasp_ahclkx,
- g! X B3 a' P" Dinput mcasp_aclkx,' y* ]3 V7 i8 q9 `
input axr0,8 ]4 F: h: R4 U; q- h$ v
5 r& d m- F8 I: |- Z2 {+ u7 boutput mcasp_afsr,
% l: d- X9 q* o! ]0 r8 G( Uoutput mcasp_ahclkr,# u q8 S' x0 N D' r
output mcasp_aclkr,
1 V u! `; k4 e/ h) A6 doutput axr1,6 Y) H5 v$ }+ b: K
assign mcasp_afsr = mcasp_afsx;
# r7 b# o5 a6 Passign mcasp_aclkr = mcasp_aclkx;* u$ u; D, V* i" c7 y& H! ], V
assign mcasp_ahclkr = mcasp_ahclkx;1 ^! N0 T- {8 A3 X# J& \$ _ r
assign axr1 = axr0; - b) h1 A! o K% C$ y' `* V' Z
* J. L& u7 B5 D" W- E# q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: ~6 a7 C6 m: D( `0 Sstatic void McASPI2SConfigure(void)
0 u$ E+ o' s6 K; x3 s( D{
8 r8 {% G2 d1 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! _- H- a! v/ r5 t/ P2 i6 Q, L6 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 c) R2 m( E5 R1 ]. wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* \5 p4 ]$ l5 O; O% n6 PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 y: @" E5 j7 l; X/ i! qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! s6 ?/ { u) LMCASP_RX_MODE_DMA);1 }5 e8 s0 q: G" R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# {1 r/ S p( r0 ^/ t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 a5 y# Q4 e! |9 f" E7 S* W/ jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % z; m6 B7 I, |& {2 p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* G$ M- T- v, W N8 z9 o' |; AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ s* w/ e+ I/ n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 [& z6 l9 w1 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; C! h0 r( o& j' [5 [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 t5 T2 l# |# _$ e3 K- h( |0 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. @( Z3 q' t# y( ]0 |
0x00, 0xFF); /* configure the clock for transmitter */
2 u0 S# |% J& Y& oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! F5 Z6 w5 u8 [. N* c: hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - k9 j& X/ @. S% s, {. E$ d" j% F7 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 i$ c. p* X0 h* u$ F+ l3 j0x00, 0xFF);
+ R0 O1 t# ^. n3 t0 p: L
/ N0 L G- a1 Z( b8 z2 j: G J/* Enable synchronization of RX and TX sections */
/ o! s3 r; o' D1 wMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( B; T( F* H9 R G F5 p0 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; T- W3 }4 }2 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: _0 V( ]+ n! q6 x$ r, Y
** Set the serializers, Currently only one serializer is set as$ I# {/ \$ s; ^0 I, ~
** transmitter and one serializer as receiver.
3 W+ |5 u7 \# _1 r H*/
& }' v9 n3 X/ e Y0 z& \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* v$ w4 D; c& m& C2 z2 aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 b% s( I% m& N, m' {. |1 G** Configure the McASP pins
. D- |0 T+ X; \+ Z** Input - Frame Sync, Clock and Serializer Rx/ R1 c& X8 p* U5 H! Q3 N' r% ~7 Z
** Output - Serializer Tx is connected to the input of the codec
0 j" y+ K# \3 d1 ?- _& r2 @*/2 K1 T# L! B& e1 c. T* ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" \5 V2 `# Z) C8 H( M; l4 N( q% G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 f% @/ M0 { _! u j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; |! [7 c& J" r5 ^9 L
| MCASP_PIN_ACLKX* K( L6 J) l/ x: @9 b* t& z, _
| MCASP_PIN_AHCLKX3 i4 D+ S! k2 N, w: ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 k4 M! h( a- v% l. |* A% e! g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & z) } C! i8 p) ^ I
| MCASP_TX_CLKFAIL
5 f$ N' D) V( j6 @3 E. B| MCASP_TX_SYNCERROR7 g7 n& q5 V7 L( C6 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR F) j6 ?2 _8 V3 E
| MCASP_RX_CLKFAIL) {$ S! p0 G9 {( r! x6 ]
| MCASP_RX_SYNCERROR ( r5 ^3 r0 R* @- l- m5 o& b
| MCASP_RX_OVERRUN);# ~3 R$ A; T" S
} static void I2SDataTxRxActivate(void)* l- M1 q" u8 m8 s# M! n
{* {) m/ R" t* G* I& N% i
/* Start the clocks */- G- a. K6 f' W; c+ K3 o4 T1 M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 m# X7 T9 Z% S0 b7 p' Z7 R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 y3 D: g3 P. m A& z# s: FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! ^4 ~# G8 R9 Z, s/ e
EDMA3_TRIG_MODE_EVENT);8 b! D; S T# c0 t' a, E9 j+ S, ?
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) _- e6 U& k! E" v& g* nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- i) k4 U9 a; i7 [$ c& k8 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* p, U: W p$ c1 e/ e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 m0 g7 L# d/ ^5 m( V5 }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ @' z- Z9 m% mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, W7 r& u2 n" K) EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" S& Y* {5 e# T. B( I0 b" n) U}
8 b' ]$ f* b* q# H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 O: k' \$ I k. i* U; ^9 R
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