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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 u( ~( _% h+ N- H$ E: S! b
input mcasp_ahclkx,
5 i& k( P2 N& }! s" oinput mcasp_aclkx,6 ^7 v# N, X+ L2 n
input axr0,
: s" t% U& h' O# q4 ]- c0 P5 a- t7 W& {$ p; c' H+ I( D
output mcasp_afsr,9 Y) U" _) R9 _7 B
output mcasp_ahclkr,- ?, A1 ?; N0 \9 O O
output mcasp_aclkr,
" M- p: f& F1 I3 T8 ^output axr1,' m' A+ F) |* F2 v- K) a
assign mcasp_afsr = mcasp_afsx;
& x5 m. r* ` ]: I; L% \% rassign mcasp_aclkr = mcasp_aclkx;
7 g$ E5 o( H% A9 ~assign mcasp_ahclkr = mcasp_ahclkx;) N9 v7 A$ x( }, j5 J
assign axr1 = axr0;
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+ _& d0 X5 B7 \7 R8 I m3 G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - b! O' n/ Z8 _+ A- X) d3 v; {
static void McASPI2SConfigure(void)0 w6 b, Z' R2 N2 Z5 E$ A$ L
{- E! E0 b/ k" d( k. T, {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 o% `0 p1 P9 Q0 y& ^" XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. ]% \* ~4 k3 w1 i m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ Q$ i. [" i. ^4 H0 p) L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# W' Y: @0 H4 n7 s/ B2 N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," L& s5 l" E* t) z, E
MCASP_RX_MODE_DMA);* r2 T0 L) G+ {% {0 I
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# t7 D8 \4 c0 [& C' u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" X* L8 O! F& R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& b# h) ^; |0 [" vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( }5 d5 J' K- t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 C S1 N, |/ v3 IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ w/ H# g+ w# O7 D* y, x1 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& A0 ]% t: V' y$ P) A' q yMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * k4 H9 b* k% m; _. k1 e9 e+ B+ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ y7 m3 x8 d% d+ U1 e& w( j
0x00, 0xFF); /* configure the clock for transmitter */+ [1 A5 h+ m8 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 ^7 P% P* A4 b: zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , p3 o0 Q, T+ L! k6 q% r/ }/ _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# v& C1 B0 u3 p+ E7 y/ y9 q0x00, 0xFF);% F; j0 M3 C% P
- {$ ^: I' n5 n' U' i2 e/* Enable synchronization of RX and TX sections */ - z, t' P; w; d& M3 W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ t$ [1 Y8 ~- q: Q0 u; i! E8 UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ T, \$ ]! X3 a8 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** j" m+ m* K& Y( H! s* y
** Set the serializers, Currently only one serializer is set as
0 @, M& \' F7 l- V( m** transmitter and one serializer as receiver.
, Y- Z1 v% v8 g" Z& b5 R*/
8 {$ ]- F8 Q8 D0 `$ CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 s7 T0 D$ T$ H4 N/ C# t' q, u
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' l8 Z+ c0 C7 \+ V# F, R* f' q/ E
** Configure the McASP pins
& a7 j7 |; e8 }** Input - Frame Sync, Clock and Serializer Rx- g0 t4 {9 q: X7 i% e7 t
** Output - Serializer Tx is connected to the input of the codec
6 U& S* ?3 F+ ~*/
/ ]$ m5 M5 ^+ V4 w7 R! ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* G- F1 D4 D3 v3 sMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) p& F* t2 W1 m' E0 U# f, ?McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX( w* L4 C7 U; Y% G% c" q$ Y
| MCASP_PIN_ACLKX
q, L- M* B. r; {" a| MCASP_PIN_AHCLKX4 b2 Y9 w- `6 b* L! P) F( L8 ~, M! }/ T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 D, I' s, H8 ~2 f o, ]1 g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 s+ K; R5 q7 W/ H/ P' k
| MCASP_TX_CLKFAIL
: V7 W# I1 w6 x8 ~0 g: ?4 {0 ^| MCASP_TX_SYNCERROR
6 P6 r. @8 @+ f3 v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, ?+ n6 ~$ Z* w9 L- W| MCASP_RX_CLKFAIL2 w8 E) I7 z- v; `
| MCASP_RX_SYNCERROR
. t s+ ]4 }. N, k| MCASP_RX_OVERRUN);
9 {6 l& ?- B" R( Z* a} static void I2SDataTxRxActivate(void)
5 r) D4 C% k- Y8 E1 ]( b{2 |6 L. G" q# T, g5 e4 ^
/* Start the clocks */
& R( b3 ` n3 k' j2 FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% W( G1 V+ ~* d; w6 k0 |. `' f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// K# ~( z% [/ H- h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' m6 C- M( j* f1 W8 h6 M$ eEDMA3_TRIG_MODE_EVENT);
) N$ Y; t( @! Z+ EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% k% U" J- J. X! REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- e$ K7 S2 U6 ?$ J% [! }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' j" f* J, G9 I' O7 u* [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 @9 o4 R( ?# G' _. i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; L/ v3 ~# x- O5 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# o0 A7 N( i# Q" {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 e8 O! O [/ H% K# @) ]
} 2 j% B% X' @$ C+ F- K7 i8 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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