|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. [& p5 f! m/ |. z. ?' ~6 `, p8 c; einput mcasp_ahclkx,) x! z' i- p% I. J
input mcasp_aclkx,' B! ]3 k4 H' X/ ?8 M: p- l" N% A
input axr0,; a! p* f7 k+ y! W @' m
! z s2 @5 |! I) h
output mcasp_afsr,; d( e* I( M! x1 n# ?
output mcasp_ahclkr,
: U" E# x$ ?* v4 N" k7 G Goutput mcasp_aclkr,
- w; Q8 e! {. K- poutput axr1,8 ~; p( y) m7 @
assign mcasp_afsr = mcasp_afsx;% v7 \% u1 `2 h8 H. X7 E
assign mcasp_aclkr = mcasp_aclkx;
, l' C; f; Q3 a( f9 dassign mcasp_ahclkr = mcasp_ahclkx;
' z$ a1 o3 v2 t% v( T* Yassign axr1 = axr0; 5 N7 k/ T& l2 z, ]- [( i
: _! |+ C& Y0 V" G9 Y9 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; G1 _* {& B6 m7 b! \) |
static void McASPI2SConfigure(void)! p: B _; { }3 Y( y
{
0 E# A$ p% c5 b( ?& p/ N% xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# x, F" X/ y' `5 Y4 @
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 X, D- U7 Y8 G/ a: q6 O$ nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! G% e+ B/ \2 H* M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ @0 }: N6 {9 d2 iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 |* c- ^% z& ^0 |( H6 B }9 M
MCASP_RX_MODE_DMA);
, ?' {/ `3 Q. MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 a" @, ^5 |- P" B4 h2 u7 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. F! ]5 u$ a" |3 y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( Y F: m1 n7 B/ KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% i7 ?8 v( [: ^% @" r% ?% g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; b& Z, _; N2 V" G) K; `4 yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* }6 }+ [' E6 [McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: S, n' ?( ~/ L) dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 m) l4 ], o# G1 M9 [4 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 I$ G& _; `! ?) M/ `5 O" g1 e0x00, 0xFF); /* configure the clock for transmitter */
# D# {. W, {, ~! E4 [7 YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) {$ W6 [3 u( N1 D% F: FMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; q0 l- u! w4 M9 \1 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ A) f' o( @ D" u$ _& ]
0x00, 0xFF);
1 k) z9 Q3 L0 f# E; o2 Y; R$ ~; T! U7 F G
/* Enable synchronization of RX and TX sections */
\4 q( x6 L, J: S$ XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 E F$ B% L9 Y* q
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( y8 B2 a8 c ] O9 c5 v L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 H ~2 n% u9 C& w' _- Z. `6 m* g
** Set the serializers, Currently only one serializer is set as8 N) D( I W4 k& X5 ^" S
** transmitter and one serializer as receiver.8 E! Q! U+ {2 ]) F- S& ]' D0 F
*/. a$ ` G& Q0 e: p& r" ]! ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
m% C" ?, O& a8 Y' D0 d# }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( W& Z( _5 p& U7 y1 W
** Configure the McASP pins , S' A* D( t9 _
** Input - Frame Sync, Clock and Serializer Rx
& M7 T+ Q, |4 ^+ V: O8 I b** Output - Serializer Tx is connected to the input of the codec
) t% e; t+ P. ?3 J*/
+ w- o( A% O3 O# iMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! s, {8 Y* L, f; O9 p3 Z" r3 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 L/ l5 K9 L1 w
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 m4 Z+ ?" V E3 @) N| MCASP_PIN_ACLKX; W, ~% x |8 ^* {
| MCASP_PIN_AHCLKX
1 D% i# U% _6 y6 z3 L- N- _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 c! S; C! _' u# K' a& G/ GMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ Q9 @ d- o% j& K| MCASP_TX_CLKFAIL 8 u$ Y5 o c# I8 Y v ~
| MCASP_TX_SYNCERROR$ S6 E) [7 o% s; r2 V. a
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 U: P8 f( ^( c) O) }. k: O4 S6 h3 C
| MCASP_RX_CLKFAIL- K3 {4 T8 _5 H! N7 C+ X1 B2 A, p
| MCASP_RX_SYNCERROR
9 N, I5 ]& w. R0 K- @| MCASP_RX_OVERRUN);
8 k( p# ^% W# g6 z8 q8 C} static void I2SDataTxRxActivate(void)- I( ?7 J( Q6 c
{% t' [6 t" ^9 }( k a
/* Start the clocks */8 j1 I4 c) v3 Y6 J5 i0 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 \1 |! F) F! l. Q* y! f0 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 ?6 o: Z+ Q7 r: O, z8 \" ?; m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 I7 y6 F8 d. d& A7 vEDMA3_TRIG_MODE_EVENT);* ~% |2 u2 N, @2 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* }& ?, x& Y0 p9 J9 V/ ^+ `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ h. V$ \+ {3 k6 j: F; k( s" y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); A8 _( m% a _ _3 _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. ] l7 Q; [1 G9 Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 @/ X+ L5 J6 @& K9 a8 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( o1 e, `7 H2 W8 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
r" }/ h! C5 s5 P2 }} H0 g9 o# i2 N; K! N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : j+ W/ J. e% i8 y/ `/ o
|