|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 @- `2 F2 T+ {input mcasp_ahclkx,
7 M! W% i' D+ x) t% winput mcasp_aclkx,9 Q" W3 G7 d3 h
input axr0,9 ~' c7 W8 }9 h3 a3 B
% V9 O$ m, _7 B5 O; t& xoutput mcasp_afsr,# Y" J5 w: n! w9 X4 R) s
output mcasp_ahclkr,
1 B% O' X) I2 R* N4 ^output mcasp_aclkr,0 @) g2 a/ Z7 [ y
output axr1,
# C+ M( X, _! P2 ~) r assign mcasp_afsr = mcasp_afsx;
1 X6 q; `/ [) C4 S: xassign mcasp_aclkr = mcasp_aclkx;
3 b9 F4 B$ k/ N8 j0 @% l7 m' F o% Uassign mcasp_ahclkr = mcasp_ahclkx;. H8 t4 E. R& i0 h. j2 }) l
assign axr1 = axr0; ! j; M5 q' W! P: S
0 Q5 m7 h: u6 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; Q" W5 V& l# G# o7 Q
static void McASPI2SConfigure(void)
0 N2 z+ U5 @7 w- ]1 x6 r{
" a) `8 P8 j# U& q8 X- FMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" X: {+ [. v K" s7 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 ~4 r8 a) E" ^3 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: S# X q0 C( j' t
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 N' s* p+ s: P* k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, R! H& Z$ } D3 V! {1 c, P- RMCASP_RX_MODE_DMA);1 f: O5 c" n7 q2 y4 \; @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& D6 q/ @+ o4 g _9 q$ }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ u; m7 l$ t5 N: {" e3 X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % O+ A2 D3 W @) L+ v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 U0 e/ ?9 M& p1 W
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , ^6 |+ ?' Q7 W; ?4 X1 p% Q6 J2 ~2 L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 L* g) {: K' `+ B h$ E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 m: T3 e d, R% a, Q. zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' u2 T- V1 X: Z+ R7 @- P6 f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, G" t0 R T% m( @7 Z" n2 @
0x00, 0xFF); /* configure the clock for transmitter */
' V7 g3 U8 z# F& r; ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* K- g; g0 E5 z( n2 L( F. MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! W" G, a0 { O+ Z' B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% j, i$ l6 \0 V+ }8 W1 m2 g3 g6 k
0x00, 0xFF);9 c1 {' ^/ w5 ?
* t% _" l5 [3 X. _& R1 A: e. d/* Enable synchronization of RX and TX sections */ 8 }, l- g1 d0 G* L% E5 g8 V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ Y3 ], W& c$ K3 ~( lMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 y4 {: Z; d" M6 p9 QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 e, q; ?$ f; S. M3 x: t** Set the serializers, Currently only one serializer is set as
# z: {/ L V/ z, I** transmitter and one serializer as receiver.: x, P- g0 \. F: v; ^8 k8 e! j
*/
4 V. k8 H9 w2 U- P5 }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 c& y' \. P; A) N3 i& V* PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; S1 \( ~* q6 _** Configure the McASP pins - w/ ^% i4 H: |
** Input - Frame Sync, Clock and Serializer Rx2 r2 K( e8 z9 @* n
** Output - Serializer Tx is connected to the input of the codec , S6 c4 G7 _. `$ D% f h1 f
*/
8 j! @, j; G" dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ @7 k) L2 a3 U" W; n6 V& ]5 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* J% C% D1 `' [0 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- ~8 M2 p4 M. z0 X3 `
| MCASP_PIN_ACLKX
) l- W* R, V3 a" t1 P! H+ ?| MCASP_PIN_AHCLKX
' W n x: |0 ~8 o C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 s7 S. U, _; H/ G. |* ~5 JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' p0 N& I+ i# _| MCASP_TX_CLKFAIL
/ y9 N9 ~! t( ]# I- |& y7 v1 L| MCASP_TX_SYNCERROR+ B. @6 J. c3 w/ d# s7 _8 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; W- Z h1 |: f7 L( M) l- ?0 Z4 [
| MCASP_RX_CLKFAIL( y! I2 q8 |* Y* X8 M
| MCASP_RX_SYNCERROR " r# G$ R& r F8 A& u* O
| MCASP_RX_OVERRUN);
, o% N- g4 J* W4 N/ {2 q. x/ u} static void I2SDataTxRxActivate(void)4 q. @( n7 O+ A) J
{% M" g+ h8 [$ k) G5 X' p. N& P
/* Start the clocks */
6 G( D! g. E9 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ y/ @2 W$ ]# ~: x. J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 Q& k' C( x( N3 ^6 a2 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 v, d6 G! m4 }- J
EDMA3_TRIG_MODE_EVENT);
8 Q1 o+ ?2 y" f/ R0 H( Q% Q6 p2 @4 QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- b" u! j) r* q0 C# O9 w! @/ M# JEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 B% e/ v# e( `$ @% d d! ~5 [
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( W3 x; y; h/ O- K% F5 j( T/ K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* t6 i' I# k8 u5 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! F- @, d% ^( h5 w5 o
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! S5 V8 S- \) g9 V! l3 v8 J: sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);% G* v) b1 W' A% l
} , l8 k$ v6 [' V7 D" O- o' E
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
7 b# n" V4 s2 g: l |