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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! i8 ^' |" [6 |. |1 g
input mcasp_ahclkx,( q& H% R. L) m; k1 {
input mcasp_aclkx,* ~& j% o/ `7 I
input axr0,
3 q, n2 f# C7 j5 l- F" B# c
$ K. U6 v8 ?3 _# H& ~output mcasp_afsr,
9 W+ P" p: r" [" s4 [8 d) u6 loutput mcasp_ahclkr,2 }$ |/ C0 F; {: _9 X
output mcasp_aclkr,
7 h! h' k5 r1 ?! F: [output axr1,: J6 N1 S! o4 o- q1 b9 Q1 Z
assign mcasp_afsr = mcasp_afsx;) E+ p) Q2 A' y! A/ } ?
assign mcasp_aclkr = mcasp_aclkx;* h( Q0 H9 R& a' d9 I# j" S- n
assign mcasp_ahclkr = mcasp_ahclkx;: Y+ X1 z& d- A+ T* B6 D- r/ L
assign axr1 = axr0; 2 i& ^' v# z- l% d8 \/ K
5 G8 ]* {2 {2 N1 ]1 c: _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 p: B/ l+ Q Qstatic void McASPI2SConfigure(void)0 I) \, F+ w, V% P+ ?# L0 i4 V
{, V+ K. M& v5 U+ i2 ~" V7 [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) v8 F, i. g# a) h& f1 CMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ _3 n. i8 f7 _* o4 rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 w* x4 k2 `1 x- V& S% c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. Y; K; ^& N% Y$ c% q2 _: E. vMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( L0 {# u9 x3 m/ ~- p, i
MCASP_RX_MODE_DMA);
4 W/ A( U+ F, d3 a8 q! M) I0 [# i/ _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ \6 L; I! y. a! p7 w! rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 R' i5 q: g# P0 ~ c* VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' T# z% k# ]) ], tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 M+ e; e1 H' }" R# x( qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : m2 a5 ?6 e0 j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( o5 S: L3 t3 E: L. ?, _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ j* e8 H- s$ `% hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 `. ?5 j% D3 h$ ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; @! G, ^7 r# c6 C) t5 t0x00, 0xFF); /* configure the clock for transmitter */
" P" S! i. n* G( z% T. j# t$ BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 D9 ~5 V# u& k$ M) a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& y. p3 o. `0 R0 yMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; x6 C" Q9 X9 \) r4 \0 e( v& r
0x00, 0xFF);
9 u7 E2 l! c- @- a/ d/ }
; n9 m; P n- b9 T) \1 \' C% _. T t/* Enable synchronization of RX and TX sections */
, B: I9 n/ U* I' f7 _6 k# W6 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 E# _/ t: Q' }- t6 p) l; U
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 x+ \6 D: V( _) f* D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. a' u V9 K$ ^
** Set the serializers, Currently only one serializer is set as
, D) R1 [+ O6 N, J+ K0 h' W** transmitter and one serializer as receiver.. R% Y% e0 O8 C* _* u( u, W
*/0 ]% B* X9 M1 h A- q/ y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 L ?4 u$ B% t; HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: T4 q& @; G' \* \
** Configure the McASP pins
* U% D+ f) u0 O, D' T* g** Input - Frame Sync, Clock and Serializer Rx
' a" V7 i* m1 q8 F; @, L** Output - Serializer Tx is connected to the input of the codec
1 n& O. Z5 P7 h+ j4 w*/
9 T [; x+ ] O1 V A* wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 D- p* P5 ]: q7 ^* N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ ~% ?- m3 {2 I N% HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- k& z" K0 k/ q& B% d
| MCASP_PIN_ACLKX/ x% h; }7 b; n0 u p$ C
| MCASP_PIN_AHCLKX8 J/ l4 z2 f& J( t, z; H! R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% c8 g7 L/ @" n( ~+ A$ \+ o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 d# c' q- ?! B" b
| MCASP_TX_CLKFAIL
; q# t H1 w: m9 \$ W| MCASP_TX_SYNCERROR
3 X4 Q' [% m: v3 U2 d5 }# A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " s3 u. U- Z2 C5 }0 f/ ~ j4 w
| MCASP_RX_CLKFAIL
$ |3 n) ?4 Y ~$ l| MCASP_RX_SYNCERROR ) }. M6 o7 T9 Z3 [ n
| MCASP_RX_OVERRUN);, C0 H8 D: u6 Q) a
} static void I2SDataTxRxActivate(void)$ @ s$ K( A; z8 Z/ ^+ o
{; P+ |& D$ ?$ f. O0 J$ b
/* Start the clocks */
1 }# G3 D. x) Z+ W% |! j& kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- Z/ i2 q) m- MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; w4 I& }1 G6 m. o* R. S7 a* H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. `* [ X; W" [' x- Q/ v
EDMA3_TRIG_MODE_EVENT);
! s* P3 B& p0 H) ^, Q* DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) t- _/ h- ^% u9 |! J6 a) f) Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 I) h f: F+ d8 ]& L5 X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- S/ g* ~3 Z* p- TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 o! n! V8 {( }, S bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */( T" b& P2 V; ]; S9 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. Z3 |5 y8 ?8 L: iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& q' e6 u) o) R
} ' B, g; j$ l7 z& D% ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 0 i+ k5 a9 m5 f0 x0 `4 c
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