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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 h/ U0 k. D0 ~4 n
input mcasp_ahclkx,& ~8 w* z# V8 P5 x# B( F5 w
input mcasp_aclkx,% X5 M1 N6 w1 Q' z' q* P
input axr0,
0 C i7 J3 J# \1 l
- E- ]" u8 b" ~& zoutput mcasp_afsr,' ]: e% U$ r! T Z( [' O
output mcasp_ahclkr,
& k. H% K& E* O6 }0 N, V Ooutput mcasp_aclkr,: |2 E0 ~+ U6 }
output axr1,
6 k9 A8 A- O0 J7 Z$ H4 w/ l6 Q. I& ~ assign mcasp_afsr = mcasp_afsx;
& H- C( c$ ]7 I, v) O1 z ?1 oassign mcasp_aclkr = mcasp_aclkx;+ x8 W2 t% j/ D& H! }
assign mcasp_ahclkr = mcasp_ahclkx;6 |, i9 K: d* S1 `4 l5 \, i
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. X. L2 h( U9 l) D, }0 gstatic void McASPI2SConfigure(void)
/ B. F+ N) O& }* V6 N( p, I{
! W# \4 I- t8 V0 X2 I- oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 Y3 X$ \+ a5 Z% Z# L9 b: d! A( v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, Q8 V( I& b7 h. j" {1 ] @McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. W& ]( C8 K5 g6 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 @/ Q" Z2 w3 q" YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 o" Y8 H+ d# D, O. d4 r6 J: CMCASP_RX_MODE_DMA);$ H0 h% w- H |& K# r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- R' F* N- V7 w' q) Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 y- T8 g, p6 B8 }8 H; x- MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 M! p: x) T g1 Q# W1 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* ]' R/ c8 w2 d" X8 G0 W) N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 k( o( D# Z2 h4 G. s( NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 J" v9 X6 L+ |/ A6 F! W+ dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# O# M- \# U/ I5 S9 e! k# G8 U% K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ g' `1 ^1 H0 kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, A& r( T8 M* ~) V/ U3 K0 S0x00, 0xFF); /* configure the clock for transmitter */9 F K; ~4 E+ ^$ q( ~6 K1 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 n* x& Z% v/ u9 mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 Q0 F" V) f: t% @! Z' qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, Y* `5 a5 j9 Y
0x00, 0xFF); B6 r/ k9 L) q& V0 R: X
) j, ]3 }0 @2 t; m4 Z/* Enable synchronization of RX and TX sections */ + I7 k2 a j! Y, b5 {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 O, D( v5 l9 H
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: b# g8 o$ r1 t* J0 H/ MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# C5 r ~' p9 d& A C** Set the serializers, Currently only one serializer is set as3 @# f- p. K% ^ G6 t3 m6 v
** transmitter and one serializer as receiver.
4 v5 b1 L# a1 P" G! X, P+ I*/& R4 J) L1 Z% j. b7 o6 J. ^1 U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ g) ~2 O. ~6 x9 L) a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ L4 r& r! l* D& o* v** Configure the McASP pins
$ ?' }" L0 w$ G$ T** Input - Frame Sync, Clock and Serializer Rx
& I$ s& C8 X+ N- W7 P** Output - Serializer Tx is connected to the input of the codec ; ^: ]+ o& A' j3 ^& D( \
*/
$ t+ O9 H" f+ j, S+ ~' @McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! B* a3 v0 P3 w& b) Z& A# P$ z' }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 C' z" @4 \0 L9 |% z7 IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% A2 S. Y% i* v8 R3 N| MCASP_PIN_ACLKX* R: Z2 N/ e2 n9 N+ [$ M& U- R1 @
| MCASP_PIN_AHCLKX2 p- Y `" p# ~1 M- i! F5 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) i9 Y* k9 f& Q7 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ J/ N$ f9 b2 l7 V
| MCASP_TX_CLKFAIL
3 A4 ]1 R$ n, ~) I| MCASP_TX_SYNCERROR# P1 d9 c3 g- j3 l1 j* D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 m3 L( e$ K2 ^1 e| MCASP_RX_CLKFAIL0 a: `; ]$ d7 `6 C" @5 p
| MCASP_RX_SYNCERROR % N2 d% x% @" X
| MCASP_RX_OVERRUN);
) O F9 D/ v( p9 x3 Z5 ]} static void I2SDataTxRxActivate(void)* w. D9 |# F2 n Z6 }1 o
{7 p% N x; V4 `. S0 p& {
/* Start the clocks */: U$ A( W, l* L( n
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; K* t0 |3 t' {# A0 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, h# d; @8 c& aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,$ l( \6 v# S! V- L) }
EDMA3_TRIG_MODE_EVENT);, ]4 U. f3 ]5 x6 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * R9 |. A: w0 Q9 U8 T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 k7 V; Q) j/ T# g% b) yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 W" _. C) i6 Y2 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) h' h4 |/ [7 y2 Z( a' q6 Q, swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 W! E+ Q C6 F+ { @5 P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
T0 T; D5 u2 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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( W/ _4 M8 c' \& R6 {! b! ]1 y3 ~请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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