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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ p3 {2 K8 l( M
input mcasp_ahclkx,: g4 R$ ~, e' n
input mcasp_aclkx,
$ A: j1 ^. S( P; v4 O% Qinput axr0," C- c3 F" o$ M V6 c
$ ?7 a' r. \. J8 toutput mcasp_afsr,
3 w0 `4 ?: }/ F3 N/ ]4 H6 x4 youtput mcasp_ahclkr,
& T7 E3 \# X9 loutput mcasp_aclkr,' H* {, o2 C! v+ z
output axr1,
3 [3 @ x* T6 ?. V' K assign mcasp_afsr = mcasp_afsx;
3 j9 g, S2 _2 Xassign mcasp_aclkr = mcasp_aclkx;+ G/ ^/ y; [* K# J0 p! v* _
assign mcasp_ahclkr = mcasp_ahclkx;
7 u- Q8 {( V3 {assign axr1 = axr0;
5 H# P0 S7 N2 p, Z! A
6 T2 c: y, z1 W( H3 ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . s7 }& _! `- b' m& y6 l( U" S
static void McASPI2SConfigure(void)7 V. i$ N3 M8 `8 _- }
{
7 d' C: }: {5 l TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 R( d C8 ]& z) d7 R0 P& fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
E) M/ x @( H( d6 _- eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ x# U; y2 q& B5 D" S9 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 U+ U7 f; f" \" ^$ aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) ~7 _% A3 I) F. V- j5 ~
MCASP_RX_MODE_DMA);+ L) z! K0 S6 n; _. B' ~- O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' I2 Z( Q5 ~1 U6 `: @+ E! n$ E( Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" l8 ^1 a: }, H+ l4 I5 {
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 L! I8 s, v& ]6 ?
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 m8 f1 A1 @, CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + r% Q+ F. Q" k/ U1 T9 V
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. i q, a: C6 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 w4 O4 r1 Y; c0 w/ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : H6 k& y* _- t; s1 T# Q$ U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% p9 j% w1 p# k p) N
0x00, 0xFF); /* configure the clock for transmitter */3 Y0 q! F8 s! R( ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! F& Y: p! u9 V' Y* O, C) [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" d. [" z: Z, ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! e- ^3 N) X% w7 f& T
0x00, 0xFF);7 q z) V% M) E- ?: z) R& Q+ Y
0 G, M% S) a/ L" W+ v/* Enable synchronization of RX and TX sections */ + z" Q# B B) J- z; f8 y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; `- j# y f0 G8 M, g, x8 o5 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* f ^; r% E, g* ?; C- {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; v2 {8 }! h* \0 L. K& t% T6 Z** Set the serializers, Currently only one serializer is set as
5 E& [7 }6 t) m. e5 Q* j: j** transmitter and one serializer as receiver.& [6 B7 K* {# l% u
*/
+ R4 j9 t) d/ E# I' G) Q8 JMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);6 _ r: C7 `, l7 I2 L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 z* p3 @# y' ?. r7 S** Configure the McASP pins
) C) i y# j1 @8 Y# l8 [** Input - Frame Sync, Clock and Serializer Rx
2 k" g5 y9 R3 n+ Y** Output - Serializer Tx is connected to the input of the codec . [% m/ Q% b8 ]
*/$ r9 Y$ _0 F5 s4 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( ?" E5 z/ v# I1 i( Y J+ e
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 E2 l0 _ R4 b& @( E# L. ?2 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 a, E8 Q1 W+ y4 Q ^* s| MCASP_PIN_ACLKX
6 W# n2 ?) R. f. `5 `0 l8 W| MCASP_PIN_AHCLKX
* H0 y* ]7 D, u! G+ O, F/ H/ i| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* Z- h9 H4 d# |( s2 }7 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " E4 _) g5 L& J4 t3 [% F2 B# Q
| MCASP_TX_CLKFAIL % {$ P2 r6 ^8 @
| MCASP_TX_SYNCERROR
$ Z& l$ h% I5 V$ J! i# A/ D$ k) v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; H0 {6 c; W4 M% f
| MCASP_RX_CLKFAIL+ b) Y& T. _7 j( H; I/ ?" j
| MCASP_RX_SYNCERROR
& T: T; U. \ k1 K7 u2 u| MCASP_RX_OVERRUN);
9 j7 m( K" e2 b- ^ [/ C} static void I2SDataTxRxActivate(void)
. B- K! ]) |. j{
+ n! E0 o ?! e; P/* Start the clocks */) _& n% \# j' `" X- t+ A- T( o8 }
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 `! L+ r9 V: `6 y8 N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* _2 d8 |$ L. g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 P+ m' B7 s2 f& m# iEDMA3_TRIG_MODE_EVENT);4 {: A/ ~0 e5 p. m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . O9 o8 d ]" T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 f p8 d' o8 s/ oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( X6 o+ F0 S" @7 z' V) YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 m- F* _3 q, J% j% C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
P# \6 V+ n$ PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! U3 e+ \8 S( A3 R( mMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ E5 x8 V, n) I5 G# \ C$ \ o} + A# P! W' ]8 W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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