|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: A& O+ Q3 E5 ]. Jinput mcasp_ahclkx,
( u# A( m) x9 o* x8 v( ?input mcasp_aclkx,
* }# B" X5 x7 c6 c4 w$ ~ C; `input axr0,
3 V8 g; `2 U+ D8 M& e
% C/ U" n5 @* Y2 ]$ b5 d/ j, ?output mcasp_afsr,! q1 b O: {; X& T" V) F
output mcasp_ahclkr,
; H" P0 ?- @& F0 T' V$ T k- u( t% Noutput mcasp_aclkr,& H5 p! g4 Q7 Z
output axr1,# ]. e% X9 B/ u
assign mcasp_afsr = mcasp_afsx;3 l$ Z8 s3 {7 j8 d. L
assign mcasp_aclkr = mcasp_aclkx;2 B: t5 ?8 v6 P( q9 U) C3 Q& U
assign mcasp_ahclkr = mcasp_ahclkx;+ t; ^9 c: ?, h# i5 K
assign axr1 = axr0;
0 { _' c4 ^9 S: w3 i. P' N! \' }1 G8 X/ t* h! L
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ c; |" H+ i* c0 _0 n7 B* u0 p
static void McASPI2SConfigure(void)( E- R% ^9 ]- [* B# J1 f* w) F
{
E1 ] i/ {+ @1 F9 x" t6 ]/ xMcASPRxReset(SOC_MCASP_0_CTRL_REGS);* P1 m0 D6 p% a# E: L! N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ I- u" p' k( g; C+ T2 V" o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# D/ s0 D: {6 x/ q5 Z1 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 U4 E+ H: o1 h+ A9 oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) z1 h' A \5 A4 U) y" w* \! C0 g
MCASP_RX_MODE_DMA);) {0 |& E8 y) E/ b) d
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 ]; t- Q" H+ N2 IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" z( i) q! z' ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 X0 u1 C6 W5 \# \& R+ k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; v1 r$ m$ y3 n! o" c2 a3 u. ?McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 l4 \% ^+ i, k8 l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; ~+ {1 \$ b9 S! T0 C# t: I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 T: X8 I7 C: p* C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 F: N) B9 _; d0 V
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. y/ F" ^, v% l4 d, \0x00, 0xFF); /* configure the clock for transmitter */1 o$ n& M1 Z% [4 W3 p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" [4 m3 H4 `: r3 V P( rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! R9 H; ]6 m1 D# h( ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, @: i9 Q7 N; m) M6 W" O2 `; s
0x00, 0xFF);
" s, i3 x5 `0 K. k/ k& g, z+ @1 v
: ?6 q3 R" `/ M( y7 t! H- W+ o/* Enable synchronization of RX and TX sections */
$ {: V/ |0 r0 FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 O. D; H) J( Z+ AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 R, G4 ]1 K7 U8 x8 _, [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- O1 ?' S7 |2 O9 Z' |7 I4 v** Set the serializers, Currently only one serializer is set as
8 b/ ^( ~3 ^1 }* N- G# g& F! K** transmitter and one serializer as receiver.
3 `! d, o4 ^- _8 Y# s$ p*/
$ h. d, G( ~9 U4 AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 P3 T F0 G! T/ ^" CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' H5 t8 \* | J3 R: o
** Configure the McASP pins 8 Q+ {9 e9 M. L( @$ ^9 T! o
** Input - Frame Sync, Clock and Serializer Rx
# _9 v- H4 q1 V7 `' e9 c! c** Output - Serializer Tx is connected to the input of the codec 2 j" \$ e& ~( ]
*/5 k& j8 m% a9 I+ a `% L4 ?& V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 X- g0 a$ d7 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 E0 T, o' v& J9 A% ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, ^# B8 [2 R# F, t, a" H4 q| MCASP_PIN_ACLKX
3 d( x( k, |7 v% t9 ^! d% T3 t| MCASP_PIN_AHCLKX
+ j& s8 r. t* F1 J* x, d| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 ?2 r7 q) ~* w' N" T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) q' L6 N* @( F5 R| MCASP_TX_CLKFAIL
% h- a, q( j# e, s| MCASP_TX_SYNCERROR
! X/ e4 ?$ `9 k+ E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 h3 x* Y+ D/ N4 k| MCASP_RX_CLKFAIL
9 C; m& T6 W% y0 m3 @! b| MCASP_RX_SYNCERROR
9 W. z' P$ l* [ E% ]: b9 s| MCASP_RX_OVERRUN);
4 J' q- |& }' Z, r2 T} static void I2SDataTxRxActivate(void)
1 J" y( k$ k+ d' w{
8 q O0 H: @" r2 W% x4 b% a/* Start the clocks */
; P& z* B; t' g! D9 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& I2 T' l1 i7 ~6 H' H6 b2 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 H# |, u' b0 Z* c1 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," ^3 y9 i7 n p) H' q; [
EDMA3_TRIG_MODE_EVENT);
+ r: ]% W$ e; o; K* MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' M$ h$ Y- E! ?/ i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 k7 B7 j h+ o3 |$ F: k
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) M3 W! N- G' u$ [8 ?# d5 r5 h, a
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( g7 R5 K2 l# ?8 h0 P/ X' Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
) x5 E. u) q# K; R- u |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 D: H1 q/ T) g0 h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' s1 D" v3 U# K4 \
} 4 t/ x' ]+ @. g) z- F( a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
0 P; P: W% X" }$ r7 _; J |