|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 G8 S9 e% r" L9 r3 y0 j# Z
input mcasp_ahclkx,, ]6 [' c k" h4 H G- l
input mcasp_aclkx,4 P, g: W3 L1 R- p) S
input axr0,* ?7 `- s+ a6 R4 c" K) y( c: i
8 z" E, G% a$ x+ D3 y+ u/ woutput mcasp_afsr,
2 @6 O4 [# { N& m: k: X* eoutput mcasp_ahclkr,
3 L5 l$ T6 b3 ~& |0 Routput mcasp_aclkr,
1 z8 N$ x+ |. }" G( I% }2 U% coutput axr1,7 f r! p8 K; j; E8 S
assign mcasp_afsr = mcasp_afsx;
7 M+ T! r- [+ [" o: S3 T, L- F2 V5 W, iassign mcasp_aclkr = mcasp_aclkx;1 o& { V; M% V4 j
assign mcasp_ahclkr = mcasp_ahclkx;6 ?" T5 n- M% b/ C8 g
assign axr1 = axr0; 2 {# N0 A* e1 k f2 u. i! _
4 N! U2 @' t6 E; e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 n% d# Q K) ]: B5 {- Ystatic void McASPI2SConfigure(void)
& Q: u2 @1 L/ u. [3 \* D{
) d8 d) T/ {+ gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 b; t% } h6 y6 I5 L2 Q
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 v% y, f$ t, _5 w- ?: _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# J( B+ p3 R% r; |/ k v Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 b n; ]5 g! P5 `) y8 x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 j4 @! G: a5 I: i
MCASP_RX_MODE_DMA);
5 [# Y1 H8 R* }McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
o u$ y* C( z$ n3 `# v# O# ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( r4 g7 r2 g k6 Q2 w4 sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) o/ W* L% V* A" xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 E" D6 h1 S$ _7 J( J% i* b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( [& J' c" p! Y/ v& D' S2 Z" pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" b2 n, g' z, z; x4 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 p. D* ]8 `% Q i' E7 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% k7 [6 Q/ c4 HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' Q" [1 b. E+ V& x( X5 w0x00, 0xFF); /* configure the clock for transmitter */2 B# l+ M7 f9 ^. z- a# v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; q& q+ n) @& q& z0 F) ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* ~& ~- o) E, w: w' DMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ G; |" e e2 p
0x00, 0xFF);
) d5 g5 a9 k! n) c8 E7 s& c1 K+ K6 @0 k7 Q' h$ u: @# W
/* Enable synchronization of RX and TX sections */
" l9 R% t/ t% t: z) o& H4 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ ]+ \, ` B* C7 |. w# ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: S% v1 I+ W' ]/ O% q/ p- xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 C0 C9 k0 A4 T6 p3 U** Set the serializers, Currently only one serializer is set as
. P: H# t V% r9 @, V** transmitter and one serializer as receiver.
+ o7 X4 @7 s8 ]. K3 t% n*/6 M- k) q1 L3 T8 E5 t
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: R- k- X: r: X8 F& z, wMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
h& f5 ]' W) W! c1 G+ f** Configure the McASP pins
3 ?2 l4 {' L' T** Input - Frame Sync, Clock and Serializer Rx3 h2 M- ?' N" J, m
** Output - Serializer Tx is connected to the input of the codec + G5 R. {" M. k! z7 b% X* |$ v
*/
, Q' R7 j( J$ D \7 `2 X7 D/ V& HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. K/ J' G3 j: |0 k3 ` M9 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% q3 U5 ^" X/ `% Q( V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% }# N. f9 w3 B m" O' F
| MCASP_PIN_ACLKX
0 d4 E7 D o/ I% v* L9 F1 C7 \3 O( Q& H| MCASP_PIN_AHCLKX
& W: ~2 w, r T0 W$ g! }% b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 h* A( }; f" _" Y b$ N& lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & [; P" f5 L& ]3 H
| MCASP_TX_CLKFAIL
8 C" \# S* I: u3 ?| MCASP_TX_SYNCERROR
" a6 |5 t# k1 t% d: f* j/ e+ P- e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 k" W6 R# L0 ~1 S& q| MCASP_RX_CLKFAIL
' Q* m1 \# q( v, B. M5 W4 n: e| MCASP_RX_SYNCERROR * e0 v) z4 W$ Z) h$ K
| MCASP_RX_OVERRUN);
w G7 T7 `. x8 ]1 t0 }/ H} static void I2SDataTxRxActivate(void)
' a& r3 c, J {* b+ i{% E! O# G: z: z1 L7 @3 K0 c$ S
/* Start the clocks */
0 [* G; W# ^# E4 }: bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 v7 a$ o& c+ B- V* Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 t8 n( Q8 t; n: P5 N& D/ Y! t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 G9 k* p) i2 K1 }0 v. AEDMA3_TRIG_MODE_EVENT);* ~- v: ]: l2 G& ~4 H, z" |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 Q: E8 C c7 Y& a) |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 D& e3 p$ A# f! b6 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% D, J1 [- p b8 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" p8 b3 A* ^: V. U3 x# Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; ?& D) ?9 U% e2 M: r, y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% {1 c+ x7 }& u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 g; a) {) q7 C8 v$ M, ^1 f}
, _ Z1 a3 v( X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' W4 f R- N+ U* C8 x4 G
|