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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 O2 z0 g4 l$ f
input mcasp_ahclkx,: S3 h, Y: n4 k2 r1 V
input mcasp_aclkx,
0 h1 l+ ?- r& Linput axr0,
% ^7 ^ D& I- h
# m0 I9 m1 |, c1 B8 Moutput mcasp_afsr,0 I S5 L2 O' C
output mcasp_ahclkr,
% D, P- _/ I7 T2 R! p5 Voutput mcasp_aclkr,/ v/ }3 w- H+ m' f# ^( D$ R n+ B
output axr1,- u7 {! H% z6 I, C3 @9 G6 X+ C
assign mcasp_afsr = mcasp_afsx;
) O: S s- u8 z+ X( t |; Jassign mcasp_aclkr = mcasp_aclkx;: v# Q& C1 R4 J0 v, B
assign mcasp_ahclkr = mcasp_ahclkx;
) M6 v. Z/ J0 P# Aassign axr1 = axr0; 0 |- ^4 ~, i( {2 g
5 L8 c' l% r ?; Z% O6 b S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% q) H+ I5 _; K7 A5 ^! Ustatic void McASPI2SConfigure(void)/ w7 r5 R4 F' E
{& h: r- H; D" N7 D4 I: D: p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 R4 y6 p% F/ {) |3 m" W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% L( {; G% B9 g5 M" Z+ JMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! B* M6 d9 C( v# z+ K) ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 U& H! Y' n% k* ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 |% c1 h$ K) g. c. d7 ^4 NMCASP_RX_MODE_DMA);, f6 B5 {8 i9 m! S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- L/ g* W+ R- g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! {4 H; I2 _9 P" I( n3 \, VMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, O8 O4 {6 ~2 c& R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 X/ z* L; c, x. _& wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ S) V" J! R4 k4 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
_8 @4 q1 X5 S$ m2 |/ rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; K. \8 B, ?- d' r3 Y8 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 X' u, G: \' i" T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 R* E# {4 @9 X3 U6 T, M/ B: p
0x00, 0xFF); /* configure the clock for transmitter */
/ `- K9 G, D1 r7 w6 MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ ?& q" t6 `$ i* A2 w n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" M1 U+ q) \" J1 M! UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 o! Z, W6 w5 M* C% ~' C2 X5 k7 _% o0x00, 0xFF);
" Z6 i7 Q! p. c4 d, |( N! Y" D' C* z! j3 f4 M2 J, ` F! n
/* Enable synchronization of RX and TX sections */ 3 G1 B+ ?! x! N k& }: {! f
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 F2 {5 B) B- D+ s7 C n0 ^% b1 R8 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 s, x$ _+ f0 _3 A0 m8 R/ t5 ?7 {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" g& T9 s7 `+ P- A# L% @! ]/ U! j** Set the serializers, Currently only one serializer is set as
- v) H- Z) D7 b6 j4 i** transmitter and one serializer as receiver.- W% ?+ h) f. I. Y2 S% A
*/
& l4 x% w x9 b( J( ~$ C7 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 Y" V6 c0 H& w! ^) ?3 E& C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
& [2 M" N0 o* ?3 L# I" j$ k** Configure the McASP pins 8 M7 P- O* r; u; J+ z p2 E% ~
** Input - Frame Sync, Clock and Serializer Rx- n+ z8 g# c9 v
** Output - Serializer Tx is connected to the input of the codec
: x0 \/ H& S- c*/
8 `1 C# _+ o- J& n+ qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 d' q! M7 c7 @7 P1 A q+ B! J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' x. F0 r& P8 Z* A! P! I DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 ~5 H8 z8 s* ^
| MCASP_PIN_ACLKX
9 D# `# f. E: ~- V/ B9 p) k| MCASP_PIN_AHCLKX
1 L2 `+ a9 J7 Q' I8 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, ^! h* f# L' s* Z0 Z; VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 m5 s: o5 C4 ]3 \+ k% C
| MCASP_TX_CLKFAIL ) @# W. @# L& g! G- P8 q
| MCASP_TX_SYNCERROR$ ]" H9 O/ u& |
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) ` v: O: f3 B7 g5 {; P| MCASP_RX_CLKFAIL
, p5 M2 [- M. O3 K P, u| MCASP_RX_SYNCERROR
0 E1 R& I& w. g* F* c; O7 H| MCASP_RX_OVERRUN);
. T$ G R$ H: ~, M- \6 t. p' N) U} static void I2SDataTxRxActivate(void)
" i# v) G, e- S4 S2 }/ p{
8 [% t: O$ @/ r6 ?* E/* Start the clocks */) R& e& m, P9 [) m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ `7 ]8 X a# W C$ i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 @( a( w2 v7 I3 c) {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 }: i# K5 d2 @, @6 H
EDMA3_TRIG_MODE_EVENT);
2 i1 G& n+ \. X1 p" k0 P; DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( E# _5 u0 O* C- s; m% L$ i' o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" F& h7 h% [ s$ w: Y# ^% R5 I: H
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% o' w# m1 d$ v7 r' c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# f( j. b2 ~% U8 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* }& l- c2 l8 }9 B5 Z* ]2 h6 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 p) v. r' p! x; i5 M4 u0 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# D! T2 P1 y7 [5 m
}
0 `* J! R! J8 W: e* W请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; V, X4 ?. C2 k+ d4 ~
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