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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, T, V' O& Z. F5 \( l! ~9 d9 C& S
input mcasp_ahclkx,
, Q7 ^6 l$ k: w! u" Y1 d; A% Zinput mcasp_aclkx,+ @9 g, T; d8 R! _% ^2 i5 L
input axr0,
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, R$ y4 R+ q! I/ @8 @output mcasp_afsr,
; |: E$ t* d7 r1 B% Coutput mcasp_ahclkr,
2 q, z6 B; z; y6 i- I `7 O* z/ C" Foutput mcasp_aclkr,3 ^3 ] ^! v+ @% T5 |6 r! d
output axr1,7 f3 [; Q* e# x- A- b* t3 G! f4 r
assign mcasp_afsr = mcasp_afsx;# p4 ?' r1 ]4 |- L+ W0 v8 b) x
assign mcasp_aclkr = mcasp_aclkx;6 Y j2 C+ W0 U2 u
assign mcasp_ahclkr = mcasp_ahclkx;
* I8 N+ Y. W) @3 ^/ Passign axr1 = axr0;
. a: Z, p: c7 ~: a. @* ~
# \$ H, ~) R7 ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 O' q4 a+ Z7 _- R1 V- Sstatic void McASPI2SConfigure(void)- s7 z( F! b) m' M
{5 v2 o0 T+ \1 \5 N. y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* R3 w7 [: q) T6 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ R1 `" u R6 Z0 g0 h( I( G$ g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ ^4 [7 Y$ H$ q, ~; J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 Z6 \4 g' s5 @$ CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ i8 L! |8 }9 K8 O+ B
MCASP_RX_MODE_DMA);& m" r8 H) W8 x& \% {5 [. _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( a/ @# F" G! QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& ~3 j1 G$ P+ K$ | H# c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 y: [# t) y2 s" ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); C" k/ t6 y, t: b: f9 X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : M- ~+ j1 C; L z8 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& t3 M, E" @% q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! s6 C* M6 E- w4 c* V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 a5 F' E+ n2 g# lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ n0 @ Q. f' s, r3 p% \0x00, 0xFF); /* configure the clock for transmitter */
4 b' ^7 _! [- Z: ^& C" |# U2 U9 `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; ^1 X) |9 A5 a6 jMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. B I: V' P" sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" `( ^0 D( P% {; R0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
0 J- j, E4 F, F# {, }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 H# ~! ^. c; m5 i" Z7 L, s0 R+ e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 G( K) I4 N# K) k1 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 B+ w, h$ N+ c3 u7 R** Set the serializers, Currently only one serializer is set as
# B7 Q5 m3 [4 V- j; w** transmitter and one serializer as receiver.
5 `# J3 K) E+ P% R0 i2 v*/ k6 C7 S( K) H1 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( A1 G1 e# Y$ R1 T, ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& Q/ ^- A& @+ s: V
** Configure the McASP pins
+ O! g5 z# w9 U! u; N" s. w1 T** Input - Frame Sync, Clock and Serializer Rx) \1 s- O P2 ~/ c7 {( g( A
** Output - Serializer Tx is connected to the input of the codec
3 R7 G+ m7 D- j g, H3 Z( j! Y*/ J) F/ _- E: F7 L/ }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 G. F' }: m8 O( S# v# j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- c; g+ A3 y& T( s( [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: O$ A7 b! ^6 X1 c, b+ @- J| MCASP_PIN_ACLKX- T. w+ c. X# _0 m
| MCASP_PIN_AHCLKX
' ~; n% y: l. T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- \# _, P- W A! t7 E8 m( d4 t8 K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 H. z- W5 Q% }$ V
| MCASP_TX_CLKFAIL
# u8 u, f: f. Q- o( y/ X| MCASP_TX_SYNCERROR" Y( G" b3 c! V. S- r3 `* j+ Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! Q2 ]( o# o4 C/ {| MCASP_RX_CLKFAIL
2 q( t8 o' |) o# x| MCASP_RX_SYNCERROR
; C8 B) d# h g( _| MCASP_RX_OVERRUN);9 g5 q D& T4 O7 B. N% S) ?4 B
} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
8 l6 W4 P/ O5 Q& M9 }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 M% o2 p; i7 D1 D: _, ? o! m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 U3 ^: `4 M9 ^: y# Q3 H9 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 \) T7 d% w0 R% B% o% GEDMA3_TRIG_MODE_EVENT);# h: G! @8 X% C7 I6 b& D9 E9 @1 j5 N+ g6 x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 A2 X4 [+ k, {9 ?1 @& d4 W
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 D- u. r" D, [. {9 f( ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% ^- g" Z2 }! a, s# y; eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 q/ o0 a! C4 Y' k" Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 O# H8 `' `( I6 TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. ?% b( f! y" w! `9 y/ C/ b4 m1 uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 y) }2 o8 J. a
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