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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 {7 j( i C" j$ r+ N0 n' }) Binput mcasp_ahclkx,
! O' a# z3 B9 A7 u0 _2 linput mcasp_aclkx,
8 Z- f4 h) }; Z5 z! ~% q: Cinput axr0,
# n9 N- S3 W0 h' T9 |% K1 x0 Q
6 l6 l7 T. B/ Noutput mcasp_afsr,
& j( w- d6 [# ^- t: }output mcasp_ahclkr, h4 R; `! {5 d. t! D) u
output mcasp_aclkr,% w8 C; k7 A4 a1 b! Z2 H/ c
output axr1,0 T5 G2 D8 Y2 y9 f7 o( c( b' r
assign mcasp_afsr = mcasp_afsx;" k$ Y* c0 C/ |" g2 W1 v2 A
assign mcasp_aclkr = mcasp_aclkx;0 F7 ]* d( T" ~) ?2 W8 ]) V
assign mcasp_ahclkr = mcasp_ahclkx;
6 ?0 x- D& i1 T0 V% G+ d' fassign axr1 = axr0;
# u* X+ }( a1 {5 T; X* k9 O% {( M9 w) f) r; z/ ]* R
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ u8 a2 P; y9 Q
static void McASPI2SConfigure(void)
$ k7 V! f4 { l& _/ Y{* w5 R- h* R* C7 k `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 r S: |* k( C" o7 T5 u: A0 W4 A
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// [% q0 e" o3 A6 i( \( l g4 j
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* D' L3 |3 ?; `* o) O( EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 w( Z' \( h/ o# r* o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) k7 t% r. _" ^MCASP_RX_MODE_DMA);8 e8 c! ~) n$ G# c+ }; `
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 T) w, c0 S x; OMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. U7 R8 k; {% Z# f c3 X4 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : f, u* e$ W+ j! E5 t* n
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! J8 L# h$ i' m( hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 S' c" k+ |; u9 GMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& T: H& K1 |0 l7 s; g
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) I8 z) v8 k+ dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 E& y; I: C4 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ e% G- C- ^& ]$ p8 D4 n2 g. d
0x00, 0xFF); /* configure the clock for transmitter */
. v0 k4 P; r/ B% b' lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ K! E6 C1 H+ q9 g8 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 q& d# d: q. b! [% v. Z1 h1 A9 `% EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 G5 H5 w/ D5 F' y0 m# Z2 F7 R
0x00, 0xFF);
+ A( Z0 O% ~7 o& Z7 ~2 ?, G; z. F4 M+ y
/* Enable synchronization of RX and TX sections */
8 s" N8 l7 M9 R7 {1 N" \5 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) {5 f; U O& Z) h7 O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- L, K" a4 }$ wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# @4 P( M) g& u* e! a6 G) `- R** Set the serializers, Currently only one serializer is set as
/ _2 {1 d; t7 Q3 B! a* J** transmitter and one serializer as receiver.
: g* k6 ]7 l$ F; l8 j*/4 G0 i# s, _' J& s/ q* R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ Z: ^( C& ~7 |' U8 t! W+ F8 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* G+ @' w" z. S, ?4 b0 @! Q** Configure the McASP pins
3 f) T. n' v9 K/ h** Input - Frame Sync, Clock and Serializer Rx. z1 i2 V/ F/ i2 N4 C
** Output - Serializer Tx is connected to the input of the codec 3 ]/ y7 J& o; s$ }$ h
*/
+ y7 C M" |/ N! e; a- u9 I# p) uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! P N% ^# U7 H `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 V# W' T: M1 a; {6 F' k& P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" F/ R6 G$ q& M5 F: @: C7 l
| MCASP_PIN_ACLKX9 V' E) v# y0 J# w5 t! V* Z
| MCASP_PIN_AHCLKX
$ I+ M$ z k/ ?, h| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 G/ B0 I( U5 v0 s1 @* \ ]' N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 v- o. o, E# ^2 ?/ v1 m| MCASP_TX_CLKFAIL 1 Y, T( z/ N% r) N. u
| MCASP_TX_SYNCERROR x3 f- h1 r* h m2 ^% H6 o4 j
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, J+ D/ A) x& Z3 |: r- ~7 q| MCASP_RX_CLKFAIL
/ D0 R3 b3 P& C: m# l% V: U/ E| MCASP_RX_SYNCERROR ) ]: [) [+ a) @
| MCASP_RX_OVERRUN);1 c2 o2 i* C+ U
} static void I2SDataTxRxActivate(void)
6 p; E% j2 p3 i" I{
& K8 V; W B: N/* Start the clocks */, m8 j0 W6 n X7 [. y$ E5 o6 V, ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 q2 L5 }3 K# V/ q8 J# I( a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; L" Q; w% E) Q4 h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 b& ]2 k3 B2 M% N6 H/ G% [ u
EDMA3_TRIG_MODE_EVENT);$ F0 C2 k: U n3 J m1 p* p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 L! y8 \5 q$ s0 L) q- ^: x: k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' X% L! Q7 d; h9 e9 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 m# e6 ^% k$ U! S7 B/ wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( J' K- b- e5 Z0 z8 A: S; ^5 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
# b- Y+ ^0 Q0 T+ t; N* }, CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* ^% h# X) s; Z/ B& ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- o$ \7 F# F% A* o9 v4 ?
} 4 E/ Y. Y+ f- a2 @. C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 l# ? F+ h$ ^3 r
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