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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- R4 u) r' g. o3 Q0 m7 kinput mcasp_ahclkx,
/ ]' L/ `% z. B9 B( N: uinput mcasp_aclkx,
4 F9 f$ M% J$ p" G" kinput axr0,
9 T- } o, U9 I) }! ~! N3 C# V
; K# O' A5 X3 v* Y9 \output mcasp_afsr,
/ l/ ~0 {+ w. v$ F0 Ioutput mcasp_ahclkr, d5 T K# o6 v- Y4 V7 T0 i
output mcasp_aclkr,
. N: J0 E, l# {! h. coutput axr1,' k7 Q7 ^' f' ]( v/ S
assign mcasp_afsr = mcasp_afsx;
0 g6 G* l: v7 Q* N; `9 @: ~ |7 gassign mcasp_aclkr = mcasp_aclkx;
x" [6 y& @ I# _assign mcasp_ahclkr = mcasp_ahclkx;& B6 n& _2 I# }' Z
assign axr1 = axr0; , y8 T. I$ Z7 Z* K0 l$ R5 o& O, q
3 t( h& Z- G( p3 K+ L1 J+ L3 A+ [! M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' N9 M! x% ^: d& A0 ystatic void McASPI2SConfigure(void)
& l4 y! H/ E4 N+ k9 [{) _2 L- {5 X3 T) F; c0 u: l/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: Q$ D+ u3 L Y$ u- x( \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 h8 \# N0 E5 ? q8 v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 t( y" k) c9 |$ n' F" Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ ^* x) i6 v; B9 {% L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; {' @& i/ { A! p6 GMCASP_RX_MODE_DMA);$ Z' f: o. o. j! P+ J' R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, |; H! o0 U5 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 Z. d. g+ s& g* @& x9 W$ c zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & G' i, f4 o+ i$ i* n5 v" v, G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: ^/ W2 l3 A4 ~; _( U, N
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; Q* U' _5 `- u9 u+ T7 E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" F( s. c5 D9 n+ ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 r' Q/ e9 @4 D7 A' Z; NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 T( A& v! h2 b) f# k2 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, x' d7 y: [! J
0x00, 0xFF); /* configure the clock for transmitter */
+ t3 k' F0 k- y* f2 vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. G# P; G4 R6 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( G, ~- i$ Y$ N! A$ QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' m0 L8 y7 ^' P- m, a# N( A0x00, 0xFF);, a' `7 C# z* b( m4 F% Q; ?0 N
3 Y% Y2 Z- ?6 |
/* Enable synchronization of RX and TX sections */
( P6 |" ^. K6 B% b" F1 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: E" m/ `" o; Y1 y9 [- E$ F fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 [* @5 _* d5 l' t4 [4 S% Q# Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ [& u$ v$ i9 M0 X7 t- d' p5 B. s** Set the serializers, Currently only one serializer is set as
5 H4 f( K9 n# @** transmitter and one serializer as receiver.: P' I+ ~$ ], \( T
*/' Z B2 B+ ?- {& }$ ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 s1 h4 Q T* f0 [( w2 j+ sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& }( w# j" `+ q! {7 t/ e
** Configure the McASP pins 2 |. b) @( Q! Y. T
** Input - Frame Sync, Clock and Serializer Rx
$ f b ^$ A% A- O4 S& b/ G. z** Output - Serializer Tx is connected to the input of the codec ' V( R2 [: X+ z, t
*/
8 ]& i. D; w- t: n8 cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% O/ |( a" [9 ]5 }+ H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 B; p' A: s& x, r/ PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 k8 f, c5 e+ u4 C+ o. Q# Y| MCASP_PIN_ACLKX# [9 Z. |1 @* c5 O& ]
| MCASP_PIN_AHCLKX
+ D" c. b) V/ m7 b; o1 D. g" x6 r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 T: J0 p. k8 vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " ~8 M2 y v! z+ R; n
| MCASP_TX_CLKFAIL
% b9 `( z; P/ R: N| MCASP_TX_SYNCERROR/ J; j( G \& e& J# y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " r4 C1 T0 n9 c& j O, y# G; w0 u
| MCASP_RX_CLKFAIL
# X' g$ q2 Q. q- {2 ]; d| MCASP_RX_SYNCERROR ' _# f2 b2 u1 `' A. J3 X; T$ E+ B' D
| MCASP_RX_OVERRUN);
2 f4 G0 V- i2 p. U i; }} static void I2SDataTxRxActivate(void)
& d' @; ^( l! D* O s) f3 D& E# R{1 X+ _: q4 |; ^
/* Start the clocks *// f" K7 s Q) _0 ~ X$ w% t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 U: i$ d* N* D; N! `3 j3 C1 ^" {& k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& b, \3 q9 @2 F6 u! JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 W- K1 f1 F* M9 X1 Y+ B2 B- E
EDMA3_TRIG_MODE_EVENT);
5 [: }6 N( B& b8 z/ K2 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . h5 f$ Y6 `0 q' ^2 @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 Q! i) }+ q' v& ]% GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! {) i5 L/ E- ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% | |7 u; y8 I( t* F. Y Pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% N$ w7 c% |2 Y! Q! \% |7 bMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ h# b8 \. i3 hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! N# S: [6 a" S' E
}
1 g8 t$ M9 [, K! [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 l; L w+ O) Z3 ]% n6 ^
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