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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 o1 {. }7 I n' I" N# \- A* t) J
input mcasp_ahclkx,
/ b+ f5 Z$ x5 m6 c0 binput mcasp_aclkx,
6 W! E; j6 x3 {* l% [- V; Finput axr0,$ w4 i0 {1 W3 n8 L: _
* ?7 q: u- ~ u, ?output mcasp_afsr,
/ ] g) d. K; b) _output mcasp_ahclkr," Y3 d, a* U" K" P* s& r4 T
output mcasp_aclkr,$ {3 K% b G- F$ G1 D
output axr1,' y8 P& K, M' c0 _
assign mcasp_afsr = mcasp_afsx;
" A! y) j) c% F4 K4 Oassign mcasp_aclkr = mcasp_aclkx;
% [, p2 `+ A G2 u; Lassign mcasp_ahclkr = mcasp_ahclkx;
, }: }# A! f; Y- W% i5 Hassign axr1 = axr0; 9 @ q5 }8 @, Y3 ^: a9 {; u( u
6 { }1 e4 C& m/ N+ P. h. L& T
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 n. Y$ [- M$ V- J# }
static void McASPI2SConfigure(void)
, f* `" S0 ]. C T" e{
* q1 w0 q: N1 _3 C/ p7 F1 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, u. \" Z) R9 |, i P% t, i+ k8 h8 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ B: c" V4 o) s& J4 S& v$ ?# Q. v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% o8 F, P0 Z; n, M; AMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ [# P+ v* Y' h! y( u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 @) \8 h& N0 LMCASP_RX_MODE_DMA);% L8 D5 p" W( @2 D6 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 U& J9 p6 F! W, q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; N6 R/ S. R6 O E' P8 T' e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; h4 B% P4 x& w8 hMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);1 X) L& V: d! w5 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 M4 Q8 ~3 }" O( o/ S
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) H( C) G( l% G! d8 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. ~; A1 G o' y# hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 X8 @' O7 w+ u; `$ a4 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 C0 |/ ~% c/ E, o% {' `* y
0x00, 0xFF); /* configure the clock for transmitter */+ X1 f7 t8 Q9 I( M" F b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 I8 ]' j" Y! S* Z. sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. U8 G" T) s+ C! m+ w/ D3 `6 N) \# ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" `$ ~" d8 o7 v3 p* ?0x00, 0xFF);- H) h1 s K+ C) d
7 _0 _# @# J$ H$ |! \/* Enable synchronization of RX and TX sections */
) o' D1 e: j/ ~7 ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */* d! b& M3 R+ ^* R* B
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 i; R; r; N; s; L OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 B1 Q7 M8 O5 n
** Set the serializers, Currently only one serializer is set as+ |5 v: k) @6 b) Q3 L
** transmitter and one serializer as receiver.
% f% {/ a' l1 j1 w$ d+ @( W0 {5 {*/. V/ A$ |* }( r" [7 f, n
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% P% U. s5 \* ]2 v- C) c& D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! F, K; y9 v5 h k! h2 R5 `. q: ~** Configure the McASP pins 1 p \2 T9 X/ u$ Y
** Input - Frame Sync, Clock and Serializer Rx
) t+ e; q& O1 Z3 |** Output - Serializer Tx is connected to the input of the codec
# I; I! R+ A4 R# G- b9 J*/, t/ r& d2 v* B }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: H. z# N3 B `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& a- D5 [/ w& p7 z, V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, _/ V" t7 P; U* L( t
| MCASP_PIN_ACLKX
5 K" z( n: T$ K6 R& r| MCASP_PIN_AHCLKX
6 V# i0 X- k8 K* m8 I) b) K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, K' |4 t2 \3 O1 B: i: oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 m9 x- m0 ~. M$ N| MCASP_TX_CLKFAIL
' e$ b2 {4 l& N7 j+ U/ ]: L| MCASP_TX_SYNCERROR
2 |- X/ P, Y" t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! s: D, D0 [% S0 {7 ?
| MCASP_RX_CLKFAIL& |% L" w" J( Q+ y# B. J
| MCASP_RX_SYNCERROR
5 K1 I( ~9 T( t7 H2 H# l| MCASP_RX_OVERRUN);
% V! }" U; F* m; s. I8 G+ g} static void I2SDataTxRxActivate(void)
( B' v# N0 A2 I4 J; |0 d& g{! v! Z! n3 R4 J3 i/ w; i
/* Start the clocks */' U2 G* Y$ n2 e3 s* \+ W' k2 P' c; m- o. O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 p, g* N0 q9 `" K2 F4 e* a( W
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 {8 g0 g S8 Y$ E
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 k8 U5 p0 G0 @EDMA3_TRIG_MODE_EVENT);3 r# e4 N" G3 o' p$ |8 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 z5 h$ ?7 k2 l4 b; V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 n/ M$ B+ i: Y3 d2 J4 B' f0 GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. v1 {5 I% p/ ~0 q: H. A! }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. v$ Y; f9 P# j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- r! }, C c" c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 F! p w. U8 U+ }/ ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);) H2 q5 g$ k( h4 P
} 7 D. r7 E8 H2 L3 ~' N4 J$ D$ A/ c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : N/ K% }2 e2 J: A6 a
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