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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 x d2 s! z2 X/ r6 ]input mcasp_ahclkx,
& S8 r" C: m g7 Y& ]8 ~+ B7 Ninput mcasp_aclkx,( H9 p; T5 \- c- G0 ]" t
input axr0,; W: w* w+ x* s5 ^' f; v _
, q7 k o/ f$ `5 U' H; y6 V$ Eoutput mcasp_afsr,# g$ Z3 M7 F: g& [: p! n# l7 N
output mcasp_ahclkr,
" r: `' b0 S6 B6 @+ Moutput mcasp_aclkr,
3 g5 A& C; G, A% z1 I/ m1 houtput axr1,
3 L; ^9 L, Q! w9 X. [ assign mcasp_afsr = mcasp_afsx;
: h9 D: D+ Q% a# Massign mcasp_aclkr = mcasp_aclkx;) p" ]. f; L$ L7 u7 p% U+ C
assign mcasp_ahclkr = mcasp_ahclkx;0 b* @0 L! u9 p0 D8 }
assign axr1 = axr0;
; g$ ^: B. E/ c1 u* `) x3 U9 a4 D9 G5 Z" }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* q: V# _2 K, j3 Rstatic void McASPI2SConfigure(void)
% f( ~$ V6 o e- X) y C{
$ v# h; t8 E. R" q( V2 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
% x) H' @* H) A. ~5 s" f* P5 q# O7 `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ l1 K5 R4 W; UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 O' _" f5 L+ O1 K% r' d* }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: g* S3 [, F4 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ~0 l+ z, M) R/ B4 Q
MCASP_RX_MODE_DMA);: G0 C/ t% i( _$ ]: m# w& k6 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 Z z- |( Y% J7 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 x) K1 E1 p6 l/ D# D" U- \7 W! ]- HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* Q* A3 @- F1 S& F# a" S$ GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 L0 m* T* n( |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' O$ H1 X' V G0 h+ q, [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ U9 ]0 E ?$ O* P ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 V+ Y+ {* _1 B% g( Y4 }; iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 ]& M4 T: }3 x- g3 v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ R2 U, B. N3 T( i
0x00, 0xFF); /* configure the clock for transmitter */' N# [' k& j- \0 W; {2 ]" B5 o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( A; v/ l" \5 L. Y9 F9 C3 Z+ U3 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ ]+ [, @- l% zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& `. K: c( e& g' f
0x00, 0xFF);$ e4 o4 s! C0 A$ W& ~ H
. Y4 E/ W9 T( K7 I! E! D/* Enable synchronization of RX and TX sections */ 2 K f# Z. r$ g. Q7 c1 h6 d
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 j, N1 p3 B1 F8 u( `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 u2 o/ Q0 ?2 k# I; \, i6 ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- |$ v9 ~. ~& c# z/ M, r** Set the serializers, Currently only one serializer is set as, v D2 s% D% @8 B6 K- z- Z0 L' }) K
** transmitter and one serializer as receiver.
& V0 O- X4 E% G*/$ F+ a8 I" [" t# G% j2 O0 Y. j" S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 X/ h/ O2 ~) k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- ^+ M! g* G: M) _) U** Configure the McASP pins
3 _# v0 l' z7 G/ O7 r, m9 j+ P** Input - Frame Sync, Clock and Serializer Rx. E, h, N4 v" p6 S4 R* a
** Output - Serializer Tx is connected to the input of the codec
0 Z2 }7 [5 X4 M- r+ ^*/- q+ B$ \* Z! m9 M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 u; T. o1 _: @3 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 l$ t" [- G% ?- b! l! P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" [1 o8 W" o M' d| MCASP_PIN_ACLKX
6 E. `/ U, k, B, P# A2 r| MCASP_PIN_AHCLKX
" {5 Q; [: Q* G7 y# [; u' r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 @5 s0 h0 H. O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % Y) ]9 h7 t; V/ v) s- z
| MCASP_TX_CLKFAIL
- x# y! | I0 C6 L6 X| MCASP_TX_SYNCERROR
/ q$ I* U( X4 v G0 e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 K m# f6 N7 Z( U+ e. r
| MCASP_RX_CLKFAIL
: Q: R j; |. A9 B| MCASP_RX_SYNCERROR 5 M1 ]" i$ |; Z
| MCASP_RX_OVERRUN);& C( V$ M0 l8 f; E7 r
} static void I2SDataTxRxActivate(void)
& C" {7 ^# B* e, P{
' Q. d) [% v. q* u+ T% U/* Start the clocks */
( }; \% V( d6 C6 i8 GMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 e3 d. {5 d. ^0 M* H' k$ v0 uMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: ~; o$ h! S' H: V1 ~5 L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 W6 m |9 f) M# ~' m) N
EDMA3_TRIG_MODE_EVENT);
# d a1 ?! D, `( lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ r6 b: V6 [9 s& {9 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 B, j: w! C$ j3 P. D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) S0 Z* S+ r. R2 X4 I5 r% r6 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 E/ C V1 I$ U0 {& ^& i. I- F% F. j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 ?) m/ J& F2 G4 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 k j- x k" @+ UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! s4 I* Z H0 v8 [2 q$ |. c( J}
. V: A5 Y( d; D# y# [$ `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 y" D. G }5 @* I% t. ]
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