MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
) [7 W/ v% h& s( P% H9 P8 I7 Yinput mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
$ k8 t  n& a, D7 N: Uoutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

# M! x3 }2 K# ]) p4 O0 g
: R2 A3 S; b" t2 a

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
% \. @" Y  [) G8 m{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
2 p; f' }. E1 V8 w3 NMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ t$ N6 b) O% _9 {/ aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
+ _4 |0 S5 x# w8 z0 |3 u: S* gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ |" r2 J, Y2 E' M+ eMCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 X5 ]- x/ ~! _+ aMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) e  ^" o, j  R1 U9 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, B8 M6 |. E7 f, }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; _7 N+ p) e$ o( C6 E; \0 T; M2 tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 y3 E/ @) n) D& f, f$ o6 Z, lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
2 s. `/ Z# O% c! _1 T, r
- Z6 o2 N7 T' l; Y4 ]/* Enable synchronization of RX and TX sections */
$ u: B1 _" S! G0 p& z6 B5 x4 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& u3 \" Z+ o% A/ m6 xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
* c$ a% k2 N/ u8 j& b6 K0 Q** Set the serializers, Currently only one serializer is set as
3 Z$ K* I9 l" i2 V# V** transmitter and one serializer as receiver.
) \9 }1 k9 N% F" R& V( S( C*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 |1 {5 O. s' X# _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
1 v: x0 q0 C( ?% j% K  E: _** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
* w; J. {+ b! u3 V" H$ M& D8 i% w** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. ?, u' |  U! o% K5 _$ @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
: d; M! |) L+ Z- Z7 J* q; |4 {| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
" F+ q  I) Q. l9 H& Q, xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
$ I# K) z5 b; H: j0 d) O6 U8 G| MCASP_TX_SYNCERROR
* r- Q! t) v. n5 a( z  W  I% s: X1 _| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
, e+ B# V. @6 T+ Y0 ]# p. ]0 h& B}

static void I2SDataTxRxActivate(void)
1 ^$ j# ?2 Y7 M) C. M4 p; [{
/* Start the clocks */
9 A5 Z# @  X/ a+ u% T% }. gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
# I. b6 @5 Z; a0 q6 x' V4 SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) C; j; |3 V5 W6 w* \; l/ mEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. ^( m" K/ w  @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
: a, Y& V" l9 K4 S/ ~McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: B: P$ Y2 e; eMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
% Z8 ~  ^/ ]$ j! twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
$ X0 Y& g% \8 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

8 w6 n+ U7 H: n' c; v: \! L

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

0 V, a. d, O) \+ v