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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( }! d( d3 V% ?8 l- C; D6 C" S* g3 G winput mcasp_ahclkx,# w2 ]. w) X+ p3 [/ K
input mcasp_aclkx,
1 P) e; e' [8 X% minput axr0,% H" v: v! |; l* e# S
2 l9 L$ X" [2 h6 }0 \2 a
output mcasp_afsr,( {6 W! a' }7 [8 b6 z
output mcasp_ahclkr,
2 B6 \+ k" s0 ^- M8 Foutput mcasp_aclkr,
, G) T% S+ d$ z- H/ e6 ^6 ]output axr1,
- Z7 y9 C; |- Z q- T assign mcasp_afsr = mcasp_afsx;
& U% c) O/ H3 q9 T8 P6 Lassign mcasp_aclkr = mcasp_aclkx;+ ^ d8 ~& I' `3 Z
assign mcasp_ahclkr = mcasp_ahclkx;
- f/ W8 o. t+ r( l \% _assign axr1 = axr0; & l) x! r. g# J" C. ^5 q3 @1 @
: [& v! s- T/ x7 b, O& q5 U! @* a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" P5 p7 V8 O% _' fstatic void McASPI2SConfigure(void)* P, v4 x* A# I
{9 s# a: P1 S8 o' k3 P' c) S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% T1 B# x# o9 O4 f# [/ mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ a0 Z- S6 u! \; r9 V! BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ r1 P; v" [- \1 c5 W) @7 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 K* H M8 v, t6 O( B. G' ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 I3 v7 V1 Y+ S+ R0 a" [MCASP_RX_MODE_DMA);
% f( {! ^1 F/ xMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( [& i5 j* i3 M ^, qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 Z/ A, D' a1 n% C& [; y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; Z" U& @5 P6 B8 L5 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; X1 T8 o$ ^6 d- c; Z( k. ~: @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) H% Y3 ?) E# v& [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. L l8 o: G! [9 k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 g# y* L/ e+ ~1 BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " v! B7 O5 }9 n0 w4 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) s4 s4 W; X4 o2 r5 A
0x00, 0xFF); /* configure the clock for transmitter */. H* c/ W' [: X3 S# o$ A( p/ N7 A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ f4 L4 x2 `; bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
Y9 q( K- ?) L$ k1 l9 lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" U8 h, w" v% p3 k9 b0x00, 0xFF); s1 R/ m$ E+ C! @6 U5 j' b
. u. t) v! W0 z% W6 @: `1 g1 [& @/* Enable synchronization of RX and TX sections */
' k8 m4 r1 s/ _" w( GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# Y4 `: J5 Z) _% LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( R, ?& ?. G1 c/ s3 W2 q; G' E4 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) _ n0 g- Q- U8 n% W5 G** Set the serializers, Currently only one serializer is set as+ K+ v* e8 I+ Z9 ]
** transmitter and one serializer as receiver.
" E* l- V7 [; M*/
( T c! ]' l- Y N. H/ w/ j: M7 QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) t" y) c$ E* f8 m; ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 B7 D7 j8 Q3 ~! l/ K** Configure the McASP pins
0 _; _6 q7 i% R( u* P. y** Input - Frame Sync, Clock and Serializer Rx5 m- @: d6 }2 h
** Output - Serializer Tx is connected to the input of the codec
, U) }4 Q: g5 e e*/
" c4 q/ `$ }' x% Z9 OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 e& y/ N6 e6 B: i' s1 XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- I" \: t$ ?. x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* `5 Z# y1 p5 G
| MCASP_PIN_ACLKX
: D2 ~7 b) @! w8 _| MCASP_PIN_AHCLKX
* u3 Q; B9 F2 u) c( p4 V+ r- \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; L j& T g1 O' {5 W* k. l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * ?, P9 J7 p) f' Z
| MCASP_TX_CLKFAIL
0 m/ z3 N+ ] N o| MCASP_TX_SYNCERROR
' p( F6 k$ o' y) a7 `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 e4 U6 c* v! n+ P- c' ?6 L+ L
| MCASP_RX_CLKFAIL
( M- l5 H K' Q2 s5 X5 x| MCASP_RX_SYNCERROR . m; @+ _, [2 @+ B( g1 _. }
| MCASP_RX_OVERRUN);
8 @; A' X# c0 Q- H* K6 {7 J* }" B} static void I2SDataTxRxActivate(void), ]1 ?: r; ~$ B8 ?
{% i( O5 ]( Z, l/ Q) y6 M
/* Start the clocks */: T( T2 J: }: o3 J! T+ O! Q! r3 [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& I3 N* @# V) ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 j6 v5 g# m2 n# _$ |( ? MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" [% A2 Y! r* y5 r4 REDMA3_TRIG_MODE_EVENT);
5 m* a4 E- I9 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- s' |9 C$ J2 k: D+ y$ oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: u1 M( Z6 h5 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 ]: N, y6 J6 o& c) A
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ J& I9 @/ q& s9 N: q8 M+ ^3 k) Q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. J0 M/ j/ U+ H: R! H3 b, R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 g D9 a/ \8 {3 e/ h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ ~: j/ J6 c! N3 H/ Q
}
, f0 |# e& D8 u- u+ D8 q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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