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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ [- [; i \4 ]* S4 u7 c& W' ninput mcasp_ahclkx,
. R, R! L `. o" p. b; K' Oinput mcasp_aclkx,
' l/ C7 e$ S+ {; Q C9 i2 l" uinput axr0,
% u& C% p3 M" Z
6 }# J4 x( U; F! {- X- S joutput mcasp_afsr,
6 j- b8 H' X6 @2 R# {; i% `output mcasp_ahclkr,
: H( Z0 z$ ]; N$ n; @! Y$ s# ooutput mcasp_aclkr,) n' E% d$ i& H, W& j, w
output axr1,. u, c7 d+ G" {7 [" t( F+ H
assign mcasp_afsr = mcasp_afsx;* u, V8 p: l: @9 K5 o: @
assign mcasp_aclkr = mcasp_aclkx;1 n9 T0 `- @$ j8 {" n9 y$ q8 Y
assign mcasp_ahclkr = mcasp_ahclkx;
3 n0 Q" g; ?1 `) ?% cassign axr1 = axr0; 3 k8 R+ n. u# y5 M
# ]; z6 J1 Q' V3 R" L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# I% o+ n8 O/ h6 P @2 Sstatic void McASPI2SConfigure(void)( i2 z1 v5 f4 \8 ]
{
3 E0 u) K( R! K" s! n2 |0 X# gMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- X1 Y- x9 p, M3 _9 Q, j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 ^2 C" @9 |& r T3 Z5 Q( f5 t
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 ]! j# h t) h3 a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 v( [2 R1 g0 l2 _& }- v/ l0 z/ G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 b( S( I' c& M* MMCASP_RX_MODE_DMA);' t5 n7 I% z% Y" K# p7 ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 S8 b. P# e9 j# J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ f1 i4 D0 a4 k2 H n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 _+ d7 k) V- S$ rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! T% M5 u9 X& C8 I [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ^, N( I$ n% cMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 |$ b' q A# m* k2 A
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& y/ i7 z, t6 _2 ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ ?9 m1 U) i' s: P8 `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, {" \$ C2 h) Y
0x00, 0xFF); /* configure the clock for transmitter */
) p: _. j7 f8 G/ h3 B& ?! {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) d4 v( N8 L; L! \0 I6 W: D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% y9 a6 |( C5 u% y" a. zMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 f. z" ]! R, N9 m
0x00, 0xFF);" B$ S6 H& u! i
- S ~7 V9 S8 n; j o6 W; H
/* Enable synchronization of RX and TX sections */ # A; K4 l6 F9 j! W5 `5 h4 f! w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
@# a, d1 @, K6 p0 d# j' `) CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 c9 M, r" K' M; v0 w* R" QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* E; ]9 s9 @7 l( c3 X5 u3 I8 f/ t** Set the serializers, Currently only one serializer is set as
6 G' Q3 U+ y2 P `: ^0 _; j0 U** transmitter and one serializer as receiver.3 M. _7 _% H$ _ l+ \
*/) e, V/ I- @ c
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; z9 \4 I4 I7 a0 W' Q% L& ]) rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 n$ P3 A; w, s5 k** Configure the McASP pins
& p8 v) ^) w* V( ^4 p% s ?2 p** Input - Frame Sync, Clock and Serializer Rx; H" D, J' M: d& h
** Output - Serializer Tx is connected to the input of the codec
% C4 H4 [; J/ s- _( ^% O*/
- i/ i6 O. H2 I1 b# T1 DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' f* }5 [/ F8 U5 J5 j X& zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 O# }& s' y8 ]$ L6 o& k) T" V
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX& ~+ ?3 z/ k1 B* h' ~$ T" ^; d" P
| MCASP_PIN_ACLKX
# K( ?. n" k, E. _+ B| MCASP_PIN_AHCLKX8 M7 r7 J9 h$ U' t C, v' {
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 g$ Z( r% f" j+ Y1 ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 l! c$ T& d% G* w. O6 o
| MCASP_TX_CLKFAIL $ Z+ s, R( r" n" y; \( X, A
| MCASP_TX_SYNCERROR$ z) C, D9 f: x) E, s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 d8 W# I+ t8 e" z| MCASP_RX_CLKFAIL3 H& \& `! K4 q6 c4 h" r$ h
| MCASP_RX_SYNCERROR ) B& Z$ L6 g e
| MCASP_RX_OVERRUN);
! M+ H3 E) _+ X) g} static void I2SDataTxRxActivate(void), V2 x3 R1 b. g8 H6 r3 S' y
{
* _ d0 z3 f' u8 G+ b/ ^/* Start the clocks */
6 Q0 s& I- ?2 c8 pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! e# h' K* k, k6 ?2 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' A* q) z' m/ Z! q% l* c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 d0 C" H' q u
EDMA3_TRIG_MODE_EVENT);1 i* s3 i N: B. O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : s$ k( @: C: g& g9 N0 b
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 L# }; W# h8 }' G/ v" g# dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 U" M7 H q2 \: f+ r) UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: A5 ]+ J4 R% q t& Q& ~6 Y9 Y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ @4 A# m( v( M# K! u8 ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. E( w' Q# A1 u$ w6 F, nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& |1 m W9 [ d( T5 o! E$ A
}
1 e, ?7 l: n8 N& B. [% q( m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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