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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 S; `0 `5 Y+ V& q+ X* M* {) |9 vinput mcasp_ahclkx,# y( G ] e% e+ j3 T( X8 D
input mcasp_aclkx," o5 N/ `% T( v; w
input axr0,3 l) F2 E% x9 D' o6 O0 K7 ]. Z
, |( p, c7 H" F4 B
output mcasp_afsr,2 A/ A" O. p8 Y2 f& h$ [" L
output mcasp_ahclkr,
) t& S. i! I9 O, J4 O. m/ R8 J- routput mcasp_aclkr,
4 }6 A, c9 D# Q m' U3 {0 Doutput axr1,
) H0 D; s$ \* K assign mcasp_afsr = mcasp_afsx;
7 J* ^5 Z3 g- J2 M: ]* A2 Gassign mcasp_aclkr = mcasp_aclkx;. y- G/ [) N* m) B2 G# d
assign mcasp_ahclkr = mcasp_ahclkx;
0 S$ ~! H6 f- r; E+ O/ r0 Sassign axr1 = axr0;
0 B, E [4 j+ G) ]3 J3 v( {; [! M
# U" l0 {5 p* ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 q. @# @7 I5 N! u. X7 Lstatic void McASPI2SConfigure(void)
6 d: Q* l& ^& h" T{
U7 i9 ~: S% E% h9 h) f; p1 {: ]McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 P9 c! J8 e5 C/ y1 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 s6 `" E' x; h% ]) \$ `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* S7 R: u* Z% ]2 N0 Y- XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
H! E4 h6 W1 E" \- O/ @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" ]6 F2 t# K" M& \2 cMCASP_RX_MODE_DMA);1 c. Z0 I. K/ H9 U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 ~1 Z/ M+ a7 O. n. {0 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 B, Y f! K$ p& e5 s" o0 K0 r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' r, W# G; \3 l. Y4 P, V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. C' e8 r! J! ]% S' _3 sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * F7 c. P4 P% k3 I8 u2 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 q: V. J5 r0 t: p/ [, V, a3 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 K! l7 _; r( F' ], v3 i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " k$ R2 T5 N& v& ?* s4 X+ L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; B8 \+ m* d7 w- x2 f2 B0x00, 0xFF); /* configure the clock for transmitter */; ^ F1 @' Y' t6 B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
5 B" t6 Q, G. K6 O& e" WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 y ?& p$ z3 i, @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 g+ _% v8 t/ V0x00, 0xFF);+ J# Z; g6 E5 o8 g( {; }, z
; ]9 v% L4 P# \+ D/ h2 N/* Enable synchronization of RX and TX sections */
9 |2 L: E" J3 N- aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 M/ f; Q' r7 l
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ r+ ?1 A9 o, Q; A6 g! L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- [* L1 U4 [ {0 s, I* n
** Set the serializers, Currently only one serializer is set as$ d( h- o3 m0 k( m- e' B1 J6 ~1 \
** transmitter and one serializer as receiver.- F! u( o4 g: K3 U8 O
*/- Y# _- z$ I; I# e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 ^6 h2 Z3 D" FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 m {9 Q" n: v! ^( G: b% w** Configure the McASP pins
4 Q' Z: r9 ^6 o- e8 b0 D% z7 D** Input - Frame Sync, Clock and Serializer Rx
( x* u" H) h0 u0 D0 p6 a5 u** Output - Serializer Tx is connected to the input of the codec
5 k/ ?8 o1 N) H9 V/ F1 Y*/# o) o5 z' B7 q$ `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 r( V6 z3 U; a% Q+ qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" f) }5 Z6 h8 G! YMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& t6 ?; O m6 E( G- g: b| MCASP_PIN_ACLKX
3 r/ ?, t; q( o8 I( r| MCASP_PIN_AHCLKX
8 V7 c y* J, K! ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& w) r8 u/ v, f, H# H2 o- CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ M: D1 z: b7 e7 m4 H9 U| MCASP_TX_CLKFAIL
0 V8 p; w' r% o# D: j5 J8 U+ C| MCASP_TX_SYNCERROR& n0 N1 _, P/ C1 `+ P! z: ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- {" C. Y6 v' v. ?| MCASP_RX_CLKFAIL1 T# q/ L* M, ^2 _; b. {
| MCASP_RX_SYNCERROR " Q( A+ G" n! [% Q7 X5 @5 }
| MCASP_RX_OVERRUN);
! C! ?. `" N) H} static void I2SDataTxRxActivate(void)9 M h. K5 c4 @5 n; s3 R5 u* F
{" Q0 N" |+ Y% B P9 z) ]" y* v
/* Start the clocks */) U, I7 }) F3 E) ?* k
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 J' F0 Z* d) V; X* w( c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 t% i# J7 {% A$ CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- k! U! \& B2 }8 sEDMA3_TRIG_MODE_EVENT);
2 g+ S1 Q( D$ u/ P; D& r" aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - P0 G8 d( b4 c/ a" k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& }+ a7 p4 q+ ~+ z& |: zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; T; o$ g5 M# E5 f+ s$ T- _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 \& r7 {7 ^0 x* J9 M3 r, _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. W4 c6 R- e: \5 G: f# k, q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 ]/ F/ g' F# {- F8 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, G* |/ H4 u" q4 t. ^
} ! c+ S% |/ e9 g" I: C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - ?6 d" N# E# k f0 `
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