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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,, \; R% |" d( l+ ?/ ?) f5 ~8 y
input mcasp_ahclkx,
1 n6 O! e8 g- Jinput mcasp_aclkx,$ J3 l& e' T1 ^ {* O6 C6 d5 H, [
input axr0,
+ s& B" Z0 ^1 A: k5 [5 b+ s4 V$ v5 f5 j* Q6 I; n
output mcasp_afsr,! H+ v* q" R' q
output mcasp_ahclkr,: r' T+ V. o& G
output mcasp_aclkr,! f+ ~- L( m- u3 }# s9 V
output axr1,8 \2 e& v" i; M* _* _
assign mcasp_afsr = mcasp_afsx;
, A5 w6 y. R- Qassign mcasp_aclkr = mcasp_aclkx;7 {! C3 i/ R+ h7 B
assign mcasp_ahclkr = mcasp_ahclkx;
( G9 ]' C# q+ I& oassign axr1 = axr0;
. R# p+ q9 R9 p( M! H$ |, w
* K( m# K/ U; u# s# Q+ u& H. g( b k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) [& m) i, M; t/ Q2 ]$ K v
static void McASPI2SConfigure(void)
$ ?1 D1 X0 S: n" r' \7 I0 b{1 b1 U! Y- ?! K- |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 O0 r8 x5 B3 o2 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- T; Y# f: m: I, D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 K) F$ @/ l- i3 |- z4 \/ o. `) G
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 n+ [1 V, N8 C3 s: iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# ^0 [. M9 t, p: ~
MCASP_RX_MODE_DMA);% \9 n, E. P: k. ]% X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 N' C; q5 v! i1 P: i5 O! E aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* S4 n0 W0 m5 m" DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! f7 e1 A6 t+ _1 |/ D) z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ ?$ E' i8 J- V! a2 X7 G' K: ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * i s! H/ Q& t; D7 K) }9 X8 Q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 N9 V' E& p# k* f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' g/ T9 a: n. \) N7 k' E2 v) P/ BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 U+ U/ U0 b& R0 Z/ {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 m; b9 p' ], q1 z. O. i0x00, 0xFF); /* configure the clock for transmitter */
. |/ }& W& l7 r9 ~" o" uMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, g" g. U% e! i" |) s$ KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); w0 R" I6 z t7 w" U3 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' d3 v. Q, i: @; n+ [1 `0x00, 0xFF);& U% Z) z/ T5 m' }% k7 s) ~
' W3 {' _# [' H7 r/* Enable synchronization of RX and TX sections */
1 j! t6 F2 g% h) |" F$ D1 uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 p1 K# z' Y" t9 IMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& Q; \% i9 c, p. {& v3 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% k2 X1 S0 k3 \8 w3 e. Y" ]** Set the serializers, Currently only one serializer is set as# j8 ?( v/ r# B( F! b4 L( Z
** transmitter and one serializer as receiver.
H4 Y# W1 s/ H- n3 b" E- ]/ x; C*/* ]* J& P7 L- F5 ~1 @, p" h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" s: B; s: i' w) f! P6 Y' I0 _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% M$ ]- l, L5 U! _( `
** Configure the McASP pins ' V" A- V p3 {& i- e$ }
** Input - Frame Sync, Clock and Serializer Rx
4 b# O5 _: o1 i0 M** Output - Serializer Tx is connected to the input of the codec # @/ D. V& b$ G# C6 }* m
*/
% ^! ^: F8 f8 \! b# IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% _- W! ]$ N: M; R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ U; i/ d7 J X0 ^/ E' }" F6 Z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( X) ~$ v! h; h: {8 k1 E| MCASP_PIN_ACLKX
1 e& f6 k8 B2 W |5 y% w| MCASP_PIN_AHCLKX
- B( d* C: Q1 Q; {. t) F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& S/ ~ q; v2 \9 K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 N1 r! r# O# d3 m5 X6 t* I# a T| MCASP_TX_CLKFAIL 0 I2 t* ~% u* [# T/ [2 C
| MCASP_TX_SYNCERROR
- a2 I6 m2 V# s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! F5 a5 n: d$ z! |8 M
| MCASP_RX_CLKFAIL5 K4 j- T; A" H0 P t: X
| MCASP_RX_SYNCERROR
! N6 ~) M4 y2 ~% \% X8 T1 D' a" w| MCASP_RX_OVERRUN);
& m% I& T- c# v5 u9 h# Z* I} static void I2SDataTxRxActivate(void)6 `/ T* B# P* W! g, b, u# h6 O
{
9 L9 ^+ }; U' n- D/* Start the clocks */
( D0 u0 \0 E8 t+ EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 L% c$ o4 e( D& S4 l SMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// V4 z- c7 Z9 V' C1 l* h8 E5 Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
o+ c4 L# M) {4 j$ wEDMA3_TRIG_MODE_EVENT);/ R ~9 W( x+ z6 x( V7 t; F" k4 j+ `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * L2 F1 S3 P* c- K9 \/ k4 d$ {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 R$ h6 m1 o# ~. uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. b0 {% U Q' A8 _# {; H2 I! I
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. c2 m" s/ T( x& ~/ i: f" ?
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. Q! ] V9 |' I2 _* M! TMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 x5 o! `( T3 q1 W. aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! _' Q" w. y; r8 C' e. X
}
. \/ a- r" b8 e: K6 C) w. ^请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " D% h! v- ?" e! e4 P
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