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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, Z+ P, ^. @+ _) w. w& j0 z& k2 S' }
input mcasp_ahclkx,$ ?" a" L: I; V( B
input mcasp_aclkx,1 \# Q* c( ^5 x0 X3 R: [+ z
input axr0,( g. I8 N4 ~; q& D& |
: |+ ^" {* \' Q7 m( j' D
output mcasp_afsr,
: l9 z: i$ c2 t2 u7 U) Voutput mcasp_ahclkr,
# N/ u3 b! ?6 }; e: I! Zoutput mcasp_aclkr,+ B! w9 W& v8 p+ H" B
output axr1,/ V* y' Y/ k( e2 c+ J
assign mcasp_afsr = mcasp_afsx;
6 c3 S9 k( k7 j( q0 O1 r3 N. Iassign mcasp_aclkr = mcasp_aclkx;2 V! |5 m$ i$ M+ A/ u
assign mcasp_ahclkr = mcasp_ahclkx;
6 J! w7 ]) r2 Y3 wassign axr1 = axr0; / y4 _2 ^1 Q7 ^
l6 |, `/ r9 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 @ S4 z4 W4 _
static void McASPI2SConfigure(void): @# x; u3 F# z- h! i9 k' {
{' F7 O: o4 W R+ Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; ]9 N% {- J5 u7 P/ R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ E" v( ^1 _5 z/ x: r" R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! D! Z# F/ Q. h' G' y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 a3 d0 u. d1 O0 P( C, s! G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 I& j; r! a6 Y6 i/ f5 mMCASP_RX_MODE_DMA);
! C0 P5 O* I4 C$ sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' V8 `8 u$ C2 l) u% }
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" s; E0 }4 t }! N2 t! F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % r) w a& c7 @6 a& `/ `& _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& m( Q7 O# w9 A" p0 D6 K6 @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " i7 s- V( x7 s
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' L3 T) y* L8 w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 z& s1 z: D* L7 H3 UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) j k% `: D5 S/ I; n0 S; HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. n. N5 M: {6 Y& {9 t* q: m
0x00, 0xFF); /* configure the clock for transmitter */3 M: i+ P: Y" g. X$ [& ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, {8 O" @6 {# u1 [5 @8 z: CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 U+ b6 @: u- j& }7 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 L& I6 w3 k' Q* t6 c" m) A5 Q" R
0x00, 0xFF);
8 D# D, n3 k) D9 p# n! w) e4 M) Z5 C+ |9 h4 w$ \9 P+ v6 Y
/* Enable synchronization of RX and TX sections */
0 p, p! `$ g3 L8 j& Q0 i4 [4 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: ~+ t/ h7 d( \0 C$ M, }- o
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* w V3 E) y, _: HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& L9 W2 A8 b! L7 {& _7 b' F
** Set the serializers, Currently only one serializer is set as
! `% P- C$ B) f t** transmitter and one serializer as receiver.
5 x5 ~9 Y5 [$ W. {5 I*/
7 b; q# z1 M6 G- _: k3 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. ]# M6 ], |" O9 [6 [- ?, P% M. X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, q( v) |/ p6 ~6 k
** Configure the McASP pins
; f9 g+ O. C& u C6 `4 i** Input - Frame Sync, Clock and Serializer Rx8 z$ y: c0 T3 ?' f1 r$ C I
** Output - Serializer Tx is connected to the input of the codec 7 m* ^% r" m. W; F4 a
*/, f# r% [0 R& d+ w5 u) ?* }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, S' n% e; q0 i+ K6 G" xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ X$ R- R/ V, L5 w1 ]: a/ HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% ]3 d0 f3 O: H| MCASP_PIN_ACLKX' m1 r* G7 I5 `$ g$ j
| MCASP_PIN_AHCLKX) c( v7 ^1 o( i; w* _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 W" [1 C1 d v X
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: n: o. Q) h+ a8 R) B| MCASP_TX_CLKFAIL ' L7 e7 N% E0 G1 x9 |4 S$ o
| MCASP_TX_SYNCERROR
! `- }- s9 G. ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 U" h% \- x( j' c| MCASP_RX_CLKFAIL, s7 y/ [. M. H4 Y
| MCASP_RX_SYNCERROR # U9 L1 a) A' U% W/ `
| MCASP_RX_OVERRUN);& N5 I; y: \$ l$ X" g
} static void I2SDataTxRxActivate(void)4 A" `! ]! [+ g
{
/ n w, ^2 ~+ y g1 G; g/* Start the clocks */
3 u+ z: o$ Z8 P- d# XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 r4 E/ B: p/ ?2 r) M8 x1 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
C% p, Q0 d1 H6 H: SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& S4 M) h" r, g H% ~% }EDMA3_TRIG_MODE_EVENT);, V" @& ]" S8 P' M+ k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, d4 s0 j# T) n3 ~" w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" i$ U7 Q3 R- }6 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; t6 U _1 W, M; i8 W* BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, i$ F+ B6 a( Q( b( w- Q% m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 z4 }5 \4 G: B+ b
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ k" K$ t9 k' a1 n. h- j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 V3 C% W4 g8 L8 W: T
}
/ X& c5 W" y* O) S: t, T1 |- b请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 V9 {& z& j; j- l( y2 a) [
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