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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 B* p* d1 a) ?8 m Xinput mcasp_ahclkx,1 c( P- a3 h5 W* {' e
input mcasp_aclkx,5 o# M# J! h/ b t* O4 F% @
input axr0,
! [* v# x+ D& n5 N. m- N& ^% @
2 o3 c' b: ]( s1 M8 Z& loutput mcasp_afsr,
5 K4 L6 {1 U% D& r8 t) [1 noutput mcasp_ahclkr,/ ^' `$ l6 @7 C ?4 T
output mcasp_aclkr,1 |7 Q1 V# h& k7 R) Q( U/ M
output axr1,
" k( o( D- G1 Q5 O8 l assign mcasp_afsr = mcasp_afsx;
9 C0 G! i; k, [8 Y( sassign mcasp_aclkr = mcasp_aclkx;
; V) {2 e8 X+ K' F2 v- k5 sassign mcasp_ahclkr = mcasp_ahclkx;2 A0 v: \% Z% ]/ S' {+ y( }
assign axr1 = axr0; ; z5 {' |0 W6 M% ?* O) F; ]
1 P+ [! v8 V' F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 F4 C7 @7 m1 R; n Zstatic void McASPI2SConfigure(void)
2 Z$ R, r( x: e/ o& y2 C8 p{
* \6 |- S- \$ |" j* `3 t: ?1 [# B. s! PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- O0 O$ \7 N7 l1 c V* U- ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- m0 @0 N) \5 P+ O2 UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 m7 I; C! u1 _7 j0 g! q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 E. S4 w+ b2 Y- _( V- w! N, W9 K9 EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 U8 ~8 ~8 X' s6 w9 s, sMCASP_RX_MODE_DMA);0 D4 |) H& F: @5 I# D' B" z, t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# m! X d4 F5 ~0 QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 t+ W# o) n* Z) G$ \2 b. S6 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 V& t- d Y, b3 ?& F: x$ D5 i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! m5 _( k; c E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , M. H6 _, s; g) B6 i8 Q8 b& f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. s, m# i" g: t* {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 C- V9 Z) L* l: u& P1 w& t$ n" AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + w% s) ? C! F( w& ?6 C9 r
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; U; o; M. c' V! K; y# u$ ~% \' T# @
0x00, 0xFF); /* configure the clock for transmitter */. a5 u( a8 B2 d! g+ `+ Y- q0 X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 P# M1 a1 m3 p$ B k1 m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + B0 a% X! H* Y& S
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 c, i5 q5 p$ c2 a: y
0x00, 0xFF);9 I3 F" I, ~. v5 M
6 r, [. F' ~$ w
/* Enable synchronization of RX and TX sections */ 0 t0 r7 m3 w! p: H1 B" p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; h5 P( ~: R( B/ q% N$ m2 |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% u) J- _+ l: G: ~0 f( l/ C
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" Z& n4 V. e9 O; ?
** Set the serializers, Currently only one serializer is set as
7 `+ W7 g5 ~" O** transmitter and one serializer as receiver.; T% S4 A5 B2 q. g' ^ x6 Q
*/9 Y! ^& A& l/ g* Y7 N8 N# x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 x0 @6 B" E/ H: R$ i5 z$ F: l, bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 F: o: Y0 {, V
** Configure the McASP pins ' ^: _9 |! [+ g' u" I" H% t
** Input - Frame Sync, Clock and Serializer Rx }& }% q3 G/ Z2 `4 D
** Output - Serializer Tx is connected to the input of the codec
- u8 t; |' c" y1 G0 {0 ^*/
4 v/ {, ]2 P0 ]& l1 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% Q6 B/ S8 p( f, B: y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 F8 f: L ^1 a/ m& ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- q! L( R/ A. s
| MCASP_PIN_ACLKX
- \- [; R$ N% ^2 E( j- s: u| MCASP_PIN_AHCLKX# v5 M: L5 T- b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. N$ c# j* n2 [% h& u2 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
@! m& {& p& W| MCASP_TX_CLKFAIL r# v9 M, L' j$ ~7 c
| MCASP_TX_SYNCERROR$ i1 w |* f+ r# P- z% M( d- ~' C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & L6 n/ i( V- g3 _ h* ?/ R
| MCASP_RX_CLKFAIL7 S2 d& ?- V& D, Y. a d, y- e1 g$ @
| MCASP_RX_SYNCERROR
5 O/ P$ b1 N, K. L| MCASP_RX_OVERRUN); t6 ?* M4 K" D5 i6 X4 P
} static void I2SDataTxRxActivate(void)
% ]3 v" ?$ D6 e2 h( n{
9 n5 P$ t" D* {; d" J/ V" `, o/* Start the clocks */
. Z6 F! }( s* B7 ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 h* S4 T- N0 L( `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; `! x% l2 l9 V4 i6 N3 a2 E9 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, L9 m( c. N: `
EDMA3_TRIG_MODE_EVENT);4 D& @( [/ N- P3 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , X. N: l+ ~1 h/ m; o$ [4 ?$ L. x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% ^9 E' B/ m! X$ d- nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) T$ G. ]( r% q7 m; N; i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% M N! ]2 W/ {: T8 M- V2 M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ \/ Q( X% C A5 p* U1 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# Z0 v9 A& z5 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- i) C o$ o8 r/ v/ i, `8 S; e
} 6 o9 m9 I: M8 W# q3 W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * E/ J7 B0 h2 G
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