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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: Z: e7 B( z- C9 _# k: Ginput mcasp_ahclkx,6 k2 @# u, T/ x- L* }1 m
input mcasp_aclkx,# Z& f8 c% A" ?; a
input axr0,% r5 c$ o5 F+ g$ P' V% G4 q* a- i
, z! }. O* m, }: k
output mcasp_afsr,: f- ^1 t: Y3 Z! V
output mcasp_ahclkr,' {/ `; M5 h5 @, X( E. B# d) k8 ~# u
output mcasp_aclkr,& x3 q5 u" i" I& E+ p
output axr1,
4 W6 S% S6 R( `" P7 f% R assign mcasp_afsr = mcasp_afsx;
$ o( h! \% [3 Passign mcasp_aclkr = mcasp_aclkx;- r6 ^* I* A; L3 K
assign mcasp_ahclkr = mcasp_ahclkx;
) i- u. i& J1 t, s& v+ ?1 S+ D7 n% t* jassign axr1 = axr0; 2 ^0 _# U8 T0 c1 g9 e- a
) r% ?& P: E. I+ L8 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 \1 r* T# T1 t) ~" Y$ Ostatic void McASPI2SConfigure(void) E/ m; r8 K/ N1 I
{" Y. ]+ n' u- ^5 z/ e& n6 l( a& \$ s: b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 V' A+ i6 G% k7 K) y, c: |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& G6 R: m3 z% W/ HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ t5 s$ u2 i6 W0 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: k) c4 i7 ^- I, W, W1 z, P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 \% z* E. R7 V5 DMCASP_RX_MODE_DMA);# H; ^' j) K; j4 j1 ]) r- I# L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' [6 g! @+ \2 D8 J8 A# A I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- k4 G5 U; m- a7 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 R. I0 j1 U5 h wMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% \' T: }6 R7 }( E- N/ f
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 _4 p/ j$ V) Z: W' r4 m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */, |7 |" R* |! p6 \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 ?" ^" s+ @* w7 J$ I3 t5 x. rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 y" [) y0 u6 R$ d6 J8 C& M: I6 C6 |3 |McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,4 h( F1 \% {7 f( d+ r: b
0x00, 0xFF); /* configure the clock for transmitter */
V8 t) ]+ J, U3 s, TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 F3 A4 ]5 w5 g" G; t' y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( t0 ]( R( i4 D' {# sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. q' N. l' Q- l/ Y$ |0 ^
0x00, 0xFF);5 Z* t. b5 b$ a, g# P
+ e& Y! o$ c3 X/ e
/* Enable synchronization of RX and TX sections */ 9 f% m5 Q ], l0 o. a) U, Q
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: }# m9 }* B, K' E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 T9 F2 y3 F ^ x$ p+ p* F, o% fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 c& D1 l6 n3 t9 I `( L+ e** Set the serializers, Currently only one serializer is set as
n. k0 |9 i( B, e( e3 b$ y! j** transmitter and one serializer as receiver.
( i; v& h2 U. z( c*/
! z6 U; q% C9 g3 _+ iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ H8 h( i3 b+ q7 }6 J% a) |McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# |/ ~: ~0 |1 x' ]# t$ G- q' H* f** Configure the McASP pins ! J% p5 Z0 C- \% S8 F1 b. U" d1 f6 y
** Input - Frame Sync, Clock and Serializer Rx
2 d' T" v! q: c' e** Output - Serializer Tx is connected to the input of the codec
; Z6 q, D' T' ?2 ?*/* ^" Y5 F" `! {/ x% I" a# v, D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% i) D% z$ ^, J0 W$ S& LMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ O3 u, i$ X, k/ I8 x0 U! S0 dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ R a7 M' g) U* t7 ~1 a; x: L3 s
| MCASP_PIN_ACLKX
0 h& W* N- k3 D; s| MCASP_PIN_AHCLKX
$ @. \" j2 e7 ]: F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 G; P; y' j4 i- B+ [+ L* sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 k( O$ `/ y3 m
| MCASP_TX_CLKFAIL
/ W3 b* I! z9 q, f5 O, j| MCASP_TX_SYNCERROR
# f- r* H- F0 r. k# c0 P3 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# f, c) T% T5 || MCASP_RX_CLKFAIL
/ W2 n! B$ q+ D0 y2 || MCASP_RX_SYNCERROR 4 c/ ~9 k: O1 {5 V0 _* x# H. J) V
| MCASP_RX_OVERRUN);+ N. b& v0 v# U M
} static void I2SDataTxRxActivate(void)+ E+ e$ q) ?: X* ?# @
{
, ~$ t- u! x4 w0 i1 d/ u/* Start the clocks */
* S, S" Y# e6 O" j8 m* `6 ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& i ]- P+ w/ D: c# q% b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 b& {* i/ F- T0 m8 \& F/ @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 H1 ^- P* `+ V
EDMA3_TRIG_MODE_EVENT);
1 `2 W5 x# t/ J3 H6 M0 y! M( l) eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 u" x" d- D: a5 U- N8 IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& U" P- o( l! ]; Q& ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! Y% R& W2 Y& N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, F% A7 q+ R( o, l' E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */2 L8 ~* U/ r# {4 F O) n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);' R2 P2 K1 A$ V& J9 A
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' E2 p m. g% e" h; C4 P}
. j% t8 q2 H5 a* Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / X) x4 I( O X2 g
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