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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 Y8 Z% w" c/ l+ g
input mcasp_ahclkx,
$ z+ Z; O2 J, W) minput mcasp_aclkx,
4 K2 K, k# T0 p8 hinput axr0,3 v* U+ D0 L* i3 d
I2 ~% b$ K$ g0 V1 H6 T
output mcasp_afsr,
$ c' ]1 f' w6 f8 Goutput mcasp_ahclkr,+ u9 X# x6 j- l# l% ]
output mcasp_aclkr, z) g, b: m/ \- N% U* I3 I
output axr1,7 n* {3 q6 y8 U; K/ P
assign mcasp_afsr = mcasp_afsx;9 K I( t3 `6 r8 @
assign mcasp_aclkr = mcasp_aclkx;# e! t+ s% Q. W. C3 k, l, O0 F
assign mcasp_ahclkr = mcasp_ahclkx;
: M% K8 T7 S2 i$ I& t4 h; Lassign axr1 = axr0; # a2 ]' y: h9 z/ p
$ P1 \, H; d a: d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) L4 N2 i/ T! C$ L+ q
static void McASPI2SConfigure(void)' ^# N2 g! t7 @% x9 F* o% j
{ k0 r: U! v; }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' v) |1 m% x$ b3 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% S. z3 Q4 j7 y7 @- ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: G$ q. t( N* ?* ^& X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 y' U1 x% m0 _1 X7 S+ l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* H8 d9 ^8 @% F/ W& M3 RMCASP_RX_MODE_DMA);0 l2 B9 T$ ^* v5 ]9 y* K. S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! z! k$ V; q T8 W! A# ]5 b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* W. y5 M& z) mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ q; e0 F( T1 C& h1 ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% X1 X4 p' i G" w: R, }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 h9 g+ k6 |7 a4 Y3 G( e0 ? C2 i
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 H1 j3 l+ \1 Z! I0 _( \" \; H7 XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; p0 h. h# Z$ a! z% n( {
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% ^ B( v; P3 y' f ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," t; W; B1 F2 t6 l) O: P; Z8 J& w
0x00, 0xFF); /* configure the clock for transmitter */
# p8 ?9 y }' B' i! @2 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" p/ ^: g s5 {8 u! S6 X! gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& I7 b4 e2 q( D( [2 ?5 x/ {4 @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( r' U/ G) \6 k' V, O, y0x00, 0xFF);
# s. H; i, |$ u* G5 k; z" N+ t" R- M# h, W4 e; @# K
/* Enable synchronization of RX and TX sections */
2 z0 n' w0 {( o- \9 j1 h& \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# M( M+ B$ t- F* F6 H3 d2 e% X$ y: eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 _, z2 r! {& P0 e% v" F. dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" }4 y* b4 A1 T% U$ S5 H) b( Y
** Set the serializers, Currently only one serializer is set as
1 D5 }1 C( x* [/ D) b* m** transmitter and one serializer as receiver.5 T. ?5 c- F* y. a" b% o8 p
*/
& _* i, N) D! i0 h" ~McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 B K% |! j( o3 E# g0 D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 `4 ^# v' ]3 Q+ v9 Y5 b8 @
** Configure the McASP pins a9 C+ N7 i, O( }
** Input - Frame Sync, Clock and Serializer Rx
* e1 h9 [# W7 v** Output - Serializer Tx is connected to the input of the codec
! @* v0 V Z0 m+ @- [& g6 c: ?*/4 Z! l7 [4 q* O/ i5 f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); K/ h u1 |3 f, f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 D4 E% B+ c5 ~3 t& B: MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 x7 |0 m. @5 Z# }) S% v6 `1 G| MCASP_PIN_ACLKX
) |8 r. C: e2 w| MCASP_PIN_AHCLKX' _ P; m' N0 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ r" g% y4 B; k9 S/ uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; ]* M f8 V0 {0 D, C; N5 p
| MCASP_TX_CLKFAIL % }4 @+ ]8 l# ~2 y( ~# |
| MCASP_TX_SYNCERROR
' [1 k1 V# l0 S" O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ p+ d# v3 G9 |( M1 H+ ~| MCASP_RX_CLKFAIL
: p$ y O% x C. B3 {$ }, N| MCASP_RX_SYNCERROR
[. [5 G' {8 G9 t| MCASP_RX_OVERRUN);+ N" T" n& l! O" K1 c) n
} static void I2SDataTxRxActivate(void)
. ?" I# V, T2 O7 |# \{
1 O: j. o) }4 k, x' o) u" H' F& ~/* Start the clocks */; z! c+ u4 N$ O% t
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 }' M( `8 J1 @& e( H. y. NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 C- q+ R) ^5 W% u* {" J! W# d' hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* C: F2 j- U, n' I. }
EDMA3_TRIG_MODE_EVENT);! f+ ?0 C% ^0 u% T; l2 \% }' p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 Q6 i& i8 A1 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 h! H( v$ k, ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ D" T# _9 J" w& w: i! T3 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# q- b' W2 \. s$ c. R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. r1 J: J9 U" E% x' tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 I. B% n$ Q# V3 c" R0 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' ]0 t3 [- F1 a6 n9 C} + J( D1 A" ^( D6 ]& W! u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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