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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ W0 _+ f8 O* P3 o
input mcasp_ahclkx,
% j& E3 q& f* F3 binput mcasp_aclkx,# ~) Y; A0 K" E* O
input axr0,9 C, i# F" _" l0 C1 m% X
0 p3 d8 Q3 G5 Z& _; `# q" Woutput mcasp_afsr,# U2 o) x/ I+ s9 ?5 C+ K
output mcasp_ahclkr,3 Q% m7 p1 t. T; J, H) w# q: {, ]/ x
output mcasp_aclkr,
$ \2 B$ x/ b7 Foutput axr1,; o$ j- I! ?; d3 q
assign mcasp_afsr = mcasp_afsx;9 x- H2 e9 M) p i
assign mcasp_aclkr = mcasp_aclkx;
7 I* T$ g& Q7 bassign mcasp_ahclkr = mcasp_ahclkx;. S( _7 ]$ n5 h0 K
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) k5 p: s8 ~3 O* G% D
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 E2 g) O) q! y1 G( G. Y6 J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% G( l2 D2 E8 f0 C- B- jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( ]8 K0 \3 ^& s/ O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% A& W% h+ y; H0 r# D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. W' B; w1 C3 {/ d2 E' J. Q s
MCASP_RX_MODE_DMA);1 O) _. d+ Z) V$ K7 f$ _4 {; [/ m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, s7 ~7 s, d0 ~! \ t9 s* xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* e# |' k/ t/ j; f/ n# B) h8 y) ?- \McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 D/ @, P& _; S3 e' s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 J; i. G8 M" I9 V) S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ G3 l: G$ ^0 s3 T( ], W1 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
! [( A2 I% N' _9 y. D2 {0 Q, C+ b7 dMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' n z2 m% u/ ], b' i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ |1 O, ~4 a, C9 M! }0 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 }$ S; e* z* ^+ b; {
0x00, 0xFF); /* configure the clock for transmitter */
7 Q4 s6 P, h% g) p; @7 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- x# K# r5 N2 l0 V) E4 [! X# V5 m% N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ X2 W0 @7 H* cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 u o y8 V9 c
0x00, 0xFF);0 t& d& s& |: H$ i
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/* Enable synchronization of RX and TX sections */
7 o- {1 Y* h2 x$ x6 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ _* Z; b6 X: I7 ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 |, ^, q$ \9 t# _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! ]) L# W& d' V# a
** Set the serializers, Currently only one serializer is set as8 [- j/ O; h' ]+ @/ }9 j, q
** transmitter and one serializer as receiver.
5 e3 l$ x( K1 k) b: J% o' K*/
+ l5 g d/ E+ m9 i8 W3 A% O, fMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 w- e4 f- M8 e# O/ E9 _5 U/ ^7 j4 YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: \2 W1 J2 ]4 [2 T; ?) n- B7 r2 h
** Configure the McASP pins
1 I: l, e' y/ Z% r# g** Input - Frame Sync, Clock and Serializer Rx* B- t: y( ]7 T& g6 o: r
** Output - Serializer Tx is connected to the input of the codec $ U4 A5 b" i. ]/ [: L
*/% Q+ r+ _+ c' O/ \, m8 `0 b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 R/ X' P1 P( @0 o: R; T9 M3 ^5 f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); M; v0 Y% _- z- G) U- B3 w9 E
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, Y d) A& z9 Y. U7 |% J
| MCASP_PIN_ACLKX; H2 Z$ [7 P$ k) I* B
| MCASP_PIN_AHCLKX7 J0 k1 [. g# l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 Q8 D; ]3 B, J0 c) m' Y. O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: v- H6 b7 H" r" ^1 A| MCASP_TX_CLKFAIL
+ z% {. A6 r0 d9 R| MCASP_TX_SYNCERROR/ ~8 {0 L" b6 r& V4 h
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 q; P K( g7 t6 e# F+ T$ i# q
| MCASP_RX_CLKFAIL
' A: F0 B4 Z5 _$ H+ Z# e; }) O! l, T| MCASP_RX_SYNCERROR
5 R# V" X k) M| MCASP_RX_OVERRUN);
0 w4 ^* o$ W6 e8 Y& V& D% n} static void I2SDataTxRxActivate(void)
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/* Start the clocks */. t) i- D b! O }. X. b' j0 u7 A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 @. a6 s+ l3 z/ W4 R+ P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' f* `) h6 J6 Z9 |5 X, w1 U# c3 B, w, vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 A6 w' k* Z# u. Q3 U* GEDMA3_TRIG_MODE_EVENT);
6 k% n$ ]4 T9 w* i0 g# V& ?' EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% J& k% v( l: X( N `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) |5 Z* Z+ t3 Y1 F# q: u7 I1 D% iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( p H- e* x* S- I4 V6 E m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( ~* ]2 W3 Q6 |0 `! U1 h8 M" p7 ]+ L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 s9 V* h* }; y7 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% w9 O- a6 s5 A3 x' ?7 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# P1 W0 F* N" K; M: Z
} & ^8 j1 q: l9 A1 I7 m B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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