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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 I6 c, \1 ~6 a7 G' ?
input mcasp_ahclkx,( _( V! D. m2 t5 @2 D2 k
input mcasp_aclkx,
7 I8 `% L. V% v- L C; ~8 K: F$ |! vinput axr0,
* C9 V Y. R. D) M
" g# Q0 i; ~# U V" Routput mcasp_afsr,
* T3 q }" I1 `$ k. R& {output mcasp_ahclkr,
4 U) r( \2 y2 q5 q: m2 O* Houtput mcasp_aclkr,- k0 ?# l+ l! C4 y8 V' A
output axr1,* L1 r n- ? y/ w, G
assign mcasp_afsr = mcasp_afsx;) o0 Y& Z' [ {4 z3 ]# I2 D4 b
assign mcasp_aclkr = mcasp_aclkx;
! f1 ]: r) @- b3 t6 z% F& F: Oassign mcasp_ahclkr = mcasp_ahclkx;
0 ?! ?% ^. r/ u; m5 wassign axr1 = axr0; 4 a0 _- W/ c4 N* V# O; o; q
7 z J/ e5 ~, l3 V' N8 f& ~. N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ F. v4 R S G2 E$ ^static void McASPI2SConfigure(void)
! K: `4 H3 H- f$ Z$ a7 E: }{: i" `* k4 b' S/ f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
P$ y T3 |% p1 G+ S/ Q2 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. y2 N$ U$ @/ E, e1 y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" {2 T3 }% G/ ^" KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 _, T! G1 n( E( }- Y; W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, P5 B/ w. O$ R
MCASP_RX_MODE_DMA);
8 n9 l% I. d8 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 W( n% g. h; q) r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 l! Q9 Q+ X$ O2 L' ]' y3 k. U
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# i5 J+ W% `4 ]1 PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; y: |4 m$ d5 h& XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # X$ O: L0 a+ h0 a1 L, h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* C# f( t% A- j9 O
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); ~# m; l) d, u/ Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: T: f U* p% _! ^3 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 {: n" w$ _+ o" {; e, H0x00, 0xFF); /* configure the clock for transmitter */
+ X) o4 w+ ]& i8 r4 \. h9 J1 d: TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, s6 z; Z$ u3 N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " i! g% d9 R4 K k- ~! ~' B4 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! ?, z% I% u- V5 \0x00, 0xFF);2 `) `- K% {) W& B+ U" Q9 x
4 C+ k) k9 z. E9 w( z" K5 Z
/* Enable synchronization of RX and TX sections */ 4 T. A" G! X+ L6 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# _* l; {( s" s6 V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);4 x! D& M8 D8 m" a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) G+ d6 y# B! F/ j2 {3 P: ^% A9 I2 Z
** Set the serializers, Currently only one serializer is set as, a4 v) O6 C1 ^
** transmitter and one serializer as receiver.
( j( K3 u* q6 m*/( P/ ~' k; |/ c0 ~; r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 x+ H3 p( c; `; \" _$ I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 a6 j# y) e0 F1 P! }+ F: C
** Configure the McASP pins % B# C' B! n6 M' o* D0 C
** Input - Frame Sync, Clock and Serializer Rx( i# u6 }3 q P4 t& v9 N+ U7 r3 X
** Output - Serializer Tx is connected to the input of the codec
: Q1 K: w: Z. g. f$ w8 v*/
! F0 r. v# k7 w) }6 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. }9 i; {6 I% ]% P9 Y% g$ d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( P' t, x* q' U& KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* a7 I" j8 L: B% R j6 S* x
| MCASP_PIN_ACLKX
. W5 Z, ^/ K! V| MCASP_PIN_AHCLKX, T q0 s5 j9 N$ f, j6 Q* u5 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ g, M4 _# U$ X/ [2 x* n6 E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / q( b8 n) {- \( [2 l; s
| MCASP_TX_CLKFAIL
/ G9 T4 g) `6 P$ t, [& N| MCASP_TX_SYNCERROR
* ?0 f$ z4 i, h$ V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ N" y3 |; }! A( N0 v6 O
| MCASP_RX_CLKFAIL
7 d% X3 y4 D# x$ O& u! c6 H| MCASP_RX_SYNCERROR
& y4 G0 e5 b- g( T! Y| MCASP_RX_OVERRUN);5 c2 w- |1 W, T$ z$ r# _$ \
} static void I2SDataTxRxActivate(void)* w# E- W% a% Y a# A. H/ W
{/ P7 H; Z9 h% h
/* Start the clocks */
+ G4 _; D5 @& N; r) ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ x6 E) S A( m: xMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ T; a* V# `8 b7 h4 d) M% {! REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 J0 }8 s) ~) I9 I( fEDMA3_TRIG_MODE_EVENT);5 p6 B# \: e! d; f* ~6 v3 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 B; s5 | O* `( I" Y
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' W& @1 I6 s6 vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 e; g7 Q2 F5 l i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% k6 }: ]4 Q) B) w5 ^, W, L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& Y" N+ |+ s) G/ AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ q& u7 _) I/ z# k/ [' ?; R, s. l) L/ HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" S! _* I) l6 r- R. _& U
}
' o5 R7 o/ `3 M! @, t4 O/ N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; g% }' c5 s' U7 W* s X3 v2 I
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