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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 ^8 f- `: }, g+ k1 C9 {. N+ S
input mcasp_ahclkx,! l4 \# u% q# v) w' R
input mcasp_aclkx,8 @% k% |6 B, O7 W6 s! n# y& R- b
input axr0,( A& k+ w! F( _/ g$ i+ w0 |. Q
% K, X" v5 ^, [; b' houtput mcasp_afsr,
, W! U) M+ t) j; |7 y1 ]7 |output mcasp_ahclkr,5 q0 [) D1 e& Y0 ]
output mcasp_aclkr,
- R" y* y' w8 n S6 Zoutput axr1,
9 q {+ N) [' J; L assign mcasp_afsr = mcasp_afsx;
% G6 r$ _- C2 n1 t3 Hassign mcasp_aclkr = mcasp_aclkx;
5 O7 C) t1 ~# H5 ^- p3 D3 a. Zassign mcasp_ahclkr = mcasp_ahclkx;6 b. G6 |' D& y% |
assign axr1 = axr0;
5 Y3 C3 F# @9 P* D
, j7 D. X( r. V4 ^, e在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 d7 q( Z s& [. x: kstatic void McASPI2SConfigure(void)
- \- N7 u6 M' i2 V0 L! g{
; z3 F0 c2 o! K9 j) hMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 h9 N: N0 [' F2 `1 n' W2 x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ r' k" Z8 |+ i# @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ R; C: i. q, e: U0 }, lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- g2 M$ D) L" k' X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( X1 a: y2 ?8 S) pMCASP_RX_MODE_DMA);
7 [5 f' E; K! J) ]) R8 P, mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) a+ F$ a. I# v5 P6 B \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 v! ?5 U" w! f$ q' D2 Y1 q1 v% x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' t$ p* G, F/ L7 Q Z/ _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! ]& M5 q4 _$ J4 h7 |0 nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 i C' f* q- v# y) x' |7 R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 \, R/ |, l3 F5 J O. sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 E8 M7 C* W3 q
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # a6 T6 _6 i I. O4 L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. x; p: s3 ?# c$ Q* J% t. e0x00, 0xFF); /* configure the clock for transmitter */
$ w- ^9 w3 x+ S" cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 W1 {# u7 t9 \! s, @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 _( M* X' E/ X+ U. c0 k+ RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 U* [7 ^7 e" d, f- g0x00, 0xFF);+ }+ a3 ]# l: e- t+ z
( z1 {; `% v" n
/* Enable synchronization of RX and TX sections */
! t) W7 w% l. H; l) t$ t( uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' W2 y+ r8 O2 E, o" g' SMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% d, E7 T m7 D- c$ LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ H( ]6 C4 x( L8 E& X
** Set the serializers, Currently only one serializer is set as7 m4 V. U: [1 N( A' J$ Q
** transmitter and one serializer as receiver." _" c- N E. Y
*/
' ]. a7 u7 ?* A. x9 s8 NMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* {2 {4 k! }# h. \7 u, n& t
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) l5 s# b& _# ]) w9 u) y
** Configure the McASP pins
9 g. y+ V$ P0 H1 m, ^5 l** Input - Frame Sync, Clock and Serializer Rx
3 l' V! p5 \" J2 R8 }0 Y& D5 ~** Output - Serializer Tx is connected to the input of the codec , {7 }$ Q, h$ j) f P
*/' X7 P* ^1 b: U) @* r: _; e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: N( _9 h7 ~3 I! V% Z ?. b& ~McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ q! o3 P8 k$ C" S( \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' v8 O0 d0 [8 `& \- g| MCASP_PIN_ACLKX0 w* Q1 E1 N+ G# a, t' c/ R( u, N
| MCASP_PIN_AHCLKX
# o. g' H- {0 ~3 f2 g Q9 i, j% V7 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( A4 A$ ?" \ r) |4 {9 p, f1 |McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) n. p" l1 } t# f; X, B
| MCASP_TX_CLKFAIL
6 H ]4 O& n: g, l0 M+ s/ x| MCASP_TX_SYNCERROR. D, B/ O# {# u' M" O" q# ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , [! e5 }+ f; H t
| MCASP_RX_CLKFAIL- B0 T. ~5 F3 @/ R
| MCASP_RX_SYNCERROR 8 x' P2 e+ L; i
| MCASP_RX_OVERRUN);- V/ \8 y( g5 F* p2 Z: t3 I
} static void I2SDataTxRxActivate(void)
3 S, ?7 h" E" I+ L{
C2 @% L8 e4 X- [/* Start the clocks */ X0 X7 s$ L# |. X6 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* e" t3 ?* ~% u2 [McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ v0 y- A! `: w" Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% x% B9 M- M" j/ b T
EDMA3_TRIG_MODE_EVENT);
& ^7 Q8 g1 w* N! eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 x! a; v+ Y7 A( }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: K# `. D1 E: ]% O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, N- m9 Q* B8 lMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) U: c% _0 z6 _2 d0 k) r
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. M; ^) K1 O5 f( _McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ G% B" ^. Y8 v; OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) a5 N* \; U& Z4 P: q6 D) J& s8 F% U
} ( F8 q+ \* N4 [5 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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