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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ `4 x; F3 g B9 e1 \4 Y1 v
input mcasp_ahclkx," b! o4 b7 Q2 r# }/ ^8 s2 ~
input mcasp_aclkx,
# v) [* L! M" K0 zinput axr0,2 }, C9 K& Y. D, F% \3 J% g
: B8 [' C' J5 c+ d6 O6 Z- l& Q! d7 K
output mcasp_afsr,
4 v( T$ |9 S( R& C- B+ ~output mcasp_ahclkr,! n* U+ S f% _" Y: P
output mcasp_aclkr,! I$ q4 R/ h% H8 a1 _& U2 D
output axr1,! z! o+ q: } B3 f9 f( \. I
assign mcasp_afsr = mcasp_afsx;
; L! @7 m( V& L0 c6 b. D3 aassign mcasp_aclkr = mcasp_aclkx;- h) i- n0 v; o8 N& l/ S0 o
assign mcasp_ahclkr = mcasp_ahclkx;/ g* I' E2 x9 K# K5 s
assign axr1 = axr0; $ _0 X9 k2 `+ ^& J0 g8 q8 i
# ]4 \& j: j: G2 S
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( f7 B5 }9 g- i0 o0 G$ [! j6 A! dstatic void McASPI2SConfigure(void)
" f- z7 e5 U% H/ F{+ X) m! H! `' l: i: a* S0 F7 q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: z$ T' |8 ~, N C! L c; kMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& D: I; {2 i/ e; W R5 H
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, [3 Z8 w9 a! H! H, S A: k& \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# [- u5 R0 C4 {( O. ?3 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# v! N- z! }9 r; g' ]' w, x# R% S5 q' t
MCASP_RX_MODE_DMA);
: j v$ X2 K# A" g# T, E$ B/ J4 W0 e9 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! Z! q5 u' e2 u* kMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
i0 Q/ U" a) z7 [- g$ ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 y# ?' n3 c4 ?9 a+ t( bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 A+ V1 h# v) S" |/ E8 E- P+ O% {McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: o) P1 a5 Y& EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 F: `) I1 S6 `$ M, v/ ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. X4 X' K/ A; a# ]% ?% u
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 m; R: |% A5 ]! O: d( H; h: z5 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) I( c" Y. V; p1 F! H; d! S
0x00, 0xFF); /* configure the clock for transmitter */' J# g1 N$ y% S a; y% _% c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ c' ]# Z& r! k' v4 ^9 b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 d2 |! }+ A( f: X3 V* S: X- s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' e7 @0 K1 B. f& N8 I( D) ~7 Z
0x00, 0xFF);0 ]" S' z9 a1 |
" X! s/ Y4 h1 X' w/* Enable synchronization of RX and TX sections */
# V7 [5 K. S4 _9 U! xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 |6 |; m# S+ Q& U9 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! t& {' K5 c* g( e* ~" d1 N* F5 n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, F1 { F" L' a6 P** Set the serializers, Currently only one serializer is set as
& E& c- S, P4 k- w, H% E7 y* F6 ?" j5 M** transmitter and one serializer as receiver.
* [* V+ \: n+ z! U e2 ^0 R- [*/
5 d3 T) v s/ w) }7 R7 a; z/ H/ ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- J# l% I8 K6 x! RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* g- s7 f5 P# n% I* X. L
** Configure the McASP pins * m( `6 t. |7 k- _- {7 `
** Input - Frame Sync, Clock and Serializer Rx
9 X" U7 F2 B+ ] ^- C6 m1 F) M4 d** Output - Serializer Tx is connected to the input of the codec , p) a2 D. ~0 i' o
*/) F; t- d' ?( U$ B
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" h& ?5 y; ^! iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 Z: T. u5 G6 p/ W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' z6 ]) H/ i L) u| MCASP_PIN_ACLKX
, i9 g( k2 {: u5 _ y) V0 || MCASP_PIN_AHCLKX: V( M- d) K8 Q6 J2 J2 _
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 F/ Q3 N0 Q* U9 E0 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& T2 I" W! U# v8 t| MCASP_TX_CLKFAIL 2 u b' x. \# z3 ^% y6 B7 U
| MCASP_TX_SYNCERROR
, y2 s; M/ F3 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 i! t b& w, i/ f8 @
| MCASP_RX_CLKFAIL
* \( _& T" T! ]! x2 d0 t' G| MCASP_RX_SYNCERROR 0 u a* j6 _/ f' d1 Y J
| MCASP_RX_OVERRUN);
/ p& m! b0 |: s) C9 t6 D" N% _7 v: u} static void I2SDataTxRxActivate(void)
/ n8 T- {$ a( l5 l5 Q" F% a s{, D" \" F% F& n# k
/* Start the clocks */7 C3 L* ~, H# M
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 O X( N, N* g. iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; I4 F. o& V$ c+ L* `, L2 @3 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: I, \5 @5 o) I- |
EDMA3_TRIG_MODE_EVENT);
* H; M3 o5 J/ H" d# tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% ` i! n% d/ pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. H3 y/ l/ v1 z+ K1 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- w* A ]: i$ T1 PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ b8 u) Y& Q$ m6 z" xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, k( ]% W$ K* ^( i* d* Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ Z0 H c8 `; c& C8 j. z- gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, P1 n" r, E6 K: T" `) D2 L} 6 @; t. f6 N T. B3 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 e! @- A! z- k: F8 m
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