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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: _3 |, v4 b# i( K a! n, hinput mcasp_ahclkx,
, P8 b+ g; l4 x( @& {* pinput mcasp_aclkx,
0 K1 D( Y/ T% c& }8 F, c- Linput axr0," c+ c, L0 y6 S0 l
$ {8 V) a# k8 Y" d# _output mcasp_afsr,2 x& o/ g5 K' C+ O7 R
output mcasp_ahclkr,
9 n+ t- M- b( l% @( T% loutput mcasp_aclkr,
# a' D) d, v0 \: n" _- uoutput axr1,8 \1 d. s. y6 t% ?. N4 F; g! z
assign mcasp_afsr = mcasp_afsx;
4 C7 g" `' e) kassign mcasp_aclkr = mcasp_aclkx;
~1 ^! f& _" a( y) w9 wassign mcasp_ahclkr = mcasp_ahclkx;5 g1 p7 Y3 J! x( D5 K3 b( i
assign axr1 = axr0; 5 k; u6 b- L9 `
0 Q6 u1 E) D; X" C在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' l! ]& H' ^/ |. _4 V& @: L
static void McASPI2SConfigure(void)6 A! u8 |% Z9 v- j
{/ [0 T( l( I ^$ x( f( t
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 Z, ^, ^& L0 m( R! Q* S4 i8 f6 t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! l( P" B; A9 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) t, f0 z- x4 ?$ x9 K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! f2 B9 k+ p/ ~2 i4 R$ w$ n1 Q4 U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ `! p5 R/ v0 A4 U/ lMCASP_RX_MODE_DMA);9 D& d" I% @, f8 b% ]3 f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ D# z/ ~7 d1 G$ o% Z8 b; y( M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* r8 s' A# }" o; n; @' X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ m1 V9 ?& v7 h0 _! s/ L0 BMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ V- g; d+ P. B9 E* ]4 d% |6 [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # E( e5 p5 X- E1 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! Q, D$ I( |( x) C I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 k% ]3 y( O: O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + }3 W( a* T, @6 e; k% x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# H( F g+ B+ f: a" D4 \$ u4 P0x00, 0xFF); /* configure the clock for transmitter */
/ r$ y4 ?; @! rMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 U8 W' H3 e5 |2 y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 z9 W5 f3 z) q/ i2 J2 W7 Q- l5 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# {' a# {6 H& g* w, q; k( {8 e
0x00, 0xFF);9 n( Q6 q9 ~# |3 S: C
8 L+ d* ~4 k2 Q0 A/* Enable synchronization of RX and TX sections */
; Y( O# K8 P! D$ E2 |6 g$ `McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, |9 U* @' @( `! @' X/ G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. B& w; [6 x4 s5 n0 P) E- AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 G& [! g4 R" X0 F9 v( h
** Set the serializers, Currently only one serializer is set as6 m' O4 W- p" O# r! T$ L
** transmitter and one serializer as receiver.
0 K# y) w& v# D8 K- x*/# [# h* |+ U: j/ f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
m; L& W& u/ e9 w, K* ]% mMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. Z- o0 c, j Z3 u) R8 w G5 t
** Configure the McASP pins
; |4 j7 h5 G! b* o1 E& o& h** Input - Frame Sync, Clock and Serializer Rx ]% D3 b5 E" ^- [% e5 s$ R
** Output - Serializer Tx is connected to the input of the codec 4 R; c' d2 ?$ l" f# [. W
*/( T$ }/ d% D4 V3 P- x) E& X6 L' }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 m8 Z' F- m# }7 FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 q# k3 x$ S3 V) S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 I. V8 \$ ?# m) ~| MCASP_PIN_ACLKX9 x) U( C5 G5 E3 ^8 a0 A! k4 f
| MCASP_PIN_AHCLKX
; ^5 O! x9 w+ f& {0 T/ |& I| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& J/ m+ L, u9 c
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 f7 Z& ~7 N- U- ~$ \" Z2 T: h9 \ s
| MCASP_TX_CLKFAIL ) t- S" D/ z. a: j; }
| MCASP_TX_SYNCERROR
$ F" C. ?3 | M& y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 A _9 G4 p6 @" K! C# O2 f| MCASP_RX_CLKFAIL+ f3 b/ `! j8 I$ E9 k5 {
| MCASP_RX_SYNCERROR ) A8 i/ F# m- Z2 N
| MCASP_RX_OVERRUN);" C- ]1 j8 a- \: Z6 e
} static void I2SDataTxRxActivate(void)* ]; d( u$ X$ Y% P# C5 v
{
8 [ L; _4 [3 I- r9 v/* Start the clocks */# [/ r k- d3 q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 ^ }/ p* P+ ^8 y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 \- ^/ g5 E; x8 y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
t4 c: p2 j% V! Q8 u1 V8 D, E; Y' GEDMA3_TRIG_MODE_EVENT);7 l: r" q" {( N1 F( h& w2 c" [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ n; L L& f- b& s; T+ G9 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 [- j4 T/ T; V, m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 E; e" k4 V- O1 RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
1 N, o8 ?, c9 B4 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 y' i3 ?- k* eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* l0 H; _0 k9 o! k0 d5 Q( ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 B4 r; M0 M3 Z3 h6 p
} 7 R3 ?7 N( v5 J k! H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . _4 Z. s7 y. ], q7 i% N& c7 p
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