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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 N# b' j) w, b( j
input mcasp_ahclkx,
3 p/ S$ g3 t. dinput mcasp_aclkx,2 |2 n# t) C1 c6 G9 V
input axr0,5 g8 r( ?3 r! G. o" X
! o9 S- C' L: Y8 s, v' f
output mcasp_afsr,
3 |, T; @8 P0 G% ]! q1 \2 D4 C9 `output mcasp_ahclkr,
- ~' O W2 r- M+ N" Moutput mcasp_aclkr,
2 H( v+ d3 e% Z, |! {! I& qoutput axr1,
8 |$ {$ i' N; N! o assign mcasp_afsr = mcasp_afsx;; Q- D/ a! D- |8 o& e+ {
assign mcasp_aclkr = mcasp_aclkx;
: R7 k& @0 S2 ^- e9 z1 J% \assign mcasp_ahclkr = mcasp_ahclkx;
% N p3 q8 n# D3 H( B6 x+ R5 F5 `assign axr1 = axr0;
7 o" J3 |# K3 j( {5 F9 k/ g
( O @! ?% u* f! _0 M) `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 n; H2 m2 h8 ?& i9 g
static void McASPI2SConfigure(void), ~ ?: A4 ~3 l* R
{7 g+ ^1 f) Y9 }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 b' h) W3 E2 {) B+ K& J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ u: @+ a' Y# p+ v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
[1 o! b7 r9 B" _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. M" G% A' R8 ` e9 r5 UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
~5 u q( L0 T9 S1 cMCASP_RX_MODE_DMA); k7 m V% C4 n2 N+ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' S ~% o, C; W+ b2 q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 i5 d9 c% o6 c4 K' a" x0 A! D; oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ _) b' U) M2 e1 pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 N h8 U8 c9 f5 u$ @2 EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 Y0 {- R& ?. C2 O
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" ]1 K& j$ _4 r& h, o
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. G" o; q! e J8 N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 j4 P+ m8 R. K+ rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- J6 s1 o# c/ X7 |; f c- M0x00, 0xFF); /* configure the clock for transmitter */$ N/ D3 `& p/ Z' Q2 a: G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# `& S" O" s+ b: M( k9 \0 EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : T* ~3 G6 }1 k7 s; v; {$ V& b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, {: p" }+ L( \ k! I2 x, h
0x00, 0xFF);
3 J" E" v) \& z! G
$ G" A& q1 {6 P8 S. `/* Enable synchronization of RX and TX sections */ % G6 `/ k4 K# Q# T. o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, `8 `% c2 B: \ u! N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ A5 j; m: {' S) a, \4 C- [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 Z3 {" n& ^6 p3 U; y# w* f
** Set the serializers, Currently only one serializer is set as
" f( \( V# \+ K: b8 _9 u; r** transmitter and one serializer as receiver.
9 D$ {% z# D, ?% J, y6 b*/9 n& ~$ ~: ?: C* _7 e. O! S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 Q1 W' F1 u9 F/ M& Y! X, N7 |# _McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 F$ p( }8 n& X& y+ [
** Configure the McASP pins . U1 i& |4 O2 \% Z! K! B
** Input - Frame Sync, Clock and Serializer Rx0 J% H$ i6 t4 n! r: }
** Output - Serializer Tx is connected to the input of the codec
" F/ D: a$ e2 p2 Z: p* N; t5 G' ^& I*/5 f& g# I1 T: c$ b) |; r2 M: X
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 z: P; t2 `! c: i$ AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 U) \4 Z! H* z% ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 z5 ~8 R" r$ M% x! ?
| MCASP_PIN_ACLKX) T' d9 Z) Q; c& h
| MCASP_PIN_AHCLKX0 D1 M4 }6 t$ a i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 I2 \# w2 C% p! mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) u; C: \2 i& O- ^| MCASP_TX_CLKFAIL
$ K; N6 v& m& \ T+ g3 E9 f| MCASP_TX_SYNCERROR3 f* d& W, I5 B7 V( D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) K+ c! w( K0 r" Q
| MCASP_RX_CLKFAIL
% p' H& q: _4 @| MCASP_RX_SYNCERROR
9 Y6 `( J! y6 R0 E6 |% ^1 i| MCASP_RX_OVERRUN);
' w$ e, @; X% t1 Z3 _* N} static void I2SDataTxRxActivate(void)
2 B/ _1 K- e2 g; P6 u. c{" I$ h( `8 a; n( ]: i2 S
/* Start the clocks */- h2 D4 k2 o7 e/ Z& k6 ?4 ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, C+ T. w6 N6 ^ a6 G( dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% G/ L- ?+ U+ _, `( y( x6 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 }$ a3 ^7 a+ Y6 C6 ^/ kEDMA3_TRIG_MODE_EVENT);+ {# U: f+ H! \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) t D. m# v0 J, }5 {' n, aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 |* [- m7 B2 w- ^8 X! g8 `. EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ i! p9 E( I% Z, mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- A7 J8 }" k+ G" _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ U( j0 }# N5 e& I4 @" \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);, m% D) D6 ]) N3 [( c
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% A2 f3 i3 B X6 q
} ) N D! a: x% s* j$ F- \8 N
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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