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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 ~) U1 }: z. W& Finput mcasp_ahclkx,
; b5 q" f2 ^0 Qinput mcasp_aclkx,
1 J3 j! k/ g, a: F( minput axr0,4 C' {0 V( E% i7 @: {% C
1 F* S6 B$ e' ?5 K7 d9 h- @, f3 Youtput mcasp_afsr," y1 ~& ^2 h5 s# ~/ l
output mcasp_ahclkr,
5 j& r- a$ x8 B- c. houtput mcasp_aclkr,
/ D9 O7 J/ ~* I( routput axr1,
9 s3 V% l( H- k assign mcasp_afsr = mcasp_afsx;
1 i2 n3 Y6 D2 R0 Oassign mcasp_aclkr = mcasp_aclkx;
2 x% b* W/ h9 zassign mcasp_ahclkr = mcasp_ahclkx;
/ K7 c. o1 m+ F8 h9 l/ N8 ]assign axr1 = axr0; . F ^7 O1 E- c5 q1 Z% U* X
. A; c% t7 ]4 c( s# F! _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 t4 g5 @1 ]9 Xstatic void McASPI2SConfigure(void)
7 f( z) l, A2 N4 D* y- q- j ?{7 P( @' g9 ^4 W; H3 G* B& h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% J1 D/ d5 x1 e6 ~; G- e dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- l6 _! B# }2 M! y/ OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ w0 Q7 ~+ Y; Y jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 D% Q$ n/ T/ Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 R( R! o/ s' @1 ^) R7 X* C3 LMCASP_RX_MODE_DMA);
5 x, `# }) |5 @% {& QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: n3 j/ E, H3 Y G% zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 A# T% v0 ~9 F2 l, k; C; d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " m; ^7 q1 H- ]7 x& [0 A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
m, s: M7 v) y- v( J% ]- d/ z/ ]+ |) s, k; UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( D4 C1 D3 _" V( L. J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% o8 q1 F' f( U* y( [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ ^4 l( G0 p l) V4 QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & M' a( \9 k5 c& @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! K; `6 {4 j7 |, l: Y" v7 Z/ t( k
0x00, 0xFF); /* configure the clock for transmitter *// R5 ~$ K& K5 h4 ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 e3 {$ S7 W# s0 E4 P( S% _McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 C d) L+ Y w u, O; W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ d, t1 y* Z' @+ |4 r y, ^4 r
0x00, 0xFF);
( C) P0 B5 |/ \+ s/ d6 X
2 W0 }6 j+ q* k2 }& L1 S% G/* Enable synchronization of RX and TX sections */ 0 \3 c) s- W* @6 r$ ^) n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) j" X2 g: n* E. ~( I1 _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ E9 t* Y) Q5 B/ e9 b+ Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) ? J7 t8 S9 t" o5 L: Z** Set the serializers, Currently only one serializer is set as& n, G9 p9 w' R; ^# P
** transmitter and one serializer as receiver.) ^; g+ D: W/ u, s
*/+ ^( d. Z3 M M: p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- K2 h/ [: y. j4 M% _3 @McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- z0 W& S( l, e) ^4 @: c! q2 F
** Configure the McASP pins
8 p) J! p2 J+ p% l) |** Input - Frame Sync, Clock and Serializer Rx
5 L$ v5 J* S, u* c! x: l** Output - Serializer Tx is connected to the input of the codec
4 V7 d& d7 Q& ?6 x5 q*/ A4 i4 G* V+ v1 {6 C) N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' @5 ^ Y0 l- P7 z2 g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) q2 s. h3 z6 v- e2 H$ C6 v( zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 K! @- R6 Q( s! ?( B
| MCASP_PIN_ACLKX( W+ y! P7 D; ]
| MCASP_PIN_AHCLKX, T- w- o$ W5 I! }& ]+ ~ m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! V9 d* B h$ t# j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ R; V6 L0 E. e& V) _% N| MCASP_TX_CLKFAIL
; k {# Y% K! I' \$ ^| MCASP_TX_SYNCERROR) `+ d5 `1 L/ N# q) b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 f- z g+ D! q: i$ Q| MCASP_RX_CLKFAIL
+ i: b9 i( ~* m+ c| MCASP_RX_SYNCERROR 0 E7 i8 c( M, }: G1 r
| MCASP_RX_OVERRUN);4 P3 W, a( X! S4 d
} static void I2SDataTxRxActivate(void)+ Y) y7 H: V; v: Z
{* I, D+ C4 y; i$ k2 ?) W
/* Start the clocks */# i( R/ ^. ?% p N4 `5 o4 a. f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' T0 n3 @* X$ y$ ?. S& WMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& s9 u, A2 [0 Y" D* l2 H) H- _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 Z1 O: b7 F0 Z9 NEDMA3_TRIG_MODE_EVENT);* t- I* F( ]) N% R% r4 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" M1 Q% \& D3 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 B0 k4 q/ P( c: C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ Y& Z$ n# I- w, R% A6 }: O: |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// M; g P5 d& q2 G) v1 M, m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 [- {% @7 b& H* C8 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ D5 s2 D: y. O+ U' j) O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* o4 B' e% y( r; E} 3 Y, h0 V. Y9 b. S" j; w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 l. O1 w5 C5 U& _; V: ^% |# m# C
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