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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 f/ E* ^5 a" Z A6 B! n, }3 ^0 F
input mcasp_ahclkx,3 i; m( Q( U) g' F- {
input mcasp_aclkx,; y. w, Y; l H- N( ]* a
input axr0,4 [7 S, ?3 h/ D- U. _& Q
: i+ A! P4 W- G6 ^6 R' |
output mcasp_afsr,8 k' `. E( ]% f' n/ y1 j5 h
output mcasp_ahclkr,
3 }% _5 [0 H% S1 c* qoutput mcasp_aclkr,
4 N5 x7 X& Z+ X/ W2 soutput axr1,5 L0 u8 `5 j$ |1 z8 z" j3 X
assign mcasp_afsr = mcasp_afsx;
+ y& C( G. q) q. O# e) ~) \4 u' sassign mcasp_aclkr = mcasp_aclkx;$ w) t& P3 s8 H" V, R, p
assign mcasp_ahclkr = mcasp_ahclkx;/ ^8 T4 P* ~; j! ]: e( l
assign axr1 = axr0; - `, h: B+ B/ J. g
2 s. R) N6 H ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 q$ F! x8 S4 Z6 R' j. z$ e, ^static void McASPI2SConfigure(void): p9 u2 z7 S8 R* ^ c8 }
{
4 L& [" r: g g; }$ X6 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. ?1 ^: {/ O$ {: t. M6 H/ GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ l! {% e+ ?! H% X# o4 Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' ~/ a! r1 E. OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 f6 m/ z, \1 \1 `) p* @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! X% q8 X$ ~* G. m$ ?. o7 D- pMCASP_RX_MODE_DMA);
3 P+ e! M1 S- O( v& oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," v2 I" O7 W! b z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 H! j4 D: b$ u( B; q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, U, W7 L3 x3 a7 V# iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& R! Z5 f+ b2 ]) t0 @# [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( U; n6 O4 F j5 Z4 m' m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// }5 d# U9 k' o* y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ _+ A2 y) a( z, n# X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 ]5 \% ?4 m: NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. L9 m% X& V4 Q, _0x00, 0xFF); /* configure the clock for transmitter */, ^3 ~, P% R# g: X& v) o4 j
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 Q. I! |# \; V6 ~- w( @
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 I, _1 i5 F4 g( e% j2 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 M7 U5 r4 C) ?# c6 Y% `7 U1 \7 f" K0x00, 0xFF);
C) b3 F0 J+ v+ q/ i V2 `; p
+ g6 }0 |6 [+ n/* Enable synchronization of RX and TX sections */
5 K1 E/ P0 m1 W; F: uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ G$ t8 v& C& z% G! W( \/ {5 oMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' I3 s( c! ?% t) A; p3 K/ Y! a2 |McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! Q& ?5 U6 @1 z! n** Set the serializers, Currently only one serializer is set as
/ I: u& y$ y. R! k** transmitter and one serializer as receiver.
4 c1 x' p$ F3 s( b*/0 k3 L- {& Q( ]" Y$ H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 x n# L1 h3 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 S. s( c* s. L9 @( Z* D9 v
** Configure the McASP pins # ~6 w& d3 t% x( q
** Input - Frame Sync, Clock and Serializer Rx7 b& Y. K( E4 ~7 K3 N
** Output - Serializer Tx is connected to the input of the codec
( r/ u% N$ Y) h4 U*/
1 l+ `: |+ |0 z/ PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- M( s( l( Q- Q3 W( ]) h% ]. nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) ?" h( v* v9 T# Q8 n" LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* k/ ^+ x' _! g
| MCASP_PIN_ACLKX
/ m) c- X& ~, V' _8 Z4 F2 H| MCASP_PIN_AHCLKX" b( M2 p* ~ e( `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 G/ j5 O& n' d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' H# Z$ x( y! |- o# u| MCASP_TX_CLKFAIL
. n* Y4 d+ W* ?2 W1 s) u8 Q| MCASP_TX_SYNCERROR
; ~0 @& L+ T; z2 F! `9 F" h9 R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " A" e: e0 M- ?0 ^$ V& F% ~3 i
| MCASP_RX_CLKFAIL
7 m5 K, p: e: b) ~, I| MCASP_RX_SYNCERROR
& Q3 t u$ h5 d6 U/ K| MCASP_RX_OVERRUN);1 n) {8 x) G( w
} static void I2SDataTxRxActivate(void)! M# [, @" ~7 J
{+ ?1 }. }6 u8 t! [8 V% R& {
/* Start the clocks */
7 q1 F( Z/ z" ?* t/ O3 m0 tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, I' Z7 Y% ]8 ?7 A5 J7 O/ v' GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ [- m) t& E$ `! [5 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 g# [" i' b, s' `* V2 m" jEDMA3_TRIG_MODE_EVENT);! c0 O0 h# F2 A% d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# t; f$ E O# J9 f s1 LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
N# ^0 T' R2 G3 A$ ?, t% U, oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- M% r$ E% c4 H4 i& b0 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. [% p# z0 G8 a- W Y) g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. k! p( L% X b' \) X/ AMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 U; c' H1 @* t" {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ c7 t3 y* d* _# | p}
( u% w! M5 ]; X+ L# D* y9 U% n! D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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