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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; h( |' S6 l& }, s7 [3 _& ~2 \6 n& a1 j
input mcasp_ahclkx,
' }5 X2 n, s# a6 T! Ninput mcasp_aclkx,
* |! F( U' K2 B, @# W; F8 e2 {input axr0,9 b' |; B0 ? e, O$ z
2 ^" r- m4 K ~$ i7 Toutput mcasp_afsr,
8 X* {2 i n. poutput mcasp_ahclkr,
% u9 }% J6 Q; Y9 ?$ s7 a% G% Soutput mcasp_aclkr,+ F; F/ `$ Q9 z( k3 L$ m
output axr1,
# P# G+ Z x% Q$ b: L. C7 L assign mcasp_afsr = mcasp_afsx;7 m& C$ _! \* e u7 ^$ G
assign mcasp_aclkr = mcasp_aclkx;! I0 U J2 s/ G0 W; a8 s
assign mcasp_ahclkr = mcasp_ahclkx;' { p8 `2 b* ]
assign axr1 = axr0; ( [! E7 A3 F; M. F; v; ]7 r! A
( S, o* W G# V# E/ i7 E* K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ o* G& R: H5 ?1 t$ N0 f$ M( Astatic void McASPI2SConfigure(void)) W9 R0 k/ v2 t, Y, R! z
{
4 f$ }* Z9 R; W2 D. \1 i: k2 fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 d: S7 q" R$ t K7 s9 S, e
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ g( l x& N& s0 VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' f: a/ |3 B1 P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 n0 y' s/ D$ p- IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 L6 O. K9 F Z0 M0 y; Z
MCASP_RX_MODE_DMA);7 h) r& e, O, y( F. l! x
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 W$ t' O+ r: f; g& j: TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% X( K0 H! V4 w! R6 f9 [) K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 q0 S; p5 O2 `4 u4 @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; f2 S; D. Y* f3 W1 SMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + ^# O# ~/ K! L3 h' E _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 G! K6 Q$ ^: i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ s+ d6 ~1 V! q6 k; r7 [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" ?. x' `5 `. d1 k* W, ~- YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- E5 Y+ P" P2 ?% x$ n9 q0x00, 0xFF); /* configure the clock for transmitter */
7 S, J- x$ ]! R" c) B' v- M' ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# B7 R( p6 s$ F) S4 a
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) `2 V: n& F9 V) y7 K7 b9 LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! _& R8 g# J" s5 C3 T
0x00, 0xFF); i9 U' G9 p/ D" A9 r
5 j' [7 C2 q! t. P' V* A
/* Enable synchronization of RX and TX sections */
5 \+ U Z3 H. [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' u# H" K6 N! PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
k1 [; n% T7 O4 s" gMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 h8 V5 f# G2 ~8 o/ R2 Z- K6 i
** Set the serializers, Currently only one serializer is set as* O* _2 j1 s, K& L4 }
** transmitter and one serializer as receiver.! H b/ K5 T8 R5 B3 @ G- m' I) Y) ?
*/% ?. \* N! `: T+ W, y5 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; {, ~, k# W4 o. K6 R
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; W8 M3 b% x1 _" Q1 }- j2 Q8 B** Configure the McASP pins
4 } `/ A: z: [7 k0 \5 e** Input - Frame Sync, Clock and Serializer Rx
1 [' z, A& E% g8 |; h** Output - Serializer Tx is connected to the input of the codec
4 [% n0 q! C8 z, l( d*/
, Z8 \* Z; J8 YMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( h3 u" S4 [6 d* PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, j8 {5 K% M+ p3 f; I
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# Z9 D. ~7 a9 u| MCASP_PIN_ACLKX
& \4 {( ]& V2 Z| MCASP_PIN_AHCLKX r% J) r$ j6 J% A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 o4 X- k" T+ y" LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) @' |+ a. u& I% r8 |5 ^3 t% J| MCASP_TX_CLKFAIL
T C$ j5 y: O9 I| MCASP_TX_SYNCERROR# T. M' n8 g3 v3 J+ P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * w. X) A" w7 H7 Z$ V1 O
| MCASP_RX_CLKFAIL
" k8 E. Y( v. i: r0 r2 \( c9 n| MCASP_RX_SYNCERROR ( l! `5 C- g* z, B
| MCASP_RX_OVERRUN);
/ J' N) @' H* D* y3 i# R2 m} static void I2SDataTxRxActivate(void)# P" C$ l5 ~3 x* ^0 s6 K
{. v( W4 {* I) y' V
/* Start the clocks */# |/ O: @/ v7 m
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 m) ?- V6 G" B" r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ X( C; J5 ]9 v# F7 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 F3 b$ Q7 G$ T4 [ h7 UEDMA3_TRIG_MODE_EVENT);
# j. ]2 s: Z2 c8 w# I; s$ y4 n! ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% B' g, F# b9 _7 |; ^' ?: i$ p* aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* o* |+ x8 M; B. X3 {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ p. a' F% @ T {( a% r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 x1 D% f8 q, R4 e* h3 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! _+ Y8 j, a" }# `* `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 K3 T4 s( B) i' K* e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 M6 D7 i P; `1 F3 Q1 ?}
; r3 G) z: q/ ]* j" }" K请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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