MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
; m) z, a2 D3 K" l! a2 F* Yinput mcasp_ahclkx,
input mcasp_aclkx,
- \3 W( V* |2 s9 I  N" e# `input axr0,
. p. V+ Y! x" Y; ~4 C# I8 O
output mcasp_afsr,
  Y/ J, J/ Z$ L! D' V% J! q2 Loutput mcasp_ahclkr,
output mcasp_aclkr,
# _" D% ^/ U5 _* ~" K) Voutput axr1,

assign mcasp_afsr = mcasp_afsx;
2 m# ^( I4 o1 z( I# S) Y/ Sassign mcasp_aclkr = mcasp_aclkx;
0 w1 d, ?8 `; t5 e/ F* F  t- i! _assign mcasp_ahclkr = mcasp_ahclkx;
" b  p0 I' ^: g9 H- r  Q+ aassign axr1 = axr0;

& O% Y. Q# u) ]6 }
5 y" z0 I: a; m( ~+ M) l& G9 w+ M( C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

& S7 d+ I- K2 Z# o- P

static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 X1 W/ Q/ O7 m; P, P6 r0 ZMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 k7 N, X, X6 }9 p- o4 w. hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ G& c& ^1 g4 A$ H9 vMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 \/ U( G7 p! A) p. ?0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 G" x( W' R/ X: mMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 V+ h  M5 G$ X/ _McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) E1 E% ^1 h2 G1 j* r) P5 ^" a( L0x00, 0xFF);
! ?' k2 [' n0 @; B+ F  R$ |& Q
# R9 z  D/ {+ R, X/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 y% R; x9 P/ z" v9 }6 p! w; U1 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ n* ~0 D; z" J4 c+ V1 IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
: F6 P7 K" I" S% B/ q% `" o** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
: [& H9 N8 o" g+ t0 n( I2 @" Q' ^*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 ?) [2 Z. N; q& e. u: f- h- oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
# n" \9 X0 X1 e7 y" Z** Input - Frame Sync, Clock and Serializer Rx
2 S* q# |) @+ ]7 d- j** Output - Serializer Tx is connected to the input of the codec
1 ^: w, d* e2 I+ D4 n+ D+ V& K# M*/
. \0 G& a2 f# o# I! r; s- i3 v9 lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
0 V- ]2 D2 J0 C/ F) q! }! x| MCASP_PIN_AHCLKX
) i$ P! M5 P/ g1 Q| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
: E  i* |1 i9 L9 M: Y3 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
6 B1 h2 h8 d" W. U! u" D| MCASP_TX_SYNCERROR
1 |9 a+ Y( C, b1 e0 C| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
" t1 r, t0 t8 {4 J. W}

static void I2SDataTxRxActivate(void)
8 S' i  f6 K. Y: K{
/* Start the clocks */
) b% A4 }; D  {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ J  c' f5 L: N' DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 }8 e% t. }& A" {& i, Z4 BEDMA3_TRIG_MODE_EVENT);
! G  B+ }2 ]* KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
7 p* @- W; _, v( h% ~& m- sMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
# ~$ S. |6 k2 Y& j+ o0 J0 t. o6 vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 m2 L. G1 i" X}

* G. E4 X' L' [, {" ^+ G

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

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