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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! R8 b8 ?/ p& M4 x5 }7 I/ o" J1 ?' d
input mcasp_ahclkx,
# _" e0 j; H( k% U# R9 C9 Minput mcasp_aclkx,
$ M' ^% E, l8 l8 {$ u' J) J, ^% T0 Winput axr0,
0 X; [0 h; ~$ W- K2 U, K1 K& }
. K A3 H3 ?; X5 Xoutput mcasp_afsr,
2 U$ m3 j) Y7 i# Q8 w% P; Soutput mcasp_ahclkr,) R4 a, G% \5 |! n% m
output mcasp_aclkr,
+ p1 [8 @* j1 Y! e. T- |output axr1,
5 s/ ?$ X4 j9 X+ W1 {3 w assign mcasp_afsr = mcasp_afsx;2 V3 R6 ^/ t) J2 [5 ~6 y, @* ^( X
assign mcasp_aclkr = mcasp_aclkx;3 `2 v4 V5 q1 F$ j
assign mcasp_ahclkr = mcasp_ahclkx;' I8 f) G, ? v/ A8 _' m c. h
assign axr1 = axr0;
]' ~3 Z# D, E' Q( r$ E1 X) \; n+ ^ z) w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 c. i4 Q. h7 Estatic void McASPI2SConfigure(void)0 k; @+ j; `8 U X7 |1 @
{
) ~' [6 {& }; eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 M" s+ m4 q T2 x3 S3 jMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% p1 g: T; j5 z# H) ?" ]
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 R% R3 X" l0 k5 U( cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! A; z* i2 ?: f0 }: l2 iMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 x3 I. B/ B8 ]+ U. N
MCASP_RX_MODE_DMA);
4 [5 V5 U g* V# z% w, QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 }' S/ q0 }( z6 v
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 w% ~+ }: _' F% S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* f% I4 w5 d: p2 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 x: P7 s0 {$ ?6 y0 u4 z; r9 G! WMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - t; l* M2 N; C K( ]+ C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 [; r* Y7 y. r$ M AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 C3 C% g+ J7 k! DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 e- T7 a; [. \# j4 W7 _( j; l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& G+ F1 w4 D9 W! O0 ?0x00, 0xFF); /* configure the clock for transmitter */
) U5 E; |2 B' Z' L1 i2 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& C3 f6 a X1 X8 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 [& G8 A$ D% T# m( |0 ?
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) h$ Z, }; }& G f6 E
0x00, 0xFF);. Z5 _# _; r) o! e
! M# g R( [+ E5 T7 D1 @/* Enable synchronization of RX and TX sections */ 4 R6 u+ e) f# O# S( l( I+ a8 y( ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 ~5 D% P( N$ E- U' {) l8 N
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 ]. Q$ E" R6 y6 h$ n; XMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 B" o2 _% O& L, _+ Q" J
** Set the serializers, Currently only one serializer is set as |; C) j* ]1 V2 r
** transmitter and one serializer as receiver.
% R/ S; v4 ^: L0 b% W& _*/- `+ b# F, i- }( b3 V1 k9 ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 R* T Y4 g" B. sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, \' r4 n [% ~9 t. i** Configure the McASP pins - D ~( ~1 f3 j' J* }3 {
** Input - Frame Sync, Clock and Serializer Rx
6 I( F& j7 w" n" c** Output - Serializer Tx is connected to the input of the codec
. b1 X9 a# h" b& x$ n( ]0 Z& F' @5 V*/
# ?8 O" L; Y8 a+ C6 uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# m; Z3 X8 L7 P* V3 x# k8 c( u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 c& G3 L; z4 M1 x/ fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& o% v6 D, z! T! v D( e| MCASP_PIN_ACLKX3 g. `9 B4 A! Z- a8 ]: I
| MCASP_PIN_AHCLKX: B+ U% ~) A$ J& B: S/ i
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) M: ?+ ]% \1 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ f! s5 W0 [! O# Z$ h| MCASP_TX_CLKFAIL 3 j$ a3 S0 h( y& J! z& A
| MCASP_TX_SYNCERROR
$ L+ P& h2 R$ P6 q" s7 E$ P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " M; h1 @1 {' E" k6 s! t
| MCASP_RX_CLKFAIL
( t. c& w9 V4 w/ l9 n2 q| MCASP_RX_SYNCERROR 2 C( h7 z, M2 m' v- ~
| MCASP_RX_OVERRUN);6 C$ J0 |! z: \
} static void I2SDataTxRxActivate(void)
1 g" [. I' ~$ N7 H8 o{
8 ?7 E0 a+ j& ]- }+ M0 {/* Start the clocks */
, e7 g6 z4 I4 T! ~' k$ K- b, `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" T% f+ I, @9 g, m$ k2 l; @5 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 ~( D; t. i: s0 L5 z. t# U/ |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- h8 n& ~0 s+ Z' Q( ` y
EDMA3_TRIG_MODE_EVENT);- p% Y4 x7 d2 g% h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 @' |+ R7 X. B) T7 x# zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 I# |+ }4 q' J- G8 A9 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 a, H8 T- g. w \( h! iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */5 ?, Z& l1 Q; m# K! m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 F: ^) G; Y4 d6 ~+ r0 ^) c% uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; H* J/ |% V1 C8 z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 \: \1 c- E. b3 {: x
} 4 q0 g5 a, K. Z1 s- B& o& o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / ?% y) y* D( R6 q! s( F" h z' S
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