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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 |0 H+ P+ A' Binput mcasp_ahclkx,5 u7 U, q E* c
input mcasp_aclkx,9 P+ w5 a3 C( I/ X7 w- X
input axr0,
" E, U2 {# _; }5 H6 p
6 s( h; z1 r0 o1 J* @output mcasp_afsr,
# s: U. ]" ^2 L4 d. ^+ Goutput mcasp_ahclkr,
5 `! [+ \# P6 c- voutput mcasp_aclkr,3 ?) G5 j- P8 E s
output axr1,& D% `$ O& \7 N) Y2 m. ?
assign mcasp_afsr = mcasp_afsx;
. T5 j9 D& \% Q+ E1 zassign mcasp_aclkr = mcasp_aclkx;% P; e7 I- n( k8 E
assign mcasp_ahclkr = mcasp_ahclkx;
1 r- |# V2 \: F* o M% q7 Z6 Aassign axr1 = axr0;
( |' Q8 ?- e$ e; g7 S2 ~ Q! m/ N3 V/ y Q5 G* [/ C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 g3 b' \; h" @5 z: V2 _5 S6 L* ~, gstatic void McASPI2SConfigure(void)
" k9 e2 e2 X! R{
$ O! \$ T- f& w" z: t' G8 [McASPRxReset(SOC_MCASP_0_CTRL_REGS);* l2 I2 h# T4 M: @- x
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# V4 U; r; I6 K, D1 |; F3 n+ V8 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ f0 Y7 S; P, L; L/ N- j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; j2 N4 j! g2 d$ `+ HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' X+ h8 G" b+ OMCASP_RX_MODE_DMA);
2 a- u6 G2 Q+ ~2 RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# K6 o7 U5 C1 b5 {+ {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; n; \3 F1 Z, c$ P; |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 B- C0 i4 ]# T$ N/ K& `6 P* SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) Y5 Y3 N! @) a2 l2 n( xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, ]% P' d5 `3 `. \# CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" W7 Q/ r9 t7 r9 zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 x3 R2 P- {" ]' {8 cMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / ?9 o9 a, f+ L7 _
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,- `" A( f8 d; K; m8 F/ T$ E
0x00, 0xFF); /* configure the clock for transmitter */, A4 B6 x5 P. H! v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& V/ [- A" ]- D9 C' sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 B( G/ l+ s4 U- S! e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% v2 P* G' E7 }+ e" ]0x00, 0xFF);
4 v- v# N$ \: \+ Z, w
" K S5 I( F8 r) k4 J( D+ ~/* Enable synchronization of RX and TX sections */ 9 B* x3 Z I% i# g ]8 X! h/ G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; |/ T) S) H0 @- dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) S; V" ^ Y6 Y$ V( ~5 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 L; L% R* v( z; {9 T& K
** Set the serializers, Currently only one serializer is set as% O/ f7 a1 c+ O& G0 T' Q
** transmitter and one serializer as receiver." C. a# V3 d, v2 }
*/
4 r1 I0 F" g. I5 E3 {! p3 wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; j# g1 a1 D3 H8 C: {) X" hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& `* O% I7 E8 ?8 y, P! X
** Configure the McASP pins
% u, w3 t2 o6 N- z' ]- t3 `" B** Input - Frame Sync, Clock and Serializer Rx
b0 F' U0 ]$ p: N( P Y** Output - Serializer Tx is connected to the input of the codec - ]$ s P+ [" K0 [# J2 X
*/: n* F9 X5 y: v# f
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( b/ b- k) N) a, s9 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 E! j! Y2 `6 s v% @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 s" {2 _' C5 F! D| MCASP_PIN_ACLKX" r0 F0 }: N, c9 Q! ?
| MCASP_PIN_AHCLKX" u( m4 S8 [: R' i- u% d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 r( z0 c& ? Q2 H# m1 N* N7 @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 O: d( ?+ P# J" D8 u ~1 Q| MCASP_TX_CLKFAIL
: {$ L9 @ p: z, \| MCASP_TX_SYNCERROR" ~3 ]3 ?4 n- e3 w0 N1 M8 T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + [% m W* j2 ~/ B
| MCASP_RX_CLKFAIL
1 w, V) ^8 T* d4 n2 w2 Q| MCASP_RX_SYNCERROR ! r) U+ N+ U/ L* M* Z; M4 s
| MCASP_RX_OVERRUN);! }( w3 x* _) p6 v
} static void I2SDataTxRxActivate(void)
& B H0 J* q8 b# G{
. r. I% c- e2 e: |( ]6 x1 c* y; N/* Start the clocks */
/ p* W: _: U6 dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! V L: {9 d0 d2 x5 @. g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 s. k- I, I' x( T6 {, {! o2 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 ]! T' p/ J, B; H5 LEDMA3_TRIG_MODE_EVENT);
' v9 Z; Y7 \6 q% B) vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, }) A8 q5 }0 ?9 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- {7 K+ B3 d7 [8 |McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); f% ~% M! X( d7 |+ ?& S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ P# Q1 Z. n; R/ w. m/ D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 a4 {1 e' M2 v3 c/ q+ p) pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; ] E g7 d9 p$ |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# f+ F! D& y3 S: }
}
; \& V' H7 H! @0 j5 u请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 [2 r" O2 B* U8 b w
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