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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 v0 c. ^# x+ b* ^
input mcasp_ahclkx,* N$ u- Q- T& V8 A
input mcasp_aclkx,4 D+ Y0 ~: [% Q2 r' R ^
input axr0,
6 K! n0 f" V; s: B3 X& Z
: X" \# c5 ?% G7 eoutput mcasp_afsr,+ a u2 V+ H7 W9 q5 \
output mcasp_ahclkr,
9 G) E# x2 `8 }6 L, Z. V* Youtput mcasp_aclkr,
( w0 G/ B5 c0 r3 goutput axr1,$ ]9 n# {5 m( e5 W) L
assign mcasp_afsr = mcasp_afsx;5 I) x3 b1 A0 p! Y+ ?- z! c. K
assign mcasp_aclkr = mcasp_aclkx;
% {" ^4 X" r a, I9 M# B8 Yassign mcasp_ahclkr = mcasp_ahclkx;8 _" ] w6 [. C* i2 M; C4 W+ c
assign axr1 = axr0;
, z/ Z; p/ j- i f$ w, {& Z+ P* U0 L! `& z K( N' q5 N" ~. L- M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / \$ \3 m( i9 a' E. ~
static void McASPI2SConfigure(void). u8 [$ z) m5 i7 q+ B! r. V6 @
{) m+ i' q3 x! O7 a. U. x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: \& W# v) X0 D7 D' e# P
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, T, H+ o& X1 W/ L8 c: z/ p% tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- O. q7 _- r+ B5 N' j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 S* Z) } ]; z& v \+ A) KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 U# D3 }9 y1 l- ]1 V Z: }8 c: S
MCASP_RX_MODE_DMA);' p9 A2 r) {, E x+ x. @4 n# x$ v$ O! t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 w: H1 j; d. C* nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) Y1 p/ ~( M V* |. r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 {+ h+ N) z5 i: I" I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% N; N7 j/ P1 p! J# D2 a
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 d( ^3 R1 R% @9 ^" Y: f& yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ Q$ O. y4 }) K% s- { fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. B4 L$ v6 `7 A5 N" H
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 Y" E" I5 f5 W2 y& \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. n% U. x0 K% |1 c n
0x00, 0xFF); /* configure the clock for transmitter */
8 @( T3 i- z- x" _4 FMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 V# U8 K1 J s7 a2 y+ W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 H; U. b* }3 e0 ^- w4 m: t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 F9 i# M5 b; e! w, K! w
0x00, 0xFF);/ ~, p& \3 Z+ X, B
9 k! Q1 u3 J' g- B
/* Enable synchronization of RX and TX sections */
) H+ I U0 l+ u# n# k4 Q. d7 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 ]2 f W2 a4 P4 z9 A0 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ a; G' J$ e" ?3 T0 k6 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 ~6 b7 ~* X6 I$ i
** Set the serializers, Currently only one serializer is set as+ ~" f# A7 V4 R P. b7 }3 I. v
** transmitter and one serializer as receiver.
* T. k7 R% t8 w5 n8 P*/9 b0 H3 F2 d) A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" t( f/ [8 }1 ~/ N! m6 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
; m3 u, T! Y R' \3 e0 l. b% H# U# E1 | D** Configure the McASP pins
) `( z4 d! F( p' ?5 Y7 p @7 l: n) k9 m** Input - Frame Sync, Clock and Serializer Rx
2 M5 c" r6 v/ K4 `! |4 b** Output - Serializer Tx is connected to the input of the codec
% ^+ U4 [) A# [: v5 y*/
: l2 J6 q5 d2 D1 }/ e4 ^: rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. }2 w/ T1 Z1 |% n) ?. G1 wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) n5 ], g0 p( \# k; }! w# |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- I3 u* e8 T0 |' w/ j: n% F| MCASP_PIN_ACLKX
$ _' n8 B& @: A' s% `| MCASP_PIN_AHCLKX4 D) c% M- B! @0 W/ {4 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: r" g3 |% |% Y+ p; w* T- j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& x0 e6 p3 y9 l3 Y| MCASP_TX_CLKFAIL " w# }6 h: x# }: r
| MCASP_TX_SYNCERROR
! y$ q. f1 J1 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 ]& j" O3 R* S: d. P
| MCASP_RX_CLKFAIL: m1 _+ J& {$ ]- `0 w
| MCASP_RX_SYNCERROR , l8 H/ q* F ]; e9 t( @
| MCASP_RX_OVERRUN);- f( \2 Z9 E, Y! V* r
} static void I2SDataTxRxActivate(void)! @! P" k5 P9 a. ~3 e
{/ x; n( q1 C1 o4 ^/ |, w, K% z
/* Start the clocks */$ i7 \$ @9 n+ C# e1 ?' J
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" [, X- `6 B+ ~, t, d3 J
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: E7 i/ O2 B6 e# K( A' \' r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( b3 f3 k- C* h2 y
EDMA3_TRIG_MODE_EVENT);! U& P" m0 [# J2 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 [7 Y2 M' V9 N u. w/ ^8 Z' ^; sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# G" p' t; h, U: B R# s+ p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 Z, S' G! \$ Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ s0 } y4 P2 N- ]" e' I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 B; q7 \% }, R) Z* a, pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. R+ h, e: ?) R$ J# L( e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 l+ e' E c' y# f/ [
}
0 f, Z G2 n9 d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 ~- E- ?( N; E2 `- Q
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