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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 S0 i0 C2 ]2 ^2 Y% M
input mcasp_ahclkx,
/ R8 b+ }7 R8 K* Y* _2 u3 oinput mcasp_aclkx,
9 S4 Y0 l" d* e! Dinput axr0,
8 D( S) a' `6 Y0 H' ^
2 j; e: c+ M# Y* poutput mcasp_afsr,
9 |0 J6 \' ^/ g, a% ^2 coutput mcasp_ahclkr,3 W: m! B/ U# C5 t
output mcasp_aclkr,
+ I% B4 }) F1 l& F0 @& ooutput axr1,
8 `# t+ @2 Q8 ^0 | assign mcasp_afsr = mcasp_afsx;+ g F7 y: ~0 }% ]5 N- p( n
assign mcasp_aclkr = mcasp_aclkx;
! o# t0 S3 p9 S8 A3 v# @8 p6 Fassign mcasp_ahclkr = mcasp_ahclkx;
, E+ W3 l* h" V( X" uassign axr1 = axr0;
5 |/ _+ w ^: P9 q6 u6 t$ j+ ^+ l* o6 X, D! A: e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 M$ `2 k! d5 V& O; cstatic void McASPI2SConfigure(void)9 A+ q! W+ D7 P
{
& p9 t& N# B. a) i/ S# V- ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);& e; |2 h# z7 \* u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ u$ H& @9 g( W2 e9 S0 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& d. l8 E& P& k; S7 m* F$ w" _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 L" g' N6 T1 P% n. c! L3 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( j: s* T6 V/ iMCASP_RX_MODE_DMA);
; x4 z A7 k- }5 i& ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ \0 ^& j) J$ Z' n1 T
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: f6 U) |- b+ I" U N; G* `) l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . I7 r) t1 r& {4 I, t9 K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 o+ w- w. }$ m% O% s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( E9 ]6 D1 J7 }, W5 H3 ?/ U5 @
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# w) C9 C+ g/ V- j- G& P" gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 W7 k7 N% z% I8 ?' ]6 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ q: K% d' t5 f+ F! @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! _ k5 j% }5 j- l6 E
0x00, 0xFF); /* configure the clock for transmitter */& ]0 G# \- Q( F' a. [# R I& u
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* Y7 |+ J$ K+ h- F" F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * s0 v) \2 E- O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
E: O2 k# u; `0 x+ l0x00, 0xFF);
1 _0 n0 ]9 c1 `
) m7 ]: F" o) D/* Enable synchronization of RX and TX sections */ 1 |. }9 ?3 W" |7 h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ `, ?4 {8 u. a9 u8 R% C* \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: S, F: L" m8 tMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 }7 u/ r: q4 L! T0 w
** Set the serializers, Currently only one serializer is set as
! u7 l# @9 m+ K& u** transmitter and one serializer as receiver.# X, a5 G/ e m
*/! {% _+ S+ v& G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); s3 E' q4 i( f- n) ?1 k9 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 r; ~: P0 J4 ]& U% L0 `** Configure the McASP pins
5 \6 ?* A L( j: s( ]4 H+ g/ ^) |- r3 n** Input - Frame Sync, Clock and Serializer Rx1 K0 Y! H+ m6 N* f9 m% q6 @
** Output - Serializer Tx is connected to the input of the codec , M5 j; J" Q2 [9 F. Y% B
*// [5 n. k0 F( ^1 {/ o* N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 |, \* S6 x- Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- I- n+ S& n- J1 X/ P9 f( |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 l) [' ^) y8 h5 m4 z9 q/ V| MCASP_PIN_ACLKX& P- `' N: n1 R" K
| MCASP_PIN_AHCLKX
9 n( e; S# ~ m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" A* j. o4 @ j- ]8 d R V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) {" l( k; U& [8 K| MCASP_TX_CLKFAIL
* M* _$ w6 t5 v, y: V5 A5 q4 g| MCASP_TX_SYNCERROR3 G" v+ \* |) X
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. [4 p+ h) t, p! h" H* ?| MCASP_RX_CLKFAIL+ u2 S! K: g( X" N5 a* h
| MCASP_RX_SYNCERROR ( l6 q% {6 R, r3 r' d
| MCASP_RX_OVERRUN);2 q8 H: l: Y( w, A6 U
} static void I2SDataTxRxActivate(void)
$ a7 d2 o, O8 C8 F{
' _9 ?6 Y& }9 l1 e8 H8 V/* Start the clocks */
' u1 C3 l( r1 v, pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 v5 |- E4 R$ ]. _, w9 T# N. R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, L$ t3 o2 ?; w1 \+ W9 U$ d+ `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,9 V8 f3 Z7 N0 {6 E
EDMA3_TRIG_MODE_EVENT);- F' R3 g# u- h& ]# D* l$ @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & N$ ~1 s; V% a' o
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 ]) m1 R1 T6 M2 O
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 ^. T' l( S% c9 @6 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' B: t8 o5 H+ m9 d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' W% r* j7 r3 S f! |1 H/ CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 b) g T: S, a9 ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ }0 E1 @: p8 }+ D}
& I/ v2 J; k+ L8 {/ [# @1 X5 f4 e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # m# _. z2 J0 e% @- ?2 l, y2 ?
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