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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" d! r, u% q6 q9 x# Qinput mcasp_ahclkx,( B; k% c3 A6 k4 ^) @
input mcasp_aclkx,
7 `7 C* M: x+ }input axr0,% ?; Z1 H, p# Q2 s2 y$ f
8 u3 U* |3 V* Zoutput mcasp_afsr,
( ~ V* N. S8 S0 q; \1 M5 L1 T( |output mcasp_ahclkr,
' h9 ~! q8 @. g* P$ h# [output mcasp_aclkr,4 l" `: i7 s" O
output axr1,
k$ U* M, E( x" X assign mcasp_afsr = mcasp_afsx;3 M) h+ [- x/ S& j
assign mcasp_aclkr = mcasp_aclkx;
0 i6 ~* N) B k/ d& |1 Sassign mcasp_ahclkr = mcasp_ahclkx;% k! e0 \- ^- Z8 X; Q: G
assign axr1 = axr0;
/ m& }" Y4 d* b5 _/ g; J5 G1 D* t9 g! D7 Q% z/ m3 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . Z, t8 g7 c4 o- i. |
static void McASPI2SConfigure(void)$ a' \; E2 N' \! m7 w
{
' t2 i; p& e6 r8 _2 jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);9 F4 {+ {* f/ R) e; \3 Q/ t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 k9 U( y. e7 H: o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 K" ]+ B4 X6 D* \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 @, }$ {- d K# @! C& R }/ S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" {7 s7 G1 ^# l1 R3 \3 {6 l: eMCASP_RX_MODE_DMA);7 j7 @- m; R9 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 v/ r7 s. k( a; N4 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 M( F8 E3 r& V5 M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( |( M8 @) F% ?- cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! C# E2 ^9 y. s- d( W6 ] XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & N( g q% @/ F( c5 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; s5 z( n& I( h# e- sMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; d9 R* P* ~% ]3 i/ R6 k6 Q6 ?
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: `2 t/ D4 f, K$ @( j9 b& Z5 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 U( C7 D4 w$ W0x00, 0xFF); /* configure the clock for transmitter */" E6 F7 G' Y! ^$ H. R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; n% M# I( Y+ P5 ?2 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . v0 D# ]" o' i- S4 o
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 s4 J9 B, d, T0x00, 0xFF);* c) j2 |' u+ w5 g6 Q7 y$ l( g9 s7 V
1 L) n* k# D$ `! \2 o/* Enable synchronization of RX and TX sections */ 0 R0 i% {- k% J6 C4 S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' B- V+ r& ]+ b" z0 o# @/ ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. H) ~0 a" S5 u- A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 b: G, i' S7 ]. X** Set the serializers, Currently only one serializer is set as
: h8 U$ G, v) N9 R% d0 [** transmitter and one serializer as receiver.$ q/ X: X0 P0 {2 Q. k
*/9 J r! f; g- {4 J, Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- i! j) E7 y& |3 W, Y4 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, @8 g$ k: \3 e** Configure the McASP pins
& [6 R ]6 ]! s! s' ^# X9 Y* Y+ s** Input - Frame Sync, Clock and Serializer Rx5 @, R5 s' W. o( j$ q- O7 i
** Output - Serializer Tx is connected to the input of the codec
! f+ ~1 N: I+ ^' @$ ]$ H4 e*/0 C( y: S/ Y7 I) A% T& P0 ^$ c- v
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: j* O) g0 i- \) ^1 O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); Z, t# d1 t' s+ A* o% v, q; @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 z& {* L! W) h$ W* q" H1 P, g! _
| MCASP_PIN_ACLKX$ V) i5 m, p; a3 A s' N2 i
| MCASP_PIN_AHCLKX
% @# T# H' t1 O4 I: e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 w2 L9 A) n( B+ K' G" `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + R4 F; u0 e2 N9 ?
| MCASP_TX_CLKFAIL 0 k# p Z$ l) V! F
| MCASP_TX_SYNCERROR* _2 l& B0 @, W5 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 f/ S: P9 H1 k
| MCASP_RX_CLKFAIL
2 c; u" b# V) `6 ^) C9 c| MCASP_RX_SYNCERROR , J( j) k1 b5 o, Q8 K
| MCASP_RX_OVERRUN);
' t! |: S; w7 U} static void I2SDataTxRxActivate(void)
$ {5 e H/ _+ P+ l- c# l{/ X3 C3 W* C$ @! a8 G7 e: M, N! k
/* Start the clocks */: i9 E9 l1 i M+ D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: x& i. ^/ _3 J' g |McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' ?7 a* n) ^: G& @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. g; h/ j* a, h% I+ D
EDMA3_TRIG_MODE_EVENT);
1 L' t& K- T$ V% CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " i, a+ M( x+ L- T/ |$ I: q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 E% e x% S) ~$ b2 k: @5 [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! P) {( P) K" Y" yMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 _3 ^6 f5 O8 ~3 t
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 B" d0 l# V6 [/ P3 q$ V0 S5 o, X/ mMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* f! G; t8 f3 E4 {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* n# Y5 c7 [4 D% M1 c& n: ?' W
}
9 c% M4 }" q) Q' ^" k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( X! f$ w6 ~9 k& ?0 n2 R% m
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