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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 X) ], x$ d8 B) M4 K- |input mcasp_ahclkx,
; w9 U4 c- i: @* n0 Tinput mcasp_aclkx,; P8 T! U. n. c1 B4 Q
input axr0,& B/ o: ]' T. T: F& o& h/ E1 q
2 C# n4 n9 p4 }3 _0 f% r1 n
output mcasp_afsr,
' _, ~: e. A- i3 _: }) t' x8 youtput mcasp_ahclkr,! p5 p* |; Y3 E; e
output mcasp_aclkr,
T3 _* W' {' c+ a! R& ~" Ioutput axr1,5 z% d, i" D7 s' I" ]# M
assign mcasp_afsr = mcasp_afsx;9 Y- F0 p; u3 Y8 e3 M( |
assign mcasp_aclkr = mcasp_aclkx;
' s# ]# R. y8 e6 H7 tassign mcasp_ahclkr = mcasp_ahclkx;
$ E7 @+ z; w- I2 }5 N7 \9 E( \) Jassign axr1 = axr0; & r. q. l. [5 x4 @( t
: e0 @, T H% A8 @) q- O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: g- C7 K0 T0 r7 y+ r/ ostatic void McASPI2SConfigure(void)
& ^- E9 s j& p3 V' }* ~4 |* {8 K{
, b) Y1 [ I, a7 a* E3 s9 VMcASPRxReset(SOC_MCASP_0_CTRL_REGS); N) ~" `1 R' e+ \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- O7 G, n& Z [: Q1 F: ^+ pMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- F! x; x2 d/ y' ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- M$ A& K$ V }: A% \$ gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 I; _ Z) N! D0 v% f* LMCASP_RX_MODE_DMA);
0 s! V2 F/ l& H0 _- H. [# E7 T0 A) jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 [+ ^- X3 K/ W0 n) a' m7 [4 dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, l. _! S! e2 {. {7 d6 @) ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' T% J3 U% M( b7 |/ ]# v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 R) T1 k, C; P/ w, |6 aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" r# y ~' g/ H7 P# t; L2 h: s1 k; i- FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 d* A% T5 l+ m. S' C# `0 ~6 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# M/ Y+ K( Y! GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 1 b# P& E# j I7 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ I* h6 x5 f) F! w9 C3 f+ _: U0x00, 0xFF); /* configure the clock for transmitter */$ v5 A. p" p; Q' `* k. s& ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ P) J4 B8 X& p3 Q- z9 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, u7 i$ p* d, X& O& t- r1 U6 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 ^+ }: s( p. I3 X
0x00, 0xFF);% E1 [! N$ r. {+ ~0 U% G
y# w9 h" ~9 u1 O# [2 E/* Enable synchronization of RX and TX sections */ 9 k! H* a) i5 w$ X5 v" h- ?9 `0 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 @# s/ U R7 N; a# Z. z. z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' R( B4 e" ]$ Y$ C) uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, \$ V5 _0 R0 X; O4 z7 a6 J** Set the serializers, Currently only one serializer is set as. |- Y9 }( s' U- ^1 o( |
** transmitter and one serializer as receiver.
7 v8 y1 s4 D- u P# j*/& o n* F2 e# z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ o2 l- v# x! ~% `1 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ i; }( I& k* G4 R1 f
** Configure the McASP pins ) W [5 d: |& V' S( A B( j0 y8 l
** Input - Frame Sync, Clock and Serializer Rx: a( R. H& a' } \5 O% m
** Output - Serializer Tx is connected to the input of the codec
" m! ~" M$ |5 G& b" ?*/7 o) R# y" ^% u* Y" c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* O" ^1 D1 u- FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, I" L! @8 |' U! p8 \ l; `/ F( J1 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 b& h8 i) ~4 i% b7 K; k7 J
| MCASP_PIN_ACLKX
& M/ J L6 k& n" z| MCASP_PIN_AHCLKX, c. z. e7 A( F% A) M6 m ]
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 E7 n b6 q: l7 ?) w# {; J& z
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( I, G4 H8 F9 Y( t| MCASP_TX_CLKFAIL
) W0 L6 k( U+ c8 y4 m( _| MCASP_TX_SYNCERROR
& o4 [# v, U: o4 ^; V| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, p( I, a% w, Z- I" C) X6 }- K| MCASP_RX_CLKFAIL/ ^0 i- c% M. @( b
| MCASP_RX_SYNCERROR
( i. I2 V' f4 H. L# ]| MCASP_RX_OVERRUN);
+ i, c, D! D3 q+ l+ F3 s} static void I2SDataTxRxActivate(void)
+ r3 R6 z. N+ R3 X+ T$ @* w{2 O9 I9 l8 z& {7 l3 M# c+ o
/* Start the clocks */* ^4 C! r' J7 V* N1 o
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 ^6 i4 [& m( T% J0 m( rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ x0 ?3 n+ A6 B, D$ z" u! l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 V e7 n8 l& x( d
EDMA3_TRIG_MODE_EVENT);' m3 ~: I9 |) A+ j! P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 L" _" s2 Z6 P) [" gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. c) Y4 M- @/ l7 A( t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 s" p$ [( s& i s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( {- A/ T: T/ ]+ b# u6 ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- L1 D. j0 N5 Y3 `& u% CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 E) y' p( r5 R( R, L7 ?& JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS); H5 S% g$ a: l5 q7 d; W8 N
}
1 E2 t% C3 y& g请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 @1 ]/ w3 X" S+ F( y! L0 p6 u
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