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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! D( a j- W" A, O& h
input mcasp_ahclkx,
. C% s3 O. l5 b, o2 m! `. c, zinput mcasp_aclkx,
, b4 `" ^$ q) d! i" Ainput axr0,
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output mcasp_afsr,
/ h; A5 ?6 C1 S9 t3 f# M, koutput mcasp_ahclkr,7 v1 i6 ~+ e% q: ~' t* z
output mcasp_aclkr,
8 Q- K3 G! b( ioutput axr1,
. n# ?& u& X- l assign mcasp_afsr = mcasp_afsx;
$ m6 Y A0 }/ w" O/ y: Jassign mcasp_aclkr = mcasp_aclkx;
q- N4 K% z3 jassign mcasp_ahclkr = mcasp_ahclkx;+ ]# b$ ?5 u, r; y1 a$ d* c
assign axr1 = axr0;
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: G9 V6 W2 \7 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - H( @2 m, S& s; n
static void McASPI2SConfigure(void): a9 Q+ v A: d+ i2 s$ M; \
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; U+ Z s: R+ ^" DMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ z4 e+ ?% i m$ VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; d% i5 _6 @; z; R' z/ YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; a8 n- N, N! C' R) _: [8 {" w2 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 B( B6 ^; D$ t; A# R
MCASP_RX_MODE_DMA);
. P0 x8 n9 W' H( R" u% V$ k6 tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ w8 c) Q, _; n& z3 f' F5 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 l1 b, r- P/ d% O: z6 h% M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& z6 ^9 o1 S* a$ ~# [0 sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# C! A4 j5 t$ J1 |! FMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' t; f# g m; T9 v8 l2 I+ kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: E+ R/ V9 P/ b4 e; P& ~* v0 ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% N" p% s9 t l* W# E3 X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* k1 Y# b( ^$ D! [$ Y$ z1 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 d- g& y+ U, a+ P' c% X, ?% O: N5 X0x00, 0xFF); /* configure the clock for transmitter */- i' S ?% Y1 R4 |3 x% ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
' b i6 c/ x8 }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ C8 o: B+ q% q1 H* f0 N( }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, r5 {! c2 t& @0 H, `) \
0x00, 0xFF);
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/* Enable synchronization of RX and TX sections */
! }0 ]# Z4 n$ W% V# ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 Q# j9 U5 B7 u. {' m8 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" n" g7 u0 L5 ]0 p* W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' Z6 ^( N6 l4 B1 |) o; S1 o
** Set the serializers, Currently only one serializer is set as( W2 X# w& R' _* B
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% X+ v6 U% X2 \' d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! F2 q' n: \ W( s; f
** Configure the McASP pins 3 @% I. m7 {, _. s3 e; J) p
** Input - Frame Sync, Clock and Serializer Rx
) ~; j! x: x1 u8 ?- X+ k. U** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 n3 s1 } F7 A/ L" c3 ~; B8 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 V/ \0 [0 h2 p4 v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% r C9 u& \3 P6 P| MCASP_PIN_ACLKX- T; K* l( T/ G1 a) f
| MCASP_PIN_AHCLKX
$ }0 H! H4 _5 e' ?' |6 W# C$ x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ C2 W, f2 O8 H5 h4 W& L* R9 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 J. O" m8 [; y% i' c4 E9 O( S" |& p/ h| MCASP_TX_CLKFAIL
- F+ X3 w7 f; f- T8 [& G. f6 f| MCASP_TX_SYNCERROR
" _$ t( S8 N# O1 G0 U* x2 T( `# n9 @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # m4 ?8 J) ^; k8 p( f
| MCASP_RX_CLKFAIL
& |- R3 e& R! X" L" G1 v0 C| MCASP_RX_SYNCERROR
- `7 k7 H2 X2 G| MCASP_RX_OVERRUN);7 b6 u# I7 x0 i6 [! D* K2 u
} static void I2SDataTxRxActivate(void); o' h$ y" X: o& u) ~) y6 a
{$ }& E# f w, U* B$ u8 y
/* Start the clocks */
$ `5 f1 |" f' a- A& p V7 TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 m) M! d" O B# I* `+ s7 _, v" s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 z; U7 [* W3 \4 m" d' u" z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 p5 @4 B+ d& n, F+ c8 z
EDMA3_TRIG_MODE_EVENT);
( u* R+ @$ F' r; {* WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . G# B" F. }7 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. g0 F/ Q$ p, Y y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 c6 j! H Z& F5 ^0 }% p3 w0 c7 k. _9 B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 Q' q) _ H* ]# r/ d0 `, E7 c/ E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. m+ b, B4 T" i1 G, |( m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 J7 R, C( P+ l& Q) N) [$ }, f8 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 ^$ w$ M% B! O! ~2 p# P5 k6 N5 m
} - Z, F) n! o* A6 U( t0 {& `5 M/ q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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