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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! f/ ?- B- _. ^' L+ @1 h+ Xinput mcasp_ahclkx, f. H, b$ z( s k! l
input mcasp_aclkx,# P. {9 v: E7 y* U* n0 l. w
input axr0,- c( V5 X. N/ \+ Y' E7 q4 s
; S. ^/ a _- O8 a# P8 k
output mcasp_afsr,: O6 M" L3 E+ S3 D% V" @2 Q, X; L
output mcasp_ahclkr,7 S4 _+ J# J/ R/ I7 F
output mcasp_aclkr,
* [* M% Y6 e# \- P B$ [output axr1,& v3 H- E) O% T. A, d( ^
assign mcasp_afsr = mcasp_afsx;
1 A3 N5 X- a( w* B! K" dassign mcasp_aclkr = mcasp_aclkx;# E/ M- L: N: a; w2 m
assign mcasp_ahclkr = mcasp_ahclkx;' X {- o9 ?2 T+ S9 x# N7 u4 e
assign axr1 = axr0;
3 x& ]7 }3 F1 X7 h d' `7 C) ~6 u' ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" A& c) l. G$ e4 ], N$ tstatic void McASPI2SConfigure(void)! n( Y" `0 Z) o/ y* S" ?
{' }5 b- c6 p; [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, x; x8 O0 n; C' r4 B+ tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 w) I, ~* S% S: DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); ^+ @: N. F% z0 J2 `8 p- a
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 u/ ?* S8 ]& x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! G2 D7 v) t! y1 m* L E# ~
MCASP_RX_MODE_DMA);
. G; Y4 q9 s5 y6 E$ Y3 e' qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ^" ^8 v9 ~ T+ BMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 {/ W9 P: o7 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + o1 p/ B9 @" S c* J$ z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 y2 u, y" `* R$ @/ ?4 d1 P, L4 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 R1 S- X4 k* b8 r& o1 m4 Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ y9 \5 P; r% [* v. K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ l+ U6 v, G5 n H( C7 ] C) ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 g2 g/ [% P h% |: P2 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 d1 [0 D; n/ `' u9 ]) d+ p
0x00, 0xFF); /* configure the clock for transmitter */
: Z7 @! o. X3 S8 W7 GMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 ?' r9 e9 @. U: v y8 s/ F( ^; P
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' b: S5 Y X# A/ Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 f1 u! X; |3 K Z$ ?; Y9 N& r s
0x00, 0xFF);
# n3 x$ j& h; Z- N6 Y/ ?
: \$ l' g6 ?* ?( Q/* Enable synchronization of RX and TX sections */ 1 q) B: z5 _0 ?/ S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 p- U+ ^ Q! X1 z0 r+ Z U# @# {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& y" l. j8 \" \' d/ L1 b5 t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 o- U" l! a: I0 ]
** Set the serializers, Currently only one serializer is set as
6 j+ e; b- ?$ [** transmitter and one serializer as receiver.8 E; x0 q5 U2 x! _
*/
4 s/ D" d( V9 M9 i: PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% K8 P. ~4 G5 XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 s% A9 p$ R+ D8 [* L7 L** Configure the McASP pins : b- A2 P% v4 k" |
** Input - Frame Sync, Clock and Serializer Rx2 _' j/ Y9 H; `7 M+ y5 w
** Output - Serializer Tx is connected to the input of the codec
) a0 H8 a9 A; m*/
9 F; |: O$ v5 O0 cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 B. [$ a( S' x/ i2 |McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 C y4 G1 H) E7 i- k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ Z0 y( Y- T+ z/ |5 [2 z, v| MCASP_PIN_ACLKX
9 z7 Q7 ]% M, H" s& l| MCASP_PIN_AHCLKX, T6 L0 g5 H+ G' r0 `6 E
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' O4 M' r/ k+ i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ j3 a7 [- T. G6 e7 _! J6 ~0 V
| MCASP_TX_CLKFAIL - h0 u' m G4 s! ^
| MCASP_TX_SYNCERROR- ^, \8 v( G6 ^# ~2 e8 K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 N6 R: Y5 P+ c9 M2 l3 A| MCASP_RX_CLKFAIL
. l% t* F: \& d. m/ U| MCASP_RX_SYNCERROR
6 U! \2 @7 n' a. S" Q% A| MCASP_RX_OVERRUN);1 i! x: o5 Q) N* y M
} static void I2SDataTxRxActivate(void) h6 G* P# G4 p
{2 m9 |- r2 B3 ~& E D
/* Start the clocks */2 h& P6 J% C6 x! Z5 S6 Q ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: {- V$ v0 X7 n: a* V! `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 n/ P/ p# {. Z. C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' g2 j! S* m8 U! ]0 m
EDMA3_TRIG_MODE_EVENT);4 p4 Q! J: Z4 x+ U3 ?8 j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 }: Z$ ?+ G' S- p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: g3 ^" Z0 K @( N. |. P( x* MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ p1 j5 d7 `$ A+ a" F0 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. O# S) y, E1 a) M, Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ p; Q% Y+ g3 m% S- m i( {1 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);. f1 ^- k; Q7 L/ M- V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 X, ?* Y% j7 a7 T+ Y) E/ B" C t: `} . _" I% R9 y- W9 o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' l4 \' [: A2 g& j, D% X& ^$ W
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