|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 Q6 [! x7 q; i! J2 Ainput mcasp_ahclkx,9 q$ S$ P5 U2 J: l0 W0 G5 c$ r
input mcasp_aclkx,
, G' w8 M+ W- i1 l1 }& Rinput axr0,1 ~" |& m; t2 T. g3 ^* T! s8 o0 h5 t
0 E- _& s+ \4 @+ n! ?) c% t
output mcasp_afsr,% ~! q* c" o/ G+ L
output mcasp_ahclkr, _. a/ O8 M# ^, j' |% T( b8 ^
output mcasp_aclkr,
7 c+ {6 i0 Y- @( }9 Foutput axr1," M7 H$ M' c3 o! G) @: Y5 ~2 M
assign mcasp_afsr = mcasp_afsx;1 n0 _0 l' x2 k) H. J
assign mcasp_aclkr = mcasp_aclkx;
) g* I y8 o8 P5 h3 kassign mcasp_ahclkr = mcasp_ahclkx;
! C9 h; R' Q; Nassign axr1 = axr0;
' I7 Y' K* H# w% v4 }2 h+ b4 `+ C4 P3 S- J9 Q# @$ W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 v" Z' I8 h ^; ?static void McASPI2SConfigure(void)" u9 }6 z2 D. E$ ^: g2 c' D
{6 j0 A0 r2 ~) O3 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 @( `0 |# y" z+ ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 R' g2 k( F f6 s0 ]) f; OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 Y Z7 y& I% U2 |9 `- z! _! S2 J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% d. D; u" |! o; E: D$ Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ {# n8 z8 Z" ^! s5 v
MCASP_RX_MODE_DMA);' g" i4 _1 X; G6 _1 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 E! b$ w4 C6 r) c' e( r* b* @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" @% {7 d4 O0 a% b8 R! A+ D+ _* uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " {8 s; ~2 Z# X0 ]1 B0 W' X& l# P
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ f. u- M3 d8 d& |2 i$ |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! O' U( Z' B9 `) H& i+ U5 W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& }2 k+ F& t7 h- |0 t+ Y: `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% l' P% E! _ \" WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ I. K# W, J) v* O8 | e: t8 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% `1 [) z% ?$ W. Q1 S, s
0x00, 0xFF); /* configure the clock for transmitter */
2 \: A6 D. l0 d2 {1 K5 TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ |6 o6 ?* e7 C: qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, e# {5 V) A) m8 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 j1 _* E, g3 i; Q5 ^. Q3 n* S
0x00, 0xFF);
, J5 N7 u6 t: |3 l8 G- S
( N$ K9 J' V! f3 ?2 }/* Enable synchronization of RX and TX sections */
) D" T: @2 j1 C6 ~McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& Q- P3 ^# [, f* D& Y# CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# ]; E) h7 ?3 j" F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* ?8 p y4 f0 c" I$ p** Set the serializers, Currently only one serializer is set as M# A2 ?& a3 w9 Q5 a
** transmitter and one serializer as receiver.. J0 z* v z0 B) n8 K/ C
*/
6 k# q) O) U' w% @) L; b( F. g6 DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! w: C/ ^1 _% Z% J# H; i4 U$ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" F9 c3 g1 s" F4 d6 p
** Configure the McASP pins
7 L( @: b+ ]! u** Input - Frame Sync, Clock and Serializer Rx
( [! P2 G' E6 G$ ]; a** Output - Serializer Tx is connected to the input of the codec
. M' g3 m# i9 I$ R$ W*/) c& J) k; _" J( W2 ?( J' N+ O% X+ q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! S; T& j" m, u' j5 F: xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( Y. U. i, L4 d
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 i% }, A8 z, o4 h| MCASP_PIN_ACLKX
2 ]/ R9 Z& B) Z* ^/ {& r| MCASP_PIN_AHCLKX
3 p1 {# b M a5 O x( ^4 U/ V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
G! \% O2 q& |( i0 y9 uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 R' K! J4 b7 N" V
| MCASP_TX_CLKFAIL - x* s" a" Q2 K, y3 @% J. k
| MCASP_TX_SYNCERROR
# Y) ]+ C% X. d$ J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . L! u6 V# Z( ^% G4 K0 C: _7 \
| MCASP_RX_CLKFAIL
3 g3 _; s7 L( K6 c7 Q0 S0 }: O| MCASP_RX_SYNCERROR
: v, C, k. D4 W0 N% [5 j4 r| MCASP_RX_OVERRUN);3 M Q) S( y; X# X" g9 `6 F+ q
} static void I2SDataTxRxActivate(void)1 C/ I; V! o z, L
{
: Y t% b( ?0 K) X/* Start the clocks */
7 D) u% ~6 a% h$ ?, h! \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" l; n" a/ \$ C7 i& ]( ~8 z' \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! ^: b" c2 r6 U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! v' d# b$ X1 q2 f# H# j M
EDMA3_TRIG_MODE_EVENT);
. c( f5 x- _3 D7 I& l1 |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 E' \7 e" \9 L: I' E: VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( _7 V+ _$ Q0 l: }, m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ ?# G) L% U- ^5 u* I) kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; ~ h( I$ T% R. `% M2 H( t; A6 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' g7 n ^8 t& {+ P" BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! _0 d9 q7 k: b0 x2 Y8 W% o+ f5 y3 \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ `% U) G4 N3 B/ e" G1 a}
* f" F( V. B- c, s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
4 \0 Z K( E3 w& [2 A4 C |