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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& M4 D" C* y+ j- s4 f& V6 Q1 Ginput mcasp_ahclkx,9 P2 a! `$ o5 M* Y
input mcasp_aclkx,
% U0 X# i' P+ a+ d0 z6 Y( v2 Hinput axr0,2 u# n% S9 R+ i" W: [9 K
' a" r% T, \. F" b$ b( o$ Ooutput mcasp_afsr,
( i- ^) S6 W3 k' \# X2 houtput mcasp_ahclkr,
, e' U. }1 K" u# n- h# coutput mcasp_aclkr,6 M4 u$ t( g% n$ m9 f
output axr1, I& `) P* P( C$ y6 \9 `! @4 ]/ ~: O
assign mcasp_afsr = mcasp_afsx;
" S0 b: f; H1 k$ c& M: V! fassign mcasp_aclkr = mcasp_aclkx;( m! n; L M- H. C4 P0 p
assign mcasp_ahclkr = mcasp_ahclkx;* r6 l7 s M3 H% V$ `* w
assign axr1 = axr0; $ u4 r, s% u' F) _! w
) r5 _: g* ~3 z/ a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, F. j9 r/ W$ F9 c5 Y" t0 Vstatic void McASPI2SConfigure(void)
( U" i& m$ x9 Z( D- b3 S7 ~{7 A# L: H6 U9 \" x+ `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 C/ ^- @( ]' M* m3 r: I# ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 a# j/ q& ]% r9 L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 }1 q. p; w- {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ W9 E- Y$ a4 Z) [7 X( U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. n, B( p. V3 _- U w+ ]7 } o0 `
MCASP_RX_MODE_DMA);8 w9 D/ | p% z" `% _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ w/ A5 c9 y* `5 D& j i' t; C+ cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 M! r7 Z' v/ Q' K7 `4 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ b* j' S2 k- e* U! Y f( V: u' bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: i$ E) C+ e t' t9 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! d# u0 c, Y3 z+ K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ O8 i. E( p" F& Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 q! F4 W6 ^9 Z; r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ K+ f! _3 z7 K, k/ \3 R4 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 b" V4 u2 M1 F# @/ _0x00, 0xFF); /* configure the clock for transmitter *// U8 P) R# ^1 A2 ~* P5 @: p# E- d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; b$ k. i, i( a J0 I+ ] N( VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) r' v+ C: O4 ?, W* ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! t$ J8 L B( Y' l) X
0x00, 0xFF);
. s X Z* \! E2 ?- c. \
3 `1 f* o6 S2 {# x! R& y+ c/* Enable synchronization of RX and TX sections */
9 T7 D, t3 Y$ M, P7 A7 m6 hMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// e0 n: o, p! E; T- M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& R0 r0 Q' V2 Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. B& V' W% b$ l4 C1 r7 X
** Set the serializers, Currently only one serializer is set as9 Z4 {- J. H/ e, p, W% I- h
** transmitter and one serializer as receiver.8 t' w1 C" t7 |
*/
3 A8 S: U/ u6 ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ ^7 o, X3 m3 J" C7 h! I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( q$ y9 b2 V* o6 m" w: Q X
** Configure the McASP pins
: ~# @9 C+ h) s- Y+ V! C** Input - Frame Sync, Clock and Serializer Rx
+ ?4 z4 P5 [2 M+ |** Output - Serializer Tx is connected to the input of the codec 7 P, a/ t& s) @) z9 H
*/% n& Q P: S! e s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. O4 n- l; ^! n1 V |. Q3 c; |4 Y- MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. s& V6 L4 t/ ?) W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 Q" l. t+ O5 b) W9 e: X
| MCASP_PIN_ACLKX
$ N+ ?1 P U. P! j, j2 m& b| MCASP_PIN_AHCLKX& W% y5 F5 @$ _6 `( t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, Q4 e5 Z2 o K$ O) g& T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 g/ `% O4 s1 R) |
| MCASP_TX_CLKFAIL " u7 w7 y" }. Z- L$ u' S
| MCASP_TX_SYNCERROR o5 `5 K! S7 o# _) E; Z! t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 V4 k8 ^2 _ o- K7 ^
| MCASP_RX_CLKFAIL
4 Q. T. q/ R7 y! H( B8 a; ]& H| MCASP_RX_SYNCERROR ; c2 k# \9 p- U8 e/ }9 ]
| MCASP_RX_OVERRUN);1 @6 I) W- j4 l* n. r
} static void I2SDataTxRxActivate(void)
/ u5 A) r0 D. z{) a1 }+ F. T5 u! y Z
/* Start the clocks */
8 @' }, q9 ^1 V6 B4 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! J o: o, t4 U2 A: U1 W/ YMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) v, f& j+ l- b: n9 j" gEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, B& p" {' z& F; f/ w
EDMA3_TRIG_MODE_EVENT);
$ z- X: L* @' \$ `9 l# [) K& jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, I* H, S. q+ T* R6 W* J0 G' Q# O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# \7 e _$ e9 L$ k4 l8 M7 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ S i; ], G6 H uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
S( Z5 R- K/ Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! j. \. W6 G5 m8 ]# @2 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! _$ a1 w1 e/ `* Y/ t$ l% QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);. V9 P" N7 |5 T
}
( D! C+ T5 A$ D: @! x+ b- K$ f" |! Q. O7 L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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