|
2 Y; i" i$ e% r+ d. W寄存器初始化那里就给出来了啊,如果DSP要发数据给FPGA, 那么CLOCK是由DSP去控制的,如果DSP要接收FPGA的数据,则CLOCK是由FPGA控制的,START跟ENABLE信号是用来控制发送使能的。这是我的初始化配置(我是用8位宽度通信的,对于DSP来说,B是发送,A是接收):! k' F: [, m" R0 e
static void UPPInit(void)
) E6 R) X1 c+ i7 s{+ O: e6 h) {5 |* h
unsigned int temp_reg = 0;
" `9 _8 T; y' ]
) |3 f- S* h- F* G( F // Channel B params) a& l8 f. S9 y2 R
CSL_FINST(temp_reg, UPP_UPCTL_DPFB, LJZF); //Left-justified, zero filled
) S# P2 ^9 `4 W7 j7 X CSL_FINST(temp_reg, UPP_UPCTL_IWB, 8BIT); //8-bit interface
2 p7 a: o) `; C$ m) z7 Z CSL_FINST(temp_reg, UPP_UPCTL_DPWB, FULL); //Channel B bit width = 83 b* V1 _* Y8 u T5 _9 ]
CSL_FINST(temp_reg, UPP_UPCTL_DRB, SINGLE); //Single data rate
, X1 D, S: w4 [5 u* O! |
6 g7 |/ f2 ~' d4 q // Channel A params a- X0 |- t% u& j
CSL_FINST(temp_reg, UPP_UPCTL_DPFA, LJZF); //Left-justified, zero filled5 V I% V8 ]* d
CSL_FINST(temp_reg, UPP_UPCTL_IWA, 8BIT); //8-bit interface
( s' G- ^7 x& {7 V+ u# ]+ k CSL_FINST(temp_reg, UPP_UPCTL_DPWA, FULL); //Channel A bit width = 85 e& {0 e: L7 R0 i" J. B7 @
CSL_FINST(temp_reg, UPP_UPCTL_DRA, SINGLE); //Single data rate
/ c$ z4 ]) l8 h, w3 F9 V) v0 ?" h; G* S$ n; U1 b) ]
CSL_FINST(temp_reg, UPP_UPCTL_CHN, TWO); //Channel A and Channel B are both active.: }9 t" i/ r+ J* j3 u
CSL_FINST(temp_reg, UPP_UPCTL_MODE, DUPLEX0); //Channel B transmit Channel A receive
9 }2 _! F5 w: z# T" i Q
4 o% r, g5 K! f% A4 q upp_reg_hdl->UPCTL = temp_reg;
) b. {6 H: ?+ w4 F+ u% z: H1 C
1 S+ F9 k; H. H& j, |! y* K8 |& O. O temp_reg = 0;
' N3 d) G6 p4 A* e% k) M" [9 C4 m& S% ? C- o$ A* ` \2 P& x
// Channel A params3 {4 Y1 W: H3 H% [5 ?9 a
//CSL_FINST(temp_reg, UPP_UPICR_TRISA, ENABLE); //Channel A data pins are in a high-impedance state while idle
- b" m. N/ Z9 r, j2 M( b //CSL_FINS(temp_reg, UPP_UPICR_CLKDIVA, UPP_CLOCK_DIV); //Clock divisor
! G: d" Y( ~3 B CSL_FINST(temp_reg, UPP_UPICR_STARTA, ENABLE); //Channel A START Signal Enable.
5 c4 N: A1 t( P0 |4 Z CSL_FINST(temp_reg, UPP_UPICR_ENAA, ENABLE); //Channel A ENABLE Signal Enable8 S3 _) M P7 S
* b1 E. E& J% Z- F
// Channel B params
+ I: e. d4 ?8 e1 u. Z* d0 x CSL_FINS(temp_reg, UPP_UPICR_CLKDIVB, UPP_CLOCK_DIV);
+ f0 Q( M q0 ]0 o a1 }1 W: O CSL_FINST(temp_reg, UPP_UPICR_STARTB, ENABLE); //Channel B START Signal Enable.. a/ t/ A- h; \8 r
CSL_FINST(temp_reg, UPP_UPICR_ENAB, ENABLE); //Channel B ENABLE Signal Enable
: y; [& I2 q$ G3 J0 ^1 @" Z; L3 ~0 T0 j1 [$ W. Q/ P
upp_reg_hdl->UPICR = temp_reg;) N1 h+ r+ m/ z! W
3 K' u, W0 c$ D( ^) I& U
//temp_reg = 0;
& e, l6 P; Z' a+ J# c7 @8 ?# A; a
4 l: F& }; b: g4 j( d2 @# Q //CSL_FINS(temp_reg, UPP_UPIVR_VALB, 0x7b7b); //Channel B idle value# C e8 ^& i4 S3 r0 c
//CSL_FINS(temp_reg, UPP_UPIVR_VALA, 0x7f7f); //Channel A idle value
) q6 x1 ]; `! \* A1 R: i
3 g+ V) I& h' g+ A1 A0 n1 Q //upp_reg_hdl->UPIVR = temp_reg;( V/ J+ Y9 Q# m
9 {; ?, T) Y' @" g4 K //temp_reg = 0;
# \% T8 b" P, [5 }+ X, K; U" E
, a" \5 V ?7 k$ E! ^( D //CSL_FINST(temp_reg, UPP_UPTCR_RDSIZEI, 256B); //set 256B DMA I
! V* r2 e- W6 m: l //upp_reg_hdl->UPTCR = temp_reg;, g) T1 F, a9 w$ I9 o E& X
2 f: ^! C& o4 ]) ?4 c, t
//temp_reg = 0;- M4 @- _4 Q: A: ?, \+ F$ q9 {5 d
//CSL_FINST(temp_reg, UPP_UPDLB_BA, ENABLE); //B to A loopback mode enable4 P; ]6 d0 `; @0 M
//upp_reg_hdl->UPDLB = temp_reg;& ]3 _/ R# T8 t1 U- l% y9 _8 U
7 ^8 b7 O. F3 m' H; I# Z5 f} |
|