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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% e- ]" K- x! }; {5 b' [ ~input mcasp_ahclkx,
$ S9 D# Z$ L3 l3 H5 U- U+ @: c/ ^input mcasp_aclkx,$ t" j8 D1 e/ @7 t- O
input axr0,
5 j n% v( P S$ _6 v
' D x2 p6 f' D/ p! r1 @, aoutput mcasp_afsr,) K- ~0 x7 r1 W* Z1 w3 {
output mcasp_ahclkr,
, s& x. _, R. W" p3 _& [output mcasp_aclkr,
/ Q) q9 ~% R7 m; |output axr1,
7 a2 |" i7 P$ G! d p. Q5 i% L assign mcasp_afsr = mcasp_afsx;) ~3 W {# P4 Z, ?+ V# [
assign mcasp_aclkr = mcasp_aclkx;$ j3 r: _( o/ P# A& n
assign mcasp_ahclkr = mcasp_ahclkx;
+ o* J8 w9 p7 T" Y+ L: E# tassign axr1 = axr0; $ F8 h# R* Z+ Q- Z* g- x! n
9 f3 f. ~* ]; H2 ~6 g6 X$ G( n3 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & n* S4 z" w2 G+ D+ X- s9 h7 {: g
static void McASPI2SConfigure(void)
! V( z C/ y, p1 \9 E5 u{) E0 n. k4 q, b9 x/ q6 F
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 r% H' r, I$ p# J [) uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" ~7 b4 P& _. p! Y3 P9 D
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 i/ k- ]8 G8 |2 \( V" j2 Y4 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* v' `, G( D0 C* J: a, v- p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ~7 R3 @" m- Q9 HMCASP_RX_MODE_DMA);
3 K1 p0 ^& O- ^) M3 J& [McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* r G: ^( M# P" e% a) \& YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 Y4 A2 L- c& `) k$ E$ x+ ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . F2 p1 V4 k9 E( \' V4 e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE); f1 V; a0 E% P* D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: g& f/ i+ Q, u, Z! q' v' vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- z, f8 o' M5 B- a: A H2 w8 E
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" r; K3 c9 a. M) f6 r" n9 F$ A# T
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! M1 J; B2 c k- k7 L, G& o, @
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) w' c# M6 a4 y& a4 ^0x00, 0xFF); /* configure the clock for transmitter */
$ Y3 _* e) v" t( ?5 [- VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# \" i; [- m4 eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 {1 e- \' g0 J* y( }$ i+ EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- i( h( B* p: k- m. t8 K& P- R
0x00, 0xFF);- k+ S+ n7 B" `; V& v* |
+ b5 k0 k! C+ P0 U/* Enable synchronization of RX and TX sections */
- j) D' z6 T# {: h" b5 [( K1 e) ^# S9 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 E, N9 l2 s B; D( W# }McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 z( B. l# P: j5 L3 a1 YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( H0 Z- R& o \2 y6 N6 H% }
** Set the serializers, Currently only one serializer is set as
6 ?4 c& H2 m& {; s: o" ?; W** transmitter and one serializer as receiver.
9 l4 c! j' m' D+ g*/8 Z' O$ Y `9 P( r' h( S+ X" X$ G
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ G" m# N4 u4 Q% H. @: `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# Y2 I$ H0 Z6 k' C3 u! m
** Configure the McASP pins
2 I- _- T2 `! P8 v** Input - Frame Sync, Clock and Serializer Rx% R7 k6 T! O& a
** Output - Serializer Tx is connected to the input of the codec - A3 z( Q7 A" @3 h8 @
*/
Y& A" H( q8 r! ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 o( W: ]) m, X8 h) Q1 x% x
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ E2 B1 N5 D) ]2 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 Y$ G; F S8 |1 u: ~. c$ ^
| MCASP_PIN_ACLKX
+ K. q; L& |5 Q| MCASP_PIN_AHCLKX
6 j8 q3 g. P; M7 G9 Z2 o- Z2 E7 b| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 [5 S3 `- n, k0 c& S# X _
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 `' c2 }* m8 [- F/ H& t
| MCASP_TX_CLKFAIL 0 W* j' n( ?7 k
| MCASP_TX_SYNCERROR
, \" s7 r Y( h, G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ P) \( r e4 |( o' s: |- E' B| MCASP_RX_CLKFAIL( d8 V* J& `; u
| MCASP_RX_SYNCERROR
. z) |. p1 z' K8 M| MCASP_RX_OVERRUN);1 ?4 P% [) I9 N% p& m; ?
} static void I2SDataTxRxActivate(void)
% a5 T! x0 ]2 Z! p{' n- P2 `5 B! m6 B6 u# K5 [) E
/* Start the clocks */
( {# d( H, g. pMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 e6 H4 l: J8 G) F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ r, T0 g I9 s* d7 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 y0 O1 Z0 P/ V! k& C. ~- E6 K# H0 C$ Z
EDMA3_TRIG_MODE_EVENT);! s" P8 E- @" z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ Z" G6 o2 b# G9 S2 F& Y nEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% p3 _; H" x% y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" F! X+ @( R' W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% X' s- `1 `2 ~7 N8 S$ _while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# E, N- W5 ]: {. ~7 K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); \ I- C( W1 F( O" ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); O7 G( V& T9 k" |. o4 P
} 0 U5 k) U6 c& v( w1 T [
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # {* ]1 |: B( r% w6 [
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