MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% l2 ~7 R3 M4 O9 k6 f3 f0 Iinput mcasp_ahclkx,
input mcasp_aclkx,
. K2 e) s5 T$ f& _! _9 Sinput axr0,
1 k" e7 y( Y/ A
output mcasp_afsr,
/ W' P* ?$ ~' Foutput mcasp_ahclkr,
3 i; _+ H  W7 A( |: Xoutput mcasp_aclkr,
output axr1,
% i3 U- N9 r; @, |6 e& z

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
( H: w. ^( O! u! t' g7 \: [assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

1 T2 d, f! [6 X$ o
4 M9 j* S# R! f. T, W. i

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
{
' R; z4 Z' q0 f6 e4 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. x4 l3 @/ r# L4 ?. HMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
+ P8 h/ n$ I2 j) }- S4 AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
  P. j  Z8 ]1 _- A8 l7 v  ]( T$ NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 k% m5 j4 u" ?, m" j# @0 [MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ o+ o, s( ~/ d) K+ `; a2 y- cMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
6 W0 r  B! g! f, hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: }" N1 A6 W! y0 F( E7 `$ V& `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 D* m% ~9 a- v  @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) |( Z' R% N! N9 T$ g) G0x00, 0xFF);

/* configure the clock for transmitter */
  w. W6 f' \& _* u& f9 b: [+ v2 V: PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* {; l4 b7 E9 l+ J/ M0 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, d+ ~) f* n" KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* L4 E, X- Q7 z0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
. \  o8 d5 L' z9 M1 I9 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
% J4 j) `* l: s! e, |: u$ u( CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& e6 _1 |' S& V9 ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
3 [- O3 c; S# p" |# S** Set the serializers, Currently only one serializer is set as
# _5 K. Y- K/ Z. g3 U4 |7 k+ J+ X** transmitter and one serializer as receiver.
*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
7 p/ @0 `+ K7 N( ]** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
" O% G% K* O1 q& e7 T5 k7 oMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, ^- _+ w6 z6 L6 P' _McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* M3 E3 o& ~% R4 T7 i1 K| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
& ^7 H( T0 \. \. b8 p| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
0 O/ G- O0 o; s2 G2 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
( S3 `: {2 h9 z" {( w/ _| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
6 G! s) ]) h. }6 d- \| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
6 t) Q$ ?( ^8 u. {}

static void I2SDataTxRxActivate(void)
{
6 c9 X4 h/ d/ h: }# k/ u# e* y/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( @  R7 a' G! y- k7 R& B2 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 ]9 m- d, l8 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
) ]7 W! ~, W/ iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
' v; o5 C% K9 [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 {5 e+ i/ [1 C% I+ [- k& f}

& g% I( M& R( s7 B7 X

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.