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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- A3 H) \9 |3 }7 q( g% ?
input mcasp_ahclkx,
4 w; S6 O) w% Oinput mcasp_aclkx,
6 `5 n4 s1 f$ |/ n* }1 L' [3 jinput axr0,& J3 F6 t5 L$ o# X4 Z/ R
& C e! M$ E& t6 P5 ^' c
output mcasp_afsr,
7 `) ?( @% V0 m5 {2 Eoutput mcasp_ahclkr,
7 U9 @; Z) O8 `* Y- foutput mcasp_aclkr,
+ N$ J! f" B! a" X9 E9 E4 z/ r/ Coutput axr1,
2 Y: b0 N$ [# M3 {( y# T& ~: T assign mcasp_afsr = mcasp_afsx;
+ N- e2 b3 h6 m/ k3 H2 [# massign mcasp_aclkr = mcasp_aclkx;- B$ c* R; L3 K8 W9 o$ f
assign mcasp_ahclkr = mcasp_ahclkx;- f- _: f1 }. T: N; I
assign axr1 = axr0;
' X( m, z( S* C8 X' }
( h6 {- F( a* A: d6 t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ ~; u7 E: ~) k9 |) Rstatic void McASPI2SConfigure(void)/ U- ` z$ A8 I/ a& w3 _6 N
{. b! t8 z* g) r2 n1 K/ `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 @( a% g& Q c' f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# \7 N# O' v/ Z# HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ Z- H, x4 e0 P9 ~; f; X- m# gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
A/ _3 i$ o7 Q% ~" F9 Q3 ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; C, K+ p$ x. x- v5 {' t# t
MCASP_RX_MODE_DMA);% |: w3 b1 B7 b, R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( E) w! n- y8 [5 W- O
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 G! P! J2 t' Q7 N& g0 T+ vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* N5 z3 b$ h! a+ S% a* ?% ~$ ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 p" k- I" q2 ]6 @+ |0 @4 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 i" K# v# E6 i/ SMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 g1 p/ z& n. ~. |- ^% g# u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- r: m0 @) r/ z4 I" K% o% Y# wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 d- I0 Y+ J2 ?! y; {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 n6 W$ H, i& k4 l8 |1 f0x00, 0xFF); /* configure the clock for transmitter */3 F5 R+ O5 m, y; C" c! r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ d; e" [( z! Z. L+ y' g6 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( g7 Z( u! v" B: u* u) q" @$ I" Z$ _7 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' j- Q' S8 v9 M9 t- n6 Y0x00, 0xFF);- x3 y% j: j2 t9 p0 a
, W3 D& k( N3 Y! ~3 z; u7 X
/* Enable synchronization of RX and TX sections */
5 k6 R0 S- Q) F) BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 i) ?! v/ G# a' P* W1 i9 z2 kMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 B9 N O$ ^# @2 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- }- T4 w& c2 {, `* [; h** Set the serializers, Currently only one serializer is set as" k( ?2 v. J( }4 f3 k q7 {
** transmitter and one serializer as receiver.
9 P" {7 b$ P0 K*/
5 V8 Y: A( ~! c4 c5 VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 s, j" B- a. z0 `- H0 p# Z0 w9 \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 f6 s; c9 }9 K5 O2 K
** Configure the McASP pins
5 i- A, y9 \$ v4 b' T** Input - Frame Sync, Clock and Serializer Rx" @6 r8 d [* d5 e, n
** Output - Serializer Tx is connected to the input of the codec & ~. F, F( } s* @
*/0 i x/ h7 c: J0 ~2 {0 v8 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( @1 }( _+ U& k3 m" W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 E: {4 ^* Y+ X( Y4 K4 Q1 c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. S' F9 v+ z, t4 u2 B% P
| MCASP_PIN_ACLKX8 m% @5 M: {' o
| MCASP_PIN_AHCLKX
- \- Q N6 T( O$ U' D p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 G3 O; H2 o+ _$ |3 g6 {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% P# n5 |2 i D# ?) q$ J| MCASP_TX_CLKFAIL & O0 ?' ^# N/ I, E% S- w
| MCASP_TX_SYNCERROR8 C: Q2 P; ]4 v4 v& T1 S( n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
# x+ s" Q$ A/ T9 X| MCASP_RX_CLKFAIL4 y& w+ N a! }9 S0 g/ A6 g
| MCASP_RX_SYNCERROR
7 G6 a) v+ J) Y" p' \$ J2 x7 X) P| MCASP_RX_OVERRUN);: I/ ^' w% X# }( s9 b3 y# U3 `
} static void I2SDataTxRxActivate(void)
* f& _; ]: M' G. h7 _{
, O! d+ s- R1 |7 u7 d6 d% q/* Start the clocks */: b$ X9 K* A9 \# L) ~ F
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
Z# }' k+ X2 ]$ A/ d. ?. S" vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 x) S0 G# U, g5 h! U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 ?- A' l( }! m- w/ e0 qEDMA3_TRIG_MODE_EVENT);
: m7 [% D, g* s- ~3 l) MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : `: X3 E6 d9 ?0 g; N% i8 N/ O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" X3 k0 ~2 _. t6 J
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ ? ^0 c- n2 i* H: W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) G- J- h8 V) x' P! \
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: X1 v2 B: }( W) K* w( VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' u7 o. {, | U+ OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ u7 W0 o3 x. B- G- K}
3 s9 j2 u3 s# \# T( y) h6 L! o0 O, O请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 m9 O: V, g; S% D0 g, g# O
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