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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) J! S2 R' F/ _9 n) Jinput mcasp_ahclkx,
7 `+ o- A5 j: m: V4 J* P G4 h `% ^input mcasp_aclkx,
0 H) I( C; [+ {' F, _; Uinput axr0,
- }! z4 |5 e5 Q& W. J
; p ?, h# D+ V* T9 {" s6 T+ Routput mcasp_afsr,
+ A0 m8 N8 V& xoutput mcasp_ahclkr,
0 c, v5 D e5 @6 e6 f3 V! B3 Youtput mcasp_aclkr,* j" N9 q8 Q6 R& N, a" R3 p
output axr1,8 S4 S( V; s2 k8 b0 f6 U u8 x
assign mcasp_afsr = mcasp_afsx;6 F: M' z- M* i8 t9 r: p' @* y
assign mcasp_aclkr = mcasp_aclkx;4 r: U; Y7 G$ h6 }
assign mcasp_ahclkr = mcasp_ahclkx;4 ]+ ^* ^, H1 O' C
assign axr1 = axr0; 7 H# d3 E' b# A) l# }9 p$ o
% s' Q8 m$ Z. ~2 r2 e1 b- F7 f: K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ` l. X# [& U9 M
static void McASPI2SConfigure(void)
( b' ~* S3 Z. b' ?$ R. m{8 P- `5 G" ] f* @$ h7 i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; c1 a; ^8 X2 c! p4 r6 k3 z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 s0 m3 t! E/ [+ \) q5 U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 }8 d7 {" ~' R: l7 t( Z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! f# l# ^3 B' ^+ |5 fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 s0 Q& V! H! A' `9 J N$ c3 XMCASP_RX_MODE_DMA);
3 w( ^4 N+ H9 h! H! GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; N8 a% H" ]# Q1 b0 W* B! oMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- D" s6 g& U1 b% [/ p8 n1 D9 J" |
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' A0 B. z* ]4 E6 K
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 Q+ A. Y, P; U: {; wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " U: O; f. W) y/ X- ?8 y5 e' `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! r2 g/ Q( G5 s% M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! N" U9 q1 r5 m9 W: N# l0 X/ BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, c0 S- u; O9 H7 U! |/ K; t0 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. H* W; ?5 D0 o2 n; V" \0x00, 0xFF); /* configure the clock for transmitter */1 W+ X" ^/ }- Y& G. e1 S9 ?2 U8 O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 z5 c3 h# G1 [0 J. n3 W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- S( [2 W# J! Q; C4 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 v. k; Y- B1 `2 r0 z- m9 o
0x00, 0xFF);+ w" f8 u, X% Z% i; c
+ d& a; I/ Z, Z2 c5 `# R/* Enable synchronization of RX and TX sections */ 9 D$ A9 Y- w P3 F8 _$ I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 X% Q' ^( t: ^6 D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ @! |& e/ V- b4 v$ \- r6 s4 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& x3 X' d! c- |4 k$ s2 G( C
** Set the serializers, Currently only one serializer is set as
* v$ O* D8 u9 i) s9 `6 a5 S* R+ q% o# r** transmitter and one serializer as receiver.! W2 b6 z6 Y8 n. ~4 d: n
*/
. D9 O. } A* `- P5 U& i9 _McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; T4 i8 T- p7 d1 Z: R" `; D) w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. B( F+ ~8 ^" L' K3 H** Configure the McASP pins
# C- Z7 k2 | M3 W8 |/ s** Input - Frame Sync, Clock and Serializer Rx
* ?4 U3 J# U/ M3 G3 B2 U$ T** Output - Serializer Tx is connected to the input of the codec
! G7 O7 M1 T6 A3 r6 l*/# i: u; A3 I1 `' R# |3 g3 s
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. i: {* W# p) K0 }6 K1 cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 x6 Z$ \5 p+ X! s2 r6 r4 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% {( X: S2 U8 n# u& z4 Y% Q| MCASP_PIN_ACLKX ?; k3 v' e6 X4 G2 s
| MCASP_PIN_AHCLKX
: `0 r) l" p. l3 W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 L, T+ {4 s) I( @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ i) W' ?, @) Y! p! `
| MCASP_TX_CLKFAIL
; ~4 {# S' w: ]| MCASP_TX_SYNCERROR
8 F+ C0 R, i; i1 m4 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! V& N. b1 m3 a/ k& b' M| MCASP_RX_CLKFAIL% ?! O* X& N7 I
| MCASP_RX_SYNCERROR 5 b1 |* J8 E# Q* N
| MCASP_RX_OVERRUN);8 @( N" Z" [& P( ~% D
} static void I2SDataTxRxActivate(void)9 ?+ c0 U# E# `6 y
{
2 P! |' C! }" ^6 v/* Start the clocks */+ B l, H; N- i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: W' z3 h; w M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ }& M0 I# p6 ]/ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. f3 j0 @ T3 E J1 J# t3 U0 |
EDMA3_TRIG_MODE_EVENT);
: [0 W7 _* [: }. Z+ P6 S) bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : H) A& f6 a4 p5 ]$ s9 W) p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 \+ l/ }( b% g! n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- r( `4 N' S4 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 k U1 d; c/ a* J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: Z, }& Z+ h4 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS); B; K, X, L* W2 e5 D
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; J# L( @# _" ? A5 S) a! w; ~
} # E* d6 a0 v# a! D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 f1 s9 f. r, Q6 n1 A0 Z6 B) o
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