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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 B8 |3 u6 I2 F0 @/ `
input mcasp_ahclkx,+ j0 L0 {$ z& ~ ]
input mcasp_aclkx,' }% G* M7 N- u! H' o
input axr0,
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output mcasp_afsr,
. e7 a2 q+ `4 v0 o$ K# l6 goutput mcasp_ahclkr,
; X0 M: A: R3 r T7 _2 [output mcasp_aclkr,1 m; Q' [! `: H
output axr1,% u! ?, Y+ z/ M @+ O. A
assign mcasp_afsr = mcasp_afsx;. z7 p$ k5 e1 J/ T; p/ T$ T
assign mcasp_aclkr = mcasp_aclkx;
/ j8 i( v. Q' L- gassign mcasp_ahclkr = mcasp_ahclkx;
7 f/ M' t" q* L$ X2 _$ lassign axr1 = axr0; : E7 ^( F3 G- r; @" O7 N/ ]; F% l
d$ L$ a) {! s: }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" H2 v, S T$ Kstatic void McASPI2SConfigure(void)
) ~4 `* C5 B7 I2 o+ x{+ X9 P% U) m$ E: v& J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 i3 U1 V0 w2 H& FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. v/ x0 j* H! w0 d" |* f6 o" b
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 V/ m- O# q" p2 v1 R, l7 o( SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: k$ ~0 l0 J0 r" P8 S, |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ J, r- v% _/ c7 JMCASP_RX_MODE_DMA);
/ [8 d" k/ v+ N, i5 K$ Y0 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ X* w$ n! e, i% u# A* h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& a* s$ K( M/ G q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " W% A0 d3 u5 ^
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) z% u; h/ i. L V6 F# E1 R A: pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) W$ x, H L ]& [. U4 s/ CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& q5 O! Y% y9 e( f" WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, f5 H: D5 F9 Z, H) x$ e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" `, {7 [" M, N. i' }' F) iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- Y& v3 B5 o9 B5 ?# ~0 o4 |# c2 v) Q0x00, 0xFF); /* configure the clock for transmitter */* K8 z, A8 _" m( g; {& r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" d. m& h+ _, G1 H/ w6 Z
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( e0 o2 N/ M% D4 Q* w9 i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! {' d! F1 h. A* ]. ]/ C4 x5 K1 \4 ^
0x00, 0xFF);
& l- Q+ ~# H( _" }
$ o: P0 h9 h K/ X3 \9 j! ~8 E/* Enable synchronization of RX and TX sections */ ; i% t, W5 N* r0 H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" Y9 a/ b' T, Q* U! H# F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ G1 ^3 J! I3 k2 L: n6 \$ a" \1 g7 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
( h9 F6 x4 v# e. z6 N, T** Set the serializers, Currently only one serializer is set as2 z, s$ ]; k0 _; R/ l" e5 |% S
** transmitter and one serializer as receiver.
! f: E1 `8 X5 f& B* {% z*/
9 \% M! ^/ x/ R4 s6 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 a0 ^$ _0 }# p3 ~4 @/ rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ J4 _! j& T/ G' w3 a** Configure the McASP pins
7 |7 t$ {. c) h& h** Input - Frame Sync, Clock and Serializer Rx8 `, T8 Q5 V C4 ^ ]% [
** Output - Serializer Tx is connected to the input of the codec ) g% i5 P$ j, w+ W* @4 L# P
*/
+ r( U/ b8 b% J- _1 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 B" n( W0 b. l6 A) I
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! S$ T, q. T4 c6 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ |# b4 }. {, {* Z
| MCASP_PIN_ACLKX
# K7 t( w( B( B- h- S5 t, J; [; [| MCASP_PIN_AHCLKX
( S3 h3 n# A* `9 V| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* K9 F7 R, e- F9 a9 YMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; b1 G' O A; }0 W( R| MCASP_TX_CLKFAIL . t. r# u+ R3 J2 Z- Y. r, p
| MCASP_TX_SYNCERROR, x8 a# Q& ^" W+ W7 s2 [1 B
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, X% s3 `) }( v3 u| MCASP_RX_CLKFAIL% b" y; d6 e$ W* X' R7 A
| MCASP_RX_SYNCERROR % L% @+ ~+ c5 w9 B* N6 Z
| MCASP_RX_OVERRUN);5 g4 h6 t+ _1 s* v# ^
} static void I2SDataTxRxActivate(void)
# r; u: \' r/ @' l/ d{
% {7 v% D! b6 f/ ~/* Start the clocks */
% A% ~- q7 W* wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 d7 } u( a& Y! |5 PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ ]2 e+ a' d7 k$ O3 U7 A# b9 t0 K1 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* q1 b% X _' q4 i6 h2 b. O
EDMA3_TRIG_MODE_EVENT);7 {2 S, U! O4 V- S2 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 k! \" X( W. l$ z* e$ g+ c, B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& y* }! M, H, X* q7 Q6 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; z) [7 ^! p& M1 e( PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) \5 ?+ a8 `1 b8 d. }- }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, c$ D( {6 ?6 L) \% C2 L2 I- p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" P9 A: B0 n0 b* J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ y& p& m9 g% E: j& n}
! h: E' Z3 E7 f/ A# M请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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