MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
7 l* x5 d8 A8 u9 v$ A; A! ginput mcasp_ahclkx,
2 y" t! A6 ^# V% Y% U7 Vinput mcasp_aclkx,
% n* u, |1 e" g& @1 z7 [9 C1 b7 f& ]input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
+ `7 M. e3 |8 a/ moutput mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
+ e' B# l$ X; L, R3 V9 R3 v% S" }assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

! j1 e0 i  Q- i
& F8 U/ B* C: y3 ^$ x2 m" ]

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

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static void McASPI2SConfigure(void)
{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: S4 G6 z; i+ S5 \; w( kMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
0 j6 P7 h* o, h( B8 ?" z2 |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 j7 m4 g8 Y- R+ M% v% p/ LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
# L% S% y; Z1 C3 p$ p/ m, XMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' t9 J7 l3 S5 w# Q% C& R+ c/ ?MCASP_RX_MODE_DMA);
4 x% A+ r1 S# \/ _, iMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# r9 f( t+ q7 p* x" [2 dMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 W9 C5 n: `' ?7 Q0 ]$ |McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
/ M& n: V: v0 e/ ^' F4 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 j% A& o4 p: s0 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' Q$ l# c5 z) u6 `. U0x00, 0xFF);

/* configure the clock for transmitter */
" R7 B7 {. L  R: ~5 v5 k( ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
, R1 h7 h. |1 o2 |
0 |" D8 v/ ^$ Y9 c% [# s, G/* Enable synchronization of RX and TX sections */
9 y" N( k+ b; F2 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
: u: f; }3 K$ V7 t: f6 j( G! I% m6 [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
' Z  r1 G# m, E- l% a# x+ l** transmitter and one serializer as receiver.
. a% p- u8 p5 W8 Y; I/ D# x7 {*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 s/ {0 u. i# J" F" lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
1 v3 R2 x' t: v6 m% K( q( g** Input - Frame Sync, Clock and Serializer Rx
  S8 |5 i+ P, v- g** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ i2 h7 V  ]" a0 D5 NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, _1 e! m; }, s: m8 {( B| MCASP_PIN_ACLKX
% y. L& r' ^8 N9 w! P0 c7 v* N| MCASP_PIN_AHCLKX
$ {5 j# N5 M3 I3 Q7 s; k| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
3 q$ d, D$ Y3 I; w0 u* ~3 y| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* |8 y5 l, \, b- b+ i( d3 `| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
0 B" n( o6 X- L1 n+ U+ z| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
{
4 @; ^( z" ]1 h) q7 L- z/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 u8 b0 O# c2 J# {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
! J) ?: V4 @% X" {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% k* h+ `, p) v3 G- P6 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

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