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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, q3 Y# B# Z r( {3 u; B
input mcasp_ahclkx,
6 r! I! E; J* K0 `! C$ \; linput mcasp_aclkx,
+ x4 t( C% @$ P2 Cinput axr0,
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output mcasp_afsr,. a4 `7 i; f% q) {
output mcasp_ahclkr,6 A( h, g1 [( C/ l% n! k
output mcasp_aclkr,# y7 k2 E4 n, E& n$ U) B
output axr1,- O4 V1 L. s5 L) [7 c( s/ X! x
assign mcasp_afsr = mcasp_afsx;2 H- A6 H d* |, R1 @
assign mcasp_aclkr = mcasp_aclkx;
" t+ a$ {. j3 Y1 M+ R/ n# D, gassign mcasp_ahclkr = mcasp_ahclkx;* A: `4 T/ `0 d! ~0 C2 T& S' {
assign axr1 = axr0; ; h: P- ? c) c* M/ v3 a, b& ?
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 1 ~% d; v! E d8 O2 Y4 s
static void McASPI2SConfigure(void)
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, g" V! `* h& F1 v0 I* p: qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# v# x* g0 P" N& qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 `: K9 n' C: T J/ G2 f' R9 @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ [4 v% l: ~9 c1 V0 n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- x: r8 i6 ]5 k0 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 \1 O+ ~+ h+ d% |MCASP_RX_MODE_DMA);3 G5 n7 n8 a' _6 v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 d [6 S+ D) G" q5 P) B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ B& T1 c5 {6 @; b8 m! H) c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 J' O- T1 V8 t \$ u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 p; P! X; P: J/ G0 k2 f& }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( P8 s4 d; Y7 l) j! b
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 F8 ?0 Z: i4 c6 ]9 q! o# g& w8 J% m$ eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ B; G8 I3 i% s2 r4 h, h) I" U. ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; p e( N! ?$ h3 e0 ~. U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 H+ ^ x+ x O$ b6 Y9 d4 E7 B+ z0x00, 0xFF); /* configure the clock for transmitter */- n; N. b3 u, D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- q" W# [. b M0 v# D1 tMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 w+ x. w" S1 `$ Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 O& o G! X: D7 H6 t& Y( ~
0x00, 0xFF);3 A9 r, Q/ M" k6 V0 S: M1 P/ a
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/* Enable synchronization of RX and TX sections */
7 f; P# T+ ~' R* l; ~) h5 a4 ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 l& T U6 E. d* B$ Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 x# j, J9 p% k( Y- {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, Q4 l. t4 m% A0 z! u0 E
** Set the serializers, Currently only one serializer is set as9 P/ Z% H$ z+ C3 _
** transmitter and one serializer as receiver.
0 X9 ?$ N/ l/ t4 \' V*/5 v1 @3 R4 Y1 k6 T3 O2 V: b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: `* L; p. b, S$ i. P) b( l9 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 t) K3 U0 J! B** Configure the McASP pins
9 ^) f1 {( Q, x8 _% v' |$ V' |** Input - Frame Sync, Clock and Serializer Rx
; S* ]3 m( f) [- s: r/ d$ o** Output - Serializer Tx is connected to the input of the codec
1 B" ^: N" _) J* y* P- F5 M*/& L2 [+ j% }3 \" n/ I4 q/ m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( p7 |0 @( a# q5 D8 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& Z! _9 u" W1 W, UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, _. D! m: ^1 h3 h4 h3 V# J4 }, H
| MCASP_PIN_ACLKX
- E% z2 h9 ~$ s! T| MCASP_PIN_AHCLKX5 b9 d- s+ ?# i2 @+ i5 a9 g8 p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% ]% `, L- t r4 N: TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 p- X M+ V! F5 O! g9 z* A| MCASP_TX_CLKFAIL & {5 [0 M4 O% @7 w$ U
| MCASP_TX_SYNCERROR& s' h9 z. E2 @9 L& I2 n) X& }
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; b$ Z, p% C) R; p8 M* n6 U| MCASP_RX_CLKFAIL
2 ]* w/ g$ s; A2 M| MCASP_RX_SYNCERROR
6 c- K$ I: J1 o/ D$ a# O| MCASP_RX_OVERRUN); E2 h2 a$ n' @
} static void I2SDataTxRxActivate(void)
% Q3 p6 F) g4 e% e0 ]{
( }6 Q* e2 C+ Z8 R/* Start the clocks */0 n) N( }1 S) `0 }( K2 k: N
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: n7 ~. X1 h& Y) m- b2 A1 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, X2 Z v! v# G! @. Z5 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: e; K( w( s. ^9 H, e2 b
EDMA3_TRIG_MODE_EVENT);; Y$ n- _" H* { n2 x' O$ _) F3 k- [
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . K# _1 R7 v3 j- E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 ~1 Z- Y9 N) e
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: K( ^( k1 `9 ?( P* p* U2 c! ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 @1 h2 a7 e2 P, d) N* T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// m' _: H. @4 B9 T5 ~9 Q5 l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 A; }1 E/ `$ C1 k TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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