MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
* F& K3 l, p! ]) X5 yinput mcasp_aclkx,
4 |% b, L7 p- T9 Winput axr0,
2 r( S0 r+ I) c" a( f, {( m" S* H
output mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
7 [4 `7 Q* g: W4 poutput axr1,

assign mcasp_afsr = mcasp_afsx;
) A: ~7 M0 }6 S5 V* g0 ^assign mcasp_aclkr = mcasp_aclkx;
* z! P0 ~9 B, U0 O4 oassign mcasp_ahclkr = mcasp_ahclkx;
: j/ b& H( e+ q3 \3 Qassign axr1 = axr0;

& E; V* Y) i* U0 h$ T: Y' [% U

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
. w8 t, h; w8 F4 [* w{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
( I0 c. s2 |1 h0 n) e9 f# [0 K" HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! Z, O' v& f! EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
5 r8 j! Z" D$ @: ~% dMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- Q' Y1 \$ `- ]5 |4 C8 V& x7 R6 Q4 lMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 X  O/ L3 W" B+ sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# d, x" s& L% w: o) G1 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
6 p& x# ?- f- f" P. ?6 M3 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 p' w+ _. }2 H/ O* U" p  o4 b8 k7 c7 tMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
- w& O7 o" o- W# L9 j" UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" R: P+ `8 F& }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
9 ~$ r. r! j  e! Z+ J
$ J! b; J6 R% q' O  w8 J- Y0 v/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- N! |' f" A: z5 Y3 B* FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
) b+ w& f% H' A, o8 Z** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
5 N0 b' e6 z) `! i0 U*/
& G. i" c8 J0 p! N& K; sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. q, |7 l, X3 H; t& n7 I, c- \McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
9 g# _( U- r9 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 h  X3 _# ]7 d# ?  G5 ?  `- i7 E# UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
2 e# `, k3 h  y+ P9 Q- g| MCASP_RX_OVERRUN);
! G- C% M: b8 l% c' G/ x}

static void I2SDataTxRxActivate(void)
) G" y& ^0 i6 [{
/* Start the clocks */
8 a% i9 a0 A" [  d' a* Z' ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" R6 o/ ?7 c) }# tEDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: A& R; M( W+ g) e' R7 oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
7 E' T- I4 {' K6 m- c2 UMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. y- m; m$ n8 YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
- Q/ [5 |) a5 s' [: }% B0 Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 z: I. N+ }: I5 N9 e}

! Z5 z8 `# U' r* ^/ j# q, M0 q. c) E

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.