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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' r @6 R x4 L: S: Q: Oinput mcasp_ahclkx,
: N8 I2 e* w9 q Yinput mcasp_aclkx,2 d2 f; q t! a6 |/ i
input axr0,
: T8 c2 ^ A! ^' v( ~8 D% F/ J( h4 Z4 ]
output mcasp_afsr,
% `& ?: H+ Y. O/ Joutput mcasp_ahclkr,- l" }, y) b# E8 M! m5 [" a
output mcasp_aclkr,* _7 j& e {, g2 z* G
output axr1,: K* B: D+ Z6 O( X8 Y3 Y6 j
assign mcasp_afsr = mcasp_afsx;
& Y$ @) v9 }# U- _+ I" S3 M0 @# _$ zassign mcasp_aclkr = mcasp_aclkx;
9 _$ U' {* l1 [- Q- jassign mcasp_ahclkr = mcasp_ahclkx;, L# c! r4 Y# `1 C- _) z
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , f/ `$ [: j' f3 m- A: f5 W
static void McASPI2SConfigure(void)
7 d3 }9 o" Z% F1 x8 M{
. \/ i/ h$ X: K& A. y- V3 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- H" h _$ W6 H7 g# }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. _. p0 V0 S* a H) b; [/ K; a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);. S. v3 O( S9 ^& Z! N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& J T$ U) M8 J: E3 [% `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 v/ Q/ D3 d: u5 i9 f
MCASP_RX_MODE_DMA);
7 f% g$ x3 n8 U+ p4 I6 [! yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 B1 H3 k3 c' y: ?( [" A7 K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: |. B! G* J* y* L( S% FMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 {/ O8 D& y6 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- S* e$ F$ I% a+ w2 g% F! mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . A `$ C- A. A2 R, N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* n' k, L& A# h% OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( r1 | u2 M" _' j% w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' q4 p/ J% M" j% [$ {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( W$ ~5 g G! [- Y" }" E0x00, 0xFF); /* configure the clock for transmitter */( V0 K. h/ ~3 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 @) m+ ~ N) j1 \# V; @) _0 PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# ~5 C$ o7 M8 O9 `0 e! UMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' I8 S, C( H2 O2 y. f4 e0 ~. W* g: p
0x00, 0xFF);4 a' j: c5 L; l2 }# T$ H! r
1 z8 }; `9 [. a4 q1 F8 H
/* Enable synchronization of RX and TX sections */
+ u, d, e0 W" j! R& T, @+ yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* k; _0 x! S* XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); d' u. e; J* F0 o% \6 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) m: n2 l! n. _; K, A" `) l* m: I- Z: g+ a** Set the serializers, Currently only one serializer is set as1 f- n9 L1 g5 U% V4 u9 _9 {
** transmitter and one serializer as receiver.5 Q4 T$ V t3 v/ s# @! \
*/# H6 i b) D U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ m3 ^ l G) J2 \
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 I: i& J' z! @# F9 e
** Configure the McASP pins
% R- P. ` r& i- Y+ Z6 N Q** Input - Frame Sync, Clock and Serializer Rx
f3 N# a6 ^6 H0 Y- ~1 f! K) |; I** Output - Serializer Tx is connected to the input of the codec
5 b% [1 A7 H* x0 u; ?*/7 p9 P% [$ z5 ^
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# k9 `' r- |0 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! C* o! e, U1 w6 |4 iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ ?+ h" g5 E7 a' u# V3 e# K2 ~| MCASP_PIN_ACLKX
6 p/ z A5 r/ d6 Y| MCASP_PIN_AHCLKX% P" \* f* e2 w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& d1 w* p* E. d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 L% n4 m5 z4 ^! q6 i {| MCASP_TX_CLKFAIL
3 f7 r W2 T3 [& x9 C| MCASP_TX_SYNCERROR
% v \1 B: z Q+ f9 \3 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : h0 r5 K# F0 ?1 T. X
| MCASP_RX_CLKFAIL
7 u# F3 |; o& K* a' M| MCASP_RX_SYNCERROR * n& H$ ^" ?4 | F9 G$ K
| MCASP_RX_OVERRUN);, c) a- \9 ?5 n
} static void I2SDataTxRxActivate(void)
9 o9 i2 G, j4 e, z D' ~{" j! Y7 _3 B% Z& I$ }$ @$ z, i! V# t6 [
/* Start the clocks */
+ }, E$ c% K$ b! q% W% l4 NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! [' W4 d. @! d- B8 U7 _% V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. j$ X7 ]/ L& n% [: _& _: N+ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& Z: a& d6 q% x5 I9 u3 _EDMA3_TRIG_MODE_EVENT);+ C- \5 o I" }, r( z6 o# z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " H# T: I( K$ V+ ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 X$ V* ]' d2 I; G9 q' I9 s8 ~5 k) yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) G5 Q* ^6 b! ~1 L7 m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; Z, N9 }' W1 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 \7 l8 ^7 Q) L5 R8 Q, v8 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 s, @+ v+ t, y$ u$ h ?! U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS); j$ q1 I5 J' @
}
1 E- v* o% V6 n, P, G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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