我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) G, R! s! b( Z2 binput mcasp_ahclkx,
& d8 N3 _( p- l6 V1 ?input mcasp_aclkx,$ ?" H! y' A' J) x) r3 Y- G
input axr0,
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; ]3 _' \) h# m f; |; Uoutput mcasp_afsr,9 ]' I" W" h0 a6 |( U7 q# `
output mcasp_ahclkr,
% U# _* C( x/ L/ g( d2 y. Doutput mcasp_aclkr,
2 d8 O0 Y# Q$ O9 u" }9 ~ n/ zoutput axr1,' U; @2 _, X f
assign mcasp_afsr = mcasp_afsx;8 g2 V( w' E' `
assign mcasp_aclkr = mcasp_aclkx;
5 s# H6 _ M7 Q! Xassign mcasp_ahclkr = mcasp_ahclkx;
% g4 O3 y: f; J! u1 p. Passign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# X4 q2 a7 f1 U* u: H- w& Bstatic void McASPI2SConfigure(void)4 J! b( M5 n- r0 C, _0 B
{
. j6 h' L& [8 j, S6 @5 J' u; }5 yMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" h% d' b3 v0 m; O J5 Y9 ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 i) d1 v: @2 ^" E
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 \& y* @! Z: IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
3 k1 y7 k( r& c) |/ v2 h& a% QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) o2 H- y6 F0 [; u9 n# }, K: ^
MCASP_RX_MODE_DMA);5 [# J3 a& Y" k# v, _) h: x# _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# R' @9 U+ j3 @5 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- f( ?# G# ?1 w% l) Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% ~4 i( I+ E& bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# d7 R9 B1 u' o! i Y, |
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 h& R& Q& {- S% Y& CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- M2 e V7 L0 w' }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( y& }8 @2 L9 }6 x9 l. B4 @6 d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 G( U7 m3 @- z- h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# ^# f% ?: o2 c2 d- ~+ M3 O( K7 E0x00, 0xFF); /* configure the clock for transmitter */$ g: I/ l3 Y9 o; i
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 P7 E/ n9 l. s8 AMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* n$ g; Z% a* F. u2 T) tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 m9 e! b! _* H5 \" R ?
0x00, 0xFF);
- p4 A% J" d/ ]0 O5 \" [+ J; M. h; @. x$ H s; r& {9 B$ X
/* Enable synchronization of RX and TX sections */
: n$ j& i0 h: a8 e( X+ x/ bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( M' w2 e+ h1 f% R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 e( l4 n. N0 d4 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: A( j8 S$ Y z3 R! o; \
** Set the serializers, Currently only one serializer is set as2 J; g! y. u* ~' X. c
** transmitter and one serializer as receiver." _: w. \& l! d, P
*/
8 E7 i$ y+ U ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 K1 h* t. H. j- @, d) a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, k1 d$ U+ {! g5 x
** Configure the McASP pins
7 O" K' M" c" O* A** Input - Frame Sync, Clock and Serializer Rx8 a4 K# Z) Y$ I. E# B3 i
** Output - Serializer Tx is connected to the input of the codec
7 C$ i( ?/ M/ W*/' ^ X7 q( g: m4 `
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& a7 g/ u+ r% W( K$ {7 S: e/ ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ q) E$ f- K2 x# D- |' ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& i! M" F/ U, j| MCASP_PIN_ACLKX ~9 y5 b6 t' P1 H& @2 X3 y
| MCASP_PIN_AHCLKX
" S+ o1 b1 S; s% C ~' r9 `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 Q' Q) H7 v# r8 k" \6 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . b0 n" I% J% m
| MCASP_TX_CLKFAIL
, B# b0 `" E9 S| MCASP_TX_SYNCERROR7 y$ y z6 `: E: p1 g3 _. k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ M0 L" U- o- G* g$ v2 _( a8 F* ^
| MCASP_RX_CLKFAIL' ~6 F& y& Y* t- M
| MCASP_RX_SYNCERROR 9 I Y4 j( v F3 t. x
| MCASP_RX_OVERRUN);* a, W, \8 U' e
} static void I2SDataTxRxActivate(void)
5 i- H7 ?# B" L{
. q+ i* N5 D" @" T/* Start the clocks */; i4 i2 M. Z. Y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; q$ i }& a& j' gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 m6 p7 i* D: r h1 ?# t5 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 |/ u" R5 t3 \9 g. p$ WEDMA3_TRIG_MODE_EVENT);$ w/ _9 F3 ~ t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . |. M' X9 P) u% Z8 c2 O/ q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 f, N- \( K/ ~& l" T1 PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) z" I! F b0 ~1 K8 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// [; C7 x, m& |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 b N4 L& }9 g+ F2 P$ W) H) S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( M* n9 k. }! N0 }8 U* A. r* f
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' W) ^/ y; s/ Y$ X& o5 t3 O, X2 [
} $ I$ Y/ B- J; W) C* _/ V
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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