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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 Z* |' B3 b- Q) u+ Xinput mcasp_ahclkx,
1 a5 e) s0 u8 A" C! jinput mcasp_aclkx,
" W" p% B2 u1 c3 W+ w5 Linput axr0,
+ m( @! N; |+ l+ l N0 T1 K7 Z* n0 ~3 q8 p& @5 F. e& G3 {. _
output mcasp_afsr,
4 D( Y6 h# B5 d9 m" D; toutput mcasp_ahclkr,
: H! {$ O$ {5 A- ioutput mcasp_aclkr,; K8 T% {: i2 _% U: i- I8 |9 B
output axr1,% A1 T& |; \( {+ m
assign mcasp_afsr = mcasp_afsx;& M H- d6 s% n X# ~
assign mcasp_aclkr = mcasp_aclkx;. Q* e9 y: j2 f. q
assign mcasp_ahclkr = mcasp_ahclkx;% u( \; V" J2 \( R7 M& d
assign axr1 = axr0; ! Q3 F4 p4 L! p% v, G1 P
' M9 m; `* U! L8 @& I! W$ j2 g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ G* D/ F6 l4 h# l( J6 q
static void McASPI2SConfigure(void)
) _, b* k& q2 i0 U& u7 p{
' c6 J) X& U5 k0 f; t* q( Q( V2 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS); j: n6 I# `# \" a- U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 p4 i" D* U2 r8 D5 `0 ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 l) Y, L7 o8 f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ N4 O7 m6 k4 O* _McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" m1 h" Z: H) H3 JMCASP_RX_MODE_DMA);
# n. G/ I- s# g0 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) l. P& _ ~% T* M, u' J5 v1 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 h2 L6 n% I. m* E, ^3 Y# t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & i8 b/ A/ t% I3 i8 w
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
Q7 G0 u. }; l! lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 d' W) m# ?2 e0 x# [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- @. s9 o% b. j; j' T* D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' y, q) s# c5 M. j7 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 a. Q' X0 m- V! F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- o. Z: q* X6 k- m5 U) R% r9 d0x00, 0xFF); /* configure the clock for transmitter */
7 V+ g& M* h, Y7 b- VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- W3 O7 N) `, L& r- T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( Z7 }' v9 ?1 W1 n+ e/ e0 rMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 b# }" g* ~; u; E) a$ p
0x00, 0xFF);
& p% V1 ~. @( G/ K& R/ |9 p% S$ Q9 S* L# k' z- g" d7 @
/* Enable synchronization of RX and TX sections */
6 O+ j) Q0 y( \7 v) ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
Y& P& a0 c5 CMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 X7 Y3 Z; |. ~0 L1 m6 g6 cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% f" f3 S* ]; ?( k
** Set the serializers, Currently only one serializer is set as/ u, u$ S* c8 ~" c3 V% O! S' ^
** transmitter and one serializer as receiver.. `9 X; A+ B: p. w. L
*/2 q7 t9 `2 n9 x9 f9 d+ m& \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); A8 }3 L+ m. y' x7 z& ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; {+ I1 Z3 Y) Q+ k/ f5 D8 z1 Y
** Configure the McASP pins
/ w# F; X* @% ~ S% { F+ f** Input - Frame Sync, Clock and Serializer Rx
8 t) g2 B6 V; ^5 u% c- {" O** Output - Serializer Tx is connected to the input of the codec
$ x2 C/ X4 b+ n' B; c, {0 A*/
% n* G- T. G# x3 Z8 P' a9 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ K0 J- K+ `0 l* a& ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 @. Z% i7 ~+ w8 W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* B6 P% b9 u/ j% v( z# F1 w# p| MCASP_PIN_ACLKX
9 G. _: T5 {' `| MCASP_PIN_AHCLKX/ |- }+ U; w5 ?5 m( I: @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
/ ^/ K& H5 y/ Y u0 CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 N g5 G0 [/ t| MCASP_TX_CLKFAIL , {' k3 ?$ B5 r: l
| MCASP_TX_SYNCERROR
" o Z6 |1 C8 d$ I, t| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
0 `; \3 S i1 V6 K. z( _& g| MCASP_RX_CLKFAIL
$ C j: T* M7 a| MCASP_RX_SYNCERROR
. y4 F. x" U2 f3 U I; ]| MCASP_RX_OVERRUN);
1 I% X% y* ]9 r} static void I2SDataTxRxActivate(void)
3 h$ w* N# s' u, J! r. B{* X; T) Y( R, }
/* Start the clocks */' R( w& r* ?, O# s. u; w
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( [4 G- T+ Q6 C/ m# i- S" q' b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ O. x( ?$ \! C9 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) G2 L: f) d& f9 n$ W q
EDMA3_TRIG_MODE_EVENT);/ g7 V8 h% l+ v( v2 E/ S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ R, K* b9 A7 T& }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% i( G; S' I3 c, ]; D# J3 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 Y3 X. ]+ V* G9 kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* N# P9 d6 b3 p5 E9 R F: Y1 U$ g; ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& I) M8 F" y9 F P, V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# E6 T( |+ N; J- i# AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 O! M W7 a! b7 g* Z& `
} . U3 Q4 E- d R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) X! D( \# F/ Q5 ?8 Q
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