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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' v# F3 \9 @) y+ T; g5 h0 M" i' z
input mcasp_ahclkx,- b* x" Z4 W" |; ], Q; y; s* k
input mcasp_aclkx,
0 n& s Y1 X; {& \input axr0,
' _8 B8 k/ U, `9 W# [1 z
- _- U B. Z/ i: b8 Q' l; t- S8 Uoutput mcasp_afsr,
. u* P1 Z, t( E( v& Foutput mcasp_ahclkr,
" M$ f9 n9 ]) P4 ]output mcasp_aclkr,
r3 J; F# S0 F! Q$ B1 W6 M7 ?- @output axr1,
% @1 A$ K; T7 H4 W) W assign mcasp_afsr = mcasp_afsx;
+ O! `8 E" f6 D0 J/ I: hassign mcasp_aclkr = mcasp_aclkx;% r- r3 a+ [' X* p
assign mcasp_ahclkr = mcasp_ahclkx;0 g& W+ s6 X7 @( j
assign axr1 = axr0; 0 ?% M" R5 c5 a" X( q
, ?1 C& G( S* s Z* Z6 q+ ]/ Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) A6 U2 ~. _2 d% m1 g
static void McASPI2SConfigure(void)
+ j1 o& s: ]2 r& M. Q% B{6 E8 ?9 \$ [1 C+ a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( I1 ^4 R4 q8 N" h- c5 @$ \8 A& l8 `McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( \$ ~( Y6 T* N' V O% nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 ~/ \0 ?9 _- O+ R2 ~; V: Z8 M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: y; _$ N) C% V2 J2 ?4 T* g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 O) ~( o Y: x3 t1 IMCASP_RX_MODE_DMA);
9 E- H; v7 L, T0 DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' X" w- C* }+ z& i4 j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ s% a- z: z6 c1 @. g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ ~. b8 p5 x# d3 g2 c0 FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# g8 v5 t& P. N$ q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, P4 L7 q' K/ t% T( @$ M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! u) I% d7 w1 a$ \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) M$ t0 ?+ N$ a! _3 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 a% a4 [0 _2 K: h9 Z% x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; x% @& }) G2 s8 ^. P# N
0x00, 0xFF); /* configure the clock for transmitter */8 ~# m) y% A1 U% I! _- B
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" u6 Z+ V5 A3 m- Y4 V+ h3 W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( G q" q7 E( p7 a# mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ s, q( Y+ c, J8 q! y) X
0x00, 0xFF);* F! X2 ^) P/ a" i) A
" {; e; g% ^- S7 ?/* Enable synchronization of RX and TX sections */
- f! |: r n k3 T- B$ k4 W3 r* ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ P& o% d$ k+ Q W% E7 i5 ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
5 z( V* a& x; W. H1 [& U- HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ D! r1 o9 C2 z6 h# {7 L** Set the serializers, Currently only one serializer is set as
5 U, W- r4 D& O2 Y# s# U** transmitter and one serializer as receiver.
" l3 B/ Z2 d5 R3 z; O6 r2 l% T*/: }- I5 d9 Y. D9 ?4 d/ T" I
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ I/ I( ?! p+ g |6 ~9 w( qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 A- T' S) q" J** Configure the McASP pins
: E5 q4 X) V9 x** Input - Frame Sync, Clock and Serializer Rx
+ V8 Q& }+ A, S+ f' n** Output - Serializer Tx is connected to the input of the codec ' X3 E3 G: e: ^/ F& ^$ V8 P
*/
' w' x# w0 ^/ r- ^/ M* |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% y: N$ ^, ]" H& f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 s& |' D5 q' ]! K: k! TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 c2 E+ w: f5 i7 K# Z| MCASP_PIN_ACLKX, t) \$ z( a- y& W! `' {
| MCASP_PIN_AHCLKX
4 W v. Q \- }0 N! J1 D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' y4 ?# z9 q& p9 `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
5 I. }1 p& G9 b8 K' F! W| MCASP_TX_CLKFAIL & |! U8 [' S( Y8 \5 J' [
| MCASP_TX_SYNCERROR* n' ~$ G6 ~8 m0 }1 Z$ N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! ?+ M/ P9 d+ w: N| MCASP_RX_CLKFAIL
W: M* k' H, M O) h9 q4 J| MCASP_RX_SYNCERROR 4 `. n9 J# F2 B/ ~ q, }
| MCASP_RX_OVERRUN);
2 Q E% ~. G) A+ R} static void I2SDataTxRxActivate(void)
( _3 P& D8 ]4 {+ A{
9 [3 y; `( ~9 G' I% q/* Start the clocks */8 L$ T9 q7 R1 J/ y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 K( U+ A, ?, o0 o, k' Q! @# U
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ]* W3 u# X X- hEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 J L& q) j2 o5 r( w) P
EDMA3_TRIG_MODE_EVENT);+ p% Y: G' M4 `9 ~% j3 y+ d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' S% h6 h& A& o2 F. ?- S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 s6 c; _$ V- A( l/ F' @ VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- B- h1 I7 C9 Q, }2 h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 T1 ]5 z) v f1 owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ r$ S) s; Q; x. B3 O- @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& w5 ]7 W6 l( u+ ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 S$ ]0 z( \9 |% [1 C# e; f1 a} 8 s3 z0 N$ D5 m- \& M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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