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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% {. P1 |) v) U, k9 e, @* T' \% Q5 H/ r" L
input mcasp_ahclkx,0 B% K h6 ~" Y# {
input mcasp_aclkx,' \4 M7 h7 s2 V- G
input axr0,5 F+ o& i% p( |3 C& B/ t
" j1 t; \1 g* w8 q) y
output mcasp_afsr,/ A- }+ H' h5 [% H2 i
output mcasp_ahclkr,
. ?7 i( W; N8 u" {6 Aoutput mcasp_aclkr,8 o# c) E; L0 X
output axr1,) {9 A3 s! {: I6 {7 y' Q, D
assign mcasp_afsr = mcasp_afsx;5 v$ p. V+ [- {2 \. @8 X
assign mcasp_aclkr = mcasp_aclkx;" s2 J: W/ ~; _9 x) j
assign mcasp_ahclkr = mcasp_ahclkx;
7 O( O+ t0 L, i2 h! N+ `assign axr1 = axr0; : Z. {6 t: g/ u: ?$ H+ {* s6 K
4 y- B5 S! B1 W! r4 j8 }) [. ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& d1 p. T4 l5 @: A( G9 w4 Mstatic void McASPI2SConfigure(void)
+ {, m0 V2 ~2 X1 Z, v5 f{" X& }* M# a) l6 V9 E
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
' }& w, [5 T' C/ H* ~2 E) iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, h% X6 w4 w* _$ {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; V3 p( I/ r# {8 p8 h/ ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: r- B3 U# m. n E" A) G3 P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! w, Y7 R/ h+ o) \* B% z6 \, DMCASP_RX_MODE_DMA);
6 p: ?. d) L; tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 @- t: f# O. s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) K) s4 E, r$ uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # X1 _; S$ e" {6 X( p0 W3 ]5 n6 Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
" y; e/ V& n+ v! E% oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! S9 b8 `2 A# w# J y3 o3 x: _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! _8 C; _' f3 x' j, b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 n3 J3 y S9 W b$ [
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ Z+ h+ c: f, Q' x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ i; o2 l/ C" P5 t& ~& v j! Q
0x00, 0xFF); /* configure the clock for transmitter */4 m f1 P, ^- k" k9 z, d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 B2 b+ A/ C$ R1 _, S4 d/ U2 J, eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* M& w% t8 |0 ~) k5 f/ {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. B# o0 o: o! D4 W/ Y( ~( Y A0x00, 0xFF); }! B& S; @: L
! T: d ^, ^* ?$ ]- }( @, p/* Enable synchronization of RX and TX sections */ 9 N3 l5 U2 p+ L: X) X2 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 m* Y, U7 k- J9 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 q9 A- ]/ C% h. R( p- o+ i, ^) uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, h+ @2 D- s( l8 N6 n
** Set the serializers, Currently only one serializer is set as6 X& p% k+ D4 ], H' q, Y7 `: _* w7 L
** transmitter and one serializer as receiver.& E" ?' b8 O% ]1 S d' C
*/
5 m/ o! n, j/ f, M9 g2 ?, a- vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: ~$ J2 f2 O/ m! B: Z, a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 X, l% c- B4 a' ]+ E5 y8 ~** Configure the McASP pins
E# C7 {! R a P% l) F** Input - Frame Sync, Clock and Serializer Rx2 D8 h3 ]" J! P. n) k# I3 p4 o. d
** Output - Serializer Tx is connected to the input of the codec : }1 C5 s# I* S0 o
*/
& p; v& d( |! z* k2 {- {8 `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 A. |/ G W ~/ q3 Y# QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% e$ t5 c; F2 J6 m& I p* O
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% j$ Z. B. z( V| MCASP_PIN_ACLKX
% r2 r T9 l4 ^! c| MCASP_PIN_AHCLKX
) h: x- X7 J3 P5 X' g7 j| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 ]' Y& b- Z, [0 ` g( LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ [6 y. e! C" c; I8 X3 O' `* G| MCASP_TX_CLKFAIL $ p3 \1 J+ Y7 M0 S% ^/ I7 F
| MCASP_TX_SYNCERROR
$ V. Z8 ~& x7 K1 j) {8 o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
u9 {* c: U' e, J" Y: J" k| MCASP_RX_CLKFAIL, Y/ K y* ?1 K( Z/ Y
| MCASP_RX_SYNCERROR 3 N$ [1 L; h$ l
| MCASP_RX_OVERRUN);4 X% D2 ?$ c4 A
} static void I2SDataTxRxActivate(void)
& U6 H5 T- _; ?$ ~2 r5 V9 V{
7 X4 e8 X6 P. E6 W/* Start the clocks */; G" k* A9 e5 H6 f' j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 U1 N" H& C7 g* U' M& D7 L3 `$ m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: F" e6 ?4 }2 D( M5 h9 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. w( Q1 m4 E& V
EDMA3_TRIG_MODE_EVENT);
2 X& ?1 ^0 C6 U7 D3 Y+ m- qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
^- I0 V0 b( {: u# G* C: mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ ~( `: G2 q; U( N7 o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% s j% I6 U2 q' P# ~# i& g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( x3 B% T& m9 p: v+ M5 k# C+ n$ ]. m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 @7 i* p7 Y g" y1 v+ b! J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' k* \! L, K. JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 k$ v# e8 L8 X} 4 s( k. U% O& ], D3 X* b$ b3 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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