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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 w D) T4 s1 a; b) d5 E5 O$ q
input mcasp_ahclkx,
2 N! `. M& K# L& R; ~' Rinput mcasp_aclkx,1 H, N, k& I8 l0 G
input axr0,
# g& ? h) X. ?) L& \8 A8 q F) }. r: ]/ z1 H! e
output mcasp_afsr,4 m) D% B# R( s5 j, Y! G, J3 P
output mcasp_ahclkr,, r: K) G9 l2 V; X+ P3 e
output mcasp_aclkr,. F; a7 K" ^4 W; [! b2 N$ r% \. ]
output axr1,
* j$ k7 H, Q( \ assign mcasp_afsr = mcasp_afsx;
$ y0 a! L4 Z7 d m+ v$ v( @6 b$ Eassign mcasp_aclkr = mcasp_aclkx;
, v7 m9 F' S: |* d! oassign mcasp_ahclkr = mcasp_ahclkx;. H* p; P! K' D k: u" A
assign axr1 = axr0;
: A# ?* x' @) Y5 I: G5 H0 o' a& C; K3 U' [6 B/ O, G& _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* c! I/ ^/ J4 y3 Tstatic void McASPI2SConfigure(void)" O! ~- g1 V: e7 O: k
{
; h9 C% b/ S7 k* n- CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% K" D# }5 H: j& A2 A1 F b* c7 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% x4 a( I$ D# Q4 g4 |4 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 m7 i2 ]0 @6 {+ |. s/ }: V" k hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 K# j3 v e1 H+ u4 Y1 H( V. EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 H% }/ C' l) [! `
MCASP_RX_MODE_DMA);) D p* ~) O8 i3 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," c: E# z" o& W6 T/ ~: M; b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */+ B! g" a" Q5 F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 W/ ?% h4 N4 i" }- tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 @: a0 [& A& r5 g1 mMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: o+ n8 g5 | `) N5 H1 O6 D, MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ \4 m4 X' D3 o' {1 B$ c7 CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 i3 h" c# s9 P# H: z$ S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( }3 R$ _, W% P( y, ?8 h6 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 O1 C) O' F/ P4 L
0x00, 0xFF); /* configure the clock for transmitter */
5 E' P! o* x$ zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 t% ?. n6 P( q, r I: T# M' d: V L' }$ ZMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) A4 H* E: u, y3 h) l. H8 e3 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. V+ L! E6 a: D1 G; H, t4 C0x00, 0xFF);
. r3 t! U6 @+ g$ n# w2 s: n5 }. P2 b6 U3 [- q, P
/* Enable synchronization of RX and TX sections */ + a5 k+ U" P& A5 E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- e, E/ y% z. m8 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 M; `( @, J$ ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 q6 ?* ?' O% v0 i6 E2 [+ v
** Set the serializers, Currently only one serializer is set as! Z, e9 Y# n; v8 Z2 G
** transmitter and one serializer as receiver.
5 q. K# \4 i ^& j$ @+ H*/
3 z5 c2 m; ^, |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: y7 p7 e9 {; b0 N1 _
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ T x$ Z4 }" N1 k3 P8 I** Configure the McASP pins
: ~ p/ E: P( Z** Input - Frame Sync, Clock and Serializer Rx
; O* F3 w3 v9 } g9 f** Output - Serializer Tx is connected to the input of the codec , K# C, m6 e. R$ W
*/
7 D. J3 u# f2 JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% s/ y# }7 S: c% `+ x' N/ g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ]' F, [" v* v
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* \" B# L" ~& M2 e& a E, r| MCASP_PIN_ACLKX
7 i9 `6 I+ ?, @8 F| MCASP_PIN_AHCLKX& g: `. F) ?9 N% |' F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 M* Q2 K1 a# c6 D5 E6 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 0 B' O3 C+ }% q! t' I( n
| MCASP_TX_CLKFAIL , V7 F0 D$ B+ Y+ c0 S( _
| MCASP_TX_SYNCERROR9 P( R6 h# [9 n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: S+ V# o4 S6 t' {| MCASP_RX_CLKFAIL5 W! V: ~$ m9 _, X# L' Y5 `( r
| MCASP_RX_SYNCERROR 6 g$ I/ \" U s& m
| MCASP_RX_OVERRUN);- ^* n% h# C9 i, p+ M# B
} static void I2SDataTxRxActivate(void)
. s \! r1 V& A{
0 b3 i: C4 ? K4 Y# p/* Start the clocks */; w1 q/ P4 P* a2 @& s5 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 G5 \4 a9 _8 }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 w- _9 Y7 q3 S2 Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 b, T# j1 V+ U9 J3 e. L0 q$ K
EDMA3_TRIG_MODE_EVENT);
9 u; x2 _/ [/ |: {; D0 L8 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 [) A1 Z& n! {# p: n2 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: x/ D2 j6 [- k/ F" m! AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 @9 ?- l1 Z7 H% f" h: f) A$ b& ~McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ t0 g6 s8 a/ ?: p2 I lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' }0 \, t" C1 M$ \' U3 H5 P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 W% {" `5 f& S; n; Y# y& |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( }* S3 |/ s0 z2 t7 K} / r5 d3 e" h S) ]
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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