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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. x/ o0 B8 K; [' S- h; |2 jinput mcasp_ahclkx,( l; `/ u& a B. p" s
input mcasp_aclkx,
8 g3 l6 b8 F1 M7 U; i" p, V2 t, x9 hinput axr0,
8 S# f- U' ]3 r+ l# F
3 {+ `7 m4 c7 `& Koutput mcasp_afsr,* \" G8 T( A3 _5 F% u4 V q/ N
output mcasp_ahclkr,
8 r7 L4 y% b, a4 M* f& u" ooutput mcasp_aclkr,$ t. ^( q& |- |& @8 i7 i& `
output axr1,
5 t8 k, y# J7 p) \+ A. g assign mcasp_afsr = mcasp_afsx;
1 y8 `& w, c ]5 G& c# K5 q! oassign mcasp_aclkr = mcasp_aclkx;
: Q- b x* w' W \( c: Y' gassign mcasp_ahclkr = mcasp_ahclkx;
) O6 z# d: h2 X& passign axr1 = axr0;
" R& S2 K! {% x! A0 C; g0 g& t) {
, x6 M9 ?4 T7 `1 l- C& P0 @( X8 r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 q0 J, S7 v0 T5 \0 T6 M1 X! m4 e' nstatic void McASPI2SConfigure(void)) o7 S/ o& A4 t" y
{+ j9 q3 s. x) D/ N k3 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
: Y% w$ O0 |$ E% C G {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; n% f8 u6 i# e/ \' w4 hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ F$ F4 v2 F: k& D4 ]2 iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" k9 c1 q" z( [8 U& d+ T/ BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, o6 y( |! k3 y1 h: D, A0 j3 }MCASP_RX_MODE_DMA);$ w* E0 ^" Y8 S. B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: @5 O8 s2 j! h# O- Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% |, k& ~0 W' \& l" y, q6 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ J& ?8 v$ Y7 `/ p: J0 X) c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' x& n( u" x( @/ sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ S0 K6 D; n$ J8 M/ a! X* yMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 g) z+ B/ [. c W
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! r) I7 @) J. y+ }3 Y, |McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 [( o; }1 B* o! zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 y. @( e( H9 ^, A2 D; n0x00, 0xFF); /* configure the clock for transmitter */
! W. Y- B: i9 @7 U- U8 b* MMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% Z- J; J1 i! e( MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; R, ?1 P& B+ Q; ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 f% t% p9 b z2 a$ W0x00, 0xFF);# I3 c2 }# O7 {) p e
" O) t8 w& l& ?) g! Y7 @/ K
/* Enable synchronization of RX and TX sections */ ; _0 \4 ^% ?4 Y% L. s) A. W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- ]! Z( A8 H' o; G- X1 l0 D0 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 D1 }( e6 M: s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* _+ r) ^- A9 ?3 Z! x" g** Set the serializers, Currently only one serializer is set as
1 U1 g/ e9 x) O6 l! Y** transmitter and one serializer as receiver.
4 J, c! J. _/ A O4 D*/, i9 g+ @4 {; I' L. G# S C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 S& F3 L* Z6 ~# o! L/ E2 L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 I( z0 V* [" T; r
** Configure the McASP pins
0 w2 Z/ R% a' ` h) G. o; E, k+ X** Input - Frame Sync, Clock and Serializer Rx/ _; }0 k, I+ v0 M- H$ x8 l; s: Q
** Output - Serializer Tx is connected to the input of the codec
4 U5 ]/ N8 @7 m* L( z |*/
& g( r9 o& x& K+ O9 w1 bMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* [8 h2 N4 f2 q B, y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));1 ~0 Y7 k( } d1 `* D$ t8 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX i+ M. r$ _* {8 {& b2 N
| MCASP_PIN_ACLKX3 B( q f0 N, T/ u' A- ]
| MCASP_PIN_AHCLKX
+ t" E) g3 f+ w| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 E. W# ]' e$ J* W& V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - v: I# M; m( I# R) }
| MCASP_TX_CLKFAIL ' x S0 R9 ^4 S/ y+ H1 m* K
| MCASP_TX_SYNCERROR
3 ^1 H4 B) \6 t5 b8 ~$ J) n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) X0 C8 t% g+ N0 R3 ]
| MCASP_RX_CLKFAIL% N1 c1 Z8 z9 U- D' C ]4 _) w( L! k% F
| MCASP_RX_SYNCERROR 3 T6 B) ?! S( I( s$ o y% Y2 @' z& ~9 y
| MCASP_RX_OVERRUN);; |' {/ j7 P3 x
} static void I2SDataTxRxActivate(void). X$ k1 W2 j# L) u6 V
{
" I) U, s4 D2 t8 i: J9 d/* Start the clocks */3 v9 a6 T( M g& T6 b8 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) P5 [7 S( V: H3 y2 q2 j# U- y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! `7 r- n5 |( Q' [, vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% {5 i1 T* V. M; d# s
EDMA3_TRIG_MODE_EVENT);
( f" f- Z, Z! GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # C2 x. G; s! T! Q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ A5 o- Z4 F2 s# f& Z( |1 C6 Z n' \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, k3 n" \) Y9 V+ i; g/ t5 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( r1 @2 _. i7 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: K; g( e' G/ J3 `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, z) p7 L* J( k c2 ~; DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);, v/ _/ b7 `5 _- Y* H
}
2 A: `- ]4 ]! a# l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
l' s9 j" r- E( a9 \ |