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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: t [( H8 w, X$ ?0 finput mcasp_ahclkx,
5 R0 [1 W- H8 v# Kinput mcasp_aclkx,
* { r; v' N' u! n* v9 v" j5 P6 D& Q5 o8 K' Linput axr0,
+ G4 G4 v, R- A( {, f( ]( D) o
% f1 O5 L! Q. I) c. {4 r/ M/ ]output mcasp_afsr,
) y, c: L$ X: W) Z W# q. _, I& routput mcasp_ahclkr,
% T: k$ f, A2 i4 M+ Koutput mcasp_aclkr,. u" X6 R+ F4 U" e5 }
output axr1,
# C0 q$ C R2 i3 S. Q8 Z% ^( \* Y assign mcasp_afsr = mcasp_afsx;$ r9 @$ E, v0 o4 E6 {8 `
assign mcasp_aclkr = mcasp_aclkx;
. ~ J& O3 G$ w, S9 Zassign mcasp_ahclkr = mcasp_ahclkx;
0 m3 [3 E6 |$ r/ J ]assign axr1 = axr0; ( q+ I; S) w5 {$ j2 s% K" G4 u* J
2 v' l1 [0 H/ o% k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " H4 T2 c" X4 [5 f) u$ F
static void McASPI2SConfigure(void)
3 j* ] z9 x( p" Y' t{
; c( s* _. M; u& I4 `( @9 ^* S5 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ R( m* [# E( @$ S$ o3 V* gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) E+ R7 q! J, ]/ v0 C: nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 ^, X: Z# l: \+ z0 `# X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* q$ p) }4 M5 }4 B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% ~. W) q0 b# BMCASP_RX_MODE_DMA);
" d. w, y3 o1 j( j0 W/ m8 z, mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. [* e& x% x' H9 N% }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 j! G" _' C/ q0 O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
E. o7 ?" ^8 H DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' c- [ K! k+ @0 XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & I" E0 l8 w, j4 l2 o9 r* A. w' ?* |" Q0 o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) i2 t: G! Q% T& t6 G3 p( b K" J/ E$ M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 q4 m" ]( l3 i3 x6 `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 V% N1 ?* ~7 Z% n' |6 w1 u" FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 s5 ?5 t3 x6 A% ]+ u' u( f
0x00, 0xFF); /* configure the clock for transmitter */. ~3 l+ V0 N: V+ C$ R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: `: m* \( y. v# t" c: [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 i7 c8 ]8 {% d9 h! U$ |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) Z' q5 ^5 M8 V2 t" R4 Y0x00, 0xFF);
# W/ R& i2 e( m/ Q
& C0 M7 w: b h1 R# D, m/* Enable synchronization of RX and TX sections */
1 O. S) d; N5 M4 @, FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# u, w3 x( f' A) t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ C# r3 K1 W9 j$ f8 ]$ s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& V1 `# t$ @) G" Y; O6 u** Set the serializers, Currently only one serializer is set as
* C, C: q$ V* o8 w( r$ @4 z** transmitter and one serializer as receiver.% k* ?& e2 o) d
*/
7 V& N; o/ \" V2 x0 Q5 m, ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! c0 h2 |6 S$ u: E4 q6 ~McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 T' I' x* P- v$ a7 }** Configure the McASP pins 5 |+ R' _; Y- d
** Input - Frame Sync, Clock and Serializer Rx
7 a4 g: l( G' h/ S D# Z8 C7 }** Output - Serializer Tx is connected to the input of the codec , }. H( ?. o& C- h: ~+ f% j
*/$ h0 l& \) v( m* n* W* I4 \) A! t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 l) O8 E0 l$ ]' f: J+ R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ t% O9 g- E7 Y* y; a9 S+ xMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# D0 J- p. p. x: l6 }$ }, S1 `
| MCASP_PIN_ACLKX/ A4 E5 @" |; ~3 g# z- Z
| MCASP_PIN_AHCLKX
' @) P! C" S# y4 L% U- n- E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: w# o1 e8 N$ r1 A( h$ {McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. ~2 g* U+ k7 F" I2 n9 v7 q# U8 Z| MCASP_TX_CLKFAIL
( O* Q; j4 ]1 ]8 ~- f; {| MCASP_TX_SYNCERROR
- F, G' O1 K/ n& E$ s* B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 C" \# Y0 h2 ]6 ?| MCASP_RX_CLKFAIL" D8 h; @4 N' w$ u! z2 J
| MCASP_RX_SYNCERROR
# D2 Z; u! {% g6 `* q! h& W| MCASP_RX_OVERRUN);
' p% A& n6 M) _, K1 f' L1 b, j) h} static void I2SDataTxRxActivate(void)
9 w r$ r! H0 A3 o) J& }+ ^% y3 R{2 O9 Y% N5 Y( Z( n- \
/* Start the clocks */7 p$ V" Q- u) u! G8 e% W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" `. n2 j5 Z$ J9 p! l" ^5 e3 oMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 p+ c$ f# f/ T: q: ~0 t* E4 q, ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 N1 C* r, b6 j! R* l0 {EDMA3_TRIG_MODE_EVENT);" {2 c4 q) h& T# Q I
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. o; L# t% T _) t4 PEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 [+ f6 c. s( tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 }5 g! W' d/ H4 P6 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- |5 A K0 t9 s1 U( f: w2 }% T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: l" J0 j! l. c9 {
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ v" S8 ]( M/ s9 MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);2 H8 ~! T: @8 e! E3 s( `
} 8 `0 U2 [; {6 |7 E* Y, a c1 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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