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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( v! n! L) Z: o8 |
input mcasp_ahclkx," f3 H/ a$ L$ k% s+ |# U% u
input mcasp_aclkx,$ f \- p, X( p1 _( Z5 W6 @/ R
input axr0,, C2 u6 @* b- e! b5 z
* Y7 e# V( d% boutput mcasp_afsr,/ M) C' B2 y8 n( e* A
output mcasp_ahclkr,' W ~2 e. p. c8 i3 c
output mcasp_aclkr,
B0 D% W! {- qoutput axr1,& R. N- l2 q' I
assign mcasp_afsr = mcasp_afsx;
+ q4 S: ^ k* E3 |. `/ ?assign mcasp_aclkr = mcasp_aclkx;- L: Y1 N! ?8 Z
assign mcasp_ahclkr = mcasp_ahclkx;) _- v% F$ ?; ]5 e* h. d4 W7 [6 C
assign axr1 = axr0; & F! e9 y, g8 M+ k, x9 E8 J
; k& E N9 l) N+ x2 P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ x# q6 b* `; P# L N
static void McASPI2SConfigure(void)) c- U3 `: L* m7 X$ O
{
$ F2 N& N( x2 \# _McASPRxReset(SOC_MCASP_0_CTRL_REGS);" v! |4 F) D- c( c" p" R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 _( N% {* D; C2 O( t6 M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 i3 T% C/ ` f$ s0 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' }, n8 ], s! X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ G: f0 x* `. _; PMCASP_RX_MODE_DMA);! x: G! c! u- M: w* f% k( ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 x u1 R3 U! t7 Q7 uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# t- F' k2 v% @0 E4 A) n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & w7 X' K% x) G( D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. r# {! A& P) E: G# a3 \; _
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % u' l; }2 u. b1 ?4 _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( B5 `+ h6 n8 [3 }- c- Z% ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 R8 K4 b- e1 V! x0 S, a% ^6 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 r0 f. ?! @( V% U/ D: [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- ?0 M: V( I& ~ t2 Z9 N7 Z0x00, 0xFF); /* configure the clock for transmitter */! r2 Q: ^; X$ M5 \7 Q+ Y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ O, { I# H* A& z b6 W8 ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 @$ |% J3 i* M- ^7 K: AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; M" @9 T7 k2 q% r% z# q& n# _
0x00, 0xFF);
$ i* `" y7 h3 E) ~. P1 w. f
) y" ~$ c0 J. H: R! e/* Enable synchronization of RX and TX sections */
- @) `! B" N7 J* E, L: uMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! x. \6 Z( h1 v8 M1 R w0 x0 i3 c. @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
y% U3 i' M' I" S' DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 T! Z1 T3 x! f( n9 ?
** Set the serializers, Currently only one serializer is set as
2 Y. G x5 M4 m8 Z# d** transmitter and one serializer as receiver., V& I' i5 @7 Q$ X1 c ~3 \
*/
7 ?+ C3 v& }6 R8 J* W7 CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% a" f& ^4 ?# O, R/ w* kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: C% K+ O' `. ? E" F& e
** Configure the McASP pins
6 x1 ?0 q/ U6 e** Input - Frame Sync, Clock and Serializer Rx
; n, P: I+ n. o$ g6 Y) ~** Output - Serializer Tx is connected to the input of the codec 5 s- D2 C9 `" a4 n, c4 C- a
*/
/ l2 M! Q# A, |, \. a: zMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) L" g! d$ f7 S7 O. v7 l. }McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' Q/ B! X3 q& z3 o, b/ c7 R) |- g5 HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# \- |1 U# P* y
| MCASP_PIN_ACLKX
0 N% B, `) T" U' `, ?| MCASP_PIN_AHCLKX& ^4 c) e9 u3 Y: m6 H6 ]; \ |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, d% c/ d# s4 T! s! @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! }4 _8 M# } F
| MCASP_TX_CLKFAIL
# p3 N1 ^! i3 N0 ^0 u8 L| MCASP_TX_SYNCERROR4 C" [1 G, Z# H& N0 ~5 h7 r0 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . ^- k$ @* m9 [3 I1 E% M- j2 x. I
| MCASP_RX_CLKFAIL
, k! {1 H2 h; c8 h, W6 ^5 `) }2 Z: N4 u| MCASP_RX_SYNCERROR ) h5 B8 \( a7 P
| MCASP_RX_OVERRUN);
! u3 I$ d9 v0 B3 G. I} static void I2SDataTxRxActivate(void)) C# a# l; V- [- K* y8 _- E/ {5 ^
{7 D5 T+ {5 \) t& ^9 A
/* Start the clocks */ B' n5 T- _! |$ P& X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 p- O! D3 R4 h0 c7 f
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 ~ n" }2 p- s4 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) j- z! ?* h. y, S- h; AEDMA3_TRIG_MODE_EVENT);
$ O# `3 {: I- T; vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# Z8 v" C# n8 e: n& h, eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: Q1 r! Q: g9 DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* e) r3 [3 f7 t: h( D, u: tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 ^8 Q, e; ]: J$ }! _, a- a; ]6 k. k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// l, S4 ], x e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 ^: M# q4 ]. \. G* Z7 J& ]- w* FMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! S/ h2 C1 _$ @! ?, m
}
1 r* o2 p0 ~$ E请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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