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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* T% D% W4 O+ B8 c
input mcasp_ahclkx,
) k7 @8 ~: ?( N F, N! @input mcasp_aclkx,8 J: y3 D4 W5 ]7 q% W7 O3 I3 W! p
input axr0,
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output mcasp_afsr,1 l& }7 u, M. m7 `
output mcasp_ahclkr,6 v8 z+ f, {/ `% } d' B+ U* k
output mcasp_aclkr,
' b1 U) S- d2 b5 b; Q; Zoutput axr1,# r* \; i/ J5 }0 r
assign mcasp_afsr = mcasp_afsx;
7 s3 z5 h9 s- @. L+ Rassign mcasp_aclkr = mcasp_aclkx;
" W1 i7 |; v$ E: D+ j5 Uassign mcasp_ahclkr = mcasp_ahclkx;
' x5 e# Z$ T( _& Cassign axr1 = axr0; 2 J9 ?2 ~) _, r# c
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( q# q2 v$ X; `3 l9 ~static void McASPI2SConfigure(void)" r& |: P" K' D. A& {$ z0 P) D! o. U
{
8 f6 F. R! H; Z( MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; s1 q+ r. n s- r4 P6 eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 b8 R$ n% m4 x) q @- s6 y' ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 @+ p! Y/ A$ g5 \; u7 m/ |6 O8 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# Y' ~1 T2 f& F0 W1 ^8 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: q- P/ V2 ]4 E( J( nMCASP_RX_MODE_DMA);
6 l$ {4 U, G1 G9 n1 UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 f; t3 d6 Z4 V1 @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 g( i0 Y3 D2 C' @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) y, ^! ^' N0 l5 N2 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* d% R4 M/ c* B/ A, ^4 l! i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' M0 g" o6 Z5 i$ m) UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, D# \ U- ]4 i9 @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. D, T9 b2 z8 F u" ]; [, k3 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) v. d6 U0 I" N- |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 E, F/ I e9 @& }" h `6 h
0x00, 0xFF); /* configure the clock for transmitter */$ A7 C) J- y7 ]/ K7 D, {* V
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" v( Y- k6 c% u' v9 k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& j8 ~' G3 U" c/ L# T( h7 r6 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( R/ f" `$ _* b a; h0x00, 0xFF);3 W& I2 Q$ R$ w& W5 D
& ^; [( J4 V, |5 ~/* Enable synchronization of RX and TX sections */
# O" l* q" `' ~ q; B& a# ^8 ~0 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( w' i9 x# x' ~% E" sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' w, r. [9 d G0 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 L8 }) T! {# b9 W6 c1 a& c
** Set the serializers, Currently only one serializer is set as
1 W4 b, E- `$ m1 n0 a** transmitter and one serializer as receiver.- m( W5 L9 G- O, K
*/
+ w9 t2 V! t" W6 [. x& lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 D& k7 |9 r6 X" q: j1 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ Z% Q( j* d- ]; d S3 Z2 [** Configure the McASP pins ; Z0 R' y( M) O8 v' Q. G) i
** Input - Frame Sync, Clock and Serializer Rx
& f- P& I5 I3 Z8 j! U' K+ V. M: @** Output - Serializer Tx is connected to the input of the codec 3 v5 K6 q' S; @) b; p
*/0 u' L" i5 E% H" S7 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' X, Z' B3 d5 O* Q! z( p* uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! B, C2 c Z8 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" W X8 x$ Q4 g. c& V9 {
| MCASP_PIN_ACLKX( P+ c( }7 ~ \5 ~" x! k; t0 ~
| MCASP_PIN_AHCLKX/ g* G- y! b6 ]& ~8 A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) [% l1 a7 c4 B3 c0 V
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ! C: i1 j5 u% a5 f
| MCASP_TX_CLKFAIL
( [9 R2 |, e# J2 P1 s) @| MCASP_TX_SYNCERROR" ~2 O) W; y4 Y/ l& p+ v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 c2 P7 x3 }) C# [( f" a2 C) w) q| MCASP_RX_CLKFAIL4 N f$ V8 [1 W5 E$ f; C; ?8 }
| MCASP_RX_SYNCERROR 8 p t. N. o- |% O: p. h
| MCASP_RX_OVERRUN);
3 G: T' T' _9 U) x- N} static void I2SDataTxRxActivate(void)
- j/ _/ E4 t! {; g& ^{7 R. o2 L! U2 N' y+ m3 z" f
/* Start the clocks */$ G6 @3 d4 S! n/ r5 e- d! d, i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* U, C6 @ g) y: bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 ^" w, o* o ~9 y9 b L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 E7 ^( d6 W( M
EDMA3_TRIG_MODE_EVENT);
# a) s5 {) O' ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % z+ E, G/ m) {, c1 B# A
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) g. w( o# M0 x/ rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); N# z( b+ {4 W; \3 t
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! T, Q8 {3 `- g1 \% l* V5 h
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' O( b( g0 Y2 Y, `3 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" q4 e9 t! _2 [: `5 r! _
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ d z' ~) E7 V; d
}
5 I: L3 G8 O1 C* w请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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