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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" l3 i; Q9 f& `: E# Yinput mcasp_ahclkx,
2 S8 z/ q. i0 Winput mcasp_aclkx,9 X# V$ g1 t8 O0 l+ g9 r( U+ a5 ~
input axr0,
0 S6 J; y# q: T& b+ u2 u; t+ `1 e3 l( V2 c# r
output mcasp_afsr,* b% X8 V7 P" q- S; D
output mcasp_ahclkr,2 h! N I! B& t; I, Z8 R
output mcasp_aclkr,
6 B8 u' C& |* R8 E) ^output axr1,3 S0 d8 i( D6 q5 ]
assign mcasp_afsr = mcasp_afsx;4 n/ P3 x% M% _( P5 S
assign mcasp_aclkr = mcasp_aclkx;
8 a7 T5 k6 }3 N9 @8 {assign mcasp_ahclkr = mcasp_ahclkx;
" x9 |! ?: |9 V' ~3 Massign axr1 = axr0; - a E' F$ h% s$ ]' x/ Y
* y" x: X1 V. }% I: {2 X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 [, A) o8 I: Ystatic void McASPI2SConfigure(void)
; u3 j5 Z4 J' [5 |, n{
& R+ C) C n1 T/ m) G9 QMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ f$ T8 {9 V+ f8 a% l" A$ j' MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- Z/ [; t1 {5 F% r& n- D4 N' i5 I: i- Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 Y: k5 f0 B7 j6 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 F! g. E) Z. f( ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 ?2 j+ [1 X- B* v4 h4 a
MCASP_RX_MODE_DMA);
1 N- v( }9 \1 U; IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, ?& l' ]$ r Q& w, [$ i! w7 ]& `" nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 Q$ j+ F& I2 |1 K4 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! P+ t5 T9 W+ o, K/ ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' i, d$ ^' ^, ~3 i6 qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! P1 T& g- J: H U- ~MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 O( O) \& r3 Y9 N0 h
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, f- N" i5 t4 M" A4 n0 D, jMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
s% d6 r9 Z" b" [# t( D: ~; a/ G) KMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 Q! B u9 O2 b2 p/ [5 g
0x00, 0xFF); /* configure the clock for transmitter */
K. w' j5 a* _$ z* YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
1 {0 b- f4 g2 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ U( |# C: S4 \2 p) n& ^' P. H [McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" [; Y! d; e: W* z m( `* q- | J2 x0x00, 0xFF);
3 b. U% G" W/ q* {; b
. h' N( B9 R5 u9 m! R6 h9 M4 G5 O/* Enable synchronization of RX and TX sections */ # L3 Z2 i' E* B
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# V" n) V% y; h+ o, {! r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 h+ r) m1 @! E h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, j. {. [7 D) }** Set the serializers, Currently only one serializer is set as) ?: l- U$ D2 }4 x; `- X$ _4 Z
** transmitter and one serializer as receiver.
) s; C( h% \8 A- k9 Q*/
2 D) m# A3 j$ B7 T7 {* q! CMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( u6 i1 G* _4 Z. ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 E, A: V* S1 d0 @( ]
** Configure the McASP pins 0 Z% _2 S+ n2 s! C* A) _/ _
** Input - Frame Sync, Clock and Serializer Rx& J! M* A2 v& X$ H6 G+ S
** Output - Serializer Tx is connected to the input of the codec i5 G( R/ d/ p$ M; {
*/
4 ]! \- Y+ @) yMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) _. f# u h. J5 T
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); ~; ]- D, w' K+ Y- ?$ Z1 @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* ~0 N: Q0 G: U
| MCASP_PIN_ACLKX* h# m1 o7 o( m$ I( @- E2 ^& {/ D, Z
| MCASP_PIN_AHCLKX# f8 a& m) C# q7 q3 I& Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 T* ^6 x5 _& a% \- n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- o) E0 Y: L9 A| MCASP_TX_CLKFAIL 7 y1 s5 x+ I# f+ M3 E
| MCASP_TX_SYNCERROR# ? V- }5 j9 A4 ~ Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; b( s9 T9 a* N1 f, l, w| MCASP_RX_CLKFAIL, p2 Q6 A# h$ h' M; v
| MCASP_RX_SYNCERROR 0 Y8 i- w1 g) S, p
| MCASP_RX_OVERRUN);3 f: J7 Q% M$ b+ |* f+ h" J
} static void I2SDataTxRxActivate(void)
3 H- E6 o' z" r% ~; z8 U{9 D3 @7 B# V3 }) C E. ]; `, g: K
/* Start the clocks */& m4 N8 y4 B( R* Y6 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" ^$ a5 Q. K1 j* H& p+ ^! W; V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 h1 A) Y: G. _1 p5 x" h6 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ Y* w5 i! _0 y5 [
EDMA3_TRIG_MODE_EVENT);
( N$ P" C9 \. EEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. s1 H* i; A5 m: g8 k* xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; c0 [6 [& _' @) C3 p7 E5 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! D2 e8 F! ~3 q l9 E5 ]5 `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# E8 K, {( V& g4 h8 U: Z) H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 q: B& E3 K; R, `& G {' lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ U0 ?4 u s) a* P5 M$ q/ |6 a: z7 g2 ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; {0 y5 b1 t0 r7 G}
k! h/ [. q6 Z y+ T T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 P7 L1 R% L }+ h8 H1 _
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