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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 o% q6 M0 c( J
input mcasp_ahclkx,
: r8 S/ N; ^, t. Z2 Kinput mcasp_aclkx,
4 Q# n5 c! ^+ Ninput axr0,
) l- C# U1 u% v# r4 J" J( A/ x
9 S2 R4 ]* J6 n/ ^1 c3 R* Loutput mcasp_afsr,. J I' D9 ^5 N* {! ~$ ~
output mcasp_ahclkr,
5 U( p4 r. R9 Y" o! q% toutput mcasp_aclkr,
0 P5 [1 K/ p; t; i+ Zoutput axr1,: o. v- e7 _& z1 w
assign mcasp_afsr = mcasp_afsx;
& y5 }. V; X6 D o/ t0 [9 h4 _assign mcasp_aclkr = mcasp_aclkx;3 M' r( Z1 D5 `) F3 o
assign mcasp_ahclkr = mcasp_ahclkx;- `( K! P& h5 X6 H' q
assign axr1 = axr0; 4 X+ f) ^+ r$ R) x* C
) T" A7 F. A' ? ^$ {& n8 c, ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & x* i+ r+ r8 @3 E
static void McASPI2SConfigure(void)
2 f# Q& Y) \3 W# L; ?$ h) H{( Z5 ^! ~6 }5 u+ n4 R0 B% _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 n% G; K) R8 Y8 K4 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' M' q! K: r! Z3 R4 W" CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
) U$ w' y `. s3 J6 UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
e6 a" Y( q' @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 q/ _: J& o: f! d* H0 ~. w6 k/ g
MCASP_RX_MODE_DMA);
$ V: a' |! f) }+ v/ T& S; o/ sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ g! b5 U' a5 n2 `
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 I' A" |$ V8 _0 u/ r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 ]& y. X6 \1 g' |; s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: U4 f6 C) D; I: B X: ~9 B8 b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 Z) P6 [, H0 z; T$ vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 f% F( b* e1 s$ Y( v; s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! h! V `% p' L- w5 V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 j6 ]1 y: h) j5 O
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ R: n+ ~% E! B0x00, 0xFF); /* configure the clock for transmitter */5 P+ y6 J% @) j9 p' L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 N- U5 w' v! n& F0 OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
' G, I- T+ u3 q8 y* m7 |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& Z' V: D* U7 u6 M; h0x00, 0xFF);
' m; L# l1 x. Y2 \) W9 P/ a, B, d8 h- l1 S2 \) \+ C8 Q! a2 Q x
/* Enable synchronization of RX and TX sections */ , \9 J1 y2 ]0 t9 y% \7 v2 o9 X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) Z" H6 C* e& _1 I7 Y. g. s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 [* M& B) v6 [6 B' V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% d5 h) E4 k! r8 L% k$ O X7 h** Set the serializers, Currently only one serializer is set as0 t$ A% e: G# V" P
** transmitter and one serializer as receiver.
$ K3 S+ o7 D R# }. X*/
( g2 K s0 m9 {McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" K/ R# D' G' _8 T7 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* ?) }; A% c$ A% X
** Configure the McASP pins
1 D7 o A4 n- O0 ?) Z** Input - Frame Sync, Clock and Serializer Rx4 k- O, t5 Z( j! o& d; `
** Output - Serializer Tx is connected to the input of the codec
4 \8 ?: y6 ^4 g9 i, j! y; z, I*/
6 x/ L5 j" c# `' P1 e! rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% D" R7 c8 `& z, N9 \8 [* i wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ _" @' A0 }7 }4 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& X2 I" k( S& H: H7 V( I2 h| MCASP_PIN_ACLKX; W& N9 [& q% ^
| MCASP_PIN_AHCLKX
$ g; }$ ]" I1 O3 p+ ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* O5 I% p) W* s* B& n+ j. w) k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; `, w6 L/ q* I; `4 v5 `% F$ k6 O| MCASP_TX_CLKFAIL
5 P, _1 h8 Q, b9 e7 G7 H| MCASP_TX_SYNCERROR
* F/ o- D3 T/ V# k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* l5 x8 J' T# X$ C| MCASP_RX_CLKFAIL
( n+ a9 ^) `6 w* r! x6 Q B$ _( @7 a| MCASP_RX_SYNCERROR
8 b5 b9 v- d8 L| MCASP_RX_OVERRUN);
M# B6 B; W1 G# a2 O} static void I2SDataTxRxActivate(void)
T X: n$ Z, b/ A( b{
& O# I* d8 I1 { s5 Q# ^: u: z% h% y/* Start the clocks */! i5 C p- S4 c/ M, O7 {( D4 t. C
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ t9 h6 X8 S* U6 H6 [2 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" @! p$ s: E1 N; j6 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* W) f' I+ [/ {& \# ]
EDMA3_TRIG_MODE_EVENT);
( J5 V4 }; P5 }8 l* Y4 j$ x2 K' PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ ]2 U* ?6 u8 W+ U1 R7 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* l/ d+ o' m- O! j& U+ X* ^+ | g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
S" r/ d, ]1 A7 h: PMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: _) e, V* n* u, X5 {( Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. H: N1 j J: e; E2 U9 i6 W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 X2 F% C) f' O) ?8 H2 IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);8 p4 P5 X8 H5 L9 N0 p3 S, v ^+ V# n
}
3 i, [% e1 p5 g' F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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