MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
% b+ B: w1 X* {  o
output mcasp_afsr,
6 D0 W$ z. H, v& K/ I8 ]1 houtput mcasp_ahclkr,
output mcasp_aclkr,
5 g) E" ]; s, ?4 Ooutput axr1,

assign mcasp_afsr = mcasp_afsx;
; [9 q7 T6 E2 a3 }1 s$ oassign mcasp_aclkr = mcasp_aclkx;
/ j! Z2 \; k4 k( L* ^- a( lassign mcasp_ahclkr = mcasp_ahclkx;
; _/ Z1 b% q* Sassign axr1 = axr0;

# X  Y( l# {2 Q% }
  k3 F& W. i' G7 S( {5 |! e

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

9 V% K# Q( F$ ?; {) M6 v

static void McASPI2SConfigure(void)
6 \+ W4 a( {; ]& M{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
: ^9 Q  g$ C$ M; \% H% c' z6 D( }McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 O- @( U  i9 t$ HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
3 q; P! i' P3 H* V) cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
9 c# r7 d6 |+ ?" H6 H9 [7 x( Z! a1 _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 ^) m" J* R  A: ?( _8 zMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' v$ I- w- N5 \) s+ L4 C% U7 hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. f8 i% ^, {# }0 a0 uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" \, @7 l6 e7 U9 Y- Y5 NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

* n5 M2 g' L6 O: f8 [/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ R& R: s+ s4 G1 X' z6 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
% b3 u/ C9 y, A' b4 N0 _7 _8 q** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
8 w5 V9 s9 T- d8 t& ]) h*/
) W; T6 x+ F+ y8 C2 iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ x6 _) T- N$ P+ a( f9 l. sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
9 x, ~% H5 m+ u  `) `** Configure the McASP pins
3 j  _# u1 A& m** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- A6 r! x, K; Z: r6 w$ g# mMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- z9 L* e8 O) U* S+ ]| MCASP_PIN_ACLKX
: v& R0 `( y# z/ g: b) L| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) |$ R2 i& s, K) k0 V- v% m8 f| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
+ a0 V# t' a4 U% _! d}

static void I2SDataTxRxActivate(void)
$ `# F5 r1 K4 Z; o3 L{
8 N; Z' B8 b5 {7 J" o2 e/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# V3 e/ }$ x' j9 H" X; H) t* cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
% C4 K5 ~+ `2 {: U1 S: [4 J( [7 a5 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) U; F8 i) n) m. K% s' z8 P8 }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% Q; o0 z; L; k$ VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! d3 a% U" W5 \}

5 J; N+ J* V) e" j' U

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.