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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: C* y: w3 ^' G9 z1 x1 F" Y; g+ }input mcasp_ahclkx,) N9 B) j& g9 Z6 `1 w9 D1 S
input mcasp_aclkx,/ W" D; E- n4 o
input axr0,
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output mcasp_afsr,
; `4 U7 {2 N4 F M0 @& u1 x- Qoutput mcasp_ahclkr,
8 r# t$ f/ h* n. F D; u9 Z0 ooutput mcasp_aclkr,
* a" ]/ n/ c" ?: Eoutput axr1,* p, G" {0 h9 @, |( m
assign mcasp_afsr = mcasp_afsx;# i4 z2 z: m4 @* a
assign mcasp_aclkr = mcasp_aclkx;2 Q3 o( I% z4 t1 C3 N% i0 w
assign mcasp_ahclkr = mcasp_ahclkx;- e, G) r5 ^, ]- D" W* k5 O
assign axr1 = axr0;
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V Y* R; r1 G& i) ~在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! \0 [+ N# s6 i o7 a- L# l8 [
static void McASPI2SConfigure(void)' B2 t. T$ p2 \, m$ E
{
2 B) z8 ~5 t; E Y) _7 r: TMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
' w* _" V0 |. H5 S# B; c$ RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 g) x: K: u7 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); q1 I4 q" X7 N) }8 G, k0 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
4 x" S' v0 l G }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 c$ S: U5 Z3 k$ s PMCASP_RX_MODE_DMA);' `# O: R7 L% ^# v. m- ?, G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 d3 f" U) ?$ e4 y6 H' WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- B, F9 W' p6 b% UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 v/ K4 A8 ?8 y& L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# p/ G; _" w# d. @. _& t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, , ^- `& ?2 k& p, V7 p! W3 c
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 Z& }7 ^5 l" P. R0 |/ U3 Q. _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( p0 e/ y$ c; P( M4 V$ s$ OMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 E1 z, e1 d, R, {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 ^$ `. m& g5 C: b% U0x00, 0xFF); /* configure the clock for transmitter */
D) K& Q0 c6 g% q; ?" S$ P* |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 T# _' @: @; D, d$ _$ j0 |. q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); j* x* Q2 |* H3 J6 x: o2 I4 R& a- B) M
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 f/ b- w2 |4 g E) l2 D( e p
0x00, 0xFF);
) O* a8 O4 ~9 r0 j9 K7 w- T" E; O5 E0 ]. g
/* Enable synchronization of RX and TX sections */
' R. d' f" `8 }5 g* {& ?McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 I: z, e0 m+ U( [) f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% N' }1 P, h( C! O4 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; g# t7 h9 j) h. ?5 n( C
** Set the serializers, Currently only one serializer is set as
+ v4 _2 R0 c( }! T1 n) L: O** transmitter and one serializer as receiver.
, L5 P: K( {9 ?8 d B: R9 X! a( N*/5 ^9 @ I" U3 f+ a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: }+ Q% Z0 q/ w1 {& G: W7 F$ x* [3 W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# {- I% O- C! u0 y3 O: f
** Configure the McASP pins ( I5 r, c/ X: _* r t
** Input - Frame Sync, Clock and Serializer Rx
$ r1 X6 k- [+ z- ?** Output - Serializer Tx is connected to the input of the codec 8 |) X7 M. e7 c7 H4 h
*/
$ y) t$ d( h+ j0 tMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" i6 v k+ z2 d6 C; x. |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( k- Y0 W( F# i7 {
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! ?* t& z# A! \: s
| MCASP_PIN_ACLKX, N ^! l8 b6 S
| MCASP_PIN_AHCLKX
$ [! m! C3 [; o: e, S# F| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- k( U; [( p* D- ~% uMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 `2 S! n5 W* l# P: L/ f- @| MCASP_TX_CLKFAIL c" A) f$ P9 s; J
| MCASP_TX_SYNCERROR
' Y- S& U7 }" ^. J# E% G- U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. U7 x# {# [5 D* S1 q7 \0 m- F' G: _| MCASP_RX_CLKFAIL% I% E( F8 p5 Q; {7 l
| MCASP_RX_SYNCERROR
1 x: p% r9 [ U9 c) q| MCASP_RX_OVERRUN);
Y# Y3 _! @/ E$ o1 z( `! P5 U! F} static void I2SDataTxRxActivate(void)
- p" z" b3 r& u5 Z; D8 p{0 Q3 E, L- T* J l
/* Start the clocks */) p3 n. |2 B$ g0 ~5 c
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, t J) {9 S4 F7 Q7 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 h8 k2 r3 w7 _/ q) ^3 u2 w0 t# v: A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 h/ c# ]2 S$ c, V( WEDMA3_TRIG_MODE_EVENT);5 i: t1 d/ H6 e& a9 ]0 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # T6 N' M7 @4 W, E8 F+ T
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* d) U) v& H) Q: w+ k! Q1 F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' P6 B* ?. T# N5 |6 O& }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; ^2 R4 C2 D' P3 ^ v: i4 y8 ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! d8 k# O& o9 p( Y7 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 s3 X( p$ W8 ?1 sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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