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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
h) [4 G$ ~4 g5 i$ ?input mcasp_ahclkx,
: g! Q; l9 \4 v& b, I1 N: U5 jinput mcasp_aclkx,
5 i" v0 Y/ T0 E' O! L" x) Binput axr0,
$ V" D. q# p$ \: }
; h$ K! S7 D. Moutput mcasp_afsr,
# C! U; b0 x! |output mcasp_ahclkr,5 Z4 p; E7 B9 z4 f/ w
output mcasp_aclkr, S% f r* [- ~: C' W% h* ^* Z+ `
output axr1,
- ]/ x& N" u5 s% h9 ~ assign mcasp_afsr = mcasp_afsx;
# I0 I6 n& W/ c5 R0 ^assign mcasp_aclkr = mcasp_aclkx;
9 U! `. j% A/ m' R" k- Iassign mcasp_ahclkr = mcasp_ahclkx;" K$ ~' l } ~$ O1 O J9 P
assign axr1 = axr0;
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: |2 [) \0 z+ L+ d( G. ?1 R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 C8 L, H2 W6 E0 |static void McASPI2SConfigure(void)2 A: B# Q+ C7 Z; R W7 k- S
{3 {; H; s4 |7 w% _) V1 J% H4 I- ^
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 H0 u1 E/ O& Q5 {' j9 N4 VMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* ]% D& q8 ~4 @) h! Y& Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; F. A7 w3 x9 e: D5 n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- U2 S- T% K- L! b6 M; k0 j/ VMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. F7 q( V; O& O! k4 Z& F% eMCASP_RX_MODE_DMA);
4 s6 \- K# Z' F4 z/ mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 y6 Q/ u' I' R* y6 T) Y# T5 XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; @! I% a* b1 o8 U5 i7 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " ~; f& G @* N2 D; W* J# `; _
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( I; @5 J. N; w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; X$ e$ l) C* p( H1 c, ]) e* `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 j. D7 I% B n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ B" `+ b+ ~" N% z$ g8 z, Z$ Q. A
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, D2 D J. Z- S' M3 E9 `0 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& X2 f; a8 v$ ?, }7 K0x00, 0xFF); /* configure the clock for transmitter */! t" z6 Q5 o B( d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ v9 v) s i2 [( Q2 dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * H# Y0 l/ T6 E0 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 G* k8 g$ c# }
0x00, 0xFF);( N& t! C8 o7 b0 @1 ]3 R! s/ t
# {' ~# f! k( x- ?/ J/* Enable synchronization of RX and TX sections */
* y+ p& N, \3 i* XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 |& A1 V, O2 S8 d0 ~! [# xMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 Y$ e- y/ D4 M( F; _4 ]8 f, NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, p4 }3 H" f+ l, S$ Q0 t** Set the serializers, Currently only one serializer is set as
+ O1 z# |+ t3 K6 o, T! B** transmitter and one serializer as receiver.
! ]3 Z9 x4 i* } k*/( L) V- @+ ]# B! ~/ U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, N9 Z( s3 e. a0 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** Y L( o" ?$ F
** Configure the McASP pins / n% f/ g( O) d. J! e, n
** Input - Frame Sync, Clock and Serializer Rx& w& x9 k, v- A: M4 c- {& O
** Output - Serializer Tx is connected to the input of the codec 4 K4 c& \, @+ d* f- C
*/% a1 S& Y. v1 J5 O0 p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 d* e0 V4 \ q+ |5 }* C- X: \# a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) m2 Z0 u0 n9 w5 J4 l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; u# Y% c4 `4 I8 B4 b| MCASP_PIN_ACLKX
* e* \: R/ X% b+ {) t# V6 G: ]& m0 a| MCASP_PIN_AHCLKX- h1 ^7 u$ A" y9 X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 Y9 S/ o9 C7 O6 m; E3 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' E9 l8 G* ]5 ^; Y7 _| MCASP_TX_CLKFAIL
( y: g9 b* \2 X u| MCASP_TX_SYNCERROR
# t# ^" d) r7 b/ b) y- w- C! a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; W v3 o+ U' M' t2 t| MCASP_RX_CLKFAIL/ ^+ o& Q, H! l" ~6 z( V( J' f" N
| MCASP_RX_SYNCERROR
+ [/ t1 D d% e3 f/ h, M| MCASP_RX_OVERRUN);3 U$ ]) q& w: e
} static void I2SDataTxRxActivate(void)
3 R0 l1 G7 R$ K! ?$ _3 V; j) R{4 I' ?3 p& ]& _2 @* @! s( d
/* Start the clocks *// q9 n4 X! X8 y' ?3 Y$ e$ q! \
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, k6 W. G& C- H4 [) a* D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 \0 Y- ]( E+ aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 W, w& k- y4 v- m# K) wEDMA3_TRIG_MODE_EVENT);8 r4 `8 X* u" }* A ^6 |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ r5 {, V' J! s8 r2 ~8 R5 S; [& TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% ~9 ^* x1 S6 S1 B- B0 Z* ?3 zMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ ~. {3 X. n3 `8 q9 j; p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 z2 O! g( I2 A& h% l) H9 swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) ^' u" e/ e7 i/ ]* H( Z! W0 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( U/ R+ Z$ K2 q4 H+ n3 p |$ Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);# ~0 G# ?7 z0 \; C" M, S1 c
} : |* x4 E2 r6 d3 y: y3 j; I1 g+ p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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