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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# n+ u* N# j8 O# `input mcasp_ahclkx,5 i; G0 O2 x4 |4 B: t3 d0 P- d \) q' x
input mcasp_aclkx,% ^: \. z9 O6 v; s
input axr0,
# C# C7 K$ e; j; l: f# v! k5 u* A* C8 l& l6 a9 X# Q
output mcasp_afsr,0 q, g. x# }- b9 Z" Z4 @
output mcasp_ahclkr,
( t4 H# I1 P, @output mcasp_aclkr,) ?* F, q7 I3 ?+ Z7 W
output axr1,
: H3 p& o0 c$ ]) l assign mcasp_afsr = mcasp_afsx;
/ Z5 E6 u! @8 r& V7 Y( R$ ]assign mcasp_aclkr = mcasp_aclkx;
) n9 U! H3 a; P# y6 V: d" Massign mcasp_ahclkr = mcasp_ahclkx;
# E4 a9 B) Y+ P% e8 l* C* Rassign axr1 = axr0; * k* M( r7 O1 K3 h# R6 o/ I" o
5 C! m% M) Y: ^) k, v8 @' ?: E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ?5 o9 I5 ~" B! f! x
static void McASPI2SConfigure(void)& [( [- c3 i5 e V& d
{% F6 L1 R& S; k+ O6 ?; Z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);2 Y# ]2 C' J0 Y0 `: j3 q' z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" `$ V. o% Q+ F) ?7 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% Z' F, V' X+ w- R3 w. s. s, V( m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) Q& z0 d8 T. H1 [- U2 C% n3 V. IMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 d3 X& |* T# K0 |( AMCASP_RX_MODE_DMA);
; ~/ B2 |* K. W- }9 Y( W9 pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" }6 y, O% i7 S7 r& ^. _5 }, |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! E& Z. _0 u# d% U' L3 E% {( W" F
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 b, A! `7 [% B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 s# l: g4 L3 U# t
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" S9 m6 `3 m" V- S/ n a+ p' g0 r2 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 [% W* F' m; \* E+ l% jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- \( g+ o% A1 @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ' G( g( o5 f& L: P# p
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& J- U2 G; f, Q8 n
0x00, 0xFF); /* configure the clock for transmitter */
' G% D1 T3 X- i0 @McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ I0 ^7 N% }0 m, _: l8 ?% d" v4 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( I( ?, r- a8 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,7 r l# V/ x" g* f/ K7 g1 c
0x00, 0xFF);
% \3 C0 a( |" g8 e0 q) `' g3 t$ P
/* Enable synchronization of RX and TX sections */ ) g- }7 E+ U3 B8 e, A# h$ E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& C9 e- n! L8 x3 M+ i2 S) h7 S& c! t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 M7 B( _, i3 o- w9 k" f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% s+ ?( ?" G5 Y# @
** Set the serializers, Currently only one serializer is set as" d) j& D' n- D% a9 \ R
** transmitter and one serializer as receiver.$ M6 U9 ~. W4 P. b! I
*/
6 t9 C u" n4 ^5 d. c+ N6 W. b( O/ E3 eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 m+ A. D* X; |5 p V$ |
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 C$ n/ P. c! E** Configure the McASP pins 8 a" p4 W; w+ i. }; y5 J
** Input - Frame Sync, Clock and Serializer Rx
; v( ?- t% ? E6 ]" c** Output - Serializer Tx is connected to the input of the codec
, w5 d9 x/ n1 a$ B*/9 m W; h" z2 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" F n: ?6 {/ b4 K; c; C. S0 U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 S9 {. I) `2 l8 d) M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ k6 \: X1 W" L6 H/ S8 n, P| MCASP_PIN_ACLKX
0 X: R% {: f1 K2 _3 K! S| MCASP_PIN_AHCLKX" ]# g% s4 y5 Q) }' r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 J: [, ?6 l2 p% {
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 m2 j1 |' a2 Q+ t/ o6 U| MCASP_TX_CLKFAIL
' E* W j: a C| MCASP_TX_SYNCERROR) Y* U7 z1 ^' K0 Z Z. I0 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 [+ ^, l# f# O9 y+ c, x
| MCASP_RX_CLKFAIL
l) h0 |/ w+ C3 m/ N2 O/ \5 V| MCASP_RX_SYNCERROR
4 f, w0 t- K+ i1 `5 S, \8 J2 G| MCASP_RX_OVERRUN);+ Y; V& i& E( L2 w. Q/ e$ a6 c
} static void I2SDataTxRxActivate(void) m8 U- H" t% ^- J
{2 M: o' t2 f3 K/ y+ w
/* Start the clocks */# S: f' d+ k6 L/ q4 V# j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! J) r+ u! _* p% [" ^McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( U1 [0 Q9 S6 H/ {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. O( a, A5 S8 q& A
EDMA3_TRIG_MODE_EVENT);5 R, T. y; F6 U* }6 D5 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) f8 K3 k9 N" g1 |8 v: v) G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% q u5 C7 N' _: w% M" T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( ? j. @, ~" \0 _& g0 V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. _+ m8 I4 X" q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 [$ Z1 Z; i% e( ^1 u
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 V7 Z. L% A! o$ C2 B" c8 M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- @) v0 I1 u8 F8 G' T; E
}
' E& V- T6 P. i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 u! B! b& `7 Z. a) m |