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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 k* h* [3 B/ I7 j2 g+ [) `4 G3 G) finput mcasp_ahclkx,
" G V9 l3 i' Z$ h0 n$ _; `5 A1 Ginput mcasp_aclkx,# Q4 h" m7 I; }6 p
input axr0,. |- e& L; M! D5 v. R5 b
. p6 j& U1 e; f8 Y) Poutput mcasp_afsr,/ L$ k! f4 K$ A1 s ]2 n
output mcasp_ahclkr,: r. e$ f" Z# C$ W
output mcasp_aclkr,. S' _* {& n: m" Y. S" a" p
output axr1,
. x5 Y) y! |! K% J& t assign mcasp_afsr = mcasp_afsx;
0 [9 @" U# X5 E: p6 fassign mcasp_aclkr = mcasp_aclkx;
1 _2 M+ ~/ J( N/ v2 Y8 _- _assign mcasp_ahclkr = mcasp_ahclkx;) d% _; ]+ D |, F- r* Z$ X
assign axr1 = axr0;
0 ^# N, W" s" a) T9 q% z8 r" a6 _
0 g9 z9 X3 Z. |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 F0 X% t" M3 X- dstatic void McASPI2SConfigure(void)
5 t# K. n; N4 G{' z! _2 d5 w W/ i: X9 ?! ]2 }, {
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 n7 j; @: m7 N, dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: Z1 y/ T2 Y. u+ z. ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ~1 S9 u9 _9 Q" E: f/ b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- h% @, S# \8 Y& zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ?& W& b4 d7 e% B8 ]# o
MCASP_RX_MODE_DMA);
( Z0 u0 D2 [- \5 H1 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 w* ^, U# F/ wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. k- _2 D$ q8 X" n6 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* c, w% g8 H7 eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& y9 A4 {) n5 `$ _9 K# IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, a+ @) L, N# \" l L$ h! XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ w9 {# |5 f( rMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. z& L1 E* U- d, e1 LMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ e" {4 Q% J* y5 t4 x- AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 n: P+ Z: q# P( v9 A0 k9 {# ?0x00, 0xFF); /* configure the clock for transmitter */3 c- d. R0 j5 l3 p5 p/ H. S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, w# C# b ~ g9 k; kMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 M+ i5 K- u* S1 `1 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' V! |: U/ ^- U- X0 F0x00, 0xFF);
8 n6 k& F z1 N& s& L% E0 \: p/ T
/* Enable synchronization of RX and TX sections */
/ C$ Z3 D7 e; l9 L [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; _8 Y. `/ Y, h- {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" [; ^7 u4 F) a7 v5 |$ v/ A% G# Q, xMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ }& J, k8 e) m, c% s; v7 H, ~
** Set the serializers, Currently only one serializer is set as
% V5 b4 }2 `/ n8 e: S** transmitter and one serializer as receiver.
9 @- ^. Q& T" Y0 t$ D6 k. F*/
" H1 x1 I, f9 n1 L2 A3 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 l9 s, S6 ?, {+ t. q2 ~/ t$ z2 Z) MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 h, C ^7 t) E) k3 u** Configure the McASP pins
& m, {! L7 a" p; k** Input - Frame Sync, Clock and Serializer Rx8 q$ `6 l( A* K& t3 m
** Output - Serializer Tx is connected to the input of the codec
5 ]& R3 k0 o4 A/ ]8 Y* @. T*/: M) R+ |% Z2 w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 E/ E% w2 I; m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 C9 Z$ \" o' U: B8 E y! n( ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ h! ^, o8 R8 v' } d3 S& z
| MCASP_PIN_ACLKX. {" n& f) o( |. c' R) ]# F! V
| MCASP_PIN_AHCLKX# U0 ]# x3 j# ~
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 v) f3 {# O: [+ J+ y" g* n3 y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 z) i! {4 a* l| MCASP_TX_CLKFAIL 5 x# [; ~; m# e
| MCASP_TX_SYNCERROR
H- N' b0 Y/ b) w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 z0 @- D" o$ h) s* M% U. P3 @
| MCASP_RX_CLKFAIL
) @; y: E/ M- p' U. ~2 M| MCASP_RX_SYNCERROR
2 E" m2 n- D v( ^# @: c| MCASP_RX_OVERRUN);* N$ K/ O% O3 Z) f
} static void I2SDataTxRxActivate(void)
1 D- ^ {+ Q6 @{
* O, }8 W" k- i$ A1 M) b/* Start the clocks */
" F @) \% k: AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; D2 U! T! O: J: Z& sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! U) T; Q& X0 n: L2 R8 nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ j/ c6 e# n+ m6 @% s' h% y: MEDMA3_TRIG_MODE_EVENT);+ s. L% Q1 F) q1 C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 C5 j& `0 v$ c+ m0 lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' }5 l/ `3 t0 F4 KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# J+ |# B4 x* \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) I, z1 p8 e0 m0 B2 R/ V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 c- v' J6 ?' ^) ^. R- eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: d: J) Y [1 @+ V: wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- n2 ~: W; ?8 M( d! \2 _" j# J9 X
} ' {9 n2 j( r" Y1 A8 j7 a b0 C9 I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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