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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 h% {: Z8 v9 a) J0 G( Q- x3 S" N# Qinput mcasp_ahclkx," Z2 C, f: E0 d# z, d- n
input mcasp_aclkx,' C4 F' t' W+ N6 B$ H; b
input axr0, l" H& G2 U0 C4 f7 y
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output mcasp_afsr,
8 I+ l1 G0 d$ L* youtput mcasp_ahclkr,
- r5 j) c$ d' Youtput mcasp_aclkr,
l- S, G, e1 ]6 E1 R- x4 moutput axr1,
! U' J; G- s! K- S3 h assign mcasp_afsr = mcasp_afsx;# h( C* {% C1 _9 a' g. F
assign mcasp_aclkr = mcasp_aclkx;) c/ \, x6 i$ U: p+ f5 X" E
assign mcasp_ahclkr = mcasp_ahclkx;. P3 c' ^; f8 a; c6 r
assign axr1 = axr0; 3 ^0 U r& x0 v6 l# w- S0 ?
& q1 @! _+ }6 N* ]7 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , W/ w+ M& m2 `! P
static void McASPI2SConfigure(void)
$ L/ `! J3 p, v$ L$ X{
, B% v3 b& ` x4 ~* x- bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
[0 C5 s% r8 D/ E% t5 @ j' tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 ~; s4 D) K$ O3 Q9 b( RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 y3 _1 d% D& U s2 Q3 @8 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; A% Z4 ^4 D+ a4 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, b, F% p2 e' U3 f* x
MCASP_RX_MODE_DMA);' g4 U3 ~. ^/ U- F( N: U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ W& y( A' `8 k x$ T9 ^' lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( w" v' F5 ~: z6 N1 }4 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & T& R- Y1 |1 \9 g9 ]! D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; a4 c! H9 c% l* k3 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; U, a1 K8 P' S" wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' [- Z9 O' H. eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 H% `1 `. A8 CMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 |. V+ k: X# j+ N: u1 H. V/ hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; i) i) Q" ]- x4 h- r0x00, 0xFF); /* configure the clock for transmitter */6 @6 h( `8 |! i% U# v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- ^6 \/ l; a2 [0 gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 |- A( F% J* X4 jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 O: u; I! I I0x00, 0xFF);0 ^+ H: q0 `/ }
. F) \* q% V! ^# o& K1 `9 X2 A3 h. g
/* Enable synchronization of RX and TX sections */
* ]7 h6 @% b* R# D. XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 w) Q7 q3 o+ r: V' ?: Q+ a
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 q" w7 C' W2 c. i/ W E
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ \, S9 O) A8 J) F% {: R
** Set the serializers, Currently only one serializer is set as5 U) j# x* y3 P; e, i g! G" c/ U
** transmitter and one serializer as receiver.& p' Z. I* L; I
*/" y) z9 A& I8 `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' _9 j: V" [1 F& P7 w; FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" I1 X5 d9 K( T1 x** Configure the McASP pins
1 p- z! A) v+ `' N** Input - Frame Sync, Clock and Serializer Rx
! x( c% |7 G+ C' n. \% c- W** Output - Serializer Tx is connected to the input of the codec
* E$ N7 o) K# |% S3 ?6 A* V*/$ A8 v2 J5 a, ^7 B6 O/ M* j# G
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( C; ` x( W" u" G& u/ [0 AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" V. [5 x2 m! UMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: e' x Q4 C' S0 N1 a7 d| MCASP_PIN_ACLKX& e! P1 |0 f$ Z/ r1 P) s
| MCASP_PIN_AHCLKX
9 q* h0 {8 }) w! O# B Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 R) K$ H; f3 j; bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 r6 H& \( r3 ~5 `* ?. W0 d+ u| MCASP_TX_CLKFAIL ) ^8 f2 d5 \" h* ~
| MCASP_TX_SYNCERROR
0 M0 }! e# l4 {' s4 X3 j& T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) y! J/ q5 f& K+ _" O: B
| MCASP_RX_CLKFAIL; q, y" n6 N% x5 }& l; `
| MCASP_RX_SYNCERROR
& x: s6 g% `' j) {7 ]" V| MCASP_RX_OVERRUN);2 I0 l) c) ~& P1 k
} static void I2SDataTxRxActivate(void)
3 O# ?. e9 _# \{
2 |2 y! S. X9 s) X, l y1 y. |/* Start the clocks */
+ E. G/ U& B2 ?) q# P! j4 ]McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* b4 K4 n9 G. G: g' q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 O, g8 G$ y+ A8 T/ }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 @! ~3 ?6 c1 Y6 C" QEDMA3_TRIG_MODE_EVENT);
?0 H; k( U) K' YEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
^$ M2 Z, D9 F X$ o, bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 F. u. e) q" X# vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( D7 U' j' S- m' s; ?4 T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% o/ m' _8 X$ Q1 j1 F/ E, z: a2 pwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: _* Q; T. O1 p. S7 G8 Y7 s0 {1 h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 A% A" V6 y5 V# _4 C* K
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ K) |& r5 }7 e0 T8 W" _3 }: W}
! Y3 b* x. Y- \4 I& B: N. F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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