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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 {& @0 ~' f3 z* @5 B
input mcasp_ahclkx,. _4 f8 N( ^( J, G2 ^9 @
input mcasp_aclkx,0 n' I2 O; R6 h3 M( z- o4 |
input axr0,
0 A4 b/ ?' M$ R4 U! K, }' L, _
0 ?$ o3 q7 e+ uoutput mcasp_afsr,
) h5 G7 s$ J8 `# O9 Z& Z9 loutput mcasp_ahclkr,& Y6 b4 c% e w* {% i$ | J9 |& x4 R1 f
output mcasp_aclkr,9 S; W" Q* K) [0 x: L5 r
output axr1,7 R# c' z! T% X( [% E7 N
assign mcasp_afsr = mcasp_afsx;
% |' s0 O* G' y K1 G% L7 V/ @2 Rassign mcasp_aclkr = mcasp_aclkx;0 C# X3 i0 X: l) \* \* V% P
assign mcasp_ahclkr = mcasp_ahclkx;
; B, i- p; E- }, ]1 p: n. G6 Eassign axr1 = axr0; # X, l5 i3 A( y6 w! w
* W/ N9 _/ f9 c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ k; o3 _" q1 _7 y! Nstatic void McASPI2SConfigure(void)
, C! P; L' _7 z4 ?) ?4 j0 T{
2 G' ]) J& U# R* N: f* y/ K+ ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 }5 p3 f7 G4 }: n _3 W+ M7 V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 C, d8 s: z0 g
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 x% A7 j4 @( |9 D0 p3 A
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! ~, y9 C V5 s- o6 r I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) u! h/ y4 w4 ~ L5 `9 p
MCASP_RX_MODE_DMA);
7 t/ c2 H# D i3 Q+ GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" b* u" q+ E0 l, \+ ?) g VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; \* p# _9 Y4 i8 a4 [McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. S0 P4 A/ M: _) h4 O* [/ mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' ^' v0 e. H) A% Z& s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 R/ N5 J" A" kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# h6 Q4 h- ]* p/ l0 E3 MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 s& q1 x+ L# E/ t9 sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : w9 B" _2 R/ @/ }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& z7 y, P3 ]! m! J8 w0x00, 0xFF); /* configure the clock for transmitter */
% e5 A) G4 C, r9 {% U3 s# l% @/ pMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, j2 W% C" y7 k7 g$ Y# y# |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. N0 ^5 P- `1 O2 `9 ~( MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 [; U& ^2 n( X) r4 O2 \ Y
0x00, 0xFF);
# u T! h* J8 c8 F/ e4 E% L: i ~7 d C& C' A& t
/* Enable synchronization of RX and TX sections */ , x0 p& A" L- v4 k; z& I1 F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 V% t. s% Q$ f: G. h7 C, R- ?9 x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 q: a8 _% Q% |$ K- d& U1 N) iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 G; t0 E+ T5 I: K
** Set the serializers, Currently only one serializer is set as* s7 K1 _) \- x$ z/ \) K
** transmitter and one serializer as receiver.) L5 F# u/ J8 s/ n2 d
*/) {0 O, a$ K" a: {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: c! R3 I! V( E+ c5 c% y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ ^7 }' C3 d$ D: p c9 _6 Y
** Configure the McASP pins " \# r; ]7 e* v8 k9 U
** Input - Frame Sync, Clock and Serializer Rx
( d# [* K% i( C9 Q! U** Output - Serializer Tx is connected to the input of the codec
1 N+ }% F2 n& X: \, ~; M( z*/9 g( n! G; H" K+ A, t! F& Z! O& O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: g3 q' s4 {& {3 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));" f( A4 H, r Z' k4 A' i7 x
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 M- s* @3 H' O0 g
| MCASP_PIN_ACLKX
Q, ~3 h6 Y0 z% p| MCASP_PIN_AHCLKX3 p* `3 }* s2 ]3 y, ?! [0 D
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" U* O' b' D) b+ G$ kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, F+ X/ B- ]" \* u' }| MCASP_TX_CLKFAIL $ I) n, N+ D+ k+ \: h
| MCASP_TX_SYNCERROR. ]% G4 l" L) l& F" n0 v5 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR % o+ L0 u% x1 g0 w
| MCASP_RX_CLKFAIL
% U8 k* t. b5 N# B| MCASP_RX_SYNCERROR 9 g3 s. a- E3 T) E6 U+ g: b
| MCASP_RX_OVERRUN);- w! L' F j* m
} static void I2SDataTxRxActivate(void)& _/ [* @) ~) k: d: \
{' L) P9 N) z* q E/ |) t
/* Start the clocks */
; |% F7 O9 X+ Q$ u6 W% w$ L, C7 O* ]9 W& WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% ~2 F0 p/ k" W6 `1 b# z0 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 Q1 Y& r) i2 R' k: a; n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 H3 `1 [: t' t/ J% X/ k" LEDMA3_TRIG_MODE_EVENT);
2 j3 a0 R- y# }% F5 T* KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % f& R' J( x( g3 E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. _) Y5 c. g4 a4 b
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# V4 z& ^2 M# U( e% O- e- b7 ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
A+ [# [( s2 i1 I6 gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 ^' e4 H8 B4 m3 C9 z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 n( p q/ F+ ?2 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' V0 a# [3 m: r8 B: P
}
# Z( i" J+ ?# C, j- J9 X# v/ B9 l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 O/ |* P- P9 p0 d0 g; ^8 c0 i" ?
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