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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 M. B0 U& p' M$ A+ p# C4 binput mcasp_ahclkx,0 i# m; E6 z0 O( \4 P5 d
input mcasp_aclkx,
- Z8 n! @' n* s- }2 }input axr0,5 ?$ s X& D& [6 z+ P7 E
5 _1 A E6 I) [: ^. z; q! Poutput mcasp_afsr,, Q+ D5 I# d. [* r" ?7 p( D
output mcasp_ahclkr,! {) d" U3 N/ W* Z
output mcasp_aclkr,
8 K7 N" F7 b( ^output axr1,) y" J# ^3 @, m
assign mcasp_afsr = mcasp_afsx;
/ t# r5 _6 W# B6 A7 f9 yassign mcasp_aclkr = mcasp_aclkx;
% s% K% V) |8 R5 `9 d) g2 H g7 oassign mcasp_ahclkr = mcasp_ahclkx;$ s1 h( z- F9 K1 f6 T( \
assign axr1 = axr0; ) t9 E, w4 N$ g/ a2 Q4 ]
( |6 x% f" [( l F" g |8 D/ n. @- G }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 A3 h) f# m) _static void McASPI2SConfigure(void)
) U/ d1 o5 _6 r9 d{+ Q( {+ G: V, b' i: X# w e
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% j. v! m* Z+ W! G3 O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( J+ D( p& q. a/ t1 c. U/ S4 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 C6 S' B& s$ w5 w' i# x+ IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */ `/ D( H4 k" b) e9 g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& r: T1 y! Y' W- zMCASP_RX_MODE_DMA);/ f, L) Y' }6 X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; a: v2 F, A6 q4 Z' i: h R! C# b) eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. p* X2 J! L( G( J4 Z0 v$ w+ HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ R$ n9 D( Q' h* l& F1 rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ W4 c# a& v/ h# XMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 l+ u8 `* \/ f, K- W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% y' _8 A& |/ X7 Y1 @% v8 R- LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. R B- o; o( u$ m+ N7 M2 q$ K! X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, R6 @2 }) r! g- g+ zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 } i, h1 }" u8 V+ S( |
0x00, 0xFF); /* configure the clock for transmitter */8 X# v5 P# k1 v/ j( M k }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 K4 C4 E! ?: O. D- e3 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 L/ x' p2 D, q$ J) hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' Z6 a3 X) X+ I& \( \0x00, 0xFF);# p) Q4 z7 N, {$ I- {
* c! F$ Z" ]* \# G) c" D: j
/* Enable synchronization of RX and TX sections */
. X" A! w* P& Z+ u& |2 o/ CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// C, d3 C; g3 Q6 O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# ?( U6 N( r+ x. JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ ^$ G1 F* n) K3 x: x** Set the serializers, Currently only one serializer is set as
& F; |; f$ b8 e. D** transmitter and one serializer as receiver.
! @% c$ H1 c, a* G+ Q. j*/
+ _/ b) ]& f4 {) G! iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; I9 n2 |5 B. X# B6 j' p: z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 ~/ ]' r& U: W. K2 _! c0 z6 t5 e** Configure the McASP pins $ g1 y. _' M* }8 R& E/ C. \2 V
** Input - Frame Sync, Clock and Serializer Rx7 [- P8 d4 U7 b9 L# j% S
** Output - Serializer Tx is connected to the input of the codec , v r& Z% h5 y$ i) ~
*/, j. h& `8 L, b: ^6 I# R+ o0 k( j. Q; z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. p4 s' c0 k5 ?; \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, r) k: B: ^& A% jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 c! X- y) K. o| MCASP_PIN_ACLKX
4 ]2 }$ {2 x& J1 J8 i3 D( b4 _* k' Y| MCASP_PIN_AHCLKX
! p7 L2 G9 y, v/ l% g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 K$ A1 R3 P+ H8 o. W2 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 r9 U/ _6 n2 x| MCASP_TX_CLKFAIL
, _8 p( T8 M2 w0 w% y| MCASP_TX_SYNCERROR
2 k( R& E- G6 Q r5 |% J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 L' y6 S: h7 D% X7 W! s| MCASP_RX_CLKFAIL- ~' H6 {+ B8 }1 E2 Q( T; k0 T" P% h
| MCASP_RX_SYNCERROR 6 z/ e. y L' ^7 g
| MCASP_RX_OVERRUN);( B x. }$ C) ]6 R5 l3 h1 T
} static void I2SDataTxRxActivate(void)
9 ?7 }# R! C) g" N{
9 f; E5 G1 U: y- c/* Start the clocks */* P: u @4 n2 x, A4 m9 y D
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 ^$ C2 d7 j5 B# g0 q( z0 R7 [, \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
N8 C2 j! n: x# `' ]8 j+ |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) C/ ~) `6 X, \+ g% e2 r
EDMA3_TRIG_MODE_EVENT);2 T1 e( _& a6 d7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* S- c" m' }- R) _8 Q' V# ^EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 {' r; y! V5 ?! c$ Q) A) dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, C7 M+ C. [4 P9 j. l* q5 L" _' e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
/ [! I5 a9 z1 G/ _( gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 D! G. R1 A4 y J+ }3 M( Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ r; ]" X) M x7 |' r2 p uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 E, r( v+ A% \- z* b
}
+ D0 x0 p7 i/ y0 ^ k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 a/ c: o, N T; y/ @7 n
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