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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; ^0 z2 d& e) t9 D
input mcasp_ahclkx,8 ?! W9 S% {3 A8 I- D9 R% C0 m
input mcasp_aclkx,
7 c& ~2 ], `/ ~+ s, a4 o6 _input axr0,
, W3 l( j2 w+ f( p4 C8 B; q" {8 @" Z F$ h) v e; [% V; c
output mcasp_afsr,
6 P5 z; ~7 F R' u# }output mcasp_ahclkr,) A; z3 P) b) n- S( D1 N! q0 r
output mcasp_aclkr,
8 H- w! q/ r1 z* N* j. G' G; x% ]output axr1,
2 w: M7 g; I: ~) J2 X/ c assign mcasp_afsr = mcasp_afsx;
3 ^* s( B. H' r7 R' P9 h3 ?. passign mcasp_aclkr = mcasp_aclkx;# @! B# \+ U' S7 T ~9 p) \
assign mcasp_ahclkr = mcasp_ahclkx;# k; d0 v: h" x2 i5 Q
assign axr1 = axr0; ! o* G" g6 x- b5 k3 K }
/ G1 S* V Z/ @7 P2 i0 O7 @! Y4 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : c5 M c2 Z- w; T1 T# H, C- K
static void McASPI2SConfigure(void), _1 A* N8 V/ a# {/ w- @8 Z& X4 ^" P
{7 S4 C3 Z* |4 M0 N- f4 ^7 \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" ]3 l8 P2 d( \2 X3 S# aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. O5 H' T L$ I/ Z% c" BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. k' C; ?3 q3 P: ~, CMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 R3 Y' h/ k6 B' Z0 }! g5 p+ P. r+ Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& A+ m' ~$ ~, r# ^5 {8 j# sMCASP_RX_MODE_DMA);
, l3 [1 P7 K; X3 zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ S2 ]8 l4 }! ]1 u1 q! h! YMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& A7 e! n( S0 c0 F, y/ w* XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . @0 c. M9 M% V. c3 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 m2 \1 J8 D. \' E, \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( }& {2 i2 N2 u$ p4 A# a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 f, _2 F3 O8 G5 ^6 F+ [1 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 E9 T2 ]. o' O3 [ i/ }- qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & U% q7 E. m4 l" e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( y7 m. Y5 y) ^* \0x00, 0xFF); /* configure the clock for transmitter */
* s- g) Y+ i8 s9 [McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& P8 D! i! L* [) o$ @" W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 }" V: x1 N/ v
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 [$ Y9 _. Y, r; g `+ y
0x00, 0xFF);. u' z1 x K, K% P( h( F Z
- ]* H* ~$ j( U. ~
/* Enable synchronization of RX and TX sections */ N! A+ a2 H0 z" H; c$ I$ g. `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" H' T( b5 }& C0 _2 h) s4 U. M: A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 G# q3 Q0 E% u/ I2 B' w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 f5 `$ J, {, J, f2 t
** Set the serializers, Currently only one serializer is set as5 M% ]' }' \+ D, P
** transmitter and one serializer as receiver.- }; C2 [9 r) `7 V7 Y3 c
*/
) r" z0 i F) ?# j. N% I% }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ Z a# N* l0 ^0 R4 @9 qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. a7 u) r+ i+ h( m, Z E7 [
** Configure the McASP pins + f' ^7 i+ K U/ M" {: G* u
** Input - Frame Sync, Clock and Serializer Rx
! @$ C+ M3 q/ e0 H** Output - Serializer Tx is connected to the input of the codec
+ {" @, j/ `5 Q*/
) v- C; x8 o; A) p5 xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' x' s1 p) T( ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 Q6 J8 z- L7 ~5 Z+ f& z9 L9 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 j+ h" J* C9 G' j# ?4 Q| MCASP_PIN_ACLKX5 _% a) c) u% Q+ n
| MCASP_PIN_AHCLKX, T- ]" b; [) G' G- |' v B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 x9 y5 s& M2 O) |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - C' F8 E a5 t/ W8 Q
| MCASP_TX_CLKFAIL 0 S) C2 H; {: L6 }7 E" L5 R8 w) q# S
| MCASP_TX_SYNCERROR" ]4 w8 [; i6 R- S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: W/ N9 I1 R6 j8 Z3 s7 A| MCASP_RX_CLKFAIL
4 e4 |# k+ z8 ^| MCASP_RX_SYNCERROR 1 A; P+ F" c% B: x& {
| MCASP_RX_OVERRUN);
7 d4 z& T+ F$ T} static void I2SDataTxRxActivate(void)
- J4 d M, R( \" m+ U6 C) B' N{
- ~* ]5 z0 T7 V$ L/* Start the clocks */) I, W8 b6 q+ [! J2 a) E9 f5 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 |; ]( ~/ z& h9 S. W, s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- I! j3 r; X" E8 `# t( u0 ^$ iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," M+ \; V G3 S; h' F, [
EDMA3_TRIG_MODE_EVENT);
/ ?' Y- |' t1 Z& p* s+ [; nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( |, i* l0 ~$ D, m* B. \. B) G7 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, ]4 @" T* u# j1 w, E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
E% s$ T1 @# _6 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" y; e! W1 p( U7 A- jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// b8 s3 R2 A; g- U' X+ u, d: W( ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) d9 L/ b4 M+ z6 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 {: _# E1 f$ [7 f" R}
/ a$ T8 \1 R: x4 f1 p, r: v+ d8 t U( I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 w& z# f3 o4 s/ J1 B# Z G- m1 _
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