|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 Q: V& N* d$ }2 Q% g4 q
input mcasp_ahclkx,
/ w5 g1 V% k: yinput mcasp_aclkx,
% B; j/ S1 i5 U I# { ~: zinput axr0,
! H- t% a& V- H: I4 w) G0 U* l5 s$ d X9 ` h: g
output mcasp_afsr,
4 }4 H/ F. l2 T1 A4 P; j" y0 youtput mcasp_ahclkr,' B' ^9 z# Q' |$ l' F0 @) H, _
output mcasp_aclkr,
( j" l# b- |6 e& s! x& s! \output axr1,5 D! d2 E+ r/ T! k
assign mcasp_afsr = mcasp_afsx;
" I9 o& r% N8 {! h4 P$ M6 hassign mcasp_aclkr = mcasp_aclkx;
/ O/ T& E! T- Q3 u$ x, ~2 ]* D$ cassign mcasp_ahclkr = mcasp_ahclkx;/ h; v- n' J/ y% N Y& ?2 k% ~0 O: b3 N
assign axr1 = axr0; 2 o2 a9 ~. U' c
6 \* w4 E O! {$ T5 h$ K* s! l4 ]- a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) f8 d0 h! d" f" E0 N
static void McASPI2SConfigure(void)
/ O# O* B; s" B{# }+ Z0 P. e0 X& x& a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ A2 D7 u# }' Y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 M2 d0 d9 H+ w6 }0 ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 m9 {# H; i, Q2 V$ M, i. LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% {4 v) U$ U% J6 @; K l. rMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) N/ w k+ p! Q% N+ [+ N5 E( H" @MCASP_RX_MODE_DMA);
' c. }/ H# O: s3 u lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ v9 P( m- W" E% @; e h5 ]% Y0 uMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, ~6 F# D/ z! F4 hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 C; b" }- a* y2 ~- \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# {: H3 F1 w6 G( K! `% \' Z, L8 T* sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# S5 n0 ]# _& U4 f% l2 OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* |3 R. @- f! b& g3 vMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 @4 m% v" g; m9 XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* B1 m: D$ }% Q& GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 |# r& O4 P2 f& m1 c6 |0 R0x00, 0xFF); /* configure the clock for transmitter */
2 g3 q8 `& |2 f4 q- EMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* |$ ]1 t/ I/ r' K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - m, j/ X- ]( s# d* [1 p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# s0 s/ ^2 c8 A! v+ f( ^: y) d- o0x00, 0xFF);$ k! a/ E9 r. P# l& k
* u! O5 R. D' V& m4 Q" q, L
/* Enable synchronization of RX and TX sections */ 0 r4 Y5 f& r. H) W! h2 p V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, r) V! f' p7 _( F" t w
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. r; d' {& V( d9 [! I+ HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 Y( N: K" h- c3 r; R J" g2 N" [** Set the serializers, Currently only one serializer is set as- j2 x/ W; {) Y# D: F y8 E" b# T+ E; y
** transmitter and one serializer as receiver.! R( h9 d* L) F- E
*/5 Y) S* a" h6 O q' s5 ~6 t$ R% W* ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. m. G5 p' X% X: \' x$ DMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. r0 C5 \6 e& b0 o! k
** Configure the McASP pins
& E9 |' D3 A- w( }1 P** Input - Frame Sync, Clock and Serializer Rx6 x! Y) T u. q$ ~8 B3 o8 R; u
** Output - Serializer Tx is connected to the input of the codec ! }0 z4 S% P( e/ T1 `0 ]7 ?/ H
*/0 o$ q o) V" E8 P6 U6 |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 w0 {' z) |: M# P: n! s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! J# T% b4 m$ u. j" KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 P: d) @" B( ~3 U| MCASP_PIN_ACLKX
& ]0 ]& c% O* b J6 M; K5 L7 W| MCASP_PIN_AHCLKX
# \+ I: A) u- ?. F. A| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
' a3 t) b G. h N' q; L3 x5 OMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / |. y) u+ s/ j1 l% S/ ^5 O7 O" J
| MCASP_TX_CLKFAIL
% {; M8 f5 D3 d% g* ^| MCASP_TX_SYNCERROR
4 M# [* A9 c/ I+ W% N, Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : a* I: O+ z. \0 {6 e2 J, E+ T
| MCASP_RX_CLKFAIL
) l9 K H5 Q3 N* F| MCASP_RX_SYNCERROR : j, D. K. b& \6 ?
| MCASP_RX_OVERRUN);# l5 U" C# M, L! S7 I
} static void I2SDataTxRxActivate(void)4 p' J- b1 T) G
{
, |! K% @" Z8 S/* Start the clocks */1 a4 W$ Z& r' ~1 t! ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 l" I. r- A& I' u/ y! _9 e: w K; O
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, ?" W8 e4 f! x) p" p! p$ K) N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 w7 a& q! ?& ~+ U* d7 l9 D" ^4 b& mEDMA3_TRIG_MODE_EVENT);
. s5 p9 n8 i/ n; XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) y& d! I$ p) w2 d7 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ y& ]+ q4 L2 v+ Q7 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
5 j$ R8 ^& R' K; |/ B' ]% s4 w7 \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ g# D# a3 r6 ~# Z! e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ I7 y9 h& `- b, n P; k- Q( t* \McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: @+ l ^" h& c% m" {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. o0 q' O' C0 K$ X
} 8 D5 y# P7 I. n' E- A' i3 T w5 J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; R! R& |0 z& Y% A4 W* O
|