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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
S! j# g9 k J, F! u2 Y! Uinput mcasp_ahclkx,
3 v8 u) U* v3 W6 Q( ^" r, einput mcasp_aclkx,6 N, p7 G8 Z5 E- S9 \8 G5 e7 _
input axr0,2 q7 X2 @/ L. a( D! i
, m) s0 w1 g- `* G, `
output mcasp_afsr,
; n& h! Y, m$ U& u) Koutput mcasp_ahclkr,
0 a/ Q$ c) N6 R Goutput mcasp_aclkr,
) S C2 s4 D. u4 x) B4 m5 joutput axr1,
2 _" n1 d4 X! r- V assign mcasp_afsr = mcasp_afsx;& }4 q$ \3 m3 m+ F$ l* a+ z. u) J
assign mcasp_aclkr = mcasp_aclkx;' c( ` u/ F$ j6 G. ^ s
assign mcasp_ahclkr = mcasp_ahclkx;
) h' a/ c- I7 Rassign axr1 = axr0; ]2 G7 ]$ X$ ^. {2 [8 m/ s. A1 e
$ h3 J8 H; h9 e- `, L' O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* q" L1 M9 W/ b" Q- b4 h" }% G* \static void McASPI2SConfigure(void). U4 C- u- [. G; m1 Z; d
{- ^4 z3 a/ t; ?, M, _. @0 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);( V6 y0 u# w/ ]0 A6 W+ @) E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ p' m0 f1 [. `) z. {/ mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 E; C1 Y2 E) H$ c) d' X0 o
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ Q! J$ O: g0 L& |, w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' J U( \# ^1 u1 ]! K$ w
MCASP_RX_MODE_DMA);* g) }) @) u& r# h; H3 G! o" y# u
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) d5 }, C6 @. n6 A+ Z: c" c
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ z: I- I1 M3 G F8 kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 b( P+ K" P& ]& @1 t- H' g- WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 T& L& `3 V# v% h- s* W A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % |' `6 [8 m: }. y$ s% I" j9 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# q% o& x# ^; _$ s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' O- E0 @( N% P( A% I1 O/ @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / c. y2 c$ i) S& y5 g( e3 s
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
, x) j0 r( M, Q6 B8 ]0x00, 0xFF); /* configure the clock for transmitter */
/ I* W; j5 g: c, L7 L; o8 d: zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, Y7 p" X }" T% M3 B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % Y% Q: z# f3 L9 }2 s3 |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% h0 ], g: U7 }( y) k- h3 _
0x00, 0xFF);& u( C) {2 y- \# h; p/ n1 \
! d2 }2 l& O; Z8 o/* Enable synchronization of RX and TX sections */
, \; i2 d5 n* t* NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) b/ ?% n, B& d; N) Y. s
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ R6 I+ y( J: h8 v5 l
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
G# {+ v: Q) G9 v* N** Set the serializers, Currently only one serializer is set as1 C) ]$ J" k8 E) ?. \! ~0 v
** transmitter and one serializer as receiver.
/ i7 J! Q; w m* m+ _* @9 p*/
8 X" V' k6 E* I8 r0 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. | i0 l2 K" O9 F6 SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ I* B: H4 V! V( L1 V4 E** Configure the McASP pins + `2 @2 U, i; r/ P/ U7 _
** Input - Frame Sync, Clock and Serializer Rx2 _" E Y- C1 r" Y5 G& N0 G
** Output - Serializer Tx is connected to the input of the codec 2 h" m' |, m8 f8 H$ Q6 s" ?
*/: X- o+ X" i' k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ X O+ `( Y" B, q2 {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- d& |+ {, B) p. WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* F |3 B* I) x7 ]- u' ]| MCASP_PIN_ACLKX
" ]- @9 s3 T9 ~/ w7 e5 m b# I o| MCASP_PIN_AHCLKX
- U/ n8 h. c6 k" ?& M& G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 y) q+ N* Q( @5 S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( L6 s( G% @% [ @2 ~$ \# N) v( Z| MCASP_TX_CLKFAIL 8 x, s6 e0 R1 S* _" L z2 h& l
| MCASP_TX_SYNCERROR
) o. V9 n$ D5 X) { d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: n4 N( l. @9 z1 H| MCASP_RX_CLKFAIL8 x1 i) L1 D9 G7 W% r9 W# Y
| MCASP_RX_SYNCERROR * |' ]# k2 M/ U8 \" F3 N
| MCASP_RX_OVERRUN);' R1 H* k# L) G
} static void I2SDataTxRxActivate(void)
, `9 l/ y1 [" U9 {$ u& ]{3 j$ @. ~7 h8 J) ~! H
/* Start the clocks */
: M" j& K( I/ b6 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 s9 U* i V. J. U& ^6 k hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 G. C: ^5 A, C0 b- m
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* n! `* _% [! u9 f. Q7 v& e V7 @
EDMA3_TRIG_MODE_EVENT);1 @3 S8 m' q7 c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" l7 ]4 s1 ?" [" oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! A- f4 _- P. |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 N$ ?0 X& ]7 e% I8 p5 ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! i: \# `- \; A" }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; Z& `. b7 x, l0 [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. z; ?( T1 \$ g" L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& d. i9 T& f# m8 y+ z} / G4 x% m; h( e! i2 M
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. D5 z" G* m8 O8 I
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