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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( f l% s0 w0 ?8 v3 [- v& J- u. S# xinput mcasp_ahclkx,& a1 y3 k1 f0 {
input mcasp_aclkx,
+ R; r9 m) e/ I8 iinput axr0,- _& u2 Y$ G6 L
% r* M# Q0 y0 \* [$ Q4 Doutput mcasp_afsr,+ r% \. g$ W% L" Q% {! o; J% u
output mcasp_ahclkr,# }. z$ A g: X- ?1 Q! L; H
output mcasp_aclkr,& W/ P* G0 |1 `7 S I' t" G. J# `; r
output axr1,+ a! Q* i- z: _) \0 Z
assign mcasp_afsr = mcasp_afsx;( Q' |9 {, e7 t) P
assign mcasp_aclkr = mcasp_aclkx;
" h0 q3 u2 n9 W# m! _: L% A6 Iassign mcasp_ahclkr = mcasp_ahclkx;
; c* A, B$ S0 Z: hassign axr1 = axr0;
* m9 \# G' m8 r3 r+ |
# h4 `. c; n+ x6 ?6 E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! N/ B3 Z- m Y
static void McASPI2SConfigure(void)0 W/ X0 y, h6 o
{
4 w2 \5 Y" c$ w, L& rMcASPRxReset(SOC_MCASP_0_CTRL_REGS);/ E- e% @$ x2 E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ y8 G' j3 E& W5 P* nMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) R B! w3 q; W! C3 |" s( B
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 U* A8 a0 _6 a$ N8 @- `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* C, g* p7 P5 t% F G: wMCASP_RX_MODE_DMA);
* Q' ^; w! c& u3 F+ E+ Y4 E3 zMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& I J4 k8 j6 z# f2 n0 r; C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* w1 _+ a/ J X0 L$ A
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 \/ ^3 l5 r. h0 ~( I+ A) Z/ x- C0 W* |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 M+ R( p9 p/ X7 o+ u5 B5 ]. }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
O. H [8 S, H0 o& gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ j- T% Y3 o7 }! |# g0 VMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' {1 P8 g Z8 r4 z7 J0 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 k! N1 Q7 e. EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ S; b, j4 u" F; L0 t, r/ Y0x00, 0xFF); /* configure the clock for transmitter */% |6 E, ^! d8 s! |* R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* b- b1 {$ V# R' y. _
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; A/ W4 ?* B. j- l4 G0 x2 S6 d
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" E4 U4 ^: o8 j% r+ `2 K0x00, 0xFF);! L; z( T7 F. G; ?( |% t/ C8 p8 o
/ z( r4 f3 `# W5 ?
/* Enable synchronization of RX and TX sections */
; b" l ?6 w3 k8 D+ |. iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 L! \3 y' ]- o5 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 d; ]8 M. T. c5 Q% ^1 \; ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" H4 y/ h; r1 {1 t/ L4 E** Set the serializers, Currently only one serializer is set as
6 Q0 ]) P' f' b7 T& g6 H** transmitter and one serializer as receiver.3 ?2 v. Z6 r( N5 s% m% c7 Y+ m1 J
*/
/ k7 i x1 m) f l/ m! \! [+ UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 k7 k' P+ ~1 q5 ?% f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. E) u2 K3 k7 r
** Configure the McASP pins ! D1 E5 z& _' W, J
** Input - Frame Sync, Clock and Serializer Rx
$ \% z8 v7 K6 C0 a |4 x** Output - Serializer Tx is connected to the input of the codec
9 t! X) O }1 b; V5 D- M1 W! @*/$ u4 R$ j* b# k
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 X$ ^; A# k# r5 q0 e uMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% O' ^+ i5 E. Z. N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 N0 |6 m4 x# L {2 ]
| MCASP_PIN_ACLKX
6 x9 `; @3 h4 K6 r5 J& w! g| MCASP_PIN_AHCLKX
7 S+ W8 l( G3 _- p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: t/ _. |# h( r8 y* TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 a# _+ I% \5 [# q% l3 X3 W| MCASP_TX_CLKFAIL ! K" a$ ], _$ G1 x8 ?1 b
| MCASP_TX_SYNCERROR
. q2 e! B4 q* x5 b| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ G' ^% Q8 s- h# T5 |* \" A| MCASP_RX_CLKFAIL
% u4 e: y5 _9 ~- _* H| MCASP_RX_SYNCERROR ( N w6 n8 L1 o1 q# ]# a
| MCASP_RX_OVERRUN);
! k+ N1 o- [! b9 \. q. |5 Y: T* f} static void I2SDataTxRxActivate(void)0 m* H0 X9 m8 [& X4 c
{
* B/ _6 {- s B: f: x+ G1 M/* Start the clocks */
! W+ K# X( H1 A; VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 q% n" F* u( T: j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% }9 I1 I! v1 p0 z3 R5 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% P) {( ^' h, \% }# @) j7 SEDMA3_TRIG_MODE_EVENT);! a& Q* @# i: A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# X; `4 ~: a: e: S: a. REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& L, `# @5 k$ k3 ?+ NMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
* j3 S+ M, j" [* P! r% K. K8 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 K9 d/ Q6 \' F
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, F/ V0 @6 p/ T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 V' s5 A6 Z" J+ R" K4 I- n% sMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) K; v' O9 e- K4 ?6 p}
* ?; X% a2 Z/ z! Y3 R7 P9 g& e6 g6 P请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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