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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: E2 K2 f2 `9 a4 T4 m" |: f! Dinput mcasp_ahclkx,
" o5 W. Z5 P" Pinput mcasp_aclkx,
0 b# L& e0 c Y7 Linput axr0,
3 A8 j& D" l) Y% q6 F3 ]7 s( G( f# ]# H# P' T% F6 e. O
output mcasp_afsr,
1 a) b: S( E6 @% U/ y" l. ooutput mcasp_ahclkr,, V! d, [. L. ?& X
output mcasp_aclkr,) H$ r6 A! |# `4 ]: {1 u
output axr1,. _5 v1 B) a }; {, \
assign mcasp_afsr = mcasp_afsx;
) i- ?8 C+ c8 @' ]: gassign mcasp_aclkr = mcasp_aclkx;9 z$ I9 m& J. ]( m) I1 n
assign mcasp_ahclkr = mcasp_ahclkx;1 w' H7 B1 q$ U% I9 A
assign axr1 = axr0;
* o. w- X5 W3 e0 o! ^; I0 r
" }+ C3 z+ n& M) L$ b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 w( e% n1 G4 L' V# n9 e
static void McASPI2SConfigure(void)* i& A, G4 |& [6 m) ]& l% E
{+ N1 Z5 R% \3 V; b: ~* |, X( |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 O# y0 R( D! G; w# \: d: X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
2 a. C4 R6 [3 SMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" R9 X z' \) b- I& L. gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 K0 p4 g6 J* ^+ m8 P0 lMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: z) N* D# u4 k! r: |2 uMCASP_RX_MODE_DMA);
q; i j8 K) R' [4 X. Y+ yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' Q# e9 ?" x9 v- y0 IMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 _6 ~5 ^* y: ]( v) B
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) k% N8 _7 I8 r1 J& a {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% t( j& w0 a' K: R/ D$ E1 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 T0 N1 s4 ?& ]. X" R; x l+ L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) i. h" ?' @6 ^5 X- bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
2 F+ `, q" ]- r4 TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 T$ a+ L/ m0 m! c6 y6 ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) k6 s) ~& B# z+ z3 h
0x00, 0xFF); /* configure the clock for transmitter */
% g/ `7 i$ e+ B. J* \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); a% T# ^1 ]+ e5 Z% A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( q' j) d$ u: y$ BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& S+ p. m7 T2 k. ^9 j+ ^
0x00, 0xFF);7 ]" V' t- Y3 Y: q M
& _: r/ z6 c! C. g- a/* Enable synchronization of RX and TX sections */
7 H) O# x8 U3 A/ o5 [& rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 }1 I R' _, j. VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. ?. q+ z9 N* V% H1 _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; }6 V4 w( K) |
** Set the serializers, Currently only one serializer is set as/ A M6 p4 r- q4 g7 G! M; q: K
** transmitter and one serializer as receiver.$ c' |/ W9 k/ \
*/
U: p2 s9 a" B2 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 A4 c J' I0 l+ h7 z: M$ h. n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 g7 ^* c t7 K' B! w( k& {
** Configure the McASP pins + w1 |0 N$ @) Y" J/ N6 e* S
** Input - Frame Sync, Clock and Serializer Rx
7 }- V5 `( R5 t4 [* N' T: u& ^** Output - Serializer Tx is connected to the input of the codec M0 r# h; G4 P7 K
*/: V2 w0 z* ]' t/ A; n7 [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" |3 ^. M' u2 Z1 h2 e: Z* @# ^
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: }, V/ k; p! G& D. |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 A" b& V) E X+ B
| MCASP_PIN_ACLKX8 p& _9 A: X }% ^3 F E5 _
| MCASP_PIN_AHCLKX
* F# K7 p' m- I- E- _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( u- ^8 u/ z7 F8 q+ x: a/ K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ K: \( @' A) A$ l/ s; q; e
| MCASP_TX_CLKFAIL
; C a G1 w8 H4 z' u" D# N+ W| MCASP_TX_SYNCERROR1 o5 c0 I- ]. a6 ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 ^8 m- U, Y* W- F6 j
| MCASP_RX_CLKFAIL8 @: ~( u$ X, z/ o! x
| MCASP_RX_SYNCERROR * ~- B! F$ W! i
| MCASP_RX_OVERRUN);
. W' z; G& q4 i7 E} static void I2SDataTxRxActivate(void)$ i! W) e8 d! X- }* p
{
) z9 y; t; l7 G$ C/* Start the clocks */6 W8 y- L: b9 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ U! ]: G/ K& i. H$ E; KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: |' x. @* d2 C, Y: X) T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 A! S7 e. t) S' _+ l* ?
EDMA3_TRIG_MODE_EVENT);
+ V0 u) j7 S1 j9 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( f! g+ [2 t& O
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 a$ k9 D9 a. r) K- z. X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( p& w0 G k* @" n. n7 wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, ]1 ?! |# o% ?% twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" U& q! j8 n9 j0 t5 s) ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 ~" d2 U% q) M" y" U' ~ j% a1 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 r8 \3 u, ^2 l% g% u8 A
} ( R% u* y6 l% b) A+ p
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( e7 B' O4 k; O, n
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