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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) Z- w7 w& K( I5 P q
input mcasp_ahclkx,
8 S$ g# o* S9 H4 m1 qinput mcasp_aclkx,
2 H* M# `# s- ?6 | D# j' `& Zinput axr0,
& ~* L6 c$ B; }( |2 m: s
# s' r2 {( v( V8 o9 c( R6 ^ ooutput mcasp_afsr,7 @! w& f3 r- R; e
output mcasp_ahclkr,( N% s% |6 Z: y7 y" R6 J3 Z
output mcasp_aclkr," T4 w$ |+ J- M; F$ B
output axr1,
}7 A5 Z2 e& Q7 `) @' A assign mcasp_afsr = mcasp_afsx;; y: `, i+ u8 W/ v+ Y8 v$ N
assign mcasp_aclkr = mcasp_aclkx;
8 ?/ W1 h0 S' W$ ^assign mcasp_ahclkr = mcasp_ahclkx;5 Z, s2 n8 h& V3 q, z: g7 Z
assign axr1 = axr0; 3 D& j/ M$ h0 p3 h6 [% p1 k) X- M
8 m5 M- i/ f' ?$ B% F; {* S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' g7 C$ t, K% N0 f- u
static void McASPI2SConfigure(void)0 q% i8 e% j) p+ U0 U- v
{- r0 r# G/ ?6 o6 m# L8 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);' [% n0 X" @8 ~2 Z% \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ F( B$ C* a7 sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" M. }/ g6 [, n1 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ q% c4 J2 Z9 K0 A2 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 C6 V) F# ]( J7 j# ^1 T, gMCASP_RX_MODE_DMA);
\$ b! b) W# mMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( D& \7 [0 A. L" N( H( EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- C8 p2 E6 w c, r- GMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 ?8 y: c+ N! f# X& J5 u
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* [( f0 T; p& r T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 O; \! q; O4 S9 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# v- X5 }% L0 u j4 x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' q4 E' x, i$ P8 \2 M8 qMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 @# W, v+ U. M$ v7 ] K( b& ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# P: e; C4 z1 s* L c# U' ^6 Y' \0x00, 0xFF); /* configure the clock for transmitter */4 l5 l1 c( v3 [; N4 }) T8 ~9 @, q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' y" A B# ?5 r; C& s6 `" e, y! W
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 m v9 E( b; {' }4 P4 B$ s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 l* S8 k' P" K2 `0x00, 0xFF);
, E7 G6 K' b ^5 a2 G8 {: _2 D+ q/ I. l- T& @! Z' n* V. i1 H
/* Enable synchronization of RX and TX sections */ % `& B$ G5 Z* m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 Z: K; k" k% \) I- ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: D% D4 ~+ m3 ~4 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 [4 @, [) P f* t; S9 n- B* D** Set the serializers, Currently only one serializer is set as
* J" i3 |/ q, j8 k** transmitter and one serializer as receiver.* @# |. I3 c5 \% W% O$ R
*/* `3 W% T! a; z- \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# [, k4 i3 m( H9 j1 A1 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ B" z ^2 w0 m
** Configure the McASP pins 9 m! L, Q3 Z( V6 j! E! V+ l
** Input - Frame Sync, Clock and Serializer Rx" Y' d% Y" p9 V- E' o* \
** Output - Serializer Tx is connected to the input of the codec $ h6 y7 M3 A; N# K
*/; I6 |3 }/ d2 u/ T8 Q6 H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' z) G1 s) v, w- O! p! iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' {9 \' N% N5 @, j, q- l5 e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 ]5 c- S* W/ G1 b9 @| MCASP_PIN_ACLKX
2 g/ c# f0 S7 Q3 i% U- K| MCASP_PIN_AHCLKX
0 N* A# b5 D2 a! O: ?( n( x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 N$ b9 k1 [3 L% k' ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 G Z( T3 v% K( O7 J9 s| MCASP_TX_CLKFAIL
0 l% c' C$ O/ c| MCASP_TX_SYNCERROR
6 C$ K7 L+ Q: T. ]2 M) r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - G! A* \' Z( O) c6 M7 B/ G* B! j
| MCASP_RX_CLKFAIL
3 [" a2 @6 q4 L1 r/ p1 A) k| MCASP_RX_SYNCERROR
, U% S" s1 E2 C# N8 D3 S& H9 a. M- w| MCASP_RX_OVERRUN);. A4 i+ S' Y# w% {( j9 V
} static void I2SDataTxRxActivate(void)7 t* ]/ J: _* D# G+ j
{
4 H/ q. l2 ]" m" s, D' H/* Start the clocks */0 V& l& T5 q- ^& u
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ A6 q/ P( {4 U' v* {+ R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 j1 Q; Y: y. Q+ P+ I- iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, ?/ g' Y+ l* i9 i0 B% l' c- q
EDMA3_TRIG_MODE_EVENT);
. R$ R0 ?1 W" ?0 ~: \% CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , Z# C$ ]! e% |! I. U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 m( P; j1 b, S J+ k1 X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 S6 ^$ t7 U' P3 ~/ QMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- O$ u# s, R N7 z9 P2 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- h- U- a1 D YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 v3 ?' x; S: S" g+ X9 Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. }* i4 k3 J7 [" _2 X" W
} + g5 E' R0 t0 v3 ?" R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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