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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ I5 [- Z: n& L0 U1 j2 Z1 Y/ \2 t( H
input mcasp_ahclkx,
6 N- N" _* V& ?6 S0 linput mcasp_aclkx,
; c4 T5 m: |+ b0 { T: ]6 Oinput axr0,
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output mcasp_afsr,5 B3 j, Y* L) O. ~1 L, V
output mcasp_ahclkr,8 D9 V: {" b3 {; a7 c/ Q5 |1 y
output mcasp_aclkr,
; [6 F h6 Y: e3 i& ]output axr1,& f* b& _, i' u5 u, B# Z
assign mcasp_afsr = mcasp_afsx;
8 B: a# {' {( o# t# sassign mcasp_aclkr = mcasp_aclkx;6 ^( v' Z0 H. T2 j* ]2 D4 Z6 U+ l
assign mcasp_ahclkr = mcasp_ahclkx;
" O# v% K7 w' ]! rassign axr1 = axr0; 9 e1 p# s6 A+ }' O! a( _/ d
+ _9 }* G5 h: {; K* e4 ?+ `
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # |+ V( m! H g: m& Q; |
static void McASPI2SConfigure(void)
& |1 v7 J; _& t) k9 c( y{
: b6 i5 X0 O& l& V! E/ \McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 `0 Q; [# {$ H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' o, M8 y* s* E! K9 Y5 v+ iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, K+ D" Q1 o; n: x: N. ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 }" l: F4 ^. q2 M( ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' a8 V* I) d i+ R1 ^* n NMCASP_RX_MODE_DMA);. ~3 N8 ~) I/ d% b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ P) i9 T/ u6 h( m7 q }+ A( q% PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 z T2 O8 X. k5 d X* nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 ]: x7 ^7 y4 F2 ^1 `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" X' H9 o h0 X: Z, a4 t, l2 ~6 J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 W. p# b% j, d |; y& e% r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( t4 y' g9 W8 _6 ?2 q( n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- [, H2 M. W6 Y* d- o
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 {$ l4 U0 X4 i4 j- n, zMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! n& t' z$ K9 F+ u* h2 {" d1 _0x00, 0xFF); /* configure the clock for transmitter */
* U& V( A. I) ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 B) _5 [, @1 q7 Q3 w( N) @& b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 b7 m: x& M& @; qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! c9 K6 \/ s D6 l
0x00, 0xFF);
- `. b0 P4 @/ R/ x v
) }* k0 x4 j1 T1 |/* Enable synchronization of RX and TX sections */
' I# C- Q" \! XMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! H* l" F7 _0 zMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 ^2 J/ g/ G. j) ?) M4 _5 F
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" B# `5 M; G9 d i6 T; p** Set the serializers, Currently only one serializer is set as
_' ~( f8 v' A" K) Z5 \% D* a** transmitter and one serializer as receiver.9 k( D: L& r* l0 ^. M2 b& Y
*/' q W. c9 Z! u5 ?# w
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* t# f0 _# N6 b, ]/ D- H# g# hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! a2 [1 p7 c9 |
** Configure the McASP pins
6 W& M& J2 i; B/ z2 _** Input - Frame Sync, Clock and Serializer Rx# `/ n, R3 R! _& Q m( p
** Output - Serializer Tx is connected to the input of the codec & \: m- E2 F# @
*/
2 n; _2 m% h. o3 }& aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' H+ N0 \, w H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* M3 Q; J: N; `3 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
X" I" z, T3 p3 K. L. b| MCASP_PIN_ACLKX
9 ^1 c6 Z! A" [3 h| MCASP_PIN_AHCLKX: y8 l; a9 [. f+ g# C7 R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */3 P, p; {0 j$ Y$ c/ P3 L3 T7 L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 c. x) j6 ]2 p' q
| MCASP_TX_CLKFAIL & }1 b' S e, T8 X- A; x+ H0 T
| MCASP_TX_SYNCERROR$ w5 u; b, A' D# U @0 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + I2 E8 S# ^' c! u$ C% O' G J
| MCASP_RX_CLKFAIL0 _1 Q5 k( c% a9 K: n/ }9 \
| MCASP_RX_SYNCERROR
: T4 I( v0 k! A8 Z* k| MCASP_RX_OVERRUN);( Z8 |& {' u: ^4 @* s: F
} static void I2SDataTxRxActivate(void)$ @& u/ i1 R- t7 F* R! a% a: X, a/ d
{! _, t/ v2 t+ Q6 s5 W
/* Start the clocks */7 S- c, c2 F9 j- V, s f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' o* J4 f) H+ CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 b% y# s0 |4 [/ S6 T& N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 {2 {( {& o/ ?, z
EDMA3_TRIG_MODE_EVENT);, o' ? `& H. }8 v2 }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 G+ P9 o, e& ~! P! E* t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; ^/ P: n6 @" N; ~/ F1 b- h* @McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 `( B1 J7 m% X$ t3 H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( I6 W3 Q$ I, r* Y' wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- B4 [: a6 W/ F# n& A1 d7 P8 c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 U( x- x7 J% [7 c# W: t$ xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 k5 |- E6 U5 x) A} 6 F9 f8 k, q# k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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