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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ G+ x5 c! [- @; n, L: T g) o
input mcasp_ahclkx,/ X. e D5 [7 d. c* j9 a/ x
input mcasp_aclkx,
% A3 \( ]5 i( u" n0 j5 n' e( D) Ginput axr0,* G+ G4 ?& Z) Q) h* }+ U+ ]
( H$ r4 \4 }$ L" X4 n# `! u% d
output mcasp_afsr,8 Y- h& J6 c' A5 w' y5 d
output mcasp_ahclkr,. Y) g- A+ E$ L2 g: K
output mcasp_aclkr,
: c4 }+ V! i. \0 [output axr1,. m# C0 |: L7 P
assign mcasp_afsr = mcasp_afsx;
: L4 o- p3 B9 Eassign mcasp_aclkr = mcasp_aclkx;% ?% Q* x$ H) _. }3 T6 g
assign mcasp_ahclkr = mcasp_ahclkx;
2 O: a4 Q2 I, }' E2 Passign axr1 = axr0;
5 g8 {8 h [' i
& f) {; ?4 \& b' g! d% l- b' r. g在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 T$ D/ X2 \+ ]) O9 Bstatic void McASPI2SConfigure(void)
7 s+ R8 Y7 N8 U{% b) [3 D% Y! L3 W) U. M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 Z ~! C- w* n. w$ ~" gMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 k! q8 c# k2 k) S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ w9 |' _" o" W8 N* s% \/ U4 }
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 @2 f6 Q+ a2 o$ O6 T, e1 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ j: g# r4 S' J2 A" a, G; ^MCASP_RX_MODE_DMA);
0 v" R4 j f4 n/ CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 n$ J3 W9 `- L5 p4 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' d+ ~7 d7 Q4 WMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " Q% M7 p7 v/ k0 q* i7 [
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 g6 A# ^! @7 a r6 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 W" p# Z/ @1 o7 v# JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) ~/ O4 P5 j8 P H) ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& a7 ~ C$ j; B; G. t# G( VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ( q+ _; }! X) `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 n1 `! f1 f3 O4 y, @0x00, 0xFF); /* configure the clock for transmitter */
N; P" [$ ?7 t4 |* _+ M# w' |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 W N# l7 V# X2 h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ T7 I8 Q% @$ c+ w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ Z! \7 h& K& d; v0x00, 0xFF);
6 V0 }& Z0 P6 }2 R8 d
5 F+ W6 Q" `& V' q& T/* Enable synchronization of RX and TX sections */ ! C$ i4 D; b+ @- }& S$ r( R' ~! v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# H8 N8 G( x; j0 B6 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
s9 R0 `- u- u! m6 r- YMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ O* Z1 L5 I, B' x4 c" x4 r( Z** Set the serializers, Currently only one serializer is set as
7 F% i9 ~: I/ _$ a" M5 o** transmitter and one serializer as receiver.1 s8 E8 R; q0 J' |
*/3 R4 T3 _6 {; Y- h8 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& e5 @& P( L! y0 l9 jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; m+ J$ E$ y, k" q4 H- U7 O6 i
** Configure the McASP pins + f: @& U9 [% E, z! T+ Y. S( G( S; {
** Input - Frame Sync, Clock and Serializer Rx
0 {+ W+ D. U: y1 ]0 o! L9 M9 J, U** Output - Serializer Tx is connected to the input of the codec
* w& u. Q2 |1 T9 w* t) G*/
8 T! F. o$ d$ _' xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
' t: h$ K* j. g5 F; {" N; wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! y- J- |/ g0 A M9 fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 `% c+ \' e: o: e8 m| MCASP_PIN_ACLKX
$ x8 P3 [0 i5 D5 e2 P: ]| MCASP_PIN_AHCLKX
. F2 {+ j0 L0 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, q) I& ]0 a' W2 r3 w3 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' d6 Q! {# R( M* R; q6 q7 y7 X
| MCASP_TX_CLKFAIL
7 l7 s# G! d1 || MCASP_TX_SYNCERROR9 }. b$ B2 B4 q7 d
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! W5 m7 _! N" S3 D! k
| MCASP_RX_CLKFAIL+ D9 x7 s( Q- R/ C: T$ x
| MCASP_RX_SYNCERROR
$ A+ Y/ A3 ?% D| MCASP_RX_OVERRUN);9 I- |: i$ h: Y0 z% _. E$ A
} static void I2SDataTxRxActivate(void)
$ Q2 {4 Z4 [% _% v! J6 I! S{
; F3 M! U/ x& x% @* @ i/ s1 r. g/* Start the clocks */
. g1 `2 e- M0 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& m& K$ Z+ ]+ Y& X' ]( c% J0 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 m$ e7 P4 D5 w3 \! u- A9 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ H6 @' {. b, qEDMA3_TRIG_MODE_EVENT);4 g# Z# ?; w: ^5 z( w7 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: W! U8 t3 [. g" A" t7 d$ s: h' mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 I: U2 F( b2 o `5 I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);0 |1 q5 }0 B6 f# b% a! Q( F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: @( q3 _3 R9 p2 k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 R" J9 P4 S& B( s0 A! |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. d; i" |! t6 c+ B" k A! J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
W! K$ ]* u1 _3 m7 z# G3 u}
% }7 y5 h, h7 Z, P' o1 ?" [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * h$ y9 m8 |# z8 d( M* J+ v
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