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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 h2 h) p* ]* j: ~
input mcasp_ahclkx,9 q, e9 N5 l9 I' E
input mcasp_aclkx,
7 g9 ?! r6 b4 c7 h- U5 X' uinput axr0,
* K; _3 F4 B' n
" a- c$ c- c9 c' Z4 routput mcasp_afsr,0 J0 m! x+ p2 X& ?! t3 Z# }7 T) a
output mcasp_ahclkr,3 H+ d! J* N9 ~9 m
output mcasp_aclkr, F* t5 j$ c4 j. z$ q
output axr1,' v, Z3 G+ A$ R: j
assign mcasp_afsr = mcasp_afsx;; L& e+ \4 c Z: I2 i F
assign mcasp_aclkr = mcasp_aclkx;
5 t! N; r. _$ C1 V0 O! L# Kassign mcasp_ahclkr = mcasp_ahclkx;
: }5 }5 f3 d$ Tassign axr1 = axr0; B5 Y. Y6 ~6 _8 U
! l" k" S0 g( M; p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' i+ u! f- w+ v0 k, u
static void McASPI2SConfigure(void)
( y5 v$ t# R" G- E( m w Z{% n0 d! D8 x& }, _
McASPRxReset(SOC_MCASP_0_CTRL_REGS);; |4 X! `9 A- D: s% \ s: O8 J4 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 g: j7 p4 j7 V$ lMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 V& y+ E: u) T; c$ Q, x yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! Q! Z7 t) M. \; U) x3 ^+ t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& ?, c+ W5 z) S$ `1 W9 t6 P
MCASP_RX_MODE_DMA);
' V! w! S7 S0 I2 T k9 p) pMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ L, q6 W3 _" X' ^- H
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 _# o3 A9 z1 V3 ~9 [3 K C, }1 EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 E) v S# L; U' p% _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: Z: }, g5 ~9 u% F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 i0 t. M2 D5 r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- e6 `3 \; p3 P1 ]5 l* M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 B( m3 k; R# U, e: Y% sMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : `3 |- t$ r, g) i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 l c# n4 {8 G+ h0 C0x00, 0xFF); /* configure the clock for transmitter */; \, `2 P& b! d+ t% l7 A
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( |4 s: H) M1 g. Q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 P: p ^7 |! b4 i* S' s4 Z* Y
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 x# N' W3 c8 W9 p
0x00, 0xFF);! E6 l1 T& P. z% ] p
, H' h* N& A" M+ ]6 ^! l$ x3 q6 f/* Enable synchronization of RX and TX sections */
7 A4 \0 Q. M/ N1 s* K# | |, f$ gMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# K3 V8 w# L% B3 `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! O. R( `8 F( J( m4 ~# t AMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 D3 [1 R$ L7 v6 _& n2 P** Set the serializers, Currently only one serializer is set as- R, ^+ @, `3 @$ |& e
** transmitter and one serializer as receiver.- D, `* R4 X d0 s# H9 P4 K
*/
' }; R3 n3 Z8 H) q) h& C* ^ \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);4 N: X/ H4 `! {4 E0 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
o4 |/ Q c. r0 ~3 }! d0 Z+ p** Configure the McASP pins . z/ g! |! B$ z7 P: P! ?
** Input - Frame Sync, Clock and Serializer Rx! z/ _- h7 W& v* N, m5 @: c
** Output - Serializer Tx is connected to the input of the codec $ G. e% @; b1 V6 u8 Y/ l" `
*/1 J/ _) b" A1 e: g1 r8 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 w0 q( R5 E% P2 y! v& ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; c, T7 q& u+ AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: u* R& f. v! w. Z8 I t3 T
| MCASP_PIN_ACLKX: w5 J8 t- _1 k
| MCASP_PIN_AHCLKX
0 m' w5 H* \' y# X( Z& b) v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% `1 A3 w/ V' z6 @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 L: ?1 J% ~( W: N| MCASP_TX_CLKFAIL
) w: B' m s7 i/ W1 k" _| MCASP_TX_SYNCERROR
" @: ?" j- q3 ]% d- l( X& r1 m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ]2 o# [# ]( Q& e4 w/ a; @| MCASP_RX_CLKFAIL
2 B/ K4 o$ c6 }/ H$ _| MCASP_RX_SYNCERROR $ z: x5 F; t3 s! I! C6 g v5 r
| MCASP_RX_OVERRUN);
y6 I! C R9 ~} static void I2SDataTxRxActivate(void)
! \% @; V% V. K- d) H: E! h{0 U8 `" H- z: v2 a8 S+ M% t
/* Start the clocks */
1 T3 n$ L- g" G7 @' IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ l, s; y+ m! G/ {5 cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 Q9 w# v# V/ Z. ^% v3 X) V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 y( k1 a! l; V& h% T3 MEDMA3_TRIG_MODE_EVENT);
8 c1 N1 X) o8 w* KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# z4 M: a8 y0 q% M0 F7 }EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( M6 z& h7 W; |4 wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, v; r5 |, Q, t. V, H
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* j! @3 C5 T+ c: E- xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ Y$ J0 {9 f7 a& @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# Q3 y, E1 Q9 }/ ?McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; w/ Q4 y! x! N0 p: d3 y, s} 2 H9 U, m9 I- r- s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 J9 b9 z# ]% q: u8 ]" h
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