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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% }) c1 w* y* b# [ p; T6 Hinput mcasp_ahclkx,
7 h/ W. `- i* Y# b0 |0 I7 h' U4 Pinput mcasp_aclkx,
6 T% w: `! e d, x& n2 Ainput axr0,
7 t2 ^# n+ \6 Z( g Z$ ?
& p9 M% o4 H+ c1 w8 toutput mcasp_afsr,: H6 N( F5 q! L7 b
output mcasp_ahclkr,1 h E$ C5 o: l8 i" F8 g) e$ s6 v7 j
output mcasp_aclkr,) ~; V. X& z1 P" {; Z4 b; a
output axr1," I9 e ^) i- L
assign mcasp_afsr = mcasp_afsx;
7 ^( C4 q- r& d9 dassign mcasp_aclkr = mcasp_aclkx;
# e6 K/ H, x& D2 U; f! kassign mcasp_ahclkr = mcasp_ahclkx;
* o. ?% s/ T* s- ^, Iassign axr1 = axr0; / S4 s3 _' M2 _4 E% V' B
* ~2 \+ ?8 W2 x( v* x0 d. I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% R. ~. P/ m# p) x8 D4 ystatic void McASPI2SConfigure(void)1 U4 _ H" E1 x5 q, Z
{
% ?/ [$ M. b; p. ^, c: jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ o7 I! I2 K/ p% L# X! {9 V1 `$ y; \6 T7 tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 X) Z' ^- |2 _; m+ k- Z& Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' U2 _8 V# `! W1 w: {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* d* {, ~. a2 J; I5 }6 N$ T6 P0 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; Y% U8 L# L! O, ]* wMCASP_RX_MODE_DMA);: [8 M1 v- r# x- U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: `% ^0 ~) U: k. @$ K6 Z9 l6 NMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; L$ T1 |1 A+ J; Y' M$ t; N; J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 M5 t9 J* i3 J5 d$ b# s& o: v
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 r; ~' \+ P9 L* ]- k, pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * `- c9 K9 z$ u9 ^( A4 \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 p7 {4 _0 T8 J$ [5 a6 N7 T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! t& I, n/ _+ C/ ^, Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 z, n$ E; J3 d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) x9 B- f( ?: X. N4 P
0x00, 0xFF); /* configure the clock for transmitter */ p3 N: c+ N6 K+ L' u; w: N; |! I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: Z" t8 m2 w8 @ Y' f' s6 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: P$ Y+ g1 B$ q2 c0 _1 |8 m6 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: m- h7 ?. ]1 q, U5 _
0x00, 0xFF);1 ~7 N+ D- P( T; S5 P+ y
4 h3 T+ G- q8 s! Y& k+ c. e
/* Enable synchronization of RX and TX sections */ " L; C6 O. v0 {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ v7 i& n4 D3 v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ S) G/ [5 v" j* V$ o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 A1 S$ P, H+ B/ `4 Y2 l
** Set the serializers, Currently only one serializer is set as( B( c0 A( L' X) W6 l
** transmitter and one serializer as receiver.
$ _( ^+ s0 M4 d) ~) |*/
, h( m! [: K' [! j$ J" BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 u' D* i- j0 v8 A' \) r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, r1 E5 h( b2 u8 }/ [** Configure the McASP pins
; ~( |/ l+ v1 H) }8 Q' W* n** Input - Frame Sync, Clock and Serializer Rx
# U: A* [2 q4 n, { |3 K** Output - Serializer Tx is connected to the input of the codec
+ ^/ e/ v9 r& l$ O z*/ [9 Q' i D2 ?& {: E' H# w
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% o! L. g( n- C: K6 b! O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 b2 t+ A0 [2 o) c& m
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 O& h& D/ Q; J9 e7 r$ @| MCASP_PIN_ACLKX8 P$ j$ x: R& q; c$ k+ l) D- P
| MCASP_PIN_AHCLKX
9 f0 T* r8 J' X. ^/ @" A. _# ^/ D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& V( N. d1 i% F4 b$ EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( s) K& C2 `/ N- O Y8 l| MCASP_TX_CLKFAIL + h# Z! N* o% w7 M* r7 D) F' M
| MCASP_TX_SYNCERROR3 q' {9 w% s: f& g7 J4 V7 O1 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" ^) |% [+ `- o7 G3 j. t| MCASP_RX_CLKFAIL1 g" z* R& V7 N! |' V+ i
| MCASP_RX_SYNCERROR
+ b! r4 K* A' j| MCASP_RX_OVERRUN);
O: a9 Z8 Z& `0 F8 D* S) q} static void I2SDataTxRxActivate(void)
) m9 \& u3 M" d! k{
1 s" E# ~/ h4 q& K* s' S5 y/* Start the clocks */
9 j4 ?5 `7 G) S( Z G! z1 HMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
8 a' h- u! x& V; a" J' L9 e5 v+ B. dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 M7 Z2 j: q+ c' AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ w6 Z. M: H' Y; k; V
EDMA3_TRIG_MODE_EVENT);
+ Z: j4 V. y0 h8 E- e; ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 K5 a. \$ ^5 P' e+ A% E' F9 S/ [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 O0 T! J7 y; JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( }' e; M# i' D2 x. S- x/ N4 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 q$ D" Q7 ^8 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 p4 g- Z( d6 {% M( i* g' O/ JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 v$ N( D! e5 W1 |, DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; S- d J3 r+ b/ F
}
( A) l3 j" ` i' `6 ~6 T' A% J% r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
$ ^( A. {( y0 r( k6 g |