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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. r; D0 H2 N- g! ^9 i# ~
input mcasp_ahclkx,9 P o- N- ^: Y* A' R( o
input mcasp_aclkx,' ~& p K- z0 {, Y" w
input axr0,
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# h3 m( @6 H, W/ {5 t6 s7 ~. Noutput mcasp_afsr,* p: H4 F8 Q: w* j
output mcasp_ahclkr,+ y- O" v/ j) N7 o1 ^4 D
output mcasp_aclkr,7 j& z4 D! z& K! S: h
output axr1,4 h L8 D5 g# f# o# k
assign mcasp_afsr = mcasp_afsx;
, K5 l4 H; [7 L/ Cassign mcasp_aclkr = mcasp_aclkx;+ b" `8 g+ O9 M5 T
assign mcasp_ahclkr = mcasp_ahclkx;1 {- V9 k! n) y2 w/ U$ x
assign axr1 = axr0;
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3 a F& Q4 R, L5 I: A) y8 \ K/ A$ I. `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: p' I. e, x9 Nstatic void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);& t, z/ T9 T6 \- d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 L. ~1 d# U$ X) N: I0 ], Q6 C* M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);+ c+ w" j) `, [5 ^% M
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( b( x) ?- `! s8 `" r* X' d( C/ W% o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* Y) N8 ?& c4 I4 ^; NMCASP_RX_MODE_DMA);
* \4 V% S+ U K( D0 o h4 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ Z! y9 H8 z9 @8 J. h9 _" [MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, C6 \: `/ D% X% C0 i: |/ H' I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ G+ v9 f$ Y( E( gMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 D; M& `( m z# v+ gMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: p3 k, Q5 |! J8 n( G; Y! V0 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// n9 l( T) s9 c0 }: H6 m
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, T- O& j# n6 c& s! g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 W! q ^: T1 j8 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ N, H& c3 d- v" B$ z/ r3 j! S# M0x00, 0xFF); /* configure the clock for transmitter */
i3 n+ x8 ^2 Y8 A' M+ ^( ^" o5 B/ R" dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! N% m( C, z0 f2 p/ i; S2 @9 H! m! \* fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . u' L+ z& o; C7 z Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- J1 C4 ?0 z' B. c- D
0x00, 0xFF);0 a( b; v" X4 t, M+ ]& k
2 \- E" s0 ?# b0 c* Y8 J
/* Enable synchronization of RX and TX sections */
1 }& P2 ]' E2 y( cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, J: `6 @ M- s5 a- Z y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);" @9 ]2 Q# I& u+ P3 Z4 Q. s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: F4 X7 l, i7 {4 S4 Y** Set the serializers, Currently only one serializer is set as& G6 h# _ R& Y9 W
** transmitter and one serializer as receiver.' d# ~! T; C/ `
*/& g2 c! v5 r" ~" {! Q* C$ I: T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);# J5 B( b+ J6 S$ z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. l H2 e a! E' L& h" s) a
** Configure the McASP pins
+ Q3 W# f# C: I/ @ [- N** Input - Frame Sync, Clock and Serializer Rx
& B, H. s- s5 W% F! E$ D** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ l; | q J5 m# \8 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. u3 r) O. Q) D! gMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX1 Z" B2 y Y8 f5 Z; V0 ~
| MCASP_PIN_ACLKX
% z+ h* f. l: ?4 T| MCASP_PIN_AHCLKX7 ]2 N! g3 N: B
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 G2 ?+ |3 v' } N5 d% l! ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 R- ]+ q8 H8 i| MCASP_TX_CLKFAIL
" s) y4 M2 F) q! u& o3 U| MCASP_TX_SYNCERROR4 B4 B4 p3 z! |2 O. u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - q* M: J) ^ d# w
| MCASP_RX_CLKFAIL% ~! i$ F: |+ ]! t
| MCASP_RX_SYNCERROR
" y8 A. y: |( F9 z| MCASP_RX_OVERRUN);
* x0 a* S3 o3 B/ ~: O5 P} static void I2SDataTxRxActivate(void)
& j4 k/ |" N; |& p8 @{
/ s' Y2 z3 p! @% n/ D1 g% W/* Start the clocks */
* x% o/ w% a( o6 o* p) z4 nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ F4 k3 ^+ T) A( ~! J2 u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 Y+ l% B% S0 V3 C4 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 w5 Z/ L9 s* gEDMA3_TRIG_MODE_EVENT);* Y# M+ b4 N6 I* `) `7 \% Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: q& X- L1 o, F) mEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# m1 ?# X. |; E1 e( h4 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 S& A7 {, p0 l6 v3 k0 `1 B5 n
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 x, W5 j/ ^$ Y" gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, R# D/ r0 f$ e, ?! V/ N c
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);2 m6 X- p2 J4 a3 e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* i! R" _. a2 P& f% W! @ k
} # ?. C/ R# T9 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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