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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! z/ w+ |; {" X. m7 v5 E W: yinput mcasp_ahclkx,8 G' h+ e4 U2 g' q# u
input mcasp_aclkx,
# T4 O5 g5 \ M5 g" R9 c$ Finput axr0,
' F; z) n! z1 ?% E
; o" Z5 {0 ^& a% Houtput mcasp_afsr,, ~! F3 N/ `. c3 D
output mcasp_ahclkr,+ R/ R! b" h; P, F
output mcasp_aclkr,* W+ _; l9 D+ m) _" F$ J9 |% r
output axr1,% Q& o t/ R# H! i) \
assign mcasp_afsr = mcasp_afsx;5 f' v2 h5 N3 }) S
assign mcasp_aclkr = mcasp_aclkx;
+ n0 b- J1 u/ v8 c+ @' \3 Vassign mcasp_ahclkr = mcasp_ahclkx;
; w# t8 c/ b2 d' cassign axr1 = axr0; - f0 g, @. Z- n4 M2 ~
4 q Q. Z# V9 \* p2 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; O4 z2 R# M# ~static void McASPI2SConfigure(void)# G' d0 r8 U' F( ~
{1 D/ I! J$ n7 g* E' G$ s/ y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ s$ f% e& U1 E; V: m* r7 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 k3 }; e, L1 _) g' f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ i- Q, t O9 m j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ A6 j0 z! U- S; [! x2 _0 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, M" I( C% N8 t6 ^/ o: m1 f! K: A
MCASP_RX_MODE_DMA);+ j4 Q; p2 x5 J- E$ k9 L0 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 Z5 j6 X/ [9 h" \4 t/ V4 _
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) u5 d3 | C$ C+ c$ q# r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ A# p& {# H7 ^$ XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. E" v, H7 V0 O* ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 m# v: f) T" y7 [) U' F1 F" m* EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 C: a( {+ o& H& W/ X' Q" C$ H- ^) cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 o9 a7 d( [# X6 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' s6 U7 M9 A; U! }1 b6 @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,3 `) E$ E" h4 T ~9 X: V1 R
0x00, 0xFF); /* configure the clock for transmitter */+ l0 |* w# @9 l( l1 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- B1 F; _9 A" a+ O- ^8 K4 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 u- ~1 ]. s( M5 }3 ^* L7 uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- d) Q& Y, j8 z B* q9 ]0x00, 0xFF);
9 o' Q' C: _" O# K. Y) s$ V. {# J" [4 k7 q' R
/* Enable synchronization of RX and TX sections */
; n; D/ f7 x r0 a% T3 VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 W% N9 [( v1 ~7 ` R: L% s0 r- c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. D9 H5 w. m1 {& d1 o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 |8 x& \( |$ f** Set the serializers, Currently only one serializer is set as+ M6 P3 V l2 r/ ~% ^
** transmitter and one serializer as receiver.2 L& b8 G5 g( k% z0 a6 X! W
*/
2 L/ {" N7 a9 j: K* }6 {' ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 u! P+ c# s- \. A9 cMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 V3 m; V. S. C6 n** Configure the McASP pins + @% J4 S" O% x g
** Input - Frame Sync, Clock and Serializer Rx
+ o& z' Y& u' w4 f Z. ^** Output - Serializer Tx is connected to the input of the codec ! K3 j. k7 _& `% I6 J
*/3 m. P- U& [0 l) o( g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 a* m8 b4 Y0 Q( Z( q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! s5 h6 ?8 ?3 \ {( B
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. F6 u7 b! q/ G" N5 D; `0 U
| MCASP_PIN_ACLKX
9 ]- o3 F" W( m2 l9 d| MCASP_PIN_AHCLKX6 Y1 t+ Q' m( c
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 }! ?% L9 W N" U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 f+ P7 Q/ X; D0 p6 K5 I: J3 C
| MCASP_TX_CLKFAIL
/ b. }, v6 o. { Z9 y| MCASP_TX_SYNCERROR
' H4 \+ Z1 `6 E2 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) w5 w: L# Y& A9 `! i| MCASP_RX_CLKFAIL0 m/ Y% d" N8 y* \4 [- C# h5 @+ F
| MCASP_RX_SYNCERROR 8 M8 }: g k) r6 U# P( w
| MCASP_RX_OVERRUN);0 O' l4 O' Q! A7 [+ A# y6 H: d
} static void I2SDataTxRxActivate(void)
* d4 k6 O# ~2 \' V( i{
+ r: c. x" @+ j0 t/* Start the clocks */$ l p; ]- ~- c$ ~" S, i* H
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# z0 ]# i- y# v- g' ]/ m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 m5 |& x9 k2 `7 l& C4 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# c8 ?: L/ P* J% ?8 eEDMA3_TRIG_MODE_EVENT);# C- ?5 T& K! v, b$ t4 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; R# ]2 Y( d* }+ u5 U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ F, X' }& ]! t: t6 L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 V3 O% y$ f& H7 @' m& }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 _) D8 s( F; w2 w Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
, T" A8 T& G x/ j: {' ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ Y6 K m0 j2 vMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 Q G; k7 L) Z2 F7 s. V} - z, p5 F( h. I5 i! @
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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