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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* y3 O) [# n' F7 sinput mcasp_ahclkx,$ i0 j! d. T, N1 f; a* V
input mcasp_aclkx,
( S; u) L" S! N& K* F3 ninput axr0,
0 _3 Y0 }( C; S( f
. K+ Z1 o+ Q1 moutput mcasp_afsr,
6 U. s: v% u* l- loutput mcasp_ahclkr, b1 Y+ o5 [6 Z) p/ m
output mcasp_aclkr,
' {0 P5 F$ @& p" t3 B l- Goutput axr1,
8 Q( O9 B0 |! q* g& R0 t assign mcasp_afsr = mcasp_afsx;
& Z: b% v7 z+ W1 [assign mcasp_aclkr = mcasp_aclkx;) e$ m4 z2 K* r `- I9 ]) s
assign mcasp_ahclkr = mcasp_ahclkx;
) Y. v9 Z" ?5 s$ E9 O. K5 X* oassign axr1 = axr0;
# W% n' Z8 T0 e/ }. f( U8 k( ?( G2 d/ d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' A3 E' }) Y. S% G5 I" Y" O9 x' D
static void McASPI2SConfigure(void)
! }; e& p* c5 H- S+ N0 B{: ~5 o! ]! j' m! y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 T1 E2 P4 ^$ d a" F. p+ RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! Y2 \- F; ~5 }( e0 g3 M0 m0 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 d4 `0 }+ }8 {- ?& C6 Y& T3 f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& s4 l5 {. }( B- J8 {/ ?: N* p. S/ h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& [( U8 G2 I8 e, L3 vMCASP_RX_MODE_DMA);
% O, H3 n8 y, N% Y6 n, w5 v3 h3 nMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% a5 i* J( I8 j S4 d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! [" s7 T2 e" ~) m( I4 ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ I" W; K' u' M: p4 J& O2 g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 Z$ c, G) V; U1 x3 J0 y2 V& ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" B* f& g8 h5 B7 \+ m$ b# bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: f, _9 ?+ b" R2 H8 t9 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( l& W6 Z% z% t2 l) {' y/ o& ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 [. @/ ]9 v+ Y* q# m9 T" iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" k2 z8 L, ~; M, ^/ I: ^+ [0x00, 0xFF); /* configure the clock for transmitter */# q# t& S1 F2 S) X# T# m1 l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 V& K7 A& k; U2 ]. i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # I# p. ~& u- L) I$ ~2 L
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& e: d" c) @8 L0 k5 |
0x00, 0xFF);7 l9 S% l; r G* g/ D3 w/ }
3 b. f3 {) d% `4 _/* Enable synchronization of RX and TX sections */ 5 F1 h+ j: ^9 J" U, k" V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
; W4 v" p4 C% K. _ q' E- D# U& |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 _2 k/ @1 h; s- ^# Y: TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 P1 x9 f2 @: B1 v
** Set the serializers, Currently only one serializer is set as
; ?) d' |, C1 U" S** transmitter and one serializer as receiver.
3 ~2 Z0 b# v6 i' c& J*/
6 V' B! H/ B/ W: E+ mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: G% w9 h* Z2 y1 ?6 n, a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, b1 o' C N7 z8 B. T( s. H0 H( y** Configure the McASP pins * ?, ?* U+ q) ?7 P& F! H
** Input - Frame Sync, Clock and Serializer Rx
5 W* S5 z$ a/ b' B** Output - Serializer Tx is connected to the input of the codec 3 r% |7 M1 _2 X e
*/
5 J5 Q; A# I/ C% n& xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
, ~7 Z) H( D. w c/ {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 l# ~* c7 w5 ?1 C3 uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ s/ @5 I. {" c9 y' E, o| MCASP_PIN_ACLKX2 e8 L; O9 m1 i+ t" ^8 d+ n! @
| MCASP_PIN_AHCLKX
% Y" B; Q7 X' D+ c; [9 @! u& o0 E" s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. R. |' a9 y0 ]3 h A T* A2 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : O. d" H, c# t( R8 I3 [" r
| MCASP_TX_CLKFAIL ' s9 V1 {( p% n0 r- T+ F
| MCASP_TX_SYNCERROR
" C1 _1 E$ ]( [0 T1 o8 u; x| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : y; H8 V' K- ]
| MCASP_RX_CLKFAIL4 g" E( y" b, v% i( w
| MCASP_RX_SYNCERROR , Z: [6 z! v/ Q8 J
| MCASP_RX_OVERRUN);3 \ d6 ?& c! D; V. O! M
} static void I2SDataTxRxActivate(void)$ h- v+ U' m. ^: ?' b8 O% f
{6 l5 @* y$ m6 e8 L7 s6 Y
/* Start the clocks */
- k- w9 m3 }- s9 Y, |( K; zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# j+ C/ z3 w. JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% b6 H! u; q- h: i1 b$ H9 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 D+ }# F1 V6 `! {$ b
EDMA3_TRIG_MODE_EVENT);; ^+ {: q% o4 j! G! @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 ?3 v. j1 N4 O6 f( u: bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: C0 k$ |4 V( U& d; B6 xMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 Q/ R" {' E, u& }8 N" r9 k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; j6 F; |1 C0 ]6 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ X9 Z* X0 r$ Q; g$ f" Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ t" @ Y! K6 R& L" K* m& {/ fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ h4 E! g7 {+ ^# p) Q9 H}
2 Q% c' G, Y+ L请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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