|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 \+ V5 q/ J3 g( h( F5 k" Q3 B
input mcasp_ahclkx,$ Z) g& @0 e0 |3 J2 z0 S
input mcasp_aclkx,) ~- M; p. m% ~# M8 |& y
input axr0," `, P4 M+ g+ \9 V" [4 ^9 y
& J1 O+ y& N! s$ V2 d- `
output mcasp_afsr,# h! z* e8 k o' c
output mcasp_ahclkr,! R3 O0 a$ U0 ?' m* D$ {* K, M
output mcasp_aclkr,
0 E% s2 I; b" G* k B6 o, \1 {output axr1,2 w! e9 u/ u5 _2 C% n4 f) U8 q
assign mcasp_afsr = mcasp_afsx;
, u' h" j; \2 O a- nassign mcasp_aclkr = mcasp_aclkx;7 }: W9 h$ k( ~3 H
assign mcasp_ahclkr = mcasp_ahclkx;: A5 K0 _5 t9 n5 l
assign axr1 = axr0;
4 H6 y1 t" j' s# {
2 K, ~3 R' [1 M m! H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : B* x2 p" m) z4 ^: ]* u
static void McASPI2SConfigure(void)
. n+ @( i8 G( n( j5 E- N{
& x$ s5 e8 G( o) O- s5 Z6 o1 tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);; {1 u2 r! J( f% t4 D0 B3 f6 Y6 p
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& [( v: l. O" L& q9 I% m7 b @4 o$ mMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 h. ~) j* T, x6 @% s' {' lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) [2 T5 W# V: H7 ?4 u" P- f/ R! ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
j7 O2 H: ~+ P) ?. a4 o5 }MCASP_RX_MODE_DMA);
2 Z! o9 Y4 j* r% X0 R/ lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, X, M: r) X( T* u! [7 \5 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" g+ ^$ L& b) ^/ x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# K; [# B7 k L9 F5 H& pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 \, _. h4 P2 D! Q3 w1 f3 R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ R" M, w4 b! w$ R" r* o9 }; W$ ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 D, w& f, c% fMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ T* j7 k# d F( R+ u; R. ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) J2 Q/ O- w7 R$ SMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ l V! M+ ]3 O) g0 S# K% ~' }% Z
0x00, 0xFF); /* configure the clock for transmitter */) |1 u4 [1 x9 Z5 t @ j* g
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);; s5 p2 F8 V" \3 E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / d$ z* L% S+ Q( w1 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 P* n0 e, Z* u0 N5 s' Q
0x00, 0xFF);6 H1 t; x, e: S* O
4 w9 [" Y, \, Y2 W! G% s/* Enable synchronization of RX and TX sections */
! w( E" T2 Y4 T) m/ |( \McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) k3 s& q0 J* t8 w7 ~; PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); g1 ^) r) c' q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% k X8 m9 p9 l2 w# G) {; a% Z% e( i6 ~6 ?** Set the serializers, Currently only one serializer is set as' {6 F3 A5 A! `- _0 q1 c2 R" p
** transmitter and one serializer as receiver.
; T& b p. I+ K/ N*/8 M7 c( u7 i9 Y7 Z9 Q) q% K) f
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- x4 H, [) v' ~; O# EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& e" K$ q- Z* {" w) |
** Configure the McASP pins
# S1 m6 K7 u: u8 G: U$ \1 z** Input - Frame Sync, Clock and Serializer Rx
5 ^% M# K' i8 W" l. q% }. u& U** Output - Serializer Tx is connected to the input of the codec
" v- T, U! R5 Y0 }( p*/3 ]* N+ `& O: p0 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
: d3 w- c. Q2 m, r4 BMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 B( e4 c8 l/ {6 h' c: iMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% E4 c E( r' j9 r
| MCASP_PIN_ACLKX
" u6 j# ~5 Q1 K1 I8 A, F2 H| MCASP_PIN_AHCLKX
/ A& Y% e7 @7 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# _* j* X+ }, t i. g6 u
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 o8 x m4 I2 X2 N* }6 K+ j# e' u! J( ]
| MCASP_TX_CLKFAIL
/ [8 n: W% B8 r! n( n| MCASP_TX_SYNCERROR
6 P3 p% ^& P" w- E0 ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 E/ e& i+ K9 U| MCASP_RX_CLKFAIL
3 L1 j& R( k4 R8 U8 j| MCASP_RX_SYNCERROR - Y1 J, s0 H, W" Q) K4 W
| MCASP_RX_OVERRUN);
; G* h, ^6 h a$ e/ ^} static void I2SDataTxRxActivate(void)
2 K$ o9 m* E, k) r3 |+ u) ~8 x{1 F) v% r/ {1 }) Q
/* Start the clocks */
/ [! p% M2 [+ wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; B4 R$ ~/ P1 N: z/ Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; O) ]4 l0 c( W& G6 x- O) g1 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- M. S9 n2 L( REDMA3_TRIG_MODE_EVENT);: U, s- S+ V, @& c) ]4 A" B! B1 P6 K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 W9 u/ k! d, w1 }" P& B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: A& A, A# t7 H+ n0 n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 }0 t6 e% o! { [# ~' }) HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! }$ f7 D2 n& b2 c0 @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' n2 }- O K, E+ R; I' [
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
g/ i8 X- P" I1 g* Z$ nMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);- I/ @. C- c: _
}
% |4 q Y3 C0 A7 \4 }, F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 p. X/ m7 p+ y |