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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% q* h" ^/ I/ P* m% o$ f! _" }
input mcasp_ahclkx,$ z' h; ^8 \; g. B R8 a" `
input mcasp_aclkx,
3 g2 Z7 e2 Y3 b9 v; |input axr0, {7 C7 a+ g$ A3 ~5 H
. I. S0 P2 v: x! v/ E
output mcasp_afsr,
: v) @8 Q. j: xoutput mcasp_ahclkr,6 S, x! N4 F' K; ?0 F% N
output mcasp_aclkr,
* |. N- _/ }, R; loutput axr1,
' e$ P+ P7 u! @$ G8 n! G) B+ I& H assign mcasp_afsr = mcasp_afsx;: Z$ U& s4 t2 m& g) e: t& m
assign mcasp_aclkr = mcasp_aclkx;4 O, K7 [' z( F% v
assign mcasp_ahclkr = mcasp_ahclkx;
5 m1 z, [0 S0 Y9 b. D: |; wassign axr1 = axr0; 6 m2 ]- U( ?2 N: q/ G
3 b$ ^+ [5 x" O( W( W
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , C, C( }9 i! I: ^) V
static void McASPI2SConfigure(void)9 U9 n* i2 i% j! Y- q
{, ]8 {3 h8 G/ t* l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 [# e$ v; K+ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ Y+ j8 g3 j4 ]) y: L# R) ?7 E, [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ] i7 L0 h7 C- G0 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- f8 }+ {( H3 I. h- a0 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 T! x- t+ Y* u2 X8 W$ b4 N
MCASP_RX_MODE_DMA);* m+ P+ T$ ~0 \' i f Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% x# T3 j/ [7 L& F3 k j4 u' r3 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
L) ?" z7 F' g* ^; N* AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; W2 S/ m& J- Q% t! [- Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 r o& d! G2 O- `, I u5 ]6 p
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # h+ R! P5 O6 t7 h
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: U" C J* Q: F
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 A& y$ v! n; Y+ C. _; M% U
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - s2 p5 s! c; r i
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ n- Y/ M7 s& I' d4 K2 C: S0x00, 0xFF); /* configure the clock for transmitter */
0 T/ [% o6 a5 X/ X- @* l7 f# p" u( }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 N& X5 C& r8 b$ U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , w; s, g, n, L3 a& w9 w) m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ O }6 _8 l1 i" h. P
0x00, 0xFF);$ e2 l$ y% Z( w1 y( P
4 p) v. g8 s/ u' D/* Enable synchronization of RX and TX sections */ # E7 q* e* ^2 E4 w/ x6 @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ c& W/ M) l; D: XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 M* q( O, T5 X# z: J7 F# ^( D+ ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* t4 w4 q; _% \( i7 x6 X7 F
** Set the serializers, Currently only one serializer is set as
" s4 o9 p, B% @; \/ Y' }** transmitter and one serializer as receiver.+ o0 b& _) w# f( U" f1 D3 H
*/+ e' m Y- P) z" H9 i% P+ r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ t' b( ? @2 F% T4 U) h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, F9 `( W# L9 D+ A3 W: G** Configure the McASP pins 3 a" Q" W. ]% |5 s
** Input - Frame Sync, Clock and Serializer Rx
3 J% J6 W3 {; s1 q, C3 M** Output - Serializer Tx is connected to the input of the codec
3 A, P0 T9 K3 o2 p, n' a*/& W/ a' a, w$ }; B {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ U* i( ?7 k3 K' @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- u, J4 c9 O4 w) Q7 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ s9 t$ a4 U1 b1 f9 V. N
| MCASP_PIN_ACLKX h/ w7 l) G& h/ U7 }0 p8 U- r
| MCASP_PIN_AHCLKX
3 L. f* v8 U/ t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) B. m( d o$ B' S# N& J# |) V+ kMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ i: F+ Z8 A4 {: L. s& E* p| MCASP_TX_CLKFAIL
! ]' ]/ A9 E5 @8 p5 B$ Y/ j| MCASP_TX_SYNCERROR
+ ~ v7 Q+ K7 ]% J5 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( X' g+ }. Z0 j2 ]& z
| MCASP_RX_CLKFAIL+ y5 g& P5 G( ~
| MCASP_RX_SYNCERROR # Z4 Y3 | p# X$ ]
| MCASP_RX_OVERRUN);( P- K9 r+ F! a7 Q1 Y. q6 \
} static void I2SDataTxRxActivate(void)
- s# Q+ c: ]6 n2 a8 {{( y5 [1 k2 R+ |+ B
/* Start the clocks */; B) u0 }! e+ }+ [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# L$ o" v, G/ d( l2 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 V+ e9 A% t) l# D O6 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 }% j9 i l* y0 Q
EDMA3_TRIG_MODE_EVENT);
1 E8 E) _9 N0 Z M3 S, W* QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 I! _( I( Z) E1 {1 @3 ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& [* X* C" Z- s" x/ c" M4 K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ A4 `' I; u& [* o7 l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 g5 N0 K, H6 {. s" s3 w) _. z! k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: x8 |- X' s+ {+ @0 F4 O$ GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" p9 A# l l" }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, X% U! N( M- C# D0 R/ E
}
- T6 v. B$ S5 K+ l" E7 {8 y R1 Y# a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 q @2 h3 E5 \6 ]
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