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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! @6 O8 u b/ E! ~8 w" Uinput mcasp_ahclkx,
% B7 w9 Y& ~$ f5 g& Uinput mcasp_aclkx,! O8 Y% S2 O6 W# I
input axr0,' p: V1 o+ a3 t( v$ x
: t; o& V& `0 M4 U( {" l- D
output mcasp_afsr,- z0 ~. O! z3 q0 d
output mcasp_ahclkr,
4 x: O3 ]+ P$ j* ~3 w% ^output mcasp_aclkr,8 N" D$ N; a2 M6 P J
output axr1,
- V6 O$ l- O7 [ assign mcasp_afsr = mcasp_afsx;* S6 u# R7 p$ n n
assign mcasp_aclkr = mcasp_aclkx;
7 p/ \/ p [6 C* P* hassign mcasp_ahclkr = mcasp_ahclkx;) Q( g/ |% C9 q0 R' y5 T+ U
assign axr1 = axr0;
/ G1 g) V+ Z. ~1 N5 P) R
5 Y3 O; w7 k( i) N D/ Y在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 S+ ^ I5 A) E* ]# S# Xstatic void McASPI2SConfigure(void)( n) m2 x5 | p: W H
{3 r, Z2 G) b/ T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 P$ ^; [& Z$ m$ Z: \0 v
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 u. L9 M& [: W3 [McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 j. N+ h) N6 Q* N# X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 j P1 T2 c3 ]: p: T8 }4 z( U- UMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ y" s& J3 O* z2 E' I8 o
MCASP_RX_MODE_DMA);
v" A- i, `6 R2 gMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; | R; o$ B$ ]' z9 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 Z( H) [3 P" P, mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % x8 I S" ?) ?, z9 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ [4 E, w! Z' Y8 xMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # p, V$ E& R! h/ _
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// u$ |' }' I, u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 p4 L( ?3 s3 C! B3 t+ Z: XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! Q, T# p7 v2 _0 m! W. y6 U4 U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; e" F9 p; Q- ^9 X0x00, 0xFF); /* configure the clock for transmitter *// r! X# i$ @' h# h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" ` u' p4 Y |9 dMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! r$ g( U1 k* O9 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" O; a) [9 e; |0x00, 0xFF);
! }/ t; Q5 Q7 U+ g$ ^0 n5 o# b
/* Enable synchronization of RX and TX sections */ 3 y2 B- x1 O( E% n1 \8 l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 g3 e6 D( }+ L T h3 R* JMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ E& b" t; k" u0 DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% C' @9 W b# {4 G
** Set the serializers, Currently only one serializer is set as
$ Z; ?3 |2 a% f3 o/ g3 l** transmitter and one serializer as receiver.
, C. Q- S: X7 g* s*/
# B! x+ \) ?) K6 E! ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 v* V- q! X" y. P4 p% T4 Z B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: T; E0 \$ J, j% ]8 v/ J
** Configure the McASP pins
+ @3 E( v6 V: Y5 M) {6 O** Input - Frame Sync, Clock and Serializer Rx
/ z) o' R9 a7 x4 T$ A5 _** Output - Serializer Tx is connected to the input of the codec
4 y1 `0 A; r8 H) z; r& Q1 Q*/
2 G5 A; Z: A' o2 gMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* Z! B, i) _3 N- h% {2 s7 z/ ~; WMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 q6 g7 L% G( V% h; D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' E+ t0 e X( P8 _. A7 s' b| MCASP_PIN_ACLKX
6 x! s0 o2 i+ C7 ]| MCASP_PIN_AHCLKX
% v6 @2 ~+ Z( Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% A+ U( S1 L9 b% v* lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 N( ~* p4 _ d* M/ y
| MCASP_TX_CLKFAIL ! z6 @, P- S/ J8 T6 a& g
| MCASP_TX_SYNCERROR0 R( F" r6 I" R% [0 g) y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* U* C! E- V& f5 p| MCASP_RX_CLKFAIL
1 Y, r# r) w. }' Z% E| MCASP_RX_SYNCERROR
; q# H, t5 k* X| MCASP_RX_OVERRUN);/ t6 l& V" o& g4 m
} static void I2SDataTxRxActivate(void)0 @' q6 _1 f2 G$ P
{
t" P8 T/ ?: N Y8 w; f/* Start the clocks */
, y8 ^' J# x9 |; K. w( Z3 SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);7 y: j* l+ f7 D8 r `8 T" j4 l
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; y1 k0 H) A2 x: z0 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* I9 I( o7 D. ^+ j3 B
EDMA3_TRIG_MODE_EVENT);
6 S! X$ W/ t( P" Z9 g. HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , T) p- O- c. H! r* b J: @! r! P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* i) k5 Q) d9 v S8 V; Z3 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( X7 {0 r" z7 b& f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 e/ T6 n7 I( T2 h* b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ |$ O9 v4 H2 o8 o; |/ b# c# |McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' C( [- P% w4 s+ Y D! Q4 D' `+ y. LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 P' _# [7 S) @# s0 v6 D}
" g+ d8 y+ b$ R) d, r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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