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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 b- v$ u/ b$ z+ l k% b
input mcasp_ahclkx,
: [7 u* o) N- k! m5 minput mcasp_aclkx,0 q9 z2 ?7 s6 y, _: r
input axr0,! O8 h l% u' z- S9 A6 B
7 D, i! d9 g8 g& {, \' uoutput mcasp_afsr,
, Y& w: e+ }+ xoutput mcasp_ahclkr,
/ z2 j, ~& L! s, l# |9 Routput mcasp_aclkr,
# a8 i, J1 \6 m. goutput axr1,
: a3 F* o6 e$ _4 Q: c! F \$ { assign mcasp_afsr = mcasp_afsx;7 l4 P# j8 @- Y0 P1 V
assign mcasp_aclkr = mcasp_aclkx; v# Z! Z- k+ W W, ?$ _, K
assign mcasp_ahclkr = mcasp_ahclkx;) i- X3 J1 Z3 s" J
assign axr1 = axr0; 6 R @5 g6 o. |5 D1 `! Y
. ?+ {! L7 ^9 H( \) R: w6 e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ^* F- N- K7 l8 W
static void McASPI2SConfigure(void)
H' h7 A# b* f. W, D5 u# y. k$ ~, u- z{) w- O( s) n) v1 [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% b* @- b" s6 B% v5 }- v8 C
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& w' D0 n& f0 t; i# f( P0 `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, T6 C/ s, T, g! {# ^. ~
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 F: i, f9 F" |' |4 V
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 ]$ h( k+ |1 y" LMCASP_RX_MODE_DMA);" D+ `8 C# w' u( r" x) {: U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 @ c$ ?2 S. t: C% t7 {1 _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* g3 {/ ^6 U- J% j1 Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 R1 \5 x& c+ V& `& x8 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 _( |' _( s/ h& _5 `
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" K; ^1 L, H+ o1 aMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 [8 |/ r! t- _, ~McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& m, Q: ?7 ~ q0 N# [6 a/ h8 u Q+ a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & [, x- _: D! h/ b4 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 Y" S9 y1 i9 Z+ K$ {
0x00, 0xFF); /* configure the clock for transmitter */
! c& ^6 o N, M8 I2 Z/ p; ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);& G: }1 a! x2 {& e
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 V1 j8 B' h$ d Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ p n7 g) ^6 a r% v$ P
0x00, 0xFF);
], P1 R) g) P7 c4 |
3 q6 G( L( |& `) n/* Enable synchronization of RX and TX sections */
4 i/ J8 ], F% iMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. W3 X& `9 C( X( R* g) ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 x' y" a3 d/ `1 C! ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ?/ J& x; o- f/ v( x" t
** Set the serializers, Currently only one serializer is set as. G, y! M7 f8 L$ Y
** transmitter and one serializer as receiver.2 d2 c" c5 v d4 _# [0 |, m* J
*/
& X6 o+ A: @9 @) k0 n8 qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) a3 H$ G2 m4 n9 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 G7 h! I- |. s, V4 t** Configure the McASP pins
7 u' w0 h+ t9 ^8 D** Input - Frame Sync, Clock and Serializer Rx
+ G, L/ P& W6 c# j9 R$ `# B** Output - Serializer Tx is connected to the input of the codec , k) ]6 X5 t( ~9 o9 ^2 F
*/
1 r: J) V V7 ^1 b- |2 Y9 ^, RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
3 Q; u/ Y% y8 K3 w& h: V# Z8 R2 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 u" y& _: z3 P+ TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 N/ o- G" _6 s| MCASP_PIN_ACLKX7 C: q* X1 i. b2 j; C
| MCASP_PIN_AHCLKX/ l9 V9 j2 L8 [7 X1 v1 u/ f& v
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 E% [$ b1 Z7 N; `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 ]. U% @( E! V5 N6 T
| MCASP_TX_CLKFAIL
/ ^2 ?7 S; H+ e- L/ B' P3 N$ a| MCASP_TX_SYNCERROR7 e7 P% n+ P4 D) h6 Q9 q- S
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - _6 s, d7 `$ f& k* D x6 f: p) s$ I
| MCASP_RX_CLKFAIL
( \* m9 ]4 g8 p5 M+ R| MCASP_RX_SYNCERROR
3 `$ C f1 H! `' {1 N) t; D| MCASP_RX_OVERRUN);: I3 E7 }/ o/ V+ h- G8 H& K% u' ^
} static void I2SDataTxRxActivate(void): e @7 X5 T9 f3 ]1 q( `. V) l f
{
$ C& F/ w/ I( ]* {& X- V* f/* Start the clocks */6 p/ d+ o! a8 ]( \- \0 A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% D, T& E" t8 e9 r* t/ J: S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) v0 w# x6 f$ ]$ p' p6 ]+ ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( B$ ~. I4 I1 F" i3 ?+ k# G
EDMA3_TRIG_MODE_EVENT);4 F& D3 {. `# j7 v9 o' v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ e! @0 j6 a$ |" WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( J M# M& g5 t, h- U5 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. R. m9 i* {) c/ l- f" {. iMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: h4 y4 h q! J3 G% {- Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ t/ {. c T1 J) i( m
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 k( ^/ e1 L, s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) h9 g4 {8 h% m! l; U} + Y8 E3 O( [$ f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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