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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. x4 y2 O4 U' u9 }) x
input mcasp_ahclkx,# i. k- u" g: S$ l8 e, s, J
input mcasp_aclkx,& L! r$ x( v$ h9 c2 ^" Z
input axr0,* O6 q/ q& b2 L( y! A
0 `2 g% O% D; I4 Y( Houtput mcasp_afsr,
+ v. o: X9 E( F! routput mcasp_ahclkr,) q9 b; F3 u/ J
output mcasp_aclkr,
$ Z2 Z5 q7 }# g. w/ B( ^& soutput axr1,: Z; _( `6 Y7 \' j" p- m" K
assign mcasp_afsr = mcasp_afsx;1 l: |' ]; B7 F
assign mcasp_aclkr = mcasp_aclkx;$ b$ T$ E4 x& Z4 k7 ^
assign mcasp_ahclkr = mcasp_ahclkx;
& [$ v+ ?6 y, o# S1 M0 ]assign axr1 = axr0; " k% C% Y7 m4 R3 D+ Y0 {) h8 u
: d( G2 D+ b6 ~: u v/ C) B9 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 h$ b2 L9 I$ O$ ?6 T$ Wstatic void McASPI2SConfigure(void)
# f0 b/ l- Y5 A$ _: N6 D; P{
7 ?6 j+ f R7 b, `McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 L5 b3 d; q. Z4 v7 f3 ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 ` E5 d) B+ W% G/ W7 R6 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 T0 I: M7 F3 k9 k$ [) ^
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' s& d9 |' h- I9 y! zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; U3 a% w. B6 \
MCASP_RX_MODE_DMA);
# \& b5 q m8 K0 @. cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) }9 G9 @- W8 b+ F8 ?5 S6 lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% \" @3 M- z7 \ y. TMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' _! R3 _$ `: b0 }- D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- K4 |4 F0 L& i1 E& R% Q: K1 lMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 W- T' e6 W6 s& y& v# i7 ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 U5 A. t) k1 F; t* q" J: jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ ]/ H, ?/ T9 Z1 U/ n& m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - D z. S: L @7 l- h
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 y' {5 }8 ?4 \0x00, 0xFF); /* configure the clock for transmitter */3 D `6 D5 a% Z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; B1 J% r+ h# c/ O' x" q6 NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) H, O' a: y2 S- r
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* i8 v# c9 o+ t0x00, 0xFF);
: u" M- U8 t* I. j/ E
3 a% P" Y. p# Z/ V& r) x/* Enable synchronization of RX and TX sections */ 0 w' g8 o$ f; \0 Q2 P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: `# l1 r' \: F# s" E nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# y0 w4 {% R# `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
j2 P- R8 O0 T6 ]- c7 Z( ?** Set the serializers, Currently only one serializer is set as
# q+ i( P- S5 k3 X( U** transmitter and one serializer as receiver.
4 M7 B. D( F$ i*/
1 ^& A3 y# u# |- y4 W8 S6 o% }! p3 \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 b$ s- Q8 {: z/ c+ w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. w! G! I7 [+ h( W0 C! @** Configure the McASP pins
4 n* k. E" ^) H/ }** Input - Frame Sync, Clock and Serializer Rx
" k4 M2 `5 f5 a7 w1 E3 o** Output - Serializer Tx is connected to the input of the codec
; b( I9 e0 C2 ~* H; s*/
! e# V. x8 \2 F" ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, W- _9 |4 {1 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 E M" ~9 I. l8 `0 x- pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 c( |( z. p' W, S9 U% c$ c
| MCASP_PIN_ACLKX
& j' j2 w1 E/ v) D- W1 {( h2 z| MCASP_PIN_AHCLKX! R; U$ Q5 ^+ ]% f: |# B9 k
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 f' a& }$ t% P ]' K/ r. xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* V; D- q1 g; z v$ g6 N| MCASP_TX_CLKFAIL
& k9 r! m% [' R) Y, \5 b| MCASP_TX_SYNCERROR: ]1 N! n8 E* G, I c. I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , E O: p6 i5 o( v. c4 \
| MCASP_RX_CLKFAIL
9 Q1 n7 X* i/ x( b& f| MCASP_RX_SYNCERROR
6 Z" f) z* U3 H" [8 L) y1 G| MCASP_RX_OVERRUN);- i2 l; L* F# K+ E3 d3 [ T
} static void I2SDataTxRxActivate(void)4 a1 }' k! A; N- E$ a- a
{
8 b( B) V$ F4 V* g* g5 ]/* Start the clocks */8 ?) Y, ^' A/ @4 ~% `& B A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# v' o6 l* u5 n( Z" B' QMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// f% n4 a7 W4 q% V! ^8 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ A* {- }" l, N1 R. ]" TEDMA3_TRIG_MODE_EVENT);
; e, l8 ?5 m5 J" n8 Z0 ]6 I9 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: R+ U2 [% i% t4 H' VEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 C g; ~5 E- N1 uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& e) o# ]3 V' {/ Z- j% h; {
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 S% d5 ?0 {% g- c+ Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 a$ x3 }5 ?# B$ `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 u' l5 S s3 v2 [' c' fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
G' b3 m" b2 m* t; h* z} ; T- {( P4 }' J# w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - i# w }4 a: N7 Z- H( v! A" b9 v6 ~
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