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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. V q6 T; `* h% [
input mcasp_ahclkx,# Q V1 x- b' P' V3 l- Z0 v" ~
input mcasp_aclkx,
; o" j9 _# c; j( C: ^! r4 u! r6 ?( Q. iinput axr0,2 Q9 e& L- m m2 V: i# @
) w% d8 M% w" }' Q& H' P2 j! c
output mcasp_afsr,. r' u# F* r% z2 v* H9 O+ Y4 G
output mcasp_ahclkr,. \+ e& H. a5 c/ p7 _6 W1 u: ^
output mcasp_aclkr,
5 k/ j" x- ^% h& loutput axr1,
9 P+ S( {( y7 F4 T assign mcasp_afsr = mcasp_afsx;% Q: E8 }0 H. [
assign mcasp_aclkr = mcasp_aclkx;
3 _0 J5 d. P1 Q% Xassign mcasp_ahclkr = mcasp_ahclkx;
! |8 N m2 ~2 H4 d4 t. j7 n9 _assign axr1 = axr0;
3 }# }5 X* t1 n" \0 ?
/ g, C: x0 ^- r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' w4 x4 ^3 Z' a, U) D
static void McASPI2SConfigure(void)
2 l) j8 z0 o5 F8 I2 o& v* T{
; |$ {: ~5 A6 r! C. ^. lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
! S* |" c! E9 Q* d1 L6 ]( KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, P! s" R" W* }: c. N3 u; `) ^9 HMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# f. p, y# J. P" f) l# b
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, @( L+ f ^$ R( H% l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 b- S4 R( U: C- v& lMCASP_RX_MODE_DMA);: S/ J( r5 ], D- L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) n, A. i8 H9 `% _6 p$ k
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' Y; n% ]8 f; M- l* u" g7 q, p$ sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ R! ~8 i5 p4 g4 e& O5 X& d6 Z! R( TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ e, m- U5 J& i( q ?* tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( q* J/ R4 |% E& {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) B# s' i' H. F6 j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 ^/ ?9 k& n) t1 z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ B3 C$ G& C" O' w3 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, i; z' f0 V/ w3 a$ g
0x00, 0xFF); /* configure the clock for transmitter */
( d4 G7 F0 f* S0 i- J. w' R' U0 PMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. Z* m. E) I8 d l' D, ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); / N' w; m: T# f4 e- }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
[% h, z' ~3 y3 q3 j0x00, 0xFF);
9 |6 {2 O! z2 f6 p
; X. K: u b" @' x' J* [/* Enable synchronization of RX and TX sections */ " ]* T, ~" _! [ |+ n3 o
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ l" {: S* ^3 m& r$ F) ]% F x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& X9 \! K: A9 a6 A' M$ m+ A# [6 OMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) L/ c; s+ c- _
** Set the serializers, Currently only one serializer is set as
$ N& d. [5 j4 g, w& b( L9 f** transmitter and one serializer as receiver.2 a U. G4 K4 g$ L! Z
*/7 D# d+ D/ [+ P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 h+ p7 T) v( L( C- S' i8 JMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
k7 x+ L8 ^4 Y0 }6 [. ~3 I4 C** Configure the McASP pins 7 Q2 m9 R' s- X$ j
** Input - Frame Sync, Clock and Serializer Rx( o" \5 ~7 `) \, h! d1 R
** Output - Serializer Tx is connected to the input of the codec 5 N* u2 J6 X+ w% a4 ^' J9 y1 {
*/9 V) ^6 A% ~# u- [1 K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ ] M0 `$ f; Y9 H; @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) M+ j( M( T- `' q! x" ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ a# G* e' H! J5 x; D& {| MCASP_PIN_ACLKX
6 } f4 J9 s+ w; q y, r# y6 I6 N| MCASP_PIN_AHCLKX
! T x# @- H2 H* A3 T% I& T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 | K b0 R+ q% zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- P* O# G9 t1 h3 || MCASP_TX_CLKFAIL
; t$ c' {& R, R4 q5 C+ {$ || MCASP_TX_SYNCERROR
) o3 n( y2 B5 }3 [! t& J; j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 l) A7 F/ G6 Y$ i2 Z| MCASP_RX_CLKFAIL9 Z3 Q- q2 {2 H8 S( w. g
| MCASP_RX_SYNCERROR ( C7 E8 @6 [" z
| MCASP_RX_OVERRUN);3 ^+ }- Z6 Y* G& J+ N* [
} static void I2SDataTxRxActivate(void) P7 M% F5 Y; Z; _3 R: M% ]
{
8 l) M/ F4 M9 Z/ x$ @$ N/* Start the clocks */
) e4 R+ U2 F( R4 i# _( @! VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* R0 A% I( L5 G3 \2 XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' A/ L3 c2 S% u5 d7 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" |4 p* E$ ]% ~8 S4 A9 n( fEDMA3_TRIG_MODE_EVENT);
t+ b t% R; y+ K- ], b' ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 J$ f9 h% C( D* l+ Q: D8 M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
' l- ]/ k' q& |5 B8 qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* }4 x; o1 \* P4 n* }4 |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ S3 H+ c$ ]: L4 T Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! B) O2 K3 Z1 T* M) zMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( z/ k+ R4 \1 L; }# gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( J# v2 Q4 k4 P
}
# l9 [% V+ f) z+ q) V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + {& _4 |1 a/ }
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