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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! i% U' L: u4 p9 Jinput mcasp_ahclkx,
# L9 C% c9 \/ P5 {input mcasp_aclkx,
( `4 v: _* T7 m$ R8 s# j5 h6 l, ~input axr0,
' H+ ]8 g" ^1 m- g* R( s' _6 K+ P3 e2 M8 o
output mcasp_afsr,
9 D% ~1 a c1 @0 b+ T9 M2 ^output mcasp_ahclkr,/ ]2 J, r1 }+ ]8 x
output mcasp_aclkr,
& C. [ {/ o% B* R! Goutput axr1,
" k3 o3 Q9 n7 r assign mcasp_afsr = mcasp_afsx;) D* v3 r- }: [
assign mcasp_aclkr = mcasp_aclkx;
9 R; L' I& t4 o' ^& u1 uassign mcasp_ahclkr = mcasp_ahclkx;( _5 p9 _5 M2 Q) w* e& n2 F
assign axr1 = axr0; - h( S% Q4 i9 R f$ F
3 w; n/ f. c2 E1 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 }, p n- ]/ K
static void McASPI2SConfigure(void)
( o. h3 ?( h* x& W' ^{
: U! o0 H# F. ]0 m# E$ X3 YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 d: [- J' h# [, g* r7 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" u2 W' a y" S( G0 c# Y" E) B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 ^1 F) _9 _& a& S% U) WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' M! H5 N2 @. B7 A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% I5 i0 k3 n" I& t2 o: @MCASP_RX_MODE_DMA);
+ x+ \0 A9 d- [0 j! r( XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 n! q/ S9 l( }' H6 {& p% hMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 U4 U$ T. q6 ?' ^4 }! @/ l, uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' J- z- j5 `7 JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' z+ ~: s" c- ?; ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( y# N2 i! C! o/ r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 z; Z' t' o& r$ C, m8 _) z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 Z$ _5 E% G' O) ]McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : H1 k. P/ O+ W: c& X$ `- N8 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* l9 n" Q& `% I
0x00, 0xFF); /* configure the clock for transmitter */
1 w, J" t6 V6 u# OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 N9 o# l' T" D* t2 B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); T7 D+ X, h% a" Q3 @* Q9 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. O* i+ _( N8 S/ D3 j0 O
0x00, 0xFF);
! _# E U' i# x) N) V
& ^+ u! n( U: ~) b/* Enable synchronization of RX and TX sections */
$ k7 b: g9 t4 ]* U) D% F% z) h' JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */7 Q0 b" b1 `7 B/ d. H; P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 m* ~2 P( ^( | v5 h8 `McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ q: a! W, `) o- K** Set the serializers, Currently only one serializer is set as
2 N( ^" F. u# O- Y2 _. z** transmitter and one serializer as receiver.
: ~' T* i: }" T' G- F6 j, u*/' e! ` }; Q# T& x7 s+ l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: X/ Y# {5 D6 O% O( O& Y$ e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" C& h: p. e+ U. m
** Configure the McASP pins
6 f! ?7 s$ j+ z* t** Input - Frame Sync, Clock and Serializer Rx+ P {, G$ b: ~) m; j r2 W
** Output - Serializer Tx is connected to the input of the codec
& w8 x- I& U' B, x `) b# z5 u*/
1 v0 q7 z9 e( X/ y1 r4 a% }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ O9 u8 L! l8 E& U. |6 _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ P: f4 i/ x9 h9 a$ uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX3 N6 \* R6 B g. a) B
| MCASP_PIN_ACLKX
7 [. z3 Y, e( b| MCASP_PIN_AHCLKX
5 }: A G3 t; Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 S* O4 D9 H6 k1 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . h& t9 X. i( w4 C" L, p; Z
| MCASP_TX_CLKFAIL
& H8 n- s( @( N) k; |3 y8 @| MCASP_TX_SYNCERROR/ E4 ?0 G# W% F* O8 g$ {. _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 Z" p- ^4 G& w8 w* s
| MCASP_RX_CLKFAIL
$ L; R$ }0 ~: ^2 K; L| MCASP_RX_SYNCERROR
, W% g0 @* ?: ^! R( ~| MCASP_RX_OVERRUN);
. I5 B6 U% w% ^# q} static void I2SDataTxRxActivate(void). z0 w, ]; }3 M' A" o' q8 F
{1 Y b: A) A& K7 @8 D6 y. m
/* Start the clocks */
- [8 V0 V" C& M9 ~2 h4 j% r6 IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) B O; g1 {# I
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ B0 J$ ?4 Z. \9 M) ?9 Y& BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 z) w0 R' G/ q* @4 F/ WEDMA3_TRIG_MODE_EVENT);" j9 R' s1 c7 K2 Y: v: D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + D3 b* S; M5 d" }8 W( l8 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* U3 x1 ~5 u- R# F* X" GMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# P3 K: f* N) M; ]% x6 uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. ^' J+ N# }4 i! |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! f6 G, _! W; D$ e2 g
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ c; i7 b( t( c9 b) y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 l6 E2 B- S% }& g3 w: ? { Y
} & ]. k, V3 X* ?- ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # k8 x9 ~: i) ~; p8 Y
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