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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,* u- E+ ^+ \8 [5 j
input mcasp_ahclkx,6 [+ _# V) Y, x. z9 y5 O: q4 t
input mcasp_aclkx," E* s8 b& G+ q* I
input axr0,
' {% R, N1 o0 n/ c2 `5 E4 c; Q2 a* d4 S6 K$ C
output mcasp_afsr,: m4 I# e5 v( g2 W/ Z5 K, v, T
output mcasp_ahclkr," s+ ^& s4 d) |# c$ G: G& ?
output mcasp_aclkr,5 l$ ^( \( `2 Q! }( y3 u& I
output axr1,
2 T" `$ X+ O; h( G3 h+ ] assign mcasp_afsr = mcasp_afsx;
- t. V: e: P: M. ]5 [assign mcasp_aclkr = mcasp_aclkx;
3 f- m+ U# x5 L P$ `assign mcasp_ahclkr = mcasp_ahclkx;
; E# X& w1 j- h6 Y. Yassign axr1 = axr0; + ?$ }9 c; }6 q: V' s- L& u5 J
3 A/ u* S) K( n$ \& Q: S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 H6 x( x/ D. j, W8 U0 nstatic void McASPI2SConfigure(void)1 j1 r5 u* j+ l$ g6 d8 R9 `
{
- U# O3 _7 F* g1 \- q- ^2 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) `2 \' n1 [$ A! U" [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */% s2 d1 ^$ n0 h9 t6 u) Q( {
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);2 n+ i/ F: d. C0 u( H8 X
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ j3 F0 V& [1 @( k; L" @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 z& T3 W& O0 l1 P6 BMCASP_RX_MODE_DMA);1 N5 B! w, z% B7 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 v" h5 I5 r) D6 ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 e! A, r' @ e! f+ C ^, m- PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # ?7 ?; H" {; w: Q& V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
Y8 B* K. z* c9 x* Q. bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ) x) R0 U5 D& i2 t! x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 Z1 [& r& j6 R) M% i* E: aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* Z9 M* [- T+ H% Z s' M2 ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . c$ P# r4 _: E/ v# q8 R* c2 `/ `
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' |4 w# J7 o' D- H3 a3 ~% D- }1 y0x00, 0xFF); /* configure the clock for transmitter */7 [+ N4 T3 H3 O/ u- c5 T) I) }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 A' c/ o+ c. \9 P' i) \" S
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 d6 C9 U7 C. h; O9 u z2 mMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% S7 ^7 C) D; p; z) O h0x00, 0xFF);
! l6 r" W/ ^8 Z5 W' ^6 u
! e" V, K7 c& j0 k9 m/* Enable synchronization of RX and TX sections */ 3 e4 s r% g* ~" `; ]9 X; K+ L) e; H
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- J; Q. ~5 s N" N E1 x; mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. ^# X$ \* E# g+ t% w& Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" A# B1 q8 l. `1 B6 S6 m* {
** Set the serializers, Currently only one serializer is set as/ i# S2 R8 U% w' L* J# {7 E
** transmitter and one serializer as receiver.; ~: T. ^+ ]) k |* }; @7 d
*/% `6 ], {5 I2 i @' Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 @# O0 x5 U5 GMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% v( k8 ]0 S: Y5 x( v# K2 B! o# P** Configure the McASP pins + G& r" | {$ x5 G& Y0 O7 O, c$ `$ [
** Input - Frame Sync, Clock and Serializer Rx0 m3 \& I. V, x. K1 z4 }2 ]
** Output - Serializer Tx is connected to the input of the codec
. i" P/ _( ^8 J*/7 j# S: @5 L7 k8 g
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ ~# v, T( a' T ` R+ MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ A" d- v. w/ m" v0 z) @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# ]! `- p3 V* J+ L; s3 g| MCASP_PIN_ACLKX
) s& S8 U! K" Y) {* X. x& Q| MCASP_PIN_AHCLKX. V/ J: ^7 L' T b2 [
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 }9 Y1 |# j& O! a7 x* ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # l) c3 U1 w9 e7 P4 B% T% k9 C
| MCASP_TX_CLKFAIL w. n: d/ t# B
| MCASP_TX_SYNCERROR
2 [! |$ K/ n! r& O5 z8 @2 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , m2 B) a9 g$ V8 I8 k3 A
| MCASP_RX_CLKFAIL/ O9 J v/ O5 R; Z. ?2 h- i5 X1 l
| MCASP_RX_SYNCERROR ( P: A8 M; g! t# g
| MCASP_RX_OVERRUN);
6 l0 ]9 J7 I$ y% N5 w7 [} static void I2SDataTxRxActivate(void)
; R3 e W/ o M) g. Q3 ]" f{
6 ?) @$ o5 s; X: Z4 G; c/* Start the clocks */
0 r! I+ R) P8 s: v/ `/ o9 y% gMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
! c2 Q. E% ?0 y& _4 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" b G5 ~8 l: {+ n: ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ E0 Z1 M1 E3 g4 v: E
EDMA3_TRIG_MODE_EVENT);' l. ^) i/ w7 ?. |: C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, C: s9 A. S$ g; ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 \, x+ i' p3 ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 A# \1 D: W; J' h+ E/ m
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% p) g0 m3 v( h$ F' l( b1 e$ H8 D( @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ u# R1 o( f v. ]! }. `1 dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! n3 O2 J+ ^( I2 AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 _, p3 {# @+ [/ K$ W4 ]6 u
}
~" v* `3 x: w# Z& A7 x4 p; N+ F6 [请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 I2 S, r2 ~* ^, d) F
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