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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' K% m ?( K G$ g0 i
input mcasp_ahclkx,
( B0 g) K7 |; hinput mcasp_aclkx,
, J% U' H; P. b) hinput axr0,
8 {( { o+ A& A% i$ V% g$ o
8 i5 \ [, e2 L, X% soutput mcasp_afsr,
F* G* ]2 P: o" @: F- |0 K3 g( @7 ?output mcasp_ahclkr,
7 L% h+ R F6 z+ j& m- k2 t! A4 q Boutput mcasp_aclkr,3 d% e2 N& S% q# I
output axr1,
- B; {" U H; t. ~ assign mcasp_afsr = mcasp_afsx; I' u/ Q- s! y% j
assign mcasp_aclkr = mcasp_aclkx;
, i( d; t0 I- U& g) D+ {/ iassign mcasp_ahclkr = mcasp_ahclkx;! ^+ Q" d3 q2 e# H! f5 u! J
assign axr1 = axr0; 6 T( L5 H/ I5 V, q
& [8 t" e7 \" L; I3 S3 D在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 . D9 h3 V4 q1 x6 L7 M- q8 l
static void McASPI2SConfigure(void)
/ x4 ~# J0 _" O, L2 S7 p( B{
2 ~( I0 V1 {" \McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ r5 |- P$ x# {, i5 U. v" ?1 _* U
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" `5 G% c' P% FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! X2 h+ s9 L$ j. c; G4 F0 yMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ a% L# z: C: f% s1 y2 a& g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, b6 y1 Q3 h7 a; {
MCASP_RX_MODE_DMA);, t5 C) r$ @/ i+ c- B+ j9 S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 I, W) z4 I9 @- c: z/ e
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' F+ a9 J# g$ m; M6 t/ q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; P) n6 x( ~$ ?/ [" @0 a" f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 E8 A3 i, Y- O. d- h* n- r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; j( `4 \; k6 t/ Q3 W3 U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# r1 d4 {% G0 g0 i# B3 HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, e$ y3 [+ G2 w$ t. V& G$ |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) \( Q2 P7 T0 ?. ]& N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# d" m7 P8 b: k0x00, 0xFF); /* configure the clock for transmitter *// ?" W9 p$ s M1 c" V2 \/ o; a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% k% Q) Q4 l5 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 `( N1 a# w; W5 s$ C5 ~% B2 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 E; f, p7 y$ `) b9 J, e0x00, 0xFF);, }4 D! W4 N; _, b; Q
/ n( [: W( @4 o3 w/* Enable synchronization of RX and TX sections */
- V @/ l, w: Z, {/ GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( |: Y0 Q4 K/ ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 }/ \ c# R* vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 m, k/ y/ Y5 U7 s** Set the serializers, Currently only one serializer is set as
0 O- m6 r w! b/ _** transmitter and one serializer as receiver.8 H% z7 m/ ]. K6 O/ z5 S
*/" H5 b# ^9 W. S" A( `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
| L0 r1 g! f0 F6 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* J+ J& J4 H9 x a; }6 Y
** Configure the McASP pins
$ Z8 x' b8 c7 |9 p8 K* z" C** Input - Frame Sync, Clock and Serializer Rx
2 I7 E2 D5 E# T7 X** Output - Serializer Tx is connected to the input of the codec - Q2 g* m0 B( Y" a& {6 s
*/+ ]$ H# K7 }" G5 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 n( L% u7 M) a' T( I+ H9 r! QMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) e! N W5 s. J! X9 @2 X4 QMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
r, z4 G: [) M( f! y, X| MCASP_PIN_ACLKX
6 U! ]- |: \! v4 V+ U& q| MCASP_PIN_AHCLKX& m9 p% u/ F% Z1 j, U y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) I B6 b4 K) c* \" t6 q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* }. ?! B; i: B' E9 W! s: b| MCASP_TX_CLKFAIL & `: b$ U; D, h3 l2 F
| MCASP_TX_SYNCERROR
" g' |! M2 c! @% N" f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 1 l; {1 {* i1 `: T
| MCASP_RX_CLKFAIL
) X) m) M. R4 {5 ^| MCASP_RX_SYNCERROR 1 U5 @ R- P! `3 q( X, I
| MCASP_RX_OVERRUN);
! p& o3 T" P: q' C} static void I2SDataTxRxActivate(void)
: }% P' ^8 _# [* y$ I! F{/ f2 _" H6 Z& B& j7 x9 c. X
/* Start the clocks */3 j, e- c' K. g: g: ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 y' O. e# a5 X( E
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 F9 g7 v4 z e* q5 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ G! w& @- S! t
EDMA3_TRIG_MODE_EVENT);, W. @* X( g, n4 P& W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * @. ?6 p7 ~' X. a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: e5 r$ c) s1 [. ]McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 D9 _3 Y1 x3 ]% s( h. R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 l b2 B0 P% u) L+ s
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */3 W/ m& x* P1 [! i1 n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* j; [! q4 o9 ^$ E
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 C& v/ G5 ]1 N% l o* c$ ]} + {$ w: t' ^. q4 e( i# u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. |3 F9 H# b* ~2 W( {, w3 P
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