|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& M- v# `( M2 a6 K. }; |input mcasp_ahclkx,
+ T; u4 K. ]. c/ ginput mcasp_aclkx,5 f- g& r# T0 R3 c1 C! I
input axr0,* p, \; b- ~, v0 ^9 }5 D1 ]" w
, W: B7 Y& R, O" @
output mcasp_afsr,
7 F6 k$ Z: j% s' ]0 j# a% ooutput mcasp_ahclkr,
% w* D/ X" l9 N6 U0 ?output mcasp_aclkr,
2 U: ]9 | N# ]% houtput axr1,! @2 g0 c0 a" f3 v1 a5 `# m
assign mcasp_afsr = mcasp_afsx;
7 K* c7 }: F- {$ \assign mcasp_aclkr = mcasp_aclkx;7 t3 x* |$ N" W* X4 ?2 e
assign mcasp_ahclkr = mcasp_ahclkx;
. [8 S- j1 m: I, x: Massign axr1 = axr0;
4 V- _" H. a) {- [, Q6 Z: m- c8 D% u% I" x8 F4 [ f0 N1 }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
4 f; r6 I$ ~% Q6 ]2 p6 [3 istatic void McASPI2SConfigure(void)
; l& k* k7 ~7 T: j. p. _9 H{
0 C$ D0 b2 O$ F* \& M ]. MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& h2 {1 K: S! x, V v. ^9 o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ i, a) _) h" S& m' |- I. C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# y) |( N4 T8 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */1 D2 W3 ^% [( T% \+ ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 R; w3 D8 C6 o/ IMCASP_RX_MODE_DMA);5 T! G7 Z# O7 _) u \6 c* b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: O* L( q9 y- P: H' e! I
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ z9 L5 `: R( o0 F2 g; u+ x2 L6 RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ t" p" D$ p. i4 PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 E6 E6 ]0 s" |# z/ uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - C) H8 {2 V6 B/ J& ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. g9 Y, \4 l3 ~4 _/ FMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 j4 t( A7 ^& U+ @0 p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ L1 W1 u7 c0 b
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. L2 [( }) A5 y0 O2 Q" o8 c0 g/ O
0x00, 0xFF); /* configure the clock for transmitter */
9 @& N0 c+ E7 c5 S3 kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 Z9 x& P; Z9 z9 B* G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : K% D# I8 v: m. ^5 ^' P! Y+ t7 D6 b
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 q: k# P" p8 ~' f; s0x00, 0xFF);- X" ^. D, Q% {' P$ x/ J {
4 t- Z% |# h2 D" ^$ @/* Enable synchronization of RX and TX sections */
) O9 G) }9 {5 t8 c9 T4 BMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( h1 H) L. H# e: t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# u: g9 `4 @, {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 @+ d$ i, Z, z** Set the serializers, Currently only one serializer is set as
% w; a E9 M9 @8 P6 d** transmitter and one serializer as receiver.: {8 `8 K- K' \8 }
*/5 z2 ^2 }- |) y3 o* y. ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& I0 u; _7 Z0 t' z q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 L1 `4 w6 O4 N. F** Configure the McASP pins
) N; O7 _% O5 q** Input - Frame Sync, Clock and Serializer Rx: c8 }& ^/ v+ L9 K: n
** Output - Serializer Tx is connected to the input of the codec
4 r+ @% ` S$ D( W*/
7 k& ] {4 t+ F1 D# {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! R0 b: b4 c) {) R
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; G, S a p, J# aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
W$ h9 D9 A, W! t7 u2 S. ~| MCASP_PIN_ACLKX+ X, `+ E6 O, w% ?' F4 L
| MCASP_PIN_AHCLKX# K* L6 A5 Z# B) p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# T' X h$ @/ Y) [0 M$ ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" h; F% X+ A u* o" X. w5 ?. n7 q| MCASP_TX_CLKFAIL
- d& W2 i6 b" _7 U e" O6 k| MCASP_TX_SYNCERROR
2 c6 T: }' D8 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . @9 K* a2 {* M$ ]& o8 v, r7 E
| MCASP_RX_CLKFAIL
& |1 S8 w5 a( ^4 P: b| MCASP_RX_SYNCERROR " D Q) W8 j# A" {* V
| MCASP_RX_OVERRUN);
" r G! o, s1 Q! E. ~} static void I2SDataTxRxActivate(void)
- Y( A0 ^+ C8 S: P2 q- \0 \{
0 [$ W* ^+ H% Z6 E2 b; R/* Start the clocks */
6 I" ]' K h8 m6 e' N0 kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: Q, _2 a8 u: C' L* ~1 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. k; l* F% f0 m8 A k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; @8 t4 }( v2 Z2 JEDMA3_TRIG_MODE_EVENT);# D- O$ z$ y& N9 _% j
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' F6 f8 r. B" g! o3 z+ u& x9 FEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, @2 F8 R2 g3 ~; G- j1 e5 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) T8 y& q% r4 b1 a& P6 ?. l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
, W$ M% |9 ~, bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; m# W' t- D% p+ uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# g& E; o; K) S! l/ HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ x( S) \4 I3 [* F8 a9 g9 O}
4 p. Y% t+ Q; K% G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + d2 T' l0 L. [ F
|