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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; g5 T2 m8 N, H: g. tinput mcasp_ahclkx,
! k, K: T$ k, @" [) I0 oinput mcasp_aclkx,
% e; m7 Q; S4 d8 H5 l4 Kinput axr0,( R8 b+ l0 E T. O' h$ O: j, T
% }! V2 R4 A2 e# i
output mcasp_afsr,
3 ]0 v6 ~! c! P# ]$ G$ goutput mcasp_ahclkr,
9 D" k7 t9 w! k8 Y% [3 }4 boutput mcasp_aclkr,
# B/ |' ~6 L! M5 y' f; houtput axr1,9 Q. h+ N! a3 D
assign mcasp_afsr = mcasp_afsx;6 U% E4 [/ M, L& J% O" b* G
assign mcasp_aclkr = mcasp_aclkx;
/ U- a1 ^- J. f8 K' |. p+ c6 aassign mcasp_ahclkr = mcasp_ahclkx;
; z* r( p2 c3 e; kassign axr1 = axr0;
- b4 i1 j3 O4 U! V
- N, F1 g+ d$ c$ ~: Q* ^' \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 |: C- R [+ p+ s- ]/ e3 x
static void McASPI2SConfigure(void)
: P0 t+ l6 Y& A{
( A" f6 L+ u2 |, U- z4 bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 E1 W6 ~8 @5 I4 \7 eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 B9 W5 Z2 k1 w# zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) ]: ~4 Y: C/ x2 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" S6 z# q" I) o- x) |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( e2 e# p* [( m3 R4 _
MCASP_RX_MODE_DMA);4 P7 y7 Z* _$ Q- d7 O9 J# S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 h, f* c9 ~$ H. l" sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 z0 j/ v& v' Z( U5 l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ P( ]8 C; |% n- x' }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: R2 m" Q& A* k, f# ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% |2 {- V- l/ f4 A% ~/ T9 gMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 ? i, w" r6 G5 ^* g/ R. }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 f. b% L+ x' F! v( z4 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); P* a4 h H* \# i* J. {4 G' @1 g
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 G+ T* o/ G" e7 e$ W5 {* E0x00, 0xFF); /* configure the clock for transmitter */
) o/ N/ G& T- a# t w& f) \McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) H. w* A# J7 f9 C# [4 j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; _8 @. o* L$ V4 m& j+ bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- _" d- d6 W0 k
0x00, 0xFF);
) {9 a9 b2 b5 V1 \. }
4 i$ T& a1 f% t/ d* x1 u/ L/* Enable synchronization of RX and TX sections */
u0 I& f/ k! j! YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) R% {3 M; s4 s9 O7 q, |# u0 W
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! ]( ^2 ?+ A2 n9 V7 \* O1 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) B& c% k1 Z' F6 x4 ]" q6 M
** Set the serializers, Currently only one serializer is set as+ t+ o# m& N' u
** transmitter and one serializer as receiver.9 }: v1 n! N4 n9 {
*/
/ n; R4 b- ^' K! y4 F3 e! }) vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 m a, M0 t% l+ ^+ EMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 g$ q) ~2 O2 ^- \- A/ {** Configure the McASP pins ; V! y' |. E' q0 e
** Input - Frame Sync, Clock and Serializer Rx2 P7 ~! a! D. t& X/ _5 n
** Output - Serializer Tx is connected to the input of the codec
# o ~% n8 e3 c* D*/* B0 U, |5 E0 G7 n2 g% Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 a7 E/ i# W, i8 v/ j$ _" iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. X$ ~& ?- i. F7 r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, M9 p4 S- D l. @* g, g
| MCASP_PIN_ACLKX0 B' @2 W3 Q* y
| MCASP_PIN_AHCLKX0 h" g: L' U7 p* F
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: f3 h) V+ C" g. p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 X. ]% T2 m3 l1 J2 Y# u8 a| MCASP_TX_CLKFAIL / ?- d ]+ G& P" ~3 l2 ?
| MCASP_TX_SYNCERROR
: i7 E4 a5 e+ I# f0 r2 k: Y# h( n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ n4 Y; w& i8 Q2 X! Y" N3 m! c| MCASP_RX_CLKFAIL
- ]! L3 [2 G' |' q. X| MCASP_RX_SYNCERROR @# V1 B* v: y# r( W/ W. c
| MCASP_RX_OVERRUN);; b$ ]5 L* `1 P M( p# S
} static void I2SDataTxRxActivate(void): P R& D9 U K/ C" U5 ]0 j( |
{
2 Y! Q2 |# f7 P, W' `3 |$ n/* Start the clocks */
( z) U7 A# x- G4 g$ oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# K; ^" c4 X2 i) |8 S+ t- Q6 ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 {' w7 I; m/ ^! t6 h& L) \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 t* C/ n- D6 G% t& JEDMA3_TRIG_MODE_EVENT);% U: K9 y/ ^: X! v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' A& ]# Z# L; zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ n4 B! |6 } S2 ^# A5 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ s6 X: g4 d, I3 v5 B. i% \4 L9 F
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 K Z9 F W$ V& K1 U; @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 c1 e& X, F- P0 D" J8 x. c& c" s5 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 H$ J7 {- @3 K3 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 x( X- X9 P1 Q8 u* B; q: d
} ( Q& a' E4 a6 I) v' k0 R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! i, g8 J' c8 Z* X v
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