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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 ^$ v3 _3 `- x1 }* U% Z1 G
input mcasp_ahclkx,
8 F9 I3 W3 Z) H& E& H! _" _! Sinput mcasp_aclkx,% h: u$ y/ ` l2 l
input axr0,
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, e( v M6 s; U- e6 Moutput mcasp_afsr,* I8 D- F8 X! Z8 u2 ~9 w3 ~& S. z U
output mcasp_ahclkr,
' ]) x9 e K1 v S* i9 Boutput mcasp_aclkr,
/ ?/ }2 m7 |9 Y$ X. o* W; Youtput axr1,: T: J. |; j4 @" @9 J
assign mcasp_afsr = mcasp_afsx;8 j2 o* _) v( `$ C* k, x7 e
assign mcasp_aclkr = mcasp_aclkx;
+ f, b2 z! s/ S6 M: e% I: f0 G3 o8 tassign mcasp_ahclkr = mcasp_ahclkx;
- j" ?1 \# q5 i6 Jassign axr1 = axr0; , Z, S3 x: |* `
7 B- Q' i, F: h" b在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; h$ V$ d& V' jstatic void McASPI2SConfigure(void)
4 f" E' P& l5 c, i{: I" I. u. Z/ I" q; r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ z/ M& q- W( P$ t' qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: J" x5 d4 Q8 v& G7 a8 O4 a2 C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- b) ?$ [4 p! h2 Z, k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */, d) ^# ]/ {% X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# x& c4 W1 m: z4 LMCASP_RX_MODE_DMA);. Z: D0 Z7 V% N( P! ~
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; K$ N1 U# w9 h; m! t/ @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 ^$ y$ F0 [' e t" hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 C" M( {0 c3 O; p6 X* L c: n( R/ `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);9 T$ s/ r& s( P" b3 c8 |, r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 \4 n3 D! F* MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
) U+ b; K, |. \" q4 a: ~0 TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 | s; k9 t9 Z% xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. F# H& h& G3 L5 K/ EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" I5 S J- N" A0x00, 0xFF); /* configure the clock for transmitter */) h1 O, A4 A( r: _- Q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ m3 l2 c+ ^" j C2 E, }( y+ ]( d
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 `+ z1 R8 A1 E# x) G7 ]McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. Q+ y: l4 n+ E0x00, 0xFF);2 h' d3 O4 j C$ K
* |0 c8 L6 W/ V$ |5 m/* Enable synchronization of RX and TX sections */ . v$ r( k/ ?# u. i! m
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( L- l. ?7 v6 A* r- Y! L
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 ^, `$ v6 G" |
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; \" l1 m: |, T. J( z, b6 Q; u4 Y
** Set the serializers, Currently only one serializer is set as, J5 A' h% C: q+ L' ~* Q
** transmitter and one serializer as receiver.
W8 p, M0 ] z# R7 Y D" s1 `2 ^*/+ N0 g! s1 G. a. c) C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: v2 U) B! d- M! e7 J# IMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! b) L* ?3 L2 \2 I. y, L** Configure the McASP pins 1 D: x+ s, r: X1 u U
** Input - Frame Sync, Clock and Serializer Rx
_! H3 Q' d- _" `6 x; C** Output - Serializer Tx is connected to the input of the codec ) l: A+ J, V4 I' T) ^5 U7 \ Y
*/
|' u0 s' Y) C# o/ h% W# K- lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ N W6 e5 ^2 \0 s4 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) o) l; A; I( m, f3 v5 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' L: V& H+ ~* T q/ G1 i
| MCASP_PIN_ACLKX
# z6 m" }! w3 ]9 W; l6 Z6 d7 o# }! j| MCASP_PIN_AHCLKX+ p; w, \# C H$ V) @. p3 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 `/ B3 w% _& t9 Y% IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 I1 a+ y ^0 f8 V
| MCASP_TX_CLKFAIL # P* {" O% \2 q( I- d& G% Q
| MCASP_TX_SYNCERROR
# U/ e2 i4 D; B b) a| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) A9 N( @; j( S# L0 r5 \$ B7 B
| MCASP_RX_CLKFAIL u/ o* h2 q* k
| MCASP_RX_SYNCERROR 9 o/ i# a! C* {
| MCASP_RX_OVERRUN);! u. `! a W) |: o! B
} static void I2SDataTxRxActivate(void)+ a) e4 ]# G5 F/ a2 h) c
{
4 r8 \5 P" K' r9 U/ Q1 c9 X6 }/* Start the clocks */
/ E3 _: e; B. }' q5 h$ ^2 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 X8 a) z8 h! F, O" w+ b
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 y7 |; [8 W$ f' E9 E/ LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 y/ G, X" h' ^( f4 _
EDMA3_TRIG_MODE_EVENT);
' a8 E' ?: f$ |8 O, `' e8 XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; K& d) F! w3 V: j) ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 f* W3 |% s% c0 R
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; y$ u1 [ ~% OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! e ?7 i! F) P+ I/ P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 ^' ?; C* U1 q; v V1 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. C# f5 t5 m# [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- l1 C3 L' L8 b9 |. K: S}
6 c+ ~6 J5 k$ e' \3 d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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