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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# a2 d3 r8 V4 g& Z" Y
input mcasp_ahclkx,5 r9 n) i" `/ c, x* S& s2 b H
input mcasp_aclkx,
6 Q( A8 p& E8 Q* K0 l* R' dinput axr0,) F9 L3 S6 Z5 x) ^% `
8 C; ?& \, y7 O- A V
output mcasp_afsr,
7 L- i, g" R; f+ w/ x( K' uoutput mcasp_ahclkr,
2 O, N- E) N5 n1 I1 @% Z& woutput mcasp_aclkr,
1 s8 T# {1 [, C7 I9 S# Z5 P+ uoutput axr1,
0 Y6 B- t _1 ?+ K" x assign mcasp_afsr = mcasp_afsx;
; @* F( r" x& u2 O( R1 dassign mcasp_aclkr = mcasp_aclkx;
; Y1 R4 c/ w2 L) b# Xassign mcasp_ahclkr = mcasp_ahclkx;
8 W$ f9 z* S V9 A, Eassign axr1 = axr0;
& b { i0 _' P0 V& w& F0 s" X$ E! S5 }; D+ z6 o
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 q2 E3 k$ _! x) _" ]static void McASPI2SConfigure(void)
8 u1 `! w0 {$ p7 j& i6 X{
* p% e/ ^- l: {/ B7 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. f# k3 T5 ]7 s
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 B, j# t. d0 B! EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& l/ X- u$ X: Z) O1 f6 e
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 a/ e& f) C* {$ h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& K# h: s5 e6 r% bMCASP_RX_MODE_DMA);
+ d* r M& {7 W- |/ r- TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& j- V' E( P$ u7 J+ L M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& x! h; J. D) a0 l0 uMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 q& n2 a( y! F/ D' oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 E$ W, b/ |2 ?; r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 M5 \% H, @# R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 H6 i' N7 q. \( o, |. DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ b/ X ^6 z9 f. D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 R! I! ?$ R% O* Y$ @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! ~2 s. F% w, f: Q0x00, 0xFF); /* configure the clock for transmitter */ Z N. m) X I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 `) i- t1 P0 r3 J& u. G q( P/ l$ QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! n1 K' D5 {0 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, r( R& I* D* b3 `$ A; g: P" P6 P
0x00, 0xFF);
( A# D. ^) u3 p6 C0 C B) v0 Z4 o' M3 Y4 r
/* Enable synchronization of RX and TX sections */ $ s8 ]- S8 O3 E+ m/ l: `! h
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 |, P- ], e p- e; P9 L! s+ @& {McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 H+ K' E0 U4 J+ v, u. M- B! B
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 n. g% x+ N {$ N+ N4 b" {" f, O
** Set the serializers, Currently only one serializer is set as3 o. P1 o/ h$ w. p+ d2 O
** transmitter and one serializer as receiver.
2 N" s+ U" T* X9 e6 T*/
! r' P* }6 `4 q" U% @$ _% \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 T/ d! T7 ~+ |: Z4 P: tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! o3 l% H p6 Y B
** Configure the McASP pins # b& O2 y3 k- c. N) o6 z* u
** Input - Frame Sync, Clock and Serializer Rx" B+ L! s+ j! F3 [8 j
** Output - Serializer Tx is connected to the input of the codec
7 ?& q1 z4 ?& N, l2 S. c*// r9 P1 @6 q1 y r/ R+ {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* T, s- q# j7 p1 d6 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" v7 x$ e- }' c) O0 {: S% [- wMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX6 u! Z) O9 ?8 ^/ h5 v. d
| MCASP_PIN_ACLKX
# D i" T/ N" M' Q* U7 X- B| MCASP_PIN_AHCLKX
5 `3 l% X+ K0 w1 S3 N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 X; e# _" H0 B1 E0 O
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 4 r' |# k) p, a
| MCASP_TX_CLKFAIL / h, L3 y3 I; P# p% |
| MCASP_TX_SYNCERROR
, k# |2 \; m. M8 ~9 a5 E2 B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( D1 k9 m- T; R6 G| MCASP_RX_CLKFAIL
1 H- O) F4 _ H( f| MCASP_RX_SYNCERROR
& x$ l+ \6 X- d3 ]| MCASP_RX_OVERRUN);
: f( b' D7 N( C# O4 W} static void I2SDataTxRxActivate(void)# q& h8 c0 J, W9 Y
{: L ?! q6 D& u) M
/* Start the clocks */
, B9 B% k2 H2 i. }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, f! u. W. A! S- N" \; Z. iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" }+ _. E9 u* r6 D9 t( uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. ~: Y* N! H2 T, I; I
EDMA3_TRIG_MODE_EVENT);
3 o3 ]$ i& \6 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 _8 _/ Y D8 t+ e" F, Z! Q8 e; R# Z$ s
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" [7 o9 L% x& XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; L& W1 J/ E4 H& O3 Y0 K0 M k
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: Z# |/ U+ q8 U5 r Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' I3 x$ h& Z! s3 E1 ?* A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& X* x) d+ [# [* F4 L9 C
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: j" E! u/ D& g! g}
) Y7 L+ F) ^$ {" H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 g; Q) @) n0 E" [" k) u
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