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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% I7 C- I6 U' H4 S* v0 r( H7 Z0 Qinput mcasp_ahclkx,! o: U* b8 M; f! ]9 E
input mcasp_aclkx,
' C9 R: Z9 J. m; {" }, W: Tinput axr0,! g+ u% O5 }4 ?& m
6 e+ J& D# J# b* Z; |6 R
output mcasp_afsr,
3 x& _$ w- V5 t, qoutput mcasp_ahclkr,- M- {4 p# T' b4 d* |. ~2 s
output mcasp_aclkr,
) }. n6 H% C1 m6 {- joutput axr1,
3 Y0 P* R* g @0 | assign mcasp_afsr = mcasp_afsx;, V( H3 K0 O7 U& {1 u/ e
assign mcasp_aclkr = mcasp_aclkx;
( I" Q" y7 b1 X+ sassign mcasp_ahclkr = mcasp_ahclkx;
9 ^! @% d# |* g% L4 Z( bassign axr1 = axr0;
- G) `* K& B! Q% f) i' [) Z! Y* a4 b" u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& [$ y7 L0 L1 }, A) istatic void McASPI2SConfigure(void)
/ O, m' ?7 O& ?{' _/ s0 T, c& m2 D F% c( s
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- E3 D8 z# A, uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ I3 p) {0 h- f) C: r- E6 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 S3 x8 r; I% r; S9 v( }$ G/ p
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" |; @* w- D' b. H" c+ h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" p z. i; d9 j, m" gMCASP_RX_MODE_DMA);
( }1 \* @$ u/ y1 J' e; hMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ L1 N; C) R9 h5 Y5 z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 Y# q( P4 d4 x! N7 d; U6 dMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! [, L$ V4 A3 f! ]" ~( V9 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; W4 p" F2 T2 U1 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 B" A& L# g" U" d( V' m" e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 v/ R& J2 S" W0 [4 n" NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 J8 C; u! O F' H) eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# g) z3 B2 \- { m W' d8 AMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# Y/ x0 U) V! a0 b
0x00, 0xFF); /* configure the clock for transmitter */
; T( s. A5 m8 |$ @- k% ~. XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ @' {# a& y& l! p N3 G+ t1 T9 HMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 [& b7 z' c1 U+ g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 v; T+ |/ N: I; W% F
0x00, 0xFF);* l. x/ @5 x R; e
$ s- s$ W. k v# g: b+ v
/* Enable synchronization of RX and TX sections */
+ D4 _& k* ~; X5 G/ q8 v3 EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
) v2 k" F' t9 F( nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ s5 |- {5 v% z, V# U) b: l( UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 }& Q' s3 O: K: V
** Set the serializers, Currently only one serializer is set as
9 a8 z! ^. R& u- |+ o+ k8 L** transmitter and one serializer as receiver.
6 S' W( C; O: ], a$ v*/6 M- i+ e3 e1 {% r8 K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' Q3 n l4 N+ nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* }! \: ^9 W" }
** Configure the McASP pins ) c# Q0 j1 q! _
** Input - Frame Sync, Clock and Serializer Rx$ M+ Q; b+ d8 J% D! [
** Output - Serializer Tx is connected to the input of the codec 3 g0 H, n- q4 r6 A$ @
*/2 }; }% Y6 g5 j- c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 p# h& g! R; R+ Z8 j5 EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); l: s0 y, }: X8 Q- q
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX w8 i. G/ P9 m! `8 ]
| MCASP_PIN_ACLKX* R3 n3 P1 {* T' U
| MCASP_PIN_AHCLKX5 e+ l$ h3 Y! G% o$ n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; b0 Q% t# V x3 MMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, P# d. N" P$ ~! N" m; Q. @| MCASP_TX_CLKFAIL
# k( u O# ` M1 j| MCASP_TX_SYNCERROR7 [3 B: ^4 n& L( t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " G2 y& X- P* _2 l3 U6 Z
| MCASP_RX_CLKFAIL$ f6 q) a' [- N! v6 X
| MCASP_RX_SYNCERROR
. B5 h, o' O$ R1 ~0 ?7 [3 t| MCASP_RX_OVERRUN);; L/ H% ^! R' [
} static void I2SDataTxRxActivate(void)
6 [8 p+ v+ G7 M D( |{6 q/ i/ \2 ^8 J8 x" W
/* Start the clocks */
! i7 v; A0 C6 ~; t# D) B; RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 y5 y) H- W) h9 d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- {7 _6 ^; f, i1 W5 }+ K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ a) |. }% p A8 [% `
EDMA3_TRIG_MODE_EVENT);0 }1 z y- Z6 Z9 e/ g1 J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( |6 k9 N# F1 i! q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! K( B9 G# L2 m# g3 q' IMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 b2 v, \- R" t# k( M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! Y# K* x! e# m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 P( g5 q' {( D4 b5 hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" Z( m- Y; N6 s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# B/ j0 g1 m7 x% e% t& z* `} : L5 t* W9 x8 g; j; u3 V& L1 B) j
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , F p% p( x+ n4 a3 [
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