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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ Q& k) D. x V4 ] ^3 W2 c
input mcasp_ahclkx,
4 f( l; I/ ` ]8 Y" Jinput mcasp_aclkx,8 w+ l) u2 {! O6 m
input axr0,2 o' [* w% F# r- R
) f: ~* |) x3 a5 I+ J W* woutput mcasp_afsr,
4 o: w* u" z0 k! N$ Routput mcasp_ahclkr,0 B. E* z7 M) I
output mcasp_aclkr,
& o- Q) ]9 r M" B$ ?' }& poutput axr1,
# Y6 a8 I9 O+ e4 v! q assign mcasp_afsr = mcasp_afsx;% n3 n$ u" V$ i$ ~- M
assign mcasp_aclkr = mcasp_aclkx;
* Z# w) Z1 m7 Hassign mcasp_ahclkr = mcasp_ahclkx;
' V8 q$ q6 i$ Z6 c. Z3 R+ {assign axr1 = axr0; * X O5 }; l" [0 q* @
% R2 L) \ q( q* A在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% B; {( U: p9 u% C- E/ Y5 B( D! }static void McASPI2SConfigure(void) m4 q% ?7 h' |, b2 E! _1 l0 u
{
# i9 t' M: }* }McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ ?* J7 V; y9 P0 U1 w( t
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( P9 P W$ L8 P" C& E# P0 bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; u! |. P5 C/ F0 D* h# Q" JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& K0 }, d* f; D: M0 w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" X+ R! b) R1 j$ s/ L1 f1 ?" aMCASP_RX_MODE_DMA);( e/ s% W; X8 H7 h8 e3 |7 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," Q- M7 k/ H% P! L \' k( b, ~
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! }9 C8 I1 u; l: P- B* P# pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
5 ~7 C1 p# b4 [2 D4 H, uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 G+ e$ M/ G! V9 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & r( ?7 b; i7 B2 A# ~* F5 Q, L
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 L; l \3 O9 n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 B, T. I' d( H7 x! T k
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" p1 S3 @2 Y5 O, b' @McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ L. J K9 d1 p4 d8 Q
0x00, 0xFF); /* configure the clock for transmitter */$ u s" n9 y- f; c" u5 q5 j# Z" k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* [$ L; N& N8 Q5 p! U+ t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ Q p3 s7 s' E9 s; d2 a9 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 w( V. W9 V( m& v5 D
0x00, 0xFF);( [. ?1 a4 [# Y% u
}8 ?6 h: e3 Q) y* }9 }8 z/* Enable synchronization of RX and TX sections */
! l( k C9 |# ^# d0 A% m- mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 Z, Y/ D. i- F" v
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* m8 m R' s. z5 u$ uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ s- F5 ]' y$ f& ^
** Set the serializers, Currently only one serializer is set as
; w1 L; J; @& t0 s3 c. ]** transmitter and one serializer as receiver.& ]6 X3 I9 {0 T4 @3 Q$ L6 ^
*/6 ^$ [% U- t# R* j' f5 L/ e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 H+ H7 J2 f& J: t5 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
G/ v/ I4 J. J3 _) Z9 U** Configure the McASP pins
* p8 b4 e& s- p" `** Input - Frame Sync, Clock and Serializer Rx" y6 W0 r9 N6 {, ^' @
** Output - Serializer Tx is connected to the input of the codec - N+ K! {4 Q, y4 F4 S1 D
*/
& S! L8 m7 \, m% z4 kMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 A% W# F" s7 A# \! q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 r7 R! ]( J2 D3 t: }2 ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( t0 H0 T6 F& O5 j& ~1 E- t| MCASP_PIN_ACLKX
* `8 ]% d8 x, g* z; P5 C# B| MCASP_PIN_AHCLKX
, N$ G! @3 x+ N* a$ T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// q8 Z/ S4 c. ^: s8 I6 E5 l
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. K4 g$ L B |) @" A- R& ]+ z9 h| MCASP_TX_CLKFAIL
4 G- Z6 l( o# r' @| MCASP_TX_SYNCERROR& s* v( h! |5 y* G2 |- y9 E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! W C/ ~/ Z9 u# y9 o
| MCASP_RX_CLKFAIL0 N: c# g% ^$ D2 W" I
| MCASP_RX_SYNCERROR ; I$ k9 ~9 |1 l! N. s+ C
| MCASP_RX_OVERRUN);/ U0 z& R+ M' G" D$ P- @
} static void I2SDataTxRxActivate(void)
* k) t, y% M' @+ U) j0 _{
{: Z+ I L5 T0 ]1 V5 z* h/* Start the clocks */
6 H4 a0 z6 I7 M6 v1 VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; J4 E! P- s6 B9 F9 G, g( ^$ gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 Y- s) W/ i4 ]6 x/ D5 g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, D$ W* E5 p& H* z* q$ M
EDMA3_TRIG_MODE_EVENT);: p! _0 g) \5 |8 Y& L; F* B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # r ^9 {$ f1 l# ~/ r" l" x
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 I% B% x% W) \- J; Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 [4 g' i1 z+ o% `4 X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% p% [2 g3 D2 `; Hwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 ]: {7 }. s2 c8 aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 Z2 \0 o4 P8 P1 x+ QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ Q/ E& l; K# m. p/ V; j} 8 ~; w) x- e" g1 j+ p6 T8 D
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) H5 }) N2 m0 g: r# _, q
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