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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! q) Y. f y n% p
input mcasp_ahclkx,/ A! @" X1 g7 m0 |1 J4 P" J6 t' Z
input mcasp_aclkx,' p3 V( |2 q# [0 y' B! B# s
input axr0,( [& f& n1 s; k
# D/ @) y5 N5 J* v4 e8 H* _
output mcasp_afsr,
0 i- ~) Z# E4 t2 }6 T3 {$ uoutput mcasp_ahclkr,0 L, O1 p( |6 j
output mcasp_aclkr,' ]" `+ G, S; c; ]
output axr1,+ l, d% @6 p# B. D; f3 ~) z/ `
assign mcasp_afsr = mcasp_afsx;
/ F( E' F/ w* ?assign mcasp_aclkr = mcasp_aclkx;3 a; e0 B! R/ Q% F6 O4 d4 [
assign mcasp_ahclkr = mcasp_ahclkx;6 \$ ^- i, l" g
assign axr1 = axr0; ; ^/ \. K. h! S. i. M
6 b! P! W/ S9 Q3 }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. e8 v. e) W. ?! `6 kstatic void McASPI2SConfigure(void)
[% m4 a9 z$ ~8 |# ?{
! Q! _& u7 Y& `0 Y" MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: Y. I" C7 B2 c5 M& [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
/ [$ G, z- s( k4 y. K" s$ B0 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% w" |9 a/ o- c( W9 u5 @4 uMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 }- U, n3 f `% _/ c& V5 x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) w i4 I1 I4 V0 @
MCASP_RX_MODE_DMA);
: S% U* m1 n5 E( `- T7 C7 _" QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 | a- b+ |4 M. D1 w7 vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 c& ]' C# t3 d' x# H- J$ W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 Y% p/ s+ ?1 Z8 K& w( V! kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* o7 R w- ]# {/ {) M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * {! r8 _5 ~0 T5 a) q9 M; E, C" `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( e6 U+ T$ D; p4 O3 u) t
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);: t9 _, J" g! a9 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
J+ ?3 c8 I+ iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
v: |+ e4 A" A0x00, 0xFF); /* configure the clock for transmitter */
8 G' W% S1 z: o; d, F2 v# g; {McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ N& B! n9 z( z1 j6 G2 N/ p0 [5 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 t; g0 H8 I Y( X- a6 W7 oMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% v0 _3 E8 l# ^5 p- N- K, \0x00, 0xFF);
+ q% Y0 ]1 X( X: J$ {7 p# t: [
# P4 r% g S' A3 E" a, G/* Enable synchronization of RX and TX sections */ - G& v! g0 ?1 ]) }8 u+ Z, x z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' k" }. q. U! ~& mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 e1 J) o8 e. O, m- W* _$ X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 F8 y j6 x8 S- z. |+ o4 K
** Set the serializers, Currently only one serializer is set as
9 B# e2 D0 S8 d3 @: g( O. h2 V6 x** transmitter and one serializer as receiver.
, X% p# H+ R( h7 {*/
+ q% m3 ^, E5 T* TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) c8 p* m- d$ U9 [0 @0 C/ |9 J4 Y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' ]8 c) A5 V$ a1 g0 W1 P2 m" Z** Configure the McASP pins
, d% x' z$ l. M2 Z$ @ I** Input - Frame Sync, Clock and Serializer Rx
7 Y1 l6 Q0 ^7 h. w, g** Output - Serializer Tx is connected to the input of the codec
5 Q# Q- C0 O6 Y/ q*/
1 e- ]7 B5 Z. N; ~5 EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 }4 k5 p* u8 d6 nMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 T9 x$ F9 L% z( |
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ f# n X0 c2 o: v& O| MCASP_PIN_ACLKX
! `% G3 v. F: \- W| MCASP_PIN_AHCLKX
# Z) x) o' r8 e3 ]$ t; [% Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 G% p# X6 o6 FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 Y8 L; [" S% b6 w) e
| MCASP_TX_CLKFAIL ' |1 Y' r4 W# a q G6 A Z' X3 J) {
| MCASP_TX_SYNCERROR
8 Q: `. y1 \) J2 G6 ]( g| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" i! e$ ~0 x) C( ?1 M. H2 o| MCASP_RX_CLKFAIL
$ R; M. o8 b, ]) @3 }8 [| MCASP_RX_SYNCERROR $ T, T$ d. e- ?: ] Z
| MCASP_RX_OVERRUN);" m N/ [. N) G
} static void I2SDataTxRxActivate(void) Y: O; L3 \, M- g! H
{; S9 {5 U$ {% l& Y
/* Start the clocks */9 \+ z: e, Z6 ]8 ]* n2 t' @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 g+ R r! r) `) R; ~: J! w# zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
`9 [% Z* [6 A/ m# KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 V* s: Q6 z3 ZEDMA3_TRIG_MODE_EVENT);
$ Z% ~" ^( O6 N) REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . s/ G$ w' n$ o J, t
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" f6 O( ^# R& @# o4 s% yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' S# T8 V9 d& I" P- [7 j. f% N8 wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# S, w$ g9 a( O' m# J- ?. zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 B4 ^1 l( v: }5 O& JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 n$ t9 O. z, K+ o4 j( QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);; d. a4 S* p' z( v3 o+ T
}
E3 u8 {5 H, q请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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