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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( P8 M2 _3 K3 u% }
input mcasp_ahclkx,, X3 j5 x- I5 y7 r
input mcasp_aclkx,
2 a0 o* o, }4 z! |" O2 c7 m+ |input axr0,
* Y! ~( [! M2 [; Q% C5 v- m5 C0 m
output mcasp_afsr,# ^0 U7 |, D. z) M, \' `% l
output mcasp_ahclkr,
4 c# \7 Y1 q$ u! Eoutput mcasp_aclkr,
) J$ c, D- c+ x5 A( B( s9 F" ?( t9 moutput axr1,& r* w, m7 m: I% K6 I5 @ I& K2 ]
assign mcasp_afsr = mcasp_afsx;! x- n8 j0 v* J/ P, B
assign mcasp_aclkr = mcasp_aclkx;
, G; `* y3 `. L }assign mcasp_ahclkr = mcasp_ahclkx;! {8 G1 k( T# M9 Z# {
assign axr1 = axr0;
9 j4 U& `5 T* y- i/ D$ q4 l
, H8 X3 X+ q5 Z. e/ P! l在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ M& @ b# {. d/ O! s2 V7 x4 X+ {' M; B4 ?static void McASPI2SConfigure(void). s* z a) L* O0 N% n/ J! `& s d
{' `6 {+ P+ K6 N* c
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ i& d8 R/ T$ x$ P, u1 yMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& B G: V; u N1 d0 m; F: ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ T. a ~- g( s2 V2 T# ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ X& |& _3 H* q" WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* ?5 q- I5 W2 n+ `
MCASP_RX_MODE_DMA);% W _' P1 V0 o. k5 P j9 s
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 C+ R$ k3 g( j) t& l* T& C
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) B/ J' R6 Q4 K. k, w. W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& `6 Z! c$ V! b3 s8 \. VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* J* M. ^" Y Y$ Q0 CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, h4 X, m4 V( _/ @' I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ x; s, ^" z; R: L1 n6 hMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( X( C8 ?( R# u0 @5 y E5 ~* i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) E% X: c7 H Y! ^( Y9 T. o3 }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. l7 S$ l% e( d" P; Y- [
0x00, 0xFF); /* configure the clock for transmitter */+ U) T# ~/ m6 N9 h% W* d
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' `* I8 n; \9 {6 d* j$ ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 R" t1 z* D7 I( h2 \4 P; @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& ~% s5 X' H5 I* g; W
0x00, 0xFF);3 e) ]! y) \# i( Y
7 f& Q' t/ `" X: y) a, ~3 o
/* Enable synchronization of RX and TX sections */ " `1 D8 _1 A! s7 H _) @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ z* |. E& s. g. u2 }5 s8 j. V# X
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 s) h1 `0 p& \- Z; @! j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 {% u/ x* t) P** Set the serializers, Currently only one serializer is set as
( m/ \$ ?* n$ l** transmitter and one serializer as receiver.
) O7 { d( C) g2 K0 f5 ~7 k) I6 t*/
9 l2 i7 b6 {5 c$ ^6 A/ R1 |5 LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' ^" f i: x; s) R# Z
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! A" U0 v: Y L" h** Configure the McASP pins / P: z* t. ]: q/ I) N1 c
** Input - Frame Sync, Clock and Serializer Rx' e0 e& G" d# e9 G. x
** Output - Serializer Tx is connected to the input of the codec
, i: v, `: P' j) h1 s1 a: F*/
' B& Z( c- B7 P5 QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 U1 R9 E5 n: R! b4 IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 S" e3 b1 g0 q) h9 h' x# D- k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 O [# B% A; @5 r| MCASP_PIN_ACLKX+ w- @+ K5 W% P* p. T& p) x! x1 C
| MCASP_PIN_AHCLKX
# y9 J3 s- r2 F0 p8 D- f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 u2 m% d; U; v; ~7 A6 \5 p/ N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % B- E. _. y6 J; r( l5 m5 s: [
| MCASP_TX_CLKFAIL
" L& O N: j" [1 c| MCASP_TX_SYNCERROR
% }, [% L, |2 H) S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + @ \/ n' x/ Z+ _
| MCASP_RX_CLKFAIL" M1 u2 X6 r. l$ l; d8 T Q
| MCASP_RX_SYNCERROR
- q5 ?$ m7 z% a. X! J4 z| MCASP_RX_OVERRUN);6 C2 T. k; B# Z1 T& I3 d5 K
} static void I2SDataTxRxActivate(void)
; D3 H2 D1 C2 f! C) [{
8 l5 T! B }, I2 K/* Start the clocks */
& E8 Y) f9 _% L/ _6 o1 q. cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 D K! p# R/ a a' f0 L9 `# I: ~8 H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */5 ^: ~, ~& O' y3 k9 \3 `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ ]5 Y" {+ x$ N2 L
EDMA3_TRIG_MODE_EVENT);. m/ W3 W" T# y! t3 E+ n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 O8 Z) I, y6 @- @) w0 uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# c9 `( T9 F3 u; U* o3 U! Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
L9 \4 R5 N+ K7 A" |& F( @- zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: N+ T1 C+ S& E8 O+ Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ {; ^* h. ~- M1 {- I0 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% b* X' N& I4 z, D: {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* [' V/ ~$ f3 j* Y" K
} 7 Y5 m5 L0 u Y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 d E. a, m. u) K6 O. D. {
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