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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 \, A& e$ D% g8 z4 Hinput mcasp_ahclkx,# ]" ]8 S4 P! h# J2 Y
input mcasp_aclkx,2 N5 d9 _4 h, _% |( f, a: M* Q
input axr0,
" Q9 d9 f, w" S6 ~
1 R4 Q; |4 Z1 d& uoutput mcasp_afsr,! V( ~" g+ ?- T
output mcasp_ahclkr,
2 a5 j7 L- \+ `- z youtput mcasp_aclkr,
1 U1 Z3 r( a% M# soutput axr1,
% R, z+ X' R! y; h* C/ V! Z assign mcasp_afsr = mcasp_afsx;8 U4 |2 n! p+ g% k1 u; k
assign mcasp_aclkr = mcasp_aclkx;4 Q% D- K- y5 t- `
assign mcasp_ahclkr = mcasp_ahclkx;
3 _5 y. V" C) _1 r. f8 ]- n5 Z: j7 nassign axr1 = axr0; 8 b1 N* l7 M |# b* v/ y' }' q
( L4 Q* F$ r$ R. v, {, L" `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ U0 y h. e( x" B5 t
static void McASPI2SConfigure(void)# g- l* U$ X# d& j% N2 m
{1 `$ F! F0 k8 [6 |3 Y% M$ H& m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 ]7 T+ ~' S* y* D5 R+ c4 zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ h$ m- P$ T9 W w: z( W" AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 w7 w) O7 Q# x0 M7 }6 ]+ ?( xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: M- K1 a( v. t3 p: p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; F! q& ?! ^0 K' O
MCASP_RX_MODE_DMA);3 S1 z! `3 C8 B5 T: s) k5 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ K9 p+ W F; T) Y7 N3 B: ~: R. D" Z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 ?( W# e) n! @! ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " }8 a g& u) ^% \: @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 |/ C; M" y. Q+ h6 c W+ AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! J7 z8 L0 ]( I0 N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; T4 b6 L' D% ~7 }& {; s0 f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; t: m! S6 ?; `
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . ?9 _7 l5 @8 d% k& v2 M& w! M$ {; R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( y" r; X3 |+ u4 `0x00, 0xFF); /* configure the clock for transmitter */
% H0 Q6 Z" y4 f2 Z2 |- `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 F( g# d5 t% C) z* r! ?' `/ o9 g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& p, k; M5 N3 x% C4 W* r; q4 HMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( E m( V1 u5 o/ z) Y
0x00, 0xFF);
9 Q* Y* t& i- S# Y4 Q; L
2 [; R0 R0 N6 D+ {) N) p/* Enable synchronization of RX and TX sections */
, E2 V. e7 w# {- aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ I& c* l* m9 i7 N2 E7 [! P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) K4 I$ [# t& ]1 L, L/ JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
' o! p1 g1 [" W$ T1 _** Set the serializers, Currently only one serializer is set as( }4 P8 f( v1 h( \% y
** transmitter and one serializer as receiver.
- m% F8 h" i" J9 C*/9 I7 g, W% L4 w k4 Q. n- e
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* A2 D: a3 z( S. YMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 O5 l l$ H* c; g' P
** Configure the McASP pins 5 t) V) G+ r' x0 m) w: n
** Input - Frame Sync, Clock and Serializer Rx
/ g/ m& G3 M; S% M** Output - Serializer Tx is connected to the input of the codec
% `( }& R) L+ D*/! b) \7 {# H# x. H& C1 Y1 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, G6 \+ b6 c. s' g- B7 D8 F
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- Z: V- ]4 `7 |( r: Q( PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 w" h: s/ g/ J* h
| MCASP_PIN_ACLKX
7 o9 P/ p, d5 g| MCASP_PIN_AHCLKX
6 w, y$ a8 W" t3 `) Z0 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; J: y+ H2 s7 y; V4 F. LMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- Y: Y! w# @0 i8 }+ e! O) S| MCASP_TX_CLKFAIL ( n E' m" M1 A- F- l F/ C: f
| MCASP_TX_SYNCERROR& a) [; l7 n" ~, ?/ a" ^. T
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 6 P) u, p o9 j6 R1 @* Z' Y. @
| MCASP_RX_CLKFAIL
2 K) Q4 B$ m6 T3 i! y5 B| MCASP_RX_SYNCERROR : Y( ~" e4 r9 J$ k
| MCASP_RX_OVERRUN);; q# r5 Z, F; |* O7 C4 I& j
} static void I2SDataTxRxActivate(void)% a3 O/ h: C1 h* X+ j
{
, r N% S0 h* v5 E$ |1 D/* Start the clocks */3 c$ I, E( R4 o' E& J: P1 j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) k' M7 ^4 g, ~+ C: bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// T/ T+ }0 q0 x2 T# B5 x! N' k, [- `: D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ~1 ~, B3 o7 y4 U+ W! g
EDMA3_TRIG_MODE_EVENT);
9 y) e: S" X: c" d+ E, jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 `+ Z3 z2 E, g2 K' ~6 L% {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! H1 K5 Q* S6 A) a/ N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! Q3 O, M) `$ D- m) J& o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- j9 A1 c8 t. s; Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% ^8 I, v& m2 f4 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ f5 C/ l$ \9 h" b }1 C' hMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 j# D; T2 v+ `" k/ Z}
8 |3 i. m( m- J- s S+ r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) V! ]& ?% m7 y0 b
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