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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' M1 F/ _3 T, D1 m1 b8 R/ u
input mcasp_ahclkx,
: U/ S4 }7 Y* [& binput mcasp_aclkx,
0 E. J) S( ?) ?6 ?input axr0,& _9 t7 N2 ?. i
3 b- i2 s1 c) \ Y3 @output mcasp_afsr,% q4 Q7 x$ q+ P' t, z/ O, {/ s; j. i
output mcasp_ahclkr,
$ v+ S; z. _- i& k* S- y! s0 R- Houtput mcasp_aclkr,: {4 u* v7 T Y- D* Y1 ]
output axr1,1 t; o* w) }; ?4 ?
assign mcasp_afsr = mcasp_afsx;* v" C* _ a6 U! _6 @; ?& |
assign mcasp_aclkr = mcasp_aclkx;
5 |* C1 q, O* I1 H8 \assign mcasp_ahclkr = mcasp_ahclkx;$ P: F" ]3 T8 S" X8 o' e
assign axr1 = axr0; - O1 q/ T# N0 I& a* p9 w: ?. S
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / u7 k5 \ ]6 B& H) I6 }. T+ J8 k
static void McASPI2SConfigure(void)
/ Q4 O7 U* L" V4 U; g{* _3 L% R' N) s9 ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ @8 `! ?4 `: [* ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// M, |$ Y J5 z1 X6 m: C
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 `4 |! V' c; t$ W4 [" T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; w9 q% E- N+ o" n6 e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 n( I0 R6 y+ }; V) W$ M
MCASP_RX_MODE_DMA);
' P: `/ Z+ r( w% W$ BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, n6 Y2 e* p D7 Q. U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 M/ t- L4 u) j% R. L5 E/ _" l& ], z: aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, `9 K, r9 f! X; c1 m3 g3 {! PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 F$ G) U5 ^5 I( [1 Y! UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 c) G! K( X( U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 I l2 J. y* {, d. _
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 x* n/ u0 ^( t* }- `( q" ~! p1 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 D! b, b0 ^- e1 UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! @( K) @! X/ Z6 ], ?* a! V9 u* l0x00, 0xFF); /* configure the clock for transmitter */+ c, e+ Y5 r" ~
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 J" {) {0 ?$ N rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % E5 S& G" U/ { L$ @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 q* P ^! F5 Z% A3 ~' D
0x00, 0xFF);
, ~* m; l4 H% G+ c {, O- H0 y4 _( v# d
/* Enable synchronization of RX and TX sections */ 2 U3 y: `* N# `* G' H7 v* P
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ e$ N* w; h/ {+ M" O W7 mMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 S2 u6 o& D6 E, K/ w2 wMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! T9 `0 q. y# e. q' x- }6 }8 A
** Set the serializers, Currently only one serializer is set as
* M& E9 U7 F8 I$ j! V** transmitter and one serializer as receiver.( F& [$ b8 h& I+ l* C. ?1 c
*/
$ L Y# _8 l/ g' @5 P5 m. g2 N0 J% B4 C. ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 h, L# _: c, a- r. v8 T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ |& ~& r' j7 f/ u' F0 C! N** Configure the McASP pins ! i2 v1 h" a" M5 z* ?4 q8 o% G& E
** Input - Frame Sync, Clock and Serializer Rx
! n2 t8 r; G9 L& x& q% }** Output - Serializer Tx is connected to the input of the codec 9 h; e3 @! p P/ q. \
*/2 J% Y2 t" a& w$ p* Z. a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 o) [* q8 O4 d, R3 h& z4 VMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 k5 P7 t! C- _1 _1 b7 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; I1 r+ T6 c4 k) j4 s/ B
| MCASP_PIN_ACLKX* d5 c( E8 o0 w! a3 j
| MCASP_PIN_AHCLKX
{( ~8 [; Y/ n) E8 \- h: }+ }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& Y3 D0 U7 T: ^# y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 7 z. T- @, o0 B7 @
| MCASP_TX_CLKFAIL
3 V8 j' e+ _. H| MCASP_TX_SYNCERROR( n |$ L. ~9 z. R$ n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* J1 u5 T1 o$ R6 b# K| MCASP_RX_CLKFAIL* q; z8 P. f: Q5 U6 D) R: S
| MCASP_RX_SYNCERROR
/ u8 V5 i H" n, C% j" h| MCASP_RX_OVERRUN);7 P# u# q- ^2 g9 m# }
} static void I2SDataTxRxActivate(void)5 c y) L) ^3 ?- B6 h
{
5 I. D* f) u1 R L; `% I2 y# G" ~; g/* Start the clocks */
( n+ V9 }* T9 e: N z7 a, C9 wMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 x% A+ `% F- M5 HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ?# r# c6 z+ Z0 b5 p8 e+ @" N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 V/ t% a; g' g- \( n
EDMA3_TRIG_MODE_EVENT);
5 N" z( K* ~4 q) \1 a4 w! [0 rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 e; Y% K# N& C' n! `( g+ f
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ p0 k, u) C! L$ P0 D4 ~0 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" H0 H0 m- ^7 c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 I1 J1 x3 n; A9 A2 h6 j* R, j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# K. p2 h0 D" @2 ^8 L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);- I, Z( x5 k9 h4 t& K- @3 z4 [1 L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 Z B9 A0 m" `- Q4 ^6 w
} V/ S8 a! B/ c9 x8 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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