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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
% @. P5 `: n. }input mcasp_ahclkx,* n& d3 m0 H% G/ g7 v
input mcasp_aclkx,
, z r: _4 h# i& Y" Q% g3 T3 X0 Z+ dinput axr0,
4 M, V" j$ ?4 _! i3 |; E4 T) E( `5 g
output mcasp_afsr,6 j' _( A# z$ R, q
output mcasp_ahclkr,
* {7 F& C% t6 P8 `' Z' J' T* S4 Noutput mcasp_aclkr,
9 l& D/ @; C) @9 \. n" soutput axr1,
& N z4 q* B5 x# G assign mcasp_afsr = mcasp_afsx;3 ~8 V) I$ ~) X$ U/ o
assign mcasp_aclkr = mcasp_aclkx;% F* A: W+ d0 W' g% r
assign mcasp_ahclkr = mcasp_ahclkx;
1 C% ?* \: K% w- X1 w1 `6 j sassign axr1 = axr0; 8 e/ O/ @* T8 s( ?
f+ y, }+ N) z: G8 d d* k$ e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 O8 c& Q; l [6 C* O4 Lstatic void McASPI2SConfigure(void)
0 d5 Z. `$ p& m8 K{
+ L4 B, l& B3 @7 C! @0 P& }McASPRxReset(SOC_MCASP_0_CTRL_REGS);8 f0 j2 E% d& m' w) c
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 I$ p: `9 p. \' C" @3 QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 S# `( x) l' i$ [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& c' o/ y o$ ~, h$ S6 x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; X* m- Q6 j8 j8 }! h+ j
MCASP_RX_MODE_DMA);4 f6 @! {3 V7 t+ P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& d, p) }( p0 W) Y4 p4 G6 X2 tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 Z0 F" }+ K& U: z( d0 }( I- A0 _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! k6 t4 [: B0 w( `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 b8 K8 h: M' {2 _. n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 n/ L8 Q2 o+ r, r8 E. h4 f$ Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( {7 D% v8 l) I) d H) R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- I2 w& E6 t: {/ T& n0 SMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 J" a3 }7 G" E* rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ h( W0 u6 r, H" o: X0x00, 0xFF); /* configure the clock for transmitter */
5 F0 l, ?1 N( O" q- ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: [8 B# @1 {9 y$ vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 N5 X: q8 w3 R! aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. Y; f# g2 U9 |) }& `& L1 y- @! t
0x00, 0xFF);0 g" o# A8 r! U6 @
, U5 M: t3 ^1 E& s
/* Enable synchronization of RX and TX sections */
. U s7 C8 W( |, r+ ~# RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- g- V0 x- ?# ~7 n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& u# Z( ]+ V" i% m: T, dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 }% W% _9 h0 r8 v: P9 @** Set the serializers, Currently only one serializer is set as
6 j5 u5 P1 L: |0 T6 @& j** transmitter and one serializer as receiver.
. p) r% e9 W) g4 i4 H7 Z" m' I6 z*/
# |1 X( D' r# K# y& a/ RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 k) O7 o: u- {9 d9 T2 S! HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ r" k7 C" H) `) R8 B* w, v
** Configure the McASP pins
8 O' r9 j' H* i+ t1 g& j6 Y e** Input - Frame Sync, Clock and Serializer Rx
n R" y6 p+ W) S9 ?! G' K** Output - Serializer Tx is connected to the input of the codec
! Y7 `! M. F" z1 U% [" d5 ~*/4 b. G: ^# S+ C1 y% H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ e( J, Q ]/ A" E; F4 p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 m. Q. R+ _6 B( V+ U+ KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 P+ ?8 ^5 I# k| MCASP_PIN_ACLKX
, S; P$ j1 j9 }. Z6 `: r5 c| MCASP_PIN_AHCLKX& x8 J$ x. c* p7 a! _2 r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 P% R4 b4 A. p& O3 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR % o5 {/ o, Q2 M9 h+ n0 L3 c9 }$ W
| MCASP_TX_CLKFAIL
$ Z) |+ T/ m5 Z| MCASP_TX_SYNCERROR
# T% n" q2 Y. @, p s2 _. k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR - I! ], w+ }, I2 _# m
| MCASP_RX_CLKFAIL
5 \2 ?$ n! f+ x| MCASP_RX_SYNCERROR : Y3 g" B( U6 Z2 R0 x. g
| MCASP_RX_OVERRUN);0 ^1 y& i9 Q/ P1 r
} static void I2SDataTxRxActivate(void)
4 W% B" k, O. a" b{
. `0 V. h% G8 ]2 U" v/* Start the clocks */7 G8 Z; z( W: T+ D' m" |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);9 ~' b( C6 g: G8 U7 u3 I0 \( k S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
1 U3 ?9 g! h, q" WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 M: y& ~+ }9 n" c0 L
EDMA3_TRIG_MODE_EVENT);
9 \4 f* [! D0 ^& N3 K2 P( {) c/ O5 L" LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 D- ]' W/ Q T- |% KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* X& j1 A) R. u( d$ Q2 |5 ^* Y% {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 r; ]$ K8 q P: V4 h$ bMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */+ @& s# Q; i K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */! f" C- J! f) ^. U2 |% s
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
) z( _ ?* H" \" {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: u0 v. n& X0 M$ D. @, l
} 4 W( G% j! E) f% v5 U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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