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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 A5 s: Z% T$ D3 _: [input mcasp_ahclkx," n) ^3 a5 d* i" ^1 ^2 B I' h
input mcasp_aclkx,2 K- a, l: `9 m' `/ b. @" m4 G
input axr0,
& h b: J: q0 z- }# h8 J, q$ W) a& z( x3 i ?, r: [% @5 ]1 G+ e
output mcasp_afsr,* N) }, N* A$ y0 l
output mcasp_ahclkr,) n" S) O% I1 D$ t
output mcasp_aclkr,+ o0 R' C* {5 f( n' I% X( U( o
output axr1,
; n: K& J7 ? m' I) Z: o assign mcasp_afsr = mcasp_afsx;
" U+ J. ~2 o; c6 E) G' oassign mcasp_aclkr = mcasp_aclkx;
3 c7 A( ?/ m" ^* t0 n' wassign mcasp_ahclkr = mcasp_ahclkx;( i" Q6 j8 [% k9 C/ R
assign axr1 = axr0; ) b1 Q: |* G1 ^, D0 q! L: }" ~9 y
' M8 F* A( n4 V# Z( S% ^1 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 u) n9 z! Y$ ? P# U; ]
static void McASPI2SConfigure(void)
% R4 y1 U0 Y4 W# N% D{% h8 m @5 U7 W( A0 H+ _# C
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 r" Y1 R( k- |! m, q2 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 ]. v. R4 Q9 }- H- \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! q5 n5 D' v6 ^+ a: B \. `3 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 f" l1 l2 A' `
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. [- i, h& Y6 x: L3 ?, j# WMCASP_RX_MODE_DMA);% ?! |$ q* [" }3 }7 H. Y: H7 T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. t5 C( t7 x: l/ ^7 D1 UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ L5 |( X$ d4 [$ T& Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) m) {% H9 [2 f9 s# W0 h, n7 T2 z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 m# }0 a+ S& m9 n7 X* u( P5 @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' ~# L$ k- o2 Q# W+ V# zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 F" ^: s- y# `- l/ c4 ~7 @- x
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 Y2 a4 a4 H1 l; m4 VMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); / a8 ~* {7 r. j' H3 \8 O5 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ V! A, \8 d( y% `' R X0x00, 0xFF); /* configure the clock for transmitter */! t8 X/ Z$ F: O+ `6 T
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% A* ` `- R7 y5 A% y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 P' T2 F2 M8 B+ p) j# RMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- t9 w0 D% u- }7 l: \0x00, 0xFF);$ S7 ?9 W: O8 d1 [! Z" u; Z7 f2 \
$ c% i" x% p6 e8 O' w: f6 p
/* Enable synchronization of RX and TX sections */
/ \, I" q0 Q1 }; S' c0 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ j1 u) e8 A; c- w3 |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; j& D: }8 J- e# ~; K
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 e( b% j* g# {* u" s2 g** Set the serializers, Currently only one serializer is set as
* _3 j* p6 R& `# }" X& L2 H3 C** transmitter and one serializer as receiver.. u9 w r4 |% c
*/
, P1 Z' c( b7 l$ ~5 `McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ P! _5 ^ V* _' M v" j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 u# l j! n8 N1 x9 |** Configure the McASP pins
. }# j0 N9 H; |! q" ?# o; S** Input - Frame Sync, Clock and Serializer Rx
* t3 h1 D( l- Q9 u u y6 T** Output - Serializer Tx is connected to the input of the codec
% h: I( ?/ A S" I*/
; R( Z/ C* z5 t" uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( D W( j N" Z$ R0 n
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); Z9 h2 q3 J @ y+ ~; I# k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" v) Q. Z5 W+ V: K" H( {1 p| MCASP_PIN_ACLKX( r6 {2 z/ T* h% C; i- [+ {# a* ]4 F
| MCASP_PIN_AHCLKX
+ Y0 u. G, a5 O; ]- o' y( Y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) c# h! S. C$ t" U, y8 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# ?8 {" ?( S3 w) F7 t$ i| MCASP_TX_CLKFAIL ) W: Q# C( K) S' \$ c1 Q
| MCASP_TX_SYNCERROR
' ]' t' ]3 x7 r" R, _3 Y' Q3 a9 d| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, E/ y' X4 N5 F9 E$ l| MCASP_RX_CLKFAIL
, s, K8 W5 ?9 m. q& A/ q: x| MCASP_RX_SYNCERROR
. P7 {8 z" J$ {0 j4 w8 @| MCASP_RX_OVERRUN);- V5 Z4 [2 @) V) X. y
} static void I2SDataTxRxActivate(void)
* D' \! A6 i* b; M4 [5 r0 [9 P+ O$ w{
: u6 \+ D8 q. R/* Start the clocks */" _. }5 Q9 @# w! }' U; w# i- p2 e
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( D4 y+ F q8 k3 K! NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, _$ T0 p. W1 M- n" p8 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) O1 P* F' A! [* i
EDMA3_TRIG_MODE_EVENT);. U* ]- w; r9 y- E" i8 o9 `2 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 z, m, k, [' g8 x- y, _8 K1 B: T& {
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 S+ z( q% u c3 R) XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- o9 v/ M, Q0 I0 ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 D; ?7 c/ t$ D; ~2 `3 s& O I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% `$ G6 ~, R# O' q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 j1 C7 X) D1 w: t! MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
' c) A) w+ O" d) M% ~}
6 i4 g9 h2 W: k% `& b' F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; _* i n/ e3 p- l2 o9 P
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