|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! m( A+ B$ G$ o. `input mcasp_ahclkx,
: I7 k, B1 |: `! v* Q" sinput mcasp_aclkx,+ D% c. M" X3 n( [8 E1 ?
input axr0," j" |% ?# M, A" n
+ f- j0 m* v: [% E. N0 ^% moutput mcasp_afsr,% Q$ G" {7 F, g) u9 A; J
output mcasp_ahclkr,
! J/ @3 H! D- I3 X3 ?9 a* N4 k4 Moutput mcasp_aclkr,
' G3 b! Q+ K( y) ?/ ^- soutput axr1,3 P8 n# H3 ^$ z- {7 n# L
assign mcasp_afsr = mcasp_afsx;2 ?/ \3 J& J8 W$ \: c9 I3 }
assign mcasp_aclkr = mcasp_aclkx;# c$ _+ A0 C. `
assign mcasp_ahclkr = mcasp_ahclkx;: J- e, \0 P0 q: z/ n9 F# F7 [
assign axr1 = axr0;
) D8 w3 B4 j ^3 {' u0 K" P% a( h+ e& o* i8 c6 J7 v
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- f7 u/ c: X5 I1 Rstatic void McASPI2SConfigure(void)
* T2 s( Q/ P- f+ A' w* w$ A{7 C. ^7 ~1 m. d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ y/ |) P! s& k \" PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */9 {: @7 y: r$ A& }- ]2 z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* B3 ?6 v8 z5 p9 _- i& d4 s0 tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( G& T# O) Q! p
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ e* W) I6 K9 v |/ I7 k, FMCASP_RX_MODE_DMA);
+ k7 R3 b7 j9 |, lMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 v, G5 z. ^1 iMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# ?9 ^7 y1 Q& o0 n) K! Q' f
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 |" z: ` G% Y e/ |( K" g
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% a1 j- b1 N/ nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* Q& D& i) j2 g$ j/ v" EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* o' v( `$ v0 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 R9 L. N) d7 V2 HMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 |+ m! b w9 e0 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ O0 G+ L, U( ?. h+ s$ f" T& U0x00, 0xFF); /* configure the clock for transmitter */1 B5 q" d! e, l: `% e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. w3 g0 a, j- d) J* t$ q+ {% [% q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 E. h! Y; R* Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 B4 j- _" w- S' _5 \0 a, A
0x00, 0xFF);! Z7 @5 u1 m& {. Q6 P2 Y$ k
0 C1 @' ?# j& D {2 F
/* Enable synchronization of RX and TX sections */ # K/ @* f2 s' t9 L7 Q* ~" I0 w
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// S `+ {" f# ^7 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ U& a2 {; L7 f3 D7 f7 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 S$ M" k \1 R! {; _** Set the serializers, Currently only one serializer is set as
* J' h+ `. e9 H2 {** transmitter and one serializer as receiver.( r5 e1 D U# K+ E- n
*/
- M {7 j' F* ~9 o# LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% z4 |+ e" C+ NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 m8 ], ^) U4 m7 i** Configure the McASP pins
0 s0 j) N) r. Z K5 H: h** Input - Frame Sync, Clock and Serializer Rx+ ~, v, }$ t5 o h+ U6 f3 V
** Output - Serializer Tx is connected to the input of the codec ' P+ s1 `# A4 @3 X: F
*/
5 A7 R' A7 M0 q( UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); @2 ^* z- z( A8 U0 A6 t7 J# Y- X4 j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& P7 _! h0 C: jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX, a0 b1 Y: C0 U( K, g* W
| MCASP_PIN_ACLKX
3 U/ x M/ X4 I' v& L1 {' ?2 i| MCASP_PIN_AHCLKX8 V7 U' @4 P$ j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' D% l" R- \1 h% c+ A. t) A, ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & \' V: b$ E& k4 G; n
| MCASP_TX_CLKFAIL 9 o8 ~$ `5 J6 F7 K. W6 [* d2 M
| MCASP_TX_SYNCERROR- |2 l0 u: U0 |% H8 R& @
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR M. R. Z: k# p8 ]& @! i
| MCASP_RX_CLKFAIL- p9 b1 j7 d( l1 w% K; l& Y+ q6 t2 i# ]
| MCASP_RX_SYNCERROR
+ y% d7 N3 J" `0 W3 k* t7 v3 X| MCASP_RX_OVERRUN);
- ~' a2 ~+ u! ^ N} static void I2SDataTxRxActivate(void)
6 c. t2 P+ O4 z; Z4 d$ \6 d{$ k6 g t$ g3 V
/* Start the clocks */, l! \. o3 u! I9 ?! w9 G$ P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ j- a/ B4 m1 h: F/ MMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) t! A9 h& p9 E7 a( K4 q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. S. Y" G3 B! P9 |EDMA3_TRIG_MODE_EVENT);. L6 j- l' y v, L
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 ]" Y {* U' s1 n7 QEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 O5 J, K4 i4 C @- x# oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. h, Q0 E E8 E" U* Z0 ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" N2 g. J" P% S( |7 |- X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& w! W) x' Y5 i) E" }+ b8 h+ x) G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& x5 \& d3 M2 F2 x' N9 a5 rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ s' w+ `5 s+ {9 m% q+ _
} ) i$ X# k- y+ p$ K) s: e, R7 a
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
' c- \: Z; X" ~9 l" {& ?1 s$ ` |