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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! y9 h! V7 b( i" r4 n7 P
input mcasp_ahclkx,7 r( ^8 @( i. O2 K; D
input mcasp_aclkx,
7 c5 w- L6 B1 Linput axr0,: Z7 W3 W) P% Y+ a" J' P. X+ L
6 z! {% K% |( L& G$ h
output mcasp_afsr,3 n4 b% g# j9 f/ }0 I9 Q8 R
output mcasp_ahclkr,! `% P7 j ]- U7 m+ x r( _
output mcasp_aclkr,# H0 }+ B7 b% q2 w+ p! W- e8 `9 g2 L
output axr1,
4 M6 j; A2 z' X3 d' t assign mcasp_afsr = mcasp_afsx;
, v; w* q6 e. q% Fassign mcasp_aclkr = mcasp_aclkx;
L( ` j7 N3 K) E Rassign mcasp_ahclkr = mcasp_ahclkx;$ `) D% Q& H' f( D3 k! }$ }1 F
assign axr1 = axr0;
( f7 ^" K! d: N, {! I$ M$ y- p" {2 s6 t/ U0 c) C, P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 f' |3 P( o% A) C, f% }* P. m, v! c
static void McASPI2SConfigure(void)% S3 Z( Q9 Q' e
{
: P$ W/ Y# P2 i0 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 r5 k9 d+ s& `& g
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
7 l( J' ?/ c" F3 \9 L* `7 j& T& [ jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 g+ ]4 q& P8 [/ m
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 x; T7 m }- g% t7 d* s4 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: j; _ i M9 o5 i( q+ q4 V% |MCASP_RX_MODE_DMA);7 q' K0 I+ T/ Z Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ w. ~+ P( X9 X8 }+ S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; S+ S( o$ ~% P q7 E( R4 ^
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ a# X, B3 Q% j: }MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! X4 O9 h' L- H3 K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 {+ U4 f1 F& x! j. y: lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ j6 \" P( s7 U+ g. e* LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 H; E9 B3 `3 w5 \9 |9 `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
! \2 A I) S1 e- W8 OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" @% ~; q) P: ?! F2 E0x00, 0xFF); /* configure the clock for transmitter */
! Y; S. b! X: oMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
2 B) [; l' M- @2 b0 ]6 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 V2 F$ o' d! c4 a) Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! c) p( a% K4 S7 V0x00, 0xFF);9 R: U$ t9 r. _- E+ [
2 y8 P- C% S" o# }2 G+ u7 t" N0 s/* Enable synchronization of RX and TX sections */ 0 R9 J8 _. E" r3 e9 D
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
d; E% C2 }- E0 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- O/ x5 U: w: f* G- L, vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% }/ t* h; j0 p+ h( Y; M** Set the serializers, Currently only one serializer is set as
3 g7 h6 s. O' P* F. y** transmitter and one serializer as receiver.
+ I( j8 Y" G1 @9 I7 Y*/
' y+ f% W3 W, `( @5 N6 v, QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) I& H0 ]2 j8 ^) {McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& N# ^4 @7 z6 ?! ~9 S
** Configure the McASP pins
: h. z. E8 ~. z8 ]: m. [# g+ L** Input - Frame Sync, Clock and Serializer Rx& J; M- G) y+ ^5 D
** Output - Serializer Tx is connected to the input of the codec 0 @1 N8 w; E4 B
*/
7 N# v+ V `6 I6 _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! c A9 `. E3 L. E, s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. N$ l" z" F% i; H8 g8 V" e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 q* e7 c9 m% @| MCASP_PIN_ACLKX
7 P% n- M1 o2 y- F. f- P| MCASP_PIN_AHCLKX
. \% T% J5 _& U6 U) a$ n| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 ?, P5 @+ V/ J% A6 e0 `
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
" D1 G3 g* I U# W| MCASP_TX_CLKFAIL
2 s: F. G7 J2 j, Y4 T| MCASP_TX_SYNCERROR/ J& p3 i$ ?9 |1 J3 y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; o. H6 \) D. C, p+ n5 l3 N| MCASP_RX_CLKFAIL
4 {4 _$ P$ @; ^! c8 K| MCASP_RX_SYNCERROR
- n# o9 f6 t7 f8 }& O- `| MCASP_RX_OVERRUN);
+ e6 ]# E6 B7 E* s6 X; l% ^} static void I2SDataTxRxActivate(void)
+ H2 M* }1 k6 t' s{
4 S4 e+ I+ ~ l, a1 R/ K/* Start the clocks */
) O' `" l) m, z* \7 @3 @, NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. Z) e& Z2 W% V- b' P3 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- B( c9 v* V h9 ~6 y2 G9 G4 M$ [" J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 o# w$ P& L) v/ t% z3 _2 s( E: @EDMA3_TRIG_MODE_EVENT);
2 V$ t$ U& R: x d- ]8 d1 q/ T: VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) ^0 X9 i. r9 G) M
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! a2 b% e: h; F$ J% s0 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ |1 [& K' Z5 K) W7 O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. p' @5 |+ ]4 R* Z* ?$ p. Q% c8 p
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 E- R- U3 ?, H; Z. V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 e; O8 ^" k: MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" r# m" L& d3 |% F3 S0 ~) p}
- I# g* @* E* S6 G9 s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ?8 w5 {. E9 `& O N, z3 P8 z% m
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