|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, Q# L* Z0 q5 i) W L4 F- u2 S
input mcasp_ahclkx,) E: ? V) F/ b- r" W6 F
input mcasp_aclkx,0 ? t0 ~9 n( b( N
input axr0,
* X3 _* P( n) g+ Y9 j) g# l
, @$ }1 B. I5 ~- koutput mcasp_afsr,
" k1 b7 f! N9 {, c" B9 z' Boutput mcasp_ahclkr,
% h' V( v+ ^9 `+ z2 l) x+ eoutput mcasp_aclkr,$ k2 y* _8 D+ B# q8 V
output axr1,: r; N2 A' l; R" ^) K. K
assign mcasp_afsr = mcasp_afsx;
3 }0 x. ^* D5 Wassign mcasp_aclkr = mcasp_aclkx;1 n( r8 V( C7 R
assign mcasp_ahclkr = mcasp_ahclkx;
+ ?+ y4 M* R, P. j/ \8 H7 f2 Vassign axr1 = axr0;
" D$ z6 i% Y; q" N: E4 U, C( ]: G, w$ A- S9 e9 ]. B5 Y5 G: ?# X
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 V# }1 T$ W$ T! `* W2 R
static void McASPI2SConfigure(void)
& m. I) P" \" i" H# X{
# k5 g; H2 V, A& H" u* }+ E. UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);( K5 v" d) W- u/ Y/ j; E' V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 {4 _7 r/ q8 y! h# tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( D7 b u( D, d& W5 u) M7 kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ g0 A$ S* @" ~8 @! S U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, M9 v' |/ U2 G! {) o R; W' u: pMCASP_RX_MODE_DMA);
- }' }$ t2 ]; E: W4 |McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( C. y$ [+ s4 d; @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ M! H- g C0 W& q+ ]0 r, a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 f5 H/ M! u) Z0 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 i8 {+ o# \$ i/ m" Y5 g: O8 CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* n, h$ s8 P& u- N$ dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. k8 r$ b, R- U' W' o& `5 JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 Z5 ], Z/ G! b2 `+ P# u7 }
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % M8 O6 ?6 d0 b, F5 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 n" J2 V4 R ]( }! E( K' Y0x00, 0xFF); /* configure the clock for transmitter */# O" |9 o) w, G( S' S* x1 y
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 b7 [) b9 u$ b" _$ P% Y4 v2 ]3 rMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 t+ n3 Q. R( j6 F% N+ u- c/ P" ^9 g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, i& ]6 @2 L2 W
0x00, 0xFF);
+ X- b2 z2 F2 H8 O0 ]) H. P( Y
- P( t- [- e9 N# K" I( }/* Enable synchronization of RX and TX sections */ 4 L& k3 Q6 `" \9 L" w! O+ O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ [9 _2 M) t5 A% Y" V5 ZMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: o4 Z% H+ p0 J" w" }4 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# \" x. T; b- L8 U* i
** Set the serializers, Currently only one serializer is set as
# G$ o$ n0 [% O3 M0 M6 ^9 G+ a** transmitter and one serializer as receiver.0 @. z- l: I4 r8 u8 ~
*/
& C; s ~; Q* v( KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* w! D9 {4 s) S) F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 H. z4 y3 j" | u
** Configure the McASP pins
! Y u" e' f) o6 }$ \" k, U8 k6 x) g4 b** Input - Frame Sync, Clock and Serializer Rx- K' w, @; C9 _& d
** Output - Serializer Tx is connected to the input of the codec
" _" G+ r Q7 n6 u*/
% y: o! _4 ?( L& L6 K4 g, d" H2 WMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; A, b' `2 r: `. S( h" xMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: d$ c- C) @- I7 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% l0 V- W3 C8 D7 i/ D
| MCASP_PIN_ACLKX% x! p; ^# `% N, x7 V- \5 j) y
| MCASP_PIN_AHCLKX6 {/ r' H" X+ |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: j1 ?( Q7 b$ |# w$ H @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " Z" a0 }1 h1 o" D4 C
| MCASP_TX_CLKFAIL
9 e M( s0 A! R: @+ `| MCASP_TX_SYNCERROR
) O/ o0 ~- l7 T| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 4 x' W3 {& B9 k: _+ n& U/ R- [
| MCASP_RX_CLKFAIL$ v* N* M; ^" L
| MCASP_RX_SYNCERROR
4 S' Y0 ]$ R5 L| MCASP_RX_OVERRUN);. Y( o: ` A, u- Y
} static void I2SDataTxRxActivate(void)
7 J) _- M5 e3 H7 _! U5 g{
7 \) x+ |8 |' ]* B/* Start the clocks */; ?& T, `9 F) C/ K' W
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 @& E8 u: B2 `/ Q4 G' JMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; B" k6 d* H& S/ k" _: lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 o, g/ H5 t2 G. k7 }0 y
EDMA3_TRIG_MODE_EVENT);
# \7 r& O3 s+ N+ k- VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 g* K8 X0 n' v9 ~% U4 REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 H. a( F7 H; w# v: m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, Q1 i1 s# Y x6 ~3 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 [7 }7 G0 c7 k" d/ k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; ?8 O, d/ x. m1 x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);& H8 J+ |- k$ I4 u5 R, f2 o8 c1 y0 {
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);. Q5 X! e* D& m8 R3 ^3 z4 R
}
" L3 S! ]! S3 P& ~( {: t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " r( s# D2 m: N$ M+ Z% j. A- k: ^5 ^
|