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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! E: f1 |3 w N, W0 e: i
input mcasp_ahclkx,
9 S, N" M: F! H1 H2 m$ m5 u4 Oinput mcasp_aclkx,! } v. z: T% g
input axr0,2 Q7 w( Y, d- {+ u( x" E8 [
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output mcasp_afsr,7 M- d1 M4 B0 n* \: y7 k: s+ t' k
output mcasp_ahclkr,
* _( _2 c8 c" K$ k! c% t+ j. I9 aoutput mcasp_aclkr,# c; }9 G, J+ J' A3 j8 Y, H& \/ v8 ]
output axr1,( ^3 H- a, W9 J8 Y
assign mcasp_afsr = mcasp_afsx;
) x; i1 E( \3 q3 H+ P: q s0 Iassign mcasp_aclkr = mcasp_aclkx; _+ q$ @& N* c# r) a* k4 i
assign mcasp_ahclkr = mcasp_ahclkx;* C( `" X/ P* l" `7 L) e. Z
assign axr1 = axr0;
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3 n6 |7 e: R, M) G G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
B" v! b$ L% Y' O; Y5 J2 Xstatic void McASPI2SConfigure(void)% }+ S4 u: M) U) E' K( l: z# M
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McASPRxReset(SOC_MCASP_0_CTRL_REGS); y4 N6 y7 B6 q3 Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// w9 b* m8 W# T. O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
8 h" B/ y) z+ @$ \5 W; q1 h1 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ F# H" h4 i# F# Y4 | D0 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ h4 F( A/ t; cMCASP_RX_MODE_DMA);
$ a" W; a) Y. d) j1 g/ c, HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
`6 b) ~6 I3 y6 x. EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% ?: A$ ]0 w3 X) Z( B, H4 q- vMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) ^( _) L* _" u# j! c$ i! N; W, iMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 B8 `7 O; i$ Q/ v* DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 ]) |( w0 S0 ?( m j0 j' I; f8 XMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 z, x: v/ y' J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 j3 @" n, I( m$ S0 r! L0 E _! ~7 u; j/ AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, S. D; E& {" O7 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. V* j e, C7 y o/ T
0x00, 0xFF); /* configure the clock for transmitter */
, j3 Y9 Z8 S$ V* QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 I5 N1 `5 Y7 \2 V' J* q- X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 K6 R7 R1 B8 s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ I4 A+ a6 A2 z6 C" d& n
0x00, 0xFF);3 ^ D, Y' p/ N* s. B; U
2 C. j/ U) c; T
/* Enable synchronization of RX and TX sections */ 1 b4 H' a0 o; M8 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 b: {- \' M% n. ?& ?2 {9 w' uMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); N- W7 O$ k/ y' d* I7 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, g1 q& ~/ W1 T$ l* y7 N2 C
** Set the serializers, Currently only one serializer is set as0 H1 {, l4 h) c7 [. F+ t
** transmitter and one serializer as receiver.
8 t6 t0 c( N$ i* @' D) A3 ]*/
; }( z* b/ Y) pMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 \' i3 o) E% y& J. Y0 K) D2 D1 [McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. d4 Q% h% ~* P** Configure the McASP pins ! S/ k9 d9 T: F! f0 c
** Input - Frame Sync, Clock and Serializer Rx
' o2 `9 E% A# q$ n T** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, D6 _ E. u( x- @- t8 c
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 [" R* A& f: Q8 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 o: K: W3 n. f& S/ Q* @| MCASP_PIN_ACLKX
- z# F( r" V+ R# [$ a k9 a| MCASP_PIN_AHCLKX: z: D! K- G! z; ?, J
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* v8 v9 w; L' Q1 Y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 z* H6 a# R4 G. q+ ]' _
| MCASP_TX_CLKFAIL $ r1 h1 u# W. j& J
| MCASP_TX_SYNCERROR
+ M* t. w5 ^+ V6 ?4 j3 h* Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 m, R7 X6 W* P' t4 d) w| MCASP_RX_CLKFAIL
4 n \; p; Q& G8 J# } `: k- ]| MCASP_RX_SYNCERROR
+ ], d6 ~/ }$ t| MCASP_RX_OVERRUN);
- w: K* L, }$ l" H' \* B} static void I2SDataTxRxActivate(void)
) S; _3 Z- k9 y; C4 E{
" ^3 y! K6 T1 C. J( G& u/* Start the clocks */, {! o% [2 P3 v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! c: P$ @4 S. R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 W0 k' L& e. x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," `% K9 T0 B. {* q5 H* O
EDMA3_TRIG_MODE_EVENT);# H" D) L2 p' t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 J6 z/ o+ I$ \, C3 {5 u+ @1 N9 rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' l( q7 b8 Z& B, t7 w
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: r L( K! D" Z1 K3 `6 \7 @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
( L7 k* J" q) C) Z- {3 s8 [& Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 A9 i6 y0 O% k9 V0 z" Z3 HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 v3 Z5 m1 j6 T( I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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, N- {# a3 }# ~' t/ e请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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