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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 G. z. T- c% vinput mcasp_ahclkx,
- r$ W0 K" a; i) F% f( n" W& R7 `4 Hinput mcasp_aclkx,) T; u3 o" o: d2 Y. Y
input axr0,6 L$ Q( x+ w* w* n, g0 M
u. M' p' \3 uoutput mcasp_afsr,
* q# O5 z1 S1 |- U. o1 U* X. J8 Youtput mcasp_ahclkr,& b. M# i$ f' {- o3 j. C+ |+ h) G" `- s
output mcasp_aclkr,
: V* ]2 }9 j, ]( {0 i: L# z; Toutput axr1,. B$ g2 p2 U; N6 T
assign mcasp_afsr = mcasp_afsx;
% W4 n+ n% C7 D: F. t' Tassign mcasp_aclkr = mcasp_aclkx;
+ K* ] g+ `# D% b& Z% ~; Rassign mcasp_ahclkr = mcasp_ahclkx; s5 g; S4 M6 Q
assign axr1 = axr0; 8 [ \ |: r2 }- x% G
2 ^0 N8 Y$ y: S在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
* s) U8 [6 t1 R( b) istatic void McASPI2SConfigure(void)
2 J. V9 U8 W) G{
* k5 G; o! o0 m7 \5 IMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
" P1 L' V' E) BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# h9 Y9 b! H) I2 x5 K9 ^& \. k n1 `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 R2 y* b" F1 S! y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; r9 i- E$ [: N/ k5 d
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; m! [! {) R6 A. V
MCASP_RX_MODE_DMA);" ?& i* O3 I: ^6 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
?: l; D1 [4 v/ `3 O8 sMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* a' H5 |' L: S" ^* e4 V+ oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; u2 Q1 \* z- U2 s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 _3 k* o }0 c1 C- eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # h! A" W/ k8 P/ ]3 q/ E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' w) I" `! k* A( W/ [. V/ ]7 d6 [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& F4 U. Z" s9 X+ E- }" C9 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 p: o$ v# g3 ]1 D7 e/ F5 M4 ~
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 J6 B' `, I5 ^+ M
0x00, 0xFF); /* configure the clock for transmitter */
$ C3 f) H' D$ p) P8 _' A; _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% F: B4 A+ n5 n @4 O& lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& j5 G2 p& H* {+ _ xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. e$ N! c- V/ q) y6 F0 i
0x00, 0xFF);$ [0 e9 c! W( C1 N+ v7 y! f/ }
: _* C$ B) e9 l$ d' ~
/* Enable synchronization of RX and TX sections */
v' M: ]; b; U P& @( f, I% kMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// |8 p8 B ^6 t, r
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; t1 ~ J2 I: |$ CMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 I: [/ q$ E \! Q3 ]
** Set the serializers, Currently only one serializer is set as
1 u3 o j* P. m* N5 r# ?$ N** transmitter and one serializer as receiver.8 { Y) w% h, u
*/0 ^% E _4 M% h) ]! `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. l, ?1 z8 M* @8 E/ v g: ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 D6 B) D, U5 q8 I+ Q0 g** Configure the McASP pins : [2 u. q$ Y. C% d& e# J. J; @
** Input - Frame Sync, Clock and Serializer Rx) h* N* ^" C' E
** Output - Serializer Tx is connected to the input of the codec
$ I8 A2 a* z3 i& Y& S3 Y6 W*/3 c7 y: H6 a( b+ }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& X% T8 m2 i @7 n6 Y$ e6 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' D( I8 y4 ~$ _! j5 o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. W- _9 j! j+ X- s, R% `| MCASP_PIN_ACLKX+ H# ^4 [9 L6 m7 @, a
| MCASP_PIN_AHCLKX2 `& s- f& o/ {6 ]8 D! W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 o) ] o& a6 M5 K+ eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : d8 R( k+ o% F
| MCASP_TX_CLKFAIL
9 Q$ x4 h2 x3 `: `( f5 |$ L/ x7 }. h% m7 M% || MCASP_TX_SYNCERROR$ ?; i. z' r+ l, e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 H( G6 V Y" k w B| MCASP_RX_CLKFAIL# }2 [- C1 \' W7 V( s$ G
| MCASP_RX_SYNCERROR
# X+ E- z1 x5 U% |0 A| MCASP_RX_OVERRUN);0 p4 `. c- ~8 d6 A
} static void I2SDataTxRxActivate(void)
* F6 L" E/ ~; t$ B{
5 z+ P" M! Y* Y1 P& T- v) I) ]/* Start the clocks */
: {" `( r: L* w" ]2 B) s: Q! IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 r- c7 U! V" r# z& W- Q% z$ {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// r7 \* a1 a! X0 J, E, r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 R, w- w b. E& `EDMA3_TRIG_MODE_EVENT);
g& ~( y b# K2 [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 V: i, h' e! v c
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */6 {" E8 q D5 v) Z3 y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 e+ Q) ]. {& K' \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, J7 T/ A7 ^1 a( S% E
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! p: e; D7 X; h% F1 D2 H# |3 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ B9 Y! ]! o6 C0 h" h8 TMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( _( W& e8 w9 I u} ( k4 k5 } O) N0 R# K$ i X5 w' T
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 ~% {2 |' l- \+ R, E4 d r3 ? |