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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 e L; a' Y# Iinput mcasp_ahclkx,* }6 J2 G, |9 J+ p2 m4 }7 C9 y5 v- p2 V7 c
input mcasp_aclkx, R k$ \+ F0 N8 ?% H
input axr0,
' \4 ], Z+ J7 m( k! k, @1 b, O2 p- ]0 ~' @( F$ q* l% u* r2 X
output mcasp_afsr,2 `! y. u* y7 v- Z ]& z* E% z
output mcasp_ahclkr,8 D; \% I& ?8 x% |' ~5 }
output mcasp_aclkr,1 m* w, J) g5 A9 Q. t
output axr1,
}+ ^4 P' @( N assign mcasp_afsr = mcasp_afsx;, p4 e' c. k( D A% |/ H% k& S9 u
assign mcasp_aclkr = mcasp_aclkx;0 ]; H( d2 n( {* C
assign mcasp_ahclkr = mcasp_ahclkx;! i y$ w& C, p+ G4 u5 e$ D
assign axr1 = axr0;
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# k7 @4 [% W( ^" U+ _ h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 G" f$ a/ ?6 [static void McASPI2SConfigure(void)
9 V! G6 d' G4 k |! N7 n9 H{' l9 I' h- |7 o& Q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);: W. \! I9 G8 v! h2 a ]3 L/ [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 m2 c6 n( q4 V: i# I
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 z: X. m9 q6 T
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! L0 Q% e$ a6 U7 k& y; `1 ~# {4 w/ YMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! F4 p' f; f) A2 X. s( E* n- XMCASP_RX_MODE_DMA);
2 a0 ?$ V0 T0 u! W& {4 H7 K- OMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 H/ X1 o+ @; ]+ B- M& X6 ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 n* } L$ Y9 U# s
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 }) F) r6 M5 h" t$ a& z: ]3 lMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 C3 [2 ^' X6 \" ]! a. `, y" M5 o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 n. Z0 A1 f5 ?. T( IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ K3 Y5 X9 z2 `. ]( Y) w2 k" V; k
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 m# H" _* T: k+ D1 n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ A. n. }" _; X# D: C6 R0 a1 \7 V3 |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! _* ~% v1 L& _# D
0x00, 0xFF); /* configure the clock for transmitter */
7 U9 R# A$ |3 `* ?McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);+ l/ d$ i! l" f% I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; Y d* }! f+ z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% [. B" _% }8 a
0x00, 0xFF);
7 {6 V9 Z e4 Y1 u1 G) p' [+ M/ h$ q7 {; z
/* Enable synchronization of RX and TX sections */
4 i/ A# I8 j3 f& f+ |3 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ f* ]; n$ b6 W# d
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% G* H* a( I: Q4 |0 W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 ^, L" S2 A- o
** Set the serializers, Currently only one serializer is set as
4 h' D$ p6 L6 i; L** transmitter and one serializer as receiver.
. H7 f/ p. T( E3 m# b/ c*/; w' M2 R, b9 x* `9 d! [5 {, y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 [) L$ g _9 U& R4 J5 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ x5 o# R+ A, c, K, j** Configure the McASP pins . L/ P( c* M8 F4 R' l# o
** Input - Frame Sync, Clock and Serializer Rx' k. |/ U$ p1 P; |1 [
** Output - Serializer Tx is connected to the input of the codec ; j$ u0 G4 Y( F
*/
4 w7 q9 ]# ?$ ]" o8 T0 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ P! A, |, Z( z$ R! F5 W! GMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ s V) S( \2 S; a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX n |" v7 Z2 w2 n
| MCASP_PIN_ACLKX5 A- b% d4 |3 x" C
| MCASP_PIN_AHCLKX
4 W# c9 f e" || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" e- d0 G+ m6 m% r. K" n; h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 W/ [) h L. ~
| MCASP_TX_CLKFAIL - z0 q, h: b4 {
| MCASP_TX_SYNCERROR
1 F0 U1 A6 H8 |, O| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 c+ C' P; ^5 D9 h% n4 V k
| MCASP_RX_CLKFAIL, Q7 V& r' y9 b) t' J( d* m
| MCASP_RX_SYNCERROR
) G9 V1 l) Z9 @; V+ N5 F| MCASP_RX_OVERRUN);
P% R6 z9 [0 @6 E% B} static void I2SDataTxRxActivate(void)
- ^! V# m2 ~2 {+ U0 {" R, Q0 c{
$ U; _5 a3 D- x; Z+ N/* Start the clocks */2 O- d$ w0 h9 T) h+ P. P" ^% B8 C( j* V
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ z# w7 y- G; A0 }5 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// M1 }5 Q6 `7 K1 Y; X+ B9 D. T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. G$ P! \: O2 J3 Q9 SEDMA3_TRIG_MODE_EVENT);
0 Y- |7 X4 I: cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 C7 t6 A, A0 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ U/ ?" {* y7 @1 YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 l; y& p& B9 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 R1 s) r9 K7 b. N$ \% r8 e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 d4 m7 Q% @% x$ ~+ GMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 j3 {% V& ^% E) o+ X7 x! } [6 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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