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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 n$ I. ~- F9 S) f m% h9 E
input mcasp_ahclkx,
" `& m8 r+ L4 V" L) g/ [1 qinput mcasp_aclkx, x o4 ]# ~* G+ r$ v
input axr0,
" {5 D; A9 i& v& ]6 u G9 d
0 g$ \& ^/ I! ]/ i7 ]output mcasp_afsr,
! f0 G+ t! J4 m' Qoutput mcasp_ahclkr,
) t$ q# [! y0 z' s* toutput mcasp_aclkr,2 o& m1 Q9 o* P7 r4 a
output axr1,
4 F4 U' s! }9 w assign mcasp_afsr = mcasp_afsx;( ?3 o* V+ E% p
assign mcasp_aclkr = mcasp_aclkx;$ a. H8 `# b1 `" |
assign mcasp_ahclkr = mcasp_ahclkx;
. v; k4 i$ P( F5 s& xassign axr1 = axr0;
+ \- C; }$ m5 M& m; M v8 a+ W( U" `( T: g7 I/ m% \* G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( R0 C. o9 c. |2 X+ z S$ @1 Vstatic void McASPI2SConfigure(void)
" B4 E8 y0 k$ m, S! _{* s) g- g& ? g, k! r" c* M2 d o. T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
* S8 i1 I8 \, z, C0 G1 ?3 fMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
Y! `! i' p4 Q( S) K! r* A: ZMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: `- W9 ]0 O, R9 X; h3 ~/ n
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! g6 F+ L! B6 ?3 L, O( X0 H- {" A0 I: w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 K( A% T r! r! u( E) R! _9 T$ R6 l
MCASP_RX_MODE_DMA);6 \# O7 E, N: ~6 Z2 \
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& N8 V) M/ x9 P( Y: t
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 i; l+ y9 f; _) c0 z, i3 H" B) s) R
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ A4 _2 i; t/ L5 G$ G/ W+ V! l
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 K0 @+ A/ s5 S% {, `! pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * S2 P& {1 X. v! k7 K8 m" x
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
% C b- o3 z8 z! oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 _" U* z* K- W1 P% i7 V# XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" u) o, j. L" d ?5 G/ ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& ?2 H, q! B5 J4 L2 ]0x00, 0xFF); /* configure the clock for transmitter */4 S! ~6 s6 s) O- k+ W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. {( H8 [( W/ H# S1 t- G' VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . r6 `* E; C5 ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 j+ K ]/ C- z1 Y1 x; P- p0x00, 0xFF);$ b% j6 |9 W& @& B' z5 K
/ T- V$ w' Y! F5 J3 i
/* Enable synchronization of RX and TX sections */
m. T; H/ N. ?& B2 @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ B6 P0 D+ [- Q5 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ }$ Q5 K6 J8 A9 j$ D- {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) ]/ x2 H p t" a6 n
** Set the serializers, Currently only one serializer is set as
0 u( e) c3 s) `** transmitter and one serializer as receiver.
* x# ?& {4 a* \: ]5 e- `*/) S# Z( \' p4 k' U( @# V& D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' p9 F( c# ]) X8 n# R6 J7 F* }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( v: a, C: z) j' P** Configure the McASP pins
% ~: S# ]6 y* k, m, R& s. b** Input - Frame Sync, Clock and Serializer Rx
/ L9 J1 y `& I+ D6 H** Output - Serializer Tx is connected to the input of the codec
6 n; O8 r, u$ d1 C7 C$ U9 v: P*/; v5 z' |( } ]3 N# A2 o
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, F m$ |$ i1 L3 x3 u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ j' n; @: E$ S7 l4 {4 a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ E: S9 A2 f' \3 y' ?
| MCASP_PIN_ACLKX
l6 s* |1 l' ?$ Y( b1 @| MCASP_PIN_AHCLKX
9 V7 z7 i' w/ ~0 f2 B6 U9 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 G6 A" x/ `) P# l. H
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 B5 E0 g" y$ q4 q
| MCASP_TX_CLKFAIL
* o9 M0 m! B' u" z| MCASP_TX_SYNCERROR4 Y( Z% [2 i/ u' Q# z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ d! Y1 g; V4 A" s s| MCASP_RX_CLKFAIL
4 {- Q( H7 ^; M; K; c# p! ^| MCASP_RX_SYNCERROR / B. r3 n' c! P
| MCASP_RX_OVERRUN);5 m a2 W! g% A+ V% [- `
} static void I2SDataTxRxActivate(void)
$ N1 u8 Y" i- ?2 y$ V. N5 \: ^{" V( x5 I- G$ A. G" P4 r+ a
/* Start the clocks */
* f3 p5 v# M$ e" L0 K6 ~$ M# NMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* g, l2 E* `% Z% d+ L# W3 c- fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 {- N4 J- d5 b* F% ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," y1 W! I& Q& R5 n& k# K
EDMA3_TRIG_MODE_EVENT);
# P# a* P1 }( `8 r4 }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* j. \. X# U- @* WEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. }" |1 T% m# d9 W# s6 }5 c
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# k" J. t7 V9 s4 ^1 UMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( A n9 Y u+ n1 u2 K' T, K& ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: N$ b* x Y( [: w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. _% ~0 R* G( m- e0 R
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 [; i, e, J C} 9 p1 h4 J C8 e1 l# t: M3 B
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # `4 d5 E4 |9 C* M" p, _; x; I8 h
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