MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
/ v1 A4 B5 Y! o: N# H" J  T; einput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

output mcasp_afsr,
output mcasp_ahclkr,
' n; C3 a) z  \3 o- q$ koutput mcasp_aclkr,
4 n: j; g3 e( B3 k9 c$ G; A0 noutput axr1,
0 U. N% p; q8 p  V( {( H

assign mcasp_afsr = mcasp_afsx;
% S2 ]+ y% |0 `  gassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

- b$ u" w3 E  G

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

+ A4 ~# b3 W! N( K

static void McASPI2SConfigure(void)
{
/ F" w" B9 v  a' Y0 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
0 N, o7 ^) i# z5 _3 f/ ]McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 w; M) c5 Y4 u7 EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' }. F' v+ m* |- h7 x, LMCASP_RX_MODE_DMA);
* Z) g2 k5 `$ GMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
; Y2 M' `& V" N/ p0 AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 A- p  v& s# vMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
- L) n; P- ^0 r/ OMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' d7 C) O6 U+ Q+ GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ H0 }. Y* ?% h9 Z. A1 bMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& h$ P+ w2 o1 N) ]0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 d9 H; \1 M/ `! F+ e; CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
  j4 L& f5 E* p' _/ lMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

7 E% l* ~5 e* ~2 ~/* Enable synchronization of RX and TX sections */
6 S! d- Y+ Q0 H4 x0 Q9 A" p1 d5 z: DMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* }) K& _: e; f# c! X$ mMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
' S2 O! u# _3 ~  Y( C2 i** transmitter and one serializer as receiver.
! p+ Q' l$ U) X$ g*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" f& v$ b% @+ o4 j" l: WMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
+ N* V- I/ c$ i1 i9 ^; T; J** Input - Frame Sync, Clock and Serializer Rx
" z0 c$ C$ O) q* ?" v. z" p** Output - Serializer Tx is connected to the input of the codec
+ @5 s1 E1 }! p& t*/
! I, r* d2 u8 T7 K7 t3 pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; p4 N# Y9 }1 ^6 hMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 y! i* B* s! e2 A- t| MCASP_PIN_ACLKX
8 N: g& g9 ~4 }! c| MCASP_PIN_AHCLKX
5 r3 X6 X2 S( ]) e| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
  J0 M9 _6 L" i. }| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
7 B$ G0 @: V& m% M| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
! N, u( V+ }! v. {. K" k# o# n{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
9 Y/ o" `! y7 {  t5 P% ?EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
3 X9 f( d( k  \5 u) QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
( v  H  Y$ d1 A$ p/ WMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

% k. d- X3 ?+ {& l, G1 d5 O8 u$ l

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.