MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
& [: H9 s% N0 N  D6 {3 Kinput mcasp_aclkx,
input axr0,
* p0 f. ]/ e* I) H) r4 O& a, b$ v
/ Z- [1 n5 g! S) `/ boutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
. p" j5 c5 K1 s" J+ a1 P! U. soutput axr1,

assign mcasp_afsr = mcasp_afsx;
: O! E# u! M0 Passign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
5 K# q+ c' A  Jassign axr1 = axr0;

- C3 ^0 P2 c2 ~' x

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
) y; u, r) m; T4 T6 Y& W{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 ]/ _& o' o. d9 J' _8 M% [McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
1 G/ B0 W$ p" f# @# F8 EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 D0 i* P1 h8 ?: F# Y$ M$ l" vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
5 b0 {0 X4 C1 `" c! r$ }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% C! k, {+ I& A) }: DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, Z1 r5 o0 ?) n- W' ]2 |# b5 JMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( {4 S2 M5 o9 L) t, d9 Y3 `MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
, g2 ]# e. G0 C+ R3 ]3 Z1 r% |McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
9 w7 h  D6 d1 a, E2 X1 sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# {) w2 ^# i; U# OMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& ^5 h. V( n! \' [3 d( Y$ p9 T- dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ Z6 N. r2 w! v4 ~; u0 c  {0x00, 0xFF);
# q% ]% Q9 f' O: f/ @
7 J& j' O. Q5 }9 ?& C% S- J1 {/* Enable synchronization of RX and TX sections */
+ T" H: F* F+ P. y& {/ }McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
% n2 i* f) m3 D/ P  z, XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
& M4 K5 M) F" N) _/ y% n6 o0 T** Set the serializers, Currently only one serializer is set as
) m6 H' Z# G8 V* U) y** transmitter and one serializer as receiver.
) z/ ]3 V: ^0 }  N*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ {% A6 A4 j6 h0 p/ c' ?" pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
3 `# \- `  ]9 ?4 S: t** Input - Frame Sync, Clock and Serializer Rx
! o, t7 F/ Q  J+ ~, n; z** Output - Serializer Tx is connected to the input of the codec
( Y3 ~7 }+ T, K+ y+ G*/
$ C% G( F* z- J. pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 P! z+ T: [0 ]5 U( ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 D2 L! z8 M2 A, SMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; V" w. @' F, s1 I, d- Z6 W| MCASP_PIN_ACLKX
) v/ E# ^. |4 H. Z6 @  C| MCASP_PIN_AHCLKX
  f8 V! d( O- H# V& E| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
7 L+ ^* q% |2 |0 n( C& C| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
, P) B" k# X) b- d| MCASP_RX_SYNCERROR
2 S8 J' K& b, t8 m" }. _| MCASP_RX_OVERRUN);
2 D! I( c* M* Q- a1 N* }! c; s  w}

static void I2SDataTxRxActivate(void)
4 b6 I4 n2 k( V# _2 e* L{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
5 E3 N& }4 M8 l  n# G9 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
' X" I9 ?0 W9 m  G4 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: F2 V6 C# F0 R) J: ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
& ?% g. H+ W6 J: C5 J! Uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 V7 i% f% [$ b" g$ s" ]* B0 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.