|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 v9 [; n: o5 a4 G/ L% f
input mcasp_ahclkx,
9 z# O' I" i1 B6 tinput mcasp_aclkx,
9 g# p! v% ]) b. Dinput axr0,
8 B/ R, Z4 j3 _8 K+ p- p# M5 B' I
6 |( v: [2 ]3 C9 g" Z7 youtput mcasp_afsr,
: Q* T. E, m4 S d7 eoutput mcasp_ahclkr,
( K, Q0 e' y7 D3 l/ Zoutput mcasp_aclkr,
. g0 S9 k T: ^output axr1,
, N' r8 g+ z' ^5 Y% n, ]8 N assign mcasp_afsr = mcasp_afsx;- u; W7 ~ b& f/ ?4 P
assign mcasp_aclkr = mcasp_aclkx; }* \( P" f7 o/ u g' S( d$ y! e
assign mcasp_ahclkr = mcasp_ahclkx;
7 C7 ]/ L+ p; m' B+ b- D( N! ]assign axr1 = axr0; 8 C8 V5 x# d" I1 l5 b& N
! E- W! E2 y* E" Z' Q [# g! I/ M2 _+ r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 n& \6 s4 \$ V* a. @static void McASPI2SConfigure(void)
$ Z& @3 u! t+ V. X{
: V7 u; i; V- n6 Y) W( aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 E+ D$ ?' A& A- {% v* P5 dMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 p; K2 g$ c7 T3 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 Z S+ a- F9 ?% eMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 o$ ~, J1 f) X& G1 E% r5 b6 Q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z$ x) p% W, F$ K$ Q* Y, }MCASP_RX_MODE_DMA);
- l0 M1 A) `) |% h2 Q# N) IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# z! j: ?' P6 v3 X, h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# I ?, n8 r n4 jMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 z' T+ N( r. V# ^" O6 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 {: H S- \, C+ \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' g( P1 o6 S2 T9 r8 ^
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! ^7 G/ H- m/ x7 J" c' S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- T/ K) ~: |" a5 }2 @( F6 n( a
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; P& S" X$ @% W) [- C8 q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ r4 o$ }6 z, r4 U0x00, 0xFF); /* configure the clock for transmitter */
. G3 A+ w* Z) O ~* tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 w" A/ d, k8 g- J
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 \7 r! q& T% i4 U. x9 D1 \1 j ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 @6 u) A9 |( y7 V% R& D
0x00, 0xFF);; k2 c/ w2 ?* |. X2 m4 a- f
: |/ G* O7 ^! E' }8 r5 W/* Enable synchronization of RX and TX sections */
1 B: H) `) R- C8 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! D9 v$ T5 J7 e4 k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ D, ]' ^1 x9 {6 {5 B: l0 ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 U! L- ?$ g0 l' G; f) U
** Set the serializers, Currently only one serializer is set as5 A- s# a% _% b2 ^. X* G
** transmitter and one serializer as receiver.3 V8 U( u, D0 O
*/
: `. S8 Y7 _$ Y) X7 m5 PMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 k! K/ R5 ^+ A+ u$ f8 E( ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& S/ K& P4 q9 E, i3 \9 p0 ^1 u( \
** Configure the McASP pins - y2 h- }- o0 k* h9 o; H* z
** Input - Frame Sync, Clock and Serializer Rx
2 I7 d* U* E# p# Q** Output - Serializer Tx is connected to the input of the codec
5 l$ q7 Z, t* {7 C# M$ z*/0 |2 {8 U- g3 D( J4 y7 q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& W0 ^2 A& ?5 c2 {' D9 zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, W& i" p: r( C
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. I; a+ Y7 e) n
| MCASP_PIN_ACLKX. v7 J3 k* M( x# d5 Q3 a
| MCASP_PIN_AHCLKX/ y. C# x( i! n* G, z/ S6 h- \# f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% \( `8 F- v. n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 N# G3 M* b" ?% i2 [6 H {7 q
| MCASP_TX_CLKFAIL 6 D+ F+ m9 d8 g5 @. ^0 x
| MCASP_TX_SYNCERROR# ]0 a0 z4 g2 w# S- ~0 i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 y0 W* `4 J4 \, e1 C# N| MCASP_RX_CLKFAIL
( e. h9 h! Q0 |( i y7 H6 b9 r| MCASP_RX_SYNCERROR 3 ~, C6 d0 D( P2 ]+ ]. C0 S
| MCASP_RX_OVERRUN);
( a6 i. I4 w% D& |} static void I2SDataTxRxActivate(void)
. K- f P4 d# q Z( R) R) P{$ F3 Z d2 m! v' C# i
/* Start the clocks */
0 D$ r( ~/ l/ \. x% g s- dMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. ~' ]* ^2 G9 E4 I$ PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" S" P0 U5 u; r" O) |2 Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# c9 T$ L' m2 p0 u" g6 T
EDMA3_TRIG_MODE_EVENT);' ]" S- p* Z3 h; T5 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ' P/ R. b L3 m1 O6 Y) @) P/ v
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 O9 L2 {8 o- ~/ m7 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 z S. T( M3 n; d; b# x% j4 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- v( B" ~ e; q9 N: F8 ~, [$ W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
m- I" E) X, @& N4 ^6 R0 uMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);$ c! \% K! V) G1 L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, a, w- R' W! m% r0 j
} 5 q! p/ y; I& r; o8 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) y9 i5 N. J3 P' O6 D4 |
|