|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ ^* d* @4 h# E, t
input mcasp_ahclkx,* N+ O" l% ^. y/ Q% M/ `5 b
input mcasp_aclkx,2 j) X: d: r) F9 t& W- Y
input axr0,' y Z0 E# e8 c. N$ g" u# C0 u' G; s
' _/ h' Q4 R6 O& b% |. P
output mcasp_afsr,' r2 k d% Q/ J0 r/ ]. J- [. M- s" `* a
output mcasp_ahclkr,
! b! r! c1 d" {3 B9 w' v- p/ y9 B- houtput mcasp_aclkr,; Y p& e7 Z, M3 o4 W( |8 G( A: q
output axr1,
$ v' F* L* O5 L6 q7 K0 [ assign mcasp_afsr = mcasp_afsx;
. G8 Y- Q7 W. P, fassign mcasp_aclkr = mcasp_aclkx;6 }1 y! ]2 k/ [) W# [
assign mcasp_ahclkr = mcasp_ahclkx;
9 n+ [; f* T4 E4 h+ Massign axr1 = axr0;
! R* Q, z, X& | H. x3 X& k9 g P
0 I p3 r+ W* I, M. d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 {+ Q: z. N4 H" T. q
static void McASPI2SConfigure(void)
3 n, v# d% ~1 |4 |{
: C" H1 P& l/ Z5 {3 @# F& DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
) w' t( y$ a; A$ |5 E6 w* i& t: \+ {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
" z9 |* q! n& M5 \0 D" QMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 [& ^5 C# @. |' c5 |! v3 |McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 m8 D6 [' a' p7 K& K- I2 M7 DMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; E2 A6 ^) R B" I
MCASP_RX_MODE_DMA);
- ^- K7 ^7 A" W0 L" _0 sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* ~& A3 {) u( Z. wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 |. t6 L& O" H9 c4 HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* U6 v m7 |1 E7 G5 ?MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: M. L) o+ ] r! Q5 O$ D" B& i: D
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 ~. E/ m% l3 N! I3 n. _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 V% W1 b+ g! ?" Q. s2 i4 }McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% o: g% s, x' F; \3 w4 b
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 E6 s4 j5 Y" W& L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ K ?, z5 X! i( ]% P' `. _/ Y0x00, 0xFF); /* configure the clock for transmitter */
( H8 n" h$ p& m# q! ^+ UMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ X# s/ q5 |3 r, P2 A E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 l% E- K% ` _. {8 YMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ W2 C, N+ ~* s& m
0x00, 0xFF);
0 J6 k$ y9 Y+ S, b/ Z5 ]" W# m* J; |
+ }* o1 d; D5 w6 x( B1 G/* Enable synchronization of RX and TX sections */
' Q) T5 v O8 n2 l2 v* ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) O* u/ ^% H7 T8 A2 |
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 P2 h! m1 Y% ?% q9 s7 m$ e. @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ q& @: o5 A2 l3 h
** Set the serializers, Currently only one serializer is set as( N8 `- z0 \! b2 F. t/ l! N
** transmitter and one serializer as receiver.
3 p: O9 c+ p7 G2 \* {) q*/
2 P4 m4 P" n" f5 o/ RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 C+ R2 T( J9 r3 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 ~' @9 k4 I( W6 `0 D9 z0 k6 o
** Configure the McASP pins
) h" a- E" ]* {- o* ]1 K/ b& F** Input - Frame Sync, Clock and Serializer Rx1 j9 T. W" ^* S' S9 z d
** Output - Serializer Tx is connected to the input of the codec
* q* `5 [+ T. J# T" l* y*/
3 g. O: n+ f/ QMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 x) a# D0 I W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: S8 M* Q' B% J' n! X d: _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; a9 G. ^0 d; n3 ^" `3 q9 m| MCASP_PIN_ACLKX
1 J% m2 \2 x; a7 x& Z$ y' [| MCASP_PIN_AHCLKX
1 `( `2 p' G# k| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ S: q8 P! b8 I2 j! f. i
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 V5 V$ m8 Q1 q; E5 Z| MCASP_TX_CLKFAIL
) X$ D) Y) T( m2 q+ r| MCASP_TX_SYNCERROR
. I/ e1 [- k3 A. r5 G| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + c5 L( u- S* d) ?% q( P* R2 Z
| MCASP_RX_CLKFAIL' K' o$ T2 }% V; P6 D* @4 z; b
| MCASP_RX_SYNCERROR
9 @* T" Q) K, f3 z, A0 \0 C9 l| MCASP_RX_OVERRUN);
/ U6 p( I& Q3 t& f} static void I2SDataTxRxActivate(void): w$ P' c# ]2 O" M- Y5 W
{
c% C0 Q2 Z3 A/* Start the clocks */8 t+ J. d7 p9 L; U. E" k% e1 i% p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& Q4 t3 q! Y) ^5 Y+ XMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' I; {) C1 r5 P/ V9 V% T; m$ t; n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 V9 P+ C! l" x' S( q3 ?EDMA3_TRIG_MODE_EVENT);
4 ?; G2 ^: [6 h/ ~/ n U" v! aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, : i% S4 A* A; h2 W! e( }0 t' V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, z* J% d' M9 z5 q% I9 u( A! Z6 ^5 yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& X" m( Q7 A y6 L( }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% h- f* Q# V* v8 {9 Gwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" r# u1 |: e6 h2 KMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" H+ V5 O! r( G# d H, {: C4 ]
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 }% V* O$ c1 ~' e3 K( ?8 {0 i) {}
" e4 E: Z, q8 u0 Y s请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 |5 f: J1 h1 c0 f9 x( L: q |