|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 j# {- {) w7 S2 \input mcasp_ahclkx,) e# E: O) e0 @! |+ C, o4 l
input mcasp_aclkx,
$ G( _( e$ x# d' T" Y$ X5 minput axr0,
7 ?+ [# C/ R8 L, t9 a! w3 }- x e$ v" }: o+ i' c [4 ~6 r
output mcasp_afsr,
" [" C. e: @0 ^. x% t* woutput mcasp_ahclkr,1 ?& c2 E0 F7 z) b* Q
output mcasp_aclkr,7 X& g9 X. x; Q, r; N
output axr1,
. M- F. G" J2 } assign mcasp_afsr = mcasp_afsx;0 t3 K7 B/ w6 o, D. n0 V* [+ U
assign mcasp_aclkr = mcasp_aclkx;
$ i) O- }5 e% j1 J- u; I; fassign mcasp_ahclkr = mcasp_ahclkx;
1 C* t p- N1 L4 x$ `- }assign axr1 = axr0;
1 x# J. j" \& z% k1 V+ ~, Y8 w3 Z% N, D+ z" k4 z' E
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 f; G3 b+ y' z8 n9 m! c# @static void McASPI2SConfigure(void)
1 X$ l' d) P! U0 \, @* X5 B: o{% I) A! _1 {" [' e& r5 }3 j: D5 X
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 y4 b' A8 U' JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 F( X6 b% ^" l( ?4 w3 _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- B, m5 M7 I0 G* V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& a, }& e. ?: f, N' [0 l
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 i$ H' X9 d* x/ p0 G/ @8 B
MCASP_RX_MODE_DMA);' Y, w/ J" u" i4 I& }! ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 n7 h# o' l1 v( D( zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* y3 ?7 \* q9 fMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, J3 k5 m. F; T n* I# pMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ K* o! k s( J8 ZMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 n6 |: v0 N% K1 J5 ]* oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" ?% S% g+ c& J3 WMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 P( s( K0 Z9 i8 O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. \; @+ K5 c' q: z9 E" }& RMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" b, r0 K0 [& l+ z' d0x00, 0xFF); /* configure the clock for transmitter */( Z% Z/ z: i0 S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! U: w8 l, `: r" ~7 A ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 }* Z% z, `; ~8 S" Y& Q1 `$ ]
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 @- Z1 s9 |; d6 G; v6 `. f0x00, 0xFF);
( t& L0 Q! K1 o+ _6 H& r/ O5 R# M/ n4 U+ m/ e6 s+ M" H; f
/* Enable synchronization of RX and TX sections */
3 i0 Q0 C# ]4 F0 u' _2 W! U* o. d4 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: V+ }! Y, ?/ F) ^
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% Q; k9 f: v# D, W+ K6 l! c2 q& {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; I* g" q, n0 ?- M% h3 |5 J** Set the serializers, Currently only one serializer is set as. w- i1 M" l* y# n5 M
** transmitter and one serializer as receiver." c; A; |( l: x- i+ t. Q
*/
3 r1 \3 N6 f VMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! W3 V P2 {6 J" G* y. x
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* v6 e* e5 W$ n% a+ V** Configure the McASP pins
& H8 \1 B8 J- G: o7 F** Input - Frame Sync, Clock and Serializer Rx
0 W `5 g0 K( S! Q# S$ V3 y9 U0 j** Output - Serializer Tx is connected to the input of the codec / {( x- Q0 A2 |7 j
*/
- f, w% O1 }+ {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 P, J, Q a! D2 i; _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 w, ~8 |' Q5 G$ M7 e, u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. I& d( o- |2 M2 f' c! W| MCASP_PIN_ACLKX
8 p' b4 {9 E7 U5 X/ ?5 F# x| MCASP_PIN_AHCLKX& _4 Y, P! f$ @( y }: n; j& v5 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 c; c8 O+ I6 `; o& \; x7 m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 q I! b' V# a2 W8 I! o| MCASP_TX_CLKFAIL 6 [) S6 A( I1 z1 M7 x
| MCASP_TX_SYNCERROR
; v b: w) p* o$ j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 i% k, l9 F& X$ D! R: V0 q3 T! F0 B) l
| MCASP_RX_CLKFAIL3 C$ c# g, e3 z+ T
| MCASP_RX_SYNCERROR 2 x" N0 i* H" d
| MCASP_RX_OVERRUN);' z9 a$ R0 o+ u4 {/ n
} static void I2SDataTxRxActivate(void)7 k6 t+ e1 I( l# I( r
{
/ Y3 o" Q% A$ A2 Z/* Start the clocks */! }- T E5 I+ K# k H7 @. F$ b
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, T1 J" n; d; R+ ^5 }; }' g0 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, r8 }; J) D) t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) ~, Z/ n3 Z6 {$ `2 h$ m6 N# LEDMA3_TRIG_MODE_EVENT);
, t0 R; j$ P! F( w$ U3 T5 j1 ?8 | XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, & g: G' F8 H$ C M8 [& b, q
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 X( |2 e4 a/ m0 |6 Z" Y) } uMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); D8 E4 a/ w& O9 ]. r" H6 }- [" P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) @3 U0 Z" F& F! ~) @0 awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; N& b+ m2 H- x2 G, d0 |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 h8 ^6 m# O! O. H1 cMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" P% }) B2 d& a: G* Y: y7 @+ Q6 a
}
) Q0 o3 x3 F2 t F请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
. u+ b! V7 g& d5 { |