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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& `! f/ u, ?, Z. e( v
input mcasp_ahclkx,
5 w, n) a m. w9 n2 G Ginput mcasp_aclkx,
. f2 W1 e K0 e k2 D5 {input axr0,
5 e: C( Q! N4 a- d0 B( n
; ?* ]6 d# i" P3 F1 soutput mcasp_afsr,
* F3 B+ S- f/ ?output mcasp_ahclkr,
- T# ?5 a$ E4 p/ P% l) `- b! Eoutput mcasp_aclkr,
/ H" l7 F! D( T% ~3 p4 w2 L1 Doutput axr1,
' D2 |7 f* |- q1 ?6 e assign mcasp_afsr = mcasp_afsx;
' @0 s% T+ ]& U2 Q) P$ n- K! Massign mcasp_aclkr = mcasp_aclkx;
% M. p; [' v0 Y4 Yassign mcasp_ahclkr = mcasp_ahclkx;
* y9 f4 M+ L2 n8 ^+ i9 S- \assign axr1 = axr0; 4 g i) |$ e0 M9 Q4 G7 [# `8 ]
# u. ^+ H5 ?$ d
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) J. M( w% Q6 U) `static void McASPI2SConfigure(void)- b+ A" q9 q/ H9 n2 E. N! b4 M
{
/ `& B5 O; A$ u8 j$ NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' A& h9 L% Y% P% V
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! B. f9 s4 B4 L) h$ P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 H4 J. h! Q9 w* @+ j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 a( n, M+ O: v6 K+ B; A+ o
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 [+ p8 b$ s; j" k0 k8 j: f* s7 u
MCASP_RX_MODE_DMA);
; K& i% L2 J o H1 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: B0 [( h) O2 W d" @ S
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 w" @/ M3 i0 ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# k% D# _. C! S o' sMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ }4 e/ e3 Z {+ {3 F4 [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 n% ?- S1 I" _" ^/ C- rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 ^0 p+ a, F+ m, D$ P! [+ jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! T! E0 M9 X0 A6 n3 v0 xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 x: u- }* d3 n. E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ u z4 t8 S: s# [( M. }- N7 j0x00, 0xFF); /* configure the clock for transmitter */2 N/ p2 f& \- }4 y' B1 Z* N0 q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: |8 W8 C! V% I; v7 l6 V
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 E$ N% O4 b: S' s
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' ~* w I! d5 Y' A u0x00, 0xFF);, t9 D8 K2 p2 T+ @( T
) h0 d% A5 c. W$ i& B/* Enable synchronization of RX and TX sections */
6 q% C z$ Y0 u: E* r6 V0 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// `! C# D2 O( s/ r. g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' H& D+ P M; QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& V0 B2 U% d& g2 s$ e! f( I9 k2 W** Set the serializers, Currently only one serializer is set as" y. l. M: u. t: X* X0 V! A
** transmitter and one serializer as receiver.2 h, c9 p$ f& y5 a9 e8 V# {
*/( g1 Z _' U5 Y, S$ g+ W0 a6 W S. x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) y% |' ~* O P. k
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! X1 n! q4 X# f9 e1 y% o/ U** Configure the McASP pins 4 _+ j: g2 a: _! V. I* `
** Input - Frame Sync, Clock and Serializer Rx
; o. b M* |- {# L* X** Output - Serializer Tx is connected to the input of the codec 0 O& ] R' d$ y( J
*/- V- C; ?. _ r, D) d/ S( Y
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 L4 ]" w! l' C6 v W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: H- R+ r3 r: TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 o3 x& w( ]( A4 v& }3 ~$ ^. T, D| MCASP_PIN_ACLKX
+ C2 E8 z( ~' `; y# l C| MCASP_PIN_AHCLKX6 T7 k0 U3 v! f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 t7 w# \4 F. @. [& ]McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 S- C2 O, a( i; v/ H- q& i
| MCASP_TX_CLKFAIL 4 R3 l6 p( k* ? F1 x
| MCASP_TX_SYNCERROR0 y( L' j2 z5 B, S; r3 E2 @6 Z6 b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" D" g9 X7 z8 ?' j" y| MCASP_RX_CLKFAIL
; z7 q5 b! {; R8 o! A0 q| MCASP_RX_SYNCERROR
/ u9 D2 C, F4 p x. H3 [6 J| MCASP_RX_OVERRUN);
( O& n9 I! c7 O} static void I2SDataTxRxActivate(void)' H5 h8 C- N4 M5 [8 q+ R
{
) s8 f3 R, N. b1 k( i' _/* Start the clocks */
3 O2 V9 o. B: p& x' |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- h8 U7 w+ E0 c! ]3 U* GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) A w: _0 u" C2 dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% y4 t! a( X2 b7 f: C/ K2 N' dEDMA3_TRIG_MODE_EVENT);
4 k7 \% ~1 B+ X6 l) mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 _- q& |0 v, x( j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
$ O- T$ P. U8 |* ~+ F. `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! s4 l3 I* g: x+ I! t& u6 ]6 e; o& v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 Z. b2 K1 @+ L) I. K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' \# \# R/ ?$ j5 `. j# CMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);" {! [& h4 t8 }3 x
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) `" R m8 o( g/ X}
0 ?/ y4 R' [' `7 ]; w' H. R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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