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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) k. K" {/ h9 V9 h
input mcasp_ahclkx,
2 Y5 {$ l( O2 j& Ninput mcasp_aclkx,$ ^/ B3 M8 {/ e B! O; |
input axr0, |. U7 ^& J) {5 e' |# ~# z! c
* s: w2 ?# r0 v8 `0 I. D3 s2 Xoutput mcasp_afsr,
2 s @$ g2 e8 t' J: I$ `2 B' ]output mcasp_ahclkr,
) i) {- I3 z- W# V1 o; j" ?output mcasp_aclkr,! n* g6 w1 H. @2 Z, K" c* i
output axr1,( k' Y# ~8 Z e; Y) U/ F0 o
assign mcasp_afsr = mcasp_afsx;
( m" ]4 w2 [' Uassign mcasp_aclkr = mcasp_aclkx;
0 r( T% S: r7 M& ?0 s. dassign mcasp_ahclkr = mcasp_ahclkx;
" T9 ~+ Z/ `# t$ R' x" s6 g, zassign axr1 = axr0;
9 X' {5 |% t& U& s% K; \% i
) N4 E8 ~( b- G- `# O5 c( G& ]在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! U: Q! ?! C5 |
static void McASPI2SConfigure(void)
! i& j2 P" h& G+ e! [{
( L1 _. D+ ~: i. [ [McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 ]5 A! |' f& lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 x( \# k1 E) U- M" A) Z/ N% ?" d5 B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" I' s# n; D7 j6 Y" c/ j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" h x# v2 X% M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 P8 ^0 y9 E% GMCASP_RX_MODE_DMA);
8 k1 S* O J$ X- W7 v: jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- v: ~( I2 h6 g% B x- y- w
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 M" g( w0 o" f- _McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ i9 ~" u; J6 J; B# ]MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ]& \+ M; _8 X1 V+ W8 Y# yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 v9 O. \7 a2 \0 ^, K, b0 TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 M# o) |. x% V+ |$ w* C+ T
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& l, {" a0 f7 uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % ?8 U& I0 b6 O4 X- L! }
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
/ X4 l2 B. t* m0x00, 0xFF); /* configure the clock for transmitter */7 U5 q3 C0 M3 _/ \2 Z# r5 p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: `& j2 O! l! N# n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- K: {/ e: j. ]9 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 a2 i* l- V6 Y8 f3 a! d
0x00, 0xFF);' Z$ B2 H `+ s9 I* y; I
& ?( F$ r( B y7 [# }/* Enable synchronization of RX and TX sections */
" G; U$ C) {$ \% `7 d/ Y2 o9 K! HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 O0 g$ H: E) h/ H& eMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 N$ g$ v! m3 m2 J6 I5 l2 a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& V. y" K5 m7 k3 ^$ V** Set the serializers, Currently only one serializer is set as
( u }6 `% U% b5 g- X** transmitter and one serializer as receiver.
7 R0 O- U6 Y, B*/2 d# B/ g* }. j" P: H
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, I7 N& c8 v0 L: V# n# G4 ~
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*5 u7 | i, i1 k' v' O( ]. N
** Configure the McASP pins
2 D9 Y4 [( b" r2 _% X. U. j* z** Input - Frame Sync, Clock and Serializer Rx
5 W7 N0 Z% V9 Q7 h+ c8 ~** Output - Serializer Tx is connected to the input of the codec # S9 Y: X, d/ O# p) Q X
*/; [' g$ q! ~+ v! U& Y' P l! s& D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 D* ~+ X/ R- CMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. I2 @ e6 G/ r0 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 |/ k3 {, O0 a, H+ c| MCASP_PIN_ACLKX% W9 H, ?, L8 F! J( g, A
| MCASP_PIN_AHCLKX* d$ Q% F5 M8 O% r" q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" F: q, ^/ P. C* |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 x! ]# o* Z6 [( d( E; c- \| MCASP_TX_CLKFAIL 1 X! @; \% |0 c. F6 w3 ^
| MCASP_TX_SYNCERROR7 ^5 d$ q& ]* k U$ J i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, M! }! S9 f( k% G/ o| MCASP_RX_CLKFAIL
7 j* U" y5 t2 q l| MCASP_RX_SYNCERROR
|; |7 @) C8 Q& U| MCASP_RX_OVERRUN);6 d7 |# R& j% q9 I7 Q6 _
} static void I2SDataTxRxActivate(void)9 T( o. `* @" ]
{
/ R; f7 F; f/ w* D2 N0 p/* Start the clocks */* A8 C7 u- w( i, L# T: K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" u; b5 u! D- L+ c1 d+ ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 i8 v6 t; K. l' o; S( v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. v* e+ n Z2 ~/ \( b3 q, GEDMA3_TRIG_MODE_EVENT);
% m3 t. `! n& S: A( V8 `# A+ W( uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
C+ m$ w. k, ~( \' o5 X P+ s2 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ T- h: A; q2 g% s" l- C
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! o: v& w2 \+ R" [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
7 B: v# W# \$ |6 c* D+ A: Bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! d4 X* e5 x# p; O Q8 a9 N! @0 aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; z2 x3 Y0 L( X) C: q: S' `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 V& l. y0 x+ b( o# M
} 3 s, |( N m# S* x6 y- C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
; b5 F+ Q* [" z( `4 ~' h |