|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# A- t( J1 ]6 O8 @5 n- i4 tinput mcasp_ahclkx,
, K7 w, t/ j8 U4 n _3 @% `input mcasp_aclkx,
4 ~7 R! h6 ~+ L: jinput axr0,
& ?) y" w& b, N* Z' Z) T0 _% w8 ?/ k' ]) T4 V; R; l
output mcasp_afsr,9 L2 w- Z. `* S( X& w
output mcasp_ahclkr,
6 ?1 }- Z/ g Q# D% t8 X* Soutput mcasp_aclkr,* e' v9 ~* r A8 S* d$ t5 a
output axr1,
0 k/ A" ]' u3 }1 [& [* @0 W s: A assign mcasp_afsr = mcasp_afsx;: |" Z! R; q4 H" |7 E! Z+ B
assign mcasp_aclkr = mcasp_aclkx;$ [3 y$ E3 V2 @$ @8 P3 _8 \
assign mcasp_ahclkr = mcasp_ahclkx;
# y1 w8 D1 e( v$ I* p( m/ Tassign axr1 = axr0;
/ o9 q' C8 @0 [) m1 O* w; n6 w0 K6 F: a, G. l6 y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 5 u7 |) H$ _- ~# ^ e P
static void McASPI2SConfigure(void), Z* r8 j7 f+ \, _# w. t
{; t3 G- ^& Q% R9 v
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ W; N( l `; U% B; KMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# y, r" ~. u( F1 W* wMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ S9 _! j2 g7 n2 E6 KMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 N0 w: A1 c! i+ J" [
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 d. {3 B) x- f, M' |- g. u/ DMCASP_RX_MODE_DMA);
$ m% s/ J% |3 \+ p0 d8 uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 y" {5 M. C x: L+ K' H6 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// I c8 `# C) n2 _" Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% P" E9 H0 b1 K) M2 aMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& l! T' z9 h' {0 h- }& Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 6 e4 p0 }; L5 x2 c) t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- i9 l) u! A/ K+ `. b) d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- X8 m. S, N2 c& m7 V% aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; F$ I* d, {3 h& J; \% F. ~6 O9 XMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& Y6 L8 ? f# M$ b9 W0x00, 0xFF); /* configure the clock for transmitter */
" B3 N9 c& t+ {$ dMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 B) }( M# ~! Y, [' B0 ?McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # g. G' F) q1 C( _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' `$ m4 l+ b) }5 p& N5 Y
0x00, 0xFF);
$ u, f" B) x% K9 c
" U9 F& O, d. a( }# @; N! u/* Enable synchronization of RX and TX sections */ - m( y# j8 k5 j- C; J5 l3 \
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 v7 m! B' r% BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) D9 ^/ v p6 W7 @7 I) O& d9 d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% X& x- k7 k* s s/ c5 ?% D** Set the serializers, Currently only one serializer is set as
1 B* I/ O; U& v: ]** transmitter and one serializer as receiver./ q% u& a( [) J2 a8 t' s
*/
/ D r: T4 |( W: q) t' C/ AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
@1 D( Z- w5 d0 w) pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: f: {" V9 A E1 E) u7 l/ }
** Configure the McASP pins 9 ^- L2 u2 |$ M
** Input - Frame Sync, Clock and Serializer Rx
- f" t/ E( S' q, R* u% l** Output - Serializer Tx is connected to the input of the codec 1 s3 j* q0 @0 `& I( k* u0 {8 M& I
*/9 k/ L. s, j7 q' P/ V
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 u% d9 N# R" z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ z( ]9 x) U# ]) y" `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
- |& c. S( H- P& `7 j9 Q, X2 a| MCASP_PIN_ACLKX
- u w. b$ r% H, P| MCASP_PIN_AHCLKX
+ G" @6 d- u) e% O' P| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 a$ I4 y4 B+ {6 {. S- n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ I- q8 q$ b, k. Q4 w| MCASP_TX_CLKFAIL
; Y# b" |- }, D$ v% L" l0 D1 w| MCASP_TX_SYNCERROR
5 t; t* k! u+ _+ |6 W| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " `& [. \$ [# R4 S7 E
| MCASP_RX_CLKFAIL4 b! N& T* V; ^# g) { w
| MCASP_RX_SYNCERROR
/ S" N3 ]- h1 _& B P) i. b5 b| MCASP_RX_OVERRUN);
; L9 w' K* w2 Y6 b; M} static void I2SDataTxRxActivate(void). w& R9 z4 [: S3 Z0 {# e
{9 P( |$ M- U* p- v' j+ t
/* Start the clocks */! W% |7 F7 `- h) g+ H2 ?6 d& S) p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, x |( R( g' z% s: Z- GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
: X& E) e3 k, @, NEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 `% [ ~5 `( yEDMA3_TRIG_MODE_EVENT);
1 P! z8 Y" g6 D6 j. KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 n3 ~2 k8 b7 I& O5 p3 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, h) S) I- z6 \3 b% W: x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 w% \* X$ H# j' C2 \8 g: OMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) _+ v9 @6 e/ i0 ]/ \0 xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. [( l6 g) ^+ {2 m! T1 @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ O$ R/ u" D& |% KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* C0 q, p2 P# z$ K x3 Z9 d}
! t( q5 v8 J3 e+ H5 X# H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
( Y1 H" ^( Z" L: o! q |