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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 Q& ?4 p3 A0 K& `/ ~
input mcasp_ahclkx,
. D: I& i5 \4 G# _* A/ Cinput mcasp_aclkx,
# m+ }" {& ]' G; k$ pinput axr0,
& L6 Z9 d& U1 m+ }, Y5 e& n1 K" _ ^! {5 b; k& S; Q7 O" H
output mcasp_afsr,+ H# k* r3 c. l: Z5 u0 i* F5 y) M
output mcasp_ahclkr,1 l$ D/ N8 o( j/ A7 `0 A
output mcasp_aclkr,
3 ^2 s) l+ ?/ ~, ~; Soutput axr1,
9 d! K6 d5 s. N0 E& _7 A C: ]; u: E assign mcasp_afsr = mcasp_afsx;
W. f* J5 Q3 y0 `# t% _8 sassign mcasp_aclkr = mcasp_aclkx;. i' o+ ]" r7 F' e* _
assign mcasp_ahclkr = mcasp_ahclkx;
/ S8 c) r, c9 Kassign axr1 = axr0; 1 u. T' M) _0 Y* v4 c F* g: J
% a' u( h) }: P! g: k$ Z1 c0 ~ j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 J" ?% `/ B' Z; j0 D/ e# {
static void McASPI2SConfigure(void)( j% N/ u6 J4 ~0 {# W
{/ P$ q+ O; e, o! p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 [7 q4 k2 h4 Y5 T# a+ u7 zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! Z7 f) k9 A' ^ Y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! L4 {1 O1 |/ ~7 A; \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( d* m2 S- p' ]8 K' h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! S/ M# [, `" X; [9 F: U
MCASP_RX_MODE_DMA);
3 v4 T# d0 @* y& N+ \ XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* p5 S4 y& X$ a& PMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" `1 O g: j8 n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 D+ c7 {, [3 B4 G8 |# p
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& l0 \( ~6 Q( X
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! _8 y" V; d- D+ f' I6 J% K: O' @MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( N% t; x' j7 R" @+ O+ E0 [/ ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# |; i9 A, {6 j' Q3 ]0 S/ vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 g3 h; t% E( Y# p+ vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) l2 f7 x, C8 u4 c% u5 b4 u8 N
0x00, 0xFF); /* configure the clock for transmitter */5 z. P/ h; C; h6 e( a3 E
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 C; M7 O# k* q+ K9 s0 iMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + B+ G H9 x: P7 u& k8 ~. ~, R
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 C! @+ j( Z# }. i) R9 ?7 ?0x00, 0xFF);0 ?, _ T2 e& ]* Y T: X, E
4 W, k) D: f# ^6 b. ^; q+ m7 {
/* Enable synchronization of RX and TX sections */ $ \% j6 C; @3 [, L# o2 K! f6 i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 A K. ^4 d& I+ K1 K$ O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( d+ H1 s/ M3 Q* m! F b
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 n% D) x" c9 H( N. P. b/ N" j7 f! j
** Set the serializers, Currently only one serializer is set as- ]/ y9 Z# C+ `& M" k( a$ b% ?
** transmitter and one serializer as receiver.
/ b6 R9 H0 o* Z) C+ v% Z4 ]+ B*/
) S* J$ a& Y$ sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( W6 c7 u& |5 Y- S" \2 g8 h- y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# E+ n/ Z/ l' i/ j% `- u5 o6 a
** Configure the McASP pins
+ |8 R8 t+ \8 g6 r# H; ?; K, f** Input - Frame Sync, Clock and Serializer Rx
2 `* q; Z, A3 b6 k; [. a1 H& ?** Output - Serializer Tx is connected to the input of the codec
% C$ G6 n6 R7 C2 M# j. j*/
6 n4 ]0 q/ M' h1 X. lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! l, Y/ c( f& I9 @" I5 H2 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 a* {3 f8 k. i
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" T* s P7 K* V7 q| MCASP_PIN_ACLKX
$ _& t* a! y4 U! K3 q| MCASP_PIN_AHCLKX
5 [7 ?' n, a' v8 S4 t/ j; f| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" E3 L7 \# D% F( [
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ l$ J7 S! `) J3 k- T, L
| MCASP_TX_CLKFAIL " b0 B- V, F2 a% k4 G* k
| MCASP_TX_SYNCERROR
# y: E0 h0 P6 w9 M( ^1 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' S' J% e. c( v5 |5 j
| MCASP_RX_CLKFAIL
5 i- D& b- q3 J! j/ D8 e' \| MCASP_RX_SYNCERROR % }: H& _# C* Q3 @
| MCASP_RX_OVERRUN);$ J, |0 k4 r; p/ u4 `# ^ t
} static void I2SDataTxRxActivate(void)% M4 ?" {. Z$ n% r5 I$ [
{
7 ~: b6 d- T5 t F! X r; _/ R/* Start the clocks */
, a9 A' p3 t: B! WMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 a5 M8 ~! p! `3 C/ IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ s3 c. ^6 i" O$ x* SEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 a9 A9 J+ j, m6 eEDMA3_TRIG_MODE_EVENT);
# a9 f3 z T O) S. }- zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& O& M; u2 P: {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" [5 @2 \* j8 P- s
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 Y: e/ e1 n. e& v dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: a- c: N( u. B" E8 H! d8 S& Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 ?6 O! r% l/ x( j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& F1 K6 c+ T, E5 L/ h' {- a0 q' gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) P: q3 w+ ^7 g, U/ y}
) u- G6 E( y4 i+ o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 4 B ^) c, ]1 F8 ~
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