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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,5 R- ^8 c$ g; o$ W+ R8 _7 W/ ^
input mcasp_ahclkx,5 i- T4 Q( I7 m0 H
input mcasp_aclkx,
; h. n3 ~6 w7 Rinput axr0,
' x! J. `$ T% d4 U0 a( T+ Y$ S& g' t. u2 R8 c& c
output mcasp_afsr,
7 X! m' Y/ t! y/ m5 O2 U7 O eoutput mcasp_ahclkr,: H' f, [9 \9 i# |' y% w% d4 j6 r
output mcasp_aclkr,6 \+ {+ g& V8 r C
output axr1,3 X6 d0 z, w1 v; i6 m6 u
assign mcasp_afsr = mcasp_afsx;5 m. H, K9 X% W* A5 F/ c8 p
assign mcasp_aclkr = mcasp_aclkx;
+ K6 }. Q/ h8 l9 \' W! i: iassign mcasp_ahclkr = mcasp_ahclkx;
. @+ C% d& n6 X& k) F2 nassign axr1 = axr0;
5 H6 K; a8 b$ `, |( u9 f/ w! e8 o0 z5 }( r
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 c5 W; V, r. J$ `, @& ~2 N) Z5 [# Q
static void McASPI2SConfigure(void)
: L# Y2 C* _/ `$ b9 n h/ \3 T{% E- t4 n6 y' r9 H- V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. d* V/ I( [0 h9 U. y' r% ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. ]& C1 x4 E/ N& GMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 p9 w8 w- L7 n4 M/ x# |5 z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; E* _; z# F6 c! h q: S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 l0 Y# B; D; L6 {
MCASP_RX_MODE_DMA);# ?7 o( l0 T+ ^9 V% I+ m$ b' H! ]
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,4 M' i2 @+ z0 N
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! N: {+ \' H( G, U0 K. W
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * X7 @. `# A7 \6 B
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& y {& x9 {. o' R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, c: ]$ @* |7 i# U+ ^; wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */% ]" t% O+ W* V+ `* \5 M+ K5 c
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& V0 l) f( h' ]: ^/ [( oMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 S0 u4 N: ?6 [8 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. i q. B9 |) V+ n- n$ H0x00, 0xFF); /* configure the clock for transmitter *// F5 a7 t7 J7 f. v+ Z+ n! g6 P
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- m! R9 O- X& gMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, I0 y$ y- D% [2 E: XMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 h7 d* N2 F1 \/ Q+ b: z' X [4 D( W
0x00, 0xFF);6 k- o1 q9 |. H+ o+ v8 o% `
$ {- Z' t3 L+ @2 }
/* Enable synchronization of RX and TX sections */
, [' k( n$ Z0 Q$ oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 m0 Z' T! e9 G% F4 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) d1 {9 p5 C# T/ fMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
& F; a4 t3 x) e* O8 h5 B** Set the serializers, Currently only one serializer is set as% G6 K: j {. m2 _* {
** transmitter and one serializer as receiver.
4 U$ [ c0 X/ ]*/
3 U: q2 k p- dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 X( p; t7 S' W C8 d! P( y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* p$ O( c3 P; }# ^9 H& G
** Configure the McASP pins
8 [, r6 {4 a S: P2 C** Input - Frame Sync, Clock and Serializer Rx
, t n6 R; t% E0 j. H" [** Output - Serializer Tx is connected to the input of the codec $ f9 v3 b$ p3 v. J' }( d. T" G3 ~+ m
*/
' P) A6 A2 S, e& uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
" S, `- i, T4 x: c* x1 h' fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 }( ]9 H( K* @* l. _
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 Z9 @- z, E, h: p
| MCASP_PIN_ACLKX P- G; K1 ~$ M( a* s( E3 ^7 c
| MCASP_PIN_AHCLKX
$ f5 B+ i7 x1 E7 E i7 J| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) \. F5 T" c" |+ t8 ?; g# G
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
G, z+ `! `' @( z7 ^4 u0 V. D| MCASP_TX_CLKFAIL
: t1 B5 h0 P9 z! N$ b" J' \| MCASP_TX_SYNCERROR
6 ~. G+ w: P* D" @( {| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! H3 F# \, U5 C0 n1 }: v v) t( G3 u$ \| MCASP_RX_CLKFAIL
" _8 ]+ w# t6 Y| MCASP_RX_SYNCERROR ) g1 i% L2 k4 H9 S5 ?0 v1 m
| MCASP_RX_OVERRUN);6 v0 ?+ U3 w1 a# k+ J
} static void I2SDataTxRxActivate(void)" P) f0 j- w, x" f* N6 d: a
{5 {0 W- n& x7 L* Z7 Z
/* Start the clocks */
/ o3 y, I3 F' E8 e6 jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 d% _2 I8 R: m- R4 ?* |3 ~1 |+ L
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ G7 e: n: q4 c8 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, B7 l5 j" t O, pEDMA3_TRIG_MODE_EVENT);
. V; k0 k7 z/ M) C: ^% y4 r [5 OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ O) _- d, R* t3 U9 aEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 z( r& o) i5 N' ^, S6 F( XMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 M1 s4 u2 B D$ ^" }8 SMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# ?6 J; R" |- \' j+ m! H
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& o& W5 c. |' E$ U, ~, h- hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 @0 O$ W' T- o
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. u) ?+ m- d' j" @7 }}
4 Z: @0 @3 C0 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - B' M: V. M) _: h8 Z2 R5 Q+ ]9 I4 @
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