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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# L$ X$ r: w2 l& o& [+ b8 xinput mcasp_ahclkx,
. L3 x, I! k4 A* _1 `; Yinput mcasp_aclkx,
) m1 \2 Q+ u: J( E, M, Rinput axr0,+ j1 Y' n) u; m1 I
+ k6 w& G7 z' T, ]output mcasp_afsr,
. p& ^( O7 Z4 @1 R1 Aoutput mcasp_ahclkr,
" Z/ ]/ R. L4 \' @: }: ?output mcasp_aclkr,( Z7 y( I" r P& Y+ |" P0 g2 ^& H
output axr1,3 @9 ]! f; M$ r0 J" e
assign mcasp_afsr = mcasp_afsx;
* r! U# D A0 ~, J5 Cassign mcasp_aclkr = mcasp_aclkx;8 m2 R9 R5 ?' q4 j6 C4 [
assign mcasp_ahclkr = mcasp_ahclkx;
1 @) ~" E* [- m8 C4 X0 z4 @assign axr1 = axr0; 5 b w) g- Z: U
1 u8 A0 c- s) g9 d0 {( {! w
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 J1 Q$ U# {- \0 h, j8 t
static void McASPI2SConfigure(void)6 E8 B' l; j0 g! g: |& t& X
{
" c8 p+ Y- i. e+ ?* q% nMcASPRxReset(SOC_MCASP_0_CTRL_REGS);" m: u9 H _) s. O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */3 @3 W, ^5 v8 y! a. o x& S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, p. Y* |3 P% ?$ r" z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ T$ E& p9 I& W: k$ x) {( OMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% Z+ q' |' v' X* v- ~3 G
MCASP_RX_MODE_DMA); J' X& v. n: W, S8 Q3 M9 E2 Y2 K
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 o$ ^* k' J. H* L, B9 xMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 |9 }2 q! i& S5 W4 UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ }; g t' v7 S# i" AMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 G: I2 [) G9 X5 c7 J6 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 A& b1 g: |* E& B$ R$ ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# ]8 T* N' c- M4 wMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% \0 ~2 a" N' lMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 M# Y: p1 G8 u# ^5 J6 {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( T* q. @, S0 Q! w9 R; Z3 k: E% n* E0x00, 0xFF); /* configure the clock for transmitter */
) W0 ^+ G& ]0 f% Q: {, aMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 z& Y+ b F0 n# o# D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % H5 D g$ E5 k/ H$ a4 C# p; U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 R G Q5 C9 l4 l. \0x00, 0xFF);6 m8 H. g" E8 ?7 O$ ]% S
7 G {4 Y7 y3 U, L/* Enable synchronization of RX and TX sections */
- T4 t5 h6 [2 f% q. e1 v6 s" N/ HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 U+ \' M8 i, p1 S0 j( Y6 C
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: _# W- j W9 \/ t
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
% z* T1 v4 F2 x' ]9 _4 Q3 n** Set the serializers, Currently only one serializer is set as
5 l% X1 }) W) R** transmitter and one serializer as receiver.
$ i8 `, b$ t( U4 y! H4 q*/
/ t) s; I$ F) E7 W) XMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# G( j9 J/ |4 f( U+ rMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ Q$ {8 t3 y. y! l4 |( Q
** Configure the McASP pins
. k( I' z" ], I! Y8 l4 G" c** Input - Frame Sync, Clock and Serializer Rx9 }" N, u& k8 P9 h T3 Z
** Output - Serializer Tx is connected to the input of the codec 9 @7 o+ j+ l/ p9 ~
*/
# y. {$ Y m0 G/ l- f t# s8 @ PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ K& ]0 Y( c H, K& q( S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 e! Q- N6 z- WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" g1 j0 L' e) _" j# D8 p1 ]| MCASP_PIN_ACLKX" M, G0 I" n$ r4 V
| MCASP_PIN_AHCLKX2 T# L; D# ?: `: m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* x- g0 T: ?# E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 H4 J& O$ r% u7 v# W( h+ S+ D) w| MCASP_TX_CLKFAIL 5 n8 e9 e' H) P' F
| MCASP_TX_SYNCERROR& H. r6 W, u8 x/ p0 I) J
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " | V. h- ~: @& b. w
| MCASP_RX_CLKFAIL
: Q3 \! H" q- c. B) \. @| MCASP_RX_SYNCERROR
" |9 H* l1 m8 ]5 M' j| MCASP_RX_OVERRUN);1 P+ b4 y$ ?( e) W: z
} static void I2SDataTxRxActivate(void): L& D5 h+ H6 [5 i( A
{9 C; F p4 N/ j M2 x
/* Start the clocks */
1 S+ {8 @* `3 k) c2 A BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 R" G" j5 Y3 R+ c" ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% {8 v+ _3 ~0 R0 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, `6 S2 Y0 _8 w! T8 K
EDMA3_TRIG_MODE_EVENT);9 y: @% a( [, z9 M/ C0 A: ~1 a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * T* @6 _4 @" ]& o5 i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
|4 Y7 d5 R4 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
! q( Y X: `: v" [McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! A T! y. U% G* V* \5 P8 D5 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 |- Z5 q* I; E2 P( WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 v' |2 g% U; H9 y: X+ MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% [4 J& z/ L. T% Q5 r* B} $ v% I) s% F) s9 W6 f
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ w% N( x' a3 S- S- b
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