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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 ?- t, U4 B! n/ d, y
input mcasp_ahclkx,
6 x& h+ K F. R: J# s9 T" {5 b, C4 linput mcasp_aclkx,
4 e% h. l+ z1 h3 q0 {input axr0,/ ~0 \) t- \ ?; J. |/ c* G
% }* w/ n% o/ G) R1 ~7 L1 V
output mcasp_afsr, R/ |* d( X, r, P& B( D
output mcasp_ahclkr,
+ ^# T' n, @/ z& ?# o. F6 y9 c* Ooutput mcasp_aclkr,% f/ n6 n& t' l! L+ P5 @- T0 a' O
output axr1,+ {# ?1 K7 a6 V2 [7 J# m
assign mcasp_afsr = mcasp_afsx;3 a8 ^! i' H' g, |# G2 G
assign mcasp_aclkr = mcasp_aclkx;! a- I" n9 x( L K
assign mcasp_ahclkr = mcasp_ahclkx;
9 Y+ j9 S2 ^; N; w' massign axr1 = axr0;
: s. l; C% k' L. j5 E: M1 o5 ~; m1 ~/ O
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, B( m& T# S6 c7 i% Ystatic void McASPI2SConfigure(void)$ P5 p' A6 K8 n$ v( u3 ~
{9 j3 I- L6 e! b+ U) `: V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 b' k4 N' G( V) Z
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 H0 J% ~! P( c d! g1 w+ b; W
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" o/ U3 i4 G k! D# z5 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
" ]' {" L' u `, R" a5 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 {" S# m. V6 ^$ o, m. M- G$ z
MCASP_RX_MODE_DMA);' K" z5 H( o" D v
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' T9 R6 }! E4 J( m: V; h3 e8 ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& F- X3 W4 b4 \, R, ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 _/ N6 s8 M0 ] XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" D& a8 {0 Z* h0 F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 Y7 ?* V, g& M WMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */# |3 T1 c$ t9 V9 @7 s) K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' N+ V8 h3 s5 C' e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- l( K- X" w# z! O! {McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ |9 {- h; H( u M( V' |0 ]
0x00, 0xFF); /* configure the clock for transmitter */
* o5 G& c0 j( ~, D. CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ J7 h1 S: e1 z1 [. L* c0 y0 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# a( k/ h& _3 T( V- ?9 v5 sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ e$ @5 \* j/ q& `
0x00, 0xFF);* J9 _5 G) J% k$ n- W9 g
8 l; r% h) G% l1 p+ i" G3 g- m7 k1 A8 C/* Enable synchronization of RX and TX sections */
/ E/ J/ J, S( ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 E7 q& j! O+ @. X8 h/ h8 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);7 q' t* J% ~ d
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 u, W4 R$ P; b3 i/ x$ E9 g0 d
** Set the serializers, Currently only one serializer is set as
5 N& h* ?2 c. {0 |. c6 \** transmitter and one serializer as receiver.
$ h0 j8 D/ ?* G+ b- F*/* k( p1 d9 N( S" a$ e& i' p5 Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 x. w5 v1 |1 f+ M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
3 c- e) Y+ n! f o4 o* k# U4 ]** Configure the McASP pins 1 a6 d2 ^+ y. G" t6 o
** Input - Frame Sync, Clock and Serializer Rx. m1 z/ {6 Y* x* {! r
** Output - Serializer Tx is connected to the input of the codec 4 y# P/ _ X; G5 z; ?$ d" }
*/2 F; \/ J' V$ t- z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 L4 ?: w9 q! }4 u' M4 `7 O, G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- M7 f% O' D1 M) `2 pMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ h N) B, J; g3 D: B
| MCASP_PIN_ACLKX4 d& w2 l/ J/ c8 M- M: Y" x% x, a
| MCASP_PIN_AHCLKX. [& z4 F) Z( _. @8 F7 V
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */4 c% E5 o/ A3 W! A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: N/ _3 X; x3 }1 K# l| MCASP_TX_CLKFAIL . C( b5 g0 V* g G
| MCASP_TX_SYNCERROR
8 D1 l, n' K9 m `9 V) l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / a1 Y1 t# n" C& ]3 o0 B
| MCASP_RX_CLKFAIL
- {* {6 ^( m9 E% q. V| MCASP_RX_SYNCERROR
- s# u; f& @. i| MCASP_RX_OVERRUN);
. x1 t# S- F- ~; A} static void I2SDataTxRxActivate(void)! r7 b8 J/ c/ S" i' C
{
: K2 q2 [' }5 d3 m2 `7 Z1 C/* Start the clocks */
# b/ g: ]+ q/ N* l6 MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, _% d& `: G: [- |# R9 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
B: d) _+ K, R5 BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! b1 ^% v' v/ s7 X9 }
EDMA3_TRIG_MODE_EVENT);
! u) i0 w& f2 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 i6 K# _. ?7 ?, vEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 l8 m/ b8 |" g+ {+ z2 \+ t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);5 u) y5 r' l2 A! [6 r
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 z+ v9 w, \( p7 q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 g* @ T7 e" q! C: v* }* E# U; rMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; M% q7 `& w5 U& [# T# p2 P2 DMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 C. p) o. t% R+ I1 I' C) J}
7 [& H8 D9 `6 ~1 x; l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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