MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
% v+ k1 |  W7 X# N; ^* O$ ninput mcasp_ahclkx,
input mcasp_aclkx,
input axr0,

! w/ g* ^+ t+ Z% soutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
6 D9 @2 W: [+ [4 l7 }. ]$ Houtput axr1,
7 X* L  |+ }- B, m) C

assign mcasp_afsr = mcasp_afsx;
$ V9 K8 B3 W: Y) h% {) P0 g. H  t$ lassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
3 m9 n: T$ w+ U6 K: I( ?% ~3 q+ Tassign axr1 = axr0;

5 o0 S9 z4 x: H; Z& R5 J" l

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

* B' z2 T/ X, ~3 Y7 u9 r

static void McASPI2SConfigure(void)
+ p. w; X6 n  o3 U" F6 r+ S{
7 g) S# k  g* d' mMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 g0 z/ L% C! T: ZMCASP_RX_MODE_DMA);
- O" X6 j; P& A' Y7 ~, `! A6 |" Y5 JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* a7 z0 q9 q) l4 z3 OMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* I* ]$ P- u! f4 a, f+ _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
' z  Q# x: T1 ~' r- N$ ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( ]: e8 U4 K0 J; j8 \+ {: }McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) L0 c) E+ A& M' j" l: v8 u0x00, 0xFF);

/* configure the clock for transmitter */
1 a4 |, `$ j5 t( L7 H' o6 t) k) QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) F& p; o' Q9 M1 b3 q4 \4 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ t$ w- a; F7 b, |5 @) tMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
* G# g. Z% m, M8 `. e5 Z  |) {McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
" I5 L5 U5 s' U5 r! p9 ?** Set the serializers, Currently only one serializer is set as
6 o7 ^4 i/ g- t* O** transmitter and one serializer as receiver.
* C# p6 M) q# M5 F' C* F*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
) O2 O% Q! [) e5 m$ _6 c; p5 d1 |** Output - Serializer Tx is connected to the input of the codec
*/
# V5 z- U. [* pMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) G" {0 c$ T. v9 F# y| MCASP_PIN_ACLKX
7 s" Y8 P% E7 Y9 F* V3 X: q& F| MCASP_PIN_AHCLKX
| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
% m: \! z7 R. F% Q8 X( X0 A. s; hMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ x: |% O/ {; k6 d& n/ ?, `3 u' G| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
$ y* K. Q3 ~/ |4 Z; D* b| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( h# F3 c( x9 m- s! Q| MCASP_RX_CLKFAIL
# V6 P  B2 x% }( }| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
- x' B$ d( @$ X, }$ d}

static void I2SDataTxRxActivate(void)
6 V4 c' |' I, j4 O( v{
/* Start the clocks */
' p! B4 d# \. _* X3 {0 X- a1 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& a1 L& _5 z) v3 |/ K! S2 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
7 a$ \& r5 a1 y- l/ D) ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, M  A# I' j8 N; t3 |EDMA3_TRIG_MODE_EVENT);
1 N2 w$ T- ?6 B0 I9 q6 J6 ~; uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
% r8 X/ G9 g' kMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

: F' {$ ^% C# v0 n8 {