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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 y2 h* Q) y& I% x
input mcasp_ahclkx,
% g) g5 ?/ C" D, }+ h% Binput mcasp_aclkx,' V9 Q( Q1 O$ z
input axr0,
3 j% g7 [# Z4 H& x+ Y" K& U8 Q( ?7 m$ L0 J# {! N
output mcasp_afsr,
3 B% q4 {9 t3 q' v; [ Uoutput mcasp_ahclkr,9 t+ l' F c. ^. K" H
output mcasp_aclkr,7 H, p m0 \% W# b7 B4 A
output axr1,% b) a) n1 P" R
assign mcasp_afsr = mcasp_afsx;2 Y+ A6 ~! r& I$ R$ l
assign mcasp_aclkr = mcasp_aclkx;: `0 i8 R' z, e6 m8 t
assign mcasp_ahclkr = mcasp_ahclkx;
; T6 x5 Y, R+ R/ Uassign axr1 = axr0;
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4 d3 N) g, \. ^ y* E1 I% B$ |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 % o$ {* F, C9 u( i* a& ^
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; ?' x0 a4 P6 Z8 B* i* J& ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 w% }) r: z% d+ b( M+ ~( V/ l% u! VMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 n: W8 ?9 S4 }9 r# G" ?# O/ U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% \" R5 c3 X* B- b/ CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, Z U1 k* w4 w9 sMCASP_RX_MODE_DMA);. Z$ M1 A6 r6 r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- Q8 p! g8 J9 Y/ {MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. R0 M( z1 Y7 U: \3 g0 [: [ ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ _" o6 }3 [1 C& B8 B, r% m
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 S" [8 h8 `! h, Y. i5 ?
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" n* ^5 X3 d1 N1 k" Y6 JMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ Z! V& i3 o) K' Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( [6 t- d9 |+ D/ k$ f* p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. f5 V" v+ j% c D* k, [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. ?' S/ r1 w& r$ j* p. l! Q3 C& F0x00, 0xFF); /* configure the clock for transmitter */* b( {8 i9 Z3 r$ n9 z# |" I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# T x4 w+ t8 @' D; M
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); K% t& y3 S- N; j. r# ?: t; t
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 A0 P4 }3 E7 {" ~! k$ R" b0x00, 0xFF);/ |' w' ~1 }7 S! }" x% i
! B" _# c m7 D
/* Enable synchronization of RX and TX sections */ d# H7 O5 A$ v5 v6 I3 T' @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
\3 U' J8 Y4 ?) H. }" hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& |6 }+ c) a* I! N2 Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 k- w$ z9 x, l4 V& k9 c% G
** Set the serializers, Currently only one serializer is set as
% F( h( K; m) ]$ o; X# d** transmitter and one serializer as receiver.
8 q1 X3 }/ S% o" K# M) C*/
# h& A" Y0 m5 c6 h1 n/ j" RMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, T* f$ ]- e! |; P0 CMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
6 w( T4 @, O5 q# g- ^** Configure the McASP pins , V; s. L: z4 S! p( R# j
** Input - Frame Sync, Clock and Serializer Rx
/ d* d8 m& b( l6 ^+ [8 `** Output - Serializer Tx is connected to the input of the codec
! ?7 @1 x' O# U: g9 w5 ~/ t*/3 m3 Z9 f' n7 _: F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, s7 y2 E+ l: x' C8 C3 b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 f% Y* C5 F) P# hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX m4 E$ K( b. e& ~- q9 a8 R
| MCASP_PIN_ACLKX
6 K z# q- g% ?# {| MCASP_PIN_AHCLKX! |: ]( S3 T' n$ T
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 e7 G5 b" c9 Z* g# k/ HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 `8 p5 F, i4 ?* P! ]
| MCASP_TX_CLKFAIL " y/ q& M, \+ X2 S
| MCASP_TX_SYNCERROR* ~7 g' L- q' Z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* ?& I! P" P5 f% y" R/ E| MCASP_RX_CLKFAIL
/ a0 M. r# r$ t3 [/ L% m% s| MCASP_RX_SYNCERROR
7 H1 M/ C6 M& n, F6 n. || MCASP_RX_OVERRUN);
2 o9 K, [, ^' n# ?0 u} static void I2SDataTxRxActivate(void)
c, P/ r+ V/ I5 {, n" w* D f4 C{+ f; ^4 ?, B/ |6 j$ G- M. t' t
/* Start the clocks */
7 |( ]! D I3 d- v4 B! l1 UMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- L# U/ T; c* M) w& C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 G4 j/ S. h$ Q8 }' QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' F0 ]0 y6 ^5 u, TEDMA3_TRIG_MODE_EVENT);+ c& u" P: v) K# l" l0 T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 Z( n) o! |8 d, p4 y% B
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& V' B) v" I4 RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ F0 R% I9 R, t- C" \/ D9 U
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// p+ A& m7 |) _9 f: d' {$ n
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 B, V. i- f" w: m. |1 WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 U. y; [/ K# L5 V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! w- X6 y' x* D) k
} & k8 k3 |/ i9 l; {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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