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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
?+ E' I4 `) ^input mcasp_ahclkx,% O' n- f' D/ K- S7 x
input mcasp_aclkx,& m. W I# U, _
input axr0,
# }" O2 ?5 }9 D
8 Q) i5 z2 K; _ y koutput mcasp_afsr,
7 X: B1 h$ L# Woutput mcasp_ahclkr,
+ o1 }. P2 ^3 o0 T2 q. ^4 K9 Uoutput mcasp_aclkr,
/ b- y* w( j: k& L' R! Youtput axr1,0 w! ~% D: ^" A+ o6 \+ K
assign mcasp_afsr = mcasp_afsx;
% @( k; S6 B! W/ O. `4 s' z+ fassign mcasp_aclkr = mcasp_aclkx;
$ j, k% |& t* g) }! K. Hassign mcasp_ahclkr = mcasp_ahclkx;
( T2 z2 U+ Z5 B5 ^/ u% u4 G) ]assign axr1 = axr0;
8 {" B1 \6 t: ?6 C+ S5 P# Z9 r8 a8 v5 T \ P
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ l8 A7 s6 c2 @static void McASPI2SConfigure(void)1 w y) O4 ?4 j/ E
{9 h+ b( x. m; G/ B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
1 I9 v6 |, ~; @- s" PMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 J) \5 J0 `4 O* Z: S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! D% O4 X, t% M% c7 ~, c$ S2 h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
w( Z# K4 K" f) ]' X- n0 \ x pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: q" C! V$ _! r( T6 V$ ^# e
MCASP_RX_MODE_DMA);
6 Q7 m; o1 A; VMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; j- }. j% W* f, }6 A
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ @) N0 X! y4 t7 s% o p+ u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 G; g7 [; e6 Y, L, e/ h; eMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& ]0 p+ H3 k# g! d
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & |6 }4 k# q+ r) ^2 |
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ ?1 K, y7 s% j/ B# MMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 ?2 \5 I, w+ W$ D3 h- a, `McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . m' Y0 ^8 G- t7 C3 c7 X
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% @$ {2 a! @9 q( l4 `
0x00, 0xFF); /* configure the clock for transmitter */) x' r( r8 b( e& G- I1 \' g, @
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: R6 d( M9 X G( C) B J' C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* N" ]9 r; R' S8 JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
g# n @8 U! ]% G6 u* V0x00, 0xFF);9 X6 o- A% Y; C, N* e/ w
9 M0 w4 P- L% I& P' P/* Enable synchronization of RX and TX sections */
0 ]0 I6 X& B1 T$ w% @McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */( O' U/ C- _3 X: k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) E3 O5 x1 V! l. T* M2 U, L p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 q; {4 O7 R& n; W5 U
** Set the serializers, Currently only one serializer is set as; }- ^" q: V c# Q, D, B, b
** transmitter and one serializer as receiver.- S+ A, M4 C( v5 b
*/5 s# {! s1 T1 N1 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 E2 [! X+ b& F- r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 l& ^( [- x) [$ l$ H) ` u% C- F
** Configure the McASP pins ( t0 q: q, J- `5 n- D
** Input - Frame Sync, Clock and Serializer Rx
4 a `9 M: V: P ]* M6 ?( i+ B** Output - Serializer Tx is connected to the input of the codec
b7 R/ z. C4 F+ q*/
; a) K; W4 |: E& A9 c9 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ p" e0 t5 s. G* V+ ^- {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 f8 {" }3 ~2 z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: _- y( F7 x: {4 W) h| MCASP_PIN_ACLKX( R. J! R0 M7 g4 }9 q* b' ^
| MCASP_PIN_AHCLKX
% \7 P$ [: c: n) x! s! ~: D| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# g9 z/ k! W- k4 `/ s* w7 H1 `8 F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ P1 {- N! h0 ?| MCASP_TX_CLKFAIL + w' S* @; V" o
| MCASP_TX_SYNCERROR
8 Y2 j/ |9 q. c" i9 Q4 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
Q3 B0 J7 O& z4 O O| MCASP_RX_CLKFAIL
4 E2 D) i8 y# Y+ ~7 `| MCASP_RX_SYNCERROR
Z+ i( e' ?/ d9 u| MCASP_RX_OVERRUN);6 ?- b3 s0 }" y/ n- E1 \
} static void I2SDataTxRxActivate(void)
$ }- X+ {0 J1 M; ]{
( I4 r }0 E2 y/* Start the clocks */
( ?8 k$ p: Y J. ]" X* |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. P0 R+ o$ O5 x ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
x) n; H, E5 e/ W2 ?" t! jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: I6 k& [% ]+ B {2 Z
EDMA3_TRIG_MODE_EVENT);
& }% _2 [" V' m, G7 |& i( wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& L# C/ Z; o8 w DEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" g3 \, t! P! L1 W# ~$ E! b: m0 ^McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 I4 h, W. ]$ E1 V/ C( i* M
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! v/ N( c( }5 ?, J# A' E1 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: T; l1 U7 z2 y. ~1 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
3 i2 K D% Q9 i4 lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' K& [3 ?4 P9 X5 N# U5 _/ g
}
7 I* j' c' |9 [3 }; u$ u3 _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. $ h3 e- E; J+ I9 {# d0 Q
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