|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ ~/ X- A4 c1 |" d* x: _input mcasp_ahclkx,) d0 M- i5 B4 R7 [. C1 {
input mcasp_aclkx,4 `/ c; s* I8 I
input axr0,
0 B; l- |0 w+ y" v) |! k, l, r9 Q# L7 _
output mcasp_afsr,$ _6 M1 M. `7 O+ u f z
output mcasp_ahclkr,
& p( O$ X+ `/ u) K' toutput mcasp_aclkr,# p, R' n' @& E6 t- Q; Z
output axr1,
1 _" H7 c4 l' \+ h, j/ S/ d7 U assign mcasp_afsr = mcasp_afsx;
" R: Q. j( I# g' D, M, {assign mcasp_aclkr = mcasp_aclkx;" \/ s. p6 U6 `; n- T/ d* n1 v% i
assign mcasp_ahclkr = mcasp_ahclkx;
, H/ H) m7 \+ v1 } Sassign axr1 = axr0;
* J; \- S" f7 Y, ]* H+ C/ Y2 ~ g
5 f$ v" d& K. a) ~' I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 c% w4 F3 L, r( |; L5 M3 u, h M
static void McASPI2SConfigure(void)
D7 b0 x/ d6 o9 q9 y" ~. d# M3 E{; n! G3 |# _, f! m; Y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 q$ y# m* g, O r. J2 W, K! |
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! v( c1 Y: Z' V( v0 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ d% f; Q! X* v2 Y; z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */3 D& c; y& F7 \3 O% g& ~6 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 ~2 [/ {* h! m- D6 ]" R: I; L
MCASP_RX_MODE_DMA);
1 F# q# X" n& k! DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ _# K" c8 m, h7 mMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, D0 w, M8 D4 h% k. i3 U3 o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 2 b5 `: E% `$ ]# d: g1 A, f# Y8 V+ J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
e4 m2 y4 U* k& \/ nMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( G2 g! G, R8 u6 N( [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */* k0 I5 A& S% y( Z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 m `, ^4 z- aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) q" s; u' W0 g. [- `1 [- Z
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 g. B8 R& U% p3 b% q! o, {/ E0x00, 0xFF); /* configure the clock for transmitter */8 a+ r1 J7 J) |
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& ^5 @0 U$ L/ ?1 \( sMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
4 E' M, ^. V! Z$ `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 I$ M5 Q! ]; _! x5 C; V6 g9 Z: N
0x00, 0xFF);. n5 U5 z5 E% ^8 B- M
e' x8 B/ e8 Z& Y+ v/* Enable synchronization of RX and TX sections */
; {4 t6 x6 n2 Q: g l4 M- R* UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. `( ? ~: q5 ~8 Z5 _' T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. G+ i/ ?. i# P6 S W+ iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*7 A6 ^2 q, E2 ]4 V
** Set the serializers, Currently only one serializer is set as
4 d- r# \# e5 U! W8 _** transmitter and one serializer as receiver./ z" I9 `/ A0 z
*/5 R; {+ q. C, Q1 ^/ e6 D; z$ z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) P0 k6 q6 _! {1 X, a9 |& Q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*; a5 d7 b, Y6 F; C. x k
** Configure the McASP pins # j! \& G9 K8 H O% |! M d- n
** Input - Frame Sync, Clock and Serializer Rx
2 O1 }! c+ Y( s* y2 M. H** Output - Serializer Tx is connected to the input of the codec
7 S; Z2 m- b$ u# I( v* f7 _*/, }- ]- J0 R1 S4 A/ A( W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# h! H& k+ G$ N- ?. @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ]- P4 S% r% u# ]% e$ s! i8 y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" _* X8 g4 M$ H, u8 q5 t- k. n| MCASP_PIN_ACLKX j) y& p% ]! N, u. g
| MCASP_PIN_AHCLKX8 }6 o8 J X: G [3 p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& M4 Z6 k& Q4 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 w% l: X+ [ [+ f& d: G. ?% j9 C| MCASP_TX_CLKFAIL 3 m& |# E& i4 }, P# x- W
| MCASP_TX_SYNCERROR: j0 Y6 [6 l8 ~
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 7 |% r4 Z: b6 ?
| MCASP_RX_CLKFAIL
& b2 A0 n* x0 C6 y| MCASP_RX_SYNCERROR
' |2 A E+ s1 Z| MCASP_RX_OVERRUN);& w% y& Q' B+ D0 s4 B0 l
} static void I2SDataTxRxActivate(void)6 `+ H+ L0 |* t1 b! L5 _
{; [" B* s6 n& O
/* Start the clocks */* q- y+ Q* w5 e# v" ]
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 ~) J0 U/ C3 v; V% F0 a$ R; NMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, b; N# y: a' x
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
X0 q0 Q, H8 S2 L4 [EDMA3_TRIG_MODE_EVENT);
: h' ~& R/ J" g0 b- C* O+ D; [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( {. B6 ~" U) @/ s6 Y( d# t3 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ D) l6 _+ M& o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 D' O# l3 q# qMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// F/ e4 V. Z: L1 u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, D; x9 o; s8 ]) T/ D1 h( `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. M R$ @9 p; w# H' W, bMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ O* b4 V0 A8 x8 d5 n, A0 z}
* H: m: z- @3 q7 ~- x% ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
8 f7 X" n C2 j3 n' c) }) S |