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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 ]$ {' R& Y2 q/ |input mcasp_ahclkx,
& c/ y: S( J! @input mcasp_aclkx,
/ I# B; Z" D9 D- Binput axr0,
1 d& H5 R8 ?1 g
0 ^8 J5 ~# t0 G8 toutput mcasp_afsr," U0 j1 W9 G$ h' G! t4 y* Z1 o4 ^1 g, C
output mcasp_ahclkr,! A" y# M) b/ ?6 Y7 ~1 S( a
output mcasp_aclkr,
% h% b5 R, P9 ~" e3 d8 g2 Ioutput axr1,/ C; z% Q: G1 o; i4 O5 D( A7 {
assign mcasp_afsr = mcasp_afsx; O# m: T: r. Z6 x0 Z% M" V" H
assign mcasp_aclkr = mcasp_aclkx;
6 @7 H/ x0 L6 q3 N% i( kassign mcasp_ahclkr = mcasp_ahclkx;- K, T/ `) o3 m4 t' W P
assign axr1 = axr0; 2 V7 Y) ]0 q( ^' n6 Q9 o; y9 j; T
0 O; F( d! U5 P2 s9 a4 y6 f p
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , c# e+ ~6 X* x# X% `" ~
static void McASPI2SConfigure(void)! {! |7 |# `0 c; H. I/ k
{0 v: O- m' \/ f1 \% P2 S
McASPRxReset(SOC_MCASP_0_CTRL_REGS);& Q' C# t# h7 \7 E6 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// X T& S3 W: h t: T
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* X" S8 W% {2 \+ m3 k
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# E8 a, _6 ?' [# c/ G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 }% e, Q" p+ X' V. R& O) o# \2 RMCASP_RX_MODE_DMA);
7 M j; m! P3 M- a4 y, `( ?4 T5 RMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* a$ g% M& H$ cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: V% a* @% Q' W9 j- D. V( u2 e
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! X C7 ~* P+ LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' ^8 D1 Y I1 Q! y1 k: Y. I- ]. I2 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # Q4 U, [* ?: `" P$ F* W! l. U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- _# B0 s) m' U% jMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ `1 @$ P* w& k6 B WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 t' l# Z3 Z) N8 P7 _# F' Z. U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,$ T8 K' q% O" s8 ]' o' C: A. J, E
0x00, 0xFF); /* configure the clock for transmitter */
5 c0 k* K5 e3 gMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 F' d- P" I$ ?& y( L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, w9 F$ H. `. ? x& |McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
# ]+ h! R: f( @! r# U0x00, 0xFF);
A. j1 e6 x7 H: D
. U; m, D; ~9 T' Y0 Z( h2 {/* Enable synchronization of RX and TX sections */ ! c! \# ^' e% X! z2 G
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ m/ \7 }9 I* N9 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( h/ x0 c% G5 MMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& L+ O* l6 r$ |7 _# |( d
** Set the serializers, Currently only one serializer is set as
1 F- I! z8 {9 a; A! z** transmitter and one serializer as receiver.
6 [. C+ D0 F5 Y2 N+ c*/% l; r) E( w1 J4 L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);/ l+ j; U# \% _" m/ i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) [3 ^$ r1 o# k
** Configure the McASP pins
/ x3 x. T& @0 f* h! z7 K** Input - Frame Sync, Clock and Serializer Rx2 Z2 V) I+ R- p) x" V
** Output - Serializer Tx is connected to the input of the codec ( c, e+ e( b* {
*/; c7 [' i4 w2 s4 G6 R3 W5 G/ P
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 |: w( U6 D: X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 E+ G* U* s9 e3 ]8 B" C( [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 }1 |" \" q7 S. J. s4 k
| MCASP_PIN_ACLKX" }7 C/ i1 z4 @( Q. r, N
| MCASP_PIN_AHCLKX. C% Z& l6 H/ [8 W; F5 L+ r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// N. q' ]$ M3 }+ R8 a
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ p/ @# I0 A& h+ M4 ]# U) M1 h
| MCASP_TX_CLKFAIL
- `% {8 K# s" @4 H+ P% y| MCASP_TX_SYNCERROR5 g+ ~ K4 M5 m. U
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 ~- K) O; c) K" T X7 a
| MCASP_RX_CLKFAIL
" I% @5 w) @. i5 k. E& J S5 f| MCASP_RX_SYNCERROR
+ i8 n" I/ ? [; Y| MCASP_RX_OVERRUN);
/ L p! O6 o- o4 z: I} static void I2SDataTxRxActivate(void)6 E0 G7 B/ D! N: ?, c+ P! [( e
{ b# z! V; {" a; z, ]: @& {4 K/ V4 u
/* Start the clocks */
: ?. E3 j3 j, @9 n9 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);' a. e1 S- \# A
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" b$ D$ |( E: A, z0 a9 H# dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! N; F" m' Z2 n; ], z4 UEDMA3_TRIG_MODE_EVENT);
8 n8 K( |" h2 F. OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 I2 @' i$ E6 Y& S7 a
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
4 ^7 s* F" W4 X. r8 I6 `8 QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); l) S$ |( U- \- ^. }8 q) i
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: N$ V& z9 e' _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 I" v7 D1 M' @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 d E0 Y( o( d0 Z! G, eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 ]3 T1 p+ o0 s$ {& e
} 2 [! J9 n) A- _& b5 v1 e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % {: F# O/ U* }) W8 B- A0 M
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