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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,2 X8 ~4 a# X% Y: C6 R" P7 ]7 h7 l# ?3 e
input mcasp_ahclkx,$ i+ w7 F3 a, p! S) l7 i
input mcasp_aclkx,
+ }% F3 P/ J6 a; s Xinput axr0,1 _8 t. n2 a/ j; p
; N3 |4 N) o: coutput mcasp_afsr,* y) v- @2 o0 g7 C7 f
output mcasp_ahclkr,1 t& a% D: a# f* s- R
output mcasp_aclkr,. u2 E- A% i6 h. j& M6 c4 f* r
output axr1,
# F) E/ E" |" `+ O' @" _ assign mcasp_afsr = mcasp_afsx;
" q7 D5 ?5 J8 l1 \* g( |assign mcasp_aclkr = mcasp_aclkx;9 C9 q2 e2 r& o0 Q
assign mcasp_ahclkr = mcasp_ahclkx;: C+ ~3 O6 F; ]2 D
assign axr1 = axr0;
1 w, R0 o0 s; i# Y2 _& j4 q- i' B( ~+ |( u# k/ T* ?
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 x+ M# J7 k$ |( ^3 A
static void McASPI2SConfigure(void)
! |8 w/ J H/ [5 Z6 r( D+ N{
+ N& C- Q' F ]6 ^3 ~- {McASPRxReset(SOC_MCASP_0_CTRL_REGS);1 ]. ~6 j5 H- h' K4 c( I) U1 S! P% J
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, z Q6 F- Z7 j. o: Q/ tMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 M# ^. w9 G& _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 w/ u* X* ]* H2 V& q7 `+ [McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 A0 w# n0 |& N0 u# h/ HMCASP_RX_MODE_DMA);$ ~8 T9 k; k1 ]9 j7 M" _- T/ t+ G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! M! V e6 Y; ~- k" o* @; ]
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ o- ^. G: D8 q6 W7 i8 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, J4 m3 J5 r t, O$ G/ n/ ~4 tMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' v" N A! c8 t* v% N0 \
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / d9 H7 p. w1 S. h1 w4 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' ~( i9 m+ D f5 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 B/ D5 t g9 U/ `3 pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, e8 t; W8 O9 a- I! ^9 J/ UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* @7 A$ }: S1 `4 M; D' W2 c
0x00, 0xFF); /* configure the clock for transmitter */) o8 j7 O- w9 n3 O% r( _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);- g% F c* I& c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & x% L; {7 v" z4 {& b2 L; A# |
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; p* `% C/ L5 K0x00, 0xFF);- B2 _6 Y0 w% V! Y g! r7 ~6 t
$ T! Z- d6 e4 A/* Enable synchronization of RX and TX sections */
& P- u) w" v, @! I5 ?/ P- R0 g# EMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. ^9 m+ e" a% x: W, w" UMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. N: X4 {0 S3 Q7 Z" j" t6 e* K1 w& KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& I% X1 D! F# b
** Set the serializers, Currently only one serializer is set as
/ }, c, \& c. z8 w+ [) r" d& r* g** transmitter and one serializer as receiver.+ S6 K8 E1 Z" X; X0 E! C) a
*/
0 H) m2 [6 f/ N: QMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 Z8 u O+ p4 R6 d. E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' H0 L5 M: K+ l5 J# `** Configure the McASP pins # ^: C. {% b I$ z
** Input - Frame Sync, Clock and Serializer Rx$ y9 V% X8 U$ M; w: [; F0 a
** Output - Serializer Tx is connected to the input of the codec
( G; _% S5 u6 [- _*/
! Z& o# o" j# ^McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ J4 w3 M, Z i: {4 K! p ?; ~+ U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% W. K- i1 O3 w! R% t1 kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 N" ~- ?9 b* b$ J, B" D3 Y
| MCASP_PIN_ACLKX3 o2 H+ `! v u5 B$ @- A
| MCASP_PIN_AHCLKX$ |- A) ?% ?# f% h& ~2 |$ d+ O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" l* T2 i+ @6 i1 |2 f* Z+ rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 K! i) t5 U1 ~- s( U0 L) A| MCASP_TX_CLKFAIL
, V* a/ b; @2 P+ _; K t| MCASP_TX_SYNCERROR% N+ k9 A2 I! U; n& `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & x8 Z5 Q0 \& |# a
| MCASP_RX_CLKFAIL0 g) N. F K8 x: l" h8 Q
| MCASP_RX_SYNCERROR
, v3 Z1 Q9 J2 T A| MCASP_RX_OVERRUN);* ?$ x5 `' k6 ?( Y! I: ?
} static void I2SDataTxRxActivate(void). \% O2 {$ u3 I. u4 d9 H
{8 { z& A. g& E# U" d B
/* Start the clocks */
8 b. _' b8 J5 {) w, ~6 D+ ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 W# [( y' T/ E, S) ]" O; [
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; P/ ^) R8 s7 G! ]* |7 P1 O oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ b, {' @( M) n. W
EDMA3_TRIG_MODE_EVENT);
# @6 m4 ^* b' h4 {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 B0 v1 H( m; }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 o: h' W/ `; a# w( m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! c/ g2 m3 H5 L7 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 I6 ~6 A' R% i. C! f, i7 {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* ]( y! i6 W4 y8 q! tMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# T8 V9 L1 k8 A5 d0 eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 }2 f8 L, G4 L# p- A5 e J} 1 u& m7 R3 S: w5 J2 Q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - L! j: ]& h1 ?
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