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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. D2 q0 `) t8 L) b( {' l" n
input mcasp_ahclkx,: U1 ~; e$ [# o s$ P
input mcasp_aclkx,
; d8 u) a/ L' N1 X6 Minput axr0,
& ]0 S6 ^/ o: B) {/ y
& K4 J* D8 H3 o9 _! w0 e! X; t' ioutput mcasp_afsr,
: E* u" x+ o) x4 Q# e* ?& I; {3 foutput mcasp_ahclkr,: [# _$ ]( J+ N
output mcasp_aclkr,8 v. q! w; h. z5 k- T& F
output axr1,
( K8 w1 q9 V. o+ j8 l assign mcasp_afsr = mcasp_afsx;! y8 t3 t( G6 C m
assign mcasp_aclkr = mcasp_aclkx; j. }0 Y2 t! o4 J2 Z; Y
assign mcasp_ahclkr = mcasp_ahclkx;! m2 A$ D" r. Z
assign axr1 = axr0; . O' K! S3 J5 e6 P; g3 f* {
F, F9 Q, S1 v7 f* P1 d: _: D w在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 c& S5 E0 W! p5 K) Y% nstatic void McASPI2SConfigure(void)
$ E# [4 R) x, {7 M# w7 I% |{+ I2 ~; J4 T B V6 j/ s0 b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 O8 |: w/ I2 y% S9 i% @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
L" X. C' b1 m5 t( `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' h/ B f6 G3 V( P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 t0 o4 o! E7 q
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
J$ B$ p% r, @" w$ C% rMCASP_RX_MODE_DMA);
1 c8 r; d; Y% c& bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 B" F) _5 s" a5 ^" l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 p x. c/ ~0 kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 f, V- t% |. { [MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
z. V$ d# } A: k7 r; j! Z2 U! @) d. HMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 }. Y# O9 \% K3 v; d, O; NMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 U; [. L+ o, M4 e% i% ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* f+ ^$ K# A* K, c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & w6 b) d" e0 n' K3 C8 m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ \* R Z; e8 Q8 Z7 _( R$ L/ T
0x00, 0xFF); /* configure the clock for transmitter */9 G- u E9 {, ?, Z1 @; D
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, M0 |4 ?: ^0 Z V- {' bMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 F9 j! ^* ]) w6 w
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) `$ M$ K2 ~! ?% Q3 G4 ~0x00, 0xFF);
% n9 W2 c' C; u, F
+ e% i2 Q" s: v, [4 Z/* Enable synchronization of RX and TX sections */
7 w; ^' M; |: M! B' w! t- l) QMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, ~8 @7 \! }* }5 p$ M1 MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: ]' e7 _$ G! Y6 _8 pMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
) ~) S F& W) `- c** Set the serializers, Currently only one serializer is set as
7 b% Y# e1 ]5 w% V& r** transmitter and one serializer as receiver.* K, q! U4 ~2 O) ]; i3 y
*/
% @% `) r" g( M' @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 I7 ]$ V" N, N- C$ X
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ G$ W3 Y5 ^9 D2 L** Configure the McASP pins
7 N, H1 _- A; j7 w** Input - Frame Sync, Clock and Serializer Rx2 G; s! E+ p# w% E D/ o7 o4 ^
** Output - Serializer Tx is connected to the input of the codec
0 j# m0 t* f, H" Z- p: y& s, ]+ j*// I8 D1 J! P3 _* t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 p1 V# a v {! [3 V( d& ?: `
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); C# k! H2 T( f9 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ f% K5 B( _( ]1 v, _2 B
| MCASP_PIN_ACLKX
7 R! o. ?8 T# I; U+ s| MCASP_PIN_AHCLKX
9 M5 ]7 |: ?, u7 U6 B4 y# g7 C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 d& T9 m: T% ^9 _: i* ` U( b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( U. i# V0 {; A$ ^| MCASP_TX_CLKFAIL
5 f8 H" f6 O( J$ {$ || MCASP_TX_SYNCERROR& U6 l0 Y1 U* h5 X' @9 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ l. a# S4 ]: z! J, v0 _| MCASP_RX_CLKFAIL
8 u. P6 j0 K1 P7 x& y8 T1 U| MCASP_RX_SYNCERROR 5 c* O8 d# E% c! O4 V$ J
| MCASP_RX_OVERRUN);3 i+ b# z+ p9 Z
} static void I2SDataTxRxActivate(void): n9 ^( x$ _9 Y* ]5 L
{7 U* q; v, l9 l: a; h
/* Start the clocks */
# b7 f& Z. _5 R V5 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& W: {2 X% X: f) v( M) ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 ]( l$ L1 o1 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" v( J, F% ~0 b& X8 ZEDMA3_TRIG_MODE_EVENT);
" d* U' h6 r7 aEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; `. M0 r# V6 B ~1 j+ OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) T9 R, p9 b; ~. k+ f' N( y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 ^" l3 m w: u! S8 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 @& s, _" @4 P3 U' x$ N/ Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// v0 Y: L* V$ f' X* c$ @
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 _; `' Q6 G5 J. @: ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ y+ q8 m% \) h% h x+ B! P4 [}
- ?% g" J3 b% m5 d, A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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