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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( X! M0 a& E& ]- x5 l" Y* u7 [input mcasp_ahclkx,
% S4 T* a, y4 }0 K* Ainput mcasp_aclkx,
6 }6 g" ? o7 v. W! [: vinput axr0,
1 i" `( _: Y( `4 X, r; F! f9 g! C% u' D7 M; u& j( S
output mcasp_afsr,
( I- Y- W9 ]3 s; Y& \, L# houtput mcasp_ahclkr,7 U$ l4 B$ m4 v! S' y% R2 G
output mcasp_aclkr,0 T R l$ I$ \) J* k/ u
output axr1,
) c; `1 r e* d! Y4 }# w assign mcasp_afsr = mcasp_afsx;
4 f/ V" Z `; i8 f1 N! Aassign mcasp_aclkr = mcasp_aclkx;
- E r5 o D x5 D. [. |assign mcasp_ahclkr = mcasp_ahclkx;/ l9 H% k" [- c# j
assign axr1 = axr0;
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5 U4 c2 a3 b2 Z在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 x/ k7 ?" D: s! L, I# c
static void McASPI2SConfigure(void), i3 G4 E) U& D- k* p, I2 T
{' D* }: O' f, Z( R2 |! L/ s
McASPRxReset(SOC_MCASP_0_CTRL_REGS); |# J( m( r6 {
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */( T# [! l& T8 A6 H6 X$ Q B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 V0 W! R' l* J0 |4 d+ y$ OMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ?+ q! b- c+ Z1 s* {- gMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 p+ }, U/ ~& N+ r" ~/ I- q. T2 IMCASP_RX_MODE_DMA);
7 o @' |2 q8 `2 I! H3 QMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 Z+ S4 L) c v- ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' \1 o, @/ |1 Q+ EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
1 v. P( j Y+ S6 [" _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: f( e/ R! ?- r! B& P qMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
, } P3 p2 R/ P# UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 r0 d! G. O W5 m( E8 l& N2 z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% b* t+ H! P- c3 K \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. C; E% t" U) ]6 P6 b) C! s$ O( qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! O7 `1 i. T2 ?7 e; @& I* T& g0x00, 0xFF); /* configure the clock for transmitter */
; q; E) `: i) l- p5 qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);4 ~% A1 I5 g1 U) s1 e6 n7 c) o3 t
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 Y) G) Q6 y/ x1 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& P5 z) K9 R) M2 d, z7 W
0x00, 0xFF);$ |7 q+ K2 b3 l) R( d
! T' h* |. n3 g" _. p/* Enable synchronization of RX and TX sections */
: G! o; Y* V: m3 U6 jMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 d* {2 ^1 q$ VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& {: _* i5 V# V- q; x. X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* y" V1 w% ^. \* w4 o
** Set the serializers, Currently only one serializer is set as$ {5 j8 P F( ?
** transmitter and one serializer as receiver.
* b. k0 u9 d$ F$ l* @& o1 D' `*/
: b" D2 `/ b, j( ] }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. m# E4 K4 S: e, a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: ]9 a$ w: t* m4 a" O0 N3 m1 g
** Configure the McASP pins
1 A0 I, S5 Q* i% B' e1 u** Input - Frame Sync, Clock and Serializer Rx
# x" S: @. n! r K$ N** Output - Serializer Tx is connected to the input of the codec # b, y! i( x: S# c- l/ V
*/% k$ C4 Z. I3 ? c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);1 E( l0 k) K3 x3 l5 i
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 W& Y4 K1 _% b0 Z9 v/ N4 LMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 x# s, O y+ I| MCASP_PIN_ACLKX
0 ]3 |: x! g# ]| MCASP_PIN_AHCLKX( y! y7 B2 X2 p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- F& r3 w, v* ^# t5 r
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* z( ^; p1 u) V; I7 N) p0 T| MCASP_TX_CLKFAIL . J5 C V" J, V1 [
| MCASP_TX_SYNCERROR, U# k0 L) |& U1 w4 b7 W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( ^: v. F' X9 O
| MCASP_RX_CLKFAIL7 W8 q* \ J) H: m
| MCASP_RX_SYNCERROR
0 r5 v% ^$ E0 p! _6 Y* y| MCASP_RX_OVERRUN);
4 m! M% n2 J. @} static void I2SDataTxRxActivate(void)# c, p- x: G4 l! K5 P6 u: T
{
; R/ Q8 W+ F: B- o! \" t5 ~/* Start the clocks */
3 o5 j! `/ x% f9 c+ z& k3 @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 y; ^, p) c- s# g* S" u& @0 Y1 k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 D! d5 d+ t, i+ V; v5 C. n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, x! e, ?8 N' A" J8 [4 \" U9 dEDMA3_TRIG_MODE_EVENT);
% T6 Z; o# [8 kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / H4 m d! ?7 B! ~& q- v% m3 b, U
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; `, S2 u" N7 a6 _5 P) {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! o Z0 U; X8 D$ X. G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */" \9 a. A6 _: n3 s' y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- o: w7 G! X1 t6 a6 E% n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 E6 [$ @) o. o# P1 k- u
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: V" ^9 o4 k) N: O( V0 y} , A; b' H2 s; \ J/ ?
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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