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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 J# [) J; F2 D" N" a) U
input mcasp_ahclkx,# X `7 n1 U7 y) [& G* j0 Y
input mcasp_aclkx,0 c1 A B) O* E. b3 b2 a; y5 k4 O
input axr0,6 k5 T5 O; X! C+ C7 O! u7 t- P
i% \+ \" `4 ~output mcasp_afsr,6 K8 d( J F) s( u
output mcasp_ahclkr,
) u2 K' \2 \- x/ E+ ]; n/ ~& Voutput mcasp_aclkr,8 p4 r( v6 Q$ e, _) N" o8 ]
output axr1,& _+ B- ~ z9 r- f- R
assign mcasp_afsr = mcasp_afsx;
0 W8 z) u$ B( ^' K q6 Yassign mcasp_aclkr = mcasp_aclkx;! O: I( l' s1 F% k; p6 z6 U
assign mcasp_ahclkr = mcasp_ahclkx;) o3 ^4 b, b- c- ]- J5 d( T
assign axr1 = axr0; ! k8 I, ]9 T, A5 p- U
2 Y) S, K% N! f% m; m3 M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: x; w( O6 u) m2 rstatic void McASPI2SConfigure(void)+ u3 s) e7 x5 H3 g% T
{* @! M% x' n/ z
McASPRxReset(SOC_MCASP_0_CTRL_REGS);) E6 `, O" `1 @: H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
# [8 x1 G% p* P+ l- }+ p. {0 `McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 k" x u5 H6 \/ x$ Y$ g# x0 DMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ c H7 l. ], Z0 B- h9 S$ _. g
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' Z1 N* Y5 o3 f
MCASP_RX_MODE_DMA);
! V5 \# n _$ F' F; ^$ t% sMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 z+ d: A5 B d! `; y& ?8 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 P) P' q+ t8 Q7 ?% @6 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' Q9 i6 x8 n, p6 U" f
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# X5 P% y5 d1 J, H J* n( ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 S- z0 G, t% v- J, |6 I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- u u' c" I b# R J/ \' eMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ k! m$ s( ]. `, H6 M
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. Z' j7 Y! B3 c4 k/ r) TMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 Q1 r- m2 ?6 l& V* U) k
0x00, 0xFF); /* configure the clock for transmitter */( X; G! M* w/ c1 n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& v& y# Z+ b! J& l4 QMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; [6 I1 U4 v+ c8 m; wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 i( D3 D5 R# s" E5 H; O$ l0x00, 0xFF);
. {( H, W: |# ?. c+ e# r
1 f" e+ ^3 ?3 U/* Enable synchronization of RX and TX sections */
5 Q' p4 L5 M/ V8 l# u4 o2 `3 cMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 m2 C, p2 i8 K% [6 `9 J! j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, Q( a+ K3 l) A9 V4 f+ @% P4 w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
# @8 ^4 W, i: I+ Z/ D; \4 ^' R& ~** Set the serializers, Currently only one serializer is set as
6 M4 q, }/ K0 B& S$ G! [- X** transmitter and one serializer as receiver.5 [% B( t9 ~1 ?" l$ W( a5 J
*/1 p/ ? e5 M7 K1 X- L" N9 ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
S/ A; p/ X, NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 t2 E$ o- W6 H( t" g
** Configure the McASP pins 2 @8 L$ }9 q3 r6 R7 s3 }
** Input - Frame Sync, Clock and Serializer Rx
1 h0 o1 p$ }( t& S U8 [1 a! s2 J** Output - Serializer Tx is connected to the input of the codec
" x0 y' {5 S1 Y( Z" O*/% M1 X; S S6 P. N
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- B% f8 c" L$ b8 U$ fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
& O, E4 |# R3 R1 x" OMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX X( r& A; l8 J9 K. P/ k* N% r
| MCASP_PIN_ACLKX2 G1 g; _0 `. m. l+ u7 m
| MCASP_PIN_AHCLKX, {) m! @4 |3 H! ?- t+ G) p U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 Q# e6 l/ }. K, S0 h: [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; N2 r- K4 d& k6 F" \6 n |. R' A| MCASP_TX_CLKFAIL & m" Y0 F6 g" ?! v
| MCASP_TX_SYNCERROR( \: q, \( B3 }2 G+ b
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 G: }( I1 A7 }. Q0 m3 ]' n| MCASP_RX_CLKFAIL
& b, x& F9 e' ? j. || MCASP_RX_SYNCERROR
7 X6 W/ @& @; r; b& Z| MCASP_RX_OVERRUN);
+ J, j% | s4 C, x8 ~; c! ]3 X} static void I2SDataTxRxActivate(void)
- R1 b8 h2 Z+ N! Z{
% Z- [5 Y: U9 F, s+ U& z: m/* Start the clocks */' V& e& I: R0 d/ x
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* C& h, j9 w, c& w# ]. a
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 C4 q$ K. i, D1 P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- e0 A6 \! F& Z3 V% z' hEDMA3_TRIG_MODE_EVENT);
! E3 u& K7 ~7 I. y7 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& `/ H3 y) o" r* F: F' LEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% ~# S: R* V9 B2 }4 d0 _5 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- [! y7 g% H ?+ O' N' M8 h/ nMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
B8 ^6 K0 N5 U' twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 {0 ?' P h9 t5 ~: m; M3 J
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 I" d' F6 V' eMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ Y) _* f% _+ _1 O( R" f! l G( y
} 3 i [, p5 m m0 _- _% [. W
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + s* h3 N, R; E7 V! H7 w8 R+ e
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