我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# Z% `* A% B/ q9 `# X* s% G
input mcasp_ahclkx,
, U7 m& x' ?5 Q' L% Einput mcasp_aclkx,* k; ]/ H. @9 l" W) Z. g
input axr0,3 g2 w3 {, T8 m* q3 Q- C
7 `0 b$ L ~- j
output mcasp_afsr,9 l) n% w2 @6 n1 @( F2 n; B3 N
output mcasp_ahclkr,
+ k0 K! Z# `' V' M2 o" j( Q- Uoutput mcasp_aclkr,+ @2 V1 F$ y; ~ ^" P& p
output axr1,- U% T% t4 a2 i# r' L8 [3 I
assign mcasp_afsr = mcasp_afsx;) d1 ]' [5 @" M
assign mcasp_aclkr = mcasp_aclkx;
3 [+ \" |9 A5 r2 H' ^assign mcasp_ahclkr = mcasp_ahclkx;
" w! R$ v( c" kassign axr1 = axr0;
) `. r, c! v: a' N, G N" }) X1 P# E# _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- z/ j. H! `. K9 l/ dstatic void McASPI2SConfigure(void)7 \! \6 ]7 m4 t
{9 Y/ F2 ^! V2 O/ R+ I1 J0 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);! D3 Z x, ?8 M, W0 U( {' }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 N; q- w, a2 U2 k0 Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 a" |3 R3 O9 S" `# ~* H
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- Y: e8 I2 @; x0 o. t+ g- P
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! ]& M0 {2 g9 G6 y$ M G8 ~
MCASP_RX_MODE_DMA);
- M- g* U) Z4 h0 @ q) tMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 j# Q! J9 P6 }' m" m2 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 S0 R' Y; c `9 E- P3 e3 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, A( H5 T1 s- }& SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* P: `/ q$ {0 J; b& b1 r3 ?/ G/ }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 9 x6 H3 X' p4 j. {5 M" Z) d
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 L3 _# b+ x5 n+ E8 `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. h; j' H7 J2 G$ ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* j# H2 H# q0 V, Q8 I* rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# q' @0 n9 s4 p* \2 J
0x00, 0xFF); /* configure the clock for transmitter */1 @' K/ m3 P5 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# P% ^0 i! U$ u5 ~- G s' Z( VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 B. B/ x V, Z; vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! Q1 T/ G X. T0 J# o# b0x00, 0xFF);5 H+ t( v8 ~% T
* l8 J2 d% ^* E- U# y/* Enable synchronization of RX and TX sections */ 1 X$ K7 `' G( R: f+ i- @4 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 i6 p& w- E$ U' n0 d& }
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* `2 j0 I; B8 A" v0 p4 n8 D4 U, \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* g$ e0 U4 M% O, }
** Set the serializers, Currently only one serializer is set as5 @7 c6 q5 G) E3 Q6 H1 L9 k8 z
** transmitter and one serializer as receiver.# v8 [8 C8 D/ [: c' X$ _
*/
2 A! p; x6 m9 N7 l1 G1 T5 iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 W2 g( D3 f/ VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& i3 ?8 I8 K N4 Y8 n
** Configure the McASP pins
8 r* K2 O8 a0 S** Input - Frame Sync, Clock and Serializer Rx
2 A% Y5 _0 z( A** Output - Serializer Tx is connected to the input of the codec % V5 z$ V4 f& e" D2 g
*/
3 E0 K4 Q) |. lMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
8 A$ ?- x3 y. B" G$ ?McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
6 \5 ]: M2 Z9 A3 S, _! qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
( \6 L1 G+ C% M$ }| MCASP_PIN_ACLKX( h0 F7 h6 @% b+ ?5 W: W3 c0 q) B
| MCASP_PIN_AHCLKX% ^8 I$ _+ M9 I2 I2 X2 r( X2 f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
* K/ N) V# i6 Z. j8 fMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 Q& C: t W& f! O
| MCASP_TX_CLKFAIL
; Y( _7 i& f- X! z| MCASP_TX_SYNCERROR
/ u7 w) u2 s \& d- B2 U| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : N, z2 _- @* Y% B3 E0 K% A
| MCASP_RX_CLKFAIL$ W! b$ }5 H$ `0 d6 H, b
| MCASP_RX_SYNCERROR
" L* H4 F& \. V5 H- ]& A+ i; O/ M| MCASP_RX_OVERRUN);
0 @6 r; _& W( T2 E6 ~} static void I2SDataTxRxActivate(void)' A( o% H8 Y4 W0 B6 e
{( w6 t! l2 B1 V& z
/* Start the clocks */
7 K, f7 `$ c# w4 H# R6 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, E( n& K+ Y( E: v3 n1 B! x* g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ W2 t( B& z9 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; J+ `7 k/ }( kEDMA3_TRIG_MODE_EVENT);* C. s. ]1 z. x Y1 S% w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& Q9 V- C ?7 p4 ?! U+ ]. H$ Q9 ]5 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- A+ p/ m0 e q& vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* ~. U7 z" ^% s$ e/ V6 k" w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
* w1 \- n9 U1 d; Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; _! y# j& l2 P% L: k5 c; G& yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);- e/ t0 g1 C7 J$ U- w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- _* L& b ~* C9 l8 J} / W; P( H2 j( t* Q2 G8 P+ ^% F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
# L* C4 l) b; W0 Q |