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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 R7 ?( X# H3 tinput mcasp_ahclkx,8 x- K6 C4 y; O }: i* e0 E
input mcasp_aclkx,) w$ `, T! x1 b1 C
input axr0,
; O0 R2 |* N: r2 V) J4 n9 d- j6 j b6 R9 K0 z" o. o! O
output mcasp_afsr,
, V8 z3 |6 _% houtput mcasp_ahclkr,
4 ~5 E9 k9 F# G3 M5 R4 P# O2 Boutput mcasp_aclkr,
. }4 z' r+ B+ D; S# d; r* P0 noutput axr1,
2 z" J( g( V t( \ assign mcasp_afsr = mcasp_afsx;- l% w" _7 {6 I
assign mcasp_aclkr = mcasp_aclkx;9 X4 Y: h5 Y& ^' @
assign mcasp_ahclkr = mcasp_ahclkx;' x! V3 y/ S' S
assign axr1 = axr0; 6 ] a/ c& u* H
1 _) W2 @0 p; W& D* u7 U
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
. W+ k$ W; m# _# j0 ]static void McASPI2SConfigure(void)
5 P, ]/ \! f+ \9 P6 g" O; E. \{
+ v/ h- Z% X3 r$ Z) tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# d M7 i, ^# o" M2 F8 e! YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */; l. ]- t1 x2 G% `. X) E7 k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# V: s. N$ M, x# _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% v& ]+ M9 m4 ~; G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; W% w8 ]) D& ~7 x4 g
MCASP_RX_MODE_DMA);. A1 G& A6 }8 d: Q, ^) H! G) Z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' \& V# s0 m3 H9 l0 U9 w. r4 dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ `- W# r) z7 \& t+ b1 ?3 g
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 f. x6 S* o' xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. W% }# @6 w+ ~9 `# {: n
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " f' n* y; ]8 g. s2 q) H) `6 @0 f
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 W' M+ A! p0 d0 o8 uMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( i/ N4 U5 {3 h9 Z8 ~3 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, x$ @! m# ^: rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( J+ }* K) u( m0x00, 0xFF); /* configure the clock for transmitter */
# `. Q& u1 I" x1 A7 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, V% w( ?, x9 B3 e5 ?3 j B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 u5 I: J+ _" xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: h) ~+ n ]! G/ m! _8 {7 x2 [
0x00, 0xFF);+ S4 @9 A1 w% G" d
, t' n3 o% k8 d( o) Z* r- t/* Enable synchronization of RX and TX sections */
3 h/ o% x! p6 u$ H4 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: Y% f+ l% m; N; B- o9 M! t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& r5 S3 S9 U7 C- M$ N8 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* v( I; c, } F: b' S
** Set the serializers, Currently only one serializer is set as' M: S7 k& `: k; x6 n
** transmitter and one serializer as receiver.- i/ ?7 R1 d, z2 Y
*/! M% j7 A' W3 d' [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); L& S0 \/ D: i8 Q* u$ h1 T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 a5 q2 x* X3 T$ u8 z* x** Configure the McASP pins 8 a: [% R$ G k6 e
** Input - Frame Sync, Clock and Serializer Rx: h% B- w! Q. f* m5 q- U5 Z
** Output - Serializer Tx is connected to the input of the codec 4 O. ~* I) U& ~5 P( l: L
*/7 D! O: z$ N& S% X8 T) z7 n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: Z' K! d; ?9 E6 v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& q9 @5 \* }' D/ Y/ q! N6 c) [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 R8 r6 s* v- s' m% j| MCASP_PIN_ACLKX* T+ P% p) Z, l; ^9 J7 K4 [9 c
| MCASP_PIN_AHCLKX# a4 n: C' l$ {, D" g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# v/ K& R, b+ G, y5 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) ]8 e1 R7 Y5 ^* t" q1 y: @: w. K
| MCASP_TX_CLKFAIL . H- f) {; H% N% g$ r3 d7 M
| MCASP_TX_SYNCERROR: J# ^( N4 \1 v: S& I, h1 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / P- q5 s2 }- i7 J9 E* k% b! E
| MCASP_RX_CLKFAIL$ i( W* \5 ~6 r1 A
| MCASP_RX_SYNCERROR
+ [5 [% g, O* E) c9 ]7 v& ^# U| MCASP_RX_OVERRUN);# e" F( j6 Q( C" t1 _: z
} static void I2SDataTxRxActivate(void)
# z' }4 Q* j J. |) C{
- X8 C/ |7 T) D+ C/* Start the clocks */8 T; g9 q1 f3 d3 u, t) p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, p2 R1 |) i. g3 e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 g* m A, O6 a- }; d0 P8 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 |& `4 U8 p( b! I% K
EDMA3_TRIG_MODE_EVENT);7 a1 x5 y+ t( ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ j3 @- R+ {5 w1 i. oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* t$ D! }* W" v A0 f; ~5 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 z6 x# C) s3 i! e/ ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 H" l" i8 W! ^4 T: m: u! C$ J$ Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 _$ [& m v( f3 {0 `McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ g# [, K2 F1 Y6 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 F/ n) \( f6 O. V7 g
}
) ^' x. c0 D$ w: W6 u! D请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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