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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! X4 M1 {( N6 k4 | e
input mcasp_ahclkx,
2 m; p/ {! ?4 E$ l$ l4 \5 Vinput mcasp_aclkx,0 U# n# T. G: r3 O" h6 d' f% j/ w
input axr0,
5 o' f8 J5 K) Y! a3 W9 {
; Y0 ?' @! I; ?0 Aoutput mcasp_afsr,5 ^9 O+ |# d s3 `' l, f
output mcasp_ahclkr,: u) d' g6 S- t3 v5 f, B) w, @
output mcasp_aclkr,: A* z& J' d( d) d# S
output axr1,
& x) m m* m1 p assign mcasp_afsr = mcasp_afsx;3 p5 h+ y% g: P [0 Y
assign mcasp_aclkr = mcasp_aclkx;6 a$ b6 O; n$ u
assign mcasp_ahclkr = mcasp_ahclkx;
" c5 N. ~( C7 A7 d1 r& q& Gassign axr1 = axr0; ( u1 H& W. m4 k+ s. A/ q& Z
7 ^& K' f4 K& U) s$ G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) F" [1 Z9 R' Wstatic void McASPI2SConfigure(void)0 F0 h# ?4 X. s$ C7 X/ @
{
% t; S3 \3 {: d: U; g# [McASPRxReset(SOC_MCASP_0_CTRL_REGS);. V t& }7 R1 R9 K3 ]( {: [
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ U0 K9 E N: d0 X# [- \* t: M$ Z
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& N& J6 T$ `/ o& e2 iMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ o# K1 ], q O* B5 Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' \# G, H+ d* P
MCASP_RX_MODE_DMA);( h+ u8 l; t/ S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ w, L: `5 k3 a$ a, c0 _$ Y, u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// {2 X- T# ]" q/ p/ C
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
/ \$ E# W/ |$ F( U: u2 T) }2 ^MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);0 B# t4 }% E) k: D8 F' q8 y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ B. R$ [9 R9 E' y! w& k$ \
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: I1 F7 j4 B- E& s2 ?9 Y0 v: U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 @8 K1 f; c$ w: f' C' DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * n) S. ]# C: b& x' C
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ \- L. r" M) o, V7 _2 D2 U
0x00, 0xFF); /* configure the clock for transmitter */
3 ?, D& n+ ]6 R. Z3 N/ q+ NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: h0 D8 t/ l3 m0 p+ X& EMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 6 p' N$ R" U$ z( ?1 M, i6 P" J* x' g
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. r! u9 w d- }3 e; C: d8 D6 g) K$ p0x00, 0xFF);( n/ ]; O/ a. m9 w5 H$ d8 V
& S& E t7 w G& R/* Enable synchronization of RX and TX sections */ . {% L4 N9 j4 z4 ^6 C
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, T2 B9 H$ l V/ o- M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ y+ {% Z, u/ i" J0 M+ lMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 v' w2 ]+ U) H4 d2 p# @** Set the serializers, Currently only one serializer is set as
" g- Q) L* P6 X0 g @** transmitter and one serializer as receiver.7 T6 F. e, `5 b* g9 g% V
*/
: H+ @& m$ ^7 {7 h3 UMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);3 j* p' B1 a( j9 y$ n* e
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ P- m/ e3 q: F2 k$ d: ~9 K# l7 e
** Configure the McASP pins
" X8 I* ?1 |' J. I; A3 D** Input - Frame Sync, Clock and Serializer Rx2 _' C7 g* V* {
** Output - Serializer Tx is connected to the input of the codec . o2 I! _4 N @. `8 H5 F: E
*/
& O& t3 }, K% [McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% a& y- m: a$ b8 jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 r- P/ E5 }! m" uMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# T, {! c6 F9 u8 v1 s8 \0 B| MCASP_PIN_ACLKX
6 I+ H1 S( A) j3 l, x5 O( O| MCASP_PIN_AHCLKX$ h+ g' K c/ O- w* H- W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */) ^: \8 v2 ^. i% F' e3 E, O& {7 D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 x' h$ z2 \1 A9 W1 c, @| MCASP_TX_CLKFAIL
2 W5 Z* I4 [, X' p| MCASP_TX_SYNCERROR
; g& G! R" o) K1 i. |2 A5 K# y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 S) v- \, D$ m* @, y% m| MCASP_RX_CLKFAIL
9 z$ K! ]. u9 e1 A/ ^| MCASP_RX_SYNCERROR W5 |& y9 a% G4 [; r
| MCASP_RX_OVERRUN);
! M7 W# O/ t% o( ~} static void I2SDataTxRxActivate(void)
$ r$ q9 W/ l* n/ L' \& V8 o0 g: O5 C{
0 O' n3 m- Q; w7 z3 e1 }/* Start the clocks */
/ I3 X( J1 J R& P# P {McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- Z! ^# v, M% w9 x: j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 H- g; M( n9 T) a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 E, i( M) c6 J/ v7 R+ E, E$ L
EDMA3_TRIG_MODE_EVENT);8 f: e$ S" X7 N/ }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, F' {8 F% f8 E, m- C( I9 |% |: EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, W0 X0 E+ X1 N. i( s- U8 G5 w8 EMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ M: ]& w: }5 z0 s2 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ S+ l% E* f7 O9 N+ a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. g0 J3 {( D5 |. [) H' ]McASPRxEnable(SOC_MCASP_0_CTRL_REGS); I9 w- o" e5 }6 _4 v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 a7 V5 o6 J& w+ @- G! q" H! j" ?
}
1 {" w9 k. B+ x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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