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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" S2 S) J- {4 D" V4 Vinput mcasp_ahclkx," \4 I- O6 K8 n; E1 n2 h4 f
input mcasp_aclkx,
! M# ?: `' ^8 {1 ^5 sinput axr0,
" e: u: c' j9 }" i1 Z+ ?& d/ A
output mcasp_afsr,2 v6 n# x& M2 b3 `- ?$ _
output mcasp_ahclkr,
* V/ x; C. s; M* y0 {5 O, |output mcasp_aclkr,$ \- `0 E1 S3 F. x5 U+ a) N" q/ n, o
output axr1,: I! ?3 \, x! M7 w- p+ Y
assign mcasp_afsr = mcasp_afsx;
# k) b0 {2 V3 Rassign mcasp_aclkr = mcasp_aclkx;
) Q( t9 c$ L5 R+ L6 a6 Q, X/ S6 `assign mcasp_ahclkr = mcasp_ahclkx;
6 N- W* |$ V, vassign axr1 = axr0;
" P% i9 K2 a+ m- V* j
0 L' U6 `; c' M) r2 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 Q5 t2 B0 z/ ^+ M% W6 m. M+ Ystatic void McASPI2SConfigure(void)3 u3 f$ G# \; b9 X2 b0 Z- u- U
{$ G: z. o8 P. j3 j
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 n/ ]8 g/ K( o
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 E( G& g0 U. W5 K! m9 t" J* fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* g$ h5 p4 x& g! z- o% x3 U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! V0 _, O0 c. h( ?* j" z y& ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, \8 ^& @7 `' ~$ q+ T; H4 h% g1 E9 P) aMCASP_RX_MODE_DMA);
' H. \$ r' @- D$ K3 h2 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& I. x2 ]& d" j" R* q D7 r
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 k, @* J; l+ A; q9 m5 W: ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ h/ r1 s1 z" w( _MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ x1 U: C. A: z3 ]6 ?! a) ~2 L
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ D9 b' L0 [( f |* N# e( V# v1 @" I
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, a9 a: }( q: n5 M5 V, ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 n: p' s# Y/ Y/ ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); J t6 P/ A' g% y; k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 F$ o, Y$ G1 Z- _' a; o( ]1 {
0x00, 0xFF); /* configure the clock for transmitter */' B2 L e t4 X' t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" P$ W9 o7 S* L7 I$ h- ^
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ( w* P9 R, q2 _' q" b% |+ d4 b9 G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 o8 }0 t/ }; x6 }
0x00, 0xFF);1 U1 d+ e4 t, Y
) z! Z/ r+ g2 Q& d/* Enable synchronization of RX and TX sections */
" f K, w) s, J, L5 j3 |) W+ qMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. u4 b* {2 a% {$ V; P' [McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); L; r! X3 k; u, }$ b5 F$ p
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* ^' F5 e* Z* n6 p7 }& i4 E4 y# K3 d
** Set the serializers, Currently only one serializer is set as; y4 n+ `2 Y7 g# ^6 U
** transmitter and one serializer as receiver./ j6 |0 y4 W6 a; d V; _9 r
*/
8 [5 e1 Y0 h7 F. I! ]# LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); ]. t/ n& z1 N& _4 h
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
" f. d* ]; |! M# N7 _** Configure the McASP pins 5 c9 w0 _; z% H/ \) H
** Input - Frame Sync, Clock and Serializer Rx3 v3 S& ~) \5 Z5 I1 l& o0 c
** Output - Serializer Tx is connected to the input of the codec . b/ o" l8 a% k' q' T. N4 A* q
*/
7 y- f. T1 T! JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); N7 A9 M7 p! F. O1 ^! s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" b; G5 S+ f/ e2 {% [+ BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; \8 U/ a+ \1 I+ i: _4 Z7 ?
| MCASP_PIN_ACLKX: q# S1 @- i7 s" A1 u
| MCASP_PIN_AHCLKX
& Y: _, A5 a, r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; e; y! G9 y- ^
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 8 @* h/ p( h4 S1 R% z
| MCASP_TX_CLKFAIL
/ @9 c3 N) {& D/ V| MCASP_TX_SYNCERROR: L" ?( ~: B6 a) |# c( Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 [3 Z' _- n* t
| MCASP_RX_CLKFAIL- P0 O2 t: I) @& p8 t+ N- E D/ D
| MCASP_RX_SYNCERROR $ d4 J# n" W) X2 f
| MCASP_RX_OVERRUN);
! ^0 f7 d1 d1 B6 ^) {} static void I2SDataTxRxActivate(void)9 c' D9 `/ h i0 v& [! @
{6 [$ \6 }4 z7 m0 C7 C9 w/ y
/* Start the clocks */. x5 W: g0 i4 d. t, I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
* O- `$ ^7 B O, kMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ D4 H& a5 d6 r& y1 q1 o4 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 b/ o+ \9 ]( E( F: {
EDMA3_TRIG_MODE_EVENT);8 D5 l' ^4 Y5 u" k ?* P/ e) Z
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , ^+ Q" U) K0 e0 d; I# U8 `- }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& Y5 F, O# c2 s2 g6 _0 ~' Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& G. \ k! h' I: \9 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# @, y! C# v) V5 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' ]+ [0 K- l! M2 r, vMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 {4 w( q) |: D5 VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& M7 L1 g l8 W# G
} 2 K) `# {! p) c8 j3 D1 h
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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