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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 c4 G# p" a$ B# w5 F7 h
input mcasp_ahclkx,
" X" J4 ]! E$ U1 a+ |4 ?8 l$ }, tinput mcasp_aclkx,
" E( `4 S2 N8 q p& A8 Z6 D9 [9 o, _: Zinput axr0,. m: p ]. F0 u. b% ?' Q
5 J% H/ ?% s# z: S6 S- P
output mcasp_afsr,* G+ R7 _4 F, B, B9 y; A* M% F
output mcasp_ahclkr,
) p7 L) M) @; u$ Q5 h5 r. X" C# noutput mcasp_aclkr,
4 ~- m/ b$ |0 e$ a! P' G/ a youtput axr1,0 G6 t! }$ d% l, T9 y; q* E% E
assign mcasp_afsr = mcasp_afsx;1 ~) ?/ `+ V6 B' n, C
assign mcasp_aclkr = mcasp_aclkx;
; T6 r% Q# C7 q! c6 W1 z. fassign mcasp_ahclkr = mcasp_ahclkx;
% p, d& g. v' T% L9 T$ Wassign axr1 = axr0;
( x+ i4 r% d; e% S! b+ X
4 ^% y; K: W: P$ P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 A! U N# o1 W" a Z) Vstatic void McASPI2SConfigure(void)
o& s5 R4 ^/ |3 Z* z0 Y0 _{
# |' z) g1 {2 I9 h. _- S0 dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 |3 i" G/ W# {0 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 c+ t0 }2 [. ^+ Y, e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% o. t; ]* h8 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 e' n' S+ ]0 G; b# n+ cMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 x. C' ]0 p! c$ L" j5 B' wMCASP_RX_MODE_DMA);; `9 C7 t. I$ Q, |. B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- D3 c* B5 V4 [% G( q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) s+ [' u. w6 f( [2 u ], k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & z, t5 n7 a, o+ N: X$ e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; y2 n9 h4 | c( a6 N; zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ U# E6 O# D( S3 h* O9 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 f3 V8 Y, ]7 z+ F" Z8 N- k- ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' i# p' ^8 Y5 V- a. _7 o8 ]
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 G* a: `* s9 F }- z: ?$ A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# i6 t+ i3 N# ?( V- H) y% z3 N0x00, 0xFF); /* configure the clock for transmitter */" P, o7 ?1 ]5 N+ ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# k) ~$ k0 C) {6 L4 p3 yMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 C( E% W+ i5 D( q l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, R$ R2 c7 l( u1 R2 x
0x00, 0xFF);
1 {) w7 G0 Z% W/ _2 K: m) }, S5 g. B0 W b$ v t7 V; N' I' x
/* Enable synchronization of RX and TX sections */
z. D/ w' h% g% x$ l b9 eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- ~+ j5 A! z" P/ T4 dMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- r9 t0 d. J ]7 _ O4 r% w* x5 N
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*$ V6 }$ t d$ T" @
** Set the serializers, Currently only one serializer is set as
" I7 k* d9 j ^; X** transmitter and one serializer as receiver.- Z% V; X+ m" _+ X% p
*/' V# G! D! `& C: o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! ~8 t$ ?1 f$ j# H% a* L) vMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ D7 q. N |% m2 O, d# I: u** Configure the McASP pins
* ]2 j' W# U6 E" @2 F0 x** Input - Frame Sync, Clock and Serializer Rx
) f! b% P; k; h% l& B C** Output - Serializer Tx is connected to the input of the codec 1 u/ U( b0 w$ v0 K6 }1 K8 ~/ Q
*/
# T4 S- A. t" ?- ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ \ V; ]5 L2 z5 v$ ^McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 {" `9 T9 H2 S* s9 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ ^: W# h, i% d8 y5 S* H: n| MCASP_PIN_ACLKX
" i& y$ |. m. m7 l6 v0 o& ?2 j8 p8 }# C3 }| MCASP_PIN_AHCLKX
s! q- R8 t7 F' V4 g6 E| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& f6 M7 W! O) J! U& |4 Z' CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - i( v; c7 q! O/ H
| MCASP_TX_CLKFAIL
4 U. E; Z' X! X3 i| MCASP_TX_SYNCERROR e4 J9 o4 A7 |+ n/ b9 b+ w
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
7 t/ ~! ?: M# O9 E1 b* D| MCASP_RX_CLKFAIL
; T" R. ? a4 Y| MCASP_RX_SYNCERROR
8 s; g, H; q. t$ \| MCASP_RX_OVERRUN);
, ?, ]8 {: O" Y* ?} static void I2SDataTxRxActivate(void)
# Q' U& `( U' }& V: o- U{
! A9 J4 D6 r! f; F5 u/* Start the clocks */
5 Y7 }, I& R6 ^/ ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- @5 x9 R- o9 b: y+ U) U8 M. n6 A4 bMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */9 z4 b+ z, _4 ~. g! H/ ^- m8 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) k# U) p" b, E& e$ S
EDMA3_TRIG_MODE_EVENT);; y9 @- }5 H8 O T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 ?" @$ y; T! \, }
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */7 _9 p0 j5 u6 x7 Z. B9 x. U; V
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ D( l# x; U: O0 Q, c( {' j3 L) BMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" M2 P. G5 D5 ~, Q3 e$ W" o9 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 s3 F% }* P2 }+ E' ^) Q1 @0 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( b! T: o0 ^; s$ G% J* w
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
b# ^1 v# L7 F}
* w6 @, R: h% l- ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 5 A% ]2 A5 c0 p# \; _% J
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