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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( q' {% }& O) U3 r: R% dinput mcasp_ahclkx,
+ [; x0 k; S1 m3 P, Y" Uinput mcasp_aclkx,7 q. o, h& z5 v0 {8 @/ w
input axr0,
4 Y C. @, g; v9 e( b8 A) P: ~
9 M3 H! i4 ?* V+ y: u6 Z$ M8 Soutput mcasp_afsr,
j/ u: I- c/ }" w! X' zoutput mcasp_ahclkr,
9 b% R8 B* I8 _( t4 Boutput mcasp_aclkr,
4 S$ D$ ~% i; r8 c# h4 |- foutput axr1," Z* q r$ j3 z" _) o/ B6 y0 o
assign mcasp_afsr = mcasp_afsx;" C$ z$ h# G4 o3 c+ @( x% Z
assign mcasp_aclkr = mcasp_aclkx;
& _5 I% N( G A' t/ }3 c" Jassign mcasp_ahclkr = mcasp_ahclkx;1 {6 m; c* ^8 ~/ n% c6 q: J
assign axr1 = axr0;
7 M6 ^1 \/ A5 Q2 p; W. H' Q+ w9 y; F. I4 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + V3 q4 V) q F V7 y' ]; y2 h
static void McASPI2SConfigure(void)# y) I! ?* U' u$ J. T
{
9 w3 f+ j: q2 {8 [' PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
- ^$ G0 Z! b* K# tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 p* ^( | }' X+ }, `
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 P) j2 {# { v( P2 v2 x2 Z, _6 w
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! C2 ^: n9 g3 c* @3 |4 S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& o* f" g* G% l9 ~) ?
MCASP_RX_MODE_DMA);8 j# {* Y# \2 v9 e' h
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; }8 l" |, [7 q6 {* d B( h+ N7 vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ X. ^9 {7 m7 R$ c1 Q3 F wMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! W7 T# [, z. v4 s- RMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; ]% p. m* X6 h) uMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' C& m, n4 u, L6 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( i; w9 P0 G5 b- [% ^9 b3 k; aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- X6 @1 j- E( q% N/ k+ e& TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . C1 W' x+ T0 [* e, g" g n# l# b# ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 a: ]2 K, {& T7 C% Z* N7 P7 E# L0x00, 0xFF); /* configure the clock for transmitter */
0 k" B" n/ i7 C4 W$ x- A( z4 `0 nMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
: W1 z8 Q. P+ z4 }* T uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 U. P1 C4 p( N. c! K
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 M1 u4 x1 Q: A; c& Q( G* r0x00, 0xFF);# u/ f# Z8 Z6 X7 J5 p1 E
# Z8 B+ z3 [, Q( S% G* z
/* Enable synchronization of RX and TX sections */
0 q5 p1 }6 |1 fMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; M( s7 P: q* I' J2 S7 ~, z! w: ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. ~8 j3 H" s# c' A
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! b7 M g7 j. @0 {2 _** Set the serializers, Currently only one serializer is set as8 J/ n3 Y! g* n% g: R0 H: z
** transmitter and one serializer as receiver.
& |5 g* ~! g7 d8 o' n*/1 Q2 b; j8 ?' k& x1 v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 f+ [/ t+ Q; c/ I1 v( W! ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 c8 h8 H8 v" L** Configure the McASP pins " {# _5 `- Z; S, m( h6 i* ?5 x
** Input - Frame Sync, Clock and Serializer Rx
; z; `# [/ r8 s$ T6 C** Output - Serializer Tx is connected to the input of the codec
! u% V# g' ~! ] \) }$ V" R*/
- m2 l: P1 h* i3 \/ {3 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; a% @ r0 r' z2 M' d# h4 _- jMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) _0 Z5 O' Q; }% A" J6 B: c, A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 X& i% E! m8 W" O: a| MCASP_PIN_ACLKX$ q. x9 Z2 ]3 m7 x5 H& b e
| MCASP_PIN_AHCLKX
: B+ U ]# E5 L% C8 I8 U M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' K. z, _' }6 r/ `; O- w+ f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 n9 H! q' t/ h5 x5 || MCASP_TX_CLKFAIL
$ D1 K& a6 m$ C5 n* F| MCASP_TX_SYNCERROR! w3 {" j" E# D- j( [ V3 N2 g) n7 i
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & h- L- M9 ^8 Z( U. N% X$ z
| MCASP_RX_CLKFAIL
0 Q9 `3 n8 ^ L# \9 i( C" J| MCASP_RX_SYNCERROR 4 Q% ?" G+ ^* _% {) C; p
| MCASP_RX_OVERRUN);6 r* X/ ^- [5 @/ u7 K, i e
} static void I2SDataTxRxActivate(void)* F6 ^8 ^2 b* k9 S' H
{
( B7 d5 R' h/ A3 Y' ~! n/* Start the clocks */
+ ^/ r( _9 x, @! MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- n- ]8 c; n2 m2 ?
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- W8 Z' C3 D$ \# @) ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 ?5 H& O( i% y8 }7 ]EDMA3_TRIG_MODE_EVENT);, N' V3 J5 O( S( ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) J h( c" S K3 K3 G3 c: n
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. ]2 p$ q4 g9 n% P, t1 {" \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% q9 `% W( X6 J4 g1 {( t: w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 v, r. m9 V) y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
: L' J+ |$ G; hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# T' o2 d+ `/ g3 QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. d4 f% R2 H8 U7 H" a- @7 D} 0 W5 z# Q2 V2 K+ Q) O1 b
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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