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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 ^2 o2 J3 e& C4 x& w4 O
input mcasp_ahclkx,
9 @7 q) q9 @* _input mcasp_aclkx,
7 Q! l! G- w; { }% binput axr0,4 R1 z8 c+ P( ]( I) `
( O) u# t) w9 M+ Woutput mcasp_afsr,; ] [7 Q; C5 {: R
output mcasp_ahclkr,3 d) }% J: g7 m& o' `
output mcasp_aclkr,% ?# s8 K6 x- Z: r) h
output axr1,
3 p2 [& c) m* W c assign mcasp_afsr = mcasp_afsx;
; T/ U$ R$ K# p7 Y" J" [assign mcasp_aclkr = mcasp_aclkx;
0 X" Z2 J) a+ e% b2 \assign mcasp_ahclkr = mcasp_ahclkx;# m. H! I6 p& J `5 K
assign axr1 = axr0; % e9 ]) M: i% Q- E& z3 z# Y
: @( B8 L- J4 T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 n! R, b$ E; e1 n$ J" y4 U# }' fstatic void McASPI2SConfigure(void)" z* n6 X. K8 h/ M
{
. Z, U' q" L! H6 Q1 vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( S; L$ D1 J& Q2 r& aMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ D: c5 g$ h" E( \McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 q0 ~' ^* G3 Q8 _; q% L9 S* ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */. q) f9 r. }3 u. Y; f
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; g1 f$ z8 Q2 o% U5 R- b( ^4 |
MCASP_RX_MODE_DMA);
" R$ I6 x' _4 c o) \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: B6 f3 S* O1 T1 m0 qMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 ^, p+ v" N" {: IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: s4 M, N n0 L% A% |4 I/ a5 b; oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 N: Q; p0 s$ _7 A8 f* pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" d' z8 _" l. o2 t/ MMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 t+ x9 q1 s+ A# u* BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 L# r# x: G3 d XMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
; ]6 N% b) \. h6 W+ o0 j0 DMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,1 B9 O) i4 j, {! p
0x00, 0xFF); /* configure the clock for transmitter */9 Z3 w( D% y: q/ U, [1 t8 |8 k
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); @1 E3 `% r8 b" y& r# k: T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" }: W8 L3 o4 ~" {! g0 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 O$ r0 W! Y7 l0 s$ V0x00, 0xFF);
9 M% F1 k8 F3 T0 _# m4 ]0 f
8 B( d+ p4 h3 m; I3 f/* Enable synchronization of RX and TX sections */
$ O9 e8 W1 h2 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# ] a: U0 l0 _5 t' ^3 c( ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! H4 c% \. S. X& p5 U, T2 J9 iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( j ]8 T# U; @" V. N
** Set the serializers, Currently only one serializer is set as$ `" B# i) C5 t3 ~1 x/ J
** transmitter and one serializer as receiver.
/ g7 G4 K. X( C2 Y. b*/! q, T7 }$ p: O- B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
: U0 o E' |4 G% qMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
- a" j! q' k. V/ D. l5 p: }* K** Configure the McASP pins
/ v1 g4 ?2 ]. N) D** Input - Frame Sync, Clock and Serializer Rx& c& j* ~& ~# n8 G- d
** Output - Serializer Tx is connected to the input of the codec
; B9 W/ ?4 ?3 v# n1 k) E; d*/1 t! h. ?# G4 }. E# L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* ~/ S; r( T9 x1 p. {McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ O% s' S' b) p- |1 rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX s& n d F2 B# A: r0 Z
| MCASP_PIN_ACLKX
/ s T/ T- ^; {4 ~| MCASP_PIN_AHCLKX
) E2 n$ b m H! Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. `& R% U& `: T3 j% wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR / u* W8 s, R+ b! o% g
| MCASP_TX_CLKFAIL
0 ~9 X# U, `. m5 ~| MCASP_TX_SYNCERROR* P& @& V$ P4 T* o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / ^" L: j* k5 Q' t) i* Z0 c
| MCASP_RX_CLKFAIL
e0 g8 v$ Z/ M) \9 k| MCASP_RX_SYNCERROR
8 m7 F2 [1 Y0 l0 ?6 V% c' p| MCASP_RX_OVERRUN);" V' l# |/ [ i1 i ?! f% l4 q
} static void I2SDataTxRxActivate(void)9 G; g& S/ }( K# j4 D- U' Z/ V
{
, ?5 C" a4 I% {& G7 M* ]/ A+ M) k) ]/* Start the clocks */4 o, K, [* M- T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. _) A- j' U- i2 dMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */# ^( L: y8 v6 o1 X- F, V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; z- O, }4 `4 B0 l( J
EDMA3_TRIG_MODE_EVENT);8 D( u4 v! Z' ]9 ?1 i
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: `$ n/ m' [8 u: Q6 Z8 ^5 yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: [: d F9 n) ?0 \; iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
u" t# q; d- y8 [% ~) u7 zMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 s( O. j. O# l: a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. v' h* H0 G ~3 i! M; v$ t
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 T7 t. w% e `/ Q2 l( E$ |6 xMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- r8 N; `5 s: i; o9 @}
, L$ T6 U+ ~5 h& d3 S请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & I3 f. O! j% U
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