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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,9 G. n* w) o* e9 u' x
input mcasp_ahclkx,2 G; o5 o+ a. a% [) [: D G
input mcasp_aclkx,
, V) U; E: B `1 t" Hinput axr0,5 [" }; J0 @0 ~, U+ r3 h" F) O3 j
5 Y! } z/ A4 u a/ K; woutput mcasp_afsr,0 B) F: l7 C3 k* h% {
output mcasp_ahclkr," u. E) u, ?, Y! Y1 n
output mcasp_aclkr,6 T* S, n; y( V; ?' ?, @
output axr1,* I$ ^% t0 \8 |% B0 j2 J2 U
assign mcasp_afsr = mcasp_afsx;( l& c7 j" b( I6 r9 B
assign mcasp_aclkr = mcasp_aclkx;9 d) R+ |/ }- g+ g
assign mcasp_ahclkr = mcasp_ahclkx;; H: V% Y; Z6 N/ p. H3 Y
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& k @" O0 U1 vstatic void McASPI2SConfigure(void)5 H c4 v! `( _/ B- r( c+ R& _
{; t+ D7 Y8 q) k8 o& x1 G8 q. c+ d
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 S7 s- L. s, o8 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ D% @1 m. ]! U8 w9 @$ xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! c9 q3 \& t( V% [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: e0 N6 F( e% @# C# n
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) B# B, H9 W3 r* Z" I, v, wMCASP_RX_MODE_DMA);
: r. w6 q9 }, {: v6 R1 A NMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 U+ F! v B8 j# R% u |5 V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- Z% M, Y8 q" }6 Y. V6 G: A: ]* v3 |McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 y* g" ^3 c/ M6 _7 |: u, r! LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) j2 y2 G/ b$ r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% e$ C1 l! Q8 z2 z" N/ KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
4 X4 \% O+ q) D( V# p7 R3 _3 G1 t/ RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 P8 F' N, T) i# O6 k5 O: m( @
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ y Z: N& ~, u' H! m% lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 E9 V+ t! |( G" F) o' m7 j0x00, 0xFF); /* configure the clock for transmitter */8 L3 h- P t3 @- J M) q' d# p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ S: A7 D7 C& ]3 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
& _# ]- ^# T* E+ A( O" Q) \% v* IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 Q1 o9 E: H7 p$ i/ c' P0 t4 T. ?. d0x00, 0xFF);- I+ v* b7 A% @$ R, u* @* g/ G4 i$ u9 n
8 }8 e' q r1 D/* Enable synchronization of RX and TX sections */ : s4 y- H+ e2 g) s% t. d- ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
" T3 N' R$ K3 z1 ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* y" b0 e7 z$ o: ~: G% X
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 _8 {6 \2 T$ }3 _
** Set the serializers, Currently only one serializer is set as. _- \, I! @/ G
** transmitter and one serializer as receiver.9 Y; L* e# x+ S$ o- U$ s
*/
$ v2 c+ [: j# A: o$ _" @McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 k x) N: ] E$ w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, c' a, }( t6 A7 p7 \/ L
** Configure the McASP pins 6 J" J/ s4 h2 Z/ c7 {! O
** Input - Frame Sync, Clock and Serializer Rx$ C; O" H* v" v7 K' [" c
** Output - Serializer Tx is connected to the input of the codec
- ?. q( Z# N6 G. s3 }3 o! P, k( h4 [: [*/$ _3 D. d; @* K+ V- G6 i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. i H% t( v, [; h4 q! Y5 {
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- l0 c# l" v6 P
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 ^3 D* S3 G! m: d1 b( O4 C
| MCASP_PIN_ACLKX8 F* V0 }" D% x0 `. B8 D
| MCASP_PIN_AHCLKX' }9 z! Z' } u- e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, K: p2 l# }, L& t$ ~1 sMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. K' C( T. p9 f( ^- ^: m| MCASP_TX_CLKFAIL - x ]% \+ e, a/ F3 e
| MCASP_TX_SYNCERROR
2 m7 ?- Q/ Z% q" @% N' K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # o+ \9 l6 k; w* x* q; T/ \: \
| MCASP_RX_CLKFAIL+ J8 ?; P" }+ b/ U
| MCASP_RX_SYNCERROR
w( S: d# ]3 w9 u+ F, T| MCASP_RX_OVERRUN);
" I" @/ O E7 Z: N% v; y- s1 o7 a} static void I2SDataTxRxActivate(void)
7 g9 y" C6 m& _4 ^+ }{
) j L- {0 K- t$ {9 X- W( ?/* Start the clocks */
4 o1 l& ]( D9 Y1 j, kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
# ~- D+ X/ j: E' \& d0 RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 C, J ]0 U+ z8 v8 s$ e2 \EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' X7 H% O# ]$ mEDMA3_TRIG_MODE_EVENT);
1 X4 D/ }6 Q7 S8 l! c: mEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, C d( |% l$ {3 n8 w
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 p' ]* f: P. M' @# b: M- yMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( z Y; T- ~6 M- O7 w/ R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) M3 Y( V2 y7 F$ x; { E, V6 ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 r1 U: x+ ^; l, I" E/ N5 B5 a9 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 q3 k3 h$ n. rMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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