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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ f) o0 f' n( [
input mcasp_ahclkx,
- ?; y0 }3 A! P* r$ p3 J/ K' Ginput mcasp_aclkx,& j2 c( U, K$ t( _6 J7 a- ?% \! w
input axr0,/ V5 |" d L$ t7 ~( t1 q g
0 @1 r7 {$ x# x( n1 F% P' _, Boutput mcasp_afsr,' w5 M& C% Y/ j8 ?- S( f
output mcasp_ahclkr,
0 z+ ? b2 Z6 u3 o2 O9 b% |, J% aoutput mcasp_aclkr," g9 t4 Z) S1 a
output axr1,* e9 Y# R* ?: I5 a2 t" ^
assign mcasp_afsr = mcasp_afsx;/ a- Y4 v# e/ o& J! ^' l6 I; f1 O
assign mcasp_aclkr = mcasp_aclkx;
) p# V1 D$ h) F4 O2 ?" z4 rassign mcasp_ahclkr = mcasp_ahclkx;
a7 P/ {( [. A3 c% e( _assign axr1 = axr0; / m( a: n# `! g+ _1 T
$ V! H" j9 g) Q; T' E( m: d1 {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 x8 g) T2 w D3 j" y
static void McASPI2SConfigure(void)3 J. _9 ^& A Y$ z
{5 @6 J( B0 t# q" B/ `* P9 _% ~
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 H% C, S) J3 d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' Q/ o _; N. A! d& X9 e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ]* N, G0 g' [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. K* M/ Z+ T8 M- oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ B3 G& L" X+ p* p1 i% {% Y O* fMCASP_RX_MODE_DMA);( ]1 p, b4 E, c
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- R. \7 c, m% @! E$ q; V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( H: R; X& H5 ^2 S8 r; l# J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, V% {: U- `3 ^/ L; R5 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- o) ~, `, g6 Y/ H: p/ ^0 B. E
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' v5 M( a& l* d- t, A
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
+ ]+ t3 I. z$ q/ i6 K" z/ gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
% t. M' C; Z5 F( D( c7 [ DMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * b3 ?; i1 e' m' u$ }, V6 a7 J. H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 R' N. V6 C! u5 b/ ?* ^" v0x00, 0xFF); /* configure the clock for transmitter */
! _2 x1 c- C$ m; e" j/ JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" X1 I3 t, b+ ~McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 E. Y. q- Z8 c- PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. n2 R t3 y7 W& z% F0x00, 0xFF);6 @* x( ~3 o0 p
7 b. X8 e( g$ ^5 f; ^0 s/* Enable synchronization of RX and TX sections */
1 T# u" z1 D8 r: y" \! x9 dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* @3 Q! }8 ?% m# iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# }3 @4 b7 y0 r1 U" o, k" BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 u/ N, e: f* j** Set the serializers, Currently only one serializer is set as
1 D: L5 p. {, ]6 A$ D6 x1 y** transmitter and one serializer as receiver.
2 R# D* v% C3 i( d# k*/
' u. Z! ]6 U" \. M5 D4 m+ ?& FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ Q; I1 F- A1 [: P+ M
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* T8 N! ?, e- \/ d2 d; X
** Configure the McASP pins
7 E# z# x& f8 B- N! ^( k- V** Input - Frame Sync, Clock and Serializer Rx9 X7 z; \, H& p# N* I
** Output - Serializer Tx is connected to the input of the codec & ] a& e8 Y* e% g: j
*/' J! l: A' k) t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- q& g5 ?6 U1 L. d! F- r" ~6 gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 K+ k0 C J( a, g: i! vMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, j, t* {9 ~3 K% k2 X8 H# Y| MCASP_PIN_ACLKX, ^; V$ o9 F$ c5 T) c5 d8 K' s
| MCASP_PIN_AHCLKX
9 r& {' D) D {3 p# ?9 _+ b1 ~| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
- F. K8 G2 K- B1 r8 G. iMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ H! c0 p2 O- z3 b! w7 o3 j. d| MCASP_TX_CLKFAIL
5 U8 L; X# a. Q" i1 R0 Q, u( K! Q| MCASP_TX_SYNCERROR
_. s# U: @2 K: S8 p| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . i C& b6 N! _9 {. F8 y3 T
| MCASP_RX_CLKFAIL
- u: x) D! u" T| MCASP_RX_SYNCERROR 6 a; a# R) ?) P( j8 }6 P: |
| MCASP_RX_OVERRUN);2 e& o. L4 i. X d4 }2 S$ b
} static void I2SDataTxRxActivate(void)+ B0 ^ z' p" l0 L' [; D
{
: s/ x4 M; c: `; o0 d/* Start the clocks */
$ ^, v" S" v* z6 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 \: L( T: V% C# {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */, h. e6 j" {" e" f5 R$ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& E6 z8 q4 T9 g3 n
EDMA3_TRIG_MODE_EVENT);
$ u7 h5 z2 d( p# G2 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" j" T6 L4 b2 H# T3 hEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# N7 J$ x/ H$ p& B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( s; C: K4 D: g8 N+ Y$ w6 }/ h5 r+ FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 ]9 t6 Q; c0 q4 _9 nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- s8 M/ f7 {+ ~6 ], {. t) q# HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' Y( p, n6 l: y a; QMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( f/ H) H/ G9 o6 d' ~& N} ( K& n6 D8 y9 T! l9 k2 G {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " S+ t$ O( C4 B( r
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