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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! A( Q( v8 p3 _9 rinput mcasp_ahclkx,
2 Y+ _/ p7 P1 f) ginput mcasp_aclkx,3 Z4 P( G p. ?4 t
input axr0,
4 ]5 \, Q0 M4 z3 a, a1 C
) a0 G8 B$ k V7 c t( \ b7 [0 zoutput mcasp_afsr,
+ O$ g# y ~% V2 t1 v' koutput mcasp_ahclkr,
8 ]# N. F8 m$ y5 o% [. W; xoutput mcasp_aclkr,( t4 I0 n4 r L
output axr1,4 d; ]% C2 x$ Y9 _4 K
assign mcasp_afsr = mcasp_afsx;
^/ ?1 |9 E, Y' g+ |$ fassign mcasp_aclkr = mcasp_aclkx;) i+ T5 B2 A7 v
assign mcasp_ahclkr = mcasp_ahclkx;# E5 s7 S8 ~& `7 w G& k
assign axr1 = axr0;
% K$ v d& f5 ?; u5 g0 k- a( T0 _9 @) w% i- b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& \# E) b8 t( g* L" Q) t6 Ostatic void McASPI2SConfigure(void)
$ w/ x! _7 ~% @/ s8 p3 o% o5 N{4 j, a+ _$ ?, i0 l1 X* m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 I" ^ m. P9 B, b) }7 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 A( p$ u$ d5 BMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! H# A# ^1 @- z9 @$ U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% r" G8 n* a" H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ x7 e4 R9 H. g/ `' yMCASP_RX_MODE_DMA);
/ ^9 @/ |) I( XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," I/ ? @. \8 d; b
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 x6 } B, m h' w n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , w+ p3 }9 A1 w, D/ [ H8 I
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 F9 {% V$ W$ ^- N7 F$ Y, B' ]McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( q" \+ G! @& `6 `9 sMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& g) o2 T/ }! B$ z# A2 ^7 T/ W: B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. m0 Q$ G' b( u/ ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, C, q f/ r# ^# x& w6 MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; ?7 g; `9 v1 B$ e" Z9 Y, o
0x00, 0xFF); /* configure the clock for transmitter */* [8 a- f" Z5 W+ I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: f8 y" Y% W2 F: w, X3 K9 f B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 ~+ l/ m/ ^; I, u$ E! v8 ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, ?1 H- Q9 N% m6 |; P
0x00, 0xFF);
5 F1 o- b0 s4 n) u7 V( Q0 D4 q9 {3 b! k4 g8 m' F! P
/* Enable synchronization of RX and TX sections */
" P% ~9 J( B, NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ _: \0 [7 `1 E6 `7 w0 U5 P. @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 g& \+ e" k6 T6 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 s5 ?9 r$ d+ v+ [1 i3 s** Set the serializers, Currently only one serializer is set as
5 }3 o/ E: L7 y6 l( p0 ?4 D: {+ |( f6 p** transmitter and one serializer as receiver.
9 ]& k5 e$ |" I# [& G*/0 V( ~, w/ R7 C" U5 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ S, e. H" ?) @4 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ T2 }9 ^% g$ S" T" ]7 e6 A- N; D1 x
** Configure the McASP pins ; d+ o( z& C( K. A
** Input - Frame Sync, Clock and Serializer Rx' x) l$ Q/ { v3 E
** Output - Serializer Tx is connected to the input of the codec + k, a1 l4 ?8 g$ @% u' j
*/( |) A2 | @2 [& R
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
1 M) E* b8 B) O8 [ iMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- Y* ?4 C3 \: J2 p
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 J2 ]* V" t" f0 L. Z B: f S
| MCASP_PIN_ACLKX
* `# W1 @, r0 H; N| MCASP_PIN_AHCLKX3 O( Y# ]7 L1 O: [5 p( ^8 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( k0 Q2 |+ i2 w0 J5 [+ U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 9 r! R3 i8 U# j b1 {1 J5 k5 p
| MCASP_TX_CLKFAIL Y+ q+ `6 e4 @; Z
| MCASP_TX_SYNCERROR0 D) G, o6 b* Q( r7 n6 h3 ?0 Z5 j5 e
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & A: f O: h# J* Z
| MCASP_RX_CLKFAIL
9 U1 b: c1 g3 f, b( x! X; A+ _| MCASP_RX_SYNCERROR
$ ]- W( R5 k( e2 _7 K6 i| MCASP_RX_OVERRUN);/ @4 Q2 C$ }7 I% G6 O+ ^; }9 ~2 b+ Y* @
} static void I2SDataTxRxActivate(void)
0 K# j1 Y" p9 S7 n* |0 R{1 w0 P" ^% I1 s3 T. N8 M+ U
/* Start the clocks */
4 u0 w5 c# @- e. W6 u: uMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& m+ D7 O0 x8 \) e1 Q6 cMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 ~: F& x& U4 \- T8 f2 M& c# F! u" @EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( S; q: I1 j9 T" p0 VEDMA3_TRIG_MODE_EVENT);; v+ D3 F: ]3 c2 @4 o9 Q5 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 G! o# Y8 Z( n, Y8 ~2 kEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. s2 |# m9 B8 Q% U! N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 ]! a$ P* J- I# e
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! Y6 V# l G! t1 l/ l, Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( z5 B! X/ p8 x1 H" C! IMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; G6 h" y. T) b; uMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- R$ O2 B: K: S( q# T}
' r T2 e9 ?! O3 A: ?! l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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