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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 ?# X) k* d& I' k5 f; Y
input mcasp_ahclkx,
* |- ?+ \. K, O$ dinput mcasp_aclkx,+ f+ T4 v2 P, U
input axr0,( O6 e* `$ H/ U
4 b% O1 N U7 |: G' t6 E
output mcasp_afsr,
$ y* k# E8 l1 q1 `0 H- A" ~output mcasp_ahclkr,
) j+ F0 ]2 U$ Eoutput mcasp_aclkr,
, H1 F6 l* T; b. }" E0 S foutput axr1,/ T( F( G/ M$ T# Y; ^. i
assign mcasp_afsr = mcasp_afsx;* ?# d3 y# C( X u. K
assign mcasp_aclkr = mcasp_aclkx;
' h- c3 G0 u. q; I$ `assign mcasp_ahclkr = mcasp_ahclkx;
) w$ u8 r/ Q) I! z* `- \assign axr1 = axr0;
( P, C3 G" f8 u% K x* U' V! A, d6 a4 {, K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
5 k, E. O8 [+ c$ h! ]static void McASPI2SConfigure(void)
2 ? W W* v, j" @' O7 G1 w2 F5 M, {{; n) |2 j$ p r
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; L& v' q. K q' UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ |) m" J0 m4 E% j! @' a
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- }/ L% D+ H6 ?- |+ ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" j" ~# b4 g0 v8 ~ ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! l1 ?! N$ I5 q* Q- @
MCASP_RX_MODE_DMA);2 j6 m w- L1 L. f7 ~5 b
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ i) w2 M' `5 ]- U) D( _; e' T) }; u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ I+ v \7 q: M8 o$ y$ `
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ I. j& a- v) V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 S* l ~9 q* L) i; U3 i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ! b0 W5 L" L+ b+ t& ]7 e# B' K/ o
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- X t) d$ d P @0 c8 ^
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 r; R3 s/ a4 j' rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 t) R4 f% T3 c/ e9 R5 V* Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ v! M1 M$ ]% b! m5 C- ~0x00, 0xFF); /* configure the clock for transmitter */5 v8 R! \* n1 }) a* X- a( q
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);2 R3 H1 d! ?8 X+ O) G
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
A, T& a. ~2 G3 N$ U0 u" sMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,$ T; A" D! G! t4 h1 j. _9 R" D% e' t
0x00, 0xFF);
" I; j- A/ s8 \# o4 q
: B- D( {& C2 Y) e$ A/* Enable synchronization of RX and TX sections */ : Y4 ]2 H' b$ p5 e0 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */0 f$ c: ~' }+ `. T8 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 b! F. k) _! V" O6 b; N _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) h3 |2 Q8 G+ q$ ^/ V
** Set the serializers, Currently only one serializer is set as# y' o2 C, W" d( `) \! J3 |
** transmitter and one serializer as receiver.: H' K F% E5 j4 s9 @0 C
*/2 K5 \8 ~5 _0 L7 }) O/ l2 [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); ], o {4 T9 W6 [' r w
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. y: y$ n. N% Q1 T
** Configure the McASP pins + {5 w8 H! `% Y$ l( M
** Input - Frame Sync, Clock and Serializer Rx
2 o4 n" P% `# Q6 D# v** Output - Serializer Tx is connected to the input of the codec
; P: x( u8 Z E1 c* n. ^, u. S- ]*/' Z) S( M% K9 F+ e: T6 d1 I
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 k7 R$ H4 M/ U! h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 n9 n- B m* p) ?9 f$ e( m# U7 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX4 x6 L, T/ v# e* S. P
| MCASP_PIN_ACLKX
; m9 T- a: x$ \: O| MCASP_PIN_AHCLKX
& k, ]! j, _5 t: w8 q& ?| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! I$ [7 H" d. Q, W% q$ ~3 ]1 Q- @: ?% yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: m" v4 } b9 f w| MCASP_TX_CLKFAIL 4 b) ^4 k6 }2 R8 n, F
| MCASP_TX_SYNCERROR
8 x+ U# Q, N; @& Q9 D| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; S0 h" B8 O5 V
| MCASP_RX_CLKFAIL
$ S# k0 m. P% m3 \" [# U| MCASP_RX_SYNCERROR
( e9 _5 Q5 `1 v* ]" b| MCASP_RX_OVERRUN);
( d6 P% \! x( }5 d& R" C} static void I2SDataTxRxActivate(void)$ m9 N* }8 l3 n" C2 [& G! t
{
9 z7 s; w/ e# ~8 s/* Start the clocks */. f- k- @7 R' Q3 T$ L
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( ]9 x+ C+ H( B1 m. f/ ~ b" z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) F* ~' L( a. i) oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
% Q2 W/ p: v2 K$ v$ vEDMA3_TRIG_MODE_EVENT);( c+ l" N: P/ K: i0 J" |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
# L/ G6 E0 ?# x/ GEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */+ N8 c) C4 Y& G" _" ~, \8 C$ \1 Y
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) g5 L. F7 V. `4 O3 P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */% Y' @1 n: h; ^8 C8 @* _
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
C+ I1 ~6 k8 U, Q2 T* C4 H S9 WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 c% Z+ U& }8 g# V
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( m2 L/ a9 K. T}
% U ]9 [, u% a2 _请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. . D; r( i, ~" W8 g5 b% n
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