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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 O' e Q! J- F7 r
input mcasp_ahclkx,
+ n* [/ s3 ?5 D' H* O: |input mcasp_aclkx,
3 X) m8 _9 @; \" vinput axr0,
3 \+ I( J2 s- x! Y' [' I5 R) g# |$ ^
; Z& T, _% R4 w1 y2 C" b' ?output mcasp_afsr,3 |$ ]! I0 F) N# \
output mcasp_ahclkr,
s& K/ h6 K, p1 x: I! Youtput mcasp_aclkr,
+ w. N+ q5 m" loutput axr1,9 H) Y' J1 a* f& v
assign mcasp_afsr = mcasp_afsx;/ F: u: P4 A/ [2 z& }) B
assign mcasp_aclkr = mcasp_aclkx;
0 u7 U; R, g, wassign mcasp_ahclkr = mcasp_ahclkx;
8 [5 k% w |) X# u! ~9 o' m/ passign axr1 = axr0; ! r% j: F- }0 `8 O- h% h
1 l1 T6 I- K: c2 _) F
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : e& s( x$ R' [3 \. n2 U6 A
static void McASPI2SConfigure(void)' Q* v8 H9 S3 v- K
{
4 X, H5 X$ T. r% xMcASPRxReset(SOC_MCASP_0_CTRL_REGS); [. E A. l9 J, N" x+ J/ ]$ T. V! }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 a/ e8 e: c/ o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 f9 B3 V* a1 z5 u) y4 a1 ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' F8 p# a. Z0 i" [- E4 h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" e7 r/ }% h6 j! q6 o4 cMCASP_RX_MODE_DMA);/ r6 {# x2 d0 Y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 G/ {, l' E7 o/ t; f2 w* G5 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
( C' e# r- X' O& N. PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 K" E; K0 F& }5 D( U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* A7 k7 E8 s+ ^# y1 g
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' g. R" d& Y X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, |8 X2 o4 E: N# l2 B' t7 L0 _McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) |: b5 ? o3 j# U4 V! S9 r& O' g+ f) ]" F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& P8 x7 F: n: F* aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! S& M+ Z$ s, N4 f$ `" f
0x00, 0xFF); /* configure the clock for transmitter */
; Y! Y( m+ N9 h5 |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& b& W% l4 X! d5 m8 o% F: M7 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * T. X$ {( M! ]$ i
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" p( |, i# v" s: M' ?- m& l& Q0x00, 0xFF);' \( a% T# {9 g+ a# H: p1 m
- i* o' y. J$ q
/* Enable synchronization of RX and TX sections */ 0 l& ^; m2 \( l( W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */! f6 j& y3 j! l3 N9 c
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, L8 i9 Z# s' F w
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 F% x# ]8 v" F. l, o+ U5 k/ W
** Set the serializers, Currently only one serializer is set as! ]* y1 S7 Q4 z
** transmitter and one serializer as receiver.
% u( C/ s' C$ L, P- ~9 h, ]6 p, _3 n*/9 Q8 D- h( Y! L$ y& S5 E
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. S7 A# ]9 m7 D6 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! D( m% c( K; P8 N; P** Configure the McASP pins
2 h4 I/ U1 }2 Q8 ?7 ]0 \** Input - Frame Sync, Clock and Serializer Rx; w- k! G; ]& Y7 q
** Output - Serializer Tx is connected to the input of the codec
5 I C$ y+ k3 N. S/ `! ?*/
1 {* [0 m& B1 u& e- k) aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; W5 C2 t7 c6 S9 j% C1 q% kMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 ]+ b* V$ p/ @" B5 L
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
x/ Q, h- M6 c C# H3 G( f| MCASP_PIN_ACLKX
$ [' x3 \/ v- R: r& N% i' D7 U' G| MCASP_PIN_AHCLKX
; Q# f/ I; d9 f H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 V5 O7 @! Z" E+ j) rMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: P, y. U/ V0 s0 r, f| MCASP_TX_CLKFAIL
/ [( K# n. t5 k* z| MCASP_TX_SYNCERROR
+ V! v1 E+ S5 W || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) c) X r" C, U3 K
| MCASP_RX_CLKFAIL$ r7 d9 l; B& ^# c d% Y
| MCASP_RX_SYNCERROR
0 e0 L! B) H$ Z/ i6 ? E| MCASP_RX_OVERRUN);+ Y+ j3 e9 v! Q `
} static void I2SDataTxRxActivate(void)0 K& N, E+ t( `% f9 u
{
. o9 y4 t' J( ` I( i/* Start the clocks */
, ^5 z, l$ A+ B3 t: B8 bMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 g- l* L1 i8 P$ T9 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */( b) m6 m8 H) V! H8 @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- w" K+ B: J- z! W: AEDMA3_TRIG_MODE_EVENT);/ x2 g% a( A- `4 @, X: }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ @8 c* u5 F C$ eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 V& D5 e. B x" X$ F7 S' YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 J* V1 D+ i8 P, ?3 A/ l" RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 d3 @+ U" ^4 a1 A0 Z$ j2 Vwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
% |9 @' F6 I1 G% B& ?: T0 PMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
2 F4 A9 \2 n) I. P# Z% C4 S' ^9 _# qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 f& E& @; R" W, P3 C( _} 5 W$ f+ t+ K: i G9 h& u
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / k) U0 v& @5 I6 L" O4 V/ q
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