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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 i& `- g, u! I6 rinput mcasp_ahclkx,
9 ?& U1 h. G! _- M) I; H. Oinput mcasp_aclkx,
@6 ?# i. L" @. kinput axr0,
5 P$ O/ E; j4 c2 f, e: L8 [2 y, @: w0 f3 }% Z C8 g- f4 |
output mcasp_afsr,
7 [8 \" J% h" b' i' A' m& \8 houtput mcasp_ahclkr,+ n f3 H* u% n0 f5 M
output mcasp_aclkr,; R4 P+ V; H1 D" M1 M$ o. u' X" t3 u
output axr1,3 y9 [1 w! y8 e/ C: e, Y* q' B
assign mcasp_afsr = mcasp_afsx;
4 C* X% P! m+ Q, L5 Yassign mcasp_aclkr = mcasp_aclkx;
* K- P: C1 c$ K' u, [0 w8 I9 \0 jassign mcasp_ahclkr = mcasp_ahclkx;& S& U0 m O2 B8 Q
assign axr1 = axr0; , M2 ]0 V7 u1 T, X$ O' S% l
1 A7 Y4 j2 Y* A
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 l: T" V. Z0 \) B% I6 pstatic void McASPI2SConfigure(void)% M6 M' b0 a/ k- E" u( G/ o6 W
{
" Q# N+ [! C4 P3 Y: G, KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. m. r) G! e+ W. i; p+ EMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* x+ n5 a9 X9 @: b8 zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 }+ f8 p% W( O; A% F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% s3 U( Z4 g, I8 B& I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 @, r0 a/ D8 v r& ~6 M
MCASP_RX_MODE_DMA);2 O% ~ O7 x* i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 u; m* Q' a: q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 e+ \% w+ Z( o9 H" H3 d- @$ g! NMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' J! }. u! I+ JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& M# n+ b& n9 sMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ V% f0 t* S/ R z. F$ G0 _) a3 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" x( P3 _( b2 m) \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ t* Z: C9 r% U, y* Q9 dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- I8 ?3 j$ b$ hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- O( l M m' Y) R) q' P( S" i0x00, 0xFF); /* configure the clock for transmitter */
2 H$ {4 U- [' u! N" i6 l$ jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! T/ u7 n" H6 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" F5 n/ x8 I4 e$ F7 IMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," a# j: L7 A! Y8 e0 S5 z
0x00, 0xFF);
. { H; l1 e' E: f* f4 }+ p. K- S# x% X" d
/* Enable synchronization of RX and TX sections */
f" ]0 A4 C# V& ]" w! t! q' NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( }0 ^: @4 x9 B' E4 E9 R |0 Q( YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: n2 O7 M2 L. _3 yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*, I7 t/ ^7 d, [. U4 `% D8 {. w
** Set the serializers, Currently only one serializer is set as5 `# b; s# S2 P( R, ]
** transmitter and one serializer as receiver.
( Q" e! }/ A. d) V- B*/+ X$ z' q# E- F5 O P
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);" a+ T- v# c! Y' N; K y, D
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# V0 w' s0 Q% Y9 x6 m** Configure the McASP pins + I* i: I7 d2 v( g2 M* Y7 c( p
** Input - Frame Sync, Clock and Serializer Rx
) C8 `# U: {5 W- s' D+ Y* h** Output - Serializer Tx is connected to the input of the codec
: f5 i7 l m( }2 a$ B0 s*/
0 c r* M8 N6 \) }4 F' `) CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 w" ^0 y4 R2 TMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- V6 r5 c7 Z$ N H9 H4 qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
3 N. h1 O7 L+ Q4 \! `( @( u3 K. b| MCASP_PIN_ACLKX
- L- u; p+ h, _- }& |2 F8 Z| MCASP_PIN_AHCLKX
1 l9 k6 O, ]& }0 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ y. j: s; d) j" i" Y' F. ~& C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & |- n& M9 v" D# x2 T7 @
| MCASP_TX_CLKFAIL
* W; B, \! H' p || MCASP_TX_SYNCERROR0 v$ o9 t' K+ T( p$ H
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 d! b, H2 F3 E& z| MCASP_RX_CLKFAIL
* w( [5 X2 k+ X0 p9 s$ s' y9 _| MCASP_RX_SYNCERROR
& E8 H5 h$ i3 Q& ]| MCASP_RX_OVERRUN);
6 r, [8 F @( L; E" Z2 T- D} static void I2SDataTxRxActivate(void)7 Q1 n0 s) G" K1 V6 D
{
/ s! E5 F) t( W* w4 y3 y/* Start the clocks */
! O% \1 n1 {+ @$ W$ b5 N c( c- }McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" f2 w. _. C2 \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: f4 \/ x D/ ~' S" W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
+ s5 e- n1 W5 v# W/ X7 ?) dEDMA3_TRIG_MODE_EVENT);) z4 t/ K( ~! l7 v2 b& ^& Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. T2 Y4 l1 }0 S8 SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
% N( Y' w( ]9 M/ C5 Z6 f& Q! c$ PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! i2 g# C; V# ^2 z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 |( p: N2 ~7 Y- t) @while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! P7 `$ p& |7 X- z9 fMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);% j1 m: t$ t/ e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 ^( Z: {. t3 k: j0 x$ |3 i: L}
5 d4 {8 C: \/ z+ W! _+ \6 P4 I请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 J. x1 e* }7 B3 ~+ Q) D
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