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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," u. ], n j- O' e+ A% a& ?6 E
input mcasp_ahclkx,
z+ ~$ U \2 U8 ~input mcasp_aclkx,
! G8 P" h" n6 Q& l; m- d: X: A: M6 ~input axr0,
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; ~( v. ^6 I' v* ~output mcasp_afsr,
( j" x. c0 g; U8 joutput mcasp_ahclkr,' P, ]& L; S/ x0 T
output mcasp_aclkr,2 I0 A5 p' C& u: G$ q! E) A
output axr1,
$ L5 n& n4 o$ p" s& h& k, L* {% i7 [, U3 d assign mcasp_afsr = mcasp_afsx;
5 `4 s; A( P& Y' ?5 T6 b* Eassign mcasp_aclkr = mcasp_aclkx;
/ W ~0 s, l! I( Gassign mcasp_ahclkr = mcasp_ahclkx;8 c9 X. f, ]- T4 h6 | s, I7 i) I
assign axr1 = axr0;
) F8 x% K% n# v0 `* {: ?9 K: L" k; P
( Y5 x& Y* @; W3 S9 ]% c4 K! z1 r在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ v8 C2 j4 ^: \8 ]5 Zstatic void McASPI2SConfigure(void)/ F& k7 t# ?$ u, j
{/ |' N D9 o& ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);5 _( W) l1 p$ {7 p' X. t" y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- P3 m/ y+ Y( S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) P- R6 x& h8 S( Z7 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# g# f: h) r, G9 y8 I. ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
3 G6 u: r/ Z& _% {9 Z' Z2 QMCASP_RX_MODE_DMA);% _5 ^) K1 a, k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: Q2 ~+ b6 N4 V& R. m: f7 W6 cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. w4 g; A, O6 C+ k. i) KMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! w) j" O! {) uMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);( z) C- f7 n) Z; B4 `3 B1 j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 q: W3 w: X6 Y$ D+ IMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 K% x. G2 Y* N& P B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* c' |7 E3 I0 F: m" u# NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" N+ W; [, q5 |: iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 n# v* D3 j: M( g w! i0x00, 0xFF); /* configure the clock for transmitter */
7 Y$ c: Q8 B- z; d! d( IMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# Z/ S2 {2 k( l8 I; Y9 L* b! }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 r* \9 I9 r( M7 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
, Y+ J+ G4 k9 I& Y0x00, 0xFF);
' X% V1 ]' x7 b( ~! V
' C4 s: h) @7 ]0 F7 ~+ a& R; A5 `$ ^/* Enable synchronization of RX and TX sections */ & P4 d% i2 m# A' V
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 l$ e- x" b$ h2 u7 j; T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ j1 Y. X, k+ t' I. yMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*2 y. P+ }8 V0 O' C/ `' t
** Set the serializers, Currently only one serializer is set as! i- V9 R! ?# ~6 ~$ u. J" k/ u
** transmitter and one serializer as receiver." D. K. b' j( _/ |/ d; ~ `
*/
% Y7 N4 B( j: iMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) N) e6 h; m+ L
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" l. t% z6 C6 d* I2 Q
** Configure the McASP pins 2 i/ I4 Z1 b ]
** Input - Frame Sync, Clock and Serializer Rx- F% h! {2 g! X
** Output - Serializer Tx is connected to the input of the codec 7 x$ C% r0 Q; V7 C! O% |% h- }
*/) r8 x; [8 {( a1 i' n6 z9 b# K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- j4 a# ?" e! I# tMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 h; M1 x% G5 U! \5 i3 ?
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 |6 A9 j" @1 L' J8 d5 W
| MCASP_PIN_ACLKX
) \1 b, { H7 W" {* R% Z8 T' N7 p* N| MCASP_PIN_AHCLKX- g$ d# h1 V: o6 P0 |" Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& K6 p" m' _- |$ `% eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 i( A. \) A' n) p| MCASP_TX_CLKFAIL
% [( x" N- B/ N| MCASP_TX_SYNCERROR9 z, X# Y1 h! ?, s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ Y+ h" @' B6 R- \" t% ]6 h" E! P| MCASP_RX_CLKFAIL
+ W! Z+ J+ n% F. b+ D| MCASP_RX_SYNCERROR % Q, q) e: U, B! F; e2 x
| MCASP_RX_OVERRUN);
, l$ f, U$ @+ {} static void I2SDataTxRxActivate(void). p- `" y3 o; g. a+ V7 [
{- f+ g: m1 o# v0 V' O( \$ W
/* Start the clocks */4 K+ j* @! P7 @, S, V2 d6 u: x/ s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% _0 A. ]' }! N6 J3 T* }
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ }; U4 w# q0 a6 c) g4 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
5 M$ N3 `9 x+ s& E# h2 GEDMA3_TRIG_MODE_EVENT);
3 L4 C6 |, s6 g+ o+ b7 U5 MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% N- M X7 W7 K) H) n' M1 g* }' KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( H5 Z7 W( ~: |' qMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( _, c4 O# V, U# H, l* j" |5 O6 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */9 N. x! U, l' s' y) r7 V
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 O0 n. g9 @8 U$ }% G1 j2 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* K* t7 {) _" V% V* o9 T y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* f$ y4 R% n/ ~+ U- z4 |}
1 q, [3 Q+ ~8 b a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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