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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 \) g% R$ g9 F# pinput mcasp_ahclkx,
' f# u4 h6 X8 p* Ainput mcasp_aclkx,- z& o8 a! L7 R, a2 k- y4 [
input axr0,- B5 \6 Y5 n. w" t9 Q2 u
L6 o( t+ H, k! t( {output mcasp_afsr,0 g; O! n/ I4 v6 J
output mcasp_ahclkr,
8 z$ w( v A$ H: p% d9 youtput mcasp_aclkr,% |+ d; @+ C5 ^/ V
output axr1,, Q H. H/ A# H; X
assign mcasp_afsr = mcasp_afsx;8 N4 o1 d- I/ i7 t) U$ a
assign mcasp_aclkr = mcasp_aclkx;
i( @3 v; c8 N5 e; U- V: y2 cassign mcasp_ahclkr = mcasp_ahclkx;1 B# E0 J3 V/ `
assign axr1 = axr0;
6 X. Z) ~$ _8 k) I u4 c$ b2 |0 |$ p- M3 u/ R7 w/ K& ^0 ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 D# U0 w' D7 O# I. @static void McASPI2SConfigure(void)
- m% V0 p p# _$ F{
$ N+ x4 L+ o, L* s( d6 L- N9 AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 `4 K i5 |$ m; S
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
) j! c' Z6 ?7 hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ V2 \) }& v; r: R, K4 y' n1 cMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& R0 a. w, _- s, e }) I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! F7 k( b0 Y) ^7 q8 b( sMCASP_RX_MODE_DMA);' z# n8 B A' ?$ X. U+ D
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ d. J$ U, `8 ^
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ g$ C9 S& Y* b4 [! V# Q$ D4 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 H; A0 b; g: y+ _1 R5 XMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 x4 }! _) f8 j: W8 e2 z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 N: f/ ]0 H) r; oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 {$ R% m' F/ }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, {. b1 g0 L7 X. `; pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + c6 Y/ ]8 n; ~+ l. m \1 L& v) U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: @- ]5 Q" }! v0 W6 o0x00, 0xFF); /* configure the clock for transmitter */- D: @" J+ N1 Y4 [
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: M1 C; q; e! T7 w$ E; q: F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 2 [2 F$ l _9 j9 s, G5 B8 D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 g9 ~0 @; C% @9 j
0x00, 0xFF);
1 z& E$ C$ u" u: B3 N1 \, D* l$ ^5 A& f. Z
/* Enable synchronization of RX and TX sections */
' n, k: X! O p5 r) ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 T" H" F8 \7 t! x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! n4 H2 B7 c! M; Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: o0 E- Y& w7 x$ m** Set the serializers, Currently only one serializer is set as
7 I# l$ z) ]9 a2 |- J6 ~6 h7 W** transmitter and one serializer as receiver.) S4 f" [& s$ t% `! i' H
*/
* N N" L1 H5 S; e( i$ l2 z7 j, eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" I, o8 O7 ~; }7 H( t) y, jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 w0 z) o9 H, h2 F5 P* I5 l' i
** Configure the McASP pins : R( \+ [* J, M5 y
** Input - Frame Sync, Clock and Serializer Rx
% R7 M) {% @4 o7 ?+ `5 P7 o% d' U** Output - Serializer Tx is connected to the input of the codec % _, E; t9 N4 E/ l/ r
*/
( P k; d$ M s {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 O y# g" d. F) _/ K$ @' v- U; C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' f" e/ W' {7 N4 w' X* Y7 k1 X/ IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ Z4 o+ h' A0 o8 v1 s
| MCASP_PIN_ACLKX
# {5 N: v" J* _4 o: t3 P$ Z| MCASP_PIN_AHCLKX
0 R( \ a7 z6 o W6 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- h8 e+ ]7 |- T0 M" @) n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! Q* ^& ~2 j J4 e, f/ B. Y| MCASP_TX_CLKFAIL
& \ Q# z; n: o| MCASP_TX_SYNCERROR
2 c' B/ Y( N5 f5 S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 9 A$ T. ~/ }3 l4 V! Y7 I1 `3 ]
| MCASP_RX_CLKFAIL3 r q6 p0 g" J9 [: v' S
| MCASP_RX_SYNCERROR
' p; T8 R. n) h! m: U7 _, n| MCASP_RX_OVERRUN);
7 E x" S _4 v5 j! F; y} static void I2SDataTxRxActivate(void)! a, e. L7 {+ k/ d9 U0 [
{
6 k# P: Q( p4 l# k! w* F9 D/* Start the clocks */- @2 k, n4 z1 }4 D$ f
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. Y: n# ^& K. p; Q& O& o7 t# u3 pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ W! y& F; ^. p1 n5 X ?( oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ @" `0 ] Z2 |& SEDMA3_TRIG_MODE_EVENT);+ x# X9 _# M- Z6 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 k! r7 v( T( X/ F0 x. A7 V
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; t+ I& Y5 u8 l+ |" j
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 j6 r3 D( J% h$ C; T, E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 `8 @9 g" }9 @1 J. \/ y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 l# J7 U5 o. G5 q Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; A! W: Q8 a/ X7 d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ I: G. g! x6 I. P" I- L
}
$ u+ }3 h! q2 _0 Z" `8 b- p! S4 ]请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
5 ~* v+ f) j7 W |