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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, j9 P: g2 H0 ~) \, U
input mcasp_ahclkx,' @6 Z) ^( E( h: ~$ @; f8 k
input mcasp_aclkx,. p! k) S0 b" c. b
input axr0,
# T; n3 e, C! {, A5 E! p
9 J9 L9 C/ X& C. T; ^output mcasp_afsr,
+ C+ ?+ p' J: D$ x1 }output mcasp_ahclkr,% M0 @6 [( A/ A
output mcasp_aclkr,
; p4 K% _0 V1 c' h& Boutput axr1,
6 R: S1 ~0 A; W+ D assign mcasp_afsr = mcasp_afsx;
8 p) x$ f4 H/ r. O" T8 y7 _7 Jassign mcasp_aclkr = mcasp_aclkx;+ a8 e: D6 e, f V \
assign mcasp_ahclkr = mcasp_ahclkx;
' w, ~: E6 A" `; Z2 q% ]7 X/ a% Z% X; lassign axr1 = axr0; 9 w8 W/ L4 M, {& F, Y5 A
5 j; o# m8 N: E( X. K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 f" l: ] c8 z. Z4 G3 X1 H" ~* B
static void McASPI2SConfigure(void)
( O- M. M4 N! w{
$ Z8 B/ s; ?3 N' V6 ?2 @+ u1 L" SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
E3 r4 @, y* F6 X4 l8 [McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 J8 j- F% N: x9 r
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 N+ d6 m% d, g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 R2 n, d- ^1 ?4 w" nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# d- a5 l# {4 f, F ^% J! Z. w
MCASP_RX_MODE_DMA);/ e! b; r3 E; J, M: N0 ]6 {) ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 ]; {# n9 D1 A! X0 _, C5 CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 q: v$ f( n0 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ; v8 ~4 z7 B7 b; @8 ]& l2 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 p& i& P& Q/ N$ b) e p. A8 f+ R; v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 1 }/ z3 F6 K, x' F; O k! t: q
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" w. h w3 t) R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); C1 F; M* p8 n1 f8 b/ _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 m! G. t* l8 D: YMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ i7 Y8 @4 t6 R- ~4 I* U- C0x00, 0xFF); /* configure the clock for transmitter */
) S; @% J$ n$ ~% g" J, HMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ }$ i: M* {( XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # N5 I: \( W- ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* I% {8 n F% Y" [. I7 F6 @0x00, 0xFF);
r, `! i6 w3 m( n) X1 D3 |
. Z' ~$ Y; {" ?* R6 p% z& X/* Enable synchronization of RX and TX sections */
# u1 |0 O2 Y5 G9 |4 mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; I+ Y! Y7 [' T1 ]5 I' P4 @
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 D9 N7 e; g3 b; ?1 r
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 `5 E* e& T1 l8 k* Y, d! d
** Set the serializers, Currently only one serializer is set as( c0 d* A# I/ w4 a% E" y
** transmitter and one serializer as receiver.9 m( y/ C! ^2 X- Q# W3 b
*/
) _: s9 q w+ G/ u _$ [* mMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 p* f( r# x- VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, {# K) a" U- S! w** Configure the McASP pins G1 n/ p$ h4 `
** Input - Frame Sync, Clock and Serializer Rx
+ @5 K$ {! }8 h- E0 M$ O# b! h( U** Output - Serializer Tx is connected to the input of the codec . {! R4 z1 T+ J7 I& B
*/5 w! Y0 t6 G1 D3 Z4 z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! S. B& Z( H7 R5 y: `McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));# v% w3 M% \5 E: h. M; l) F
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! G: ~) g, |6 W; |
| MCASP_PIN_ACLKX
6 d. ^3 K2 ]; c4 @ `0 R| MCASP_PIN_AHCLKX
5 Y/ E9 G1 \$ w' n4 C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" Q- q( C8 Z! o7 @! ~8 D/ @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 I1 b5 W0 _) J0 `+ ]6 w& L| MCASP_TX_CLKFAIL
5 `/ P8 f$ N* w7 S) i2 D| MCASP_TX_SYNCERROR
+ Q7 `1 ?6 ?3 S! ~3 r. [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 ]! |) M) z9 k B0 m" a: T| MCASP_RX_CLKFAIL
- A1 ~' w0 J0 b! @| MCASP_RX_SYNCERROR 6 P- {% v9 B7 s( c
| MCASP_RX_OVERRUN);
& T" e, Y Z$ \} static void I2SDataTxRxActivate(void)
* m# M) D8 i" Q8 o1 O0 g4 I{, m5 r& w; ~: `4 j! M' Y: l
/* Start the clocks */
& N; G6 D4 O. N; A% QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- Z) R, A4 \8 a1 O Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
s! |( V% Z1 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 p! c" L. ?3 l' C* B3 bEDMA3_TRIG_MODE_EVENT);0 x) K( h# I8 c5 W
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' X( ?1 U2 u& eEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! q8 _; r# {, U* h! Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);+ i5 J, b/ Y8 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
5 J$ U {% L$ r6 w ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
. I9 F ]9 |! D" H/ NMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% b% e# R2 _" k/ r BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 P1 [: }, a$ ?; k/ ^} 4 U! A' D8 ? _4 r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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