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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 Z# ]! V2 J0 G: N8 Ainput mcasp_ahclkx,& N& d! q) J- ^& Y# u
input mcasp_aclkx,8 B! H# K; W! Y8 c; Q$ i
input axr0,
" S F# b/ J! s8 ^- m8 p( g4 \4 y0 ]
output mcasp_afsr,
6 o5 H! f1 u& [# C2 v# @output mcasp_ahclkr,) T& h. X4 b5 y4 N
output mcasp_aclkr," ^) `. W" I. m6 R6 @& \; }
output axr1,) Z" X: c: {5 Y& c
assign mcasp_afsr = mcasp_afsx;
- p9 e% E, X& Y8 B* @0 e$ M/ Y& v3 Iassign mcasp_aclkr = mcasp_aclkx;
" ]3 v( L- }7 J% { hassign mcasp_ahclkr = mcasp_ahclkx;
3 F7 o! V* \; B+ ^assign axr1 = axr0; $ Z }/ N3 v1 A1 `
8 m' o* e1 u- x. x! I在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 6 s; R. F! r9 F7 E
static void McASPI2SConfigure(void)3 R& K5 ]* X# Z6 {5 @1 n! n
{" S+ r4 Q" e6 {+ P. z! @1 V& b2 i2 J
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" a% ]* {, `3 X6 f6 f! n! b8 H
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 D5 M4 r9 P! u6 D% cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ]$ v$ l2 s) @4 B& P }2 {. w; F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ I' X" C3 s9 d: G, x$ |9 Z3 TMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' {3 @' p/ V3 ]" jMCASP_RX_MODE_DMA);' [# a+ A! e' k/ h! M, P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( ]0 ]) ]1 h! M9 m
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 j S+ S; z, N+ h# k, b( X3 pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 K" `3 _- n1 T) @MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; G' [4 j% B! \* Z
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 O3 L" `/ h$ B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 D' i0 h; k5 S) k! |9 b1 }: l# G
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 W. D( \- H% w; b/ x' O' e% @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # Q, a( `, E% j, }0 w: t( L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,! v3 u# Y, e. ~$ l
0x00, 0xFF); /* configure the clock for transmitter */
5 t, e, S" i) A: `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ t7 `4 \0 Z0 J, q
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 j# t0 S! k6 q4 B1 j5 MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 [3 ^6 v9 N% u4 P0x00, 0xFF);
$ n% \ k: d9 [* B7 E
P' ?$ p) H& [/* Enable synchronization of RX and TX sections */ ! d' M& q: A$ |# X2 o8 n
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 a. G t. [& B& Q6 V" `3 HMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 q8 L# u% U, B9 j0 FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 s. R( C+ d0 \5 U \
** Set the serializers, Currently only one serializer is set as9 X O1 B2 J- y3 @% m n
** transmitter and one serializer as receiver.
% u6 o6 b7 u5 k( W; t5 y: F*/ @9 @3 T: H! N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 b1 U( ?" g, E. E& e1 m7 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 `% ~/ i! V' i7 }$ q1 B
** Configure the McASP pins
* @5 \* S& X1 r* w) n! |** Input - Frame Sync, Clock and Serializer Rx! g8 n5 _: ^0 i7 f6 O
** Output - Serializer Tx is connected to the input of the codec
" g2 [/ l7 U! G- {1 g*/
; a5 E$ ?2 X" _: `" dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 T9 K, g N" c+ W" p2 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
x4 C2 {( a) M9 n3 d9 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) D7 Q( Q+ b4 ~* B| MCASP_PIN_ACLKX; D* X, w* q" K- ~( O- _
| MCASP_PIN_AHCLKX, }; t; F: V- {/ g
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 ^# q% S% ]5 K/ tMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * y: P# d) \3 Z2 n. m6 O1 ~5 s
| MCASP_TX_CLKFAIL : N9 H" m6 S6 z
| MCASP_TX_SYNCERROR% Y" b$ T8 s+ x2 x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( s3 s' ?1 f8 X8 F
| MCASP_RX_CLKFAIL j. ^$ `+ l$ u3 @ K
| MCASP_RX_SYNCERROR
, a' [& j) L. C| MCASP_RX_OVERRUN);. i6 b- [' D) V3 @' S9 ]6 E6 x* v0 i
} static void I2SDataTxRxActivate(void)
( W2 }" n+ y" \$ h& I& E{
, \2 G: h' d, e, v. |/* Start the clocks */
# u* v5 m V* D; | t g* S+ M" k/ TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
$ ]9 S" f' R' Q+ i" e8 B; nMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// Z, r, N3 c9 g& ?9 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ X$ u5 e0 u4 ?: ?EDMA3_TRIG_MODE_EVENT); P: X& K. T' J& o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % M, M! b9 w3 }! M0 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) X8 H1 A3 Y* t: {+ }' L
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: D5 j5 T& n9 t5 d' i, l% n' P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 x& O' ?6 N1 Q% E/ @
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. @7 r0 c( X8 ~0 J9 t7 s7 Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 r ^! J% @+ w# {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 u2 M* A* ] H0 j$ w
}
; `/ w& E7 M! c* w9 S# M. t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 ]1 ?% B: z( B6 R' X" ^& f
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