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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 A, @5 R. @; ~% winput mcasp_ahclkx,
6 t% U( ^# j5 {3 R& n( g. Hinput mcasp_aclkx,) @& G4 I" P+ y# k% I
input axr0,
$ x) r6 ]1 z. Q3 y
! {* y# s2 G. \8 f. A+ @' M7 m) i* Noutput mcasp_afsr,( l+ e0 Y* g; W/ f6 s
output mcasp_ahclkr,% T7 P1 z3 h' J6 v8 [& Q: @
output mcasp_aclkr,
7 a8 \6 y s$ N/ Noutput axr1,% f& D# g7 j g% Y2 o7 w3 k' t5 y
assign mcasp_afsr = mcasp_afsx;
% ?, {( |3 W% e) R$ x6 z' Xassign mcasp_aclkr = mcasp_aclkx;
, n, m* y8 E7 O( Z/ Cassign mcasp_ahclkr = mcasp_ahclkx;
3 B z. p9 n4 Cassign axr1 = axr0;
/ Y' e# u" Q* q; K( a
+ ?' Q# g/ y. D. E+ P. x1 k在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: P6 L' F0 z: }& o, q8 tstatic void McASPI2SConfigure(void)% I+ a" ~# I& L
{
. Q' e: f5 T& \8 x2 DMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 N2 i7 d9 u1 i! ?1 @# uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. s7 e& s) L& g% w
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 h9 J9 e. B5 H" S* ?3 aMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" z! s6 w0 u& z, b+ Y: ~: X7 T
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 Z" h: |8 N. g' KMCASP_RX_MODE_DMA);$ H- F; t6 T0 Q& [9 n$ p# w) J
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 f7 J+ V2 n8 j: U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 A2 C9 [0 l( ~McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 q4 c. r" `3 i7 j- |2 i+ r6 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 B- J" a- b; n. O2 n7 m1 N/ LMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
8 z# {" n1 z# ?1 KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, w0 ~1 A, T7 {) P! A! W; ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 d# E$ a5 Y; `7 ~9 a1 E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + a* A8 u. j7 }+ {. Y1 b0 J9 q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 Q6 a8 h3 T' I- Q4 o1 ?0x00, 0xFF); /* configure the clock for transmitter */
5 ^4 c; @+ D- x& f( _* _! _: JMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); v S g* M( {$ c7 F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) }' ^2 P9 i6 y+ P4 k& J9 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& l4 ]0 V! p+ r0x00, 0xFF);, E1 P6 o) _: P3 r8 f! B: g
0 j" T! z2 H7 {: [" i' F/* Enable synchronization of RX and TX sections */ / h W2 d, R7 T; K& \1 ~4 u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ [) y2 Y; r+ U9 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& T6 \2 m, f {( \7 b% ^; QMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 f$ H1 P. K9 |! u: f7 }: @** Set the serializers, Currently only one serializer is set as
2 m! |! v8 U; C" O, t** transmitter and one serializer as receiver.$ M8 ]* j7 c1 l1 ^+ I
*/: U$ C b8 C6 c& ^- L1 g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);( A1 \8 ]2 n, r6 D5 K5 Q% x: C) D" V9 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: ]) S* Q! S. L" a( w2 [, X** Configure the McASP pins # b- F8 V, G' z5 w( t- h
** Input - Frame Sync, Clock and Serializer Rx* M; W; e4 y+ p
** Output - Serializer Tx is connected to the input of the codec
' m5 K) I- q: n" J% N*/$ x, s0 F% D/ }5 z1 h
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; R4 ` x; T7 @" G$ G: q ` EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; {% A1 E7 @, K& m# w! R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
{+ ?9 e9 V, W5 p; B3 k& ?| MCASP_PIN_ACLKX
8 T3 o. r' u, B$ ~8 G. q0 i8 D: f| MCASP_PIN_AHCLKX
) y1 Q3 P0 p- p6 a' N| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. L2 K0 I8 w1 _- F6 S- ?. l6 RMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 {: ^! k! ^* y5 k% Z| MCASP_TX_CLKFAIL 5 o# C% M# T2 ^: e! u% J
| MCASP_TX_SYNCERROR
# o9 {1 r, b7 o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, O# x. g4 o& l+ m9 [( _& p/ Q| MCASP_RX_CLKFAIL
) o! u2 m1 Z- D) s0 G b- Y| MCASP_RX_SYNCERROR
0 B9 {# A" |" [/ V5 x5 }6 f9 d# R2 c| MCASP_RX_OVERRUN);+ J0 e) a+ { |6 u4 T
} static void I2SDataTxRxActivate(void)5 r7 Z; I: M3 g
{" ?/ _6 C2 b" Q8 u
/* Start the clocks */2 Z* p9 O3 x" T+ ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ j. O I( N+ U+ G6 L1 Q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
7 |4 y) ~- y& W% d8 F: bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 e" y# r) R: dEDMA3_TRIG_MODE_EVENT);
6 H T! E% d) Q) UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
; L) p1 l& a3 S+ o" lEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. F" o' s1 A9 F- B2 v5 T( {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# ?9 k$ ^2 ?+ R- V; s- ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */( C% ^8 B a! ]3 Z, V+ q
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ G6 c- B% B6 E: s& M
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. Q2 {: E0 g* W8 K0 q& W7 h* OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) q! r O' Q) z9 n3 [
} ! M, d# E$ d1 k
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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