MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
3 e, ?7 e4 ^% Cinput mcasp_ahclkx,
1 Z8 E; P' h  n$ w  \/ z' ginput mcasp_aclkx,
8 M; B+ ?+ I# X+ sinput axr0,
8 B% n+ D* c" Q: c+ G) b. c0 Z
output mcasp_afsr,
$ F" F% b% i5 e! u0 x3 z3 Joutput mcasp_ahclkr,
  E3 _7 m: ^1 t' [4 L: T  t6 toutput mcasp_aclkr,
" H6 T4 }, c3 r9 F( n3 g8 Boutput axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
assign axr1 = axr0;

/ s' j- P0 A- w2 }8 B8 r7 j6 B* j! ]

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

0 a" L0 k2 k' Z

static void McASPI2SConfigure(void)
" A0 X+ ]. m. `{
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ S! }) r- i, A2 u  CMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 `/ [& d5 G) r9 ?: t# m  JMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
! m' [4 V# l  P# c5 ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" E" }0 m  L/ R/ h4 n) YMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 |. J2 V0 y. e  M9 o: G) ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
6 U. V7 y, E2 l' nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 v# L; `( W' S/ z1 pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
; w  B4 l, }8 [, K9 N0x00, 0xFF);

/* configure the clock for transmitter */
- \* ~* K' h1 r. u: XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
# B4 N* e: u7 M9 s: Z% r
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
- }6 ]; e+ d* Y; LMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
+ |: H* T- d' s) @; e** Set the serializers, Currently only one serializer is set as
  N$ U+ c, o) V7 L** transmitter and one serializer as receiver.
*/
- I; v: T  N! t5 g- e9 w" C4 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
; @# k0 D' w+ E** Configure the McASP pins
: y8 @9 j8 `% A** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ q: X( a' Z" O* k* U' F7 hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ C, z- d* @* x+ s0 r. C) `' \% x+ C| MCASP_PIN_ACLKX
/ S) h3 ]8 r. Z- Q3 u| MCASP_PIN_AHCLKX
0 z& |% T* B- C* I, m: x0 k8 _| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% c6 b  |/ d3 Y- G. t8 E" A7 D| MCASP_TX_CLKFAIL
8 a  B( m0 S( d/ G| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" |9 L. B* c3 _| MCASP_RX_CLKFAIL
| MCASP_RX_SYNCERROR
| MCASP_RX_OVERRUN);
9 [  o# E3 j* j# c5 M6 I" u}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 g. Z# D4 b, S5 W0 q& u' x4 w, EMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 |: Y% h2 s! D0 QEDMA3_TRIG_MODE_EVENT);
- H4 |+ A: w! F8 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
, |( o3 [& U8 D+ k" EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
3 o# k" P1 O% Y: ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
3 Y& \* ?' y: c5 T- E6 V8 SMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 j0 E1 V* Z3 {) i8 H) WMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

- m! i' G1 R( J3 {; C. ^% T# L

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

  f0 g8 P" n2 g1 x$ p! j