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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ d- z, x/ b7 T0 Oinput mcasp_ahclkx,
5 i, n' l7 |, ~7 p# E, B1 \input mcasp_aclkx,0 L: }8 w* }+ E5 C, j' I+ t3 S; V
input axr0,
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# X: x+ f x# S, e! A+ |$ X5 boutput mcasp_afsr,
* w( _+ F2 x# R$ `% f( H! c+ S7 koutput mcasp_ahclkr,* E( ?- L# s4 H7 ]+ w% N
output mcasp_aclkr,. y1 A ?5 r0 `/ D8 z
output axr1,- c( G2 I3 L! G( ~& d
assign mcasp_afsr = mcasp_afsx;5 b& v8 k" Q2 U; U
assign mcasp_aclkr = mcasp_aclkx;
t% Q3 _4 i) P2 J4 eassign mcasp_ahclkr = mcasp_ahclkx;3 F% w o0 x# O. B4 G
assign axr1 = axr0; 2 S# Z$ p! L, F: U! l
0 G! G3 c9 J0 K1 H9 o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ! B, w) S# w4 R8 n! G, E7 J
static void McASPI2SConfigure(void)
. p3 ^$ y2 c( n C% S7 K! ?7 K{
& H- J% e& h# o; K. W) dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);7 K9 u' G/ ^, [9 Y) \" O
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 {+ I) s7 [3 y/ _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);" r0 H8 d3 A9 j# e# C" g6 g
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" J% J$ W0 {: k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 }" H. i0 c/ n: h- _. X
MCASP_RX_MODE_DMA);4 W7 B( U2 e$ E$ f, L
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
m- L. ^- W( W+ ]7 Y1 Y' _, `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
# r6 ^2 \( ^1 K$ ]McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 `2 O' w" m; g2 M3 B" c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; O# s7 O3 {7 r- J' o" \McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; V( L$ E4 j0 ?: d. hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ B% M! X! h7 [) A o8 I, A; gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);0 e" L0 H" Q. D$ j, H/ {$ t* n, S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ z. [2 c6 E) L) Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 P6 O3 v5 r- d1 ]" n! Q8 T+ |
0x00, 0xFF); /* configure the clock for transmitter */
5 e( W) }+ O6 y" [& A: wMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, j2 M% n$ f5 C5 |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 x s" h9 G, S$ P- M" {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- l: h4 Q' v# Q/ E! v0x00, 0xFF);+ h% Z) v# }* F9 F9 a o
' Y7 {" w% T1 f, Y: {+ j( P/* Enable synchronization of RX and TX sections */
0 \0 J/ G1 U7 oMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */4 a/ z. R. K# ]8 C6 L9 y7 I* m+ F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 C. m1 O1 V2 x/ a. e. l9 t4 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*9 Z! f6 m3 A# z5 }& J
** Set the serializers, Currently only one serializer is set as
( ~. M5 k& S, e0 q% q( g** transmitter and one serializer as receiver.6 y2 B! @3 Z5 `% i
*/5 ~: S) g6 Q* h' f' n x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
5 n( J2 p( o0 k. u* N1 w4 I0 d& NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 R. R8 T7 W" m. w) ^$ ?
** Configure the McASP pins
& X7 |! X$ m' I5 r0 d3 c** Input - Frame Sync, Clock and Serializer Rx) t, K# w5 d2 L9 W. R3 p/ m
** Output - Serializer Tx is connected to the input of the codec ( U2 D0 }+ q( u s- c6 T& b0 E
*/* y Z4 H" F% t' H/ j' S4 P: G, C
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) w" v$ v3 a; f! Y/ U5 q4 R0 b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));) n$ _5 n$ R7 E# j
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; ^( U2 J& U: U5 ~1 L/ y
| MCASP_PIN_ACLKX, D2 z( Y! Q, ~: |
| MCASP_PIN_AHCLKX! x, ~; @% X, n2 O
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// Y; V( [& \* w% J2 A0 X0 s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ a p0 H+ j$ d6 P V| MCASP_TX_CLKFAIL
# M/ Z) f0 G9 z X: s| MCASP_TX_SYNCERROR
" Y2 Y3 h: G9 P: B| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: {; ?4 x( Q7 W/ H( M, k6 X! F| MCASP_RX_CLKFAIL
0 s' l6 J1 f4 v* e| MCASP_RX_SYNCERROR
1 P; k2 A/ b5 Z4 P5 A- [1 O! ^| MCASP_RX_OVERRUN);, d _1 I: R- I' M
} static void I2SDataTxRxActivate(void)
j! h* M- |0 Q* G) K6 H7 j t0 F0 L' Y{/ {# e2 K! I( s/ a, x9 _
/* Start the clocks */2 j3 b# l" v' U1 `
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( A3 o% q& A- K: E( e9 {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- K+ [/ k' u7 R: b! }1 ?; e3 {* d& jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 w! u e0 @; A" J2 A$ U8 o3 J5 zEDMA3_TRIG_MODE_EVENT);
3 b2 p$ x& n3 J' v/ `. B( a# G: OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- T% M" z9 o1 s8 {8 D Z8 Q/ SEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */) {+ [5 c/ C% B$ i& Q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS); h+ e- y7 Y1 }
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
k: S% a$ j% {while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */: i2 L& N6 g! i; Y
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 t2 l( ?. W7 K+ {3 w& H& S! C4 I
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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k+ z/ d9 z" }, N$ T. I5 `- m请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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