MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
input axr0,
( Q* X5 X% H  M6 m
' T, b8 G. X* \6 E; X8 S* @output mcasp_afsr,
6 A" r3 U' F1 e! l1 }output mcasp_ahclkr,
output mcasp_aclkr,
5 O: a3 n8 M& `& E+ ooutput axr1,
) M7 s0 B4 X3 n6 ]

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
! _$ Q: z# W- Z7 u9 X! g2 massign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
9 d8 _/ c& P' T3 o8 Z{
, m$ S: x& w2 `6 ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 U% |# E% W" c; `" a: \, ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
  J, @% N3 I5 P( y: s: j+ r  PMCASP_RX_MODE_DMA);
' ?7 f6 @! ~% K" Z. \* _McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; T3 p, `- O" e" F* D5 ZMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& V1 s7 w+ y6 j1 m% C5 U2 @3 EMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
. v, Q7 r2 `3 U; ?( e) {9 _% xMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" P0 G6 q. ^$ `& ~/ D2 W0 NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# M5 V0 V. j6 c% AMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ {( Y: _. A& ~5 A0x00, 0xFF);
3 E5 j8 E9 Y  Q, j
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
( ]) Y  J: Y, y/ g, f/ b*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
8 I% c. \) u' A4 v" l9 Y** Configure the McASP pins
** Input - Frame Sync, Clock and Serializer Rx
& g$ j  w  J4 n( l9 f9 C& S** Output - Serializer Tx is connected to the input of the codec
" J3 g7 Y; u* u' a+ b*/
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
/ g" J" k+ }  W% ]; C| MCASP_PIN_ACLKX
( g! U2 |: S" O  U8 s| MCASP_PIN_AHCLKX
3 \0 L# V' W% H3 n4 j| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
! X4 }& \. }% eMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
- o# d) {2 B# [) `! f8 j$ s" }; B| MCASP_RX_SYNCERROR
5 v  ~0 H+ Y$ w; J. F, \0 v% p| MCASP_RX_OVERRUN);
: s- C4 g2 n. L+ b3 _' S! P}

static void I2SDataTxRxActivate(void)
; ~) N" N) y  V. p& V{
1 X, N3 x0 Z5 d& o3 Y! X# s/* Start the clocks */
1 U4 w3 s2 R9 m# B' e. r. F4 Z% b" ]6 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( o9 \- w0 v" gMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
& z9 V" R; z; _EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 f1 |1 X: l  U1 y- _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
2 f8 M. M: P8 m$ ^! y! v" YMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 ~/ ^* f& f" @* Y) J$ }" {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
& e) u$ R( n4 F& Swhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& j# r1 l% j4 A! y$ oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

- I5 p( r- n5 W1 _# K+ v# w