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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 L$ @: p( m$ ?6 a
input mcasp_ahclkx,0 S; s8 B/ J0 e i8 X' \
input mcasp_aclkx,1 I* q$ Z) x3 Y
input axr0,
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output mcasp_afsr,6 n: o6 {3 k( L" h. w) U" P1 ^
output mcasp_ahclkr,
2 c. e) B( x' t3 a. soutput mcasp_aclkr,
! t- R0 T6 v0 h6 I, k' Goutput axr1,; f/ J! @0 O4 T
assign mcasp_afsr = mcasp_afsx;) {4 H$ l9 D" `0 P( |3 N
assign mcasp_aclkr = mcasp_aclkx;) H/ X# T4 G; ~4 {4 A
assign mcasp_ahclkr = mcasp_ahclkx;# L- G/ x' W- u* P! j% w( B Q/ U
assign axr1 = axr0; ' I& D6 W9 M, s3 f- }
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( |9 q! V0 n& o# J, s. ^5 r
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 C [1 W1 G9 ^+ |, Q7 n9 V& d
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */" ~6 p7 B; |9 z$ e% Z! L
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; u) I/ }0 `+ r& }$ y7 j
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
[9 d, E& N8 K* J" J" u" ~McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# T/ b. R" w1 mMCASP_RX_MODE_DMA);
. I% I0 V* z" w# `/ p+ A, ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! F z4 n1 j% h b; V" u9 TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ E" \" f, b6 @8 {: U" F" [+ b5 ~4 P
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# e( v6 T1 \3 o7 cMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ W7 ~* p9 x9 v1 ~ H& RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
1 [3 N1 q& X) y/ u, R2 f. @# TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 O: Z+ e* F$ F p. A+ cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ @# D' [% p" S+ eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) X$ d3 O& V( A6 E3 w
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 e M3 d9 [9 \/ |: }+ s0x00, 0xFF); /* configure the clock for transmitter */7 l8 z9 [1 ]8 p; L& }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# c) j: Q { Z9 ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & l7 s5 r1 T% x6 P% a' d2 X
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 d- ]% y; j8 a d: {, f# y8 A$ i
0x00, 0xFF);2 @5 C* u# u3 r8 T
2 K$ w5 \8 | a; A: d/* Enable synchronization of RX and TX sections */ , x, K8 ?. L% g0 n- D3 `7 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' S0 y+ [* {" P; ]6 Y
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, n8 ]' B4 h; ?: g' N/ rMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 F* z% n/ W- ^& X# ~** Set the serializers, Currently only one serializer is set as5 g' y* E+ n$ |; W& |
** transmitter and one serializer as receiver./ l+ Y9 @0 @' ^ f. k9 X
*/
+ ?' Y1 W5 m8 x! lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; K5 t, p' H9 \- }+ h1 U
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 r; ~2 r4 y$ C1 ]% U- H** Configure the McASP pins ( A, @9 B) c8 k& G& M4 A" V
** Input - Frame Sync, Clock and Serializer Rx
1 K N0 C: ^' W1 s- E/ ?** Output - Serializer Tx is connected to the input of the codec
: s7 p R" n3 t! t9 `: `$ d3 [; Q*/) [! c m& N. d5 ^8 ]- G+ n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! Z8 d$ u7 z2 T' F9 w- L/ c2 R# N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ d5 W m8 Q6 _* V9 e
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 R/ k( F& A$ X! L8 T& O| MCASP_PIN_ACLKX5 I: d, Z% d2 ]2 h. R! Q
| MCASP_PIN_AHCLKX, }3 R& F7 T' f& ~: p
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# t6 E8 Q1 U% d% C9 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : q. l6 q1 S4 r+ [8 ?
| MCASP_TX_CLKFAIL : b, @6 n6 u$ \1 {2 J- k
| MCASP_TX_SYNCERROR8 V# I! i4 ` J0 ? N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
2 h8 ~* R- E" }1 i1 z8 V| MCASP_RX_CLKFAIL
- v% V: m! D( |( V1 p6 q| MCASP_RX_SYNCERROR
1 s2 q: t; z$ B) p+ c/ r3 L| MCASP_RX_OVERRUN);
! ^( _. J4 \& l' g8 a" ?: k} static void I2SDataTxRxActivate(void)' v; P1 E: Z( ^" h% [) q) I" J- Y- O( k
{
* C% ~# L- G N* h/* Start the clocks */
$ \8 ?. L8 A9 ]& N p* `. `McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 y B1 z. C- aMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 G/ C; {. M0 o, p( z8 k1 a/ |1 R( H8 VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" l% ?. a N& _" x7 y9 r% [EDMA3_TRIG_MODE_EVENT);, q* d$ d% H* ]7 r0 c( a( P
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) ?' \4 z2 @& T) @% [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
3 D6 W5 M; @7 W6 v% c" \McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# ~' A+ B* y/ \, A% |: ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, F3 F9 N* e9 m
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ J, q% z2 n) K- j' i% m" |
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# E0 o6 f0 h& d) ^* ^
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);" U" n5 ]/ p0 E& J
}
% K1 X' w e7 i) [$ E4 p0 a请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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