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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,( f3 z, [8 k% }' v8 }4 G& r; Y, q
input mcasp_ahclkx,
. p6 l; o! G cinput mcasp_aclkx,3 V: l* V7 I9 w: r* {. H- z2 B
input axr0,3 b E( j" Q9 U% z
7 L1 u# ]$ G! J4 ]) o) _8 uoutput mcasp_afsr,; {$ h0 E8 ?, _4 U- M( y: S4 [
output mcasp_ahclkr,
; \! m- |. X' F- zoutput mcasp_aclkr,- D: {. `, Y* V" t- z+ g0 _
output axr1, T: _1 ]: @' U& w, I
assign mcasp_afsr = mcasp_afsx;/ x0 W! s; m6 ?1 l
assign mcasp_aclkr = mcasp_aclkx;
5 N' q) O8 Z! t& b/ j8 c2 G* o: [4 uassign mcasp_ahclkr = mcasp_ahclkx;
" z* P( ~* O- b* O( N& Xassign axr1 = axr0;
H9 F% m$ l) N1 y3 k
, r$ k. y2 V$ |& D- P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 }, N4 e2 a) Q2 j! r: Tstatic void McASPI2SConfigure(void)
; g/ ^! v. z, G( i{
+ o/ {8 Y5 f6 C7 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
$ E- E* T) p! U; ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 b& N5 y* ?: ?+ f% l9 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Q; F, E2 w; [9 t( ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */4 A: I" c a3 y4 t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ @3 H5 e; _" j& r
MCASP_RX_MODE_DMA);
0 B0 W, N q8 XMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," E/ n' M! t" x T& Q2 r/ s
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: [2 r6 n% J+ q, t6 r, \* n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 i v3 p% C8 n3 {5 Y, a% Y3 H# O' U
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- X, [. f: h7 }. p: x/ vMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ ~( C! _8 E$ }9 UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" m0 |0 `7 |9 V8 ?: R: H# d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 O3 j4 V$ ^/ V- [% B- _8 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
7 V! o7 C. v8 C0 P) A) V% m2 q6 Y( ^6 P: eMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
- \; d6 n+ A$ i5 B: i# G5 d0x00, 0xFF); /* configure the clock for transmitter */- _% q/ K: T) ~, j* G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
4 F$ ?; V/ v3 M* _% MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* x- N7 V9 I5 u) M' i2 g3 q6 W/ LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
N) h; B* n: [4 W+ k7 w5 l0x00, 0xFF);
4 T. v- d! t/ z7 ?/ Y& l' _. v$ o' c
/* Enable synchronization of RX and TX sections */
& i* ^& t: H6 ]" j& R! vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
$ N/ B. l, }; S. @% y/ g( _McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
! u% Q% q6 k- c7 ^' k5 _7 e; NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*) n% ?8 `+ j j8 p7 u1 ~
** Set the serializers, Currently only one serializer is set as
7 C; M! V5 n4 L2 I5 r1 F/ V** transmitter and one serializer as receiver.( }+ }) T, L+ l* V H
*/, y5 k( [1 {" K& Y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 d h' I8 |' b8 H; J4 l+ W! g' kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* q) Y% c- V! s
** Configure the McASP pins / i W% q* v* B( e2 S& z+ c4 S
** Input - Frame Sync, Clock and Serializer Rx
. W0 |( ?/ K x( @8 F# C** Output - Serializer Tx is connected to the input of the codec
1 O \! d) O8 e* h*/: y/ h, p9 G5 k* |
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( c* I2 H+ }2 y9 ]7 a" zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
g. O" v: o4 r6 ^% tMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; e7 i) J6 N& S) p) `+ ~| MCASP_PIN_ACLKX
- Q1 e( e5 J( O- n) X) e+ H| MCASP_PIN_AHCLKX
8 s m9 C( W+ v' G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */& G6 f2 H; |3 W1 e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. V" B) O+ Z/ r! @. B* u. R| MCASP_TX_CLKFAIL
0 [$ ^# E% v& b7 d6 f4 E1 S1 L+ v| MCASP_TX_SYNCERROR% O" k2 h' q( Q+ V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
$ h9 ?( N1 O0 r4 G3 I5 m| MCASP_RX_CLKFAIL. ?6 R: O* P! ]+ L& u
| MCASP_RX_SYNCERROR
3 ~* o/ V3 I o+ u; `* Q6 E| MCASP_RX_OVERRUN);
; x4 t9 N* |0 C1 ?- b# j} static void I2SDataTxRxActivate(void)
' k; q8 }3 h+ h{
6 i" o7 x% E% b( g$ Q- I& r/* Start the clocks */2 G4 h0 v5 q# a0 E8 \1 I
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ b# t2 U! j, V. {! d7 BMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 W& a, B. p9 u
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,4 p: R$ ]. N d+ b4 x- C
EDMA3_TRIG_MODE_EVENT);
- P( C8 [) H( a$ S8 j4 V# LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 l, }, P# v! G+ M5 _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// v$ W9 r& H8 Z. v/ V3 F' T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 R& y/ G7 [% w& S# `$ t* J/ O" ]% z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */7 J; ~) H. |" l- L+ M
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( M3 R7 B9 S* G( {8 S8 pMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 s* ^! _( f1 s h# ^McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ t$ V G' i* Q2 g! a; K}
, s* s6 p# I7 g# i7 ~( t请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 7 @* ]% _4 V, M7 p
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