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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,8 u' z1 W5 S5 A* F
input mcasp_ahclkx,
# k/ N" v5 v, {& _input mcasp_aclkx,
' z9 ~# q) ? u& F6 finput axr0,& L! K9 | m% I8 i4 c9 u3 e
' x7 [7 O9 R$ D$ Ooutput mcasp_afsr,5 J9 Q- `( T2 J/ ~
output mcasp_ahclkr,; v9 S' Z+ h( V' w; o) `
output mcasp_aclkr,
6 r6 O# V0 l, D! a& C& z8 loutput axr1,2 {) E) g. Y& ^) z3 I: ?
assign mcasp_afsr = mcasp_afsx;
9 W1 E( ?+ J, j N7 Uassign mcasp_aclkr = mcasp_aclkx;
( Y% |+ q4 ?6 @0 P0 k+ F; |& @1 Fassign mcasp_ahclkr = mcasp_ahclkx;
' p6 o A& L6 qassign axr1 = axr0;
2 @9 N) E5 s- |* `6 q$ M4 M
( S; ~' \9 W9 c$ q0 h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 U5 ?, t, g1 @, U+ d
static void McASPI2SConfigure(void)- ]* y/ P- H8 g( X
{
% O2 ^/ D3 I" A: z0 o pMcASPRxReset(SOC_MCASP_0_CTRL_REGS);% W, I& Q1 d" o$ T# s: X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: G& W J) ]' z9 H+ a3 a1 uMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 E( O! Y) t! Z, v2 T" u( G5 V' B8 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 C' Z$ Y8 z# o5 W) L
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 w/ \4 N+ c; D( B- v
MCASP_RX_MODE_DMA);7 [& B" \$ p. T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) {' ]- {7 ?, \9 h: @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) I- q: G) c( J7 B( s1 ]1 D1 O& PMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ e7 O( @+ s- ^. I. c {8 M Z! \
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 @. d2 k, J2 ^ {, @
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
s. x8 o, N) J, o a5 VMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 b2 {5 _5 X( e# Q$ l. ]McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# B& O+ v/ v# H3 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ y) K* r& ^; W( pMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 Y. K, k S" w* e0x00, 0xFF); /* configure the clock for transmitter */
% m, b; D9 ^& s6 k* YMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" a0 h5 z V+ S6 n! n3 p
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " H1 b U0 d8 b! o7 H; M U' `/ L: _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# V; V' Q' F8 H
0x00, 0xFF);1 D) d z1 l# v8 D6 ]6 [- ~
) X4 N, G4 N! ]2 e5 X/* Enable synchronization of RX and TX sections */
3 f: a( _. h9 P1 R( {' C4 w _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 D3 F" ?( _- v/ Z8 S FMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( V/ f/ X0 f9 C: `
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 f$ A7 H% M. u. ?
** Set the serializers, Currently only one serializer is set as
6 y% G4 ~' S6 A. g, M2 e7 D** transmitter and one serializer as receiver.( i4 n, o n: \/ R0 k. K" e
*/7 {0 I- y x k: O! y6 C. b M P& r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& Z9 W# O* k/ b; {' q4 t* E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' ~" a! y" a% R0 t** Configure the McASP pins
. x, n0 f( [# T** Input - Frame Sync, Clock and Serializer Rx# Z1 F% b! _* a1 j
** Output - Serializer Tx is connected to the input of the codec
9 A8 d- ?: E) }5 d: I* g" H*/0 F9 K5 |" z: a1 {& x, C* M
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 l& d, f9 F" C2 A$ I+ ?
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 l" x: Z- n- B1 q; rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 x7 z$ N* ^" m7 v8 e1 o! n| MCASP_PIN_ACLKX
( K( Q& V& Z* c9 y$ C2 p| MCASP_PIN_AHCLKX
" N0 F5 j) y+ C: M1 h+ k7 T5 ?# S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' A; d2 s# W6 o/ j
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
/ V$ ?% I O( H& D& G$ Y6 I) O| MCASP_TX_CLKFAIL : c) z7 Q0 }8 |. z# v& o
| MCASP_TX_SYNCERROR
P! l3 W; k& K- G6 ~" n) O1 s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ P" K/ k- O6 d| MCASP_RX_CLKFAIL5 \" j1 E4 l7 ?) a7 l0 j5 P
| MCASP_RX_SYNCERROR
% {! r/ T" T0 F! J2 ]2 A| MCASP_RX_OVERRUN);
: `" x. k+ Q, H9 w' S; g1 P- C} static void I2SDataTxRxActivate(void)# e2 K" K* h, L0 G
{
% s+ A( Z/ {$ W* m. S" j- W! D/* Start the clocks */- @) h- D z) a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 N9 W0 m. L z- G& a( HMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- \# |0 S) h2 z0 X1 I7 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: H. z; O- C1 P7 X& s4 e
EDMA3_TRIG_MODE_EVENT);) v0 P' X0 X! Z" ^9 {% O' A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" Z5 v& r; s( r+ J5 |8 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& [' l8 A }5 x/ e2 I/ PMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 @3 ]: X1 c/ G, Z8 \& `McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 l9 H1 M7 [+ a) g' Q* u0 Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* N8 s* [9 ]& YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' Y! Y& |4 @) m* z' P tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);# i5 m& }# U9 B( r0 Q& B" `, F; r
} 5 e6 Y$ s( o7 c/ ^4 ?/ x3 O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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