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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 b. q4 G4 A2 ], |4 H4 N0 K" Minput mcasp_ahclkx,* r3 O! p5 M9 V) `% U
input mcasp_aclkx,
5 G0 V0 u4 }1 p8 @input axr0,1 A( q$ p3 ]: y( o4 G, v
+ Q6 j1 j! M r Q2 |5 Boutput mcasp_afsr,
8 N* \% H* T5 G: }2 Ooutput mcasp_ahclkr,6 b5 P( K: s/ q* p, g
output mcasp_aclkr,
5 f, i4 y4 i# H3 Xoutput axr1,
) M. |( b4 c% K/ s" \" l assign mcasp_afsr = mcasp_afsx;) K/ S9 ^# o0 j6 Y; W# B
assign mcasp_aclkr = mcasp_aclkx;1 v8 ]* g2 q8 g
assign mcasp_ahclkr = mcasp_ahclkx;( C1 Z7 b. y# W( ^# R' D, b
assign axr1 = axr0; ! z& C% n0 g! @8 W/ T: w
9 H, `" H( S$ \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# k; M, [: v' s9 }3 B& Hstatic void McASPI2SConfigure(void)( S, N4 D( q8 r4 }
{. n, ] W% ^& w5 ?' a4 m G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 l1 n6 v* h: TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer *// ?$ k7 H( U3 C& } R, s& R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 [# Y3 q2 F- {) ~6 |; O
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% S x: Y+ I0 K S: ^McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: z/ `, p$ X9 m! t5 @
MCASP_RX_MODE_DMA);/ [5 F8 |0 b0 {/ A( ~- t- U) V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 A+ Q7 s; Q* V% n) k5 ]8 eMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */$ V$ H' |1 g$ k: O
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
: J4 c. s6 j+ v$ q+ z! m) M4 NMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 [4 C }, |) a! o. [8 R7 U! UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : t6 @2 ]+ C0 o: f# \+ `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */. X6 w# L* K$ v* G) Q/ @$ |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);8 E) E3 I" f: _/ V3 c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) c! w2 r$ w, w9 T* [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 F& ?! G2 L3 F; X% H) x0x00, 0xFF); /* configure the clock for transmitter */
+ g' w. t0 B# CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
+ f: G+ U1 G% C7 A! Q2 s4 w+ }, eMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 U5 x9 d- l X7 eMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ K; I- D: y) R8 D0x00, 0xFF);( ?# x; B' e/ _$ a3 ^
- u0 }, ~* Q7 u2 O) j/ B# o/ B
/* Enable synchronization of RX and TX sections */
. w" w9 T$ I( j3 u( | f: ^8 SMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 R1 L5 e. `/ U; [! U) ?5 E/ O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% y7 e) |& m) f. D2 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 F4 Q4 M" z) Q* l
** Set the serializers, Currently only one serializer is set as
! }; L# U% h$ t7 s) U** transmitter and one serializer as receiver.: t6 A0 p5 a& J) T7 E3 x: T! _
*/) J0 Z6 q4 x- F0 q U; b) K; Y) @4 }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; P n2 P' h5 r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# r a, G* d8 T- R
** Configure the McASP pins / a* f, n7 B& [
** Input - Frame Sync, Clock and Serializer Rx
, v7 O. V5 ]+ Z) H. A** Output - Serializer Tx is connected to the input of the codec 7 F7 V" p' n; k: R* J7 _
*/
+ {+ S, e* W4 U! O/ A4 }McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
6 V& w7 N" k1 ^$ k+ l3 J+ a: ?1 ZMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 b- A: g" X, z8 ?' }9 ^8 k: ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 j) Z8 N( o" l8 q
| MCASP_PIN_ACLKX, _' I" L) B g0 V
| MCASP_PIN_AHCLKX; U/ g5 m( ? O3 \" X
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- C, r! b; u$ X( N
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + Y2 y, p3 L( ]+ N& d
| MCASP_TX_CLKFAIL
8 A% Q# \$ s& l. k) U/ u| MCASP_TX_SYNCERROR+ B9 u, \6 a ~" t G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- ]2 M8 E- G. H& i+ r| MCASP_RX_CLKFAIL( L2 R! [! Q$ i$ v/ z
| MCASP_RX_SYNCERROR
4 @; q. i5 t5 v| MCASP_RX_OVERRUN);
; d; I0 f" i9 o5 m/ a} static void I2SDataTxRxActivate(void)
8 ?6 l* |: `% c7 w" Q{+ I X% Z+ Y% {( l* S! O5 U! I
/* Start the clocks */
/ J$ ]: L" \/ \+ q; E1 cMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 D- m8 h: f8 t M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! {" W; K2 [6 _" `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
3 C, b% @/ G9 z; [; B6 JEDMA3_TRIG_MODE_EVENT);
9 h6 w, p- ?1 v5 [" [' [EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
7 A. D% P' y% ]7 @* zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
6 F, ^- H) ?. N) pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: z1 M# n' n2 D7 K- m/ F( J4 p
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; d K; O; Q* l6 m$ j2 s, r7 [
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* ] u$ I( x; r/ ~! a
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);. X( n& P, g7 j7 @% a, Z% q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 S- X# P4 u$ r# S v* J
} # L ~& x" S1 P5 y5 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' { [' m- U/ v% a
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