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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 m$ e! z. ~& p; Finput mcasp_ahclkx,0 ?" @6 V& K/ X% P
input mcasp_aclkx,
( Q$ Y" H6 G x5 G' minput axr0,3 \9 Z- Q# \. _+ D
- \ E# G Y3 _, z# @; h! e5 v1 poutput mcasp_afsr,5 Y8 V# I5 A3 j/ w6 e8 g0 b
output mcasp_ahclkr,5 \0 S2 z( l j( i* }
output mcasp_aclkr,$ I; q* [" c% Y7 j. X H
output axr1,
! U' H8 g& d9 q: R' }0 U assign mcasp_afsr = mcasp_afsx;
7 T: W9 K( V! Fassign mcasp_aclkr = mcasp_aclkx;& N. _% U; y8 ? R1 [
assign mcasp_ahclkr = mcasp_ahclkx;
. S& g0 j! k% nassign axr1 = axr0;
\/ `* z0 f& O% Y1 I! K6 O( Z" ]
2 w! t* o0 F3 f8 ^' B8 a( `在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 W- A, z. G! w8 F5 m( h: Mstatic void McASPI2SConfigure(void)" G7 J2 m7 z0 h! a* j, ]9 A' S
{# d$ B& D0 p! y$ r% m+ ]9 l* g; @" a
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 ^% ^7 [- ^3 p" U3 q7 S& D$ qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ v. c4 M+ I, o% g. H) Q1 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' x z$ d- `8 A4 y/ A9 `
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) `) S0 b8 ^$ f' I2 i+ u$ X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 D) M( M6 Y' H* I+ E, {MCASP_RX_MODE_DMA);
6 E- t+ h/ [8 V; I$ cMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 b& q r' U4 j2 b( j T5 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */4 q+ y2 i! r, l9 {9 d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ' O* z! G( X+ U6 J
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 O) D4 V1 b! W$ V5 E, BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + P) @9 [8 ]) S( k; L( Z! J
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// S7 A% j% d, _) z7 H
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! w9 v4 m9 h: N6 J. r7 ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 c7 r' Z: {2 M' z4 sMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 M/ P' S! Z+ }1 D% Y$ [0x00, 0xFF); /* configure the clock for transmitter */* q. f+ F4 @+ O; o9 W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* Z) O; S6 {$ c( F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* Z. ]% _, x& i) ]; {* K, @McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" E3 Y" M" G* y3 j5 U5 l" x( @+ H6 d0 Z0x00, 0xFF);. O* [ O$ H+ P) U+ \* K- D
- q* x# b* r: Y/* Enable synchronization of RX and TX sections */
( V- Q$ r/ t6 a h! sMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' d1 W8 S. K" l$ B! j* ?7 BMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) q6 v g8 L8 \6 F- W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
3 ?# }+ h+ H1 b3 c i** Set the serializers, Currently only one serializer is set as
6 ~7 i0 S* V& S- S, y9 z M$ Y** transmitter and one serializer as receiver.& G J! S1 N: F8 R7 v
*/
2 [+ C: _& \4 W D( p6 w: g# }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ e2 G+ H+ }% u1 n; k6 P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 Y1 h/ Y& q1 Z. e1 X9 G) ?7 x, N** Configure the McASP pins ' h6 v& x3 n8 F# I% L/ I
** Input - Frame Sync, Clock and Serializer Rx4 P6 w6 k" f! K
** Output - Serializer Tx is connected to the input of the codec
& M' a$ A( d) `5 h8 b8 O) K*/& Z7 Q$ c# c5 j: j
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
) Q7 b. n+ k; vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& A" w# p' |' A3 `7 j. b# i6 U) }( [/ N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
2 [. c! C& v `| MCASP_PIN_ACLKX0 `, U2 m" k( C9 U; Z$ c" n" H
| MCASP_PIN_AHCLKX6 ^: o/ V7 v( r
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */' G6 v; ]& G( ?$ t% W; d6 F- T
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 s- M/ N! i M3 D: Q! ^- }| MCASP_TX_CLKFAIL
) y l! V4 Q2 g \- v, [8 ]| MCASP_TX_SYNCERROR
- U# N) ^2 J4 Y3 H* m7 E2 m4 g. S| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " N/ d) M( D) \; g+ a
| MCASP_RX_CLKFAIL
% K6 ?8 f. S: ], b| MCASP_RX_SYNCERROR ' n& G6 D( r: Q/ V
| MCASP_RX_OVERRUN);$ ~( R) S) M+ b% }+ W
} static void I2SDataTxRxActivate(void)
3 w l( T$ p* w4 {4 {1 W$ C! Z{
1 I, w6 h/ G: }! L* M9 {/* Start the clocks */7 P, E9 D6 `) k& {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ Z' V4 Q2 p0 X/ v1 ]# G. { f9 DMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* g/ h- l4 K8 |* q1 O9 L$ W6 N
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ \5 I( n" n ^9 f \* [0 S
EDMA3_TRIG_MODE_EVENT);; p- H6 x5 c% }9 d# @6 W: R* t) ^. @; }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 ~- o; B8 X8 B4 E. l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
8 ^% v7 p2 C1 @2 a7 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 z6 d' v$ o8 N$ l5 o
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) M+ G. r" P% g- |+ ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ ]& h% Y- m% l6 i) A" T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);0 T7 K5 {) C& l& r5 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
5 S9 x% {$ N7 r H3 G- u2 m}
+ ~2 ^/ s" P+ E F9 b, `请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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