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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," F0 H9 b4 O/ F6 i+ C7 u
input mcasp_ahclkx,
1 v- ]* e" \4 o. k4 N% U$ Jinput mcasp_aclkx,
7 Q0 D* H5 \& X; I, i3 z* ainput axr0," ?4 p. [/ U" D( ^2 {) @& I
' z% u- j' W# R6 z9 W/ l. houtput mcasp_afsr,
4 a& I7 i7 w2 T6 z- d) U* u* }output mcasp_ahclkr,: \( g% f3 B6 |$ y. ^
output mcasp_aclkr,
" d- m! P% E4 [output axr1," Q% L& m5 f, J6 x; X0 C# z$ X
assign mcasp_afsr = mcasp_afsx;
; ?& o+ X6 U4 H( }assign mcasp_aclkr = mcasp_aclkx;; } _- U ^$ V# N7 h
assign mcasp_ahclkr = mcasp_ahclkx;
6 I2 g0 ~# V, V Q$ m& r% _5 c# ]assign axr1 = axr0; " V8 ^# r1 p3 s! j& u- @. ]
) G; Q! u7 D p; h在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' I- D6 \' U, i2 U" h8 V
static void McASPI2SConfigure(void), z4 D8 g, s E& l: n. \
{
8 N. k9 X" E3 \& u) ZMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: v3 B9 x0 G; h. ^& n4 E3 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: l$ k, D7 e# g3 j8 ?
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 s3 M; P" j. r$ SMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ Y2 C3 l, x' w. m; O5 P$ ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
o! I1 L% }7 ]8 u; ]MCASP_RX_MODE_DMA);
- ~/ }0 I: h4 Q- n3 }1 R2 _/ \McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 o2 D5 V6 p* S% f1 q u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- S# ^' U+ c# L& x3 bMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 C" K4 w9 ?! [: G" r- R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) ]; A5 J$ y# G5 ^8 v
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 0 s& q9 S. M4 M, i6 g7 ]+ D' }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ W: Z% z6 H, w" d3 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; P9 S$ I: ] b$ E/ E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) A1 U8 T* k7 k
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,; A! ~9 b8 F; k4 a1 u. y. a
0x00, 0xFF); /* configure the clock for transmitter */, H Z6 { V7 N4 G
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& i& V! _( P- U# NMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 y) I0 N, l3 ~6 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& F( ]1 x! h5 O! j! t2 \
0x00, 0xFF);) U) ^( A6 p' s2 n/ j( X
9 C8 E# X4 @' [; e* H% \2 Q
/* Enable synchronization of RX and TX sections */
! X/ [) \1 O* _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// _! ?9 Q5 E+ c0 {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 n/ C3 S( r* D9 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ k2 f1 S' E! W( { o- h" n. ^** Set the serializers, Currently only one serializer is set as U: }4 f/ ~5 b8 P- U2 t6 s9 s
** transmitter and one serializer as receiver.4 z8 X3 e* X# E* B5 X7 q
*/. q; Z, B( v/ Q; i! Z9 W% ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' A2 [; s6 L4 D* E; q4 oMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*2 D g. U+ |% N7 Q9 r
** Configure the McASP pins 2 p3 K( P2 U6 ]8 C2 p0 b
** Input - Frame Sync, Clock and Serializer Rx
J8 n3 U4 u" m$ c a [** Output - Serializer Tx is connected to the input of the codec : x8 ]* V; c4 a
*/
; w. [! S: s1 U; @/ XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* b! a6 J( V$ r) H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% w" J: t5 Y+ Y9 w2 b" o8 [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ x7 z! {" i/ p7 P( {
| MCASP_PIN_ACLKX4 z5 q. M! z; m5 q
| MCASP_PIN_AHCLKX$ h. J3 u6 a( y# S0 F1 [. n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 C9 W. h1 t) z N; \, B$ v2 f0 ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , g, Y8 f1 t5 g5 o2 y
| MCASP_TX_CLKFAIL ! v+ i7 `( B' v/ h1 A
| MCASP_TX_SYNCERROR! O8 Y. F$ m2 f- g n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( p; O( H3 @/ m8 Q* i
| MCASP_RX_CLKFAIL+ P$ |6 L! }: f7 t8 \( M
| MCASP_RX_SYNCERROR 7 Y7 P3 p# N5 ~4 e) o5 A3 t
| MCASP_RX_OVERRUN);
# t9 K$ n6 e& z o7 A} static void I2SDataTxRxActivate(void)( @9 z/ c/ R! B* O+ N: \( O
{0 j0 C+ V+ G2 r4 w* N5 \6 ]* g
/* Start the clocks */
* x ^& _7 i. m( {% r' u# mMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 A" `0 J+ o- C( Z0 j" S* ]8 q% e! PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% D' k1 ?4 k2 F/ x: d3 Q i% F, K& H, S
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 j2 p [( T, p6 |: q& b: i9 wEDMA3_TRIG_MODE_EVENT);1 `0 ~) P6 a8 j6 v0 S! [; t+ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
- T6 Y. o' O3 C' r4 NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
b, ?; g o8 X/ g, mMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; y5 [" Z$ `, Z/ L/ m/ TMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 B; I0 q% e# qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# M* ]3 D Q7 [+ d' {( S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ L" F! h0 A* U7 g Z. a; dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 z% M4 Z7 \1 M. W# \} * y- I+ {: ]/ |( c. g" x
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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