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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
0 @2 ]& t! u! s; g% ^+ Minput mcasp_ahclkx,% J7 w- c2 w" f) X- C" w
input mcasp_aclkx,/ H& v5 [0 X; E" c# z6 X
input axr0,
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! B6 I9 E7 L5 r9 `, o5 n# Eoutput mcasp_afsr,
& F6 i1 A6 N+ o8 [; E uoutput mcasp_ahclkr,* r6 P4 O! y& T4 l
output mcasp_aclkr,
$ O# U1 e# p7 [0 @ L/ zoutput axr1,8 d# K) a) s' ^
assign mcasp_afsr = mcasp_afsx;' g( n: g' D& z9 ]/ t+ r
assign mcasp_aclkr = mcasp_aclkx;
& P! j5 }: [& O' e* k. p4 a4 vassign mcasp_ahclkr = mcasp_ahclkx; Y$ B5 G+ |, Q7 o! y" v' r
assign axr1 = axr0; & t4 Q" Z5 ~3 Q2 A9 N& _ n
6 X8 ^* h8 o" V. E8 T. X在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 A( X K( Y* _7 D& Q5 M0 Cstatic void McASPI2SConfigure(void), K6 g' B( V6 r \/ J) y5 J- L7 w) K
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
D+ y% j- l4 |; v& U5 w! tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; \2 W& e% s5 o. ~7 TMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 y! }( y8 f5 `5 Q! UMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 D/ `6 M- m, o' l, D
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! p. b! o6 l1 m4 dMCASP_RX_MODE_DMA);& v: f: U. H# G3 v r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 c [! {+ q* U8 U0 h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( \/ j4 O5 c. b0 S' K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( @. c, \+ Z% ^: D; @
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
; W, }) p+ n4 n9 A7 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( B5 z X x9 p1 E- qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// q3 p0 w0 X* c+ E/ O( w
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, `8 X' w4 x0 D
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : [4 c; J. J I; Y0 E3 X/ L4 Y
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 l2 i- t9 U6 v) n0x00, 0xFF); /* configure the clock for transmitter */
# @# F' B h, qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 ?8 C% ^' M# ^1 _/ V- @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 \1 N3 O5 E; H% q* ?. aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* O' G3 \7 M2 i' R* O- |" Y. W
0x00, 0xFF);/ ~3 D: `- s4 X. K
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/* Enable synchronization of RX and TX sections */ / O% I6 R# q6 t7 J; P, S+ ~, a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ ?: [: I) E, B/ O" @9 L9 Q$ R. P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, `% v9 y9 g: i" v" ]McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& L2 M/ [5 q E$ E2 p z
** Set the serializers, Currently only one serializer is set as
- x9 ~. d4 a j, m) `5 ~4 g** transmitter and one serializer as receiver.
, V7 b( C: u' n) V*/, \8 C0 M% F1 x& u3 \0 f3 r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 \2 ?0 |% i+ E+ _/ G i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' v5 X* @6 s4 P( ~9 G; R4 b** Configure the McASP pins : }6 T. \: Z% Y
** Input - Frame Sync, Clock and Serializer Rx
5 U5 Q7 ^% ?( B1 X( A0 @2 w** Output - Serializer Tx is connected to the input of the codec
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McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
( l* d$ @/ b0 n2 ?# X, Z, cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ {$ u) S7 d3 h lMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ [1 I# r# G- C( }' W/ G
| MCASP_PIN_ACLKX
0 Q, M! K, _' m& k' p| MCASP_PIN_AHCLKX( N5 C# X) o, D; T3 Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ B; }3 g4 {1 V q, ~: g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( H$ u6 w# v' F' I9 l0 ^
| MCASP_TX_CLKFAIL
" ^, s4 J) t8 l! Q: r" M8 y| MCASP_TX_SYNCERROR8 C/ }6 E" u$ k1 J! E5 Z# P( O P; t
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- X8 P& }3 n& w3 A3 B( l| MCASP_RX_CLKFAIL
: V, m' S5 V: ]6 k/ Y5 i0 A- x% q# y| MCASP_RX_SYNCERROR 0 }1 I3 u1 {1 I: |; ]* `& N
| MCASP_RX_OVERRUN);& r2 E5 l1 e$ @$ F2 ~$ k# M
} static void I2SDataTxRxActivate(void)* j5 \) D2 h6 E* Z/ K
{1 K( H* J" ~) [! J. F
/* Start the clocks */
6 o* t* ~5 E9 r7 o, zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 l) m: f/ R2 ?, O! m2 H o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 z$ Z. X: w+ jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: K1 x" U; a- w
EDMA3_TRIG_MODE_EVENT);
. P8 C* [( ^% `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 4 F6 {& \* E1 _7 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
* R( Q( H! ]% p" E M7 E& DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 _; h+ `( h, b/ ]. _, |
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */2 p A- ?: K, {$ } w4 z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( W- S3 t; I& K) i3 G; Z& A EMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ {; {* N2 d- q8 dMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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