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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 T0 t' F9 P; ~. B( d% e0 d
input mcasp_ahclkx,
3 l- @4 ^; l, u6 b. J# Dinput mcasp_aclkx,# N7 M1 f& @/ e7 ^6 p% ]/ q
input axr0,
0 X3 u6 v$ S7 o4 a" ?3 v w
+ I, i* g6 {; {3 y- O% C) Noutput mcasp_afsr,
: B& b" k! j# D* F7 eoutput mcasp_ahclkr,
7 D* A( N1 M2 _1 zoutput mcasp_aclkr,
3 O; T! d& _5 P, s1 N- q3 |output axr1,7 {- W+ ]8 p1 m/ B4 u- T+ F5 _
assign mcasp_afsr = mcasp_afsx;. i* t" H) {. A" Z* C1 s
assign mcasp_aclkr = mcasp_aclkx;
+ L0 t3 ^/ @+ v8 z" tassign mcasp_ahclkr = mcasp_ahclkx;
2 X( A7 p/ O$ @: d( {assign axr1 = axr0;
0 c3 B7 c+ e5 \4 ?8 c7 h2 |# U0 c7 {' f; @1 u
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : N+ C5 [5 w7 R# u" @7 r$ g% }+ }
static void McASPI2SConfigure(void)7 \$ l6 Y! k, p( e
{5 o- H' V2 s1 p4 G) H6 M0 t3 t$ _3 i ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% o( Y* [4 Z u& E, C4 H! IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' D$ J+ ]5 G Z$ L: f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
3 u k# g/ i6 c4 X7 e7 fMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 [% Z+ B$ F; j* y$ d$ A& r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) V: j8 t, H8 W0 f# }/ D
MCASP_RX_MODE_DMA);! W3 \0 K% E( x8 `& s# f
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 H% E e* J( \0 s6 p. [) ], N- U/ B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! [+ f5 U4 V; H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 0 e; t( \" L8 ~7 P2 I4 k
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# |& g3 |+ C1 Z: i& Y% i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 ?) l; _0 X& P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 y+ e: G/ D' I" DMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 F+ E. K7 M1 y g& `/ UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . k: z" H! s) @+ C2 L" t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) l% X# a7 w% z1 t% C1 U
0x00, 0xFF); /* configure the clock for transmitter */9 @2 B/ Q/ J/ m0 }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: y% L8 V. q9 p. T! w$ r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. `6 ]/ O' ?6 ]3 H) {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
. a$ C. H2 `3 \6 p) X2 v0x00, 0xFF);2 w- O& J. f% b. n6 J
- |1 a9 A$ e3 t$ d4 A; S6 I2 U
/* Enable synchronization of RX and TX sections */ 8 T9 T7 ^8 ?9 `. x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 n4 ]; v `2 A9 C- s# [
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
) j; }/ X2 f1 WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: y# H) ^6 |- R0 I1 ]
** Set the serializers, Currently only one serializer is set as3 o3 |! C! F% I; E$ w
** transmitter and one serializer as receiver.; Y: Z n# Z) H5 o8 i
*/+ J0 g. C6 D' O% A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 R# m$ e7 o' h5 k4 w3 N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*0 F1 g. w* y7 P! v& f
** Configure the McASP pins " W" {9 o0 ^3 T- k( d) y
** Input - Frame Sync, Clock and Serializer Rx
& t, j) {4 `# W" X** Output - Serializer Tx is connected to the input of the codec
3 k4 a' a. P1 {4 g' s8 ], ?, `*/4 C$ ]; x& X1 I6 q; ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ t6 W/ H0 { L$ F8 d( @" f
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( \) o# w3 {0 j8 G' ~McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 A9 ]& P8 [! Q, D; W6 _, ]; Q| MCASP_PIN_ACLKX
" X7 o7 O$ ^1 E& \# s6 ~| MCASP_PIN_AHCLKX# i4 y+ v% ]. ?4 }
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- ?$ |( Z6 _ z5 U! z& e
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' B! V" N8 R* n- {
| MCASP_TX_CLKFAIL
: ]' k& R& j. ^2 o, l6 u| MCASP_TX_SYNCERROR$ t. `5 G. L: h/ q' r1 {* E
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( X P: o) _* Q+ }+ q
| MCASP_RX_CLKFAIL; j0 _6 I: s1 m2 H1 X7 b" ?- [
| MCASP_RX_SYNCERROR 5 N2 }8 a/ g+ Z2 g! i7 z# w
| MCASP_RX_OVERRUN);
7 y3 c, T. d5 w+ r' X7 H} static void I2SDataTxRxActivate(void)8 I) w) J+ b3 K* z j' l
{% z J! w m- c$ h4 A( @
/* Start the clocks */+ Q) A/ ~8 M$ i' `& P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 f0 m# r/ E' l& `, w- D" mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" p; v. z$ C% B, J+ v/ j* f0 t( MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 a& r" w" ]3 A/ CEDMA3_TRIG_MODE_EVENT);5 s3 K0 `& r4 o2 g- X$ Z5 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 G9 U7 W2 n4 V4 j( N4 e6 oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% y, }/ r; }9 b# d. v8 T. i8 f
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 q- j% @* Y+ ]% C$ p& j2 A" v
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */ l) x) K0 Y# \$ A) L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */& _( J% d2 R7 B( L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, D w: W, r' AMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
6 K3 S7 F2 C Q* I5 C8 ^9 t) p} / \4 Y, Q( Q* S, E- s, \( _# w& U
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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