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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,) S- Q0 b% E5 L# q" a
input mcasp_ahclkx,
. Z, h# K u ^+ ~input mcasp_aclkx,
% L9 t! u8 C" R5 Ginput axr0,, t S& W2 F9 V) M# K4 @$ p$ r$ A! Q
% i* ^. z& r" h/ V$ v8 N$ f0 @
output mcasp_afsr,
+ k# z9 b& ^2 c% }5 F routput mcasp_ahclkr,, ~9 Q. J- P) w& A7 b- o
output mcasp_aclkr,
* S" F4 {& [+ z0 b6 j5 Ooutput axr1,
, W' z5 I/ v s5 A assign mcasp_afsr = mcasp_afsx;# U8 l) [2 V$ T4 d+ Q; H
assign mcasp_aclkr = mcasp_aclkx;: _/ Y& @& o. D( E1 X- S
assign mcasp_ahclkr = mcasp_ahclkx;" A h8 L8 {- X$ {, H5 r
assign axr1 = axr0;
0 T5 U4 w4 G& P1 {0 c0 h+ D6 b+ a$ T) h, w! V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 q" C& ~( K* o9 G
static void McASPI2SConfigure(void)+ D+ b, y4 @! [; U' j8 U
{
: x# u6 X& s3 x4 {7 C: i. \5 t8 d, eMcASPRxReset(SOC_MCASP_0_CTRL_REGS);5 N2 X1 P9 `3 G5 ^
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ L% q; r3 c R
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& ?4 u+ R' I' f. t: B# ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" Q. Q/ P5 N! G0 h% v3 [8 X
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( U/ ^! Z7 ~) q; M% M+ EMCASP_RX_MODE_DMA);
" e! u# K3 n6 Q% f; t$ r8 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 g8 h3 W2 `; D# @, q, ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
3 ~9 t$ l# A2 C' gMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, |' n9 l6 C( `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 q5 o3 e1 P0 bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 V. n' Z+ Y: e. O" CMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 I6 E. E9 _7 d
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
8 ?8 ]9 \+ |5 l1 a, P! dMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 r2 B+ M; X7 A
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 M8 W- v5 N8 Y. T4 K% F0 _
0x00, 0xFF); /* configure the clock for transmitter */
' }/ B T& P$ s6 V: QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! Z% `* j6 w- J( F( r/ \+ g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 A' x G3 I$ `3 b" xMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* K. o5 k3 Q6 ?: r! ?4 G3 ^) r0x00, 0xFF); G- b. B( @0 J# F% K6 G# P; f
! h3 U! u1 ?5 B* F, {/* Enable synchronization of RX and TX sections */
1 o* P" N6 R" ^; Y" zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: L& Q; s, ^/ Q' }& A4 E; R: B0 g/ {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 U. L8 h3 C% Z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 t9 V3 n& f& ^; z8 j# J** Set the serializers, Currently only one serializer is set as
- T! E! g1 l x# d: ^9 W5 {" Z+ J** transmitter and one serializer as receiver.& ~3 T8 z( U. p+ V. E
*/$ A( j1 ?9 \+ [/ R3 ~9 r6 V6 C
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) W# o2 f. F5 V; i- A% Y' aMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
{8 f4 }+ p) ]% g( t3 ?** Configure the McASP pins
c, _- _8 N4 v! ~6 o/ m9 \** Input - Frame Sync, Clock and Serializer Rx _7 Y) ^" L* K" w4 }# _/ l1 H
** Output - Serializer Tx is connected to the input of the codec
; N$ V! g4 H4 O4 P. p6 \*/7 ~( r4 A1 X, G4 v7 Y/ N* n7 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); W l- ^$ r* G: u5 t L
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));- ~- G( K' M' D. d' J n8 K+ [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX. U2 h/ n D! |% `" k3 {1 M6 r
| MCASP_PIN_ACLKX3 Z( ?) M7 X$ a, C; ]
| MCASP_PIN_AHCLKX
. |! T& ^7 n+ q0 w- N* s| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) a' L$ Z) H) \) I3 Q0 {$ PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 ~# h+ u* C; L9 G @| MCASP_TX_CLKFAIL ; ]* s+ a4 n& ^. |* m& L# G. U
| MCASP_TX_SYNCERROR
( k8 x/ S2 |) O7 c| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 h3 s9 O: w$ |/ H; h$ c| MCASP_RX_CLKFAIL9 c& @6 R7 V$ G, U3 u2 [5 E
| MCASP_RX_SYNCERROR
1 T- _9 d7 ~2 J3 s% d$ o" I1 n| MCASP_RX_OVERRUN);2 v# r' ]; m$ Y4 Q
} static void I2SDataTxRxActivate(void)( }2 `! p0 t, o/ ^
{
2 }$ I- F" H# q5 N( i( D/* Start the clocks */
( l5 M% |# F+ f1 a% \3 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; {- W- i) a/ {( s# h. R' V6 V7 D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& l5 V; |3 V- b. N6 M2 Y# LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, Q* w) n& F2 _ @0 M! e0 H
EDMA3_TRIG_MODE_EVENT);6 T7 D0 U& \! d' Y1 ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 9 h2 ~; W8 J/ ] c, B8 X: V2 h4 Q( i
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */0 y; t5 [6 q% |3 y' G! B: k. ~
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' Q. Q# o. N. f4 M! ]. \
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 `, \! m) Z8 O; R. B" U5 ^3 q8 |
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- ?" e, T- f& r, N P3 ?McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 K" m$ u5 N8 H* }+ i* G
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 X7 d B5 q* _" n( {}
) ], z1 G) j/ r V请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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