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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! n& ^* }4 o9 q6 c
input mcasp_ahclkx,
5 _1 q& p" V: ainput mcasp_aclkx,5 ^7 ^) [% z: i' S6 P% `+ Y3 U
input axr0,3 ^+ D/ Q! d* [( \6 i; ^ M7 u
/ J/ n! }/ l1 E* |+ \output mcasp_afsr,6 ]4 z! D& d2 Q! f' m. a
output mcasp_ahclkr,
; C- I) S; Q9 D0 Ioutput mcasp_aclkr," C( d7 J1 v Y
output axr1,1 A8 t. Z @6 B- _) X) S- c
assign mcasp_afsr = mcasp_afsx;' R9 Z% q9 [4 u0 l" b/ H
assign mcasp_aclkr = mcasp_aclkx;
' F+ q1 e2 n) |; P/ T& }0 dassign mcasp_ahclkr = mcasp_ahclkx;6 Y! v$ P4 ]9 m1 K
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " H7 Y6 s: s( c) g
static void McASPI2SConfigure(void)! E* }0 }! L3 c5 K
{
$ _2 N! U$ @3 z* y5 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. ~$ e1 k9 P1 A* |5 iMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 K" a/ M. A7 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 H; r' L2 T3 a1 |( E$ B+ g# ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; O; D1 R: w0 b/ ]! _4 h! ^: oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# Z, M- R6 ?- n# \
MCASP_RX_MODE_DMA);+ I# D1 ~3 x3 |' h7 i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% h: c; ~) r) k$ K6 L- R" y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 V4 k6 @& h/ l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, x3 S3 @7 H: c+ { F; FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 @) w0 n$ ~& U1 j- e
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
}/ N- i5 h7 }6 p) ?; O( K* DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 x( L; @$ A- T7 ?7 F: i
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' X3 g! p. K2 C' E& J
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' d5 m" m7 J; V# m/ q: A, C0 s& P2 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,2 I2 V* {" f2 R% O3 k
0x00, 0xFF); /* configure the clock for transmitter */4 I4 o% R( i3 h) J
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% s f% u x- p+ R6 y& Z! \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! ?! G" ^# Q& w6 l6 }* E5 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 r; G/ d( P: Q8 ^& r" O
0x00, 0xFF);
3 N c2 p' G" n! Q$ M) N( T G% [9 V {& D
/* Enable synchronization of RX and TX sections */ + P0 h$ [- d& g% V: p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. S! P1 d/ {! ?( H* k8 sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ p1 r% K! a* n% l: L2 @) W
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
. B; t6 O3 F7 ~, Z, p** Set the serializers, Currently only one serializer is set as0 ?( z3 N* R W4 h+ T: b
** transmitter and one serializer as receiver./ Q# e5 M( I4 i/ G4 X
*/0 d: n9 U( `' G/ a! Y7 S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 O' `% [! v3 MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. V8 p4 H1 V& n2 d- N, d$ L, O# {** Configure the McASP pins
; x$ Z1 x$ ^9 n- N; z** Input - Frame Sync, Clock and Serializer Rx
# W |: k8 H2 l2 u; W% _/ N** Output - Serializer Tx is connected to the input of the codec 5 D7 Y% U, p( s
*/7 ?7 P4 B% O {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" f' p2 y$ K' S4 t$ M: j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& @! d; }6 U3 m$ b N5 \
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 N; R6 h. S# H; I| MCASP_PIN_ACLKX5 t) o" F7 K* f. k, w; W: w. C
| MCASP_PIN_AHCLKX$ ?' A& w9 t! P5 J. R
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% o! l" O3 C+ D1 N5 W' CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 {/ X8 v- E1 v, @, K7 ~, P' k, J| MCASP_TX_CLKFAIL
0 K$ b2 o) d& L. `| MCASP_TX_SYNCERROR* n5 B& j' i. S ]
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " T" l* O: h- s6 N$ P7 t
| MCASP_RX_CLKFAIL
$ x" `3 D ?7 E1 j| MCASP_RX_SYNCERROR
! q! `5 X. G) t| MCASP_RX_OVERRUN);
4 n. K7 S& ~0 J3 }2 |- v} static void I2SDataTxRxActivate(void)
' N$ S% h% z' Z% W$ I{
0 L! C2 W" a" J5 n# |/* Start the clocks */5 \" o! A/ P D* n! Z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 d( b, E; V9 s8 V0 j3 G/ K3 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 \/ Y7 n F7 i1 i8 j2 w% q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. `! U* M. k& v! |$ G
EDMA3_TRIG_MODE_EVENT);
4 p8 m5 q$ T! W6 C+ i. ~6 REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * L' H# \% U' s5 g
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
y( g# B. S/ r, @) ^# \) \3 Z: l7 p- JMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* Y. Q3 X8 H6 f j. i% Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% Z- A9 J( L% J ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) [* d" K7 I) q* t( x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. [8 e" _& E0 r( G: p/ M0 i# ~7 SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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