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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 w6 Q( A! l) B9 A9 \+ vinput mcasp_ahclkx,
% @0 i2 l7 q" ], D1 ^ `3 P/ tinput mcasp_aclkx,
' T' [6 f2 |1 t& t: T3 Uinput axr0,
: n8 j0 `* \( B, Q. |& e
, S5 m% W4 r: w- D: zoutput mcasp_afsr,5 ~$ I3 ?" h0 L; f. J2 U
output mcasp_ahclkr,
6 _! R) V! ]# h. H' r, ^output mcasp_aclkr,( G. i: U- @ N1 m# L; a. P) `* A
output axr1,4 f5 h# }0 i: H: Q/ ?! i* h1 H
assign mcasp_afsr = mcasp_afsx;
! B2 s5 i6 D2 a& nassign mcasp_aclkr = mcasp_aclkx;
- B$ H1 ?, U1 Nassign mcasp_ahclkr = mcasp_ahclkx;
. N8 i$ f0 s6 V' y0 m" J! nassign axr1 = axr0; 5 H( z0 \) k5 W
+ D6 C7 l; R+ Y. T在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; m9 k2 {) _( e5 p& _9 Ostatic void McASPI2SConfigure(void)
3 ]" S7 F: v3 b) f) Z: q, `) v{% [" R* G/ P6 t% N. ]' g' p9 B
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ Y, B4 t: e4 O- WMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' F1 q. j8 I2 ^McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& g( t) z0 l8 y9 f! r% IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ |' o9 l+ ?. y1 F" l& b$ |1 d' ?McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ j# i5 V; {" a$ I! nMCASP_RX_MODE_DMA);2 u+ r* B3 A+ @4 ]& O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 Q/ p L8 y8 O4 Z+ a
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */ c- w( v5 R# z5 l) o) n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 i: F5 w' Q" n% l! W% ^# r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) b8 z% K0 m( }% L! i
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
Z+ Z7 K c4 H9 F7 dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" G9 Q) _+ g% i5 d4 \
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- z D% f( ]( p: o4 h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
0 G8 l9 k& y8 M yMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
Y e. ~1 d: E! y6 P6 {! {0x00, 0xFF); /* configure the clock for transmitter */
) N7 h. [; r3 `" @7 A9 i( ZMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 Z4 T4 _" m9 u5 lMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 C. z8 B0 {7 p: u7 @7 e# x) a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 W1 n h' N) L" h; o3 x K2 e! Q
0x00, 0xFF);: x, V0 f* |- K2 O2 i
& J* J7 M9 j% P' ^! G
/* Enable synchronization of RX and TX sections */ 2 S2 ]8 i, f6 @7 C, J$ Q% V8 t
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 N1 x4 D# y1 M" j3 pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- e* l) \2 T$ D7 ~$ R, `: ]* g, h" m
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 H6 _; f' S6 c: x** Set the serializers, Currently only one serializer is set as
( m& a1 `8 H6 a6 L* S3 }** transmitter and one serializer as receiver.
4 q, \# D/ F, Q3 ` p4 h+ `9 @*/$ z# _0 L: c+ g; d7 r1 ^! A; v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 A- k, Z- b2 X# K) b7 Z# d( q
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! e* r% B% R' s** Configure the McASP pins * K( c4 m. E2 ^7 L, O0 U
** Input - Frame Sync, Clock and Serializer Rx U' \' g5 B2 \! Q: G3 P
** Output - Serializer Tx is connected to the input of the codec
) p- I% }8 \) `" I* W*/
2 F) W; l4 i! H9 o F3 E$ `/ f; |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; q( ^ T! f. i" V7 pMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 K" l- B1 W3 X2 X5 x6 k# }+ fMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: K, i3 U# t. [6 Z: G| MCASP_PIN_ACLKX$ j, e& z! k& f% N3 z
| MCASP_PIN_AHCLKX5 _- [( A+ i3 o* w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& z7 q1 p& F, NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 @# Z5 `* K# C8 P( F, U
| MCASP_TX_CLKFAIL 0 x, f, U; A2 [1 k, J! h n
| MCASP_TX_SYNCERROR
5 D1 g6 p6 ?8 d8 i| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 N: a0 U! P) M* K F5 s! p0 a| MCASP_RX_CLKFAIL$ W, r4 o1 J4 t
| MCASP_RX_SYNCERROR
4 g4 M' e. w6 _| MCASP_RX_OVERRUN);
9 i# I: R9 i9 h5 o% Y* X3 s" z} static void I2SDataTxRxActivate(void)
2 `0 N% z# S, e2 i/ g0 b1 }! ]{
! z( p7 e7 w9 l! \4 b" U/* Start the clocks */
1 {# g: C, C5 eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);5 L0 K/ u$ c' R c ]# C! M4 q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 Q/ ~6 T* Q/ B/ c0 p. c
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* r. L- Y$ u! ?; d
EDMA3_TRIG_MODE_EVENT);
# ?4 l# e( i1 D) T) O! j# VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( w; s$ n- N* b$ e9 Y2 _
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */( {5 F& ^$ }, G/ Y3 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. I: `6 @) ~) _6 mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
8 i- t1 a$ C2 Z- \4 ^while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
8 L& G8 n2 B( T. FMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);! q- Z( F( T1 J% Y
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 r7 o- d* j, a# b. A6 Y& z
} : p* L; H8 _! q% R% E1 N$ R2 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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