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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 Y5 s$ ^9 n! K/ U5 j# Einput mcasp_ahclkx,6 e! o; T q- P3 ? \; f1 z
input mcasp_aclkx,1 r* |1 Y# [) G2 O- Y' H5 K
input axr0,
; [- } C+ C/ L
0 H! [) X* e# m; ^# R- Houtput mcasp_afsr,
' |9 c" L& z% X" Y) ^2 Uoutput mcasp_ahclkr,' b1 r0 L7 n+ V$ J1 t* ~( ^
output mcasp_aclkr,7 y7 v9 g6 W4 D; h4 ]3 g7 |
output axr1,! f5 b! ~4 |5 ~' N( B$ J
assign mcasp_afsr = mcasp_afsx;+ E; D. n6 {- @( u9 o" u1 V7 o
assign mcasp_aclkr = mcasp_aclkx;, M, _: f" M5 ]( i; } t( x( M0 q: u% Z
assign mcasp_ahclkr = mcasp_ahclkx;
( Y6 c8 C# X. D# Eassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; Z$ K) Y6 Q$ N! _( b9 l! w' D+ astatic void McASPI2SConfigure(void)
0 U0 A2 y4 e8 T# g& H{, i @3 X+ h4 V
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- [ q* r9 H( P9 _' I) ?3 \3 uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, ~& S# H( u5 c
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);' `# \' { C0 }; U4 Q% {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) ]5 S' C c8 d" u$ }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ k0 `" F/ K7 |4 ~( SMCASP_RX_MODE_DMA);" _( f8 S; d/ u% {( k% o
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" I {5 t. v3 d' L( q( @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */) z/ s) s2 d# X! B, ] D; G
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
9 L. q O, |7 \MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& C) ?8 c S! Y# \! U3 m4 p* j
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- M% C4 d0 ]! _3 wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
6 L4 E6 z# Y* CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
- M0 M2 K: K3 rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) D# Z# M g6 _& x* m6 k9 mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, P% j! B# l, d/ B' _5 _
0x00, 0xFF); /* configure the clock for transmitter */
2 {: P) q3 q8 k" E, ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" b1 r; [9 W( j/ `1 _4 @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); % G/ h0 K5 u- o& x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! B8 D/ P0 K) p0x00, 0xFF);/ T. b1 h% d u' M- Q6 L7 K6 U
) |+ _, q( t8 C& I$ V6 j8 J
/* Enable synchronization of RX and TX sections */ 3 i/ |7 X8 w# j( t K0 O) F; T: O5 h6 v
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */$ O+ n% M0 d: E. M
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* K' I" v7 m$ G; L7 g$ ]
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 o; l( A& p$ O, W5 o8 t* [9 n** Set the serializers, Currently only one serializer is set as/ X! \5 r8 q: m
** transmitter and one serializer as receiver.. f V/ E/ E5 u2 f; C0 r. @, B
*/
2 K3 Y8 a" G6 N2 s1 }McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. ~1 o0 L: m7 {- W) C: ?" kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 x" ?& S. R7 G9 e+ z5 Z* Q** Configure the McASP pins
6 ?" A2 |- D: H" P+ z** Input - Frame Sync, Clock and Serializer Rx
& @& S3 D* i+ F** Output - Serializer Tx is connected to the input of the codec 5 k! {! |$ w5 E! u. [
*/9 Q1 o) f: ~- t7 u% O3 K" [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 j. F" j6 W! b2 ~$ k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));2 q4 ~* v7 x4 @& I' E& b2 y8 b& W
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' ~; s4 K8 d) b5 l4 w8 B2 X8 }
| MCASP_PIN_ACLKX
$ s1 E# g& {$ P# f# C0 M: T* _| MCASP_PIN_AHCLKX2 F# `7 U6 D5 M" E+ @
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( _# {8 u4 E* T/ \. Y7 i0 IMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, A( ]( R/ H' d! X2 j8 z, L8 A, P| MCASP_TX_CLKFAIL
( C' g( F; }6 P j( Q| MCASP_TX_SYNCERROR
' _+ [" {1 T8 u2 j6 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! r) S# G! N3 R% Z4 b1 S7 K
| MCASP_RX_CLKFAIL e) M0 o& k9 Y5 I4 n/ q$ {: Z
| MCASP_RX_SYNCERROR
8 @9 i! w0 Q) J- u/ I F| MCASP_RX_OVERRUN);
7 A/ U3 f$ `* R} static void I2SDataTxRxActivate(void)
! O6 b: M8 j) ^- R) H9 @; r{
' f8 a$ C# j: Z1 W/* Start the clocks */
% U& Q; D) c+ J. I8 RMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
% F) J( ]. f, {0 Y' \McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ U9 H5 R6 b* `$ M& Q9 z8 l
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' ^6 L% z Z- o# W! s/ gEDMA3_TRIG_MODE_EVENT);, g, c+ u% a! D* i2 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* `7 \# d6 q8 I" sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; \% ]2 M( O/ d! f. u
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ _9 z* N1 ]3 p# i# T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' l1 T; t1 }) [/ \6 ?) Z) W, e6 b: D
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' o! o. O- o: {( S
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);% \+ z# U( g1 W7 p6 T Y% a
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);, _( V2 Q. z' f3 d
} ' _% r" u* P( @; S8 @- z
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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