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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,# b2 ^( {& ~- m. ^1 g' w
input mcasp_ahclkx,
& @; C* L2 w h! pinput mcasp_aclkx,
1 i8 l5 X* ~' |4 K% p( T$ Yinput axr0,+ r3 i/ `$ n3 r; m5 y2 ^
. p( \6 `" v8 b0 j3 ^output mcasp_afsr,
* W! O% }1 C- Loutput mcasp_ahclkr,% K+ H' K' U2 m, |' b* W) C# z
output mcasp_aclkr,9 m) P4 O! z% K9 m9 D. S
output axr1,( Z8 A8 I) c3 X" Q- j/ R
assign mcasp_afsr = mcasp_afsx;) x! G5 J9 v9 Q
assign mcasp_aclkr = mcasp_aclkx;, G: [+ f& {) W7 ]5 n, d7 ^
assign mcasp_ahclkr = mcasp_ahclkx;
$ e E2 |/ B3 M: c% ^* e( Eassign axr1 = axr0;
# T- j+ G, ~* N- O/ A0 q/ [; i) [4 T( K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" m. w4 S u. |) |static void McASPI2SConfigure(void)
3 j- {- T5 P, p/ f# w8 Q{
- S$ e+ C# v/ W) X c# K4 G2 XMcASPRxReset(SOC_MCASP_0_CTRL_REGS);1 l3 |4 V5 [; R. N) ~6 `5 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; S4 T8 C' C/ A! P$ j3 T! oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 Q8 @# y5 F* n6 \! ^McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */8 v1 a- a8 K! b* k
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! ^5 B. k& _( c8 TMCASP_RX_MODE_DMA);
; I1 k. M. l, n ]3 Z# UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' X: `' y" T! m1 y
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
$ _3 p. |, n5 w, @7 c& RMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) E( m A# r3 u# FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
Z2 U8 W# A9 ?7 PMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
0 P" u. _& H, B3 T& T% D% e4 _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" k! G9 h, A3 AMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ @& o7 q- g; wMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
+ A3 k3 ?. o& P1 t7 d3 F8 w! u, lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ [: H6 z4 [' E' a2 S0x00, 0xFF); /* configure the clock for transmitter */5 @9 ] z0 C! @, c- W
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: p$ M0 b$ p7 Y9 x3 u: L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
, `, C8 L8 n+ ]( y; _% k" NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( N# b" l4 D( i$ u4 h, j
0x00, 0xFF);
2 Z/ q( X+ q, \: |# K3 ?+ I5 U( ~% ~# O6 K8 k8 K7 T/ b7 k* R! u
/* Enable synchronization of RX and TX sections */
+ Y6 l7 O y2 Y5 ]: P4 a J1 O0 KMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* I% |: [' M# b( c* K: ?, x7 wMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ c& W: _+ H `( N- I- r. {
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" C z4 m4 |( L5 E6 U N& D
** Set the serializers, Currently only one serializer is set as/ o% {, v# n8 c9 P0 u" l
** transmitter and one serializer as receiver.1 t9 r4 j. H c
*/
+ n. c# y* w5 ?3 d( h+ r9 qMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, q) t5 ]" Y4 i3 F5 X% ]7 m1 @" l _0 HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
i. J5 J9 T {/ C** Configure the McASP pins ' s1 U- }# {: u) @/ e* J
** Input - Frame Sync, Clock and Serializer Rx
. D# t/ G0 Z7 W/ i7 _** Output - Serializer Tx is connected to the input of the codec
5 G* P# B4 `% B; ~- x*/- U# R# ]* b5 F) [. t
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);! i. B7 P& e, i* [: R. p* H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" e7 _* X6 u2 U8 o8 V. U" HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 t" o! v2 s2 e. q i! t5 h| MCASP_PIN_ACLKX; E, d( {$ ~4 o. m; O: t! G
| MCASP_PIN_AHCLKX( v, F6 [* i' ]+ D' A
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 h7 L/ ]. i- u) _/ TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ q; d7 h. Z* z5 n& S
| MCASP_TX_CLKFAIL
( e* o, m9 T2 Z7 f| MCASP_TX_SYNCERROR
! o1 V5 |4 J) B) c8 A| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ T2 X; ^6 w- S8 t: C- F7 || MCASP_RX_CLKFAIL/ t3 p1 i* |! n$ k. D$ E, S+ t Y
| MCASP_RX_SYNCERROR ! \: o. p4 \" p
| MCASP_RX_OVERRUN);
1 v) g4 O( B1 \2 @6 z} static void I2SDataTxRxActivate(void)
" Y7 O0 l' t+ w/ j! d+ }{; O9 k2 j% t/ H& V
/* Start the clocks */
% U8 z9 I9 V, aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 @& i2 V+ W( r
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ w, d9 ~: I' a% N# a
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 _! k" I! W2 _6 o. K/ sEDMA3_TRIG_MODE_EVENT);# @5 d) |( V [) m5 x/ s! @1 O
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ t( Y4 Q/ \# U/ rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: Z6 h) W5 F t. v. M) f9 R7 SMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; u; ]: J5 O0 ^McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 r) q: t( B& d" twhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 K% o% ~. U3 V% A5 f, F1 v aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ q: X) q7 K0 X. i# }! HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);1 i3 k) L, ^) a2 Q. W& S* R6 |
} ' {8 b& d- |$ T6 m- ]" M* o
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / Q0 @6 C2 ^8 `! \( y/ r( O$ `7 B
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