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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) I* B I; C( Einput mcasp_ahclkx,; g4 w; m, o5 M' h6 ?
input mcasp_aclkx," `. ?0 ~1 U5 F4 V& Q3 r
input axr0,
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output mcasp_afsr,' v* M! A6 d3 ~) u1 v! n
output mcasp_ahclkr,
2 @ _, }+ n$ R Z5 e0 uoutput mcasp_aclkr,
8 \6 J' v2 A$ m2 voutput axr1,; |; a4 m* U# t8 l; M7 I8 n
assign mcasp_afsr = mcasp_afsx;
4 x6 ~/ ~& M' S3 w9 Gassign mcasp_aclkr = mcasp_aclkx;: c9 w& U ?4 q6 J% ~
assign mcasp_ahclkr = mcasp_ahclkx;
3 }8 q0 D; \; y( kassign axr1 = axr0;
3 l3 O+ }- m9 ]. f% i* L- \, k+ k) v9 z: M
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 l. a1 L6 w) y
static void McASPI2SConfigure(void)
3 ?( }7 X8 I! @4 j{5 V( i& y! H6 W* C. [
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 U2 h, d$ x2 \/ tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 a/ k) g# a+ k8 f, s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); z. v( s! u: d Y# v
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- f5 x+ e* X3 t) x! T" p- z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ~$ Z# {$ ~% g8 k/ X
MCASP_RX_MODE_DMA);
+ Y9 Z' d% F& s$ oMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 B. [1 t9 Y0 A+ s: o% B
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 w! r' z; W( u0 W, ]
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; t: f" W) e5 r+ JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ O- }3 ?# u) j( Q) A
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" f1 v9 b& [5 lMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 |, _6 {) w/ Y
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0); @1 x, W. p; t
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % [! u) B8 X3 ?
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) |8 @! O) {* x2 H% B
0x00, 0xFF); /* configure the clock for transmitter */* ^6 z9 {- z5 s6 b/ `9 x% O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
% r7 [9 T3 v! s* TMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); j2 N b5 M5 d! d2 ^& x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, T; o: }. N K1 S' d* n
0x00, 0xFF);
; I9 y& p7 [; N) n1 |6 s! J5 `4 Q- c$ g5 @
/* Enable synchronization of RX and TX sections */ 7 q1 N! s* [/ x. o) m- ]2 O+ x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
- L, V5 D* Z% A8 \6 Y5 U# pMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& }4 {6 f& Y9 e# j. H2 A0 @# h$ I9 TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 n) N+ r2 G6 I: m [0 {! [** Set the serializers, Currently only one serializer is set as
/ M- _' j6 t8 N5 E** transmitter and one serializer as receiver.
, I6 N6 V9 E0 v6 p D* F*/
_9 o% w; X8 A- f6 A( wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% D# P( f( R1 e7 gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' G- f8 C- h u$ n+ I- m
** Configure the McASP pins
5 Y- n; c) f% L* q** Input - Frame Sync, Clock and Serializer Rx- {1 [ g) A, F; h+ F7 x% {/ O2 ^
** Output - Serializer Tx is connected to the input of the codec
& B. F+ B# X) ?+ }- l7 K*/6 U0 B M. @, \- l& B9 w7 i5 Y3 [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 ~+ w6 q' w2 ~% b* E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, c: I8 C+ X( Y' n5 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ h7 K7 S M3 d& [/ U" P4 ?
| MCASP_PIN_ACLKX' P7 c+ h1 O* P
| MCASP_PIN_AHCLKX
4 f3 ?, I: S1 ^: U# D# m| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! e+ Q- ~. F, U {5 b$ V6 ]# o# vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # f3 E% \- L- h C4 Z9 V
| MCASP_TX_CLKFAIL
. q; B) Y A# K| MCASP_TX_SYNCERROR
' ~/ q1 O1 l0 ^ E| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( l5 b. K$ J. ? P! H# l3 T| MCASP_RX_CLKFAIL+ Z- O h& w6 s5 |$ a# D
| MCASP_RX_SYNCERROR |, M; L& B8 {9 O2 d
| MCASP_RX_OVERRUN);: s# y, l5 C- F4 l
} static void I2SDataTxRxActivate(void)
" i. O7 z, N" v$ u2 @, l. p2 w{
, n+ h6 s+ g) z9 x. ?! h+ z) ?+ U/* Start the clocks */
9 M8 X6 c: ~& N% Z9 rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& l4 v/ y" Z0 v4 j% A% h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
g$ F+ h# x* |! O, _1 h2 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; n$ ]' C$ C/ ]6 H) `# h2 [$ [; ?+ J& \EDMA3_TRIG_MODE_EVENT);
6 r- G; U0 s& a d/ F6 R: A' Z TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , F/ L' |( I) U, J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */1 L* x: k. V# X/ a ?1 m
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) W8 O4 C# O8 Y% o5 E1 sMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ q' J$ a! u: l! Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ t# U2 s& n- N0 Y" z* E
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; X% K+ @9 r; b7 Z [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% |0 j; f# \! c}
2 s. @+ p; @, C5 B! l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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