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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- v- w% c' P- _4 j2 S7 U
input mcasp_ahclkx,
, J o. H5 R/ s0 R& l0 linput mcasp_aclkx,
- O" |4 d0 S' k1 @1 Oinput axr0,
7 ~, [* ~, E. y& P% K
5 ?: K) N2 r% e" k6 voutput mcasp_afsr,
) {! `& q2 y$ R6 s, G- ^: Boutput mcasp_ahclkr,
: @7 V3 a+ [- q/ B8 O' koutput mcasp_aclkr,: D: P5 r+ | @, F8 \% B
output axr1,6 ] c d o) U7 D) ]4 w* w
assign mcasp_afsr = mcasp_afsx;
2 | z( i" S( W2 [ O/ Massign mcasp_aclkr = mcasp_aclkx;# L3 M* S' L5 B: a
assign mcasp_ahclkr = mcasp_ahclkx; f# M0 k4 {& M+ d6 M) {
assign axr1 = axr0; 2 X3 I7 R5 Z, N. b. q1 t
- n1 R+ v+ O8 T; @# Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 $ z( u) N. h' e/ p
static void McASPI2SConfigure(void)
& J1 e8 E7 k* r$ ~{
: [9 s6 K2 w* M) KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
3 w4 w/ |9 w: P% s. LMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! c& k- v a1 E, l- _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ T; y; d; X9 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 T) G$ K5 n+ i: r% r$ R# M
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 X: C! s) b7 ~5 K1 v
MCASP_RX_MODE_DMA);8 O$ G4 H) f. w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; j: t1 O/ P2 r7 T0 `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 ~6 h! o% \0 D( Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 k' B8 G2 p- U3 ]" zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( O; t% s. Z" f/ c9 A7 X6 iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# W: A- N5 l& i7 EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 `( ?7 M$ Z3 C8 s1 X* q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# h9 N8 k: z9 m
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* q1 r$ `& E- a9 lMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ N8 o. S& D3 L$ h) _0x00, 0xFF); /* configure the clock for transmitter */
' j: M* | U# s; F$ sMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 q7 F, {4 x8 Y6 X9 N7 VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 H9 r4 Q+ \# q+ cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 w, p) h: l U& L* W0x00, 0xFF);
, K: E$ h! V$ C9 ]' ~
+ H4 `/ u: X! L' d: V3 S7 @( x/* Enable synchronization of RX and TX sections */ 0 ?( Z. ~) t, B' P" R/ `
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( {# ?4 s* V+ ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% W$ X1 y- g: ]) S/ X4 K, ZMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; G) N8 V. \/ J& P" y** Set the serializers, Currently only one serializer is set as
" D' W( I' e. s# f2 n. W7 X5 F; N** transmitter and one serializer as receiver.) d: v! o3 u2 ^, [
*/. E" M2 x5 Z, @$ F' m) N5 o) }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, A: v: x- `7 r# Z3 C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 g. x+ G+ r% x8 R* a; E: k/ m( \** Configure the McASP pins 5 ~/ E6 G M0 X* d4 |. k
** Input - Frame Sync, Clock and Serializer Rx% A' |4 A% {' }. L4 y, y6 R& o+ p
** Output - Serializer Tx is connected to the input of the codec
3 u) D9 m2 X2 w% u/ z0 k! S*/
# z! V( _! V. S2 HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" _ b I6 C- e0 U5 Y6 Q% z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
b; \6 I7 Q6 F3 NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) r( L. c5 _% c$ m| MCASP_PIN_ACLKX
2 Z: [* q! {6 r& _| MCASP_PIN_AHCLKX3 h5 S/ s. R+ m; g8 r0 t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 Q: H5 ~' E; [1 ^McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& D' Y$ D' x5 T| MCASP_TX_CLKFAIL
/ }5 U: T) c) c% ?| MCASP_TX_SYNCERROR' R/ k* J- Y& r$ | j' c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ R/ b# ^# c: L6 C% T, |! g4 g( W- [| MCASP_RX_CLKFAIL
) i+ r% J$ {7 e& z) z# x1 m| MCASP_RX_SYNCERROR . T+ z. w2 ^: R+ `8 N7 D
| MCASP_RX_OVERRUN);7 M2 c: q9 a! D4 T* m0 ?9 T
} static void I2SDataTxRxActivate(void)
( r A) [7 F- c; a0 r{
6 B; x+ Z8 m3 @% P/* Start the clocks */
d4 \ ^ H. e( FMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( ~+ G# X1 f* T, h+ W4 w# H
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; K, ~& p+ V/ p- b" J# n; QEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 ]: \) u, ^" j% WEDMA3_TRIG_MODE_EVENT);
& J/ v6 ?4 ^' j6 Z2 cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 u& z8 a7 t& Z* o- P6 w5 |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 j7 i4 M) ?( _1 [. Q, x. pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
" a9 N2 g3 ] H; o2 p) YMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ ]; v# o6 E, Iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 \5 g* ], g2 p9 ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
" ^5 h( n( N& NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
" O% z4 z2 D2 v; K}
# F2 K1 j' k: P7 \3 \* ? M+ N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : r6 s4 o* {. r; U, @2 Y9 ?
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