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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; K3 y: l, |0 \9 L& U) t" B4 R
input mcasp_ahclkx,2 l ]; y: V z& J* [) x* r& E
input mcasp_aclkx,
8 }/ B; W: I& w( o3 E. Z Yinput axr0,- Y" Q; u+ @ W4 P( X, ]
; ]% O* x/ d5 W+ qoutput mcasp_afsr,# ?1 k' v: w! e5 p
output mcasp_ahclkr,: _# u1 e& s: |
output mcasp_aclkr,6 j+ \1 ]* t) v5 j3 J
output axr1,
! j' F+ D0 o7 S: J, G8 W assign mcasp_afsr = mcasp_afsx;! [( t/ S0 K+ ?
assign mcasp_aclkr = mcasp_aclkx;
/ I( R$ Y) E' M: w w! d; Lassign mcasp_ahclkr = mcasp_ahclkx;
( [- W5 E# s/ e6 ?' S; W" Uassign axr1 = axr0; 3 a/ B; o" T, U. a& q/ {% x
) u* p$ P3 T* ]8 x' U: j
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( J" A, J8 m7 S: g
static void McASPI2SConfigure(void)
. }! u) Y) b1 O# G" `{
, |: l- c1 g; @2 h8 MMcASPRxReset(SOC_MCASP_0_CTRL_REGS);# }6 q4 w/ a3 h7 M g3 R5 w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( c& n( T- ~. u7 gMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 m8 U+ s3 }( V' ^+ n5 t$ F% Z5 E
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- Q, n7 j) v! X+ h; ]9 t* n# I
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ ]) x# [; z& q$ }MCASP_RX_MODE_DMA);0 K+ C3 {" g! Y3 s8 b- p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, H) Z. n6 F' t& ~7 M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 ?, H+ _2 {' a0 u) kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
7 R B Y+ I$ A" ?" rMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 W1 |+ [# d. ]2 {/ h. ^. h: kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# c+ b8 `" K3 ^) qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */1 f3 O; U& o& U8 @) t' u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 t1 z0 w1 u A9 N/ E5 l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); h/ s8 B8 _9 k! O6 A2 V: v, v
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) p; O" B0 ?+ l* }8 z) @0x00, 0xFF); /* configure the clock for transmitter */
, V! t8 G* r4 }0 i7 \$ V1 p% ]McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 \4 [, [: _* w5 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , j) u; M! W; M5 W9 ]" | o% e
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
J( D9 D" Y6 |9 N0x00, 0xFF);
/ s7 F" r* {/ y. S& z- `4 ?- F2 M( A0 t8 D4 E' D& p
/* Enable synchronization of RX and TX sections */
' h0 J6 N% Z f) n; W7 k7 xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 T8 @) y( j8 B w0 r+ {2 H( Z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* Q; n4 L4 }: E' M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*. q2 R! J9 u* g9 \8 O% k' e. x. ?
** Set the serializers, Currently only one serializer is set as' C, j7 H. }: _ N$ T# P& y. b
** transmitter and one serializer as receiver.
. m* h$ U1 U% Q% O/ ?*/; f0 W# c$ [) t- w! e; v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);+ R. ~' K$ M' p% K8 a
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* `/ W' n5 W, N/ f! \7 x4 n3 }
** Configure the McASP pins
8 R" d( G1 o7 d1 m** Input - Frame Sync, Clock and Serializer Rx
2 u$ o% |6 T! A4 Z** Output - Serializer Tx is connected to the input of the codec 2 X7 b4 q; R% n! Q8 }/ P/ y. |' ]
*/4 Q) |) h& Q# b0 v, c
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);5 _ F! ^- d/ q* R7 b) W0 W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ y) c% P6 L# ]- K- u. y8 i9 G3 k: HMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 @9 T1 q3 `" D
| MCASP_PIN_ACLKX# G& u% k# X% q z+ I
| MCASP_PIN_AHCLKX
6 f7 e8 M7 k* V0 x| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */" y$ a- h) c/ h
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 _3 \9 }; k& v| MCASP_TX_CLKFAIL 1 w- e% p& `- X X
| MCASP_TX_SYNCERROR& N# s h5 ?4 h P3 `
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR , v6 f# s3 B! O, W# K/ |
| MCASP_RX_CLKFAIL
* x% A' `; D. x$ W# f9 M9 V| MCASP_RX_SYNCERROR
7 {2 m) u) ]2 w6 U5 w| MCASP_RX_OVERRUN);. |& @! n. R" L2 b. n
} static void I2SDataTxRxActivate(void)7 b) Y4 }. F- C
{- I* Y! ^5 Z2 Y" s
/* Start the clocks */ O5 |( K7 L6 _9 C- {2 X& T1 E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);( y- k# m; O7 n9 S* S! G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 G5 }8 T0 g/ Q. p c, X( y) HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 Z) W- r8 L# i/ Y8 E# h; z# E: |EDMA3_TRIG_MODE_EVENT);
' Q0 Z$ z% A! o* Q1 JEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: M7 D% ^: I( ]- \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* \7 [6 V J+ V9 g3 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 |% V; k( @$ \+ r, g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
s- D# n7 v; Q/ O' x1 bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* d) Y' K! w2 L I. G) yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 z7 S, R+ U5 j" O+ b; ]4 f, EMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ r" j9 h+ G) R. b4 `
} + T2 K2 M% S5 e- p, f% \4 d2 \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 O8 W' e! p1 ~ N* F; F, d
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