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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 w, O' P& n: A' `" j: oinput mcasp_ahclkx,
m3 E: e5 w3 L3 n8 Binput mcasp_aclkx,
; p2 T: j. T W5 P: g) q8 q! Yinput axr0,1 o4 V- A' p7 E& |
, \7 |1 t! I4 n+ P# houtput mcasp_afsr,
. R1 c# X+ c9 i6 p/ N$ routput mcasp_ahclkr,( U, z' x+ ?. v+ ?# R+ Z3 F
output mcasp_aclkr,5 m( [4 O) }5 W! e; @) `
output axr1,
2 z. i- j" P; j j- m% M @1 l: w assign mcasp_afsr = mcasp_afsx;
, m& p, h. |. Y4 ? Yassign mcasp_aclkr = mcasp_aclkx;
1 u# [+ c; r1 J7 i6 rassign mcasp_ahclkr = mcasp_ahclkx;: t: |( @2 l& T% k! I- b/ m
assign axr1 = axr0;
5 r. G+ A9 i, k+ [4 f5 P9 W; ?- {* [8 ?: u7 S3 j }
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 ]8 v3 Y) r x8 i; _ P P
static void McASPI2SConfigure(void)0 S; z, A7 y. }4 T! ]$ E) y
{
" `) j. E6 x/ X2 u. B0 q- dMcASPRxReset(SOC_MCASP_0_CTRL_REGS);' B/ n* Y4 D8 ?7 Z# U8 m4 `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# o4 W3 e" B/ k* @
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! `& D* |' g2 y. j& z5 ], jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */! f3 S# j) ~$ S* q" y v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- o9 `+ [* J/ _1 k
MCASP_RX_MODE_DMA);2 n! U! ?/ _9 x8 `- K; t" G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 l3 z6 f! _* J1 {) h! A4 B! n
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: m' v2 A: k$ Q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + @4 E0 X5 `8 V1 z" u7 n9 D
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);4 ^! [% j! f# e6 H$ Z L P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( ?* Q2 d$ e8 X
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 f% `7 O& q* k7 Y( v0 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" e+ f- S5 `, f& QMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - H% b) O; ~; \' h5 Y- S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 e* w5 [, ], f9 O' I: u, n k, P+ n8 l
0x00, 0xFF); /* configure the clock for transmitter */1 E0 Q7 c! J6 h, }
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
, O0 \" M( B2 Y7 L9 k# Y. PMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , N; R- ^. ~0 T3 x
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, D& k1 t; p7 d) r5 i
0x00, 0xFF);
1 {& C6 u% r$ J" f" n7 N& a: Y
1 Q' T% c4 K0 S$ v& T/* Enable synchronization of RX and TX sections */ ' E$ `* n; g3 B4 ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. i+ U! q9 l) r8 N1 O7 i% l Z0 cMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ B* ^4 Z) e) W# R6 hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 e3 [# ]: Q) A8 L
** Set the serializers, Currently only one serializer is set as# d0 |* B; m$ J1 h6 i# }. |# ^
** transmitter and one serializer as receiver.0 ?% I- `9 {2 i) g* Q
*/4 b+ O6 w$ `# B1 o+ D
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% M9 \8 V' p# K% J+ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) }$ n- {# j' y( u
** Configure the McASP pins 4 g3 p& X' {- D3 q) g9 D9 F
** Input - Frame Sync, Clock and Serializer Rx8 E# H" b' c1 s% `5 I) J
** Output - Serializer Tx is connected to the input of the codec
$ K4 t7 |2 }* t*/
8 T! G) A, I& {) XMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ u+ j, ]7 ^. I2 J
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' Q( |7 l' `+ m; F! A0 I: V, b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; _, k: O( a$ C! ~| MCASP_PIN_ACLKX! h1 C3 k7 U' Z4 z3 ^
| MCASP_PIN_AHCLKX/ |+ t+ C. T5 f, ?; @7 C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 \. z" P5 f, i2 ]& Z2 s, WMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# s4 }, B1 O' n% D: `; f6 ]* g| MCASP_TX_CLKFAIL 3 P+ K: O( x' r! b( s, S
| MCASP_TX_SYNCERROR( U+ a1 W) ?8 ~. f
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
- ~; y* C+ s% a3 B$ d* R0 ?| MCASP_RX_CLKFAIL' N: h: s! c8 N0 n
| MCASP_RX_SYNCERROR 7 y& Y& W& e. @" B6 K, O. f {
| MCASP_RX_OVERRUN);
% u8 J8 R, s) I6 `5 l} static void I2SDataTxRxActivate(void)
/ K+ Y# t3 I9 l/ u2 a{) F9 G2 h0 x6 J
/* Start the clocks */0 [* y2 Y+ T* v- k2 ~1 g2 O3 O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 ^2 D9 E2 a7 |" z. e' q
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */4 |# `% [: a& x2 L7 J& b
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) ^: J, [$ j! `3 y
EDMA3_TRIG_MODE_EVENT);
3 |% ^! y( h2 \) W( T/ r: yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 \5 |) O& M1 u. NEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. _2 w: p0 d. RMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ B) Q" X( S9 f. i* w$ A( mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 h% G) _3 p6 ~& y5 `# d% g, fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */6 R3 q' W( k# I5 f6 F( ~* ?) u7 Z
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 ?, T+ A0 m( E8 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ K8 Y' i' ^8 u+ K* k; u" m& X
}
8 X% c# [6 s( d; H请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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