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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx," J9 R$ t2 @1 U$ K0 T
input mcasp_ahclkx,
6 X; N" P/ m0 o3 ~input mcasp_aclkx,
2 F2 u: T" n) A$ R4 [! k& {6 Uinput axr0,6 z1 q& J: n& L# m: G" h' W
: J3 g. `& N# H' p) r; b1 m4 v* [output mcasp_afsr,1 V4 t8 w l2 `; E8 D+ e
output mcasp_ahclkr,: V# H; U: \- s w6 d4 O) c9 d
output mcasp_aclkr,
+ m0 t& G5 y! T4 Ooutput axr1,
8 u. E1 h- C) E' l assign mcasp_afsr = mcasp_afsx;9 J& y: c3 `+ z
assign mcasp_aclkr = mcasp_aclkx;
- E/ y: d# F3 C, ]7 R, oassign mcasp_ahclkr = mcasp_ahclkx;" f6 ?; B/ w4 g* A' r
assign axr1 = axr0; 8 C1 y* Y ?7 u1 V5 K I
& H/ |1 r! [$ J8 r/ L. k j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 @/ g* j. Q8 D5 jstatic void McASPI2SConfigure(void)$ y. T# l. I3 R! `5 f; u
{ z+ @7 ?4 q( U9 B& z5 V; o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- _$ a {( Z2 r' I1 A0 }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: U+ ^% K4 q3 l& [- k, o9 xMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- Y5 D: j+ f7 ~. d9 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 l2 {9 Q4 _* A. G9 w# g! a& S
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 o U# z. ~. Z/ }1 @MCASP_RX_MODE_DMA);) A& X! x' V) i- k3 l/ Y+ ]1 _
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' O! c2 A/ u8 Q
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
) ?# Z) b! i# ~$ b: O! eMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 a1 a% P3 p- j5 t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' D/ y2 L8 S4 h* s( aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# J' D- c; U# \8 K' ^1 m; kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 X3 C m5 }/ e3 ~6 v! F5 v1 O( S. O& R
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- J' E5 L' {- d `7 [( ~9 R, w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 H! i8 J3 j0 o! _3 r/ d$ UMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ~0 S$ E. i2 F: F
0x00, 0xFF); /* configure the clock for transmitter */7 R I$ `5 {. A! S+ y: b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; [# M8 V3 Q4 u' J; zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) u* }; R5 e' n' N/ M, r8 X$ u2 }: GMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
4 i+ k% Q& f S# q( D0x00, 0xFF);
5 K* H+ r, U \ _4 @% x* _
1 u8 t4 r& Y c) Y: K/* Enable synchronization of RX and TX sections */ + M2 q4 o- |3 a8 Q" |' J
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
1 J4 m4 V5 M+ \! m$ DMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- _1 c0 a2 A, NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' j' S) E$ P2 K% C/ Y9 @# U! d
** Set the serializers, Currently only one serializer is set as
$ m( W: f6 x/ \** transmitter and one serializer as receiver.
9 W `# ?* F/ R, s7 g7 t) Y*/
! M/ G1 D5 w0 ~+ D: s! vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- I; g$ c' G4 n
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 n5 t" I& ^% t y. n, K2 z
** Configure the McASP pins
- [1 w, r& Z$ x# ^9 G4 Y Q** Input - Frame Sync, Clock and Serializer Rx" u4 e! }# f" c7 m& n
** Output - Serializer Tx is connected to the input of the codec
$ N! f# [" f+ P; D* P*/" X) t( C- w* n. A
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);; v6 r1 S- B8 p, Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ w) M& {# Q- O1 n; ^McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. y Z5 p. W" ~7 u, @| MCASP_PIN_ACLKX. r' E' P" y% t$ r1 d: P3 C
| MCASP_PIN_AHCLKX
( Z3 U: U$ ^+ a6 H3 l" e3 E4 h3 @' `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
" ^# m0 d# {1 I/ {/ w4 zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
, _& g* O1 [/ N1 [| MCASP_TX_CLKFAIL
, S7 ~, H& ]' d) ?0 H' r| MCASP_TX_SYNCERROR0 U/ O ]& p$ t* _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' N0 g* U6 J- ] N( {, h* V$ @4 T
| MCASP_RX_CLKFAIL
. f2 z5 e- c7 b, ]5 D$ r, S. _4 L| MCASP_RX_SYNCERROR
9 T* T$ u1 q/ B/ d& G7 O| MCASP_RX_OVERRUN);
; F) \ t+ {1 D; w0 k- Y} static void I2SDataTxRxActivate(void)
7 x3 H9 g+ U$ I0 ?) J+ h0 H- `{3 z6 t4 D, p$ f+ i2 l2 l4 s+ D! L; \% _
/* Start the clocks */+ F- c' K9 m' r+ M9 m. D2 v
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: [% V2 E+ h2 v. A" S3 D" r2 F
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ ?/ j% F8 S) \8 r" u6 m9 M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,* a* d0 q1 c1 o; f
EDMA3_TRIG_MODE_EVENT);
3 W7 v( J% B5 R1 b/ Q: r: kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ D" [- y- \2 m* {0 F7 REDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' x3 W% j$ u. \0 {0 {
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 ]! D8 W0 G& M$ D$ ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, C; Y/ F! n1 w8 [) l! m5 {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 \4 ~" K. j& ]* i4 ^. OMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( V& U$ c0 C2 Z1 Q: fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);7 L5 I8 n* P5 h$ q; J1 ^" d' U& ~
} - S, ?* c9 [) ]2 P0 t( K3 X
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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