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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* U0 ~' o( u: I& x7 g* w1 Minput mcasp_ahclkx,! \+ w* D+ R$ R
input mcasp_aclkx,
0 y O! p. a4 i" }6 Einput axr0,. b' a) w$ H( N/ A8 B* u0 x6 v
. a/ w# O }4 }$ t' C/ r8 Houtput mcasp_afsr,. f2 ?0 _; P1 L
output mcasp_ahclkr,
$ U) U1 Q/ G+ |8 y1 E, F- R$ f! x/ ]output mcasp_aclkr,* C. a& m' {# ~% P9 t+ \% N& v- x
output axr1,& e9 \3 X9 Y$ p$ R; y
assign mcasp_afsr = mcasp_afsx;# \/ f6 S' G' R1 b# k0 E
assign mcasp_aclkr = mcasp_aclkx;: ]$ |0 Q2 I# `% N! ]( E
assign mcasp_ahclkr = mcasp_ahclkx;8 f& z0 F6 a6 V2 B0 w3 W% S
assign axr1 = axr0; ( a4 e( X5 k% n' {8 a
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 @/ S1 q/ U; b; W2 X. _7 ystatic void McASPI2SConfigure(void). t' Y- {4 o8 n" l" ^( O) z
{
) w2 [) K4 C+ q! q! aMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 l% \8 t$ b6 `. r ?* I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */6 `; [. c+ u) j9 ]' J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# v0 M7 U# y2 W, o# m# o4 sMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 v! Q4 P" D& G! Z0 o: A4 e# N5 LMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( l4 C; o' I( ?5 S
MCASP_RX_MODE_DMA);
- x) y& @& F6 _4 p2 E& X/ yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 {; |. a/ X2 ]% V8 ^8 r/ V
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- h4 z- }7 g# p `4 u8 t( A2 }
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, \, L* y; s; @1 a5 }
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);/ e3 G* }0 B# s8 }& o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ w1 ], ~# M) v% a( f4 g# w9 ]MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- j3 P( K' H( A/ o j+ j8 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ n$ x" H# h+ [6 }" BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); @3 s' R6 K- n/ H3 N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,( @" @$ y, K* o; T, U1 [. y
0x00, 0xFF); /* configure the clock for transmitter */
/ G0 R8 z! I4 x# BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( K9 p* Z3 m3 ]8 T
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 S* Q5 x1 m/ L: Z6 x2 E
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32, f1 u. y$ ~# M5 a; a
0x00, 0xFF);9 F) w- P1 o( u6 W) i4 S3 C) u' V6 S, O
# r! |0 b; U# R4 J+ A1 l
/* Enable synchronization of RX and TX sections */
8 @8 s* f. b- h% q4 r8 Y; j7 pMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 U0 g6 g4 b, p9 @" ] m# `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( O) x6 L( r0 u& b! [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( Q8 ^, J: `- U3 [: K
** Set the serializers, Currently only one serializer is set as
8 ?0 N1 A7 V+ y: ?8 y Y+ F6 v** transmitter and one serializer as receiver.
8 d- i: | p0 h*/+ \9 ^/ n+ s0 e: _
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ k; @; z6 R5 a( w7 PMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 p' g0 | M' p7 s4 y" k
** Configure the McASP pins
, N2 {3 J2 U1 P6 M5 a' S** Input - Frame Sync, Clock and Serializer Rx
% w$ g/ @7 S. q2 j. s** Output - Serializer Tx is connected to the input of the codec
3 ^) M! I9 I- _# J( x2 }: { ]: n*/* Q' D+ p) [$ B7 x0 ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 s, S6 ^# t% D) [8 q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, Y7 A* _1 ], yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! _6 Y: M2 h3 ^| MCASP_PIN_ACLKX
" o' `4 O. t9 r9 t P| MCASP_PIN_AHCLKX2 I7 ~$ K( R3 ~# [/ Q: V$ m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */; |, J/ l9 L6 O2 Y( ~
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
( h5 P9 U8 J# S- [| MCASP_TX_CLKFAIL
7 u2 G" t0 D: A6 l| MCASP_TX_SYNCERROR
" n! |. \( x4 M1 l3 p* @| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) z& W& g5 L3 B| MCASP_RX_CLKFAIL
0 a) o1 Q& j; e| MCASP_RX_SYNCERROR & R/ X/ x% J' L% g$ d
| MCASP_RX_OVERRUN);. `/ @- ~6 J0 }9 _
} static void I2SDataTxRxActivate(void)% ]) }# n7 U+ f, W( J9 s$ w& y
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/* Start the clocks */
6 _' l% {; p7 w$ n/ zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# c! z6 D- h* x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 c! l/ B5 y; f2 H* oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( E1 i3 g' H& v. V: B
EDMA3_TRIG_MODE_EVENT);
+ S. p4 I2 j, l; ^% |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 j1 J, T, |3 A3 ]& I: f$ @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
x+ a4 m+ A% T8 l3 Z& p% aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- a" T! h+ F- Q' C% i; Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# W. Z3 g4 x& D% l: j5 h9 Z6 E# u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 P' K1 [6 ^# YMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 B; @. t& J/ a' }7 c" d, W/ GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);9 z+ Y, @0 s2 P4 M8 D2 I
}
3 I- E9 |+ g6 @0 N6 }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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