|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
( ~! A* k* u/ p& ~input mcasp_ahclkx,
% C& R1 m9 L! W* ~4 {4 N' P) cinput mcasp_aclkx,) u) B5 a, P4 f: L( S
input axr0,! W, y7 a+ w* e- i) K& h
0 y. d& x4 g ]! x& |3 u/ ^3 }, poutput mcasp_afsr,9 W+ U9 C$ i+ d
output mcasp_ahclkr,6 @' v+ e8 `6 w) g1 c- T
output mcasp_aclkr,
* k" ~! a% l: z; W" Eoutput axr1,# t! u0 ]8 k- n! g2 |
assign mcasp_afsr = mcasp_afsx;
/ j S# e; A9 R1 I! T# ~assign mcasp_aclkr = mcasp_aclkx;2 x/ ^3 R* R' B( n
assign mcasp_ahclkr = mcasp_ahclkx;
+ B: Y4 h$ b2 f) ?# W. p5 Z* Yassign axr1 = axr0; " r* K! l, T* t8 `' G, b) {# s
: [. f J/ G/ ?0 L4 y- _2 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ W+ b) y3 y# V S) j6 Y: Cstatic void McASPI2SConfigure(void)0 G3 Y/ e7 Z$ b& O7 L4 m* E* l
{$ D' @" v$ m' j/ f
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& ?6 d' X- l" i2 E" D: uMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ ~- W0 ] V+ Z( H0 S
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 Z( u V$ ~8 w) z5 z a6 ?$ EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, K) X2 Q9 E' o, |1 H# mMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ h+ ^5 a9 g5 F+ x1 G5 t
MCASP_RX_MODE_DMA);
# l* j) F' H# L! IMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- h# R2 |* F7 W4 g
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
0 h6 y3 w6 }1 ]5 q0 q! UMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( s6 a! W! [5 ?( Y! Q0 M
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 Y5 o& D+ M* z c L+ z4 DMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. Y0 q e# T4 F+ W& _8 QMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver *// N) i8 o7 O( T0 M7 N
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 M. H+ e ?% M- i
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# e; I: t- j% x( X3 _7 hMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* n& a, W! d4 j k5 S- c
0x00, 0xFF); /* configure the clock for transmitter */
2 r( J+ G1 d6 B5 m& ?& F5 N3 M$ ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 s; {8 K( H! r9 P; _4 w+ ^5 Y
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 3 P% r2 F' i+ V' [* v% _
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 L8 x4 f' L5 u2 n* {5 A
0x00, 0xFF);
* l6 p% u; i$ T. {5 w4 C7 U0 s( [7 }) W) K1 l- m: |
/* Enable synchronization of RX and TX sections */
2 j: w- E. b- O- F9 @( GMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# z% f, P& L) N+ T1 a* B& ?# c0 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
: B- _# {. e B4 ?0 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ l9 F% Y; \/ N# h/ d) N# H
** Set the serializers, Currently only one serializer is set as+ v$ X( A7 u, g1 b
** transmitter and one serializer as receiver.
8 ~. G" R, H3 G2 D" m$ P2 y3 P*/
# h7 l" E6 [; Z* p# gMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ N6 D; K- Y2 j, ^% a! p! i2 z# U9 FMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 G7 W+ q3 p/ {8 r, m
** Configure the McASP pins - h" r. u% {# t9 G. c* A
** Input - Frame Sync, Clock and Serializer Rx
/ D6 g: W/ ~! Q, L7 P1 x3 U** Output - Serializer Tx is connected to the input of the codec 3 L) L( n3 `- a$ V: V
*/; l1 u( T# k, Q
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' D' w: ~8 s( H) h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); T. Z) ~# L7 ^2 V" m4 v D
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX/ e0 b% [6 ], y, K4 }' \% b& a/ x
| MCASP_PIN_ACLKX- _7 J5 K. R) c, K/ T' j
| MCASP_PIN_AHCLKX
; _6 [/ k, o3 n& E( f4 j1 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 C% R$ Z- ]7 i+ V* k0 V1 @McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR - E4 N# c6 _7 M: l$ e& _' P( K3 H" U
| MCASP_TX_CLKFAIL
7 q* G1 h& B2 i8 w& C! O7 L- c| MCASP_TX_SYNCERROR* _$ I, v+ L( h" o
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ Y1 O) Z0 u( s1 I* y
| MCASP_RX_CLKFAIL& r" q* r4 |8 C! e6 d* p
| MCASP_RX_SYNCERROR
6 O- x+ o" a5 c/ p1 I# m| MCASP_RX_OVERRUN);
: I0 Q7 S4 U8 n8 U} static void I2SDataTxRxActivate(void)2 S( f, \- F1 T5 j! w* L. |9 [6 `' C
{
5 K* f3 V5 h4 r3 d0 a1 y! N: C' Q4 C/* Start the clocks */0 r' c3 h/ f! Q+ b. `5 y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: I# M2 _* N& D. zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; V* Y8 @8 V- y0 ]4 p! u( |EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 M8 k; m) s" y( r
EDMA3_TRIG_MODE_EVENT);
/ C) H @# k* y: S3 x: o# J oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . V- _- D8 @: n8 h+ e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 x2 v4 y! E- G- U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' Q" W' \$ g7 m) G( Q1 ]" g2 |McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ i" E" y5 _/ G) Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 `% N5 i, M" ?. b2 Q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ^8 h( e( {. w6 BMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);! }& q& a+ _! b( ]$ I$ `
} , S% r2 k+ J8 j9 B7 `6 K l) n
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
6 J& g& S, I) R- ~ |