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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
+ ?% j* [3 U$ V! Binput mcasp_ahclkx,$ B6 U2 Q% q2 D! i1 P- g
input mcasp_aclkx,) d: k( i q3 i, t& @$ o \ z1 I
input axr0,
% e) K3 m/ u9 W6 H% y3 X
* i% n! [4 s, ~output mcasp_afsr,
/ {5 e O" K* V2 L2 j2 J5 Noutput mcasp_ahclkr,( Q, E& `2 U5 F) ^0 z4 o( q9 k
output mcasp_aclkr,+ _9 T6 F& @( G* R& E
output axr1,* N9 N6 b9 {( k) p
assign mcasp_afsr = mcasp_afsx;; Z0 T! g6 g7 d
assign mcasp_aclkr = mcasp_aclkx;
1 }8 ]# U5 }0 S% L9 aassign mcasp_ahclkr = mcasp_ahclkx;( p) k/ k* f! B
assign axr1 = axr0;
* ]: _- X/ m0 X
D; p' Q9 \4 ]1 f+ m4 h! K在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 b. Q, ?; H4 i) ], m0 k& _static void McASPI2SConfigure(void)
R3 o9 G: O2 o: v3 y# D{( K$ ?2 M8 J" q% P5 r( v2 ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);+ B' T4 c% U; @) ?! p, C1 ]
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! j5 v4 ~- C, c* V, w" LMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) Z2 @! v4 u! {
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 w8 G& f2 w& N( n0 v/ p. QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! @' w+ x" T( G; x! x
MCASP_RX_MODE_DMA);
" Z9 t" ~/ r' K( j3 ?$ i; LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ v9 A5 D `6 r, q0 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots *// R/ H, ]* J0 F" V; [( d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
j1 f) I' M" V8 g; P8 M& SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, `9 ]' Q8 P$ J
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 \# X3 t5 \; [2 Z( Y+ y: tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 S, u* m5 ]/ E+ K( HMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( J. b% n3 \6 q; H _
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : a0 Y9 E. l4 y: F! q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 p& s4 k6 z' o) y& ^( n7 j0x00, 0xFF); /* configure the clock for transmitter */; u3 X! W: a3 I; l8 ~( h
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);5 J; Z8 M2 [& d) u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ b. ~! Q6 l, q4 C) K* t% pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,' M: W, D6 \* ?' l" D5 S' Z
0x00, 0xFF);7 m$ K% v3 Z$ p1 H
/ K8 C& d' M6 A/* Enable synchronization of RX and TX sections */
8 L0 t% m( z2 c* t# RMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 Y+ t; g! S: F8 G& R ~, WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; m( C* \/ | n3 Z* p: O, h
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 c& e. B: s' i: f+ }2 X5 `** Set the serializers, Currently only one serializer is set as$ ^: i( }- ^2 u5 N7 W
** transmitter and one serializer as receiver.
: K, }- n& A ?: H*/! \3 T2 b" d' j; j* f8 ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, T7 l+ X6 ]. G- j, T$ ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& L! N2 [- n* J! U5 U z% ]/ f
** Configure the McASP pins 9 \! y. v3 M3 n& J2 M
** Input - Frame Sync, Clock and Serializer Rx
3 R/ M( I: k5 A+ L, O** Output - Serializer Tx is connected to the input of the codec
% ^2 X) C) f! n: Y: T8 M*/
* }5 b8 C! w m0 W6 @* JMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) h4 a4 S* y' h( Y4 V5 ^( f! Y+ P7 @
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 q& R) D" j; }# t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' b4 m2 A' z# C7 || MCASP_PIN_ACLKX
: b; ?- s1 b+ J$ H) r" v G| MCASP_PIN_AHCLKX
- n' r9 x: I/ L. M8 \0 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
y( N) h+ D6 t% b# ]5 g; oMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. M$ E- U3 V7 v. v7 O# F| MCASP_TX_CLKFAIL
9 f/ A% }. s1 T8 N. j| MCASP_TX_SYNCERROR# Y! j* @% g( z5 L9 c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 }& C K# W. T4 W$ Z
| MCASP_RX_CLKFAIL8 T- ~' x6 W i4 ]1 P
| MCASP_RX_SYNCERROR
4 N7 s- S* t! C& X0 D m| MCASP_RX_OVERRUN);; I) q2 Y1 _/ t9 M' _1 |8 l: C
} static void I2SDataTxRxActivate(void), r9 ]& T9 B3 i: L3 W$ J( g
{
+ L( D7 l7 v2 ?7 f$ s/* Start the clocks */
& g- \$ c( \8 S- OMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 W5 x" B7 r* h" y8 g
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 K+ \) _: q$ r8 X) kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! q( {# v4 @9 _6 r, y. t* U
EDMA3_TRIG_MODE_EVENT);" ^) t& E V. J _# p' D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
1 M- o* ~8 \& l% W" uEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 |( p' J9 ?, S- O7 A( |4 K3 O+ cMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" z6 Y* v* y3 u, [
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! w: Z/ [9 ]$ N2 G, d c5 e: b0 i- e. {, k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */ r$ g% ^/ j3 ?9 \9 x4 }' e
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 f0 u' {: ~0 s, N; M
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);! z) G0 }( R8 R! h
} ! m' B9 u$ Q% X9 S8 K% F+ q
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 F4 t6 t6 p, U0 E
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