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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
" P1 F9 K6 B7 b ~0 y! ?! ]' J$ Binput mcasp_ahclkx,: ~2 D: i+ Z9 J3 J' w+ p0 h
input mcasp_aclkx,% U, P# {) U, f( w! \3 Z: C
input axr0,
6 Y1 o/ Q) P. m% q& E2 w" P& a, I) [3 L) t6 W3 U% T
output mcasp_afsr, ]9 f0 o2 W4 v
output mcasp_ahclkr,
( Q0 o1 e% d; z/ B9 K: |output mcasp_aclkr,
! ^$ k. ~$ n, ]+ F5 S2 poutput axr1,
2 U$ X& K8 a D1 e# {) d1 } assign mcasp_afsr = mcasp_afsx;8 T! @5 @6 j2 L) r
assign mcasp_aclkr = mcasp_aclkx;
* C& n6 W# }, u' V# ~( t* R' Rassign mcasp_ahclkr = mcasp_ahclkx;
2 X; p4 U- b4 T% L0 ^( f% ?assign axr1 = axr0;
3 X. O5 \! F) |, Q7 ~# P1 ^+ b4 f& u: ]+ G; v: I, e
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
& }- Q3 Z; P6 astatic void McASPI2SConfigure(void)
/ c7 n6 ~$ f. b1 p$ P7 X2 f{/ e6 T. v$ L. m- r* Y0 H$ b
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
+ L) ^" o1 P8 m1 Z4 u: s' H3 TMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* s0 P' T3 e$ F! Y% ?0 n# F3 S0 i2 O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
7 J. B- M9 C, C( r* h' EMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- y. a7 H) a8 I( V$ N) E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) S% s* Y! o5 `$ g) G, I
MCASP_RX_MODE_DMA);) J! q8 H1 @$ _* G& q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ Y* _; ^5 L/ d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* g: f* z. g+ V2 f% E& oMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
) e" G. u. G6 I V3 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
, }! A5 f- u, @$ z9 S: zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 b4 ~6 J6 q7 ?& R6 M4 z$ P9 o/ {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& w. P6 | @; N3 ]9 h- LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 G. t$ |7 U/ h, j4 |5 \McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 y& A! f0 ?2 j2 qMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ?- b: h U9 d- Y; b H9 E
0x00, 0xFF); /* configure the clock for transmitter */* N, @% p) q* x
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! ^8 M4 u4 Q5 Q& j
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # C& x# O2 _1 c4 f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 Z% d @: e+ [1 X! _
0x00, 0xFF);
% i( C% q" s6 N2 ]
. r1 g: E h" i }! T/* Enable synchronization of RX and TX sections */
1 A5 C) R. P# g0 ~- Q9 ~! ?0 P8 lMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 S2 R+ u6 s- ~- a8 J# MMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. ]* v3 R% [. e* ]* Y$ }9 R9 oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! |8 X" g) O- i2 m% A6 b** Set the serializers, Currently only one serializer is set as+ D' |8 s+ y/ J% F
** transmitter and one serializer as receiver.' t8 I7 v- u/ }) r# `& x3 C6 f
*/
9 r T2 l# k. f7 f/ bMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! S$ y7 J) b# v
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** Q* M) I' t# r: f3 J% E
** Configure the McASP pins
, D1 X5 o, V2 }2 T. o* ]# ^** Input - Frame Sync, Clock and Serializer Rx! q; l" Z+ w& s, r: ^$ N
** Output - Serializer Tx is connected to the input of the codec
, V3 }0 V' B4 a* k f! G*/7 y( p7 U3 N6 @, \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
% R" U5 [" I2 p. Y3 G" [McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' [9 e7 q6 W: o9 Z" oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX W' z' b8 m7 Q7 y; x) j
| MCASP_PIN_ACLKX7 x$ t4 T; B% p2 f% r/ u
| MCASP_PIN_AHCLKX
( k* K. J& K. {5 L| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// {4 L: }. |* D' ]6 A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 3 s; k$ E" D* C B% J, Z9 M
| MCASP_TX_CLKFAIL
0 i7 O8 M+ ~2 l' m3 T| MCASP_TX_SYNCERROR
5 ?. t- e) P8 y; ~8 l| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( ~! A/ j* K- `) `| MCASP_RX_CLKFAIL: o# ^7 B& V+ `
| MCASP_RX_SYNCERROR _7 h- ^, |0 b9 z3 e
| MCASP_RX_OVERRUN);
- n) X6 w; \: t} static void I2SDataTxRxActivate(void)/ y, ?/ Y+ r2 V$ Q( I
{ w9 s1 d, U0 x8 g5 s+ V% I
/* Start the clocks */* Y7 m0 {- V6 L) O
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);0 G: P7 j# R# Y2 p2 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 V( E- Y: l: e2 u+ sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
, Y& z( v6 v. o* ~( y+ JEDMA3_TRIG_MODE_EVENT);
, r* k3 k$ F: f6 ^: F4 b1 B. zEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; K, n) F; W9 u$ b. C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 X* o/ }' Q9 {: h5 ]" w4 g
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. ]6 o0 @7 B( e, n4 ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
' A' b6 N/ c# j# iwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
1 P$ g2 O0 z1 |8 BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* H" \ b/ a' R tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" V1 x3 y( w! m" K9 j3 v/ a
}
( C z0 y0 E5 @请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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