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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 h8 C( [! P" l8 @/ u4 X& }input mcasp_ahclkx,
% {3 W6 N% T. X. S: y) W* @4 ~input mcasp_aclkx,
' q! E9 s% P: o: Ninput axr0,3 ]4 D# {1 p) J0 C7 I+ {8 c8 L9 p
" F# t: S6 p/ e3 Youtput mcasp_afsr,. f1 l+ u; _/ ]% p1 o
output mcasp_ahclkr,% r9 B7 j# f: q7 r
output mcasp_aclkr,
+ c% w" y( P# N% X# d6 poutput axr1,/ ?9 K7 M- G# L( k( D( E, n
assign mcasp_afsr = mcasp_afsx;
0 A V) ?3 Y& F1 O4 {assign mcasp_aclkr = mcasp_aclkx;
1 c! E7 w1 N9 a7 V5 U( n7 _6 ~- [assign mcasp_ahclkr = mcasp_ahclkx;
# ?# @; [ o) ~$ yassign axr1 = axr0; $ ^! ? X5 X7 [! y) U6 b
! H8 d9 f& U$ J2 Q+ C
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
+ t1 W7 U7 l7 o# ^/ B3 R. sstatic void McASPI2SConfigure(void)
6 }( Q! q6 W. z/ l/ Q{0 R. t4 ~7 L! d, x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. U! t" [1 l" p U$ Z, {McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 N' v5 Y3 n8 D" J
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 ?$ g" x3 Z( F4 D" G3 A2 T5 J2 ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 M& z* K- z# x* QMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% N3 I- B' a I u
MCASP_RX_MODE_DMA);2 y" u' l; z4 k3 i' @& P5 Q( @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! V' b, S, @% z* UMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* S2 j# I4 L; p4 d3 K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) E* k2 N3 w! P0 V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 x% R7 E- s# H1 k$ rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + Y2 g1 D a5 r
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" o" }; Y+ x- r7 LMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 Z7 J2 B2 i# S" {+ e6 f- h3 }3 P
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * x0 C U, D; F8 F$ b, e
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
2 n- H0 J' Q+ J* j& f1 Q6 G+ L0x00, 0xFF); /* configure the clock for transmitter */
6 m7 G, N( X) n% jMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! l" ~. ^2 d- L. S* z* |* w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 s9 f. x; d# G) v3 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- E' V" B% o! O; L3 z0x00, 0xFF);
! ?4 o8 S5 C" I" v9 S6 D6 H% T4 T- B" K: E& r* {
/* Enable synchronization of RX and TX sections */
: z" Y$ y% A8 NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
4 M9 G `# j! T* }! gMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( H+ k; J' h) z. kMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! x2 o; |- U3 h' z8 E0 f1 J2 p** Set the serializers, Currently only one serializer is set as& x5 S P# N" _, l& J
** transmitter and one serializer as receiver.
3 Q5 v; `9 K, o% M r/ n* e" y*/
( L: D1 v7 Z% aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, N4 i$ j9 E2 E# n, A. M( iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 S7 P! c' p* @9 t7 ~ |
** Configure the McASP pins
" v5 `+ i: s& \0 W** Input - Frame Sync, Clock and Serializer Rx& d' j' P1 [, o0 e9 z9 G; D* [
** Output - Serializer Tx is connected to the input of the codec
. k9 X# N H5 ^9 G$ D% f# h P* T1 ^*/+ V" [$ I) X0 D7 K$ o0 Y& K
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% i$ ]& d7 Y: M0 C! u; g. C
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& G: w5 V9 ]6 z" ^
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX: L, |# M- h! ^ O. s7 l
| MCASP_PIN_ACLKX
5 N; x. F, Y# W" o6 P; `) u| MCASP_PIN_AHCLKX/ r: V2 i S1 y. N: d5 d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- ]6 u# N* l" a2 Z ]9 x% A
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 Y, j6 Z8 Z! q/ U| MCASP_TX_CLKFAIL
* H! Z% O. O7 M0 T& i" s b/ v| MCASP_TX_SYNCERROR
4 P. G; T6 O+ K: D9 r| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
9 |. l5 o1 y/ A, J! M& U2 q. u6 L| MCASP_RX_CLKFAIL; q0 \* l: m" K/ ], U2 t
| MCASP_RX_SYNCERROR
5 F t2 _6 Y0 m. {# u( h0 {| MCASP_RX_OVERRUN);, y k6 z. |* }
} static void I2SDataTxRxActivate(void)4 d7 ]* ?8 k r; R; v8 I% B! d
{& w6 l$ ]% _9 _1 V+ ?) t
/* Start the clocks */
! u/ \+ R% l8 C! EMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 l5 o. K0 \0 zMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& m0 ]8 a+ u5 Q' MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# N1 e Z2 i, j9 N: Y" {
EDMA3_TRIG_MODE_EVENT);1 F5 U- e% N% o# k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! k- n+ z+ {% G& r9 wEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
. l) G' k* E3 bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) j: a b) S; r0 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 @4 `" @. y2 o4 Dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' D* H" D! E3 Q5 N4 H
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& `, f' N, x" u" i2 j( oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);5 y! j+ X* G2 y4 {/ K
} ( H* L) {* x# U; }# [8 _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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