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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- G: l$ R( H! W ~: Ginput mcasp_ahclkx,$ g" y. i* t8 |+ \* }/ o
input mcasp_aclkx,
1 ]9 G1 H( Z- i+ |, D/ Zinput axr0,
3 g; y6 ?7 m$ s0 o. p4 U. w8 w; P9 i, a# { V4 p. \
output mcasp_afsr,. c% l- M) N9 i) R" S
output mcasp_ahclkr,
& l) m, t3 @2 _) S; ^. H5 xoutput mcasp_aclkr,
& V! W B# I& l) f# doutput axr1,
- R" t; F; S" W assign mcasp_afsr = mcasp_afsx;
* ? Z: P6 Z/ n. c6 oassign mcasp_aclkr = mcasp_aclkx;
: G+ _, F+ l* E1 Fassign mcasp_ahclkr = mcasp_ahclkx;0 u2 g3 L5 f( H
assign axr1 = axr0; # k$ W1 E! A9 T; }) q9 q
1 J; H7 a- z# A" \1 w+ j P在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' S2 H: w/ [7 ^1 y4 M% }' J0 P+ i! L0 ^
static void McASPI2SConfigure(void)
4 u/ h1 Q! f5 ~0 A9 L( ]{" R% B( o8 l8 z- q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
) _% K, T" S. S9 e9 T6 oMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
4 z+ D3 R* Z2 iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ \& D# D0 {- N) t" y+ |5 [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// u$ J; J$ u# m$ Z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: ~* L `$ Q) K5 wMCASP_RX_MODE_DMA);/ G! \; k' g* w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 | K4 L4 q, c! A1 t: w/ \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: ~/ ~- C0 I5 X& A: ]" C1 v5 t
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 Y7 y' o' p, l8 y2 d/ @2 b/ |
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& \5 q/ T5 I/ I, m
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 4 N' t. v2 s4 @3 ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */! t% i j1 _) r( ?. e% M: a" r5 U
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( N& }& T& t9 \% ~1 c' ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 J" O4 Q/ L2 u- J* y: L
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 N$ W4 {! C5 Z6 }- N0 @5 N- w0x00, 0xFF); /* configure the clock for transmitter */
s. m0 Z, K8 s/ E2 V3 S7 ~McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( O3 `$ `% @$ U- Q: |
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
I" x6 K, j" LMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& T @# V7 y1 m7 x3 w0x00, 0xFF);
/ R6 l8 @7 K; t: Y" N9 N% G$ ^0 y/ h3 H+ g" _
/* Enable synchronization of RX and TX sections */ / O2 N0 O. g( T% ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ I8 B( `$ M* b; h- AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
% A# v8 a8 f. S+ g! hMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
6 d: C2 P" x- T7 ?9 z9 O; ~. b** Set the serializers, Currently only one serializer is set as( F# Y3 W* j1 b- ?+ [1 E
** transmitter and one serializer as receiver.
- O* ?, A0 h& m" e, C*/9 x0 [1 R' ~- u. y
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 j3 J: S1 l( Y+ MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
, G F; c/ y1 @/ |9 E* A** Configure the McASP pins
" D2 W V" i5 e/ ]* n' k. ~** Input - Frame Sync, Clock and Serializer Rx/ T$ D- W: K3 S6 m& t9 l
** Output - Serializer Tx is connected to the input of the codec , u- I& n4 w! x) ?. E* ?' y
*/
7 u4 k8 K- c9 |McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ L3 d4 i! G, h F# M2 R. J" j) zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( P( d7 s3 `1 x6 k0 I# S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ t# H& y( e" ]| MCASP_PIN_ACLKX
7 `7 n8 U8 G1 T) y$ c: D* m3 d$ {# P/ n| MCASP_PIN_AHCLKX
& D" X! B7 Y* i/ r& V/ _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */- ?) S# F) s. M8 v, q+ C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR , ]. v+ W" x6 o( `
| MCASP_TX_CLKFAIL ' Q% v5 D, `+ W4 K- P' B/ M" i
| MCASP_TX_SYNCERROR
8 T% ]" U2 q; }1 m' }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 ^) ]: ^* P. c7 a" H
| MCASP_RX_CLKFAIL/ @$ ~" v$ f+ m" \0 D" o2 e
| MCASP_RX_SYNCERROR
! S# l+ W# k) e% D( O| MCASP_RX_OVERRUN);
& o: u' I" C( M9 M} static void I2SDataTxRxActivate(void)
+ B- \6 J7 w, e2 G{
' b- V3 b* P6 s# x/* Start the clocks */
0 [- e7 V- B$ Z! h Z/ ^. IMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
7 n5 c% e- p+ RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ H U7 A W; V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,/ I0 a& \5 @$ J- J! U3 Z# X' x" z
EDMA3_TRIG_MODE_EVENT);
+ s! o6 u2 U' ^% nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
) `% W5 v" f% k5 [! K7 G3 m' EEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
# \2 Q* e, P. O7 n* c* ~# x$ g bMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);9 ]' k2 N5 y- `, _
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- J& S/ N2 }+ g) t- bwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' U, q6 |" i: t6 N6 C: e( qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
g) ~3 m% ~( NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 b9 G1 K# v* Y, y5 U} ( r2 U- Y8 t, K F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) T) g, M& J6 s! L% P
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