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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! m# |5 k0 P# J8 zinput mcasp_ahclkx,: t7 M4 ]0 b+ a0 ^' a: l
input mcasp_aclkx,! P2 @9 R; o4 H0 |6 _: a' o; _( o
input axr0,+ v( _2 n) B, r3 T; ~2 P1 M
* t$ p4 l4 o- |. g+ ~output mcasp_afsr,
& X+ y; y2 L# ^7 ]output mcasp_ahclkr,
7 |& U0 f7 z, H) `" g& w0 uoutput mcasp_aclkr,* N8 S) b3 ~6 P* V. g8 V: H; Y; q
output axr1,
1 c0 X2 v P1 _9 y9 o4 Y( _ assign mcasp_afsr = mcasp_afsx;) x+ v5 R7 ?9 e, H. {# x
assign mcasp_aclkr = mcasp_aclkx;
; G5 w Y K% j9 f5 u( E) lassign mcasp_ahclkr = mcasp_ahclkx;8 F) K, {- L) ]6 X: h; s( r1 X
assign axr1 = axr0;
% f( M- [' L4 |3 ]; R
- ]1 g9 G. P$ a& Q7 W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 {5 X- e- B; S1 u1 q3 ?; S
static void McASPI2SConfigure(void)7 G* `8 \8 h( C2 `9 v
{
. x5 H3 q- R& [2 U' H8 s# jMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
( i1 {! D, ^" BMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& p5 @" l D% i6 G% N$ h O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 z h# n. L8 R# {# _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* M( [( ^6 B' T4 T) O) [1 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& \" L8 I$ W9 p, R& ^1 FMCASP_RX_MODE_DMA);
% @& Z4 ^) x% S! g) I2 F# E( DMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) f: u3 y$ }( c- _0 o6 V! ~* @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; G2 C) K/ z5 h' _2 \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. |/ x, K6 U7 R" V v" _9 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ w- t% F, @7 M9 I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ z1 S) S3 V) KMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 `' |* Y& y+ g M1 GMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ b1 Q a, P. N2 ?* i5 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 3 U3 V5 t; p+ u7 x
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 E- \( n2 k/ I* Q7 K7 y
0x00, 0xFF); /* configure the clock for transmitter */% z" K, n3 [+ r4 w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);6 D4 @1 L+ |) q! t7 b1 w0 R& p" I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 5 `4 C9 t* i8 X2 ]% l! G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 h; N. F% G) \, g, q' o: m0x00, 0xFF);: G! P, {" \4 p& i+ T7 G4 h V+ N
5 m5 W1 L( }- T
/* Enable synchronization of RX and TX sections */ 2 e& @! J7 \; S2 E% c% z
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */& Q g6 ?% P( ] ]/ E
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 \% ~2 U& ]0 V$ i; i( o7 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* Y7 H+ b! p: _) R/ |( N** Set the serializers, Currently only one serializer is set as
7 P6 d$ r n0 V$ ^+ F** transmitter and one serializer as receiver.
8 I" s( ?. t. H1 w/ b6 S*/
p$ h) Z; R8 `- `) N, N3 m+ OMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);; r! O7 u) k7 x k% I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ E0 E0 o: Q4 c4 |: v# ?2 ]** Configure the McASP pins U. ~. }9 U3 r0 i0 S
** Input - Frame Sync, Clock and Serializer Rx* ?- u" b" U! i+ m8 h& l. l# @
** Output - Serializer Tx is connected to the input of the codec
6 ?4 d" n# ]- _*/
3 Y% o3 T( U( l; d. IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 S2 L- }1 S/ R: P( I9 P' l$ k" vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; x8 U) Y! U% q5 G. g$ T2 R& \* p- J& ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
9 f9 b$ C& k+ m- Y2 B2 h| MCASP_PIN_ACLKX
! t4 T) d, H% W7 I' {7 @| MCASP_PIN_AHCLKX
- K; e, r* u1 s' R' d _2 o4 ]| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 P9 G0 f6 d7 x2 t- SMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; g2 ^: r& y: K- z$ \' r% N% k
| MCASP_TX_CLKFAIL
7 P! {3 @/ o2 G' G0 a| MCASP_TX_SYNCERROR
3 p1 \( t! I/ m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: t4 ]( [$ D' \| MCASP_RX_CLKFAIL
6 q( I& Q3 M1 q$ ^3 {8 \| MCASP_RX_SYNCERROR
. x Z1 ?6 k M7 x4 A- @* a| MCASP_RX_OVERRUN);6 z5 s f( W! Z1 f
} static void I2SDataTxRxActivate(void)
2 `$ T5 o1 L9 ~+ [' E( Z% j, q; O{
2 b8 L# V3 p, `$ V" h- }8 d2 u/* Start the clocks */ s, [/ u3 a0 w7 K' y# B
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); f) ~) `* b/ M' Y
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
( z: I/ N2 Y, |/ k/ FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,) t2 x- F7 b' n# _* D
EDMA3_TRIG_MODE_EVENT);+ _7 f `9 A- x9 j8 w3 C5 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % j2 l+ G$ M- `& P/ W8 f8 z8 d2 Y$ E
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 I3 E9 H* h* K3 t
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ P$ \9 ? g7 X) l( HMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) |$ g. R. ?7 }6 P; mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( X& y4 a7 X a, hMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
4 E9 a4 w& \; D- wMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ \9 ?* t1 ?& L, F
}
% L3 ~$ V, F/ o; u5 X, I% u& T请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. + M. K/ w' J- t8 ^% Y! ?& `& V/ q3 f
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