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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
R; J4 Q& S! M) Z) m2 ~: Yinput mcasp_ahclkx,
9 m( B" x% N* F4 a% F3 D+ Linput mcasp_aclkx,% P+ B1 n" J! A, a9 G
input axr0,* n7 v9 j8 N& s
W4 e P6 O1 T& I9 a6 k; P
output mcasp_afsr, a- z( F( |, j2 h4 R6 v5 |7 a5 e
output mcasp_ahclkr,
9 Q2 a- e o1 t! ~/ U5 r9 ?6 boutput mcasp_aclkr,
: G s8 G; p$ e1 joutput axr1,
, }, ]- e. e4 L- b5 i( B assign mcasp_afsr = mcasp_afsx;0 a; ~0 K0 R, e
assign mcasp_aclkr = mcasp_aclkx;/ ^2 F2 Q7 Y( `; N& ^! R
assign mcasp_ahclkr = mcasp_ahclkx;$ o& `' X) D1 z( ?" \" J2 V
assign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 A! K5 y9 S& F3 m. n
static void McASPI2SConfigure(void)
) r/ B* d9 @$ M) t7 P& d{2 Q; e7 X. a$ o0 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- a) e3 x( D* _: GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ H2 R; a7 s8 T7 m! N' l
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);) O& Z3 z( m0 ?4 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ |* a* J/ ~: H0 r/ \; o; r, c0 J
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 \ m1 E i. v+ f! u
MCASP_RX_MODE_DMA);
- l H, e" q8 U9 f3 BMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 j. {8 s% q9 s6 _MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 E2 f1 F# x$ D, N0 V5 }. a, OMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ o" X* k$ a, f8 V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 X( t3 ]$ V. ]- V; y y' s U' T! D9 C1 R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + @) ?( [0 D. s+ f* o+ d1 p1 Y
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& V: ^+ ^/ S' w' l& ^ `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 n2 v6 r% d( v7 w: ^: rMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 w2 ?9 l% N7 q4 EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! n4 M- m0 x% S* C, ?! X* ^7 A# y! e0x00, 0xFF); /* configure the clock for transmitter */8 V. j+ B6 E# G! I3 @# s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( W/ q3 R: E4 ?7 Y7 LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); # I3 v1 y- I, L! Z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; ]8 K6 v6 Q* @& p# G0x00, 0xFF);
/ z' x# }( E* S' P! U+ d0 c4 c9 |" @* c4 a& h6 c
/* Enable synchronization of RX and TX sections */ ) W8 u+ a" d) l
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */+ b1 N% H3 V8 N1 R3 ~- }3 J% ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- \1 C7 f6 a6 I p: _7 ^McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 x# F3 a6 @% z) U$ ]
** Set the serializers, Currently only one serializer is set as
7 [, t2 r c7 X! I9 }* J8 I** transmitter and one serializer as receiver.
: _( g- F x; \) d8 B*/# W4 H4 ?* G( _/ l" X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);2 K8 I( n2 _) F* ?/ i8 ^
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# b( \" }+ k5 R3 ] U** Configure the McASP pins ) `1 G. t+ S9 S8 w
** Input - Frame Sync, Clock and Serializer Rx2 W' l3 K6 L6 |4 s
** Output - Serializer Tx is connected to the input of the codec 6 ^" x7 K! B) |8 b+ A0 k! g1 ~
*/
8 s3 {) w( f' J- m1 I. b; x; DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 x4 l/ j5 S9 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: W& D* W6 s; w- qMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, @- S) d0 G" A2 W% O/ z7 C7 V C| MCASP_PIN_ACLKX" ~# O& c x3 ^% i
| MCASP_PIN_AHCLKX
& K7 M6 f' {: H( u& Z6 H| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( S; U; R5 f5 j4 r4 j+ F* s
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
6 Y* ~7 [2 [( M8 b6 U| MCASP_TX_CLKFAIL
( v0 [9 j2 ]' n0 \# S| MCASP_TX_SYNCERROR T+ p. e$ X8 G6 b5 z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; P; U: r# Y( Y) b5 M7 _8 R
| MCASP_RX_CLKFAIL5 }, t* X1 ^0 R U
| MCASP_RX_SYNCERROR
* K5 \$ T# }9 ?1 m| MCASP_RX_OVERRUN);
0 S( ?0 U+ c0 z5 y( Q! I} static void I2SDataTxRxActivate(void)
+ y- d( i0 a/ G) c; R{
- ]8 L% p+ o$ q9 Y. }% S/* Start the clocks */6 G: E6 E P3 K l
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 H* C$ u$ S2 B% R+ i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */8 ~* Y; {* o- o# H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# {0 V2 f% t3 c. ]
EDMA3_TRIG_MODE_EVENT);
3 T) A9 R* o6 B# LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; W6 P5 U3 m( P* X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 Y, d% Q, N/ {McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% P* ~0 S6 `( c* X* ]$ c
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 `: Z1 P, Z$ ?# R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ }9 [6 S/ y/ R) x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) U9 z- B! W( i+ a6 Z2 T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& o: n( C# R: S! s, j; H8 {0 M
} + @' Q, W! ]; r9 X) b; y. {3 {
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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