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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; j+ g" z% X6 ]4 ginput mcasp_ahclkx,6 X. {/ L7 l+ {/ B- _2 P! M
input mcasp_aclkx,8 k: k+ J; q3 P/ F" [ w% H* B; m# M
input axr0,
3 O; Q# D1 W1 d
- A3 c9 n, }- { d& a! soutput mcasp_afsr,
' R4 o) X" V5 ]$ [( x7 \- ]output mcasp_ahclkr,
' z( H8 `* C; joutput mcasp_aclkr,- w0 |) V1 e8 X" {. e9 {
output axr1,
/ r1 y; ]) k. n' u4 B. w& D' g% i assign mcasp_afsr = mcasp_afsx;
0 P- r' @( E1 P! C: A3 U! xassign mcasp_aclkr = mcasp_aclkx;
" Y3 \1 |: Q- S) D( Rassign mcasp_ahclkr = mcasp_ahclkx;
/ ~2 n3 {0 g4 m. d9 t( w/ E4 h p9 massign axr1 = axr0;
: a! B: R" h4 N5 k; Y4 _$ j2 U
- m' z; V% E1 o9 p4 L- w6 E* ~) ?在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # ]3 ]6 U9 P9 y. f! g% S( `5 ^
static void McASPI2SConfigure(void)
5 O& I' s4 M2 v9 b{
* _! K+ \+ x- NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);- X* B9 U8 F5 L! R
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, i, M: b0 ~0 ]9 P5 _) t* U
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 x3 t, v" g1 [$ L- [McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( v4 ^( _$ z( u5 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; ~+ U; A/ L/ V+ O
MCASP_RX_MODE_DMA); {& ?6 }$ j+ v( o: ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ ]& J8 T/ T P" x9 P
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 u0 \+ ^$ J, `! c, t) \2 w1 BMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( c0 |& n$ |" y |" s/ e6 dMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
* f7 u% ?+ k) e6 U4 t" W" hMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
# [* U0 { M3 {0 qMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: R; G( I1 M) w9 l4 ^$ a+ D @
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ }* ]: X% w( f5 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * E/ Z! {2 ~0 }* S, \ ^- f0 \$ R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& v/ I* ~; {. q! `( \
0x00, 0xFF); /* configure the clock for transmitter */
- u+ T) ^. q- f; Y" e; z% J7 SMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
( G+ @& n) W* w& m$ a* {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! Q0 x* i7 Z- j' q8 [: ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, W) v) j; s7 o5 W
0x00, 0xFF);
6 F2 e3 B' Y" i' J# Q) w
" F4 C P/ g! c; i5 b/* Enable synchronization of RX and TX sections */
- m5 y2 Y8 j/ l D4 H8 c4 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 R& a+ H& T( d7 ]2 A
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, `& b2 Z0 c: ~& FMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 |8 f" t& V# A! O3 [, ?# \
** Set the serializers, Currently only one serializer is set as
. y! L U# I I* J: M# m# U** transmitter and one serializer as receiver.* i; O; [4 B5 Q0 ~5 V
*/
4 M2 G( T/ ~5 s4 z% S8 oMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
& |4 C$ F: s, m* r* HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& I' Q0 c! @/ y, \. H4 S6 r! {# J7 Z( h
** Configure the McASP pins
& \& |8 z4 z3 ^! S: }5 C** Input - Frame Sync, Clock and Serializer Rx/ Y+ [; F: M$ A8 _" W$ E. o: V
** Output - Serializer Tx is connected to the input of the codec
# k( r E/ {; \0 i. l*/ D" X+ i/ Y4 j# b+ T, q/ I5 l4 a
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);+ ~( R% N9 [8 m" `' d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
+ G# Q: q: u. @8 }4 d8 mMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' ?# g7 O3 c) L9 V# g B
| MCASP_PIN_ACLKX
4 s1 G6 t; w. y7 J, B3 n| MCASP_PIN_AHCLKX& u! }5 k9 d% G+ } e# Q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 m' v k; n- E; zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 l; _. r! V9 I+ H) I/ U' ]- X| MCASP_TX_CLKFAIL
9 e A, w9 e2 D+ x. {6 i8 r, \| MCASP_TX_SYNCERROR
% e1 ^: u. Z7 h ~- J( E) x* v| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 g8 i D, h: j| MCASP_RX_CLKFAIL5 p0 J0 f' r8 s/ D, c/ R# t
| MCASP_RX_SYNCERROR 0 a" q4 c' e9 R2 K
| MCASP_RX_OVERRUN);# ~$ z- A4 Y& F
} static void I2SDataTxRxActivate(void)
2 D0 |, l$ B0 L0 L; x% \* a' a) d{
8 ~ b1 N9 l3 l$ \ M( v4 B# d/* Start the clocks */
& b% d( J7 S4 H/ D9 x# y9 y( C' ~McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; k% X5 v/ ~. p3 ~
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 N6 `* R0 J2 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 H3 S9 ~$ @! L! T! c( j- m
EDMA3_TRIG_MODE_EVENT);
. b5 M( ~/ C$ P* ` F0 F. a. R% g4 lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( U: }2 P6 _+ d4 ]
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */# ]1 }( ]& }( j4 W3 T# p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" @ {- @/ x3 j' j o% I' B
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 D9 G* @5 {. o+ k- C! {+ Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
- s) n3 H+ d! V" l* M& VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' u- z- @( h; e/ HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- q/ q3 D$ v3 j8 s}
& s# ]* N0 s; j4 k! M1 B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. Q. a2 v: Y; o3 c
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