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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& D# I" D, r0 L$ \6 P, ^input mcasp_ahclkx,
4 |3 j- ]3 z, ]8 B% T1 D- _input mcasp_aclkx,
* F- L4 X$ ]3 Q* b' S+ binput axr0,
; s7 G8 Q7 F2 v- @# L3 F
+ F! }0 e- y/ Y& doutput mcasp_afsr,
( s- e" m: s: Y1 d* g& |output mcasp_ahclkr,$ H* z. W A/ d3 L7 Q; K5 @. V
output mcasp_aclkr,
: e& [9 J, X6 @9 P: V( t9 Soutput axr1,
7 r8 ]3 `/ F; }$ }, k' m assign mcasp_afsr = mcasp_afsx;2 c: Z9 e# v5 |" D) p* J2 x$ v
assign mcasp_aclkr = mcasp_aclkx;9 p4 \* }9 e' g4 z
assign mcasp_ahclkr = mcasp_ahclkx;6 \* `, {7 r5 r
assign axr1 = axr0;
& R4 Y. i- R0 A! ` h* A; h6 N* M* G. `* b
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 z- A$ S4 X$ F& S- A: xstatic void McASPI2SConfigure(void)
4 D8 [& @ y$ H{7 g5 H" B. P1 {9 Z' x0 B% q
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 o% M$ I0 |! Y2 qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ D" k5 ]1 N( [- I S$ |McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 b b2 [) S6 ^: U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 P" A4 n/ i$ I, ~, x) V* HMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 h' `, ~2 x) B. v& p% E
MCASP_RX_MODE_DMA);8 _8 f5 u h) S3 Q* d2 K3 l
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," O0 R- i1 D# K0 L4 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: K4 _5 Y {& v- f- l$ hMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 3 r1 D* {% z) x4 i% V
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 S$ j, P! h t. A8 t5 }McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' |3 F- ^, i1 P% } J! d5 z/ t# N
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 ~( f' F# V; n, s6 e" v# aMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);# }/ g) C: b Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); : p3 ] W! F( g3 z3 a1 H* O" }5 {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% o% g5 t' t: w4 m0x00, 0xFF); /* configure the clock for transmitter */
# B7 S$ }4 _# }6 ]! F! TMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 t l6 a1 E* L* }. |5 G& G2 j- b4 BMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); " J. w/ F! k# C+ t) a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
' u. @0 \# K8 k+ Z F; b$ F0x00, 0xFF);
2 @% H( E' l- `, g# B! x+ i
& b& `9 v. [: K/ g8 I/* Enable synchronization of RX and TX sections */ 4 c+ |1 w2 [" ~& ?5 X
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 O0 Z! M# {4 t j# ^4 e
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 C, t: j! q7 e6 W) h# M2 K( KMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* T, m. E" Z2 D* Z/ v** Set the serializers, Currently only one serializer is set as+ {, c# \8 d- W; A
** transmitter and one serializer as receiver.
6 R) n( e7 v2 F! C6 ~/ j*/: X8 B) e2 B5 L( [ Y7 U( ]
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
' W4 a# a$ S) C5 ?, d* yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*' y( _. M* P# U/ ^6 N8 A
** Configure the McASP pins
. c9 E ~$ B$ O" g: B** Input - Frame Sync, Clock and Serializer Rx
2 R7 B8 n# B, A# y( e3 G/ q** Output - Serializer Tx is connected to the input of the codec 4 I% ^ g; D) N& K/ v2 h
*/% m9 b$ F; Y r3 O! Z5 W
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
4 |; r* C; s# XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 p4 [7 b ?0 ?+ y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
, O) {0 ~$ O2 R7 Y i, Q) T8 u| MCASP_PIN_ACLKX! M2 _: N& b$ y+ G) i
| MCASP_PIN_AHCLKX
$ d5 F+ |: r$ }# ]3 s0 _. B| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# t, W- {! k' @; x' l& p: M* AMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' R, U; U8 ~& N| MCASP_TX_CLKFAIL
$ M( Y9 V ^0 P, x/ x| MCASP_TX_SYNCERROR
9 z4 u( D8 O, I$ _4 U7 N! m. w| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . H2 |' w7 O) b- A
| MCASP_RX_CLKFAIL5 ~! R7 a, Y3 _5 c
| MCASP_RX_SYNCERROR 1 Z1 g9 E4 V. T- m$ J5 Q
| MCASP_RX_OVERRUN);5 h) s3 ]/ {' Q1 j, q6 G
} static void I2SDataTxRxActivate(void)$ @+ Q5 Z, l" K2 H/ n* ?
{: q( T0 h$ y1 S+ K% X
/* Start the clocks *// p5 h, J4 c l; ]6 Z4 M, r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ Z* Y, C* E. D1 ?+ t7 m
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 |/ j/ q& k1 {7 P: u" \5 q( @
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; W- k4 U( d# Z0 UEDMA3_TRIG_MODE_EVENT);. R2 J" ^, e% v5 ~7 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
6 _& R, a* G1 r5 zEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& O$ |. w( ~) z x1 ?" S# dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);( b2 N: }4 W# J2 @' S
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 a( Q8 f# \& O; {9 H5 q8 ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
\# v I; U5 C+ iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ v9 c& t- V d. [( j' \McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
& j3 U" R" b$ J* S+ L k}
# J- H! E& k! }9 h+ A请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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