MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
input mcasp_aclkx,
0 h) m0 D: Z6 N; T/ \5 hinput axr0,
2 d: s; q9 K, m, R! [/ Z
! S6 t) i) e* t! v  noutput mcasp_afsr,
output mcasp_ahclkr,
output mcasp_aclkr,
output axr1,

assign mcasp_afsr = mcasp_afsx;
assign mcasp_aclkr = mcasp_aclkx;
: E$ k7 Z. L- e0 C0 c6 y5 Massign mcasp_ahclkr = mcasp_ahclkx;
% U# |( @9 w- Q( ]. `) `assign axr1 = axr0;

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

static void McASPI2SConfigure(void)
, y7 L2 e- s6 I7 n' y9 n( @4 N{
/ |7 }) R& ?% c+ M; D. {7 Y9 VMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
McASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
& _  v9 n- \3 f/ c. h0 I& vMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
  ~8 e% W, r  Q2 D/ PMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
# N7 g& Z; D! i& R; |McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ H7 V" p6 X+ dMCASP_RX_MODE_DMA);
8 `% ]: o7 N2 n# ~McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
, k, R7 @, }1 t7 p5 b* @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
  a6 b+ A  ?  q# i' ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, I  C7 D1 Z. I  Q! C0 g8 GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* U* K" K+ L: c9 XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);
! a6 u0 G) J: D
/* Enable synchronization of RX and TX sections */
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ y; o% e, F- d2 n6 }; A9 f6 m& qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 b+ a' U6 v* r9 oMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
1 y, Z0 N! M9 y1 z1 f** Set the serializers, Currently only one serializer is set as
8 X2 w4 J0 }$ ~# o) T' |** transmitter and one serializer as receiver.
" `+ h! Y2 u8 f9 Y7 n7 U*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- v! p0 F8 ~9 f$ z& o1 `  j% bMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
** Configure the McASP pins
# U* E% W  c* E( u' |# X1 D** Input - Frame Sync, Clock and Serializer Rx
** Output - Serializer Tx is connected to the input of the codec
*/
) S" F  d' I+ v. sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- Q9 Z- Z8 c% aMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" o1 u9 }" r- g/ Y' q| MCASP_PIN_ACLKX
| MCASP_PIN_AHCLKX
' ~# w' y3 X: `. F) g+ V5 p4 o7 \9 h| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
& m* o. U- S8 }8 G4 M8 ~! z: cMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
" ~6 r, p8 b2 s5 Y4 @& || MCASP_TX_SYNCERROR
2 U" o- U4 L  h! ?: k2 g  {| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' \- r# R9 Y+ ~1 }# o: z| MCASP_RX_CLKFAIL
) d& R* m9 }$ U& s/ F+ C% t| MCASP_RX_SYNCERROR
4 z: ~; F: \( E, ^' {# P) P| MCASP_RX_OVERRUN);
0 b" _0 p4 T* L}

static void I2SDataTxRxActivate(void)
{
/* Start the clocks */
$ j# I) M) Z7 P) DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
  G# w  Q# ]7 Q, z3 c9 ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
. P$ H& `, S2 X0 \% y) bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! w/ K; K9 h! YEDMA3_TRIG_MODE_EVENT);
0 W$ u# q$ R3 Y0 k9 N8 eEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
" S7 u4 S  S% i" OMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
, w% _# @0 V9 O2 v+ m* S; N4 Owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
+ g) b' n% p% l3 N; [: HMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

! O6 M# E8 {: Q