MCASP自环配置。

wapdasta

我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA，所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。

部分代码如下

input mcasp_afsx,
input mcasp_ahclkx,
, |6 Q2 E! `3 Sinput mcasp_aclkx,
0 ?4 D& c  m+ C+ Hinput axr0,

% p- V) [/ ^# `" y8 f3 woutput mcasp_afsr,
8 |5 f% a9 E: @9 A$ m) G* R% loutput mcasp_ahclkr,
output mcasp_aclkr,
; P1 H5 k2 ]; [  voutput axr1,
' Q" Q8 _1 o  _4 @7 R) H1 I5 g

assign mcasp_afsr = mcasp_afsx;
$ i- o2 F7 h& t9 C+ b0 l: Dassign mcasp_aclkr = mcasp_aclkx;
assign mcasp_ahclkr = mcasp_ahclkx;
* K8 ^, ?, ]; _3 |9 n6 uassign axr1 = axr0;

8 q, y, Q* s7 ~6 V; U! C

在OMAPL138这端，通过axr0接口发固定的数，axr1接收。

在配置MACASP的时候，发送全部取内部时钟，接收全部取外部时钟。

一直循环发送，但是接收不到。在FPGA端也没有看到时钟和信号的波形。

部分代码如下，关于edma3的部分未做变化。

" w7 C/ Q$ E' y# r; }

static void McASPI2SConfigure(void)
{
( q" e4 L! M! V% o% n2 u! A; PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 ~1 c' d) ]& S( q! g) QMcASPTxReset(SOC_MCASP_0_CTRL_REGS);

/* Enable the FIFOs for DMA transfer */
/ d- q5 y+ y4 N% b2 T. cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);

/* Set I2S format in the transmitter/receiver format units */
9 y3 t7 V* L$ c5 Y7 f1 WMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
MCASP_RX_MODE_DMA);
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( ]2 |' u& N) _7 ~9 WMCASP_TX_MODE_DMA);

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* v5 X/ O, Q% \3 D: h% CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* B% t5 d5 p! t0 c6 i" \( S! s- bMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE);

/* configure the clock for receiver */
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 m( j9 y9 ^+ r0 z4 PMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0x00, 0xFF);

/* configure the clock for transmitter */
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. s; X+ C; e: O/ v3 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* X) h# p9 w8 d) a' ~/ fMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
0x00, 0xFF);

/* Enable synchronization of RX and TX sections */
2 y2 V/ d% O% j9 _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 [0 d+ x/ {" j% {, T# y" w7 O+ WMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

/*
** Set the serializers, Currently only one serializer is set as
** transmitter and one serializer as receiver.
7 J2 j5 z) z+ K+ h  i*/
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* m: p' ]' d$ @8 s  p5 sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);

/*
& D" [: L0 h) H3 ^6 }$ _** Configure the McASP pins
7 E2 F" i8 _$ v/ i4 g" Z6 r" u! Q# B. S1 J** Input - Frame Sync, Clock and Serializer Rx
  n8 k+ K/ Q* v. G" a( k) s** Output - Serializer Tx is connected to the input of the codec
' ~+ ~+ `5 B; o* L*/
- r* l' S& u* e6 ]* a2 CMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
0 h1 W/ e7 _# L( l+ M- PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 V1 j$ @+ f5 I6 I, `* ]" EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
| MCASP_PIN_ACLKX
: m8 @( @- H* K! m# I% ]3 `| MCASP_PIN_AHCLKX
( ?; U( i! ]0 r, c- Q0 V| MCASP_PIN_AXR(MCASP_XSER_RX));

/* Enable error interrupts for McASP */
) B# ]0 U# N* B& xMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
| MCASP_TX_CLKFAIL
5 {4 Y3 d: P& Y% I| MCASP_TX_SYNCERROR
| MCASP_TX_UNDERRUN);

McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
| MCASP_RX_CLKFAIL
) K0 u0 v- ?4 f# C. \4 n| MCASP_RX_SYNCERROR
- V, o2 v  l1 `: g| MCASP_RX_OVERRUN);
}

static void I2SDataTxRxActivate(void)
" z$ L# K4 ~  l; X: U{
3 ^7 \/ s; L7 ], C% I0 c/* Start the clocks */
5 L! W- `) n, j/ rMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- q" x% G+ D# `1 k- h1 M0 hMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL);

/* Enable EDMA for the transfer */
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
EDMA3_TRIG_MODE_EVENT);
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);

/* Activate the serializers */
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
/ R2 e$ G+ G! V9 W+ @- o) p  ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);

/* make sure that the XDATA bit is cleared to zero */
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);

/* Activate the state machines */
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 n9 {* ~, A' _) O' z& K7 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
}

: `  k% v, T( x) z& F( {

请问：问题出在哪了，时钟按照这样配是否有错。

另外我看XDATA一直是0，接收的rxbuf0,1,2里有一般全是FFFF一半全是0.

: p, X; ^; A! Y) v5 n" h  i2 L