|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
) U: r; q; R: |) K& Uinput mcasp_ahclkx,8 W: ~) O- `7 e: V1 ^# U) p) c
input mcasp_aclkx,
5 ]1 I& ]) U8 K( @" i% b7 Rinput axr0,
6 g3 S0 `# G% X) W3 m2 @7 V; ~) ?
output mcasp_afsr,7 M5 N$ w8 w- G9 T3 ]* V, e
output mcasp_ahclkr,
% d+ x3 Q& ?8 Routput mcasp_aclkr,- ~% K7 F, v8 ] @! U
output axr1,+ b* M* j) c4 L. z+ z6 _
assign mcasp_afsr = mcasp_afsx;
, g* _. n0 F. c5 M; zassign mcasp_aclkr = mcasp_aclkx;
1 ^! b. J! @/ T! Hassign mcasp_ahclkr = mcasp_ahclkx;$ F$ e& A+ [+ ?8 x5 e4 k% E
assign axr1 = axr0;
8 s1 I% J0 i4 T0 b4 W2 h7 M* l) |! ~8 g2 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 _1 N! l o4 cstatic void McASPI2SConfigure(void) I x% R& ]7 |4 w- ]
{
" t6 J. [, f6 UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
: A+ m: G+ f7 u3 l; q' ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ h/ ^2 i3 w8 a8 m
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 B0 w5 S8 p! o1 t9 Q3 bMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 a0 o) A$ W Y& x, g# ~% }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. ~$ i- t8 ^* ~# `0 Y% C+ {
MCASP_RX_MODE_DMA);/ b; E( z% \: V) V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," ^# a9 ]6 e1 d$ x% I3 c! D, ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& O7 D8 N- N5 A- d+ N& @0 _8 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* F* k: H8 r7 g- xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 [$ B- F+ X' G" ]6 R: F: B9 CMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
" D: f1 d5 `) x Y, C) Z3 j. \$ D' EMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 C3 E$ ~: V; J, C& r
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& j4 `9 Y" t/ E, [/ Y6 _. ^/ zMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* i% B! e& L8 l3 w; ^) H8 ]McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& f5 V k- S6 E! a# y7 E. t0x00, 0xFF); /* configure the clock for transmitter */8 Y9 O( ` l# R) X# g9 a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# h( r& A& ]% K! ]& w- U* B; T# R
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
0 k& \1 i- {7 D5 TMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ x3 V+ A2 Z# g1 @& A
0x00, 0xFF);
. p# j+ O' Y. h" ]
7 B' y/ L/ J4 _7 v( p3 p6 j. E/* Enable synchronization of RX and TX sections */ 9 g" ?3 {! T$ z; }
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
* P( v7 E0 h2 h+ s& GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 y0 c4 J+ {- B7 z) q1 H8 _
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
f# N6 y: D, j+ Y# K** Set the serializers, Currently only one serializer is set as
6 b& `' n% @' Q. [- y: d& I' m4 h** transmitter and one serializer as receiver.
1 A3 z( {6 o6 p2 e$ e*/
1 J' F! @8 `; wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
6 i j* J6 X2 i. C# o2 Z0 pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. K- t( G% k1 D2 n1 d% ?5 {** Configure the McASP pins
: |5 a1 p7 O! ~** Input - Frame Sync, Clock and Serializer Rx1 V3 i( r8 v4 Y* E. S, U5 b P- o
** Output - Serializer Tx is connected to the input of the codec : v, [7 w- R2 R+ M4 d
*/
* \8 c' w6 h8 IMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( a/ j! B2 r& e3 k
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 l9 L R3 K4 ~7 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' w+ t6 b6 @$ N# y" L& c" e& j
| MCASP_PIN_ACLKX
: m( \. p+ Y v6 U9 r) D0 d6 Y| MCASP_PIN_AHCLKX
$ H. c7 ]+ [2 w2 M| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
3 J# q" h5 e4 w% ^/ M, wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' o+ N% M0 `; t# o6 {# [( d: H| MCASP_TX_CLKFAIL 4 C$ T9 @; C0 M1 \; d' Q: k! l
| MCASP_TX_SYNCERROR2 G6 }% r- J$ F) [5 g5 o0 I
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' B* o& H/ `8 m3 R9 u5 ]
| MCASP_RX_CLKFAIL/ h8 ]' n1 Y9 ? Q2 R6 t
| MCASP_RX_SYNCERROR
0 k$ d8 v, u9 N; a0 u& n| MCASP_RX_OVERRUN);
' U3 t( a7 C+ ^, t: n$ R, S} static void I2SDataTxRxActivate(void)1 {/ k! I5 g# c8 @
{
3 e$ t4 O f, h* p/ M6 P/* Start the clocks */
8 z. \& j8 ]7 L: T7 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' i& u+ ^ @) w' c9 g9 A6 yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; b0 i- w8 ?! o! e9 U& U+ A3 O0 ?7 ~
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,( \( |6 b( i2 c2 g2 F# Q9 `/ H
EDMA3_TRIG_MODE_EVENT);( q* r ]5 c/ ^5 E& s4 C! T
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) I) d9 G9 ]) b% ^
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" c2 Y N' R, W- h+ N' @; vMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
O4 b; T2 ~0 {! RMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 F2 I1 d7 f2 @' j+ wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 H/ Y9 ~1 B7 C2 Z" k: i) Z6 R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 n# a5 H5 P" T) ? C" M! Z1 G6 tMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
; j/ o/ `% C+ G* W} " }4 _3 F# t! ~4 \) i% A4 ~) g
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! c# U: o k+ \5 g
|