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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. D# M! e) e9 _+ n2 Z% g( G( B
input mcasp_ahclkx,
( u1 Z0 o2 W* Z2 ?) Tinput mcasp_aclkx,
B7 e; m: a, _' X& z8 q' }1 a# Ninput axr0,
1 k. k6 }! `+ I& x" B( S" P1 ~9 h' V' U# J7 Z5 M
output mcasp_afsr,
! W }1 M: W, d0 U/ ?- Loutput mcasp_ahclkr,& Z2 o+ f7 e* ]* C# j
output mcasp_aclkr,' P. r) G6 k! R$ P
output axr1,3 d, X2 z$ L5 w
assign mcasp_afsr = mcasp_afsx;; O& _! W4 S1 B4 w P
assign mcasp_aclkr = mcasp_aclkx;- _7 y6 D8 Q! R r
assign mcasp_ahclkr = mcasp_ahclkx;+ F" E5 M- Z- E i) u6 _
assign axr1 = axr0;
& |1 a o' F: \! b. Z9 u+ Z0 a* x) t( x d h, c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 Y9 j' N" P& s, rstatic void McASPI2SConfigure(void). v% Q# y* X2 Z; o8 N4 }. S% I
{8 w' G8 x2 A# i, R
McASPRxReset(SOC_MCASP_0_CTRL_REGS);* `) |2 R+ \3 X' f( _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; y6 W; T/ q* x# N" V" eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: W7 Y. U5 y1 i1 @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 d! A6 e1 B% @ qMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- ?; h4 O! z3 b" d4 K0 h$ m5 C0 R
MCASP_RX_MODE_DMA);
9 j+ q) r0 c( `1 Z3 F7 ^McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: I* U8 k" R' m$ ^( }8 V; ^5 {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: D, O0 p4 J' h5 y5 |6 `7 o! v
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * h9 m0 g; [. [: C
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 K& ]# K6 \8 U2 RMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & r+ V ~* M: Q4 N J% R: G
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */" c; e) G1 \5 F. H- z
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ l$ r$ k2 W7 E! P8 h/ @+ xMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
, ?! G& L: E+ L9 `( d5 WMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 y$ S8 G. D. m
0x00, 0xFF); /* configure the clock for transmitter */6 ]; u5 M8 O0 Y$ v
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 c& Z: P3 u' e* ~% n. @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 4 n: q5 |4 ~- f, O+ a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: D, W. `% }2 Q2 W3 Y8 A& C
0x00, 0xFF);0 a- E+ U D) D5 p, A* l/ h
b: Q& g0 N2 ~0 T/* Enable synchronization of RX and TX sections */
t- @/ h% Y+ }# V% b. mMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' T7 b9 @3 N) x( XMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 R. F; F8 |/ z0 l) D- o0 U
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ I. T. @: d2 m3 p& ?
** Set the serializers, Currently only one serializer is set as
& w ^$ F6 S; y# L/ `** transmitter and one serializer as receiver.
4 w9 V& U3 h+ u4 R( F2 B*/
: h I; F3 w& FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
1 r3 ]1 R( |: m! }+ _/ lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
# O A4 K1 { K8 F- w4 {8 c. l** Configure the McASP pins
% G% A$ V3 J1 D4 z+ ^** Input - Frame Sync, Clock and Serializer Rx B; y c4 M8 J/ x( ^/ z1 v2 u
** Output - Serializer Tx is connected to the input of the codec
3 r4 X [- b- Q" r*/
, T2 h3 C* T8 ^* @% M0 e' l& RMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); x2 m- x7 s9 f' Y% g" q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: o; Z( m! j& P5 c; x; u( A
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' {! G3 n: o+ o0 d0 F1 J| MCASP_PIN_ACLKX
: H. o' r7 z: Z+ G. }4 X/ O" R| MCASP_PIN_AHCLKX' i' W# s* E* _! ?" C
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& K8 Q/ o* u: FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
) n, M* E$ G& ~# L| MCASP_TX_CLKFAIL
6 L0 {# \8 \* [1 Y V6 `& L| MCASP_TX_SYNCERROR
5 @/ {8 f! Y( S* B& p. z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( E% ]# \3 F; K. ^. j
| MCASP_RX_CLKFAIL
# U4 h6 _1 ~+ s& } n: c% A* V| MCASP_RX_SYNCERROR ; O) [ B! n1 k( ]/ k
| MCASP_RX_OVERRUN);
' L) k2 O4 N* R0 C( J- E' B) T+ T} static void I2SDataTxRxActivate(void)
# T: |( d, n6 \0 p' o, Q4 a{
1 O* \# H p. J! P/* Start the clocks */
4 k$ H# b+ s) N4 XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);6 `2 r* V2 f; B0 h
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% E$ k2 Z. P" A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
) [7 M; e( b$ uEDMA3_TRIG_MODE_EVENT);3 Z) a; ~' l, p% m8 h6 j( H6 v
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " S7 ?, Q- w Q& Z9 `2 l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- |0 \* T' H: k3 W0 r5 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 m5 p( [7 U8 i0 g4 d- f! VMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ x' N: v: n h! D1 D3 _5 ^1 |, F, e0 Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 t- J. I& E- k( B9 lMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 `5 f* {: i. w3 @McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 I9 p R/ T$ J& X' M' H; ^
}
: H. J7 j$ W& _2 Z请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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