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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 N* l8 r3 x6 q# f5 U' [input mcasp_ahclkx,) c8 r3 z5 C: ?0 A; J* k
input mcasp_aclkx,
( {( X: g+ Q* Q( oinput axr0,( {- h6 G0 i) R$ y4 q$ P. m
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output mcasp_afsr,$ y) n" I/ N* k
output mcasp_ahclkr,, C) q6 q6 R0 x$ v: K9 q
output mcasp_aclkr,
( M( g. ^4 M/ }output axr1,
" k* _. n, Y" a: O! U assign mcasp_afsr = mcasp_afsx;2 w! b N- T% o! P
assign mcasp_aclkr = mcasp_aclkx;
- {3 F- O7 w& L& Q2 w" Passign mcasp_ahclkr = mcasp_ahclkx;( d; o8 C7 z) l6 L/ p( I
assign axr1 = axr0;
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% c# D# t. l- ?. N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 7 u0 ]) Q: r# ~, H' j
static void McASPI2SConfigure(void)2 q7 Z3 D1 M1 o% [4 e
{; K& F8 [! \. y* ?
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- b) y. o- z1 b; G" @' D
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ p9 I. D- x5 I0 E8 o# f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
: q' [& ~" W, @# ~3 w: IMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
9 D5 B) b$ [0 y% fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 v8 C; m: b2 C$ i8 oMCASP_RX_MODE_DMA);& T% ^ r& a. ?* L5 \8 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- m# B+ b6 \* r; s# ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 F& a$ L: e& {* P& I
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! G6 V. P. r' `" N( z VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: n* h2 H( H5 ]9 V5 C# S7 M2 ^, d1 IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ o8 d! ~: [0 AMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ b$ Y- j4 `; @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. o/ M# W; ]! R; d& c
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) l2 X8 f x# @1 n2 Q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 \- n$ k: S2 ^, O3 X
0x00, 0xFF); /* configure the clock for transmitter */0 \/ A+ D6 E8 v- g, _7 t: w
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 P0 U% [; i3 L
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ W5 c3 {% j5 i" G; dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 u/ M# N: Q+ i5 ?
0x00, 0xFF);
9 [% A" E* j3 l/ K
3 e1 z& R( b* i; q C/ m- B9 D/* Enable synchronization of RX and TX sections */ . \) c; z9 t5 J) n7 ?( d$ Y' s2 b$ S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& }$ o) ^3 X7 x8 G5 d: WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 ]( j( q8 L3 w5 C3 vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*: G6 v- d3 \3 i$ U
** Set the serializers, Currently only one serializer is set as
4 E' W. L, I) ]& d% s** transmitter and one serializer as receiver.3 k2 m) r. I- c( h9 V* ?
*/
8 m6 m F( Y: FMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);. J" e! \3 o d }7 A5 R$ t4 }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ W) R; L" \ [ F7 q# ~& w. X** Configure the McASP pins
; D( z4 N6 R( X7 {** Input - Frame Sync, Clock and Serializer Rx. b3 u$ \6 x, Y1 E; w3 C" _9 y; W7 ^
** Output - Serializer Tx is connected to the input of the codec ( k% Z' b$ }; f% v
*/
) H$ Y1 [6 u6 ~' j, ~, uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);) P0 W: S0 ]( b* _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
# u" ?2 W! M. P8 c& M* v# MMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX! @2 ^1 h1 B0 ?% q) i9 D
| MCASP_PIN_ACLKX
' u w t3 N# ~| MCASP_PIN_AHCLKX
7 L4 s: r. y2 _" z& m* I0 B5 }| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */5 M* t( i0 d1 {! O4 A6 v# Q" u. H5 f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR " n+ G3 H8 s7 E7 S1 y: D4 N
| MCASP_TX_CLKFAIL ) S4 q9 u& z$ f
| MCASP_TX_SYNCERROR
1 t% |, v0 T2 U P| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
; R& M$ N( v$ h1 s) f| MCASP_RX_CLKFAIL
4 A9 `7 c L/ Y* Z7 J k| MCASP_RX_SYNCERROR & \/ L; v' z8 Y# ]3 D
| MCASP_RX_OVERRUN);
% Z, M. \8 a( R1 L} static void I2SDataTxRxActivate(void)
- h/ S4 q/ H% n/ b; _; C9 W1 Y- v{( d7 @: ]3 h- T
/* Start the clocks */
2 z ?0 v7 y% {# eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);+ X, f( u/ ~) C) I% e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- V6 q6 o: D' R P$ t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,0 x% m# J$ g% K; y7 o
EDMA3_TRIG_MODE_EVENT);/ J, n3 ` D1 ?0 _0 {
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, " y- R' V2 c+ G$ i* Z O4 G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */2 F- \8 w7 B$ _0 ~# U
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 F9 u" ~: T9 z: W% S$ kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* x) o l' ^3 S+ C4 J. l
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 P# ?! Y! N4 H5 Y+ d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& a- U% t" X* r, ~! ?6 Q, p' c4 ZMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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