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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; @: }' M+ c6 `7 Kinput mcasp_ahclkx,( `$ t; y: k& n! e
input mcasp_aclkx,
. e# U1 T9 I7 Minput axr0,6 C7 C; u! @- Y' A
2 y" n& H! x1 c% s6 ` [- Xoutput mcasp_afsr,; N, N9 P0 ?7 o- ?* \2 i
output mcasp_ahclkr,5 j. m& D5 i6 N
output mcasp_aclkr,0 @8 d8 }3 @1 a* Z' U. R
output axr1,% n: ?: L' Z9 q
assign mcasp_afsr = mcasp_afsx;' s: N: o! E% X# ~
assign mcasp_aclkr = mcasp_aclkx;
) q" ~; z$ e' H; L! O' zassign mcasp_ahclkr = mcasp_ahclkx;
, G( w" o, x/ I* C) v @/ }* J$ Xassign axr1 = axr0; : W7 r/ j1 r* x d, n
+ g' q! L# a N" Q- m1 d2 o- N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ' S- L# a! p* P& Y3 t7 `( o( n
static void McASPI2SConfigure(void)7 I" s2 j4 c) v7 ~( ?! B5 P8 f
{
0 \; O% O, f9 d; H5 S8 v$ wMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
# e5 W+ v% `: E* RMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 H# ~& ^8 V8 _1 [$ ?4 Z0 e8 f: m! B
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
, \; o! V( N) ~( H6 RMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */* E5 ]1 i6 I7 T' q+ t: ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, o% {* f" _ \# @* @* RMCASP_RX_MODE_DMA);; x' O4 q9 W7 K; t4 ~+ p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& Z: P. [$ u% X0 T6 d& p) {! _/ @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
2 Q; ?# Y5 Q' aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
0 ?4 n7 ~( z$ ^/ PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: e; h4 J* }- D6 U* ~: Q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ( ?6 {; }* V! T+ }; {+ p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 @% F: S8 D! K# S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! [( c" _6 d2 nMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); e9 i5 i6 i; a4 t
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 M' v2 i' W+ L5 O+ G0x00, 0xFF); /* configure the clock for transmitter */$ l* u3 s8 O! N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
# p5 Y, j& i, J# W, CMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' o" I6 L1 l" c( j5 Y, Y& G
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 U k& B8 y+ @6 [3 z
0x00, 0xFF);
* y5 K" a Z* w1 T! @6 ^( [4 _
$ w9 d; _6 Z0 i4 ]" k4 m/* Enable synchronization of RX and TX sections */
& [/ d* {8 R6 q; H; UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 Y0 ?* _0 M* q: S: iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
, J+ ?) q1 a; D' m$ R* UMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ V, C. ^# Q$ u5 z
** Set the serializers, Currently only one serializer is set as8 l* W$ b O- ?0 k }* c" F
** transmitter and one serializer as receiver.
; E/ Y8 u3 ]( I) J. D, M' g*/8 d: D/ k t5 W" e4 h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 a, I K9 v' Q, L8 g# J$ n( pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* }8 F: p% Z1 L4 Z( U$ I9 `$ I** Configure the McASP pins ! e! W" l* D* G- x4 U( z
** Input - Frame Sync, Clock and Serializer Rx
" o+ P* X e( r* U& A5 H6 [** Output - Serializer Tx is connected to the input of the codec
) v) T( h0 V2 L: Z( |6 w3 [*/! C0 {' w% M. e
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* h X9 t/ W( [
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));; I7 |9 v* H% D$ U7 S ]; g) Y
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
+ @" N. ]9 w) ]4 u| MCASP_PIN_ACLKX0 E' h4 q8 r. J. \3 r
| MCASP_PIN_AHCLKX$ i& r; j6 j" P# S( e; j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 D6 w) ~5 T W- j# H* r8 }: z8 lMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & q+ m) \; K/ b4 i# M4 a* E' h5 q# S
| MCASP_TX_CLKFAIL
' ^, ]1 a0 @& u| MCASP_TX_SYNCERROR
( J1 B3 ~; m) R& y4 `3 F| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR $ j" c$ o8 C# x; I$ A4 X6 S9 v( i
| MCASP_RX_CLKFAIL: p& t) z7 N4 H+ j& P
| MCASP_RX_SYNCERROR
; Q/ r$ u" u5 p+ G| MCASP_RX_OVERRUN);3 ]3 C4 {' e! n" p
} static void I2SDataTxRxActivate(void). `( f$ R1 o0 R, S
{
9 N4 ^0 [: Q4 B( B3 ^8 p# @ f/* Start the clocks */
% O7 W( i7 T7 R& P7 sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 N% c& x% A G4 X0 KMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. F$ `8 Z" R/ J4 X2 sEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% ]- q1 J& c4 C1 ^
EDMA3_TRIG_MODE_EVENT);! c* O( J( C8 O3 a" [" Y
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* t( }1 ]% u( [1 c) OEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
9 V( L0 n; i7 t& t& P' jMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( \* o4 w, `. @" z' J4 u- k# oMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. b8 |% K8 h+ b, I) k: k$ x( i) jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines *// o2 E& G5 n9 m$ S k/ V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: ~7 u/ `. @ X% F* f3 o {: f% h
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& h* \% k- y3 w: w/ Y6 e$ e* [4 P
} ' [/ E0 h) h4 } C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / A4 z: {/ J4 g* q
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