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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# |) e: s" R: \$ zinput mcasp_ahclkx,
5 B& d2 s1 Q" Sinput mcasp_aclkx,
9 ~8 P# B+ P% a$ }0 Kinput axr0,
J0 W7 @1 V, P* l1 l( f( m. x/ g, k
& i' w6 D3 R& G& x" V7 D; ~7 doutput mcasp_afsr,! F/ i6 ]/ B% T% @: W" B
output mcasp_ahclkr,
9 W y3 c' ?+ k4 loutput mcasp_aclkr,
8 j/ N" @* C6 R6 \' Foutput axr1,$ [- G, X/ K1 K
assign mcasp_afsr = mcasp_afsx;% F& \$ g1 G: C. y0 V' m) I# e
assign mcasp_aclkr = mcasp_aclkx;' w) n/ K/ @# j* p2 s) J/ g+ i' q
assign mcasp_ahclkr = mcasp_ahclkx;
2 e* u% F" v+ r) ^5 s2 |/ yassign axr1 = axr0;
3 W8 t# l8 q) y1 _: V; J1 O4 h! \, h3 @; Q; y Z6 F) N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) i8 E' i$ E! B$ @! W4 s7 r1 zstatic void McASPI2SConfigure(void)6 s" G/ N) n+ L' b, K
{. I. e- i8 n; S5 U5 R$ M# i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% T8 [% j" M* K7 c3 W! @+ A- v6 lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
t2 e. `: I4 }. l' H) T; dMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: E! M! o' X% [0 h9 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% v V; w% R" ~9 n$ F7 |* m& bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ c; \% ^1 T) X3 V# S& ]+ C4 c1 q5 F+ NMCASP_RX_MODE_DMA);# x( E5 V8 O& ], R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' {5 c6 |& P; t6 f* \: l5 Z6 WMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& i5 C+ Q8 Q' ^8 C* Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 o* ~+ E5 R8 {/ R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! w* _: k5 I J4 ?. W/ K- l9 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, * K" X/ u0 t% h- S* X" a* K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( {* u# O* I9 H3 F! ?+ v" B
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' I; B- p: p" K" P" K
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 e; x ?" ^& {1 `1 j0 aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32," R& \4 @# z0 n3 M. f- b
0x00, 0xFF); /* configure the clock for transmitter *// c+ A) i, h' M( Q. j1 F
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: R/ N S* @! ?# b2 J E
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); s4 T3 E0 `9 @
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* a7 p6 |4 C* l0x00, 0xFF);
/ ]0 G) T- G- \
6 ?# [2 A L! `; G2 n/* Enable synchronization of RX and TX sections */
, [/ ^0 F' s' }5 H8 c5 x$ o7 YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, W; R8 p8 ]+ B" e3 B. f6 `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);1 @9 Q; a& r+ l4 d9 f
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*5 c p2 B3 g. c
** Set the serializers, Currently only one serializer is set as) ?$ U8 P/ j2 }) e/ n# r4 ~
** transmitter and one serializer as receiver.( t7 z0 s) x' [, [: }3 @
*/
. V b% ]# T" d5 xMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- R& ?8 w& A/ s8 S
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
$ b, T' ^# V% X* J8 g2 [8 Q** Configure the McASP pins 7 D9 h7 \9 _$ m+ M/ l
** Input - Frame Sync, Clock and Serializer Rx
: [2 w) I0 N: d8 z** Output - Serializer Tx is connected to the input of the codec 7 z& F: t+ O5 i- r1 l( Q
*/& ^4 G0 z6 `5 f3 u
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ k, b( M; ]6 k5 C) T6 a FMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ ?0 |' D$ p9 R }. J& zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 r: M% u+ Y! n W| MCASP_PIN_ACLKX: c, g$ E! L" |4 g& o: r. B$ d# R: a
| MCASP_PIN_AHCLKX1 ~. Y. C n- ?) t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 U* K3 R: |+ p/ FMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* h* _+ n0 f) H S4 N$ W| MCASP_TX_CLKFAIL
% R# Y; B8 }: @) ~| MCASP_TX_SYNCERROR! Z& t4 |* [# k! y: A4 Y
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, E8 {6 j# W) _8 ?; h| MCASP_RX_CLKFAIL' }0 g. R+ z7 X( Q/ V* f7 s1 y
| MCASP_RX_SYNCERROR ! i. ]1 e e4 k* H( I$ ^2 S
| MCASP_RX_OVERRUN);7 F9 }- t, x; a6 T. I0 L- L. M
} static void I2SDataTxRxActivate(void)
# E/ I' v" A$ Y$ A4 j- x0 H{
, @* A% z7 ]0 {4 u* C& {6 o/* Start the clocks */
: |" b" b0 S: DMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
: [$ E# d: T& I4 m. p* a6 OMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) b& f' E b9 g2 t2 k' ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 q* Y* ]- P& D" H/ A. C; Y: Y
EDMA3_TRIG_MODE_EVENT);* r7 q1 `1 L4 {* n& ?# n. o9 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
C! B! [+ f7 Y) ^- yEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ O: F4 M! K/ |, k' r" ` B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) E2 J! `6 ] k& X1 u& O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
! b' p9 K1 ^+ z% ]0 ?while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ w! s# w& U: l' {3 W5 d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 I1 _. Y* B2 l0 d0 XMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! {/ h9 V- t4 m2 b) Z& R8 c}
" k; T5 H2 h' l请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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