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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
4 L) @, t( L; u2 R6 Ginput mcasp_ahclkx,
. f/ A3 _; a7 Yinput mcasp_aclkx,! S: b. x- b7 q. l) W6 S5 d
input axr0,! c, _1 N( w0 I
* M& I4 C, [! w1 J% }output mcasp_afsr,
) J, r4 ~4 Q2 N8 B! Woutput mcasp_ahclkr,
j9 {; p9 w& U& ^3 `8 K( O- `output mcasp_aclkr,
7 o9 {* u% a% C9 X# J2 v) N! p- v7 `output axr1,
! i; ?/ k9 b& _2 I! Y assign mcasp_afsr = mcasp_afsx;
5 h4 E" ^% Y+ f: y" |/ ?' X7 massign mcasp_aclkr = mcasp_aclkx;
( q$ }5 r. j' t/ ]" C( o3 A9 O. nassign mcasp_ahclkr = mcasp_ahclkx;1 C, K" g6 s: a- G! [
assign axr1 = axr0;
( ]% ]/ Y* P, P) W# o6 l$ W- z6 B" z* G
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 , V" e+ J0 a$ _$ M
static void McASPI2SConfigure(void): ^; k: Z3 z: }. A
{
8 [8 Q) \; I) d# B4 A5 [8 n5 c) CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 a9 A" u; P! r8 @6 m: JMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- q; l! R. S8 n2 oMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: }, ^5 D& {$ _ B/ g# d$ f5 c
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 u6 ?8 R6 f0 v" q3 ^9 hMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, H: s8 b. h6 ~, w: g7 I! z& b' }MCASP_RX_MODE_DMA);
' o1 g) H8 L! Z _9 X( eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," m; l( j2 n) U9 a) E
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */& K# C' u7 v4 x. S( N0 v; K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% i3 U3 o5 C* ]. t$ Y7 `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 h9 K2 z& M- a% ]! U9 ?) O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, : R. H7 s- q2 q% {8 ]! W* E
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
' x: }' X( l+ _" h4 h0 xMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
9 k- Z- D/ ~- ]4 K' pMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ; Q3 Z2 o! j% J5 I$ |+ K7 n& K
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,& r/ d2 Q( v( o6 [% r0 q; H
0x00, 0xFF); /* configure the clock for transmitter */: K9 b Z- E- Z1 P$ X
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);! a# S. p; _& Z' l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) m6 J1 N( j2 o, PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ m' Z# o" j& s' B4 Q
0x00, 0xFF);" l0 {& p% u. }8 e8 h
% D8 |4 \ Y. V3 I
/* Enable synchronization of RX and TX sections */ 5 F- f! v) o8 W1 y8 d( s8 w% S
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) @- z" O7 F/ h |* p, K" X1 n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
" i& K$ L# {5 n7 L# |; ?. X8 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
9 Q) j: o* {+ {" Q9 p- u3 y** Set the serializers, Currently only one serializer is set as' j2 U; W4 h! K- {9 T2 K- m' H
** transmitter and one serializer as receiver.8 X# ]8 N1 x8 Q2 U" ^2 [& A
*/
6 @: x" T0 u& A& V4 y, l$ c, eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 _- X( w* m1 }5 b. |7 O
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
' M9 d! P, z- q# |& z6 J/ Y** Configure the McASP pins
! F; j* y. z% O0 f4 c# U** Input - Frame Sync, Clock and Serializer Rx
' n/ {/ @4 y9 W6 ^** Output - Serializer Tx is connected to the input of the codec
( n& P' s% m- l*/
' O$ A- a. p7 w/ y3 I# E8 qMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: B5 X% ~8 C+ _7 A: Y' N* \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* _6 y7 m. L6 B+ q, b% q' @
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX' n2 k- T# s: U9 L M9 C' C* d ^
| MCASP_PIN_ACLKX
/ R3 i L' T% ~2 b/ V3 F| MCASP_PIN_AHCLKX& d! a% I( N. ~& G" c$ d$ \
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
4 U7 p! W: W0 n$ \McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . ?* P ^) m2 n
| MCASP_TX_CLKFAIL , ^9 S9 Y" T8 F4 _- C/ a
| MCASP_TX_SYNCERROR
8 g# w0 z5 x! f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) f1 P# p: s3 R3 k) C% |+ r& m
| MCASP_RX_CLKFAIL
5 b0 b3 `5 c5 p" k* R& i1 y| MCASP_RX_SYNCERROR
3 X- c4 c4 N7 U( I( y& a8 G| MCASP_RX_OVERRUN);
$ g# g7 v( Z# Q9 r9 Q} static void I2SDataTxRxActivate(void) N: m2 `1 I8 {. |
{
7 `7 A4 i1 @4 L( a6 ^- q/* Start the clocks */7 G) {% w) W& r/ {
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, K$ C5 B# |, T$ h1 @
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 _; q9 S% L* _5 y1 w
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,- X, }! m T1 ]
EDMA3_TRIG_MODE_EVENT); }6 K/ d- K: d# A! n, G3 E4 i$ p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, . t, Z+ K/ U3 a' Q4 c$ [
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */% `: E4 s7 z$ Z2 T; p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 t) u# v1 ~" V! }4 t3 cMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 E- _$ u) z+ b2 g) H0 f6 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 C' W+ S( f! A' z% ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);* Y5 N6 G6 H4 K; X# ]' T) s
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ p" `5 L, w0 X0 v: [} " v' W- k, t0 l$ u* \
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 t, o) j7 Y0 w4 }
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