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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; t- \# W* c5 y8 a. B6 E
input mcasp_ahclkx,/ C+ h' a/ p9 j! Z
input mcasp_aclkx,
# Q& ^3 z" I& linput axr0,/ b9 o$ N6 M) f% t8 ~' j0 u
; ~8 b% E+ i2 `8 g, j! Joutput mcasp_afsr,# x! y2 m3 t+ V
output mcasp_ahclkr,$ c' O5 F7 Z6 c/ O4 ]! B$ i
output mcasp_aclkr,
1 \1 P# H7 @$ `" }( Uoutput axr1,9 C0 U3 p$ [1 E& a6 P& b
assign mcasp_afsr = mcasp_afsx;
1 L' [0 s! L4 |assign mcasp_aclkr = mcasp_aclkx;
' b1 M: A3 [0 ^4 g4 l& Cassign mcasp_ahclkr = mcasp_ahclkx;
* E7 l% L$ e8 iassign axr1 = axr0;
1 V/ v3 J% @& O- |( s! ?4 g/ O, e
7 V. I: o0 p& f( D6 `$ c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 G7 Z Y- I( o$ a' T; q
static void McASPI2SConfigure(void)+ X; ^. h: f) n$ k- K A
{5 j7 d& b% J$ o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);. D' e7 Q4 f5 ?0 h
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 m1 L! K: O8 Z+ ? d! zMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ ]8 L7 [8 K: WMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 H" G" j: C- d* ^6 ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% Q- S$ _9 m3 y0 b/ B. y r/ |0 \' {MCASP_RX_MODE_DMA);
7 o& s1 ]3 \+ \( B7 @$ y7 qMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ J3 h2 ]' @! }% Z% K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
~& v, |1 @. iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, + ^$ M6 s; j( s$ E( z3 U$ q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);- e: Z9 i! d4 q
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . w3 g H$ m+ I1 M% R
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 I( q; d# }# C6 z3 G1 H( X- e1 t2 UMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' i4 e1 y( ^! n9 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - a8 @# D3 @8 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,. ^% E6 c4 b: {( C
0x00, 0xFF); /* configure the clock for transmitter */2 Y! I8 s4 ^# }4 f, f7 D( n: _* n
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 \7 u( X: h" U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 G" T/ I2 |5 D9 iMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ a+ @: g. x/ r' S2 |) I0x00, 0xFF);" W8 h- P" l: x2 g
% Y/ J% P; y% P, X ?/* Enable synchronization of RX and TX sections */
1 {7 Q, m+ H" W tMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' b9 }- a" p" H* c" iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
/ I3 t8 a- k7 h J" V/ HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*! q* ^0 \2 `1 e& v$ m+ j7 P3 |
** Set the serializers, Currently only one serializer is set as" x8 f4 }; v, S
** transmitter and one serializer as receiver.
6 r3 m: Z X5 }*/: P4 p; x5 f3 z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, P5 j: R1 `! w1 c: [
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
0 Y% O7 A! J8 N** Configure the McASP pins 4 X6 d: q5 k5 ]. V/ _8 n! S- _; X4 M
** Input - Frame Sync, Clock and Serializer Rx1 P" v. m. p$ c0 u
** Output - Serializer Tx is connected to the input of the codec ! L# N8 H9 c! W4 _4 p
*/! V. s' E( ] g+ D8 d1 ? c' ]
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. s+ ` J }9 G7 A* i( { X' D" |
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' L; ~7 {0 k0 y! ZMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 s3 g- C C! ]2 f8 S# F0 K
| MCASP_PIN_ACLKX
3 n/ L' y5 a: |% T( q| MCASP_PIN_AHCLKX
3 Z, G) ^% F% e* s/ X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 J4 _) }4 U/ a; k! a1 S. F# aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
! W! P2 @9 j0 r/ ^! P$ h5 ~| MCASP_TX_CLKFAIL
* O* w$ z2 G; g5 v0 k| MCASP_TX_SYNCERROR% t5 W' ]- J! [' j! G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
! R7 V7 n; I5 q0 O4 F| MCASP_RX_CLKFAIL' B. R8 H8 O ~1 r; d
| MCASP_RX_SYNCERROR
8 u) S( _/ M% o2 q" ~| MCASP_RX_OVERRUN);
& o! l. D \ g0 q! b+ Z% H( q) g7 m} static void I2SDataTxRxActivate(void)
2 V4 T# y @) @& \/ F5 P{& @) ]- _6 R8 Y- A: z4 J1 I
/* Start the clocks */
* P+ b" a }% Z( Y; w4 L+ SMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
/ ?0 `+ }0 ~( d7 RMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */0 |$ m0 }4 E: V$ o8 V6 o8 O; D
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, S) R! y9 W$ M6 ~
EDMA3_TRIG_MODE_EVENT);
! a" y4 i7 d' J* ]3 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 u" }8 {5 V# g' k) xEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 {7 S8 W& |: |' d0 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: P6 _* G# s K! S! KMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 A( t& B6 T" p) Qwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 C- \( \& z, `; T
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 F3 H W* p: q0 u8 k& {% iMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
/ c) p, W5 u* `8 ^; D: `: e( j- O}
- o. |0 m$ A: E b3 Q& W' i请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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