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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; t5 @; P1 ]6 a' K9 @- p8 [input mcasp_ahclkx,
& f0 m1 w# F; H% P* ]input mcasp_aclkx,
/ a H% u3 q9 l' i. _input axr0,, {! m+ a* M+ b8 Q+ Y9 |0 ]' d
7 q" M# g+ ?: P2 t( D( Qoutput mcasp_afsr,! a3 ]" C l* g, v* i T
output mcasp_ahclkr,
8 @6 G& g: R% p' J7 Poutput mcasp_aclkr,$ G* l* j( W' I
output axr1,1 g/ p4 i- T( j- u
assign mcasp_afsr = mcasp_afsx;& m) c |, h1 ~- G
assign mcasp_aclkr = mcasp_aclkx;3 p9 m# G) X6 p% K5 j; A7 G
assign mcasp_ahclkr = mcasp_ahclkx;
1 z4 B. w6 R* n& S9 Q! @assign axr1 = axr0; : G+ u7 g! ]% u1 A: J6 R
! R: b/ @( `9 M1 W0 @在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 + F+ R; B9 ]7 q) h" G
static void McASPI2SConfigure(void)- H9 b6 a7 f% Z; D/ C: g( Q8 D
{2 I! Y3 ]4 y( ^( v& }
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, r# c% H# W! A ^' XMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 @! X- M7 ], i8 w# h3 T. r+ qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);/ y( ^, \2 e+ w [8 [' i1 e. A3 @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
* t) _/ e) O' y/ t& Y# }McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- c: s8 q3 } h. ^( Z- E, eMCASP_RX_MODE_DMA);9 F8 Z, b8 w1 E% c; R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! ?2 s7 U N* ^: S, U: I) |MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 X) m* P* V" ?; h' ^$ @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 s. V/ {: E, R& Y! f8 ^' t) {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 `% f- g# _' v* ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, $ \! _( ^/ M, S# U, @- G/ `( ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
5 U% q' H& ?# U3 R/ U9 v$ [0 U gMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
) Z2 w1 W6 n0 `5 }& V1 p' X, gMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 `) L( t+ p! `, u' d
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( U+ |/ z0 p2 p% c7 N0x00, 0xFF); /* configure the clock for transmitter */
1 }1 |" z M" T" M8 l" XMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 X7 J' ]6 r9 d8 s
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ' U0 ]9 R, |2 B& {8 A; s U p
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,; e/ B2 H2 [( _0 p
0x00, 0xFF);
5 O5 `+ t; N" ~/ E; K# B/ M& {6 j5 N. k+ E
/* Enable synchronization of RX and TX sections */
2 `7 x) {) p% {" t7 rMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! X% t1 V( s [( {6 y+ Z( y: W* `McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 _2 |" x% ] r! _4 m: D: N+ F- IMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*# t6 m; S& l2 P7 M0 h
** Set the serializers, Currently only one serializer is set as
5 \6 o* V6 M" z1 F5 V! h** transmitter and one serializer as receiver.& a9 ?2 R+ ^4 ]4 p
*/. }( t+ u E' U) Z# N
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);& t& ?: B0 o {9 T6 a" w/ N
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
5 b* r/ u' K3 Y9 r4 t# v3 K** Configure the McASP pins ! E' ]8 B- N& [2 d& m- \. w
** Input - Frame Sync, Clock and Serializer Rx
) ~8 |# D% J- ^3 h; g** Output - Serializer Tx is connected to the input of the codec
0 X4 K* m* N+ T7 }2 M9 J*/% B" I- p; \) A& T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. b- v2 y. ?$ A, r6 h" p
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% {* R' J! U3 r& c( CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
7 t5 B. c9 {4 q| MCASP_PIN_ACLKX
4 T- h+ p! ~7 i| MCASP_PIN_AHCLKX* C% {/ E5 ~0 Q/ g' {/ e
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
# j1 K. s2 t4 g! O/ G6 r( W% ?/ t9 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: Z, `) a3 o( R0 s| MCASP_TX_CLKFAIL + t9 ^- P; n% [2 T6 ?- |
| MCASP_TX_SYNCERROR
. P% J/ ?% ~" N; v' d0 z7 S) || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! i! i7 B" k& U7 D2 l; J& i
| MCASP_RX_CLKFAIL
2 O' w$ s8 J, Y7 J+ q& r| MCASP_RX_SYNCERROR . A( P! G: v0 q* W) j n$ T j
| MCASP_RX_OVERRUN);
( B0 p x2 d/ J5 x( j f' _! ~} static void I2SDataTxRxActivate(void)
# ?1 x! ?5 a9 X- T+ f; f: t{
* Z; y7 K# W9 [/* Start the clocks */7 F9 o1 [, Y; L0 }) `2 c. _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);1 Y R0 i+ }& M: W7 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ J. y/ z2 m: ?) \4 w5 a0 R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! ~5 `$ i2 n- M/ Z1 Y' }EDMA3_TRIG_MODE_EVENT);" Q& ~$ B& n6 A7 s3 G& R) `
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! o# V2 n. ?4 ^/ [" ?EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */: [$ M, T) D# T: I
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);6 Z' w( B$ `4 K3 Q+ Z; t: z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */$ _/ Y/ U' g9 ~
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; `9 o4 H7 Y \4 \
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# V. G6 j" ?+ L/ z) \3 k
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ W) z* ]; I2 J! e5 O1 F! T2 U}
9 ?+ a; Z; b( f* G, J& f7 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ( a: ^$ v' Y$ p6 I5 M3 @7 T
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