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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
; V* k+ w( `' C$ z: Finput mcasp_ahclkx,
# S9 ~9 P: L: P4 f% Hinput mcasp_aclkx,5 b0 O* {3 l2 V3 G
input axr0,$ B) N+ V2 T% S) a: N# w1 d: ^
& p7 c9 d* u( N' |" T
output mcasp_afsr,5 m7 M0 C" i; v7 S
output mcasp_ahclkr,
6 D6 p, E5 s: v) T$ j7 poutput mcasp_aclkr,. y4 O4 ]) ^' e; w; ]
output axr1,: I. L: c5 L$ M- o
assign mcasp_afsr = mcasp_afsx;; S( r5 h( v! Z, N
assign mcasp_aclkr = mcasp_aclkx;1 U( `$ H1 l7 ^1 F' H5 A3 P1 M/ Q
assign mcasp_ahclkr = mcasp_ahclkx;+ K' a. y5 F9 \$ I
assign axr1 = axr0; : @. P; n1 ?" n1 s& j
K0 i1 t* g' p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; h9 m% T* @* q' K; ~; ?" ustatic void McASPI2SConfigure(void)) c) {& @9 e- s& H- F5 i* L+ O' U2 H
{
# g- P6 q9 N4 |' RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
0 g7 M/ A6 }4 e0 J' P- e3 SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. `3 V% J" Z3 h1 h
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 |* f; G& J( k" jMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */) D$ m4 \+ D8 F: A0 s% d( ], R i0 R
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 N; Z" c0 W2 G; g L ?3 xMCASP_RX_MODE_DMA);
! u( F# \3 N6 h' o; i4 V& S% w- \0 eMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% n4 o2 D, }1 p, V& K
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */* Y" S( I8 ?: S6 m/ H6 f' \) l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : X( g* n6 O" c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) I! z! r6 D; b; U" ?8 x2 O2 p( rMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
! ^' w. z2 v: M& L- [MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* i( {2 W8 c# B+ e+ a1 qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
a4 ^9 l1 B' v. b/ E5 F9 U. ?3 L( ^McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
1 W+ f# P3 [; l* h8 l" G. kMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, @% l3 B' i0 b4 u+ [* p) D5 j
0x00, 0xFF); /* configure the clock for transmitter */
" r% ~5 T& g$ O% b& \# _9 VMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
! I( {" G" I: f; }McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . s$ w! k* k9 Y; Y2 a
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 C( _$ ~( Z" J( r0x00, 0xFF);4 x) X i: w! ~* a3 _
_+ R5 A- J+ J/* Enable synchronization of RX and TX sections */ & A6 p4 ^0 _( G( [7 l4 j
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 g/ M0 s/ J6 K% ^; w: r' w, hMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 X% I( P& J) x; H/ Y/ [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 @8 w& [. \4 l8 V5 n** Set the serializers, Currently only one serializer is set as
% J, z, v+ j) K% o3 r( t3 y/ ]** transmitter and one serializer as receiver.
* C' _* {( j* R. J*/
; c- ?: h% i7 [8 C# rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, _3 F. M; l; f% j u/ s! }0 y0 KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( d |) X. ~" c1 I1 H+ \& ~
** Configure the McASP pins 2 }$ l4 O8 ?: O& D
** Input - Frame Sync, Clock and Serializer Rx
: x! J: z/ B: T2 ?2 \& u" P. A** Output - Serializer Tx is connected to the input of the codec 6 ^: J4 M7 \1 s4 q' {8 i6 q
*/
9 O# v5 s1 u. G! OMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' B7 e6 i. i. o4 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, \, T) ]3 r$ ?; i, F1 zMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ g& P5 I& _6 q+ M& l) G0 |' n
| MCASP_PIN_ACLKX
& t3 r1 W# q+ C/ c; n, t| MCASP_PIN_AHCLKX8 h+ v3 P T6 q d/ R7 ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
$ q( c* l. \3 L* a vMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
l9 M! W* Q+ h# c3 |$ N) \| MCASP_TX_CLKFAIL
3 r% H- y' P) ]/ @& f3 P& K4 ]| MCASP_TX_SYNCERROR
! _$ ]$ T! p; r5 ~. D2 Z| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) E% y4 e* J$ E. M, X5 n. Q4 {| MCASP_RX_CLKFAIL
~ i8 \# O" v6 j7 ~1 O" l| MCASP_RX_SYNCERROR * H6 \- `0 G: X7 m
| MCASP_RX_OVERRUN);" ~2 h Q: c( K/ r- }+ e9 d
} static void I2SDataTxRxActivate(void)
% q/ ~$ T4 B+ B0 \4 t! e{
, J$ t) w$ r3 {/ t/* Start the clocks */
8 s+ B' O" z% Q; a+ kMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 x4 q. t; y$ m: B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ m! P& y* k# O# Z) U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
$ u8 b$ R- s: k+ p9 SEDMA3_TRIG_MODE_EVENT);
N; P; j7 H ^8 M! e) yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / R4 U0 y& J! ]! J' U. a% m4 L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ n6 S- ?( X- i/ z5 p- t4 ~2 k' Z6 B
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 v. n* m; i) J$ `. O0 l2 f: ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ D/ e3 s3 x& V! }. I" U- fwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
3 D$ m- Y! I" U- y9 e D$ _8 MMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ }7 w$ Z# y' OMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# J& p5 D- q8 N+ [ P} # T$ G/ S* X8 j6 e/ b- Q! i2 J6 b! c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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