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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 S9 ]3 C, U3 z, [" binput mcasp_ahclkx,
2 c+ m% i* L! p1 e3 Q' D6 O- l# minput mcasp_aclkx,2 J ^2 Y% l' p' U" K& F- f, c
input axr0,
& E! [; r2 q: ?3 Y
' E- c1 ^1 g; k X7 Woutput mcasp_afsr,7 j! ]8 [. M3 M4 V, ? n7 \
output mcasp_ahclkr,, V$ Y- k$ {) w/ p' h- T
output mcasp_aclkr,
5 [; [( Q: |5 l5 m/ Doutput axr1,! @, C/ P0 `2 D* n' Z# K
assign mcasp_afsr = mcasp_afsx;7 D: O u8 u7 a H7 d
assign mcasp_aclkr = mcasp_aclkx;
4 Z" x1 M* F( R$ Massign mcasp_ahclkr = mcasp_ahclkx;
w3 v3 s/ l$ n0 s" x# aassign axr1 = axr0;
2 e" {: c4 D5 T6 m
5 X$ \# e! w8 Z2 O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : X q( q, E0 [3 @ I3 S
static void McASPI2SConfigure(void)/ i* C* D3 D3 }2 u) X
{
8 l1 Z9 R$ z1 B1 i9 sMcASPRxReset(SOC_MCASP_0_CTRL_REGS);& `/ ~/ c. @7 P$ S) J7 N: I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! ]6 V1 X/ @" c [$ o& rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" H1 N8 E% J0 b$ j: s- Q2 A9 ~% HMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! [; {6 l, F+ u& Z2 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# J9 R* l& |; h0 W, A x" ?: R
MCASP_RX_MODE_DMA);7 w5 e' R# R( W$ y7 \ A: U0 P
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
0 o, @, u! j9 \MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
. I+ {# x$ d% y4 D6 ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ F4 I9 N' R8 t* U, d6 n4 }6 X/ j% PMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, t) Q1 r, ]' i& L" C; ^( N9 V6 A; w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' k- c% f- ]% y p3 k T0 X6 DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- k9 x: p* _& d9 D$ e, XMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& y+ l6 _9 R0 J6 V9 \ FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 2 r" V' n1 ^" N B' ~/ p/ n$ E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( m4 f* [0 g' o" Q I+ x6 i. |0x00, 0xFF); /* configure the clock for transmitter */' U0 H1 }3 u, s1 w, ?; S$ ~4 }6 ]2 ]9 e
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# @3 [3 x2 g/ A& B% g9 w- s4 f
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); , R4 I. x. e: V
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% c( M* \+ R: o- H' N2 t
0x00, 0xFF);0 [) o6 [" a3 I# o
5 M5 z4 @6 V) c7 p/* Enable synchronization of RX and TX sections */
, d' P, a+ z3 D" e9 ?# H+ V! WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( @3 i4 b# i. I9 f$ s- b' P; g+ ]McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
h" R5 }4 H$ j, I5 a# @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ s- S$ \. {2 b2 u* \3 L m
** Set the serializers, Currently only one serializer is set as e2 e& }, U& r. }% ]
** transmitter and one serializer as receiver.( I; Y4 D, r* r
*/* A# O0 V. ]. l. R) g4 }/ L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ H1 t# z+ B$ Z: }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ h! V4 p- a K7 ]" z
** Configure the McASP pins
5 X# e* r5 i: h5 i** Input - Frame Sync, Clock and Serializer Rx
9 e, v& O' K: j** Output - Serializer Tx is connected to the input of the codec # P0 M7 C7 {6 i
*/
; a1 u+ Q: L, U# G) L" p4 ^+ q3 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* }" t% U: F$ x0 p) O
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));* Z7 O1 Y' W/ j6 u3 u
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
j0 g% ^( v3 V" ~$ L| MCASP_PIN_ACLKX9 ` E4 {0 @8 m2 N% S! E
| MCASP_PIN_AHCLKX+ p* k4 d. T$ Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 A5 N9 s/ d4 ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; {/ Z& @2 O' Y4 k8 u4 ~, V4 P| MCASP_TX_CLKFAIL ) }& r; Y, E6 X/ A3 X! S
| MCASP_TX_SYNCERROR, t. p8 h2 t) E5 n, J( u( T5 Q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* r3 n6 J; n7 M, ?7 d. l| MCASP_RX_CLKFAIL/ T+ F0 E5 b; S
| MCASP_RX_SYNCERROR
$ J+ e+ F. u- r5 g3 A7 N9 O' P' S| MCASP_RX_OVERRUN);/ d7 N9 @& S- b4 L* |# E
} static void I2SDataTxRxActivate(void)
5 X- ]& S) l; r5 w. _{1 V) p& n) i9 L/ G' U) b! n
/* Start the clocks */1 j' S$ s, L3 M7 `1 g/ U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 B) C$ z* }2 U+ b, IMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
' y& h" R5 F4 D5 _; A/ pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 W/ D) S7 |- |* h( l% E1 m8 b
EDMA3_TRIG_MODE_EVENT);! \3 J z* Q( W# _+ t
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 N T( r# Z* n- _( s! L0 e
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( J, [ c; k z9 LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 N+ I# C: ~( XMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */. l- w- ]. p. }3 y0 S2 T
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; m$ T7 D4 t& x( }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
# a7 ?' C4 c5 ?5 Z* o. x. }6 |McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
$ ]! G. K% ~7 |* k" N8 _1 B* k} ; p$ x. } ?% u( W& K/ |! c j1 M8 k' S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * {% b0 j4 H$ ~
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