|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
1 ~3 l6 M: I7 I0 u' sinput mcasp_ahclkx,
9 ^* b4 {% I0 s q% H& Q# e- z3 kinput mcasp_aclkx,9 W8 P7 Q4 `5 _! x) Q$ i
input axr0,9 @ R7 |+ \! Y
. c8 n1 d4 T+ X8 t/ Noutput mcasp_afsr,
0 \. H |7 H8 ^* h9 H. ?0 xoutput mcasp_ahclkr,
/ ~ F C6 Z0 R0 moutput mcasp_aclkr,
) C# i! G, T! k( o: r4 U" zoutput axr1,+ o& t" w. f1 y% b/ p) X
assign mcasp_afsr = mcasp_afsx;1 }6 X5 x$ I7 L1 } t
assign mcasp_aclkr = mcasp_aclkx;" ?; e. i1 r+ }! j0 h
assign mcasp_ahclkr = mcasp_ahclkx;6 s: v8 k- }8 |- Y, p" c) j
assign axr1 = axr0;
$ B9 z: j* L/ }, p: i- e6 H! @# }4 ]) l, L7 l
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
% g' I. G) X* n0 Hstatic void McASPI2SConfigure(void)
& A, W6 G* A) ^% v$ C{& V5 U! V @7 X# S* o
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 ~6 | k& v4 R& \; j$ G$ HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */) v4 Q; F$ F" M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% s* n( R; j- @$ _" q. b( Y5 V
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
1 I1 g* |! o4 k+ [2 kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! j9 m2 ?8 y% s% T, Q6 x9 i2 HMCASP_RX_MODE_DMA);9 m: n+ g' z0 m0 U8 [
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ u+ {$ F; h/ l9 h8 K& F
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' s+ ?6 Z- ~& A$ O' i
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, s% X' w1 a( o# a2 j/ L0 Z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: c+ ~1 A6 r' T" `+ _1 M: [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 z! z+ ^. x) o3 p& eMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ H, H/ z# `$ o3 x9 w( G$ zMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( y( M# g; G6 S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 y1 R# d2 M3 |* z$ G6 h, ^McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. {) i+ ~$ b/ T! X U5 ^0x00, 0xFF); /* configure the clock for transmitter */
8 ?9 K. b; z9 J; `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* z/ X! |! y- @ aMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); . } Z. o& F" z( D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
5 o, K) y1 W9 y$ V% Y" t* ^0x00, 0xFF);
: G9 r" j' S! h+ z: D
" ~4 ?" E; n# n' t6 R2 D/* Enable synchronization of RX and TX sections */ 0 C( R9 P8 N- e/ I8 ?- w- O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */: g" Y. J9 O; m2 R% t
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ H: K y7 O$ k& k Q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" E8 W( k$ i/ V) d% W/ v0 Y F
** Set the serializers, Currently only one serializer is set as
! Z8 D R7 P" t2 T; z8 q** transmitter and one serializer as receiver.1 [$ O9 g# q3 P6 u, r
*/) T2 H) A6 ^! u8 y8 W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ ]6 j/ t: _' E# M4 N! n% \4 m' l3 I
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*7 J' s& O" q, k5 Q$ h7 V
** Configure the McASP pins & I, L; \- t, x$ j+ O/ A
** Input - Frame Sync, Clock and Serializer Rx0 R6 s5 P4 k) G( n$ \8 r
** Output - Serializer Tx is connected to the input of the codec
- Q+ ~, y6 y+ Y ?8 l4 h*/. \) ]; _ D ?$ p
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
. v3 P. z" M" l* u( ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
1 p* C* @, e( l1 W9 W( `McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
8 }* z: m9 B# x( ^| MCASP_PIN_ACLKX& z+ v, q9 Q/ c+ R1 K5 S5 g
| MCASP_PIN_AHCLKX9 \. Z4 d$ z8 ^" \; B. u! u& t
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
6 O+ r" y' U- y( c* P* qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 u/ K/ T( y) {5 s* k9 ?" V
| MCASP_TX_CLKFAIL
! |/ k7 B% _# T0 I/ y| MCASP_TX_SYNCERROR
) l3 F2 H' ]& N- V3 {8 H| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
z9 I' H1 y2 C1 ?3 c, P| MCASP_RX_CLKFAIL& Z: o9 P/ R& G- P/ k3 t9 ^& D
| MCASP_RX_SYNCERROR 9 V2 T2 z0 `' r% P
| MCASP_RX_OVERRUN);2 Y7 X" }/ C6 x, I9 M9 S
} static void I2SDataTxRxActivate(void)
* Z7 F$ m+ C' f0 |# Q; ]2 _{
9 t* K3 |: T k) L& Y& V9 I/* Start the clocks */
9 j. o) H' S/ K0 \3 K4 T8 K e) M# |McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);- n8 q& u% [0 ]' |! [4 y& k+ a3 y, e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' d; V! a& { h
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
8 p1 ^' C9 G/ [+ hEDMA3_TRIG_MODE_EVENT);0 |, u0 V l# s: p( ~ X1 d
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 F; `, ^" m) T _0 BEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 v3 H# K& |( x0 c; r+ g: eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
. e' I4 k9 g4 b& D) {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' C+ v9 O( w4 v8 h5 I9 y- o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; u( i7 [/ Q% } o, U, {5 B' JMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; \- u( m; b2 Q J/ HMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ @/ v- l: U- S} . n" I- t3 G3 \. j) e
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 1 ~, m- }- o0 Z4 S6 Y0 O
|