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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 Q) n7 J- ^' Y0 i
input mcasp_ahclkx,
7 o+ j- B2 @& n; n% A7 q3 I, V4 Ninput mcasp_aclkx,
% ~( t0 x& ^/ Xinput axr0,$ L6 D; w1 W1 }# s6 M
+ x! s; E6 Z3 R( v
output mcasp_afsr,2 _% E6 c* S6 A" y4 m5 d4 S* ~- A
output mcasp_ahclkr,
' [8 [# [9 n" \output mcasp_aclkr,, p/ Z: B% [, G
output axr1,
" a" ^" v0 q; r assign mcasp_afsr = mcasp_afsx;& K) W; C! |/ d- a
assign mcasp_aclkr = mcasp_aclkx;
~3 X) V1 b) n) P0 Lassign mcasp_ahclkr = mcasp_ahclkx;
7 s. G1 @* q3 i; [" o9 _assign axr1 = axr0;
' c% W4 [3 }* z: N9 t% q$ M& f; |
7 ^* x6 E+ W: ?( ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 Q" g2 H3 s4 u2 jstatic void McASPI2SConfigure(void)1 [& e7 j1 E6 n" L, C H0 ^
{. x& a2 o4 s7 E( ^4 n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
" Z8 V2 f4 z% |0 Q9 a* Y( L7 y$ zMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */' f) C% c- }# i
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ R2 X P: J% B+ a' j+ Q* f3 gMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 t9 }1 P8 K( i, x7 N/ e" Y
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" k6 [/ w' w0 O: L# b- nMCASP_RX_MODE_DMA);( V4 \$ }: u" M$ p6 q
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 C6 V" n+ G% W; p1 F5 }MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 J3 W0 h; F* X1 }. [
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " G; a9 J9 L; Q) e6 H
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);6 a- V% Z# \' E# l3 H
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 F+ ?7 @8 C pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 N: K1 r+ V. G) ]4 ^2 y' w5 KMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
( ]( }' D+ }& ?; S) w4 p, O% \1 @: eMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 I9 R% N+ L$ @( I6 [McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 g: U: j9 p& A; \& D
0x00, 0xFF); /* configure the clock for transmitter */8 F U* \: t, u" I
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
9 t8 @8 h1 a5 N8 N$ E- V4 {McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); : r7 y& A% y. L/ U. p7 i0 \
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 Y* G$ l0 X/ I0x00, 0xFF);9 g8 h# B" y1 {8 P
" ~1 C, y7 Z$ i. q( N
/* Enable synchronization of RX and TX sections */
1 `* ?+ ]1 n5 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" _/ J. X0 b% o- F, l. y3 v" N* J
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 [0 o! v, `9 R- L
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
5 w- A/ \( n/ F& l: U** Set the serializers, Currently only one serializer is set as7 J% m1 P' J d0 Z2 b' K
** transmitter and one serializer as receiver.8 O* i: U( D, P: Z6 _+ H. W
*// C) m+ v" g: |4 H. J6 k/ r( f: s
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, W' \& p. O1 j' g4 v- QMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
7 w" R% }( Y; V1 z** Configure the McASP pins 5 \% |% T+ Z( L$ [4 O8 J1 e9 a
** Input - Frame Sync, Clock and Serializer Rx$ G7 Q' m( E* |# y$ \" L- O
** Output - Serializer Tx is connected to the input of the codec
* n5 I# G0 C2 Q( h*/- ~+ G8 h% P9 B( u! D+ S
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
/ W3 T. \' R6 N- n$ R% A9 J/ H' AMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
! f; E h R: ^" k) l, u- f/ BMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 D2 `/ o2 O2 S% R) i" L
| MCASP_PIN_ACLKX
4 ]- s0 B) V# z0 M9 i7 B5 j| MCASP_PIN_AHCLKX
6 R: ?, }& y$ ]4 N' || MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
% B5 b0 C- s9 j1 |- w' V P* F: W+ bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR : Q+ H! |! n# g1 d8 P
| MCASP_TX_CLKFAIL
1 j: v0 c. Z& z! Y| MCASP_TX_SYNCERROR
7 W' C6 F& V( ^+ `5 Y| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& |' V& i: a/ _% [| MCASP_RX_CLKFAIL% u! A, t/ f5 B: p) I" s
| MCASP_RX_SYNCERROR
+ a2 n& O2 s t0 M3 K/ J| MCASP_RX_OVERRUN);
/ r" q. m8 Z* d% p} static void I2SDataTxRxActivate(void): @, |5 f1 y- J
{# q3 L9 z( h- I9 z3 z1 m3 \
/* Start the clocks */
; p" T$ R5 |2 v, a& \! XMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* s) ^# j7 {, }$ R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; g9 Z: R( z, x% D4 m; [4 A( AEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
* l( m/ y) l5 B( Z, L1 h7 ZEDMA3_TRIG_MODE_EVENT);
) p/ X) ?, K- a! I: f. k* q- TEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 d, Z% O/ j7 m4 v/ ^- u1 ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
: L5 P1 l! ?- v ?/ fMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);4 D0 J8 U" Z; H9 N8 c2 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */& h ?' Y$ G3 |. I; d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */$ l4 u F% l# Q- D" c; {$ a3 }0 R/ k' O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 Z, \5 ?0 _% S7 {; b) o& @% j
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);4 _: K& T" ~: z& @ i+ [. x8 q5 a
}
: M6 |1 q% q9 Y; ^4 @. @' ?1 W) v请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 3 W; |' l2 p! g; R5 y k
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