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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! t" j! D9 e* s9 W2 @0 Cinput mcasp_ahclkx,
- L B" o: B% ?% P5 c) p, u# l+ _input mcasp_aclkx,
# g1 h! ` M5 h/ G; R& B4 kinput axr0,
- b. N4 R6 j, }0 o5 l( Z
' X9 e- h! H2 l7 [$ r1 eoutput mcasp_afsr,9 m7 o, D3 S2 {6 O7 \
output mcasp_ahclkr,
9 e/ C0 q# j& Poutput mcasp_aclkr,
; y( C! f3 g5 ~ F6 Ooutput axr1,
8 T3 R2 ?2 |9 T0 w! L& g assign mcasp_afsr = mcasp_afsx;
: X+ f5 Y V% n$ P; x9 K8 M6 jassign mcasp_aclkr = mcasp_aclkx;2 R; e& S3 u" W$ h
assign mcasp_ahclkr = mcasp_ahclkx;
Q2 R5 v! J, f; }! D* t+ t8 |assign axr1 = axr0; ; A4 n% i. n. w/ U/ N: r
) ~7 I& D, g3 P, T. x: \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
# A N& I" [' e& `static void McASPI2SConfigure(void)' S+ s; A. a8 P- s+ v
{' B& L4 w2 X* J# l3 e* t( G% E% T
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. x$ U0 h9 o( z. ?" J. {7 x" m+ FMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
$ N. R- G7 x8 G; E+ PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);# O+ S* B9 j; u+ G- k% Z' t) R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- i) W# |# D1 Y: R7 f, dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ _ f$ I6 O' S3 Z1 {9 Q
MCASP_RX_MODE_DMA);
: @0 J/ Y$ M. A+ L" uMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% r0 P9 N3 \ x- x7 g. L
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 k. d3 S K3 S# r" EMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
v) i) l: o: {MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 p- W, h8 ?; ^1 s. `7 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
U+ C" H' M$ Q2 ]9 H& rMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 p. V$ h D' p4 j, j5 K
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& o9 h( B* E& a5 C) GMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # H, n5 b5 |4 G' o. d9 u
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' k% k y# Q! ^0x00, 0xFF); /* configure the clock for transmitter */2 q; w1 u9 A8 X, R8 M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 q5 R2 r5 Y+ O$ L8 R% s0 H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) E# v0 L; B! ^/ E# a: v- H
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& ?& P% i( c! I
0x00, 0xFF);0 i1 r- W: d( p1 s, _
8 n1 m Y6 l1 ^5 w4 z- b% G
/* Enable synchronization of RX and TX sections */ , X$ b* o4 M2 |( U/ n5 u
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 ~5 g$ E) o% l* J& K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; ?0 [8 i! R" h/ H
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
2 O o8 U* a/ e" ~** Set the serializers, Currently only one serializer is set as
$ I1 W6 E- V* G! }** transmitter and one serializer as receiver.4 [; Q) D5 v: Z' D+ Z' x- f7 G
*/
1 g+ S& ]6 N. ?* v' }! \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 E! R5 `9 e9 H5 P. g( {; lMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* p* H, X# R2 n8 b
** Configure the McASP pins . |2 d8 R1 N1 O- }
** Input - Frame Sync, Clock and Serializer Rx; h, y# B$ ~+ n' M! W
** Output - Serializer Tx is connected to the input of the codec 3 t/ A# |4 G9 g; j1 b& _
*/
. c% N% B6 S* N5 K+ \McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& @% c3 L2 h7 vMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: X- H2 m- y# u5 r* u3 KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% q$ H7 F! {( Y9 j| MCASP_PIN_ACLKX3 z7 V. x" x+ I6 R
| MCASP_PIN_AHCLKX) b, B. A! W# M! n
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 _+ t% [; W; {' F
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 @: ^$ p& R) p1 T/ g( \| MCASP_TX_CLKFAIL 1 Z" p+ x- y: i7 _% `, l
| MCASP_TX_SYNCERROR2 o6 d; R) u6 ]) K- K) ]0 a0 ?
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( ^" m+ K/ a9 |; q8 Y0 Y4 X| MCASP_RX_CLKFAIL+ l( F8 u/ m4 i o1 R
| MCASP_RX_SYNCERROR
8 P+ C- G3 L- C% O| MCASP_RX_OVERRUN);
7 T7 m, G3 ]' B, x* |0 H$ l} static void I2SDataTxRxActivate(void): g( x8 s* }' u f2 e% {
{- l6 v, g. [5 m" ?
/* Start the clocks */! Z1 K$ @, o1 Z9 T
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, j2 X( b7 i0 g" J: J. d& t- {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 M: X) B6 H. s8 Z% p8 PEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 ?4 Z% G6 g: j" wEDMA3_TRIG_MODE_EVENT);" K4 i9 r* c5 l, l3 ~& J5 H( Z# H
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 F8 h/ }( O! a6 Q7 C) I+ G- H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 R( W) @ F& A$ v! l5 j: aMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 Q; s% X* m! x U) X% r5 h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */! k: ~+ V9 U3 B* R
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' I$ M. W% v- m7 n# z8 u9 o% `
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 E; F- U: f3 ~5 F# P3 qMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);' L, l6 @& Z6 d( i
}
6 z* p, W# E/ l% A0 {- H* y. B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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