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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 l: U- P4 i1 Y( E# ^) [- iinput mcasp_ahclkx,
2 u) q7 a4 M. F, d9 J! e; g$ yinput mcasp_aclkx,
+ y: a) U9 o2 W8 H! B+ Tinput axr0,' x. {% l& b. O. M
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output mcasp_afsr,
2 _0 Q' a* S& p% y) V# y/ aoutput mcasp_ahclkr,
$ W0 |4 C( d$ L5 x6 j# Woutput mcasp_aclkr,; K* x8 I- A7 O7 Q4 |4 g, L% W- u
output axr1,
$ b" j4 K3 R7 K) V* w1 [ assign mcasp_afsr = mcasp_afsx;" A* o/ X. o5 j% v5 d/ x7 V! j8 N
assign mcasp_aclkr = mcasp_aclkx;
5 Z4 D1 }4 b) j7 q$ j7 F; y# |' Cassign mcasp_ahclkr = mcasp_ahclkx;
* x/ q3 c6 I# J9 @: B& C' y4 L" w# O6 Passign axr1 = axr0; % w% V, j" \: p
+ p: e9 Z/ h" C. c& J; _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 # n; R& F4 G3 J0 @* q
static void McASPI2SConfigure(void)! B+ H$ A% B9 o# ^1 r" x
{
% Q7 U7 o. T, W. f" g0 U7 KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! s5 {! K9 C: Y% j8 N
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */$ E* B0 e& D4 D% t0 s2 i8 Q
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);3 x! P0 E% f5 H) a1 N! W
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# V6 y0 j+ d7 AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- r& r" O* _% m' S* Y/ f" oMCASP_RX_MODE_DMA);8 f. |% h" [' W! {& d2 t3 ?
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& f: ~, b& N2 S: _$ c9 S& |1 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */- _' O2 ]) g/ d) q! g7 k
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 v6 o) {* ?" ?' R0 g, kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. e6 _9 Y" T! [4 _7 P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
. |" Q) w, }- b$ j5 a. w9 YMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */9 ?8 O0 v1 U# q$ Q$ U, G# m9 C. l
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);5 Y$ G7 F8 y5 {! e, V
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
" g# K' ?% ^/ [! HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,) `1 A$ r7 Q: K% Y2 v5 ~# g
0x00, 0xFF); /* configure the clock for transmitter */
% Z9 R: M# q- ^3 f1 f- e5 G) L) kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- E7 {9 \& F" X9 _) B& uMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# |1 r, W" t0 O( J5 }McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
/ [4 U ]2 d6 ^0x00, 0xFF);# T: p d3 t8 J7 Q# A+ y% i( J( K
5 @# q9 S1 y' `( F) [! C
/* Enable synchronization of RX and TX sections */
# ]- R% e7 ?8 {3 ^McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# R, e' k( M& P' ~% [% o( `: |McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' T" m, a ]0 S8 A w2 G8 VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: V5 y X$ _3 i2 k9 l7 Y* T) X: M** Set the serializers, Currently only one serializer is set as# \& E+ Y# Q6 t: x1 e
** transmitter and one serializer as receiver.4 _/ ^6 J6 V; }2 I
*/" I' _" m, j! V. t: _! o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
* r2 B% D) P! v: w2 A, w1 Z3 N& T5 yMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ I* u9 o$ o. M** Configure the McASP pins : }1 \, @8 u0 C) p- [( F# ^( u0 H
** Input - Frame Sync, Clock and Serializer Rx
3 J- L# h1 g6 u2 y8 K8 I5 Q" q** Output - Serializer Tx is connected to the input of the codec 9 X; N/ G& U3 X# N' U
*/
0 p1 |2 `9 Y8 F1 K' k# cMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
; q& U. ~% R* n" s( gMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
5 A% e& ~+ r, o, b3 \McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' H- \, O1 `: w# W# `& T) u7 o: `| MCASP_PIN_ACLKX; I) O$ u: Y* r+ }
| MCASP_PIN_AHCLKX
5 X: |( }7 S* y# c7 ]2 Z5 Z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& q( q) \& ? S( S [+ K7 TMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 F6 u# W& o6 P| MCASP_TX_CLKFAIL 6 p, n1 [3 r+ l3 u3 w- L
| MCASP_TX_SYNCERROR
( i# ~# Y7 ^9 ?7 v$ e| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" U9 b i4 Z/ ^' ] `9 e| MCASP_RX_CLKFAIL
0 U9 G1 a% ?! _ m# m5 J0 ~| MCASP_RX_SYNCERROR 7 m% k/ F* p7 @5 d0 Z3 x
| MCASP_RX_OVERRUN);
* }2 k$ ?8 r9 ^7 L} static void I2SDataTxRxActivate(void)
3 T3 w* O1 D0 H5 o{* f: m4 p7 ]6 ]- i$ ^
/* Start the clocks */
7 m5 B0 s7 I- L5 e* O8 v# O g# h/ YMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: Q3 w( c5 r1 B8 j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */! s- [# p8 b5 z+ |! y' E J
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, t' X O: c! N/ @' Q: m$ c, Y
EDMA3_TRIG_MODE_EVENT);
6 S6 D5 D$ y1 P- s: p0 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
Y: r& U4 m v7 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
1 h- C3 I Y" h4 F5 pMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);% _9 ]9 c6 L- n0 p$ P
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- |9 b+ W, S6 C! d
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 Y0 u- o/ M8 U2 q' a0 D$ @4 }McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: z& x0 B' U# X- l* Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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