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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
# R# Y, g1 B' A' Einput mcasp_ahclkx,. F* y3 x" u4 g8 g
input mcasp_aclkx,3 D, W/ x: p- o5 I7 N
input axr0,0 v# _4 t% x7 A! M
& q$ I( w5 q2 l# s% _, I0 b; V
output mcasp_afsr,) d: f! D9 U( s& j4 t' A9 V
output mcasp_ahclkr,3 p7 y9 Y5 R2 }& ~0 C# n
output mcasp_aclkr,
y# U2 B. x5 Boutput axr1,
' @1 Y1 r! t. W; b6 Y) N assign mcasp_afsr = mcasp_afsx;
7 k( k# S# [9 S& C3 Rassign mcasp_aclkr = mcasp_aclkx;' O1 O) l0 O# V1 y) R
assign mcasp_ahclkr = mcasp_ahclkx;, B& X( S' W6 U) r# O, e4 {
assign axr1 = axr0;
: L. g5 ^+ t9 X2 o* p- `2 k# P2 C" e; M4 l: _( ~7 P; S6 J$ Q0 k
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
9 m. t6 d. r- b5 R0 sstatic void McASPI2SConfigure(void)
& ^+ {' h$ v& S; G{2 M4 r* I4 Q9 I- @; L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 m4 B. [( G" M- h; Q2 u
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ x. H7 G5 R( i0 j$ `6 T6 f
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ P: d/ {) H- J; Q+ i( U4 }McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
a7 G M0 d( SMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,. h+ y- H4 q: x6 z; P& R
MCASP_RX_MODE_DMA);
! C. r1 u% O N" N: R! SMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ g1 x7 F5 g# Z. _- G
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 ]8 t* d5 l N% ]/ u! d! n; @McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - V8 f) J9 s: C+ } I2 S
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 _9 J8 \$ b) ~' B; R" I) [
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ J1 ]' `1 ?2 _: g# z5 C+ C1 l OMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ s& r5 K' @8 _; _$ p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ i8 _. |5 h' a) \/ X7 {$ hMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 h& h. `1 u5 M4 @' a0 h, E m( NMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' V6 V! {+ ?2 p0x00, 0xFF); /* configure the clock for transmitter */
4 p, k! T5 i+ L: KMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 c/ G! \4 u& K" C0 M$ z# m, fMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 [0 M2 p6 k2 ^0 dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! b/ h( p2 V8 P4 Y2 H. o3 h* ]0x00, 0xFF);
. |- [% H5 t$ Z! N* t8 V% r3 N- b [& k* D; f0 G! p
/* Enable synchronization of RX and TX sections */
4 U5 y `- F/ y' [+ {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; _. Z" P% L, A7 ?) `- d9 J) ^) ]
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# V# @, o% s: U3 l( _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
+ e: B1 ~( H5 [** Set the serializers, Currently only one serializer is set as7 p0 I: D8 s; y. {
** transmitter and one serializer as receiver." x% ^4 p) t. z( q6 D& m7 W
*/
8 P0 Q$ F* ] C$ h1 sMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) d. H [# v$ v$ k( N& r
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( S; X* k% V2 A T6 K& R
** Configure the McASP pins - v4 n. D9 O) Y
** Input - Frame Sync, Clock and Serializer Rx
- W$ t, X0 i+ _; Y& b' l3 Y** Output - Serializer Tx is connected to the input of the codec
6 G/ B2 m0 t5 {+ Y X*/, O0 k9 g1 M% {# J( H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ V& \5 o1 k6 v( O% f5 ]McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
; {/ a: t1 B r6 NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 x- \4 X5 z. s6 s) n& q6 q& J+ K
| MCASP_PIN_ACLKX
1 V; N2 y6 V1 A| MCASP_PIN_AHCLKX
; v Z$ W3 Y3 ]2 K; V4 f5 h" q e; v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
( {* N0 Q4 i( v/ Y% CMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
# q) w4 U1 P1 d" \1 M" M| MCASP_TX_CLKFAIL
# o% F# n' Y2 u j; B8 T! N( y| MCASP_TX_SYNCERROR
0 k# ]% X& g$ M \| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
* Z: L9 u1 {2 U5 t$ n; x| MCASP_RX_CLKFAIL
* s" j$ H ^9 _! t4 ~% `( w, J| MCASP_RX_SYNCERROR
. D& d# a8 y. p9 Y x* S. I9 {| MCASP_RX_OVERRUN);6 b+ Q' r# i& A8 [7 }" j" {4 }
} static void I2SDataTxRxActivate(void)
7 B$ j4 M# g4 V# p! J6 N{3 C- o8 H# g4 H% u+ z+ V
/* Start the clocks */
- @& K0 K+ D! x. jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; x% F Q, z: A3 B: ?McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */7 l3 `. O: O7 A/ c' |
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
2 f$ Z" d, X" ~9 k% zEDMA3_TRIG_MODE_EVENT);. Y2 ^3 @. r. D! o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 ]) I2 @( X$ N* C* n5 J/ \: d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
( A' O. l# k( V& FMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: F; Q3 O7 L: z2 ~; Z" ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
9 P+ Z4 J' X7 w$ S& nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' @9 l4 l d e' L3 _
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: ]- x: q% g2 z. T, LMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 Y, C+ }( ^( q4 a! s} + ?) Y+ w' W9 h; T; v, K; n, J' H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : |# l& o( Y1 f( }6 h5 S
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