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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! B% y7 `& o3 G$ m2 `4 H& `* g- C- l7 C
input mcasp_ahclkx,
- O3 S4 E1 ]( Q: ~" p$ Qinput mcasp_aclkx,
9 s- I q" k) [6 K( i$ V1 \* Rinput axr0,, D, T. }* K+ l1 R7 Z
5 L2 t8 D- \+ Y9 j, o6 s
output mcasp_afsr,# l) v* ]7 G6 Y& o% k5 T
output mcasp_ahclkr,% R3 P/ h9 w/ X
output mcasp_aclkr,
' N7 `2 q# o1 _& Z( o3 L! Joutput axr1,8 R8 ]# w. `% X- p1 J; S/ X
assign mcasp_afsr = mcasp_afsx;- o9 y( D v( ~% E9 O5 @
assign mcasp_aclkr = mcasp_aclkx;
/ F1 A y2 o& _' L" Rassign mcasp_ahclkr = mcasp_ahclkx;
# ^, r" w. X; ^+ ~3 y, c4 a" _assign axr1 = axr0;
) X4 R, e9 q/ B7 I; a, l' G" ^* D7 T* z" e5 M3 Y( v4 a
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
: M2 q0 N6 L% e. @" c/ m, U: U, ]static void McASPI2SConfigure(void) C! J, S) {6 ~$ ]( V# i4 [
{
# y0 f+ k6 P. T7 GMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; v# Z5 {% \' i% b) c7 wMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */: O' n0 W7 x7 H- h9 p, F: P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* ~7 K7 J4 ]. W' Y/ G+ Q3 W: J
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( {# m( P8 a) Q8 r' ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ P S1 ~3 Q3 P/ M( Y" t- [8 Q" ~MCASP_RX_MODE_DMA);+ |# K7 i. G$ L. |; Z: ~* C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 o4 q# t3 j& |* M! h6 |6 J% s( E0 u
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
- Y# a, @5 b0 l2 d K3 ^% n# ^McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 4 Q m7 p& c* o4 `
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);5 i1 ]3 Q6 ~. w* M6 r
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 p: ~5 I& \# m$ p9 @" [
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 z2 }/ Z* a9 ^, b; T) m( BMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
# W/ I( ]' f/ S f" T, c% k& C/ NMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # E; W0 w0 k# T
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,# N% n* D; N3 \# E0 L
0x00, 0xFF); /* configure the clock for transmitter */' U, f+ Z4 W& n$ R! M
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; W' I( i, D4 C# L! IMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ l3 y/ }" e( MMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; ^8 c& t- J( K3 {' I+ Q' L: ?0x00, 0xFF);
* s1 }: T& @, @' S+ | y
! v) v% \* V3 p/* Enable synchronization of RX and TX sections */
4 s3 |: \9 g2 z" R- {McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
: ]9 u4 T% {# ~6 @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 C! K; e# k* [3 G1 p% m! D: BMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* O& a$ B, R1 o+ o5 E: W& M
** Set the serializers, Currently only one serializer is set as
$ E* p* `4 x- M8 R1 f# Q3 W" C** transmitter and one serializer as receiver.! K/ a R2 s! }
*/
2 d* v2 B7 Q6 r5 t6 @$ ~4 ]McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
; N- S: o( i' @ m4 iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*" ?* G7 q1 s) B
** Configure the McASP pins
: y5 p- c; ?9 u& U, h' F# m2 j2 ~- d$ @** Input - Frame Sync, Clock and Serializer Rx; q2 h( f( W$ _6 x0 k
** Output - Serializer Tx is connected to the input of the codec
! A8 T( w/ y2 n( \*/
4 Q5 I' ?+ d3 l5 w, dMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 ?3 J$ }( q! t0 f3 g8 A0 m
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 L% P' N6 I# C$ {! oMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX% Y4 c; K0 B: ~9 x
| MCASP_PIN_ACLKX( s1 Z1 y( J9 E, E( \8 H6 y7 Y& Y
| MCASP_PIN_AHCLKX0 _" q& m# F) X+ \" j3 |
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 c4 t9 C; W6 B6 q P; |9 zMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 ]* x+ @1 P' c% H3 m# M" n| MCASP_TX_CLKFAIL 8 U T# d+ V4 n9 Y, u2 I
| MCASP_TX_SYNCERROR
) p% Z" ~: I+ O) z, `| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
8 l: r# V+ \' t( |$ ]7 W| MCASP_RX_CLKFAIL
& Q: r3 I7 ~; a1 N5 P| MCASP_RX_SYNCERROR
3 R$ T1 L( U/ N( t7 V- l: ], w| MCASP_RX_OVERRUN);2 c' k% e4 i/ d3 e7 t( ~: @
} static void I2SDataTxRxActivate(void)$ Y; f! V) F6 V2 S6 h8 b
{- \5 D5 s% h# M1 k& c/ e
/* Start the clocks */
$ ?* o( L& ]$ z- W# R; V" hMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 J3 G+ l" p/ n; q8 h* GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; I9 a2 w' X# u# Z7 x2 Q6 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,; ~" w9 s4 R5 c, r
EDMA3_TRIG_MODE_EVENT);
$ G" F: P& x" K. ]3 f5 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! B1 X7 U) X0 I5 ?1 J
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; r2 f% s1 D* R' H2 E
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 ?, C6 ~ E- q# [8 V6 [! I" u2 ]
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* V$ g; {! w: v% j
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 T! r4 Y2 \5 v, P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);6 c, x" K @( h7 n2 F" X
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 `$ e6 f" g D* _* w1 c `# u} % v! Q+ i. J% g6 d
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. / g% L3 d. h: E* P; |, H
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