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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 {4 ?7 l5 B. \! Dinput mcasp_ahclkx,
6 Z9 l2 r- F1 o8 k- Qinput mcasp_aclkx,
3 `0 g. E4 y0 x5 n2 X3 Z* B/ {input axr0,4 @0 z. z. C& S" p* h; W$ n5 d
0 Y9 H; K# E) zoutput mcasp_afsr,4 H8 W- a9 Y! c3 ^1 y( \/ ~) w& X
output mcasp_ahclkr,
3 W. ~4 N+ e0 r% B* @output mcasp_aclkr,
6 Q6 F! a* l8 soutput axr1,
( l8 b9 c; Z4 |, {* H assign mcasp_afsr = mcasp_afsx;9 ~1 O/ l0 W- G: L& \4 A2 w
assign mcasp_aclkr = mcasp_aclkx;
0 A6 T- W* S5 q/ j1 ^: E$ Wassign mcasp_ahclkr = mcasp_ahclkx;+ t+ K; E, m6 k! ?
assign axr1 = axr0; : K6 v, C* E: e; a: H7 ]$ V
3 i1 d6 R5 u- D8 n! y
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- U" I" v' c' u" N& J+ F Xstatic void McASPI2SConfigure(void)
. F( F% U8 A* N{: t W5 O) W% Y2 c# ^# n
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; p/ X5 L# p: j p# tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 L, U8 s' V3 A/ j- sMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
! E" J( ]3 D' ~+ @ ^/ r- kMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; ` I5 m! ?) q+ j" |5 j: z* X1 N- A
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, I/ H( G0 q) [' ]4 o& X0 f
MCASP_RX_MODE_DMA);4 Y% {5 s6 g: r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) t* H6 A% `+ k9 gMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
F3 H4 o1 k9 Y7 C- pMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
6 ~. t! L2 L; O6 x7 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);3 P' N3 w) k+ b) R, T/ o
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
& S3 T0 [8 `( R t& xMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
9 t1 \4 {. k) K: X+ Q0 E5 x0 B# nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, V% `( h0 w6 o3 E' i% ^ V1 K! H+ h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 k# F5 h; T" G# U+ vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 I: K' r+ J0 ?0x00, 0xFF); /* configure the clock for transmitter */: A3 j3 ]7 P4 R8 t. @! l* N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' a: |2 s0 b) I# m3 x( S- c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
2 V( q, K1 x7 N( A. t( O/ J$ {McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,8 O: n) o2 p6 e7 b9 D
0x00, 0xFF);
. c4 y7 P5 Q! P* X8 g' e+ R. Z2 [( e, G6 i
/* Enable synchronization of RX and TX sections */ + ]" C a3 A7 V o0 l& O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */2 X6 E" z5 z0 D/ x- K* o& {) a6 n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. M' N% o, I) Z: DMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: s0 W0 m( W9 }+ d4 n8 @% k; J& h** Set the serializers, Currently only one serializer is set as& w4 k; m+ U: s# E' f
** transmitter and one serializer as receiver.3 f L0 V6 E6 h# e5 Q( D
*/
: R2 Y( L0 E+ Q x, BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
+ K( N# x9 j; W. }. KMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* L& N: M5 t. _
** Configure the McASP pins - c- i+ O$ c/ ^9 Y5 a
** Input - Frame Sync, Clock and Serializer Rx5 F+ }( U6 |# M! c, r
** Output - Serializer Tx is connected to the input of the codec
, Q- w8 N$ r8 b' ~9 v* d0 j8 }* m*/
, U( G \( p0 x$ Y) K4 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# ]3 S$ e6 k% d/ SMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* V7 O4 e( p8 Y0 D1 y) a jMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
{* L$ N, Y9 M8 [% m) C) a8 ]| MCASP_PIN_ACLKX5 s* w* B' y* E1 e
| MCASP_PIN_AHCLKX
/ k' k/ M3 i( Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// `, C2 X5 @+ c& o+ w! C
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 U! w9 c- A8 s4 W| MCASP_TX_CLKFAIL
5 s# o0 g6 [( r* O| MCASP_TX_SYNCERROR. M. f2 ]9 l0 h2 A
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ) ^2 j8 b# N( { e8 ]2 ?
| MCASP_RX_CLKFAIL: z6 Z3 a& A' D1 i5 E9 \( O+ }
| MCASP_RX_SYNCERROR
1 }3 |: V% i' T) p| MCASP_RX_OVERRUN);
Y2 h- ^' Q0 j6 ^} static void I2SDataTxRxActivate(void)
' ^! {& Y0 }& p$ D+ h# j" ~' _{
! i C# S2 V$ y F( B% U' i |/* Start the clocks */" j8 e- X/ a1 U" E; R3 n! _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ a' T) x% x: t5 V
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */$ h9 S6 v! l8 `8 k# _1 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
9 B' w+ p$ v4 V) @' S' oEDMA3_TRIG_MODE_EVENT);
$ N8 r3 g A* J- l7 I) uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) e4 ^1 w# s( @4 Q) `2 `
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& D* P5 c; b/ @' Y4 K, tMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" B2 p7 F9 x7 Q
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 @/ d3 }, _) Awhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 D7 h1 X" E+ L! h& h T( V
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 g! R; `- n) V3 i
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 [0 I8 \! e& f} 4 l( i; H5 z! h3 Y+ m8 J3 E9 p5 J. P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 2 U" a3 i. e- s/ v# z) Z) e
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