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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,+ H/ S1 O( ^. s2 W% f) I
input mcasp_ahclkx,
% t6 y6 |. m5 M- ?: c0 @$ _$ Ainput mcasp_aclkx,
R7 w4 T- L2 iinput axr0,
, b: B* c# D4 J, K" b9 y" h: z$ L# a( ] w [& o4 C
output mcasp_afsr,8 F- L6 w( ^7 q' @+ R
output mcasp_ahclkr,' t: r9 i2 z% Z/ x! p7 y
output mcasp_aclkr,) X A7 G2 R7 k! X
output axr1,
2 n) `$ b' o: ?& w assign mcasp_afsr = mcasp_afsx;, l! }" [/ E P2 w
assign mcasp_aclkr = mcasp_aclkx;
6 V; @- S V3 b& s3 Eassign mcasp_ahclkr = mcasp_ahclkx;
* y# m+ K& k' [: Gassign axr1 = axr0;
9 Z* d" }) c+ B
) ?" @/ j; Z/ x# T; O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 M7 Z- N' ]8 e8 X8 [
static void McASPI2SConfigure(void)8 w+ g: }! p; b& }
{
3 c! }- @& [3 Y) x/ CMcASPRxReset(SOC_MCASP_0_CTRL_REGS);! P: D1 M$ V4 i# k& E4 d; a
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */. p V6 G2 I, d0 V. f# s2 B& A" y1 P, v
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 x. [! d/ o) [' z
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
5 c" L2 `) m/ @5 bMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) a2 M+ v$ _8 J: g: e% W1 u
MCASP_RX_MODE_DMA);# H, \/ s' |' A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
) F# V, }: T' W4 `8 }1 L' I9 TMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 i7 n8 v5 Q3 m9 a- n8 @5 ?McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, . K$ B( k. E7 X" s& `. t
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ {- |: d7 h8 i, v8 u3 H4 o8 k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
$ h8 O4 ]: ]( M9 }! pMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
- V- Z' N+ m8 V: K7 n9 \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ v4 V+ o1 c4 S( _2 E: X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 Y, k. f- e/ aMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 \; [$ L* x7 ~7 v" n h0x00, 0xFF); /* configure the clock for transmitter */
' _$ v( N2 z! w( z' QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
) }3 H# h9 k0 ]" H$ d% WMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ m, K2 s; f- ?McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 X. J4 m4 O3 Y1 u1 v! U% d/ V
0x00, 0xFF);
2 S1 Q4 a% @# M: c" ~; m. |; _' w3 H" `/ ^% I- t: k
/* Enable synchronization of RX and TX sections */ 1 [# [$ @# M7 a @4 ]+ E
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots *// N7 c8 H# o% _! R& T" ?9 O% x% {
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);2 i* M8 I; L6 v3 x' n% N1 E8 l- G1 j
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 K9 c3 N" B% ^. j6 H" f2 l' B** Set the serializers, Currently only one serializer is set as1 g. F" F, p9 }7 _' x8 f2 W
** transmitter and one serializer as receiver.
- C: F2 J. B/ R, H, N' W8 |# q*/% A6 F2 p# q* w& _' q) q5 A$ ^* X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 L; E& Q9 t5 l- V7 s% o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*( V1 w9 h2 \7 e: P7 T
** Configure the McASP pins
" c6 g. E: O4 j9 e( y% r$ Q! n5 ?** Input - Frame Sync, Clock and Serializer Rx
$ r+ E# M; j) V8 B. p* k0 m7 @** Output - Serializer Tx is connected to the input of the codec
7 Q+ K8 s5 {( R6 [* s*/
, _2 F) u) J5 f; h* ^# PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 ?/ W; ?' R+ {. d' \
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. b3 B9 H# a% l( s9 T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 A. X1 r: X& N0 J9 ^# E
| MCASP_PIN_ACLKX7 u s" @; _3 ]
| MCASP_PIN_AHCLKX5 @, g1 ^9 F0 }( `" G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 T4 ]/ e) M) P8 ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 m ^+ X: S) v' g/ @
| MCASP_TX_CLKFAIL
: O D5 X: P& c) J. s4 H( K4 O0 N1 F| MCASP_TX_SYNCERROR9 z+ a7 s) G# `8 z; w2 N$ _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR f7 p& d0 k& _: i8 S3 C
| MCASP_RX_CLKFAIL" O, [) b; Z8 S4 Z7 d; Q
| MCASP_RX_SYNCERROR
6 a, L n+ p2 g1 a) g| MCASP_RX_OVERRUN); ~3 {) l" {+ h# Q5 {1 E# D
} static void I2SDataTxRxActivate(void)! A% j& w1 _; {8 R+ A
{4 k% p% H* i6 ?/ ?; Q/ }# C
/* Start the clocks */
5 t! W- ]% t* W. z+ C3 ?McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ c- ]5 ?& f2 ~9 V: {. G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */; T0 l# J/ W4 A: C( f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- q* Q7 Y5 r1 c+ g) f6 l" tEDMA3_TRIG_MODE_EVENT);
1 N7 z( u0 }1 y+ A* REDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! a5 \) v3 e% C) q' W, bEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* l& S: C4 \1 s2 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" q5 D$ @+ C/ c# | u( g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 y8 O( h. }1 ]0 M0 x
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, r9 i8 c6 k0 h& W2 j1 R1 W+ q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* x+ p) N8 |8 C$ ]McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& c. Y9 ?: Y+ }# l. H% p
}
' ?! _1 i8 M7 Q$ w! R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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