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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 M# b$ B( o3 n
input mcasp_ahclkx,7 }$ b& w7 X) `; u
input mcasp_aclkx,1 m' C$ ?' b: R9 e
input axr0," J% d- _8 e) m" J7 U+ D& L; n
, a* d! v. @" M1 i1 E! _
output mcasp_afsr,4 F/ j1 X) G; R" H k
output mcasp_ahclkr,
4 G8 O" A9 | o1 l1 d3 voutput mcasp_aclkr,7 g0 N4 z9 i) H& ^4 t6 U: O. p
output axr1,
! D: u0 B) M! _* f9 ] assign mcasp_afsr = mcasp_afsx;% Y- M# U* T* U6 ^9 P" J
assign mcasp_aclkr = mcasp_aclkx;
* x# M2 w q: N: w! K, v5 M- }# ~assign mcasp_ahclkr = mcasp_ahclkx;' L g# M' ^; J/ x0 w* k
assign axr1 = axr0; 5 S1 r1 y* \6 s* c. W+ O1 g
% i0 K) L, T1 v; N/ l; }; |在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 ~5 D$ H" h# ]. P- j/ ^static void McASPI2SConfigure(void)
" V! }# ?% p0 @+ \( [5 w{' c2 c/ y. _8 I3 Y+ p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 @9 |2 c! P5 w. o4 F2 t4 H( xMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
( D# O* E% p/ e* yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' T; X/ H* b) Q0 \McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
/ G, `0 K" k- ^/ b$ o* Y/ y: nMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ f! g7 w& B7 K( Y
MCASP_RX_MODE_DMA);
+ a' C$ ?7 n# q2 a7 i$ CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: S( [8 O8 K0 ?* t! i6 @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( V% ~: z( M% w6 B: W D7 f- M7 J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & K) [5 |" f: L- L
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# T7 J, o0 X, V" K' h- v& F
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " @: b/ E" u8 ^( U
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
: j/ @) X/ J0 F6 r( }( L+ I8 D nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 x' {3 a, `6 s
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 c' n9 |7 h/ a6 K) U
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
! D1 @5 k- V# r# N0x00, 0xFF); /* configure the clock for transmitter */& G9 K& c7 M7 J2 P" E& o7 S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);0 g; @: b! w1 l& U
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + X: t8 e9 h# b0 s# N
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* r# K1 g( [- W' P+ S( p# D0x00, 0xFF);9 z; Y& z3 L3 ~. H1 H. F. c# B
) m1 M$ d. Q w# M0 y2 w/* Enable synchronization of RX and TX sections */
; u1 u+ l% X/ h F) b5 CMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. u% t- l% i( { K2 m M6 W1 I" @McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);- i7 Q! h/ j5 ~& D* o2 H: O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 N. y* D4 t# J1 O: `4 H }
** Set the serializers, Currently only one serializer is set as
! R- w5 U% a; a& L3 S5 Y- C/ S O** transmitter and one serializer as receiver., r& b6 X1 M" Y2 w
*/
0 C; I A6 o) G! }0 vMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);5 `7 h$ x; t" ~ b
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: S/ b1 y$ q* p# C! {4 j8 `
** Configure the McASP pins
5 U$ b: D9 c+ S z1 k** Input - Frame Sync, Clock and Serializer Rx
% c9 W! Z- f& D- v; @0 a** Output - Serializer Tx is connected to the input of the codec
8 I. C( G, d6 ?9 S7 j*/, z1 S: p' H+ V) L4 m( t: A6 Y5 `' m
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- P/ O, {0 v8 g6 @/ yMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
, ^8 P9 @% `1 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX8 V$ _2 M, s5 `4 L! u/ e
| MCASP_PIN_ACLKX
. z* d5 c7 k$ M* g- K( j" N| MCASP_PIN_AHCLKX# ~* l. E# y. t) G) f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 H; E8 W# o* x S0 B! w( O% p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
$ {5 b' S: h3 {. N7 _| MCASP_TX_CLKFAIL
; V5 i9 w0 i" ?8 `# G8 d9 E8 E2 P/ j| MCASP_TX_SYNCERROR
9 F& ^6 d& Q. D( Q2 x+ f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 [8 ?2 o0 N- g| MCASP_RX_CLKFAIL+ b. H1 w& [' C. } Y7 W
| MCASP_RX_SYNCERROR
- o, W% H& f: H- e% y8 Q| MCASP_RX_OVERRUN);
9 q9 x0 Y4 a; R7 S. N} static void I2SDataTxRxActivate(void)
* z! C0 J4 u6 c2 ]: `{
0 F" j! b4 S7 D$ W. q$ M/* Start the clocks */+ H7 |8 Z1 s3 B3 E* ~" v, U
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);4 S4 ?+ G8 R8 ]3 K- Y. y: B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
. L$ j% f$ V' T% P0 ^; KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' l9 B& G' y* a6 S( n0 r4 w: e
EDMA3_TRIG_MODE_EVENT);
/ A1 [# m; T. k6 q" ~" A4 GEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * Q- c0 }' j: W3 X9 m
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, A. K/ D" z" C, `. p% Q( LMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);' \" C1 b- U1 J9 d0 _! V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// w7 g. p% L, I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
4 o- ^4 P3 }1 `1 N3 VMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
7 k# ~5 I' Z4 d7 ]9 NMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 ~. r- u! L& t; V} 0 E$ D9 ]& @. m5 r; G# H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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