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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 k- r& X8 M2 N& ^
input mcasp_ahclkx,
/ @. X; a. P( u5 `/ V, H4 yinput mcasp_aclkx,
& T' p3 [2 J! @9 {+ linput axr0,3 e& |. }/ A' F! v
2 \" R5 Z. B/ r& ^2 v1 p4 Y2 m0 S
output mcasp_afsr,; X; t' _' |1 a# H+ N, E
output mcasp_ahclkr,1 h3 z8 H" g) P' D
output mcasp_aclkr,
$ G+ w7 v i" g9 noutput axr1,
7 h3 s+ ^" h& t* z+ u0 [5 L; E/ E5 ~ assign mcasp_afsr = mcasp_afsx;
0 d" \) M0 n5 j( G( hassign mcasp_aclkr = mcasp_aclkx;: f7 c# S. V/ Z2 r6 ]
assign mcasp_ahclkr = mcasp_ahclkx;+ h, o' l g- P! ]% W! [5 n# t
assign axr1 = axr0;
l2 n& n' Y, w+ t
( z Z& C# t+ Z$ i6 Z: }在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 e% t* k+ n, X& }
static void McASPI2SConfigure(void)
~1 a: l4 W; ?) k. B{8 n$ L; x7 w: g1 I( L3 w- m& W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);9 T8 N! R. C# s7 V8 i3 _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 y# f4 @3 D) h% \. t9 a4 n7 g! P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 @8 j" C8 S! N
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% w( {2 \. @5 ~% g" u) F# Y) v. pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,+ n7 m' G2 f1 s+ m2 W. W" w" q
MCASP_RX_MODE_DMA);2 g8 X5 H9 K% V( W4 e! ^
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ y( `9 P$ {7 M4 N- Y- g! F h( QMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 W# E, s7 {* G% N& ~
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, / G: V: t6 i9 n* _8 ]
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' N+ J$ V0 [0 G2 {" D! F; X! J EMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " z+ p0 o6 I5 q, G2 `
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
" e" J4 i! v. g6 k+ e) qMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ F0 v7 ?1 h$ UMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); * q/ u7 e5 a( [2 j% {
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, p4 p; ?/ I6 F- V- H
0x00, 0xFF); /* configure the clock for transmitter */
( u& E4 y0 W0 \% Q; tMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; X# A- `* }: R7 [McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 M! N6 I. l1 n% ^6 }2 \' ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
8 s) T& g2 `) |) B0x00, 0xFF);
9 [3 e5 Y& J% D2 @3 ?) f5 H
, C, V* V! p- g1 R/* Enable synchronization of RX and TX sections */
; q5 M8 g; _8 H1 JMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 @4 s! Z+ D0 k. M5 w8 V. W9 i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! f, P; _$ v; z5 N# n
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' d' V1 E; k4 E' G1 `# [
** Set the serializers, Currently only one serializer is set as
6 ?7 C2 o" T6 }2 L E** transmitter and one serializer as receiver.
_/ A( T& b1 o2 t2 Z. w*/. X, h5 c- y( \+ Y" j; ~8 x d
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- N) A) \, e* MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
: s' P, W3 R7 m** Configure the McASP pins 7 d8 w1 x; i, y& w( o3 l# S
** Input - Frame Sync, Clock and Serializer Rx
4 o& y- }7 p4 j! c) X' [* O** Output - Serializer Tx is connected to the input of the codec
# w' l, G0 {) ^) ]*/
! ~; }4 L N C3 g2 {7 n9 eMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, a* I. w8 h9 |% b
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
/ Z$ r: W b( _- {. q& x2 WMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
1 K+ ?6 R+ W/ a9 _| MCASP_PIN_ACLKX
. R9 I: X( T9 o8 T5 K| MCASP_PIN_AHCLKX6 v. e) H+ p, \5 }. u) G9 p; L: i1 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ c8 Q& q s- o7 z9 B0 [. Q
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 1 V3 n1 z7 ]" J. {! x, ~; S
| MCASP_TX_CLKFAIL 3 t8 L+ l0 b' T' o
| MCASP_TX_SYNCERROR
- Y6 ?& \( \ U# G+ }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
& A. ]9 D, o1 _/ d" O| MCASP_RX_CLKFAIL3 ?0 G2 W9 s; g/ C7 e7 Y5 a2 \
| MCASP_RX_SYNCERROR
4 o" A" F1 }4 E/ h7 m6 { F$ s% E| MCASP_RX_OVERRUN);) t' R t5 [" J2 Z. l3 o+ x- _
} static void I2SDataTxRxActivate(void)
8 L) f' o* h3 v{
/ L9 G- p- i3 @) G/* Start the clocks */
/ W$ S2 s9 ~* ~+ `6 ^8 J1 V8 zMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);! @9 ~. y% Q2 a9 P
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* v% }2 B2 ~/ q% y3 i( Q4 o
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( G/ ~* S- x: E* {! HEDMA3_TRIG_MODE_EVENT);
3 o% n& i( F, w( M" MEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
9 r7 g8 d: O" _EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */4 [1 M) T3 h# ~$ W& Q2 q
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
, N( l8 @# s# D& E/ s! xMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% r Z( |' N: }, h4 Cwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */' @+ X4 {( \! X7 i, c* W
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);1 Z( T" c3 J6 r) v/ ^6 d; H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 Q- s( T5 B' ^( g4 u
}
( y5 J* T& j$ ~' W+ p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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