|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 R1 k* e+ T+ q# M: X+ linput mcasp_ahclkx,3 u6 L0 U. b* }% F# Z' q/ m
input mcasp_aclkx,5 L/ O3 f7 B, S6 u: B* x
input axr0,3 f$ o# v/ E. q5 ~& g& r" R
7 s* r& ^( Y0 x. `) E* b7 I% U: O. eoutput mcasp_afsr,: v) g* }4 S D0 G) B5 S
output mcasp_ahclkr,0 M/ ^2 T8 ?$ K7 D3 }5 Q( B( S
output mcasp_aclkr,
1 q: O- S+ u- b8 O+ k7 ]output axr1,# d; E# p9 K' b. k
assign mcasp_afsr = mcasp_afsx;/ N, N; i7 d, @; ~ D
assign mcasp_aclkr = mcasp_aclkx;
7 r' {( ]9 u" {. {, }: Sassign mcasp_ahclkr = mcasp_ahclkx;
! J) g) H3 N0 m+ x& y3 H: hassign axr1 = axr0; 3 F/ v$ S; b2 d
7 O% r4 I- D: e4 m
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 v( Y z/ S1 C: [/ hstatic void McASPI2SConfigure(void)) z0 i& J5 n7 E9 u" o) j
{
4 X# i, G6 f/ ^7 X9 K$ Z3 b3 LMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 I5 v. ^& x/ V2 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
! Z+ {8 s3 r, w) L3 Q. h2 f1 FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
- U$ f( v5 u3 {McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) M' U. W( w$ e: F7 `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% _; @4 G K$ H: s9 S* E% |( F. @# jMCASP_RX_MODE_DMA);
, \" _4 n5 C% Z, UMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- d- O4 L6 e- n+ C$ a! B) x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! V) a0 x1 T: p) Z9 q f+ W1 h
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
3 l, z2 w9 U/ s: I: oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 J# T9 E% D9 k' N' QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 v0 e0 ?+ P" |7 r. P0 ^/ _MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- t" P0 N$ E* V8 n/ I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);- a8 ~) L4 i e0 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) {; g+ U: M. M: m& N: \McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: J9 {- Z9 X1 T! d6 _% z# P# _3 [
0x00, 0xFF); /* configure the clock for transmitter */
, M/ \, [& T* h4 }McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ `+ n- u2 T- t9 \
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" }* e; m2 {, `McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ H9 e0 |8 Y9 J: E0 N9 l" S0x00, 0xFF);- I- H$ Z$ `# V
1 u4 v/ W4 [0 ^0 Q7 f! l$ a/* Enable synchronization of RX and TX sections */ 9 O: p+ Q+ y( J( `& T
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */1 V4 Z, D( B) c+ C9 g! G
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& i4 L1 v, h9 Y6 k9 B+ u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- N% P$ I" {* o* F- Z
** Set the serializers, Currently only one serializer is set as
7 }$ F& e9 L+ K! Y** transmitter and one serializer as receiver. c- p6 I C) S" g3 ^! n
*/
) _ x0 P, Q+ _- ? |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: A, ]+ E3 _/ ?7 G( G
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% e+ F4 s0 ?, `: b N( Y a' F5 j5 g
** Configure the McASP pins
% z6 U" Z7 p" L2 H** Input - Frame Sync, Clock and Serializer Rx
5 E2 S3 m1 O* \6 z: R$ A8 X0 r** Output - Serializer Tx is connected to the input of the codec
- ^/ r6 _) z1 ]$ C- }7 K4 ?*/
3 b9 r6 t) ]$ hMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 W& C) t, D. A( y/ q+ Y: RMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( D1 Y8 X1 Z# w- F) t1 X
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX; e3 B |3 m# ]* k. U* i$ Q6 N$ y
| MCASP_PIN_ACLKX( @8 q a G/ w/ e
| MCASP_PIN_AHCLKX
- s5 x6 ~+ {3 i4 }9 z j5 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; J x' M; p2 U6 U8 {& ?/ mMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' Q' O/ B* P7 l: J( I
| MCASP_TX_CLKFAIL
' S! g/ u* x5 e) q K/ e( @| MCASP_TX_SYNCERROR
( K. L8 y- E4 j| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
) a- ^: ]1 g O P8 j K| MCASP_RX_CLKFAIL, Q5 w' E6 s+ j8 B7 t7 [9 n( F
| MCASP_RX_SYNCERROR
, X* }$ v' n! g& V8 |) T% || MCASP_RX_OVERRUN);* g9 q+ m, f, e* P0 H0 Y* x2 ?
} static void I2SDataTxRxActivate(void)
# ?8 n, s5 C# }+ m6 H7 D& j8 H{7 \7 _! _0 o0 [) Y; R
/* Start the clocks */5 p3 D; i, s/ t7 K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 h& i, g; {; c3 |* x+ M& G
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// `# j" P2 B9 O! K
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" _7 z' c* G! D7 Q& k0 ?EDMA3_TRIG_MODE_EVENT);
8 Y' B, s5 x1 z, ^7 k& q5 q$ i% e" LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 q6 ~- s. N5 g0 L: N( \* d6 q( {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */* o0 U+ J& K; l# a. _
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; k% I7 J8 x+ m5 d+ s) a3 dMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */- l1 G; @ L8 a' c
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ d$ U# ]+ L5 [! B" yMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 D# ~0 {( I2 g P+ D6 X& d
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
1 {' L( {' }& j7 O" x* A1 h} 3 @6 w* t2 b4 g5 H) }: R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
: W, C5 k9 C) T3 u4 n( Y |