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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
5 @9 N/ Q$ C, ^( k c2 `3 ~0 binput mcasp_ahclkx,
# X+ |& g. H- z$ M" t4 T8 tinput mcasp_aclkx,
% T3 S! s2 a' [+ h5 Xinput axr0," N9 I' t1 }: r" O" D3 ], T
5 Q3 {' u% i3 V1 M- Z: poutput mcasp_afsr,
1 n! r4 ]( A) C. {2 q xoutput mcasp_ahclkr,: l6 @% t, E1 I% d* Q' e
output mcasp_aclkr,1 i$ I( [1 U7 C* W# Z* i0 s9 E6 Y
output axr1,
0 i$ E; F" L' G- E2 U1 H$ N assign mcasp_afsr = mcasp_afsx;4 u6 A3 e9 Y" _4 N' ~1 R
assign mcasp_aclkr = mcasp_aclkx;3 R4 L( `% c% w' q
assign mcasp_ahclkr = mcasp_ahclkx;
& v' B/ ~( s9 Gassign axr1 = axr0;
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 [* {) M( U# r l9 e6 i
static void McASPI2SConfigure(void)
0 a6 S- N. D: u" w1 Q8 p{$ e) e0 P* _! u1 |! d0 R! V: A5 U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% E2 I. o# m. U6 }5 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& K: {( s( R! S0 v _$ q4 \; s% H" ~5 x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
' ?" g, T7 L4 R8 V: YMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
! ^0 V1 O' K$ [1 D I! wMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 y& j! X& g* ZMCASP_RX_MODE_DMA); x$ ?; ]; Q. ]4 S9 |) H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) ?" o, p' e t6 x
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: u0 t7 X7 n1 {" K+ y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ D0 G2 Z9 ?. r
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
+ p: S+ w) C. n) G; U( S; zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 \8 k" k, m+ F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 C/ o0 t N* z7 M
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( U3 Y0 A6 c( M/ G5 x" C; ^
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 r$ |8 _2 u9 J6 t x' MMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,5 [( e1 H! R M- S9 y5 O
0x00, 0xFF); /* configure the clock for transmitter */
7 m; H6 K _3 M2 I% G0 A' g1 a# L2 mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);" K o1 k# H! G6 l' ? b8 S" ]4 c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; p) N3 D% @+ L6 ]+ [- P7 h; D8 aMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,! H& q9 q, x9 D9 D* @
0x00, 0xFF);# \$ s" K! @$ Z% |- f! Q
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/* Enable synchronization of RX and TX sections */
5 C+ b3 X2 f. ]( W( UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ N, c9 g$ ~" C4 T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 e1 W$ E! d2 @. w3 w: ?/ R- o7 v* GMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ a2 j1 O! ?3 e
** Set the serializers, Currently only one serializer is set as
! {, R# H1 ?- m+ j/ x1 ], o** transmitter and one serializer as receiver.
# m# C6 W5 v1 Q, i3 z6 W$ C! m# O W+ h$ }*/; p( ~, n% W O! w0 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) M" @' z* m; _" h. XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
?* m& i* s9 F: N" X1 a" x- k+ ]** Configure the McASP pins 0 `, [6 @2 j0 R' z0 ~
** Input - Frame Sync, Clock and Serializer Rx4 z2 F8 \8 J _
** Output - Serializer Tx is connected to the input of the codec
; X: U7 }# g% b, b: T8 \) \2 W) y) C*/
8 O9 R- s- i o- e/ HMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! T! o# ^' s/ YMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));6 V1 G/ k$ }& x+ B) a
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 {4 l: |/ m H! s/ D+ W- e
| MCASP_PIN_ACLKX
/ y( b$ u, T' i9 h+ V' D| MCASP_PIN_AHCLKX
! p2 m8 w7 R2 {9 G) l9 }8 z| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */: s& ~2 s2 C2 @3 ?1 w2 m1 ?
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
9 D& P: y8 x; a1 p| MCASP_TX_CLKFAIL
/ Y! [: W' o# l; P# y" Z| MCASP_TX_SYNCERROR
- |' K- `; u, u6 k| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
v& [% _6 c& s| MCASP_RX_CLKFAIL' B; A( ]; v- s9 h N
| MCASP_RX_SYNCERROR ' W' v* \3 p, Y. g* L
| MCASP_RX_OVERRUN); E! x( f* L" C5 I7 Z4 z5 ^
} static void I2SDataTxRxActivate(void) U9 q# y4 M9 n0 l' M% Y8 ~) E) n0 I
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/* Start the clocks */
+ W& S/ D7 d L0 ~# }$ e% @McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
3 l# ` F( W) n7 j& b# Y. @# V: pMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */* X) _5 x* _- e( A. L- m% ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! z2 U/ m& i: S0 ~: V# E- wEDMA3_TRIG_MODE_EVENT);4 R# e) C& c! b. W+ X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
]! x* @; |( v! [% d v* e' |EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" u- C& ]% X" F, x5 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
0 w$ N6 c7 R% ?' GMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 e% c: r! n, U" \' s8 ^/ ]3 P
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 G5 m% m$ ^, \1 r5 u( ^+ M& w$ n
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
& e; M8 B% Q# O" t& j% O4 `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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8 ^0 a7 X" c7 F; i0 s0 G请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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