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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,6 R3 t/ F y" I( @% v/ H; b
input mcasp_ahclkx,' L) n$ N7 s8 t6 _; U+ z9 {
input mcasp_aclkx,, }$ L- ` z/ [( F1 U7 c
input axr0,- \. I' f' }( F, J1 j
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output mcasp_afsr,9 M$ c: V! j n$ W
output mcasp_ahclkr,1 D* L# }$ P. L3 [& P
output mcasp_aclkr,, P2 r; C+ r4 i0 ~4 f0 q% @( `
output axr1,
5 {: C: t( L/ S( [& E' _ assign mcasp_afsr = mcasp_afsx;
& f% x6 m* `, W. ^' q. passign mcasp_aclkr = mcasp_aclkx;
?7 N: x/ y( j% k$ i! I& M7 Uassign mcasp_ahclkr = mcasp_ahclkx;
3 I: s1 j% _* Q* a' S9 T% Aassign axr1 = axr0;
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7 s @7 V$ G/ L在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / [. b/ o( x( ^, U0 o- P; q
static void McASPI2SConfigure(void)
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ G2 u7 Q9 g H6 x5 o N5 HMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */# \5 B* {5 Z& D: e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); h, R$ b, A! g$ S' l* t$ P( \+ l
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
, p8 L2 a; ?3 pMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE, y1 d2 g. z0 R" {# G( w* O
MCASP_RX_MODE_DMA);
7 E& Q, {5 N2 X# WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 t2 o+ m6 \- ?, v1 Q& g: w2 U
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
9 }( H$ _1 o' z- A7 r$ ^& IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, K& a- G& A( L8 ]9 o+ I% h' {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);* Z; e' {9 i6 ~6 h" _5 q! s
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( y: H: H& W; S! N# c7 F& k. n- wMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
; [- ]8 H' h& RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ H0 H( g3 I1 G5 E1 A3 K! k; f) BMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % ~- i3 s& d$ M' |5 ^
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 c' a/ e# _; \. i3 c
0x00, 0xFF); /* configure the clock for transmitter */7 I4 K2 q/ y' ~; a
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ F7 G6 p/ Q' O+ ]$ x$ I6 ^1 f& K5 v
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" e. Z% o9 q. b" [/ r* ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 y! ^. E; o" D- r8 j0x00, 0xFF);- {( g. Q8 K8 i& T* c
: i9 C; h4 B7 m/* Enable synchronization of RX and TX sections */ : r# v7 F# B# ` R2 ^3 k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */ I3 N6 i4 M+ V7 W+ }7 s) k
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& _* I1 ^ C! p8 l) Z% @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( B) e! n8 E) z# O, R2 P
** Set the serializers, Currently only one serializer is set as
2 m x% v) t+ M: C }8 s5 H** transmitter and one serializer as receiver.$ V& l' ~: h# \0 R ^. v* C: s
*/
?9 G/ b+ K) aMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 n$ Q9 X0 m+ s" q5 d$ LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*- z, M; O9 \4 l0 n, S5 K! T8 ]
** Configure the McASP pins 4 E; p1 f8 o( ^) S; C* S$ O1 j
** Input - Frame Sync, Clock and Serializer Rx
: K; W# |/ a- u4 y0 X: Y3 `** Output - Serializer Tx is connected to the input of the codec
* x, y, @1 w2 U*/, K% c) G+ k; s, J
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ T+ o+ k* R+ k( S: Y7 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));/ i1 ?. P$ {5 Z6 c- K; {' C, b
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX$ B+ z) s# K/ Z
| MCASP_PIN_ACLKX1 Y/ r; a, D- G0 L; B# C
| MCASP_PIN_AHCLKX2 h! x7 I: O3 @$ B! y7 c& @% M+ `
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 s7 L* x1 K9 u, g& qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
; \% ~% C/ D; X6 n8 X0 I7 u| MCASP_TX_CLKFAIL ! }7 s' w- Z5 P p1 b" D9 R k
| MCASP_TX_SYNCERROR
- _) D8 Y. J* ~' j, f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 q Z. J0 a) Q9 d
| MCASP_RX_CLKFAIL/ I' a! v9 }6 }: W0 v
| MCASP_RX_SYNCERROR 2 y9 J( Q, s, s2 a2 {
| MCASP_RX_OVERRUN);
, V/ R5 h" U+ P8 U" Q$ \7 E) N* Q} static void I2SDataTxRxActivate(void)) O7 b* y" |8 H" h: Z; y
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/* Start the clocks */
9 C2 Q* E/ R P* H* z. H- MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
6 u U, v! W9 Z- I' E# D" tMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
, ?5 O3 l' w1 [2 x$ ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
. l. X/ R* Z4 M. R0 rEDMA3_TRIG_MODE_EVENT);" ^5 z' V" x1 R; F0 b6 o9 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ [5 V+ _) D0 W' TEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ Z# a" D) D. A1 Z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);/ c7 I" B& I5 `& R- k9 ^
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */, s! n) F! X: Y* C
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' ]+ J$ f5 J( V3 m6 eMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
; i0 p3 q: ^1 }- N! i) lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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. N) Y% }/ ?; u0 }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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