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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,3 u( P5 U' z2 w+ m) ^
input mcasp_ahclkx,7 t9 q/ ]8 m- t% |( W2 ?/ Q
input mcasp_aclkx,7 G7 s+ A7 o: _# z+ s" B7 O. s
input axr0,
0 ^9 u$ z2 ~6 l" ~" S9 p+ [6 w0 E6 [4 M+ D3 c) b. K: o4 C
output mcasp_afsr,
( W9 v; R. m( P- o( c0 V6 N- Voutput mcasp_ahclkr, J8 X Z( o& Y5 v
output mcasp_aclkr,
7 w8 O+ B8 V c! E Houtput axr1,
: g8 [: V5 m/ T8 W- b5 x. c assign mcasp_afsr = mcasp_afsx;
. j" y0 g$ ~: U8 \2 g' `assign mcasp_aclkr = mcasp_aclkx;, Q/ W/ n+ p" y$ `. M
assign mcasp_ahclkr = mcasp_ahclkx;
6 |/ R( g3 G% t3 @% P7 T5 iassign axr1 = axr0; 0 x9 o% `3 `: V+ b# l! Q" u
3 t. x# O. w1 L0 C8 x5 E. G在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) K5 X8 U U$ d/ R7 j
static void McASPI2SConfigure(void)
/ s% a% G0 {: F3 I8 x{& k* {0 P7 A( E7 L+ R1 F( w
McASPRxReset(SOC_MCASP_0_CTRL_REGS);- ~% v( G8 t* Q8 g7 n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 _, X! Z- k& E7 U8 OMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);- ]8 @, n1 i6 L+ ]
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
; m9 ?0 f8 p- _* \" zMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ U: y0 k: G/ J- M
MCASP_RX_MODE_DMA);
' i; {$ _8 r3 @- t! B- S5 AMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# V% V$ r, z( f/ dMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" [2 @# }) W* X' U# a; o
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- }% B. P) }+ U/ B! E! nMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! p+ ~, X7 j" i6 c ~& K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( F: R- Y. d+ Q2 Z7 F& LMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 @( K N7 h9 Y: K/ b; \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ @0 G) u) Z! ]1 N' q* {$ |! W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 U1 q6 h# y4 S& VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
0 J* T7 Z* Q3 Z% I0x00, 0xFF); /* configure the clock for transmitter *// N& S/ ]' l3 y' o/ o
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 p# Z* Y/ ?1 w1 K6 v, t; qMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ A) C; i+ n- L$ R# P6 x6 }
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
$ v- k( k) o- m' E( N$ _0x00, 0xFF);. w0 \) g$ ^# B5 B3 S2 v" e
! p* W4 o0 W5 k1 h% a- @
/* Enable synchronization of RX and TX sections */
' r E+ k2 d- s" a& vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# i4 f. k0 p4 I. i0 ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- s: g) V1 s8 e" }! ^ cMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*& p8 Z% E* ]2 q- L+ x
** Set the serializers, Currently only one serializer is set as
% s: w# t- z# ~/ e+ |$ D! O3 [5 o** transmitter and one serializer as receiver.
$ y3 l+ {7 c3 E1 t*/
% V- ?0 b1 q9 ^; o' l6 p9 BMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 n9 U% x) @% R5 i+ \2 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 V! T8 s5 u. X+ w K** Configure the McASP pins
0 ?0 a! ~' |1 P: p6 [** Input - Frame Sync, Clock and Serializer Rx4 V) J$ U. m/ n# h9 \3 |$ p
** Output - Serializer Tx is connected to the input of the codec
! Z& i( M/ H! c7 X8 a$ ? S*/
% u( U: x) ] U5 J* ~2 |1 i0 ?McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 v" ?; k1 f$ ~8 T) cMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));, X' H& _$ K1 U
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX+ _& A G8 h( Y0 g, |7 v
| MCASP_PIN_ACLKX
8 n- j4 W/ N$ B2 Q8 d| MCASP_PIN_AHCLKX
1 l1 r5 q! b" o1 J: W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! g, r w. W( M5 a. o9 _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 n& g. R+ M7 |+ _: v3 b$ t. E
| MCASP_TX_CLKFAIL . N1 ^3 L3 d5 Q" F4 m
| MCASP_TX_SYNCERROR: W8 X! ?9 u/ r4 d5 v
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ' G( o) a4 q* g
| MCASP_RX_CLKFAIL: n% k* s! k; h" [
| MCASP_RX_SYNCERROR - X7 T: `, B+ u' H5 F
| MCASP_RX_OVERRUN);+ g# q) F6 {7 F
} static void I2SDataTxRxActivate(void)
& Y+ }4 ?) ?8 M) \2 ?% w1 v& g/ V{9 N& K6 o0 I3 D! f$ w3 c( I3 ]
/* Start the clocks */
; D8 V! ?" P4 j% U+ z# W( jMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);% W' `, l) m& X4 \$ m P- o
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& B; D ^' ?. y; S, U: Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. b1 b' z2 [. x2 c* ?* o
EDMA3_TRIG_MODE_EVENT);
' j% B% A/ L' N' ]! X" v& w1 w) b+ rEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 P9 [0 a \) w6 p
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! o0 X" z! a7 y: t: j* _5 ^# K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);3 f; s. D- W# @
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# T% O; q1 W3 kwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# V# h9 W% z' ]
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: W" w/ R! \$ G1 `% M1 p& |
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
- c e; U, g; `& @. h; B' l}
( O: W$ Z# I/ w! q5 z) j请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 F5 m! K7 u6 @/ M1 ?7 p
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