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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 I* p6 ?; W' _6 E5 x: z* y Hinput mcasp_ahclkx,, r) ^7 Z* G% j+ x+ M5 Y8 y, B* O
input mcasp_aclkx,
: j. f) P8 l% y# g! }input axr0,
" ~5 x$ B0 Q9 h& f6 P
" `0 v6 I- e) e/ c3 Soutput mcasp_afsr,5 b( e X0 B" K/ y. ] H
output mcasp_ahclkr,- Q* ?8 ~$ a7 M
output mcasp_aclkr,
* G, ?! W# p/ B C* Z, D Joutput axr1," u& M! t& N& {) O; R9 |
assign mcasp_afsr = mcasp_afsx;! }9 e& ]$ i7 x. ]/ X6 H1 I& ]
assign mcasp_aclkr = mcasp_aclkx;' H. D# d7 {* {- F! O: y( d; c
assign mcasp_ahclkr = mcasp_ahclkx;
\4 G. @' J* p6 C. j* y2 Nassign axr1 = axr0; ( P1 R, C; x& a+ _
2 b, q# X: h" g9 _3 M+ _6 n4 J在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) g* U; a. y; x
static void McASPI2SConfigure(void)
; k8 [5 B" a7 M7 ^; @; ~" r{
( w4 U; V% i+ c" bMcASPRxReset(SOC_MCASP_0_CTRL_REGS);: r2 b8 c# w- y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& K! l% X* W: r4 ~McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 V' w' X4 E: S3 e/ z' D
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
0 J8 q# b5 K' T) I8 oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- N% [: h) v0 T$ @$ |
MCASP_RX_MODE_DMA);! ?# j! t- n* J7 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 S% q# S& r+ }7 LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */. O+ G! n2 z4 K- t8 P* L3 Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* h6 J( @0 \8 \, ^' F% `MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);) s6 L2 G/ R0 H+ O, g9 R
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 j m( l3 t4 F- } v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 J& J+ C, ~8 c+ R" R! cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; c6 E3 E( z9 Y$ s. m% q* j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: @6 |2 {3 S. HMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, c- F0 A; b) y& B8 Y* J# h. e. T; P% d
0x00, 0xFF); /* configure the clock for transmitter */) g; A4 s6 E5 C6 P) F' z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 ^. e7 O3 o/ q" n! U& h9 F, b
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
: t6 Y7 [# R% K5 \4 d/ jMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" W6 e4 N) U0 \0x00, 0xFF);# z; h5 _" ]$ d# w, F
( Z& F) C4 M" q/ o. M3 G2 t8 P' ^+ G/* Enable synchronization of RX and TX sections */
- D$ Z- Y9 w' F$ R3 m4 O6 Q+ e8 u- zMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
# H B! h8 t5 e, v. [0 fMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
( r D% X5 b3 [6 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% S# s9 G3 O3 \7 v: z
** Set the serializers, Currently only one serializer is set as
6 E4 ~ V4 a) q3 T8 m** transmitter and one serializer as receiver.- m6 ^. w; ~. c" T% H L
*/
1 @8 Y* ?& S' g- s0 N5 h9 lMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 h' [: s! a3 i* U+ O# k& gMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*% ] P# M9 ^# t5 y% j I
** Configure the McASP pins
- M. v, ?" a/ W5 D! B** Input - Frame Sync, Clock and Serializer Rx
) M- B2 ]$ e# H- o, R7 D D+ s- V** Output - Serializer Tx is connected to the input of the codec
5 v2 z+ ~8 y2 Q- P6 M*/- F8 ~- C# f: b0 L J& G8 Z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);4 f0 s4 f/ I3 A- q5 o* o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 U4 y9 e) f/ h9 N* f+ z7 A" z
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) w9 z9 }# r5 d6 ~" ~7 p8 J| MCASP_PIN_ACLKX3 R. |0 j" Y, t4 X2 `5 n
| MCASP_PIN_AHCLKX6 U. a9 y1 {$ {- i4 k) t3 M
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
+ M! P- R$ \1 ^# Z7 M* _McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
: f9 C& [% K* f( J- q| MCASP_TX_CLKFAIL ) T; R( U4 t9 c K4 R& X/ \ c
| MCASP_TX_SYNCERROR
3 p& x' m% k* w: f: Z/ M& [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
3 }4 o; m9 X9 u7 r: L0 t| MCASP_RX_CLKFAIL
5 J0 t' ?7 z; d/ \* z4 T0 D| MCASP_RX_SYNCERROR 2 w" w! ?# M. k- k1 E- w l
| MCASP_RX_OVERRUN);
. m6 n- S) S* h, T9 z+ x6 @} static void I2SDataTxRxActivate(void)) J/ m* M# {" L! V
{) S' m$ p! B9 C3 @8 T( g3 ^% K; I- v
/* Start the clocks */
; C: P5 m' ?+ PMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 e1 ] Q O$ D( |8 B' R
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 B5 p7 n+ D+ _* M) o; R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
7 N* C& ^6 I0 {0 m" K+ Q8 Z1 A5 u. yEDMA3_TRIG_MODE_EVENT);0 `/ E- I4 V1 ]4 y D/ }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ o. J) q0 f+ m( f9 A( a% _8 gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; n4 R; g# ^' Z9 P1 M, k3 \0 M6 x
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 X5 [5 }; m% N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
; s: k2 _, a* Ewhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' |3 {5 T" C6 p& LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
6 ?4 J% l+ J! G( gMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! W/ x# i9 K9 S4 t- k}
( C) R' q Z# R5 c; D' o请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & ~, ]. _% a: c1 s8 T
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