|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
, t% [+ \+ L4 N# T* Z( l: Qinput mcasp_ahclkx,/ Z' H+ \5 A" |0 h: v
input mcasp_aclkx,7 \3 o3 J1 m" g1 L
input axr0,5 ]+ [2 C! u* ^& U1 f/ m
: Y4 D% M4 S2 O0 R, S
output mcasp_afsr,' k& g* f9 i3 z: M% {2 b) j" w- @
output mcasp_ahclkr,
% E! F1 W( A" d( B2 goutput mcasp_aclkr,
( \5 u4 X1 j% V: a# `! poutput axr1,% K# c B0 v& j" a v( S I- g
assign mcasp_afsr = mcasp_afsx;
0 E; O4 }+ V' [7 p6 v: Lassign mcasp_aclkr = mcasp_aclkx;: |. |: {3 f! r6 c
assign mcasp_ahclkr = mcasp_ahclkx;; N& v9 B3 j0 k# m% e; n2 V
assign axr1 = axr0;
! W7 J' ~1 N" [1 m: b/ R
: @9 G* s4 Z! C& H2 h* f在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 8 Y5 \$ o" J4 B( ^& D# Q# z
static void McASPI2SConfigure(void)5 g0 p2 Y: A2 m
{4 ^2 c3 Z( k( k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, M+ F4 S6 R% n5 o; l0 vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
3 w6 I, p- f1 PMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% i/ C0 m1 X- x+ mMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( s# F/ D1 B8 q3 e+ R" t
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 o9 x ^ e! U! o
MCASP_RX_MODE_DMA);; {. D% l. l2 d! G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# x! w% e* t }0 nMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& m: L$ Q) H% p! v! i' T2 ]" iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 z( ?$ Q. ~; S! P7 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
`6 K2 ], V7 ` `7 b; k/ BMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 V* F4 O% B: C( C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 `0 n. |0 ?8 g3 ]8 L: H0 e4 NMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 g5 j e _! G! u3 R9 v0 ?5 t- n
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 _. C: _5 f' k) n) P+ r3 \7 L$ FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 y5 W& u5 s1 g0 @ `! }0x00, 0xFF); /* configure the clock for transmitter */. S" H3 [% Z6 L! t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ x! v) F! V) p& H! {0 G# i
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
5 {/ b; h, ^' EMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
7 }: D3 L5 E7 R0x00, 0xFF);
; L- L% b6 M' x8 M9 x
- t3 W5 Z# ?1 g7 Y# C+ T8 g/* Enable synchronization of RX and TX sections */ ' ~* t& t& T" J: a( Q7 e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
/ W" Z& D' x" b, f0 YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ |; B7 V% b0 HMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ J( P) z* @# M3 p
** Set the serializers, Currently only one serializer is set as
' x$ [# C! |* S. H** transmitter and one serializer as receiver.
$ K- b/ L4 ~; n, W2 [& N) T/ k*/+ U4 y, B Q% X4 q; r7 X) e5 ~$ q$ j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 t0 I0 u" o' q- C" VMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ q' Q. Q7 l) x" h** Configure the McASP pins
3 ^$ a @8 Q8 x8 t1 v4 z" C/ J. @** Input - Frame Sync, Clock and Serializer Rx) T5 |$ @* x1 z: w& N
** Output - Serializer Tx is connected to the input of the codec
6 I- K) t5 d5 o* b*/
% r4 |( \$ r) `9 M- i: y. H0 PMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& c. J0 O* [4 C. v% I! W [9 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));3 T4 ~9 p% x8 f
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. k% i% W1 `8 `; j) j3 `| MCASP_PIN_ACLKX r6 O; a/ X4 k7 r# i/ l% v& i
| MCASP_PIN_AHCLKX
5 g+ e5 i3 @4 x: W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */( H- n! c I8 E% d
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' k9 O. u. w3 i| MCASP_TX_CLKFAIL
6 g/ q( A1 p0 ~/ o3 P# b| MCASP_TX_SYNCERROR
5 a+ I9 o$ e0 `( ?| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 3 J7 d7 f Q( q
| MCASP_RX_CLKFAIL
% y1 F; B& B, ?% J+ H| MCASP_RX_SYNCERROR ; T0 f& G' `" [
| MCASP_RX_OVERRUN);$ {% F% {, b" j8 _9 Q
} static void I2SDataTxRxActivate(void)9 }1 L4 s% ]& X; T& E2 M
{1 B# V, L2 |1 d' @8 U" G% k4 M: p
/* Start the clocks */: \; H5 |3 m5 ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: w7 S+ c- r; h! F/ J; B
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */& ]* D0 c+ S; _4 X- }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,5 d, s0 `0 J: e& V% D& \$ N
EDMA3_TRIG_MODE_EVENT);
+ H8 a+ d& y/ L) v" ?: h1 [1 UEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - m7 M0 W; G3 G! n k
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. q# @1 i& L( c+ T
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
' g, h0 o3 p" W5 D! I4 x; O% W$ x' _McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
+ M) S" q2 m& a9 E5 u8 g# q6 e3 Mwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 r9 N: T' j# K+ [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' v" d& `, |2 b5 V2 @4 \ o% s$ YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);& Q7 t, V0 Y( u" _
} , K' m2 @- E' }
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & Q" v: C t1 L1 ^. }
|