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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 a+ G" T* B: F- w% m7 G0 m
input mcasp_ahclkx,6 o8 l; b4 j2 L
input mcasp_aclkx,3 {$ z* u: U+ N2 h" L- n
input axr0,0 ]; x( _5 D9 n! C5 h
5 r+ J+ G" ^3 C6 c5 B, u, Z' L+ soutput mcasp_afsr,
5 A$ ^7 q7 [, L r/ Uoutput mcasp_ahclkr,
8 I9 h$ G# e' F6 e, V: u noutput mcasp_aclkr,4 v$ w' V) F+ {7 u1 n
output axr1,
" ~1 g+ \: ^# e0 e6 L+ l/ e assign mcasp_afsr = mcasp_afsx;/ f% H) r, X8 C) t p- x& U
assign mcasp_aclkr = mcasp_aclkx;3 T7 A D2 a' i/ J3 X
assign mcasp_ahclkr = mcasp_ahclkx;
* Z# k% f1 ?; i1 E9 N- h% Sassign axr1 = axr0; ; A. E3 w5 Z' U p
% m" E1 [4 f) i s- ~
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) a8 n" `3 ~3 h: A R
static void McASPI2SConfigure(void)$ p! p+ a/ U- l- i% t
{
% }; Z, [7 L1 }7 S- fMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
6 I& |. l$ p2 W5 F: S9 y, `: U+ mMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
: e, d) c) W1 {7 B+ k4 p5 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); s7 Q5 S3 n% ?& D7 ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */# u. o3 q" i2 ?+ c G; i6 s
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ J e7 d1 O6 G: A. S9 WMCASP_RX_MODE_DMA);
( J6 Q! ~) V k7 d! TMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( [- Q( F0 }- ^+ b- q) o& j2 X6 GMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 T: E5 K3 S- t# \6 s) t4 kMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; E0 c n% q2 d) h- FMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 ^- q) `+ Q( X9 S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( a8 d! w* w' g- k& dMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# X1 D. k! W2 c$ H; L/ q( IMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ H6 v2 _3 N$ h. ^9 Y
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); " t" x, e* O$ S8 d, o
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* D" b, N- ?4 B; ^( w F* L3 Y2 N
0x00, 0xFF); /* configure the clock for transmitter */
- p. O# L/ n# Y! c4 }: }" NMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
6 u. n( h6 n$ ]2 zMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ Z; K5 N0 q1 B* e0 BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
! t1 I9 Z' G' n! _ d- V( V8 T! u0x00, 0xFF);
% }* e% i; h& z: j' o+ Q
3 \0 X8 l8 u9 y3 @; _4 }0 X2 {+ i/* Enable synchronization of RX and TX sections */
3 d4 M8 q2 {" G( R+ w/ dMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& J. b# x5 q! A3 L' F; ^McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 x2 P5 Z$ A+ I, z( T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, r; ?+ y( r) m* w9 X" u$ Y** Set the serializers, Currently only one serializer is set as {+ L0 I% D# t9 C) o1 u
** transmitter and one serializer as receiver.
0 W! A: K/ y0 q# M- K4 p: |8 W5 b*/1 y' A3 |/ K( V [0 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" {3 P3 a6 S4 [3 q kMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, @) j8 E9 g1 S. W9 _% f
** Configure the McASP pins
9 n' Z* T _0 k: @7 }" Y** Input - Frame Sync, Clock and Serializer Rx
% M6 O) M" ?: {* X% A& x; p! G5 V** Output - Serializer Tx is connected to the input of the codec $ m( `1 `* N4 L0 g
*/0 k. m: j. S& t* F! b
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: z! F: W! H! y% N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 h2 |: k' q( X# O, H
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" y( y2 e5 [! @$ ^| MCASP_PIN_ACLKX5 O! j0 Q, C2 U( M. k" r
| MCASP_PIN_AHCLKX2 E+ a) C. S( U
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */ E9 r5 o( Z7 F- i; E
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* t: T3 d+ s+ m8 q0 O, g. w| MCASP_TX_CLKFAIL
1 H" w$ Z5 H7 j% v& j t| MCASP_TX_SYNCERROR
# G: `" g6 B( U* Q/ J| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 5 w$ X, a+ Q0 }. q( A7 |% N
| MCASP_RX_CLKFAIL
6 ^& V9 i: B7 ^5 M| MCASP_RX_SYNCERROR & U; D: `5 r" a; W: V( B! R8 h$ o% j
| MCASP_RX_OVERRUN);4 |6 @" z m+ }/ q- Y. I( o+ M
} static void I2SDataTxRxActivate(void)
% ?( e$ h9 `; a4 j! U, Q# @; c{
5 e4 |/ m5 V* c- L, s/* Start the clocks */
( ^* D: [0 x: g, }& ]5 QMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 w3 s& c/ V7 ~& k3 l& vMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' A7 R# l$ s* K+ Q3 g; w2 c1 ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,% S0 \/ a1 _* Y: d1 m2 S: @
EDMA3_TRIG_MODE_EVENT);
; }- d: e" `% W" I3 w( D* CEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, # q* k+ C* @9 e6 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
) M6 }4 R( o; o* o3 ZMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 C. w9 V/ r& M* b/ k/ a% G0 {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- {/ I/ i L6 a* d% _& owhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* w( z2 \# y1 c+ }: K: N! @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, R3 k+ j6 ]' r5 D( U7 fMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 L5 t# h2 }% L) G1 }1 q* Z$ `
} - D" J% Y8 n8 u8 [8 d* V D# L6 K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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