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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- A% Z# P* c' X+ i o8 ]input mcasp_ahclkx,
) c7 g7 ~( S6 b: ]input mcasp_aclkx,
1 ]' t5 X7 e/ t0 c/ j( S6 i: Kinput axr0,
3 d5 e' f% i& R4 T9 e: ] b. ~' u# g$ J; ^
output mcasp_afsr,) m7 o4 J Y" I2 @ Y4 i
output mcasp_ahclkr,! R+ l9 D: H" f, [
output mcasp_aclkr,1 A% r+ q- U; m' f. h* s. J
output axr1,4 ] E+ H2 h- T
assign mcasp_afsr = mcasp_afsx;
a$ ~1 x: Q& ^8 K" \assign mcasp_aclkr = mcasp_aclkx;/ y3 {) a. F5 k1 T5 d
assign mcasp_ahclkr = mcasp_ahclkx;
. N! `) v" h8 N3 wassign axr1 = axr0;
; K3 N+ V3 O& ~0 T9 R
1 Y& q0 L: ?0 e( o7 O- c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
2 Q4 N) g5 N+ H9 vstatic void McASPI2SConfigure(void)
: s ~7 X. Q# b/ @' G{* Z* V6 p* N; d( `
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
. K9 T9 y9 [8 ~McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 O3 n# `, ?7 u% e
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& _+ y5 v, [! R1 s- ]; f9 z2 hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% n& H% g3 X* @0 `# [4 u. W8 }+ t% BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; e; k: C/ G4 f: aMCASP_RX_MODE_DMA);' m8 E+ B( G& S
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" B8 u: T) i' P f/ XMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 P: N& b& W) N2 g0 E6 b( f/ AMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
}* R3 n, \2 B! WMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ s7 d; C h: y* \; V8 m% G1 UMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, - ]3 y0 k4 r; j$ R0 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
( k1 l {6 D7 \6 a2 N. lMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
r- ?# k" c- d- O- TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); $ u V! [: M' R4 E
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,7 V9 I% w6 ]2 i6 d/ F; X, Y8 {' T8 p
0x00, 0xFF); /* configure the clock for transmitter */
: F( ~" n, e- d5 l1 U1 S6 _McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);3 Q$ k, |4 u5 D! s! X1 O* h
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) M, r# w3 M# k6 `0 T) d* {! n* d3 vMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: F" ]( m; h! |1 v
0x00, 0xFF);1 j8 }# D& r& l7 X
6 U1 d) ~. E' H0 b4 A+ O' Z/* Enable synchronization of RX and TX sections */
6 [* w5 s- ~$ t1 n$ w+ ]McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 S& K4 x) a+ \3 K( K1 VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 `* b# v3 a2 m/ G/ [9 E) ^9 v
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 \) p) G; z4 P: T** Set the serializers, Currently only one serializer is set as j5 n5 F6 N" C' Y, p6 G: E
** transmitter and one serializer as receiver.
/ Y& e* n; i5 U! V*/
3 k: S; b0 ^! k4 d3 w$ H1 |. dMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);* @& `% K% E2 q- z, c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
g5 y) l, A0 k0 J** Configure the McASP pins . Q4 X7 c& n% s% }) t
** Input - Frame Sync, Clock and Serializer Rx
$ I! ?- h; g$ Q/ P( B+ G9 q- J* f** Output - Serializer Tx is connected to the input of the codec 8 V4 S1 |; B o4 U
*/2 T/ B, m- p0 O, R" [
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! S) u" n, F! h$ F d4 N. F' ~+ o- XMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));4 r+ W8 p# z) y9 ]: }- K
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# s, o4 p4 V7 _) Z| MCASP_PIN_ACLKX
. b9 k+ }5 \; P| MCASP_PIN_AHCLKX
& ]. f" z* h* {& ?7 o* S/ R$ K| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
8 T1 g4 d8 [! F" ^, `McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 U$ Y4 e; l0 s$ G. t" Q| MCASP_TX_CLKFAIL + y4 A3 Q3 H5 H$ B* X1 q
| MCASP_TX_SYNCERROR# Z6 F( ~* s& o" P# s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR & |% j* D/ O# z
| MCASP_RX_CLKFAIL
/ q) M `* k- R/ O| MCASP_RX_SYNCERROR
% N& T; d0 Y6 ^& y# G& p% s| MCASP_RX_OVERRUN);
$ o) t7 w9 ?3 c4 ]* o0 X# l} static void I2SDataTxRxActivate(void)
4 t. {1 U/ r! H) g5 M{( |1 H. K. b5 w
/* Start the clocks */; {+ X' b% b E
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);) x, L2 ]" A( n% n' F8 |8 w
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 Y3 U% W0 w) Y! l) t! U9 _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: L1 C f$ I E1 J" j& V
EDMA3_TRIG_MODE_EVENT);
- z& Q( E8 D7 R* G7 ^EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
K' x7 p; q, @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
7 Z! x' q- h I" W# [McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 i; `6 m7 m$ s, f
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 r$ D( Y' C6 A3 y
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 z0 q# @3 U" U9 c" W" S, r
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
9 _+ [ x2 o5 c1 H& V2 oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);0 }0 f" M$ I! c( A k; Q
} 7 p' N4 N4 u, s: A J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ; n5 c( {8 e6 @# ^* u
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