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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ ?: }: Q% G, h1 K+ e9 r
input mcasp_ahclkx,
- r. [& B0 c. ~9 w @7 z/ Y5 O2 Winput mcasp_aclkx,3 R. i$ O: E% e
input axr0,+ ^' W! s L2 C& D5 n2 c* [7 M; M
2 B! Q0 w( s9 f- v. D
output mcasp_afsr,
5 T4 |; a/ q- G3 T# Q. I- Uoutput mcasp_ahclkr,
; F8 F/ T. G$ A" goutput mcasp_aclkr,) K8 u2 o; ?( }+ x' P
output axr1,3 ?3 ^; a* B! e# c' m; J
assign mcasp_afsr = mcasp_afsx;+ x4 |( T1 K2 o& q5 m* s
assign mcasp_aclkr = mcasp_aclkx;. |) ~, f( M0 N3 u; D# b
assign mcasp_ahclkr = mcasp_ahclkx;3 ^" P3 S, a0 N2 ~
assign axr1 = axr0; . l0 c* S# ~ } Y
" B* f: B, b# c0 W( l B
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! g1 V" r U% b" c9 Xstatic void McASPI2SConfigure(void)% M7 A+ l+ Y# m6 @9 w3 e( k
{
$ c, ]* ?3 Y/ |) R9 WMcASPRxReset(SOC_MCASP_0_CTRL_REGS);6 A* z/ ^* I9 a1 O6 L
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. H% A/ |: ~: n7 d2 f; K* ~( AMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
* S& \/ o& T6 n. r+ E" ZMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */& S0 r. h$ `5 G
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
9 E0 s: i9 }! Z9 MMCASP_RX_MODE_DMA);: h( h0 d' s6 ^* p+ [4 a5 f/ l8 A
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, B7 R% h2 t) ]7 C) F; M
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: g( S: U2 t& _$ K$ ]3 C) R0 {McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
% m, B" V7 H- X9 T3 zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);& @6 V6 N8 x4 T) g0 _3 K9 C- b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 {8 i0 I9 U& S3 H; ]
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */6 P. S4 F% }1 V7 a
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. D" I" r* `1 i& l% J. C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); & R' }7 X$ w0 ?& d2 ] Z* B) k" [
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 b, T. p( f! \3 z! m# s, }0x00, 0xFF); /* configure the clock for transmitter */4 u6 y# B! W/ G t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
; Y2 ^. l. Q/ oMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
6 Z6 M; ?6 _* D- y7 R. NMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ K8 y) ~* a& p- y( g+ h! Q* f7 W
0x00, 0xFF);' Y7 c( h9 Y; l+ \1 I$ C
8 f1 B- l2 l7 u" h0 y, |! z/* Enable synchronization of RX and TX sections */
, \4 c* f% |$ YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */- a- Q5 L/ s: D
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
# N9 \; U5 _# x9 JMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** t4 x3 I9 C( M. s
** Set the serializers, Currently only one serializer is set as0 u6 r1 M9 A7 {; f1 S/ x3 ?
** transmitter and one serializer as receiver.6 e" t( F; F, D/ e
*/6 [/ F) E6 `: w V: X7 B
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 S$ g; ]; T R( G" F/ V! o# l pMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! h4 z" C$ ]( {# m4 C& q/ ~** Configure the McASP pins
" j( N" l& a4 U. z** Input - Frame Sync, Clock and Serializer Rx
& w+ e h, i$ O6 z' O** Output - Serializer Tx is connected to the input of the codec
( N% s) d! |3 V4 z" ?5 z. q*/
* g( ?3 S; j* ~/ a7 V5 R' c# uMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);0 I9 G: A8 k2 c$ d4 K3 O3 x5 f! N" q1 Q
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 P! X/ e& p; \7 Y- T |McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX7 `! D A/ V( q4 | d* \3 N# F
| MCASP_PIN_ACLKX0 Q8 z! b0 T( d" {
| MCASP_PIN_AHCLKX5 P- C8 `/ z$ w
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
! c0 B4 s2 b" h' T2 aMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 5 x4 i+ l2 c I) v5 P- d
| MCASP_TX_CLKFAIL
) g9 |3 `' m f/ b: ?: S% c& U1 u% q| MCASP_TX_SYNCERROR- x+ n0 b- @; G5 d5 Q8 X2 C
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
+ M- p Q* Z+ S$ y6 I8 v! Q5 [" R| MCASP_RX_CLKFAIL1 y+ m) ]' M' C) Q6 b
| MCASP_RX_SYNCERROR
, I/ w. x8 ]# P4 u| MCASP_RX_OVERRUN);" r k4 D6 D1 Q$ h$ x' [% q
} static void I2SDataTxRxActivate(void)! E8 f2 L$ G6 r" e, F- v1 Y/ j) C5 C$ [
{/ i- ^& T6 W, ^
/* Start the clocks */
" E; y( j5 M6 _& `) VMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 X8 N! [8 S/ s) p
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 V% {, V" ?# F1 f3 V
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,3 t& O# S& G. A+ Y
EDMA3_TRIG_MODE_EVENT);
/ J& k6 h- M2 h9 a# V( Y5 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 8 u" U6 \; T# w, D7 u
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */! L/ k+ m ]- E' ?* X- h$ o o
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
1 y4 {' i) u% G8 uMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 K9 {+ E( |. ^! k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
( X! {3 [. K! |+ U7 DMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);* p. t1 g$ s9 W- Z
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);$ D4 S; H/ D, x- ~
}
0 i% e, h: |8 k请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ! N1 W# H; ^" y' G, F
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