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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
2 V1 L9 Y% b& w- e' c7 _" Tinput mcasp_ahclkx,
* a0 ~! z# z! q$ U4 {1 Sinput mcasp_aclkx,
& x1 s5 P$ K# {& C/ uinput axr0,+ r/ x4 A) B/ h- _+ W% p2 U# W
$ D1 S" S- o" t, D4 n1 G. coutput mcasp_afsr,
) H; U+ [( @; R( U5 U$ p* F2 {output mcasp_ahclkr,! C# U6 G2 X, d
output mcasp_aclkr,
- s2 a- Q9 d% i% e/ k0 voutput axr1," Q! F6 a! p/ `% y" _
assign mcasp_afsr = mcasp_afsx;* n% W1 W/ G* D+ Q" l& Q
assign mcasp_aclkr = mcasp_aclkx;
: F; {: |/ D5 O8 Kassign mcasp_ahclkr = mcasp_ahclkx;
; a2 V3 X4 j0 z8 cassign axr1 = axr0;
& |6 |4 Z) f& l, n
, D$ M2 {) z, e3 T" j在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 m @1 H, y0 D1 N$ xstatic void McASPI2SConfigure(void)9 k4 k& D9 S. R& k! i
{) ]- b4 s! o; h( t/ r, F1 a3 x( m
McASPRxReset(SOC_MCASP_0_CTRL_REGS);/ k$ b, a+ m( P- L' E
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ j. Y: a! L+ Q0 I9 [6 \! \( CMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 s8 D( O2 @. r3 L
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */5 {# n+ i* @1 ], E
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ ^: k: a3 q' Q# i; Q$ |MCASP_RX_MODE_DMA);
) `7 Y" M* C2 I. H1 JMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: ?/ g9 X) X! C* G/ G# AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% F1 T. B, b6 I) w$ sMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - A( |% l( }( k$ H: X' a
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: B% L7 n8 b1 h2 n/ X7 p' j$ O8 zMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( X( P1 N2 C7 W; h1 E& ^MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 a6 t) {3 s/ N& ~
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
: ^1 }# c' p7 ?McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
8 c/ v" _& j- N! p1 b4 jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( [9 {; _: n7 a1 Y* [6 }0x00, 0xFF); /* configure the clock for transmitter */
6 E9 c$ {8 a7 q+ QMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# H$ J; F, ^, M3 F
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); - _: L6 T" |* {; P6 {% K+ ~: W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: h0 c) {# R7 [+ Y9 m. [4 H
0x00, 0xFF);2 t+ d( ]9 t3 z: w# a
5 \* ]% O1 _/ W2 o/* Enable synchronization of RX and TX sections */
# E& x- @: y o c# g8 m% bMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 A& P1 m5 J$ y' S; k, ]7 YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);$ C0 V& ]) d2 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 }: b' y% G( ^ i; l" r
** Set the serializers, Currently only one serializer is set as. C7 e! ] u' N" C' g
** transmitter and one serializer as receiver.
8 R2 ?5 G z1 e" h4 V*/0 G% z/ p2 T* ^4 N" J |1 j: }
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);9 i2 L% T M# N4 w* C
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*& Q% k3 d5 M- y: K1 a
** Configure the McASP pins
. d+ w% i1 @7 s* `** Input - Frame Sync, Clock and Serializer Rx
$ x ~/ i& R& s5 T& ]** Output - Serializer Tx is connected to the input of the codec 1 m) S ]$ {! a: G
*/
$ J5 u. @; J+ b+ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF); M& o& C7 A' @" j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));: Z+ M! @& h' n/ v, N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 l2 W, V$ ]- O5 a- l! t* A4 [
| MCASP_PIN_ACLKX
Z4 P% `( |; z$ o) b7 L- v| MCASP_PIN_AHCLKX
$ w1 ]* V+ H& T1 m% ~# R6 U/ }- C| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 g& Q3 s: b4 K x4 C& _, N) ]
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ( J! S8 O/ R7 x' \5 T4 b8 U. V: [
| MCASP_TX_CLKFAIL G, {/ w: z. f6 T" O9 r. w2 \
| MCASP_TX_SYNCERROR) t9 T7 F6 p: X3 Z/ G4 q
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # o. Y& O' L3 Y' k! T, G" J6 w
| MCASP_RX_CLKFAIL( ~4 Z: w H5 Y4 b
| MCASP_RX_SYNCERROR
# |3 R j' m1 f| MCASP_RX_OVERRUN);( I- x0 K6 B, I8 P+ z3 g
} static void I2SDataTxRxActivate(void)8 y( T1 @9 q4 H6 o! i- p
{
" V3 g- ^4 W3 b P# m+ K/* Start the clocks */, e) U8 b+ p* Q6 \* u9 r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) V6 Y: R9 \% ?' W" K0 @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */ E4 q" `/ l) |/ ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 ~; R, o; K7 sEDMA3_TRIG_MODE_EVENT);
7 h) ^8 U X+ x$ H& lEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ; S! y+ u# S# K* K2 I0 C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; ^5 f7 k$ L$ F8 t7 iMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. N) W5 R9 o& a: ~0 a: |, V2 C3 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: Z' A+ d9 j3 T7 u/ Y6 _4 V. L A4 `
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 V$ L, o8 ~1 O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 o4 F: W7 T. SMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 V! g( @1 d( _# a) z2 j: S
} 5 H' k0 _& y& K6 o& A) j% y7 c
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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