|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. S3 B: z0 b0 r! |0 G0 f
input mcasp_ahclkx,
- q& K6 u1 m; R6 K: d* `" p) L1 W" Oinput mcasp_aclkx,! m4 m3 f3 B) c4 M1 v3 K1 E
input axr0,( G/ n9 k2 h! N
7 \0 k9 x1 h p* l& T6 xoutput mcasp_afsr,, [- i6 n2 [+ h% o4 i2 O! w
output mcasp_ahclkr,
0 ?: _2 {2 h9 t# R0 M* poutput mcasp_aclkr,/ `" F$ w) y* A' f s/ E
output axr1,
H0 M( F. n# G6 @4 J assign mcasp_afsr = mcasp_afsx;1 z2 z8 `2 n& c& c
assign mcasp_aclkr = mcasp_aclkx;
+ @& R1 p, M! k+ kassign mcasp_ahclkr = mcasp_ahclkx;
3 Z5 q9 _# D5 p# [assign axr1 = axr0; 5 I" ~# R' V' v0 x5 c/ s
- Y: ~3 w4 W" _; o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 : V! p6 Z9 R7 h' c: `+ r. C8 L( ?* \7 i
static void McASPI2SConfigure(void)
0 w# O7 |% _) [{3 e' _. X6 J$ s1 I: N+ u
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 C/ T6 b% N; U& M' T2 IMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
0 T7 D4 N: y7 ^* bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 R8 y# G. U5 o- F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */' r9 m. ~. [1 K4 |
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
& [, P! e$ Y5 ?+ R( x$ Y& jMCASP_RX_MODE_DMA);' v; ?) ^" _7 u( }
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
- H9 ]/ Z& N% X6 d" s' ZMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, S: V4 W. G1 E" \
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 5 N2 w( X. }6 a$ [4 b' D0 L2 ^ o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% q* l4 o; J# a; m0 s+ w
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / f! l; }& T8 V8 ], P' g; Z1 M
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */7 W4 m& J4 l3 O( S
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);; M' P, W! C0 J; O
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); . l& P9 ^$ }( k1 L9 K$ f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' O1 U2 C$ \# ? o6 N& L
0x00, 0xFF); /* configure the clock for transmitter */
7 u) {" n4 r* C4 f0 K+ BMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);( Q) H5 C2 X/ W6 r" y2 M, c+ r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 8 \, C; p7 J/ ]* Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,0 [7 R/ S( g1 t# o5 ^/ v0 k
0x00, 0xFF);
0 a/ F' x7 H7 b j
2 h9 l/ @3 g8 g: x# r/* Enable synchronization of RX and TX sections */
7 r4 e0 l8 w5 x, \2 nMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
6 H, r. Y0 A. k' X( yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 X$ ^2 a3 b8 Z' i5 H/ T8 S, y8 o
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
: o8 i, W9 p5 q X2 ]; c** Set the serializers, Currently only one serializer is set as
: Z: B7 P; V C: X2 u% G' W$ h** transmitter and one serializer as receiver.
! V9 E9 h" y: B L4 W1 u; x*/
5 ^1 H* l/ x1 I4 r. hMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);1 r2 H& k$ [7 M" }, g" F* Z' z5 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ P* C* p* A ^4 q$ X
** Configure the McASP pins / W7 K* Y1 o: M& j& p/ T2 {/ C
** Input - Frame Sync, Clock and Serializer Rx
/ r O" ?( r# G! _; u$ D! U' H% c$ f% p3 H( i** Output - Serializer Tx is connected to the input of the codec
; L+ c6 B" M7 I/ Z: r- @*/
; z' ?* d* A) h4 N+ w( R) EMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 j; T9 M, Z( z9 D
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));( ~% r1 ]# c- \7 c3 O& S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX O4 d: }1 C4 ^: ]- M/ n/ z F
| MCASP_PIN_ACLKX
. n# [5 v4 o1 n5 v| MCASP_PIN_AHCLKX
, |4 S' H: Y# T+ ~9 S9 [0 _| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# v, n, u3 K$ t8 j6 `5 }
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ z$ q! J% ]/ ?, x3 K
| MCASP_TX_CLKFAIL
% K; P/ X2 Z& ?: S/ A: C| MCASP_TX_SYNCERROR# G) y3 R0 p- Y; O, K; ^$ c
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( y6 w: Z7 r1 v' g- G3 p| MCASP_RX_CLKFAIL
) w' h. \0 |4 U7 o" S* u% D| MCASP_RX_SYNCERROR
7 x; p8 d% q# C( A| MCASP_RX_OVERRUN); O& u2 q+ I2 g
} static void I2SDataTxRxActivate(void): c& y2 J0 N X) ?: \
{
) F- j+ \8 u& ?3 a( L( Y/* Start the clocks */( K" G4 q3 j5 X( z+ R
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
9 I. I( `0 i7 J0 rMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# W# Z& ]- T0 P/ |% D$ ?/ qEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& [8 f: ?# A% k* u& r& k
EDMA3_TRIG_MODE_EVENT);( c# }" N* p2 k
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
+ T Y: h5 R7 d3 v; Z* ~' f9 I8 k' ~EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */- e; ~: @# D6 r2 S; l/ h: C; X
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
- q* Q) G4 l7 v. ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 S& _0 p4 x. k
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
/ B4 H0 F/ y Y2 s# e" aMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 {$ D( W W9 e3 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& _6 T. `/ d( e9 ?! X' K _; k8 L/ ?
}
7 k$ C ^1 T5 h, h9 O0 a5 l9 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - J6 M+ s/ V; Y( {7 h- m( U* f% Y
|