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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
* d: P! J2 j# H( Finput mcasp_ahclkx,
2 X+ Y, s3 [, d8 `# einput mcasp_aclkx,
7 b4 e, j% v$ h4 T. D+ {input axr0,
5 S1 T4 |$ ]* R2 L% P. z% V o
, y" d; e' U, X' ooutput mcasp_afsr,
9 E8 C, \9 l+ F$ X# S* h% Loutput mcasp_ahclkr,- y6 y2 N" u1 R {
output mcasp_aclkr,; E# W$ V, Q* C9 l
output axr1,! y# ^" S1 v2 s2 Q2 Z v
assign mcasp_afsr = mcasp_afsx;0 G: h% X, Z6 S0 I& i
assign mcasp_aclkr = mcasp_aclkx;3 c c! w$ G [1 W9 o7 Z& h% I6 k
assign mcasp_ahclkr = mcasp_ahclkx;
% @5 A1 I; l% fassign axr1 = axr0; % N3 G) R& ^$ `, p" O' Q
7 ^5 Y9 ~( q2 |! m+ {
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 [% f4 h* i; {! K2 W# {8 Lstatic void McASPI2SConfigure(void)
/ p* q; n& k$ T) | T1 A; Z{
; g- Y9 G3 ^4 v! K$ C8 |2 ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! [9 u" {2 x0 y8 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, B5 O# Z& X$ B- u- m; p$ |
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! G/ S: p& B: M& p% h4 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
( d9 y# R% g+ {" yMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 t9 `, M( _' k: w4 z$ G+ H
MCASP_RX_MODE_DMA);) `) h4 Z8 i! o7 k8 j7 C
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( J8 e9 k) z, u/ ]4 Q, Q6 i* e' h2 @
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */0 n' b+ M3 [" j! h* i+ p
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
2 y. { _; x: qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! J1 J9 X. k1 O5 M. oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, . E! v+ j% w* m% z5 P5 t
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 u, v/ w6 z" T+ L- L/ `
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 F- W) E a0 @McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 M- Q# u8 C8 V/ ?: J3 k* ?! N
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 \/ X$ v- Q @0x00, 0xFF); /* configure the clock for transmitter */
h3 i1 \7 q3 R$ ~( W# p6 kMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ G" X5 t4 B' A5 a, V5 O
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); & M. b& s; X* W# B" ?. j2 I
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
" u- h$ G: \. s! B8 T2 D: `; q1 L0x00, 0xFF);
- c/ g1 k+ K' i, \; D7 K
" `0 U$ Z0 s0 `: r/* Enable synchronization of RX and TX sections */ ! w. k( D5 p+ f, C! i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 W# z# T% K6 iMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);: x: t3 G# k* a1 [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*- S1 Z$ ]( y7 l' }& _6 R
** Set the serializers, Currently only one serializer is set as
6 S% s; C" s: r** transmitter and one serializer as receiver.7 b! }9 U: }" D& s' i* z# G
*/
7 X" O4 l i6 d/ f+ AMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, h) F+ |+ A; HMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! u% v0 R( S2 Z# Q o
** Configure the McASP pins 7 l5 q! G& h5 U" Q% E4 \
** Input - Frame Sync, Clock and Serializer Rx! c6 @# y% ^3 c/ t: b1 V. ?& \
** Output - Serializer Tx is connected to the input of the codec
8 M( |0 x! s- s+ C) Z1 }( ]! D*/
. f/ ]+ Q/ e3 aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 u" x& [2 r) X
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX)); v' B! L' ], l0 t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 H$ E0 B O4 p6 h$ f# X; ^4 w
| MCASP_PIN_ACLKX
1 C- B5 m8 b5 c' S# I| MCASP_PIN_AHCLKX
; f: [' a( K1 K; t8 p| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. a+ E1 {' q- G: l/ q3 gMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
- Q+ A2 C1 v+ o1 b# ]| MCASP_TX_CLKFAIL ( Q+ u2 E7 U: D' X( e' ]
| MCASP_TX_SYNCERROR7 g2 U# n. U3 a" k4 i$ I8 F% a0 Q2 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( Z/ h& ?& o8 J2 g
| MCASP_RX_CLKFAIL
$ L7 |9 f: U/ j! t| MCASP_RX_SYNCERROR
. d4 U4 ]2 A1 C$ W8 E* F' N6 w% W| MCASP_RX_OVERRUN);
; n9 ~1 J7 U7 w- K} static void I2SDataTxRxActivate(void)
# s: C1 c- z( L5 E{. O& H9 c5 D; H; ?3 ^* W8 D5 A( ?
/* Start the clocks */3 ^, ^ Q' ]- _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
, U: r$ O9 j( b9 FMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */" q! U T3 [, T4 g, R% p
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: G0 B* p$ O6 A
EDMA3_TRIG_MODE_EVENT);9 P P1 x' l" h) m: v! g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* z' v6 S: U z* sEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */& p2 ~# L) g) e# O, K
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ [+ P0 R9 M# C6 M, i% [* T
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# b0 O. e, W7 }2 f, p: [/ uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
|$ N. I% @6 U' y* P7 @$ ^, ~9 t cMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);; z* B1 f3 g! g, B" |* q
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);; U7 v- ]! ~7 Z8 V8 q
}
+ ^8 O+ T" {) {9 O2 |" x& F/ Y请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
D; T: p# T6 O3 J' v5 G |