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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
3 N- V' T/ } Q. p6 K. Ginput mcasp_ahclkx,; |+ p' G0 `( }) H5 M& I( r! ^
input mcasp_aclkx,
) t+ ~4 a K/ l' i3 dinput axr0,
- o; ? D3 y( k
- H9 s1 O, E- W; Y: V4 Boutput mcasp_afsr,
; X7 |2 @) I" D7 E& E& coutput mcasp_ahclkr,' L8 z5 y( N! s) q, V+ o
output mcasp_aclkr,
& `1 W. W3 x3 g! M3 eoutput axr1,
" G* l$ {; W$ K0 `3 ~8 ^ assign mcasp_afsr = mcasp_afsx;
/ ^# x4 a1 h1 W& v% jassign mcasp_aclkr = mcasp_aclkx;
% t0 J6 l. e& }assign mcasp_ahclkr = mcasp_ahclkx;2 o' R) y4 |) A+ A7 h7 X
assign axr1 = axr0; 7 ~: \- n4 X9 E) K6 E
3 S) J+ V$ X/ @% j9 i- c在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) k, ~) H* K+ R/ L- ~static void McASPI2SConfigure(void)% }- T6 W! x: B4 {* t
{4 ~# N9 l* Z q, i
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
- E5 _7 C0 r; d2 G7 ~" V- tMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. L1 ?6 a( H7 RMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);: a% ]2 R, V, n) \4 W A; \
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 u, j% g+ q$ KMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 {$ ~& @/ Q, mMCASP_RX_MODE_DMA);
9 O3 X K% @, y4 }1 |, X% v6 f6 FMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ Y0 z. \3 X" b7 VMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */! ]& r, x. c' g- r. _) J
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 B2 d* k7 z+ f. {: kMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
9 j8 b# T: F6 ]0 _4 MMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 {7 z, S' n1 E! Y6 X% _9 {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */$ T1 S! J ?' B4 D
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) M0 l; A: _4 W0 @1 r
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: |. T1 \2 x. P% N& n! oMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
$ [+ T- z& L3 ~8 p* f+ `0x00, 0xFF); /* configure the clock for transmitter */
% |1 P* `+ c1 CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 i% \2 r5 h( l1 A1 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" f! e5 o! k. L! ?! _0 z0 W4 kMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
% c% c. u! k; A8 b0x00, 0xFF);
: d# p; v7 x. V& Z$ |" L% w) |
/* Enable synchronization of RX and TX sections */
2 b" O' o2 t+ k+ ZMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' A# z6 Q5 K. }0 QMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);' W) s- V0 f9 @8 Y# }5 \8 O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' r( y8 B4 O) Q5 V
** Set the serializers, Currently only one serializer is set as
& W- j4 W4 E0 d3 q' c** transmitter and one serializer as receiver.0 f* P$ Z( }4 S8 n* u' J% B2 W
*/, G* `' I8 @) [
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) a& n1 U5 O' K/ X A A8 d+ i6 }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*# U% Y& T6 I+ Z
** Configure the McASP pins
- Q9 f' p% P/ k3 l$ b) K- |( K7 Q** Input - Frame Sync, Clock and Serializer Rx" a8 k- m/ B+ d' Q, @4 o
** Output - Serializer Tx is connected to the input of the codec " I& S3 a4 s+ ]; l2 u4 K; F% s- V3 f
*/
. t) n+ d+ X3 }1 jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);' x k% F$ ]7 j0 f2 [! [! u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! \; |; }& Q, L5 c, t
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- H3 @# w4 ~# g: G; B# Z p
| MCASP_PIN_ACLKX! ~! L* W a- O3 t$ l* u2 X
| MCASP_PIN_AHCLKX) t* m- @4 L2 Y- b8 v/ T5 w. q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: p& {# E& I, Q DMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
4 q5 d& T0 k' \/ [+ e( r* s8 E| MCASP_TX_CLKFAIL
: M5 A: S" \3 o. I2 _6 J# c5 s2 X2 ?| MCASP_TX_SYNCERROR
! q) G& N+ P+ W2 E! P, C# l, o| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ( Q: S6 o1 ^& f7 N
| MCASP_RX_CLKFAIL3 P, e' K1 _! I# s( N
| MCASP_RX_SYNCERROR / S, K! T: t( X( p
| MCASP_RX_OVERRUN);( p$ E7 v0 O% M: z& D
} static void I2SDataTxRxActivate(void)
`, T2 P% D4 p1 Y$ {7 F8 e{
% r% v3 n$ L! z/* Start the clocks */- E3 k1 I8 O9 w: r, ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ m- [: s Y Q M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
6 X" S) |+ Y8 K kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
; B- I* V. d; [0 x) Z$ A; MEDMA3_TRIG_MODE_EVENT);
+ a9 }7 q5 `1 Q V# kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
( N# Q8 o, ?7 d& d9 N% |; ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 M0 T U/ w+ {2 \1 B! QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);: L! `& Y/ u) u$ \3 v4 b
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
& N: V( I' e. q2 h8 uwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
+ g$ L& h- E% _# Y* ~& _2 dMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
' S. ~$ \) x9 h' o7 x4 o' I4 aMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);+ }( O) E5 x4 k1 m
}
3 ^/ `9 o( O& P; Y8 x请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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