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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
& Z4 U8 L- }6 w* d6 H2 _0 b4 Yinput mcasp_ahclkx,4 o7 [- y% Y; R* a
input mcasp_aclkx,, H: y1 r" ?# U* i9 R m
input axr0,
x0 _) D2 _( X; E, j& G; {$ c1 m- T1 ~8 u
output mcasp_afsr,
2 q r H/ A D1 `& j" G$ \& l+ Foutput mcasp_ahclkr,; s: i/ A0 D% j$ u0 }+ |! _3 G/ {
output mcasp_aclkr,/ s1 Y3 D$ t! j; {$ A! o
output axr1,! C- }6 K G; F4 t( L
assign mcasp_afsr = mcasp_afsx;
8 C1 C" Q% ]6 }1 }2 n* F. k f$ n! y3 aassign mcasp_aclkr = mcasp_aclkx;7 K( l' O9 a" W' p+ }: ]; i
assign mcasp_ahclkr = mcasp_ahclkx;
# A Q1 T p$ R! I$ x8 v- {. v1 ?1 Zassign axr1 = axr0; 6 C P# O! Y, A: p* i W) u
. C( p; T! _! E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ) H1 h p, O* Q8 v$ g0 u; T0 |
static void McASPI2SConfigure(void)
1 l8 Q8 b; n7 G9 ]+ X* n. w4 b ?# m2 O8 p{
$ I6 K, m( o3 ^& [6 \McASPRxReset(SOC_MCASP_0_CTRL_REGS);) P" R. N: M" v3 j/ i( E* _
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
1 | z# `' Y: z8 _1 u5 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
/ C( w) k! M. i5 BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */$ }# l6 M5 G0 a# ?
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 m. Z# P1 F- a% z R' y% R. nMCASP_RX_MODE_DMA);
# } D! @% j, r6 P# O; kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 v0 S' L3 Q/ ^& EMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 u5 Y" U( W% M( ~( l9 H
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; g3 ~$ J* ` Y3 ~0 QMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- G; v& C9 N: c5 R5 }2 fMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 7 \- W+ x7 q! H. y2 f1 o6 b, v
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
0 r: d8 g3 }4 z& x9 v7 d: `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 p# p" A! ?9 C0 T9 p
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 0 j8 r2 b/ s+ X4 `" o; v9 q/ S4 a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' e- j. W( K c7 d0x00, 0xFF); /* configure the clock for transmitter */
6 \0 y& b, W& \8 ?. N+ fMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);/ A7 Y9 ~6 J2 }% y# l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- E, v- P) r# U4 E# ] KMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
& U. S4 `4 \. `$ x* D0 G. I, e0 T9 o& ^0x00, 0xFF);8 g3 Z, ^4 @! i1 L) F, b
# X- O$ h5 `, i7 w9 F/* Enable synchronization of RX and TX sections */ 9 {9 L) |0 }+ N" m5 E8 i; ]
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 W: P! D; W* x" n8 S* M- e8 ~# ~
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& r3 L- Q2 S+ X- s) [6 V
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
0 G+ g! h8 v R1 `9 E% J) S** Set the serializers, Currently only one serializer is set as3 i- _# w, @, L" `0 k! e2 [
** transmitter and one serializer as receiver.
1 J) v, _5 i/ S2 h- X; h*/
7 k$ x% F$ I! Y4 k( |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);: L( H8 s! {& L' _: \5 E
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** k- g' H# u& b/ D' S \+ g
** Configure the McASP pins ; R8 N: K: }! b T+ l8 B
** Input - Frame Sync, Clock and Serializer Rx
7 v' C# ?$ i* n! n+ ~. N1 F** Output - Serializer Tx is connected to the input of the codec
7 F: S# u8 C1 J% C*// }. `' l- ]& ]" B, w3 U, R0 T
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- Z0 V7 ~4 U+ V7 ~% V( P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));' A* M+ n3 `$ ]1 n2 a1 q/ N( x" r
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" J$ ^# o1 I: V0 M1 M7 }' ], w| MCASP_PIN_ACLKX
" E8 o) n% x! M( {. E, u| MCASP_PIN_AHCLKX
$ r4 Y u% |8 a. T4 c| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */8 c" B0 n9 Z1 c7 H% f: J: d+ K
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 H {/ i1 T/ u| MCASP_TX_CLKFAIL 0 I1 F+ _7 n8 r" o
| MCASP_TX_SYNCERROR% X9 R$ S0 p: e& E: T. k
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . {; ~) n6 }+ `( }& _4 {' _2 n
| MCASP_RX_CLKFAIL
1 h' x- c, E% j0 G }| MCASP_RX_SYNCERROR
0 n4 ~' p- C. r" T; i" c| MCASP_RX_OVERRUN);; m! |" Z! c* J- Q6 ^5 h
} static void I2SDataTxRxActivate(void)
4 N0 t, C4 X8 v" u{" L. v) s0 Q& }" V9 Q+ Z
/* Start the clocks */
- c' w' e h$ sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; X# b% J! K7 K9 W9 t3 T8 F, q8 |
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */1 |8 f$ B+ U) H |* t: V9 M% _
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' X) B& b, T8 R
EDMA3_TRIG_MODE_EVENT);
" ^2 U- G4 g' C8 y5 A& \, d/ n6 `EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 5 z$ Y, Q! P% z, O8 h/ P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ k( F' b& u3 D, G# k1 `McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ c& o, e6 ?0 q, V% {McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# v" Y7 B/ _% I2 }: \- J9 M) g' Zwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
2 J5 \* a8 B, ?8 R/ }4 C/ B, Q: @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
, z/ D. m" ^& y+ K1 t9 v3 JMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 q+ M' c+ j3 y} 8 r4 r0 ~1 b, A; L. y* U: y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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