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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 W/ V* H9 ? F, m
input mcasp_ahclkx,' Q6 j3 Q. `) R7 s4 ]& {& V
input mcasp_aclkx,) S& B( Z8 k9 p2 T
input axr0,
t5 I" H6 K$ T4 e {: F$ E) F# k4 x; {
output mcasp_afsr,
+ n, v& L$ T$ \, toutput mcasp_ahclkr,. x5 ^$ v$ l2 X& h) t( U& _
output mcasp_aclkr,
9 H' Q, L( K7 g0 F! T# o2 Houtput axr1,' P" s; E5 ^1 E3 _$ Q4 x# w
assign mcasp_afsr = mcasp_afsx;
3 d: f3 M" \! Aassign mcasp_aclkr = mcasp_aclkx;
! Z+ \: D) t% Z& ^assign mcasp_ahclkr = mcasp_ahclkx;
# i8 i" U* O! ?& G; @! Oassign axr1 = axr0;
. t ?* h7 K2 y) z0 p# H4 \2 w7 a' d6 @9 n" j# E& T1 c; ]
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 3 v3 S& P( s9 z" M( o/ j
static void McASPI2SConfigure(void)# |* W# O Y, C5 D1 ^2 [
{
" k% y) p- H+ s* `1 v0 v9 vMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ T1 g7 F! L* w+ e" E8 T, UMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */0 G5 r5 L/ S O' |7 u% o
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 P. o+ I5 H9 V/ h. lMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; v+ _% ~0 P7 z& ^8 ~' b
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ _5 R+ b0 K0 t+ |0 U7 @+ A4 kMCASP_RX_MODE_DMA);, D( H8 w* [* U! Q) g% k, n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 i: G7 w- w& i( ?, k; \! C zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
& s% K* F0 j {9 `McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, " e/ m$ p p5 P2 v& M% L o
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);' s( X: q1 ^. o5 Z( O
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ' L4 O& h6 H8 c. Z1 p) j
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 N7 O1 d0 M. m5 u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);' S7 v9 `1 ?2 d: I2 A, h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
# G, M! \) Q% r$ k. Q% EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
9 A- Q: [# ^1 L6 p7 {( \0x00, 0xFF); /* configure the clock for transmitter */
3 L. K, X# E) bMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);. W! I# r6 S3 f5 V9 a& z* D
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 t; _6 ?$ B' O! M" X7 i2 c1 O
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 i0 S$ y* J' E! ~$ x" j$ {; }1 V0x00, 0xFF);
8 X, t2 o/ A$ U8 P( m p4 D0 _, N% f. N1 P# G; M. T z
/* Enable synchronization of RX and TX sections */
3 e' [7 H/ \, n$ ~ yMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
0 x2 b2 t: d; E! \- p2 ~) r7 _ VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 `; V+ s' T1 W/ T
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" R% `; e" t* d, u2 ]& x# ^" r
** Set the serializers, Currently only one serializer is set as, _# _! w2 Q2 F) M5 p9 p! {
** transmitter and one serializer as receiver.- L7 ^6 K+ W% e7 Z8 G& `+ m
*/
6 Q5 @0 e' p4 j2 N1 l0 |McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
3 M& F. q1 v$ e# j& H0 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*$ v4 L$ F; [ V( U0 U3 ], G/ L7 C
** Configure the McASP pins ) R1 L+ |8 {" x
** Input - Frame Sync, Clock and Serializer Rx' K& V6 A( y, {8 \7 C0 u, v
** Output - Serializer Tx is connected to the input of the codec - ?" @& ?6 E8 U1 C+ a% \$ d
*/) j( W) u# Z7 Q6 k& w1 }
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( j& c8 ^: Q! ]
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 l- v8 q) l5 G4 {/ h; PMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" ^! s1 s# r6 ^6 ]4 [2 r: e4 N
| MCASP_PIN_ACLKX- D8 w0 Y- _5 N; H3 c! V
| MCASP_PIN_AHCLKX; S# F! D* p& o _- B7 L' y9 W
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */$ _& Y, ` p1 E" M: `! ^7 q" D
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR * C5 ]8 _+ i2 i
| MCASP_TX_CLKFAIL
5 ^- l! S% Z0 P| MCASP_TX_SYNCERROR
; S9 N% U' a2 b* ^+ v! K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 z# {8 `5 r5 C* I' r: J" w
| MCASP_RX_CLKFAIL
/ J+ W' h5 k4 N% u( i* I P( q| MCASP_RX_SYNCERROR , q& ?& v, c' _' z @8 i
| MCASP_RX_OVERRUN);. w' w( w# b9 l
} static void I2SDataTxRxActivate(void)
3 Y {: |/ N& v. @1 k1 T2 R{" N( n) P9 G5 B/ R- J. ]: B
/* Start the clocks */
) F/ s* U' _, x* k, |7 Q3 A, aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
+ q1 b, b, p0 sMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 O2 w9 p' {+ }, g- t: G1 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,' E6 v3 [; o0 ~$ ]+ [1 O) S2 o2 Y) G
EDMA3_TRIG_MODE_EVENT);
7 |; W$ B% o- t3 m$ V$ m* _EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 M$ a+ K. ?+ w; K+ O& IEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" M' k6 F. B0 p/ t$ E: l2 l
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
; L8 I& U$ l9 L( F, U: }McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 I' F: J+ r8 c4 q! z8 Lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */7 w" E& b- c, @+ V9 G1 D2 L5 ^
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ j% f& b3 [4 o" s2 Z Y% M9 H
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) {3 l: I7 c2 B1 v. m# t} 9 _# K, u* F9 S
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. , p2 S9 H: x; i& n2 a
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