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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,4 c! Y& j5 D% ~" R y& n
input mcasp_ahclkx,
& ]! R4 W8 j7 k* [3 f1 Finput mcasp_aclkx,
- Q- Q% Z. M& @ J) Einput axr0,4 ?* L6 T8 }1 K# G9 V
) b+ M; j$ `3 A" x5 P5 T
output mcasp_afsr,
& ^8 Y9 D; u- W3 Qoutput mcasp_ahclkr,
! i; v! T6 L- Woutput mcasp_aclkr,
# q& |' y+ T) _, coutput axr1,
( @' {* x% H1 Y* o' A/ n1 k8 c assign mcasp_afsr = mcasp_afsx;
% x! B6 n. |3 ^' K3 E- \6 |3 g% Passign mcasp_aclkr = mcasp_aclkx;
4 p# [% S) \7 ]% q0 Bassign mcasp_ahclkr = mcasp_ahclkx;+ h# @( w) y$ }2 R; z
assign axr1 = axr0;
5 w4 S+ ~$ C! s3 V0 x8 [1 r0 u3 c
! X# B; ^- K6 P. N! t在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
) f$ a) {9 V: B. G. estatic void McASPI2SConfigure(void)
# U' d/ \: \% ?0 y/ [* Y& O% r{- ^( M6 _4 L3 Z: d- W( U/ M
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 e8 A- g4 U9 T, e1 {) SMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
* z' t' ?( _$ U. B4 {McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);* S! G( S4 Y4 s
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 D( z* Z7 q4 q' b6 ]+ L3 GMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* A: J- F$ F& ]' q- y
MCASP_RX_MODE_DMA);
9 P% F7 }, u0 n" j" u2 @McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: x; u: `: S4 s* K3 p! vMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */7 i' d, W" P! o& O* J: {3 p# L1 r
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* M7 R( i- r$ o% z! KMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);7 H% X, N' ]7 e6 Z: R5 Y
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, {9 i, ]2 A# P
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& g/ O, i# ` X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);! Q5 @ W- I) _) j1 `' _; A# Z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 j3 B. L4 D, ?8 c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( K" F( k! {! z6 A* Y& H( ?& m3 x0x00, 0xFF); /* configure the clock for transmitter */8 M ~& i3 i/ g2 \
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
* Q' Q* l# q. J, n3 V9 d2 KMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
# S" S' j, H8 L# G+ N9 J: r; cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 J7 q; b# b3 |2 w. Z9 ]
0x00, 0xFF);
2 r+ o A2 @$ @& u4 g( s4 u, [" y5 I" ^) |6 b
/* Enable synchronization of RX and TX sections */ - a/ L) ]: S# I6 N- E+ S- W
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ T, o( M; O6 o0 i+ vMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ R) {" N0 ~; }) d# p4 @McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
- d6 v- L+ t1 {# u** Set the serializers, Currently only one serializer is set as* ?2 G3 U2 M& e" E0 |
** transmitter and one serializer as receiver.4 R) r7 f0 g! R
*/
- ~2 s; W& r0 z; x. T6 I# LMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% `8 X' d% s6 q$ ^McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 t7 B! M9 K, q& C/ k) m6 c
** Configure the McASP pins
6 A3 f+ [2 O4 T8 z$ C0 v& t** Input - Frame Sync, Clock and Serializer Rx# L Y! H+ C5 l3 @
** Output - Serializer Tx is connected to the input of the codec
U2 ~; Q) P+ J% t$ ^3 _2 v# A% x*/) t; c: H% m" ?* E2 v+ o; L
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# c u; i* d5 y$ e1 V& I4 g3 lMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
' }4 C6 ], H; P( rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 K" O- c% Z8 Q
| MCASP_PIN_ACLKX8 r. Y# @% D& Y. F
| MCASP_PIN_AHCLKX
, @, q; e# j8 N/ I, ]. n0 G| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */% g, T* d0 a* s3 |( O/ h3 n
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
* c8 J0 c6 h; H( G; k& K| MCASP_TX_CLKFAIL
6 `$ t* x. c6 z/ C| MCASP_TX_SYNCERROR
& c5 J& z3 x0 Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" H4 H1 i' l0 g0 \% e+ A1 \. {| MCASP_RX_CLKFAIL# E6 _, O! Y+ U$ Y" ~( X
| MCASP_RX_SYNCERROR
# _$ H9 h1 f% o6 Q| MCASP_RX_OVERRUN);* t% _6 X- u) {( O$ M
} static void I2SDataTxRxActivate(void)
' U5 @- Y6 ~8 G( W{
) t7 I$ a) f* j/* Start the clocks */+ x$ _6 x0 K' y0 i
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- a. k8 ^. V" `7 [* f, c5 t* PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
0 r. a* `. e5 G7 W7 ]8 P, z2 bEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' w+ Z0 D0 v3 s/ zEDMA3_TRIG_MODE_EVENT);
; t8 L7 i( e1 b5 t, XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 0 ^, p8 s w/ x6 J+ z9 u) Z
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */, c: C- x" p5 a8 P2 H* `1 t# t* z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 k4 \9 b4 b" Z$ ^) H, IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% D4 v" Y) I6 e5 o7 Z, r$ xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
$ s% K4 P% j5 QMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
/ v4 n' \2 f( L* z( a! VMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 p( K* h' ~7 c+ h. h: G
} + E- s# h; P5 O6 n F
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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