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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,7 Y L. }( u& X2 _& s$ b" n
input mcasp_ahclkx,3 \. p9 r4 F* n9 P# E5 o2 c
input mcasp_aclkx,
( C- S% T" O# l0 I: c7 l4 ^input axr0,
1 s2 F: V! v7 `5 }! \- C# t
; Q" ^& O* e4 Voutput mcasp_afsr,
* t# _+ X& }( z* ~0 i) x& Uoutput mcasp_ahclkr,
; k1 \3 [1 E5 b1 x, @output mcasp_aclkr,$ u- ?7 p* ~+ ~8 y
output axr1,& h3 a9 A) G# r& Q8 s, r1 m+ w
assign mcasp_afsr = mcasp_afsx;# U% q# {. [- w4 X( o G$ F
assign mcasp_aclkr = mcasp_aclkx;
# }1 y. D- l" N" @assign mcasp_ahclkr = mcasp_ahclkx;, ~4 Z( W2 \1 Q4 W
assign axr1 = axr0;
# z4 d7 ]( O- {6 T& S. E. @% k9 L; F9 z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
! w2 \" u1 p, ^2 f: lstatic void McASPI2SConfigure(void)
$ f; l' J! F+ ], E. H* o0 _{ H! ?2 t4 N8 k
McASPRxReset(SOC_MCASP_0_CTRL_REGS);3 l; D" c u* x6 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
. V$ D- u3 E1 D$ y rMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ v# a. e3 C* ]* x$ QMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
7 K) O6 `% j' ?; {' j# NMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* V2 b/ _1 B: g. Y8 e [MCASP_RX_MODE_DMA);
+ e, a1 `8 k. ?5 d# ~* M1 P" j( D yMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. N v; M" L) |5 I& Q z) }( lMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 V9 N( A; c* h a0 zMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ S* ]0 i) m4 y6 P# HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ K* C9 V5 r0 E6 ?' t& K
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 @6 n0 R' r v. P- {( d2 h. }0 D
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
7 i2 K+ d' E. i9 k) l. A2 oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
/ z( p. X8 h- |$ G2 x4 R! iMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 4 z0 Z( P8 a8 i; @/ m6 R9 W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 F$ { j' X- O- V
0x00, 0xFF); /* configure the clock for transmitter */
0 U% W% C, K* N) }. {& F4 n. vMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);: r+ v. h6 V0 N0 {5 o4 I- H
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
* d% d) p* q M$ F4 h6 j uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,) Y* N3 t, g$ D. T& z/ O" y. k
0x00, 0xFF);
4 \% ^7 B* r, Q
/ {: J5 c ]" c, u" O' J P/* Enable synchronization of RX and TX sections */ ) H& u$ z9 l& X! o# F
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */' _, F$ \' N, b e7 ^$ ?
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* X' T+ a6 o, ^1 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /** r/ g* c; _/ \
** Set the serializers, Currently only one serializer is set as/ |- o/ d, X; Z. k
** transmitter and one serializer as receiver./ u. @6 ?. G M4 u; n+ M" e C
*/
8 O1 k' ~8 E! s9 y k0 \McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, N% u1 `( V5 o. P
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 X8 ]; f4 Q" b$ H** Configure the McASP pins 9 [$ [' w- j" J, O
** Input - Frame Sync, Clock and Serializer Rx
* u* w7 m. c6 e5 k** Output - Serializer Tx is connected to the input of the codec
. a: c3 ]6 H% i0 o3 Y! Z+ n*/
* t9 u3 o9 u: v7 k+ G0 [& ZMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% x4 a+ l/ T& {- p8 q4 ^) W
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
8 ]& x) z+ `$ y Z: NMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ N% k; _: J- E6 d, U& [1 Z| MCASP_PIN_ACLKX
N! t0 x7 U2 S3 Z7 {: x$ J% o| MCASP_PIN_AHCLKX; O: r9 n( U* S6 u( _% D" u9 I
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
, V+ ^7 J4 ~$ ~& jMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 K5 n! {0 I5 d| MCASP_TX_CLKFAIL
" N$ P7 D& }/ ]% y| MCASP_TX_SYNCERROR2 }0 Q! \8 e& r5 f( J0 x+ x
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 u$ i! R1 d: Z% N, M3 b' o3 e
| MCASP_RX_CLKFAIL
- P) K( E( q* ^! Q* ^0 b| MCASP_RX_SYNCERROR
* ]% q. b% g/ D# j! |$ r7 B2 Y| MCASP_RX_OVERRUN);' p8 k' [9 l. c7 U( N0 t! N
} static void I2SDataTxRxActivate(void)
& K- a3 d: \" L6 P4 v{
5 k" }7 R) Q6 f' X7 j6 q+ W; J% B7 ]/* Start the clocks */
. t2 u {# Q. A" lMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; X7 R* u3 O4 t4 b$ a ]
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; o1 {4 ]& g+ h0 iEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, ?* G; t: C$ q7 s
EDMA3_TRIG_MODE_EVENT);
& @" c' m: y5 e \2 s; n4 ?' E9 IEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 h5 ^1 j7 U) }& a: N% P
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ {# r4 g5 D0 B& W6 W: M
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: n+ f& q2 W" F: H a% ^1 hMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */8 R, z, k* v9 b {( J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 _' v6 O- [5 }& k7 j0 @1 [* qMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);/ g' |& N) K( m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
, b! y- F5 {/ Z1 `9 V( N( R, R} 4 _, [% O. M% ~
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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