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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
s* r. j0 p% H$ ?8 Kinput mcasp_ahclkx,
" `# h- p5 e. `2 u; Yinput mcasp_aclkx,/ I% z! q/ G8 T# x9 V
input axr0,+ n b; N' h6 Q4 r* n% s
6 z2 i, v" t3 Y* f- ?output mcasp_afsr,
' s; w# [; _8 `" @' K Routput mcasp_ahclkr,! x+ w, _0 |: T
output mcasp_aclkr,2 L# a: K- e3 K/ L, e
output axr1,
4 |+ h3 C# w/ @- \# d9 F5 ]( p assign mcasp_afsr = mcasp_afsx;$ \3 U$ D8 G' f
assign mcasp_aclkr = mcasp_aclkx;% S0 |+ b! @# B
assign mcasp_ahclkr = mcasp_ahclkx;& k. N; t4 k4 N. e- q" W
assign axr1 = axr0;
* }4 \8 a- F" ^6 w/ v
* G @" ^$ h0 ]' i9 r) s) _在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
6 x7 Z; t* W5 `( ^( ?- ?* z7 r& ostatic void McASPI2SConfigure(void)8 h' q+ ~' S( i
{
E1 F3 d& H/ r+ PMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
2 r8 ?5 D- W) }4 AMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; b8 r/ \& R- [9 ^/ F5 yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
2 j2 R, w* f$ f2 ?; c7 x, tMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
. n( F2 P7 ^% v9 k0 H( Q& oMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) L1 [2 B Y3 L, Z( p0 j
MCASP_RX_MODE_DMA);: P+ L) k& E& G
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
% U& u# N0 q8 K E1 C) _- E' zMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ |# R9 I: x% t* i7 j" h7 ]! aMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
* |) H2 t! Y2 x& w. X3 qMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 s/ f- U/ S. {& o5 J5 z7 AMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
' \" P+ c+ C! n' k( ~6 FMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */( }( u1 }6 T# Z' [6 L+ i2 Y3 J
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% [% C! u1 [" g! \. B1 r r8 d
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % ?- x, [1 Z# i1 ]7 _- j' m
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 T' F& D8 ?, \# X/ l0x00, 0xFF); /* configure the clock for transmitter */
, ^3 R8 H: u* z0 V6 CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 ^+ J9 ]8 j$ d: A$ ?8 n0 ^2 _6 C
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! d' S2 {, x- A, P2 nMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,6 l9 B4 R, q9 N/ g1 S: P1 v! D
0x00, 0xFF);3 x0 T V; d# j& J9 x
7 \7 v; Y, p' d7 e q/* Enable synchronization of RX and TX sections */ 9 s. S& v( E+ {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */" V7 k2 K! o8 b/ m
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);, E8 A5 X! T$ M3 @9 H( h" G
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
4 |( P# A4 Z* b1 v, n+ W** Set the serializers, Currently only one serializer is set as7 A$ W& D. Y2 P- I- c6 C
** transmitter and one serializer as receiver.
7 e6 m3 Z2 m: ^/ n*/
0 W# l, |9 v; r: Y, {7 z6 \( ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 @& \8 r! c- F) X4 r0 `0 K' B" @. F
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*. w& W; c) ?: I. A
** Configure the McASP pins
! m$ r$ E: ^! g9 ~** Input - Frame Sync, Clock and Serializer Rx& ^4 a+ e; I; ?6 l
** Output - Serializer Tx is connected to the input of the codec # g+ d0 G1 J# ^, m5 @
*/
1 H' z% H3 G, y# H2 J3 v+ xMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 j3 H3 s. j+ JMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));$ L* X2 |, u& R# P: E6 e& \5 G$ l
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
" G2 e, a! Y/ a' A, `# O1 a| MCASP_PIN_ACLKX8 A: W1 x- y; _0 a0 Z" ^ W
| MCASP_PIN_AHCLKX
0 A6 |. z8 j3 x. X6 O5 Q; \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 X) l' ?; L7 i- H' g9 nMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 @. i8 b# R( |, y8 [: g) ~| MCASP_TX_CLKFAIL . Z. i, M" b1 ] q+ r1 i
| MCASP_TX_SYNCERROR
- r. Q5 U3 v- N6 x! G1 m+ ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, f r* N* @. A# o3 l! \4 D: M| MCASP_RX_CLKFAIL
; [% k+ b. R2 K: g+ U- X6 D| MCASP_RX_SYNCERROR 5 |9 n+ L# z+ P$ r9 M _
| MCASP_RX_OVERRUN);
' q2 L; M$ V& N$ h6 f} static void I2SDataTxRxActivate(void)
+ I9 e. B# f3 b u% f [: Q5 C{& D/ V* d& N4 K) g3 s# i t
/* Start the clocks */: F5 M3 N! {* n2 ]8 e5 a
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);* Y1 V+ x- C+ K8 C
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */3 u! ]6 {- r9 i& ?. ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 K' w4 d9 W% YEDMA3_TRIG_MODE_EVENT);
, j! N4 P7 w* W; d8 h! WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
0 K) `; ~6 {% W7 a* f: HEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" n [0 p, X% k3 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ ]$ }% b, \" ?
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
) c) {0 `5 i6 w8 F& O: ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 ^" s }/ F. N9 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
0 e2 A F# P' v3 ~/ c2 C: r3 k! K6 j% lMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
P! M0 S# V+ ^$ c0 H}
. l0 L! t! Y3 Z2 I1 {0 R请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 9 c9 e7 `' l; {4 s1 K/ P5 U
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