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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- q& r+ u X' ~input mcasp_ahclkx,
# I, M1 u" d8 `0 t& ainput mcasp_aclkx,
& ]( d* f/ l2 @6 Q' `input axr0,; N6 U/ h4 V, U; s
& W# A, x8 U4 O( c Eoutput mcasp_afsr,
e$ r1 y2 H! e7 O; C: ioutput mcasp_ahclkr,
* L6 v3 S: _3 { M) i4 K9 `output mcasp_aclkr,9 e9 i1 P' }3 e8 t v
output axr1,# W0 n+ m' Q( H7 o) l9 H& L
assign mcasp_afsr = mcasp_afsx;
# {6 q, t: {7 T) A( f$ D( y! iassign mcasp_aclkr = mcasp_aclkx;4 `6 y! F: f7 E8 w. \
assign mcasp_ahclkr = mcasp_ahclkx;3 X, `( V/ d; y9 V' L" E
assign axr1 = axr0;
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8 Z' y4 ~7 @; B8 p在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
3 x" L$ q0 S( u" e# h" c) Kstatic void McASPI2SConfigure(void)% U8 T# O( L- Y2 e4 e
{; Y, `) s. H7 W: b1 p) h2 H
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# T. H( A/ L3 H/ @ p5 @+ hMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */5 e! v) Q; s+ y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);4 ]) e" K. D# @' M7 K8 S
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
- u2 f: o7 f7 c( fMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# u+ f0 C& X. ~8 b0 f
MCASP_RX_MODE_DMA);- a- r8 ?) N4 O# V7 x4 d) G4 y" J4 B
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,/ k* q1 b$ o! r8 x4 q3 G' j
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */( |- C, s! N! o; n4 D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ y0 s! T: ?6 j4 V) z* I" j! zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 q- f% z3 u+ u* a/ b- k" OMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 h. D) l5 t' Y; r$ r5 nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
& S1 a0 J+ l8 x& b& X- t V: oMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);4 u ^/ e3 z) q5 R
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); # o# h- k8 V6 [5 O; H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* k2 k2 i# E9 A" t
0x00, 0xFF); /* configure the clock for transmitter */+ O2 S0 t7 _4 c2 v# b- z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
. b. ]1 A) q' M/ C4 VMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 9 l* L0 l4 |# q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ W* k/ f, F, ^7 Q, F
0x00, 0xFF);
' }8 b% N9 @8 i$ K: _! C+ {3 H7 ~( F! P0 h
/* Enable synchronization of RX and TX sections */ ) ^( g7 }: o7 W2 T0 g
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
' E s% }! ?+ a- h1 r* EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' [; o, e' \" q4 m1 R2 `, R' c* NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 \* F9 ~6 E& L6 p4 P5 d8 u7 r! h
** Set the serializers, Currently only one serializer is set as
$ N: M& r$ u# F# U1 [. k5 A6 r2 e6 z** transmitter and one serializer as receiver.3 \# i' x2 u1 k4 b9 q7 E$ p* b
*/5 o3 G% e7 S, ?! E/ {% i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! l) m. N ~- q& E/ [+ NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( i1 C$ @% |2 q7 g0 v- b' a& A** Configure the McASP pins
" Q9 K& _+ V+ b0 Q! }** Input - Frame Sync, Clock and Serializer Rx
8 X0 X+ _9 A' }** Output - Serializer Tx is connected to the input of the codec 2 V0 q6 u4 T+ H7 n8 t
*/, [( \. @, ^: i7 {
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);7 \. ~9 P9 j' y; D$ c( j
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));. V1 E2 A! h, N
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 @; E+ m B$ u" Z2 ^9 C1 ], B/ Q
| MCASP_PIN_ACLKX# V& P& y7 H& [* W8 j0 R
| MCASP_PIN_AHCLKX v4 p# L4 x) n& H1 N
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 _! j) P5 G, \5 v
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 u5 b M& D5 l3 I. ^| MCASP_TX_CLKFAIL . D. k4 v" |: d. V
| MCASP_TX_SYNCERROR
& U: _" D, S. c. D5 ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 l/ h3 M. {5 Q# P ?| MCASP_RX_CLKFAIL
. u% w2 F. @. x5 Q! P, O| MCASP_RX_SYNCERROR : T+ d$ Y# ~4 H( M! _5 K
| MCASP_RX_OVERRUN);4 D2 M$ p4 D9 Y7 ?3 y! D3 c
} static void I2SDataTxRxActivate(void)
; ^* ^1 U7 i# \5 f/ F# D{
6 V" s/ m6 e( \5 A6 Z- U4 H! ]* J1 u/* Start the clocks */, F# w1 ]1 l7 t/ D& j% \" [
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( x3 q0 {3 N' z( ?6 Z' TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- j+ _* E& @# `& m$ J$ ?4 f
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" e( S* C, g; z0 t2 x0 @7 z& KEDMA3_TRIG_MODE_EVENT);
: K. f# Z4 ^1 h% FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, / @: g9 C- T3 C- e v7 X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
& z& v/ w: Z( H& h( T, _McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 U' D1 y, T- i- V/ c I; CMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */: z1 h I7 y( Y& Y! F, i" G
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */8 k' [6 [! `8 c" ?: X6 p7 E; h
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! h/ H8 a/ H1 j) PMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);( M9 f7 `1 Z3 s4 R, K/ h# X
} ! ^# [9 Q5 p% I
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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