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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
r$ W' ^9 F1 c$ y) N; e5 n) Sinput mcasp_ahclkx,
3 ^* ?( S7 D8 W7 e" Rinput mcasp_aclkx,
( N- `1 R& Z Minput axr0,
( d' X: m$ O' t( Q% k% t' n; N) l, ^" z* d) `: Z" S4 x! O
output mcasp_afsr,
2 d2 s' s E# a3 H& B( [. m9 R- doutput mcasp_ahclkr,
- S- B: E/ B+ y+ |* H& ~output mcasp_aclkr,
o: G3 }. y. s4 E4 H, Q& p/ Poutput axr1,
; I* M: G6 j1 s4 Z! A( R6 S3 n assign mcasp_afsr = mcasp_afsx;2 s7 A3 }, Q2 `# H
assign mcasp_aclkr = mcasp_aclkx;( M+ W' v' [7 x5 g* ]5 Q0 L* v
assign mcasp_ahclkr = mcasp_ahclkx;1 Y+ E5 ]. b1 }. s+ G
assign axr1 = axr0; 2 l2 p; _% B, P* w* v" U7 J8 _
6 i( H! [! {- ~) w/ ]8 e8 S( d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
( N4 C. h1 i. u+ bstatic void McASPI2SConfigure(void)
& r+ J- t$ {- g3 M( P+ ?0 g2 E; o{9 o4 R/ f: Z+ t7 ]% D
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ \9 \' U0 W- M! z' q& s" t1 Y: P, y) qMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; D! H* `& L- X/ t$ W. L9 Z6 }1 DMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
+ w1 B: @- O* Y0 ?McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */; B6 y* u8 M' ^' _! V3 K$ m
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
x" C( G9 p0 ^' ^) wMCASP_RX_MODE_DMA);6 ]( o: J" ?! `+ E3 o- V6 p
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 {0 v# X9 v9 h/ q7 _: ^MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 ^$ P2 l9 C6 ~+ w/ JMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& I; R1 b1 Q7 X) v& q* j2 C2 xMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);2 Y2 c' s4 X: U9 K0 T# B
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; G$ |, q( H& DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 h' V9 V1 ?& q7 }5 v) J1 cMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);7 Z, ]7 f( K" v2 `, L
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 B% |8 ~% M( Z8 CMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
7 }" g# c# b3 Z+ U0x00, 0xFF); /* configure the clock for transmitter */$ O9 f7 R1 q) O3 s* f0 b
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);' y* L% I, v- T g- R( N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + x2 e. g R) D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,& [' |, ?9 |3 B# A B. g
0x00, 0xFF);3 V! U+ V/ k1 [# H" }7 P
' I# b0 x7 P2 L/* Enable synchronization of RX and TX sections */
7 @- K& P2 C# |4 V$ WMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 X0 E' d/ G* s. z2 ?5 Y O. S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
& f% c& p2 R3 qMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% |: K6 z2 U# w+ }1 e e
** Set the serializers, Currently only one serializer is set as: P v$ i+ c' L' Z! |7 |
** transmitter and one serializer as receiver.
3 U5 t" ]5 ^! I' r' k4 q" o: a8 U2 r*// v- _$ H8 k* o% f# S9 w* V* L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. T. N! @9 t) q5 m5 `" G# LMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 H0 t9 Y% q, C4 i ~4 s, r$ L
** Configure the McASP pins
& R( g- i; j- R8 j** Input - Frame Sync, Clock and Serializer Rx/ V& [: z7 g% P$ s8 k
** Output - Serializer Tx is connected to the input of the codec 1 X' r7 d0 R* Y2 K$ M
*/) L& ]6 ^; K8 I0 r2 F& i
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 s0 U9 R( [' c. S
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ R( H% |0 J6 t. ~; m% KMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# x6 s$ Y3 m" d1 ^. f% }
| MCASP_PIN_ACLKX
( B+ m" E' R4 }7 X8 Z: d| MCASP_PIN_AHCLKX0 m5 G0 ?& @0 F8 @. Z
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
9 h4 }6 G1 L+ J. y4 g& h2 ?McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + c, ]9 j: b4 S* e* P) Q8 c
| MCASP_TX_CLKFAIL
/ z9 P! F2 S2 F4 U# R* \* C| MCASP_TX_SYNCERROR" ~) E& E R8 z B M
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR " j+ h6 Z( K, J. T
| MCASP_RX_CLKFAIL3 _' a+ E0 s) R0 O* G3 ^$ O; ^3 z6 J6 w
| MCASP_RX_SYNCERROR
* r! z p* D0 K# v T! k9 v| MCASP_RX_OVERRUN);! C# r" Z3 M- U4 }2 V
} static void I2SDataTxRxActivate(void)
$ O) I0 d: _! @) u! G{
8 W( K' c4 O' y; x& g3 N/* Start the clocks */. q9 f' z, ~/ G; l% |
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ O+ \$ K8 [/ k+ L" {% ~/ b' c
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
& n2 B* H0 J: {- ~% {EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX, x, V G2 N5 e/ X, G
EDMA3_TRIG_MODE_EVENT);
, O4 X; v: I) _: y v7 I1 L1 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, , Y" s# W7 z! Q6 G. ?
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
f( f3 z% H9 @, s* f* hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# v: J; C9 x+ L$ W
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* P% t6 `8 C' b- ?, M0 h1 b/ i
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 ^$ z) y6 i1 d" P. t6 E6 s, jMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
1 l( x1 G, i: `5 UMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
! e5 H+ h& H: \. \6 V} . a, `$ Y) O7 @6 b3 A
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ' U8 F: Z1 Q; U2 [
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