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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
8 v$ @$ X& W w6 F1 \input mcasp_ahclkx,' L2 [1 \4 |* L- K; F' x
input mcasp_aclkx,
, j; ?* ]7 g, G! ^" Dinput axr0,4 R: i+ V+ G6 t* ?" R
2 M$ {7 I5 r" `; Y' R# goutput mcasp_afsr,
3 M& c3 q$ m: T% b! Y, `output mcasp_ahclkr,- M) }' f( V+ v3 M. j# l# E
output mcasp_aclkr,
- v* c+ e' T3 ]+ toutput axr1,
$ @4 B1 Q( K( w5 t assign mcasp_afsr = mcasp_afsx;2 [6 T' s* ^/ E0 ~: U* R, t) D
assign mcasp_aclkr = mcasp_aclkx;8 j' _5 [: c6 b+ ?
assign mcasp_ahclkr = mcasp_ahclkx;/ v8 [" T: F- }' H7 u7 {3 J- ^$ l: W
assign axr1 = axr0; 5 J9 x2 r4 w! t3 K* [& {4 M
* N0 U+ a! R/ K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
' h* W7 [/ F [% Gstatic void McASPI2SConfigure(void)$ H0 p k. e: W1 G. C" ?1 q
{
0 Q. Q" Y( v8 T) s( a' SMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
; m& T: y& h% K, P# vMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */* }0 H+ Y6 J+ x
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
& l" j1 M' z, S( [9 X& H. pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
# ]; D* R8 K$ J) `1 {McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( X b9 a. f1 A# |+ OMCASP_RX_MODE_DMA);
+ G3 v+ X: P# D! I5 MMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,( p( C( v4 M# g/ I( C2 C/ z" l
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
O. R1 l' i6 H6 SMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
! c E* F% G" H1 y$ X4 k( DMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% V z% F: W! @1 x7 J0 W7 V. @ k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
) a5 P. B. G+ c' Y* h! vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */; t& q8 s: F4 C% f! ~0 a1 l9 ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 r2 l z5 p, X6 {McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
( h5 i, l3 T+ |3 wMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,9 D! s2 v% q% f4 x
0x00, 0xFF); /* configure the clock for transmitter */4 w8 p6 W3 L j6 I* S
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ Q; R- _* b; d# UMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
+ p6 l7 I# D6 M( |# pMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 C( Q/ ^% r4 F
0x00, 0xFF);
/ n! C* d g* V( A
9 F+ }2 B* M1 \: u/* Enable synchronization of RX and TX sections */ & n' w1 F! ]/ q- p
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. H5 H! b0 V& p) _8 r' ?! T
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 s9 q! e) o4 {: \' i/ dMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*0 x, _3 P1 ~8 u+ V( A5 e
** Set the serializers, Currently only one serializer is set as
& D6 l x0 u1 g m** transmitter and one serializer as receiver.
2 n5 \% F i* C4 X4 Z2 A: k*/
& Q/ \- \) B3 A: ]1 G2 P2 ^McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 f5 |$ ~7 e% u; a/ T2 ]
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
+ D& `: O0 W# }+ i3 e# W** Configure the McASP pins
! ^9 L+ ?" r$ _** Input - Frame Sync, Clock and Serializer Rx
6 ?9 ?9 j6 ?: ^# ~** Output - Serializer Tx is connected to the input of the codec 3 x( A; x1 X, m/ l, X) O& b7 T
*/5 H& o/ W2 `' D( u! e! p, n
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& ]5 N0 \* ?0 i, g6 w% EMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: V1 D( b* p* n& c# L/ [McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX# K+ {2 i# H4 y
| MCASP_PIN_ACLKX& j% J$ Y" a. _ E* S' @) b
| MCASP_PIN_AHCLKX- Y, _0 i9 K# n* v Q' u/ X ?
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
& ^) ~4 Q; u/ QMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ w) W( N4 V, G6 ?# o. i% D
| MCASP_TX_CLKFAIL / k; c( n0 s- b) @
| MCASP_TX_SYNCERROR$ s$ g* l! p8 P: A9 m6 J# i3 a, W
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( d2 T- P; l% H x7 q0 ~. M8 D| MCASP_RX_CLKFAIL6 q/ }0 S$ V7 \. T W2 ?, U/ q4 l" k
| MCASP_RX_SYNCERROR
- X Q" _& g! ~ _# F| MCASP_RX_OVERRUN);
8 [7 g3 i! h: ]} static void I2SDataTxRxActivate(void)" @5 c- {2 g O, D7 d! ]# E
{: [7 D: O I, B4 Q r/ ?2 K
/* Start the clocks */) t( a5 \7 l0 y( b+ |* a H- F5 P
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); C# R, m( u$ q! B& B$ o) J' N
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
; R# }! j/ b2 P! fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! L! u$ Q$ l/ s: Z0 k% J1 R g
EDMA3_TRIG_MODE_EVENT);
i5 G J: L3 v/ A% Q5 Y9 B5 oEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
! b/ v6 {# C5 I( b w( C% |9 XEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
! P/ ~2 X" D! D) R- dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( p' U, V: W+ g; F+ C. b0 gMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) _4 k+ @0 A1 n1 f& o! u
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */- J' v1 `: u8 b1 w) J; Z/ K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);8 ] W2 q# S7 q6 v
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 a' n" o9 Z0 l3 f9 j( e6 l} ' h% R* v+ d9 N) D4 s! P
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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