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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, H2 U/ V. a4 } O
input mcasp_ahclkx,4 k S- X3 a" F' H6 i- I' D6 F0 R2 K
input mcasp_aclkx,6 x9 g7 h% b' l+ d$ i1 s
input axr0,
8 }8 U8 }. X3 E2 q: D1 Y! M: I. x5 w/ [
output mcasp_afsr,, D; h7 ~/ G4 L
output mcasp_ahclkr,0 `% D) [' |! b) L
output mcasp_aclkr,
, g# X$ b1 f- Coutput axr1,: G8 Z( B# W0 M
assign mcasp_afsr = mcasp_afsx;
4 l# a7 t$ d" f4 v+ Q9 B/ Rassign mcasp_aclkr = mcasp_aclkx;
1 B% V! ~3 m" ]+ s6 @0 v1 Fassign mcasp_ahclkr = mcasp_ahclkx; V# [0 T- `2 U; _
assign axr1 = axr0; # D8 M) ~9 A7 n$ z
7 ^$ ?' [5 ~* y. H" g
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; G, K' _" Q$ x
static void McASPI2SConfigure(void)! X7 m# }' e8 m% P. d( o- T
{$ K* v& F7 m2 [
McASPRxReset(SOC_MCASP_0_CTRL_REGS); X( ?7 P' _* b4 W
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
8 v0 C6 x/ {2 Z5 KMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
( m" d8 w) p; G% `! g3 wMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) K9 w% j9 G9 F0 d' RMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) f1 m/ J3 A; W4 ]1 ^- g* P
MCASP_RX_MODE_DMA);
+ a: P5 S3 ?3 H) b, m. y& CMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 j4 _; ^( |: B6 ^0 ?MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */# W( {& b. E8 t) L: X
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- k+ m$ m( v7 M0 SMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
6 H/ e$ C" V1 q7 z: ?# [McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- W# {- r: ~7 RMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ \* _( v ~! i# m; {( `McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
' U0 [/ B& _0 |* fMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
) Y: Z8 }* D1 J" S% D! w M& EMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 ~4 N7 v5 M" j4 [' M0x00, 0xFF); /* configure the clock for transmitter */
; x# _7 H) E% z. \6 OMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* O8 Z$ i( a0 X. B% g
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); * S# y: P) S1 Q: i; Y3 l
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,( j- n/ L2 S# ?4 {! I% _% g
0x00, 0xFF);" ]3 O1 E9 I! r
; B- D: [, g" R8 x
/* Enable synchronization of RX and TX sections */ Z- E. F. j8 Z" @
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& n4 l8 I. {: @, J$ E# nMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);& w) F' {' v/ }: N3 T1 p2 y# P
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
; }6 H8 ?+ ^6 a- U7 _6 v** Set the serializers, Currently only one serializer is set as1 B* |1 t) V8 O$ I) m" G2 v2 b
** transmitter and one serializer as receiver.% W% n3 {7 w3 t- [, A' q
*/) n" R! i" r3 N0 D9 p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- y: C+ c4 V( ^$ N- D: j6 z+ p }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*+ A% m6 @0 z( ?/ M
** Configure the McASP pins
6 y5 q, M i' O* l+ W3 r& O2 Q** Input - Frame Sync, Clock and Serializer Rx
" A! J2 ^* z2 a" g. _$ b7 m** Output - Serializer Tx is connected to the input of the codec
6 m% c$ ~2 @( y$ [*/
, [: u/ K, k* r; m/ v# t4 U: aMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
! a- U2 b' m5 P4 U2 k3 w/ {9 PMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));9 Y0 R r- u# }' @6 t& U! `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX- f/ g. Y- l3 d
| MCASP_PIN_ACLKX. H; T9 X7 F' Y0 T+ L& E. d& W6 C8 I6 z
| MCASP_PIN_AHCLKX
; `. |5 n5 j5 W W8 e3 M9 B( l1 v| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */1 b4 G3 ~, Y, \% ]6 B
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. I" H% P$ ?- D' H- A; h| MCASP_TX_CLKFAIL
/ q4 {' u5 n& U| MCASP_TX_SYNCERROR. e) s( i$ I* n* e2 Y$ n- K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
, i" [# M' _( @( R| MCASP_RX_CLKFAIL4 W/ ^% V$ `0 M/ H p* ~: y
| MCASP_RX_SYNCERROR ) H4 q* o4 N' p1 ~( s
| MCASP_RX_OVERRUN);. v8 D1 E# {" N8 Y& f; z1 _% y
} static void I2SDataTxRxActivate(void)! G* ?+ s2 I1 }5 f
{$ `% ?3 u) s* i- y$ f# J- i8 t
/* Start the clocks */
" R6 ~' S( J. ^+ a/ n, sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);& H- u% b9 F I, p. j
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */- e' ?, U. U8 U$ d3 R% s
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
! i- f. ~4 H3 H4 H; VEDMA3_TRIG_MODE_EVENT);- l- T. O( L R5 V. U
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* `1 t/ u( _+ M! n% T7 m, `EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ J( a# e. ^& p) D: E3 O8 x8 a
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! M% P1 H ?( P' @& ~
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// F% h: g& l' Q s1 {; @5 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
; k7 F6 Y3 O" ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);" ^1 h. `6 p$ `9 ]! Q( y O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* D0 G$ {0 b5 t0 Y }( l
} , T0 O' D0 e/ Z4 K
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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