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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
6 v0 x7 q$ S. q6 yinput mcasp_ahclkx,% @" ]3 m* [* z9 q7 p# R
input mcasp_aclkx,
2 H3 G$ @" r) C: N2 ginput axr0,
3 e% R# d* q0 V1 j. I
6 G9 h- k |- h- x! ?output mcasp_afsr,+ F# L p. _3 C- Z
output mcasp_ahclkr,: k/ u/ T U- v# t8 N
output mcasp_aclkr,
+ P0 g* {5 T* V9 b! Zoutput axr1,
' n; F! l7 m e& r' C assign mcasp_afsr = mcasp_afsx;
) e" R7 b. q3 }assign mcasp_aclkr = mcasp_aclkx;
- r+ I. w/ m; \1 Xassign mcasp_ahclkr = mcasp_ahclkx;
9 M& R! Z( E' u' {+ hassign axr1 = axr0; 2 s5 X5 X9 f% c0 U, N
5 K$ v) r, n( ^6 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, |7 F( y1 S% ^3 Dstatic void McASPI2SConfigure(void)9 o) s$ f$ Y; l- f0 g3 C6 a x/ W
{
! Q" f* F% Q0 X/ e6 qMcASPRxReset(SOC_MCASP_0_CTRL_REGS);0 r3 X4 a3 n4 s, O) w
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ o5 ~# W# M+ z! m9 fMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
0 R5 E/ ` Q* n! q3 GMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
8 ]4 O C2 l# {6 m! K% c0 ZMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,9 m7 h2 s( u. _! Q. [
MCASP_RX_MODE_DMA);2 Z# ^6 w; j6 W3 S8 w4 \) N) y
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ {- S- v% s5 x" R- ?& q# t8 x. O; J
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' y6 N% b2 L; w2 R: m$ _6 G$ iMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, : N- Z, G2 t3 w- h% A
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ~+ Y! z! A) n- ]
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 2 t$ {0 d. g4 x/ s' n, ~
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */4 K9 I* o- b" H3 M" O2 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);/ s* n" C- E, z: t4 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 E8 E/ U" B# e5 e) W
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, J$ u( T. C c1 M. s
0x00, 0xFF); /* configure the clock for transmitter */" |9 p+ L2 T6 t) _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
U3 F' n4 [( B8 K+ Z9 ]McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! c. i+ Q& O( l8 ~0 s* F v) D; x2 U
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 b: N) g3 _9 R6 V/ q b, O0x00, 0xFF);
4 b# y0 l! \* K' L6 G) m. `
$ s, a2 e8 B: R: u! K2 g# p c, t/* Enable synchronization of RX and TX sections */
' D4 j2 f4 U; o5 P$ d7 [McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
! t- T& q6 r8 z; R$ TMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 f) I1 I5 f1 J0 }# ^
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*1 d( f4 B9 j' }; u! F4 z
** Set the serializers, Currently only one serializer is set as
+ S' k4 c* Y- l9 I5 b6 f** transmitter and one serializer as receiver.# m% \( e% b I
*/% `. k7 i& A: f: `) a' p* p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# S" @5 E3 E, U. jMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
* a! V; S5 ^. Q4 n* U3 b** Configure the McASP pins
( Q' h; ]# I1 }7 d/ ~0 J** Input - Frame Sync, Clock and Serializer Rx
3 _* e$ `2 O/ r9 y** Output - Serializer Tx is connected to the input of the codec ; z* I8 s/ c1 \! j
*/! B: y3 m8 |' o' O
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ i7 | d' [2 fMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" `3 c( l; m# F2 E6 s9 TMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX5 ^7 m' W3 I2 J; d. j' U
| MCASP_PIN_ACLKX
: D% a* ~2 e9 `| MCASP_PIN_AHCLKX- y- Q4 Z2 R `" n- e. y0 q
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. F+ j/ C* Z7 j& [3 s4 m
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' W9 I: _ v# d. H( V' n9 B| MCASP_TX_CLKFAIL
. |' M8 H D8 L: O| MCASP_TX_SYNCERROR
, m2 L4 }& l: u) G2 W/ t1 g5 n% s| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 x# U, r$ r2 D# N
| MCASP_RX_CLKFAIL
1 U7 x0 v: h# _- \$ P' c% g| MCASP_RX_SYNCERROR
. }# p* p) Z4 u* ?| MCASP_RX_OVERRUN); F2 c( a1 z7 s) {
} static void I2SDataTxRxActivate(void)7 X/ v# U, p% f& I3 s( o6 ?
{
: u+ P% P, o% p! ?/* Start the clocks */
1 d# ^( V1 {; P5 X5 z, c; v9 i; T5 ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);. E5 J* }1 K" @7 Q% e. t
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
4 b' i# K u5 _7 ^4 F! }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 K( @* y$ c v1 {
EDMA3_TRIG_MODE_EVENT);7 D$ c. t* U' e. } ^7 x+ F
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, + L1 V( s3 U+ o- {' a' X
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
, }4 F R! r5 U( M QMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);2 Q: C$ Z' S, l6 d
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
$ Y1 H. A+ L- ]- \, D( lwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
6 ^( k# s* k- D o' J3 Z1 @McASPRxEnable(SOC_MCASP_0_CTRL_REGS);4 I- }4 N) x, k% \
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: J. h. w* ?6 e}
/ ^4 a$ t9 Y) H1 C) y2 W& ^; T# d请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. & w* ^8 u' N9 t* [. j6 Y, y
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