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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: K- Y! W; F& ^) binput mcasp_ahclkx,7 G! s+ C/ W! j' u5 q3 y! G# y
input mcasp_aclkx,
7 j3 V: E, Z5 g" _input axr0,8 W% m/ U! g+ V9 W4 i6 X2 X
, Q) f. w9 U. Q% Q9 ?
output mcasp_afsr, |# O. K1 P4 v- Q
output mcasp_ahclkr,5 r! d* V3 Y, h: w# U% R, H% O
output mcasp_aclkr,* S! D" B |, m6 d% D3 l! W
output axr1," w& J0 g4 F& Z n0 Q
assign mcasp_afsr = mcasp_afsx;
, A6 x, b& b O0 X: x3 Wassign mcasp_aclkr = mcasp_aclkx;+ h/ d! n% E: c) }- }, I2 o! p+ p* E
assign mcasp_ahclkr = mcasp_ahclkx;$ i+ b% B1 p4 ]" E
assign axr1 = axr0; 2 y/ z* e9 l' ?( D- v3 k: E P- m
* \1 J9 Z, C5 v7 Q* D8 z" w: j o在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
, B3 `! t( N* m/ \# y% C9 m; Astatic void McASPI2SConfigure(void)- x, Q- D; M. c) I5 z7 T; q, B
{
+ X+ p3 ?+ f. g# Z3 q8 p2 ?McASPRxReset(SOC_MCASP_0_CTRL_REGS);! \& A, l- ^8 ~
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */2 V8 h) |5 Y! ^/ D5 ]1 N( b3 [
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); L& R/ _ R4 C
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 q/ x( x2 z" |5 r( j
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 S" E( `0 R7 F/ U& u6 G" a% wMCASP_RX_MODE_DMA);
; j( a; v p* P( q% @! O' a1 kMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,# J8 H4 Q, m0 e, R8 s1 Q! z
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% v; P, n0 b! j Q0 mMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ N$ S/ }+ ~" zMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
! Y9 V+ r8 E8 l- ]: H4 Y+ tMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; [ s8 s, a F1 X7 p x% W
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* Q2 U5 U% U9 c' n9 y7 N3 ZMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 O; L( I5 P* E b" O( H' [McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* m! F$ v4 g) }1 T5 BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,' K( n$ ~7 y( d+ f+ K( u- q( F% n
0x00, 0xFF); /* configure the clock for transmitter */
; f5 T. y9 a' ~' mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
8 `+ X/ q# z1 `# ^McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ! M8 ^2 ?$ B& ~8 `+ G5 k
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 k6 P, X) l+ p% Z8 Y! m: [3 R0x00, 0xFF);) S1 o8 R' m# B/ q9 { P
# y1 R: ?6 Y3 P$ l0 i
/* Enable synchronization of RX and TX sections */
6 e; Z5 P- {6 b, J3 Y. y2 d' eMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 T4 d. y" {" e1 l/ u; e- l, |4 EMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);% ? |+ ^# B9 \
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
S; ]" O) J0 v- g** Set the serializers, Currently only one serializer is set as! a: M o$ ]$ Q
** transmitter and one serializer as receiver.
- G; k' W0 A5 Y*/
) Q) ]$ T. O" [4 I, S" tMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
" W0 F) K2 ]( {; W, l# @, P) f& u, nMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
4 O$ D2 A. S( p** Configure the McASP pins 3 S4 K: U. A! _( a
** Input - Frame Sync, Clock and Serializer Rx
7 }& H: j8 y; [$ D$ S. G7 X/ B& j3 z** Output - Serializer Tx is connected to the input of the codec
+ W9 C( h& L2 R' b2 n*/# I$ J, A X* A. C6 H+ z
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ U& o" f/ K, z/ s: B$ UMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 r p4 _+ n3 ^4 T% s; ~* ]( Y! k
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX" V0 Z$ q: l) T6 V
| MCASP_PIN_ACLKX0 q" C+ ]% s& d8 V
| MCASP_PIN_AHCLKX
: {9 X1 A( f2 h; W: J: g| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */. w7 [* N: y' ?7 A; J
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR # e0 Z3 j+ k6 a2 O, T) t2 f. c& H
| MCASP_TX_CLKFAIL
# V, Z8 U4 z# _! u| MCASP_TX_SYNCERROR
1 `9 @9 d5 g1 J/ D" L3 c4 N# j- I$ K| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
/ b: Y/ x7 J2 ?- p| MCASP_RX_CLKFAIL
0 |1 x; D J/ {5 V4 \: b$ {7 t| MCASP_RX_SYNCERROR
; l8 ?8 _# H2 O, r- ~$ X) Z( G| MCASP_RX_OVERRUN);0 o" A$ B8 O. l! g; o( _! i4 {0 E
} static void I2SDataTxRxActivate(void)
# D% f! F4 @' E/ N7 L: S$ v6 P, L{
8 ~3 v* ]' p2 |$ O' m8 S& l/* Start the clocks */6 r% h: e6 P' V$ z0 j
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 ^+ h1 k6 Q# i! f fMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
! a, Z' i( v0 n" S& {( i" {' nEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 t" ~" U1 I& w" w& b4 _
EDMA3_TRIG_MODE_EVENT);/ z- c4 b4 I( V- R; Q" Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! k2 L1 ~- o8 Q: | L
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ M/ E0 q' c( c" j B1 nMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
$ j* Z7 ~$ _7 X5 q9 b2 FMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* h, }& c$ W- e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
! _) h2 K, K% \* U- w2 LMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ r. b5 H" o$ c" z; {, K yMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
# ?% [1 Q2 m0 b. P4 ?9 m} $ f9 ~: q$ x9 N( q0 v
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
2 |6 j7 F* ?5 V9 k7 s' t |