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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 s1 ]) f# Y+ O3 pinput mcasp_ahclkx,
6 A5 H7 A3 O# \7 ~input mcasp_aclkx,- N% D) M+ I) z
input axr0,, g6 t- A; a9 Y1 y
1 \" _: [; n: @2 T' }8 `2 z& foutput mcasp_afsr,
& s3 m1 N( T& Y5 _; w9 |! noutput mcasp_ahclkr,
7 ~1 y7 E/ B( l2 J2 W8 routput mcasp_aclkr,
' F: g+ e9 I; ?9 X) E J6 ioutput axr1,
( J P, L+ k+ x2 R& ? assign mcasp_afsr = mcasp_afsx;
/ Z) x8 ]# Q% `: Tassign mcasp_aclkr = mcasp_aclkx;
6 r# N/ R; O0 E+ Rassign mcasp_ahclkr = mcasp_ahclkx;! a0 ^, g) X1 U4 r1 b [
assign axr1 = axr0; # l6 O4 I$ [" X& q% J
. d, o. A, B5 ]" g: M在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; J5 e6 g& |+ {$ O
static void McASPI2SConfigure(void)' }% r( \1 N8 ?! R; ^/ r1 H
{. Y: ?& O% y6 M' u0 E" d1 M1 E5 L
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 g+ j! ~/ \5 y8 e5 _! lMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
5 d; Q" t% X, f G+ }' EMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
9 r, l6 g- m6 O0 x- x. N; M! D, XMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */0 C9 B1 A5 b, r
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) c( Q5 y4 n) A/ J* `
MCASP_RX_MODE_DMA);$ u1 o' x* Z P! [5 @8 V
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 ^/ {/ \1 E5 A* m2 @MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */9 _& M: x2 U. V& Z! F) K
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( Z. X# u, ^; p# C+ |MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' U" @5 i+ v# oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 3 W- O" V$ J1 @4 I5 e
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
, ^, N; L5 R3 U" TMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);9 _) q* `: q: A' q, Y* \
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); - b: x* J, b. ]
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
8 Q! a! q; @4 J0x00, 0xFF); /* configure the clock for transmitter */
4 d0 a3 _% o+ S" ^0 o6 Q) WMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 ]' @; c. i6 u6 g# T+ U" X9 n
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); + W) ^6 |/ F) t9 m# {0 B
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
3 G; a* i% Z+ h. m0x00, 0xFF);' `9 T( r3 O% [) M* m! i2 d
% h5 P/ u) Q; Y5 ?9 [- a& e" z$ Z
/* Enable synchronization of RX and TX sections */
5 J) y! O1 n, k+ ^4 [5 |McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
w5 \' X9 ^0 c4 A2 GMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);. Z( r* Y3 P3 \6 q
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 y, w# @& S+ V% c% ~: ]* W3 n
** Set the serializers, Currently only one serializer is set as
7 y. f# r! a: N; W( Q& v! m* p( V** transmitter and one serializer as receiver.3 `/ ^3 i) a; K5 J: f! P
*/
0 @0 e8 _, l1 o C9 rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 g+ O! J' e2 P8 M+ i
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*/ e4 w0 T( h, Q0 B; x
** Configure the McASP pins
& G4 m7 K6 D' N** Input - Frame Sync, Clock and Serializer Rx' N$ ^+ z, W8 z
** Output - Serializer Tx is connected to the input of the codec
" f8 v! C1 b ~! |9 b, k*/( N& n) U+ K. S4 r" y! H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 h, }6 q! Y8 V N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
3 q( U1 B' W: C: S B9 yMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
5 F% S9 X/ [9 a, P| MCASP_PIN_ACLKX% {& Q0 Q! `9 o+ m
| MCASP_PIN_AHCLKX
* x, W6 s2 q/ { Z4 y| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 H0 k1 z" t+ S3 ~! yMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR . b; v3 ^2 l' i W" i
| MCASP_TX_CLKFAIL ! O0 D. H5 `' ?5 l# F
| MCASP_TX_SYNCERROR& {4 u' X" d; J" P6 v4 I9 n
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' h; O& [" w# X% v/ l. }) c| MCASP_RX_CLKFAIL7 B9 G& N* Y" B) @1 o' W5 z) ^
| MCASP_RX_SYNCERROR % m- K, w! m2 O7 x2 C8 M
| MCASP_RX_OVERRUN);
: i0 C7 P, e% @8 N} static void I2SDataTxRxActivate(void)' Q# V- ]: x1 [; D1 H
{5 [' r% Y T$ L$ i! H8 Q4 n
/* Start the clocks */
7 \ s& B, H- }5 {$ TMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
4 S, ]6 u9 ]7 Y# GMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
$ A) [5 _- q+ `7 C- ]! @5 m8 jEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 [3 Y- o$ Q1 pEDMA3_TRIG_MODE_EVENT);/ M. `3 v# `. |" _0 f# i( R
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 2 `( ~2 B7 P" M/ i5 Z& `' Q9 G! ]. d
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */' z9 h( M, @, `3 |0 w) ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);# f& o- k9 H$ s4 N- {3 d! s
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */4 u! u+ M5 a+ R' q0 ~5 o
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
7 _" x1 O- t: F0 B0 K% r& k) s: G) xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 T1 x! l& a1 K' P1 _; i' N, D* T
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);/ z0 K* f* r) ]5 F
}
; Z b2 N0 x9 |请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. : `1 K% m! N8 Q5 R
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