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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
9 Q8 @7 w% B3 Einput mcasp_ahclkx,8 Q7 G. ]( v3 E
input mcasp_aclkx,
& r4 d: K2 S7 V9 l$ h- a3 C* rinput axr0,
) v$ N! w2 Y4 a( M+ B3 @
# ~$ N/ u$ \1 X$ {. {1 V1 [output mcasp_afsr,
8 m* n" v* d; f7 o5 _' Houtput mcasp_ahclkr,! w6 @$ o& o) \; I! f( n
output mcasp_aclkr,
2 G5 l+ t$ S0 d# L% a/ n4 ]output axr1,
% a! C5 z; c y3 J* Y, e8 C assign mcasp_afsr = mcasp_afsx;9 F% s! ^( j/ S* {$ c
assign mcasp_aclkr = mcasp_aclkx;; }3 E0 X- E( A C* ^( i
assign mcasp_ahclkr = mcasp_ahclkx;* @/ k# I: k" B. v9 Z$ ^
assign axr1 = axr0; 8 P' |% Z* m0 X: u
, z$ v$ y& j) g Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 0 t; {. @! k/ P% B
static void McASPI2SConfigure(void)" K, t8 p# }* t( \4 F
{% g5 g- v2 h6 O/ y* |
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
5 q; l7 P: e2 }% [3 B% ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
9 F" n4 i7 @! D: {9 eMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# W/ b" o) M6 e, J& l4 P, n# _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 [$ y: F6 b) C6 N; X$ EMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 a2 L% y+ l+ `+ e
MCASP_RX_MODE_DMA);8 Z, A5 F+ p8 y" B6 u+ Q; X: o% X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: L a; Z: @/ n& R0 \& _+ `MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, K: [8 \$ @4 ]' @
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, , L& a) g% L) j/ l+ c' x
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);: d3 s# O0 C0 c$ r* v( i P3 h4 C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % X6 O: [- _; m: X- }
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */0 b. t2 W( z9 x+ E2 }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);3 s% i/ C4 K: J- t( x& ]( X
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' G( l! G) v) d, k# @8 ?) ZMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
1 i# E/ d0 ^6 b3 V9 x0 H1 M& N0x00, 0xFF); /* configure the clock for transmitter */$ l; ~5 b! X! @4 o1 t& A U- l, s
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ O7 L, j2 ], f4 [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 7 B1 U4 e& o8 Q
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
+ S/ y! M' E7 m( l0x00, 0xFF);
2 Z8 z2 t4 i) H( {' m- ^9 J
' Y8 H. @, G$ t; W! s8 X* U/* Enable synchronization of RX and TX sections */ # i m, H6 i0 C( a
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 G. E, j; C# A9 s; ]8 \
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
1 `, d) R9 f5 s; |! }5 ?McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* T/ P2 ]" b: L- e% G# P# i4 | }** Set the serializers, Currently only one serializer is set as
" U' u( f/ L" p$ G2 b" l** transmitter and one serializer as receiver.
9 J$ |5 m: |$ Q( e*/
0 ^& A7 c% J. V( ^9 {! M2 j, `. J+ MMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 N! j8 L9 D' D3 N2 C, v6 `McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*4 Q* v. M! }# g3 Z3 W# V
** Configure the McASP pins
8 {8 H& f" {5 J" j** Input - Frame Sync, Clock and Serializer Rx
- l% _) m" c0 T9 w6 A, ~" ~** Output - Serializer Tx is connected to the input of the codec
& b1 ^1 R* I- f2 v# H% {*/
3 p/ a# A4 X% g- _McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 R; p, V; A$ s& q; l3 E7 o' @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
" i- p/ Q- \9 o) @, ~0 w# V5 }McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX) \9 b; G4 U. x9 S9 L6 W+ n
| MCASP_PIN_ACLKX) ?, x6 J$ u8 K5 h. x/ n* i- f, [
| MCASP_PIN_AHCLKX
" ]8 p9 y( X8 {* h# H; u| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */0 o3 s7 ^1 V+ y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% ~* l* x) c, q( a| MCASP_TX_CLKFAIL % \/ T J! f( ] }4 O
| MCASP_TX_SYNCERROR# I. B# K% r$ q5 P
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
" E; _. x# G9 c" g1 c| MCASP_RX_CLKFAIL
* k7 r& [$ z2 O0 o# m| MCASP_RX_SYNCERROR 2 Y4 W6 o! x& r; M% d" f, v) X9 U- X0 X
| MCASP_RX_OVERRUN);
& P8 f( |0 ~* p& O& L/ v} static void I2SDataTxRxActivate(void)! l0 S5 f0 I+ x; w O+ [$ u+ U
{
: X4 s- Y& z# }/* Start the clocks */, |! N& W$ Q$ `& h0 z
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);2 y% \" B5 w2 c; k
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 y; x: A) W) j5 `5 T0 fEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
" V1 _/ b6 P* h1 K) ?EDMA3_TRIG_MODE_EVENT);
7 q7 h5 q6 o( r; U$ b. F7 ~EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ J( b8 @& S8 s( }6 d$ \EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 `& Q; N$ \& G9 X% z8 N6 K3 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& H0 u. U h0 q" l
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
# @! z- d( { r# U, Y# wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 ^: Y g: ?. I# B2 ^McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( R" w% |+ s. D$ w( T; |' @' ~McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
3 P3 ^3 Z* ^: d: {$ F. x} C0 N) [$ q) ? ?8 C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " F, [/ A G# r. W0 Z& F
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