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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' |4 w1 b7 ?8 ?! n2 b2 W4 u, Ainput mcasp_ahclkx,
6 s3 n5 b- @% q8 W+ F, r* B' E9 Winput mcasp_aclkx,
% z' d- g2 M. m+ _% hinput axr0,
( [% C) c' L- X9 i
- l' y! _* a" \ H) ]output mcasp_afsr,
8 H0 F) P8 z8 J# a" o }6 T8 {* Voutput mcasp_ahclkr,
* @. a2 p; l; |; c% `output mcasp_aclkr,
8 _' n+ J: F# i4 doutput axr1,
P, H1 _- w e9 ~ assign mcasp_afsr = mcasp_afsx;' J$ Y& g3 J* a! ~+ d# K: ?: f$ C, l
assign mcasp_aclkr = mcasp_aclkx;
* c; A. `: {5 ^/ ?+ lassign mcasp_ahclkr = mcasp_ahclkx;. A: }- ~- Z8 I5 Q: n3 [
assign axr1 = axr0; + Y7 L& @0 k5 R# {6 A" L3 t6 _
7 j" q. y: M; N0 ~3 a在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 u z* _) T7 W C2 X6 ^
static void McASPI2SConfigure(void)
4 _# h2 G0 C0 \' y" \{( a$ y- H6 W U
McASPRxReset(SOC_MCASP_0_CTRL_REGS);" x5 Q2 p; c7 r2 ^1 O1 Y6 G
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% \3 \+ h$ I9 W( I- ^, F0 cMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);; l3 O' z! p1 I! K
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
) s c1 h5 ?& {$ R( N7 [9 V k% AMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,0 R% I) @ v i1 G+ {( Y( o
MCASP_RX_MODE_DMA);- A5 U) L; `8 n9 e; n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; P" d% Z ]8 X: Z" {6 t8 cMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */; y r3 t) M9 g$ n
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ( }8 w$ {1 _. E5 W# E8 v N- Q5 E
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);$ S' I+ }" X0 F, I
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
% e# v7 o, B7 ?- O" _" a& nMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
# A( S4 q3 k- @$ b* x$ RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 `- |* F% W) |- J. v F6 |
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 d# r( g7 W, @/ m. g; BMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# C; K( i- ~3 }7 `% _# @6 M! Y0x00, 0xFF); /* configure the clock for transmitter */
5 r4 Z6 [6 Y& Y( h: LMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);9 T& g: f0 k0 Q" b. U2 ?! j1 X
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; W* _, B( V( X$ p e8 PMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,# ^9 k+ B9 t" e/ O: F
0x00, 0xFF);
9 ^: ]; W3 q- p. |
% F2 q/ A4 |! _( _( [/* Enable synchronization of RX and TX sections */ . X: x# Z4 u- ~1 l9 |
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
+ G5 W/ }- U" p; T# O. KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);0 f( W! ?) x. ~, N/ _: ]$ M
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*8 `& D! d- q# Y: @6 K7 N
** Set the serializers, Currently only one serializer is set as' J7 V; d( k% Q( N
** transmitter and one serializer as receiver.( c3 H8 N( d' J$ T9 U& v* K' }
*/
& t8 N+ l3 P: ^' DMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! F, C8 P1 O- g8 f$ c+ H2 I* iMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, d/ q! I3 T# K& N) J
** Configure the McASP pins
( K9 t+ A N6 W- P( d8 j$ _, q3 q, o; b$ X** Input - Frame Sync, Clock and Serializer Rx& H7 e8 m# r( s a0 N4 t3 N% n5 e
** Output - Serializer Tx is connected to the input of the codec
& Q9 Z6 c3 f# e& w6 p7 t) v8 F*// ~* Y8 H; [+ ~
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);* h% t' H3 W- l+ B9 d
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
0 M2 ]: e" m! q z! hMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
6 ^, q) u8 e* M. B: E$ K# {7 e! q8 N| MCASP_PIN_ACLKX
6 A4 |) B C, S' g! l| MCASP_PIN_AHCLKX
) _3 ]4 q, x2 Y* J- @| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) [* c& U) y3 N' f0 [McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
3 k. J6 `$ M. M: V1 D* G| MCASP_TX_CLKFAIL {# n/ C+ ^, q( O
| MCASP_TX_SYNCERROR
: {2 {! O; N( @% v9 || MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
' N s/ o" i3 v3 \5 Z [/ D| MCASP_RX_CLKFAIL
) J5 M+ d7 g& ]# R5 a| MCASP_RX_SYNCERROR
' C* j0 S+ ]$ y9 ^2 g8 b% S% M| MCASP_RX_OVERRUN);
, u7 ^. l) A2 W' z* O} static void I2SDataTxRxActivate(void)! D5 b V4 Q8 @% }0 k
{
% M! _. L3 L3 N- F/* Start the clocks */) W2 w' P p6 _/ ~
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
" k# Q$ o' g8 {. a+ PMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 E: B- C5 i9 ]. A; x1 ZEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
( g; I3 K; j; }EDMA3_TRIG_MODE_EVENT);& ^ m* J s* ^6 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 7 U" F% [5 `. k/ G
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- i1 F% f' R' B# @2 o% u( rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);. z3 m4 e1 b1 Y
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) i8 W% l% r9 r& }2 L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */+ A- ^5 `/ M- C/ l
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) n4 R. z/ y: r- ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);% M2 E# m3 L& T: j7 y H
}
$ C* d8 v+ T, h4 K9 X请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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