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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,; d1 X5 F* ~ m8 j
input mcasp_ahclkx,
8 ^( Z4 q3 H2 y0 u/ D$ V7 Z) R Ninput mcasp_aclkx,
3 I9 p! d4 V; p* Sinput axr0,% T! G7 n' J; y# N. n3 u
' A6 {: j! s5 F B! K4 y! C* t& ~
output mcasp_afsr,
% t3 t a" G0 {6 Goutput mcasp_ahclkr,
2 _4 i$ a6 t8 p6 j; P6 R9 foutput mcasp_aclkr,6 }* e t$ v& y1 U+ t& I" K/ \
output axr1,
5 {8 X# K) I& y; q( P assign mcasp_afsr = mcasp_afsx;) x% c" M% @9 V7 L) |
assign mcasp_aclkr = mcasp_aclkx;2 O+ S; w8 I* e1 y4 g7 s9 O* k$ |
assign mcasp_ahclkr = mcasp_ahclkx;
) J, @) c2 K$ Y2 t: b: [4 e2 Fassign axr1 = axr0; ! y! `8 P: F9 m7 O
4 N0 ]$ `' w. K W& E- x
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 v9 f( k' D+ a+ H. Hstatic void McASPI2SConfigure(void)
: _, B# m4 }3 R# B5 J" E. _! z7 L{
4 b/ b; n5 }1 i, e4 RMcASPRxReset(SOC_MCASP_0_CTRL_REGS);2 _6 z# }5 h. a- S% Q. \( l9 f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& n' K, p* P% s# P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 F9 e( u. D- `, O) @McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// L y5 {8 f7 N7 _ C2 |5 O( F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 K2 `$ L1 e$ |6 L% X- lMCASP_RX_MODE_DMA);
! b4 C' L" f2 x2 K( WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 I: P5 L* D9 V6 u+ D) CMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
8 L. S0 `/ O& h! s. X$ HMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - D" w2 t& T4 d) v: z
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);! k9 O; }, u+ W b. P
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 _& Y9 z" G* E; P R& E0 c. ~! {MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */8 f, U+ x$ `3 p1 Q
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& V! o7 j3 u% E0 aMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % m4 h) L# o" l# d4 [ V& S
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 k# z- G3 Y% H8 [' g
0x00, 0xFF); /* configure the clock for transmitter */' `2 x _8 Q6 U3 p# w; P6 z
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
0 p# r' U* L" y; hMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
N# B i% p$ U. y3 S$ BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
* {) x) F% \, M5 E0x00, 0xFF);
- T. ]9 z! p& u) i( j, M( s9 U+ y5 ?* j9 I
/* Enable synchronization of RX and TX sections */
' G' n- X7 p; B+ c6 {! k( d& xMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
9 O% V/ h# V2 `% sMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( Q+ r8 l) f( s. { ]# o' b. [
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
" |/ s! T8 ?' z, n0 r6 b! t** Set the serializers, Currently only one serializer is set as
8 {! \% N# Q( I9 s** transmitter and one serializer as receiver.
; Q5 [# }) B( R0 s' }; X) B*/9 O m4 l! T" \( ^2 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);7 n' x# R) {1 Y F! [/ @1 P: B6 d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 F' Z( q7 A/ d; z3 c- t! e** Configure the McASP pins 4 v( M" r9 i% l/ q% ^4 L
** Input - Frame Sync, Clock and Serializer Rx
+ z P" I" J, W1 J m5 t! f( z8 n8 K** Output - Serializer Tx is connected to the input of the codec
' C" a u( G# R3 D*/
' w& @' r, k+ c! t1 VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);9 b" ?4 [' _, ^4 E, V( X- Z
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));! ^$ m7 I8 r6 j! H% Q0 B/ o
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: L5 ?0 Y" Q) J, r# [| MCASP_PIN_ACLKX C. j5 Z9 k: S- x$ U. C
| MCASP_PIN_AHCLKX
4 g8 b3 s2 B5 X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// G" y3 k. t" D( x! W2 a; b
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 A) @4 P& y" |9 s* Y6 |6 q| MCASP_TX_CLKFAIL + \ C0 J" P L. h' G" j
| MCASP_TX_SYNCERROR
3 Z' {8 n9 p0 u7 h* Q| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
}2 T. t) J6 |+ ~4 y| MCASP_RX_CLKFAIL
: v r0 l* |2 A| MCASP_RX_SYNCERROR
0 T+ w. h4 f* Y4 u1 q| MCASP_RX_OVERRUN);1 l: E& c. G5 V: U# S
} static void I2SDataTxRxActivate(void)' ~& R$ L, o% w4 A- {. k- ^
{$ _* k! l/ j! p: D$ N
/* Start the clocks */
" l8 \1 f0 B1 p4 Q/ m$ u9 S0 u& BMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 A+ X8 l7 i3 Z2 E& H1 yMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */6 i* b0 p% k* l. }
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,. ?2 D! {8 b8 E
EDMA3_TRIG_MODE_EVENT);! \, O9 N2 D6 G6 i. a+ g
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ! M) N! F1 e8 O4 \) p$ }( l6 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
5 q3 V3 i/ X) s/ t2 W" h2 rMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) }* p8 }) F4 f/ k, i2 ]' IMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
: L% `1 r. [. S. {' Ywhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */. W) t7 p9 s* @7 c3 p
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( N% M8 P5 c& v- MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 l- S+ y7 m* T- g# @' o( W
} 3 C" l. @' Q) w
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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