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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,! f. l8 i6 v* A7 Q# ]' ^
input mcasp_ahclkx,+ o" A# `, v# L* {" H* `' v
input mcasp_aclkx,
# k& r( i6 g; xinput axr0," `+ P- c% k# d3 Q# j
O& M& y }( M7 {1 @4 }! @* ^& y
output mcasp_afsr,$ d5 J; P0 U9 y" O
output mcasp_ahclkr, O$ y' L4 M% n' ^* _! j
output mcasp_aclkr,, I/ n( u2 {, U& F' m
output axr1,
) W' o. Y; w. l assign mcasp_afsr = mcasp_afsx;( S [9 n) d0 m# W
assign mcasp_aclkr = mcasp_aclkx;" Z1 [: N* v, w
assign mcasp_ahclkr = mcasp_ahclkx;) U/ X6 c! v/ L
assign axr1 = axr0;
) p( j( c$ C. k! W* z! y, M" l! h
) t9 @1 P# y# l) R% n0 n& K/ W在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
; Y4 T" e1 d9 r) k9 u& x/ j9 _' ostatic void McASPI2SConfigure(void): i4 o+ y4 Y6 z
{* k! h9 M2 d. a1 @
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
& s6 {' O; `7 q& K, D! m4 i$ W* H2 ?McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */4 D1 Y9 Z! p: a" G3 Y" r+ x, O
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
4 Q6 `# E& c' m4 E5 B& qMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
& i- {4 x6 P1 F- H4 v9 @McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: H1 v+ c; M. i' A/ Y# p0 O% QMCASP_RX_MODE_DMA);. b: }- s2 M0 k7 S" v- j* i
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 `* |0 ?- y" c$ X3 x* U3 wMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
7 |. i0 V: L# r# ^ `! CMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
- T8 X+ |, \8 oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
- G) v2 S: ~% e U8 W2 eMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + o1 B# F0 R/ v5 v: P- d3 w9 X) a
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) r j, d8 @% g1 q* c5 M( I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 _# f, |* l# A6 r9 z) WMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
- ]9 ] T9 f- X- h( D( iMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
4 c3 `# v0 T3 ~! w3 X' m; }1 o0x00, 0xFF); /* configure the clock for transmitter */% R% u2 s9 Y" j# \) Z! r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% u v4 n5 l8 w* u
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 f9 v* v0 r8 v; u# JMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; C& }6 P& R. q: F7 T# q% k0x00, 0xFF);
; T( U. v! C0 Q& F s2 S6 m) v$ k) l* Z) J3 x7 T' h1 }' S
/* Enable synchronization of RX and TX sections */ . g+ q- ]: U1 A8 b- h3 W5 {" k c
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
. ~- X2 C* _$ S9 E, g( ~McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 g ?2 L# C3 {# r: @: ^! Y6 h3 `- LMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, w3 }2 P9 L/ B' u. u( R/ M** Set the serializers, Currently only one serializer is set as
9 @5 C- u& x! Y+ f3 ?, I- r** transmitter and one serializer as receiver.0 M7 s) G4 M$ B6 R3 ^, }
*/* v) |3 \3 F( r t( Q
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# U* m1 A& C% B* t" RMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*8 {0 P" m; k B& o$ `: @& S. |
** Configure the McASP pins
( D% V; b$ r( M$ w; I** Input - Frame Sync, Clock and Serializer Rx
' b. I3 q, T0 V% ^5 F** Output - Serializer Tx is connected to the input of the codec % W1 @# z s! S D& }" c& Q! ]2 s
*/! M) B' O7 t" y: ?. a' U9 O+ P9 ?
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
2 |, ^% K8 ?, L# [( a5 MMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
( o( B$ s9 g6 a2 _: ~5 V7 V. j" EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
. \1 j9 |& w( X. G| MCASP_PIN_ACLKX$ E0 J8 m1 h9 F( B% I
| MCASP_PIN_AHCLKX- U4 d% n5 _% r1 S
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */# n2 |3 [) F& ^ p
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
2 E8 E# f9 |- |( Y# t| MCASP_TX_CLKFAIL 4 q8 {' E% M2 ~7 M; y' M8 m
| MCASP_TX_SYNCERROR5 Z7 [' Q: I T+ G$ l& D2 u' m2 C7 U7 V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR : j; F3 _+ U2 N0 c
| MCASP_RX_CLKFAIL
% f* |1 a4 q7 Z0 W* c| MCASP_RX_SYNCERROR 4 W( h( Q* Y4 A5 s- g! X. j* ^. h; X$ v
| MCASP_RX_OVERRUN);
+ d* \/ A. I5 e% ^} static void I2SDataTxRxActivate(void)9 s$ [9 m* |) M( n0 l4 q
{
! a8 Q8 U+ u) s3 q( Z/* Start the clocks */
( M6 H) A+ j' ]) l2 W% H: D( X* m! U& ^McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( q4 l1 e2 s1 b/ ~McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
5 E- a' {( N/ u& ^* _% e% {4 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," O! A* _' w/ V' \8 v
EDMA3_TRIG_MODE_EVENT);2 }6 }% q8 v$ c/ \ r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 b# x) [& x3 q( _: \3 a7 qEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */3 o1 {. U# i1 g9 ^$ h9 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
2 @8 O* c0 `1 tMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
0 I" O8 S1 m; C# o3 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */, p" ~& A0 v% T! |0 ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);: [- J; z. f. J
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% O, Y: Q/ Q! A9 Q9 E2 w; N0 r} 2 w/ A, [2 K) ]0 ^9 |
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 6 t& l5 E1 X# I- W& \/ L
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