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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,/ Q4 X# U: d, X/ A' R
input mcasp_ahclkx,
% b( ^; }0 j. O z Ninput mcasp_aclkx,, y" W3 y7 G; r$ F2 f0 ^
input axr0,
0 Q ?8 M6 H) f; f' g
- [7 v- ?, G/ [- doutput mcasp_afsr,& b7 N2 b+ M: A' Z6 D/ X/ Q
output mcasp_ahclkr,) L4 }: X) j J- {4 m2 {
output mcasp_aclkr,. D2 a3 J5 R5 U6 U
output axr1,, d( w8 ?9 q* ], _/ G; B4 M3 r
assign mcasp_afsr = mcasp_afsx;
: N& y; P, q- B1 W) q" T+ r* q% Xassign mcasp_aclkr = mcasp_aclkx;# v: p( x% ?1 ?0 D: y+ G0 k$ e9 W
assign mcasp_ahclkr = mcasp_ahclkx;9 [4 I4 @9 Z1 R
assign axr1 = axr0;
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4 d# Q$ z7 |! r/ T0 n在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 / f F6 Z- `+ u/ h
static void McASPI2SConfigure(void)9 f J9 e# S" G C7 c+ d4 D
{' C& y/ F `3 S8 S" \) l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 y! t+ b1 m* m: T! w9 Z9 J! f
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */ q* L& H) V% ^8 Z* r9 S4 s
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
|) ^9 I1 A: F: ^& Q+ BMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ h* r9 |6 w/ N4 L/ f0 e2 ~( i# Z3 c( kMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,2 o, c+ w X0 a* e4 g5 E
MCASP_RX_MODE_DMA);1 v0 i9 U( z) _& m/ F' g9 k
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 ~* B( w/ A& z: Q \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */, e" S9 P& G3 H1 g( Q# ]% C( i# Y
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 9 e4 x3 A! d! [# A. i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
0 Y# y9 i3 T" f. q) I/ G2 pMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 R( [+ p3 s& \' |# Z: tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
. k( f! V* o6 Y& b$ J. ^McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);6 H0 b) o; M# i, \& S7 F6 U- w
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
$ X! b! a4 h/ f! h) GMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 z% n3 @/ ]5 ~% y8 y5 I5 Y8 V0x00, 0xFF); /* configure the clock for transmitter */* Q( I4 y3 Q' r/ ^( h- b% ?
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ O% f% |0 C5 z8 I
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
" m) I8 a& C2 qMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 m6 m1 T2 J2 j1 p5 r8 T+ ?
0x00, 0xFF);
) f, K3 |" L+ H' F$ {' i. ]1 h1 E( N: W9 ~7 X! L q) {, d+ r
/* Enable synchronization of RX and TX sections */ 7 P* e6 A& D. D. e
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
S* a+ Z. t) Z1 KMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 o) `& Q/ V1 H3 M6 [McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*( d% l2 Z7 s s, L
** Set the serializers, Currently only one serializer is set as2 Y q, g* ~, Q
** transmitter and one serializer as receiver.( i+ Q1 _4 ^8 L0 [* m8 G
*/
9 c- p2 U, h7 l2 ZMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
/ J: o( Z# F" s4 A! E+ y. _& g" uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
) D" X' Q- ~+ ?, [9 |** Configure the McASP pins
4 g) f( q3 M% s2 X( I o5 T** Input - Frame Sync, Clock and Serializer Rx- @$ g3 C7 N# c8 |& k
** Output - Serializer Tx is connected to the input of the codec % p0 @8 e# A) ]7 t+ K' L$ ~8 m
*/# _+ E7 F* m. U5 G5 \
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# { z; @ Z3 D5 r6 ?" ?3 l
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
: L7 o: E7 C5 l6 {& v0 d) H2 v. rMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 |, ?% i3 {1 q5 R| MCASP_PIN_ACLKX% A' E, _8 R U
| MCASP_PIN_AHCLKX+ Y$ h9 _+ r& k8 W, d
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 R! @+ L; ?0 T# K2 dMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR $ k: t# C6 T+ V6 l
| MCASP_TX_CLKFAIL
$ r/ G/ e0 }- a5 {$ b. O2 b8 I| MCASP_TX_SYNCERROR
( d* J0 }, [; z# l+ L; ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR . }% W! y/ H6 J+ l4 K2 J+ L% i# w
| MCASP_RX_CLKFAIL
8 U9 `0 s) }3 i' t$ ]| MCASP_RX_SYNCERROR
' L* r$ f3 F( n7 A" [- {5 D' d& l. Z| MCASP_RX_OVERRUN);# R0 i/ ^5 d9 i& g
} static void I2SDataTxRxActivate(void)7 x, Q/ G: b. n* E( c$ ~
{& s+ A) e9 Z/ l5 g4 }) l. i
/* Start the clocks */" o# @+ Y' c. q% O- w# _
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 d& N* P$ u2 F" e! Z( G0 @McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
) e1 @$ @( c4 J1 L2 g- M8 uEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
/ {9 P0 N: p; e3 s, qEDMA3_TRIG_MODE_EVENT);
& J- j# H% W, \, Q8 ? a' G1 KEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 a: ^: x7 z, G% UEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
" P) _5 m6 U6 o5 R8 n) F# n" oMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
4 [" N, V$ m) e4 jMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 q$ y6 K2 E( l6 Q$ Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" Y& j5 \. @% ~) L) m3 WMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);+ u* d$ [3 R; b8 g
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) H i" C$ B, d) Z* T; C( G3 a# I} # d" |! \6 k* w4 _7 B: _! J
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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