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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,. O1 d% R+ i. P
input mcasp_ahclkx,1 d* R# }5 }8 b6 ~- n
input mcasp_aclkx,5 X9 J+ n7 }4 i S; F# i) f% N( m
input axr0,
2 U* ]; b% Y. r1 |7 d
6 Z& U8 J2 X$ P3 C- \8 A# Xoutput mcasp_afsr, J7 |' R P& t# E- c$ h2 A
output mcasp_ahclkr,# F4 {4 ?- b8 b* L; C# d# k
output mcasp_aclkr,& j; I$ R* C9 ~% W# F
output axr1,
9 K# f! A9 P# p5 U& s assign mcasp_afsr = mcasp_afsx;. n0 U( r+ I1 t8 ~
assign mcasp_aclkr = mcasp_aclkx;
# }# o9 k( @! U: `assign mcasp_ahclkr = mcasp_ahclkx;% a# g3 _- Q, K0 X/ Q! h& W. _
assign axr1 = axr0; + q6 {. S: h! {8 W
. `4 _* D8 ]! ~ `! |! u& a1 H在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
}, G& e. v4 y1 a! h r3 bstatic void McASPI2SConfigure(void)
% c# b: v# t3 E' h{! i$ v% R/ o+ ]9 h r# I/ i, t1 x
McASPRxReset(SOC_MCASP_0_CTRL_REGS);0 p! e5 x# j7 Z6 W# X
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */, a. `4 l! q0 W% V; g3 }
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( k' q8 j2 M, u
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */6 n9 y3 n" g U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,: M. f, r8 [% |* ?/ x( n
MCASP_RX_MODE_DMA);
) W9 [$ g3 X5 P& _ bMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! I5 c- E6 i5 d3 U7 q1 \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
+ A# r% i* N8 L. Y( cMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
; Y/ K- G6 P3 B8 {' E1 JMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 Y2 z( X( `7 |: ]& @McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
2 R. X: F6 a; G7 ~5 @, _; zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
$ `; B3 u: }) O. |# e# v; ?McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
& S: J- {4 D( M7 I6 @8 AMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); % w- K. w( h& A/ J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
L, M( @3 M4 o( Z! W0x00, 0xFF); /* configure the clock for transmitter */ C' p1 Q% b2 @/ p
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1); b5 x- U; g% d1 s# m
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
; P4 F7 i( K/ Q2 n6 f% dMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 ]. b. s$ {) p! S
0x00, 0xFF);# }# |0 C+ v+ G( }1 |, t1 H% x7 u' m
' g$ @7 g6 X! j
/* Enable synchronization of RX and TX sections */
4 X$ X# \: `7 }+ x YMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
& u8 G9 |2 ?$ a3 jMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; ?& f( c" T2 n0 }8 R
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
, x; P" R q: E' M" W" ^; q; |** Set the serializers, Currently only one serializer is set as
$ H: M3 p/ E: L0 a& v( j0 O** transmitter and one serializer as receiver.
3 Q2 G* C! v! T*/0 N: H: f2 F8 Z" L; C+ i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);- I, c f" k3 j
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
. K T' X5 \4 c% d, g** Configure the McASP pins
: F# l% T; }7 @* F: H1 h** Input - Frame Sync, Clock and Serializer Rx
; Q+ A: y9 k- M. T/ l' Q! U4 U0 N** Output - Serializer Tx is connected to the input of the codec
. D, B: T: b& d$ b*/
0 a4 b: S9 b+ G* {6 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" g- I) c* w# k7 A
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));7 K) o/ U6 V* p7 _* M4 R
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
; B" }0 O" x; w| MCASP_PIN_ACLKX
0 Q& W# D! B' Y- c i$ H$ A| MCASP_PIN_AHCLKX
& W: P+ y$ r% Q) g8 \| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
: A2 \4 |4 }% ^; L: `3 z: wMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ ]$ m1 K2 R$ E9 C" ^; b; O| MCASP_TX_CLKFAIL 8 x2 j z+ ?/ g2 l% ]- D j0 v
| MCASP_TX_SYNCERROR5 R& }" ]* M6 [
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
. ^( h8 O! m6 F6 |% N| MCASP_RX_CLKFAIL
& n* v! F0 K& Z& H6 r| MCASP_RX_SYNCERROR ! A: x+ [/ {5 V/ k9 o) f
| MCASP_RX_OVERRUN);: P1 D4 b: w8 N
} static void I2SDataTxRxActivate(void), k4 u/ R$ d& I; `" E- S* \1 n7 w L
{
' s* g3 |3 Z8 N2 J$ o/ J5 q: D/* Start the clocks */
. g2 j0 H/ d9 f3 f; MMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 L2 Y4 n' t1 A% S- |/ |5 o7 iMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */. V5 Y6 w2 U# ^
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 \2 V) o9 J: M6 Q
EDMA3_TRIG_MODE_EVENT);. B$ h& s- `1 y% _, K0 G4 X
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" N- P ^+ T D' o% h7 iEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ @$ Z J+ g8 r6 w0 e4 P% KMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
& X9 ?, W. J% `# U. x2 m) n! T( d5 D% WMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */# E* t S4 b2 Q' R8 ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
5 P( c* z$ `5 }$ `, o) Z" j) e- BMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 S) @, A! L9 f: n" GMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);" Q) g& y% t- B( Y
}
; t+ t R6 c3 s7 i p请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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