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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
7 m0 p" Z+ B) Y9 p* R6 c( Einput mcasp_ahclkx,
. V* @% J0 I& m# u$ }) |7 {7 ?0 H0 hinput mcasp_aclkx,
5 u: r% q W, F7 L' winput axr0,
w! E( N9 Q' {' f+ R3 F. y3 g6 @+ W, i" b6 C2 w
output mcasp_afsr,
# }3 k4 ]# N- _# voutput mcasp_ahclkr,% Q8 ` H0 x( f3 h& _2 m5 Z
output mcasp_aclkr,
+ R% [. [ u( {& B& Soutput axr1,- V* J7 t1 ]* O6 G+ y
assign mcasp_afsr = mcasp_afsx;
/ H5 }: {& ~& ], f& v4 _! ~2 oassign mcasp_aclkr = mcasp_aclkx;
" Y9 b% V7 P1 G% c" C2 dassign mcasp_ahclkr = mcasp_ahclkx;
0 `# Z! Z8 [4 g. S( M( R ~assign axr1 = axr0;
; K# I+ o0 ?4 j' J9 ^' j1 ~6 a5 P& u" |( ?8 j7 Q
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & o2 W, {' c1 H: G. e
static void McASPI2SConfigure(void)5 }& M# }6 k7 M# V1 c/ i
{
: m$ k; y% t' x: ]. Z5 d5 `- S% x g% AMcASPRxReset(SOC_MCASP_0_CTRL_REGS);, |( _0 t' j7 g8 F* e0 J1 C2 j
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
+ P3 D, J+ Y( j7 j+ r5 _7 z$ u7 d5 d, FMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
# I" e# D/ Y; ~5 M1 [% ]McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ S9 C& M; ~1 N$ f: d& `McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* F' o( b# b: @' `' K2 C
MCASP_RX_MODE_DMA);) z$ Q9 s# e6 h! U
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
$ y* D( ~; m* y& K, tMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
5 C5 q* i' ~! r: J7 f( XMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, e5 ^2 _: @9 i& F- O/ {
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
2 Z4 E. D6 |2 L( [0 ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* @' ~( f* U! U( @1 H% |, N; hMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 Q7 T5 A% q2 b* bMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
0 A! x a6 X4 x0 k! ~McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
2 d$ m; L# Q+ d7 |# jMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
3 G. I- T; k$ T0x00, 0xFF); /* configure the clock for transmitter */
, ?' K" v0 r' cMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);7 k, u( o$ t4 Z& N
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
$ @+ _. b$ D) O/ p( R1 G4 bMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. u( m8 Q0 [7 f4 \3 u2 o# j2 D, T
0x00, 0xFF);
9 E3 r; ?& c1 W# r7 L) H! a
* W8 ~1 l0 j; N* X6 L/* Enable synchronization of RX and TX sections */ 7 t6 J" q, t( D; R+ y
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */; @( y S$ u; N! o6 G3 O# K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* k9 `% y+ s- e* |+ D" ~
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*+ i! G: L7 r. e
** Set the serializers, Currently only one serializer is set as
, f8 |+ I/ s- i4 ?2 k+ S9 u** transmitter and one serializer as receiver.2 o0 C9 K8 l$ `* o( [0 A Q |; c
*/
& `/ j$ J4 d& u, eMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( L5 B; K1 c" b; f# U1 W1 uMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /* ^, }0 K2 i! ~* p2 o
** Configure the McASP pins
- Y/ \) Y9 Z1 c% _5 x7 ~** Input - Frame Sync, Clock and Serializer Rx# t/ r/ m! c& O& X- j
** Output - Serializer Tx is connected to the input of the codec ! Y' e5 b# b0 Y$ O
*/
: h1 Q, J( U& ?3 t$ nMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
$ D8 I+ R5 W* b' A4 J" [ wMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
) ^3 l' s0 x) K; `& D' b9 _McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX* s; Z8 @7 [: @+ R: B
| MCASP_PIN_ACLKX
$ \7 m( d3 k# e O1 {3 V: C# D8 m| MCASP_PIN_AHCLKX) a! ^: q4 O8 I9 r, g9 y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
. Q: w4 E) _ `0 bMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & f( U6 P5 k3 r! z$ Q" a: ^7 }
| MCASP_TX_CLKFAIL
4 g- c& N# r1 L# E| MCASP_TX_SYNCERROR
, b, y' B' V* x4 e$ C/ n| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: q6 M, v' G3 q# e& u2 X| MCASP_RX_CLKFAIL
& c6 j6 U* F5 a' c% n| MCASP_RX_SYNCERROR
8 l) D, W' o; `" `- G$ c3 x$ n* w: j8 d| MCASP_RX_OVERRUN);
+ y9 L% _; z% ^! \8 P! ~4 K9 @/ {* c1 N} static void I2SDataTxRxActivate(void) Q) h* h/ s5 G4 m2 C
{; g, p0 i) K, z% L. t
/* Start the clocks */
' _ ]/ }# p' K& JMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
5 a5 |' D2 v- C5 {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */: w& y/ V% Q- j# l9 B
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,+ y% C) m! O) w7 o8 S3 U0 O: \7 F
EDMA3_TRIG_MODE_EVENT);, A* n/ B& t# S8 l2 _* M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
$ h( a* s4 x; n# pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ k5 k+ H& N& u+ VMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);* Z( ~3 T( S/ f/ `
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* _) r) Z0 V' Y J
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
0 v |; r: V% d3 J6 ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
$ w a& z& J4 R' MMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) D4 e7 F/ z k- x1 e
}
+ a+ H X' ]$ v5 N9 A/ B请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
1 k' j# r' `" k5 B+ r) F |