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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' \ V8 }! W9 u
input mcasp_ahclkx," n& _1 K& x3 _1 ?3 C$ \! N
input mcasp_aclkx,3 I( R7 w$ X8 m
input axr0,& N9 a) A! A3 x5 k3 e& _) ?! X
2 L" h! H4 c& ?) ?
output mcasp_afsr,
1 w8 Q# Z# F" k( Houtput mcasp_ahclkr,4 {+ K; s2 W# _ r: n
output mcasp_aclkr,
7 A& N. N$ r) t" b7 s; O% @output axr1,7 }" X# M% W( G( `2 u) H
assign mcasp_afsr = mcasp_afsx;6 k( }$ \) J- u2 q+ y& Y: n% h
assign mcasp_aclkr = mcasp_aclkx;# _2 z% D$ f% V- Z
assign mcasp_ahclkr = mcasp_ahclkx;
/ ?- y' e H1 Z& e& a; Bassign axr1 = axr0;
5 m( [% J$ K) I7 u
* y' R5 j2 L; w: f0 O: S# \在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 @/ d$ B* i3 ^' d) bstatic void McASPI2SConfigure(void)
) k" V4 A2 f! u' j8 i' o5 s( _2 n{
. Z; K7 x: o. lMcASPRxReset(SOC_MCASP_0_CTRL_REGS);) ?5 w5 `6 U# m; Z' A2 n6 m
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& P. N' V( a1 f9 C# F8 YMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
5 y8 ^( {& |# r& S( _McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
+ P: @* \4 q( o0 CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 g( E( |* x3 Y& O7 @( uMCASP_RX_MODE_DMA);
2 h h+ E: R! u$ D8 _( ZMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 c& q& u; R1 D: ~1 H3 R8 p
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: }0 }. F0 K2 `( n& V2 Z
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. L$ V, S/ h( S" I0 B" m1 c# oMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
: q' J8 O1 q( }! q2 ~( @' F( ~McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, % f* N3 d: S6 O. C
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ ~7 Z9 V1 Q' K! R6 G: `8 Y' k; d( J I
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
3 Q: y, \' s0 W( S( {+ RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
' t, k4 N8 e" q1 y( g1 _McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
: j# U% I! |. @1 a, Z, a* ?0x00, 0xFF); /* configure the clock for transmitter */
) f7 ]5 c( y, q5 v& G& _) o% qMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% ~/ K9 p' ^. v4 q% k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
( f, c0 i- j& F8 J) O1 cMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( o. e/ m3 C- S& t' n0x00, 0xFF);7 ], d1 T: T6 g; {: o9 O
' _) [+ v+ i( U! u
/* Enable synchronization of RX and TX sections */ ) v0 T Y& B* k
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */, `* y# Z" W( X$ u! ?/ P8 R
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- t: z% d, ?) C5 G+ L. VMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /* h. D" x& H% R/ Q/ i
** Set the serializers, Currently only one serializer is set as0 q8 L2 V, h% o
** transmitter and one serializer as receiver.. u; x+ f' i9 ?2 W
*/5 |4 p m1 I. [; x
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
8 o' l e2 P+ \5 q. W- MMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 e' E6 x, a: P: t$ T: k** Configure the McASP pins
& V7 @% F1 A% ~+ M& w** Input - Frame Sync, Clock and Serializer Rx
' N5 G8 V7 i; j5 M* u" k** Output - Serializer Tx is connected to the input of the codec ' K. L- E1 F& f G; j! c$ y
*/$ J2 k7 u5 \, m! _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
5 U& a. W3 @5 B" E) IMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));+ ~( }1 q& I' j3 c7 s
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
0 n E' y" I. @3 e; Z% U; P- y2 V| MCASP_PIN_ACLKX
# T5 O7 O: }. ]9 m| MCASP_PIN_AHCLKX
0 o+ A4 p1 k; W| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 D$ @! v6 c' h NMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR & z$ b Q% v( {( c* F$ Z9 Z
| MCASP_TX_CLKFAIL
* h1 p* j/ z& u! g r3 o| MCASP_TX_SYNCERROR
) |: f( w; s* ]8 `* m1 }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; b8 f2 ~1 I3 z8 {
| MCASP_RX_CLKFAIL$ l1 L) G" H0 s% p
| MCASP_RX_SYNCERROR
7 P. E3 J @9 K4 O9 ?8 D| MCASP_RX_OVERRUN);
- m6 `3 g4 L: h, C+ ^7 r. y1 P} static void I2SDataTxRxActivate(void)
. s9 Z. Z% }+ R8 w5 l" V6 |3 P{4 |; Y' C- V; v+ x2 X2 ]
/* Start the clocks */
4 U Q7 B# \. h5 G% I+ u+ {" i5 ?: nMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
( n4 t6 U) R1 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) o6 q3 \9 ]" s c; }! O2 |% n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 T' P e8 A, H4 p- ]EDMA3_TRIG_MODE_EVENT);& T R/ q4 D1 S+ Q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, % }' V# c# ^0 F0 J' l
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
2 Q2 i5 I- j( \0 R% m: |% hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);! ~! A# r; F0 x' P* g( h
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */6 O& h1 c B N9 h0 b
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */" S% P; D! r8 _, l, ?, L
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);9 b' i# P3 B: L1 \ e
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);( O. \6 c5 e% X4 R; p4 Y
} 3 M) L& u- ?% H
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) Q1 J: L& L& d
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