|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,1 A8 y9 O/ z/ @- p+ D( D; V9 g- T
input mcasp_ahclkx,
; V1 |3 w- e& H2 _. B- iinput mcasp_aclkx,& M q% S2 _6 a f6 P
input axr0,
+ Z% S |: h; i+ I, R1 f6 y7 @6 e. R4 J- v2 `0 Q" L) C4 p
output mcasp_afsr,
e' j/ \+ Y: ]. Q) K- Joutput mcasp_ahclkr,
) F# s- H- @! b: o# K3 S. loutput mcasp_aclkr,8 E" f. Q+ k$ b) i/ P) F
output axr1,* d( B! a7 o8 |) J5 u& f1 \, w) I
assign mcasp_afsr = mcasp_afsx;) B! U% F0 d1 c6 g, F: {4 N9 i
assign mcasp_aclkr = mcasp_aclkx;
" g; M( j* m2 w- lassign mcasp_ahclkr = mcasp_ahclkx;7 Q) U+ i# C l5 ^3 I x, _
assign axr1 = axr0; - w( F- O9 {3 b8 P9 J% V
, j' ~7 o2 c6 Z2 D1 O: V
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " _8 s; k1 X& F6 b- Z4 g6 d
static void McASPI2SConfigure(void)' \$ ^6 C: Z- [ K
{' V; b$ R7 x; \. Z$ J0 h
McASPRxReset(SOC_MCASP_0_CTRL_REGS);4 n9 S R, u4 Z/ r6 G6 L$ W8 I
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 q; g' T9 _- h" p
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% M5 y2 o( U4 `4 ~McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
$ l" z1 f! H. J6 k. BMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( f# ~ j6 {' JMCASP_RX_MODE_DMA);8 N3 k# J# d/ h1 m
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; d% d8 W- v+ h0 n) I. W
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */: d* Y1 [- i* b6 w
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
' N. X* M# U z& F9 S* TMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);% ]+ o2 Y# T g* B) M
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + C* M4 U0 _( ` Y# F6 _! n
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */ u" ~- l6 c# o# ^+ ]( p1 Y7 B9 b
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);" x- y8 `5 C& T0 a/ J# w, a, N
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 c5 P9 S7 o5 g" }4 ^( }" l0 ~McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* x }7 d: b1 u5 ^ }
0x00, 0xFF); /* configure the clock for transmitter */
# P$ F$ ~: K- @6 E" w2 K6 E6 J7 V! g3 ]0 zMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ J( r5 z/ m! `; l0 pMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; G& g% P2 z7 M$ a9 s2 W
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,2 P& ~- s% ^" B& f4 ~; {# a
0x00, 0xFF);! Y% n' T6 F+ m5 C6 l1 R
! \/ Q" o: u0 i1 B9 W" o- r
/* Enable synchronization of RX and TX sections */ 1 O9 V, {1 A- \9 ^& I; ?
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */9 o: r6 X+ g2 a# a; `' x
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);; e3 s) ?/ S; A1 A. c: E$ u
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; g) t/ p( G! c W" b2 v% m
** Set the serializers, Currently only one serializer is set as
) i+ k! M* q9 ] D; z** transmitter and one serializer as receiver.5 g; n [* E F) `, x. n b& G$ m
*/
) Q% z8 X: D$ ~$ r- W. ^: o6 YMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);' Y8 `/ q3 w+ G1 H) @5 D$ }4 n) c
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
% ` N, U" d% e' S5 f5 c* x4 P9 ?** Configure the McASP pins
. ~6 @$ x7 P6 C/ q. m** Input - Frame Sync, Clock and Serializer Rx* D9 e t/ ]4 l8 v+ d1 a% j
** Output - Serializer Tx is connected to the input of the codec $ A" r, |# D: _
*/
! F ?5 g6 `! j" R) Q3 M, `McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);/ T5 D, M+ A1 ^. y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. A2 ]% d6 l' z; c1 {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# I2 ]4 S+ r1 w, w: O| MCASP_PIN_ACLKX- o U: G: }+ G5 {0 c
| MCASP_PIN_AHCLKX
3 C2 g1 p5 U) E8 Q| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */6 k0 q- \% |5 i: s. s: L
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ) _: p5 p8 R: i5 x- u
| MCASP_TX_CLKFAIL / H! y/ v j, P9 A* v0 R# C
| MCASP_TX_SYNCERROR. M* u$ z2 V6 \! `% Y3 u
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
6 P+ N0 m; L5 a, O6 S- F0 w| MCASP_RX_CLKFAIL
: K8 _# |) J/ c/ Q% S| MCASP_RX_SYNCERROR $ E1 m) K+ G6 O
| MCASP_RX_OVERRUN);
5 `$ c v: z" g9 d" V- _6 w: x1 I} static void I2SDataTxRxActivate(void); P. ]% K4 g: y
{
/ y% A' A# f3 Y2 a5 z' Z/* Start the clocks */8 ~% |; f0 l! ]! {$ s+ s
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; |) f+ Y( m6 {9 `( CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ K$ S8 Q& G3 x& pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: h, ?2 J" i2 r' F" M; e
EDMA3_TRIG_MODE_EVENT);
+ p7 x$ a- b) o& U( C0 ]EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
3 v; g# K/ v1 D' ]EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */9 G6 q9 P2 f- I( D: I3 |
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 f0 O6 b, M$ c" X* \7 |: B* kMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
% }$ ]% g1 L1 {% ]+ Wwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
* _4 n- M6 D- K. xMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);, l" V5 Q! E# p6 ?" f d4 [
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
) f3 r4 V9 H# W2 O; g} - k/ E; Q* v* g1 L
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
" p5 D/ p0 X2 s6 J |