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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
- `) z! r* V$ f! d+ j0 e* Tinput mcasp_ahclkx,
# k7 H7 K0 f& |2 l) y$ kinput mcasp_aclkx,2 ?* d/ N0 u* f- _' A8 i% P8 ]$ x
input axr0,
! i8 w3 S' p% |8 p% _0 S8 o6 x1 R9 ^: ^
output mcasp_afsr,6 Q0 o! v# Z. I9 x" G
output mcasp_ahclkr,
: {4 I* J% ^. x! J9 i) v1 d+ u! ?output mcasp_aclkr,
1 j: X6 C% m- I3 E* p7 x; B# ?output axr1,, j& \ p/ o$ `3 t4 o$ O
assign mcasp_afsr = mcasp_afsx;
B% |/ z2 `7 I0 }2 bassign mcasp_aclkr = mcasp_aclkx;1 _9 X6 _! E- j' \
assign mcasp_ahclkr = mcasp_ahclkx;! k2 H5 `+ Z2 I- ~
assign axr1 = axr0; 3 A: ]" Y4 [! W! f; M
9 X- z; O: ]9 t1 Y6 t9 M( z
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 U/ l3 }0 x. G0 s3 \0 y+ v
static void McASPI2SConfigure(void)
" \. `/ e! y/ X- [9 D. P{* m( z- ?. I4 o d; Q* \
McASPRxReset(SOC_MCASP_0_CTRL_REGS);% f5 N5 `; f( u/ R! m c9 y
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' G5 }, W: N$ @$ x3 f- ^8 bMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);8 l! \9 ^, ?( o" @+ f
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
{7 S5 p- D; [: E, w; dMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! {' h2 e U: b1 N' g+ ~MCASP_RX_MODE_DMA);( V- |5 b) E" j" ?4 @
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,* D/ ?1 f5 z. T2 U7 F: V' t& {
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
* {: ?! Y( `, G9 J- yMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 6 r1 M2 l! {1 g1 _) G+ i
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
& G5 H' _4 k/ M% bMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 8 i- D1 j4 F$ c6 H
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: K e4 @4 w* x( [
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ _5 p, u/ R/ a$ M1 A0 a1 p, S
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 7 w7 Z) o/ M8 D% H
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,6 ]+ {9 N4 @8 G1 r( _
0x00, 0xFF); /* configure the clock for transmitter */
8 g4 ~8 y7 ~0 n; `McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
3 w, s# r+ k3 s( p+ | V+ j1 l5 ^5 MMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) r t8 k% _7 p# O9 b. w% c+ uMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,+ A3 Z- `; b/ O5 r. ^1 X& C
0x00, 0xFF);' q% Y, d% r( `# f
& Z. K% _' x) ~. ^$ Q6 d! C$ }1 L4 B
/* Enable synchronization of RX and TX sections */ . C* W8 K/ g" }0 y7 x
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 i- z* Y7 X" L i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
2 J k7 L/ X$ v' p0 v# U& N TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" N" d& w, }* v' t
** Set the serializers, Currently only one serializer is set as
7 a4 }) r0 v4 S+ d1 Q6 T, {** transmitter and one serializer as receiver.
3 g9 @# e/ ]: q; c4 i+ _*/! C3 x, |. L, x r' V1 G2 w3 o5 R) V! v
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);% }' X) g. R7 ~& V
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*9 g) h6 s& B5 Q4 ^1 k; {9 r
** Configure the McASP pins
" R# x8 Y& c" m0 _** Input - Frame Sync, Clock and Serializer Rx9 V8 t# o$ n4 K
** Output - Serializer Tx is connected to the input of the codec
! P6 j9 U1 E/ d- v" c3 _: k*/
) o5 x: W( U% `: Z0 sMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);2 _! \4 j2 `7 G1 j3 N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% Y- L% [/ M& v X& _& Q3 a CMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: L- q2 p! M; o| MCASP_PIN_ACLKX
" W8 {) G% v% ~# X| MCASP_PIN_AHCLKX% e9 Q% O6 C6 U) s5 l, j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* a. q/ \; z) F! ?* K- U
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 2 H: l/ g1 o; ]/ H" @
| MCASP_TX_CLKFAIL
c7 C. t& D6 K6 x9 \; k3 K| MCASP_TX_SYNCERROR
5 [; e' V1 Y$ o5 j/ d( O1 m| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
: a: f* U1 B4 ?| MCASP_RX_CLKFAIL
4 A& p3 G3 F* w| MCASP_RX_SYNCERROR , D# V- I6 \5 K! Y8 Z. d9 H
| MCASP_RX_OVERRUN);4 ~* u, s" K: x2 @7 q4 C
} static void I2SDataTxRxActivate(void)1 }$ M% G0 |+ I
{" u. }$ t7 n- m( K" h W4 l
/* Start the clocks */
5 ^; u; j8 W% l9 v6 w+ {5 }* J3 aMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; w, ?; R' O9 o: P3 D- ^/ K+ e
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */% A- Y, T0 a) n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: {; } W* D9 Y4 KEDMA3_TRIG_MODE_EVENT);/ ]% u6 X! h/ M
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ) g6 z& B* c6 T( Q) \4 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */ f( o5 ]( u3 e+ R! J S- D- G& }
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 Y2 G! {0 E% k+ S- \McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
" _: U& ^, V% N; @' T7 Jwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; D& z: [- q! b9 T" j
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);( l7 Q" |# H6 R/ g" [( m* F
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
+ B/ O* A( W7 P. `# ?9 Z; z* Q}
$ Y) b1 A9 {0 z. S( r请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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