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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx, n% Y+ h3 O4 f! D
input mcasp_ahclkx,4 t O# A* p8 z) Z% F8 ]
input mcasp_aclkx,& Y$ F S/ Y) o6 y+ }! h+ d. q
input axr0,
' R* G) D/ C2 X) j+ l0 l
! S. ?% ?) s A5 r' Zoutput mcasp_afsr,7 Z% f+ W( L+ \
output mcasp_ahclkr,
9 O; H/ k3 R/ I& N; y( i( ]output mcasp_aclkr,
( W( S" m/ b" X- p5 foutput axr1,
- S( c& G5 q P3 b assign mcasp_afsr = mcasp_afsx;
# C5 s) \5 J% l7 u! Rassign mcasp_aclkr = mcasp_aclkx;3 \! d) `' h+ b5 d3 d0 L
assign mcasp_ahclkr = mcasp_ahclkx;
5 ]' H& `7 h9 s% Kassign axr1 = axr0; 9 v/ K4 J( Z5 J3 ]' B( p, } P
$ ~6 b2 ~; c7 m# U7 |; c
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 U$ x# D6 s; S, P u, W! D6 pstatic void McASPI2SConfigure(void)& d" D& s5 Q1 I* w
{
/ U% Q7 Y1 L* R j7 s. tMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
. G3 t0 J: c& C) Q3 w& ]McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */1 C% A2 N) Q9 c/ m* A' ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 m" @* N: v2 m# g P
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
' ?$ j5 I6 Z; v! J0 }4 JMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
, g# F5 H7 Y+ v+ N& wMCASP_RX_MODE_DMA);
2 l6 P; E+ G2 z' `: f- {McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," P" i7 s$ L2 `- {! b& y4 ?
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: U" s+ \/ T7 LMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, $ P2 O5 m# u# W" b
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
# \- P3 s5 k% G8 Q% ^McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
4 L9 W; @! e1 K$ _! zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& m' D# [/ A Q+ v2 M& W, d% {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);* \0 V8 X1 M# w! }7 C
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 8 z1 G7 l' Q3 I, R7 ?5 `; h9 v. I
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,* C. L$ U6 \ b: G
0x00, 0xFF); /* configure the clock for transmitter */
! F2 W8 p# b! J. |McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
$ ?9 n: g4 @$ A( j7 vMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ; O5 z* H6 Z5 w4 `6 t3 P$ G/ P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 J0 l# Y- x& e6 B# `& ?# ]% g8 N' f0x00, 0xFF);
& k* c7 ^5 X( Z- F- X& P( F2 K, i. O2 ^
/* Enable synchronization of RX and TX sections */
5 p1 S1 L4 q( Q# f2 S( t; G2 aMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */. V- p5 M- K4 ~% t, g- i
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* D4 q* b) T) w; Z6 z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*3 ^/ l ^. l Z3 P8 |7 _
** Set the serializers, Currently only one serializer is set as( |$ `) K8 Q; c4 a+ |
** transmitter and one serializer as receiver.
! e, M, F- Q$ S9 m( e7 D- S*/
) R' c8 O: E; G4 v ?McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) t' c5 }' c0 r8 ? B
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*1 x: z. ~: R* e6 s: [1 r
** Configure the McASP pins
' H( @( k5 d9 }% b4 x5 _** Input - Frame Sync, Clock and Serializer Rx1 B* o' q% c, Z. d1 g* A( j4 c
** Output - Serializer Tx is connected to the input of the codec
6 j' d( k$ [' K0 I# Y0 i*/
8 n7 q2 m+ [6 `3 Y/ G# ^& r$ rMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- b |* g4 `+ H
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 V* p4 O% c7 }, Q1 p. A7 G/ {McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
: y% X0 G0 ~7 a$ O$ @| MCASP_PIN_ACLKX
' Q; C1 D4 V2 y( s b| MCASP_PIN_AHCLKX
! s+ X) }$ Q0 O X| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */7 W2 [% {. @3 r7 k5 B! `- n; g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' k4 B" `$ L- L| MCASP_TX_CLKFAIL ) ]# B: d1 b- {7 J1 T0 B
| MCASP_TX_SYNCERROR! [! O: f9 o/ W& K
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( }/ m5 L- z, n: F* i R; u| MCASP_RX_CLKFAIL J# [( C/ l/ {; d1 V0 w; S7 \0 X
| MCASP_RX_SYNCERROR 2 _" x5 K( N) k8 n! d3 h
| MCASP_RX_OVERRUN);2 |6 T w2 o/ a6 N# s5 i& Y) H3 d
} static void I2SDataTxRxActivate(void)
, Q! ?* c; Q! p: K1 t. Q! L{
b, V; ^' I# l/ }/* Start the clocks */
% k/ R& Q' Z3 R2 {4 n* S: oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);8 ~ Y9 B! A) H6 X5 h7 O. M
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer *// f$ a# b* V E9 `8 B7 A/ C
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,6 ?6 l* A9 k: ~: h
EDMA3_TRIG_MODE_EVENT);4 }! \+ o* v" h1 G
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, ( G/ {' f3 ~) V1 S
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */" p) \( C6 f0 {( [# m2 S' U! ~) \
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
A; T8 X! }7 Y- [ _, g' ^4 B3 rMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
- p+ W! _: @+ Q8 dwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
' O5 U) }( U' ]) @0 iMcASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ Z. |( F' }8 pMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
4 q) [( [+ ?% q% A! j}
) k/ y9 l& x# C# f请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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