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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ z' [1 P' p9 O* j: f+ f, f+ qinput mcasp_ahclkx,$ `+ o- ~! i ^6 \6 p5 x" e
input mcasp_aclkx,
3 K' U6 I. Q0 r( d1 r. U1 vinput axr0,. F5 T6 v) R0 x1 \4 O0 N$ `: {& _
. i8 Q: T: G. m9 C) N
output mcasp_afsr,
: H2 ~4 w- w) M9 Xoutput mcasp_ahclkr,
& V8 p' ~3 S) }! W: |, e- ]output mcasp_aclkr,
: o/ H" @3 |$ f( loutput axr1,& u) z4 I6 y! z6 f3 w
assign mcasp_afsr = mcasp_afsx;$ Z7 |% e3 {3 n( S
assign mcasp_aclkr = mcasp_aclkx;
5 }. I+ e5 b' b( }4 l! ]# v( jassign mcasp_ahclkr = mcasp_ahclkx;
5 ^' M# G6 o- |assign axr1 = axr0; $ u" b( M% \ Y
$ w. v6 l" o( f# ^在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
8 D: N3 R3 t( D) M- Sstatic void McASPI2SConfigure(void)- C) L1 Z x: X- A' M5 G8 r$ q
{
- i5 Q% D! b$ @" s& KMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 i" v' ^3 p4 cMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! i2 m" u" `5 W' D( L# _
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);( }0 t3 @9 r! ?: Q
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
% x# ?! Q1 W# H7 L9 uMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ H5 c/ c f7 d' U) yMCASP_RX_MODE_DMA);& \) G, ?9 C0 l- c2 [2 Z# H3 H" r
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
# p( w6 t L3 D+ H& `3 K5 rMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
4 L8 a$ u$ N9 m) ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, - z1 Z; R1 H! n! Y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 q; y$ H: L5 e$ QMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
6 `- j6 E. D( E- H6 ? |, vMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */2 H Q! q0 \4 K; |
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
6 v- l ]; C- D' Q d, L- uMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
6 y- f& O9 N* ^4 ~4 P! P. FMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,: t. L; m: }' m4 ?/ }9 _7 t
0x00, 0xFF); /* configure the clock for transmitter */" D* V+ c, B6 Y1 N
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);1 A6 ^8 R5 a" p8 l* Q. p) ~
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! O$ q7 u( s; ^5 QMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- c0 E0 [3 d1 X0 h+ \% m+ T
0x00, 0xFF);
2 |6 f5 P% ?2 X
2 L' x# D1 y1 l! W! [5 F+ Q- W/* Enable synchronization of RX and TX sections */ ) U; [5 v+ e* o8 L
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */8 p/ P Y/ N& ?0 O/ s2 M2 Y: u$ j
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); f* N6 @# A3 `' U4 d. a
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*6 p1 l9 {( s6 a' `& V/ ~
** Set the serializers, Currently only one serializer is set as+ m8 g% L9 J& L7 Q
** transmitter and one serializer as receiver.' M9 b5 r2 l1 f
*/
# j6 d" Y6 o3 ~# Z+ zMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
- K0 F# N* U9 A, u BMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
9 b; L* p" ?9 o' S. w% Z& f# v** Configure the McASP pins # U; X: t. E! n9 O" o2 j3 ~
** Input - Frame Sync, Clock and Serializer Rx! r+ e. i ]5 ]/ ]5 E7 G3 t# e
** Output - Serializer Tx is connected to the input of the codec
& B+ d u: @. f+ ^5 I*/
' [5 ]! I& D0 a# ` J. @% r- AMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
+ q& d+ J7 `& @0 n- X- zMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
. y4 [( R- M6 p0 EMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
) l r$ i1 h, P8 N( B7 K- H s| MCASP_PIN_ACLKX0 P( T: `0 ?, G' X
| MCASP_PIN_AHCLKX% Z' J" ]- D) c* l" c! T3 }0 Y
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
7 U% t! N1 i6 G: I/ T3 EMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR + k( f/ E ^: {( P2 \& C7 W" j
| MCASP_TX_CLKFAIL
" @5 O9 F0 R: H5 ~3 V* h( b1 H| MCASP_TX_SYNCERROR9 v5 R+ g1 q7 ~% ]! G7 c& _
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 n: {$ A. Y0 p/ i2 }$ G* ]7 X
| MCASP_RX_CLKFAIL5 @$ w- u0 z7 E( E% e
| MCASP_RX_SYNCERROR
- V2 W- j+ \( G# U| MCASP_RX_OVERRUN);# Z9 g- o3 \! n0 B
} static void I2SDataTxRxActivate(void)
0 r, A* S2 m8 V. j5 J7 H{( E$ x* C( w+ g6 X( }! l; j; R
/* Start the clocks */
+ ] u, t; O/ t: {5 j- tMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; J0 E( N2 r3 `, d! {# N' W; Z
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
+ @' l; T0 y# _! R: m2 r. LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,# a: _8 I4 h" [# J! M$ r6 k
EDMA3_TRIG_MODE_EVENT);
- w! [' d% W/ B! DEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 6 l+ t* T4 ]# s: R, |, N
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- B3 w& s' o+ H7 F' j; g$ O( y# hMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);1 M7 T0 e" Q/ z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' i' Q/ {* h$ p8 g6 l3 K
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) q# X/ Y" m7 v* A- p$ M, O
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: V7 @* a3 G2 H f+ u+ X$ j$ oMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
2 B, ]( W, v( X( I0 |, R- t} 3 E& ]1 v: t5 P: Y/ _
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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