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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
' f9 N* ^5 x$ S) u( \input mcasp_ahclkx,: v- W' w4 y0 y- `# `& ]- H
input mcasp_aclkx,
7 z4 f9 G) m! A" k E, S+ W/ xinput axr0,$ F4 b( _ X5 D5 ^
$ V1 F0 J7 O$ S5 u' \output mcasp_afsr,
0 p$ N( l# G6 O& f; y3 {+ }output mcasp_ahclkr,
+ }0 I- X: O2 [+ P7 w- poutput mcasp_aclkr,
: T$ X& W0 f& {' ~( W& woutput axr1,% E( K* U6 {+ O) V+ r0 j
assign mcasp_afsr = mcasp_afsx;& d: P9 s+ X' L/ s9 e# C
assign mcasp_aclkr = mcasp_aclkx;
9 [1 J0 R$ p P* ]: y: d8 Passign mcasp_ahclkr = mcasp_ahclkx;
3 y# f, j s7 T+ Q( h9 S* lassign axr1 = axr0; ; k& u- ~) J# G% o6 _9 [ J* E
! z! }6 R4 _! P& O在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
1 t6 U* S% h% R3 j2 o1 Wstatic void McASPI2SConfigure(void)
# g4 C3 m3 c) ]; E{
. N) T j) B# a# I+ ^McASPRxReset(SOC_MCASP_0_CTRL_REGS);
! X; k! |6 A9 d" Y$ I4 y; }# X! YMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
; s4 F: `: j! f, [* K4 _/ _McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, p& C4 r; I- r) I2 _
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- I; n: }9 y6 e( s) e
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; [" b% e# [" T4 P' rMCASP_RX_MODE_DMA);
) ?( M4 j1 \2 d; H' e2 R" l+ t1 rMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,& O L7 ?& x: i! h
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */' Z. S, _% f/ w, A. c
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * n( }4 {) e& @* M8 i/ l5 b* T8 c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);, X1 z1 M: ^9 N, C
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; i: o2 [* G; D6 F, TMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */& f" K# q) O& p6 {% u
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);& ~2 M# i) u0 n" Y4 K! ~% H: e
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
/ `+ S; ~3 F$ c2 d& z* h; I& D, S0 VMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* R ^" s2 [1 S% \% F( V0x00, 0xFF); /* configure the clock for transmitter */; q; A) A p* _' @, F) s2 R
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 |" z8 K R: V! P" P0 x5 K( w( r
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
1 m3 N. e- N# ~5 hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
6 q- x. \$ Q; N/ O c4 n0x00, 0xFF);8 z0 R9 T" l0 U$ V" k
' [6 d* N/ p4 J, X9 J: m# c/* Enable synchronization of RX and TX sections */
: ]* D+ z- o0 ]' N [. HMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
( Z! o' o5 P- N" a2 _- S5 WMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 Z, T/ V! M" }' y; m& {4 p, Z/ Q5 b7 _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*; D6 N3 w- }. W I8 ^
** Set the serializers, Currently only one serializer is set as( d) n9 z. z, |
** transmitter and one serializer as receiver.
9 q2 r: ?4 B' ^4 o*/# a: O. }6 t; f$ q( F+ w. M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
( u$ w% N9 l" }( l, j: sMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
1 o+ i2 H- E2 ]; _5 V** Configure the McASP pins 5 A- H5 C8 L4 ^( |; x$ s
** Input - Frame Sync, Clock and Serializer Rx
* N4 V$ H& ?/ N& c** Output - Serializer Tx is connected to the input of the codec - F; J6 ~2 a. ^$ c
*/2 `5 t) s1 {- f/ h& l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);. a( z; r. p, D$ W* r% {& }
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
- s, T$ k' V4 J1 j( IMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
% A' W* n+ i/ \8 [# d! `| MCASP_PIN_ACLKX
, S! n( G( I- o# B3 i# G' l| MCASP_PIN_AHCLKX" q( i! q# a& Q% C7 m
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
0 Q3 {' C7 o( X$ @/ j: ZMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' e5 d! e' k9 F
| MCASP_TX_CLKFAIL
* M9 j) g' z7 Z| MCASP_TX_SYNCERROR5 z$ t0 g& O8 g6 F4 G
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR * z7 U" w1 H, F$ r- V# ?
| MCASP_RX_CLKFAIL& A: \9 t) \' W$ f7 \' ~3 A
| MCASP_RX_SYNCERROR
! u6 D& b! |0 R' N: X| MCASP_RX_OVERRUN);
& o6 c! u% t; x5 q/ M. t% }9 J& t5 m} static void I2SDataTxRxActivate(void)9 P4 Z# k: H% u' h' t. Q. Y7 x
{4 v- B% r* K: ?. v- H- Z+ y. ?
/* Start the clocks */
+ y6 P- I9 O2 v/ AMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);; T! ?! o( M: c" U S
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
9 ^7 v$ v* B0 ]1 O5 I: _( |% BEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 G1 Z% E2 I* i1 t# N# GEDMA3_TRIG_MODE_EVENT);
1 R- F! F6 D. R0 V7 n) q b: ^9 x) dEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' w+ [1 [5 b" j/ }: r* G( U; oEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; q2 {/ A, W) x2 W5 B) g+ |5 A
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( i# a$ I6 m. t2 ^/ t* |/ T6 X7 |5 wMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */0 p* H. E- U1 y1 a
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */% T. V; N) C3 f! P
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
! q2 x/ j1 m# a6 c( M" W0 [McASPTxEnable(SOC_MCASP_0_CTRL_REGS);' [& O C2 H8 q- |% Z
}
) w5 Q0 Q4 V O/ `) h请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. % K% y9 `' X- p" B" t3 ^
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