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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
. b# \9 t4 `% `, T% w5 ninput mcasp_ahclkx,
7 G8 `) h! Q, {* j9 k# d- n$ sinput mcasp_aclkx,
7 z: \6 [/ q! W" f9 l% x Minput axr0,
0 _/ }# c* Z; \; @2 f: C- b4 i' _3 B- J4 y% P* ]- B' l7 q
output mcasp_afsr,0 ]2 w( l' {! ~
output mcasp_ahclkr,; N( @) w. x9 Z. i" \6 s
output mcasp_aclkr,
- w a. M. \6 Poutput axr1,
, g: [, j a5 ^$ L j assign mcasp_afsr = mcasp_afsx;$ w8 g' S3 {# {
assign mcasp_aclkr = mcasp_aclkx;1 U+ J& q/ v V' t, n9 i
assign mcasp_ahclkr = mcasp_ahclkx;
# p W. m5 X( gassign axr1 = axr0; p g" U" O" X! ]
1 i( [, s4 {7 G" M8 ^* R在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
0 p6 ^) w2 {9 C7 L- Gstatic void McASPI2SConfigure(void)
C O- V# H; o6 N% V) q, j4 m, r{
h0 ^$ C) S/ e' v6 NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);$ M. ~$ s" m/ |" n
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
% k0 q6 B' Z9 o UMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
. B7 X: ~3 o- H) ]$ g5 Y2 vMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */+ W" v+ i9 w1 J% U
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,1 g/ y; A5 k: i. U% O/ o+ |, @% W. e
MCASP_RX_MODE_DMA);
4 `2 d" o* r0 P; u! }( HMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 E5 \2 g6 Y5 W5 {" ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ t5 F8 A! N; f; S+ m% h6 xMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
& t5 n- V; R4 q0 a+ bMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
5 U, ?/ W% d M& J% h8 K& Z( h: IMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* g# B U. u$ D$ u6 tMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
3 }. e7 P0 X' T# H3 nMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
" c, W2 t3 |: kMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* s' r7 c' B7 |0 m, uMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
5 T) c1 v( e1 C" w6 @' ^! z0x00, 0xFF); /* configure the clock for transmitter */
4 M% z- L: j; T2 ^McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);, q7 l8 V1 ]$ q9 ?) X- w! N S$ Z- H% [
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
8 K' B2 x1 E1 h$ WMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,4 U4 y# c( s7 f3 @* j) S
0x00, 0xFF);
, ?: L# H. }" `- P8 n* {$ K- r0 a
" t5 I7 [ X# B/* Enable synchronization of RX and TX sections */
) p4 d g/ R4 |! e& Q' C9 LMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */% t; m& d1 R& U" I2 z
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);* ^' y1 W' V3 G- k: F0 D
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
$ o- ?& \7 o) P0 G5 }) V** Set the serializers, Currently only one serializer is set as
* Y" D- r7 o3 P! l( P+ s. n** transmitter and one serializer as receiver.8 R& h+ q$ `' }4 n& f5 k
*/
0 v6 U& C$ P# ^9 R& KMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 B. [8 `: J! B( d, F, v/ tMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( H5 l1 l8 S: o; N% L5 D. U, v. p2 j** Configure the McASP pins - F+ Y' g$ D" H2 P, O( n
** Input - Frame Sync, Clock and Serializer Rx
) O& w3 I9 A _) w7 p# W** Output - Serializer Tx is connected to the input of the codec
4 S! a4 Q. d( ?& S+ U*/
7 C! L' \6 [% i4 W8 \* KMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
7 q% ^: Y3 d2 O! |' ]+ NMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
* A4 ? N& y! e8 [7 Y9 A! Q1 XMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 s) j( [5 r3 c- i' b( ^' A) a _
| MCASP_PIN_ACLKX
+ w. y) E! h3 v; E h| MCASP_PIN_AHCLKX( `. p0 `: G# e* d" h2 ]$ D# j
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
1 M3 t& N* H0 U% O v4 c6 w+ B0 VMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
0 a( I$ @! p1 V- `8 L| MCASP_TX_CLKFAIL 6 X1 ^ W! o- ^
| MCASP_TX_SYNCERROR
7 U0 @+ ^6 w) W' I' x0 e3 [| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
1 c, V9 W" w3 R4 d4 J| MCASP_RX_CLKFAIL0 Y- [$ V9 ]& [4 L$ b
| MCASP_RX_SYNCERROR - Q1 w. K4 y! E# i( M
| MCASP_RX_OVERRUN);
# I4 s+ Q2 q" L" }} static void I2SDataTxRxActivate(void)
3 z5 z0 r: a" F0 ?7 G{
- [* b! D4 N j2 l/* Start the clocks */. A f" x. p" b/ Y; }9 h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
. }7 s2 ~* ^ h* }% t" C" {McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 N" B ?. M7 E XEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,: M. j8 _9 ]0 z8 _+ j. ~
EDMA3_TRIG_MODE_EVENT);
0 E8 ~) X( L- q# h& i* W7 yEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& O% T- Q9 i8 w0 f- f2 D" KEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- V- C$ I' f- v/ I( P4 AMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" K0 S p% y e/ K6 ~* z
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
4 G8 W' o4 x, d- ~while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */1 \ H0 Y; d! c( T2 R+ N. A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);7 `+ w: y1 N* N
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);* ^, Y2 [8 A- ]5 Y
} 1 k: ]+ F4 @- ~% v! ^$ _2 g2 p6 h1 l
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. - K; k2 V8 T; ]0 F' Z, j
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