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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% o7 L5 G# z1 R* Q* W
input mcasp_ahclkx,; v- s( q5 {4 M1 N
input mcasp_aclkx,
$ b! z# i# J( finput axr0,4 n; C6 m' j: b( j9 k
8 v4 V4 Z. R. r' M1 ioutput mcasp_afsr, P- W) {3 M A& }
output mcasp_ahclkr,
9 o( m9 i1 y3 z! m) Loutput mcasp_aclkr,+ l8 j) O c M2 r1 n+ c. a
output axr1,
, I6 P1 W: F# Q- V' V assign mcasp_afsr = mcasp_afsx; M5 {7 ]# _* z! K* {; [
assign mcasp_aclkr = mcasp_aclkx;1 X5 @- h2 \: t: v0 E& W
assign mcasp_ahclkr = mcasp_ahclkx;
. F% C- d4 ?8 v, @assign axr1 = axr0;
7 H/ p: b1 A' _) Z! g; u) y, V4 l' K' D6 N
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 9 W5 Q+ W/ N3 a9 a$ ]
static void McASPI2SConfigure(void)
& Q9 k/ [+ Y3 _( O) x. g{# S, q9 a8 }' T k/ n0 l
McASPRxReset(SOC_MCASP_0_CTRL_REGS);7 q% Y8 P8 y( q. f. s. i0 O) k
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */- b* w" R9 s+ P- ^
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
; Z3 z3 ] j, t; z! j, C$ xMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */( a, w9 L5 g+ `, K6 @2 {* s0 f. ^
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* B* h1 `4 l% E* D Z& Q; Y7 {7 UMCASP_RX_MODE_DMA);7 }, {' Q. s/ j9 R
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,6 `( [ ?& i& q( d
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */% C' V& {% q1 S$ o: C, d
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, % @8 Y: y9 L3 m1 V: [. b' X
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
7 s& p, m/ _1 r' d5 X- iMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
5 |! f8 f% }- z; }5 e) oMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
1 N) w! h. Z. P( RMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
5 R1 @2 [' g: y3 n& b; b; K* vMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) H% v: B' N$ j6 p0 W f
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
& j+ i& A" V9 T5 b3 V0 C- C0x00, 0xFF); /* configure the clock for transmitter */
2 r" [# O8 Q/ s) CMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);) q) X4 y+ ?9 R0 r/ a/ N! t1 ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 1 @0 ^0 h7 b$ N6 \, P
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
( t' o* \1 A8 J Z- z5 O Q0x00, 0xFF);% r* e& T% v# T9 ^
: W9 I$ {- o" A
/* Enable synchronization of RX and TX sections */
; P* V0 z! C! S+ g; a# NMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% I- }( F! a# D+ x9 p5 b$ PMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
6 ~ o0 f5 P u0 X, U" M0 NMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*" C; f% L9 d" _ f# G
** Set the serializers, Currently only one serializer is set as
! C! t$ Z+ e7 h' i& q; L% f** transmitter and one serializer as receiver.
& I& u6 o- Q" W" s8 y% _*/- v5 n7 r& \/ \7 z/ g. `" x+ ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);! {+ C8 b& s9 ]5 ]( L& i1 f
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
! j: _9 P! ^& e6 A/ @** Configure the McASP pins
" J) q) g$ L" l. r** Input - Frame Sync, Clock and Serializer Rx( d' Z8 c3 r0 F/ H0 F3 F
** Output - Serializer Tx is connected to the input of the codec $ h5 }6 _$ |. d' r
*/
N% A9 L5 x4 J1 u2 V! B/ jMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
9 v) Z% ^- L- i1 qMcASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));0 C) ^7 m7 z" ^- k3 `
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
' B8 B |) `" x| MCASP_PIN_ACLKX
( R; J) ~4 O/ `| MCASP_PIN_AHCLKX8 q$ A8 p0 h" f6 O! f
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 B3 u8 }( j$ \/ PMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
% I0 }% d+ f' Y, [: s| MCASP_TX_CLKFAIL J5 N* I2 |/ n, V/ s: H6 d8 B* L
| MCASP_TX_SYNCERROR! L; P% L! a/ y" G4 D
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 2 Y" }9 _5 G% u( S( {) [
| MCASP_RX_CLKFAIL
h) I) N. C" z# C1 @) N| MCASP_RX_SYNCERROR
( Y/ \$ ?) T1 f5 Z, S| MCASP_RX_OVERRUN);0 ]5 `$ O1 g2 I
} static void I2SDataTxRxActivate(void)
! A( q% i( c x! |{
2 V' y0 W7 e' p2 P# ?/ y* @4 T/* Start the clocks */& I$ u7 ^* c! j+ N" o: f3 X
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
0 h* H! d7 `* ^# t6 o$ CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */2 m# m$ d8 U. y2 a7 \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,1 A H* n1 J; D
EDMA3_TRIG_MODE_EVENT);
/ X5 ]( O* [. p+ w4 ~" X$ D; }EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 3 F% N% n0 x5 s2 \, p8 c- @
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
/ i5 [: f0 G$ e: q b; j: DMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);- h6 n' r! c/ w( J) c* O
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */' p. s. B9 a) b& A% v
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */9 P6 a) V8 t1 z5 C
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- S) ?9 y5 X+ k# M. e( d) {McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
7 b5 J5 R. Q6 K8 I3 ~6 y0 L( A* ^) u}
w: N' Q& r# z- p7 ?请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. 8 Y" Z. d! Z8 |+ L: c: l1 {9 F+ e
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