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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,% `4 N' _, E T( u0 F
input mcasp_ahclkx,. e3 C% |) D7 @/ c/ O8 a) y% m
input mcasp_aclkx, P& U4 A/ b' {/ \
input axr0,* ^; W$ `- I- @, u$ B$ _
2 {- u* Y. j! b& N" Z: O# J
output mcasp_afsr,
) q- c3 Y% Z7 ?6 C: O; G: Coutput mcasp_ahclkr,4 B2 K0 v1 c2 F
output mcasp_aclkr,
, g4 P3 K+ \" M1 ioutput axr1,
3 p' [# u/ _) b8 {, e, @ assign mcasp_afsr = mcasp_afsx;
0 l3 O5 I0 h4 h& w( uassign mcasp_aclkr = mcasp_aclkx;
8 N' X$ H+ A& y5 o9 g. Oassign mcasp_ahclkr = mcasp_ahclkx;* e( M1 O# ?, O x
assign axr1 = axr0; , Z! X8 q' b& A$ g
- c, m% E# E7 N在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ( E/ @; Q) C" e6 L! b/ o6 H& f
static void McASPI2SConfigure(void)
2 o2 m( ]- m9 G% u4 {9 Y( O8 e{+ G' S6 _ @5 G
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
, J% |+ a6 ^8 U. x( \" GMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */& i" w# J) b4 w3 k/ U; b1 \
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);, W# e1 h5 v9 K% Y0 Y) y" y. ?
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */" ?$ F/ t0 N R; L% Z' k; Y* N
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,! {7 O. F" y1 E. d8 v% G' g
MCASP_RX_MODE_DMA);
2 m& H) v, ~/ WMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,; x( N+ P* i$ R6 F, y4 @) \
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
1 s0 f4 \( B) {. z( }2 E7 ZMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, & T6 x; ^' z3 Y7 S" y
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
% d# [/ k' q8 s/ kMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, ; o0 |+ S0 [1 Z# m
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */+ x9 t, K2 ]9 A. o4 U" ~" j: f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);( t `' o( m2 U/ }8 A& W
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
: |) X) O l+ e' W/ D) OMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
6 h i" V! R/ K0 M0 S2 E6 k8 \0x00, 0xFF); /* configure the clock for transmitter */% H4 r9 ]* _ P T3 ? _
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
- `. H* P- L9 A4 [4 c6 |McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
! x( Q( }4 U' r& b) BMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,: s2 W; _* o; v/ D7 I( T6 R+ Q) d- @
0x00, 0xFF);* _! O- Z' J$ p$ k; h8 N
: p. t3 O) y1 M( i2 F/* Enable synchronization of RX and TX sections */ . |5 r, h# {8 Q2 H' R
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
2 j: l; R, m' S- e- s! qMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
4 Y4 Q. \$ x% h9 g' g) PMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*% S l$ p8 F) {8 u8 l7 V' l
** Set the serializers, Currently only one serializer is set as
( y# r, b Y! L6 I# Z. t/ h2 g** transmitter and one serializer as receiver.
, w' x* o" e- h* y*/
( I- o5 i# ~4 q8 e7 D yMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
# C3 B' E; c O( L2 NMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
( s, h$ [ J% n! e** Configure the McASP pins
: k, ^% o% L' `2 v$ N1 m+ C O0 h0 P** Input - Frame Sync, Clock and Serializer Rx
# n) m! c. r. f9 u( @. b2 V** Output - Serializer Tx is connected to the input of the codec 1 B3 V" X/ Q# p4 `1 U; o
*/# q$ _0 r8 |- l
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);$ B0 O5 j/ v2 p/ v5 T( `) m: H7 ~
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
9 h2 A {* O) j$ X9 FMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
# {2 H5 R# z5 v. V: F| MCASP_PIN_ACLKX0 m4 v/ G3 Q9 m& N2 k& ?1 V5 \
| MCASP_PIN_AHCLKX9 x: u; U3 i$ y# b
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
; h! g+ Q9 \8 S2 N+ qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
8 }7 B% Y2 ~: U- h0 ?| MCASP_TX_CLKFAIL
; f8 e- x6 R0 p' L/ ^4 r| MCASP_TX_SYNCERROR: t& b: @2 X& ]* K5 q. @) g/ n+ s
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # j& X5 p: V7 Z; Z
| MCASP_RX_CLKFAIL' H& o+ @0 ?- ]. h. C) C
| MCASP_RX_SYNCERROR , M* B, w, v/ R, Z, R! }, `
| MCASP_RX_OVERRUN);
1 L. E5 D0 l2 Y4 ]$ c# k# Z} static void I2SDataTxRxActivate(void)' `# ~' L+ k2 `) E1 E1 e
{) X/ n/ [/ B$ P+ j
/* Start the clocks */. r1 O$ [, P8 Y( o0 K* K# h
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
- x1 c. |6 B( d1 CMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
" r; ?5 E2 }* O0 N& xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,, C; ]3 B: l% s/ w, g$ Y$ C
EDMA3_TRIG_MODE_EVENT);
% \; Q+ c; Y: r3 `! E: VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
/ ~5 ~/ s6 _; L% M! p3 pEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
0 C+ F- A5 i& ?0 i2 MMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);, o, } J$ z- H! ~- G" V& K
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 Q* e" ~ b, }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */) L) y2 h o/ W% ?) c6 U7 i) X* R
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% ~9 ^3 p$ |- f/ A, q) r+ }McASPTxEnable(SOC_MCASP_0_CTRL_REGS);& E V5 F4 w' |% r6 C, r
}
J. }, ?0 ~$ P1 b: [$ }4 M5 N请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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