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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ o# ^6 J8 E! N( ~input mcasp_ahclkx,2 ^3 m% b+ _) D+ ?
input mcasp_aclkx,
/ A) G9 `0 ]8 S' z3 ^8 Dinput axr0,
, E! \$ T+ T1 O
3 i4 Z: o( M& j0 u% }output mcasp_afsr,/ k8 ]) K6 j: Q+ I/ m9 V
output mcasp_ahclkr,3 V b9 E) d. ?, o0 T! A& I
output mcasp_aclkr,
! s4 _8 k m' v% Poutput axr1,7 U( _) Q1 P* q7 @; ^* K' x; s
assign mcasp_afsr = mcasp_afsx;
0 e: E: D: I+ k* r! [assign mcasp_aclkr = mcasp_aclkx;
: k1 O: M" u) K1 \/ jassign mcasp_ahclkr = mcasp_ahclkx;
0 D9 a$ T. t: Fassign axr1 = axr0; , p4 k- O1 i$ W3 g! e
/ Y+ |/ q/ j( S/ J) E在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
7 c5 S) S" ?# O% K% L) lstatic void McASPI2SConfigure(void)$ ^2 V6 {0 n+ |
{
: n6 u& y3 Z8 S# UMcASPRxReset(SOC_MCASP_0_CTRL_REGS);. v. H1 f3 f( `
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
& c3 v! N" q! A) iMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);6 Z {* E! C% O, v+ h
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */7 C* G7 H) }3 [3 ]
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,, m% e7 H. P H" z4 ^! i- t
MCASP_RX_MODE_DMA);0 U2 u# b( \- I; T
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 K+ e$ W" h- D2 f' o2 aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 Z& M* {1 K6 W5 D! G# a
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 7 T$ U8 s8 Q( w+ V, ?3 i Q
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
/ U8 W; e9 o: e) H2 `) oMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
/ u* D9 s9 g' j- zMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */: _2 i- F( K' E3 X ?
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. I6 W- n6 ^1 ^" ^2 g
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 5 K3 |. p$ D% G; q
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
( A; D/ u* P* W& m6 D- s0x00, 0xFF); /* configure the clock for transmitter */8 E, }2 k) Q* J" f8 f. l
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
7 `6 D: G& p" Q: @McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 Y* j* B' [: s! E+ wMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,% u( r2 n3 q2 b" Q4 y# q7 T0 }
0x00, 0xFF);
7 j8 q ]9 W/ r: l% H3 r# z; @+ {$ r: l; s
/* Enable synchronization of RX and TX sections */ 1 t$ X8 Y/ |- V2 |. v( r! [
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
% \! w: J a% |1 X& P: S/ YMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 u8 N3 m$ O* vMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*/ \5 Q- G; l4 s$ Z
** Set the serializers, Currently only one serializer is set as
5 }0 T9 V1 O# I I** transmitter and one serializer as receiver.
5 `3 R: f, ^( F6 p# W4 Q% q3 [*/7 P) S' a' j0 [# A
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
, R% S7 r8 A0 q; V! }McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
/ D( Q& D6 F, y3 h2 m** Configure the McASP pins - d$ R7 S. t# I1 l
** Input - Frame Sync, Clock and Serializer Rx
* Q! C: q$ M/ I** Output - Serializer Tx is connected to the input of the codec . v1 w2 ]1 T) A+ @6 ~% M
*/
: K& F% |& L3 a4 ]McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
& |2 ?* U5 m6 g, o7 @3 @McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
% J& Q- W, P f( dMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX0 w3 B4 j& I7 l8 D! e. e" m
| MCASP_PIN_ACLKX
* K" J: }, s6 v0 f) d) ^+ v| MCASP_PIN_AHCLKX
x, R7 s Z2 o% t| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */2 i" O/ ]. @3 S& n! i/ k- }) S
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ' J0 v1 D, P& y# r; Z% H
| MCASP_TX_CLKFAIL
0 I! \9 Y. U" _, ~7 \; A| MCASP_TX_SYNCERROR
7 s7 N( w0 D( u5 C| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
( h% s. v1 ?$ k; C| MCASP_RX_CLKFAIL# k; O* p% {" B4 M
| MCASP_RX_SYNCERROR & T3 x6 m* `. H' r
| MCASP_RX_OVERRUN);
3 l( P5 C, N) W3 w% R} static void I2SDataTxRxActivate(void)
: _2 I' }) _, ?6 S* t& R{
+ C: \ G$ T7 [3 g3 d$ r) u+ ~' n/* Start the clocks */
' O3 W/ X* f" M6 k. V' x$ E6 G; \McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ ]; j: J0 {! _7 Y' Q, _) {
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
% h' z. T3 _4 W$ F- }' O' cEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX," m; p4 V r `* K# T- D. N9 W8 x
EDMA3_TRIG_MODE_EVENT);+ T; o& k( ^# q
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
' E* }, D& B7 o) rEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
; m" F4 B3 R" F7 h: m* ?- y0 W+ wMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& B2 K" O- U% x& W- X
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
6 b: C/ X8 t0 M: W6 |3 l5 Xwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
& i2 A" H1 ]3 s$ [McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. n, e( d) P6 KMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
0 R! p. U- M3 h- Q} " ^" g; o; r% h3 V- Q5 W/ y
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * K$ P) ~; E& V% B7 [
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