|
我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,$ Q5 t$ ~9 y2 H2 W. v7 Z- j% K3 L
input mcasp_ahclkx,
& U! K) s. ]- l9 ainput mcasp_aclkx,. L; K' G2 g* T( `
input axr0,
- G9 K/ W6 _0 U' s+ c9 n& C- N/ g1 m. F) n* N r/ k
output mcasp_afsr,6 r% `+ N/ T, ]+ n$ B! [+ o' {
output mcasp_ahclkr,
6 D# ?2 d- r- y7 \ }output mcasp_aclkr,- @6 t$ \2 L, d3 D
output axr1,0 u) D0 o l7 J
assign mcasp_afsr = mcasp_afsx;! S5 R+ U7 N5 ]0 z( H- t+ x" _
assign mcasp_aclkr = mcasp_aclkx;
' \% c1 I0 [1 o* ^7 K5 B- ` Gassign mcasp_ahclkr = mcasp_ahclkx;
6 }. q) v2 X% k2 w/ b- T+ iassign axr1 = axr0;
! g3 d9 r3 O2 m5 H$ `; }# q. ]; Y9 O- ^6 K, Z# L* _
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 & f' r1 X3 A3 Z5 @( k* `$ W
static void McASPI2SConfigure(void)
+ P8 h* P- j6 x5 t% u; @2 `6 n{
* H$ }0 [( \8 h y! N! NMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
7 R6 p' R6 K. k* MMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 J1 v% C2 X5 b. d6 Z W' f) R( y
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 y5 W3 [. ~+ x: H8 w& @
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units *// Y: V# E& n9 f$ w
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; f- M) Y s0 E/ o8 ~2 xMCASP_RX_MODE_DMA);$ {' T1 z5 g* V1 F2 |6 v! z
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
' @* P, g9 B5 v& SMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
' H' q7 I& S8 S/ nMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
8 L- w9 w X% @" ]8 mMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);# ^; q* H1 T1 ~' F* S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, + q1 R+ J W, Z, a$ m2 D& n4 B
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
8 S: T* K o) d; j. O2 ?; \McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
* W8 d8 H( W/ Y; Q2 RMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ! q9 T* k/ ~& |/ `, d4 F
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
) t* v% y. C, {. f& C0x00, 0xFF); /* configure the clock for transmitter */
" R- ]# K8 w' lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
& S8 c" k$ ~4 LMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); 0 t/ ]7 U. }% U. q- `, G T- H* D
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32," ^/ U9 [' T$ D, w+ q, Q% q
0x00, 0xFF);
$ o& I- b$ t0 ~# }/ ]4 T
! E' g$ U: q, S' }7 Y+ n* R! X/* Enable synchronization of RX and TX sections */ 0 i& \. N( |; H: k5 ~& N
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */5 F. A. d2 A# u7 q; P( H0 O
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
e7 B$ p' m* p: \; z1 uMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
7 w& z2 Q# ]9 |** Set the serializers, Currently only one serializer is set as& \/ Z5 B/ ^+ g/ j7 O$ p
** transmitter and one serializer as receiver.* r: B; x% f- S& Q
*/) X1 }% `5 F* F ^
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
2 w- T4 @4 g4 o0 [+ x* ZMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*, O. g9 E8 e4 W
** Configure the McASP pins 2 q$ y8 |; l; h* j5 J% H( |
** Input - Frame Sync, Clock and Serializer Rx: z6 o" N+ w' D$ s
** Output - Serializer Tx is connected to the input of the codec
. f7 M5 g9 r/ ]' u0 @/ K7 ]*/: p! @& k0 p/ z. Z, v2 |9 F
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);, h; m! v6 b9 i7 _3 Q9 [ U
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));& Z( n: v, A3 ^1 S4 x$ T
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
* `* S- l9 ]' h5 H6 u3 i7 d: ~| MCASP_PIN_ACLKX/ G5 ~+ d7 A& m! ]& D( k! y, ^/ Q
| MCASP_PIN_AHCLKX
7 o( V. b$ a% x) m1 T. s. s, r| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */9 P' ?! J: |" ^ Y' h! h& ~0 l& k
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
+ r6 u* Y9 m* `4 e* G5 _4 z| MCASP_TX_CLKFAIL 9 w$ g9 z& [/ ]5 h. ?$ z
| MCASP_TX_SYNCERROR
z" N% _* W; ]4 }9 }| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR # Q* q5 j/ i! ?* h4 N
| MCASP_RX_CLKFAIL
& S8 N& m7 w8 k| MCASP_RX_SYNCERROR
: H* B0 [ x9 f0 t) b" j) O: \| MCASP_RX_OVERRUN);
+ Y' A- [( D7 u$ ~: J} static void I2SDataTxRxActivate(void)
' r% H5 @- k. J: R4 Z5 D3 ^{
9 l0 U5 X. E; Y+ ?! t4 B/* Start the clocks */
+ ?/ V! f P, O! sMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);$ X- V) d) o" w/ p: z" c2 `
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */' z, s' f% w, @5 n. F6 T n
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& M- k' C1 u9 e$ J( { y
EDMA3_TRIG_MODE_EVENT);
& ?; D6 d( R/ A8 P- k' g3 \9 pEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
* j: Y# K/ E8 u; ] S j. W/ f# |6 [EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */5 \/ N2 F$ A1 I6 L$ }" L3 Z4 ?, n
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);; r, e6 @# u# R
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */; r% N' d& b$ r' }: h+ }: e
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */4 ?% `" p( A! f* U! H$ D4 A
McASPRxEnable(SOC_MCASP_0_CTRL_REGS); w! {! A' ~ }3 X- o" ~
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. \( F, Q" K7 a4 [5 m9 @} " O7 o& B6 W$ C
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. n( E7 o5 F' R4 t, {) x7 f5 G. x
|