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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
! p/ K1 l9 @: \# H3 _input mcasp_ahclkx,
$ Z) X6 P1 ^5 y- ]3 M6 N9 F- Ainput mcasp_aclkx,4 N0 Q$ D; S6 Z I
input axr0,2 v/ J; c& i) z: i
* S& d& E! j* v( ~" E. @) {& G
output mcasp_afsr,6 X; n& a F! g. C( J# V' P) l8 V
output mcasp_ahclkr, E( Y8 W6 N8 K9 i' W- j: W
output mcasp_aclkr,/ k, B8 v& W% R9 f4 _
output axr1,. ?, e. h8 U z& Y' m5 [8 o
assign mcasp_afsr = mcasp_afsx;. | p: w" {: E/ L# j9 ]6 r4 V7 o
assign mcasp_aclkr = mcasp_aclkx;) e! X# U% o7 ~, Z8 `: O; X! j
assign mcasp_ahclkr = mcasp_ahclkx;
- C/ |) @5 V! Massign axr1 = axr0;
' c0 x& r& ?8 j& a5 Z2 E
" }( [! ?1 k' U J8 z1 y. Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 - b( z3 K. _; l1 z9 m
static void McASPI2SConfigure(void)
9 a- o) F$ K! d" J# ^ U6 H{
; ?6 V* _$ C0 g p6 V, oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);8 |" U) |# I ^+ q! k! N5 l
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 Z: u0 h2 c% O+ jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);! b) b7 V4 C0 f2 Z/ b0 {! K$ U
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: N B+ M' D7 L+ q$ A9 ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 \1 Y. D" k$ P& k. o* c
MCASP_RX_MODE_DMA);! B2 k/ G: n7 d* n; N# M) w
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
2 I( h* o8 E, p& ~( h0 o& AMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */3 ]4 e# {4 V* D
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, A+ w7 j9 C! S3 u* I# g \8 n' yMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ |9 I9 ]4 }. n1 wMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, 5 @* n8 t- W6 z8 d: _8 [& K
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
/ P( F% f$ w! k3 o) F! @McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);) l+ {, U3 n2 h) Q* G9 _/ q. l
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); ) {9 R8 @! F! a
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
% C$ T9 ^6 O8 Q8 a0x00, 0xFF); /* configure the clock for transmitter */" d- H9 m! b9 S! V6 ^
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);# `) @* h7 I. N- c1 Q. M. k
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); ) O4 E: R( Y3 h* f
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,3 g9 l( f! K% B
0x00, 0xFF);/ w6 m4 x) b. R# E- b& m4 P
3 f2 s" e& j; j/* Enable synchronization of RX and TX sections */
$ D5 g8 {/ k! L- B" }, V _McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */6 z5 B* ^4 ^, ]/ p7 A3 u& f
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);( @4 N6 b- r$ c" Q9 L( Z& s
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
* y g7 h5 u' W8 P** Set the serializers, Currently only one serializer is set as" B+ U8 z1 h1 {0 e. p9 m
** transmitter and one serializer as receiver.' y$ L, P* X& B: A
*/
, u& e @% x, u Z3 X) U* h8 k- rMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);8 {/ r* z& R9 L a5 l
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /** H7 K( r4 e2 x" h
** Configure the McASP pins
6 O. z7 _$ j% [+ e) W& _/ Y** Input - Frame Sync, Clock and Serializer Rx
3 ]% v9 a. B6 B6 v** Output - Serializer Tx is connected to the input of the codec
8 H; u: b- h% @( `$ ?; T*/
; u l1 | M: b6 _& ], ^; DMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);3 S$ C) z# e+ B9 [% G
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
7 L/ h! | N$ z3 DMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
$ h- `+ P+ z9 c! ^| MCASP_PIN_ACLKX
$ _. t" [6 z6 d' u| MCASP_PIN_AHCLKX
: d/ q: `2 a% V4 `| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */* q w6 n8 d! o
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 z6 R6 X0 P- x% p% W; V| MCASP_TX_CLKFAIL : X6 L: h+ U: y, ^4 m m' Q
| MCASP_TX_SYNCERROR. F+ W4 c) u; _! M1 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR / y5 I5 V2 ?+ j1 D# m- A4 w9 p+ f n& ?
| MCASP_RX_CLKFAIL
6 @" I+ m& C# Z( z. g, C| MCASP_RX_SYNCERROR
( S, i, F0 B/ Y; D' C+ R0 z| MCASP_RX_OVERRUN);/ O% [. K. }' P8 }
} static void I2SDataTxRxActivate(void)
1 v7 E/ M1 @+ k{
) f5 _9 F0 ^+ G/* Start the clocks */
" F2 Z( K+ `/ H/ eMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# |; T" H# r1 w4 B7 E" _" o. d
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */) `0 ^$ A, `( j A
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,! v! E% w' t5 H/ x2 y" G. G2 Z- X0 o
EDMA3_TRIG_MODE_EVENT);
y! R" ?: i( ?4 \. X4 vEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, $ D9 p) q# Q( `/ P& B0 ~
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- A1 L M Q* u8 D( k2 x7 eMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
8 h6 [2 M( I# g# a! {* Y. O9 z( mMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
2 Z; v' u; w8 d9 v0 m5 o& \, ?6 r; Q3 }while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
9 _+ W; ^( |. g ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);5 ^' i: y6 K! |9 ~0 K+ ^% }
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);: x3 K" Q4 D9 I( c9 [* l: @) K
} % ~% J9 n9 c7 j7 r7 J: ]$ r
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. * G- V3 q1 ?- F7 G1 I; S- G3 @8 t
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