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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
/ F8 ]; }! W+ E8 ninput mcasp_ahclkx,3 q! q8 H1 k: }' Y
input mcasp_aclkx, G. h F8 T: k% {
input axr0,
4 Y d/ [( f: {
3 N4 Q4 Z/ N9 p( youtput mcasp_afsr,
& X9 F9 X& Z9 M& b1 R. Aoutput mcasp_ahclkr,6 \) f1 ]- }+ L6 N' A
output mcasp_aclkr,6 p0 o* J& E5 O( l
output axr1,
: h! [ w' r9 |5 W2 x) Z6 Q+ U assign mcasp_afsr = mcasp_afsx;0 x4 Y" R. P; ?
assign mcasp_aclkr = mcasp_aclkx;' J# X7 {" L1 b; ]- T* B2 W
assign mcasp_ahclkr = mcasp_ahclkx;
6 C, J0 G0 D7 Iassign axr1 = axr0; ! S" g# A8 N) ~4 N5 i' T+ e
/ ^+ @ Y& H# ~9 {- A# Y9 C: ^
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
" X: L3 r! j Dstatic void McASPI2SConfigure(void)% N. b* r( D G ]
{
9 r# a- z. `7 j' x4 {' D' ?6 oMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
9 b4 g$ ?2 j, v& E5 r: h3 r8 eMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
, s! ]% r, [- B, m3 k2 L! y+ jMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);7 _- Z5 R: r8 N R& H) R
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */2 z7 b9 M3 e( v2 }
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ R9 W5 i( M. j2 VMCASP_RX_MODE_DMA);
2 v6 b: x5 {* n- f+ wMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
6 N& _/ `6 m6 y* O1 ^1 ^$ L, LMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
! B7 A9 c o2 MMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# O: d+ t. R2 o1 \( V% |8 ]4 t* LMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
( y5 J9 R$ ^* {+ yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( {# m% C8 ]/ D' W, DMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
* W* G' ?- }9 F& |6 m1 n) S) JMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);2 ~: j `# s0 Z; W& h
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* R1 C' z$ z8 i, [" c5 ?McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,, i; W: q* P9 v6 u8 w: o- U2 f% n7 Q
0x00, 0xFF); /* configure the clock for transmitter */
2 M) v0 t ~% x" D; lMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);* t4 G; c, h, b2 {* c
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); $ x0 v6 |/ B# U. K5 q" I$ G" @4 R! ^
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
) c& }5 z1 o; ^% \6 c$ b0x00, 0xFF);1 J0 ^+ c/ s) A0 {
. r4 v7 E/ J( o c+ p3 [
/* Enable synchronization of RX and TX sections */ . T5 p5 @2 X: ?0 {
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */# L. }: s4 [- v! `
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);# ^6 ~# p7 P% h! O$ ?
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
1 d: `' N, T5 i: D W$ C** Set the serializers, Currently only one serializer is set as) e1 w/ R1 O B8 [! \ j, b* H
** transmitter and one serializer as receiver.
3 j) c6 a( ^, R! ~*/
; ^3 |( j* u% d# O3 X9 L4 TMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);$ C# ^5 }; t3 R4 o% L1 j# i1 }
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*: W& j; H# k/ H
** Configure the McASP pins
: J2 ~# ~( }' i, x; ~4 z** Input - Frame Sync, Clock and Serializer Rx$ C8 o \) u" V4 q5 Z2 |
** Output - Serializer Tx is connected to the input of the codec
) T5 H7 E m3 L1 B' l& r: I4 x*/
$ T# e6 [2 v0 H {: K8 E6 U( P' F1 LMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 g1 O5 x' J, @! {1 g% g
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
G4 g/ B3 H: u- O2 `! n) @- AMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
! L6 M. M5 `7 B7 c| MCASP_PIN_ACLKX
- z' y& q- l) E3 y, j, P| MCASP_PIN_AHCLKX2 }) l0 q6 t3 j- ^
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 X( p! ?- p1 K5 c! ?; JMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
& _! C r* k6 k/ v1 C/ q| MCASP_TX_CLKFAIL & }( K2 S; l4 r9 ~. `/ r& A- t
| MCASP_TX_SYNCERROR
1 l: k- l9 T$ Y& `% L. f| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 0 \. [4 h! E/ o- a+ p. E9 u
| MCASP_RX_CLKFAIL \% T$ E% O& E- w" C
| MCASP_RX_SYNCERROR * k, U# ?4 a% S4 o; z) p
| MCASP_RX_OVERRUN);6 k) N) ~2 k9 D& s: L$ C
} static void I2SDataTxRxActivate(void)% |0 \# n0 U: ]; _% W6 h, Q6 b& f& p
{
- l- m* v* n$ u/* Start the clocks */+ @+ o( r+ q0 ~" L( g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) F' l7 j w; m% R( q o4 V9 Q" U2 mMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
2 N$ g1 t+ p/ o! {! VEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
1 t0 B& Z- x8 ^6 h, p! D) A( I4 EEDMA3_TRIG_MODE_EVENT);
7 L* ^& U3 Z, r. O/ W) h) x5 a, G: C* f6 FEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, * g; r9 s: q3 n8 d2 j) S! C
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */$ _9 m( w p( g8 v$ F
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
# _% z2 x. ~6 DMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */* v$ u0 L3 `- ?, `$ x1 w, S
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */* m/ ]% X* D5 ~# x
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; N e5 T1 t$ p' b m7 B7 O
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);3 t; Q7 ^9 u. u, S
}
& v! f5 {- k5 k1 x6 U请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. " y, I% z* O2 X* c% L2 _
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