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我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,0 g: ?7 @4 g- b( M$ @0 d
input mcasp_ahclkx,3 b5 ?% U( @. @ p- V2 w" j
input mcasp_aclkx,0 {! w+ V/ X& A6 P" s
input axr0,
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+ h) n u4 X1 a) M' b, Joutput mcasp_afsr,9 ~2 R. I* N: H6 d7 r) Z; Q6 b
output mcasp_ahclkr,
9 J+ e) c' S" R7 @& V# Z8 toutput mcasp_aclkr,6 P1 w7 c" G& a' `$ I' d# G E1 b. G
output axr1,+ i6 _. N- G( B, ~. u5 z/ m
assign mcasp_afsr = mcasp_afsx;7 Q) S' h7 i" h/ ~3 k% S! U6 Q8 h
assign mcasp_aclkr = mcasp_aclkx;/ q; \' y+ `, z" s& U
assign mcasp_ahclkr = mcasp_ahclkx;
! l; e7 M8 `( @assign axr1 = axr0;
. u0 H; j1 C4 H4 ]
1 }/ T- i2 l3 d在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 ; t- J3 w2 ~: \2 V6 W, w+ `
static void McASPI2SConfigure(void) V8 B4 ?4 _. y% J: k) p9 z- g
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McASPRxReset(SOC_MCASP_0_CTRL_REGS);
# P3 ?! i, w- a* j2 M% v; v6 bMcASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */8 T4 Y& E7 v, L% D- Q0 I- J1 _# M
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);$ }9 m- t1 M5 y
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */% X4 b( \( W. w# j" ~ ~, F
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
7 s8 N7 F. D; UMCASP_RX_MODE_DMA);2 f# i5 D5 q& c: x5 S2 w* h+ z* \0 N
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 \& q0 t) L' D8 y4 JMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 J. J( b- y. i$ x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
# t7 s/ k8 t! R6 T1 A7 c8 HMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
3 e) W; L; q; _8 yMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, " u: ]1 p |# }9 {' t: l
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */) b4 b1 W1 m+ O, a+ Q p
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);. v# w+ g) C3 e( C- S; o4 x
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
3 K# u) d% r8 W6 {+ E0 rMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
' L9 O( k$ r. y$ K9 X0x00, 0xFF); /* configure the clock for transmitter */& [; Z6 J/ K w! L
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);% a# N8 {$ A! S" _! w
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- y0 d% n& J5 U8 i7 VMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,, [( t4 q5 ~! z d! j1 ~
0x00, 0xFF);2 d% C5 E+ z1 ~4 l) k3 w
+ i0 C( Y1 v7 a. r9 i# m% _
/* Enable synchronization of RX and TX sections */
- f& N2 S1 ]- |& U8 d6 vMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
8 v5 D2 l2 b$ ?; F' f) f8 RMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
0 |9 ]/ r0 g7 J6 k3 m/ P8 `) TMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
! K1 B& n" J+ f** Set the serializers, Currently only one serializer is set as
1 j Q$ Q# M: ?2 U1 R4 `** transmitter and one serializer as receiver.
' C+ s8 t6 \; |1 p' u*/$ p+ A1 ^( f. S+ C; U
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
4 L* v9 Y% v) H m4 Q) [; XMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*! }- }2 n% a) p
** Configure the McASP pins
/ b& T9 q0 b3 l& k! a d** Input - Frame Sync, Clock and Serializer Rx0 e6 b, B% D& T: d4 H$ o4 I7 C, w
** Output - Serializer Tx is connected to the input of the codec . U" f. Z# C% B( y4 |
*/
: _: W" p/ B& `, }% VMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& ~" f+ K1 @& _
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));% e& L; x! Q0 s$ m/ R) h
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
& ]9 \; J6 ?5 m. Q6 S o| MCASP_PIN_ACLKX" S- f7 F, n* }- T# d
| MCASP_PIN_AHCLKX x( w! u% v2 v' H
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */, [+ a2 [; h! D: B* i7 O; S& X; f
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
. K! r9 _3 Y! Z9 M| MCASP_TX_CLKFAIL
( v8 M7 W3 P# J7 A" P/ I2 W; ^| MCASP_TX_SYNCERROR; x. g+ g* G2 p/ l5 y$ G; N
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ; f# i4 f1 R$ u/ z% }, u
| MCASP_RX_CLKFAIL' G" X+ `& y. I' }' ?0 a3 z
| MCASP_RX_SYNCERROR
$ |/ j7 b; T a9 C2 A0 p| MCASP_RX_OVERRUN);# d: e6 o) X. d$ _8 q5 ~
} static void I2SDataTxRxActivate(void), M1 K! v0 t7 w1 y6 h: J
{" Z- u2 l# d: j/ D& N; W! y5 W$ [
/* Start the clocks */7 j* F* \ j* K
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);# }" `1 l7 U7 e( T
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
3 E5 S) a! h" V$ L" O! kEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
' O; b/ M, \2 B/ sEDMA3_TRIG_MODE_EVENT);
: e4 [- K& v0 M+ k) e g% OEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, 1 X _* j( b: {0 B9 H
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers *// V9 u6 C/ w3 D( ?
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);8 K# Z$ P" g6 u E
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */1 s0 c8 N; T Q% f3 W
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */
" f# ~1 f+ h p* D! ~McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
5 K2 C* Y1 g/ ?8 h. YMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);: i8 \6 c! O8 f5 A5 @/ ^+ Q. U
}
9 r' S. Z% [& F1 ]; R0 I! n请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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