我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,& j) i9 P5 G& R
input mcasp_ahclkx,% M: j' w4 m* A4 Y
input mcasp_aclkx,0 o3 f; y5 e- n6 t; ^% p
input axr0,1 P0 P: R& H7 |; O$ T
3 d$ {' E% _9 \5 Z5 Q$ _* O
output mcasp_afsr, Q! C0 J q/ ]
output mcasp_ahclkr,/ T1 Y$ Z E3 G/ o* S
output mcasp_aclkr,
' S# x5 W% e) z+ Moutput axr1,- q3 J% L8 e* R
assign mcasp_afsr = mcasp_afsx;
5 W$ J6 P# V- R. {, ]% Uassign mcasp_aclkr = mcasp_aclkx;6 [) l k7 O$ I- O6 m
assign mcasp_ahclkr = mcasp_ahclkx;
) @/ @, [; u- d+ C" jassign axr1 = axr0;
. n9 K! r; `- R
h. |' m% ]; i4 }% M. t1 y7 P" z5 Q在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
- Z" r6 \- c: U1 p# n2 Rstatic void McASPI2SConfigure(void): _; y; Q: b$ d7 G$ t
{; X1 d9 l7 O% k& D" V- D0 L0 Y2 Q9 p
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
( g+ _9 ^& v; _4 r2 k0 ^McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */! n, ~7 e! t: P9 k
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);5 ]5 t' T! f) X! g) `) H8 F
McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */: A# m( T8 \' R. l K; W
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 `; ~% v" z1 j/ [4 v
MCASP_RX_MODE_DMA);) S F! c$ W& n+ C( c$ X
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 G; @, E$ L8 a q" ^ {& ~MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */1 ?, i5 H }6 e6 q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
" O' [# W& }( |6 H7 \' V9 w9 I0 GMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 F7 k+ F7 k/ k% k
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: r8 w3 Y; z2 UMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */
2 z, J9 T. v3 v9 r- CMcASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
, ^8 {1 D/ Y- O& }/ C. JMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); + ^+ I) x v0 O0 p, R
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. Z- R7 k0 I. w# X2 n; C0x00, 0xFF); /* configure the clock for transmitter */
4 b& v) ^( F1 U7 |# z# mMcASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
/ t6 n$ P" Z6 Z: N5 k9 A0 cMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
7 P. C& B, _- `$ @$ hMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 h; r( P2 z3 a- X {! R5 ~
0x00, 0xFF);$ @; K* \3 i& V Q8 B$ n
' M& l# j9 E- e* P* Z- N7 k3 s; x/* Enable synchronization of RX and TX sections */ 7 P' P4 E, [) V1 w- D/ K
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 z; q$ l+ x, P) V7 AMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
; U0 W @+ o6 ]/ e0 X& Z) iMcASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*4 q9 b1 U4 w! I m8 Y
** Set the serializers, Currently only one serializer is set as
* i- s. @! ?! X# t8 }1 k: x8 b** transmitter and one serializer as receiver., o1 g$ |4 M5 s9 V8 T5 w% M% J8 y
*/
& q2 _& u% U1 m' wMcASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
) i! V! W8 B7 V7 e& z2 I8 ]McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*6 K8 h0 B, W& i- C0 c
** Configure the McASP pins
$ C2 t/ _/ t) G6 ^( f( m** Input - Frame Sync, Clock and Serializer Rx2 I$ E0 K, l' a B$ {- }0 e6 _
** Output - Serializer Tx is connected to the input of the codec
% ?& o0 d: Y0 T* P*/
: }$ g1 n3 H+ L- d7 X+ wMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);# A/ e4 x# Q- Y: W4 P+ a
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));5 p+ ^# [1 Q8 M4 M
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 c/ b' e$ M7 c+ v/ J& q
| MCASP_PIN_ACLKX' A9 L" S6 E' K( j" M. z, V8 j
| MCASP_PIN_AHCLKX+ o/ t% _- K4 g! T# n9 h6 P! |4 l
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
5 V) d j; H [) ~McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
1 g1 r5 b( N% q0 ^3 f' l; ^| MCASP_TX_CLKFAIL - c* b5 D4 U3 @0 g
| MCASP_TX_SYNCERROR2 p M- O2 }( q- [9 E$ s0 [- V
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR ! \/ k( T+ Z5 K
| MCASP_RX_CLKFAIL* v. G3 @1 W5 O
| MCASP_RX_SYNCERROR
9 @0 ]$ q+ |/ K7 C% Y| MCASP_RX_OVERRUN);1 M# l! i) z ?$ x
} static void I2SDataTxRxActivate(void)
7 v5 S4 S' L" e" |3 c: q5 K{
1 a+ m- g0 r( a/ w+ Z2 N/* Start the clocks */1 [: B( m3 b- g# T1 n' s: g
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);, C$ p( q/ a/ Z5 I$ |% D
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
# `! \0 |) q! W' I4 M9 _# N- M) E: m, HEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
0 P7 s( y% y' h, v. f1 PEDMA3_TRIG_MODE_EVENT);
% n0 E' }: N9 U" t# F0 xEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
% T" V7 R" q- p3 CEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */; B% C7 w$ y9 T, ^ i
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% h- u. Q- ?( ?, [" A/ ~$ b4 {9 ?McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
3 N; c7 @; w8 Z4 Rwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 `& _( |" N L! N# Q) Y7 h& G& ?
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
- j* X3 E' F3 K6 A) RMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);
* ^ `' G! [6 K W} ( W' i% G6 n" ~5 s
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. # |$ l4 Q( j. \3 c9 q7 k
|