我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,' K3 M3 M, A6 _, q' X) x2 V
input mcasp_ahclkx,
; k- C! M8 ^" Hinput mcasp_aclkx,: A$ B2 L/ B+ N2 y$ ?
input axr0,. ^8 r- q" ]) n* g8 E
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output mcasp_afsr,0 q% e" M& ^% X
output mcasp_ahclkr,& S, b4 C: A: v4 C
output mcasp_aclkr,
5 r4 e7 r$ x6 ^output axr1,! A( m% ^% X8 D- D k
assign mcasp_afsr = mcasp_afsx;
% _" ]$ j5 ]. ^* Q! Q9 l# S/ p( massign mcasp_aclkr = mcasp_aclkx;9 v6 k1 f( B. _( n# ~/ m3 E
assign mcasp_ahclkr = mcasp_ahclkx;
; ^$ N. h; W- t- V& _* Jassign axr1 = axr0; ) j% T$ I8 }! h% U! E* H
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在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 4 c( r& Y! ^8 m# _' ?7 G% M" X
static void McASPI2SConfigure(void)1 s4 J4 t% v/ A$ W2 k
{
2 x& Q7 b$ b4 f1 c \; u8 G" uMcASPRxReset(SOC_MCASP_0_CTRL_REGS);
_; F2 s3 K- l @McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
6 Z: p% q0 t. C6 hMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
1 E! J1 O" L. L4 \6 U; R" hMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
6 p. x) r1 H9 }8 aMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
4 ]# D' V9 w( T0 r7 ?' vMCASP_RX_MODE_DMA);
3 |! F9 F8 c0 I7 k; d+ S% e+ q! ?% jMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
* b! j2 M0 Q( |3 ^) _$ j% aMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
" N$ K+ s4 S8 u* DMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, # j5 Q: p& Z6 d3 a# V" c
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
4 O5 L# a+ I2 B+ G, h- aMcASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
: a( l8 Y# S, r; ~' ?MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */3 s6 Y! s' T) n5 n4 s
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);1 A2 Q* }3 K9 v5 D5 ]. o9 v' C6 L( z
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
4 D+ y' g2 N" mMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32, C3 w! ?+ r `/ ~, g$ E6 Y
0x00, 0xFF); /* configure the clock for transmitter */4 L0 O/ T" G. _# _7 C& t
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 a7 g$ A& J5 k9 z5 G' d- [7 l
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
- g1 D, k3 G% V3 R" u/ ZMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
- {' V% C, P/ o H0 y. Z0x00, 0xFF);- |& y) Q0 z4 H0 Q C
# A/ s! i. b4 o- N( v) X
/* Enable synchronization of RX and TX sections */
' `( H% p* d: ~, x% FMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
3 c$ F+ I% [4 S4 Y; O' R- yMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 }8 d; @5 S% A8 T8 J) @
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
/ V5 n" ]5 |+ r% H' B** Set the serializers, Currently only one serializer is set as7 f, U4 _; ~3 u
** transmitter and one serializer as receiver.
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McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! f7 y8 {5 R, r1 t( }5 F7 hMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*) e4 d3 }* d! ^7 n y& P: b
** Configure the McASP pins 1 ?* P. @% [; L3 q9 n0 p3 z% W7 u
** Input - Frame Sync, Clock and Serializer Rx6 Q6 ?& S) x }, }% B; }! O8 R
** Output - Serializer Tx is connected to the input of the codec
0 }. S$ _# G# A*/
' j/ u1 h( |: A$ k# b0 x2 UMcASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);% `: z1 f; q$ l6 _- c' _. N
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
$ h3 x( l6 D/ ]McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 O1 V0 O1 f. h- X
| MCASP_PIN_ACLKX' ]3 j9 ^) I" V3 a
| MCASP_PIN_AHCLKX
4 i; h: h$ j& a. w5 J0 o" S| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
N' u- u- r" g* V7 p) qMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR ; r6 ], j' M2 L9 p% ~& h
| MCASP_TX_CLKFAIL
6 d7 B+ k' J% d2 R/ k! B| MCASP_TX_SYNCERROR
8 J) U* h5 d0 z% e" W+ ]| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR + ?2 I/ x$ ?2 i; x/ b. I+ s2 X
| MCASP_RX_CLKFAIL
" g) q& g+ K' l| MCASP_RX_SYNCERROR 0 F* c: [9 D6 F# _# V1 K% q+ [1 t9 c
| MCASP_RX_OVERRUN);
" |7 ~0 E3 u7 P/ M6 {/ t} static void I2SDataTxRxActivate(void)
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/* Start the clocks */
6 c: N/ O1 w6 fMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
' u& ]6 G4 s4 wMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
- L; }( O5 ]' d4 LEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 F U! x1 ^- b9 j
EDMA3_TRIG_MODE_EVENT);: z* X* _, B4 r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
. ], M. s' X' T8 y5 i+ @EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */. d! C' k, H2 @, |6 `
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);7 V+ ~& o: h* N
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */) W6 W0 q1 H. X
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */0 E ?* o$ ^" X* q5 {) |2 f
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);# Z( n- F$ D1 Z# K) U
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
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请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
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