我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,- Q8 B, ?* R0 p3 q! ?# o( i
input mcasp_ahclkx,: _9 s" n" i. C
input mcasp_aclkx,
9 d9 N: r# {/ x2 f$ ?input axr0,
+ z0 P0 S' ]9 c: P" t A' R8 Z+ t3 m- t( e% `8 `
output mcasp_afsr,4 Q+ Y* _" E( Y# Q$ [0 ^3 {& Q0 `
output mcasp_ahclkr,
8 C, ^, _# K+ _6 U' a/ W6 u1 Ooutput mcasp_aclkr,
0 \2 h% x8 }' }% y. Z7 `output axr1,9 f6 B" J7 U# }; t
assign mcasp_afsr = mcasp_afsx;( G$ k2 g, v& H" T; s! ^8 s
assign mcasp_aclkr = mcasp_aclkx;0 Z1 M2 w+ T! y. f
assign mcasp_ahclkr = mcasp_ahclkx;) ~" S$ R9 |# {. U. M$ Y) O, K
assign axr1 = axr0;
8 Z+ q t. _6 f, Y6 z) x* ~+ l5 V! j c+ f
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 " o$ k* u8 g- ~/ P5 x
static void McASPI2SConfigure(void)$ S+ P2 g$ w4 t8 Y4 s. @
{" Q7 x4 m8 B8 s% A# y
McASPRxReset(SOC_MCASP_0_CTRL_REGS);6 ^4 l+ \& U0 }
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
' F8 w; W9 A5 a# yMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 c6 Q0 \2 U- |1 B$ LMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */- f; D. k2 f+ [; N4 u
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,' f7 E1 t# t0 c {) a
MCASP_RX_MODE_DMA);
" g% X/ f+ o; LMcASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
+ O! {- |6 ^% ~$ D' @, ]MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */
% g0 q- J" ]1 e @$ E* H3 ]' IMcASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
. W) J) q' s2 d7 O/ VMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);+ m, x8 m- V/ Z3 j6 O8 f$ }
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
7 J; F; c5 `9 kMCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */5 _3 f: d; \& f5 y6 X
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);$ a$ \6 R* {. v7 ~
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE); 9 J1 q+ Q! x0 j
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,+ ~ z; y$ f6 t
0x00, 0xFF); /* configure the clock for transmitter */" _* R, I7 w1 o1 R% z/ @! ~! r
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);8 N( U) e- p) X$ m P: u+ I! H; ?
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
T) t. F7 u( i; D4 ^/ l; D! FMcASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,* u+ p$ H( l3 A' T
0x00, 0xFF);
* H5 t5 a8 x4 W4 Z0 f2 `& r1 t# M3 r. `
/* Enable synchronization of RX and TX sections */
3 J; i* X6 c; VMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) ~+ |" D' ^, v, j: q" y0 C: P
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);) Y/ u3 m' o) D" i
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*
8 \' H' U5 @1 _, d9 l" q l** Set the serializers, Currently only one serializer is set as% D1 S( @5 S _; p5 n4 h
** transmitter and one serializer as receiver.
. o2 i6 O( X7 q4 m*/( Z5 c1 T+ u4 B' B4 M* m# W
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
! t1 x, g& J3 X, SMcASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
z% c9 C4 e. M+ k; P** Configure the McASP pins
' M2 h# x% D% L% P7 X** Input - Frame Sync, Clock and Serializer Rx a4 k; K$ B4 P
** Output - Serializer Tx is connected to the input of the codec , e& \( l! b0 c( u
*/: G* s/ M8 z- a( _; _
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);8 A) s" V+ F, Y; t; X6 x) }5 Y
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
2 M& M/ S9 e& P: I9 _2 kMcASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX
4 Q1 ?" L( ^9 ^0 T, P' U| MCASP_PIN_ACLKX8 w/ E1 X r, R( u: f. e
| MCASP_PIN_AHCLKX6 T* y' P& n2 R* f( `+ ?6 F7 G
| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP *// ]4 r$ d8 C$ q0 m: f+ g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
' i: P% z5 k1 n' ]4 h* {) i| MCASP_TX_CLKFAIL
' A6 [/ ~* [* R. b, i| MCASP_TX_SYNCERROR; |4 R y1 v0 L
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR 8 p6 R+ M2 w# \: K' ?" }
| MCASP_RX_CLKFAIL$ d2 S0 _0 s8 V1 f4 T, W
| MCASP_RX_SYNCERROR % v5 a. t2 x( u! R! V2 k
| MCASP_RX_OVERRUN);; {" y" I; J5 f% |7 \
} static void I2SDataTxRxActivate(void)8 |& Z) n4 K. W: u( P
{1 }" T2 a* ?# _; z
/* Start the clocks */
+ S/ Q; p+ l; a* n' p9 oMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);" I+ k, {# J) | z( u
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
8 n4 d7 R& \% b: N5 A2 wEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,& ~/ f! R. w" L. o7 N/ X6 Y
EDMA3_TRIG_MODE_EVENT);
) w P5 D$ E; Z8 H+ L$ tEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
5 M; u: Z+ _, A0 C$ r9 {EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */
- R: u- B7 Y8 E1 z; X* {4 dMcASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);& t0 x: r) f( _( j7 w
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */
. |$ t5 g! _4 [7 \& T4 Nwhile(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */# c R. n) `$ M7 ^- D
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
% n1 P6 J3 {( y* E6 D3 a# IMcASPTxEnable(SOC_MCASP_0_CTRL_REGS);) X8 B. P$ B- Q, J
} 5 N# G1 U+ ?2 S+ ]5 W/ R
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. A9 o0 @8 T( L! X G9 X. z
|