我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
$ ~% V- M7 ^6 e" c+ C! K2 ~input mcasp_ahclkx,- i5 F) w# y$ K$ H
input mcasp_aclkx,1 f- |3 w( `' ]+ B+ v% k" N* e- @" W
input axr0,. ^6 X- g) p5 U8 W0 P! H, C+ V
F' p% j: \: Q9 k( moutput mcasp_afsr,) f8 `8 o4 y# F# _ h
output mcasp_ahclkr,
& f5 w1 `( z* ?. Poutput mcasp_aclkr,6 V9 D, w# o/ I, H8 z- b+ m
output axr1,- C; g, p9 i4 Z0 A# j3 S6 y5 B) P
assign mcasp_afsr = mcasp_afsx;
) h: \$ V3 P2 k. f2 J5 s0 Q, Bassign mcasp_aclkr = mcasp_aclkx;
! P7 W# j* Z9 P2 A! |( k; rassign mcasp_ahclkr = mcasp_ahclkx;3 q' L) f, \. A. z7 x2 T0 }
assign axr1 = axr0; % N: l! G: t F7 r# y l" t
% H* b7 ~1 r1 J- a" m6 K
在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。
/ \. o$ B. J. O- i0 Istatic void McASPI2SConfigure(void)
7 }/ j( S4 c& }0 W{
0 b0 g) G& `$ m+ YMcASPRxReset(SOC_MCASP_0_CTRL_REGS);3 F( d4 x& K3 f" Z3 {: P3 \
McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */7 |- e% W* c. q! N5 I: z7 P
McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% t) v! t3 o% c3 y; ?1 o* zMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */
2 T! q6 H" Z7 a2 M& CMcASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
; {5 z D6 i; D# b2 `MCASP_RX_MODE_DMA);
3 h4 x$ l7 v3 Q s) ?McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,8 ~& D. i4 R8 k) [
MCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 n( Z$ M, x- N/ q
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ! k& M& u& `+ ?; S* p3 ]$ s
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);; t( l+ F) }2 I' W5 j* H. l
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, / N6 x7 ^/ k6 N6 p
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */- D7 v7 I7 ?1 j T ~! }
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
1 K/ z: L# q5 N8 P* ?1 z0 E! TMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
5 V+ K8 K% {( p' E4 m; x5 G& g$ `McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
. N9 x J2 ^/ V5 r0x00, 0xFF); /* configure the clock for transmitter */9 B8 [5 w) x! W5 Z+ K
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);$ M$ D4 Y+ n ]
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) @/ W0 t q% L! h2 h% ^McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
; `+ b( G H. ?0x00, 0xFF);
- F; w6 o' ~) Y, E- I; P
- V: x, s* F) p$ N4 C' S+ ]( J/* Enable synchronization of RX and TX sections */
+ K H. d" p" k! m0 o8 TMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */
, H- n$ [8 `* H9 w% VMcASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);3 p4 |; N+ h4 A u* U0 F C3 Q+ R* z
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' n; P) ]* K) N0 @5 j1 n
** Set the serializers, Currently only one serializer is set as
" T+ X9 Z' K5 Q** transmitter and one serializer as receiver.2 \/ {1 a0 \3 k* {) u
*/+ M4 F5 L- j. E3 f" i
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
9 Y2 E9 Q# T4 R7 ^; ?McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*3 P+ `& H, Z" J; t6 h) z0 u
** Configure the McASP pins
% ^0 ^; {1 t, h** Input - Frame Sync, Clock and Serializer Rx
3 Y% z$ D7 E6 X; ?9 P2 f** Output - Serializer Tx is connected to the input of the codec
2 Q% u! [# P" l% C Q: v/ y*/
5 [# a" P8 m3 E$ I' {McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);& D: ^* B r b$ Z# t5 h
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));
g( m6 x A0 ~- T% @McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX2 l2 R# f; v" R% u) {; w! ~2 H/ ?
| MCASP_PIN_ACLKX
- w+ d( `/ g7 b| MCASP_PIN_AHCLKX
" [; u& T1 a7 e| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */
) ]6 s9 i$ t8 f- i/ X- HMcASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR 6 R* w; X, M: n
| MCASP_TX_CLKFAIL
: H ?: n6 y( p) c| MCASP_TX_SYNCERROR
5 r" R5 c$ w8 Q! U, v4 g/ R| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
5 J) F' r, O/ g1 _| MCASP_RX_CLKFAIL% j" t9 o, W' N/ ]
| MCASP_RX_SYNCERROR 3 M6 G: y" {3 s' U1 b+ k
| MCASP_RX_OVERRUN);
$ K: _6 O5 g1 S, E' q8 R} static void I2SDataTxRxActivate(void)
7 s1 u: R, C4 u) M+ n8 q& u. H& ~{- ]( |# G! E( w$ g
/* Start the clocks */) n$ K/ s* a6 Q4 Z; v3 A
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
) m. _1 c2 {; o/ TMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */+ r2 S: R4 h+ _% Q/ P! p+ S1 |! \
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 X& ]) U" M4 c, h
EDMA3_TRIG_MODE_EVENT);# O5 _. Z7 W" T$ i! ]
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, - m+ O8 @" N6 j
EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 R6 Q7 x' F, D) Q8 s6 P
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
( L1 `: w0 W% A, ^3 H0 vMcASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero *// b0 i* |3 m0 u# `: B) @1 P2 Z
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */5 ~- D' f6 O: C/ U
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; o, a9 I( e" D5 }6 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
: d: |& _/ P; ^3 M}
6 ]6 i1 n( R2 Q* P S6 l% }请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0.
' O2 {) i- p7 Z8 H: }% L$ U+ I |