我项目上用OMAPL138的板子MCASP的引脚都是链接的FPGA,所以在FPGA这端设置的MCASP自环。把axr0接收到的通过axr1发回去。 部分代码如下 input mcasp_afsx,
: Z$ M/ k8 |/ Cinput mcasp_ahclkx,
: N0 X4 ]" [, f* ^input mcasp_aclkx,* R4 `% n. |& {+ a$ A( j$ q
input axr0,! p4 O! b" n+ i( N5 l/ g" w7 Y
' D7 C/ a/ c0 w* E
output mcasp_afsr,
7 A$ h! `9 f! C7 A3 ?output mcasp_ahclkr,
6 U' E% g0 U! I7 J, Zoutput mcasp_aclkr,
- }5 O9 [, z' J7 doutput axr1,# e# ?# a2 g2 v
assign mcasp_afsr = mcasp_afsx;7 X0 L C- T7 Y; C
assign mcasp_aclkr = mcasp_aclkx;
- O4 S5 H7 }2 w# r! C" `* Fassign mcasp_ahclkr = mcasp_ahclkx;- T0 }/ L) Z& Q* w1 B+ }* P
assign axr1 = axr0;
/ v" }: L% O, M* M; L
7 l) U% j. |5 ^( U d$ ]/ }1 i在OMAPL138这端,通过axr0接口发固定的数,axr1接收。 在配置MACASP的时候,发送全部取内部时钟,接收全部取外部时钟。 一直循环发送,但是接收不到。在FPGA端也没有看到时钟和信号的波形。 部分代码如下,关于edma3的部分未做变化。 2 Q1 W1 H% G8 j" {
static void McASPI2SConfigure(void)' C0 O9 Y; r% u9 j
{
6 R. v# |( ^) s$ }McASPRxReset(SOC_MCASP_0_CTRL_REGS);
; }, _3 U4 f' L9 v% _McASPTxReset(SOC_MCASP_0_CTRL_REGS); /* Enable the FIFOs for DMA transfer */
- N6 u. I+ G" N6 qMcASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ ?2 F( t2 O! D' @4 X/ Q* ~3 o* pMcASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1); /* Set I2S format in the transmitter/receiver format units */9 q. t# Z, H1 h$ o: H& B
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
/ N( @3 t1 _ X8 sMCASP_RX_MODE_DMA);0 h& h: D' r4 f1 m; F: ~; O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 c) j; V' }' V, P6 {) pMCASP_TX_MODE_DMA); /* Configure the frame sync. I2S shall work in TDM format with 2 slots */" D1 k# r( o8 v/ Y/ M
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
( M9 L- L2 U5 O. P1 F, OMCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);8 L# J2 o! i/ P! w$ D9 |. b
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, & _1 X% ]8 l( n. g0 F
MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); /* configure the clock for receiver */' g. _% N$ j* r- ?9 k& j
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
4 x" Z" @: p& H9 FMcASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
& W) S5 o& \* i2 d. u" s7 vMcASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,0 K& I+ Q, D- F5 s' P
0x00, 0xFF); /* configure the clock for transmitter */6 R; B; d% S- P3 c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 11, 1);
" \4 n6 ^0 M+ r. XMcASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE); L, h" n* }# Z/ Y$ t. g3 X1 z
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
9 z, o4 c/ ]+ Y h; P) a0x00, 0xFF);
2 y7 `! Z+ \$ l" C- u/ U: W; X) `8 h4 `6 N( y% s
/* Enable synchronization of RX and TX sections */
4 [6 |8 U& o% c3 Z6 J1 K( UMcASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS); /* Enable the transmitter/receiver slots. I2S uses 2 slots */) u9 L4 b4 d# x9 l e: K
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
- r4 f# f$ u4 q) w4 j# _McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS); /*' y9 o: C# S8 B8 \: b0 M8 \3 K
** Set the serializers, Currently only one serializer is set as
% H4 }+ R) M* S3 \8 c# S6 E** transmitter and one serializer as receiver.4 m6 F! Q( `! a3 @
*/4 W9 O- d% ?' c3 d) i/ {( l
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);0 Z3 _9 D. m% d
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX); /*
8 e+ X, ^% h4 N8 K** Configure the McASP pins
2 p: V' r( \) |/ ]- x6 G** Input - Frame Sync, Clock and Serializer Rx8 p) k8 ~/ E$ v" Z$ L6 P
** Output - Serializer Tx is connected to the input of the codec
; n6 ]. f6 z- U*/9 F8 U* V) c! L, D
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 E% c: w$ G2 c' k8 @0 u
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,MCASP_PIN_AXR(MCASP_XSER_TX));8 T- Y* w, ?3 M- [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS, MCASP_PIN_AFSX9 h8 n2 ?% I8 I% y* u0 v
| MCASP_PIN_ACLKX
8 o$ b0 R3 K! O| MCASP_PIN_AHCLKX
" V. N: J5 i: i; V# I) b# e1 T| MCASP_PIN_AXR(MCASP_XSER_RX)); /* Enable error interrupts for McASP */! H @3 w- ~7 b* b% {# y
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_TX_DMAERROR
7 G% o$ y; T I3 a$ C( K4 \| MCASP_TX_CLKFAIL ! k! h8 X( R4 J1 O9 }! P5 q
| MCASP_TX_SYNCERROR( x- H \4 u% z
| MCASP_TX_UNDERRUN); McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS, MCASP_RX_DMAERROR
% ?1 v" O/ A4 || MCASP_RX_CLKFAIL
~% r/ q/ s. V9 C| MCASP_RX_SYNCERROR
3 a$ R0 W& s+ A. i$ b) K6 `0 \1 @| MCASP_RX_OVERRUN);4 c! ~& b. z$ H7 F4 Z5 m" O
} static void I2SDataTxRxActivate(void)
1 I! k! h* M, S# x, J( T{7 B, G% K( O' Y) o
/* Start the clocks */
% [ } ]& q, ~, r# S6 LMcASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
^* B2 x. T( E, eMcASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL); /* Enable EDMA for the transfer */
/ B3 S( D l1 g: M9 N( w0 WEDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
4 l* K/ K' w' OEDMA3_TRIG_MODE_EVENT);# I) A2 h& s2 t4 w: r
EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
D2 ?$ `' C+ gEDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT); /* Activate the serializers */8 W2 V, D& n6 e( Q8 D
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" J$ q0 @' h! X+ ] p. @ w% V
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS); /* make sure that the XDATA bit is cleared to zero */3 J) R# R% L) h/ L
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY); /* Activate the state machines */; @+ o' o# I8 w9 |! e, q
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
+ a2 d. h0 y( e9 O/ L- `McASPTxEnable(SOC_MCASP_0_CTRL_REGS);- ^+ e# g, ^1 w4 g) ^* M
} 4 {0 w. C! g. D1 N( O
请问:问题出在哪了,时钟按照这样配是否有错。 另外我看XDATA一直是0,接收的rxbuf0,1,2里有一般全是FFFF一半全是0. ) j# U& Q# L: O. i0 G5 o8 {9 _
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