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我的McASP配置分别如下:
! t& _3 x1 T" K/ C8 d' @管脚的复用设置是:. X% p8 I6 x. \9 P1 y9 n( T
void McASPPinMuxSetup(void)
/ [4 o& w% u# C{9 d1 q- a6 d% H# Y
unsigned int savePinMux = 0;
$ F4 l: `% o2 g n0 ^! g. z2 K savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \. t$ y5 ?1 v, D) c
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
6 J5 |) s2 U( D3 {+ ^ SYSCFG_PINMUX0_PINMUX0_23_20 | \0 K% a/ r0 r3 _5 I) V
SYSCFG_PINMUX0_PINMUX0_19_16 | \
, z) b6 I! L& a' J- e SYSCFG_PINMUX0_PINMUX0_15_12 | \
: e% P/ ?+ n; x5 X- v SYSCFG_PINMUX0_PINMUX0_11_8 | \
2 b. E/ Y5 X" v; s7 x+ d( f SYSCFG_PINMUX0_PINMUX0_7_4 | \
8 F. l, I/ n; d- x SYSCFG_PINMUX0_PINMUX0_3_0);
* B+ U# a7 u( `! t& Q5 j HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
( B- |$ \% t" ~' l1 E (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \! u8 u) v; E+ r+ r
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \, X( | f5 e7 U
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
( {! V2 e' P6 h- y PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);3 O' G3 T3 F6 U! A7 u: t
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
3 P# ~! r/ ]0 r; p6 Y7 c& Y ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \( e, _& |: I3 s+ k; i
SYSCFG_PINMUX1_PINMUX1_15_12 | \
+ I5 T; \: g" r0 D- q SYSCFG_PINMUX1_PINMUX1_11_8 | \6 x2 [7 _- i; y' ^* {
SYSCFG_PINMUX1_PINMUX1_7_4 | \5 j# A6 a5 k+ B: W( W
SYSCFG_PINMUX1_PINMUX1_23_20 | \1 u6 ?- {+ m3 p' t
SYSCFG_PINMUX1_PINMUX1_27_24 | \
' g8 i8 r* R0 o3 N2 Q SYSCFG_PINMUX1_PINMUX1_31_28
& u& ~4 q2 W, X; J! S: ^ );
% L( G3 T5 H/ v; S HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
3 P5 b" ~5 H* [5 J% A (PINMUX1_MCASP0_AXR11_ENABLE | \
4 M5 }- {! d) T3 Q( @& y0 A$ Y PINMUX1_MCASP0_AXR12_ENABLE | \
$ F7 t; [8 ?8 }% h" | PINMUX1_MCASP0_AXR13_ENABLE | \% Z9 w6 i' H+ v; C* n
PINMUX1_MCASP0_AXR14_ENABLE | \/ h; r' N+ V/ q( k( Y; g; u
PINMUX1_MCASP0_AXR8_ENABLE | \
, W, j! t5 W! e$ ], _# e m3 z PINMUX1_MCASP0_AXR9_ENABLE | \
$ Y0 z+ Z) x9 _ _% {, H" \ PINMUX1_MCASP0_AXR10_ENABLE | \, I$ _* J" `. j' y
savePinMux);. J. p* l8 L" n5 E3 x
}
* Y5 H1 u0 A0 c, [7 y
2 `% H( G$ l( G; ~: c) G% J9 u1.McASPI2SConfigure(); McASP的配置程序如下:; `- o) E/ |% C
static void McASPI2SConfigure(void)& q' c. A! x6 L( c1 p: O
{
& T& b" e' L9 O& \: R8 s McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 C8 w/ \4 k- @ l& g; A McASPTxReset(SOC_MCASP_0_CTRL_REGS);
. n) T9 k6 C% ^' W+ l# p9 B4 S2 I) a$ a% R# ]
/* Enable the FIFOs for DMA transfer */
) ^# H8 j3 o4 L4 M$ {// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);# R6 O, q- B. l5 m
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
% B* N& v$ g8 f( V# i3 ~: L' m/ U! m/ m
/* Set I2S format in the transmitter/receiver format units */* T" K& {" w# y* ~9 _0 v
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,) a# m0 G' u& ~6 P, d. i, J5 f: b
MCASP_RX_MODE_NON_DMA);
( Z9 M- u0 M" ?& t5 c% E McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
! I4 ^+ J B- o, N MCASP_TX_MODE_NON_DMA);- O# Q: n5 m6 J/ h
, t; ^) _$ q; U& q) F! t i7 \4 ?
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */) r$ l' Q% x( F* p7 v* I( d- U4 S
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, ) q0 P n& r' m, D& V% E+ O, G
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
) R5 t! ]9 u# f McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
3 i/ x1 o9 @/ h* L+ Y% ]: r2 r MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
& M( r% A3 o& W7 A
: m) K/ [: ?3 o8 [ g6 _+ H3 j /* configure the clock for receiver */2 C) ]' w2 N j h
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u); X n' R: n0 h/ n
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);+ ]$ i3 n1 B& r. g" E
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
9 @" [7 c4 K- f6 _8 {( v: n McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,% K5 h% ?; _0 P. U" x
0x00, 0xFF);/ I# A; _( }6 }1 y/ H
9 R! [4 H& n9 Z+ [0 F g6 u9 T /* configure the clock for transmitter */$ t" v; A* \" h/ r/ q. u
// HWREG(0x01D000A0) = (0x00001F00);
# [" C9 J- v+ G' r9 Y. M- @3 h! R// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);3 w! G! z- H; \1 B) `
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
3 ^# b8 L) m* m8 z McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
% }; D7 E+ s! I7 k1 u$ t McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,1 p3 f0 l, b$ W6 D, W) P
0x00, 0xFF);* P* a6 R$ ]* K: B: p+ f" l s
- m" s; e9 z4 I9 J, ~3 m' i /* Enable synchronization of RX and TX sections */
0 E- m* M9 M7 r- q$ ^ McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
, T l% j' v0 r/ \4 _& Z% D8 V4 Z% w: H, M
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
; g2 U! O4 H. b _( _ McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);6 G7 n5 X3 k0 D o) a0 t! }
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);9 ?4 \4 Z3 G7 k: `5 d
7 {7 ?/ G A" s5 Y4 h /*
& X+ u% Z9 z5 q ** Set the serializers, Currently only one serializer is set as% B% I7 M5 y5 l
** transmitter and one serializer as receiver.
1 D/ C) b0 E1 V, o/ E/ R */
# O/ s; ~# D. R/ w3 c McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
$ Z5 R3 X2 A C7 c9 }4 \& l' F McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
% V' E# s' D5 B% K7 G' y7 v# @ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);: p3 {7 z8 g6 b$ `
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
/ \; H& e7 f x8 D0 n8 F McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
9 E1 H! D, t0 ^: `" D. F0 }6 O# ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);9 ^/ @) ^# h: ]- P+ H1 U2 U
3 k8 _: [ [. y6 T0 [! h McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
/ X( G' ^! P+ c! [; {/ c# i. n- l" x! E# p
/*# z) v$ z, A) q
** Configure the McASP pins
% D! d7 x( W/ [* M7 e5 o ** Input - Frame Sync, Clock and Serializer Rx
/ {) @: y+ m& \0 d8 S5 l5 r ** Output - Serializer Tx is connected to the input of the codec
. v) y6 o/ k* I0 q3 ` */
( P U* e; E/ Q6 ? McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);( G N; E. ~6 Q0 O+ o
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,' G% @- V* ?+ ~# f4 w4 ]
MCASP_PIN_AXR(MCASP_XSER_TX)# X! o' W) o+ L
| MCASP_PIN_AMUTE
- Z4 K& N! k9 R: F, x: g );. G' r3 |6 T; e& o) ^6 H+ E1 \, [
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,$ R! g% [! h0 O9 h3 t6 R
MCASP_PIN_AFSX* e. e; u' |- N. j. t3 c/ a5 B
| MCASP_PIN_AFSR
! l' g( G1 B0 ~, |6 d3 @ | MCASP_PIN_AHCLKX/ `, v7 D) N5 s: _- Z4 `, R
| MCASP_PIN_AHCLKR
, t! r- S6 H5 M9 P7 [ | MCASP_PIN_ACLKX0 m w/ M1 d$ v" W* U% N! B2 h
| MCASP_PIN_ACLKR
( {* }& J/ I a | MCASP_PIN_AXR(MCASP_XSER_RX)3 J% [9 D0 O3 _' {2 ?" q! L
| MCASP_PIN_AXR(1u<<(13u))1 B3 K. h5 v9 o& Z
| MCASP_PIN_AXR(1u<<(14u))
2 q! q r' }- O! j | MCASP_PIN_AXR(1u<<(8u))
" A1 N8 s. n" ^2 \: W* G | MCASP_PIN_AXR(1u<<(10u))2 r. m5 c, R' Q3 k t9 B1 O
| MCASP_PIN_AXR(1u<<(11u))& S- Z2 s& d* h) v/ \- H' ]; x- \
);
9 M* c5 V' @, O' P- n1 S1 q' ]# F# W) b. S, M; G$ j+ N
/* Enable error interrupts for McASP */3 ~' [, p# @+ ]* x, U8 n% c. I
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,: _7 L( A/ c2 S
MCASP_TX_DATAREADY
6 Q7 ^) z3 I- Q/ h | MCASP_TX_CLKFAIL
7 ~" b: e' c" H( A. N1 V+ X' x: m | MCASP_TX_SYNCERROR) L* P t& V/ Q! _ w* S
| MCASP_TX_UNDERRUN);
* n( T( x5 a T6 n: Z2 L' I. g' L8 g8 x9 { I0 h
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,( w% P) f& m, o; X4 C! @
MCASP_RX_DATAREADY
: p) N' p+ m \0 v5 V Q | MCASP_RX_CLKFAIL
2 @1 l4 ^0 }# I0 Y: [ | MCASP_RX_SYNCERROR & K7 l( K" l/ o% h* i' \
| MCASP_RX_OVERRUN);
" R/ G. Q, b2 V//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
4 A9 G0 K' l) l; ~7 }5 q3 ?. q1 d) h6 m) t
}) z6 F' Y/ w: N% }0 D) M
9 e9 C! X% `% Z8 k' p
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
4 x6 G+ K0 A" Ustatic void I2SDataTxRxActivate(void)" U Z4 \5 X8 c, p2 N. v
{
+ J, Y }7 k" c+ k# T. u. [ /* Start the clocks */! f7 m1 X/ U0 w$ G; y! b. Z7 B9 ^+ p
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL); @/ @; _0 `' Q1 s
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);4 t: A% s8 O7 f: M! d% j5 H
7 f$ C" X$ v6 S# `0 N ^3 V
/* Enable EDMA for the transfer */- M+ `( {3 Q% f8 \
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,7 U/ P) O+ C. V
// EDMA3_TRIG_MODE_EVENT);1 k3 N" R G$ s
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,9 s4 V( d( Y* t
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
# S, z3 `! ^9 q9 A) }4 J: b. Y E# \ /* Activate the serializers */
0 N8 T8 d5 J$ l) \- { McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
% }4 H4 R; @2 C( U3 h/ }/ o McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
7 n5 G5 }6 } z. g /* make sure that the XDATA bit is cleared to zero */
6 ]# n) r# m8 v( v1 { while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
3 S2 }* U- I( \& o /* Activate the state machines */
# s$ U% L0 z, _8 M3 f( x McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
. ~- u' [: o1 H s& E McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( }6 v! a9 B7 B McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
: q0 S6 F/ `/ e' A' x}
, d7 d5 b, a m8 M* g4 `; }' E# c" `; {
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