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我的McASP配置分别如下:) H- n8 Q7 A5 c; j' v, m
管脚的复用设置是:
1 b R9 x" A1 S# ]& zvoid McASPPinMuxSetup(void)
- X9 j" v U1 }{5 T+ J: X( e0 y: M- y$ K0 i+ d5 d' a
unsigned int savePinMux = 0;2 X8 v; h. s, F# ]. a
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \/ s1 y1 S3 j0 }0 N9 r8 n
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \, f" |5 h3 u7 D" e5 o6 O
SYSCFG_PINMUX0_PINMUX0_23_20 | \
$ A" R* G/ u, c8 e$ D% Z: X: s7 N( h' \ SYSCFG_PINMUX0_PINMUX0_19_16 | \
' R; R( X5 \# | SYSCFG_PINMUX0_PINMUX0_15_12 | \
: _9 Q/ C2 l3 S; L* Z SYSCFG_PINMUX0_PINMUX0_11_8 | \4 b# h1 f+ W1 x- x2 W' u
SYSCFG_PINMUX0_PINMUX0_7_4 | \* O- G) `: D8 T/ s
SYSCFG_PINMUX0_PINMUX0_3_0);
% |/ I$ N* X& O# b HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \% ~ y0 l7 S- _$ X. o
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
0 _3 |1 b$ V" _) j: Q" a5 r PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
6 w) L3 g" `: ~4 } PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
8 Z/ X1 W0 z. Q% H( G. K9 R; H PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);6 y, b6 ]0 ~; E( M
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \* g. R5 ]6 S' G$ j
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \3 {" i$ M% U" X3 G D- L2 S% s
SYSCFG_PINMUX1_PINMUX1_15_12 | \
: e7 t* L) ` i1 F* h" j! W SYSCFG_PINMUX1_PINMUX1_11_8 | \, y; B1 O+ d5 D) Z# F3 O
SYSCFG_PINMUX1_PINMUX1_7_4 | \$ G# g3 B8 G! N& N9 m4 f
SYSCFG_PINMUX1_PINMUX1_23_20 | \ l1 h7 J' r$ H$ S L2 B* Z
SYSCFG_PINMUX1_PINMUX1_27_24 | \1 C# h; b2 u; b1 `/ s/ r
SYSCFG_PINMUX1_PINMUX1_31_28
2 N5 F$ B. x. X6 ^ );" ]9 i2 j& V$ I; w
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \8 }+ n, y, ]* [' J- w
(PINMUX1_MCASP0_AXR11_ENABLE | \ m7 [, K Q( ~5 u
PINMUX1_MCASP0_AXR12_ENABLE | \
9 _ _2 S; y9 `, e; m9 H PINMUX1_MCASP0_AXR13_ENABLE | \
. b9 F' E0 N4 F: \4 F PINMUX1_MCASP0_AXR14_ENABLE | \
% T; G. t& _2 Q; i# U4 V PINMUX1_MCASP0_AXR8_ENABLE | \
" i0 X3 q( V3 Y/ `4 \ PINMUX1_MCASP0_AXR9_ENABLE | \
. I; g: j5 j: n# } PINMUX1_MCASP0_AXR10_ENABLE | \* e: `0 o2 q; _& E6 m/ j; K
savePinMux);
# [) s# {4 ^9 r. K6 G9 V* K}
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1.McASPI2SConfigure(); McASP的配置程序如下:* j4 c: n( ?) B# ?5 N1 s
static void McASPI2SConfigure(void), f2 U/ E+ C I
{
5 @2 ~, |8 E0 x3 X! Q McASPRxReset(SOC_MCASP_0_CTRL_REGS);: S( H# H' U4 v1 y' b0 _7 F
McASPTxReset(SOC_MCASP_0_CTRL_REGS);9 [9 `2 J6 |) t! V! \
1 P( e1 G" T" k9 X
/* Enable the FIFOs for DMA transfer */+ g$ k Z- t8 h& @( r) U
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);3 d( y6 u$ s- _0 T" u D
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
6 U/ l3 X$ [0 M: |1 g! Q+ W
. n o, w8 `4 d( |) q: q' n" b" r /* Set I2S format in the transmitter/receiver format units */) G$ v5 O& o. a0 V, k& h
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
" H( h+ a! V' j# p& y MCASP_RX_MODE_NON_DMA);( B9 P1 h+ K8 h& n
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,7 P8 q8 R* V) k" O# Q3 _2 d" k
MCASP_TX_MODE_NON_DMA);6 M; `/ M, s {4 z
' B9 {: ]) Q& _8 U7 ^
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
/ t9 V5 |1 Z" q) t! R McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 A7 q: \) a, Y' \" F MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
. x8 [9 C1 k7 O% f3 Y b7 Q! R% {% J McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
+ u# I' p! b6 z% ?! s, v1 n3 I4 m MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
5 i; a ? z* y% d4 V! n; v& P8 H y2 y8 l* y* [4 D
/* configure the clock for receiver */
- P: N5 e3 K$ v// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);; u4 [) E6 @# |$ |- b, P
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
+ E. ]: k+ }+ H( p3 s McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);2 G e, j( F+ ~) J
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
* V7 ^- g4 Q9 O% Y8 H 0x00, 0xFF);& K `% M9 l0 @$ E% i8 z
; D! n$ E2 F, k( I* m
/* configure the clock for transmitter */
1 q! w: O- q9 o// HWREG(0x01D000A0) = (0x00001F00);/ C$ g; A/ `0 ?: N; ?5 i4 S
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);# B+ Z {3 f. Z- ~; O
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);! S( l* C! {3 {. E) B
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
/ z& k8 v9 b. U1 e. ~2 g McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,5 i1 y% {; ~% @# t
0x00, 0xFF);
1 y2 j4 A; ]) y m! Q$ a! F : a3 X: ^4 v1 b1 n5 q* q
/* Enable synchronization of RX and TX sections */ 1 x, G/ y3 ]2 M: q8 i
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);8 L9 U, E ]+ c5 [$ ^
$ G" l( r6 F2 l/ N" w5 @ A
/* Enable the transmitter/receiver slots. I2S uses 2 slots */% A5 V5 P' h. v7 F
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
7 C1 H( T- E9 u( n9 F# u' G McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);/ W6 ?8 _& i' }7 L* W9 |
& R( F( l# [; i* Q9 z /*
" e: M8 b# O9 E9 _0 J ** Set the serializers, Currently only one serializer is set as8 M0 ~: a# q: a j6 ?
** transmitter and one serializer as receiver.
) _0 r) E9 Z1 H) ^ */# l4 V+ p* v" \* Z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
. ]6 v" Q( ]% F/ |" ~ McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);
' y; d8 c, e$ ~3 E% n McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
: r( g3 \1 X! O4 T* L McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);4 ]# N& s) h) T- ? O/ V. y5 R S
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);3 x- w' \ G! `6 T' \( @$ ~
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);4 O8 H3 f/ `0 t8 |# ]. H
) }7 G6 r, q) W
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);* z( P5 u s' v0 Y
+ K! L$ I i" u
/*
$ s0 R% t' f& q/ A% F ** Configure the McASP pins
( ^! C. y% ?8 ^' P) ~0 O* Q8 X ** Input - Frame Sync, Clock and Serializer Rx
6 N$ N4 G: v$ c! G% G ** Output - Serializer Tx is connected to the input of the codec
+ x! t" X# I- A% |# r- Z# C$ {) f */
: t! g4 u# ]' R) s5 N& c6 s) M McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);6 S3 ]+ I0 `9 J$ ~4 h. C/ Q! P
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,7 I3 s" N* V3 U# w0 N
MCASP_PIN_AXR(MCASP_XSER_TX)0 g( y2 h5 _: A1 s2 V" j; K
| MCASP_PIN_AMUTE
1 t7 t0 g0 j2 o) N! k% C1 g );
V8 |2 P ?5 U6 O* Z% J9 S McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
6 E) w7 t0 Q. g8 k8 J MCASP_PIN_AFSX
! @) v" J8 d) |. B: ]/ L | MCASP_PIN_AFSR' q2 V3 e" U. e# u0 |
| MCASP_PIN_AHCLKX' V% V! z; C$ I% W
| MCASP_PIN_AHCLKR
1 u, e, {7 ]6 s4 P | MCASP_PIN_ACLKX
/ U/ g5 {& m9 ?+ N8 l0 S | MCASP_PIN_ACLKR
$ d9 J( d% L$ k p | MCASP_PIN_AXR(MCASP_XSER_RX)
! d/ W) K. ] C8 B7 Q& k | MCASP_PIN_AXR(1u<<(13u))
9 k. m, N s* F* r; E$ { H# K' R, v | MCASP_PIN_AXR(1u<<(14u))
2 p1 u; M Z( y- X% n1 ~* E | MCASP_PIN_AXR(1u<<(8u))
2 c; M2 c/ D1 I' O! y, E$ A | MCASP_PIN_AXR(1u<<(10u)): ?4 p, h0 ] l# ^9 _% c
| MCASP_PIN_AXR(1u<<(11u))2 w; ]) I; X$ Q* p% x5 S
);
1 @1 h3 X: Y* v: @ R
& b6 \7 v% \# [7 B. H8 J2 E& _ /* Enable error interrupts for McASP */
: P9 j! V7 R4 p McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
/ b/ |+ V3 J# R( n$ x3 P; W( U) L, K MCASP_TX_DATAREADY
( z- @9 A" j/ H! ^$ Q | MCASP_TX_CLKFAIL # n1 x! u+ A+ O' |. {, N0 C8 T6 O3 G
| MCASP_TX_SYNCERROR L% A" m- G3 t# l: f
| MCASP_TX_UNDERRUN);' @8 ], k1 `. T( S. J
6 h9 s9 h0 i/ ~
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
7 f8 P a$ g3 L/ }7 w5 E/ o MCASP_RX_DATAREADY/ G* D4 ^2 d( \. Z4 d
| MCASP_RX_CLKFAIL6 v" ?. V" l! u2 Z8 \) m9 g
| MCASP_RX_SYNCERROR 6 ~9 ?: t: u0 u& q( z. ?' r
| MCASP_RX_OVERRUN);& t1 g8 N, k3 ]& F. Y$ Q
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
A, n5 \2 _2 t: {+ _
; {1 I2 s- ?4 v& Y- v1 J/ p}
8 S* @- m8 J& T6 k6 a# m0 j4 W2 g, w
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句# N" c+ }. W; } d$ z
static void I2SDataTxRxActivate(void)
- ?1 {6 Z& C0 i! f( [{
' E0 z* u9 Q2 r8 C7 H. [ /* Start the clocks */
B2 U5 |, G9 H* w McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
2 v0 g6 P' L2 Z' k9 z% b) D! D McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);4 D' U9 y( h0 F3 P
) o; q K0 D+ t /* Enable EDMA for the transfer */
' k% r+ u9 V" T; f& k// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
: F" N0 G; d6 S9 m& }3 s// EDMA3_TRIG_MODE_EVENT);& h5 W7 T" i0 K4 X& y U* O
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
& b5 W% b: A9 _" h' R// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
0 t2 r$ E3 f1 I) o) K /* Activate the serializers */, U. s g- s( z9 b1 O5 p
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);$ b& b4 B! w; {0 A* d+ c4 B/ T1 g
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);5 c$ D7 _$ V: P9 p: {* k$ _7 y
/* make sure that the XDATA bit is cleared to zero */) Q* c! Y" p6 _+ a% t8 S7 O) C I
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
: o0 r0 _, ` f /* Activate the state machines */
" c$ V$ X. W5 E: u" H4 _; H McASPRxEnable(SOC_MCASP_0_CTRL_REGS);) D5 I. c& D+ [. m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
. B5 ?' L# e" q$ [# [ McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
+ O* g \9 H7 V# n6 K$ Z}
7 z; K% m- @7 R2 w( ^% m' z" c8 G! O; M" v, `
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