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我的McASP配置分别如下:# j0 v" u% }& v, {
管脚的复用设置是:
4 u2 f; X3 R K8 D7 m, Q% zvoid McASPPinMuxSetup(void)
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unsigned int savePinMux = 0;) ^7 a) r0 C0 i& @; e% Q* f
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
; C! q5 {* H! `" C4 r ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
# a9 Q1 Y0 i/ z2 Q" j# {5 a' I SYSCFG_PINMUX0_PINMUX0_23_20 | \
% J4 h8 @8 m# ?: R" c SYSCFG_PINMUX0_PINMUX0_19_16 | \
0 c0 i1 Z7 L; y: r! }% W1 G SYSCFG_PINMUX0_PINMUX0_15_12 | \
9 n# I. Z6 z. L( G; G2 t SYSCFG_PINMUX0_PINMUX0_11_8 | \
- k) q" L# r5 l2 a6 S SYSCFG_PINMUX0_PINMUX0_7_4 | \- O# g9 T5 S2 D. F* X
SYSCFG_PINMUX0_PINMUX0_3_0);( K2 n1 M! ~, q- w c- }
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \" V" C# l6 ?: q/ E9 O/ L, i
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \
/ u. o/ p. \8 `% p* F" X. s& T PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \/ y) |7 r' e6 B2 L# X" [" f
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
7 J3 f5 G* D; U& e) H5 K; F7 { PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);1 ]* x2 z* I `4 O
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
s( P- d R! x7 x" h1 S ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \; W- L4 X1 Z. X$ z# }7 [
SYSCFG_PINMUX1_PINMUX1_15_12 | \3 z3 f- u1 o! v2 [# k
SYSCFG_PINMUX1_PINMUX1_11_8 | \+ ]) `* y# i$ {) B2 f7 D
SYSCFG_PINMUX1_PINMUX1_7_4 | \
7 J1 Q5 `# a; Y0 c* y SYSCFG_PINMUX1_PINMUX1_23_20 | \$ L1 P! b" V+ S5 {3 P
SYSCFG_PINMUX1_PINMUX1_27_24 | \7 e5 V7 A/ m0 l, c, W# ]7 U3 o
SYSCFG_PINMUX1_PINMUX1_31_285 N8 b y2 m! V
);% \$ Y0 b+ [3 I, f4 y
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \% E7 z2 E" o8 [# G
(PINMUX1_MCASP0_AXR11_ENABLE | \# m) j* ~& X6 J
PINMUX1_MCASP0_AXR12_ENABLE | \, U3 e5 c# l2 O" T5 L
PINMUX1_MCASP0_AXR13_ENABLE | \
1 h, Q& p( ?- P% s$ \ PINMUX1_MCASP0_AXR14_ENABLE | \. A4 i4 v' p- Z1 G6 T0 _7 t& p6 U
PINMUX1_MCASP0_AXR8_ENABLE | \
2 {. s) z/ r6 }% u' w9 j6 j) A) { PINMUX1_MCASP0_AXR9_ENABLE | \6 g5 I' {- i0 l- o
PINMUX1_MCASP0_AXR10_ENABLE | \9 o# R6 {4 Q5 v" e
savePinMux);( J; L) R' d9 t4 p' A
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1.McASPI2SConfigure(); McASP的配置程序如下:
: ?$ D7 f3 P" d9 F8 k: a& Y* K- [static void McASPI2SConfigure(void)5 U2 v; _1 g/ \( m5 _, H( M" |
{" ?6 ~8 C! h2 d3 F8 s4 p2 W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
8 b% C7 _* t _. t4 x$ }- L; p9 |7 n6 W McASPTxReset(SOC_MCASP_0_CTRL_REGS);
+ B8 K: }6 N" r+ y( {/ w, F4 u* h, w: Z% \0 I. @# G" T/ A
/* Enable the FIFOs for DMA transfer */
% H! c4 ?: w. k// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);! F; D8 |9 u$ D7 C* S- U
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);1 @7 P8 G4 ]7 B7 U
: ^, {( B/ L; ?9 f9 v: m9 E5 Y# m /* Set I2S format in the transmitter/receiver format units */# P) v8 T: ? `1 E" K
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,5 v& G& Z3 M R# Q
MCASP_RX_MODE_NON_DMA);
5 U) j+ D, i2 @( q( R: L McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
8 b/ d- O l- j/ W) G) W4 u$ F MCASP_TX_MODE_NON_DMA);, P l% Q+ Y8 h
7 ~" `& [6 ]% t) V% ]2 T# m5 n& a
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */8 p3 D/ P, P9 h$ P6 Q( o% u
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, * b1 m8 J. [0 R! e
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
$ _8 \8 Z, O S. q- Y McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
; ~0 F8 S8 c1 ?8 @5 b+ O7 ^. g MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);; y0 c; a; _& i# ^4 h: l
5 w1 P3 ~! I3 u" u0 k /* configure the clock for receiver */
& {- j1 } r* |$ B6 F// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);) r% _( ]" I5 _' W& E; {
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
. N$ m5 p, A. n7 Y0 i' ]' j, K% C McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
* l q- a0 [* i) n9 t4 C McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,8 {! C. k8 j7 S; I
0x00, 0xFF);1 R3 n. Q/ @+ x% r! {- o! |) B
, N; Z$ r) L8 \& r1 I
/* configure the clock for transmitter */( l" z% p1 A8 a0 d: e
// HWREG(0x01D000A0) = (0x00001F00);4 r3 l3 Q. ?2 x1 X2 o
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
7 E, t0 U7 }5 U% U$ h J McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
7 T: _6 x ^ v$ }# ~+ E; r- |( X McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
3 t3 L* |5 y3 W McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
1 \2 H2 x I9 j# q( N 0x00, 0xFF);
! y; j9 _' j' N# ~ j# v: }0 L 7 s2 }4 C S0 ]$ }8 J; V l
/* Enable synchronization of RX and TX sections */ 3 }; r9 n. T9 O
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);
- y; L6 Q' Y0 R6 S; K) h( x) f8 e& |) c( z8 Q0 N; n
/* Enable the transmitter/receiver slots. I2S uses 2 slots */3 t& S! Z# Z9 E) }# V
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
. i4 U. [; G3 i* z l2 ?' D McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);! T* a! O3 @) W1 f' H& z
8 ] u. o; I. W& q# }. W /*3 @. \( h5 z3 g% Q5 o; c8 V
** Set the serializers, Currently only one serializer is set as
! l7 H, u0 N$ R7 I$ t ** transmitter and one serializer as receiver.
3 V1 p2 d+ [/ ]! T. Q5 F */
) T7 a! ^6 {$ m" d7 { McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);, @7 J: I$ b+ y0 ]5 G3 M
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);8 L, ]$ _8 x2 n3 A3 z) k
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
* f" \/ C* s. W+ U6 K McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
! ~" a6 n/ W: G5 B4 ~; D McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
! }! u b7 C; C* ]- } McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
( J* G4 {- u- h! E2 _0 v) _
) R7 e+ t( X1 N% B McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
4 w* Q+ J F$ t8 I" T2 t9 l7 c8 m0 [
/*/ ^! s. N3 l/ Q/ F6 ^4 s% A( k
** Configure the McASP pins 3 }, Z2 z6 U3 l8 E+ Q* V
** Input - Frame Sync, Clock and Serializer Rx
% s0 `( P: d( e V- {/ J ** Output - Serializer Tx is connected to the input of the codec % m9 P0 S8 ]& W( x7 Q" n$ r
*/& P. W1 t3 V0 O# H
McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);- V1 t' r8 W6 ]# }; z( E
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,5 P3 D) B- ]: f1 M; V: J$ R! [9 s/ p
MCASP_PIN_AXR(MCASP_XSER_TX)
6 {) I! s1 o2 V; U8 v7 i9 C | MCASP_PIN_AMUTE
' n9 e6 U5 r3 l/ w );
4 k2 s6 r3 L; ]$ w9 ^4 F" S McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
- d6 U& u& r# _9 g MCASP_PIN_AFSX% M0 [; i( x, H1 g K+ W
| MCASP_PIN_AFSR+ O- Z; u. a' _. h5 L4 {
| MCASP_PIN_AHCLKX
0 W$ c m! u* W | | MCASP_PIN_AHCLKR
1 t6 v+ }, O* @ A | MCASP_PIN_ACLKX) ]7 o; U3 t6 H2 s5 P8 B- V
| MCASP_PIN_ACLKR
b" i |' Y5 {. w1 u | MCASP_PIN_AXR(MCASP_XSER_RX)
4 `; f w7 p# _3 v V9 _ | MCASP_PIN_AXR(1u<<(13u))
2 X# w. m% K6 }& J9 c | MCASP_PIN_AXR(1u<<(14u))+ P& B( u! O5 H r. w; c" }1 A+ X
| MCASP_PIN_AXR(1u<<(8u))7 v# _2 o9 J# S9 A' d0 T8 ~) D: J
| MCASP_PIN_AXR(1u<<(10u))
4 l2 m- l7 I2 i' T | MCASP_PIN_AXR(1u<<(11u))
% Y4 @. v0 M4 c# O, m% r );
l! i1 [' j& x( A4 ^+ y& o
! v% |1 o' t9 C /* Enable error interrupts for McASP */( L. Z4 C7 h% R5 p z0 |
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,1 m1 _* f8 S/ P0 U, C, ~8 g8 Z9 A
MCASP_TX_DATAREADY
+ [& D) H- C- O9 X | MCASP_TX_CLKFAIL 5 I' D( x1 c, j1 O6 K3 E4 g
| MCASP_TX_SYNCERROR0 ^- b8 ~) {+ { j
| MCASP_TX_UNDERRUN);
/ ^9 t+ L ^, B% p
; T7 z5 T0 D& Y* X5 y; {* G+ s; h) L McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,) Y* A/ u! \$ {( l) s! k
MCASP_RX_DATAREADY! V& q! W+ R E& P; p
| MCASP_RX_CLKFAIL( N2 {8 t ]. K
| MCASP_RX_SYNCERROR * K9 @+ A: ?2 x. h/ X& ~
| MCASP_RX_OVERRUN);7 G% D+ L# f- e% q F+ E8 M
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
2 U& w. J1 G8 @4 p9 R& N- M7 _2 l, y; E) Z- N
}
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2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句9 E5 D @8 ?5 P% ~/ W; P
static void I2SDataTxRxActivate(void)
: R# D- f0 W, o1 G{
8 b3 g5 C9 t+ |( m% h /* Start the clocks *// Q) Y6 d$ W6 y- s8 M2 `$ y
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);/ D$ V& t! s6 W' @* \
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);9 ?0 e1 n, x6 K# A2 ~
% }! T* [" I& ]9 a3 o* ^1 ] /* Enable EDMA for the transfer */2 ]& p% F) s$ E
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
M! W; e9 Z* t& b9 V// EDMA3_TRIG_MODE_EVENT);) t8 q. s/ }& {0 m
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" O8 [: o7 q/ n3 g) J. V1 u// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);& z3 |* m5 p' ~. M- I" a
/* Activate the serializers */
' y N1 M3 O* {- [9 k% ^ McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
) M8 B' M; T+ Y4 C8 t' q McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
. s4 N# Y( x3 k8 E+ P7 a' ] /* make sure that the XDATA bit is cleared to zero */5 P6 ~9 u$ f. k! w1 p2 R1 z3 |/ U6 g
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);8 s+ S0 a4 \" ^, Q+ k$ A; J
/* Activate the state machines */& f) W/ R: a+ t9 ?0 w
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
: H, b5 Q6 V/ [; S1 } McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
( M+ y q; E3 N" d# ^0 w McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);( ^* E& o9 A8 _) _6 ^
}( `* ]" c" ^( a
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