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我的McASP配置分别如下:9 s% H* d9 Q6 J8 D/ W
管脚的复用设置是:0 t' p/ ]$ P9 C' J! n1 i
void McASPPinMuxSetup(void); r/ L! D. D3 X- ~ V
{! ? C* i2 `6 L2 x* i4 H S" U
unsigned int savePinMux = 0;
8 D9 \! l8 t& g: Y, C5 n savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \; Y5 l9 X! \% N8 q* n7 t
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
' K6 t( i- f# A3 B" e; L SYSCFG_PINMUX0_PINMUX0_23_20 | \% i- }" g7 t* z" K3 l
SYSCFG_PINMUX0_PINMUX0_19_16 | \. g9 l2 q9 W# R3 X) E
SYSCFG_PINMUX0_PINMUX0_15_12 | \
( J. |. s. }% O SYSCFG_PINMUX0_PINMUX0_11_8 | \
& ]# q$ g0 S8 w SYSCFG_PINMUX0_PINMUX0_7_4 | \7 ^) \' ^' A, Z% |% A% X3 Q, n) D
SYSCFG_PINMUX0_PINMUX0_3_0);4 u0 I- f& b0 f. C1 d* c
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \7 x0 P6 u; ]% c! S, Y+ j
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \$ i# L2 p6 z* u5 y- h: u
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
2 r+ E4 O* f6 h1 a; B* ? PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
7 G1 v6 E d- o9 i2 R PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);- n" w6 b4 H: T2 W$ t7 `6 t
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \/ b& q u: V: O. E
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
; y) F( L$ z: f, L) G6 a SYSCFG_PINMUX1_PINMUX1_15_12 | \# Q- v6 N6 \1 x' V
SYSCFG_PINMUX1_PINMUX1_11_8 | \
: ]; ~& `' A( g1 J- O& n SYSCFG_PINMUX1_PINMUX1_7_4 | \- G0 O( w- ]6 M% g( N
SYSCFG_PINMUX1_PINMUX1_23_20 | \* f" `) b) g- R/ K, p$ ^* ~
SYSCFG_PINMUX1_PINMUX1_27_24 | \
/ `/ |- p% I! x SYSCFG_PINMUX1_PINMUX1_31_28
- s+ X) t! j Y% W& _% ]/ z );8 h/ ~. M! z. {. {* n
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \9 \0 ]( V# e; }3 g
(PINMUX1_MCASP0_AXR11_ENABLE | \( B% P& D( _. B6 N
PINMUX1_MCASP0_AXR12_ENABLE | \
5 @; h- o8 B- s- R4 o Y' S PINMUX1_MCASP0_AXR13_ENABLE | \7 p3 E# s2 \' ?6 p$ v% g6 l3 R
PINMUX1_MCASP0_AXR14_ENABLE | \
0 x5 O: N/ D( D) Y( ? PINMUX1_MCASP0_AXR8_ENABLE | \
! w3 |- J2 H4 n# \# y) e5 x PINMUX1_MCASP0_AXR9_ENABLE | \* ~, S/ l7 h& `& D
PINMUX1_MCASP0_AXR10_ENABLE | \
' l: f9 G4 i5 o) q0 m8 U savePinMux);2 o# x* [$ h2 w i: m
}: B& g: ]" Y; p- n* z( G
+ O" [9 H+ N; J1 M3 ~' R) a. s5 c6 F1.McASPI2SConfigure(); McASP的配置程序如下:) ~! M4 _: R3 E* ]5 Z
static void McASPI2SConfigure(void)
8 D8 @5 a- E3 i, T7 w$ f) B{
1 R: K( Y7 j: @4 \. f6 V$ ^2 W McASPRxReset(SOC_MCASP_0_CTRL_REGS); L# \; u; q% u4 t& I
McASPTxReset(SOC_MCASP_0_CTRL_REGS);& B: O0 e3 t" ~2 n3 ~( B
8 b4 I% S! g9 O/ s
/* Enable the FIFOs for DMA transfer */- |2 L9 @0 u2 @, T
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);# i8 N$ D# C6 ^. ^/ _+ z
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);& n3 C( J$ h3 k, ~0 @9 G/ r
! t- u0 w7 |3 x8 G+ V
/* Set I2S format in the transmitter/receiver format units */
. k, k- s b. N6 t, B& G McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,- W: s* [5 A9 l5 K; U7 a3 }
MCASP_RX_MODE_NON_DMA);; ]2 Z3 ?3 _7 r4 |* v" |
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
( F, o" U2 C! M0 H. Y9 _! S MCASP_TX_MODE_NON_DMA);
" ~% a2 d; L& {: ~6 z: x# H
* R( d n, o4 g" Z /* Configure the frame sync. I2S shall work in TDM format with 2 slots */5 _* Y. X; N4 F2 u1 R& g3 _
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
4 o y2 A& y( ^0 x3 c; g h MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
' p% i; ^. z% F McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
( a0 n8 D" l: ?( A MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
0 a, o, S( v. e+ @
4 w- A4 F1 _5 D8 p) d4 h* P$ g /* configure the clock for receiver */: x$ k1 a; F/ w
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
" s' R$ D! w/ ~, t8 u( y McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
$ X5 N8 ^5 n, d9 {8 r6 A McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);3 l A- M0 x) z9 D( b0 l
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
" w2 _; } k+ y7 w/ C, } 0x00, 0xFF);4 H8 C( h0 |% f$ H& O4 q
1 t0 @6 N, V5 A. P7 Y
/* configure the clock for transmitter */
7 Z( ~) _3 L7 j7 |$ e+ @// HWREG(0x01D000A0) = (0x00001F00);3 z2 [: W' E! ]% c3 t
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);) G g8 a& |$ ]; s. K/ N! c
McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);1 ]2 i1 [& j4 |- x
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
9 z# E6 H) l& A6 L, ` McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,/ m. R: i2 {, _
0x00, 0xFF);
2 o$ D! O/ ^) B/ z! j 5 w* U$ ^4 H- y
/* Enable synchronization of RX and TX sections */
2 d( H! V' X. Q& V( A! x McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);! i. n9 X) d7 }" f. Q) s h
: l4 @) p8 W8 F4 l5 Q' ` /* Enable the transmitter/receiver slots. I2S uses 2 slots */3 |- M) F" x$ ^5 g
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
3 C7 y6 L F0 l: ^( S% e: u+ S McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
+ d" J% D2 U0 B& f' Q% V$ X
% [/ M1 T( l, a; B' U /*1 E" w b- d5 v5 T
** Set the serializers, Currently only one serializer is set as
1 k9 K. b8 Q" y- G8 U- s" z ** transmitter and one serializer as receiver.
: O5 ?5 E+ S& W */* h, z# u9 T$ u9 B$ s( ] j
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
7 n9 o0 E: y; ^1 d' a, I McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);. ~ I! D4 B8 k& R+ K
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);3 x0 H; J& M' O7 c8 }5 K# F
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);
8 X& r* A' U# a McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);6 }9 m1 l" i, j- X1 T
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
6 T4 _0 L* [7 F4 e1 U
/ Z R) p2 p; J McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);8 F6 ^4 l. y9 k; \' V% n; j
: \; S& i) `3 C' W; g
/*9 w* t- M" a+ x% Z/ I
** Configure the McASP pins - `& N9 ]7 ~- i# D4 z: ^7 F
** Input - Frame Sync, Clock and Serializer Rx+ U6 u/ Z! z. f# W J% D% Q7 \
** Output - Serializer Tx is connected to the input of the codec
* X4 `4 t' j( ~2 K2 g; }4 } */
% {" x' [1 f4 z5 I' z8 Y* a McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);: P- {) ?% l5 ?0 s
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
0 I! o4 {( S/ w) ~ MCASP_PIN_AXR(MCASP_XSER_TX) [6 p$ n& m G% s
| MCASP_PIN_AMUTE: ]' x& X0 t! H
);) S# K* i) W4 F9 w/ c
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,, t8 W* P1 F$ `! ^/ |
MCASP_PIN_AFSX
}7 M) a, Z7 S9 t: b | MCASP_PIN_AFSR3 L* p9 h! l9 P# U
| MCASP_PIN_AHCLKX
4 k0 c, c# i$ X S( D | MCASP_PIN_AHCLKR/ w' G( s1 a! n9 r2 j
| MCASP_PIN_ACLKX
9 L- N G/ a3 C- w9 S | MCASP_PIN_ACLKR) Q: j+ w7 N* t1 V$ g4 B
| MCASP_PIN_AXR(MCASP_XSER_RX). F' C8 c4 V3 R; [
| MCASP_PIN_AXR(1u<<(13u)), d9 i: j5 d4 W
| MCASP_PIN_AXR(1u<<(14u))
: S1 a/ P7 r4 s | MCASP_PIN_AXR(1u<<(8u))
0 y- ?8 ~) v5 H( B J | MCASP_PIN_AXR(1u<<(10u))
. L6 X3 f6 y }& d | MCASP_PIN_AXR(1u<<(11u))
# @% F6 X5 Y' z( Y ); @0 P% x* M+ L! i; O+ E( Z
5 ?& C. _4 V2 k& L
/* Enable error interrupts for McASP */
) q7 q6 U4 l) Z McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,( y4 m6 @: V; V5 U, P
MCASP_TX_DATAREADY
" G9 E* |- v* I" q: [ | MCASP_TX_CLKFAIL 7 f( m6 ?! H* ?$ X# u2 v# a
| MCASP_TX_SYNCERROR4 L' p% y1 E7 \/ W( `5 ]$ o
| MCASP_TX_UNDERRUN);
6 h0 [2 r! y4 m* i( K( G8 W: `: a1 t0 ~3 [0 _5 W; U ~' V
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,- j8 ?! o9 c* b/ y( b
MCASP_RX_DATAREADY
, e8 r. f) J6 A9 y | MCASP_RX_CLKFAIL( ]0 Z- [. M$ E! ~$ r
| MCASP_RX_SYNCERROR 4 y8 {. w0 H/ S% v8 x
| MCASP_RX_OVERRUN);
r! ~2 W: {: g( M" t! E- p//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
3 y* E! l% }+ \, U! `6 y3 j; G" Y$ q9 D& i# W
}3 T5 [0 R; V% \, ]1 ~: l# u/ @
% _) u2 O% w# q
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句1 h2 M; Z. ^) F( g) }
static void I2SDataTxRxActivate(void)
& W$ C. t9 J3 C3 f1 J, c{
( X: V$ [" ^8 h; K /* Start the clocks */$ {/ e& r0 K, r
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
1 B/ F6 h/ N& Z0 ^ McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);
) {) d6 a D5 ^3 W/ K& z: k) F" N( P- t. @' c0 Y
/* Enable EDMA for the transfer */
3 N& N- l8 i3 n# u0 k( Q. b+ `// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,2 H) \5 q# |% R/ h: ]0 n' c* n! F9 K
// EDMA3_TRIG_MODE_EVENT);0 H! `2 b4 |, Y6 G; V) P
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
" {" C; w# u& C9 M9 v// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);7 u( {. K% s7 g
/* Activate the serializers */3 N* M$ |0 x, y4 U" | _0 j. N
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
+ T2 ]5 }3 F; M6 E. [' V' g5 E McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);! m# j& g* Z, B
/* make sure that the XDATA bit is cleared to zero */* {& D5 [1 h! z. x7 X1 z+ j9 _0 d# }
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
% D+ I$ C. Z1 s- O( \ g /* Activate the state machines */
! L& @. E& i2 r2 [7 { McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
* A! p; a) M G/ T McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 |9 C5 o) {. R( C# g0 S0 D McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
# t: R6 G. J2 n0 J f$ u7 \4 k d}' g0 O1 C- H3 I
0 t0 C0 O: _* ]: l
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