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我的McASP配置分别如下:
P7 E! t, y3 \/ I* w* K管脚的复用设置是:
# l/ G- h" b/ \, L! g. zvoid McASPPinMuxSetup(void)
% l( t/ p8 m3 G! w) H$ L# f{
( j' V+ Z) b, k% t2 S unsigned int savePinMux = 0;$ {/ B( B- \& R5 B8 a! r# U
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
; x% t( a: {; @9 ~" e( M% {" [ ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
. a% c/ i- J, h+ w% s" S* [ SYSCFG_PINMUX0_PINMUX0_23_20 | \
% N1 k }0 S7 ^& z( ? SYSCFG_PINMUX0_PINMUX0_19_16 | \; }' I7 u$ h* s1 S, d( ?; A
SYSCFG_PINMUX0_PINMUX0_15_12 | \
& e* [4 Q6 u( r# d SYSCFG_PINMUX0_PINMUX0_11_8 | \, x6 s: R: ]7 H6 d/ S. `. |
SYSCFG_PINMUX0_PINMUX0_7_4 | \" j0 b" M' @9 T9 C( v0 {8 g) P
SYSCFG_PINMUX0_PINMUX0_3_0);
3 W. Y6 p6 m3 }2 i! V HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
) w% T/ C5 y) I# D# L% X( J. [ (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \! b# A! p, N) X: p& B
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
* J5 e" v# x7 U. E# P- G' l z" } PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \
4 ?: k5 H6 l/ \$ S PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
) f8 E5 x* s: S a0 [* Z8 @$ y( e+ T! C savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \
0 ?, _5 n$ }1 E0 ] ~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
0 M; k% v" B& i# z' T8 h# g SYSCFG_PINMUX1_PINMUX1_15_12 | \
$ o7 O' e) ^& f4 a/ D8 v, b SYSCFG_PINMUX1_PINMUX1_11_8 | \
- c y1 _+ t& d6 y8 h, S* l+ } SYSCFG_PINMUX1_PINMUX1_7_4 | \6 |5 j2 l' c q' W1 Z( D% Q4 {
SYSCFG_PINMUX1_PINMUX1_23_20 | \
' G& ~( @: C; O; N& Q/ h SYSCFG_PINMUX1_PINMUX1_27_24 | \6 [% g/ h5 [- K( R+ T, g# ]
SYSCFG_PINMUX1_PINMUX1_31_28% X4 |& g7 {8 @0 Q$ T
);
* f; [9 B( K- n9 A; n HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \# H \2 f9 ?" [5 d& k
(PINMUX1_MCASP0_AXR11_ENABLE | \
' K9 I) B( a) J8 \% T PINMUX1_MCASP0_AXR12_ENABLE | \( j# o Y9 B* Q7 @" P2 P
PINMUX1_MCASP0_AXR13_ENABLE | \% V9 u8 O% N, c5 [1 S' e+ d7 O2 N7 }! L
PINMUX1_MCASP0_AXR14_ENABLE | \( i9 |/ Q/ l& V4 |- ]6 ]( f
PINMUX1_MCASP0_AXR8_ENABLE | \1 w4 x" o: Y- H- \. Z$ S- @. a
PINMUX1_MCASP0_AXR9_ENABLE | \$ f! \& t7 p9 R2 J
PINMUX1_MCASP0_AXR10_ENABLE | \0 A$ d6 z! k: C4 A
savePinMux);3 F* g. j% L' @" {0 t
}" |7 Y/ W8 ?! T& g' r3 ]
# ?9 A2 x. q( r# D U" r1.McASPI2SConfigure(); McASP的配置程序如下:+ a6 U) y p0 g- _% `
static void McASPI2SConfigure(void)5 I! k" C0 | f1 Y; |8 n
{. |6 w- T- P P9 R: R9 O
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
4 |# j5 F0 O( V0 ]: V2 G McASPTxReset(SOC_MCASP_0_CTRL_REGS);9 n, T2 `0 }3 W' s! m6 S- I2 A
' v3 f6 k( k* A7 }) \# G
/* Enable the FIFOs for DMA transfer */
. a+ S' T8 j! W2 g$ E3 T# P& t9 l// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);# o$ u7 o" A$ q1 C- ?+ |
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);0 ?- m, E- Y8 V( r$ k! d2 o
: _9 {; |. n5 ] P U
/* Set I2S format in the transmitter/receiver format units */" E( r- A3 `6 K( x" n8 |9 x- z
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
5 E2 s8 Y7 ?& p% E3 ]. j' Z MCASP_RX_MODE_NON_DMA);) ~- j" \1 Q6 H
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
. J: L! G5 R! ]% I/ h2 Q( i- P( o MCASP_TX_MODE_NON_DMA);/ U7 r! H5 b. w* t; h. O6 K
3 O- ^& _( @* T/ g: p" \3 l# M4 {' P
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
: ?0 B4 h% K7 p- ? McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
$ `, {0 A5 ^7 G MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
1 w5 z8 m" e M( Q9 N# @ McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD, # D1 e" }" j/ V9 r) Y2 q
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
0 X R) `( A- A5 D9 t7 e4 ]+ H. o1 b0 p& i; R7 W6 k4 z
/* configure the clock for receiver */
9 N: w& b6 @! X* N( C! @// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);8 V9 k* q, R5 t8 y) q; q5 ]
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
! Y. g6 W$ {" M% o" q McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
% I$ J! n2 t8 I, k/ s McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# |( f1 x& F: Z2 s' V; B 0x00, 0xFF);; k0 M# _% w8 B z. ^& b
/ \8 B0 G% w {: {5 y2 R /* configure the clock for transmitter */- `$ _7 {; |6 w( K$ R$ x
// HWREG(0x01D000A0) = (0x00001F00);# t/ o8 A4 q% W% _( h* T- E
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
7 B3 G8 [# n# k0 `; N$ ^ McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
) d: k3 [' U- R- w McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
\( X x: i1 _* \. { McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,- L* c" o1 c- v) v
0x00, 0xFF);
& e- ^& g l) c8 w) c- f/ h , B' U( @, }( c- j1 D9 k
/* Enable synchronization of RX and TX sections */
7 Z7 V9 ?+ g) W McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);; p6 V7 ?' i4 w( I) t
/ O, s; m) ~0 p: ^( u3 C /* Enable the transmitter/receiver slots. I2S uses 2 slots */
7 Z0 c& [3 H$ h5 h2 Q2 b4 a McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
$ y& |' P$ `( `0 i3 N8 r McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
8 t% |7 }9 d$ N1 G. a
: j% t. |9 ]- ]/ r" ` /*
* ]% t" d* Q( g4 T# _ ** Set the serializers, Currently only one serializer is set as
0 B a+ t$ U+ u' K( A ** transmitter and one serializer as receiver.$ S" W0 H8 w9 W" y! {; i
*/
+ m% }, K" i8 _. I/ n, p7 K) A# y McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);) r- L# c3 y8 Z; ?
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);0 O# p I& k" F7 \$ W: ?& p
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);
8 ?0 X% k7 J5 y. ^7 p, h- Q% [% C McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u); h2 l' ?; E2 Q# {+ Z4 a
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
' g. A* A& E# u6 N McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);3 H/ U- L6 b! T- _+ S( T* D
6 f" T1 x. X/ E7 G5 |0 d5 y
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);9 V' \' r( u! c
- @9 }. r* V' ?/ n$ A3 a /*
# r0 w) v9 | \1 E" ^, T$ Y8 Q, [# n1 U ** Configure the McASP pins 3 z& O6 R& u1 Y' y F
** Input - Frame Sync, Clock and Serializer Rx
! M8 w2 l. @ ?& d/ F ** Output - Serializer Tx is connected to the input of the codec
4 T2 ~; f/ j0 B */
# l& g9 b. J' q. d# Q j McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
* M; b2 Z' u0 R1 T; c/ a$ K0 f9 O McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,/ w0 E: l; A( p" E
MCASP_PIN_AXR(MCASP_XSER_TX); O7 U8 [7 ?" o$ U0 j6 E% ]
| MCASP_PIN_AMUTE( Y2 Y( c y4 f$ X
);5 ^8 @) C& Q, `& u* g+ }
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,: a% C I: d- Q' C
MCASP_PIN_AFSX
/ V7 I' [4 P4 i% D* a# ~% [0 T$ u) c- ` | MCASP_PIN_AFSR
- V3 }4 c/ Y6 m | MCASP_PIN_AHCLKX
0 W* ]% f1 q2 c | MCASP_PIN_AHCLKR) ^2 `) @6 E9 n' G7 e. q+ i: m
| MCASP_PIN_ACLKX% m! R: o8 A* f; O' |- |" I
| MCASP_PIN_ACLKR
) m* R7 M: S! A! @ | MCASP_PIN_AXR(MCASP_XSER_RX)7 Y, s6 _. i- j8 x+ ^
| MCASP_PIN_AXR(1u<<(13u))
9 o/ i% }7 _ o0 O% [ | MCASP_PIN_AXR(1u<<(14u))
5 {6 H& r2 |0 k! d# m, \ | MCASP_PIN_AXR(1u<<(8u))' x. h0 A5 n, g6 u( E
| MCASP_PIN_AXR(1u<<(10u)) D7 E0 @5 s2 X; I( k4 f
| MCASP_PIN_AXR(1u<<(11u))
& f5 k% [, k5 H% P8 ?; |. B; @ );
: X: {# Z+ ]0 l+ p) A/ a! a+ W7 K8 S: M# ^' X K( \/ T# T
/* Enable error interrupts for McASP */2 `2 h4 J) V( x9 T( i. g
McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,+ D9 x/ @6 k: g& V8 L; [
MCASP_TX_DATAREADY
- ` G6 g/ C( Z9 M" y! h% a | MCASP_TX_CLKFAIL
# i; ?; |) d) j" l/ }; ]( S2 M | MCASP_TX_SYNCERROR
4 i2 c7 @ |/ B | MCASP_TX_UNDERRUN); }, o1 t; s) z. H! R: s
: o o9 B4 h9 |
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
e' I3 R% L! F MCASP_RX_DATAREADY: p- m" V5 w8 v u
| MCASP_RX_CLKFAIL
' t- h% H, Q0 J' j1 n& y" y, |; j | MCASP_RX_SYNCERROR 3 b8 s- O* ~; {; n5 y4 E" W
| MCASP_RX_OVERRUN);
- ]9 h. q! e4 e# s- s8 `//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
) ]: [( U, i& N0 Q4 x
& ?) i: R, ?) ~2 P/ }. z N1 [}/ w5 D" w( m8 }! g. d& m
' {$ U- W: Q& e& u: _( m2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
6 d6 N7 u6 s& Qstatic void I2SDataTxRxActivate(void)& L1 W& J, F3 X8 H, x+ D
{
2 k" ]4 d$ }! @2 ]( y /* Start the clocks */& l+ T. ? V( F' }, U! @
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
; B0 k; C% i5 W. Q. y. C McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);! Q: o$ }0 e; \0 v# X$ u
0 S" S$ M" o# s5 t }1 [
/* Enable EDMA for the transfer */
$ M: Q+ J! b8 V6 G9 B7 |// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
6 x7 y! r4 b5 e- Q! F# a" ~9 A// EDMA3_TRIG_MODE_EVENT);) |, c. T4 ]7 ?6 t
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
8 J! |6 Y2 S X- \" i9 m: K// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
" ~0 f, B \0 h /* Activate the serializers */
8 c. r; {! `3 J. d2 h McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);" n3 o7 r' n4 t; ]+ h) h, x
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);8 P& b- j6 K* p$ ?. [
/* make sure that the XDATA bit is cleared to zero */
6 c& {, k' i$ |5 z! @% `4 N5 H while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);* n8 E- _7 L, @8 w9 ~; N
/* Activate the state machines */* z2 x3 N7 c n& c9 o! d
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
( F! [# G. Y) \ McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
% I7 i( C. u# G: R+ T McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
6 M! f: v& \6 F0 r7 q$ f) J4 G}
8 u& s8 ~+ j, r$ d$ J2 d
9 i4 S! Y& Y. ] |
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