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我的McASP配置分别如下:; Q3 @ b2 r# P7 k* q8 @) v1 t
管脚的复用设置是:
8 Q; k* {) {! q7 N. o1 Q% bvoid McASPPinMuxSetup(void)
5 z3 a% t: K. e3 z) _{
' p" r$ V- j5 S& `0 G7 Q2 r unsigned int savePinMux = 0;, K: ^, Z1 x0 ~# H
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \" ~8 d& W# }4 J. Y5 `+ g6 l/ D
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \& Y# |$ \ r9 n% }
SYSCFG_PINMUX0_PINMUX0_23_20 | \/ q+ M' X4 X6 _9 h: t8 w
SYSCFG_PINMUX0_PINMUX0_19_16 | \" M! _& j. ~7 v) o/ J3 N
SYSCFG_PINMUX0_PINMUX0_15_12 | \- q* b5 c( p [% z( S% o3 ?: \
SYSCFG_PINMUX0_PINMUX0_11_8 | \( Z3 a0 Y1 Z: x2 E- |: c" X6 v
SYSCFG_PINMUX0_PINMUX0_7_4 | \
. I. w" G6 P. U1 p4 B6 y# Z SYSCFG_PINMUX0_PINMUX0_3_0);
* o9 f" T0 u- e" S1 ~2 u HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \6 L: Q6 a1 t5 j( ?
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \4 P) k3 I* {% t% D2 [3 l. e) ^
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \& T( q% i" K9 n2 k0 B: O; c
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \' ]6 T3 Q: q' R: b
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);( ]3 N+ I }/ T
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \6 F1 r! J+ K. X/ ~
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \, E8 ^9 v" ~7 u
SYSCFG_PINMUX1_PINMUX1_15_12 | \
5 f& T& ]) B% \5 t7 V. ` SYSCFG_PINMUX1_PINMUX1_11_8 | \
) N9 [; s+ t0 `7 R0 r SYSCFG_PINMUX1_PINMUX1_7_4 | \
; s7 j3 [! s+ s2 q% Y/ x8 ~/ e/ a SYSCFG_PINMUX1_PINMUX1_23_20 | \
, }/ _4 E7 X; v7 s: _ SYSCFG_PINMUX1_PINMUX1_27_24 | \6 G" X# C* B# J4 e: d
SYSCFG_PINMUX1_PINMUX1_31_28' S; ?' i; W( p. t
);$ Q$ f7 t- }! R# i, u
HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
2 N) S- i* X) n$ t5 p7 H ~ (PINMUX1_MCASP0_AXR11_ENABLE | \
2 W2 U D5 g6 p PINMUX1_MCASP0_AXR12_ENABLE | \
8 J1 p! A7 U- A% y PINMUX1_MCASP0_AXR13_ENABLE | \
% }$ s/ X9 z% a" t" x( `6 S, w x PINMUX1_MCASP0_AXR14_ENABLE | \4 q+ C, Z/ o% N6 c: i$ w
PINMUX1_MCASP0_AXR8_ENABLE | \/ I1 z9 K. m4 H$ }6 X
PINMUX1_MCASP0_AXR9_ENABLE | \+ }3 F* d0 j p t
PINMUX1_MCASP0_AXR10_ENABLE | \/ \0 n" @+ K$ ~" k- M- h
savePinMux);3 P- `/ c! V2 ]
}5 N5 ` n8 m; l( Y1 l
+ i2 {/ I1 Z- E; |3 z0 `6 r
1.McASPI2SConfigure(); McASP的配置程序如下:% r! h' U3 F: K/ U
static void McASPI2SConfigure(void)
% Z$ P% B% v& x{
" j9 g" t3 g+ k+ o4 |0 f, H McASPRxReset(SOC_MCASP_0_CTRL_REGS);
/ c, U) ]6 L& {& g3 V5 C& a McASPTxReset(SOC_MCASP_0_CTRL_REGS);1 s) A( N( v2 X
+ J8 m- P) j4 k6 F- @! ]
/* Enable the FIFOs for DMA transfer */
5 G. `+ ?+ ^- `1 B+ ]5 d// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);: f$ `3 _6 m; k _8 L% t& j
// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);% m9 L& F& B" h- ~4 l
5 F/ U2 x6 b( L
/* Set I2S format in the transmitter/receiver format units */3 U6 C2 ]% ~$ x: f; U' f6 s4 x
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
1 b$ K% y, ^2 W3 f/ R MCASP_RX_MODE_NON_DMA);
% K7 b# { z2 G$ L) q7 T- f$ r McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,3 P; A" [0 {0 S* O! i
MCASP_TX_MODE_NON_DMA);
: u n" ^9 Q8 V% h# D2 w' F
7 \ U9 q5 z1 S% J /* Configure the frame sync. I2S shall work in TDM format with 2 slots */6 H$ A: \+ G# O7 x
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD, 8 T! G6 _0 X2 Z- H; D6 D$ m0 R
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);" j/ P' ^' H7 Z' v- X4 ~2 E$ ?) T
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
* G0 I* ?1 x7 h' ]( \# [4 | MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);# M0 _' `: M' c* |7 z
& m: P" q2 I! [
/* configure the clock for receiver */) K/ c1 X* [+ `
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);$ v+ v4 Q0 L4 b" j# Y; {5 f
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);, X/ O, Q: j% f$ S1 h4 X' j
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);9 n" ]9 }# I* ~/ c
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
+ |7 }2 B5 s. r7 A+ G 0x00, 0xFF);
2 ~0 I7 R; t, u9 e' s- R) ?9 r* ]( [7 i
/* configure the clock for transmitter */
# c4 V8 Z& A3 t1 M6 {7 ?/ \) w// HWREG(0x01D000A0) = (0x00001F00);0 {" a+ |2 P7 o
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
. F% |, m5 t: u% ?4 V; c6 g) Z McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);* G: R9 n( c! y. A
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
. _7 E' u A1 S5 d McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,9 r- e- v" Z1 R0 z
0x00, 0xFF);! b: d& n( _, R" {, k+ r) D
: }5 o+ W9 m/ T /* Enable synchronization of RX and TX sections */ , W. S& k: L# R `# V" Q( U1 I
McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);% n7 L5 R5 x, [5 m% G
7 p4 \* S" s( Y1 k8 H
/* Enable the transmitter/receiver slots. I2S uses 2 slots */
5 o, h7 L: A# f* e McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);8 }6 B( Y: k c) S# U% V( B- O
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 {7 v# Y/ x) r. d7 b- F
+ U u, u+ W8 s* g5 @+ k
/*" n" k9 f: e& {/ m& b. ~& p+ I
** Set the serializers, Currently only one serializer is set as
0 k2 G/ a( J; D4 J ** transmitter and one serializer as receiver.4 q. v& q6 |: g( v( j$ i9 v
*/
3 K/ U a0 Y. n" Z5 r: P# w McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
0 k+ S1 G+ `. O/ N- v o. S2 g McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);9 n I* z/ w, @
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);, L/ V6 E) Y, @% E9 D5 Z: p$ L
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);+ E; [% m+ I9 y( {/ h9 B) {
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);5 e h, u' Z- t- t6 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);* W' f8 W @$ _0 S0 e/ _
% T1 j7 C" I' l; R7 j6 N0 T
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
: H$ e5 f5 j. i2 r1 [9 N9 c* h. R6 K( F* T D$ W5 W2 H
/** U+ S; }+ z8 |
** Configure the McASP pins ) M, b! K7 t9 c/ n( m. w, Q+ X
** Input - Frame Sync, Clock and Serializer Rx
. Q1 L- L5 H4 ^/ U; b ** Output - Serializer Tx is connected to the input of the codec
$ b& e2 z8 R+ t; b7 n */
: F7 Q" q4 T2 n3 f% W0 L' [6 n) i McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
# a' Z8 f' A* Q6 t8 v# j McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS, R$ _7 H: ?/ ^8 [# g
MCASP_PIN_AXR(MCASP_XSER_TX)
+ k1 g) ]/ {5 e( a | MCASP_PIN_AMUTE
) U& T9 U0 C; K );
7 p7 u. a; W6 X ^: h' D3 g4 M McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,. B3 f: S! D5 t- t
MCASP_PIN_AFSX) m+ ?0 I* r2 {) Q
| MCASP_PIN_AFSR
+ r6 n& e& K4 t$ A! N$ z& S& K# f, k. N | MCASP_PIN_AHCLKX
s) y, Z5 N; j | MCASP_PIN_AHCLKR
1 Q; f) c- k7 h. Y6 @' E" I/ | | MCASP_PIN_ACLKX
! _2 R) L7 w( f: Y' _* L! z9 N6 k | MCASP_PIN_ACLKR
0 n0 ]% w! }7 ^: l$ i9 T8 z | MCASP_PIN_AXR(MCASP_XSER_RX)" y( ?% E9 r* i
| MCASP_PIN_AXR(1u<<(13u))0 j% W0 Q* F1 D% a. u2 T/ A
| MCASP_PIN_AXR(1u<<(14u))
8 [, L& G' C( e) }! E1 E | MCASP_PIN_AXR(1u<<(8u))
: f# j- \) v# u. V- I: z2 C1 x& g | MCASP_PIN_AXR(1u<<(10u))
* @. ~6 z/ p2 i/ E9 ] | MCASP_PIN_AXR(1u<<(11u))
# X9 ]5 G4 I. U+ P! @ );$ J0 r' o& C2 s
7 s5 v/ ]5 h+ K1 u6 w, h9 B
/* Enable error interrupts for McASP */
3 {+ K7 N$ C6 T6 J' x, X McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
6 E, i$ q0 \, F( O MCASP_TX_DATAREADY; o( r2 x3 k ?2 w% z! [. N5 U
| MCASP_TX_CLKFAIL ) j+ M' p# K2 y* n- ^2 {! t
| MCASP_TX_SYNCERROR
" y9 w2 r$ j) y4 m$ R7 P( N | MCASP_TX_UNDERRUN);
- U* Z% Y8 ^/ Y+ N4 K+ D. a ~9 r1 V0 W: A5 U# X
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,0 p- k: ^# z3 S D; d8 @- M. ?
MCASP_RX_DATAREADY& c; K6 B0 s" T" H, O# M
| MCASP_RX_CLKFAIL- D+ U" |! u( w: s( j# G1 G
| MCASP_RX_SYNCERROR
: O6 ~0 b+ ~, g4 H# P1 V | MCASP_RX_OVERRUN);* L7 H! t3 ?9 H2 U$ U) A( e
//MCASP_RX_DMAERROR MCASP_TX_DMAERROR2 A( m7 B5 i- p! {! C2 x+ x
8 a# T4 U5 S I5 r}2 t+ f7 ?; _) Z7 U+ ^
6 o' G3 L. _) j$ `; ]/ B6 X. U2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
* _8 x- E* y: Q0 Q- |. O1 ?) Xstatic void I2SDataTxRxActivate(void)" z$ M& [$ z% a, x+ i
{
6 f* e- a6 j6 h8 [4 A3 y- T /* Start the clocks */6 u% v: Z: k: e2 D* G) K8 r. Q
McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);: x* B# ~) B# ]$ |, p2 N& x
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);% r. T& n; b0 S2 |7 `
. H |* k/ R a; @ /* Enable EDMA for the transfer */# z, k* }9 I [& k2 E
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
- l/ g% \; l6 S4 o; o3 g// EDMA3_TRIG_MODE_EVENT);9 c( r* Q$ \3 ], Q4 H
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
4 e T0 d$ y. }4 S' {6 \2 \ h// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
. h. J4 A$ K* Y0 N8 S: F/ |! f' y /* Activate the serializers */* V( T7 o+ t6 ?/ l: x; K2 z
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);) {3 S: o' ^! K. I! _8 ]( G
McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
J. o3 S3 g- _1 c /* make sure that the XDATA bit is cleared to zero */; U5 s; ]; q' P8 b( ^
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
: M {0 H5 h7 O- [* } /* Activate the state machines */" y% v) @) _2 V3 j# C6 K. x6 Z% O1 K
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);; H( X) }7 {0 o2 q0 B9 m
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
9 f8 n6 w8 O% g" z McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);) z& b# R- n: z% J
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