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我的McASP配置分别如下:
: I$ S& w+ n) _" }管脚的复用设置是:2 B' U: k7 Y7 q' ]* |
void McASPPinMuxSetup(void)
8 u: L* ?- ?/ r3 ?{
& R! _" L' q. j unsigned int savePinMux = 0;& D2 h b# l2 T( z1 N1 L- m% }
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \! R) L: G2 x! W2 o
~(SYSCFG_PINMUX0_PINMUX0_27_24 | \
/ `3 _: C" u, A( D6 a SYSCFG_PINMUX0_PINMUX0_23_20 | \- I/ I- {# l) i6 x+ V9 `$ ]& O
SYSCFG_PINMUX0_PINMUX0_19_16 | \
6 T3 M; q, ]6 d l SYSCFG_PINMUX0_PINMUX0_15_12 | \
* I: M$ |) h5 w; S6 u$ o SYSCFG_PINMUX0_PINMUX0_11_8 | \
0 K$ s1 P0 i+ v! A1 L, a+ y( @ SYSCFG_PINMUX0_PINMUX0_7_4 | \
+ V+ e1 u5 q/ o1 f5 c5 a( j1 T% Z9 q SYSCFG_PINMUX0_PINMUX0_3_0);
; H& F2 m# s5 [: X HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \
k' \ ]9 m @( l (PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \) j. H' S; C* v
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \$ J. c0 F% a+ V9 t [6 v; m% H
PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \) Z4 A+ w9 w6 w" A# M
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);
0 \. Y" n8 ?+ R1 p% K. ^' {$ @ savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \# ?3 Y/ w0 w$ V" v# K R
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
9 R. z4 l( _$ W& i SYSCFG_PINMUX1_PINMUX1_15_12 | \ c5 a: u0 z# u+ Y8 z2 l e! V
SYSCFG_PINMUX1_PINMUX1_11_8 | \
' F- R+ L- C# }$ k; s SYSCFG_PINMUX1_PINMUX1_7_4 | \
* j$ Q( j, W% \ SYSCFG_PINMUX1_PINMUX1_23_20 | \
! J ?/ i1 W! `& g SYSCFG_PINMUX1_PINMUX1_27_24 | \
+ U: g! P6 C+ Z5 S0 a) _ SYSCFG_PINMUX1_PINMUX1_31_28( q5 c- j2 s! g- I/ h# C7 {
);
, {, U2 x! O) P% @ HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \$ K4 u" W0 T8 f
(PINMUX1_MCASP0_AXR11_ENABLE | \+ D. j. H5 l* D |+ R. ^- N6 o
PINMUX1_MCASP0_AXR12_ENABLE | \$ g- x" B( _6 K# u3 W
PINMUX1_MCASP0_AXR13_ENABLE | \
. S6 n0 v( o9 ^5 W0 w/ Z( e: p/ f0 G PINMUX1_MCASP0_AXR14_ENABLE | \9 m7 U. b0 Y2 V* l. Q' e! k+ r
PINMUX1_MCASP0_AXR8_ENABLE | \9 X$ N' |+ {! v1 K5 f" p n6 r
PINMUX1_MCASP0_AXR9_ENABLE | \
1 _+ z! E2 p$ S9 V PINMUX1_MCASP0_AXR10_ENABLE | \; ?$ j" i6 V: }$ Y
savePinMux);
2 J) k/ F2 {- p}
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1.McASPI2SConfigure(); McASP的配置程序如下:2 z1 q; p, E4 g E {
static void McASPI2SConfigure(void)5 Z8 z/ S. w5 m( N/ X
{0 z) m; C K- m, w9 V; ]
McASPRxReset(SOC_MCASP_0_CTRL_REGS);
% S) m* E; x5 Z: {; x1 j |' I McASPTxReset(SOC_MCASP_0_CTRL_REGS);
8 p9 }1 h. y9 ]& {' d7 e( @9 ?* H2 B3 t; W1 _2 Y% J, |1 K% y
/* Enable the FIFOs for DMA transfer */$ ?# |7 i* w& N8 p \; r
// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
( P6 h! r, u- d d// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
$ [3 s0 _+ e4 w5 Z L) u1 _- N+ ?- l) I# n$ D/ r+ X3 T
/* Set I2S format in the transmitter/receiver format units */- Z$ G5 G6 d% l6 L1 H
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE," c( X6 F# n( Y o7 ?' R
MCASP_RX_MODE_NON_DMA);2 n6 a4 }- n7 x. j* O
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,$ w7 T+ e7 S* M9 R* u3 {8 z4 g: {- Q
MCASP_TX_MODE_NON_DMA);) S! Q, O+ x: C( T: @: I
/ N6 P# A& p' ?8 b" h2 N
/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
n, S$ Y; P* F& V McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
+ M3 l: s; J, e7 _ MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
8 ~) e& [, M" p' p McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
- t0 `0 L( |% M3 q$ | MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);: G# s+ O7 v ?
$ o5 {: c% x' J6 X" N8 U+ i, N /* configure the clock for receiver */% c6 ~! ]/ P, q$ M
// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);
: t: b' G* ?$ ]4 v* }) e- P* J McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);% \! Q; O. O4 b; D0 ~5 F
McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);
. t3 B, ?* N7 n McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,/ [( r) u; J, Q0 m
0x00, 0xFF);
i' [* R* A9 Z5 n: c
% b7 H" a4 i7 N* k /* configure the clock for transmitter */: D( _5 u2 J7 `1 D
// HWREG(0x01D000A0) = (0x00001F00);
* i- T/ C% q7 W& I// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
( N8 ?3 [6 ]1 D: b$ p+ v' h5 H McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);# p% L/ c \3 B& n" Q+ K
McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);" x: l3 `2 B9 E ?$ `* f5 {7 z6 m
McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,. J. ^& F( e, L# y. H# ?
0x00, 0xFF);
( }' e' d6 ^) b" g! o4 A 9 `: U Y2 `7 E$ ]) Y% R+ u
/* Enable synchronization of RX and TX sections */
* m( Y/ O0 F y McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);) |- [+ ?$ K3 e) y$ Y+ }/ J
2 G. ] E6 Z9 P& D) ^) Y /* Enable the transmitter/receiver slots. I2S uses 2 slots */. S9 [, n3 f0 e% D+ M: n
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);+ l( s4 R1 W% I* Y
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
9 n, a9 l( O: o! \( m9 s, _8 l( k9 O& r% \! v5 i2 n
/*
1 W6 h( |- @: r3 {+ v+ m" K8 u' E ** Set the serializers, Currently only one serializer is set as
1 V. P! v; v- h/ e _ ** transmitter and one serializer as receiver.# [5 M; `" f- }
*/9 J5 l. c& b5 k3 V
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX);
% g; Q; I0 C6 D/ ^( ] McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);" k! g- G! L& C, Q& z
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);5 G Z" N/ j% j0 L: v, ~9 g+ \
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);; w3 _6 q- H+ x# R( Z% _; @; [9 o
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);
1 [8 l4 i4 Y ]- v; } McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);7 |( z6 b" P' K/ T; \. e+ w* j2 q
7 W! o, t1 R+ j$ s% G# o
McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
+ {- Y' M; f( G
0 u( Z3 p% U+ a; c /*
, z& w$ v5 w1 n: Z( n ** Configure the McASP pins # w; z' I' b. ~) d8 E9 R6 Y
** Input - Frame Sync, Clock and Serializer Rx& I: Z/ @* c; Z) \
** Output - Serializer Tx is connected to the input of the codec
+ D9 w; Y- g; ~6 y */
* Q- T( C; u* C" L& i3 B! | McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);" @3 @" v) f. C: v
McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,& R% a, }& g& F+ ]& b3 X4 L
MCASP_PIN_AXR(MCASP_XSER_TX): @+ S# k+ W! e& t* I# f
| MCASP_PIN_AMUTE& r& z8 z- z. s: r
);
, B* f5 x4 f! ?5 L0 {6 z McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,
& k; f% h( H0 } MCASP_PIN_AFSX U7 Q T, T; l
| MCASP_PIN_AFSR6 s8 s" \# c) n w/ F
| MCASP_PIN_AHCLKX
5 C% `$ H1 ^' G) L( u$ b A | MCASP_PIN_AHCLKR
: s1 e; S( a/ n* o( g" S0 R$ ?' | | MCASP_PIN_ACLKX$ I9 ?' F3 I" M7 u1 o- X4 m* G
| MCASP_PIN_ACLKR
" a* S0 e+ H* G4 _5 B | MCASP_PIN_AXR(MCASP_XSER_RX)
$ l d6 o1 X3 f8 V$ g( s | MCASP_PIN_AXR(1u<<(13u))
$ c; \, v# W. t. A3 y | MCASP_PIN_AXR(1u<<(14u))
7 H4 D2 A/ n1 M7 o& @ | MCASP_PIN_AXR(1u<<(8u))
3 K) j4 y9 F5 y | MCASP_PIN_AXR(1u<<(10u))2 d( F( f- j% W- n; p
| MCASP_PIN_AXR(1u<<(11u))
1 t3 W2 E7 \7 M7 @ );1 h1 B5 ]) f0 i& M
9 k g! _# e& T! U6 _2 K) s
/* Enable error interrupts for McASP */
" N; D* B7 W# u& W( A7 e/ c" m McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
( L$ N" H1 f5 h9 v# h% s% h* U3 j) k MCASP_TX_DATAREADY
* q7 A7 D$ ^( j; T: C' \6 x/ } | MCASP_TX_CLKFAIL , t* G5 L9 r. |& F( m; f$ S9 [
| MCASP_TX_SYNCERROR2 e! Z w* F/ K2 e0 I& m
| MCASP_TX_UNDERRUN);& E8 R2 G9 i& y m. g
3 n- C1 w8 i! T/ n+ L* T- t0 g
McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
$ l# B# S5 J8 J MCASP_RX_DATAREADY% [8 N6 M& f* h! o$ [+ }) M& p
| MCASP_RX_CLKFAIL
" R# Z! Q, z3 [: k1 P8 G. o. u" ^3 p | MCASP_RX_SYNCERROR 4 \! G% p$ C$ Z
| MCASP_RX_OVERRUN);
6 g3 L. r& C$ l: G//MCASP_RX_DMAERROR MCASP_TX_DMAERROR4 ^0 g* _$ y& k9 V2 V; ~
% m! ~5 g! w$ c" x}8 Q9 v) J# c% x5 y( y+ Y
5 d, m- G: [* j6 k; C2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句
% G6 I! H) T0 j/ p, [9 s. J2 tstatic void I2SDataTxRxActivate(void)
& f( x' T7 x/ ^; Q{
% J8 C! W" u1 r /* Start the clocks */
y5 q/ M8 _) i5 `* w! [ McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);
& _2 c+ V( w. S8 n McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);1 O* L4 I% n8 V. S
- V* a9 A" Z4 g8 U; n4 M7 U# S
/* Enable EDMA for the transfer */3 v1 z7 m$ e: S/ P
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,
# }+ Z% A0 f+ b" L% N6 j8 [, a// EDMA3_TRIG_MODE_EVENT);. C1 o( l7 l/ z3 o/ u
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,
: [9 B2 n1 Y4 o$ j8 K) r# N// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
. r, G& @0 W W3 L+ r6 F J /* Activate the serializers */8 V+ \( L t; W
McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
: Z# `$ F7 E. r( i( s& [ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);1 J5 {% j8 q! L. N0 a! o4 S3 x
/* make sure that the XDATA bit is cleared to zero */
" {+ F# J6 x4 U while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);
! P" y% h. P" b+ H4 e5 ?$ ^ /* Activate the state machines */
o4 l- h- j) x. @% P McASPRxEnable(SOC_MCASP_0_CTRL_REGS);
8 ^& h' m* [+ J: _5 L" Q$ z6 u McASPTxEnable(SOC_MCASP_0_CTRL_REGS);
8 ^- ?4 |5 U9 B, M5 h9 m7 j McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);
; z; w: S2 ?+ a3 D( a! O}: [8 t/ U# K/ c4 {& B7 w2 N, g
x9 f% K, p9 u! | |
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