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我的McASP配置分别如下:5 s# s8 @# n {0 R; C* P
管脚的复用设置是:+ {' Q) u2 e! k
void McASPPinMuxSetup(void)
5 r, |8 ^, Q R [! d3 f{
! w" I+ S( d6 ]) G unsigned int savePinMux = 0;; @: J* J$ e) d/ |& @2 V$ H
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) & \
' T0 b0 i. H* f/ e$ M( ` x ~(SYSCFG_PINMUX0_PINMUX0_27_24 | \6 z$ M8 H0 Z& b; j3 B3 S. y! {1 e) Q: H
SYSCFG_PINMUX0_PINMUX0_23_20 | \, u) K& n4 O+ D9 W9 m! z, H# `
SYSCFG_PINMUX0_PINMUX0_19_16 | \
. M+ V# k* y2 \# s) A SYSCFG_PINMUX0_PINMUX0_15_12 | \
3 ^7 B8 A' p3 F SYSCFG_PINMUX0_PINMUX0_11_8 | \
; T) O9 t! v$ s6 n3 ?9 S SYSCFG_PINMUX0_PINMUX0_7_4 | \+ P7 s$ q. }7 Y3 T5 v# `
SYSCFG_PINMUX0_PINMUX0_3_0);
! z- [# E T! K8 H, f HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(0)) = \* z$ U. m% [2 h, X
(PINMUX0_MCASP0_AMUTE_ENABLE | PINMUX0_MCASP0_AHCLKX_ENABLE | \0 t( t" X4 K3 G6 b2 V, X; y
PINMUX0_MCASP0_AHCLKR_ENABLE | PINMUX0_MCASP0_AFSX_ENABLE | \
* C5 N6 C5 W0 k" I8 ?$ B0 B7 r PINMUX0_MCASP0_AFSR_ENABLE | PINMUX0_MCASP0_ACLKX_ENABLE | \# D+ D; T1 k7 W9 d! h
PINMUX0_MCASP0_ACLKR_ENABLE | savePinMux);' Q w- N4 C- n0 A
savePinMux = HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) & \& v: i s! x( @: A" A
~(SYSCFG_PINMUX1_PINMUX1_19_16 | \
8 i- m# s' L2 n SYSCFG_PINMUX1_PINMUX1_15_12 | \
9 {+ V6 e& d+ n4 t8 w/ y SYSCFG_PINMUX1_PINMUX1_11_8 | \
: O% B$ _/ ~6 Z8 K6 ?; ~) e! s SYSCFG_PINMUX1_PINMUX1_7_4 | \
! X, |/ ], `- l1 [) K( X- Z: c, l7 M SYSCFG_PINMUX1_PINMUX1_23_20 | \( z2 R& S6 L" w, {
SYSCFG_PINMUX1_PINMUX1_27_24 | \
, Q; A1 X) Q. L SYSCFG_PINMUX1_PINMUX1_31_28
7 j' ~: I/ e6 ]/ s5 ]) c );
* q+ O5 o% ?, R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(1)) = \
7 X- e) i6 w1 w1 `- j3 g, J# A (PINMUX1_MCASP0_AXR11_ENABLE | \
! y/ `7 r& g- G; z7 o- E( C2 M( a PINMUX1_MCASP0_AXR12_ENABLE | \
h' J* ^% u* B6 c, k3 f PINMUX1_MCASP0_AXR13_ENABLE | \
% T+ b! ~5 x* W7 i$ u# I8 j% u PINMUX1_MCASP0_AXR14_ENABLE | \2 U; O9 k+ M7 U
PINMUX1_MCASP0_AXR8_ENABLE | \
" x- L$ c @5 R; \8 D PINMUX1_MCASP0_AXR9_ENABLE | \& i& q; F3 F. {8 {7 w' i
PINMUX1_MCASP0_AXR10_ENABLE | \& ?9 y4 X( D; q* p2 [5 N
savePinMux);- {% F- ~, r9 S, m+ R
}1 N! [1 q9 \# T* o
/ W. T8 q4 ~! w: _* ?' M* C9 Q
1.McASPI2SConfigure(); McASP的配置程序如下:. v! Y9 b# I4 D1 Q4 Y
static void McASPI2SConfigure(void): U6 _* K/ V; G' R+ I4 C( j) Z
{3 V0 a; n. r3 T& W
McASPRxReset(SOC_MCASP_0_CTRL_REGS);$ I: D# ?* S _+ }" ^. I3 }- m
McASPTxReset(SOC_MCASP_0_CTRL_REGS);
0 _/ q9 C& b( D( P: U5 [4 ]# w2 m% l M
/* Enable the FIFOs for DMA transfer */
1 \# m3 E C, l8 ^% P i// McASPReadFifoEnable(SOC_MCASP_0_FIFO_REGS, 6, 1);
9 Z, _* \% Q: ?# @// McASPWriteFifoEnable(SOC_MCASP_0_FIFO_REGS, 1, 1);
" D0 _% _; T0 q1 l! u% {& u, A
) g! ~$ G R m a5 w /* Set I2S format in the transmitter/receiver format units *// p% F9 d0 o j$ y- t$ ~
McASPRxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,
: d: n1 b: q8 C MCASP_RX_MODE_NON_DMA);4 u$ z- Q: _2 m) u* y, t
McASPTxFmtI2SSet(SOC_MCASP_0_CTRL_REGS, WORD_SIZE, SLOT_SIZE,% c. Z X/ M" M; S R
MCASP_TX_MODE_NON_DMA);
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/* Configure the frame sync. I2S shall work in TDM format with 2 slots */2 G9 }1 L4 f3 u2 ]! M' m2 W- Y& l
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
, y: n5 V. _+ @ MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);. C8 `) x+ g3 i$ J5 O% f8 ]7 v7 A( S
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
9 \$ {( v) P' o) a5 p MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);
7 W; C) n7 i; P- p* M; u6 R& A4 a9 _
' [2 Y2 p8 |6 i9 m' O /* configure the clock for receiver */
/ K/ @, u2 y9 ?( f; x! z0 e// McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_INTERNAL, 16u, 16u);# q- z) V' A6 L
McASPRxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL, 0, 0);
7 l, @/ H$ { e2 R0 q' k McASPRxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_POL_RIS_EDGE);1 h$ P/ o' [) q3 d1 \& |
McASPRxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLKCHCK_DIV32,
# p% E0 `# W3 }" K 0x00, 0xFF);
& @- P/ h) e+ [5 |7 i4 g0 e! Y, L/ M# T% W$ v$ C3 d& r
/* configure the clock for transmitter */
$ f( i+ n7 V0 ^0 S5 W, A6 [// HWREG(0x01D000A0) = (0x00001F00);% m0 K7 A c& J- v- N
// McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_INTERNAL, 16u, 16u);
6 s) q' [' h, p; i- I McASPTxClkCfg(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL, 0, 0);
8 q1 M/ w6 z5 h McASPTxClkPolaritySet(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_POL_FALL_EDGE);
) M3 z$ H! t+ x" s( Y. Y" |+ b2 _ McASPTxClkCheckConfig(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLKCHCK_DIV32,
2 Z4 A: Q0 r, m: V; h 0x00, 0xFF);
: Z9 o7 @/ v2 e1 K& L. J# ?; B
" q. ~' h x# W /* Enable synchronization of RX and TX sections */
" F4 u5 d% H1 j# v- ]+ q McASPTxRxClkSyncEnable(SOC_MCASP_0_CTRL_REGS);" Q5 P2 i I" x! x1 F
4 v+ p' B5 j% u3 ]# J/ S. J
/* Enable the transmitter/receiver slots. I2S uses 2 slots */% t% M6 p0 k0 H6 I# r& S
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
' a2 i( h# L* j! K# I0 e4 ? McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);5 ~5 C0 M( G: z: z9 C- M# J
# g( ?' I1 r$ n" T( ^ /*4 _7 M7 K& u9 _: S- _8 x: f
** Set the serializers, Currently only one serializer is set as( ^" H% u+ Q& @
** transmitter and one serializer as receiver.
# |' m' I6 Y$ g, t2 s, M */( ]5 l6 m- P+ W7 U" r
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_RX); U+ k/ x# N' \" f7 M* `: h
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 13u);2 E0 u8 z! J% \- b
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 14u);; Q& J5 _% P* Z" X
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 8u);) H; H$ _7 Y: Z6 k/ y# R
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 10u);& W9 U2 M0 V6 c7 _! ^! \& Z% g
McASPSerializerRxSet(SOC_MCASP_0_CTRL_REGS, 11u);
* W# @ J+ I3 X3 o# Q
4 ], v b0 H5 y) m# h McASPSerializerTxSet(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX);
8 Y4 `5 t9 ^3 U' ]/ t* i
' z0 w9 p( n3 H6 ~6 J; e9 V5 V /* v1 Z% `- C8 |
** Configure the McASP pins ) N0 _4 [! o- L" Q
** Input - Frame Sync, Clock and Serializer Rx G0 f! Q5 T5 S0 n5 o
** Output - Serializer Tx is connected to the input of the codec
9 ^" w+ A: o D, Y N: y' M */
' X. U( O, o9 N; S2 h McASPPinMcASPSet(SOC_MCASP_0_CTRL_REGS, 0xFFFFFFFF);
- v6 ?7 b9 {$ V; N7 D, f1 K$ i McASPPinDirOutputSet(SOC_MCASP_0_CTRL_REGS,
4 q) G9 R2 n5 o9 B2 s k$ g MCASP_PIN_AXR(MCASP_XSER_TX)
7 a$ g; K# I+ N% M6 H6 [4 I+ k: f | MCASP_PIN_AMUTE
/ h% I% J4 h$ g! \; l$ |, @$ Z );6 j* K0 w$ V2 K+ |& S
McASPPinDirInputSet(SOC_MCASP_0_CTRL_REGS,1 n1 V; Y3 D8 l3 L
MCASP_PIN_AFSX
- p0 e: j: B) M' H w | MCASP_PIN_AFSR7 T; y7 x' H' O0 \- A& G2 v3 ]2 z
| MCASP_PIN_AHCLKX
4 ^% [7 j! Z2 [4 b9 c4 S | MCASP_PIN_AHCLKR3 ~' h1 e: Z' r( w( o9 R) z9 w5 ?" J
| MCASP_PIN_ACLKX
8 H# _$ m# `0 ] | MCASP_PIN_ACLKR3 t; ]0 Q2 O3 p2 i0 Q: Y- A) K% r
| MCASP_PIN_AXR(MCASP_XSER_RX)' ~, E8 n; k9 O$ H% r; c t
| MCASP_PIN_AXR(1u<<(13u))- s0 J$ T; I- S" Z, d$ y% @4 N
| MCASP_PIN_AXR(1u<<(14u))
& }! ^5 K( w6 R | MCASP_PIN_AXR(1u<<(8u))! W. M. H7 O' C, t: z! ~2 ^
| MCASP_PIN_AXR(1u<<(10u))4 ]! f6 t% H" ~% w9 ^: J1 B+ U
| MCASP_PIN_AXR(1u<<(11u))
/ E# \/ d8 P" A6 c );
- S: n2 ^- e& Z! a% p: f4 p" j, P; I5 l- i5 A, U" h( p; h
/* Enable error interrupts for McASP */
: \( |6 E: k0 |! Q5 B McASPTxIntEnable(SOC_MCASP_0_CTRL_REGS,
; X+ f0 E( K9 p% u }5 e MCASP_TX_DATAREADY0 p% ^( q! ~! A
| MCASP_TX_CLKFAIL
: A& O& u6 ]! C+ f0 A, X | MCASP_TX_SYNCERROR
/ I, ^7 F9 A5 [& Q | MCASP_TX_UNDERRUN);2 c3 z4 ?2 |% S; P ?) w
0 \ ]( f6 R3 p+ A5 D2 h McASPRxIntEnable(SOC_MCASP_0_CTRL_REGS,
. I! d+ \9 t7 y) B# ^& x MCASP_RX_DATAREADY
# [. o( o/ X, N6 V2 T" m | MCASP_RX_CLKFAIL
9 O& g/ u' p; C$ N; D | MCASP_RX_SYNCERROR * _* D" ]3 a9 F- K p1 _
| MCASP_RX_OVERRUN);
) u4 W6 j p7 ^. |/ r/ q2 r//MCASP_RX_DMAERROR MCASP_TX_DMAERROR
% B- Y, ]. M: u; S0 {. X/ [( Y& ^1 k
: @2 B- j ]2 l: \% `$ c}" O) A1 R7 I: r
y2 A& z( M5 ~! A2 J
2.运行完上述配置后激活发送接受I2SDataTxRxActivate(); 遇到这个问题:程序无法跳出红色部分的语句: h/ J' w0 X: ?, g
static void I2SDataTxRxActivate(void): J2 J( r, y2 L" Z: \
{
1 Y8 O7 I9 b* a3 [1 x* G /* Start the clocks */
3 H7 W$ D4 h: n- W, h3 W$ d McASPRxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_RX_CLK_EXTERNAL);3 [6 E [8 z7 X( R9 e4 i
McASPTxClkStart(SOC_MCASP_0_CTRL_REGS, MCASP_TX_CLK_EXTERNAL);* {5 o P! s; i+ X; t! Q
9 N% x) |, Q$ i( x /* Enable EDMA for the transfer */
; A' v2 r* T1 P% _+ o: s( v$ J% Q// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX,8 D5 S, t( |: H" O+ ^' G9 E$ O# |
// EDMA3_TRIG_MODE_EVENT); k! \' I' R( p$ m
// EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS,. ]3 g* C# H) C' r6 Q
// EDMA3_CHA_MCASP0_TX, EDMA3_TRIG_MODE_EVENT);
4 }; Y) U, |+ H0 C" C% L /* Activate the serializers */
1 g, a0 f4 r5 n$ ~! B3 n( X McASPRxSerActivate(SOC_MCASP_0_CTRL_REGS);
6 S! F b3 J. }% \ McASPTxSerActivate(SOC_MCASP_0_CTRL_REGS);
3 G Q) P1 o4 \' W& S* h! v& V /* make sure that the XDATA bit is cleared to zero */0 t6 m# Q+ X' {) @& {
while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);8 D0 N0 Q5 Y1 ^
/* Activate the state machines */# f8 S& n6 E3 A: C5 _9 G
McASPRxEnable(SOC_MCASP_0_CTRL_REGS);3 \" z% w9 i* L
McASPTxEnable(SOC_MCASP_0_CTRL_REGS);6 i& \2 T' |6 M1 Z
McASPTxBufWrite(SOC_MCASP_0_CTRL_REGS, MCASP_XSER_TX, 0);) i; @' t1 ^! Q9 V6 E& y
}; a" b5 H8 |& P; s, D
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